1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "sar.h" 16 17 #ifdef CONFIG_RTW89_DEBUGMSG 18 unsigned int rtw89_debug_mask; 19 EXPORT_SYMBOL(rtw89_debug_mask); 20 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 21 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 22 #endif 23 24 #ifdef CONFIG_RTW89_DEBUGFS 25 struct rtw89_debugfs_priv { 26 struct rtw89_dev *rtwdev; 27 int (*cb_read)(struct seq_file *m, void *v); 28 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 29 size_t count, loff_t *loff); 30 union { 31 u32 cb_data; 32 struct { 33 u32 addr; 34 u32 len; 35 } read_reg; 36 struct { 37 u32 addr; 38 u32 mask; 39 u8 path; 40 } read_rf; 41 struct { 42 u8 ss_dbg:1; 43 u8 dle_dbg:1; 44 u8 dmac_dbg:1; 45 u8 cmac_dbg:1; 46 u8 dbg_port:1; 47 } dbgpkg_en; 48 struct { 49 u32 start; 50 u32 len; 51 u8 sel; 52 } mac_mem; 53 }; 54 }; 55 56 struct rtw89_debugfs { 57 struct rtw89_debugfs_priv read_reg; 58 struct rtw89_debugfs_priv write_reg; 59 struct rtw89_debugfs_priv read_rf; 60 struct rtw89_debugfs_priv write_rf; 61 struct rtw89_debugfs_priv rf_reg_dump; 62 struct rtw89_debugfs_priv txpwr_table; 63 struct rtw89_debugfs_priv mac_reg_dump; 64 struct rtw89_debugfs_priv mac_mem_dump; 65 struct rtw89_debugfs_priv mac_dbg_port_dump; 66 struct rtw89_debugfs_priv send_h2c; 67 struct rtw89_debugfs_priv early_h2c; 68 struct rtw89_debugfs_priv fw_crash; 69 struct rtw89_debugfs_priv btc_info; 70 struct rtw89_debugfs_priv btc_manual; 71 struct rtw89_debugfs_priv fw_log_manual; 72 struct rtw89_debugfs_priv phy_info; 73 struct rtw89_debugfs_priv stations; 74 struct rtw89_debugfs_priv disable_dm; 75 }; 76 77 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 78 [RATE_INFO_BW_20] = 20, 79 [RATE_INFO_BW_40] = 40, 80 [RATE_INFO_BW_80] = 80, 81 [RATE_INFO_BW_160] = 160, 82 [RATE_INFO_BW_320] = 320, 83 }; 84 85 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 86 { 87 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 88 return rtw89_rate_info_bw_to_mhz_map[bw]; 89 90 return 0; 91 } 92 93 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 94 { 95 struct rtw89_debugfs_priv *debugfs_priv = m->private; 96 97 return debugfs_priv->cb_read(m, v); 98 } 99 100 static ssize_t rtw89_debugfs_single_write(struct file *filp, 101 const char __user *buffer, 102 size_t count, loff_t *loff) 103 { 104 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 105 106 return debugfs_priv->cb_write(filp, buffer, count, loff); 107 } 108 109 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 110 const char __user *buffer, 111 size_t count, loff_t *loff) 112 { 113 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 114 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 115 116 return debugfs_priv->cb_write(filp, buffer, count, loff); 117 } 118 119 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 120 { 121 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 122 } 123 124 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 125 { 126 return 0; 127 } 128 129 static const struct file_operations file_ops_single_r = { 130 .owner = THIS_MODULE, 131 .open = rtw89_debugfs_single_open, 132 .read = seq_read, 133 .llseek = seq_lseek, 134 .release = single_release, 135 }; 136 137 static const struct file_operations file_ops_common_rw = { 138 .owner = THIS_MODULE, 139 .open = rtw89_debugfs_single_open, 140 .release = single_release, 141 .read = seq_read, 142 .llseek = seq_lseek, 143 .write = rtw89_debugfs_seq_file_write, 144 }; 145 146 static const struct file_operations file_ops_single_w = { 147 .owner = THIS_MODULE, 148 .write = rtw89_debugfs_single_write, 149 .open = simple_open, 150 .release = rtw89_debugfs_close, 151 }; 152 153 static ssize_t 154 rtw89_debug_priv_read_reg_select(struct file *filp, 155 const char __user *user_buf, 156 size_t count, loff_t *loff) 157 { 158 struct seq_file *m = (struct seq_file *)filp->private_data; 159 struct rtw89_debugfs_priv *debugfs_priv = m->private; 160 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 161 char buf[32]; 162 size_t buf_size; 163 u32 addr, len; 164 int num; 165 166 buf_size = min(count, sizeof(buf) - 1); 167 if (copy_from_user(buf, user_buf, buf_size)) 168 return -EFAULT; 169 170 buf[buf_size] = '\0'; 171 num = sscanf(buf, "%x %x", &addr, &len); 172 if (num != 2) { 173 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 174 return -EINVAL; 175 } 176 177 debugfs_priv->read_reg.addr = addr; 178 debugfs_priv->read_reg.len = len; 179 180 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 181 182 return count; 183 } 184 185 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 186 { 187 struct rtw89_debugfs_priv *debugfs_priv = m->private; 188 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 189 u32 addr, end, data, k; 190 u32 len; 191 192 len = debugfs_priv->read_reg.len; 193 addr = debugfs_priv->read_reg.addr; 194 195 if (len > 4) 196 goto ndata; 197 198 switch (len) { 199 case 1: 200 data = rtw89_read8(rtwdev, addr); 201 break; 202 case 2: 203 data = rtw89_read16(rtwdev, addr); 204 break; 205 case 4: 206 data = rtw89_read32(rtwdev, addr); 207 break; 208 default: 209 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 210 return -EINVAL; 211 } 212 213 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 214 215 return 0; 216 217 ndata: 218 end = addr + len; 219 220 for (; addr < end; addr += 16) { 221 seq_printf(m, "%08xh : ", 0x18600000 + addr); 222 for (k = 0; k < 16; k += 4) { 223 data = rtw89_read32(rtwdev, addr + k); 224 seq_printf(m, "%08x ", data); 225 } 226 seq_puts(m, "\n"); 227 } 228 229 return 0; 230 } 231 232 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 233 const char __user *user_buf, 234 size_t count, loff_t *loff) 235 { 236 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 237 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 238 char buf[32]; 239 size_t buf_size; 240 u32 addr, val, len; 241 int num; 242 243 buf_size = min(count, sizeof(buf) - 1); 244 if (copy_from_user(buf, user_buf, buf_size)) 245 return -EFAULT; 246 247 buf[buf_size] = '\0'; 248 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 249 if (num != 3) { 250 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 251 return -EINVAL; 252 } 253 254 switch (len) { 255 case 1: 256 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 257 rtw89_write8(rtwdev, addr, (u8)val); 258 break; 259 case 2: 260 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 261 rtw89_write16(rtwdev, addr, (u16)val); 262 break; 263 case 4: 264 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 265 rtw89_write32(rtwdev, addr, (u32)val); 266 break; 267 default: 268 rtw89_info(rtwdev, "invalid read write len %d\n", len); 269 break; 270 } 271 272 return count; 273 } 274 275 static ssize_t 276 rtw89_debug_priv_read_rf_select(struct file *filp, 277 const char __user *user_buf, 278 size_t count, loff_t *loff) 279 { 280 struct seq_file *m = (struct seq_file *)filp->private_data; 281 struct rtw89_debugfs_priv *debugfs_priv = m->private; 282 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 283 char buf[32]; 284 size_t buf_size; 285 u32 addr, mask; 286 u8 path; 287 int num; 288 289 buf_size = min(count, sizeof(buf) - 1); 290 if (copy_from_user(buf, user_buf, buf_size)) 291 return -EFAULT; 292 293 buf[buf_size] = '\0'; 294 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 295 if (num != 3) { 296 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 297 return -EINVAL; 298 } 299 300 if (path >= rtwdev->chip->rf_path_num) { 301 rtw89_info(rtwdev, "wrong rf path\n"); 302 return -EINVAL; 303 } 304 debugfs_priv->read_rf.addr = addr; 305 debugfs_priv->read_rf.mask = mask; 306 debugfs_priv->read_rf.path = path; 307 308 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 309 310 return count; 311 } 312 313 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 314 { 315 struct rtw89_debugfs_priv *debugfs_priv = m->private; 316 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 317 u32 addr, data, mask; 318 u8 path; 319 320 addr = debugfs_priv->read_rf.addr; 321 mask = debugfs_priv->read_rf.mask; 322 path = debugfs_priv->read_rf.path; 323 324 data = rtw89_read_rf(rtwdev, path, addr, mask); 325 326 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 327 328 return 0; 329 } 330 331 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 332 const char __user *user_buf, 333 size_t count, loff_t *loff) 334 { 335 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 336 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 337 char buf[32]; 338 size_t buf_size; 339 u32 addr, val, mask; 340 u8 path; 341 int num; 342 343 buf_size = min(count, sizeof(buf) - 1); 344 if (copy_from_user(buf, user_buf, buf_size)) 345 return -EFAULT; 346 347 buf[buf_size] = '\0'; 348 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 349 if (num != 4) { 350 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 351 return -EINVAL; 352 } 353 354 if (path >= rtwdev->chip->rf_path_num) { 355 rtw89_info(rtwdev, "wrong rf path\n"); 356 return -EINVAL; 357 } 358 359 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 360 path, addr, val, mask); 361 rtw89_write_rf(rtwdev, path, addr, mask, val); 362 363 return count; 364 } 365 366 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 367 { 368 struct rtw89_debugfs_priv *debugfs_priv = m->private; 369 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 370 const struct rtw89_chip_info *chip = rtwdev->chip; 371 u32 addr, offset, data; 372 u8 path; 373 374 for (path = 0; path < chip->rf_path_num; path++) { 375 seq_printf(m, "RF path %d:\n\n", path); 376 for (addr = 0; addr < 0x100; addr += 4) { 377 seq_printf(m, "0x%08x: ", addr); 378 for (offset = 0; offset < 4; offset++) { 379 data = rtw89_read_rf(rtwdev, path, 380 addr + offset, RFREG_MASK); 381 seq_printf(m, "0x%05x ", data); 382 } 383 seq_puts(m, "\n"); 384 } 385 seq_puts(m, "\n"); 386 } 387 388 return 0; 389 } 390 391 struct txpwr_ent { 392 bool nested; 393 union { 394 const char *txt; 395 const struct txpwr_ent *ptr; 396 }; 397 u8 len; 398 }; 399 400 struct txpwr_map { 401 const struct txpwr_ent *ent; 402 u8 size; 403 u32 addr_from; 404 u32 addr_to; 405 u32 addr_to_1ss; 406 }; 407 408 #define __GEN_TXPWR_ENT_NESTED(_e) \ 409 { .nested = true, .ptr = __txpwr_ent_##_e, \ 410 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 411 412 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 413 414 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 415 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 416 417 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 418 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 419 420 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 421 { .len = 8, .txt = _t "\t- " \ 422 _e0 " " _e1 " " _e2 " " _e3 " " \ 423 _e4 " " _e5 " " _e6 " " _e7 } 424 425 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 426 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 427 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 428 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 429 /* 1NSS */ 430 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 431 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 432 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 433 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 434 /* 2NSS */ 435 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 436 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 437 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 438 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 439 }; 440 441 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 442 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 443 444 static const struct txpwr_map __txpwr_map_byr_ax = { 445 .ent = __txpwr_ent_byr_ax, 446 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 447 .addr_from = R_AX_PWR_BY_RATE, 448 .addr_to = R_AX_PWR_BY_RATE_MAX, 449 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 450 }; 451 452 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 453 /* 1TX */ 454 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 455 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 456 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 457 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 458 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 459 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 460 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 461 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 462 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 463 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 464 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 465 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 466 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 467 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 468 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 469 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 470 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 471 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 472 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 473 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 474 /* 2TX */ 475 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 476 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 477 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 478 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 479 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 480 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 481 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 482 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 483 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 484 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 485 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 486 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 487 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 488 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 489 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 490 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 491 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 492 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 493 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 494 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 495 }; 496 497 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 498 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 499 500 static const struct txpwr_map __txpwr_map_lmt_ax = { 501 .ent = __txpwr_ent_lmt_ax, 502 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 503 .addr_from = R_AX_PWR_LMT, 504 .addr_to = R_AX_PWR_LMT_MAX, 505 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 506 }; 507 508 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 509 /* 1TX */ 510 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 511 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 512 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 513 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 514 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 515 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 516 /* 2TX */ 517 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 518 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 519 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 520 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 521 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 522 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 523 }; 524 525 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 526 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 527 528 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 529 .ent = __txpwr_ent_lmt_ru_ax, 530 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 531 .addr_from = R_AX_PWR_RU_LMT, 532 .addr_to = R_AX_PWR_RU_LMT_MAX, 533 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 534 }; 535 536 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 537 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 538 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 539 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 540 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 541 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 542 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 543 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 544 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 545 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 546 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 547 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 548 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 549 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 550 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 551 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 552 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 553 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 554 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 555 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 556 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 557 }; 558 559 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 560 __GEN_TXPWR_ENT0("BW20"), 561 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 562 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 563 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 564 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 565 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 566 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 567 568 __GEN_TXPWR_ENT0("BW40"), 569 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 570 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 571 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 572 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 573 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 574 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 575 576 /* there is no CCK section after BW80 */ 577 __GEN_TXPWR_ENT0("BW80"), 578 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 579 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 580 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 581 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 582 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 583 584 __GEN_TXPWR_ENT0("BW160"), 585 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 586 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 587 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 588 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 589 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 590 591 __GEN_TXPWR_ENT0("BW320"), 592 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 593 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 594 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 595 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 596 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 597 }; 598 599 static const struct txpwr_map __txpwr_map_byr_be = { 600 .ent = __txpwr_ent_byr_be, 601 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 602 .addr_from = R_BE_PWR_BY_RATE, 603 .addr_to = R_BE_PWR_BY_RATE_MAX, 604 .addr_to_1ss = 0, /* not support */ 605 }; 606 607 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 608 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 609 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 610 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 611 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 612 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 613 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 614 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 615 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 616 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 617 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 618 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 619 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 620 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 621 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 622 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 623 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 624 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 625 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 626 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 627 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 628 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 629 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 630 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 631 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 632 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 633 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 634 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 635 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 636 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 637 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 638 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 639 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 640 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 641 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 642 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 643 }; 644 645 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 646 __GEN_TXPWR_ENT0("1TX"), 647 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 648 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 649 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 650 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 651 652 __GEN_TXPWR_ENT0("2TX"), 653 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 654 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 655 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 656 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 657 }; 658 659 static const struct txpwr_map __txpwr_map_lmt_be = { 660 .ent = __txpwr_ent_lmt_be, 661 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 662 .addr_from = R_BE_PWR_LMT, 663 .addr_to = R_BE_PWR_LMT_MAX, 664 .addr_to_1ss = 0, /* not support */ 665 }; 666 667 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 668 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 669 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 670 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 671 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 672 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 673 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 674 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 675 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 676 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 677 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 678 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 679 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 680 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 681 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 682 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 683 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 684 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 685 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 686 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 687 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 688 }; 689 690 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 691 __GEN_TXPWR_ENT0("1TX"), 692 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 693 694 __GEN_TXPWR_ENT0("2TX"), 695 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 696 }; 697 698 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 699 .ent = __txpwr_ent_lmt_ru_be, 700 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 701 .addr_from = R_BE_PWR_RU_LMT, 702 .addr_to = R_BE_PWR_RU_LMT_MAX, 703 .addr_to_1ss = 0, /* not support */ 704 }; 705 706 static unsigned int 707 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 708 const s8 *buf, const unsigned int cur) 709 { 710 unsigned int cnt, i; 711 char *fmt; 712 713 if (ent->nested) { 714 for (cnt = 0, i = 0; i < ent->len; i++) 715 cnt += __print_txpwr_ent(m, ent->ptr + i, buf, 716 cur + cnt); 717 return cnt; 718 } 719 720 switch (ent->len) { 721 case 0: 722 seq_printf(m, "\t<< %s >>\n", ent->txt); 723 return 0; 724 case 2: 725 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 726 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 727 return 2; 728 case 4: 729 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 730 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 731 buf[cur + 2], buf[cur + 3]); 732 return 4; 733 case 8: 734 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 735 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 736 buf[cur + 2], buf[cur + 3], buf[cur + 4], 737 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 738 return 8; 739 default: 740 return 0; 741 } 742 } 743 744 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 745 const struct txpwr_map *map) 746 { 747 u8 fct = rtwdev->chip->txpwr_factor_mac; 748 u8 path_num = rtwdev->chip->rf_path_num; 749 unsigned int cur, i; 750 u32 max_valid_addr; 751 u32 val, addr; 752 s8 *buf, tmp; 753 int ret; 754 755 buf = vzalloc(map->addr_to - map->addr_from + 4); 756 if (!buf) 757 return -ENOMEM; 758 759 if (path_num == 1) 760 max_valid_addr = map->addr_to_1ss; 761 else 762 max_valid_addr = map->addr_to; 763 764 if (max_valid_addr == 0) 765 return -EOPNOTSUPP; 766 767 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 768 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 769 if (ret) 770 val = MASKDWORD; 771 772 cur = addr - map->addr_from; 773 for (i = 0; i < 4; i++, val >>= 8) { 774 /* signed 7 bits, and reserved BIT(7) */ 775 tmp = sign_extend32(val, 6); 776 buf[cur + i] = tmp >> fct; 777 } 778 } 779 780 for (cur = 0, i = 0; i < map->size; i++) 781 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 782 783 vfree(buf); 784 return 0; 785 } 786 787 #define case_REGD(_regd) \ 788 case RTW89_ ## _regd: \ 789 seq_puts(m, #_regd "\n"); \ 790 break 791 792 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev, 793 const struct rtw89_chan *chan) 794 { 795 u8 band = chan->band_type; 796 u8 regd = rtw89_regd_get(rtwdev, band); 797 798 switch (regd) { 799 default: 800 seq_printf(m, "UNKNOWN: %d\n", regd); 801 break; 802 case_REGD(WW); 803 case_REGD(ETSI); 804 case_REGD(FCC); 805 case_REGD(MKK); 806 case_REGD(NA); 807 case_REGD(IC); 808 case_REGD(KCC); 809 case_REGD(NCC); 810 case_REGD(CHILE); 811 case_REGD(ACMA); 812 case_REGD(MEXICO); 813 case_REGD(UKRAINE); 814 case_REGD(CN); 815 } 816 } 817 818 #undef case_REGD 819 820 struct dbgfs_txpwr_table { 821 const struct txpwr_map *byr; 822 const struct txpwr_map *lmt; 823 const struct txpwr_map *lmt_ru; 824 }; 825 826 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 827 .byr = &__txpwr_map_byr_ax, 828 .lmt = &__txpwr_map_lmt_ax, 829 .lmt_ru = &__txpwr_map_lmt_ru_ax, 830 }; 831 832 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 833 .byr = &__txpwr_map_byr_be, 834 .lmt = &__txpwr_map_lmt_be, 835 .lmt_ru = &__txpwr_map_lmt_ru_be, 836 }; 837 838 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 839 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 840 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 841 }; 842 843 static 844 void rtw89_debug_priv_txpwr_table_get_regd(struct seq_file *m, 845 struct rtw89_dev *rtwdev, 846 const struct rtw89_chan *chan) 847 { 848 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 849 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 850 851 seq_printf(m, "[Chanctx] band %u, ch %u, bw %u\n", 852 chan->band_type, chan->channel, chan->band_width); 853 854 seq_puts(m, "[Regulatory] "); 855 __print_regd(m, rtwdev, chan); 856 857 if (chan->band_type == RTW89_BAND_6G) { 858 seq_printf(m, "[reg6_pwr_type] %u\n", regulatory->reg_6ghz_power); 859 860 if (tpe6->valid) 861 seq_printf(m, "[TPE] %d dBm\n", tpe6->constraint); 862 } 863 } 864 865 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 866 { 867 struct rtw89_debugfs_priv *debugfs_priv = m->private; 868 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 869 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 870 const struct dbgfs_txpwr_table *tbl; 871 const struct rtw89_chan *chan; 872 int ret = 0; 873 874 mutex_lock(&rtwdev->mutex); 875 rtw89_leave_ps_mode(rtwdev); 876 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 877 878 rtw89_debug_priv_txpwr_table_get_regd(m, rtwdev, chan); 879 880 seq_puts(m, "[SAR]\n"); 881 rtw89_print_sar(m, rtwdev, chan->freq); 882 883 seq_puts(m, "[TAS]\n"); 884 rtw89_print_tas(m, rtwdev); 885 886 seq_puts(m, "[DAG]\n"); 887 rtw89_print_ant_gain(m, rtwdev, chan); 888 889 tbl = dbgfs_txpwr_tables[chip_gen]; 890 if (!tbl) { 891 ret = -EOPNOTSUPP; 892 goto err; 893 } 894 895 seq_puts(m, "\n[TX power byrate]\n"); 896 ret = __print_txpwr_map(m, rtwdev, tbl->byr); 897 if (ret) 898 goto err; 899 900 seq_puts(m, "\n[TX power limit]\n"); 901 ret = __print_txpwr_map(m, rtwdev, tbl->lmt); 902 if (ret) 903 goto err; 904 905 seq_puts(m, "\n[TX power limit_ru]\n"); 906 ret = __print_txpwr_map(m, rtwdev, tbl->lmt_ru); 907 if (ret) 908 goto err; 909 910 err: 911 mutex_unlock(&rtwdev->mutex); 912 return ret; 913 } 914 915 static ssize_t 916 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 917 const char __user *user_buf, 918 size_t count, loff_t *loff) 919 { 920 struct seq_file *m = (struct seq_file *)filp->private_data; 921 struct rtw89_debugfs_priv *debugfs_priv = m->private; 922 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 923 const struct rtw89_chip_info *chip = rtwdev->chip; 924 char buf[32]; 925 size_t buf_size; 926 int sel; 927 int ret; 928 929 buf_size = min(count, sizeof(buf) - 1); 930 if (copy_from_user(buf, user_buf, buf_size)) 931 return -EFAULT; 932 933 buf[buf_size] = '\0'; 934 ret = kstrtoint(buf, 0, &sel); 935 if (ret) 936 return ret; 937 938 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 939 rtw89_info(rtwdev, "invalid args: %d\n", sel); 940 return -EINVAL; 941 } 942 943 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 944 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 945 chip->chip_id); 946 return -EINVAL; 947 } 948 949 debugfs_priv->cb_data = sel; 950 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 951 952 return count; 953 } 954 955 #define RTW89_MAC_PAGE_SIZE 0x100 956 957 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 958 { 959 struct rtw89_debugfs_priv *debugfs_priv = m->private; 960 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 961 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 962 u32 start, end; 963 u32 i, j, k, page; 964 u32 val; 965 966 switch (reg_sel) { 967 case RTW89_DBG_SEL_MAC_00: 968 seq_puts(m, "Debug selected MAC page 0x00\n"); 969 start = 0x000; 970 end = 0x014; 971 break; 972 case RTW89_DBG_SEL_MAC_30: 973 seq_puts(m, "Debug selected MAC page 0x30\n"); 974 start = 0x030; 975 end = 0x033; 976 break; 977 case RTW89_DBG_SEL_MAC_40: 978 seq_puts(m, "Debug selected MAC page 0x40\n"); 979 start = 0x040; 980 end = 0x07f; 981 break; 982 case RTW89_DBG_SEL_MAC_80: 983 seq_puts(m, "Debug selected MAC page 0x80\n"); 984 start = 0x080; 985 end = 0x09f; 986 break; 987 case RTW89_DBG_SEL_MAC_C0: 988 seq_puts(m, "Debug selected MAC page 0xc0\n"); 989 start = 0x0c0; 990 end = 0x0df; 991 break; 992 case RTW89_DBG_SEL_MAC_E0: 993 seq_puts(m, "Debug selected MAC page 0xe0\n"); 994 start = 0x0e0; 995 end = 0x0ff; 996 break; 997 case RTW89_DBG_SEL_BB: 998 seq_puts(m, "Debug selected BB register\n"); 999 start = 0x100; 1000 end = 0x17f; 1001 break; 1002 case RTW89_DBG_SEL_IQK: 1003 seq_puts(m, "Debug selected IQK register\n"); 1004 start = 0x180; 1005 end = 0x1bf; 1006 break; 1007 case RTW89_DBG_SEL_RFC: 1008 seq_puts(m, "Debug selected RFC register\n"); 1009 start = 0x1c0; 1010 end = 0x1ff; 1011 break; 1012 default: 1013 seq_puts(m, "Selected invalid register page\n"); 1014 return -EINVAL; 1015 } 1016 1017 for (i = start; i <= end; i++) { 1018 page = i << 8; 1019 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1020 seq_printf(m, "%08xh : ", 0x18600000 + j); 1021 for (k = 0; k < 4; k++) { 1022 val = rtw89_read32(rtwdev, j + (k << 2)); 1023 seq_printf(m, "%08x ", val); 1024 } 1025 seq_puts(m, "\n"); 1026 } 1027 } 1028 1029 return 0; 1030 } 1031 1032 static ssize_t 1033 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 1034 const char __user *user_buf, 1035 size_t count, loff_t *loff) 1036 { 1037 struct seq_file *m = (struct seq_file *)filp->private_data; 1038 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1039 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1040 char buf[32]; 1041 size_t buf_size; 1042 u32 sel, start_addr, len; 1043 int num; 1044 1045 buf_size = min(count, sizeof(buf) - 1); 1046 if (copy_from_user(buf, user_buf, buf_size)) 1047 return -EFAULT; 1048 1049 buf[buf_size] = '\0'; 1050 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1051 if (num != 3) { 1052 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1053 return -EINVAL; 1054 } 1055 1056 debugfs_priv->mac_mem.sel = sel; 1057 debugfs_priv->mac_mem.start = start_addr; 1058 debugfs_priv->mac_mem.len = len; 1059 1060 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1061 sel, start_addr, len); 1062 1063 return count; 1064 } 1065 1066 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 1067 struct rtw89_dev *rtwdev, 1068 u8 sel, u32 start_addr, u32 len) 1069 { 1070 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1071 u32 filter_model_addr = mac->filter_model_addr; 1072 u32 indir_access_addr = mac->indir_access_addr; 1073 u32 base_addr, start_page, residue; 1074 u32 i, j, p, pages; 1075 u32 dump_len, remain; 1076 u32 val; 1077 1078 remain = len; 1079 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 1080 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 1081 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 1082 base_addr = mac->mem_base_addrs[sel]; 1083 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 1084 1085 for (p = 0; p < pages; p++) { 1086 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 1087 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1088 for (i = indir_access_addr + residue; 1089 i < indir_access_addr + dump_len;) { 1090 seq_printf(m, "%08xh:", i); 1091 for (j = 0; 1092 j < 4 && i < indir_access_addr + dump_len; 1093 j++, i += 4) { 1094 val = rtw89_read32(rtwdev, i); 1095 seq_printf(m, " %08x", val); 1096 remain -= 4; 1097 } 1098 seq_puts(m, "\n"); 1099 } 1100 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 1101 } 1102 } 1103 1104 static int 1105 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 1106 { 1107 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1108 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1109 bool grant_read = false; 1110 1111 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1112 return -ENOENT; 1113 1114 if (rtwdev->chip->chip_id == RTL8852C) { 1115 switch (debugfs_priv->mac_mem.sel) { 1116 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1117 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1118 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1119 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1120 grant_read = true; 1121 break; 1122 default: 1123 break; 1124 } 1125 } 1126 1127 mutex_lock(&rtwdev->mutex); 1128 rtw89_leave_ps_mode(rtwdev); 1129 if (grant_read) 1130 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1131 rtw89_debug_dump_mac_mem(m, rtwdev, 1132 debugfs_priv->mac_mem.sel, 1133 debugfs_priv->mac_mem.start, 1134 debugfs_priv->mac_mem.len); 1135 if (grant_read) 1136 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1137 mutex_unlock(&rtwdev->mutex); 1138 1139 return 0; 1140 } 1141 1142 static ssize_t 1143 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 1144 const char __user *user_buf, 1145 size_t count, loff_t *loff) 1146 { 1147 struct seq_file *m = (struct seq_file *)filp->private_data; 1148 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1149 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1150 char buf[32]; 1151 size_t buf_size; 1152 int sel, set; 1153 int num; 1154 bool enable; 1155 1156 buf_size = min(count, sizeof(buf) - 1); 1157 if (copy_from_user(buf, user_buf, buf_size)) 1158 return -EFAULT; 1159 1160 buf[buf_size] = '\0'; 1161 num = sscanf(buf, "%d %d", &sel, &set); 1162 if (num != 2) { 1163 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1164 return -EINVAL; 1165 } 1166 1167 enable = set != 0; 1168 switch (sel) { 1169 case 0: 1170 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1171 break; 1172 case 1: 1173 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1174 break; 1175 case 2: 1176 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1177 break; 1178 case 3: 1179 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1180 break; 1181 case 4: 1182 debugfs_priv->dbgpkg_en.dbg_port = enable; 1183 break; 1184 default: 1185 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1186 return -EINVAL; 1187 } 1188 1189 rtw89_info(rtwdev, "%s debug port dump %d\n", 1190 enable ? "Enable" : "Disable", sel); 1191 1192 return count; 1193 } 1194 1195 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1196 struct seq_file *m) 1197 { 1198 return 0; 1199 } 1200 1201 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1202 struct seq_file *m) 1203 { 1204 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1205 ({ \ 1206 u32 __ctrl; \ 1207 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1208 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1209 u32 __data, __val32; \ 1210 int __ret; \ 1211 \ 1212 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1213 DLE_DFI_TYPE_##__target) | \ 1214 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1215 B_AX_WDE_DFI_ACTIVE; \ 1216 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1217 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1218 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1219 1000, 50000, false, \ 1220 rtwdev, __reg_ctrl); \ 1221 if (__ret) { \ 1222 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1223 #__type, #__target, __sel); \ 1224 return __ret; \ 1225 } \ 1226 \ 1227 __data = rtw89_read32(rtwdev, __reg_data); \ 1228 __data; \ 1229 }) 1230 1231 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 1232 ({ \ 1233 u32 __freepg, __pubpg; \ 1234 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1235 \ 1236 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1237 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1238 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1239 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1240 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1241 seq_printf(__m, "[%s] freepg head: %d\n", \ 1242 #__type, __freepg_head); \ 1243 seq_printf(__m, "[%s] freepg tail: %d\n", \ 1244 #__type, __freepg_tail); \ 1245 seq_printf(__m, "[%s] pubpg num : %d\n", \ 1246 #__type, __pubpg_num); \ 1247 }) 1248 1249 #define case_QUOTA(__m, __type, __id) \ 1250 case __type##_QTAID_##__id: \ 1251 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1252 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1253 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1254 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 1255 #__type, #__id, rsv_pgnum); \ 1256 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 1257 #__type, #__id, use_pgnum); \ 1258 break 1259 u32 quota_id; 1260 u32 val32; 1261 u16 rsv_pgnum, use_pgnum; 1262 int ret; 1263 1264 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1265 if (ret) { 1266 seq_puts(m, "[DLE] : DMAC not enabled\n"); 1267 return ret; 1268 } 1269 1270 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 1271 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 1272 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1273 switch (quota_id) { 1274 case_QUOTA(m, WDE, HOST_IF); 1275 case_QUOTA(m, WDE, WLAN_CPU); 1276 case_QUOTA(m, WDE, DATA_CPU); 1277 case_QUOTA(m, WDE, PKTIN); 1278 case_QUOTA(m, WDE, CPUIO); 1279 } 1280 } 1281 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1282 switch (quota_id) { 1283 case_QUOTA(m, PLE, B0_TXPL); 1284 case_QUOTA(m, PLE, B1_TXPL); 1285 case_QUOTA(m, PLE, C2H); 1286 case_QUOTA(m, PLE, H2C); 1287 case_QUOTA(m, PLE, WLAN_CPU); 1288 case_QUOTA(m, PLE, MPDU); 1289 case_QUOTA(m, PLE, CMAC0_RX); 1290 case_QUOTA(m, PLE, CMAC1_RX); 1291 case_QUOTA(m, PLE, CMAC1_BBRPT); 1292 case_QUOTA(m, PLE, WDRLS); 1293 case_QUOTA(m, PLE, CPUIO); 1294 } 1295 } 1296 1297 return 0; 1298 1299 #undef case_QUOTA 1300 #undef DLE_DFI_DUMP 1301 #undef DLE_DFI_FREE_PAGE_DUMP 1302 } 1303 1304 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1305 struct seq_file *m) 1306 { 1307 const struct rtw89_chip_info *chip = rtwdev->chip; 1308 u32 dmac_err; 1309 int i, ret; 1310 1311 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1312 if (ret) { 1313 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 1314 return ret; 1315 } 1316 1317 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1318 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1319 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1320 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1321 1322 if (dmac_err) { 1323 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1324 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1325 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1326 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1327 if (chip->chip_id == RTL8852C) { 1328 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1329 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1330 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1331 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1332 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1333 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1334 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n", 1335 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1336 } 1337 } 1338 1339 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1340 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1341 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1342 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1343 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1344 if (chip->chip_id == RTL8852C) 1345 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1346 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1347 else 1348 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1349 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1350 } 1351 1352 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1353 if (chip->chip_id == RTL8852C) { 1354 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n", 1355 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1356 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n", 1357 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1358 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1359 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1360 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1361 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1362 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1363 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1364 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1365 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1366 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n", 1367 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1368 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1369 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1370 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1371 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1372 1373 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1374 B_AX_DBG_SEL0, 0x8B); 1375 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1376 B_AX_DBG_SEL1, 0x8B); 1377 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1378 B_AX_SEL_0XC0_MASK, 1); 1379 for (i = 0; i < 0x10; i++) { 1380 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1381 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1382 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1383 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1384 } 1385 } else { 1386 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1387 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1388 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1389 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1390 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1391 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1392 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1393 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1394 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1395 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1396 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n", 1397 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1398 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1399 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1400 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1401 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1402 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1403 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1404 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1405 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1406 } 1407 } 1408 1409 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1410 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1411 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1412 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1413 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1414 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1415 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1416 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1417 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1418 } 1419 1420 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1421 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1422 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1423 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1424 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1425 } 1426 1427 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1428 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1429 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1430 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1431 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1432 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1433 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1434 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1435 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1436 } 1437 1438 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1439 if (chip->chip_id == RTL8852C) { 1440 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1441 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1442 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1443 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1444 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1445 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1446 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1447 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1448 } else { 1449 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1450 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1451 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1452 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1453 } 1454 } 1455 1456 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1457 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1458 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1459 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1460 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1461 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1462 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1463 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1464 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1465 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1466 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1467 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1468 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1469 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1470 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1471 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1472 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1473 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1474 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1475 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1476 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1477 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1478 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1479 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1480 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1481 if (chip->chip_id == RTL8852C) { 1482 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n", 1483 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1484 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n", 1485 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1486 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n", 1487 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1488 } else { 1489 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1490 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1491 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1492 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1493 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1494 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1495 } 1496 } 1497 1498 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1499 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1500 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1501 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1502 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1503 } 1504 1505 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1506 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1507 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1508 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1509 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1510 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1511 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1512 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1513 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1514 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1515 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1516 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1517 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1518 } 1519 1520 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1521 if (chip->chip_id == RTL8852C) { 1522 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1523 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1524 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1525 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1526 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1527 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1528 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1529 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1530 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1531 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1532 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1533 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1534 } else { 1535 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1536 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1537 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1538 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1539 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1540 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1541 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1542 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1543 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1544 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1545 } 1546 } 1547 1548 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1549 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1550 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1551 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1552 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1553 } 1554 1555 return 0; 1556 } 1557 1558 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1559 struct seq_file *m, 1560 enum rtw89_mac_idx band) 1561 { 1562 const struct rtw89_chip_info *chip = rtwdev->chip; 1563 u32 offset = 0; 1564 u32 cmac_err; 1565 int ret; 1566 1567 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1568 if (ret) { 1569 if (band) 1570 seq_puts(m, "[CMAC] : CMAC1 not enabled\n"); 1571 else 1572 seq_puts(m, "[CMAC] : CMAC0 not enabled\n"); 1573 return ret; 1574 } 1575 1576 if (band) 1577 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1578 1579 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1580 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1581 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1582 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1583 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1584 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band, 1585 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1586 1587 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1588 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1589 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1590 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1591 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1592 } 1593 1594 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1595 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 1596 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1597 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 1598 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1599 } 1600 1601 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1602 if (chip->chip_id == RTL8852C) { 1603 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1604 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1605 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 1606 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1607 } else { 1608 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1609 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1610 } 1611 } 1612 1613 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1614 if (chip->chip_id == RTL8852C) { 1615 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 1616 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1617 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1618 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1619 } else { 1620 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1621 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1622 } 1623 } 1624 1625 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1626 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 1627 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1628 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 1629 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1630 } 1631 1632 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1633 if (chip->chip_id == RTL8852C) { 1634 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 1635 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 1636 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 1637 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1638 } else { 1639 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 1640 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 1641 } 1642 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1643 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1644 } 1645 1646 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1647 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1648 1649 return 0; 1650 } 1651 1652 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1653 struct seq_file *m) 1654 { 1655 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0); 1656 if (rtwdev->dbcc_en) 1657 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1); 1658 1659 return 0; 1660 } 1661 1662 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1663 .sel_addr = R_AX_PTCL_DBG, 1664 .sel_byte = 1, 1665 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1666 .srt = 0x00, 1667 .end = 0x3F, 1668 .rd_addr = R_AX_PTCL_DBG_INFO, 1669 .rd_byte = 4, 1670 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1671 }; 1672 1673 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1674 .sel_addr = R_AX_PTCL_DBG_C1, 1675 .sel_byte = 1, 1676 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1677 .srt = 0x00, 1678 .end = 0x3F, 1679 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1680 .rd_byte = 4, 1681 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1682 }; 1683 1684 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1685 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1686 .sel_byte = 2, 1687 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1688 .srt = 0x0, 1689 .end = 0xD, 1690 .rd_addr = R_AX_DBG_PORT_SEL, 1691 .rd_byte = 4, 1692 .rd_msk = B_AX_DEBUG_ST_MASK 1693 }; 1694 1695 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1696 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1697 .sel_byte = 2, 1698 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1699 .srt = 0x0, 1700 .end = 0x5, 1701 .rd_addr = R_AX_DBG_PORT_SEL, 1702 .rd_byte = 4, 1703 .rd_msk = B_AX_DEBUG_ST_MASK 1704 }; 1705 1706 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1707 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1708 .sel_byte = 2, 1709 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1710 .srt = 0x0, 1711 .end = 0x9, 1712 .rd_addr = R_AX_DBG_PORT_SEL, 1713 .rd_byte = 4, 1714 .rd_msk = B_AX_DEBUG_ST_MASK 1715 }; 1716 1717 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1718 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1719 .sel_byte = 2, 1720 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1721 .srt = 0x0, 1722 .end = 0x3, 1723 .rd_addr = R_AX_DBG_PORT_SEL, 1724 .rd_byte = 4, 1725 .rd_msk = B_AX_DEBUG_ST_MASK 1726 }; 1727 1728 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1729 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1730 .sel_byte = 2, 1731 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1732 .srt = 0x0, 1733 .end = 0x1, 1734 .rd_addr = R_AX_DBG_PORT_SEL, 1735 .rd_byte = 4, 1736 .rd_msk = B_AX_DEBUG_ST_MASK 1737 }; 1738 1739 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1740 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1741 .sel_byte = 2, 1742 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1743 .srt = 0x0, 1744 .end = 0x0, 1745 .rd_addr = R_AX_DBG_PORT_SEL, 1746 .rd_byte = 4, 1747 .rd_msk = B_AX_DEBUG_ST_MASK 1748 }; 1749 1750 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1751 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1752 .sel_byte = 2, 1753 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1754 .srt = 0x0, 1755 .end = 0xB, 1756 .rd_addr = R_AX_DBG_PORT_SEL, 1757 .rd_byte = 4, 1758 .rd_msk = B_AX_DEBUG_ST_MASK 1759 }; 1760 1761 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1762 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1763 .sel_byte = 2, 1764 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1765 .srt = 0x0, 1766 .end = 0x4, 1767 .rd_addr = R_AX_DBG_PORT_SEL, 1768 .rd_byte = 4, 1769 .rd_msk = B_AX_DEBUG_ST_MASK 1770 }; 1771 1772 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1773 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1774 .sel_byte = 2, 1775 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1776 .srt = 0x0, 1777 .end = 0x8, 1778 .rd_addr = R_AX_DBG_PORT_SEL, 1779 .rd_byte = 4, 1780 .rd_msk = B_AX_DEBUG_ST_MASK 1781 }; 1782 1783 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1784 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1785 .sel_byte = 2, 1786 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1787 .srt = 0x0, 1788 .end = 0x7, 1789 .rd_addr = R_AX_DBG_PORT_SEL, 1790 .rd_byte = 4, 1791 .rd_msk = B_AX_DEBUG_ST_MASK 1792 }; 1793 1794 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1795 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1796 .sel_byte = 2, 1797 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1798 .srt = 0x0, 1799 .end = 0x1, 1800 .rd_addr = R_AX_DBG_PORT_SEL, 1801 .rd_byte = 4, 1802 .rd_msk = B_AX_DEBUG_ST_MASK 1803 }; 1804 1805 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1806 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1807 .sel_byte = 2, 1808 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1809 .srt = 0x0, 1810 .end = 0x3, 1811 .rd_addr = R_AX_DBG_PORT_SEL, 1812 .rd_byte = 4, 1813 .rd_msk = B_AX_DEBUG_ST_MASK 1814 }; 1815 1816 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1817 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1818 .sel_byte = 2, 1819 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1820 .srt = 0x0, 1821 .end = 0x0, 1822 .rd_addr = R_AX_DBG_PORT_SEL, 1823 .rd_byte = 4, 1824 .rd_msk = B_AX_DEBUG_ST_MASK 1825 }; 1826 1827 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1828 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1829 .sel_byte = 2, 1830 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1831 .srt = 0x0, 1832 .end = 0x8, 1833 .rd_addr = R_AX_DBG_PORT_SEL, 1834 .rd_byte = 4, 1835 .rd_msk = B_AX_DEBUG_ST_MASK 1836 }; 1837 1838 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1839 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1840 .sel_byte = 2, 1841 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1842 .srt = 0x0, 1843 .end = 0x0, 1844 .rd_addr = R_AX_DBG_PORT_SEL, 1845 .rd_byte = 4, 1846 .rd_msk = B_AX_DEBUG_ST_MASK 1847 }; 1848 1849 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1850 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1851 .sel_byte = 2, 1852 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1853 .srt = 0x0, 1854 .end = 0x6, 1855 .rd_addr = R_AX_DBG_PORT_SEL, 1856 .rd_byte = 4, 1857 .rd_msk = B_AX_DEBUG_ST_MASK 1858 }; 1859 1860 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1861 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1862 .sel_byte = 2, 1863 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1864 .srt = 0x0, 1865 .end = 0x0, 1866 .rd_addr = R_AX_DBG_PORT_SEL, 1867 .rd_byte = 4, 1868 .rd_msk = B_AX_DEBUG_ST_MASK 1869 }; 1870 1871 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 1872 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1873 .sel_byte = 2, 1874 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1875 .srt = 0x0, 1876 .end = 0x0, 1877 .rd_addr = R_AX_DBG_PORT_SEL, 1878 .rd_byte = 4, 1879 .rd_msk = B_AX_DEBUG_ST_MASK 1880 }; 1881 1882 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 1883 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1884 .sel_byte = 1, 1885 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1886 .srt = 0x0, 1887 .end = 0x3, 1888 .rd_addr = R_AX_DBG_PORT_SEL, 1889 .rd_byte = 4, 1890 .rd_msk = B_AX_DEBUG_ST_MASK 1891 }; 1892 1893 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 1894 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1895 .sel_byte = 1, 1896 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1897 .srt = 0x0, 1898 .end = 0x6, 1899 .rd_addr = R_AX_DBG_PORT_SEL, 1900 .rd_byte = 4, 1901 .rd_msk = B_AX_DEBUG_ST_MASK 1902 }; 1903 1904 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 1905 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1906 .sel_byte = 1, 1907 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1908 .srt = 0x0, 1909 .end = 0x0, 1910 .rd_addr = R_AX_DBG_PORT_SEL, 1911 .rd_byte = 4, 1912 .rd_msk = B_AX_DEBUG_ST_MASK 1913 }; 1914 1915 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 1916 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1917 .sel_byte = 1, 1918 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1919 .srt = 0x8, 1920 .end = 0xE, 1921 .rd_addr = R_AX_DBG_PORT_SEL, 1922 .rd_byte = 4, 1923 .rd_msk = B_AX_DEBUG_ST_MASK 1924 }; 1925 1926 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 1927 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1928 .sel_byte = 1, 1929 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1930 .srt = 0x0, 1931 .end = 0x5, 1932 .rd_addr = R_AX_DBG_PORT_SEL, 1933 .rd_byte = 4, 1934 .rd_msk = B_AX_DEBUG_ST_MASK 1935 }; 1936 1937 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 1938 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1939 .sel_byte = 1, 1940 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1941 .srt = 0x0, 1942 .end = 0x6, 1943 .rd_addr = R_AX_DBG_PORT_SEL, 1944 .rd_byte = 4, 1945 .rd_msk = B_AX_DEBUG_ST_MASK 1946 }; 1947 1948 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 1949 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1950 .sel_byte = 1, 1951 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1952 .srt = 0x0, 1953 .end = 0xF, 1954 .rd_addr = R_AX_DBG_PORT_SEL, 1955 .rd_byte = 4, 1956 .rd_msk = B_AX_DEBUG_ST_MASK 1957 }; 1958 1959 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 1960 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1961 .sel_byte = 1, 1962 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1963 .srt = 0x0, 1964 .end = 0x9, 1965 .rd_addr = R_AX_DBG_PORT_SEL, 1966 .rd_byte = 4, 1967 .rd_msk = B_AX_DEBUG_ST_MASK 1968 }; 1969 1970 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 1971 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1972 .sel_byte = 1, 1973 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1974 .srt = 0x0, 1975 .end = 0x3, 1976 .rd_addr = R_AX_DBG_PORT_SEL, 1977 .rd_byte = 4, 1978 .rd_msk = B_AX_DEBUG_ST_MASK 1979 }; 1980 1981 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1982 .sel_addr = R_AX_SCH_DBG_SEL, 1983 .sel_byte = 1, 1984 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1985 .srt = 0x00, 1986 .end = 0x2F, 1987 .rd_addr = R_AX_SCH_DBG, 1988 .rd_byte = 4, 1989 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1990 }; 1991 1992 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1993 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1994 .sel_byte = 1, 1995 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1996 .srt = 0x00, 1997 .end = 0x2F, 1998 .rd_addr = R_AX_SCH_DBG_C1, 1999 .rd_byte = 4, 2000 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2001 }; 2002 2003 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2004 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2005 .sel_byte = 1, 2006 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2007 .srt = 0x00, 2008 .end = 0x19, 2009 .rd_addr = R_AX_DBG_PORT_SEL, 2010 .rd_byte = 4, 2011 .rd_msk = B_AX_DEBUG_ST_MASK 2012 }; 2013 2014 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2015 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2016 .sel_byte = 1, 2017 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2018 .srt = 0x00, 2019 .end = 0x19, 2020 .rd_addr = R_AX_DBG_PORT_SEL, 2021 .rd_byte = 4, 2022 .rd_msk = B_AX_DEBUG_ST_MASK 2023 }; 2024 2025 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2026 .sel_addr = R_AX_RX_DEBUG_SELECT, 2027 .sel_byte = 1, 2028 .sel_msk = B_AX_DEBUG_SEL_MASK, 2029 .srt = 0x00, 2030 .end = 0x58, 2031 .rd_addr = R_AX_DBG_PORT_SEL, 2032 .rd_byte = 4, 2033 .rd_msk = B_AX_DEBUG_ST_MASK 2034 }; 2035 2036 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2037 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2038 .sel_byte = 1, 2039 .sel_msk = B_AX_DEBUG_SEL_MASK, 2040 .srt = 0x00, 2041 .end = 0x58, 2042 .rd_addr = R_AX_DBG_PORT_SEL, 2043 .rd_byte = 4, 2044 .rd_msk = B_AX_DEBUG_ST_MASK 2045 }; 2046 2047 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2048 .sel_addr = R_AX_RX_STATE_MONITOR, 2049 .sel_byte = 1, 2050 .sel_msk = B_AX_STATE_SEL_MASK, 2051 .srt = 0x00, 2052 .end = 0x17, 2053 .rd_addr = R_AX_RX_STATE_MONITOR, 2054 .rd_byte = 4, 2055 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2056 }; 2057 2058 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2059 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2060 .sel_byte = 1, 2061 .sel_msk = B_AX_STATE_SEL_MASK, 2062 .srt = 0x00, 2063 .end = 0x17, 2064 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2065 .rd_byte = 4, 2066 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2067 }; 2068 2069 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2070 .sel_addr = R_AX_RMAC_PLCP_MON, 2071 .sel_byte = 4, 2072 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2073 .srt = 0x0, 2074 .end = 0xF, 2075 .rd_addr = R_AX_RMAC_PLCP_MON, 2076 .rd_byte = 4, 2077 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2078 }; 2079 2080 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2081 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2082 .sel_byte = 4, 2083 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2084 .srt = 0x0, 2085 .end = 0xF, 2086 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2087 .rd_byte = 4, 2088 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2089 }; 2090 2091 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2092 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2093 .sel_byte = 1, 2094 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2095 .srt = 0x08, 2096 .end = 0x10, 2097 .rd_addr = R_AX_DBG_PORT_SEL, 2098 .rd_byte = 4, 2099 .rd_msk = B_AX_DEBUG_ST_MASK 2100 }; 2101 2102 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2103 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2104 .sel_byte = 1, 2105 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2106 .srt = 0x08, 2107 .end = 0x10, 2108 .rd_addr = R_AX_DBG_PORT_SEL, 2109 .rd_byte = 4, 2110 .rd_msk = B_AX_DEBUG_ST_MASK 2111 }; 2112 2113 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2114 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2115 .sel_byte = 1, 2116 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2117 .srt = 0x00, 2118 .end = 0x07, 2119 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2120 .rd_byte = 4, 2121 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2122 }; 2123 2124 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2125 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2126 .sel_byte = 1, 2127 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2128 .srt = 0x00, 2129 .end = 0x07, 2130 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2131 .rd_byte = 4, 2132 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2133 }; 2134 2135 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2136 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2137 .sel_byte = 1, 2138 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2139 .srt = 0x00, 2140 .end = 0x07, 2141 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2142 .rd_byte = 4, 2143 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2144 }; 2145 2146 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2147 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2148 .sel_byte = 1, 2149 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2150 .srt = 0x00, 2151 .end = 0x07, 2152 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2153 .rd_byte = 4, 2154 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2155 }; 2156 2157 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2158 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2159 .sel_byte = 1, 2160 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2161 .srt = 0x00, 2162 .end = 0x04, 2163 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2164 .rd_byte = 4, 2165 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2166 }; 2167 2168 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2169 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2170 .sel_byte = 1, 2171 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2172 .srt = 0x00, 2173 .end = 0x04, 2174 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2175 .rd_byte = 4, 2176 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2177 }; 2178 2179 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2180 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2181 .sel_byte = 1, 2182 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2183 .srt = 0x00, 2184 .end = 0x04, 2185 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2186 .rd_byte = 4, 2187 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2188 }; 2189 2190 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2191 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2192 .sel_byte = 1, 2193 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2194 .srt = 0x00, 2195 .end = 0x04, 2196 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2197 .rd_byte = 4, 2198 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2199 }; 2200 2201 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2202 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2203 .sel_byte = 4, 2204 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2205 .srt = 0x80000000, 2206 .end = 0x80000001, 2207 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2208 .rd_byte = 4, 2209 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2210 }; 2211 2212 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2213 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2214 .sel_byte = 4, 2215 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2216 .srt = 0x80010000, 2217 .end = 0x80010004, 2218 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2219 .rd_byte = 4, 2220 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2221 }; 2222 2223 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2224 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2225 .sel_byte = 4, 2226 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2227 .srt = 0x80020000, 2228 .end = 0x80020FFF, 2229 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2230 .rd_byte = 4, 2231 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2232 }; 2233 2234 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2235 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2236 .sel_byte = 4, 2237 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2238 .srt = 0x80030000, 2239 .end = 0x80030FFF, 2240 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2241 .rd_byte = 4, 2242 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2243 }; 2244 2245 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2246 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2247 .sel_byte = 4, 2248 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2249 .srt = 0x80040000, 2250 .end = 0x80040FFF, 2251 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2252 .rd_byte = 4, 2253 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2254 }; 2255 2256 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2257 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2258 .sel_byte = 4, 2259 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2260 .srt = 0x80050000, 2261 .end = 0x80050FFF, 2262 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2263 .rd_byte = 4, 2264 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2265 }; 2266 2267 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2268 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2269 .sel_byte = 4, 2270 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2271 .srt = 0x80060000, 2272 .end = 0x80060453, 2273 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2274 .rd_byte = 4, 2275 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2276 }; 2277 2278 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2279 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2280 .sel_byte = 4, 2281 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2282 .srt = 0x80070000, 2283 .end = 0x80070011, 2284 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2285 .rd_byte = 4, 2286 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2287 }; 2288 2289 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2290 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2291 .sel_byte = 4, 2292 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2293 .srt = 0x80000000, 2294 .end = 0x80000001, 2295 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2296 .rd_byte = 4, 2297 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2298 }; 2299 2300 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2301 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2302 .sel_byte = 4, 2303 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2304 .srt = 0x80010000, 2305 .end = 0x8001000A, 2306 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2307 .rd_byte = 4, 2308 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2309 }; 2310 2311 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2312 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2313 .sel_byte = 4, 2314 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2315 .srt = 0x80020000, 2316 .end = 0x80020DBF, 2317 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2318 .rd_byte = 4, 2319 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2320 }; 2321 2322 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2323 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2324 .sel_byte = 4, 2325 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2326 .srt = 0x80030000, 2327 .end = 0x80030DBF, 2328 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2329 .rd_byte = 4, 2330 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2331 }; 2332 2333 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2334 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2335 .sel_byte = 4, 2336 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2337 .srt = 0x80040000, 2338 .end = 0x80040DBF, 2339 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2340 .rd_byte = 4, 2341 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2342 }; 2343 2344 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2345 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2346 .sel_byte = 4, 2347 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2348 .srt = 0x80050000, 2349 .end = 0x80050DBF, 2350 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2351 .rd_byte = 4, 2352 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2353 }; 2354 2355 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2356 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2357 .sel_byte = 4, 2358 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2359 .srt = 0x80060000, 2360 .end = 0x80060041, 2361 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2362 .rd_byte = 4, 2363 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2364 }; 2365 2366 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2367 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2368 .sel_byte = 4, 2369 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2370 .srt = 0x80070000, 2371 .end = 0x80070001, 2372 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2373 .rd_byte = 4, 2374 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2375 }; 2376 2377 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2378 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2379 .sel_byte = 4, 2380 .sel_msk = B_AX_DFI_DATA_MASK, 2381 .srt = 0x80000000, 2382 .end = 0x8000017f, 2383 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2384 .rd_byte = 4, 2385 .rd_msk = B_AX_DFI_DATA_MASK 2386 }; 2387 2388 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2389 .sel_addr = R_AX_PCIE_DBG_CTRL, 2390 .sel_byte = 2, 2391 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2392 .srt = 0x00, 2393 .end = 0x03, 2394 .rd_addr = R_AX_DBG_PORT_SEL, 2395 .rd_byte = 4, 2396 .rd_msk = B_AX_DEBUG_ST_MASK 2397 }; 2398 2399 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2400 .sel_addr = R_AX_PCIE_DBG_CTRL, 2401 .sel_byte = 2, 2402 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2403 .srt = 0x00, 2404 .end = 0x04, 2405 .rd_addr = R_AX_DBG_PORT_SEL, 2406 .rd_byte = 4, 2407 .rd_msk = B_AX_DEBUG_ST_MASK 2408 }; 2409 2410 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2411 .sel_addr = R_AX_PCIE_DBG_CTRL, 2412 .sel_byte = 2, 2413 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2414 .srt = 0x00, 2415 .end = 0x01, 2416 .rd_addr = R_AX_DBG_PORT_SEL, 2417 .rd_byte = 4, 2418 .rd_msk = B_AX_DEBUG_ST_MASK 2419 }; 2420 2421 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2422 .sel_addr = R_AX_PCIE_DBG_CTRL, 2423 .sel_byte = 2, 2424 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2425 .srt = 0x00, 2426 .end = 0x05, 2427 .rd_addr = R_AX_DBG_PORT_SEL, 2428 .rd_byte = 4, 2429 .rd_msk = B_AX_DEBUG_ST_MASK 2430 }; 2431 2432 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2433 .sel_addr = R_AX_PCIE_DBG_CTRL, 2434 .sel_byte = 2, 2435 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2436 .srt = 0x00, 2437 .end = 0x05, 2438 .rd_addr = R_AX_DBG_PORT_SEL, 2439 .rd_byte = 4, 2440 .rd_msk = B_AX_DEBUG_ST_MASK 2441 }; 2442 2443 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2444 .sel_addr = R_AX_PCIE_DBG_CTRL, 2445 .sel_byte = 2, 2446 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2447 .srt = 0x00, 2448 .end = 0x06, 2449 .rd_addr = R_AX_DBG_PORT_SEL, 2450 .rd_byte = 4, 2451 .rd_msk = B_AX_DEBUG_ST_MASK 2452 }; 2453 2454 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2455 .sel_addr = R_AX_DBG_CTRL, 2456 .sel_byte = 1, 2457 .sel_msk = B_AX_DBG_SEL0, 2458 .srt = 0x34, 2459 .end = 0x3C, 2460 .rd_addr = R_AX_DBG_PORT_SEL, 2461 .rd_byte = 4, 2462 .rd_msk = B_AX_DEBUG_ST_MASK 2463 }; 2464 2465 static const struct rtw89_mac_dbg_port_info * 2466 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 2467 struct rtw89_dev *rtwdev, u32 sel) 2468 { 2469 const struct rtw89_mac_dbg_port_info *info; 2470 u32 index; 2471 u32 val32; 2472 u16 val16; 2473 u8 val8; 2474 2475 switch (sel) { 2476 case RTW89_DBG_PORT_SEL_PTCL_C0: 2477 info = &dbg_port_ptcl_c0; 2478 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2479 val16 |= B_AX_PTCL_DBG_EN; 2480 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2481 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 2482 break; 2483 case RTW89_DBG_PORT_SEL_PTCL_C1: 2484 info = &dbg_port_ptcl_c1; 2485 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2486 val16 |= B_AX_PTCL_DBG_EN; 2487 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2488 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 2489 break; 2490 case RTW89_DBG_PORT_SEL_SCH_C0: 2491 info = &dbg_port_sch_c0; 2492 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2493 val32 |= B_AX_SCH_DBG_EN; 2494 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2495 seq_puts(m, "Enable SCH C0 dbgport.\n"); 2496 break; 2497 case RTW89_DBG_PORT_SEL_SCH_C1: 2498 info = &dbg_port_sch_c1; 2499 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2500 val32 |= B_AX_SCH_DBG_EN; 2501 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2502 seq_puts(m, "Enable SCH C1 dbgport.\n"); 2503 break; 2504 case RTW89_DBG_PORT_SEL_TMAC_C0: 2505 info = &dbg_port_tmac_c0; 2506 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2507 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2508 B_AX_DBGSEL_TRXPTCL_MASK); 2509 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2510 2511 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2512 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2513 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2514 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2515 2516 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2517 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2518 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2519 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 2520 break; 2521 case RTW89_DBG_PORT_SEL_TMAC_C1: 2522 info = &dbg_port_tmac_c1; 2523 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2524 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2525 B_AX_DBGSEL_TRXPTCL_MASK); 2526 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2527 2528 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2529 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2530 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2531 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2532 2533 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2534 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2535 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2536 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 2537 break; 2538 case RTW89_DBG_PORT_SEL_RMAC_C0: 2539 info = &dbg_port_rmac_c0; 2540 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2541 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2542 B_AX_DBGSEL_TRXPTCL_MASK); 2543 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2544 2545 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2546 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2547 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2548 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2549 2550 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2551 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2552 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2553 2554 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2555 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2556 B_AX_DBGSEL_TRXPTCL_MASK); 2557 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2558 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 2559 break; 2560 case RTW89_DBG_PORT_SEL_RMAC_C1: 2561 info = &dbg_port_rmac_c1; 2562 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2563 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2564 B_AX_DBGSEL_TRXPTCL_MASK); 2565 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2566 2567 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2568 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2569 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2570 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2571 2572 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2573 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2574 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2575 2576 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2577 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2578 B_AX_DBGSEL_TRXPTCL_MASK); 2579 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2580 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 2581 break; 2582 case RTW89_DBG_PORT_SEL_RMACST_C0: 2583 info = &dbg_port_rmacst_c0; 2584 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 2585 break; 2586 case RTW89_DBG_PORT_SEL_RMACST_C1: 2587 info = &dbg_port_rmacst_c1; 2588 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 2589 break; 2590 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2591 info = &dbg_port_rmac_plcp_c0; 2592 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 2593 break; 2594 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2595 info = &dbg_port_rmac_plcp_c1; 2596 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 2597 break; 2598 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2599 info = &dbg_port_trxptcl_c0; 2600 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2601 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2602 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2603 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2604 2605 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2606 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2607 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2608 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 2609 break; 2610 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2611 info = &dbg_port_trxptcl_c1; 2612 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2613 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2614 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2615 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2616 2617 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2618 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2619 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2620 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 2621 break; 2622 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2623 info = &dbg_port_tx_infol_c0; 2624 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2625 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2626 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2627 seq_puts(m, "Enable tx infol dump.\n"); 2628 break; 2629 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2630 info = &dbg_port_tx_infoh_c0; 2631 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2632 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2633 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2634 seq_puts(m, "Enable tx infoh dump.\n"); 2635 break; 2636 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2637 info = &dbg_port_tx_infol_c1; 2638 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2639 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2640 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2641 seq_puts(m, "Enable tx infol dump.\n"); 2642 break; 2643 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2644 info = &dbg_port_tx_infoh_c1; 2645 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2646 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2647 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2648 seq_puts(m, "Enable tx infoh dump.\n"); 2649 break; 2650 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2651 info = &dbg_port_txtf_infol_c0; 2652 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2653 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2654 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2655 seq_puts(m, "Enable tx tf infol dump.\n"); 2656 break; 2657 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2658 info = &dbg_port_txtf_infoh_c0; 2659 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2660 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2661 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2662 seq_puts(m, "Enable tx tf infoh dump.\n"); 2663 break; 2664 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2665 info = &dbg_port_txtf_infol_c1; 2666 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2667 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2668 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2669 seq_puts(m, "Enable tx tf infol dump.\n"); 2670 break; 2671 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2672 info = &dbg_port_txtf_infoh_c1; 2673 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2674 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2675 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2676 seq_puts(m, "Enable tx tf infoh dump.\n"); 2677 break; 2678 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2679 info = &dbg_port_wde_bufmgn_freepg; 2680 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 2681 break; 2682 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2683 info = &dbg_port_wde_bufmgn_quota; 2684 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 2685 break; 2686 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2687 info = &dbg_port_wde_bufmgn_pagellt; 2688 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 2689 break; 2690 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2691 info = &dbg_port_wde_bufmgn_pktinfo; 2692 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 2693 break; 2694 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2695 info = &dbg_port_wde_quemgn_prepkt; 2696 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 2697 break; 2698 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2699 info = &dbg_port_wde_quemgn_nxtpkt; 2700 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 2701 break; 2702 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2703 info = &dbg_port_wde_quemgn_qlnktbl; 2704 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 2705 break; 2706 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2707 info = &dbg_port_wde_quemgn_qempty; 2708 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 2709 break; 2710 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2711 info = &dbg_port_ple_bufmgn_freepg; 2712 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 2713 break; 2714 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2715 info = &dbg_port_ple_bufmgn_quota; 2716 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 2717 break; 2718 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2719 info = &dbg_port_ple_bufmgn_pagellt; 2720 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 2721 break; 2722 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2723 info = &dbg_port_ple_bufmgn_pktinfo; 2724 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 2725 break; 2726 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2727 info = &dbg_port_ple_quemgn_prepkt; 2728 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 2729 break; 2730 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2731 info = &dbg_port_ple_quemgn_nxtpkt; 2732 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 2733 break; 2734 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2735 info = &dbg_port_ple_quemgn_qlnktbl; 2736 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 2737 break; 2738 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2739 info = &dbg_port_ple_quemgn_qempty; 2740 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 2741 break; 2742 case RTW89_DBG_PORT_SEL_PKTINFO: 2743 info = &dbg_port_pktinfo; 2744 seq_puts(m, "Enable pktinfo dump.\n"); 2745 break; 2746 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2747 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2748 B_AX_DBG_SEL0, 0x80); 2749 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2750 B_AX_SEL_0XC0_MASK, 1); 2751 fallthrough; 2752 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2753 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2754 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2755 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2756 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2757 info = &dbg_port_dspt_hdt_tx0_5; 2758 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2759 rtw89_write16_mask(rtwdev, info->sel_addr, 2760 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2761 rtw89_write16_mask(rtwdev, info->sel_addr, 2762 B_AX_DISPATCHER_CH_SEL_MASK, index); 2763 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2764 break; 2765 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2766 info = &dbg_port_dspt_hdt_tx6; 2767 rtw89_write16_mask(rtwdev, info->sel_addr, 2768 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2769 rtw89_write16_mask(rtwdev, info->sel_addr, 2770 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2771 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n"); 2772 break; 2773 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2774 info = &dbg_port_dspt_hdt_tx7; 2775 rtw89_write16_mask(rtwdev, info->sel_addr, 2776 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2777 rtw89_write16_mask(rtwdev, info->sel_addr, 2778 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2779 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n"); 2780 break; 2781 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2782 info = &dbg_port_dspt_hdt_tx8; 2783 rtw89_write16_mask(rtwdev, info->sel_addr, 2784 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2785 rtw89_write16_mask(rtwdev, info->sel_addr, 2786 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2787 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n"); 2788 break; 2789 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2790 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2791 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2792 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2793 info = &dbg_port_dspt_hdt_tx9_C; 2794 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2795 rtw89_write16_mask(rtwdev, info->sel_addr, 2796 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2797 rtw89_write16_mask(rtwdev, info->sel_addr, 2798 B_AX_DISPATCHER_CH_SEL_MASK, index); 2799 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2800 break; 2801 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2802 info = &dbg_port_dspt_hdt_txD; 2803 rtw89_write16_mask(rtwdev, info->sel_addr, 2804 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2805 rtw89_write16_mask(rtwdev, info->sel_addr, 2806 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2807 seq_puts(m, "Enable Dispatcher hdt txD dump.\n"); 2808 break; 2809 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2810 info = &dbg_port_dspt_cdt_tx0; 2811 rtw89_write16_mask(rtwdev, info->sel_addr, 2812 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2813 rtw89_write16_mask(rtwdev, info->sel_addr, 2814 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2815 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n"); 2816 break; 2817 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2818 info = &dbg_port_dspt_cdt_tx1; 2819 rtw89_write16_mask(rtwdev, info->sel_addr, 2820 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2821 rtw89_write16_mask(rtwdev, info->sel_addr, 2822 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2823 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n"); 2824 break; 2825 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2826 info = &dbg_port_dspt_cdt_tx3; 2827 rtw89_write16_mask(rtwdev, info->sel_addr, 2828 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2829 rtw89_write16_mask(rtwdev, info->sel_addr, 2830 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2831 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n"); 2832 break; 2833 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2834 info = &dbg_port_dspt_cdt_tx4; 2835 rtw89_write16_mask(rtwdev, info->sel_addr, 2836 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2837 rtw89_write16_mask(rtwdev, info->sel_addr, 2838 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2839 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n"); 2840 break; 2841 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2842 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2843 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2844 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2845 info = &dbg_port_dspt_cdt_tx5_8; 2846 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2847 rtw89_write16_mask(rtwdev, info->sel_addr, 2848 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2849 rtw89_write16_mask(rtwdev, info->sel_addr, 2850 B_AX_DISPATCHER_CH_SEL_MASK, index); 2851 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2852 break; 2853 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 2854 info = &dbg_port_dspt_cdt_tx9; 2855 rtw89_write16_mask(rtwdev, info->sel_addr, 2856 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2857 rtw89_write16_mask(rtwdev, info->sel_addr, 2858 B_AX_DISPATCHER_CH_SEL_MASK, 9); 2859 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n"); 2860 break; 2861 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 2862 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 2863 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 2864 info = &dbg_port_dspt_cdt_txA_C; 2865 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 2866 rtw89_write16_mask(rtwdev, info->sel_addr, 2867 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2868 rtw89_write16_mask(rtwdev, info->sel_addr, 2869 B_AX_DISPATCHER_CH_SEL_MASK, index); 2870 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2871 break; 2872 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 2873 info = &dbg_port_dspt_hdt_rx0; 2874 rtw89_write16_mask(rtwdev, info->sel_addr, 2875 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2876 rtw89_write16_mask(rtwdev, info->sel_addr, 2877 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2878 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n"); 2879 break; 2880 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 2881 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 2882 info = &dbg_port_dspt_hdt_rx1_2; 2883 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 2884 rtw89_write16_mask(rtwdev, info->sel_addr, 2885 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2886 rtw89_write16_mask(rtwdev, info->sel_addr, 2887 B_AX_DISPATCHER_CH_SEL_MASK, index); 2888 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index); 2889 break; 2890 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 2891 info = &dbg_port_dspt_hdt_rx3; 2892 rtw89_write16_mask(rtwdev, info->sel_addr, 2893 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2894 rtw89_write16_mask(rtwdev, info->sel_addr, 2895 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2896 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n"); 2897 break; 2898 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 2899 info = &dbg_port_dspt_hdt_rx4; 2900 rtw89_write16_mask(rtwdev, info->sel_addr, 2901 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2902 rtw89_write16_mask(rtwdev, info->sel_addr, 2903 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2904 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n"); 2905 break; 2906 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 2907 info = &dbg_port_dspt_hdt_rx5; 2908 rtw89_write16_mask(rtwdev, info->sel_addr, 2909 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2910 rtw89_write16_mask(rtwdev, info->sel_addr, 2911 B_AX_DISPATCHER_CH_SEL_MASK, 5); 2912 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n"); 2913 break; 2914 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 2915 info = &dbg_port_dspt_cdt_rx_p0_0; 2916 rtw89_write16_mask(rtwdev, info->sel_addr, 2917 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2918 rtw89_write16_mask(rtwdev, info->sel_addr, 2919 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2920 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n"); 2921 break; 2922 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 2923 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 2924 info = &dbg_port_dspt_cdt_rx_p0_1; 2925 rtw89_write16_mask(rtwdev, info->sel_addr, 2926 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2927 rtw89_write16_mask(rtwdev, info->sel_addr, 2928 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2929 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n"); 2930 break; 2931 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 2932 info = &dbg_port_dspt_cdt_rx_p0_2; 2933 rtw89_write16_mask(rtwdev, info->sel_addr, 2934 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2935 rtw89_write16_mask(rtwdev, info->sel_addr, 2936 B_AX_DISPATCHER_CH_SEL_MASK, 2); 2937 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n"); 2938 break; 2939 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 2940 info = &dbg_port_dspt_cdt_rx_p1; 2941 rtw89_write8_mask(rtwdev, info->sel_addr, 2942 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2943 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n"); 2944 break; 2945 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 2946 info = &dbg_port_dspt_stf_ctrl; 2947 rtw89_write8_mask(rtwdev, info->sel_addr, 2948 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 2949 seq_puts(m, "Enable Dispatcher stf control dump.\n"); 2950 break; 2951 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 2952 info = &dbg_port_dspt_addr_ctrl; 2953 rtw89_write8_mask(rtwdev, info->sel_addr, 2954 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 2955 seq_puts(m, "Enable Dispatcher addr control dump.\n"); 2956 break; 2957 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 2958 info = &dbg_port_dspt_wde_intf; 2959 rtw89_write8_mask(rtwdev, info->sel_addr, 2960 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 2961 seq_puts(m, "Enable Dispatcher wde interface dump.\n"); 2962 break; 2963 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 2964 info = &dbg_port_dspt_ple_intf; 2965 rtw89_write8_mask(rtwdev, info->sel_addr, 2966 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 2967 seq_puts(m, "Enable Dispatcher ple interface dump.\n"); 2968 break; 2969 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 2970 info = &dbg_port_dspt_flow_ctrl; 2971 rtw89_write8_mask(rtwdev, info->sel_addr, 2972 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 2973 seq_puts(m, "Enable Dispatcher flow control dump.\n"); 2974 break; 2975 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 2976 info = &dbg_port_pcie_txdma; 2977 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2978 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 2979 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 2980 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2981 seq_puts(m, "Enable pcie txdma dump.\n"); 2982 break; 2983 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 2984 info = &dbg_port_pcie_rxdma; 2985 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2986 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 2987 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 2988 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2989 seq_puts(m, "Enable pcie rxdma dump.\n"); 2990 break; 2991 case RTW89_DBG_PORT_SEL_PCIE_CVT: 2992 info = &dbg_port_pcie_cvt; 2993 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2994 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 2995 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 2996 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2997 seq_puts(m, "Enable pcie cvt dump.\n"); 2998 break; 2999 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3000 info = &dbg_port_pcie_cxpl; 3001 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3002 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3003 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3004 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3005 seq_puts(m, "Enable pcie cxpl dump.\n"); 3006 break; 3007 case RTW89_DBG_PORT_SEL_PCIE_IO: 3008 info = &dbg_port_pcie_io; 3009 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3010 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3011 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3012 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3013 seq_puts(m, "Enable pcie io dump.\n"); 3014 break; 3015 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3016 info = &dbg_port_pcie_misc; 3017 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3018 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3019 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3020 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3021 seq_puts(m, "Enable pcie misc dump.\n"); 3022 break; 3023 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3024 info = &dbg_port_pcie_misc2; 3025 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3026 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3027 B_AX_PCIE_DBG_SEL_MASK); 3028 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3029 seq_puts(m, "Enable pcie misc2 dump.\n"); 3030 break; 3031 default: 3032 seq_puts(m, "Dbg port select err\n"); 3033 return NULL; 3034 } 3035 3036 return info; 3037 } 3038 3039 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3040 { 3041 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3042 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3043 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3044 return false; 3045 if (rtw89_is_rtl885xb(rtwdev) && 3046 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3047 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3048 return false; 3049 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3050 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3051 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3052 return false; 3053 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3054 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3055 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3056 return false; 3057 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3058 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3059 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3060 return false; 3061 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3062 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3063 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3064 return false; 3065 3066 return true; 3067 } 3068 3069 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3070 struct seq_file *m, u32 sel) 3071 { 3072 const struct rtw89_mac_dbg_port_info *info; 3073 u8 val8; 3074 u16 val16; 3075 u32 val32; 3076 u32 i; 3077 3078 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 3079 if (!info) { 3080 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3081 return -EINVAL; 3082 } 3083 3084 #define case_DBG_SEL(__sel) \ 3085 case RTW89_DBG_PORT_SEL_##__sel: \ 3086 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 3087 break 3088 3089 switch (sel) { 3090 case_DBG_SEL(PTCL_C0); 3091 case_DBG_SEL(PTCL_C1); 3092 case_DBG_SEL(SCH_C0); 3093 case_DBG_SEL(SCH_C1); 3094 case_DBG_SEL(TMAC_C0); 3095 case_DBG_SEL(TMAC_C1); 3096 case_DBG_SEL(RMAC_C0); 3097 case_DBG_SEL(RMAC_C1); 3098 case_DBG_SEL(RMACST_C0); 3099 case_DBG_SEL(RMACST_C1); 3100 case_DBG_SEL(TRXPTCL_C0); 3101 case_DBG_SEL(TRXPTCL_C1); 3102 case_DBG_SEL(TX_INFOL_C0); 3103 case_DBG_SEL(TX_INFOH_C0); 3104 case_DBG_SEL(TX_INFOL_C1); 3105 case_DBG_SEL(TX_INFOH_C1); 3106 case_DBG_SEL(TXTF_INFOL_C0); 3107 case_DBG_SEL(TXTF_INFOH_C0); 3108 case_DBG_SEL(TXTF_INFOL_C1); 3109 case_DBG_SEL(TXTF_INFOH_C1); 3110 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3111 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3112 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3113 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3114 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3115 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3116 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3117 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3118 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3119 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3120 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3121 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3122 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3123 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3124 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3125 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3126 case_DBG_SEL(PKTINFO); 3127 case_DBG_SEL(DSPT_HDT_TX0); 3128 case_DBG_SEL(DSPT_HDT_TX1); 3129 case_DBG_SEL(DSPT_HDT_TX2); 3130 case_DBG_SEL(DSPT_HDT_TX3); 3131 case_DBG_SEL(DSPT_HDT_TX4); 3132 case_DBG_SEL(DSPT_HDT_TX5); 3133 case_DBG_SEL(DSPT_HDT_TX6); 3134 case_DBG_SEL(DSPT_HDT_TX7); 3135 case_DBG_SEL(DSPT_HDT_TX8); 3136 case_DBG_SEL(DSPT_HDT_TX9); 3137 case_DBG_SEL(DSPT_HDT_TXA); 3138 case_DBG_SEL(DSPT_HDT_TXB); 3139 case_DBG_SEL(DSPT_HDT_TXC); 3140 case_DBG_SEL(DSPT_HDT_TXD); 3141 case_DBG_SEL(DSPT_HDT_TXE); 3142 case_DBG_SEL(DSPT_HDT_TXF); 3143 case_DBG_SEL(DSPT_CDT_TX0); 3144 case_DBG_SEL(DSPT_CDT_TX1); 3145 case_DBG_SEL(DSPT_CDT_TX3); 3146 case_DBG_SEL(DSPT_CDT_TX4); 3147 case_DBG_SEL(DSPT_CDT_TX5); 3148 case_DBG_SEL(DSPT_CDT_TX6); 3149 case_DBG_SEL(DSPT_CDT_TX7); 3150 case_DBG_SEL(DSPT_CDT_TX8); 3151 case_DBG_SEL(DSPT_CDT_TX9); 3152 case_DBG_SEL(DSPT_CDT_TXA); 3153 case_DBG_SEL(DSPT_CDT_TXB); 3154 case_DBG_SEL(DSPT_CDT_TXC); 3155 case_DBG_SEL(DSPT_HDT_RX0); 3156 case_DBG_SEL(DSPT_HDT_RX1); 3157 case_DBG_SEL(DSPT_HDT_RX2); 3158 case_DBG_SEL(DSPT_HDT_RX3); 3159 case_DBG_SEL(DSPT_HDT_RX4); 3160 case_DBG_SEL(DSPT_HDT_RX5); 3161 case_DBG_SEL(DSPT_CDT_RX_P0); 3162 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3163 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3164 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3165 case_DBG_SEL(DSPT_CDT_RX_P1); 3166 case_DBG_SEL(DSPT_STF_CTRL); 3167 case_DBG_SEL(DSPT_ADDR_CTRL); 3168 case_DBG_SEL(DSPT_WDE_INTF); 3169 case_DBG_SEL(DSPT_PLE_INTF); 3170 case_DBG_SEL(DSPT_FLOW_CTRL); 3171 case_DBG_SEL(PCIE_TXDMA); 3172 case_DBG_SEL(PCIE_RXDMA); 3173 case_DBG_SEL(PCIE_CVT); 3174 case_DBG_SEL(PCIE_CXPL); 3175 case_DBG_SEL(PCIE_IO); 3176 case_DBG_SEL(PCIE_MISC); 3177 case_DBG_SEL(PCIE_MISC2); 3178 } 3179 3180 #undef case_DBG_SEL 3181 3182 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 3183 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 3184 3185 for (i = info->srt; i <= info->end; i++) { 3186 switch (info->sel_byte) { 3187 case 1: 3188 default: 3189 rtw89_write8_mask(rtwdev, info->sel_addr, 3190 info->sel_msk, i); 3191 seq_printf(m, "0x%02X: ", i); 3192 break; 3193 case 2: 3194 rtw89_write16_mask(rtwdev, info->sel_addr, 3195 info->sel_msk, i); 3196 seq_printf(m, "0x%04X: ", i); 3197 break; 3198 case 4: 3199 rtw89_write32_mask(rtwdev, info->sel_addr, 3200 info->sel_msk, i); 3201 seq_printf(m, "0x%04X: ", i); 3202 break; 3203 } 3204 3205 udelay(10); 3206 3207 switch (info->rd_byte) { 3208 case 1: 3209 default: 3210 val8 = rtw89_read8_mask(rtwdev, 3211 info->rd_addr, info->rd_msk); 3212 seq_printf(m, "0x%02X\n", val8); 3213 break; 3214 case 2: 3215 val16 = rtw89_read16_mask(rtwdev, 3216 info->rd_addr, info->rd_msk); 3217 seq_printf(m, "0x%04X\n", val16); 3218 break; 3219 case 4: 3220 val32 = rtw89_read32_mask(rtwdev, 3221 info->rd_addr, info->rd_msk); 3222 seq_printf(m, "0x%08X\n", val32); 3223 break; 3224 } 3225 } 3226 3227 return 0; 3228 } 3229 3230 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3231 struct seq_file *m) 3232 { 3233 u32 sel; 3234 int ret = 0; 3235 3236 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3237 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3238 if (!is_dbg_port_valid(rtwdev, sel)) 3239 continue; 3240 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 3241 if (ret) { 3242 rtw89_err(rtwdev, 3243 "failed to dump debug port %d\n", sel); 3244 break; 3245 } 3246 } 3247 3248 return ret; 3249 } 3250 3251 static int 3252 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 3253 { 3254 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3255 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3256 3257 if (debugfs_priv->dbgpkg_en.ss_dbg) 3258 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 3259 if (debugfs_priv->dbgpkg_en.dle_dbg) 3260 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 3261 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3262 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 3263 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3264 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 3265 if (debugfs_priv->dbgpkg_en.dbg_port) 3266 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 3267 3268 return 0; 3269 }; 3270 3271 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 3272 const char __user *user_buf, size_t count) 3273 { 3274 char *buf; 3275 u8 *bin; 3276 int num; 3277 int err = 0; 3278 3279 buf = memdup_user(user_buf, count); 3280 if (IS_ERR(buf)) 3281 return buf; 3282 3283 num = count / 2; 3284 bin = kmalloc(num, GFP_KERNEL); 3285 if (!bin) { 3286 err = -EFAULT; 3287 goto out; 3288 } 3289 3290 if (hex2bin(bin, buf, num)) { 3291 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3292 kfree(bin); 3293 err = -EINVAL; 3294 } 3295 3296 out: 3297 kfree(buf); 3298 3299 return err ? ERR_PTR(err) : bin; 3300 } 3301 3302 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 3303 const char __user *user_buf, 3304 size_t count, loff_t *loff) 3305 { 3306 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3307 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3308 u8 *h2c; 3309 int ret; 3310 u16 h2c_len = count / 2; 3311 3312 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3313 if (IS_ERR(h2c)) 3314 return -EFAULT; 3315 3316 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3317 3318 kfree(h2c); 3319 3320 return ret ? ret : count; 3321 } 3322 3323 static int 3324 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 3325 { 3326 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3327 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3328 struct rtw89_early_h2c *early_h2c; 3329 int seq = 0; 3330 3331 mutex_lock(&rtwdev->mutex); 3332 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3333 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 3334 mutex_unlock(&rtwdev->mutex); 3335 3336 return 0; 3337 } 3338 3339 static ssize_t 3340 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 3341 size_t count, loff_t *loff) 3342 { 3343 struct seq_file *m = (struct seq_file *)filp->private_data; 3344 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3345 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3346 struct rtw89_early_h2c *early_h2c; 3347 u8 *h2c; 3348 u16 h2c_len = count / 2; 3349 3350 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3351 if (IS_ERR(h2c)) 3352 return -EFAULT; 3353 3354 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3355 kfree(h2c); 3356 rtw89_fw_free_all_early_h2c(rtwdev); 3357 goto out; 3358 } 3359 3360 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3361 if (!early_h2c) { 3362 kfree(h2c); 3363 return -EFAULT; 3364 } 3365 3366 early_h2c->h2c = h2c; 3367 early_h2c->h2c_len = h2c_len; 3368 3369 mutex_lock(&rtwdev->mutex); 3370 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3371 mutex_unlock(&rtwdev->mutex); 3372 3373 out: 3374 return count; 3375 } 3376 3377 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3378 { 3379 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3380 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3381 u16 pkt_id; 3382 int ret; 3383 3384 rtw89_leave_ps_mode(rtwdev); 3385 3386 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3387 if (ret) 3388 return ret; 3389 3390 /* intentionally, enqueue two pkt, but has only one pkt id */ 3391 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3392 ctrl_para.start_pktid = pkt_id; 3393 ctrl_para.end_pktid = pkt_id; 3394 ctrl_para.pkt_num = 1; /* start from 0 */ 3395 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3396 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3397 3398 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3399 return -EFAULT; 3400 3401 return 0; 3402 } 3403 3404 static int 3405 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 3406 { 3407 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3408 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3409 3410 seq_printf(m, "%d\n", 3411 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3412 return 0; 3413 } 3414 3415 enum rtw89_dbg_crash_simulation_type { 3416 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3417 RTW89_DBG_SIM_CTRL_ERROR = 2, 3418 }; 3419 3420 static ssize_t 3421 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 3422 size_t count, loff_t *loff) 3423 { 3424 struct seq_file *m = (struct seq_file *)filp->private_data; 3425 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3426 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3427 int (*sim)(struct rtw89_dev *rtwdev); 3428 u8 crash_type; 3429 int ret; 3430 3431 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type); 3432 if (ret) 3433 return -EINVAL; 3434 3435 switch (crash_type) { 3436 case RTW89_DBG_SIM_CPU_EXCEPTION: 3437 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3438 return -EOPNOTSUPP; 3439 sim = rtw89_fw_h2c_trigger_cpu_exception; 3440 break; 3441 case RTW89_DBG_SIM_CTRL_ERROR: 3442 sim = rtw89_dbg_trigger_ctrl_error; 3443 break; 3444 default: 3445 return -EINVAL; 3446 } 3447 3448 mutex_lock(&rtwdev->mutex); 3449 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3450 ret = sim(rtwdev); 3451 mutex_unlock(&rtwdev->mutex); 3452 3453 if (ret) 3454 return ret; 3455 3456 return count; 3457 } 3458 3459 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 3460 { 3461 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3462 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3463 3464 rtw89_btc_dump_info(rtwdev, m); 3465 3466 return 0; 3467 } 3468 3469 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 3470 const char __user *user_buf, 3471 size_t count, loff_t *loff) 3472 { 3473 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3474 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3475 struct rtw89_btc *btc = &rtwdev->btc; 3476 const struct rtw89_btc_ver *ver = btc->ver; 3477 int ret; 3478 3479 ret = kstrtobool_from_user(user_buf, count, &btc->manual_ctrl); 3480 if (ret) 3481 return ret; 3482 3483 if (ver->fcxctrl == 7) 3484 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3485 else 3486 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3487 3488 return count; 3489 } 3490 3491 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct file *filp, 3492 const char __user *user_buf, 3493 size_t count, loff_t *loff) 3494 { 3495 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3496 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3497 struct rtw89_fw_log *log = &rtwdev->fw.log; 3498 bool fw_log_manual; 3499 3500 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 3501 goto out; 3502 3503 mutex_lock(&rtwdev->mutex); 3504 log->enable = fw_log_manual; 3505 if (log->enable) 3506 rtw89_fw_log_prepare(rtwdev); 3507 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3508 mutex_unlock(&rtwdev->mutex); 3509 out: 3510 return count; 3511 } 3512 3513 static void rtw89_sta_link_info_get_iter(struct seq_file *m, 3514 struct rtw89_dev *rtwdev, 3515 struct rtw89_sta_link *rtwsta_link) 3516 { 3517 static const char * const he_gi_str[] = { 3518 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3519 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3520 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3521 }; 3522 static const char * const eht_gi_str[] = { 3523 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3524 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3525 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3526 }; 3527 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3528 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3529 struct rtw89_hal *hal = &rtwdev->hal; 3530 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3531 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3532 struct ieee80211_link_sta *link_sta; 3533 u8 evm_min, evm_max, evm_1ss; 3534 u16 max_rc_amsdu_len; 3535 u8 rssi; 3536 u8 snr; 3537 int i; 3538 3539 rcu_read_lock(); 3540 3541 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3542 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3543 3544 rcu_read_unlock(); 3545 3546 seq_printf(m, "TX rate [%u, %u]: ", rtwsta_link->mac_id, rtwsta_link->link_id); 3547 3548 if (rate->flags & RATE_INFO_FLAGS_MCS) 3549 seq_printf(m, "HT MCS-%d%s", rate->mcs, 3550 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3551 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3552 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 3553 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3554 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3555 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3556 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3557 he_gi_str[rate->he_gi] : "N/A"); 3558 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3559 seq_printf(m, "EHT %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3560 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3561 eht_gi_str[rate->eht_gi] : "N/A"); 3562 else 3563 seq_printf(m, "Legacy %d", rate->legacy); 3564 seq_printf(m, "%s", rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3565 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw)); 3566 seq_printf(m, " (hw_rate=0x%x)", rtwsta_link->ra_report.hw_rate); 3567 seq_printf(m, " ==> agg_wait=%d (%d)\n", rtwsta_link->max_agg_wait, 3568 max_rc_amsdu_len); 3569 3570 seq_printf(m, "RX rate [%u, %u]: ", rtwsta_link->mac_id, rtwsta_link->link_id); 3571 3572 switch (status->encoding) { 3573 case RX_ENC_LEGACY: 3574 seq_printf(m, "Legacy %d", status->rate_idx + 3575 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3576 break; 3577 case RX_ENC_HT: 3578 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 3579 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3580 break; 3581 case RX_ENC_VHT: 3582 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 3583 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3584 break; 3585 case RX_ENC_HE: 3586 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3587 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3588 he_gi_str[status->he_gi] : "N/A"); 3589 break; 3590 case RX_ENC_EHT: 3591 seq_printf(m, "EHT %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3592 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 3593 eht_gi_str[status->eht.gi] : "N/A"); 3594 break; 3595 } 3596 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw)); 3597 seq_printf(m, " (hw_rate=0x%x)\n", rtwsta_link->rx_hw_rate); 3598 3599 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 3600 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [", 3601 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta_link->prev_rssi); 3602 for (i = 0; i < ant_num; i++) { 3603 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 3604 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi), 3605 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3606 i + 1 == ant_num ? "" : ", "); 3607 } 3608 seq_puts(m, "]\n"); 3609 3610 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 3611 seq_printf(m, "EVM: [%2u.%02u, ", evm_1ss >> 2, (evm_1ss & 0x3) * 25); 3612 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3613 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 3614 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 3615 3616 seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ", 3617 evm_min >> 2, (evm_min & 0x3) * 25, 3618 evm_max >> 2, (evm_max & 0x3) * 25); 3619 } 3620 seq_puts(m, "]\t"); 3621 3622 snr = ewma_snr_read(&rtwsta_link->avg_snr); 3623 seq_printf(m, "SNR: %u\n", snr); 3624 } 3625 3626 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3627 { 3628 struct seq_file *m = (struct seq_file *)data; 3629 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3630 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3631 struct rtw89_sta_link *rtwsta_link; 3632 unsigned int link_id; 3633 3634 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3635 rtw89_sta_link_info_get_iter(m, rtwdev, rtwsta_link); 3636 } 3637 3638 static void 3639 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 3640 enum rtw89_hw_rate first_rate, int len) 3641 { 3642 int i; 3643 3644 for (i = 0; i < len; i++) 3645 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 3646 pkt_stat->rx_rate_cnt[first_rate + i]); 3647 } 3648 3649 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 3650 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 3651 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 3652 3653 static const struct rtw89_rx_rate_cnt_info { 3654 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 3655 int len; 3656 int ext; 3657 const char *rate_mode; 3658 } rtw89_rx_rate_cnt_infos[] = { 3659 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 3660 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 3661 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 3662 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 3663 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 3664 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 3665 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 3666 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 3667 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 3668 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 3669 }; 3670 3671 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 3672 { 3673 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3674 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3675 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3676 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3677 const struct rtw89_chip_info *chip = rtwdev->chip; 3678 const struct rtw89_rx_rate_cnt_info *info; 3679 struct rtw89_hal *hal = &rtwdev->hal; 3680 enum rtw89_hw_rate first_rate; 3681 u8 rssi; 3682 int i; 3683 3684 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3685 3686 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d", 3687 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv); 3688 if (hal->thermal_prot_lv) 3689 seq_printf(m, ", duty: %d%%", 3690 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 3691 seq_printf(m, "), RX: %u [%u] Mbps (lv: %d)\n", 3692 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 3693 seq_printf(m, "Beacon: %u (%d dBm), TF: %u\n", pkt_stat->beacon_nr, 3694 RTW89_RSSI_RAW_TO_DBM(rssi), stats->rx_tf_periodic); 3695 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 3696 stats->rx_avg_len); 3697 3698 seq_puts(m, "RX count:\n"); 3699 3700 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3701 info = &rtw89_rx_rate_cnt_infos[i]; 3702 first_rate = info->first_rate[chip->chip_gen]; 3703 if (first_rate >= RTW89_HW_RATE_NR) 3704 continue; 3705 3706 seq_printf(m, "%10s [", info->rate_mode); 3707 rtw89_debug_append_rx_rate(m, pkt_stat, 3708 first_rate, info->len); 3709 if (info->ext) { 3710 seq_puts(m, "]["); 3711 rtw89_debug_append_rx_rate(m, pkt_stat, 3712 first_rate + info->len, info->ext); 3713 } 3714 seq_puts(m, "]\n"); 3715 } 3716 3717 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 3718 3719 return 0; 3720 } 3721 3722 static void rtw89_dump_addr_cam(struct seq_file *m, 3723 struct rtw89_dev *rtwdev, 3724 struct rtw89_addr_cam_entry *addr_cam) 3725 { 3726 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3727 const struct rtw89_sec_cam_entry *sec_entry; 3728 u8 sec_cam_idx; 3729 int i; 3730 3731 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 3732 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 3733 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 3734 addr_cam->sec_cam_map); 3735 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 3736 sec_cam_idx = addr_cam->sec_ent[i]; 3737 sec_entry = cam_info->sec_entries[sec_cam_idx]; 3738 if (!sec_entry) 3739 continue; 3740 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 3741 if (sec_entry->ext_key) 3742 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 3743 seq_puts(m, "\n"); 3744 } 3745 } 3746 3747 __printf(3, 4) 3748 static void rtw89_dump_pkt_offload(struct seq_file *m, struct list_head *pkt_list, 3749 const char *fmt, ...) 3750 { 3751 struct rtw89_pktofld_info *info; 3752 struct va_format vaf; 3753 va_list args; 3754 3755 if (list_empty(pkt_list)) 3756 return; 3757 3758 va_start(args, fmt); 3759 vaf.va = &args; 3760 vaf.fmt = fmt; 3761 3762 seq_printf(m, "%pV", &vaf); 3763 3764 va_end(args); 3765 3766 list_for_each_entry(info, pkt_list, list) 3767 seq_printf(m, "%d ", info->id); 3768 3769 seq_puts(m, "\n"); 3770 } 3771 3772 static void rtw89_vif_link_ids_get(struct seq_file *m, u8 *mac, 3773 struct rtw89_dev *rtwdev, 3774 struct rtw89_vif_link *rtwvif_link) 3775 { 3776 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 3777 3778 seq_printf(m, " [%u] %pM\n", rtwvif_link->mac_id, rtwvif_link->mac_addr); 3779 seq_printf(m, "\tlink_id=%u\n", rtwvif_link->link_id); 3780 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 3781 rtw89_dump_addr_cam(m, rtwdev, &rtwvif_link->addr_cam); 3782 rtw89_dump_pkt_offload(m, &rtwvif_link->general_pkt_list, 3783 "\tpkt_ofld[GENERAL]: "); 3784 } 3785 3786 static 3787 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3788 { 3789 struct seq_file *m = (struct seq_file *)data; 3790 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 3791 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3792 struct rtw89_vif_link *rtwvif_link; 3793 unsigned int link_id; 3794 3795 seq_printf(m, "VIF %pM\n", rtwvif->mac_addr); 3796 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3797 rtw89_vif_link_ids_get(m, mac, rtwdev, rtwvif_link); 3798 } 3799 3800 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_dev *rtwdev, 3801 struct rtw89_sta_link *rtwsta_link) 3802 { 3803 struct rtw89_ba_cam_entry *entry; 3804 bool first = true; 3805 3806 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 3807 if (first) { 3808 seq_puts(m, "\tba_cam "); 3809 first = false; 3810 } else { 3811 seq_puts(m, ", "); 3812 } 3813 seq_printf(m, "tid[%u]=%d", entry->tid, 3814 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 3815 } 3816 seq_puts(m, "\n"); 3817 } 3818 3819 static void rtw89_sta_link_ids_get(struct seq_file *m, 3820 struct rtw89_dev *rtwdev, 3821 struct rtw89_sta_link *rtwsta_link) 3822 { 3823 struct ieee80211_link_sta *link_sta; 3824 3825 rcu_read_lock(); 3826 3827 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3828 3829 seq_printf(m, " [%u] %pM\n", rtwsta_link->mac_id, link_sta->addr); 3830 3831 rcu_read_unlock(); 3832 3833 seq_printf(m, "\tlink_id=%u\n", rtwsta_link->link_id); 3834 rtw89_dump_addr_cam(m, rtwdev, &rtwsta_link->addr_cam); 3835 rtw89_dump_ba_cam(m, rtwdev, rtwsta_link); 3836 } 3837 3838 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 3839 { 3840 struct seq_file *m = (struct seq_file *)data; 3841 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3842 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3843 struct rtw89_sta_link *rtwsta_link; 3844 unsigned int link_id; 3845 3846 seq_printf(m, "STA %pM %s\n", sta->addr, sta->tdls ? "(TDLS)" : ""); 3847 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3848 rtw89_sta_link_ids_get(m, rtwdev, rtwsta_link); 3849 } 3850 3851 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 3852 { 3853 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3854 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3855 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3856 u8 idx; 3857 3858 mutex_lock(&rtwdev->mutex); 3859 3860 seq_puts(m, "map:\n"); 3861 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 3862 rtwdev->mac_id_map); 3863 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 3864 cam_info->addr_cam_map); 3865 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 3866 cam_info->bssid_cam_map); 3867 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 3868 cam_info->sec_cam_map); 3869 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 3870 cam_info->ba_cam_map); 3871 seq_printf(m, "\tpkt_ofld: %*ph\n", (int)sizeof(rtwdev->pkt_offload), 3872 rtwdev->pkt_offload); 3873 3874 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 3875 if (!(rtwdev->chip->support_bands & BIT(idx))) 3876 continue; 3877 rtw89_dump_pkt_offload(m, &rtwdev->scan_info.pkt_list[idx], 3878 "\t\t[SCAN %u]: ", idx); 3879 } 3880 3881 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 3882 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 3883 3884 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 3885 3886 mutex_unlock(&rtwdev->mutex); 3887 3888 return 0; 3889 } 3890 3891 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 3892 3893 static const struct rtw89_disabled_dm_info { 3894 enum rtw89_dm_type type; 3895 const char *name; 3896 } rtw89_disabled_dm_infos[] = { 3897 DM_INFO(DYNAMIC_EDCCA), 3898 DM_INFO(THERMAL_PROTECT), 3899 }; 3900 3901 static int 3902 rtw89_debug_priv_disable_dm_get(struct seq_file *m, void *v) 3903 { 3904 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3905 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3906 const struct rtw89_disabled_dm_info *info; 3907 struct rtw89_hal *hal = &rtwdev->hal; 3908 u32 disabled; 3909 int i; 3910 3911 seq_printf(m, "Disabled DM: 0x%x\n", hal->disabled_dm_bitmap); 3912 3913 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 3914 info = &rtw89_disabled_dm_infos[i]; 3915 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 3916 3917 seq_printf(m, "[%d] %s: %c\n", info->type, info->name, 3918 disabled ? 'X' : 'O'); 3919 } 3920 3921 return 0; 3922 } 3923 3924 static ssize_t 3925 rtw89_debug_priv_disable_dm_set(struct file *filp, const char __user *user_buf, 3926 size_t count, loff_t *loff) 3927 { 3928 struct seq_file *m = (struct seq_file *)filp->private_data; 3929 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3930 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3931 struct rtw89_hal *hal = &rtwdev->hal; 3932 u32 conf; 3933 int ret; 3934 3935 ret = kstrtou32_from_user(user_buf, count, 0, &conf); 3936 if (ret) 3937 return -EINVAL; 3938 3939 hal->disabled_dm_bitmap = conf; 3940 3941 return count; 3942 } 3943 3944 #define rtw89_debug_priv_get(name) \ 3945 { \ 3946 .cb_read = rtw89_debug_priv_ ##name## _get, \ 3947 } 3948 3949 #define rtw89_debug_priv_set(name) \ 3950 { \ 3951 .cb_write = rtw89_debug_priv_ ##name## _set, \ 3952 } 3953 3954 #define rtw89_debug_priv_select_and_get(name) \ 3955 { \ 3956 .cb_write = rtw89_debug_priv_ ##name## _select, \ 3957 .cb_read = rtw89_debug_priv_ ##name## _get, \ 3958 } 3959 3960 #define rtw89_debug_priv_set_and_get(name) \ 3961 { \ 3962 .cb_write = rtw89_debug_priv_ ##name## _set, \ 3963 .cb_read = rtw89_debug_priv_ ##name## _get, \ 3964 } 3965 3966 static const struct rtw89_debugfs rtw89_debugfs_templ = { 3967 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 3968 .write_reg = rtw89_debug_priv_set(write_reg), 3969 .read_rf = rtw89_debug_priv_select_and_get(read_rf), 3970 .write_rf = rtw89_debug_priv_set(write_rf), 3971 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump), 3972 .txpwr_table = rtw89_debug_priv_get(txpwr_table), 3973 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump), 3974 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump), 3975 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump), 3976 .send_h2c = rtw89_debug_priv_set(send_h2c), 3977 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c), 3978 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash), 3979 .btc_info = rtw89_debug_priv_get(btc_info), 3980 .btc_manual = rtw89_debug_priv_set(btc_manual), 3981 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual), 3982 .phy_info = rtw89_debug_priv_get(phy_info), 3983 .stations = rtw89_debug_priv_get(stations), 3984 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm), 3985 }; 3986 3987 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 3988 do { \ 3989 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 3990 priv->rtwdev = rtwdev; \ 3991 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 3992 &file_ops_ ##fopname))) \ 3993 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 3994 } while (0) 3995 3996 #define rtw89_debugfs_add_w(name) \ 3997 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 3998 #define rtw89_debugfs_add_rw(name) \ 3999 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 4000 #define rtw89_debugfs_add_r(name) \ 4001 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 4002 4003 static 4004 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4005 { 4006 rtw89_debugfs_add_rw(read_reg); 4007 rtw89_debugfs_add_w(write_reg); 4008 rtw89_debugfs_add_rw(read_rf); 4009 rtw89_debugfs_add_w(write_rf); 4010 rtw89_debugfs_add_r(rf_reg_dump); 4011 rtw89_debugfs_add_r(txpwr_table); 4012 rtw89_debugfs_add_rw(mac_reg_dump); 4013 rtw89_debugfs_add_rw(mac_mem_dump); 4014 rtw89_debugfs_add_rw(mac_dbg_port_dump); 4015 } 4016 4017 static 4018 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4019 { 4020 rtw89_debugfs_add_w(send_h2c); 4021 rtw89_debugfs_add_rw(early_h2c); 4022 rtw89_debugfs_add_rw(fw_crash); 4023 rtw89_debugfs_add_r(btc_info); 4024 rtw89_debugfs_add_w(btc_manual); 4025 rtw89_debugfs_add_w(fw_log_manual); 4026 rtw89_debugfs_add_r(phy_info); 4027 rtw89_debugfs_add_r(stations); 4028 rtw89_debugfs_add_rw(disable_dm); 4029 } 4030 4031 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 4032 { 4033 struct dentry *debugfs_topdir; 4034 4035 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 4036 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 4037 if (!rtwdev->debugfs) 4038 return; 4039 4040 debugfs_topdir = debugfs_create_dir("rtw89", 4041 rtwdev->hw->wiphy->debugfsdir); 4042 4043 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 4044 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 4045 } 4046 4047 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 4048 { 4049 kfree(rtwdev->debugfs); 4050 } 4051 #endif 4052 4053 #ifdef CONFIG_RTW89_DEBUGMSG 4054 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 4055 const char *fmt, ...) 4056 { 4057 struct va_format vaf = { 4058 .fmt = fmt, 4059 }; 4060 4061 va_list args; 4062 4063 va_start(args, fmt); 4064 vaf.va = &args; 4065 4066 if (rtw89_debug_mask & mask) 4067 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 4068 4069 va_end(args); 4070 } 4071 EXPORT_SYMBOL(rtw89_debug); 4072 #endif 4073