1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "sar.h" 16 17 #ifdef CONFIG_RTW89_DEBUGMSG 18 unsigned int rtw89_debug_mask; 19 EXPORT_SYMBOL(rtw89_debug_mask); 20 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 21 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 22 #endif 23 24 #ifdef CONFIG_RTW89_DEBUGFS 25 struct rtw89_debugfs_priv { 26 struct rtw89_dev *rtwdev; 27 int (*cb_read)(struct seq_file *m, void *v); 28 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 29 size_t count, loff_t *loff); 30 union { 31 u32 cb_data; 32 struct { 33 u32 addr; 34 u32 len; 35 } read_reg; 36 struct { 37 u32 addr; 38 u32 mask; 39 u8 path; 40 } read_rf; 41 struct { 42 u8 ss_dbg:1; 43 u8 dle_dbg:1; 44 u8 dmac_dbg:1; 45 u8 cmac_dbg:1; 46 u8 dbg_port:1; 47 } dbgpkg_en; 48 struct { 49 u32 start; 50 u32 len; 51 u8 sel; 52 } mac_mem; 53 }; 54 }; 55 56 struct rtw89_debugfs { 57 struct rtw89_debugfs_priv read_reg; 58 struct rtw89_debugfs_priv write_reg; 59 struct rtw89_debugfs_priv read_rf; 60 struct rtw89_debugfs_priv write_rf; 61 struct rtw89_debugfs_priv rf_reg_dump; 62 struct rtw89_debugfs_priv txpwr_table; 63 struct rtw89_debugfs_priv mac_reg_dump; 64 struct rtw89_debugfs_priv mac_mem_dump; 65 struct rtw89_debugfs_priv mac_dbg_port_dump; 66 struct rtw89_debugfs_priv send_h2c; 67 struct rtw89_debugfs_priv early_h2c; 68 struct rtw89_debugfs_priv fw_crash; 69 struct rtw89_debugfs_priv btc_info; 70 struct rtw89_debugfs_priv btc_manual; 71 struct rtw89_debugfs_priv fw_log_manual; 72 struct rtw89_debugfs_priv phy_info; 73 struct rtw89_debugfs_priv stations; 74 struct rtw89_debugfs_priv disable_dm; 75 }; 76 77 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 78 [RATE_INFO_BW_20] = 20, 79 [RATE_INFO_BW_40] = 40, 80 [RATE_INFO_BW_80] = 80, 81 [RATE_INFO_BW_160] = 160, 82 [RATE_INFO_BW_320] = 320, 83 }; 84 85 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 86 { 87 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 88 return rtw89_rate_info_bw_to_mhz_map[bw]; 89 90 return 0; 91 } 92 93 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 94 { 95 struct rtw89_debugfs_priv *debugfs_priv = m->private; 96 97 return debugfs_priv->cb_read(m, v); 98 } 99 100 static ssize_t rtw89_debugfs_single_write(struct file *filp, 101 const char __user *buffer, 102 size_t count, loff_t *loff) 103 { 104 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 105 106 return debugfs_priv->cb_write(filp, buffer, count, loff); 107 } 108 109 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 110 const char __user *buffer, 111 size_t count, loff_t *loff) 112 { 113 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 114 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 115 116 return debugfs_priv->cb_write(filp, buffer, count, loff); 117 } 118 119 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 120 { 121 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 122 } 123 124 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 125 { 126 return 0; 127 } 128 129 static const struct file_operations file_ops_single_r = { 130 .owner = THIS_MODULE, 131 .open = rtw89_debugfs_single_open, 132 .read = seq_read, 133 .llseek = seq_lseek, 134 .release = single_release, 135 }; 136 137 static const struct file_operations file_ops_common_rw = { 138 .owner = THIS_MODULE, 139 .open = rtw89_debugfs_single_open, 140 .release = single_release, 141 .read = seq_read, 142 .llseek = seq_lseek, 143 .write = rtw89_debugfs_seq_file_write, 144 }; 145 146 static const struct file_operations file_ops_single_w = { 147 .owner = THIS_MODULE, 148 .write = rtw89_debugfs_single_write, 149 .open = simple_open, 150 .release = rtw89_debugfs_close, 151 }; 152 153 static ssize_t 154 rtw89_debug_priv_read_reg_select(struct file *filp, 155 const char __user *user_buf, 156 size_t count, loff_t *loff) 157 { 158 struct seq_file *m = (struct seq_file *)filp->private_data; 159 struct rtw89_debugfs_priv *debugfs_priv = m->private; 160 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 161 char buf[32]; 162 size_t buf_size; 163 u32 addr, len; 164 int num; 165 166 buf_size = min(count, sizeof(buf) - 1); 167 if (copy_from_user(buf, user_buf, buf_size)) 168 return -EFAULT; 169 170 buf[buf_size] = '\0'; 171 num = sscanf(buf, "%x %x", &addr, &len); 172 if (num != 2) { 173 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 174 return -EINVAL; 175 } 176 177 debugfs_priv->read_reg.addr = addr; 178 debugfs_priv->read_reg.len = len; 179 180 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 181 182 return count; 183 } 184 185 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 186 { 187 struct rtw89_debugfs_priv *debugfs_priv = m->private; 188 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 189 u32 addr, end, data, k; 190 u32 len; 191 192 len = debugfs_priv->read_reg.len; 193 addr = debugfs_priv->read_reg.addr; 194 195 if (len > 4) 196 goto ndata; 197 198 switch (len) { 199 case 1: 200 data = rtw89_read8(rtwdev, addr); 201 break; 202 case 2: 203 data = rtw89_read16(rtwdev, addr); 204 break; 205 case 4: 206 data = rtw89_read32(rtwdev, addr); 207 break; 208 default: 209 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 210 return -EINVAL; 211 } 212 213 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 214 215 return 0; 216 217 ndata: 218 end = addr + len; 219 220 for (; addr < end; addr += 16) { 221 seq_printf(m, "%08xh : ", 0x18600000 + addr); 222 for (k = 0; k < 16; k += 4) { 223 data = rtw89_read32(rtwdev, addr + k); 224 seq_printf(m, "%08x ", data); 225 } 226 seq_puts(m, "\n"); 227 } 228 229 return 0; 230 } 231 232 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 233 const char __user *user_buf, 234 size_t count, loff_t *loff) 235 { 236 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 237 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 238 char buf[32]; 239 size_t buf_size; 240 u32 addr, val, len; 241 int num; 242 243 buf_size = min(count, sizeof(buf) - 1); 244 if (copy_from_user(buf, user_buf, buf_size)) 245 return -EFAULT; 246 247 buf[buf_size] = '\0'; 248 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 249 if (num != 3) { 250 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 251 return -EINVAL; 252 } 253 254 switch (len) { 255 case 1: 256 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 257 rtw89_write8(rtwdev, addr, (u8)val); 258 break; 259 case 2: 260 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 261 rtw89_write16(rtwdev, addr, (u16)val); 262 break; 263 case 4: 264 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 265 rtw89_write32(rtwdev, addr, (u32)val); 266 break; 267 default: 268 rtw89_info(rtwdev, "invalid read write len %d\n", len); 269 break; 270 } 271 272 return count; 273 } 274 275 static ssize_t 276 rtw89_debug_priv_read_rf_select(struct file *filp, 277 const char __user *user_buf, 278 size_t count, loff_t *loff) 279 { 280 struct seq_file *m = (struct seq_file *)filp->private_data; 281 struct rtw89_debugfs_priv *debugfs_priv = m->private; 282 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 283 char buf[32]; 284 size_t buf_size; 285 u32 addr, mask; 286 u8 path; 287 int num; 288 289 buf_size = min(count, sizeof(buf) - 1); 290 if (copy_from_user(buf, user_buf, buf_size)) 291 return -EFAULT; 292 293 buf[buf_size] = '\0'; 294 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 295 if (num != 3) { 296 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 297 return -EINVAL; 298 } 299 300 if (path >= rtwdev->chip->rf_path_num) { 301 rtw89_info(rtwdev, "wrong rf path\n"); 302 return -EINVAL; 303 } 304 debugfs_priv->read_rf.addr = addr; 305 debugfs_priv->read_rf.mask = mask; 306 debugfs_priv->read_rf.path = path; 307 308 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 309 310 return count; 311 } 312 313 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 314 { 315 struct rtw89_debugfs_priv *debugfs_priv = m->private; 316 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 317 u32 addr, data, mask; 318 u8 path; 319 320 addr = debugfs_priv->read_rf.addr; 321 mask = debugfs_priv->read_rf.mask; 322 path = debugfs_priv->read_rf.path; 323 324 data = rtw89_read_rf(rtwdev, path, addr, mask); 325 326 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 327 328 return 0; 329 } 330 331 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 332 const char __user *user_buf, 333 size_t count, loff_t *loff) 334 { 335 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 336 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 337 char buf[32]; 338 size_t buf_size; 339 u32 addr, val, mask; 340 u8 path; 341 int num; 342 343 buf_size = min(count, sizeof(buf) - 1); 344 if (copy_from_user(buf, user_buf, buf_size)) 345 return -EFAULT; 346 347 buf[buf_size] = '\0'; 348 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 349 if (num != 4) { 350 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 351 return -EINVAL; 352 } 353 354 if (path >= rtwdev->chip->rf_path_num) { 355 rtw89_info(rtwdev, "wrong rf path\n"); 356 return -EINVAL; 357 } 358 359 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 360 path, addr, val, mask); 361 rtw89_write_rf(rtwdev, path, addr, mask, val); 362 363 return count; 364 } 365 366 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 367 { 368 struct rtw89_debugfs_priv *debugfs_priv = m->private; 369 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 370 const struct rtw89_chip_info *chip = rtwdev->chip; 371 u32 addr, offset, data; 372 u8 path; 373 374 for (path = 0; path < chip->rf_path_num; path++) { 375 seq_printf(m, "RF path %d:\n\n", path); 376 for (addr = 0; addr < 0x100; addr += 4) { 377 seq_printf(m, "0x%08x: ", addr); 378 for (offset = 0; offset < 4; offset++) { 379 data = rtw89_read_rf(rtwdev, path, 380 addr + offset, RFREG_MASK); 381 seq_printf(m, "0x%05x ", data); 382 } 383 seq_puts(m, "\n"); 384 } 385 seq_puts(m, "\n"); 386 } 387 388 return 0; 389 } 390 391 struct txpwr_ent { 392 bool nested; 393 union { 394 const char *txt; 395 const struct txpwr_ent *ptr; 396 }; 397 u8 len; 398 }; 399 400 struct txpwr_map { 401 const struct txpwr_ent *ent; 402 u8 size; 403 u32 addr_from; 404 u32 addr_to; 405 u32 addr_to_1ss; 406 }; 407 408 #define __GEN_TXPWR_ENT_NESTED(_e) \ 409 { .nested = true, .ptr = __txpwr_ent_##_e, \ 410 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 411 412 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 413 414 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 415 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 416 417 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 418 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 419 420 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 421 { .len = 8, .txt = _t "\t- " \ 422 _e0 " " _e1 " " _e2 " " _e3 " " \ 423 _e4 " " _e5 " " _e6 " " _e7 } 424 425 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 426 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 427 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 428 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 429 /* 1NSS */ 430 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 431 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 432 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 433 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 434 /* 2NSS */ 435 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 436 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 437 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 438 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 439 }; 440 441 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 442 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 443 444 static const struct txpwr_map __txpwr_map_byr_ax = { 445 .ent = __txpwr_ent_byr_ax, 446 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 447 .addr_from = R_AX_PWR_BY_RATE, 448 .addr_to = R_AX_PWR_BY_RATE_MAX, 449 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 450 }; 451 452 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 453 /* 1TX */ 454 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 455 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 456 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 457 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 458 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 459 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 460 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 461 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 462 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 463 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 464 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 465 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 466 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 467 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 468 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 469 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 470 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 471 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 472 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 473 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 474 /* 2TX */ 475 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 476 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 477 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 478 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 479 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 480 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 481 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 482 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 483 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 484 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 485 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 486 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 487 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 488 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 489 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 490 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 491 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 492 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 493 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 494 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 495 }; 496 497 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 498 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 499 500 static const struct txpwr_map __txpwr_map_lmt_ax = { 501 .ent = __txpwr_ent_lmt_ax, 502 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 503 .addr_from = R_AX_PWR_LMT, 504 .addr_to = R_AX_PWR_LMT_MAX, 505 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 506 }; 507 508 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 509 /* 1TX */ 510 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 511 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 512 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 513 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 514 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 515 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 516 /* 2TX */ 517 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 518 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 519 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 520 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 521 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 522 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 523 }; 524 525 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 526 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 527 528 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 529 .ent = __txpwr_ent_lmt_ru_ax, 530 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 531 .addr_from = R_AX_PWR_RU_LMT, 532 .addr_to = R_AX_PWR_RU_LMT_MAX, 533 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 534 }; 535 536 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 537 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 538 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 539 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 540 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 541 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 542 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 543 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 544 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 545 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 546 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 547 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 548 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 549 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 550 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 551 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 552 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 553 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 554 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 555 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 556 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 557 }; 558 559 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 560 __GEN_TXPWR_ENT0("BW20"), 561 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 562 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 563 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 564 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 565 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 566 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 567 568 __GEN_TXPWR_ENT0("BW40"), 569 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 570 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 571 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 572 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 573 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 574 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 575 576 /* there is no CCK section after BW80 */ 577 __GEN_TXPWR_ENT0("BW80"), 578 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 579 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 580 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 581 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 582 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 583 584 __GEN_TXPWR_ENT0("BW160"), 585 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 586 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 587 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 588 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 589 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 590 591 __GEN_TXPWR_ENT0("BW320"), 592 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 593 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 594 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 595 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 596 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 597 }; 598 599 static const struct txpwr_map __txpwr_map_byr_be = { 600 .ent = __txpwr_ent_byr_be, 601 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 602 .addr_from = R_BE_PWR_BY_RATE, 603 .addr_to = R_BE_PWR_BY_RATE_MAX, 604 .addr_to_1ss = 0, /* not support */ 605 }; 606 607 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 608 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 609 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 610 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 611 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 612 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 613 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 614 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 615 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 616 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 617 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 618 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 619 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 620 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 621 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 622 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 623 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 624 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 625 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 626 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 627 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 628 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 629 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 630 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 631 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 632 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 633 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 634 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 635 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 636 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 637 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 638 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 639 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 640 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 641 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 642 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 643 }; 644 645 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 646 __GEN_TXPWR_ENT0("1TX"), 647 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 648 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 649 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 650 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 651 652 __GEN_TXPWR_ENT0("2TX"), 653 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 654 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 655 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 656 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 657 }; 658 659 static const struct txpwr_map __txpwr_map_lmt_be = { 660 .ent = __txpwr_ent_lmt_be, 661 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 662 .addr_from = R_BE_PWR_LMT, 663 .addr_to = R_BE_PWR_LMT_MAX, 664 .addr_to_1ss = 0, /* not support */ 665 }; 666 667 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 668 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 669 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 670 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 671 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 672 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 673 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 674 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 675 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 676 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 677 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 678 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 679 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 680 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 681 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 682 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 683 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 684 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 685 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 686 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 687 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 688 }; 689 690 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 691 __GEN_TXPWR_ENT0("1TX"), 692 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 693 694 __GEN_TXPWR_ENT0("2TX"), 695 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 696 }; 697 698 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 699 .ent = __txpwr_ent_lmt_ru_be, 700 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 701 .addr_from = R_BE_PWR_RU_LMT, 702 .addr_to = R_BE_PWR_RU_LMT_MAX, 703 .addr_to_1ss = 0, /* not support */ 704 }; 705 706 static unsigned int 707 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 708 const s8 *buf, const unsigned int cur) 709 { 710 unsigned int cnt, i; 711 char *fmt; 712 713 if (ent->nested) { 714 for (cnt = 0, i = 0; i < ent->len; i++) 715 cnt += __print_txpwr_ent(m, ent->ptr + i, buf, 716 cur + cnt); 717 return cnt; 718 } 719 720 switch (ent->len) { 721 case 0: 722 seq_printf(m, "\t<< %s >>\n", ent->txt); 723 return 0; 724 case 2: 725 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 726 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 727 return 2; 728 case 4: 729 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 730 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 731 buf[cur + 2], buf[cur + 3]); 732 return 4; 733 case 8: 734 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 735 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 736 buf[cur + 2], buf[cur + 3], buf[cur + 4], 737 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 738 return 8; 739 default: 740 return 0; 741 } 742 } 743 744 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 745 const struct txpwr_map *map) 746 { 747 u8 fct = rtwdev->chip->txpwr_factor_mac; 748 u8 path_num = rtwdev->chip->rf_path_num; 749 unsigned int cur, i; 750 u32 max_valid_addr; 751 u32 val, addr; 752 s8 *buf, tmp; 753 int ret; 754 755 buf = vzalloc(map->addr_to - map->addr_from + 4); 756 if (!buf) 757 return -ENOMEM; 758 759 if (path_num == 1) 760 max_valid_addr = map->addr_to_1ss; 761 else 762 max_valid_addr = map->addr_to; 763 764 if (max_valid_addr == 0) 765 return -EOPNOTSUPP; 766 767 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 768 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 769 if (ret) 770 val = MASKDWORD; 771 772 cur = addr - map->addr_from; 773 for (i = 0; i < 4; i++, val >>= 8) { 774 /* signed 7 bits, and reserved BIT(7) */ 775 tmp = sign_extend32(val, 6); 776 buf[cur + i] = tmp >> fct; 777 } 778 } 779 780 for (cur = 0, i = 0; i < map->size; i++) 781 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 782 783 vfree(buf); 784 return 0; 785 } 786 787 #define case_REGD(_regd) \ 788 case RTW89_ ## _regd: \ 789 seq_puts(m, #_regd "\n"); \ 790 break 791 792 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev, 793 const struct rtw89_chan *chan) 794 { 795 u8 band = chan->band_type; 796 u8 regd = rtw89_regd_get(rtwdev, band); 797 798 switch (regd) { 799 default: 800 seq_printf(m, "UNKNOWN: %d\n", regd); 801 break; 802 case_REGD(WW); 803 case_REGD(ETSI); 804 case_REGD(FCC); 805 case_REGD(MKK); 806 case_REGD(NA); 807 case_REGD(IC); 808 case_REGD(KCC); 809 case_REGD(NCC); 810 case_REGD(CHILE); 811 case_REGD(ACMA); 812 case_REGD(MEXICO); 813 case_REGD(UKRAINE); 814 case_REGD(CN); 815 case_REGD(QATAR); 816 case_REGD(UK); 817 case_REGD(THAILAND); 818 } 819 } 820 821 #undef case_REGD 822 823 struct dbgfs_txpwr_table { 824 const struct txpwr_map *byr; 825 const struct txpwr_map *lmt; 826 const struct txpwr_map *lmt_ru; 827 }; 828 829 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 830 .byr = &__txpwr_map_byr_ax, 831 .lmt = &__txpwr_map_lmt_ax, 832 .lmt_ru = &__txpwr_map_lmt_ru_ax, 833 }; 834 835 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 836 .byr = &__txpwr_map_byr_be, 837 .lmt = &__txpwr_map_lmt_be, 838 .lmt_ru = &__txpwr_map_lmt_ru_be, 839 }; 840 841 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 842 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 843 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 844 }; 845 846 static 847 void rtw89_debug_priv_txpwr_table_get_regd(struct seq_file *m, 848 struct rtw89_dev *rtwdev, 849 const struct rtw89_chan *chan) 850 { 851 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 852 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 853 854 seq_printf(m, "[Chanctx] band %u, ch %u, bw %u\n", 855 chan->band_type, chan->channel, chan->band_width); 856 857 seq_puts(m, "[Regulatory] "); 858 __print_regd(m, rtwdev, chan); 859 860 if (chan->band_type == RTW89_BAND_6G) { 861 seq_printf(m, "[reg6_pwr_type] %u\n", regulatory->reg_6ghz_power); 862 863 if (tpe6->valid) 864 seq_printf(m, "[TPE] %d dBm\n", tpe6->constraint); 865 } 866 } 867 868 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 869 { 870 struct rtw89_debugfs_priv *debugfs_priv = m->private; 871 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 872 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 873 const struct dbgfs_txpwr_table *tbl; 874 const struct rtw89_chan *chan; 875 int ret = 0; 876 877 mutex_lock(&rtwdev->mutex); 878 rtw89_leave_ps_mode(rtwdev); 879 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 880 881 rtw89_debug_priv_txpwr_table_get_regd(m, rtwdev, chan); 882 883 seq_puts(m, "[SAR]\n"); 884 rtw89_print_sar(m, rtwdev, chan->freq); 885 886 seq_puts(m, "[TAS]\n"); 887 rtw89_print_tas(m, rtwdev); 888 889 seq_puts(m, "[DAG]\n"); 890 rtw89_print_ant_gain(m, rtwdev, chan); 891 892 tbl = dbgfs_txpwr_tables[chip_gen]; 893 if (!tbl) { 894 ret = -EOPNOTSUPP; 895 goto err; 896 } 897 898 seq_puts(m, "\n[TX power byrate]\n"); 899 ret = __print_txpwr_map(m, rtwdev, tbl->byr); 900 if (ret) 901 goto err; 902 903 seq_puts(m, "\n[TX power limit]\n"); 904 ret = __print_txpwr_map(m, rtwdev, tbl->lmt); 905 if (ret) 906 goto err; 907 908 seq_puts(m, "\n[TX power limit_ru]\n"); 909 ret = __print_txpwr_map(m, rtwdev, tbl->lmt_ru); 910 if (ret) 911 goto err; 912 913 err: 914 mutex_unlock(&rtwdev->mutex); 915 return ret; 916 } 917 918 static ssize_t 919 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 920 const char __user *user_buf, 921 size_t count, loff_t *loff) 922 { 923 struct seq_file *m = (struct seq_file *)filp->private_data; 924 struct rtw89_debugfs_priv *debugfs_priv = m->private; 925 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 926 const struct rtw89_chip_info *chip = rtwdev->chip; 927 char buf[32]; 928 size_t buf_size; 929 int sel; 930 int ret; 931 932 buf_size = min(count, sizeof(buf) - 1); 933 if (copy_from_user(buf, user_buf, buf_size)) 934 return -EFAULT; 935 936 buf[buf_size] = '\0'; 937 ret = kstrtoint(buf, 0, &sel); 938 if (ret) 939 return ret; 940 941 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 942 rtw89_info(rtwdev, "invalid args: %d\n", sel); 943 return -EINVAL; 944 } 945 946 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 947 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 948 chip->chip_id); 949 return -EINVAL; 950 } 951 952 debugfs_priv->cb_data = sel; 953 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 954 955 return count; 956 } 957 958 #define RTW89_MAC_PAGE_SIZE 0x100 959 960 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 961 { 962 struct rtw89_debugfs_priv *debugfs_priv = m->private; 963 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 964 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 965 u32 start, end; 966 u32 i, j, k, page; 967 u32 val; 968 969 switch (reg_sel) { 970 case RTW89_DBG_SEL_MAC_00: 971 seq_puts(m, "Debug selected MAC page 0x00\n"); 972 start = 0x000; 973 end = 0x014; 974 break; 975 case RTW89_DBG_SEL_MAC_30: 976 seq_puts(m, "Debug selected MAC page 0x30\n"); 977 start = 0x030; 978 end = 0x033; 979 break; 980 case RTW89_DBG_SEL_MAC_40: 981 seq_puts(m, "Debug selected MAC page 0x40\n"); 982 start = 0x040; 983 end = 0x07f; 984 break; 985 case RTW89_DBG_SEL_MAC_80: 986 seq_puts(m, "Debug selected MAC page 0x80\n"); 987 start = 0x080; 988 end = 0x09f; 989 break; 990 case RTW89_DBG_SEL_MAC_C0: 991 seq_puts(m, "Debug selected MAC page 0xc0\n"); 992 start = 0x0c0; 993 end = 0x0df; 994 break; 995 case RTW89_DBG_SEL_MAC_E0: 996 seq_puts(m, "Debug selected MAC page 0xe0\n"); 997 start = 0x0e0; 998 end = 0x0ff; 999 break; 1000 case RTW89_DBG_SEL_BB: 1001 seq_puts(m, "Debug selected BB register\n"); 1002 start = 0x100; 1003 end = 0x17f; 1004 break; 1005 case RTW89_DBG_SEL_IQK: 1006 seq_puts(m, "Debug selected IQK register\n"); 1007 start = 0x180; 1008 end = 0x1bf; 1009 break; 1010 case RTW89_DBG_SEL_RFC: 1011 seq_puts(m, "Debug selected RFC register\n"); 1012 start = 0x1c0; 1013 end = 0x1ff; 1014 break; 1015 default: 1016 seq_puts(m, "Selected invalid register page\n"); 1017 return -EINVAL; 1018 } 1019 1020 for (i = start; i <= end; i++) { 1021 page = i << 8; 1022 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1023 seq_printf(m, "%08xh : ", 0x18600000 + j); 1024 for (k = 0; k < 4; k++) { 1025 val = rtw89_read32(rtwdev, j + (k << 2)); 1026 seq_printf(m, "%08x ", val); 1027 } 1028 seq_puts(m, "\n"); 1029 } 1030 } 1031 1032 return 0; 1033 } 1034 1035 static ssize_t 1036 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 1037 const char __user *user_buf, 1038 size_t count, loff_t *loff) 1039 { 1040 struct seq_file *m = (struct seq_file *)filp->private_data; 1041 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1042 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1043 char buf[32]; 1044 size_t buf_size; 1045 u32 sel, start_addr, len; 1046 int num; 1047 1048 buf_size = min(count, sizeof(buf) - 1); 1049 if (copy_from_user(buf, user_buf, buf_size)) 1050 return -EFAULT; 1051 1052 buf[buf_size] = '\0'; 1053 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1054 if (num != 3) { 1055 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1056 return -EINVAL; 1057 } 1058 1059 debugfs_priv->mac_mem.sel = sel; 1060 debugfs_priv->mac_mem.start = start_addr; 1061 debugfs_priv->mac_mem.len = len; 1062 1063 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1064 sel, start_addr, len); 1065 1066 return count; 1067 } 1068 1069 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 1070 struct rtw89_dev *rtwdev, 1071 u8 sel, u32 start_addr, u32 len) 1072 { 1073 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1074 u32 filter_model_addr = mac->filter_model_addr; 1075 u32 indir_access_addr = mac->indir_access_addr; 1076 u32 base_addr, start_page, residue; 1077 u32 i, j, p, pages; 1078 u32 dump_len, remain; 1079 u32 val; 1080 1081 remain = len; 1082 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 1083 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 1084 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 1085 base_addr = mac->mem_base_addrs[sel]; 1086 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 1087 1088 for (p = 0; p < pages; p++) { 1089 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 1090 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1091 for (i = indir_access_addr + residue; 1092 i < indir_access_addr + dump_len;) { 1093 seq_printf(m, "%08xh:", i); 1094 for (j = 0; 1095 j < 4 && i < indir_access_addr + dump_len; 1096 j++, i += 4) { 1097 val = rtw89_read32(rtwdev, i); 1098 seq_printf(m, " %08x", val); 1099 remain -= 4; 1100 } 1101 seq_puts(m, "\n"); 1102 } 1103 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 1104 } 1105 } 1106 1107 static int 1108 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 1109 { 1110 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1111 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1112 bool grant_read = false; 1113 1114 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1115 return -ENOENT; 1116 1117 if (rtwdev->chip->chip_id == RTL8852C) { 1118 switch (debugfs_priv->mac_mem.sel) { 1119 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1120 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1121 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1122 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1123 grant_read = true; 1124 break; 1125 default: 1126 break; 1127 } 1128 } 1129 1130 mutex_lock(&rtwdev->mutex); 1131 rtw89_leave_ps_mode(rtwdev); 1132 if (grant_read) 1133 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1134 rtw89_debug_dump_mac_mem(m, rtwdev, 1135 debugfs_priv->mac_mem.sel, 1136 debugfs_priv->mac_mem.start, 1137 debugfs_priv->mac_mem.len); 1138 if (grant_read) 1139 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1140 mutex_unlock(&rtwdev->mutex); 1141 1142 return 0; 1143 } 1144 1145 static ssize_t 1146 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 1147 const char __user *user_buf, 1148 size_t count, loff_t *loff) 1149 { 1150 struct seq_file *m = (struct seq_file *)filp->private_data; 1151 struct rtw89_debugfs_priv *debugfs_priv = m->private; 1152 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 1153 char buf[32]; 1154 size_t buf_size; 1155 int sel, set; 1156 int num; 1157 bool enable; 1158 1159 buf_size = min(count, sizeof(buf) - 1); 1160 if (copy_from_user(buf, user_buf, buf_size)) 1161 return -EFAULT; 1162 1163 buf[buf_size] = '\0'; 1164 num = sscanf(buf, "%d %d", &sel, &set); 1165 if (num != 2) { 1166 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1167 return -EINVAL; 1168 } 1169 1170 enable = set != 0; 1171 switch (sel) { 1172 case 0: 1173 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1174 break; 1175 case 1: 1176 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1177 break; 1178 case 2: 1179 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1180 break; 1181 case 3: 1182 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1183 break; 1184 case 4: 1185 debugfs_priv->dbgpkg_en.dbg_port = enable; 1186 break; 1187 default: 1188 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1189 return -EINVAL; 1190 } 1191 1192 rtw89_info(rtwdev, "%s debug port dump %d\n", 1193 enable ? "Enable" : "Disable", sel); 1194 1195 return count; 1196 } 1197 1198 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1199 struct seq_file *m) 1200 { 1201 return 0; 1202 } 1203 1204 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1205 struct seq_file *m) 1206 { 1207 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1208 ({ \ 1209 u32 __ctrl; \ 1210 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1211 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1212 u32 __data, __val32; \ 1213 int __ret; \ 1214 \ 1215 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1216 DLE_DFI_TYPE_##__target) | \ 1217 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1218 B_AX_WDE_DFI_ACTIVE; \ 1219 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1220 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1221 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1222 1000, 50000, false, \ 1223 rtwdev, __reg_ctrl); \ 1224 if (__ret) { \ 1225 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1226 #__type, #__target, __sel); \ 1227 return __ret; \ 1228 } \ 1229 \ 1230 __data = rtw89_read32(rtwdev, __reg_data); \ 1231 __data; \ 1232 }) 1233 1234 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 1235 ({ \ 1236 u32 __freepg, __pubpg; \ 1237 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1238 \ 1239 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1240 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1241 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1242 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1243 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1244 seq_printf(__m, "[%s] freepg head: %d\n", \ 1245 #__type, __freepg_head); \ 1246 seq_printf(__m, "[%s] freepg tail: %d\n", \ 1247 #__type, __freepg_tail); \ 1248 seq_printf(__m, "[%s] pubpg num : %d\n", \ 1249 #__type, __pubpg_num); \ 1250 }) 1251 1252 #define case_QUOTA(__m, __type, __id) \ 1253 case __type##_QTAID_##__id: \ 1254 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1255 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1256 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1257 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 1258 #__type, #__id, rsv_pgnum); \ 1259 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 1260 #__type, #__id, use_pgnum); \ 1261 break 1262 u32 quota_id; 1263 u32 val32; 1264 u16 rsv_pgnum, use_pgnum; 1265 int ret; 1266 1267 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1268 if (ret) { 1269 seq_puts(m, "[DLE] : DMAC not enabled\n"); 1270 return ret; 1271 } 1272 1273 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 1274 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 1275 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1276 switch (quota_id) { 1277 case_QUOTA(m, WDE, HOST_IF); 1278 case_QUOTA(m, WDE, WLAN_CPU); 1279 case_QUOTA(m, WDE, DATA_CPU); 1280 case_QUOTA(m, WDE, PKTIN); 1281 case_QUOTA(m, WDE, CPUIO); 1282 } 1283 } 1284 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1285 switch (quota_id) { 1286 case_QUOTA(m, PLE, B0_TXPL); 1287 case_QUOTA(m, PLE, B1_TXPL); 1288 case_QUOTA(m, PLE, C2H); 1289 case_QUOTA(m, PLE, H2C); 1290 case_QUOTA(m, PLE, WLAN_CPU); 1291 case_QUOTA(m, PLE, MPDU); 1292 case_QUOTA(m, PLE, CMAC0_RX); 1293 case_QUOTA(m, PLE, CMAC1_RX); 1294 case_QUOTA(m, PLE, CMAC1_BBRPT); 1295 case_QUOTA(m, PLE, WDRLS); 1296 case_QUOTA(m, PLE, CPUIO); 1297 } 1298 } 1299 1300 return 0; 1301 1302 #undef case_QUOTA 1303 #undef DLE_DFI_DUMP 1304 #undef DLE_DFI_FREE_PAGE_DUMP 1305 } 1306 1307 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1308 struct seq_file *m) 1309 { 1310 const struct rtw89_chip_info *chip = rtwdev->chip; 1311 u32 dmac_err; 1312 int i, ret; 1313 1314 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1315 if (ret) { 1316 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 1317 return ret; 1318 } 1319 1320 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1321 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1322 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1323 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1324 1325 if (dmac_err) { 1326 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1327 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1328 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1329 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1330 if (chip->chip_id == RTL8852C) { 1331 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1332 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1333 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1334 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1335 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1336 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1337 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n", 1338 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1339 } 1340 } 1341 1342 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1343 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1344 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1345 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1346 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1347 if (chip->chip_id == RTL8852C) 1348 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1349 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1350 else 1351 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1352 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1353 } 1354 1355 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1356 if (chip->chip_id == RTL8852C) { 1357 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n", 1358 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1359 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n", 1360 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1361 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1362 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1363 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1364 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1365 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1366 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1367 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1368 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1369 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n", 1370 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1371 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1372 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1373 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1374 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1375 1376 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1377 B_AX_DBG_SEL0, 0x8B); 1378 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1379 B_AX_DBG_SEL1, 0x8B); 1380 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1381 B_AX_SEL_0XC0_MASK, 1); 1382 for (i = 0; i < 0x10; i++) { 1383 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1384 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1385 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1386 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1387 } 1388 } else { 1389 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1390 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1391 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n", 1392 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1393 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n", 1394 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1395 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1396 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1397 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n", 1398 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1399 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n", 1400 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1401 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n", 1402 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1403 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n", 1404 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1405 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1406 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1407 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1408 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1409 } 1410 } 1411 1412 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1413 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1414 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1415 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1416 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1417 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1418 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1419 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1420 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1421 } 1422 1423 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1424 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1425 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1426 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1427 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1428 } 1429 1430 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1431 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1432 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1433 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1434 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1435 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1436 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1437 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1438 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1439 } 1440 1441 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1442 if (chip->chip_id == RTL8852C) { 1443 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1444 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1445 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1446 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1447 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1448 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1449 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1450 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1451 } else { 1452 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1453 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1454 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1455 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1456 } 1457 } 1458 1459 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1460 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n", 1461 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1462 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n", 1463 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1464 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n", 1465 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1466 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1467 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1468 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1469 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1470 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1471 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1472 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1473 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1474 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1475 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1476 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1477 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1478 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1479 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1480 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1481 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1482 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1483 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1484 if (chip->chip_id == RTL8852C) { 1485 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n", 1486 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1487 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n", 1488 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1489 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n", 1490 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1491 } else { 1492 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1493 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1494 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1495 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1496 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1497 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1498 } 1499 } 1500 1501 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1502 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1503 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1504 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1505 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1506 } 1507 1508 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1509 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1510 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1511 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1512 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1513 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1514 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1515 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1516 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1517 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1518 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1519 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1520 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1521 } 1522 1523 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1524 if (chip->chip_id == RTL8852C) { 1525 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1526 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1527 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1528 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1529 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1530 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1531 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1532 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1533 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1534 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1535 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1536 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1537 } else { 1538 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1539 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1540 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1541 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1542 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1543 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1544 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1545 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1546 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1547 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1548 } 1549 } 1550 1551 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1552 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1553 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1554 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1555 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1556 } 1557 1558 return 0; 1559 } 1560 1561 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1562 struct seq_file *m, 1563 enum rtw89_mac_idx band) 1564 { 1565 const struct rtw89_chip_info *chip = rtwdev->chip; 1566 u32 offset = 0; 1567 u32 cmac_err; 1568 int ret; 1569 1570 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1571 if (ret) { 1572 if (band) 1573 seq_puts(m, "[CMAC] : CMAC1 not enabled\n"); 1574 else 1575 seq_puts(m, "[CMAC] : CMAC0 not enabled\n"); 1576 return ret; 1577 } 1578 1579 if (band) 1580 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1581 1582 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1583 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1584 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1585 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1586 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1587 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band, 1588 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1589 1590 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1591 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1592 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1593 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1594 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1595 } 1596 1597 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1598 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 1599 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1600 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 1601 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1602 } 1603 1604 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1605 if (chip->chip_id == RTL8852C) { 1606 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1607 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1608 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 1609 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1610 } else { 1611 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1612 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1613 } 1614 } 1615 1616 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1617 if (chip->chip_id == RTL8852C) { 1618 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 1619 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1620 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1621 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1622 } else { 1623 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 1624 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1625 } 1626 } 1627 1628 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1629 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 1630 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1631 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 1632 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1633 } 1634 1635 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1636 if (chip->chip_id == RTL8852C) { 1637 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 1638 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 1639 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 1640 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1641 } else { 1642 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 1643 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 1644 } 1645 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1646 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1647 } 1648 1649 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1650 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1651 1652 return 0; 1653 } 1654 1655 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1656 struct seq_file *m) 1657 { 1658 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0); 1659 if (rtwdev->dbcc_en) 1660 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1); 1661 1662 return 0; 1663 } 1664 1665 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1666 .sel_addr = R_AX_PTCL_DBG, 1667 .sel_byte = 1, 1668 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1669 .srt = 0x00, 1670 .end = 0x3F, 1671 .rd_addr = R_AX_PTCL_DBG_INFO, 1672 .rd_byte = 4, 1673 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1674 }; 1675 1676 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1677 .sel_addr = R_AX_PTCL_DBG_C1, 1678 .sel_byte = 1, 1679 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1680 .srt = 0x00, 1681 .end = 0x3F, 1682 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1683 .rd_byte = 4, 1684 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1685 }; 1686 1687 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1688 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1689 .sel_byte = 2, 1690 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1691 .srt = 0x0, 1692 .end = 0xD, 1693 .rd_addr = R_AX_DBG_PORT_SEL, 1694 .rd_byte = 4, 1695 .rd_msk = B_AX_DEBUG_ST_MASK 1696 }; 1697 1698 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1699 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1700 .sel_byte = 2, 1701 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1702 .srt = 0x0, 1703 .end = 0x5, 1704 .rd_addr = R_AX_DBG_PORT_SEL, 1705 .rd_byte = 4, 1706 .rd_msk = B_AX_DEBUG_ST_MASK 1707 }; 1708 1709 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1710 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1711 .sel_byte = 2, 1712 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1713 .srt = 0x0, 1714 .end = 0x9, 1715 .rd_addr = R_AX_DBG_PORT_SEL, 1716 .rd_byte = 4, 1717 .rd_msk = B_AX_DEBUG_ST_MASK 1718 }; 1719 1720 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1721 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1722 .sel_byte = 2, 1723 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1724 .srt = 0x0, 1725 .end = 0x3, 1726 .rd_addr = R_AX_DBG_PORT_SEL, 1727 .rd_byte = 4, 1728 .rd_msk = B_AX_DEBUG_ST_MASK 1729 }; 1730 1731 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1732 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1733 .sel_byte = 2, 1734 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1735 .srt = 0x0, 1736 .end = 0x1, 1737 .rd_addr = R_AX_DBG_PORT_SEL, 1738 .rd_byte = 4, 1739 .rd_msk = B_AX_DEBUG_ST_MASK 1740 }; 1741 1742 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1743 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1744 .sel_byte = 2, 1745 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1746 .srt = 0x0, 1747 .end = 0x0, 1748 .rd_addr = R_AX_DBG_PORT_SEL, 1749 .rd_byte = 4, 1750 .rd_msk = B_AX_DEBUG_ST_MASK 1751 }; 1752 1753 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1754 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1755 .sel_byte = 2, 1756 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1757 .srt = 0x0, 1758 .end = 0xB, 1759 .rd_addr = R_AX_DBG_PORT_SEL, 1760 .rd_byte = 4, 1761 .rd_msk = B_AX_DEBUG_ST_MASK 1762 }; 1763 1764 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1765 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1766 .sel_byte = 2, 1767 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1768 .srt = 0x0, 1769 .end = 0x4, 1770 .rd_addr = R_AX_DBG_PORT_SEL, 1771 .rd_byte = 4, 1772 .rd_msk = B_AX_DEBUG_ST_MASK 1773 }; 1774 1775 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1776 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1777 .sel_byte = 2, 1778 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1779 .srt = 0x0, 1780 .end = 0x8, 1781 .rd_addr = R_AX_DBG_PORT_SEL, 1782 .rd_byte = 4, 1783 .rd_msk = B_AX_DEBUG_ST_MASK 1784 }; 1785 1786 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1787 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1788 .sel_byte = 2, 1789 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1790 .srt = 0x0, 1791 .end = 0x7, 1792 .rd_addr = R_AX_DBG_PORT_SEL, 1793 .rd_byte = 4, 1794 .rd_msk = B_AX_DEBUG_ST_MASK 1795 }; 1796 1797 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1798 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1799 .sel_byte = 2, 1800 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1801 .srt = 0x0, 1802 .end = 0x1, 1803 .rd_addr = R_AX_DBG_PORT_SEL, 1804 .rd_byte = 4, 1805 .rd_msk = B_AX_DEBUG_ST_MASK 1806 }; 1807 1808 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1809 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1810 .sel_byte = 2, 1811 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1812 .srt = 0x0, 1813 .end = 0x3, 1814 .rd_addr = R_AX_DBG_PORT_SEL, 1815 .rd_byte = 4, 1816 .rd_msk = B_AX_DEBUG_ST_MASK 1817 }; 1818 1819 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1820 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1821 .sel_byte = 2, 1822 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1823 .srt = 0x0, 1824 .end = 0x0, 1825 .rd_addr = R_AX_DBG_PORT_SEL, 1826 .rd_byte = 4, 1827 .rd_msk = B_AX_DEBUG_ST_MASK 1828 }; 1829 1830 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1831 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1832 .sel_byte = 2, 1833 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1834 .srt = 0x0, 1835 .end = 0x8, 1836 .rd_addr = R_AX_DBG_PORT_SEL, 1837 .rd_byte = 4, 1838 .rd_msk = B_AX_DEBUG_ST_MASK 1839 }; 1840 1841 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1842 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1843 .sel_byte = 2, 1844 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1845 .srt = 0x0, 1846 .end = 0x0, 1847 .rd_addr = R_AX_DBG_PORT_SEL, 1848 .rd_byte = 4, 1849 .rd_msk = B_AX_DEBUG_ST_MASK 1850 }; 1851 1852 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1853 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1854 .sel_byte = 2, 1855 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1856 .srt = 0x0, 1857 .end = 0x6, 1858 .rd_addr = R_AX_DBG_PORT_SEL, 1859 .rd_byte = 4, 1860 .rd_msk = B_AX_DEBUG_ST_MASK 1861 }; 1862 1863 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1864 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1865 .sel_byte = 2, 1866 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1867 .srt = 0x0, 1868 .end = 0x0, 1869 .rd_addr = R_AX_DBG_PORT_SEL, 1870 .rd_byte = 4, 1871 .rd_msk = B_AX_DEBUG_ST_MASK 1872 }; 1873 1874 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 1875 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1876 .sel_byte = 2, 1877 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1878 .srt = 0x0, 1879 .end = 0x0, 1880 .rd_addr = R_AX_DBG_PORT_SEL, 1881 .rd_byte = 4, 1882 .rd_msk = B_AX_DEBUG_ST_MASK 1883 }; 1884 1885 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 1886 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1887 .sel_byte = 1, 1888 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1889 .srt = 0x0, 1890 .end = 0x3, 1891 .rd_addr = R_AX_DBG_PORT_SEL, 1892 .rd_byte = 4, 1893 .rd_msk = B_AX_DEBUG_ST_MASK 1894 }; 1895 1896 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 1897 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1898 .sel_byte = 1, 1899 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1900 .srt = 0x0, 1901 .end = 0x6, 1902 .rd_addr = R_AX_DBG_PORT_SEL, 1903 .rd_byte = 4, 1904 .rd_msk = B_AX_DEBUG_ST_MASK 1905 }; 1906 1907 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 1908 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1909 .sel_byte = 1, 1910 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1911 .srt = 0x0, 1912 .end = 0x0, 1913 .rd_addr = R_AX_DBG_PORT_SEL, 1914 .rd_byte = 4, 1915 .rd_msk = B_AX_DEBUG_ST_MASK 1916 }; 1917 1918 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 1919 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1920 .sel_byte = 1, 1921 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1922 .srt = 0x8, 1923 .end = 0xE, 1924 .rd_addr = R_AX_DBG_PORT_SEL, 1925 .rd_byte = 4, 1926 .rd_msk = B_AX_DEBUG_ST_MASK 1927 }; 1928 1929 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 1930 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1931 .sel_byte = 1, 1932 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1933 .srt = 0x0, 1934 .end = 0x5, 1935 .rd_addr = R_AX_DBG_PORT_SEL, 1936 .rd_byte = 4, 1937 .rd_msk = B_AX_DEBUG_ST_MASK 1938 }; 1939 1940 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 1941 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1942 .sel_byte = 1, 1943 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1944 .srt = 0x0, 1945 .end = 0x6, 1946 .rd_addr = R_AX_DBG_PORT_SEL, 1947 .rd_byte = 4, 1948 .rd_msk = B_AX_DEBUG_ST_MASK 1949 }; 1950 1951 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 1952 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1953 .sel_byte = 1, 1954 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1955 .srt = 0x0, 1956 .end = 0xF, 1957 .rd_addr = R_AX_DBG_PORT_SEL, 1958 .rd_byte = 4, 1959 .rd_msk = B_AX_DEBUG_ST_MASK 1960 }; 1961 1962 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 1963 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1964 .sel_byte = 1, 1965 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1966 .srt = 0x0, 1967 .end = 0x9, 1968 .rd_addr = R_AX_DBG_PORT_SEL, 1969 .rd_byte = 4, 1970 .rd_msk = B_AX_DEBUG_ST_MASK 1971 }; 1972 1973 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 1974 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1975 .sel_byte = 1, 1976 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 1977 .srt = 0x0, 1978 .end = 0x3, 1979 .rd_addr = R_AX_DBG_PORT_SEL, 1980 .rd_byte = 4, 1981 .rd_msk = B_AX_DEBUG_ST_MASK 1982 }; 1983 1984 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1985 .sel_addr = R_AX_SCH_DBG_SEL, 1986 .sel_byte = 1, 1987 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1988 .srt = 0x00, 1989 .end = 0x2F, 1990 .rd_addr = R_AX_SCH_DBG, 1991 .rd_byte = 4, 1992 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1993 }; 1994 1995 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1996 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1997 .sel_byte = 1, 1998 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1999 .srt = 0x00, 2000 .end = 0x2F, 2001 .rd_addr = R_AX_SCH_DBG_C1, 2002 .rd_byte = 4, 2003 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2004 }; 2005 2006 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2007 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2008 .sel_byte = 1, 2009 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2010 .srt = 0x00, 2011 .end = 0x19, 2012 .rd_addr = R_AX_DBG_PORT_SEL, 2013 .rd_byte = 4, 2014 .rd_msk = B_AX_DEBUG_ST_MASK 2015 }; 2016 2017 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2018 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2019 .sel_byte = 1, 2020 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2021 .srt = 0x00, 2022 .end = 0x19, 2023 .rd_addr = R_AX_DBG_PORT_SEL, 2024 .rd_byte = 4, 2025 .rd_msk = B_AX_DEBUG_ST_MASK 2026 }; 2027 2028 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2029 .sel_addr = R_AX_RX_DEBUG_SELECT, 2030 .sel_byte = 1, 2031 .sel_msk = B_AX_DEBUG_SEL_MASK, 2032 .srt = 0x00, 2033 .end = 0x58, 2034 .rd_addr = R_AX_DBG_PORT_SEL, 2035 .rd_byte = 4, 2036 .rd_msk = B_AX_DEBUG_ST_MASK 2037 }; 2038 2039 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2040 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2041 .sel_byte = 1, 2042 .sel_msk = B_AX_DEBUG_SEL_MASK, 2043 .srt = 0x00, 2044 .end = 0x58, 2045 .rd_addr = R_AX_DBG_PORT_SEL, 2046 .rd_byte = 4, 2047 .rd_msk = B_AX_DEBUG_ST_MASK 2048 }; 2049 2050 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2051 .sel_addr = R_AX_RX_STATE_MONITOR, 2052 .sel_byte = 1, 2053 .sel_msk = B_AX_STATE_SEL_MASK, 2054 .srt = 0x00, 2055 .end = 0x17, 2056 .rd_addr = R_AX_RX_STATE_MONITOR, 2057 .rd_byte = 4, 2058 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2059 }; 2060 2061 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2062 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2063 .sel_byte = 1, 2064 .sel_msk = B_AX_STATE_SEL_MASK, 2065 .srt = 0x00, 2066 .end = 0x17, 2067 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2068 .rd_byte = 4, 2069 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2070 }; 2071 2072 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2073 .sel_addr = R_AX_RMAC_PLCP_MON, 2074 .sel_byte = 4, 2075 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2076 .srt = 0x0, 2077 .end = 0xF, 2078 .rd_addr = R_AX_RMAC_PLCP_MON, 2079 .rd_byte = 4, 2080 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2081 }; 2082 2083 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2084 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2085 .sel_byte = 4, 2086 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2087 .srt = 0x0, 2088 .end = 0xF, 2089 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2090 .rd_byte = 4, 2091 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2092 }; 2093 2094 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2095 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2096 .sel_byte = 1, 2097 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2098 .srt = 0x08, 2099 .end = 0x10, 2100 .rd_addr = R_AX_DBG_PORT_SEL, 2101 .rd_byte = 4, 2102 .rd_msk = B_AX_DEBUG_ST_MASK 2103 }; 2104 2105 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2106 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2107 .sel_byte = 1, 2108 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2109 .srt = 0x08, 2110 .end = 0x10, 2111 .rd_addr = R_AX_DBG_PORT_SEL, 2112 .rd_byte = 4, 2113 .rd_msk = B_AX_DEBUG_ST_MASK 2114 }; 2115 2116 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2117 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2118 .sel_byte = 1, 2119 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2120 .srt = 0x00, 2121 .end = 0x07, 2122 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2123 .rd_byte = 4, 2124 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2125 }; 2126 2127 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2128 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2129 .sel_byte = 1, 2130 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2131 .srt = 0x00, 2132 .end = 0x07, 2133 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2134 .rd_byte = 4, 2135 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2136 }; 2137 2138 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2139 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2140 .sel_byte = 1, 2141 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2142 .srt = 0x00, 2143 .end = 0x07, 2144 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2145 .rd_byte = 4, 2146 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2147 }; 2148 2149 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2150 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2151 .sel_byte = 1, 2152 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2153 .srt = 0x00, 2154 .end = 0x07, 2155 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2156 .rd_byte = 4, 2157 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2158 }; 2159 2160 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2161 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2162 .sel_byte = 1, 2163 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2164 .srt = 0x00, 2165 .end = 0x04, 2166 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2167 .rd_byte = 4, 2168 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2169 }; 2170 2171 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2172 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2173 .sel_byte = 1, 2174 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2175 .srt = 0x00, 2176 .end = 0x04, 2177 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2178 .rd_byte = 4, 2179 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2180 }; 2181 2182 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2183 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2184 .sel_byte = 1, 2185 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2186 .srt = 0x00, 2187 .end = 0x04, 2188 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2189 .rd_byte = 4, 2190 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2191 }; 2192 2193 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2194 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2195 .sel_byte = 1, 2196 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2197 .srt = 0x00, 2198 .end = 0x04, 2199 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2200 .rd_byte = 4, 2201 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2202 }; 2203 2204 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2205 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2206 .sel_byte = 4, 2207 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2208 .srt = 0x80000000, 2209 .end = 0x80000001, 2210 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2211 .rd_byte = 4, 2212 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2213 }; 2214 2215 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2216 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2217 .sel_byte = 4, 2218 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2219 .srt = 0x80010000, 2220 .end = 0x80010004, 2221 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2222 .rd_byte = 4, 2223 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2224 }; 2225 2226 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2227 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2228 .sel_byte = 4, 2229 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2230 .srt = 0x80020000, 2231 .end = 0x80020FFF, 2232 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2233 .rd_byte = 4, 2234 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2235 }; 2236 2237 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2238 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2239 .sel_byte = 4, 2240 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2241 .srt = 0x80030000, 2242 .end = 0x80030FFF, 2243 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2244 .rd_byte = 4, 2245 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2246 }; 2247 2248 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2249 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2250 .sel_byte = 4, 2251 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2252 .srt = 0x80040000, 2253 .end = 0x80040FFF, 2254 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2255 .rd_byte = 4, 2256 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2257 }; 2258 2259 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2260 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2261 .sel_byte = 4, 2262 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2263 .srt = 0x80050000, 2264 .end = 0x80050FFF, 2265 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2266 .rd_byte = 4, 2267 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2268 }; 2269 2270 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2271 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2272 .sel_byte = 4, 2273 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2274 .srt = 0x80060000, 2275 .end = 0x80060453, 2276 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2277 .rd_byte = 4, 2278 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2279 }; 2280 2281 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2282 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2283 .sel_byte = 4, 2284 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2285 .srt = 0x80070000, 2286 .end = 0x80070011, 2287 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2288 .rd_byte = 4, 2289 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2290 }; 2291 2292 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2293 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2294 .sel_byte = 4, 2295 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2296 .srt = 0x80000000, 2297 .end = 0x80000001, 2298 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2299 .rd_byte = 4, 2300 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2301 }; 2302 2303 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2304 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2305 .sel_byte = 4, 2306 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2307 .srt = 0x80010000, 2308 .end = 0x8001000A, 2309 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2310 .rd_byte = 4, 2311 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2312 }; 2313 2314 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2315 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2316 .sel_byte = 4, 2317 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2318 .srt = 0x80020000, 2319 .end = 0x80020DBF, 2320 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2321 .rd_byte = 4, 2322 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2323 }; 2324 2325 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2326 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2327 .sel_byte = 4, 2328 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2329 .srt = 0x80030000, 2330 .end = 0x80030DBF, 2331 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2332 .rd_byte = 4, 2333 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2334 }; 2335 2336 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2337 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2338 .sel_byte = 4, 2339 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2340 .srt = 0x80040000, 2341 .end = 0x80040DBF, 2342 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2343 .rd_byte = 4, 2344 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2345 }; 2346 2347 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2348 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2349 .sel_byte = 4, 2350 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2351 .srt = 0x80050000, 2352 .end = 0x80050DBF, 2353 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2354 .rd_byte = 4, 2355 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2356 }; 2357 2358 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2359 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2360 .sel_byte = 4, 2361 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2362 .srt = 0x80060000, 2363 .end = 0x80060041, 2364 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2365 .rd_byte = 4, 2366 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2367 }; 2368 2369 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2370 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2371 .sel_byte = 4, 2372 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2373 .srt = 0x80070000, 2374 .end = 0x80070001, 2375 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2376 .rd_byte = 4, 2377 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2378 }; 2379 2380 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2381 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2382 .sel_byte = 4, 2383 .sel_msk = B_AX_DFI_DATA_MASK, 2384 .srt = 0x80000000, 2385 .end = 0x8000017f, 2386 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2387 .rd_byte = 4, 2388 .rd_msk = B_AX_DFI_DATA_MASK 2389 }; 2390 2391 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2392 .sel_addr = R_AX_PCIE_DBG_CTRL, 2393 .sel_byte = 2, 2394 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2395 .srt = 0x00, 2396 .end = 0x03, 2397 .rd_addr = R_AX_DBG_PORT_SEL, 2398 .rd_byte = 4, 2399 .rd_msk = B_AX_DEBUG_ST_MASK 2400 }; 2401 2402 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2403 .sel_addr = R_AX_PCIE_DBG_CTRL, 2404 .sel_byte = 2, 2405 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2406 .srt = 0x00, 2407 .end = 0x04, 2408 .rd_addr = R_AX_DBG_PORT_SEL, 2409 .rd_byte = 4, 2410 .rd_msk = B_AX_DEBUG_ST_MASK 2411 }; 2412 2413 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2414 .sel_addr = R_AX_PCIE_DBG_CTRL, 2415 .sel_byte = 2, 2416 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2417 .srt = 0x00, 2418 .end = 0x01, 2419 .rd_addr = R_AX_DBG_PORT_SEL, 2420 .rd_byte = 4, 2421 .rd_msk = B_AX_DEBUG_ST_MASK 2422 }; 2423 2424 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2425 .sel_addr = R_AX_PCIE_DBG_CTRL, 2426 .sel_byte = 2, 2427 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2428 .srt = 0x00, 2429 .end = 0x05, 2430 .rd_addr = R_AX_DBG_PORT_SEL, 2431 .rd_byte = 4, 2432 .rd_msk = B_AX_DEBUG_ST_MASK 2433 }; 2434 2435 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2436 .sel_addr = R_AX_PCIE_DBG_CTRL, 2437 .sel_byte = 2, 2438 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2439 .srt = 0x00, 2440 .end = 0x05, 2441 .rd_addr = R_AX_DBG_PORT_SEL, 2442 .rd_byte = 4, 2443 .rd_msk = B_AX_DEBUG_ST_MASK 2444 }; 2445 2446 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2447 .sel_addr = R_AX_PCIE_DBG_CTRL, 2448 .sel_byte = 2, 2449 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2450 .srt = 0x00, 2451 .end = 0x06, 2452 .rd_addr = R_AX_DBG_PORT_SEL, 2453 .rd_byte = 4, 2454 .rd_msk = B_AX_DEBUG_ST_MASK 2455 }; 2456 2457 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2458 .sel_addr = R_AX_DBG_CTRL, 2459 .sel_byte = 1, 2460 .sel_msk = B_AX_DBG_SEL0, 2461 .srt = 0x34, 2462 .end = 0x3C, 2463 .rd_addr = R_AX_DBG_PORT_SEL, 2464 .rd_byte = 4, 2465 .rd_msk = B_AX_DEBUG_ST_MASK 2466 }; 2467 2468 static const struct rtw89_mac_dbg_port_info * 2469 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 2470 struct rtw89_dev *rtwdev, u32 sel) 2471 { 2472 const struct rtw89_mac_dbg_port_info *info; 2473 u32 index; 2474 u32 val32; 2475 u16 val16; 2476 u8 val8; 2477 2478 switch (sel) { 2479 case RTW89_DBG_PORT_SEL_PTCL_C0: 2480 info = &dbg_port_ptcl_c0; 2481 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2482 val16 |= B_AX_PTCL_DBG_EN; 2483 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2484 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 2485 break; 2486 case RTW89_DBG_PORT_SEL_PTCL_C1: 2487 info = &dbg_port_ptcl_c1; 2488 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2489 val16 |= B_AX_PTCL_DBG_EN; 2490 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2491 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 2492 break; 2493 case RTW89_DBG_PORT_SEL_SCH_C0: 2494 info = &dbg_port_sch_c0; 2495 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2496 val32 |= B_AX_SCH_DBG_EN; 2497 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2498 seq_puts(m, "Enable SCH C0 dbgport.\n"); 2499 break; 2500 case RTW89_DBG_PORT_SEL_SCH_C1: 2501 info = &dbg_port_sch_c1; 2502 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2503 val32 |= B_AX_SCH_DBG_EN; 2504 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2505 seq_puts(m, "Enable SCH C1 dbgport.\n"); 2506 break; 2507 case RTW89_DBG_PORT_SEL_TMAC_C0: 2508 info = &dbg_port_tmac_c0; 2509 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2510 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2511 B_AX_DBGSEL_TRXPTCL_MASK); 2512 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2513 2514 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2515 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2516 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2517 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2518 2519 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2520 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2521 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2522 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 2523 break; 2524 case RTW89_DBG_PORT_SEL_TMAC_C1: 2525 info = &dbg_port_tmac_c1; 2526 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2527 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2528 B_AX_DBGSEL_TRXPTCL_MASK); 2529 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2530 2531 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2532 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2533 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2534 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2535 2536 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2537 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2538 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2539 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 2540 break; 2541 case RTW89_DBG_PORT_SEL_RMAC_C0: 2542 info = &dbg_port_rmac_c0; 2543 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2544 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2545 B_AX_DBGSEL_TRXPTCL_MASK); 2546 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2547 2548 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2549 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2550 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2551 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2552 2553 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2554 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2555 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2556 2557 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2558 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2559 B_AX_DBGSEL_TRXPTCL_MASK); 2560 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2561 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 2562 break; 2563 case RTW89_DBG_PORT_SEL_RMAC_C1: 2564 info = &dbg_port_rmac_c1; 2565 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2566 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2567 B_AX_DBGSEL_TRXPTCL_MASK); 2568 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2569 2570 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2571 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2572 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2573 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2574 2575 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2576 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2577 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2578 2579 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2580 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2581 B_AX_DBGSEL_TRXPTCL_MASK); 2582 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2583 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 2584 break; 2585 case RTW89_DBG_PORT_SEL_RMACST_C0: 2586 info = &dbg_port_rmacst_c0; 2587 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 2588 break; 2589 case RTW89_DBG_PORT_SEL_RMACST_C1: 2590 info = &dbg_port_rmacst_c1; 2591 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 2592 break; 2593 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2594 info = &dbg_port_rmac_plcp_c0; 2595 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 2596 break; 2597 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2598 info = &dbg_port_rmac_plcp_c1; 2599 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 2600 break; 2601 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2602 info = &dbg_port_trxptcl_c0; 2603 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2604 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2605 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2606 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2607 2608 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2609 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2610 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2611 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 2612 break; 2613 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2614 info = &dbg_port_trxptcl_c1; 2615 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2616 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2617 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2618 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2619 2620 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2621 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2622 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2623 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 2624 break; 2625 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2626 info = &dbg_port_tx_infol_c0; 2627 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2628 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2629 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2630 seq_puts(m, "Enable tx infol dump.\n"); 2631 break; 2632 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2633 info = &dbg_port_tx_infoh_c0; 2634 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2635 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2636 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2637 seq_puts(m, "Enable tx infoh dump.\n"); 2638 break; 2639 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2640 info = &dbg_port_tx_infol_c1; 2641 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2642 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2643 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2644 seq_puts(m, "Enable tx infol dump.\n"); 2645 break; 2646 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2647 info = &dbg_port_tx_infoh_c1; 2648 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2649 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2650 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2651 seq_puts(m, "Enable tx infoh dump.\n"); 2652 break; 2653 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2654 info = &dbg_port_txtf_infol_c0; 2655 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2656 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2657 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2658 seq_puts(m, "Enable tx tf infol dump.\n"); 2659 break; 2660 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2661 info = &dbg_port_txtf_infoh_c0; 2662 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2663 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2664 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2665 seq_puts(m, "Enable tx tf infoh dump.\n"); 2666 break; 2667 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2668 info = &dbg_port_txtf_infol_c1; 2669 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2670 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2671 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2672 seq_puts(m, "Enable tx tf infol dump.\n"); 2673 break; 2674 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2675 info = &dbg_port_txtf_infoh_c1; 2676 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2677 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2678 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2679 seq_puts(m, "Enable tx tf infoh dump.\n"); 2680 break; 2681 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2682 info = &dbg_port_wde_bufmgn_freepg; 2683 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 2684 break; 2685 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2686 info = &dbg_port_wde_bufmgn_quota; 2687 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 2688 break; 2689 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2690 info = &dbg_port_wde_bufmgn_pagellt; 2691 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 2692 break; 2693 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2694 info = &dbg_port_wde_bufmgn_pktinfo; 2695 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 2696 break; 2697 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2698 info = &dbg_port_wde_quemgn_prepkt; 2699 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 2700 break; 2701 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2702 info = &dbg_port_wde_quemgn_nxtpkt; 2703 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 2704 break; 2705 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2706 info = &dbg_port_wde_quemgn_qlnktbl; 2707 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 2708 break; 2709 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2710 info = &dbg_port_wde_quemgn_qempty; 2711 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 2712 break; 2713 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2714 info = &dbg_port_ple_bufmgn_freepg; 2715 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 2716 break; 2717 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2718 info = &dbg_port_ple_bufmgn_quota; 2719 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 2720 break; 2721 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2722 info = &dbg_port_ple_bufmgn_pagellt; 2723 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 2724 break; 2725 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2726 info = &dbg_port_ple_bufmgn_pktinfo; 2727 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 2728 break; 2729 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2730 info = &dbg_port_ple_quemgn_prepkt; 2731 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 2732 break; 2733 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2734 info = &dbg_port_ple_quemgn_nxtpkt; 2735 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 2736 break; 2737 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2738 info = &dbg_port_ple_quemgn_qlnktbl; 2739 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 2740 break; 2741 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2742 info = &dbg_port_ple_quemgn_qempty; 2743 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 2744 break; 2745 case RTW89_DBG_PORT_SEL_PKTINFO: 2746 info = &dbg_port_pktinfo; 2747 seq_puts(m, "Enable pktinfo dump.\n"); 2748 break; 2749 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2750 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2751 B_AX_DBG_SEL0, 0x80); 2752 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2753 B_AX_SEL_0XC0_MASK, 1); 2754 fallthrough; 2755 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2756 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2757 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2758 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2759 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2760 info = &dbg_port_dspt_hdt_tx0_5; 2761 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2762 rtw89_write16_mask(rtwdev, info->sel_addr, 2763 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2764 rtw89_write16_mask(rtwdev, info->sel_addr, 2765 B_AX_DISPATCHER_CH_SEL_MASK, index); 2766 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2767 break; 2768 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2769 info = &dbg_port_dspt_hdt_tx6; 2770 rtw89_write16_mask(rtwdev, info->sel_addr, 2771 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2772 rtw89_write16_mask(rtwdev, info->sel_addr, 2773 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2774 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n"); 2775 break; 2776 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2777 info = &dbg_port_dspt_hdt_tx7; 2778 rtw89_write16_mask(rtwdev, info->sel_addr, 2779 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2780 rtw89_write16_mask(rtwdev, info->sel_addr, 2781 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2782 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n"); 2783 break; 2784 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2785 info = &dbg_port_dspt_hdt_tx8; 2786 rtw89_write16_mask(rtwdev, info->sel_addr, 2787 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2788 rtw89_write16_mask(rtwdev, info->sel_addr, 2789 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2790 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n"); 2791 break; 2792 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2793 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2794 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2795 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2796 info = &dbg_port_dspt_hdt_tx9_C; 2797 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2798 rtw89_write16_mask(rtwdev, info->sel_addr, 2799 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2800 rtw89_write16_mask(rtwdev, info->sel_addr, 2801 B_AX_DISPATCHER_CH_SEL_MASK, index); 2802 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index); 2803 break; 2804 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2805 info = &dbg_port_dspt_hdt_txD; 2806 rtw89_write16_mask(rtwdev, info->sel_addr, 2807 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2808 rtw89_write16_mask(rtwdev, info->sel_addr, 2809 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2810 seq_puts(m, "Enable Dispatcher hdt txD dump.\n"); 2811 break; 2812 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2813 info = &dbg_port_dspt_cdt_tx0; 2814 rtw89_write16_mask(rtwdev, info->sel_addr, 2815 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2816 rtw89_write16_mask(rtwdev, info->sel_addr, 2817 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2818 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n"); 2819 break; 2820 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2821 info = &dbg_port_dspt_cdt_tx1; 2822 rtw89_write16_mask(rtwdev, info->sel_addr, 2823 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2824 rtw89_write16_mask(rtwdev, info->sel_addr, 2825 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2826 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n"); 2827 break; 2828 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2829 info = &dbg_port_dspt_cdt_tx3; 2830 rtw89_write16_mask(rtwdev, info->sel_addr, 2831 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2832 rtw89_write16_mask(rtwdev, info->sel_addr, 2833 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2834 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n"); 2835 break; 2836 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2837 info = &dbg_port_dspt_cdt_tx4; 2838 rtw89_write16_mask(rtwdev, info->sel_addr, 2839 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2840 rtw89_write16_mask(rtwdev, info->sel_addr, 2841 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2842 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n"); 2843 break; 2844 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2845 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2846 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2847 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2848 info = &dbg_port_dspt_cdt_tx5_8; 2849 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2850 rtw89_write16_mask(rtwdev, info->sel_addr, 2851 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2852 rtw89_write16_mask(rtwdev, info->sel_addr, 2853 B_AX_DISPATCHER_CH_SEL_MASK, index); 2854 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2855 break; 2856 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 2857 info = &dbg_port_dspt_cdt_tx9; 2858 rtw89_write16_mask(rtwdev, info->sel_addr, 2859 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2860 rtw89_write16_mask(rtwdev, info->sel_addr, 2861 B_AX_DISPATCHER_CH_SEL_MASK, 9); 2862 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n"); 2863 break; 2864 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 2865 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 2866 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 2867 info = &dbg_port_dspt_cdt_txA_C; 2868 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 2869 rtw89_write16_mask(rtwdev, info->sel_addr, 2870 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2871 rtw89_write16_mask(rtwdev, info->sel_addr, 2872 B_AX_DISPATCHER_CH_SEL_MASK, index); 2873 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index); 2874 break; 2875 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 2876 info = &dbg_port_dspt_hdt_rx0; 2877 rtw89_write16_mask(rtwdev, info->sel_addr, 2878 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2879 rtw89_write16_mask(rtwdev, info->sel_addr, 2880 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2881 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n"); 2882 break; 2883 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 2884 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 2885 info = &dbg_port_dspt_hdt_rx1_2; 2886 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 2887 rtw89_write16_mask(rtwdev, info->sel_addr, 2888 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2889 rtw89_write16_mask(rtwdev, info->sel_addr, 2890 B_AX_DISPATCHER_CH_SEL_MASK, index); 2891 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index); 2892 break; 2893 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 2894 info = &dbg_port_dspt_hdt_rx3; 2895 rtw89_write16_mask(rtwdev, info->sel_addr, 2896 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2897 rtw89_write16_mask(rtwdev, info->sel_addr, 2898 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2899 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n"); 2900 break; 2901 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 2902 info = &dbg_port_dspt_hdt_rx4; 2903 rtw89_write16_mask(rtwdev, info->sel_addr, 2904 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2905 rtw89_write16_mask(rtwdev, info->sel_addr, 2906 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2907 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n"); 2908 break; 2909 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 2910 info = &dbg_port_dspt_hdt_rx5; 2911 rtw89_write16_mask(rtwdev, info->sel_addr, 2912 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 2913 rtw89_write16_mask(rtwdev, info->sel_addr, 2914 B_AX_DISPATCHER_CH_SEL_MASK, 5); 2915 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n"); 2916 break; 2917 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 2918 info = &dbg_port_dspt_cdt_rx_p0_0; 2919 rtw89_write16_mask(rtwdev, info->sel_addr, 2920 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2921 rtw89_write16_mask(rtwdev, info->sel_addr, 2922 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2923 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n"); 2924 break; 2925 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 2926 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 2927 info = &dbg_port_dspt_cdt_rx_p0_1; 2928 rtw89_write16_mask(rtwdev, info->sel_addr, 2929 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2930 rtw89_write16_mask(rtwdev, info->sel_addr, 2931 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2932 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n"); 2933 break; 2934 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 2935 info = &dbg_port_dspt_cdt_rx_p0_2; 2936 rtw89_write16_mask(rtwdev, info->sel_addr, 2937 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2938 rtw89_write16_mask(rtwdev, info->sel_addr, 2939 B_AX_DISPATCHER_CH_SEL_MASK, 2); 2940 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n"); 2941 break; 2942 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 2943 info = &dbg_port_dspt_cdt_rx_p1; 2944 rtw89_write8_mask(rtwdev, info->sel_addr, 2945 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 2946 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n"); 2947 break; 2948 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 2949 info = &dbg_port_dspt_stf_ctrl; 2950 rtw89_write8_mask(rtwdev, info->sel_addr, 2951 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 2952 seq_puts(m, "Enable Dispatcher stf control dump.\n"); 2953 break; 2954 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 2955 info = &dbg_port_dspt_addr_ctrl; 2956 rtw89_write8_mask(rtwdev, info->sel_addr, 2957 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 2958 seq_puts(m, "Enable Dispatcher addr control dump.\n"); 2959 break; 2960 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 2961 info = &dbg_port_dspt_wde_intf; 2962 rtw89_write8_mask(rtwdev, info->sel_addr, 2963 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 2964 seq_puts(m, "Enable Dispatcher wde interface dump.\n"); 2965 break; 2966 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 2967 info = &dbg_port_dspt_ple_intf; 2968 rtw89_write8_mask(rtwdev, info->sel_addr, 2969 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 2970 seq_puts(m, "Enable Dispatcher ple interface dump.\n"); 2971 break; 2972 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 2973 info = &dbg_port_dspt_flow_ctrl; 2974 rtw89_write8_mask(rtwdev, info->sel_addr, 2975 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 2976 seq_puts(m, "Enable Dispatcher flow control dump.\n"); 2977 break; 2978 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 2979 info = &dbg_port_pcie_txdma; 2980 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2981 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 2982 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 2983 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2984 seq_puts(m, "Enable pcie txdma dump.\n"); 2985 break; 2986 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 2987 info = &dbg_port_pcie_rxdma; 2988 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2989 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 2990 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 2991 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2992 seq_puts(m, "Enable pcie rxdma dump.\n"); 2993 break; 2994 case RTW89_DBG_PORT_SEL_PCIE_CVT: 2995 info = &dbg_port_pcie_cvt; 2996 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2997 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 2998 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 2999 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3000 seq_puts(m, "Enable pcie cvt dump.\n"); 3001 break; 3002 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3003 info = &dbg_port_pcie_cxpl; 3004 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3005 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3006 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3007 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3008 seq_puts(m, "Enable pcie cxpl dump.\n"); 3009 break; 3010 case RTW89_DBG_PORT_SEL_PCIE_IO: 3011 info = &dbg_port_pcie_io; 3012 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3013 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3014 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3015 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3016 seq_puts(m, "Enable pcie io dump.\n"); 3017 break; 3018 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3019 info = &dbg_port_pcie_misc; 3020 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3021 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3022 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3023 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3024 seq_puts(m, "Enable pcie misc dump.\n"); 3025 break; 3026 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3027 info = &dbg_port_pcie_misc2; 3028 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3029 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3030 B_AX_PCIE_DBG_SEL_MASK); 3031 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3032 seq_puts(m, "Enable pcie misc2 dump.\n"); 3033 break; 3034 default: 3035 seq_puts(m, "Dbg port select err\n"); 3036 return NULL; 3037 } 3038 3039 return info; 3040 } 3041 3042 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3043 { 3044 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3045 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3046 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3047 return false; 3048 if (rtw89_is_rtl885xb(rtwdev) && 3049 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3050 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3051 return false; 3052 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3053 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3054 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3055 return false; 3056 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3057 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3058 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3059 return false; 3060 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3061 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3062 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3063 return false; 3064 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3065 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3066 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3067 return false; 3068 3069 return true; 3070 } 3071 3072 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3073 struct seq_file *m, u32 sel) 3074 { 3075 const struct rtw89_mac_dbg_port_info *info; 3076 u8 val8; 3077 u16 val16; 3078 u32 val32; 3079 u32 i; 3080 3081 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 3082 if (!info) { 3083 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3084 return -EINVAL; 3085 } 3086 3087 #define case_DBG_SEL(__sel) \ 3088 case RTW89_DBG_PORT_SEL_##__sel: \ 3089 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 3090 break 3091 3092 switch (sel) { 3093 case_DBG_SEL(PTCL_C0); 3094 case_DBG_SEL(PTCL_C1); 3095 case_DBG_SEL(SCH_C0); 3096 case_DBG_SEL(SCH_C1); 3097 case_DBG_SEL(TMAC_C0); 3098 case_DBG_SEL(TMAC_C1); 3099 case_DBG_SEL(RMAC_C0); 3100 case_DBG_SEL(RMAC_C1); 3101 case_DBG_SEL(RMACST_C0); 3102 case_DBG_SEL(RMACST_C1); 3103 case_DBG_SEL(TRXPTCL_C0); 3104 case_DBG_SEL(TRXPTCL_C1); 3105 case_DBG_SEL(TX_INFOL_C0); 3106 case_DBG_SEL(TX_INFOH_C0); 3107 case_DBG_SEL(TX_INFOL_C1); 3108 case_DBG_SEL(TX_INFOH_C1); 3109 case_DBG_SEL(TXTF_INFOL_C0); 3110 case_DBG_SEL(TXTF_INFOH_C0); 3111 case_DBG_SEL(TXTF_INFOL_C1); 3112 case_DBG_SEL(TXTF_INFOH_C1); 3113 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3114 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3115 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3116 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3117 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3118 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3119 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3120 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3121 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3122 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3123 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3124 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3125 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3126 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3127 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3128 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3129 case_DBG_SEL(PKTINFO); 3130 case_DBG_SEL(DSPT_HDT_TX0); 3131 case_DBG_SEL(DSPT_HDT_TX1); 3132 case_DBG_SEL(DSPT_HDT_TX2); 3133 case_DBG_SEL(DSPT_HDT_TX3); 3134 case_DBG_SEL(DSPT_HDT_TX4); 3135 case_DBG_SEL(DSPT_HDT_TX5); 3136 case_DBG_SEL(DSPT_HDT_TX6); 3137 case_DBG_SEL(DSPT_HDT_TX7); 3138 case_DBG_SEL(DSPT_HDT_TX8); 3139 case_DBG_SEL(DSPT_HDT_TX9); 3140 case_DBG_SEL(DSPT_HDT_TXA); 3141 case_DBG_SEL(DSPT_HDT_TXB); 3142 case_DBG_SEL(DSPT_HDT_TXC); 3143 case_DBG_SEL(DSPT_HDT_TXD); 3144 case_DBG_SEL(DSPT_HDT_TXE); 3145 case_DBG_SEL(DSPT_HDT_TXF); 3146 case_DBG_SEL(DSPT_CDT_TX0); 3147 case_DBG_SEL(DSPT_CDT_TX1); 3148 case_DBG_SEL(DSPT_CDT_TX3); 3149 case_DBG_SEL(DSPT_CDT_TX4); 3150 case_DBG_SEL(DSPT_CDT_TX5); 3151 case_DBG_SEL(DSPT_CDT_TX6); 3152 case_DBG_SEL(DSPT_CDT_TX7); 3153 case_DBG_SEL(DSPT_CDT_TX8); 3154 case_DBG_SEL(DSPT_CDT_TX9); 3155 case_DBG_SEL(DSPT_CDT_TXA); 3156 case_DBG_SEL(DSPT_CDT_TXB); 3157 case_DBG_SEL(DSPT_CDT_TXC); 3158 case_DBG_SEL(DSPT_HDT_RX0); 3159 case_DBG_SEL(DSPT_HDT_RX1); 3160 case_DBG_SEL(DSPT_HDT_RX2); 3161 case_DBG_SEL(DSPT_HDT_RX3); 3162 case_DBG_SEL(DSPT_HDT_RX4); 3163 case_DBG_SEL(DSPT_HDT_RX5); 3164 case_DBG_SEL(DSPT_CDT_RX_P0); 3165 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3166 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3167 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3168 case_DBG_SEL(DSPT_CDT_RX_P1); 3169 case_DBG_SEL(DSPT_STF_CTRL); 3170 case_DBG_SEL(DSPT_ADDR_CTRL); 3171 case_DBG_SEL(DSPT_WDE_INTF); 3172 case_DBG_SEL(DSPT_PLE_INTF); 3173 case_DBG_SEL(DSPT_FLOW_CTRL); 3174 case_DBG_SEL(PCIE_TXDMA); 3175 case_DBG_SEL(PCIE_RXDMA); 3176 case_DBG_SEL(PCIE_CVT); 3177 case_DBG_SEL(PCIE_CXPL); 3178 case_DBG_SEL(PCIE_IO); 3179 case_DBG_SEL(PCIE_MISC); 3180 case_DBG_SEL(PCIE_MISC2); 3181 } 3182 3183 #undef case_DBG_SEL 3184 3185 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 3186 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 3187 3188 for (i = info->srt; i <= info->end; i++) { 3189 switch (info->sel_byte) { 3190 case 1: 3191 default: 3192 rtw89_write8_mask(rtwdev, info->sel_addr, 3193 info->sel_msk, i); 3194 seq_printf(m, "0x%02X: ", i); 3195 break; 3196 case 2: 3197 rtw89_write16_mask(rtwdev, info->sel_addr, 3198 info->sel_msk, i); 3199 seq_printf(m, "0x%04X: ", i); 3200 break; 3201 case 4: 3202 rtw89_write32_mask(rtwdev, info->sel_addr, 3203 info->sel_msk, i); 3204 seq_printf(m, "0x%04X: ", i); 3205 break; 3206 } 3207 3208 udelay(10); 3209 3210 switch (info->rd_byte) { 3211 case 1: 3212 default: 3213 val8 = rtw89_read8_mask(rtwdev, 3214 info->rd_addr, info->rd_msk); 3215 seq_printf(m, "0x%02X\n", val8); 3216 break; 3217 case 2: 3218 val16 = rtw89_read16_mask(rtwdev, 3219 info->rd_addr, info->rd_msk); 3220 seq_printf(m, "0x%04X\n", val16); 3221 break; 3222 case 4: 3223 val32 = rtw89_read32_mask(rtwdev, 3224 info->rd_addr, info->rd_msk); 3225 seq_printf(m, "0x%08X\n", val32); 3226 break; 3227 } 3228 } 3229 3230 return 0; 3231 } 3232 3233 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3234 struct seq_file *m) 3235 { 3236 u32 sel; 3237 int ret = 0; 3238 3239 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3240 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3241 if (!is_dbg_port_valid(rtwdev, sel)) 3242 continue; 3243 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 3244 if (ret) { 3245 rtw89_err(rtwdev, 3246 "failed to dump debug port %d\n", sel); 3247 break; 3248 } 3249 } 3250 3251 return ret; 3252 } 3253 3254 static int 3255 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 3256 { 3257 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3258 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3259 3260 if (debugfs_priv->dbgpkg_en.ss_dbg) 3261 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 3262 if (debugfs_priv->dbgpkg_en.dle_dbg) 3263 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 3264 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3265 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 3266 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3267 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 3268 if (debugfs_priv->dbgpkg_en.dbg_port) 3269 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 3270 3271 return 0; 3272 }; 3273 3274 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 3275 const char __user *user_buf, size_t count) 3276 { 3277 char *buf; 3278 u8 *bin; 3279 int num; 3280 int err = 0; 3281 3282 buf = memdup_user(user_buf, count); 3283 if (IS_ERR(buf)) 3284 return buf; 3285 3286 num = count / 2; 3287 bin = kmalloc(num, GFP_KERNEL); 3288 if (!bin) { 3289 err = -EFAULT; 3290 goto out; 3291 } 3292 3293 if (hex2bin(bin, buf, num)) { 3294 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3295 kfree(bin); 3296 err = -EINVAL; 3297 } 3298 3299 out: 3300 kfree(buf); 3301 3302 return err ? ERR_PTR(err) : bin; 3303 } 3304 3305 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 3306 const char __user *user_buf, 3307 size_t count, loff_t *loff) 3308 { 3309 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3310 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3311 u8 *h2c; 3312 int ret; 3313 u16 h2c_len = count / 2; 3314 3315 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3316 if (IS_ERR(h2c)) 3317 return -EFAULT; 3318 3319 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3320 3321 kfree(h2c); 3322 3323 return ret ? ret : count; 3324 } 3325 3326 static int 3327 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 3328 { 3329 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3330 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3331 struct rtw89_early_h2c *early_h2c; 3332 int seq = 0; 3333 3334 mutex_lock(&rtwdev->mutex); 3335 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3336 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 3337 mutex_unlock(&rtwdev->mutex); 3338 3339 return 0; 3340 } 3341 3342 static ssize_t 3343 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 3344 size_t count, loff_t *loff) 3345 { 3346 struct seq_file *m = (struct seq_file *)filp->private_data; 3347 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3348 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3349 struct rtw89_early_h2c *early_h2c; 3350 u8 *h2c; 3351 u16 h2c_len = count / 2; 3352 3353 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 3354 if (IS_ERR(h2c)) 3355 return -EFAULT; 3356 3357 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3358 kfree(h2c); 3359 rtw89_fw_free_all_early_h2c(rtwdev); 3360 goto out; 3361 } 3362 3363 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3364 if (!early_h2c) { 3365 kfree(h2c); 3366 return -EFAULT; 3367 } 3368 3369 early_h2c->h2c = h2c; 3370 early_h2c->h2c_len = h2c_len; 3371 3372 mutex_lock(&rtwdev->mutex); 3373 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3374 mutex_unlock(&rtwdev->mutex); 3375 3376 out: 3377 return count; 3378 } 3379 3380 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3381 { 3382 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3383 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3384 u16 pkt_id; 3385 int ret; 3386 3387 rtw89_leave_ps_mode(rtwdev); 3388 3389 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3390 if (ret) 3391 return ret; 3392 3393 /* intentionally, enqueue two pkt, but has only one pkt id */ 3394 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3395 ctrl_para.start_pktid = pkt_id; 3396 ctrl_para.end_pktid = pkt_id; 3397 ctrl_para.pkt_num = 1; /* start from 0 */ 3398 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3399 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3400 3401 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3402 return -EFAULT; 3403 3404 return 0; 3405 } 3406 3407 static int 3408 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v) 3409 { 3410 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3411 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3412 3413 seq_printf(m, "%d\n", 3414 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3415 return 0; 3416 } 3417 3418 enum rtw89_dbg_crash_simulation_type { 3419 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3420 RTW89_DBG_SIM_CTRL_ERROR = 2, 3421 }; 3422 3423 static ssize_t 3424 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf, 3425 size_t count, loff_t *loff) 3426 { 3427 struct seq_file *m = (struct seq_file *)filp->private_data; 3428 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3429 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3430 int (*sim)(struct rtw89_dev *rtwdev); 3431 u8 crash_type; 3432 int ret; 3433 3434 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type); 3435 if (ret) 3436 return -EINVAL; 3437 3438 switch (crash_type) { 3439 case RTW89_DBG_SIM_CPU_EXCEPTION: 3440 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw)) 3441 return -EOPNOTSUPP; 3442 sim = rtw89_fw_h2c_trigger_cpu_exception; 3443 break; 3444 case RTW89_DBG_SIM_CTRL_ERROR: 3445 sim = rtw89_dbg_trigger_ctrl_error; 3446 break; 3447 default: 3448 return -EINVAL; 3449 } 3450 3451 mutex_lock(&rtwdev->mutex); 3452 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3453 ret = sim(rtwdev); 3454 mutex_unlock(&rtwdev->mutex); 3455 3456 if (ret) 3457 return ret; 3458 3459 return count; 3460 } 3461 3462 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 3463 { 3464 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3465 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3466 3467 rtw89_btc_dump_info(rtwdev, m); 3468 3469 return 0; 3470 } 3471 3472 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 3473 const char __user *user_buf, 3474 size_t count, loff_t *loff) 3475 { 3476 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3477 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3478 struct rtw89_btc *btc = &rtwdev->btc; 3479 const struct rtw89_btc_ver *ver = btc->ver; 3480 int ret; 3481 3482 ret = kstrtobool_from_user(user_buf, count, &btc->manual_ctrl); 3483 if (ret) 3484 return ret; 3485 3486 if (ver->fcxctrl == 7) 3487 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3488 else 3489 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3490 3491 return count; 3492 } 3493 3494 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct file *filp, 3495 const char __user *user_buf, 3496 size_t count, loff_t *loff) 3497 { 3498 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 3499 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3500 struct rtw89_fw_log *log = &rtwdev->fw.log; 3501 bool fw_log_manual; 3502 3503 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 3504 goto out; 3505 3506 mutex_lock(&rtwdev->mutex); 3507 log->enable = fw_log_manual; 3508 if (log->enable) 3509 rtw89_fw_log_prepare(rtwdev); 3510 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3511 mutex_unlock(&rtwdev->mutex); 3512 out: 3513 return count; 3514 } 3515 3516 static void rtw89_sta_link_info_get_iter(struct seq_file *m, 3517 struct rtw89_dev *rtwdev, 3518 struct rtw89_sta_link *rtwsta_link) 3519 { 3520 static const char * const he_gi_str[] = { 3521 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3522 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3523 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3524 }; 3525 static const char * const eht_gi_str[] = { 3526 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3527 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3528 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3529 }; 3530 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3531 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3532 struct rtw89_hal *hal = &rtwdev->hal; 3533 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3534 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3535 struct ieee80211_link_sta *link_sta; 3536 u8 evm_min, evm_max, evm_1ss; 3537 u16 max_rc_amsdu_len; 3538 u8 rssi; 3539 u8 snr; 3540 int i; 3541 3542 rcu_read_lock(); 3543 3544 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3545 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3546 3547 rcu_read_unlock(); 3548 3549 seq_printf(m, "TX rate [%u, %u]: ", rtwsta_link->mac_id, rtwsta_link->link_id); 3550 3551 if (rate->flags & RATE_INFO_FLAGS_MCS) 3552 seq_printf(m, "HT MCS-%d%s", rate->mcs, 3553 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3554 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3555 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 3556 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3557 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3558 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3559 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3560 he_gi_str[rate->he_gi] : "N/A"); 3561 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3562 seq_printf(m, "EHT %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 3563 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3564 eht_gi_str[rate->eht_gi] : "N/A"); 3565 else 3566 seq_printf(m, "Legacy %d", rate->legacy); 3567 seq_printf(m, "%s", rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3568 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw)); 3569 seq_printf(m, " (hw_rate=0x%x)", rtwsta_link->ra_report.hw_rate); 3570 seq_printf(m, " ==> agg_wait=%d (%d)\n", rtwsta_link->max_agg_wait, 3571 max_rc_amsdu_len); 3572 3573 seq_printf(m, "RX rate [%u, %u]: ", rtwsta_link->mac_id, rtwsta_link->link_id); 3574 3575 switch (status->encoding) { 3576 case RX_ENC_LEGACY: 3577 seq_printf(m, "Legacy %d", status->rate_idx + 3578 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3579 break; 3580 case RX_ENC_HT: 3581 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 3582 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3583 break; 3584 case RX_ENC_VHT: 3585 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 3586 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3587 break; 3588 case RX_ENC_HE: 3589 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3590 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3591 he_gi_str[status->he_gi] : "N/A"); 3592 break; 3593 case RX_ENC_EHT: 3594 seq_printf(m, "EHT %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 3595 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 3596 eht_gi_str[status->eht.gi] : "N/A"); 3597 break; 3598 } 3599 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw)); 3600 seq_printf(m, " (hw_rate=0x%x)\n", rtwsta_link->rx_hw_rate); 3601 3602 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 3603 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [", 3604 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta_link->prev_rssi); 3605 for (i = 0; i < ant_num; i++) { 3606 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 3607 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi), 3608 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3609 i + 1 == ant_num ? "" : ", "); 3610 } 3611 seq_puts(m, "]\n"); 3612 3613 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 3614 seq_printf(m, "EVM: [%2u.%02u, ", evm_1ss >> 2, (evm_1ss & 0x3) * 25); 3615 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3616 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 3617 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 3618 3619 seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ", 3620 evm_min >> 2, (evm_min & 0x3) * 25, 3621 evm_max >> 2, (evm_max & 0x3) * 25); 3622 } 3623 seq_puts(m, "]\t"); 3624 3625 snr = ewma_snr_read(&rtwsta_link->avg_snr); 3626 seq_printf(m, "SNR: %u\n", snr); 3627 } 3628 3629 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3630 { 3631 struct seq_file *m = (struct seq_file *)data; 3632 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3633 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3634 struct rtw89_sta_link *rtwsta_link; 3635 unsigned int link_id; 3636 3637 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3638 rtw89_sta_link_info_get_iter(m, rtwdev, rtwsta_link); 3639 } 3640 3641 static void 3642 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 3643 enum rtw89_hw_rate first_rate, int len) 3644 { 3645 int i; 3646 3647 for (i = 0; i < len; i++) 3648 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 3649 pkt_stat->rx_rate_cnt[first_rate + i]); 3650 } 3651 3652 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 3653 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 3654 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 3655 3656 static const struct rtw89_rx_rate_cnt_info { 3657 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 3658 int len; 3659 int ext; 3660 const char *rate_mode; 3661 } rtw89_rx_rate_cnt_infos[] = { 3662 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 3663 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 3664 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 3665 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 3666 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 3667 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 3668 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 3669 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 3670 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 3671 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 3672 }; 3673 3674 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 3675 { 3676 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3677 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3678 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3679 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3680 const struct rtw89_chip_info *chip = rtwdev->chip; 3681 const struct rtw89_rx_rate_cnt_info *info; 3682 struct rtw89_hal *hal = &rtwdev->hal; 3683 enum rtw89_hw_rate first_rate; 3684 u8 rssi; 3685 int i; 3686 3687 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3688 3689 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d", 3690 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv); 3691 if (hal->thermal_prot_lv) 3692 seq_printf(m, ", duty: %d%%", 3693 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 3694 seq_printf(m, "), RX: %u [%u] Mbps (lv: %d)\n", 3695 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 3696 seq_printf(m, "Beacon: %u (%d dBm), TF: %u\n", pkt_stat->beacon_nr, 3697 RTW89_RSSI_RAW_TO_DBM(rssi), stats->rx_tf_periodic); 3698 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 3699 stats->rx_avg_len); 3700 3701 seq_puts(m, "RX count:\n"); 3702 3703 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3704 info = &rtw89_rx_rate_cnt_infos[i]; 3705 first_rate = info->first_rate[chip->chip_gen]; 3706 if (first_rate >= RTW89_HW_RATE_NR) 3707 continue; 3708 3709 seq_printf(m, "%10s [", info->rate_mode); 3710 rtw89_debug_append_rx_rate(m, pkt_stat, 3711 first_rate, info->len); 3712 if (info->ext) { 3713 seq_puts(m, "]["); 3714 rtw89_debug_append_rx_rate(m, pkt_stat, 3715 first_rate + info->len, info->ext); 3716 } 3717 seq_puts(m, "]\n"); 3718 } 3719 3720 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 3721 3722 return 0; 3723 } 3724 3725 static void rtw89_dump_addr_cam(struct seq_file *m, 3726 struct rtw89_dev *rtwdev, 3727 struct rtw89_addr_cam_entry *addr_cam) 3728 { 3729 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3730 const struct rtw89_sec_cam_entry *sec_entry; 3731 u8 sec_cam_idx; 3732 int i; 3733 3734 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 3735 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 3736 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 3737 addr_cam->sec_cam_map); 3738 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 3739 sec_cam_idx = addr_cam->sec_ent[i]; 3740 sec_entry = cam_info->sec_entries[sec_cam_idx]; 3741 if (!sec_entry) 3742 continue; 3743 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 3744 if (sec_entry->ext_key) 3745 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 3746 seq_puts(m, "\n"); 3747 } 3748 } 3749 3750 __printf(3, 4) 3751 static void rtw89_dump_pkt_offload(struct seq_file *m, struct list_head *pkt_list, 3752 const char *fmt, ...) 3753 { 3754 struct rtw89_pktofld_info *info; 3755 struct va_format vaf; 3756 va_list args; 3757 3758 if (list_empty(pkt_list)) 3759 return; 3760 3761 va_start(args, fmt); 3762 vaf.va = &args; 3763 vaf.fmt = fmt; 3764 3765 seq_printf(m, "%pV", &vaf); 3766 3767 va_end(args); 3768 3769 list_for_each_entry(info, pkt_list, list) 3770 seq_printf(m, "%d ", info->id); 3771 3772 seq_puts(m, "\n"); 3773 } 3774 3775 static void rtw89_vif_link_ids_get(struct seq_file *m, u8 *mac, 3776 struct rtw89_dev *rtwdev, 3777 struct rtw89_vif_link *rtwvif_link) 3778 { 3779 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 3780 3781 seq_printf(m, " [%u] %pM\n", rtwvif_link->mac_id, rtwvif_link->mac_addr); 3782 seq_printf(m, "\tlink_id=%u\n", rtwvif_link->link_id); 3783 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 3784 rtw89_dump_addr_cam(m, rtwdev, &rtwvif_link->addr_cam); 3785 rtw89_dump_pkt_offload(m, &rtwvif_link->general_pkt_list, 3786 "\tpkt_ofld[GENERAL]: "); 3787 } 3788 3789 static 3790 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 3791 { 3792 struct seq_file *m = (struct seq_file *)data; 3793 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 3794 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3795 struct rtw89_vif_link *rtwvif_link; 3796 unsigned int link_id; 3797 3798 seq_printf(m, "VIF %pM\n", rtwvif->mac_addr); 3799 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3800 rtw89_vif_link_ids_get(m, mac, rtwdev, rtwvif_link); 3801 } 3802 3803 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_dev *rtwdev, 3804 struct rtw89_sta_link *rtwsta_link) 3805 { 3806 struct rtw89_ba_cam_entry *entry; 3807 bool first = true; 3808 3809 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 3810 if (first) { 3811 seq_puts(m, "\tba_cam "); 3812 first = false; 3813 } else { 3814 seq_puts(m, ", "); 3815 } 3816 seq_printf(m, "tid[%u]=%d", entry->tid, 3817 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 3818 } 3819 seq_puts(m, "\n"); 3820 } 3821 3822 static void rtw89_sta_link_ids_get(struct seq_file *m, 3823 struct rtw89_dev *rtwdev, 3824 struct rtw89_sta_link *rtwsta_link) 3825 { 3826 struct ieee80211_link_sta *link_sta; 3827 3828 rcu_read_lock(); 3829 3830 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3831 3832 seq_printf(m, " [%u] %pM\n", rtwsta_link->mac_id, link_sta->addr); 3833 3834 rcu_read_unlock(); 3835 3836 seq_printf(m, "\tlink_id=%u\n", rtwsta_link->link_id); 3837 rtw89_dump_addr_cam(m, rtwdev, &rtwsta_link->addr_cam); 3838 rtw89_dump_ba_cam(m, rtwdev, rtwsta_link); 3839 } 3840 3841 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 3842 { 3843 struct seq_file *m = (struct seq_file *)data; 3844 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3845 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3846 struct rtw89_sta_link *rtwsta_link; 3847 unsigned int link_id; 3848 3849 seq_printf(m, "STA %pM %s\n", sta->addr, sta->tdls ? "(TDLS)" : ""); 3850 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3851 rtw89_sta_link_ids_get(m, rtwdev, rtwsta_link); 3852 } 3853 3854 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 3855 { 3856 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3857 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3858 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3859 u8 idx; 3860 3861 mutex_lock(&rtwdev->mutex); 3862 3863 seq_puts(m, "map:\n"); 3864 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 3865 rtwdev->mac_id_map); 3866 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 3867 cam_info->addr_cam_map); 3868 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 3869 cam_info->bssid_cam_map); 3870 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 3871 cam_info->sec_cam_map); 3872 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map), 3873 cam_info->ba_cam_map); 3874 seq_printf(m, "\tpkt_ofld: %*ph\n", (int)sizeof(rtwdev->pkt_offload), 3875 rtwdev->pkt_offload); 3876 3877 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 3878 if (!(rtwdev->chip->support_bands & BIT(idx))) 3879 continue; 3880 rtw89_dump_pkt_offload(m, &rtwdev->scan_info.pkt_list[idx], 3881 "\t\t[SCAN %u]: ", idx); 3882 } 3883 3884 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 3885 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 3886 3887 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 3888 3889 mutex_unlock(&rtwdev->mutex); 3890 3891 return 0; 3892 } 3893 3894 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 3895 3896 static const struct rtw89_disabled_dm_info { 3897 enum rtw89_dm_type type; 3898 const char *name; 3899 } rtw89_disabled_dm_infos[] = { 3900 DM_INFO(DYNAMIC_EDCCA), 3901 DM_INFO(THERMAL_PROTECT), 3902 }; 3903 3904 static int 3905 rtw89_debug_priv_disable_dm_get(struct seq_file *m, void *v) 3906 { 3907 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3908 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3909 const struct rtw89_disabled_dm_info *info; 3910 struct rtw89_hal *hal = &rtwdev->hal; 3911 u32 disabled; 3912 int i; 3913 3914 seq_printf(m, "Disabled DM: 0x%x\n", hal->disabled_dm_bitmap); 3915 3916 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 3917 info = &rtw89_disabled_dm_infos[i]; 3918 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 3919 3920 seq_printf(m, "[%d] %s: %c\n", info->type, info->name, 3921 disabled ? 'X' : 'O'); 3922 } 3923 3924 return 0; 3925 } 3926 3927 static ssize_t 3928 rtw89_debug_priv_disable_dm_set(struct file *filp, const char __user *user_buf, 3929 size_t count, loff_t *loff) 3930 { 3931 struct seq_file *m = (struct seq_file *)filp->private_data; 3932 struct rtw89_debugfs_priv *debugfs_priv = m->private; 3933 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 3934 struct rtw89_hal *hal = &rtwdev->hal; 3935 u32 conf; 3936 int ret; 3937 3938 ret = kstrtou32_from_user(user_buf, count, 0, &conf); 3939 if (ret) 3940 return -EINVAL; 3941 3942 hal->disabled_dm_bitmap = conf; 3943 3944 return count; 3945 } 3946 3947 #define rtw89_debug_priv_get(name) \ 3948 { \ 3949 .cb_read = rtw89_debug_priv_ ##name## _get, \ 3950 } 3951 3952 #define rtw89_debug_priv_set(name) \ 3953 { \ 3954 .cb_write = rtw89_debug_priv_ ##name## _set, \ 3955 } 3956 3957 #define rtw89_debug_priv_select_and_get(name) \ 3958 { \ 3959 .cb_write = rtw89_debug_priv_ ##name## _select, \ 3960 .cb_read = rtw89_debug_priv_ ##name## _get, \ 3961 } 3962 3963 #define rtw89_debug_priv_set_and_get(name) \ 3964 { \ 3965 .cb_write = rtw89_debug_priv_ ##name## _set, \ 3966 .cb_read = rtw89_debug_priv_ ##name## _get, \ 3967 } 3968 3969 static const struct rtw89_debugfs rtw89_debugfs_templ = { 3970 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 3971 .write_reg = rtw89_debug_priv_set(write_reg), 3972 .read_rf = rtw89_debug_priv_select_and_get(read_rf), 3973 .write_rf = rtw89_debug_priv_set(write_rf), 3974 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump), 3975 .txpwr_table = rtw89_debug_priv_get(txpwr_table), 3976 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump), 3977 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump), 3978 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump), 3979 .send_h2c = rtw89_debug_priv_set(send_h2c), 3980 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c), 3981 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash), 3982 .btc_info = rtw89_debug_priv_get(btc_info), 3983 .btc_manual = rtw89_debug_priv_set(btc_manual), 3984 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual), 3985 .phy_info = rtw89_debug_priv_get(phy_info), 3986 .stations = rtw89_debug_priv_get(stations), 3987 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm), 3988 }; 3989 3990 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 3991 do { \ 3992 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 3993 priv->rtwdev = rtwdev; \ 3994 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 3995 &file_ops_ ##fopname))) \ 3996 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 3997 } while (0) 3998 3999 #define rtw89_debugfs_add_w(name) \ 4000 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 4001 #define rtw89_debugfs_add_rw(name) \ 4002 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 4003 #define rtw89_debugfs_add_r(name) \ 4004 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 4005 4006 static 4007 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4008 { 4009 rtw89_debugfs_add_rw(read_reg); 4010 rtw89_debugfs_add_w(write_reg); 4011 rtw89_debugfs_add_rw(read_rf); 4012 rtw89_debugfs_add_w(write_rf); 4013 rtw89_debugfs_add_r(rf_reg_dump); 4014 rtw89_debugfs_add_r(txpwr_table); 4015 rtw89_debugfs_add_rw(mac_reg_dump); 4016 rtw89_debugfs_add_rw(mac_mem_dump); 4017 rtw89_debugfs_add_rw(mac_dbg_port_dump); 4018 } 4019 4020 static 4021 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4022 { 4023 rtw89_debugfs_add_w(send_h2c); 4024 rtw89_debugfs_add_rw(early_h2c); 4025 rtw89_debugfs_add_rw(fw_crash); 4026 rtw89_debugfs_add_r(btc_info); 4027 rtw89_debugfs_add_w(btc_manual); 4028 rtw89_debugfs_add_w(fw_log_manual); 4029 rtw89_debugfs_add_r(phy_info); 4030 rtw89_debugfs_add_r(stations); 4031 rtw89_debugfs_add_rw(disable_dm); 4032 } 4033 4034 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 4035 { 4036 struct dentry *debugfs_topdir; 4037 4038 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 4039 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 4040 if (!rtwdev->debugfs) 4041 return; 4042 4043 debugfs_topdir = debugfs_create_dir("rtw89", 4044 rtwdev->hw->wiphy->debugfsdir); 4045 4046 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 4047 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 4048 } 4049 4050 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 4051 { 4052 kfree(rtwdev->debugfs); 4053 } 4054 #endif 4055 4056 #ifdef CONFIG_RTW89_DEBUGMSG 4057 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 4058 const char *fmt, ...) 4059 { 4060 struct va_format vaf = { 4061 .fmt = fmt, 4062 }; 4063 4064 va_list args; 4065 4066 va_start(args, fmt); 4067 vaf.va = &args; 4068 4069 if (rtw89_debug_mask & mask) 4070 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 4071 4072 va_end(args); 4073 } 4074 EXPORT_SYMBOL(rtw89_debug); 4075 #endif 4076