1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "ps.h" 12 #include "reg.h" 13 #include "sar.h" 14 15 #ifdef CONFIG_RTW89_DEBUGMSG 16 unsigned int rtw89_debug_mask; 17 EXPORT_SYMBOL(rtw89_debug_mask); 18 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 19 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 20 #endif 21 22 #ifdef CONFIG_RTW89_DEBUGFS 23 struct rtw89_debugfs_priv { 24 struct rtw89_dev *rtwdev; 25 int (*cb_read)(struct seq_file *m, void *v); 26 ssize_t (*cb_write)(struct file *filp, const char __user *buffer, 27 size_t count, loff_t *loff); 28 union { 29 u32 cb_data; 30 struct { 31 u32 addr; 32 u8 len; 33 } read_reg; 34 struct { 35 u32 addr; 36 u32 mask; 37 u8 path; 38 } read_rf; 39 struct { 40 u8 ss_dbg:1; 41 u8 dle_dbg:1; 42 u8 dmac_dbg:1; 43 u8 cmac_dbg:1; 44 u8 dbg_port:1; 45 } dbgpkg_en; 46 struct { 47 u32 start; 48 u32 len; 49 u8 sel; 50 } mac_mem; 51 }; 52 }; 53 54 static int rtw89_debugfs_single_show(struct seq_file *m, void *v) 55 { 56 struct rtw89_debugfs_priv *debugfs_priv = m->private; 57 58 return debugfs_priv->cb_read(m, v); 59 } 60 61 static ssize_t rtw89_debugfs_single_write(struct file *filp, 62 const char __user *buffer, 63 size_t count, loff_t *loff) 64 { 65 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 66 67 return debugfs_priv->cb_write(filp, buffer, count, loff); 68 } 69 70 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp, 71 const char __user *buffer, 72 size_t count, loff_t *loff) 73 { 74 struct seq_file *seqpriv = (struct seq_file *)filp->private_data; 75 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private; 76 77 return debugfs_priv->cb_write(filp, buffer, count, loff); 78 } 79 80 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp) 81 { 82 return single_open(filp, rtw89_debugfs_single_show, inode->i_private); 83 } 84 85 static int rtw89_debugfs_close(struct inode *inode, struct file *filp) 86 { 87 return 0; 88 } 89 90 static const struct file_operations file_ops_single_r = { 91 .owner = THIS_MODULE, 92 .open = rtw89_debugfs_single_open, 93 .read = seq_read, 94 .llseek = seq_lseek, 95 .release = single_release, 96 }; 97 98 static const struct file_operations file_ops_common_rw = { 99 .owner = THIS_MODULE, 100 .open = rtw89_debugfs_single_open, 101 .release = single_release, 102 .read = seq_read, 103 .llseek = seq_lseek, 104 .write = rtw89_debugfs_seq_file_write, 105 }; 106 107 static const struct file_operations file_ops_single_w = { 108 .owner = THIS_MODULE, 109 .write = rtw89_debugfs_single_write, 110 .open = simple_open, 111 .release = rtw89_debugfs_close, 112 }; 113 114 static ssize_t 115 rtw89_debug_priv_read_reg_select(struct file *filp, 116 const char __user *user_buf, 117 size_t count, loff_t *loff) 118 { 119 struct seq_file *m = (struct seq_file *)filp->private_data; 120 struct rtw89_debugfs_priv *debugfs_priv = m->private; 121 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 122 char buf[32]; 123 size_t buf_size; 124 u32 addr, len; 125 int num; 126 127 buf_size = min(count, sizeof(buf) - 1); 128 if (copy_from_user(buf, user_buf, buf_size)) 129 return -EFAULT; 130 131 buf[buf_size] = '\0'; 132 num = sscanf(buf, "%x %x", &addr, &len); 133 if (num != 2) { 134 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 135 return -EINVAL; 136 } 137 138 debugfs_priv->read_reg.addr = addr; 139 debugfs_priv->read_reg.len = len; 140 141 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 142 143 return count; 144 } 145 146 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v) 147 { 148 struct rtw89_debugfs_priv *debugfs_priv = m->private; 149 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 150 u32 addr, data; 151 u8 len; 152 153 len = debugfs_priv->read_reg.len; 154 addr = debugfs_priv->read_reg.addr; 155 156 switch (len) { 157 case 1: 158 data = rtw89_read8(rtwdev, addr); 159 break; 160 case 2: 161 data = rtw89_read16(rtwdev, addr); 162 break; 163 case 4: 164 data = rtw89_read32(rtwdev, addr); 165 break; 166 default: 167 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 168 return -EINVAL; 169 } 170 171 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data); 172 173 return 0; 174 } 175 176 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp, 177 const char __user *user_buf, 178 size_t count, loff_t *loff) 179 { 180 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 181 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 182 char buf[32]; 183 size_t buf_size; 184 u32 addr, val, len; 185 int num; 186 187 buf_size = min(count, sizeof(buf) - 1); 188 if (copy_from_user(buf, user_buf, buf_size)) 189 return -EFAULT; 190 191 buf[buf_size] = '\0'; 192 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 193 if (num != 3) { 194 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 195 return -EINVAL; 196 } 197 198 switch (len) { 199 case 1: 200 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 201 rtw89_write8(rtwdev, addr, (u8)val); 202 break; 203 case 2: 204 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 205 rtw89_write16(rtwdev, addr, (u16)val); 206 break; 207 case 4: 208 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 209 rtw89_write32(rtwdev, addr, (u32)val); 210 break; 211 default: 212 rtw89_info(rtwdev, "invalid read write len %d\n", len); 213 break; 214 } 215 216 return count; 217 } 218 219 static ssize_t 220 rtw89_debug_priv_read_rf_select(struct file *filp, 221 const char __user *user_buf, 222 size_t count, loff_t *loff) 223 { 224 struct seq_file *m = (struct seq_file *)filp->private_data; 225 struct rtw89_debugfs_priv *debugfs_priv = m->private; 226 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 227 char buf[32]; 228 size_t buf_size; 229 u32 addr, mask; 230 u8 path; 231 int num; 232 233 buf_size = min(count, sizeof(buf) - 1); 234 if (copy_from_user(buf, user_buf, buf_size)) 235 return -EFAULT; 236 237 buf[buf_size] = '\0'; 238 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 239 if (num != 3) { 240 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 241 return -EINVAL; 242 } 243 244 if (path >= rtwdev->chip->rf_path_num) { 245 rtw89_info(rtwdev, "wrong rf path\n"); 246 return -EINVAL; 247 } 248 debugfs_priv->read_rf.addr = addr; 249 debugfs_priv->read_rf.mask = mask; 250 debugfs_priv->read_rf.path = path; 251 252 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 253 254 return count; 255 } 256 257 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v) 258 { 259 struct rtw89_debugfs_priv *debugfs_priv = m->private; 260 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 261 u32 addr, data, mask; 262 u8 path; 263 264 addr = debugfs_priv->read_rf.addr; 265 mask = debugfs_priv->read_rf.mask; 266 path = debugfs_priv->read_rf.path; 267 268 data = rtw89_read_rf(rtwdev, path, addr, mask); 269 270 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data); 271 272 return 0; 273 } 274 275 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp, 276 const char __user *user_buf, 277 size_t count, loff_t *loff) 278 { 279 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 280 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 281 char buf[32]; 282 size_t buf_size; 283 u32 addr, val, mask; 284 u8 path; 285 int num; 286 287 buf_size = min(count, sizeof(buf) - 1); 288 if (copy_from_user(buf, user_buf, buf_size)) 289 return -EFAULT; 290 291 buf[buf_size] = '\0'; 292 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 293 if (num != 4) { 294 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 295 return -EINVAL; 296 } 297 298 if (path >= rtwdev->chip->rf_path_num) { 299 rtw89_info(rtwdev, "wrong rf path\n"); 300 return -EINVAL; 301 } 302 303 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 304 path, addr, val, mask); 305 rtw89_write_rf(rtwdev, path, addr, mask, val); 306 307 return count; 308 } 309 310 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v) 311 { 312 struct rtw89_debugfs_priv *debugfs_priv = m->private; 313 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 314 const struct rtw89_chip_info *chip = rtwdev->chip; 315 u32 addr, offset, data; 316 u8 path; 317 318 for (path = 0; path < chip->rf_path_num; path++) { 319 seq_printf(m, "RF path %d:\n\n", path); 320 for (addr = 0; addr < 0x100; addr += 4) { 321 seq_printf(m, "0x%08x: ", addr); 322 for (offset = 0; offset < 4; offset++) { 323 data = rtw89_read_rf(rtwdev, path, 324 addr + offset, RFREG_MASK); 325 seq_printf(m, "0x%05x ", data); 326 } 327 seq_puts(m, "\n"); 328 } 329 seq_puts(m, "\n"); 330 } 331 332 return 0; 333 } 334 335 struct txpwr_ent { 336 const char *txt; 337 u8 len; 338 }; 339 340 struct txpwr_map { 341 const struct txpwr_ent *ent; 342 u8 size; 343 u32 addr_from; 344 u32 addr_to; 345 }; 346 347 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 348 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 349 350 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 351 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 352 353 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 354 { .len = 8, .txt = _t "\t- " \ 355 _e0 " " _e1 " " _e2 " " _e3 " " \ 356 _e4 " " _e5 " " _e6 " " _e7 } 357 358 static const struct txpwr_ent __txpwr_ent_byr[] = { 359 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 360 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 361 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 362 /* 1NSS */ 363 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 364 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 365 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 366 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 367 /* 2NSS */ 368 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 369 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 370 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 371 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 372 }; 373 374 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) == 375 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 376 377 static const struct txpwr_map __txpwr_map_byr = { 378 .ent = __txpwr_ent_byr, 379 .size = ARRAY_SIZE(__txpwr_ent_byr), 380 .addr_from = R_AX_PWR_BY_RATE, 381 .addr_to = R_AX_PWR_BY_RATE_MAX, 382 }; 383 384 static const struct txpwr_ent __txpwr_ent_lmt[] = { 385 /* 1TX */ 386 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 387 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 388 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 389 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 390 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 391 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 392 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 393 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 394 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 395 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 396 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 397 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 398 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 399 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 400 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 401 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 402 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 403 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 404 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 405 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 406 /* 2TX */ 407 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 408 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 409 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 410 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 411 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 412 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 413 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 414 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 415 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 416 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 417 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 418 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 419 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 420 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 421 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 422 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 423 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 424 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 425 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 426 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 427 }; 428 429 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) == 430 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 431 432 static const struct txpwr_map __txpwr_map_lmt = { 433 .ent = __txpwr_ent_lmt, 434 .size = ARRAY_SIZE(__txpwr_ent_lmt), 435 .addr_from = R_AX_PWR_LMT, 436 .addr_to = R_AX_PWR_LMT_MAX, 437 }; 438 439 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = { 440 /* 1TX */ 441 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 442 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 443 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 444 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 445 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 446 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 447 /* 2TX */ 448 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 449 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 450 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 451 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 452 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 453 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 454 }; 455 456 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) == 457 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 458 459 static const struct txpwr_map __txpwr_map_lmt_ru = { 460 .ent = __txpwr_ent_lmt_ru, 461 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru), 462 .addr_from = R_AX_PWR_RU_LMT, 463 .addr_to = R_AX_PWR_RU_LMT_MAX, 464 }; 465 466 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent, 467 const u8 *buf, const u8 cur) 468 { 469 char *fmt; 470 471 switch (ent->len) { 472 case 2: 473 fmt = "%s\t| %3d, %3d,\tdBm\n"; 474 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]); 475 return 2; 476 case 4: 477 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 478 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 479 buf[cur + 2], buf[cur + 3]); 480 return 4; 481 case 8: 482 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 483 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1], 484 buf[cur + 2], buf[cur + 3], buf[cur + 4], 485 buf[cur + 5], buf[cur + 6], buf[cur + 7]); 486 return 8; 487 default: 488 return 0; 489 } 490 } 491 492 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev, 493 const struct txpwr_map *map) 494 { 495 u8 fct = rtwdev->chip->txpwr_factor_mac; 496 u8 *buf, cur, i; 497 u32 val, addr; 498 int ret; 499 500 buf = vzalloc(map->addr_to - map->addr_from + 4); 501 if (!buf) 502 return -ENOMEM; 503 504 for (addr = map->addr_from; addr <= map->addr_to; addr += 4) { 505 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 506 if (ret) 507 val = MASKDWORD; 508 509 cur = addr - map->addr_from; 510 for (i = 0; i < 4; i++, val >>= 8) 511 buf[cur + i] = FIELD_GET(MASKBYTE0, val) >> fct; 512 } 513 514 for (cur = 0, i = 0; i < map->size; i++) 515 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur); 516 517 vfree(buf); 518 return 0; 519 } 520 521 #define case_REGD(_regd) \ 522 case RTW89_ ## _regd: \ 523 seq_puts(m, #_regd "\n"); \ 524 break 525 526 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev) 527 { 528 u8 band = rtwdev->hal.current_band_type; 529 u8 regd = rtw89_regd_get(rtwdev, band); 530 531 switch (regd) { 532 default: 533 seq_printf(m, "UNKNOWN: %d\n", regd); 534 break; 535 case_REGD(WW); 536 case_REGD(ETSI); 537 case_REGD(FCC); 538 case_REGD(MKK); 539 case_REGD(NA); 540 case_REGD(IC); 541 case_REGD(KCC); 542 case_REGD(NCC); 543 case_REGD(CHILE); 544 case_REGD(ACMA); 545 case_REGD(MEXICO); 546 case_REGD(UKRAINE); 547 case_REGD(CN); 548 } 549 } 550 551 #undef case_REGD 552 553 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v) 554 { 555 struct rtw89_debugfs_priv *debugfs_priv = m->private; 556 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 557 int ret = 0; 558 559 mutex_lock(&rtwdev->mutex); 560 rtw89_leave_ps_mode(rtwdev); 561 562 seq_puts(m, "[Regulatory] "); 563 __print_regd(m, rtwdev); 564 565 seq_puts(m, "[SAR]\n"); 566 rtw89_print_sar(m, rtwdev); 567 568 seq_puts(m, "\n[TX power byrate]\n"); 569 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr); 570 if (ret) 571 goto err; 572 573 seq_puts(m, "\n[TX power limit]\n"); 574 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt); 575 if (ret) 576 goto err; 577 578 seq_puts(m, "\n[TX power limit_ru]\n"); 579 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru); 580 if (ret) 581 goto err; 582 583 err: 584 mutex_unlock(&rtwdev->mutex); 585 return ret; 586 } 587 588 static ssize_t 589 rtw89_debug_priv_mac_reg_dump_select(struct file *filp, 590 const char __user *user_buf, 591 size_t count, loff_t *loff) 592 { 593 struct seq_file *m = (struct seq_file *)filp->private_data; 594 struct rtw89_debugfs_priv *debugfs_priv = m->private; 595 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 596 char buf[32]; 597 size_t buf_size; 598 int sel; 599 int ret; 600 601 buf_size = min(count, sizeof(buf) - 1); 602 if (copy_from_user(buf, user_buf, buf_size)) 603 return -EFAULT; 604 605 buf[buf_size] = '\0'; 606 ret = kstrtoint(buf, 0, &sel); 607 if (ret) 608 return ret; 609 610 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 611 rtw89_info(rtwdev, "invalid args: %d\n", sel); 612 return -EINVAL; 613 } 614 615 debugfs_priv->cb_data = sel; 616 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 617 618 return count; 619 } 620 621 #define RTW89_MAC_PAGE_SIZE 0x100 622 623 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v) 624 { 625 struct rtw89_debugfs_priv *debugfs_priv = m->private; 626 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 627 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 628 u32 start, end; 629 u32 i, j, k, page; 630 u32 val; 631 632 switch (reg_sel) { 633 case RTW89_DBG_SEL_MAC_00: 634 seq_puts(m, "Debug selected MAC page 0x00\n"); 635 start = 0x000; 636 end = 0x014; 637 break; 638 case RTW89_DBG_SEL_MAC_40: 639 seq_puts(m, "Debug selected MAC page 0x40\n"); 640 start = 0x040; 641 end = 0x07f; 642 break; 643 case RTW89_DBG_SEL_MAC_80: 644 seq_puts(m, "Debug selected MAC page 0x80\n"); 645 start = 0x080; 646 end = 0x09f; 647 break; 648 case RTW89_DBG_SEL_MAC_C0: 649 seq_puts(m, "Debug selected MAC page 0xc0\n"); 650 start = 0x0c0; 651 end = 0x0df; 652 break; 653 case RTW89_DBG_SEL_MAC_E0: 654 seq_puts(m, "Debug selected MAC page 0xe0\n"); 655 start = 0x0e0; 656 end = 0x0ff; 657 break; 658 case RTW89_DBG_SEL_BB: 659 seq_puts(m, "Debug selected BB register\n"); 660 start = 0x100; 661 end = 0x17f; 662 break; 663 case RTW89_DBG_SEL_IQK: 664 seq_puts(m, "Debug selected IQK register\n"); 665 start = 0x180; 666 end = 0x1bf; 667 break; 668 case RTW89_DBG_SEL_RFC: 669 seq_puts(m, "Debug selected RFC register\n"); 670 start = 0x1c0; 671 end = 0x1ff; 672 break; 673 default: 674 seq_puts(m, "Selected invalid register page\n"); 675 return -EINVAL; 676 } 677 678 for (i = start; i <= end; i++) { 679 page = i << 8; 680 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 681 seq_printf(m, "%08xh : ", 0x18600000 + j); 682 for (k = 0; k < 4; k++) { 683 val = rtw89_read32(rtwdev, j + (k << 2)); 684 seq_printf(m, "%08x ", val); 685 } 686 seq_puts(m, "\n"); 687 } 688 } 689 690 return 0; 691 } 692 693 static ssize_t 694 rtw89_debug_priv_mac_mem_dump_select(struct file *filp, 695 const char __user *user_buf, 696 size_t count, loff_t *loff) 697 { 698 struct seq_file *m = (struct seq_file *)filp->private_data; 699 struct rtw89_debugfs_priv *debugfs_priv = m->private; 700 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 701 char buf[32]; 702 size_t buf_size; 703 u32 sel, start_addr, len; 704 int num; 705 706 buf_size = min(count, sizeof(buf) - 1); 707 if (copy_from_user(buf, user_buf, buf_size)) 708 return -EFAULT; 709 710 buf[buf_size] = '\0'; 711 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 712 if (num != 3) { 713 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 714 return -EINVAL; 715 } 716 717 debugfs_priv->mac_mem.sel = sel; 718 debugfs_priv->mac_mem.start = start_addr; 719 debugfs_priv->mac_mem.len = len; 720 721 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 722 sel, start_addr, len); 723 724 return count; 725 } 726 727 static const u32 mac_mem_base_addr_table[RTW89_MAC_MEM_MAX] = { 728 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 729 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 730 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 731 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 732 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 733 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 734 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 735 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 736 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 737 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 738 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 739 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 740 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 741 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 742 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 743 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 744 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 745 }; 746 747 static void rtw89_debug_dump_mac_mem(struct seq_file *m, 748 struct rtw89_dev *rtwdev, 749 u8 sel, u32 start_addr, u32 len) 750 { 751 u32 base_addr, start_page, residue; 752 u32 i, j, p, pages; 753 u32 dump_len, remain; 754 u32 val; 755 756 remain = len; 757 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1; 758 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE; 759 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE; 760 base_addr = mac_mem_base_addr_table[sel]; 761 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE; 762 763 for (p = 0; p < pages; p++) { 764 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE); 765 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, base_addr); 766 for (i = R_AX_INDIR_ACCESS_ENTRY + residue; 767 i < R_AX_INDIR_ACCESS_ENTRY + dump_len;) { 768 seq_printf(m, "%08xh:", i); 769 for (j = 0; 770 j < 4 && i < R_AX_INDIR_ACCESS_ENTRY + dump_len; 771 j++, i += 4) { 772 val = rtw89_read32(rtwdev, i); 773 seq_printf(m, " %08x", val); 774 remain -= 4; 775 } 776 seq_puts(m, "\n"); 777 } 778 base_addr += MAC_MEM_DUMP_PAGE_SIZE; 779 } 780 } 781 782 static int 783 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v) 784 { 785 struct rtw89_debugfs_priv *debugfs_priv = m->private; 786 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 787 788 mutex_lock(&rtwdev->mutex); 789 rtw89_leave_ps_mode(rtwdev); 790 rtw89_debug_dump_mac_mem(m, rtwdev, 791 debugfs_priv->mac_mem.sel, 792 debugfs_priv->mac_mem.start, 793 debugfs_priv->mac_mem.len); 794 mutex_unlock(&rtwdev->mutex); 795 796 return 0; 797 } 798 799 static ssize_t 800 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp, 801 const char __user *user_buf, 802 size_t count, loff_t *loff) 803 { 804 struct seq_file *m = (struct seq_file *)filp->private_data; 805 struct rtw89_debugfs_priv *debugfs_priv = m->private; 806 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 807 char buf[32]; 808 size_t buf_size; 809 int sel, set; 810 int num; 811 bool enable; 812 813 buf_size = min(count, sizeof(buf) - 1); 814 if (copy_from_user(buf, user_buf, buf_size)) 815 return -EFAULT; 816 817 buf[buf_size] = '\0'; 818 num = sscanf(buf, "%d %d", &sel, &set); 819 if (num != 2) { 820 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 821 return -EINVAL; 822 } 823 824 enable = set != 0; 825 switch (sel) { 826 case 0: 827 debugfs_priv->dbgpkg_en.ss_dbg = enable; 828 break; 829 case 1: 830 debugfs_priv->dbgpkg_en.dle_dbg = enable; 831 break; 832 case 2: 833 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 834 break; 835 case 3: 836 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 837 break; 838 case 4: 839 debugfs_priv->dbgpkg_en.dbg_port = enable; 840 break; 841 default: 842 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 843 return -EINVAL; 844 } 845 846 rtw89_info(rtwdev, "%s debug port dump %d\n", 847 enable ? "Enable" : "Disable", sel); 848 849 return count; 850 } 851 852 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 853 struct seq_file *m) 854 { 855 return 0; 856 } 857 858 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 859 struct seq_file *m) 860 { 861 #define DLE_DFI_DUMP(__type, __target, __sel) \ 862 ({ \ 863 u32 __ctrl; \ 864 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 865 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 866 u32 __data, __val32; \ 867 int __ret; \ 868 \ 869 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 870 DLE_DFI_TYPE_##__target) | \ 871 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 872 B_AX_WDE_DFI_ACTIVE; \ 873 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 874 __ret = read_poll_timeout(rtw89_read32, __val32, \ 875 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 876 1000, 50000, false, \ 877 rtwdev, __reg_ctrl); \ 878 if (__ret) { \ 879 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 880 #__type, #__target, __sel); \ 881 return __ret; \ 882 } \ 883 \ 884 __data = rtw89_read32(rtwdev, __reg_data); \ 885 __data; \ 886 }) 887 888 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \ 889 ({ \ 890 u32 __freepg, __pubpg; \ 891 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 892 \ 893 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 894 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 895 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 896 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 897 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 898 seq_printf(__m, "[%s] freepg head: %d\n", \ 899 #__type, __freepg_head); \ 900 seq_printf(__m, "[%s] freepg tail: %d\n", \ 901 #__type, __freepg_tail); \ 902 seq_printf(__m, "[%s] pubpg num : %d\n", \ 903 #__type, __pubpg_num); \ 904 }) 905 906 #define case_QUOTA(__m, __type, __id) \ 907 case __type##_QTAID_##__id: \ 908 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 909 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 910 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 911 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \ 912 #__type, #__id, rsv_pgnum); \ 913 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \ 914 #__type, #__id, use_pgnum); \ 915 break 916 u32 quota_id; 917 u32 val32; 918 u16 rsv_pgnum, use_pgnum; 919 int ret; 920 921 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 922 if (ret) { 923 seq_puts(m, "[DLE] : DMAC not enabled\n"); 924 return ret; 925 } 926 927 DLE_DFI_FREE_PAGE_DUMP(m, WDE); 928 DLE_DFI_FREE_PAGE_DUMP(m, PLE); 929 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 930 switch (quota_id) { 931 case_QUOTA(m, WDE, HOST_IF); 932 case_QUOTA(m, WDE, WLAN_CPU); 933 case_QUOTA(m, WDE, DATA_CPU); 934 case_QUOTA(m, WDE, PKTIN); 935 case_QUOTA(m, WDE, CPUIO); 936 } 937 } 938 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 939 switch (quota_id) { 940 case_QUOTA(m, PLE, B0_TXPL); 941 case_QUOTA(m, PLE, B1_TXPL); 942 case_QUOTA(m, PLE, C2H); 943 case_QUOTA(m, PLE, H2C); 944 case_QUOTA(m, PLE, WLAN_CPU); 945 case_QUOTA(m, PLE, MPDU); 946 case_QUOTA(m, PLE, CMAC0_RX); 947 case_QUOTA(m, PLE, CMAC1_RX); 948 case_QUOTA(m, PLE, CMAC1_BBRPT); 949 case_QUOTA(m, PLE, WDRLS); 950 case_QUOTA(m, PLE, CPUIO); 951 } 952 } 953 954 return 0; 955 956 #undef case_QUOTA 957 #undef DLE_DFI_DUMP 958 #undef DLE_DFI_FREE_PAGE_DUMP 959 } 960 961 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 962 struct seq_file *m) 963 { 964 int ret; 965 966 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 967 if (ret) { 968 seq_puts(m, "[DMAC] : DMAC not enabled\n"); 969 return ret; 970 } 971 972 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", 973 rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR)); 974 seq_printf(m, "[0]R_AX_WDRLS_ERR_ISR=0x%08x\n", 975 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 976 seq_printf(m, "[1]R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 977 rtw89_read32(rtwdev, R_AX_SEC_ERR_IMR_ISR)); 978 seq_printf(m, "[2.1]R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 979 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 980 seq_printf(m, "[2.2]R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 981 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 982 seq_printf(m, "[3]R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 983 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 984 seq_printf(m, "[4]R_AX_WDE_ERR_ISR=0x%08x\n", 985 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 986 seq_printf(m, "[5.1]R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 987 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 988 seq_printf(m, "[5.2]R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 989 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 990 seq_printf(m, "[6]R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 991 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 992 seq_printf(m, "[7]R_AX_PKTIN_ERR_ISR=0x%08x\n", 993 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 994 seq_printf(m, "[8.1]R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 995 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 996 seq_printf(m, "[8.2]R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 997 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 998 seq_printf(m, "[8.3]R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 999 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1000 seq_printf(m, "[10]R_AX_CPUIO_ERR_ISR=0x%08x\n", 1001 rtw89_read32(rtwdev, R_AX_CPUIO_ERR_ISR)); 1002 seq_printf(m, "[11.1]R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1003 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1004 seq_printf(m, "[11.2]R_AX_BBRPT_CHINFO_ERR_IMR_ISR=0x%08x\n", 1005 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR_ISR)); 1006 seq_printf(m, "[11.3]R_AX_BBRPT_DFS_ERR_IMR_ISR=0x%08x\n", 1007 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR_ISR)); 1008 seq_printf(m, "[11.4]R_AX_LA_ERRFLAG=0x%08x\n", 1009 rtw89_read32(rtwdev, R_AX_LA_ERRFLAG)); 1010 1011 return 0; 1012 } 1013 1014 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1015 struct seq_file *m) 1016 { 1017 int ret; 1018 1019 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL); 1020 if (ret) { 1021 seq_puts(m, "[CMAC] : CMAC 0 not enabled\n"); 1022 return ret; 1023 } 1024 1025 seq_printf(m, "R_AX_CMAC_ERR_ISR=0x%08x\n", 1026 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR)); 1027 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR=0x%08x\n", 1028 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR)); 1029 seq_printf(m, "[1]R_AX_PTCL_ISR0=0x%08x\n", 1030 rtw89_read32(rtwdev, R_AX_PTCL_ISR0)); 1031 seq_printf(m, "[3]R_AX_DLE_CTRL=0x%08x\n", 1032 rtw89_read32(rtwdev, R_AX_DLE_CTRL)); 1033 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR=0x%08x\n", 1034 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR)); 1035 seq_printf(m, "[5]R_AX_TXPWR_ISR=0x%08x\n", 1036 rtw89_read32(rtwdev, R_AX_TXPWR_ISR)); 1037 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR=0x%08x\n", 1038 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR)); 1039 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR=0x%08x\n", 1040 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR)); 1041 1042 ret = rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL); 1043 if (ret) { 1044 seq_puts(m, "[CMAC] : CMAC 1 not enabled\n"); 1045 return ret; 1046 } 1047 1048 seq_printf(m, "R_AX_CMAC_ERR_ISR_C1=0x%08x\n", 1049 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR_C1)); 1050 seq_printf(m, "[0]R_AX_SCHEDULE_ERR_ISR_C1=0x%08x\n", 1051 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR_C1)); 1052 seq_printf(m, "[1]R_AX_PTCL_ISR0_C1=0x%08x\n", 1053 rtw89_read32(rtwdev, R_AX_PTCL_ISR0_C1)); 1054 seq_printf(m, "[3]R_AX_DLE_CTRL_C1=0x%08x\n", 1055 rtw89_read32(rtwdev, R_AX_DLE_CTRL_C1)); 1056 seq_printf(m, "[4]R_AX_PHYINFO_ERR_ISR_C1=0x%02x\n", 1057 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR_C1)); 1058 seq_printf(m, "[5]R_AX_TXPWR_ISR_C1=0x%08x\n", 1059 rtw89_read32(rtwdev, R_AX_TXPWR_ISR_C1)); 1060 seq_printf(m, "[6]R_AX_RMAC_ERR_ISR_C1=0x%08x\n", 1061 rtw89_read32(rtwdev, R_AX_RMAC_ERR_ISR_C1)); 1062 seq_printf(m, "[7]R_AX_TMAC_ERR_IMR_ISR_C1=0x%08x\n", 1063 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR_C1)); 1064 1065 return 0; 1066 } 1067 1068 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1069 .sel_addr = R_AX_PTCL_DBG, 1070 .sel_byte = 1, 1071 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1072 .srt = 0x00, 1073 .end = 0x3F, 1074 .rd_addr = R_AX_PTCL_DBG_INFO, 1075 .rd_byte = 4, 1076 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1077 }; 1078 1079 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1080 .sel_addr = R_AX_PTCL_DBG_C1, 1081 .sel_byte = 1, 1082 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1083 .srt = 0x00, 1084 .end = 0x3F, 1085 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1086 .rd_byte = 4, 1087 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1088 }; 1089 1090 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 1091 .sel_addr = R_AX_SCH_DBG_SEL, 1092 .sel_byte = 1, 1093 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1094 .srt = 0x00, 1095 .end = 0x2F, 1096 .rd_addr = R_AX_SCH_DBG, 1097 .rd_byte = 4, 1098 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1099 }; 1100 1101 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 1102 .sel_addr = R_AX_SCH_DBG_SEL_C1, 1103 .sel_byte = 1, 1104 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 1105 .srt = 0x00, 1106 .end = 0x2F, 1107 .rd_addr = R_AX_SCH_DBG_C1, 1108 .rd_byte = 4, 1109 .rd_msk = B_AX_SCHEDULER_DBG_MASK 1110 }; 1111 1112 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 1113 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 1114 .sel_byte = 1, 1115 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1116 .srt = 0x00, 1117 .end = 0x19, 1118 .rd_addr = R_AX_DBG_PORT_SEL, 1119 .rd_byte = 4, 1120 .rd_msk = B_AX_DEBUG_ST_MASK 1121 }; 1122 1123 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 1124 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 1125 .sel_byte = 1, 1126 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 1127 .srt = 0x00, 1128 .end = 0x19, 1129 .rd_addr = R_AX_DBG_PORT_SEL, 1130 .rd_byte = 4, 1131 .rd_msk = B_AX_DEBUG_ST_MASK 1132 }; 1133 1134 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 1135 .sel_addr = R_AX_RX_DEBUG_SELECT, 1136 .sel_byte = 1, 1137 .sel_msk = B_AX_DEBUG_SEL_MASK, 1138 .srt = 0x00, 1139 .end = 0x58, 1140 .rd_addr = R_AX_DBG_PORT_SEL, 1141 .rd_byte = 4, 1142 .rd_msk = B_AX_DEBUG_ST_MASK 1143 }; 1144 1145 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 1146 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 1147 .sel_byte = 1, 1148 .sel_msk = B_AX_DEBUG_SEL_MASK, 1149 .srt = 0x00, 1150 .end = 0x58, 1151 .rd_addr = R_AX_DBG_PORT_SEL, 1152 .rd_byte = 4, 1153 .rd_msk = B_AX_DEBUG_ST_MASK 1154 }; 1155 1156 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 1157 .sel_addr = R_AX_RX_STATE_MONITOR, 1158 .sel_byte = 1, 1159 .sel_msk = B_AX_STATE_SEL_MASK, 1160 .srt = 0x00, 1161 .end = 0x17, 1162 .rd_addr = R_AX_RX_STATE_MONITOR, 1163 .rd_byte = 4, 1164 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1165 }; 1166 1167 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 1168 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 1169 .sel_byte = 1, 1170 .sel_msk = B_AX_STATE_SEL_MASK, 1171 .srt = 0x00, 1172 .end = 0x17, 1173 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 1174 .rd_byte = 4, 1175 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 1176 }; 1177 1178 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 1179 .sel_addr = R_AX_RMAC_PLCP_MON, 1180 .sel_byte = 4, 1181 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1182 .srt = 0x0, 1183 .end = 0xF, 1184 .rd_addr = R_AX_RMAC_PLCP_MON, 1185 .rd_byte = 4, 1186 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1187 }; 1188 1189 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 1190 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 1191 .sel_byte = 4, 1192 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 1193 .srt = 0x0, 1194 .end = 0xF, 1195 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 1196 .rd_byte = 4, 1197 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 1198 }; 1199 1200 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 1201 .sel_addr = R_AX_DBGSEL_TRXPTCL, 1202 .sel_byte = 1, 1203 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1204 .srt = 0x08, 1205 .end = 0x10, 1206 .rd_addr = R_AX_DBG_PORT_SEL, 1207 .rd_byte = 4, 1208 .rd_msk = B_AX_DEBUG_ST_MASK 1209 }; 1210 1211 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 1212 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 1213 .sel_byte = 1, 1214 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 1215 .srt = 0x08, 1216 .end = 0x10, 1217 .rd_addr = R_AX_DBG_PORT_SEL, 1218 .rd_byte = 4, 1219 .rd_msk = B_AX_DEBUG_ST_MASK 1220 }; 1221 1222 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 1223 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1224 .sel_byte = 1, 1225 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1226 .srt = 0x00, 1227 .end = 0x07, 1228 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 1229 .rd_byte = 4, 1230 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1231 }; 1232 1233 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 1234 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 1235 .sel_byte = 1, 1236 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1237 .srt = 0x00, 1238 .end = 0x07, 1239 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 1240 .rd_byte = 4, 1241 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1242 }; 1243 1244 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 1245 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1246 .sel_byte = 1, 1247 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1248 .srt = 0x00, 1249 .end = 0x07, 1250 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 1251 .rd_byte = 4, 1252 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 1253 }; 1254 1255 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 1256 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 1257 .sel_byte = 1, 1258 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 1259 .srt = 0x00, 1260 .end = 0x07, 1261 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 1262 .rd_byte = 4, 1263 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 1264 }; 1265 1266 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 1267 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1268 .sel_byte = 1, 1269 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1270 .srt = 0x00, 1271 .end = 0x04, 1272 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 1273 .rd_byte = 4, 1274 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1275 }; 1276 1277 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 1278 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 1279 .sel_byte = 1, 1280 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1281 .srt = 0x00, 1282 .end = 0x04, 1283 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 1284 .rd_byte = 4, 1285 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1286 }; 1287 1288 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 1289 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1290 .sel_byte = 1, 1291 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1292 .srt = 0x00, 1293 .end = 0x04, 1294 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 1295 .rd_byte = 4, 1296 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 1297 }; 1298 1299 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 1300 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 1301 .sel_byte = 1, 1302 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 1303 .srt = 0x00, 1304 .end = 0x04, 1305 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 1306 .rd_byte = 4, 1307 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 1308 }; 1309 1310 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 1311 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1312 .sel_byte = 4, 1313 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1314 .srt = 0x80000000, 1315 .end = 0x80000001, 1316 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1317 .rd_byte = 4, 1318 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1319 }; 1320 1321 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 1322 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1323 .sel_byte = 4, 1324 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1325 .srt = 0x80010000, 1326 .end = 0x80010004, 1327 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1328 .rd_byte = 4, 1329 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1330 }; 1331 1332 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 1333 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1334 .sel_byte = 4, 1335 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1336 .srt = 0x80020000, 1337 .end = 0x80020FFF, 1338 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1339 .rd_byte = 4, 1340 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1341 }; 1342 1343 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 1344 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1345 .sel_byte = 4, 1346 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1347 .srt = 0x80030000, 1348 .end = 0x80030FFF, 1349 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1350 .rd_byte = 4, 1351 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1352 }; 1353 1354 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 1355 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1356 .sel_byte = 4, 1357 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1358 .srt = 0x80040000, 1359 .end = 0x80040FFF, 1360 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1361 .rd_byte = 4, 1362 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1363 }; 1364 1365 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 1366 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1367 .sel_byte = 4, 1368 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1369 .srt = 0x80050000, 1370 .end = 0x80050FFF, 1371 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1372 .rd_byte = 4, 1373 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1374 }; 1375 1376 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 1377 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1378 .sel_byte = 4, 1379 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1380 .srt = 0x80060000, 1381 .end = 0x80060453, 1382 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1383 .rd_byte = 4, 1384 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1385 }; 1386 1387 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 1388 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 1389 .sel_byte = 4, 1390 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 1391 .srt = 0x80070000, 1392 .end = 0x80070011, 1393 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 1394 .rd_byte = 4, 1395 .rd_msk = B_AX_WDE_DFI_DATA_MASK 1396 }; 1397 1398 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 1399 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1400 .sel_byte = 4, 1401 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1402 .srt = 0x80000000, 1403 .end = 0x80000001, 1404 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1405 .rd_byte = 4, 1406 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1407 }; 1408 1409 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 1410 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1411 .sel_byte = 4, 1412 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1413 .srt = 0x80010000, 1414 .end = 0x8001000A, 1415 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1416 .rd_byte = 4, 1417 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1418 }; 1419 1420 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 1421 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1422 .sel_byte = 4, 1423 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1424 .srt = 0x80020000, 1425 .end = 0x80020DBF, 1426 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1427 .rd_byte = 4, 1428 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1429 }; 1430 1431 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 1432 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1433 .sel_byte = 4, 1434 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1435 .srt = 0x80030000, 1436 .end = 0x80030DBF, 1437 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1438 .rd_byte = 4, 1439 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1440 }; 1441 1442 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 1443 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1444 .sel_byte = 4, 1445 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1446 .srt = 0x80040000, 1447 .end = 0x80040DBF, 1448 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1449 .rd_byte = 4, 1450 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1451 }; 1452 1453 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 1454 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1455 .sel_byte = 4, 1456 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1457 .srt = 0x80050000, 1458 .end = 0x80050DBF, 1459 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1460 .rd_byte = 4, 1461 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1462 }; 1463 1464 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 1465 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1466 .sel_byte = 4, 1467 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1468 .srt = 0x80060000, 1469 .end = 0x80060041, 1470 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1471 .rd_byte = 4, 1472 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1473 }; 1474 1475 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 1476 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 1477 .sel_byte = 4, 1478 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 1479 .srt = 0x80070000, 1480 .end = 0x80070001, 1481 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 1482 .rd_byte = 4, 1483 .rd_msk = B_AX_PLE_DFI_DATA_MASK 1484 }; 1485 1486 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 1487 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 1488 .sel_byte = 4, 1489 .sel_msk = B_AX_DFI_DATA_MASK, 1490 .srt = 0x80000000, 1491 .end = 0x8000017f, 1492 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 1493 .rd_byte = 4, 1494 .rd_msk = B_AX_DFI_DATA_MASK 1495 }; 1496 1497 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 1498 .sel_addr = R_AX_PCIE_DBG_CTRL, 1499 .sel_byte = 2, 1500 .sel_msk = B_AX_DBG_SEL_MASK, 1501 .srt = 0x00, 1502 .end = 0x03, 1503 .rd_addr = R_AX_DBG_PORT_SEL, 1504 .rd_byte = 4, 1505 .rd_msk = B_AX_DEBUG_ST_MASK 1506 }; 1507 1508 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 1509 .sel_addr = R_AX_PCIE_DBG_CTRL, 1510 .sel_byte = 2, 1511 .sel_msk = B_AX_DBG_SEL_MASK, 1512 .srt = 0x00, 1513 .end = 0x04, 1514 .rd_addr = R_AX_DBG_PORT_SEL, 1515 .rd_byte = 4, 1516 .rd_msk = B_AX_DEBUG_ST_MASK 1517 }; 1518 1519 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 1520 .sel_addr = R_AX_PCIE_DBG_CTRL, 1521 .sel_byte = 2, 1522 .sel_msk = B_AX_DBG_SEL_MASK, 1523 .srt = 0x00, 1524 .end = 0x01, 1525 .rd_addr = R_AX_DBG_PORT_SEL, 1526 .rd_byte = 4, 1527 .rd_msk = B_AX_DEBUG_ST_MASK 1528 }; 1529 1530 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 1531 .sel_addr = R_AX_PCIE_DBG_CTRL, 1532 .sel_byte = 2, 1533 .sel_msk = B_AX_DBG_SEL_MASK, 1534 .srt = 0x00, 1535 .end = 0x05, 1536 .rd_addr = R_AX_DBG_PORT_SEL, 1537 .rd_byte = 4, 1538 .rd_msk = B_AX_DEBUG_ST_MASK 1539 }; 1540 1541 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 1542 .sel_addr = R_AX_PCIE_DBG_CTRL, 1543 .sel_byte = 2, 1544 .sel_msk = B_AX_DBG_SEL_MASK, 1545 .srt = 0x00, 1546 .end = 0x05, 1547 .rd_addr = R_AX_DBG_PORT_SEL, 1548 .rd_byte = 4, 1549 .rd_msk = B_AX_DEBUG_ST_MASK 1550 }; 1551 1552 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 1553 .sel_addr = R_AX_PCIE_DBG_CTRL, 1554 .sel_byte = 2, 1555 .sel_msk = B_AX_DBG_SEL_MASK, 1556 .srt = 0x00, 1557 .end = 0x06, 1558 .rd_addr = R_AX_DBG_PORT_SEL, 1559 .rd_byte = 4, 1560 .rd_msk = B_AX_DEBUG_ST_MASK 1561 }; 1562 1563 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 1564 .sel_addr = R_AX_DBG_CTRL, 1565 .sel_byte = 1, 1566 .sel_msk = B_AX_DBG_SEL0, 1567 .srt = 0x34, 1568 .end = 0x3C, 1569 .rd_addr = R_AX_DBG_PORT_SEL, 1570 .rd_byte = 4, 1571 .rd_msk = B_AX_DEBUG_ST_MASK 1572 }; 1573 1574 static const struct rtw89_mac_dbg_port_info * 1575 rtw89_debug_mac_dbg_port_sel(struct seq_file *m, 1576 struct rtw89_dev *rtwdev, u32 sel) 1577 { 1578 const struct rtw89_mac_dbg_port_info *info; 1579 u32 val32; 1580 u16 val16; 1581 u8 val8; 1582 1583 switch (sel) { 1584 case RTW89_DBG_PORT_SEL_PTCL_C0: 1585 info = &dbg_port_ptcl_c0; 1586 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 1587 val16 |= B_AX_PTCL_DBG_EN; 1588 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 1589 seq_puts(m, "Enable PTCL C0 dbgport.\n"); 1590 break; 1591 case RTW89_DBG_PORT_SEL_PTCL_C1: 1592 info = &dbg_port_ptcl_c1; 1593 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 1594 val16 |= B_AX_PTCL_DBG_EN; 1595 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 1596 seq_puts(m, "Enable PTCL C1 dbgport.\n"); 1597 break; 1598 case RTW89_DBG_PORT_SEL_SCH_C0: 1599 info = &dbg_port_sch_c0; 1600 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 1601 val32 |= B_AX_SCH_DBG_EN; 1602 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 1603 seq_puts(m, "Enable SCH C0 dbgport.\n"); 1604 break; 1605 case RTW89_DBG_PORT_SEL_SCH_C1: 1606 info = &dbg_port_sch_c1; 1607 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 1608 val32 |= B_AX_SCH_DBG_EN; 1609 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 1610 seq_puts(m, "Enable SCH C1 dbgport.\n"); 1611 break; 1612 case RTW89_DBG_PORT_SEL_TMAC_C0: 1613 info = &dbg_port_tmac_c0; 1614 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1615 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1616 B_AX_DBGSEL_TRXPTCL_MASK); 1617 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1618 1619 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1620 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1621 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1622 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1623 1624 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1625 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1626 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1627 seq_puts(m, "Enable TMAC C0 dbgport.\n"); 1628 break; 1629 case RTW89_DBG_PORT_SEL_TMAC_C1: 1630 info = &dbg_port_tmac_c1; 1631 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1632 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 1633 B_AX_DBGSEL_TRXPTCL_MASK); 1634 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1635 1636 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1637 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1638 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1639 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1640 1641 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1642 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1643 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1644 seq_puts(m, "Enable TMAC C1 dbgport.\n"); 1645 break; 1646 case RTW89_DBG_PORT_SEL_RMAC_C0: 1647 info = &dbg_port_rmac_c0; 1648 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 1649 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1650 B_AX_DBGSEL_TRXPTCL_MASK); 1651 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 1652 1653 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1654 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 1655 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 1656 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1657 1658 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1659 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1660 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1661 1662 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 1663 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1664 B_AX_DBGSEL_TRXPTCL_MASK); 1665 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 1666 seq_puts(m, "Enable RMAC C0 dbgport.\n"); 1667 break; 1668 case RTW89_DBG_PORT_SEL_RMAC_C1: 1669 info = &dbg_port_rmac_c1; 1670 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1671 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 1672 B_AX_DBGSEL_TRXPTCL_MASK); 1673 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 1674 1675 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1676 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 1677 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 1678 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1679 1680 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1681 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1682 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1683 1684 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 1685 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 1686 B_AX_DBGSEL_TRXPTCL_MASK); 1687 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 1688 seq_puts(m, "Enable RMAC C1 dbgport.\n"); 1689 break; 1690 case RTW89_DBG_PORT_SEL_RMACST_C0: 1691 info = &dbg_port_rmacst_c0; 1692 seq_puts(m, "Enable RMAC state C0 dbgport.\n"); 1693 break; 1694 case RTW89_DBG_PORT_SEL_RMACST_C1: 1695 info = &dbg_port_rmacst_c1; 1696 seq_puts(m, "Enable RMAC state C1 dbgport.\n"); 1697 break; 1698 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 1699 info = &dbg_port_rmac_plcp_c0; 1700 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n"); 1701 break; 1702 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 1703 info = &dbg_port_rmac_plcp_c1; 1704 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n"); 1705 break; 1706 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 1707 info = &dbg_port_trxptcl_c0; 1708 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1709 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 1710 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 1711 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1712 1713 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1714 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1715 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1716 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n"); 1717 break; 1718 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 1719 info = &dbg_port_trxptcl_c1; 1720 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1721 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 1722 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 1723 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1724 1725 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 1726 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 1727 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 1728 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n"); 1729 break; 1730 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 1731 info = &dbg_port_tx_infol_c0; 1732 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1733 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1734 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1735 seq_puts(m, "Enable tx infol dump.\n"); 1736 break; 1737 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 1738 info = &dbg_port_tx_infoh_c0; 1739 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1740 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1741 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1742 seq_puts(m, "Enable tx infoh dump.\n"); 1743 break; 1744 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 1745 info = &dbg_port_tx_infol_c1; 1746 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1747 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1748 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1749 seq_puts(m, "Enable tx infol dump.\n"); 1750 break; 1751 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 1752 info = &dbg_port_tx_infoh_c1; 1753 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1754 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1755 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1756 seq_puts(m, "Enable tx infoh dump.\n"); 1757 break; 1758 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 1759 info = &dbg_port_txtf_infol_c0; 1760 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1761 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1762 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1763 seq_puts(m, "Enable tx tf infol dump.\n"); 1764 break; 1765 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 1766 info = &dbg_port_txtf_infoh_c0; 1767 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 1768 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1769 rtw89_write32(rtwdev, R_AX_TCR1, val32); 1770 seq_puts(m, "Enable tx tf infoh dump.\n"); 1771 break; 1772 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 1773 info = &dbg_port_txtf_infol_c1; 1774 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1775 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1776 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1777 seq_puts(m, "Enable tx tf infol dump.\n"); 1778 break; 1779 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 1780 info = &dbg_port_txtf_infoh_c1; 1781 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 1782 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 1783 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 1784 seq_puts(m, "Enable tx tf infoh dump.\n"); 1785 break; 1786 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 1787 info = &dbg_port_wde_bufmgn_freepg; 1788 seq_puts(m, "Enable wde bufmgn freepg dump.\n"); 1789 break; 1790 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 1791 info = &dbg_port_wde_bufmgn_quota; 1792 seq_puts(m, "Enable wde bufmgn quota dump.\n"); 1793 break; 1794 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 1795 info = &dbg_port_wde_bufmgn_pagellt; 1796 seq_puts(m, "Enable wde bufmgn pagellt dump.\n"); 1797 break; 1798 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 1799 info = &dbg_port_wde_bufmgn_pktinfo; 1800 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n"); 1801 break; 1802 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 1803 info = &dbg_port_wde_quemgn_prepkt; 1804 seq_puts(m, "Enable wde quemgn prepkt dump.\n"); 1805 break; 1806 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 1807 info = &dbg_port_wde_quemgn_nxtpkt; 1808 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n"); 1809 break; 1810 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 1811 info = &dbg_port_wde_quemgn_qlnktbl; 1812 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n"); 1813 break; 1814 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 1815 info = &dbg_port_wde_quemgn_qempty; 1816 seq_puts(m, "Enable wde quemgn qempty dump.\n"); 1817 break; 1818 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 1819 info = &dbg_port_ple_bufmgn_freepg; 1820 seq_puts(m, "Enable ple bufmgn freepg dump.\n"); 1821 break; 1822 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 1823 info = &dbg_port_ple_bufmgn_quota; 1824 seq_puts(m, "Enable ple bufmgn quota dump.\n"); 1825 break; 1826 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 1827 info = &dbg_port_ple_bufmgn_pagellt; 1828 seq_puts(m, "Enable ple bufmgn pagellt dump.\n"); 1829 break; 1830 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 1831 info = &dbg_port_ple_bufmgn_pktinfo; 1832 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n"); 1833 break; 1834 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 1835 info = &dbg_port_ple_quemgn_prepkt; 1836 seq_puts(m, "Enable ple quemgn prepkt dump.\n"); 1837 break; 1838 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 1839 info = &dbg_port_ple_quemgn_nxtpkt; 1840 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n"); 1841 break; 1842 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 1843 info = &dbg_port_ple_quemgn_qlnktbl; 1844 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n"); 1845 break; 1846 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 1847 info = &dbg_port_ple_quemgn_qempty; 1848 seq_puts(m, "Enable ple quemgn qempty dump.\n"); 1849 break; 1850 case RTW89_DBG_PORT_SEL_PKTINFO: 1851 info = &dbg_port_pktinfo; 1852 seq_puts(m, "Enable pktinfo dump.\n"); 1853 break; 1854 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 1855 info = &dbg_port_pcie_txdma; 1856 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1857 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 1858 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 1859 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1860 seq_puts(m, "Enable pcie txdma dump.\n"); 1861 break; 1862 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 1863 info = &dbg_port_pcie_rxdma; 1864 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1865 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 1866 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 1867 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1868 seq_puts(m, "Enable pcie rxdma dump.\n"); 1869 break; 1870 case RTW89_DBG_PORT_SEL_PCIE_CVT: 1871 info = &dbg_port_pcie_cvt; 1872 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1873 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 1874 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 1875 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1876 seq_puts(m, "Enable pcie cvt dump.\n"); 1877 break; 1878 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 1879 info = &dbg_port_pcie_cxpl; 1880 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1881 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 1882 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 1883 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1884 seq_puts(m, "Enable pcie cxpl dump.\n"); 1885 break; 1886 case RTW89_DBG_PORT_SEL_PCIE_IO: 1887 info = &dbg_port_pcie_io; 1888 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1889 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 1890 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 1891 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1892 seq_puts(m, "Enable pcie io dump.\n"); 1893 break; 1894 case RTW89_DBG_PORT_SEL_PCIE_MISC: 1895 info = &dbg_port_pcie_misc; 1896 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 1897 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 1898 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 1899 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 1900 seq_puts(m, "Enable pcie misc dump.\n"); 1901 break; 1902 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 1903 info = &dbg_port_pcie_misc2; 1904 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 1905 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 1906 B_AX_DBG_SEL_MASK); 1907 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 1908 seq_puts(m, "Enable pcie misc2 dump.\n"); 1909 break; 1910 default: 1911 seq_puts(m, "Dbg port select err\n"); 1912 return NULL; 1913 } 1914 1915 return info; 1916 } 1917 1918 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 1919 { 1920 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 1921 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 1922 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 1923 return false; 1924 if (rtwdev->chip->chip_id == RTL8852B && 1925 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1926 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1927 return false; 1928 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 1929 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 1930 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 1931 return false; 1932 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 1933 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 1934 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 1935 return false; 1936 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 1937 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 1938 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 1939 return false; 1940 1941 return true; 1942 } 1943 1944 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 1945 struct seq_file *m, u32 sel) 1946 { 1947 const struct rtw89_mac_dbg_port_info *info; 1948 u8 val8; 1949 u16 val16; 1950 u32 val32; 1951 u32 i; 1952 1953 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel); 1954 if (!info) { 1955 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 1956 return -EINVAL; 1957 } 1958 1959 #define case_DBG_SEL(__sel) \ 1960 case RTW89_DBG_PORT_SEL_##__sel: \ 1961 seq_puts(m, "Dump debug port " #__sel ":\n"); \ 1962 break 1963 1964 switch (sel) { 1965 case_DBG_SEL(PTCL_C0); 1966 case_DBG_SEL(PTCL_C1); 1967 case_DBG_SEL(SCH_C0); 1968 case_DBG_SEL(SCH_C1); 1969 case_DBG_SEL(TMAC_C0); 1970 case_DBG_SEL(TMAC_C1); 1971 case_DBG_SEL(RMAC_C0); 1972 case_DBG_SEL(RMAC_C1); 1973 case_DBG_SEL(RMACST_C0); 1974 case_DBG_SEL(RMACST_C1); 1975 case_DBG_SEL(TRXPTCL_C0); 1976 case_DBG_SEL(TRXPTCL_C1); 1977 case_DBG_SEL(TX_INFOL_C0); 1978 case_DBG_SEL(TX_INFOH_C0); 1979 case_DBG_SEL(TX_INFOL_C1); 1980 case_DBG_SEL(TX_INFOH_C1); 1981 case_DBG_SEL(TXTF_INFOL_C0); 1982 case_DBG_SEL(TXTF_INFOH_C0); 1983 case_DBG_SEL(TXTF_INFOL_C1); 1984 case_DBG_SEL(TXTF_INFOH_C1); 1985 case_DBG_SEL(WDE_BUFMGN_FREEPG); 1986 case_DBG_SEL(WDE_BUFMGN_QUOTA); 1987 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 1988 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 1989 case_DBG_SEL(WDE_QUEMGN_PREPKT); 1990 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 1991 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 1992 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 1993 case_DBG_SEL(PLE_BUFMGN_FREEPG); 1994 case_DBG_SEL(PLE_BUFMGN_QUOTA); 1995 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 1996 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 1997 case_DBG_SEL(PLE_QUEMGN_PREPKT); 1998 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 1999 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 2000 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 2001 case_DBG_SEL(PKTINFO); 2002 case_DBG_SEL(PCIE_TXDMA); 2003 case_DBG_SEL(PCIE_RXDMA); 2004 case_DBG_SEL(PCIE_CVT); 2005 case_DBG_SEL(PCIE_CXPL); 2006 case_DBG_SEL(PCIE_IO); 2007 case_DBG_SEL(PCIE_MISC); 2008 case_DBG_SEL(PCIE_MISC2); 2009 } 2010 2011 #undef case_DBG_SEL 2012 2013 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr); 2014 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr); 2015 2016 for (i = info->srt; i <= info->end; i++) { 2017 switch (info->sel_byte) { 2018 case 1: 2019 default: 2020 rtw89_write8_mask(rtwdev, info->sel_addr, 2021 info->sel_msk, i); 2022 seq_printf(m, "0x%02X: ", i); 2023 break; 2024 case 2: 2025 rtw89_write16_mask(rtwdev, info->sel_addr, 2026 info->sel_msk, i); 2027 seq_printf(m, "0x%04X: ", i); 2028 break; 2029 case 4: 2030 rtw89_write32_mask(rtwdev, info->sel_addr, 2031 info->sel_msk, i); 2032 seq_printf(m, "0x%04X: ", i); 2033 break; 2034 } 2035 2036 udelay(10); 2037 2038 switch (info->rd_byte) { 2039 case 1: 2040 default: 2041 val8 = rtw89_read8_mask(rtwdev, 2042 info->rd_addr, info->rd_msk); 2043 seq_printf(m, "0x%02X\n", val8); 2044 break; 2045 case 2: 2046 val16 = rtw89_read16_mask(rtwdev, 2047 info->rd_addr, info->rd_msk); 2048 seq_printf(m, "0x%04X\n", val16); 2049 break; 2050 case 4: 2051 val32 = rtw89_read32_mask(rtwdev, 2052 info->rd_addr, info->rd_msk); 2053 seq_printf(m, "0x%08X\n", val32); 2054 break; 2055 } 2056 } 2057 2058 return 0; 2059 } 2060 2061 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 2062 struct seq_file *m) 2063 { 2064 u32 sel; 2065 int ret = 0; 2066 2067 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 2068 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 2069 if (!is_dbg_port_valid(rtwdev, sel)) 2070 continue; 2071 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel); 2072 if (ret) { 2073 rtw89_err(rtwdev, 2074 "failed to dump debug port %d\n", sel); 2075 break; 2076 } 2077 } 2078 2079 return ret; 2080 } 2081 2082 static int 2083 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v) 2084 { 2085 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2086 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2087 2088 if (debugfs_priv->dbgpkg_en.ss_dbg) 2089 rtw89_debug_mac_dump_ss_dbg(rtwdev, m); 2090 if (debugfs_priv->dbgpkg_en.dle_dbg) 2091 rtw89_debug_mac_dump_dle_dbg(rtwdev, m); 2092 if (debugfs_priv->dbgpkg_en.dmac_dbg) 2093 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m); 2094 if (debugfs_priv->dbgpkg_en.cmac_dbg) 2095 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m); 2096 if (debugfs_priv->dbgpkg_en.dbg_port) 2097 rtw89_debug_mac_dump_dbg_port(rtwdev, m); 2098 2099 return 0; 2100 }; 2101 2102 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev, 2103 const char __user *user_buf, size_t count) 2104 { 2105 char *buf; 2106 u8 *bin; 2107 int num; 2108 int err = 0; 2109 2110 buf = memdup_user(user_buf, count); 2111 if (IS_ERR(buf)) 2112 return buf; 2113 2114 num = count / 2; 2115 bin = kmalloc(num, GFP_KERNEL); 2116 if (!bin) { 2117 err = -EFAULT; 2118 goto out; 2119 } 2120 2121 if (hex2bin(bin, buf, num)) { 2122 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 2123 kfree(bin); 2124 err = -EINVAL; 2125 } 2126 2127 out: 2128 kfree(buf); 2129 2130 return err ? ERR_PTR(err) : bin; 2131 } 2132 2133 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp, 2134 const char __user *user_buf, 2135 size_t count, loff_t *loff) 2136 { 2137 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2138 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2139 u8 *h2c; 2140 u16 h2c_len = count / 2; 2141 2142 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2143 if (IS_ERR(h2c)) 2144 return -EFAULT; 2145 2146 rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 2147 2148 kfree(h2c); 2149 2150 return count; 2151 } 2152 2153 static int 2154 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v) 2155 { 2156 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2157 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2158 struct rtw89_early_h2c *early_h2c; 2159 int seq = 0; 2160 2161 mutex_lock(&rtwdev->mutex); 2162 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 2163 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c); 2164 mutex_unlock(&rtwdev->mutex); 2165 2166 return 0; 2167 } 2168 2169 static ssize_t 2170 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf, 2171 size_t count, loff_t *loff) 2172 { 2173 struct seq_file *m = (struct seq_file *)filp->private_data; 2174 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2175 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2176 struct rtw89_early_h2c *early_h2c; 2177 u8 *h2c; 2178 u16 h2c_len = count / 2; 2179 2180 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count); 2181 if (IS_ERR(h2c)) 2182 return -EFAULT; 2183 2184 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 2185 kfree(h2c); 2186 rtw89_fw_free_all_early_h2c(rtwdev); 2187 goto out; 2188 } 2189 2190 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 2191 if (!early_h2c) { 2192 kfree(h2c); 2193 return -EFAULT; 2194 } 2195 2196 early_h2c->h2c = h2c; 2197 early_h2c->h2c_len = h2c_len; 2198 2199 mutex_lock(&rtwdev->mutex); 2200 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 2201 mutex_unlock(&rtwdev->mutex); 2202 2203 out: 2204 return count; 2205 } 2206 2207 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v) 2208 { 2209 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2210 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2211 2212 rtw89_btc_dump_info(rtwdev, m); 2213 2214 return 0; 2215 } 2216 2217 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp, 2218 const char __user *user_buf, 2219 size_t count, loff_t *loff) 2220 { 2221 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2222 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2223 struct rtw89_btc *btc = &rtwdev->btc; 2224 bool btc_manual; 2225 2226 if (kstrtobool_from_user(user_buf, count, &btc_manual)) 2227 goto out; 2228 2229 btc->ctrl.manual = btc_manual; 2230 out: 2231 return count; 2232 } 2233 2234 static ssize_t rtw89_debug_fw_log_btc_manual_set(struct file *filp, 2235 const char __user *user_buf, 2236 size_t count, loff_t *loff) 2237 { 2238 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data; 2239 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2240 struct rtw89_fw_info *fw_info = &rtwdev->fw; 2241 bool fw_log_manual; 2242 2243 if (kstrtobool_from_user(user_buf, count, &fw_log_manual)) 2244 goto out; 2245 2246 mutex_lock(&rtwdev->mutex); 2247 fw_info->fw_log_enable = fw_log_manual; 2248 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 2249 mutex_unlock(&rtwdev->mutex); 2250 out: 2251 return count; 2252 } 2253 2254 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 2255 { 2256 static const char * const he_gi_str[] = { 2257 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 2258 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 2259 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 2260 }; 2261 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2262 struct rate_info *rate = &rtwsta->ra_report.txrate; 2263 struct ieee80211_rx_status *status = &rtwsta->rx_status; 2264 struct seq_file *m = (struct seq_file *)data; 2265 u8 rssi; 2266 2267 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id); 2268 2269 if (rate->flags & RATE_INFO_FLAGS_MCS) 2270 seq_printf(m, "HT MCS-%d%s", rate->mcs, 2271 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2272 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 2273 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs, 2274 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 2275 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 2276 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs, 2277 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2278 he_gi_str[rate->he_gi] : "N/A"); 2279 else 2280 seq_printf(m, "Legacy %d", rate->legacy); 2281 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate); 2282 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait, 2283 sta->max_rc_amsdu_len); 2284 2285 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id); 2286 2287 switch (status->encoding) { 2288 case RX_ENC_LEGACY: 2289 seq_printf(m, "Legacy %d", status->rate_idx + 2290 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 2291 break; 2292 case RX_ENC_HT: 2293 seq_printf(m, "HT MCS-%d%s", status->rate_idx, 2294 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2295 break; 2296 case RX_ENC_VHT: 2297 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx, 2298 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 2299 break; 2300 case RX_ENC_HE: 2301 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx, 2302 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 2303 he_gi_str[rate->he_gi] : "N/A"); 2304 break; 2305 } 2306 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate); 2307 2308 rssi = ewma_rssi_read(&rtwsta->avg_rssi); 2309 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d)\n", 2310 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi); 2311 } 2312 2313 static void 2314 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat, 2315 enum rtw89_hw_rate first_rate, int len) 2316 { 2317 int i; 2318 2319 for (i = 0; i < len; i++) 2320 seq_printf(m, "%s%u", i == 0 ? "" : ", ", 2321 pkt_stat->rx_rate_cnt[first_rate + i]); 2322 } 2323 2324 static const struct rtw89_rx_rate_cnt_info { 2325 enum rtw89_hw_rate first_rate; 2326 int len; 2327 int ext; 2328 const char *rate_mode; 2329 } rtw89_rx_rate_cnt_infos[] = { 2330 {RTW89_HW_RATE_CCK1, 4, 0, "Legacy:"}, 2331 {RTW89_HW_RATE_OFDM6, 8, 0, "OFDM:"}, 2332 {RTW89_HW_RATE_MCS0, 8, 0, "HT 0:"}, 2333 {RTW89_HW_RATE_MCS8, 8, 0, "HT 1:"}, 2334 {RTW89_HW_RATE_VHT_NSS1_MCS0, 10, 2, "VHT 1SS:"}, 2335 {RTW89_HW_RATE_VHT_NSS2_MCS0, 10, 2, "VHT 2SS:"}, 2336 {RTW89_HW_RATE_HE_NSS1_MCS0, 12, 0, "HE 1SS:"}, 2337 {RTW89_HW_RATE_HE_NSS2_MCS0, 12, 0, "HE 2ss:"}, 2338 }; 2339 2340 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v) 2341 { 2342 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2343 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2344 struct rtw89_traffic_stats *stats = &rtwdev->stats; 2345 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 2346 const struct rtw89_rx_rate_cnt_info *info; 2347 int i; 2348 2349 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n", 2350 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv, 2351 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv); 2352 seq_printf(m, "Beacon: %u\n", pkt_stat->beacon_nr); 2353 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len, 2354 stats->rx_avg_len); 2355 2356 seq_puts(m, "RX count:\n"); 2357 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 2358 info = &rtw89_rx_rate_cnt_infos[i]; 2359 seq_printf(m, "%10s [", info->rate_mode); 2360 rtw89_debug_append_rx_rate(m, pkt_stat, 2361 info->first_rate, info->len); 2362 if (info->ext) { 2363 seq_puts(m, "]["); 2364 rtw89_debug_append_rx_rate(m, pkt_stat, 2365 info->first_rate + info->len, info->ext); 2366 } 2367 seq_puts(m, "]\n"); 2368 } 2369 2370 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m); 2371 2372 return 0; 2373 } 2374 2375 static void rtw89_dump_addr_cam(struct seq_file *m, 2376 struct rtw89_addr_cam_entry *addr_cam) 2377 { 2378 struct rtw89_sec_cam_entry *sec_entry; 2379 int i; 2380 2381 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx); 2382 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx); 2383 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map), 2384 addr_cam->sec_cam_map); 2385 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) { 2386 sec_entry = addr_cam->sec_entries[i]; 2387 if (!sec_entry) 2388 continue; 2389 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx); 2390 if (sec_entry->ext_key) 2391 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1); 2392 seq_puts(m, "\n"); 2393 } 2394 } 2395 2396 static 2397 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 2398 { 2399 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2400 struct seq_file *m = (struct seq_file *)data; 2401 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam; 2402 2403 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr); 2404 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx); 2405 rtw89_dump_addr_cam(m, &rtwvif->addr_cam); 2406 } 2407 2408 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 2409 { 2410 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2411 struct seq_file *m = (struct seq_file *)data; 2412 2413 seq_printf(m, "STA [%d] %pM\n", rtwsta->mac_id, sta->addr); 2414 rtw89_dump_addr_cam(m, &rtwsta->addr_cam); 2415 } 2416 2417 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v) 2418 { 2419 struct rtw89_debugfs_priv *debugfs_priv = m->private; 2420 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 2421 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2422 2423 seq_puts(m, "map:\n"); 2424 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map), 2425 rtwdev->mac_id_map); 2426 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map), 2427 cam_info->addr_cam_map); 2428 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map), 2429 cam_info->bssid_cam_map); 2430 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map), 2431 cam_info->sec_cam_map); 2432 2433 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 2434 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m); 2435 2436 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m); 2437 2438 return 0; 2439 } 2440 2441 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = { 2442 .cb_read = rtw89_debug_priv_read_reg_get, 2443 .cb_write = rtw89_debug_priv_read_reg_select, 2444 }; 2445 2446 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = { 2447 .cb_write = rtw89_debug_priv_write_reg_set, 2448 }; 2449 2450 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = { 2451 .cb_read = rtw89_debug_priv_read_rf_get, 2452 .cb_write = rtw89_debug_priv_read_rf_select, 2453 }; 2454 2455 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = { 2456 .cb_write = rtw89_debug_priv_write_rf_set, 2457 }; 2458 2459 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = { 2460 .cb_read = rtw89_debug_priv_rf_reg_dump_get, 2461 }; 2462 2463 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = { 2464 .cb_read = rtw89_debug_priv_txpwr_table_get, 2465 }; 2466 2467 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = { 2468 .cb_read = rtw89_debug_priv_mac_reg_dump_get, 2469 .cb_write = rtw89_debug_priv_mac_reg_dump_select, 2470 }; 2471 2472 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = { 2473 .cb_read = rtw89_debug_priv_mac_mem_dump_get, 2474 .cb_write = rtw89_debug_priv_mac_mem_dump_select, 2475 }; 2476 2477 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = { 2478 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get, 2479 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select, 2480 }; 2481 2482 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = { 2483 .cb_write = rtw89_debug_priv_send_h2c_set, 2484 }; 2485 2486 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = { 2487 .cb_read = rtw89_debug_priv_early_h2c_get, 2488 .cb_write = rtw89_debug_priv_early_h2c_set, 2489 }; 2490 2491 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = { 2492 .cb_read = rtw89_debug_priv_btc_info_get, 2493 }; 2494 2495 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = { 2496 .cb_write = rtw89_debug_priv_btc_manual_set, 2497 }; 2498 2499 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = { 2500 .cb_write = rtw89_debug_fw_log_btc_manual_set, 2501 }; 2502 2503 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = { 2504 .cb_read = rtw89_debug_priv_phy_info_get, 2505 }; 2506 2507 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = { 2508 .cb_read = rtw89_debug_priv_stations_get, 2509 }; 2510 2511 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 2512 do { \ 2513 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \ 2514 if (!debugfs_create_file(#name, mode, \ 2515 parent, &rtw89_debug_priv_ ##name, \ 2516 &file_ops_ ##fopname)) \ 2517 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 2518 } while (0) 2519 2520 #define rtw89_debugfs_add_w(name) \ 2521 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 2522 #define rtw89_debugfs_add_rw(name) \ 2523 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 2524 #define rtw89_debugfs_add_r(name) \ 2525 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 2526 2527 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 2528 { 2529 struct dentry *debugfs_topdir; 2530 2531 debugfs_topdir = debugfs_create_dir("rtw89", 2532 rtwdev->hw->wiphy->debugfsdir); 2533 2534 rtw89_debugfs_add_rw(read_reg); 2535 rtw89_debugfs_add_w(write_reg); 2536 rtw89_debugfs_add_rw(read_rf); 2537 rtw89_debugfs_add_w(write_rf); 2538 rtw89_debugfs_add_r(rf_reg_dump); 2539 rtw89_debugfs_add_r(txpwr_table); 2540 rtw89_debugfs_add_rw(mac_reg_dump); 2541 rtw89_debugfs_add_rw(mac_mem_dump); 2542 rtw89_debugfs_add_rw(mac_dbg_port_dump); 2543 rtw89_debugfs_add_w(send_h2c); 2544 rtw89_debugfs_add_rw(early_h2c); 2545 rtw89_debugfs_add_r(btc_info); 2546 rtw89_debugfs_add_w(btc_manual); 2547 rtw89_debugfs_add_w(fw_log_manual); 2548 rtw89_debugfs_add_r(phy_info); 2549 rtw89_debugfs_add_r(stations); 2550 } 2551 #endif 2552 2553 #ifdef CONFIG_RTW89_DEBUGMSG 2554 void __rtw89_debug(struct rtw89_dev *rtwdev, 2555 enum rtw89_debug_mask mask, 2556 const char *fmt, ...) 2557 { 2558 struct va_format vaf = { 2559 .fmt = fmt, 2560 }; 2561 2562 va_list args; 2563 2564 va_start(args, fmt); 2565 vaf.va = &args; 2566 2567 if (rtw89_debug_mask & mask) 2568 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 2569 2570 va_end(args); 2571 } 2572 EXPORT_SYMBOL(__rtw89_debug); 2573 #endif 2574