1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include <linux/vmalloc.h> 6 7 #include "coex.h" 8 #include "debug.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "phy.h" 13 #include "ps.h" 14 #include "reg.h" 15 #include "sar.h" 16 #include "util.h" 17 18 #ifdef CONFIG_RTW89_DEBUGMSG 19 unsigned int rtw89_debug_mask; 20 EXPORT_SYMBOL(rtw89_debug_mask); 21 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644); 22 MODULE_PARM_DESC(debug_mask, "Debugging mask"); 23 #endif 24 25 #ifdef CONFIG_RTW89_DEBUGFS 26 struct rtw89_debugfs_priv_opt { 27 bool rlock:1; 28 bool wlock:1; 29 size_t rsize; 30 }; 31 32 struct rtw89_debugfs_priv { 33 struct rtw89_dev *rtwdev; 34 ssize_t (*cb_read)(struct rtw89_dev *rtwdev, 35 struct rtw89_debugfs_priv *debugfs_priv, 36 char *buf, size_t bufsz); 37 ssize_t (*cb_write)(struct rtw89_dev *rtwdev, 38 struct rtw89_debugfs_priv *debugfs_priv, 39 const char *buf, size_t count); 40 struct rtw89_debugfs_priv_opt opt; 41 union { 42 u32 cb_data; 43 struct { 44 u32 addr; 45 u32 len; 46 } read_reg; 47 struct { 48 u32 addr; 49 u32 mask; 50 u8 path; 51 } read_rf; 52 struct { 53 u8 ss_dbg:1; 54 u8 dle_dbg:1; 55 u8 dmac_dbg:1; 56 u8 cmac_dbg:1; 57 u8 dbg_port:1; 58 } dbgpkg_en; 59 struct { 60 u32 start; 61 u32 len; 62 u8 sel; 63 } mac_mem; 64 }; 65 ssize_t rused; 66 char *rbuf; 67 }; 68 69 struct rtw89_debugfs { 70 struct rtw89_debugfs_priv read_reg; 71 struct rtw89_debugfs_priv write_reg; 72 struct rtw89_debugfs_priv read_rf; 73 struct rtw89_debugfs_priv write_rf; 74 struct rtw89_debugfs_priv rf_reg_dump; 75 struct rtw89_debugfs_priv txpwr_table; 76 struct rtw89_debugfs_priv mac_reg_dump; 77 struct rtw89_debugfs_priv mac_mem_dump; 78 struct rtw89_debugfs_priv mac_dbg_port_dump; 79 struct rtw89_debugfs_priv send_h2c; 80 struct rtw89_debugfs_priv early_h2c; 81 struct rtw89_debugfs_priv fw_crash; 82 struct rtw89_debugfs_priv btc_info; 83 struct rtw89_debugfs_priv btc_manual; 84 struct rtw89_debugfs_priv fw_log_manual; 85 struct rtw89_debugfs_priv phy_info; 86 struct rtw89_debugfs_priv stations; 87 struct rtw89_debugfs_priv disable_dm; 88 struct rtw89_debugfs_priv mlo_mode; 89 struct rtw89_debugfs_priv beacon_info; 90 }; 91 92 struct rtw89_debugfs_iter_data { 93 char *buf; 94 size_t bufsz; 95 int written_sz; 96 }; 97 98 static void rtw89_debugfs_iter_data_setup(struct rtw89_debugfs_iter_data *iter_data, 99 char *buf, size_t bufsz) 100 { 101 iter_data->buf = buf; 102 iter_data->bufsz = bufsz; 103 iter_data->written_sz = 0; 104 } 105 106 static void rtw89_debugfs_iter_data_next(struct rtw89_debugfs_iter_data *iter_data, 107 char *buf, size_t bufsz, int written_sz) 108 { 109 iter_data->buf = buf; 110 iter_data->bufsz = bufsz; 111 iter_data->written_sz += written_sz; 112 } 113 114 static const u16 rtw89_rate_info_bw_to_mhz_map[] = { 115 [RATE_INFO_BW_20] = 20, 116 [RATE_INFO_BW_40] = 40, 117 [RATE_INFO_BW_80] = 80, 118 [RATE_INFO_BW_160] = 160, 119 [RATE_INFO_BW_320] = 320, 120 }; 121 122 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw) 123 { 124 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map)) 125 return rtw89_rate_info_bw_to_mhz_map[bw]; 126 127 return 0; 128 } 129 130 static ssize_t rtw89_debugfs_file_read_helper(struct wiphy *wiphy, struct file *file, 131 char *buf, size_t bufsz, void *data) 132 { 133 struct rtw89_debugfs_priv *debugfs_priv = data; 134 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 135 ssize_t n; 136 137 n = debugfs_priv->cb_read(rtwdev, debugfs_priv, buf, bufsz); 138 rtw89_might_trailing_ellipsis(buf, bufsz, n); 139 140 return n; 141 } 142 143 static ssize_t rtw89_debugfs_file_read(struct file *file, char __user *userbuf, 144 size_t count, loff_t *ppos) 145 { 146 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 147 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 148 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 149 size_t bufsz = opt->rsize ? opt->rsize : PAGE_SIZE; 150 char *buf; 151 ssize_t n; 152 153 if (!debugfs_priv->rbuf) 154 debugfs_priv->rbuf = devm_kzalloc(rtwdev->dev, bufsz, GFP_KERNEL); 155 156 buf = debugfs_priv->rbuf; 157 if (!buf) 158 return -ENOMEM; 159 160 if (*ppos) { 161 n = debugfs_priv->rused; 162 goto out; 163 } 164 165 if (opt->rlock) { 166 n = wiphy_locked_debugfs_read(rtwdev->hw->wiphy, file, buf, bufsz, 167 userbuf, count, ppos, 168 rtw89_debugfs_file_read_helper, 169 debugfs_priv); 170 debugfs_priv->rused = n; 171 172 return n; 173 } 174 175 n = rtw89_debugfs_file_read_helper(rtwdev->hw->wiphy, file, buf, bufsz, 176 debugfs_priv); 177 debugfs_priv->rused = n; 178 179 out: 180 return simple_read_from_buffer(userbuf, count, ppos, buf, n); 181 } 182 183 static ssize_t rtw89_debugfs_file_write_helper(struct wiphy *wiphy, struct file *file, 184 char *buf, size_t count, void *data) 185 { 186 struct rtw89_debugfs_priv *debugfs_priv = data; 187 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 188 189 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 190 } 191 192 static ssize_t rtw89_debugfs_file_write(struct file *file, 193 const char __user *userbuf, 194 size_t count, loff_t *loff) 195 { 196 struct rtw89_debugfs_priv *debugfs_priv = file->private_data; 197 struct rtw89_debugfs_priv_opt *opt = &debugfs_priv->opt; 198 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev; 199 char *buf __free(kfree) = kmalloc(count + 1, GFP_KERNEL); 200 ssize_t n; 201 202 if (!buf) 203 return -ENOMEM; 204 205 if (opt->wlock) { 206 n = wiphy_locked_debugfs_write(rtwdev->hw->wiphy, 207 file, buf, count + 1, 208 userbuf, count, 209 rtw89_debugfs_file_write_helper, 210 debugfs_priv); 211 return n; 212 } 213 214 if (copy_from_user(buf, userbuf, count)) 215 return -EFAULT; 216 217 buf[count] = '\0'; 218 219 return debugfs_priv->cb_write(rtwdev, debugfs_priv, buf, count); 220 } 221 222 static const struct debugfs_short_fops file_ops_single_r = { 223 .read = rtw89_debugfs_file_read, 224 .llseek = generic_file_llseek, 225 }; 226 227 static const struct debugfs_short_fops file_ops_common_rw = { 228 .read = rtw89_debugfs_file_read, 229 .write = rtw89_debugfs_file_write, 230 .llseek = generic_file_llseek, 231 }; 232 233 static const struct debugfs_short_fops file_ops_single_w = { 234 .write = rtw89_debugfs_file_write, 235 .llseek = generic_file_llseek, 236 }; 237 238 static ssize_t 239 rtw89_debug_priv_read_reg_select(struct rtw89_dev *rtwdev, 240 struct rtw89_debugfs_priv *debugfs_priv, 241 const char *buf, size_t count) 242 { 243 u32 addr, len; 244 int num; 245 246 num = sscanf(buf, "%x %x", &addr, &len); 247 if (num != 2) { 248 rtw89_info(rtwdev, "invalid format: <addr> <len>\n"); 249 return -EINVAL; 250 } 251 252 debugfs_priv->read_reg.addr = addr; 253 debugfs_priv->read_reg.len = len; 254 255 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr); 256 257 return count; 258 } 259 260 static 261 ssize_t rtw89_debug_priv_read_reg_get(struct rtw89_dev *rtwdev, 262 struct rtw89_debugfs_priv *debugfs_priv, 263 char *buf, size_t bufsz) 264 { 265 char *p = buf, *end = buf + bufsz; 266 u32 addr, addr_end, data, k; 267 u32 len; 268 269 len = debugfs_priv->read_reg.len; 270 addr = debugfs_priv->read_reg.addr; 271 272 if (len > 4) 273 goto ndata; 274 275 switch (len) { 276 case 1: 277 data = rtw89_read8(rtwdev, addr); 278 break; 279 case 2: 280 data = rtw89_read16(rtwdev, addr); 281 break; 282 case 4: 283 data = rtw89_read32(rtwdev, addr); 284 break; 285 default: 286 rtw89_info(rtwdev, "invalid read reg len %d\n", len); 287 return -EINVAL; 288 } 289 290 p += scnprintf(p, end - p, "get %d bytes at 0x%08x=0x%08x\n", len, 291 addr, data); 292 293 return p - buf; 294 295 ndata: 296 addr_end = addr + len; 297 298 for (; addr < addr_end; addr += 16) { 299 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + addr); 300 for (k = 0; k < 16; k += 4) { 301 data = rtw89_read32(rtwdev, addr + k); 302 p += scnprintf(p, end - p, "%08x ", data); 303 } 304 p += scnprintf(p, end - p, "\n"); 305 } 306 307 return p - buf; 308 } 309 310 static 311 ssize_t rtw89_debug_priv_write_reg_set(struct rtw89_dev *rtwdev, 312 struct rtw89_debugfs_priv *debugfs_priv, 313 const char *buf, size_t count) 314 { 315 u32 addr, val, len; 316 int num; 317 318 num = sscanf(buf, "%x %x %x", &addr, &val, &len); 319 if (num != 3) { 320 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n"); 321 return -EINVAL; 322 } 323 324 switch (len) { 325 case 1: 326 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val); 327 rtw89_write8(rtwdev, addr, (u8)val); 328 break; 329 case 2: 330 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val); 331 rtw89_write16(rtwdev, addr, (u16)val); 332 break; 333 case 4: 334 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val); 335 rtw89_write32(rtwdev, addr, (u32)val); 336 break; 337 default: 338 rtw89_info(rtwdev, "invalid read write len %d\n", len); 339 break; 340 } 341 342 return count; 343 } 344 345 static ssize_t 346 rtw89_debug_priv_read_rf_select(struct rtw89_dev *rtwdev, 347 struct rtw89_debugfs_priv *debugfs_priv, 348 const char *buf, size_t count) 349 { 350 u32 addr, mask; 351 u8 path; 352 int num; 353 354 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask); 355 if (num != 3) { 356 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n"); 357 return -EINVAL; 358 } 359 360 if (path >= rtwdev->chip->rf_path_num) { 361 rtw89_info(rtwdev, "wrong rf path\n"); 362 return -EINVAL; 363 } 364 debugfs_priv->read_rf.addr = addr; 365 debugfs_priv->read_rf.mask = mask; 366 debugfs_priv->read_rf.path = path; 367 368 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr); 369 370 return count; 371 } 372 373 static 374 ssize_t rtw89_debug_priv_read_rf_get(struct rtw89_dev *rtwdev, 375 struct rtw89_debugfs_priv *debugfs_priv, 376 char *buf, size_t bufsz) 377 { 378 char *p = buf, *end = buf + bufsz; 379 u32 addr, data, mask; 380 u8 path; 381 382 addr = debugfs_priv->read_rf.addr; 383 mask = debugfs_priv->read_rf.mask; 384 path = debugfs_priv->read_rf.path; 385 386 data = rtw89_read_rf(rtwdev, path, addr, mask); 387 388 p += scnprintf(p, end - p, "path %d, rf register 0x%08x=0x%08x\n", 389 path, addr, data); 390 391 return p - buf; 392 } 393 394 static 395 ssize_t rtw89_debug_priv_write_rf_set(struct rtw89_dev *rtwdev, 396 struct rtw89_debugfs_priv *debugfs_priv, 397 const char *buf, size_t count) 398 { 399 u32 addr, val, mask; 400 u8 path; 401 int num; 402 403 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val); 404 if (num != 4) { 405 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n"); 406 return -EINVAL; 407 } 408 409 if (path >= rtwdev->chip->rf_path_num) { 410 rtw89_info(rtwdev, "wrong rf path\n"); 411 return -EINVAL; 412 } 413 414 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n", 415 path, addr, val, mask); 416 rtw89_write_rf(rtwdev, path, addr, mask, val); 417 418 return count; 419 } 420 421 static 422 ssize_t rtw89_debug_priv_rf_reg_dump_get(struct rtw89_dev *rtwdev, 423 struct rtw89_debugfs_priv *debugfs_priv, 424 char *buf, size_t bufsz) 425 { 426 const struct rtw89_chip_info *chip = rtwdev->chip; 427 char *p = buf, *end = buf + bufsz; 428 u32 addr, offset, data; 429 u8 path; 430 431 for (path = 0; path < chip->rf_path_num; path++) { 432 p += scnprintf(p, end - p, "RF path %d:\n\n", path); 433 for (addr = 0; addr < 0x100; addr += 4) { 434 p += scnprintf(p, end - p, "0x%08x: ", addr); 435 for (offset = 0; offset < 4; offset++) { 436 data = rtw89_read_rf(rtwdev, path, 437 addr + offset, RFREG_MASK); 438 p += scnprintf(p, end - p, "0x%05x ", data); 439 } 440 p += scnprintf(p, end - p, "\n"); 441 } 442 p += scnprintf(p, end - p, "\n"); 443 } 444 445 return p - buf; 446 } 447 448 struct txpwr_ent { 449 bool nested; 450 union { 451 const char *txt; 452 const struct txpwr_ent *ptr; 453 }; 454 u8 len; 455 }; 456 457 struct txpwr_map { 458 const struct txpwr_ent *ent; 459 u8 size; 460 u32 addr_from; 461 u32 addr_to; 462 u32 addr_to_1ss; 463 }; 464 465 #define __GEN_TXPWR_ENT_NESTED(_e) \ 466 { .nested = true, .ptr = __txpwr_ent_##_e, \ 467 .len = ARRAY_SIZE(__txpwr_ent_##_e) } 468 469 #define __GEN_TXPWR_ENT0(_t) { .len = 0, .txt = _t } 470 471 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \ 472 { .len = 2, .txt = _t "\t- " _e0 " " _e1 } 473 474 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \ 475 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 } 476 477 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \ 478 { .len = 8, .txt = _t "\t- " \ 479 _e0 " " _e1 " " _e2 " " _e3 " " \ 480 _e4 " " _e5 " " _e6 " " _e7 } 481 482 static const struct txpwr_ent __txpwr_ent_byr_ax[] = { 483 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 484 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 485 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 486 /* 1NSS */ 487 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 488 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 489 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 490 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 491 /* 2NSS */ 492 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 493 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 494 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 495 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 496 }; 497 498 static_assert((ARRAY_SIZE(__txpwr_ent_byr_ax) * 4) == 499 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4)); 500 501 static const struct txpwr_map __txpwr_map_byr_ax = { 502 .ent = __txpwr_ent_byr_ax, 503 .size = ARRAY_SIZE(__txpwr_ent_byr_ax), 504 .addr_from = R_AX_PWR_BY_RATE, 505 .addr_to = R_AX_PWR_BY_RATE_MAX, 506 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX, 507 }; 508 509 static const struct txpwr_ent __txpwr_ent_lmt_ax[] = { 510 /* 1TX */ 511 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"), 512 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"), 513 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"), 514 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"), 515 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"), 516 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"), 517 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"), 518 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"), 519 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"), 520 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"), 521 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"), 522 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"), 523 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"), 524 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"), 525 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"), 526 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"), 527 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"), 528 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"), 529 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"), 530 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"), 531 /* 2TX */ 532 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"), 533 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"), 534 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"), 535 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"), 536 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"), 537 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"), 538 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"), 539 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"), 540 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"), 541 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"), 542 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"), 543 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"), 544 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"), 545 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"), 546 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"), 547 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"), 548 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"), 549 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"), 550 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"), 551 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"), 552 }; 553 554 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ax) * 2) == 555 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4)); 556 557 static const struct txpwr_map __txpwr_map_lmt_ax = { 558 .ent = __txpwr_ent_lmt_ax, 559 .size = ARRAY_SIZE(__txpwr_ent_lmt_ax), 560 .addr_from = R_AX_PWR_LMT, 561 .addr_to = R_AX_PWR_LMT_MAX, 562 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX, 563 }; 564 565 static const struct txpwr_ent __txpwr_ent_lmt_ru_ax[] = { 566 /* 1TX */ 567 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 568 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 569 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 570 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 571 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 572 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 573 /* 2TX */ 574 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3", 575 "RU26__4", "RU26__5", "RU26__6", "RU26__7"), 576 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3", 577 "RU52__4", "RU52__5", "RU52__6", "RU52__7"), 578 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3", 579 "RU106_4", "RU106_5", "RU106_6", "RU106_7"), 580 }; 581 582 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru_ax) * 8) == 583 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4)); 584 585 static const struct txpwr_map __txpwr_map_lmt_ru_ax = { 586 .ent = __txpwr_ent_lmt_ru_ax, 587 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_ax), 588 .addr_from = R_AX_PWR_RU_LMT, 589 .addr_to = R_AX_PWR_RU_LMT_MAX, 590 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX, 591 }; 592 593 static const struct txpwr_ent __txpwr_ent_byr_mcs_be[] = { 594 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 595 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 596 __GEN_TXPWR_ENT4("MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 597 __GEN_TXPWR_ENT2("MCS_1SS ", "MCS12 ", "MCS13 \t"), 598 __GEN_TXPWR_ENT4("HEDCM_1SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 599 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 600 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 601 __GEN_TXPWR_ENT4("DLRU_MCS_1SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 602 __GEN_TXPWR_ENT2("DLRU_MCS_1SS ", "MCS12 ", "MCS13 \t"), 603 __GEN_TXPWR_ENT4("DLRU_HEDCM_1SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 604 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 605 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 606 __GEN_TXPWR_ENT4("MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 607 __GEN_TXPWR_ENT2("MCS_2SS ", "MCS12 ", "MCS13 \t"), 608 __GEN_TXPWR_ENT4("HEDCM_2SS ", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 609 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "), 610 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "), 611 __GEN_TXPWR_ENT4("DLRU_MCS_2SS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"), 612 __GEN_TXPWR_ENT2("DLRU_MCS_2SS ", "MCS12 ", "MCS13 \t"), 613 __GEN_TXPWR_ENT4("DLRU_HEDCM_2SS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "), 614 }; 615 616 static const struct txpwr_ent __txpwr_ent_byr_be[] = { 617 __GEN_TXPWR_ENT0("BW20"), 618 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 619 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 620 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 621 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 622 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 623 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 624 625 __GEN_TXPWR_ENT0("BW40"), 626 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "), 627 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 628 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 629 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 630 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 631 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 632 633 /* there is no CCK section after BW80 */ 634 __GEN_TXPWR_ENT0("BW80"), 635 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 636 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 637 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 638 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 639 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 640 641 __GEN_TXPWR_ENT0("BW160"), 642 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 643 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 644 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 645 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 646 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 647 648 __GEN_TXPWR_ENT0("BW320"), 649 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "), 650 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "), 651 __GEN_TXPWR_ENT2("EHT ", "MCS14 ", "MCS15 \t"), 652 __GEN_TXPWR_ENT2("DLRU_EHT ", "MCS14 ", "MCS15 \t"), 653 __GEN_TXPWR_ENT_NESTED(byr_mcs_be), 654 }; 655 656 static const struct txpwr_map __txpwr_map_byr_be = { 657 .ent = __txpwr_ent_byr_be, 658 .size = ARRAY_SIZE(__txpwr_ent_byr_be), 659 .addr_from = R_BE_PWR_BY_RATE, 660 .addr_to = R_BE_PWR_BY_RATE_MAX, 661 .addr_to_1ss = 0, /* not support */ 662 }; 663 664 static const struct txpwr_ent __txpwr_ent_lmt_mcs_be[] = { 665 __GEN_TXPWR_ENT2("MCS_20M_0 ", "NON_BF", "BF"), 666 __GEN_TXPWR_ENT2("MCS_20M_1 ", "NON_BF", "BF"), 667 __GEN_TXPWR_ENT2("MCS_20M_2 ", "NON_BF", "BF"), 668 __GEN_TXPWR_ENT2("MCS_20M_3 ", "NON_BF", "BF"), 669 __GEN_TXPWR_ENT2("MCS_20M_4 ", "NON_BF", "BF"), 670 __GEN_TXPWR_ENT2("MCS_20M_5 ", "NON_BF", "BF"), 671 __GEN_TXPWR_ENT2("MCS_20M_6 ", "NON_BF", "BF"), 672 __GEN_TXPWR_ENT2("MCS_20M_7 ", "NON_BF", "BF"), 673 __GEN_TXPWR_ENT2("MCS_20M_8 ", "NON_BF", "BF"), 674 __GEN_TXPWR_ENT2("MCS_20M_9 ", "NON_BF", "BF"), 675 __GEN_TXPWR_ENT2("MCS_20M_10 ", "NON_BF", "BF"), 676 __GEN_TXPWR_ENT2("MCS_20M_11 ", "NON_BF", "BF"), 677 __GEN_TXPWR_ENT2("MCS_20M_12 ", "NON_BF", "BF"), 678 __GEN_TXPWR_ENT2("MCS_20M_13 ", "NON_BF", "BF"), 679 __GEN_TXPWR_ENT2("MCS_20M_14 ", "NON_BF", "BF"), 680 __GEN_TXPWR_ENT2("MCS_20M_15 ", "NON_BF", "BF"), 681 __GEN_TXPWR_ENT2("MCS_40M_0 ", "NON_BF", "BF"), 682 __GEN_TXPWR_ENT2("MCS_40M_1 ", "NON_BF", "BF"), 683 __GEN_TXPWR_ENT2("MCS_40M_2 ", "NON_BF", "BF"), 684 __GEN_TXPWR_ENT2("MCS_40M_3 ", "NON_BF", "BF"), 685 __GEN_TXPWR_ENT2("MCS_40M_4 ", "NON_BF", "BF"), 686 __GEN_TXPWR_ENT2("MCS_40M_5 ", "NON_BF", "BF"), 687 __GEN_TXPWR_ENT2("MCS_40M_6 ", "NON_BF", "BF"), 688 __GEN_TXPWR_ENT2("MCS_40M_7 ", "NON_BF", "BF"), 689 __GEN_TXPWR_ENT2("MCS_80M_0 ", "NON_BF", "BF"), 690 __GEN_TXPWR_ENT2("MCS_80M_1 ", "NON_BF", "BF"), 691 __GEN_TXPWR_ENT2("MCS_80M_2 ", "NON_BF", "BF"), 692 __GEN_TXPWR_ENT2("MCS_80M_3 ", "NON_BF", "BF"), 693 __GEN_TXPWR_ENT2("MCS_160M_0 ", "NON_BF", "BF"), 694 __GEN_TXPWR_ENT2("MCS_160M_1 ", "NON_BF", "BF"), 695 __GEN_TXPWR_ENT2("MCS_320M ", "NON_BF", "BF"), 696 __GEN_TXPWR_ENT2("MCS_40M_0p5", "NON_BF", "BF"), 697 __GEN_TXPWR_ENT2("MCS_40M_2p5", "NON_BF", "BF"), 698 __GEN_TXPWR_ENT2("MCS_40M_4p5", "NON_BF", "BF"), 699 __GEN_TXPWR_ENT2("MCS_40M_6p5", "NON_BF", "BF"), 700 }; 701 702 static const struct txpwr_ent __txpwr_ent_lmt_be[] = { 703 __GEN_TXPWR_ENT0("1TX"), 704 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 705 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 706 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 707 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 708 709 __GEN_TXPWR_ENT0("2TX"), 710 __GEN_TXPWR_ENT2("CCK_20M ", "NON_BF", "BF"), 711 __GEN_TXPWR_ENT2("CCK_40M ", "NON_BF", "BF"), 712 __GEN_TXPWR_ENT2("OFDM ", "NON_BF", "BF"), 713 __GEN_TXPWR_ENT_NESTED(lmt_mcs_be), 714 }; 715 716 static const struct txpwr_map __txpwr_map_lmt_be = { 717 .ent = __txpwr_ent_lmt_be, 718 .size = ARRAY_SIZE(__txpwr_ent_lmt_be), 719 .addr_from = R_BE_PWR_LMT, 720 .addr_to = R_BE_PWR_LMT_MAX, 721 .addr_to_1ss = 0, /* not support */ 722 }; 723 724 static const struct txpwr_ent __txpwr_ent_lmt_ru_indexes_be[] = { 725 __GEN_TXPWR_ENT8("RU26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 726 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 727 __GEN_TXPWR_ENT8("RU26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 728 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 729 __GEN_TXPWR_ENT8("RU52 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 730 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 731 __GEN_TXPWR_ENT8("RU52 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 732 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 733 __GEN_TXPWR_ENT8("RU106 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 734 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 735 __GEN_TXPWR_ENT8("RU106 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 736 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 737 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 738 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 739 __GEN_TXPWR_ENT8("RU52_26 ", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 740 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 741 __GEN_TXPWR_ENT8("RU106_26", "IDX_0 ", "IDX_1 ", "IDX_2 ", "IDX_3 ", 742 "IDX_4 ", "IDX_5 ", "IDX_6 ", "IDX_7 "), 743 __GEN_TXPWR_ENT8("RU106_26", "IDX_8 ", "IDX_9 ", "IDX_10", "IDX_11", 744 "IDX_12", "IDX_13", "IDX_14", "IDX_15"), 745 }; 746 747 static const struct txpwr_ent __txpwr_ent_lmt_ru_be[] = { 748 __GEN_TXPWR_ENT0("1TX"), 749 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 750 751 __GEN_TXPWR_ENT0("2TX"), 752 __GEN_TXPWR_ENT_NESTED(lmt_ru_indexes_be), 753 }; 754 755 static const struct txpwr_map __txpwr_map_lmt_ru_be = { 756 .ent = __txpwr_ent_lmt_ru_be, 757 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru_be), 758 .addr_from = R_BE_PWR_RU_LMT, 759 .addr_to = R_BE_PWR_RU_LMT_MAX, 760 .addr_to_1ss = 0, /* not support */ 761 }; 762 763 static unsigned int 764 __print_txpwr_ent(char *buf, size_t bufsz, const struct txpwr_ent *ent, 765 const s8 *bufp, const unsigned int cur, unsigned int *ate) 766 { 767 char *p = buf, *end = buf + bufsz; 768 unsigned int cnt, i; 769 unsigned int eaten; 770 char *fmt; 771 772 if (ent->nested) { 773 for (cnt = 0, i = 0; i < ent->len; i++, cnt += eaten) 774 p += __print_txpwr_ent(p, end - p, ent->ptr + i, bufp, 775 cur + cnt, &eaten); 776 *ate = cnt; 777 goto out; 778 } 779 780 switch (ent->len) { 781 case 0: 782 p += scnprintf(p, end - p, "\t<< %s >>\n", ent->txt); 783 *ate = 0; 784 goto out; 785 case 2: 786 fmt = "%s\t| %3d, %3d,\t\tdBm\n"; 787 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 788 bufp[cur + 1]); 789 *ate = 2; 790 goto out; 791 case 4: 792 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n"; 793 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 794 bufp[cur + 1], 795 bufp[cur + 2], bufp[cur + 3]); 796 *ate = 4; 797 goto out; 798 case 8: 799 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n"; 800 p += scnprintf(p, end - p, fmt, ent->txt, bufp[cur], 801 bufp[cur + 1], 802 bufp[cur + 2], bufp[cur + 3], bufp[cur + 4], 803 bufp[cur + 5], bufp[cur + 6], bufp[cur + 7]); 804 *ate = 8; 805 goto out; 806 default: 807 return 0; 808 } 809 810 out: 811 return p - buf; 812 } 813 814 static ssize_t __print_txpwr_map(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 815 const struct txpwr_map *map) 816 { 817 u8 fct = rtwdev->chip->txpwr_factor_mac; 818 u8 path_num = rtwdev->chip->rf_path_num; 819 char *p = buf, *end = buf + bufsz; 820 unsigned int cur, i; 821 unsigned int eaten; 822 u32 max_valid_addr; 823 u32 val, addr; 824 s8 *bufp, tmp; 825 int ret; 826 827 bufp = vzalloc(map->addr_to - map->addr_from + 4); 828 if (!bufp) 829 return -ENOMEM; 830 831 if (path_num == 1) 832 max_valid_addr = map->addr_to_1ss; 833 else 834 max_valid_addr = map->addr_to; 835 836 if (max_valid_addr == 0) 837 return -EOPNOTSUPP; 838 839 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) { 840 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val); 841 if (ret) 842 val = MASKDWORD; 843 844 cur = addr - map->addr_from; 845 for (i = 0; i < 4; i++, val >>= 8) { 846 /* signed 7 bits, and reserved BIT(7) */ 847 tmp = sign_extend32(val, 6); 848 bufp[cur + i] = tmp >> fct; 849 } 850 } 851 852 for (cur = 0, i = 0; i < map->size; i++, cur += eaten) 853 p += __print_txpwr_ent(p, end - p, &map->ent[i], bufp, cur, &eaten); 854 855 vfree(bufp); 856 return p - buf; 857 } 858 859 static int __print_regd(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 860 const struct rtw89_chan *chan) 861 { 862 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 863 char *p = buf, *end = buf + bufsz; 864 u8 band = chan->band_type; 865 u8 regd = rtw89_regd_get(rtwdev, band); 866 867 p += scnprintf(p, end - p, "%s\n", rtw89_regd_get_string(regd)); 868 p += scnprintf(p, end - p, "\t(txpwr UK follow ETSI: %s)\n", 869 str_yes_no(regulatory->txpwr_uk_follow_etsi)); 870 871 return p - buf; 872 } 873 874 struct dbgfs_txpwr_table { 875 const struct txpwr_map *byr; 876 const struct txpwr_map *lmt; 877 const struct txpwr_map *lmt_ru; 878 }; 879 880 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_ax = { 881 .byr = &__txpwr_map_byr_ax, 882 .lmt = &__txpwr_map_lmt_ax, 883 .lmt_ru = &__txpwr_map_lmt_ru_ax, 884 }; 885 886 static const struct dbgfs_txpwr_table dbgfs_txpwr_table_be = { 887 .byr = &__txpwr_map_byr_be, 888 .lmt = &__txpwr_map_lmt_be, 889 .lmt_ru = &__txpwr_map_lmt_ru_be, 890 }; 891 892 static const struct dbgfs_txpwr_table *dbgfs_txpwr_tables[RTW89_CHIP_GEN_NUM] = { 893 [RTW89_CHIP_AX] = &dbgfs_txpwr_table_ax, 894 [RTW89_CHIP_BE] = &dbgfs_txpwr_table_be, 895 }; 896 897 static 898 int rtw89_debug_priv_txpwr_table_get_regd(struct rtw89_dev *rtwdev, 899 char *buf, size_t bufsz, 900 const struct rtw89_chan *chan) 901 { 902 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 903 const struct rtw89_reg_6ghz_tpe *tpe6 = ®ulatory->reg_6ghz_tpe; 904 char *p = buf, *end = buf + bufsz; 905 906 p += scnprintf(p, end - p, "[Chanctx] band %u, ch %u, bw %u\n", 907 chan->band_type, chan->channel, chan->band_width); 908 909 p += scnprintf(p, end - p, "[Regulatory] "); 910 p += __print_regd(rtwdev, p, end - p, chan); 911 912 if (chan->band_type == RTW89_BAND_6G) { 913 p += scnprintf(p, end - p, "[reg6_pwr_type] %u\n", 914 regulatory->reg_6ghz_power); 915 916 if (tpe6->valid) 917 p += scnprintf(p, end - p, "[TPE] %d dBm\n", 918 tpe6->constraint); 919 } 920 921 return p - buf; 922 } 923 924 static 925 ssize_t rtw89_debug_priv_txpwr_table_get(struct rtw89_dev *rtwdev, 926 struct rtw89_debugfs_priv *debugfs_priv, 927 char *buf, size_t bufsz) 928 { 929 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 930 struct rtw89_sar_parm sar_parm = {}; 931 const struct dbgfs_txpwr_table *tbl; 932 const struct rtw89_chan *chan; 933 char *p = buf, *end = buf + bufsz; 934 ssize_t n; 935 936 lockdep_assert_wiphy(rtwdev->hw->wiphy); 937 938 rtw89_leave_ps_mode(rtwdev); 939 chan = rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 940 sar_parm.center_freq = chan->freq; 941 942 p += rtw89_debug_priv_txpwr_table_get_regd(rtwdev, p, end - p, chan); 943 944 p += scnprintf(p, end - p, "[SAR]\n"); 945 p += rtw89_print_sar(rtwdev, p, end - p, &sar_parm); 946 947 p += scnprintf(p, end - p, "[TAS]\n"); 948 p += rtw89_print_tas(rtwdev, p, end - p); 949 950 p += scnprintf(p, end - p, "[DAG]\n"); 951 p += rtw89_print_ant_gain(rtwdev, p, end - p, chan); 952 953 tbl = dbgfs_txpwr_tables[chip_gen]; 954 if (!tbl) 955 return -EOPNOTSUPP; 956 957 p += scnprintf(p, end - p, "\n[TX power byrate]\n"); 958 n = __print_txpwr_map(rtwdev, p, end - p, tbl->byr); 959 if (n < 0) 960 return n; 961 p += n; 962 963 p += scnprintf(p, end - p, "\n[TX power limit]\n"); 964 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt); 965 if (n < 0) 966 return n; 967 p += n; 968 969 p += scnprintf(p, end - p, "\n[TX power limit_ru]\n"); 970 n = __print_txpwr_map(rtwdev, p, end - p, tbl->lmt_ru); 971 if (n < 0) 972 return n; 973 p += n; 974 975 return p - buf; 976 } 977 978 static ssize_t 979 rtw89_debug_priv_mac_reg_dump_select(struct rtw89_dev *rtwdev, 980 struct rtw89_debugfs_priv *debugfs_priv, 981 const char *buf, size_t count) 982 { 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 int sel; 985 int ret; 986 987 ret = kstrtoint(buf, 0, &sel); 988 if (ret) 989 return ret; 990 991 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) { 992 rtw89_info(rtwdev, "invalid args: %d\n", sel); 993 return -EINVAL; 994 } 995 996 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) { 997 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel, 998 chip->chip_id); 999 return -EINVAL; 1000 } 1001 1002 debugfs_priv->cb_data = sel; 1003 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data); 1004 1005 return count; 1006 } 1007 1008 #define RTW89_MAC_PAGE_SIZE 0x100 1009 1010 static 1011 ssize_t rtw89_debug_priv_mac_reg_dump_get(struct rtw89_dev *rtwdev, 1012 struct rtw89_debugfs_priv *debugfs_priv, 1013 char *buf, size_t bufsz) 1014 { 1015 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data; 1016 char *p = buf, *end = buf + bufsz; 1017 u32 start, end_addr; 1018 u32 i, j, k, page; 1019 u32 val; 1020 1021 switch (reg_sel) { 1022 case RTW89_DBG_SEL_MAC_00: 1023 p += scnprintf(p, end - p, "Debug selected MAC page 0x00\n"); 1024 start = 0x000; 1025 end_addr = 0x014; 1026 break; 1027 case RTW89_DBG_SEL_MAC_30: 1028 p += scnprintf(p, end - p, "Debug selected MAC page 0x30\n"); 1029 start = 0x030; 1030 end_addr = 0x033; 1031 break; 1032 case RTW89_DBG_SEL_MAC_40: 1033 p += scnprintf(p, end - p, "Debug selected MAC page 0x40\n"); 1034 start = 0x040; 1035 end_addr = 0x07f; 1036 break; 1037 case RTW89_DBG_SEL_MAC_80: 1038 p += scnprintf(p, end - p, "Debug selected MAC page 0x80\n"); 1039 start = 0x080; 1040 end_addr = 0x09f; 1041 break; 1042 case RTW89_DBG_SEL_MAC_C0: 1043 p += scnprintf(p, end - p, "Debug selected MAC page 0xc0\n"); 1044 start = 0x0c0; 1045 end_addr = 0x0df; 1046 break; 1047 case RTW89_DBG_SEL_MAC_E0: 1048 p += scnprintf(p, end - p, "Debug selected MAC page 0xe0\n"); 1049 start = 0x0e0; 1050 end_addr = 0x0ff; 1051 break; 1052 case RTW89_DBG_SEL_BB: 1053 p += scnprintf(p, end - p, "Debug selected BB register\n"); 1054 start = 0x100; 1055 end_addr = 0x17f; 1056 break; 1057 case RTW89_DBG_SEL_IQK: 1058 p += scnprintf(p, end - p, "Debug selected IQK register\n"); 1059 start = 0x180; 1060 end_addr = 0x1bf; 1061 break; 1062 case RTW89_DBG_SEL_RFC: 1063 p += scnprintf(p, end - p, "Debug selected RFC register\n"); 1064 start = 0x1c0; 1065 end_addr = 0x1ff; 1066 break; 1067 default: 1068 p += scnprintf(p, end - p, "Selected invalid register page\n"); 1069 return -EINVAL; 1070 } 1071 1072 for (i = start; i <= end_addr; i++) { 1073 page = i << 8; 1074 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) { 1075 p += scnprintf(p, end - p, "%08xh : ", 0x18600000 + j); 1076 for (k = 0; k < 4; k++) { 1077 val = rtw89_read32(rtwdev, j + (k << 2)); 1078 p += scnprintf(p, end - p, "%08x ", val); 1079 } 1080 p += scnprintf(p, end - p, "\n"); 1081 } 1082 } 1083 1084 return p - buf; 1085 } 1086 1087 static ssize_t 1088 rtw89_debug_priv_mac_mem_dump_select(struct rtw89_dev *rtwdev, 1089 struct rtw89_debugfs_priv *debugfs_priv, 1090 const char *buf, size_t count) 1091 { 1092 u32 sel, start_addr, len; 1093 int num; 1094 1095 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len); 1096 if (num != 3) { 1097 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n"); 1098 return -EINVAL; 1099 } 1100 1101 debugfs_priv->mac_mem.sel = sel; 1102 debugfs_priv->mac_mem.start = start_addr; 1103 debugfs_priv->mac_mem.len = len; 1104 1105 rtw89_info(rtwdev, "select mem %d start %d len %d\n", 1106 sel, start_addr, len); 1107 1108 return count; 1109 } 1110 1111 static int rtw89_debug_dump_mac_mem(struct rtw89_dev *rtwdev, 1112 char *buf, size_t bufsz, 1113 u8 sel, u32 start_addr, u32 len) 1114 { 1115 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1116 u32 filter_model_addr = mac->filter_model_addr; 1117 u32 indir_access_addr = mac->indir_access_addr; 1118 u32 mem_page_size = mac->mem_page_size; 1119 u32 base_addr, start_page, residue; 1120 char *p = buf, *end = buf + bufsz; 1121 u32 i, j, pp, pages; 1122 u32 dump_len, remain; 1123 u32 val; 1124 1125 remain = len; 1126 pages = len / mem_page_size + 1; 1127 start_page = start_addr / mem_page_size; 1128 residue = start_addr % mem_page_size; 1129 base_addr = mac->mem_base_addrs[sel]; 1130 base_addr += start_page * mem_page_size; 1131 1132 for (pp = 0; pp < pages; pp++) { 1133 dump_len = min_t(u32, remain, mem_page_size); 1134 rtw89_write32(rtwdev, filter_model_addr, base_addr); 1135 for (i = indir_access_addr + residue; 1136 i < indir_access_addr + dump_len;) { 1137 p += scnprintf(p, end - p, "%08xh:", i); 1138 for (j = 0; 1139 j < 4 && i < indir_access_addr + dump_len; 1140 j++, i += 4) { 1141 val = rtw89_read32(rtwdev, i); 1142 p += scnprintf(p, end - p, " %08x", val); 1143 remain -= 4; 1144 } 1145 p += scnprintf(p, end - p, "\n"); 1146 } 1147 base_addr += mem_page_size; 1148 } 1149 1150 return p - buf; 1151 } 1152 1153 static ssize_t 1154 rtw89_debug_priv_mac_mem_dump_get(struct rtw89_dev *rtwdev, 1155 struct rtw89_debugfs_priv *debugfs_priv, 1156 char *buf, size_t bufsz) 1157 { 1158 char *p = buf, *end = buf + bufsz; 1159 bool grant_read = false; 1160 1161 lockdep_assert_wiphy(rtwdev->hw->wiphy); 1162 1163 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM) 1164 return -ENOENT; 1165 1166 if (rtwdev->chip->chip_id == RTL8852C) { 1167 switch (debugfs_priv->mac_mem.sel) { 1168 case RTW89_MAC_MEM_TXD_FIFO_0_V1: 1169 case RTW89_MAC_MEM_TXD_FIFO_1_V1: 1170 case RTW89_MAC_MEM_TXDATA_FIFO_0: 1171 case RTW89_MAC_MEM_TXDATA_FIFO_1: 1172 grant_read = true; 1173 break; 1174 default: 1175 break; 1176 } 1177 } 1178 1179 rtw89_leave_ps_mode(rtwdev); 1180 if (grant_read) 1181 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1182 p += rtw89_debug_dump_mac_mem(rtwdev, p, end - p, 1183 debugfs_priv->mac_mem.sel, 1184 debugfs_priv->mac_mem.start, 1185 debugfs_priv->mac_mem.len); 1186 if (grant_read) 1187 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO); 1188 1189 return p - buf; 1190 } 1191 1192 static ssize_t 1193 rtw89_debug_priv_mac_dbg_port_dump_select(struct rtw89_dev *rtwdev, 1194 struct rtw89_debugfs_priv *debugfs_priv, 1195 const char *buf, size_t count) 1196 { 1197 int sel, set; 1198 int num; 1199 bool enable; 1200 1201 num = sscanf(buf, "%d %d", &sel, &set); 1202 if (num != 2) { 1203 rtw89_info(rtwdev, "invalid format: <sel> <set>\n"); 1204 return -EINVAL; 1205 } 1206 1207 enable = set != 0; 1208 switch (sel) { 1209 case 0: 1210 debugfs_priv->dbgpkg_en.ss_dbg = enable; 1211 break; 1212 case 1: 1213 debugfs_priv->dbgpkg_en.dle_dbg = enable; 1214 break; 1215 case 2: 1216 debugfs_priv->dbgpkg_en.dmac_dbg = enable; 1217 break; 1218 case 3: 1219 debugfs_priv->dbgpkg_en.cmac_dbg = enable; 1220 break; 1221 case 4: 1222 debugfs_priv->dbgpkg_en.dbg_port = enable; 1223 break; 1224 default: 1225 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set); 1226 return -EINVAL; 1227 } 1228 1229 rtw89_info(rtwdev, "%s debug port dump %d\n", 1230 enable ? "Enable" : "Disable", sel); 1231 1232 return count; 1233 } 1234 1235 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev, 1236 char *buf, size_t bufsz) 1237 { 1238 return 0; 1239 } 1240 1241 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev, 1242 char *buf, size_t bufsz) 1243 { 1244 #define DLE_DFI_DUMP(__type, __target, __sel) \ 1245 ({ \ 1246 u32 __ctrl; \ 1247 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \ 1248 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \ 1249 u32 __data, __val32; \ 1250 int __ret; \ 1251 \ 1252 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \ 1253 DLE_DFI_TYPE_##__target) | \ 1254 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \ 1255 B_AX_WDE_DFI_ACTIVE; \ 1256 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \ 1257 __ret = read_poll_timeout(rtw89_read32, __val32, \ 1258 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \ 1259 1000, 50000, false, \ 1260 rtwdev, __reg_ctrl); \ 1261 if (__ret) { \ 1262 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \ 1263 #__type, #__target, __sel); \ 1264 return __ret; \ 1265 } \ 1266 \ 1267 __data = rtw89_read32(rtwdev, __reg_data); \ 1268 __data; \ 1269 }) 1270 1271 #define DLE_DFI_FREE_PAGE_DUMP(__p, __end, __type) \ 1272 ({ \ 1273 u32 __freepg, __pubpg; \ 1274 u32 __freepg_head, __freepg_tail, __pubpg_num; \ 1275 \ 1276 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \ 1277 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \ 1278 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \ 1279 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \ 1280 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \ 1281 __p += scnprintf(__p, __end - __p, "[%s] freepg head: %d\n", \ 1282 #__type, __freepg_head); \ 1283 __p += scnprintf(__p, __end - __p, "[%s] freepg tail: %d\n", \ 1284 #__type, __freepg_tail); \ 1285 __p += scnprintf(__p, __end - __p, "[%s] pubpg num : %d\n", \ 1286 #__type, __pubpg_num); \ 1287 }) 1288 1289 #define case_QUOTA(__p, __end, __type, __id) \ 1290 case __type##_QTAID_##__id: \ 1291 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \ 1292 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \ 1293 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \ 1294 __p += scnprintf(__p, __end - __p, "[%s][%s] rsv_pgnum: %d\n", \ 1295 #__type, #__id, rsv_pgnum); \ 1296 __p += scnprintf(__p, __end - __p, "[%s][%s] use_pgnum: %d\n", \ 1297 #__type, #__id, use_pgnum); \ 1298 break 1299 char *p = buf, *end = buf + bufsz; 1300 u32 quota_id; 1301 u32 val32; 1302 u16 rsv_pgnum, use_pgnum; 1303 int ret; 1304 1305 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1306 if (ret) { 1307 p += scnprintf(p, end - p, "[DLE] : DMAC not enabled\n"); 1308 goto out; 1309 } 1310 1311 DLE_DFI_FREE_PAGE_DUMP(p, end, WDE); 1312 DLE_DFI_FREE_PAGE_DUMP(p, end, PLE); 1313 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) { 1314 switch (quota_id) { 1315 case_QUOTA(p, end, WDE, HOST_IF); 1316 case_QUOTA(p, end, WDE, WLAN_CPU); 1317 case_QUOTA(p, end, WDE, DATA_CPU); 1318 case_QUOTA(p, end, WDE, PKTIN); 1319 case_QUOTA(p, end, WDE, CPUIO); 1320 } 1321 } 1322 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) { 1323 switch (quota_id) { 1324 case_QUOTA(p, end, PLE, B0_TXPL); 1325 case_QUOTA(p, end, PLE, B1_TXPL); 1326 case_QUOTA(p, end, PLE, C2H); 1327 case_QUOTA(p, end, PLE, H2C); 1328 case_QUOTA(p, end, PLE, WLAN_CPU); 1329 case_QUOTA(p, end, PLE, MPDU); 1330 case_QUOTA(p, end, PLE, CMAC0_RX); 1331 case_QUOTA(p, end, PLE, CMAC1_RX); 1332 case_QUOTA(p, end, PLE, CMAC1_BBRPT); 1333 case_QUOTA(p, end, PLE, WDRLS); 1334 case_QUOTA(p, end, PLE, CPUIO); 1335 } 1336 } 1337 1338 out: 1339 return p - buf; 1340 1341 #undef case_QUOTA 1342 #undef DLE_DFI_DUMP 1343 #undef DLE_DFI_FREE_PAGE_DUMP 1344 } 1345 1346 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev, 1347 char *buf, size_t bufsz) 1348 { 1349 const struct rtw89_chip_info *chip = rtwdev->chip; 1350 char *p = buf, *end = buf + bufsz; 1351 u32 dmac_err; 1352 int i, ret; 1353 1354 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 1355 if (ret) { 1356 p += scnprintf(p, end - p, "[DMAC] : DMAC not enabled\n"); 1357 goto out; 1358 } 1359 1360 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 1361 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 1362 p += scnprintf(p, end - p, "R_AX_DMAC_ERR_IMR=0x%08x\n", 1363 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 1364 1365 if (dmac_err) { 1366 p += scnprintf(p, end - p, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 1367 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 1368 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 1369 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 1370 if (chip->chip_id == RTL8852C) { 1371 p += scnprintf(p, end - p, 1372 "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 1373 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 1374 p += scnprintf(p, end - p, 1375 "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 1376 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 1377 p += scnprintf(p, end - p, 1378 "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 1379 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 1380 p += scnprintf(p, end - p, 1381 "R_AX_PLE_DBGERR_STS=0x%08x\n", 1382 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 1383 } 1384 } 1385 1386 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 1387 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 1388 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 1389 p += scnprintf(p, end - p, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 1390 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 1391 if (chip->chip_id == RTL8852C) 1392 p += scnprintf(p, end - p, 1393 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1394 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 1395 else 1396 p += scnprintf(p, end - p, 1397 "R_AX_RPQ_RXBD_IDX=0x%08x\n", 1398 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 1399 } 1400 1401 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 1402 if (chip->chip_id == RTL8852C) { 1403 p += scnprintf(p, end - p, 1404 "R_AX_SEC_ERR_IMR=0x%08x\n", 1405 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 1406 p += scnprintf(p, end - p, 1407 "R_AX_SEC_ERR_ISR=0x%08x\n", 1408 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 1409 p += scnprintf(p, end - p, 1410 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1411 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1412 p += scnprintf(p, end - p, 1413 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1414 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1415 p += scnprintf(p, end - p, 1416 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1417 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1418 p += scnprintf(p, end - p, 1419 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1420 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1421 p += scnprintf(p, end - p, "R_AX_SEC_DEBUG1=0x%08x\n", 1422 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 1423 p += scnprintf(p, end - p, 1424 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1425 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1426 p += scnprintf(p, end - p, 1427 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1428 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1429 1430 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1431 B_AX_DBG_SEL0, 0x8B); 1432 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 1433 B_AX_DBG_SEL1, 0x8B); 1434 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 1435 B_AX_SEL_0XC0_MASK, 1); 1436 for (i = 0; i < 0x10; i++) { 1437 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 1438 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 1439 p += scnprintf(p, end - p, 1440 "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 1441 i, 1442 rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 1443 } 1444 } else { 1445 p += scnprintf(p, end - p, 1446 "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 1447 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 1448 p += scnprintf(p, end - p, 1449 "R_AX_SEC_ENG_CTRL=0x%08x\n", 1450 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 1451 p += scnprintf(p, end - p, 1452 "R_AX_SEC_MPDU_PROC=0x%08x\n", 1453 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 1454 p += scnprintf(p, end - p, 1455 "R_AX_SEC_CAM_ACCESS=0x%08x\n", 1456 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 1457 p += scnprintf(p, end - p, 1458 "R_AX_SEC_CAM_RDATA=0x%08x\n", 1459 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 1460 p += scnprintf(p, end - p, 1461 "R_AX_SEC_CAM_WDATA=0x%08x\n", 1462 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 1463 p += scnprintf(p, end - p, 1464 "R_AX_SEC_TX_DEBUG=0x%08x\n", 1465 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 1466 p += scnprintf(p, end - p, 1467 "R_AX_SEC_RX_DEBUG=0x%08x\n", 1468 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 1469 p += scnprintf(p, end - p, 1470 "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 1471 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 1472 p += scnprintf(p, end - p, 1473 "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 1474 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 1475 } 1476 } 1477 1478 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 1479 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 1480 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 1481 p += scnprintf(p, end - p, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 1482 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 1483 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 1484 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 1485 p += scnprintf(p, end - p, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 1486 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 1487 } 1488 1489 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 1490 p += scnprintf(p, end - p, 1491 "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 1492 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 1493 p += scnprintf(p, end - p, 1494 "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 1495 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 1496 } 1497 1498 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 1499 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1500 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1501 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1502 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1503 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1504 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1505 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1506 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1507 } 1508 1509 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 1510 if (chip->chip_id == RTL8852C) { 1511 p += scnprintf(p, end - p, 1512 "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 1513 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 1514 p += scnprintf(p, end - p, 1515 "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 1516 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 1517 p += scnprintf(p, end - p, 1518 "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 1519 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 1520 p += scnprintf(p, end - p, 1521 "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 1522 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 1523 } else { 1524 p += scnprintf(p, end - p, 1525 "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 1526 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 1527 p += scnprintf(p, end - p, 1528 "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 1529 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 1530 } 1531 } 1532 1533 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 1534 p += scnprintf(p, end - p, "R_AX_WDE_ERR_IMR=0x%08x\n", 1535 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 1536 p += scnprintf(p, end - p, "R_AX_WDE_ERR_ISR=0x%08x\n", 1537 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 1538 p += scnprintf(p, end - p, "R_AX_PLE_ERR_IMR=0x%08x\n", 1539 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 1540 p += scnprintf(p, end - p, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 1541 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 1542 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 1543 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 1544 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 1545 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 1546 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 1547 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 1548 p += scnprintf(p, end - p, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 1549 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 1550 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 1551 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 1552 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 1553 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 1554 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 1555 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 1556 p += scnprintf(p, end - p, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 1557 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 1558 if (chip->chip_id == RTL8852C) { 1559 p += scnprintf(p, end - p, "R_AX_RX_CTRL0=0x%08x\n", 1560 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 1561 p += scnprintf(p, end - p, "R_AX_RX_CTRL1=0x%08x\n", 1562 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 1563 p += scnprintf(p, end - p, "R_AX_RX_CTRL2=0x%08x\n", 1564 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 1565 } else { 1566 p += scnprintf(p, end - p, 1567 "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 1568 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 1569 p += scnprintf(p, end - p, 1570 "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 1571 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 1572 p += scnprintf(p, end - p, 1573 "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 1574 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 1575 } 1576 } 1577 1578 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 1579 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 1580 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 1581 p += scnprintf(p, end - p, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 1582 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 1583 } 1584 1585 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 1586 p += scnprintf(p, end - p, 1587 "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 1588 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 1589 p += scnprintf(p, end - p, 1590 "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 1591 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 1592 p += scnprintf(p, end - p, 1593 "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 1594 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 1595 p += scnprintf(p, end - p, 1596 "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 1597 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 1598 p += scnprintf(p, end - p, 1599 "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 1600 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 1601 p += scnprintf(p, end - p, 1602 "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 1603 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 1604 } 1605 1606 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 1607 if (chip->chip_id == RTL8852C) { 1608 p += scnprintf(p, end - p, 1609 "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 1610 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 1611 p += scnprintf(p, end - p, 1612 "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 1613 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 1614 p += scnprintf(p, end - p, 1615 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1616 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1617 p += scnprintf(p, end - p, 1618 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1619 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1620 p += scnprintf(p, end - p, 1621 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1622 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1623 p += scnprintf(p, end - p, 1624 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1625 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1626 } else { 1627 p += scnprintf(p, end - p, 1628 "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 1629 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 1630 p += scnprintf(p, end - p, 1631 "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 1632 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 1633 p += scnprintf(p, end - p, 1634 "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 1635 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 1636 p += scnprintf(p, end - p, 1637 "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 1638 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 1639 p += scnprintf(p, end - p, 1640 "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 1641 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 1642 } 1643 } 1644 1645 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) { 1646 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 1647 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 1648 p += scnprintf(p, end - p, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 1649 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 1650 } 1651 1652 out: 1653 return p - buf; 1654 } 1655 1656 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev, 1657 char *buf, size_t bufsz, 1658 enum rtw89_mac_idx band) 1659 { 1660 const struct rtw89_chip_info *chip = rtwdev->chip; 1661 char *p = buf, *end = buf + bufsz; 1662 u32 offset = 0; 1663 u32 cmac_err; 1664 int ret; 1665 1666 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 1667 if (ret) { 1668 if (band) 1669 p += scnprintf(p, end - p, 1670 "[CMAC] : CMAC1 not enabled\n"); 1671 else 1672 p += scnprintf(p, end - p, 1673 "[CMAC] : CMAC0 not enabled\n"); 1674 goto out; 1675 } 1676 1677 if (band) 1678 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 1679 1680 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 1681 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 1682 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 1683 p += scnprintf(p, end - p, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 1684 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 1685 p += scnprintf(p, end - p, "R_AX_CK_EN [%d]=0x%08x\n", band, 1686 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 1687 1688 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 1689 p += scnprintf(p, end - p, 1690 "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 1691 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 1692 p += scnprintf(p, end - p, 1693 "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 1694 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 1695 } 1696 1697 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 1698 p += scnprintf(p, end - p, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", 1699 band, 1700 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 1701 p += scnprintf(p, end - p, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", 1702 band, 1703 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 1704 } 1705 1706 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 1707 if (chip->chip_id == RTL8852C) { 1708 p += scnprintf(p, end - p, 1709 "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 1710 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 1711 p += scnprintf(p, end - p, 1712 "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", 1713 band, 1714 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 1715 } else { 1716 p += scnprintf(p, end - p, 1717 "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 1718 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 1719 } 1720 } 1721 1722 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 1723 if (chip->chip_id == RTL8852C) { 1724 p += scnprintf(p, end - p, 1725 "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", 1726 band, 1727 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 1728 p += scnprintf(p, end - p, 1729 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1730 band, 1731 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1732 } else { 1733 p += scnprintf(p, end - p, 1734 "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", 1735 band, 1736 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 1737 } 1738 } 1739 1740 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 1741 p += scnprintf(p, end - p, "R_AX_TXPWR_IMR [%d]=0x%08x\n", 1742 band, 1743 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 1744 p += scnprintf(p, end - p, "R_AX_TXPWR_ISR [%d]=0x%08x\n", 1745 band, 1746 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 1747 } 1748 1749 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 1750 if (chip->chip_id == RTL8852C) { 1751 p += scnprintf(p, end - p, 1752 "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", 1753 band, 1754 rtw89_read32(rtwdev, 1755 R_AX_TRXPTCL_ERROR_INDICA + offset)); 1756 p += scnprintf(p, end - p, 1757 "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", 1758 band, 1759 rtw89_read32(rtwdev, 1760 R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 1761 } else { 1762 p += scnprintf(p, end - p, 1763 "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", 1764 band, 1765 rtw89_read32(rtwdev, 1766 R_AX_TMAC_ERR_IMR_ISR + offset)); 1767 } 1768 p += scnprintf(p, end - p, 1769 "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 1770 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 1771 } 1772 1773 p += scnprintf(p, end - p, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 1774 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 1775 1776 out: 1777 return p - buf; 1778 } 1779 1780 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev, 1781 char *buf, size_t bufsz) 1782 { 1783 char *p = buf, *end = buf + bufsz; 1784 1785 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_0); 1786 if (rtwdev->dbcc_en) 1787 p += rtw89_debug_mac_dump_cmac_err(rtwdev, p, end - p, RTW89_MAC_1); 1788 1789 return p - buf; 1790 } 1791 1792 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = { 1793 .sel_addr = R_AX_PTCL_DBG, 1794 .sel_byte = 1, 1795 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1796 .srt = 0x00, 1797 .end = 0x3F, 1798 .rd_addr = R_AX_PTCL_DBG_INFO, 1799 .rd_byte = 4, 1800 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1801 }; 1802 1803 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = { 1804 .sel_addr = R_AX_PTCL_DBG_C1, 1805 .sel_byte = 1, 1806 .sel_msk = B_AX_PTCL_DBG_SEL_MASK, 1807 .srt = 0x00, 1808 .end = 0x3F, 1809 .rd_addr = R_AX_PTCL_DBG_INFO_C1, 1810 .rd_byte = 4, 1811 .rd_msk = B_AX_PTCL_DBG_INFO_MASK 1812 }; 1813 1814 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = { 1815 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1816 .sel_byte = 2, 1817 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1818 .srt = 0x0, 1819 .end = 0xD, 1820 .rd_addr = R_AX_DBG_PORT_SEL, 1821 .rd_byte = 4, 1822 .rd_msk = B_AX_DEBUG_ST_MASK 1823 }; 1824 1825 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = { 1826 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1827 .sel_byte = 2, 1828 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1829 .srt = 0x0, 1830 .end = 0x5, 1831 .rd_addr = R_AX_DBG_PORT_SEL, 1832 .rd_byte = 4, 1833 .rd_msk = B_AX_DEBUG_ST_MASK 1834 }; 1835 1836 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = { 1837 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1838 .sel_byte = 2, 1839 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1840 .srt = 0x0, 1841 .end = 0x9, 1842 .rd_addr = R_AX_DBG_PORT_SEL, 1843 .rd_byte = 4, 1844 .rd_msk = B_AX_DEBUG_ST_MASK 1845 }; 1846 1847 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = { 1848 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1849 .sel_byte = 2, 1850 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1851 .srt = 0x0, 1852 .end = 0x3, 1853 .rd_addr = R_AX_DBG_PORT_SEL, 1854 .rd_byte = 4, 1855 .rd_msk = B_AX_DEBUG_ST_MASK 1856 }; 1857 1858 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = { 1859 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1860 .sel_byte = 2, 1861 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1862 .srt = 0x0, 1863 .end = 0x1, 1864 .rd_addr = R_AX_DBG_PORT_SEL, 1865 .rd_byte = 4, 1866 .rd_msk = B_AX_DEBUG_ST_MASK 1867 }; 1868 1869 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = { 1870 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1871 .sel_byte = 2, 1872 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1873 .srt = 0x0, 1874 .end = 0x0, 1875 .rd_addr = R_AX_DBG_PORT_SEL, 1876 .rd_byte = 4, 1877 .rd_msk = B_AX_DEBUG_ST_MASK 1878 }; 1879 1880 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = { 1881 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1882 .sel_byte = 2, 1883 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1884 .srt = 0x0, 1885 .end = 0xB, 1886 .rd_addr = R_AX_DBG_PORT_SEL, 1887 .rd_byte = 4, 1888 .rd_msk = B_AX_DEBUG_ST_MASK 1889 }; 1890 1891 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = { 1892 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1893 .sel_byte = 2, 1894 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1895 .srt = 0x0, 1896 .end = 0x4, 1897 .rd_addr = R_AX_DBG_PORT_SEL, 1898 .rd_byte = 4, 1899 .rd_msk = B_AX_DEBUG_ST_MASK 1900 }; 1901 1902 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = { 1903 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1904 .sel_byte = 2, 1905 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1906 .srt = 0x0, 1907 .end = 0x8, 1908 .rd_addr = R_AX_DBG_PORT_SEL, 1909 .rd_byte = 4, 1910 .rd_msk = B_AX_DEBUG_ST_MASK 1911 }; 1912 1913 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = { 1914 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1915 .sel_byte = 2, 1916 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1917 .srt = 0x0, 1918 .end = 0x7, 1919 .rd_addr = R_AX_DBG_PORT_SEL, 1920 .rd_byte = 4, 1921 .rd_msk = B_AX_DEBUG_ST_MASK 1922 }; 1923 1924 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = { 1925 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1926 .sel_byte = 2, 1927 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1928 .srt = 0x0, 1929 .end = 0x1, 1930 .rd_addr = R_AX_DBG_PORT_SEL, 1931 .rd_byte = 4, 1932 .rd_msk = B_AX_DEBUG_ST_MASK 1933 }; 1934 1935 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = { 1936 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1937 .sel_byte = 2, 1938 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1939 .srt = 0x0, 1940 .end = 0x3, 1941 .rd_addr = R_AX_DBG_PORT_SEL, 1942 .rd_byte = 4, 1943 .rd_msk = B_AX_DEBUG_ST_MASK 1944 }; 1945 1946 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = { 1947 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1948 .sel_byte = 2, 1949 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1950 .srt = 0x0, 1951 .end = 0x0, 1952 .rd_addr = R_AX_DBG_PORT_SEL, 1953 .rd_byte = 4, 1954 .rd_msk = B_AX_DEBUG_ST_MASK 1955 }; 1956 1957 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = { 1958 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1959 .sel_byte = 2, 1960 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1961 .srt = 0x0, 1962 .end = 0x8, 1963 .rd_addr = R_AX_DBG_PORT_SEL, 1964 .rd_byte = 4, 1965 .rd_msk = B_AX_DEBUG_ST_MASK 1966 }; 1967 1968 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = { 1969 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1970 .sel_byte = 2, 1971 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1972 .srt = 0x0, 1973 .end = 0x0, 1974 .rd_addr = R_AX_DBG_PORT_SEL, 1975 .rd_byte = 4, 1976 .rd_msk = B_AX_DEBUG_ST_MASK 1977 }; 1978 1979 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = { 1980 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1981 .sel_byte = 2, 1982 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1983 .srt = 0x0, 1984 .end = 0x6, 1985 .rd_addr = R_AX_DBG_PORT_SEL, 1986 .rd_byte = 4, 1987 .rd_msk = B_AX_DEBUG_ST_MASK 1988 }; 1989 1990 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = { 1991 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 1992 .sel_byte = 2, 1993 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 1994 .srt = 0x0, 1995 .end = 0x0, 1996 .rd_addr = R_AX_DBG_PORT_SEL, 1997 .rd_byte = 4, 1998 .rd_msk = B_AX_DEBUG_ST_MASK 1999 }; 2000 2001 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = { 2002 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2003 .sel_byte = 2, 2004 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK, 2005 .srt = 0x0, 2006 .end = 0x0, 2007 .rd_addr = R_AX_DBG_PORT_SEL, 2008 .rd_byte = 4, 2009 .rd_msk = B_AX_DEBUG_ST_MASK 2010 }; 2011 2012 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = { 2013 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2014 .sel_byte = 1, 2015 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2016 .srt = 0x0, 2017 .end = 0x3, 2018 .rd_addr = R_AX_DBG_PORT_SEL, 2019 .rd_byte = 4, 2020 .rd_msk = B_AX_DEBUG_ST_MASK 2021 }; 2022 2023 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = { 2024 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2025 .sel_byte = 1, 2026 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2027 .srt = 0x0, 2028 .end = 0x6, 2029 .rd_addr = R_AX_DBG_PORT_SEL, 2030 .rd_byte = 4, 2031 .rd_msk = B_AX_DEBUG_ST_MASK 2032 }; 2033 2034 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = { 2035 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2036 .sel_byte = 1, 2037 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2038 .srt = 0x0, 2039 .end = 0x0, 2040 .rd_addr = R_AX_DBG_PORT_SEL, 2041 .rd_byte = 4, 2042 .rd_msk = B_AX_DEBUG_ST_MASK 2043 }; 2044 2045 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = { 2046 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2047 .sel_byte = 1, 2048 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2049 .srt = 0x8, 2050 .end = 0xE, 2051 .rd_addr = R_AX_DBG_PORT_SEL, 2052 .rd_byte = 4, 2053 .rd_msk = B_AX_DEBUG_ST_MASK 2054 }; 2055 2056 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = { 2057 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2058 .sel_byte = 1, 2059 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2060 .srt = 0x0, 2061 .end = 0x5, 2062 .rd_addr = R_AX_DBG_PORT_SEL, 2063 .rd_byte = 4, 2064 .rd_msk = B_AX_DEBUG_ST_MASK 2065 }; 2066 2067 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = { 2068 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2069 .sel_byte = 1, 2070 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2071 .srt = 0x0, 2072 .end = 0x6, 2073 .rd_addr = R_AX_DBG_PORT_SEL, 2074 .rd_byte = 4, 2075 .rd_msk = B_AX_DEBUG_ST_MASK 2076 }; 2077 2078 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = { 2079 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2080 .sel_byte = 1, 2081 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2082 .srt = 0x0, 2083 .end = 0xF, 2084 .rd_addr = R_AX_DBG_PORT_SEL, 2085 .rd_byte = 4, 2086 .rd_msk = B_AX_DEBUG_ST_MASK 2087 }; 2088 2089 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = { 2090 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2091 .sel_byte = 1, 2092 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2093 .srt = 0x0, 2094 .end = 0x9, 2095 .rd_addr = R_AX_DBG_PORT_SEL, 2096 .rd_byte = 4, 2097 .rd_msk = B_AX_DEBUG_ST_MASK 2098 }; 2099 2100 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = { 2101 .sel_addr = R_AX_DISPATCHER_DBG_PORT, 2102 .sel_byte = 1, 2103 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK, 2104 .srt = 0x0, 2105 .end = 0x3, 2106 .rd_addr = R_AX_DBG_PORT_SEL, 2107 .rd_byte = 4, 2108 .rd_msk = B_AX_DEBUG_ST_MASK 2109 }; 2110 2111 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = { 2112 .sel_addr = R_AX_SCH_DBG_SEL, 2113 .sel_byte = 1, 2114 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2115 .srt = 0x00, 2116 .end = 0x2F, 2117 .rd_addr = R_AX_SCH_DBG, 2118 .rd_byte = 4, 2119 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2120 }; 2121 2122 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = { 2123 .sel_addr = R_AX_SCH_DBG_SEL_C1, 2124 .sel_byte = 1, 2125 .sel_msk = B_AX_SCH_DBG_SEL_MASK, 2126 .srt = 0x00, 2127 .end = 0x2F, 2128 .rd_addr = R_AX_SCH_DBG_C1, 2129 .rd_byte = 4, 2130 .rd_msk = B_AX_SCHEDULER_DBG_MASK 2131 }; 2132 2133 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = { 2134 .sel_addr = R_AX_MACTX_DBG_SEL_CNT, 2135 .sel_byte = 1, 2136 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2137 .srt = 0x00, 2138 .end = 0x19, 2139 .rd_addr = R_AX_DBG_PORT_SEL, 2140 .rd_byte = 4, 2141 .rd_msk = B_AX_DEBUG_ST_MASK 2142 }; 2143 2144 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = { 2145 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1, 2146 .sel_byte = 1, 2147 .sel_msk = B_AX_DBGSEL_MACTX_MASK, 2148 .srt = 0x00, 2149 .end = 0x19, 2150 .rd_addr = R_AX_DBG_PORT_SEL, 2151 .rd_byte = 4, 2152 .rd_msk = B_AX_DEBUG_ST_MASK 2153 }; 2154 2155 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = { 2156 .sel_addr = R_AX_RX_DEBUG_SELECT, 2157 .sel_byte = 1, 2158 .sel_msk = B_AX_DEBUG_SEL_MASK, 2159 .srt = 0x00, 2160 .end = 0x58, 2161 .rd_addr = R_AX_DBG_PORT_SEL, 2162 .rd_byte = 4, 2163 .rd_msk = B_AX_DEBUG_ST_MASK 2164 }; 2165 2166 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = { 2167 .sel_addr = R_AX_RX_DEBUG_SELECT_C1, 2168 .sel_byte = 1, 2169 .sel_msk = B_AX_DEBUG_SEL_MASK, 2170 .srt = 0x00, 2171 .end = 0x58, 2172 .rd_addr = R_AX_DBG_PORT_SEL, 2173 .rd_byte = 4, 2174 .rd_msk = B_AX_DEBUG_ST_MASK 2175 }; 2176 2177 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = { 2178 .sel_addr = R_AX_RX_STATE_MONITOR, 2179 .sel_byte = 1, 2180 .sel_msk = B_AX_STATE_SEL_MASK, 2181 .srt = 0x00, 2182 .end = 0x17, 2183 .rd_addr = R_AX_RX_STATE_MONITOR, 2184 .rd_byte = 4, 2185 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2186 }; 2187 2188 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = { 2189 .sel_addr = R_AX_RX_STATE_MONITOR_C1, 2190 .sel_byte = 1, 2191 .sel_msk = B_AX_STATE_SEL_MASK, 2192 .srt = 0x00, 2193 .end = 0x17, 2194 .rd_addr = R_AX_RX_STATE_MONITOR_C1, 2195 .rd_byte = 4, 2196 .rd_msk = B_AX_RX_STATE_MONITOR_MASK 2197 }; 2198 2199 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = { 2200 .sel_addr = R_AX_RMAC_PLCP_MON, 2201 .sel_byte = 4, 2202 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2203 .srt = 0x0, 2204 .end = 0xF, 2205 .rd_addr = R_AX_RMAC_PLCP_MON, 2206 .rd_byte = 4, 2207 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2208 }; 2209 2210 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = { 2211 .sel_addr = R_AX_RMAC_PLCP_MON_C1, 2212 .sel_byte = 4, 2213 .sel_msk = B_AX_PCLP_MON_SEL_MASK, 2214 .srt = 0x0, 2215 .end = 0xF, 2216 .rd_addr = R_AX_RMAC_PLCP_MON_C1, 2217 .rd_byte = 4, 2218 .rd_msk = B_AX_RMAC_PLCP_MON_MASK 2219 }; 2220 2221 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = { 2222 .sel_addr = R_AX_DBGSEL_TRXPTCL, 2223 .sel_byte = 1, 2224 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2225 .srt = 0x08, 2226 .end = 0x10, 2227 .rd_addr = R_AX_DBG_PORT_SEL, 2228 .rd_byte = 4, 2229 .rd_msk = B_AX_DEBUG_ST_MASK 2230 }; 2231 2232 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = { 2233 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1, 2234 .sel_byte = 1, 2235 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK, 2236 .srt = 0x08, 2237 .end = 0x10, 2238 .rd_addr = R_AX_DBG_PORT_SEL, 2239 .rd_byte = 4, 2240 .rd_msk = B_AX_DEBUG_ST_MASK 2241 }; 2242 2243 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = { 2244 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2245 .sel_byte = 1, 2246 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2247 .srt = 0x00, 2248 .end = 0x07, 2249 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG, 2250 .rd_byte = 4, 2251 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2252 }; 2253 2254 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = { 2255 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG, 2256 .sel_byte = 1, 2257 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2258 .srt = 0x00, 2259 .end = 0x07, 2260 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG, 2261 .rd_byte = 4, 2262 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2263 }; 2264 2265 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = { 2266 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2267 .sel_byte = 1, 2268 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2269 .srt = 0x00, 2270 .end = 0x07, 2271 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1, 2272 .rd_byte = 4, 2273 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK 2274 }; 2275 2276 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = { 2277 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1, 2278 .sel_byte = 1, 2279 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK, 2280 .srt = 0x00, 2281 .end = 0x07, 2282 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1, 2283 .rd_byte = 4, 2284 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK 2285 }; 2286 2287 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = { 2288 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2289 .sel_byte = 1, 2290 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2291 .srt = 0x00, 2292 .end = 0x04, 2293 .rd_addr = R_AX_WMAC_TX_TF_INFO_1, 2294 .rd_byte = 4, 2295 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2296 }; 2297 2298 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = { 2299 .sel_addr = R_AX_WMAC_TX_TF_INFO_0, 2300 .sel_byte = 1, 2301 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2302 .srt = 0x00, 2303 .end = 0x04, 2304 .rd_addr = R_AX_WMAC_TX_TF_INFO_2, 2305 .rd_byte = 4, 2306 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2307 }; 2308 2309 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = { 2310 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2311 .sel_byte = 1, 2312 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2313 .srt = 0x00, 2314 .end = 0x04, 2315 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1, 2316 .rd_byte = 4, 2317 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK 2318 }; 2319 2320 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = { 2321 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1, 2322 .sel_byte = 1, 2323 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK, 2324 .srt = 0x00, 2325 .end = 0x04, 2326 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1, 2327 .rd_byte = 4, 2328 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK 2329 }; 2330 2331 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = { 2332 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2333 .sel_byte = 4, 2334 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2335 .srt = 0x80000000, 2336 .end = 0x80000001, 2337 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2338 .rd_byte = 4, 2339 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2340 }; 2341 2342 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = { 2343 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2344 .sel_byte = 4, 2345 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2346 .srt = 0x80010000, 2347 .end = 0x80010004, 2348 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2349 .rd_byte = 4, 2350 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2351 }; 2352 2353 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = { 2354 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2355 .sel_byte = 4, 2356 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2357 .srt = 0x80020000, 2358 .end = 0x80020FFF, 2359 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2360 .rd_byte = 4, 2361 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2362 }; 2363 2364 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = { 2365 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2366 .sel_byte = 4, 2367 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2368 .srt = 0x80030000, 2369 .end = 0x80030FFF, 2370 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2371 .rd_byte = 4, 2372 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2373 }; 2374 2375 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = { 2376 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2377 .sel_byte = 4, 2378 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2379 .srt = 0x80040000, 2380 .end = 0x80040FFF, 2381 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2382 .rd_byte = 4, 2383 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2384 }; 2385 2386 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = { 2387 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2388 .sel_byte = 4, 2389 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2390 .srt = 0x80050000, 2391 .end = 0x80050FFF, 2392 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2393 .rd_byte = 4, 2394 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2395 }; 2396 2397 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = { 2398 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2399 .sel_byte = 4, 2400 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2401 .srt = 0x80060000, 2402 .end = 0x80060453, 2403 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2404 .rd_byte = 4, 2405 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2406 }; 2407 2408 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = { 2409 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL, 2410 .sel_byte = 4, 2411 .sel_msk = B_AX_WDE_DFI_DATA_MASK, 2412 .srt = 0x80070000, 2413 .end = 0x80070011, 2414 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA, 2415 .rd_byte = 4, 2416 .rd_msk = B_AX_WDE_DFI_DATA_MASK 2417 }; 2418 2419 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = { 2420 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2421 .sel_byte = 4, 2422 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2423 .srt = 0x80000000, 2424 .end = 0x80000001, 2425 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2426 .rd_byte = 4, 2427 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2428 }; 2429 2430 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = { 2431 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2432 .sel_byte = 4, 2433 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2434 .srt = 0x80010000, 2435 .end = 0x8001000A, 2436 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2437 .rd_byte = 4, 2438 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2439 }; 2440 2441 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = { 2442 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2443 .sel_byte = 4, 2444 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2445 .srt = 0x80020000, 2446 .end = 0x80020DBF, 2447 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2448 .rd_byte = 4, 2449 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2450 }; 2451 2452 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = { 2453 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2454 .sel_byte = 4, 2455 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2456 .srt = 0x80030000, 2457 .end = 0x80030DBF, 2458 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2459 .rd_byte = 4, 2460 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2461 }; 2462 2463 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = { 2464 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2465 .sel_byte = 4, 2466 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2467 .srt = 0x80040000, 2468 .end = 0x80040DBF, 2469 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2470 .rd_byte = 4, 2471 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2472 }; 2473 2474 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = { 2475 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2476 .sel_byte = 4, 2477 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2478 .srt = 0x80050000, 2479 .end = 0x80050DBF, 2480 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2481 .rd_byte = 4, 2482 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2483 }; 2484 2485 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = { 2486 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2487 .sel_byte = 4, 2488 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2489 .srt = 0x80060000, 2490 .end = 0x80060041, 2491 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2492 .rd_byte = 4, 2493 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2494 }; 2495 2496 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = { 2497 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL, 2498 .sel_byte = 4, 2499 .sel_msk = B_AX_PLE_DFI_DATA_MASK, 2500 .srt = 0x80070000, 2501 .end = 0x80070001, 2502 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA, 2503 .rd_byte = 4, 2504 .rd_msk = B_AX_PLE_DFI_DATA_MASK 2505 }; 2506 2507 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = { 2508 .sel_addr = R_AX_DBG_FUN_INTF_CTL, 2509 .sel_byte = 4, 2510 .sel_msk = B_AX_DFI_DATA_MASK, 2511 .srt = 0x80000000, 2512 .end = 0x8000017f, 2513 .rd_addr = R_AX_DBG_FUN_INTF_DATA, 2514 .rd_byte = 4, 2515 .rd_msk = B_AX_DFI_DATA_MASK 2516 }; 2517 2518 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = { 2519 .sel_addr = R_AX_PCIE_DBG_CTRL, 2520 .sel_byte = 2, 2521 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2522 .srt = 0x00, 2523 .end = 0x03, 2524 .rd_addr = R_AX_DBG_PORT_SEL, 2525 .rd_byte = 4, 2526 .rd_msk = B_AX_DEBUG_ST_MASK 2527 }; 2528 2529 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = { 2530 .sel_addr = R_AX_PCIE_DBG_CTRL, 2531 .sel_byte = 2, 2532 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2533 .srt = 0x00, 2534 .end = 0x04, 2535 .rd_addr = R_AX_DBG_PORT_SEL, 2536 .rd_byte = 4, 2537 .rd_msk = B_AX_DEBUG_ST_MASK 2538 }; 2539 2540 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = { 2541 .sel_addr = R_AX_PCIE_DBG_CTRL, 2542 .sel_byte = 2, 2543 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2544 .srt = 0x00, 2545 .end = 0x01, 2546 .rd_addr = R_AX_DBG_PORT_SEL, 2547 .rd_byte = 4, 2548 .rd_msk = B_AX_DEBUG_ST_MASK 2549 }; 2550 2551 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = { 2552 .sel_addr = R_AX_PCIE_DBG_CTRL, 2553 .sel_byte = 2, 2554 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2555 .srt = 0x00, 2556 .end = 0x05, 2557 .rd_addr = R_AX_DBG_PORT_SEL, 2558 .rd_byte = 4, 2559 .rd_msk = B_AX_DEBUG_ST_MASK 2560 }; 2561 2562 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = { 2563 .sel_addr = R_AX_PCIE_DBG_CTRL, 2564 .sel_byte = 2, 2565 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2566 .srt = 0x00, 2567 .end = 0x05, 2568 .rd_addr = R_AX_DBG_PORT_SEL, 2569 .rd_byte = 4, 2570 .rd_msk = B_AX_DEBUG_ST_MASK 2571 }; 2572 2573 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = { 2574 .sel_addr = R_AX_PCIE_DBG_CTRL, 2575 .sel_byte = 2, 2576 .sel_msk = B_AX_PCIE_DBG_SEL_MASK, 2577 .srt = 0x00, 2578 .end = 0x06, 2579 .rd_addr = R_AX_DBG_PORT_SEL, 2580 .rd_byte = 4, 2581 .rd_msk = B_AX_DEBUG_ST_MASK 2582 }; 2583 2584 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = { 2585 .sel_addr = R_AX_DBG_CTRL, 2586 .sel_byte = 1, 2587 .sel_msk = B_AX_DBG_SEL0, 2588 .srt = 0x34, 2589 .end = 0x3C, 2590 .rd_addr = R_AX_DBG_PORT_SEL, 2591 .rd_byte = 4, 2592 .rd_msk = B_AX_DEBUG_ST_MASK 2593 }; 2594 2595 static int 2596 rtw89_debug_mac_dbg_port_sel(struct rtw89_dev *rtwdev, char *buf, size_t bufsz, 2597 u32 sel, const struct rtw89_mac_dbg_port_info **ppinfo) 2598 { 2599 const struct rtw89_mac_dbg_port_info *info = NULL; 2600 char *p = buf, *end = buf + bufsz; 2601 u32 index; 2602 u32 val32; 2603 u16 val16; 2604 u8 val8; 2605 2606 switch (sel) { 2607 case RTW89_DBG_PORT_SEL_PTCL_C0: 2608 info = &dbg_port_ptcl_c0; 2609 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG); 2610 val16 |= B_AX_PTCL_DBG_EN; 2611 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16); 2612 p += scnprintf(p, end - p, "Enable PTCL C0 dbgport.\n"); 2613 break; 2614 case RTW89_DBG_PORT_SEL_PTCL_C1: 2615 info = &dbg_port_ptcl_c1; 2616 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1); 2617 val16 |= B_AX_PTCL_DBG_EN; 2618 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16); 2619 p += scnprintf(p, end - p, "Enable PTCL C1 dbgport.\n"); 2620 break; 2621 case RTW89_DBG_PORT_SEL_SCH_C0: 2622 info = &dbg_port_sch_c0; 2623 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL); 2624 val32 |= B_AX_SCH_DBG_EN; 2625 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32); 2626 p += scnprintf(p, end - p, "Enable SCH C0 dbgport.\n"); 2627 break; 2628 case RTW89_DBG_PORT_SEL_SCH_C1: 2629 info = &dbg_port_sch_c1; 2630 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1); 2631 val32 |= B_AX_SCH_DBG_EN; 2632 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32); 2633 p += scnprintf(p, end - p, "Enable SCH C1 dbgport.\n"); 2634 break; 2635 case RTW89_DBG_PORT_SEL_TMAC_C0: 2636 info = &dbg_port_tmac_c0; 2637 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2638 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2639 B_AX_DBGSEL_TRXPTCL_MASK); 2640 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2641 2642 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2643 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2644 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2645 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2646 2647 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2648 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2649 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2650 p += scnprintf(p, end - p, "Enable TMAC C0 dbgport.\n"); 2651 break; 2652 case RTW89_DBG_PORT_SEL_TMAC_C1: 2653 info = &dbg_port_tmac_c1; 2654 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2655 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC, 2656 B_AX_DBGSEL_TRXPTCL_MASK); 2657 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2658 2659 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2660 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2661 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2662 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2663 2664 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2665 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2666 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2667 p += scnprintf(p, end - p, "Enable TMAC C1 dbgport.\n"); 2668 break; 2669 case RTW89_DBG_PORT_SEL_RMAC_C0: 2670 info = &dbg_port_rmac_c0; 2671 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL); 2672 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2673 B_AX_DBGSEL_TRXPTCL_MASK); 2674 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32); 2675 2676 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2677 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0); 2678 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1); 2679 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2680 2681 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2682 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2683 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2684 2685 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL); 2686 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2687 B_AX_DBGSEL_TRXPTCL_MASK); 2688 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8); 2689 p += scnprintf(p, end - p, "Enable RMAC C0 dbgport.\n"); 2690 break; 2691 case RTW89_DBG_PORT_SEL_RMAC_C1: 2692 info = &dbg_port_rmac_c1; 2693 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2694 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC, 2695 B_AX_DBGSEL_TRXPTCL_MASK); 2696 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32); 2697 2698 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2699 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0); 2700 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1); 2701 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2702 2703 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2704 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2705 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2706 2707 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1); 2708 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL, 2709 B_AX_DBGSEL_TRXPTCL_MASK); 2710 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8); 2711 p += scnprintf(p, end - p, "Enable RMAC C1 dbgport.\n"); 2712 break; 2713 case RTW89_DBG_PORT_SEL_RMACST_C0: 2714 info = &dbg_port_rmacst_c0; 2715 p += scnprintf(p, end - p, "Enable RMAC state C0 dbgport.\n"); 2716 break; 2717 case RTW89_DBG_PORT_SEL_RMACST_C1: 2718 info = &dbg_port_rmacst_c1; 2719 p += scnprintf(p, end - p, "Enable RMAC state C1 dbgport.\n"); 2720 break; 2721 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0: 2722 info = &dbg_port_rmac_plcp_c0; 2723 p += scnprintf(p, end - p, "Enable RMAC PLCP C0 dbgport.\n"); 2724 break; 2725 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1: 2726 info = &dbg_port_rmac_plcp_c1; 2727 p += scnprintf(p, end - p, "Enable RMAC PLCP C1 dbgport.\n"); 2728 break; 2729 case RTW89_DBG_PORT_SEL_TRXPTCL_C0: 2730 info = &dbg_port_trxptcl_c0; 2731 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2732 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0); 2733 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1); 2734 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2735 2736 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2737 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2738 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2739 p += scnprintf(p, end - p, "Enable TRXPTCL C0 dbgport.\n"); 2740 break; 2741 case RTW89_DBG_PORT_SEL_TRXPTCL_C1: 2742 info = &dbg_port_trxptcl_c1; 2743 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 2744 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0); 2745 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1); 2746 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 2747 2748 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1); 2749 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK); 2750 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32); 2751 p += scnprintf(p, end - p, "Enable TRXPTCL C1 dbgport.\n"); 2752 break; 2753 case RTW89_DBG_PORT_SEL_TX_INFOL_C0: 2754 info = &dbg_port_tx_infol_c0; 2755 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2756 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2757 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2758 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2759 break; 2760 case RTW89_DBG_PORT_SEL_TX_INFOH_C0: 2761 info = &dbg_port_tx_infoh_c0; 2762 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2763 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2764 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2765 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2766 break; 2767 case RTW89_DBG_PORT_SEL_TX_INFOL_C1: 2768 info = &dbg_port_tx_infol_c1; 2769 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2770 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2771 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2772 p += scnprintf(p, end - p, "Enable tx infol dump.\n"); 2773 break; 2774 case RTW89_DBG_PORT_SEL_TX_INFOH_C1: 2775 info = &dbg_port_tx_infoh_c1; 2776 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2777 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2778 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2779 p += scnprintf(p, end - p, "Enable tx infoh dump.\n"); 2780 break; 2781 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0: 2782 info = &dbg_port_txtf_infol_c0; 2783 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2784 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2785 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2786 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2787 break; 2788 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0: 2789 info = &dbg_port_txtf_infoh_c0; 2790 val32 = rtw89_read32(rtwdev, R_AX_TCR1); 2791 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2792 rtw89_write32(rtwdev, R_AX_TCR1, val32); 2793 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2794 break; 2795 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1: 2796 info = &dbg_port_txtf_infol_c1; 2797 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2798 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2799 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2800 p += scnprintf(p, end - p, "Enable tx tf infol dump.\n"); 2801 break; 2802 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1: 2803 info = &dbg_port_txtf_infoh_c1; 2804 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1); 2805 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO; 2806 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32); 2807 p += scnprintf(p, end - p, "Enable tx tf infoh dump.\n"); 2808 break; 2809 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG: 2810 info = &dbg_port_wde_bufmgn_freepg; 2811 p += scnprintf(p, end - p, "Enable wde bufmgn freepg dump.\n"); 2812 break; 2813 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA: 2814 info = &dbg_port_wde_bufmgn_quota; 2815 p += scnprintf(p, end - p, "Enable wde bufmgn quota dump.\n"); 2816 break; 2817 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT: 2818 info = &dbg_port_wde_bufmgn_pagellt; 2819 p += scnprintf(p, end - p, 2820 "Enable wde bufmgn pagellt dump.\n"); 2821 break; 2822 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO: 2823 info = &dbg_port_wde_bufmgn_pktinfo; 2824 p += scnprintf(p, end - p, 2825 "Enable wde bufmgn pktinfo dump.\n"); 2826 break; 2827 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT: 2828 info = &dbg_port_wde_quemgn_prepkt; 2829 p += scnprintf(p, end - p, "Enable wde quemgn prepkt dump.\n"); 2830 break; 2831 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT: 2832 info = &dbg_port_wde_quemgn_nxtpkt; 2833 p += scnprintf(p, end - p, "Enable wde quemgn nxtpkt dump.\n"); 2834 break; 2835 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL: 2836 info = &dbg_port_wde_quemgn_qlnktbl; 2837 p += scnprintf(p, end - p, 2838 "Enable wde quemgn qlnktbl dump.\n"); 2839 break; 2840 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY: 2841 info = &dbg_port_wde_quemgn_qempty; 2842 p += scnprintf(p, end - p, "Enable wde quemgn qempty dump.\n"); 2843 break; 2844 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG: 2845 info = &dbg_port_ple_bufmgn_freepg; 2846 p += scnprintf(p, end - p, "Enable ple bufmgn freepg dump.\n"); 2847 break; 2848 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA: 2849 info = &dbg_port_ple_bufmgn_quota; 2850 p += scnprintf(p, end - p, "Enable ple bufmgn quota dump.\n"); 2851 break; 2852 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT: 2853 info = &dbg_port_ple_bufmgn_pagellt; 2854 p += scnprintf(p, end - p, 2855 "Enable ple bufmgn pagellt dump.\n"); 2856 break; 2857 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO: 2858 info = &dbg_port_ple_bufmgn_pktinfo; 2859 p += scnprintf(p, end - p, 2860 "Enable ple bufmgn pktinfo dump.\n"); 2861 break; 2862 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT: 2863 info = &dbg_port_ple_quemgn_prepkt; 2864 p += scnprintf(p, end - p, "Enable ple quemgn prepkt dump.\n"); 2865 break; 2866 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT: 2867 info = &dbg_port_ple_quemgn_nxtpkt; 2868 p += scnprintf(p, end - p, "Enable ple quemgn nxtpkt dump.\n"); 2869 break; 2870 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL: 2871 info = &dbg_port_ple_quemgn_qlnktbl; 2872 p += scnprintf(p, end - p, 2873 "Enable ple quemgn qlnktbl dump.\n"); 2874 break; 2875 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY: 2876 info = &dbg_port_ple_quemgn_qempty; 2877 p += scnprintf(p, end - p, "Enable ple quemgn qempty dump.\n"); 2878 break; 2879 case RTW89_DBG_PORT_SEL_PKTINFO: 2880 info = &dbg_port_pktinfo; 2881 p += scnprintf(p, end - p, "Enable pktinfo dump.\n"); 2882 break; 2883 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0: 2884 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 2885 B_AX_DBG_SEL0, 0x80); 2886 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 2887 B_AX_SEL_0XC0_MASK, 1); 2888 fallthrough; 2889 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1: 2890 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2: 2891 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3: 2892 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4: 2893 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5: 2894 info = &dbg_port_dspt_hdt_tx0_5; 2895 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0; 2896 rtw89_write16_mask(rtwdev, info->sel_addr, 2897 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2898 rtw89_write16_mask(rtwdev, info->sel_addr, 2899 B_AX_DISPATCHER_CH_SEL_MASK, index); 2900 p += scnprintf(p, end - p, 2901 "Enable Dispatcher hdt tx%x dump.\n", index); 2902 break; 2903 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6: 2904 info = &dbg_port_dspt_hdt_tx6; 2905 rtw89_write16_mask(rtwdev, info->sel_addr, 2906 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2907 rtw89_write16_mask(rtwdev, info->sel_addr, 2908 B_AX_DISPATCHER_CH_SEL_MASK, 6); 2909 p += scnprintf(p, end - p, 2910 "Enable Dispatcher hdt tx6 dump.\n"); 2911 break; 2912 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7: 2913 info = &dbg_port_dspt_hdt_tx7; 2914 rtw89_write16_mask(rtwdev, info->sel_addr, 2915 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2916 rtw89_write16_mask(rtwdev, info->sel_addr, 2917 B_AX_DISPATCHER_CH_SEL_MASK, 7); 2918 p += scnprintf(p, end - p, 2919 "Enable Dispatcher hdt tx7 dump.\n"); 2920 break; 2921 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8: 2922 info = &dbg_port_dspt_hdt_tx8; 2923 rtw89_write16_mask(rtwdev, info->sel_addr, 2924 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2925 rtw89_write16_mask(rtwdev, info->sel_addr, 2926 B_AX_DISPATCHER_CH_SEL_MASK, 8); 2927 p += scnprintf(p, end - p, 2928 "Enable Dispatcher hdt tx8 dump.\n"); 2929 break; 2930 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9: 2931 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA: 2932 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB: 2933 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC: 2934 info = &dbg_port_dspt_hdt_tx9_C; 2935 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9; 2936 rtw89_write16_mask(rtwdev, info->sel_addr, 2937 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2938 rtw89_write16_mask(rtwdev, info->sel_addr, 2939 B_AX_DISPATCHER_CH_SEL_MASK, index); 2940 p += scnprintf(p, end - p, 2941 "Enable Dispatcher hdt tx%x dump.\n", index); 2942 break; 2943 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD: 2944 info = &dbg_port_dspt_hdt_txD; 2945 rtw89_write16_mask(rtwdev, info->sel_addr, 2946 B_AX_DISPATCHER_INTN_SEL_MASK, 0); 2947 rtw89_write16_mask(rtwdev, info->sel_addr, 2948 B_AX_DISPATCHER_CH_SEL_MASK, 0xD); 2949 p += scnprintf(p, end - p, 2950 "Enable Dispatcher hdt txD dump.\n"); 2951 break; 2952 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0: 2953 info = &dbg_port_dspt_cdt_tx0; 2954 rtw89_write16_mask(rtwdev, info->sel_addr, 2955 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2956 rtw89_write16_mask(rtwdev, info->sel_addr, 2957 B_AX_DISPATCHER_CH_SEL_MASK, 0); 2958 p += scnprintf(p, end - p, 2959 "Enable Dispatcher cdt tx0 dump.\n"); 2960 break; 2961 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1: 2962 info = &dbg_port_dspt_cdt_tx1; 2963 rtw89_write16_mask(rtwdev, info->sel_addr, 2964 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2965 rtw89_write16_mask(rtwdev, info->sel_addr, 2966 B_AX_DISPATCHER_CH_SEL_MASK, 1); 2967 p += scnprintf(p, end - p, 2968 "Enable Dispatcher cdt tx1 dump.\n"); 2969 break; 2970 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3: 2971 info = &dbg_port_dspt_cdt_tx3; 2972 rtw89_write16_mask(rtwdev, info->sel_addr, 2973 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2974 rtw89_write16_mask(rtwdev, info->sel_addr, 2975 B_AX_DISPATCHER_CH_SEL_MASK, 3); 2976 p += scnprintf(p, end - p, 2977 "Enable Dispatcher cdt tx3 dump.\n"); 2978 break; 2979 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4: 2980 info = &dbg_port_dspt_cdt_tx4; 2981 rtw89_write16_mask(rtwdev, info->sel_addr, 2982 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2983 rtw89_write16_mask(rtwdev, info->sel_addr, 2984 B_AX_DISPATCHER_CH_SEL_MASK, 4); 2985 p += scnprintf(p, end - p, 2986 "Enable Dispatcher cdt tx4 dump.\n"); 2987 break; 2988 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5: 2989 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6: 2990 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7: 2991 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8: 2992 info = &dbg_port_dspt_cdt_tx5_8; 2993 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5; 2994 rtw89_write16_mask(rtwdev, info->sel_addr, 2995 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 2996 rtw89_write16_mask(rtwdev, info->sel_addr, 2997 B_AX_DISPATCHER_CH_SEL_MASK, index); 2998 p += scnprintf(p, end - p, 2999 "Enable Dispatcher cdt tx%x dump.\n", index); 3000 break; 3001 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9: 3002 info = &dbg_port_dspt_cdt_tx9; 3003 rtw89_write16_mask(rtwdev, info->sel_addr, 3004 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3005 rtw89_write16_mask(rtwdev, info->sel_addr, 3006 B_AX_DISPATCHER_CH_SEL_MASK, 9); 3007 p += scnprintf(p, end - p, 3008 "Enable Dispatcher cdt tx9 dump.\n"); 3009 break; 3010 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA: 3011 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB: 3012 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC: 3013 info = &dbg_port_dspt_cdt_txA_C; 3014 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA; 3015 rtw89_write16_mask(rtwdev, info->sel_addr, 3016 B_AX_DISPATCHER_INTN_SEL_MASK, 1); 3017 rtw89_write16_mask(rtwdev, info->sel_addr, 3018 B_AX_DISPATCHER_CH_SEL_MASK, index); 3019 p += scnprintf(p, end - p, 3020 "Enable Dispatcher cdt tx%x dump.\n", index); 3021 break; 3022 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0: 3023 info = &dbg_port_dspt_hdt_rx0; 3024 rtw89_write16_mask(rtwdev, info->sel_addr, 3025 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3026 rtw89_write16_mask(rtwdev, info->sel_addr, 3027 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3028 p += scnprintf(p, end - p, 3029 "Enable Dispatcher hdt rx0 dump.\n"); 3030 break; 3031 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1: 3032 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2: 3033 info = &dbg_port_dspt_hdt_rx1_2; 3034 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1; 3035 rtw89_write16_mask(rtwdev, info->sel_addr, 3036 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3037 rtw89_write16_mask(rtwdev, info->sel_addr, 3038 B_AX_DISPATCHER_CH_SEL_MASK, index); 3039 p += scnprintf(p, end - p, 3040 "Enable Dispatcher hdt rx%x dump.\n", index); 3041 break; 3042 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3: 3043 info = &dbg_port_dspt_hdt_rx3; 3044 rtw89_write16_mask(rtwdev, info->sel_addr, 3045 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3046 rtw89_write16_mask(rtwdev, info->sel_addr, 3047 B_AX_DISPATCHER_CH_SEL_MASK, 3); 3048 p += scnprintf(p, end - p, 3049 "Enable Dispatcher hdt rx3 dump.\n"); 3050 break; 3051 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4: 3052 info = &dbg_port_dspt_hdt_rx4; 3053 rtw89_write16_mask(rtwdev, info->sel_addr, 3054 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3055 rtw89_write16_mask(rtwdev, info->sel_addr, 3056 B_AX_DISPATCHER_CH_SEL_MASK, 4); 3057 p += scnprintf(p, end - p, 3058 "Enable Dispatcher hdt rx4 dump.\n"); 3059 break; 3060 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5: 3061 info = &dbg_port_dspt_hdt_rx5; 3062 rtw89_write16_mask(rtwdev, info->sel_addr, 3063 B_AX_DISPATCHER_INTN_SEL_MASK, 2); 3064 rtw89_write16_mask(rtwdev, info->sel_addr, 3065 B_AX_DISPATCHER_CH_SEL_MASK, 5); 3066 p += scnprintf(p, end - p, 3067 "Enable Dispatcher hdt rx5 dump.\n"); 3068 break; 3069 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0: 3070 info = &dbg_port_dspt_cdt_rx_p0_0; 3071 rtw89_write16_mask(rtwdev, info->sel_addr, 3072 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3073 rtw89_write16_mask(rtwdev, info->sel_addr, 3074 B_AX_DISPATCHER_CH_SEL_MASK, 0); 3075 p += scnprintf(p, end - p, 3076 "Enable Dispatcher cdt rx part0 0 dump.\n"); 3077 break; 3078 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0: 3079 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1: 3080 info = &dbg_port_dspt_cdt_rx_p0_1; 3081 rtw89_write16_mask(rtwdev, info->sel_addr, 3082 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3083 rtw89_write16_mask(rtwdev, info->sel_addr, 3084 B_AX_DISPATCHER_CH_SEL_MASK, 1); 3085 p += scnprintf(p, end - p, 3086 "Enable Dispatcher cdt rx part0 1 dump.\n"); 3087 break; 3088 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2: 3089 info = &dbg_port_dspt_cdt_rx_p0_2; 3090 rtw89_write16_mask(rtwdev, info->sel_addr, 3091 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3092 rtw89_write16_mask(rtwdev, info->sel_addr, 3093 B_AX_DISPATCHER_CH_SEL_MASK, 2); 3094 p += scnprintf(p, end - p, 3095 "Enable Dispatcher cdt rx part0 2 dump.\n"); 3096 break; 3097 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1: 3098 info = &dbg_port_dspt_cdt_rx_p1; 3099 rtw89_write8_mask(rtwdev, info->sel_addr, 3100 B_AX_DISPATCHER_INTN_SEL_MASK, 3); 3101 p += scnprintf(p, end - p, 3102 "Enable Dispatcher cdt rx part1 dump.\n"); 3103 break; 3104 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL: 3105 info = &dbg_port_dspt_stf_ctrl; 3106 rtw89_write8_mask(rtwdev, info->sel_addr, 3107 B_AX_DISPATCHER_INTN_SEL_MASK, 4); 3108 p += scnprintf(p, end - p, 3109 "Enable Dispatcher stf control dump.\n"); 3110 break; 3111 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL: 3112 info = &dbg_port_dspt_addr_ctrl; 3113 rtw89_write8_mask(rtwdev, info->sel_addr, 3114 B_AX_DISPATCHER_INTN_SEL_MASK, 5); 3115 p += scnprintf(p, end - p, 3116 "Enable Dispatcher addr control dump.\n"); 3117 break; 3118 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF: 3119 info = &dbg_port_dspt_wde_intf; 3120 rtw89_write8_mask(rtwdev, info->sel_addr, 3121 B_AX_DISPATCHER_INTN_SEL_MASK, 6); 3122 p += scnprintf(p, end - p, 3123 "Enable Dispatcher wde interface dump.\n"); 3124 break; 3125 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF: 3126 info = &dbg_port_dspt_ple_intf; 3127 rtw89_write8_mask(rtwdev, info->sel_addr, 3128 B_AX_DISPATCHER_INTN_SEL_MASK, 7); 3129 p += scnprintf(p, end - p, 3130 "Enable Dispatcher ple interface dump.\n"); 3131 break; 3132 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL: 3133 info = &dbg_port_dspt_flow_ctrl; 3134 rtw89_write8_mask(rtwdev, info->sel_addr, 3135 B_AX_DISPATCHER_INTN_SEL_MASK, 8); 3136 p += scnprintf(p, end - p, 3137 "Enable Dispatcher flow control dump.\n"); 3138 break; 3139 case RTW89_DBG_PORT_SEL_PCIE_TXDMA: 3140 info = &dbg_port_pcie_txdma; 3141 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3142 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0); 3143 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1); 3144 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3145 p += scnprintf(p, end - p, "Enable pcie txdma dump.\n"); 3146 break; 3147 case RTW89_DBG_PORT_SEL_PCIE_RXDMA: 3148 info = &dbg_port_pcie_rxdma; 3149 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3150 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0); 3151 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1); 3152 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3153 p += scnprintf(p, end - p, "Enable pcie rxdma dump.\n"); 3154 break; 3155 case RTW89_DBG_PORT_SEL_PCIE_CVT: 3156 info = &dbg_port_pcie_cvt; 3157 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3158 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0); 3159 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1); 3160 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3161 p += scnprintf(p, end - p, "Enable pcie cvt dump.\n"); 3162 break; 3163 case RTW89_DBG_PORT_SEL_PCIE_CXPL: 3164 info = &dbg_port_pcie_cxpl; 3165 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3166 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0); 3167 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1); 3168 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3169 p += scnprintf(p, end - p, "Enable pcie cxpl dump.\n"); 3170 break; 3171 case RTW89_DBG_PORT_SEL_PCIE_IO: 3172 info = &dbg_port_pcie_io; 3173 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3174 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0); 3175 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1); 3176 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3177 p += scnprintf(p, end - p, "Enable pcie io dump.\n"); 3178 break; 3179 case RTW89_DBG_PORT_SEL_PCIE_MISC: 3180 info = &dbg_port_pcie_misc; 3181 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL); 3182 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0); 3183 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1); 3184 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32); 3185 p += scnprintf(p, end - p, "Enable pcie misc dump.\n"); 3186 break; 3187 case RTW89_DBG_PORT_SEL_PCIE_MISC2: 3188 info = &dbg_port_pcie_misc2; 3189 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL); 3190 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL, 3191 B_AX_PCIE_DBG_SEL_MASK); 3192 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16); 3193 p += scnprintf(p, end - p, "Enable pcie misc2 dump.\n"); 3194 break; 3195 default: 3196 p += scnprintf(p, end - p, "Dbg port select err\n"); 3197 break; 3198 } 3199 3200 *ppinfo = info; 3201 3202 return p - buf; 3203 } 3204 3205 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel) 3206 { 3207 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE && 3208 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA && 3209 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2) 3210 return false; 3211 if (rtw89_is_rtl885xb(rtwdev) && 3212 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3213 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3214 return false; 3215 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3216 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG && 3217 sel <= RTW89_DBG_PORT_SEL_PKTINFO) 3218 return false; 3219 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) && 3220 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 && 3221 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL) 3222 return false; 3223 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) && 3224 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 && 3225 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0) 3226 return false; 3227 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) && 3228 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 && 3229 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1) 3230 return false; 3231 3232 return true; 3233 } 3234 3235 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev, 3236 char *buf, size_t bufsz, u32 sel) 3237 { 3238 const struct rtw89_mac_dbg_port_info *info = NULL; 3239 char *p = buf, *end = buf + bufsz; 3240 u32 val32; 3241 u16 val16; 3242 u8 val8; 3243 u32 i; 3244 3245 p += rtw89_debug_mac_dbg_port_sel(rtwdev, p, end - p, sel, &info); 3246 3247 if (!info) { 3248 rtw89_err(rtwdev, "failed to select debug port %d\n", sel); 3249 goto out; 3250 } 3251 3252 #define case_DBG_SEL(__sel) \ 3253 case RTW89_DBG_PORT_SEL_##__sel: \ 3254 p += scnprintf(p, end - p, "Dump debug port " #__sel ":\n"); \ 3255 break 3256 3257 switch (sel) { 3258 case_DBG_SEL(PTCL_C0); 3259 case_DBG_SEL(PTCL_C1); 3260 case_DBG_SEL(SCH_C0); 3261 case_DBG_SEL(SCH_C1); 3262 case_DBG_SEL(TMAC_C0); 3263 case_DBG_SEL(TMAC_C1); 3264 case_DBG_SEL(RMAC_C0); 3265 case_DBG_SEL(RMAC_C1); 3266 case_DBG_SEL(RMACST_C0); 3267 case_DBG_SEL(RMACST_C1); 3268 case_DBG_SEL(TRXPTCL_C0); 3269 case_DBG_SEL(TRXPTCL_C1); 3270 case_DBG_SEL(TX_INFOL_C0); 3271 case_DBG_SEL(TX_INFOH_C0); 3272 case_DBG_SEL(TX_INFOL_C1); 3273 case_DBG_SEL(TX_INFOH_C1); 3274 case_DBG_SEL(TXTF_INFOL_C0); 3275 case_DBG_SEL(TXTF_INFOH_C0); 3276 case_DBG_SEL(TXTF_INFOL_C1); 3277 case_DBG_SEL(TXTF_INFOH_C1); 3278 case_DBG_SEL(WDE_BUFMGN_FREEPG); 3279 case_DBG_SEL(WDE_BUFMGN_QUOTA); 3280 case_DBG_SEL(WDE_BUFMGN_PAGELLT); 3281 case_DBG_SEL(WDE_BUFMGN_PKTINFO); 3282 case_DBG_SEL(WDE_QUEMGN_PREPKT); 3283 case_DBG_SEL(WDE_QUEMGN_NXTPKT); 3284 case_DBG_SEL(WDE_QUEMGN_QLNKTBL); 3285 case_DBG_SEL(WDE_QUEMGN_QEMPTY); 3286 case_DBG_SEL(PLE_BUFMGN_FREEPG); 3287 case_DBG_SEL(PLE_BUFMGN_QUOTA); 3288 case_DBG_SEL(PLE_BUFMGN_PAGELLT); 3289 case_DBG_SEL(PLE_BUFMGN_PKTINFO); 3290 case_DBG_SEL(PLE_QUEMGN_PREPKT); 3291 case_DBG_SEL(PLE_QUEMGN_NXTPKT); 3292 case_DBG_SEL(PLE_QUEMGN_QLNKTBL); 3293 case_DBG_SEL(PLE_QUEMGN_QEMPTY); 3294 case_DBG_SEL(PKTINFO); 3295 case_DBG_SEL(DSPT_HDT_TX0); 3296 case_DBG_SEL(DSPT_HDT_TX1); 3297 case_DBG_SEL(DSPT_HDT_TX2); 3298 case_DBG_SEL(DSPT_HDT_TX3); 3299 case_DBG_SEL(DSPT_HDT_TX4); 3300 case_DBG_SEL(DSPT_HDT_TX5); 3301 case_DBG_SEL(DSPT_HDT_TX6); 3302 case_DBG_SEL(DSPT_HDT_TX7); 3303 case_DBG_SEL(DSPT_HDT_TX8); 3304 case_DBG_SEL(DSPT_HDT_TX9); 3305 case_DBG_SEL(DSPT_HDT_TXA); 3306 case_DBG_SEL(DSPT_HDT_TXB); 3307 case_DBG_SEL(DSPT_HDT_TXC); 3308 case_DBG_SEL(DSPT_HDT_TXD); 3309 case_DBG_SEL(DSPT_HDT_TXE); 3310 case_DBG_SEL(DSPT_HDT_TXF); 3311 case_DBG_SEL(DSPT_CDT_TX0); 3312 case_DBG_SEL(DSPT_CDT_TX1); 3313 case_DBG_SEL(DSPT_CDT_TX3); 3314 case_DBG_SEL(DSPT_CDT_TX4); 3315 case_DBG_SEL(DSPT_CDT_TX5); 3316 case_DBG_SEL(DSPT_CDT_TX6); 3317 case_DBG_SEL(DSPT_CDT_TX7); 3318 case_DBG_SEL(DSPT_CDT_TX8); 3319 case_DBG_SEL(DSPT_CDT_TX9); 3320 case_DBG_SEL(DSPT_CDT_TXA); 3321 case_DBG_SEL(DSPT_CDT_TXB); 3322 case_DBG_SEL(DSPT_CDT_TXC); 3323 case_DBG_SEL(DSPT_HDT_RX0); 3324 case_DBG_SEL(DSPT_HDT_RX1); 3325 case_DBG_SEL(DSPT_HDT_RX2); 3326 case_DBG_SEL(DSPT_HDT_RX3); 3327 case_DBG_SEL(DSPT_HDT_RX4); 3328 case_DBG_SEL(DSPT_HDT_RX5); 3329 case_DBG_SEL(DSPT_CDT_RX_P0); 3330 case_DBG_SEL(DSPT_CDT_RX_P0_0); 3331 case_DBG_SEL(DSPT_CDT_RX_P0_1); 3332 case_DBG_SEL(DSPT_CDT_RX_P0_2); 3333 case_DBG_SEL(DSPT_CDT_RX_P1); 3334 case_DBG_SEL(DSPT_STF_CTRL); 3335 case_DBG_SEL(DSPT_ADDR_CTRL); 3336 case_DBG_SEL(DSPT_WDE_INTF); 3337 case_DBG_SEL(DSPT_PLE_INTF); 3338 case_DBG_SEL(DSPT_FLOW_CTRL); 3339 case_DBG_SEL(PCIE_TXDMA); 3340 case_DBG_SEL(PCIE_RXDMA); 3341 case_DBG_SEL(PCIE_CVT); 3342 case_DBG_SEL(PCIE_CXPL); 3343 case_DBG_SEL(PCIE_IO); 3344 case_DBG_SEL(PCIE_MISC); 3345 case_DBG_SEL(PCIE_MISC2); 3346 } 3347 3348 #undef case_DBG_SEL 3349 3350 p += scnprintf(p, end - p, "Sel addr = 0x%X\n", info->sel_addr); 3351 p += scnprintf(p, end - p, "Read addr = 0x%X\n", info->rd_addr); 3352 3353 for (i = info->srt; i <= info->end; i++) { 3354 switch (info->sel_byte) { 3355 case 1: 3356 default: 3357 rtw89_write8_mask(rtwdev, info->sel_addr, 3358 info->sel_msk, i); 3359 p += scnprintf(p, end - p, "0x%02X: ", i); 3360 break; 3361 case 2: 3362 rtw89_write16_mask(rtwdev, info->sel_addr, 3363 info->sel_msk, i); 3364 p += scnprintf(p, end - p, "0x%04X: ", i); 3365 break; 3366 case 4: 3367 rtw89_write32_mask(rtwdev, info->sel_addr, 3368 info->sel_msk, i); 3369 p += scnprintf(p, end - p, "0x%04X: ", i); 3370 break; 3371 } 3372 3373 udelay(10); 3374 3375 switch (info->rd_byte) { 3376 case 1: 3377 default: 3378 val8 = rtw89_read8_mask(rtwdev, 3379 info->rd_addr, info->rd_msk); 3380 p += scnprintf(p, end - p, "0x%02X\n", val8); 3381 break; 3382 case 2: 3383 val16 = rtw89_read16_mask(rtwdev, 3384 info->rd_addr, info->rd_msk); 3385 p += scnprintf(p, end - p, "0x%04X\n", val16); 3386 break; 3387 case 4: 3388 val32 = rtw89_read32_mask(rtwdev, 3389 info->rd_addr, info->rd_msk); 3390 p += scnprintf(p, end - p, "0x%08X\n", val32); 3391 break; 3392 } 3393 } 3394 3395 out: 3396 return p - buf; 3397 } 3398 3399 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev, 3400 char *buf, size_t bufsz) 3401 { 3402 char *p = buf, *end = buf + bufsz; 3403 ssize_t n; 3404 u32 sel; 3405 3406 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0; 3407 sel < RTW89_DBG_PORT_SEL_LAST; sel++) { 3408 if (!is_dbg_port_valid(rtwdev, sel)) 3409 continue; 3410 n = rtw89_debug_mac_dbg_port_dump(rtwdev, p, end - p, sel); 3411 if (n < 0) { 3412 rtw89_err(rtwdev, 3413 "failed to dump debug port %d\n", sel); 3414 break; 3415 } 3416 p += n; 3417 } 3418 3419 return p - buf; 3420 } 3421 3422 static ssize_t 3423 rtw89_debug_priv_mac_dbg_port_dump_get(struct rtw89_dev *rtwdev, 3424 struct rtw89_debugfs_priv *debugfs_priv, 3425 char *buf, size_t bufsz) 3426 { 3427 char *p = buf, *end = buf + bufsz; 3428 3429 if (debugfs_priv->dbgpkg_en.ss_dbg) 3430 p += rtw89_debug_mac_dump_ss_dbg(rtwdev, p, end - p); 3431 if (debugfs_priv->dbgpkg_en.dle_dbg) 3432 p += rtw89_debug_mac_dump_dle_dbg(rtwdev, p, end - p); 3433 if (debugfs_priv->dbgpkg_en.dmac_dbg) 3434 p += rtw89_debug_mac_dump_dmac_dbg(rtwdev, p, end - p); 3435 if (debugfs_priv->dbgpkg_en.cmac_dbg) 3436 p += rtw89_debug_mac_dump_cmac_dbg(rtwdev, p, end - p); 3437 if (debugfs_priv->dbgpkg_en.dbg_port) 3438 p += rtw89_debug_mac_dump_dbg_port(rtwdev, p, end - p); 3439 3440 return p - buf; 3441 }; 3442 3443 static u8 *rtw89_hex2bin(struct rtw89_dev *rtwdev, const char *buf, size_t count) 3444 { 3445 u8 *bin; 3446 int num; 3447 int err = 0; 3448 3449 num = count / 2; 3450 bin = kmalloc(num, GFP_KERNEL); 3451 if (!bin) { 3452 err = -EFAULT; 3453 goto out; 3454 } 3455 3456 if (hex2bin(bin, buf, num)) { 3457 rtw89_info(rtwdev, "valid format: H1H2H3...\n"); 3458 kfree(bin); 3459 err = -EINVAL; 3460 } 3461 3462 out: 3463 return err ? ERR_PTR(err) : bin; 3464 } 3465 3466 static ssize_t rtw89_debug_priv_send_h2c_set(struct rtw89_dev *rtwdev, 3467 struct rtw89_debugfs_priv *debugfs_priv, 3468 const char *buf, size_t count) 3469 { 3470 u8 *h2c; 3471 int ret; 3472 u16 h2c_len = count / 2; 3473 3474 h2c = rtw89_hex2bin(rtwdev, buf, count); 3475 if (IS_ERR(h2c)) 3476 return -EFAULT; 3477 3478 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len); 3479 3480 kfree(h2c); 3481 3482 return ret ? ret : count; 3483 } 3484 3485 static ssize_t 3486 rtw89_debug_priv_early_h2c_get(struct rtw89_dev *rtwdev, 3487 struct rtw89_debugfs_priv *debugfs_priv, 3488 char *buf, size_t bufsz) 3489 { 3490 struct rtw89_early_h2c *early_h2c; 3491 char *p = buf, *end = buf + bufsz; 3492 int seq = 0; 3493 3494 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3495 3496 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list) 3497 p += scnprintf(p, end - p, "%d: %*ph\n", ++seq, 3498 early_h2c->h2c_len, early_h2c->h2c); 3499 3500 return p - buf; 3501 } 3502 3503 static ssize_t 3504 rtw89_debug_priv_early_h2c_set(struct rtw89_dev *rtwdev, 3505 struct rtw89_debugfs_priv *debugfs_priv, 3506 const char *buf, size_t count) 3507 { 3508 struct rtw89_early_h2c *early_h2c; 3509 u8 *h2c; 3510 u16 h2c_len = count / 2; 3511 3512 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3513 3514 h2c = rtw89_hex2bin(rtwdev, buf, count); 3515 if (IS_ERR(h2c)) 3516 return -EFAULT; 3517 3518 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) { 3519 kfree(h2c); 3520 rtw89_fw_free_all_early_h2c(rtwdev); 3521 goto out; 3522 } 3523 3524 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL); 3525 if (!early_h2c) { 3526 kfree(h2c); 3527 return -EFAULT; 3528 } 3529 3530 early_h2c->h2c = h2c; 3531 early_h2c->h2c_len = h2c_len; 3532 3533 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list); 3534 3535 out: 3536 return count; 3537 } 3538 3539 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev) 3540 { 3541 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3542 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3543 u16 pkt_id; 3544 int ret; 3545 3546 rtw89_leave_ps_mode(rtwdev); 3547 3548 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3549 if (ret) 3550 return ret; 3551 3552 /* intentionally, enqueue two pkt, but has only one pkt id */ 3553 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3554 ctrl_para.start_pktid = pkt_id; 3555 ctrl_para.end_pktid = pkt_id; 3556 ctrl_para.pkt_num = 1; /* start from 0 */ 3557 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3558 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3559 3560 if (mac->set_cpuio(rtwdev, &ctrl_para, true)) 3561 return -EFAULT; 3562 3563 return 0; 3564 } 3565 3566 static int rtw89_dbg_trigger_mac_error_ax(struct rtw89_dev *rtwdev) 3567 { 3568 u16 val16; 3569 u8 val8; 3570 int ret; 3571 3572 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3573 if (ret) 3574 return ret; 3575 3576 val8 = rtw89_read8(rtwdev, R_AX_CMAC_FUNC_EN); 3577 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8 & ~B_AX_TMAC_EN); 3578 mdelay(1); 3579 rtw89_write8(rtwdev, R_AX_CMAC_FUNC_EN, val8); 3580 3581 val16 = rtw89_read16(rtwdev, R_AX_PTCL_IMR0); 3582 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16 | B_AX_F2PCMD_EMPTY_ERR_INT_EN); 3583 rtw89_write16(rtwdev, R_AX_PTCL_IMR0, val16); 3584 3585 return 0; 3586 } 3587 3588 static int rtw89_dbg_trigger_mac_error_be(struct rtw89_dev *rtwdev) 3589 { 3590 int ret; 3591 3592 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3593 if (ret) 3594 return ret; 3595 3596 rtw89_write32_set(rtwdev, R_BE_CMAC_FW_TRIGGER_IDCT_ISR, 3597 B_BE_CMAC_FW_TRIG_IDCT | B_BE_CMAC_FW_ERR_IDCT_IMR); 3598 3599 return 0; 3600 } 3601 3602 static int rtw89_dbg_trigger_mac_error(struct rtw89_dev *rtwdev) 3603 { 3604 const struct rtw89_chip_info *chip = rtwdev->chip; 3605 3606 rtw89_leave_ps_mode(rtwdev); 3607 3608 switch (chip->chip_gen) { 3609 case RTW89_CHIP_AX: 3610 return rtw89_dbg_trigger_mac_error_ax(rtwdev); 3611 case RTW89_CHIP_BE: 3612 return rtw89_dbg_trigger_mac_error_be(rtwdev); 3613 default: 3614 return -EOPNOTSUPP; 3615 } 3616 } 3617 3618 static ssize_t 3619 rtw89_debug_priv_fw_crash_get(struct rtw89_dev *rtwdev, 3620 struct rtw89_debugfs_priv *debugfs_priv, 3621 char *buf, size_t bufsz) 3622 { 3623 char *p = buf, *end = buf + bufsz; 3624 3625 p += scnprintf(p, end - p, "%d\n", 3626 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags)); 3627 return p - buf; 3628 } 3629 3630 enum rtw89_dbg_crash_simulation_type { 3631 RTW89_DBG_SIM_CPU_EXCEPTION = 1, 3632 RTW89_DBG_SIM_CTRL_ERROR = 2, 3633 RTW89_DBG_SIM_MAC_ERROR = 3, 3634 }; 3635 3636 static ssize_t 3637 rtw89_debug_priv_fw_crash_set(struct rtw89_dev *rtwdev, 3638 struct rtw89_debugfs_priv *debugfs_priv, 3639 const char *buf, size_t count) 3640 { 3641 int (*sim)(struct rtw89_dev *rtwdev); 3642 bool announce = true; 3643 u8 crash_type; 3644 int ret; 3645 3646 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3647 3648 ret = kstrtou8(buf, 0, &crash_type); 3649 if (ret) 3650 return -EINVAL; 3651 3652 switch (crash_type) { 3653 case RTW89_DBG_SIM_CPU_EXCEPTION: 3654 if (!RTW89_CHK_FW_FEATURE_GROUP(CRASH_TRIGGER, &rtwdev->fw)) 3655 return -EOPNOTSUPP; 3656 sim = rtw89_fw_h2c_trigger_cpu_exception; 3657 break; 3658 case RTW89_DBG_SIM_CTRL_ERROR: 3659 sim = rtw89_dbg_trigger_ctrl_error; 3660 break; 3661 case RTW89_DBG_SIM_MAC_ERROR: 3662 sim = rtw89_dbg_trigger_mac_error; 3663 3664 /* Driver SER flow won't get involved; only FW will. */ 3665 announce = false; 3666 break; 3667 default: 3668 return -EINVAL; 3669 } 3670 3671 if (announce) 3672 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags); 3673 3674 ret = sim(rtwdev); 3675 3676 if (ret) 3677 return ret; 3678 3679 return count; 3680 } 3681 3682 static ssize_t rtw89_debug_priv_btc_info_get(struct rtw89_dev *rtwdev, 3683 struct rtw89_debugfs_priv *debugfs_priv, 3684 char *buf, size_t bufsz) 3685 { 3686 return rtw89_btc_dump_info(rtwdev, buf, bufsz); 3687 } 3688 3689 static ssize_t rtw89_debug_priv_btc_manual_set(struct rtw89_dev *rtwdev, 3690 struct rtw89_debugfs_priv *debugfs_priv, 3691 const char *buf, size_t count) 3692 { 3693 struct rtw89_btc *btc = &rtwdev->btc; 3694 const struct rtw89_btc_ver *ver = btc->ver; 3695 int ret; 3696 3697 ret = kstrtobool(buf, &btc->manual_ctrl); 3698 if (ret) 3699 return ret; 3700 3701 if (ver->fcxctrl == 7) 3702 btc->ctrl.ctrl_v7.manual = btc->manual_ctrl; 3703 else 3704 btc->ctrl.ctrl.manual = btc->manual_ctrl; 3705 3706 return count; 3707 } 3708 3709 static ssize_t rtw89_debug_priv_fw_log_manual_set(struct rtw89_dev *rtwdev, 3710 struct rtw89_debugfs_priv *debugfs_priv, 3711 const char *buf, size_t count) 3712 { 3713 struct rtw89_fw_log *log = &rtwdev->fw.log; 3714 bool fw_log_manual; 3715 3716 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3717 3718 if (kstrtobool(buf, &fw_log_manual)) 3719 goto out; 3720 3721 log->enable = fw_log_manual; 3722 if (log->enable) 3723 rtw89_fw_log_prepare(rtwdev); 3724 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual); 3725 out: 3726 return count; 3727 } 3728 3729 static int rtw89_sta_link_info_get_iter(struct rtw89_dev *rtwdev, 3730 char *buf, size_t bufsz, 3731 struct rtw89_sta_link *rtwsta_link) 3732 { 3733 static const char * const he_gi_str[] = { 3734 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8", 3735 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6", 3736 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2", 3737 }; 3738 static const char * const eht_gi_str[] = { 3739 [NL80211_RATE_INFO_EHT_GI_0_8] = "0.8", 3740 [NL80211_RATE_INFO_EHT_GI_1_6] = "1.6", 3741 [NL80211_RATE_INFO_EHT_GI_3_2] = "3.2", 3742 }; 3743 struct rate_info *rate = &rtwsta_link->ra_report.txrate; 3744 struct ieee80211_rx_status *status = &rtwsta_link->rx_status; 3745 struct rtw89_hal *hal = &rtwdev->hal; 3746 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3747 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity; 3748 struct ieee80211_link_sta *link_sta; 3749 char *p = buf, *end = buf + bufsz; 3750 u8 evm_min, evm_max, evm_1ss; 3751 u16 max_rc_amsdu_len; 3752 u8 rssi; 3753 u8 snr; 3754 int i; 3755 3756 rcu_read_lock(); 3757 3758 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3759 max_rc_amsdu_len = link_sta->agg.max_rc_amsdu_len; 3760 3761 rcu_read_unlock(); 3762 3763 p += scnprintf(p, end - p, "TX rate [%u, %u]: ", rtwsta_link->mac_id, 3764 rtwsta_link->link_id); 3765 3766 if (rate->flags & RATE_INFO_FLAGS_MCS) 3767 p += scnprintf(p, end - p, "HT MCS-%d%s", rate->mcs, 3768 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3769 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS) 3770 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", rate->nss, 3771 rate->mcs, 3772 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : ""); 3773 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS) 3774 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", rate->nss, 3775 rate->mcs, 3776 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3777 he_gi_str[rate->he_gi] : "N/A"); 3778 else if (rate->flags & RATE_INFO_FLAGS_EHT_MCS) 3779 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", rate->nss, 3780 rate->mcs, 3781 rate->eht_gi < ARRAY_SIZE(eht_gi_str) ? 3782 eht_gi_str[rate->eht_gi] : "N/A"); 3783 else 3784 p += scnprintf(p, end - p, "Legacy %d", rate->legacy); 3785 p += scnprintf(p, end - p, "%s", 3786 rtwsta_link->ra_report.might_fallback_legacy ? " FB_G" : ""); 3787 p += scnprintf(p, end - p, " BW:%u", 3788 rtw89_rate_info_bw_to_mhz(rate->bw)); 3789 p += scnprintf(p, end - p, " (hw_rate=0x%x)", 3790 rtwsta_link->ra_report.hw_rate); 3791 p += scnprintf(p, end - p, " ==> agg_wait=%d (%d)\n", 3792 rtwsta_link->max_agg_wait, 3793 max_rc_amsdu_len); 3794 3795 p += scnprintf(p, end - p, "RX rate [%u, %u]: ", rtwsta_link->mac_id, 3796 rtwsta_link->link_id); 3797 3798 switch (status->encoding) { 3799 case RX_ENC_LEGACY: 3800 p += scnprintf(p, end - p, "Legacy %d", status->rate_idx + 3801 (status->band != NL80211_BAND_2GHZ ? 4 : 0)); 3802 break; 3803 case RX_ENC_HT: 3804 p += scnprintf(p, end - p, "HT MCS-%d%s", status->rate_idx, 3805 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3806 break; 3807 case RX_ENC_VHT: 3808 p += scnprintf(p, end - p, "VHT %dSS MCS-%d%s", status->nss, 3809 status->rate_idx, 3810 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : ""); 3811 break; 3812 case RX_ENC_HE: 3813 p += scnprintf(p, end - p, "HE %dSS MCS-%d GI:%s", 3814 status->nss, status->rate_idx, 3815 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ? 3816 he_gi_str[status->he_gi] : "N/A"); 3817 break; 3818 case RX_ENC_EHT: 3819 p += scnprintf(p, end - p, "EHT %dSS MCS-%d GI:%s", 3820 status->nss, status->rate_idx, 3821 status->eht.gi < ARRAY_SIZE(eht_gi_str) ? 3822 eht_gi_str[status->eht.gi] : "N/A"); 3823 break; 3824 } 3825 p += scnprintf(p, end - p, " BW:%u", 3826 rtw89_rate_info_bw_to_mhz(status->bw)); 3827 p += scnprintf(p, end - p, " (hw_rate=0x%x)\n", 3828 rtwsta_link->rx_hw_rate); 3829 3830 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi); 3831 p += scnprintf(p, end - p, "RSSI: %d dBm (raw=%d, prev=%d) [", 3832 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, 3833 rtwsta_link->prev_rssi); 3834 for (i = 0; i < ant_num; i++) { 3835 rssi = ewma_rssi_read(&rtwsta_link->rssi[i]); 3836 p += scnprintf(p, end - p, "%d%s%s", 3837 RTW89_RSSI_RAW_TO_DBM(rssi), 3838 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "", 3839 i + 1 == ant_num ? "" : ", "); 3840 } 3841 p += scnprintf(p, end - p, "]\n"); 3842 3843 evm_1ss = ewma_evm_read(&rtwsta_link->evm_1ss); 3844 p += scnprintf(p, end - p, "EVM: [%2u.%02u, ", evm_1ss >> 2, 3845 (evm_1ss & 0x3) * 25); 3846 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) { 3847 evm_min = ewma_evm_read(&rtwsta_link->evm_min[i]); 3848 evm_max = ewma_evm_read(&rtwsta_link->evm_max[i]); 3849 3850 p += scnprintf(p, end - p, "%s(%2u.%02u, %2u.%02u)", 3851 i == 0 ? "" : " ", 3852 evm_min >> 2, (evm_min & 0x3) * 25, 3853 evm_max >> 2, (evm_max & 0x3) * 25); 3854 } 3855 p += scnprintf(p, end - p, "]\t"); 3856 3857 snr = ewma_snr_read(&rtwsta_link->avg_snr); 3858 p += scnprintf(p, end - p, "SNR: %u\n", snr); 3859 3860 return p - buf; 3861 } 3862 3863 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta) 3864 { 3865 struct rtw89_debugfs_iter_data *iter_data = 3866 (struct rtw89_debugfs_iter_data *)data; 3867 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3868 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3869 struct rtw89_sta_link *rtwsta_link; 3870 size_t bufsz = iter_data->bufsz; 3871 char *buf = iter_data->buf; 3872 char *p = buf, *end = buf + bufsz; 3873 unsigned int link_id; 3874 3875 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 3876 p += rtw89_sta_link_info_get_iter(rtwdev, p, end - p, rtwsta_link); 3877 3878 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 3879 } 3880 3881 static int 3882 rtw89_debug_append_rx_rate(char *buf, size_t bufsz, struct rtw89_pkt_stat *pkt_stat, 3883 enum rtw89_hw_rate first_rate, int len) 3884 { 3885 char *p = buf, *end = buf + bufsz; 3886 int i; 3887 3888 for (i = 0; i < len; i++) 3889 p += scnprintf(p, end - p, "%s%u", i == 0 ? "" : ", ", 3890 pkt_stat->rx_rate_cnt[first_rate + i]); 3891 3892 return p - buf; 3893 } 3894 3895 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate} 3896 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate} 3897 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate} 3898 3899 static const struct rtw89_rx_rate_cnt_info { 3900 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM]; 3901 int len; 3902 int ext; 3903 const char *rate_mode; 3904 } rtw89_rx_rate_cnt_infos[] = { 3905 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"}, 3906 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"}, 3907 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"}, 3908 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"}, 3909 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"}, 3910 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"}, 3911 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"}, 3912 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"}, 3913 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"}, 3914 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"}, 3915 }; 3916 3917 static ssize_t rtw89_debug_priv_phy_info_get(struct rtw89_dev *rtwdev, 3918 struct rtw89_debugfs_priv *debugfs_priv, 3919 char *buf, size_t bufsz) 3920 { 3921 struct rtw89_traffic_stats *stats = &rtwdev->stats; 3922 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 3923 const struct rtw89_chip_info *chip = rtwdev->chip; 3924 struct rtw89_debugfs_iter_data iter_data; 3925 const struct rtw89_rx_rate_cnt_info *info; 3926 struct rtw89_hal *hal = &rtwdev->hal; 3927 char *p = buf, *end = buf + bufsz; 3928 enum rtw89_hw_rate first_rate; 3929 u8 rssi; 3930 int i; 3931 3932 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3933 3934 p += scnprintf(p, end - p, "TP TX: %u [%u] Mbps (lv: %d", 3935 stats->tx_throughput, stats->tx_throughput_raw, 3936 stats->tx_tfc_lv); 3937 if (hal->thermal_prot_lv) 3938 p += scnprintf(p, end - p, ", duty: %d%%", 3939 100 - hal->thermal_prot_lv * RTW89_THERMAL_PROT_STEP); 3940 p += scnprintf(p, end - p, "), RX: %u [%u] Mbps (lv: %d)\n", 3941 stats->rx_throughput, stats->rx_throughput_raw, 3942 stats->rx_tfc_lv); 3943 p += scnprintf(p, end - p, "Beacon: %u (%d dBm), TF: %u\n", 3944 pkt_stat->beacon_nr, 3945 RTW89_RSSI_RAW_TO_DBM(rssi), stats->rx_tf_periodic); 3946 p += scnprintf(p, end - p, "Avg packet length: TX=%u, RX=%u\n", 3947 stats->tx_avg_len, 3948 stats->rx_avg_len); 3949 3950 p += scnprintf(p, end - p, "RX count:\n"); 3951 3952 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) { 3953 info = &rtw89_rx_rate_cnt_infos[i]; 3954 first_rate = info->first_rate[chip->chip_gen]; 3955 if (first_rate >= RTW89_HW_RATE_NR) 3956 continue; 3957 3958 p += scnprintf(p, end - p, "%10s [", info->rate_mode); 3959 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 3960 first_rate, info->len); 3961 if (info->ext) { 3962 p += scnprintf(p, end - p, "]["); 3963 p += rtw89_debug_append_rx_rate(p, end - p, pkt_stat, 3964 first_rate + info->len, info->ext); 3965 } 3966 p += scnprintf(p, end - p, "]\n"); 3967 } 3968 3969 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 3970 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, &iter_data); 3971 p += iter_data.written_sz; 3972 3973 return p - buf; 3974 } 3975 3976 static int rtw89_dump_addr_cam(struct rtw89_dev *rtwdev, 3977 char *buf, size_t bufsz, 3978 struct rtw89_addr_cam_entry *addr_cam) 3979 { 3980 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3981 const struct rtw89_sec_cam_entry *sec_entry; 3982 char *p = buf, *end = buf + bufsz; 3983 u8 sec_cam_idx; 3984 int i; 3985 3986 p += scnprintf(p, end - p, "\taddr_cam_idx=%u\n", 3987 addr_cam->addr_cam_idx); 3988 p += scnprintf(p, end - p, "\t-> bssid_cam_idx=%u\n", 3989 addr_cam->bssid_cam_idx); 3990 p += scnprintf(p, end - p, "\tsec_cam_bitmap=%*ph\n", 3991 (int)sizeof(addr_cam->sec_cam_map), 3992 addr_cam->sec_cam_map); 3993 for_each_set_bit(i, addr_cam->sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM) { 3994 sec_cam_idx = addr_cam->sec_ent[i]; 3995 sec_entry = cam_info->sec_entries[sec_cam_idx]; 3996 if (!sec_entry) 3997 continue; 3998 p += scnprintf(p, end - p, "\tsec[%d]: sec_cam_idx %u", i, 3999 sec_entry->sec_cam_idx); 4000 if (sec_entry->ext_key) 4001 p += scnprintf(p, end - p, ", %u", 4002 sec_entry->sec_cam_idx + 1); 4003 p += scnprintf(p, end - p, "\n"); 4004 } 4005 4006 return p - buf; 4007 } 4008 4009 __printf(4, 5) 4010 static int rtw89_dump_pkt_offload(char *buf, size_t bufsz, struct list_head *pkt_list, 4011 const char *fmt, ...) 4012 { 4013 char *p = buf, *end = buf + bufsz; 4014 struct rtw89_pktofld_info *info; 4015 struct va_format vaf; 4016 va_list args; 4017 4018 if (list_empty(pkt_list)) 4019 return 0; 4020 4021 va_start(args, fmt); 4022 vaf.va = &args; 4023 vaf.fmt = fmt; 4024 4025 p += scnprintf(p, end - p, "%pV", &vaf); 4026 4027 va_end(args); 4028 4029 list_for_each_entry(info, pkt_list, list) 4030 p += scnprintf(p, end - p, "%d ", info->id); 4031 4032 p += scnprintf(p, end - p, "\n"); 4033 4034 return p - buf; 4035 } 4036 4037 static int rtw89_vif_link_ids_get(struct rtw89_dev *rtwdev, 4038 char *buf, size_t bufsz, u8 *mac, 4039 struct rtw89_vif_link *rtwvif_link, 4040 bool designated) 4041 { 4042 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif_link->bssid_cam; 4043 char *p = buf, *end = buf + bufsz; 4044 4045 p += scnprintf(p, end - p, " [%u] %pM\n", rtwvif_link->mac_id, 4046 rtwvif_link->mac_addr); 4047 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwvif_link->link_id, 4048 designated ? " (*)" : ""); 4049 p += scnprintf(p, end - p, "\tbssid_cam_idx=%u\n", 4050 bssid_cam->bssid_cam_idx); 4051 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwvif_link->addr_cam); 4052 p += rtw89_dump_pkt_offload(p, end - p, &rtwvif_link->general_pkt_list, 4053 "\tpkt_ofld[GENERAL]: "); 4054 4055 return p - buf; 4056 } 4057 4058 static 4059 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 4060 { 4061 struct rtw89_debugfs_iter_data *iter_data = 4062 (struct rtw89_debugfs_iter_data *)data; 4063 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 4064 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4065 struct rtw89_vif_link *designated_link; 4066 struct rtw89_vif_link *rtwvif_link; 4067 size_t bufsz = iter_data->bufsz; 4068 char *buf = iter_data->buf; 4069 char *p = buf, *end = buf + bufsz; 4070 unsigned int link_id; 4071 4072 designated_link = rtw89_get_designated_link(rtwvif); 4073 4074 p += scnprintf(p, end - p, "VIF %pM\n", rtwvif->mac_addr); 4075 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 4076 p += rtw89_vif_link_ids_get(rtwdev, p, end - p, mac, rtwvif_link, 4077 rtwvif_link == designated_link); 4078 4079 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4080 } 4081 4082 static int rtw89_dump_ba_cam(struct rtw89_dev *rtwdev, 4083 char *buf, size_t bufsz, 4084 struct rtw89_sta_link *rtwsta_link) 4085 { 4086 struct rtw89_ba_cam_entry *entry; 4087 char *p = buf, *end = buf + bufsz; 4088 bool first = true; 4089 4090 list_for_each_entry(entry, &rtwsta_link->ba_cam_list, list) { 4091 if (first) { 4092 p += scnprintf(p, end - p, "\tba_cam "); 4093 first = false; 4094 } else { 4095 p += scnprintf(p, end - p, ", "); 4096 } 4097 p += scnprintf(p, end - p, "tid[%u]=%d", entry->tid, 4098 (int)(entry - rtwdev->cam_info.ba_cam_entry)); 4099 } 4100 p += scnprintf(p, end - p, "\n"); 4101 4102 return p - buf; 4103 } 4104 4105 static int rtw89_sta_link_ids_get(struct rtw89_dev *rtwdev, 4106 char *buf, size_t bufsz, 4107 struct rtw89_sta_link *rtwsta_link, 4108 bool designated) 4109 { 4110 struct ieee80211_link_sta *link_sta; 4111 char *p = buf, *end = buf + bufsz; 4112 4113 rcu_read_lock(); 4114 4115 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4116 4117 p += scnprintf(p, end - p, " [%u] %pM\n", rtwsta_link->mac_id, 4118 link_sta->addr); 4119 4120 rcu_read_unlock(); 4121 4122 p += scnprintf(p, end - p, "\tlink_id=%u%s\n", rtwsta_link->link_id, 4123 designated ? " (*)" : ""); 4124 p += rtw89_dump_addr_cam(rtwdev, p, end - p, &rtwsta_link->addr_cam); 4125 p += rtw89_dump_ba_cam(rtwdev, p, end - p, rtwsta_link); 4126 4127 return p - buf; 4128 } 4129 4130 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta) 4131 { 4132 struct rtw89_debugfs_iter_data *iter_data = 4133 (struct rtw89_debugfs_iter_data *)data; 4134 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 4135 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 4136 struct rtw89_sta_link *designated_link; 4137 struct rtw89_sta_link *rtwsta_link; 4138 size_t bufsz = iter_data->bufsz; 4139 char *buf = iter_data->buf; 4140 char *p = buf, *end = buf + bufsz; 4141 unsigned int link_id; 4142 4143 designated_link = rtw89_get_designated_link(rtwsta); 4144 4145 p += scnprintf(p, end - p, "STA %pM %s\n", sta->addr, 4146 sta->tdls ? "(TDLS)" : ""); 4147 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) 4148 p += rtw89_sta_link_ids_get(rtwdev, p, end - p, rtwsta_link, 4149 rtwsta_link == designated_link); 4150 4151 rtw89_debugfs_iter_data_next(iter_data, p, end - p, p - buf); 4152 } 4153 4154 static ssize_t rtw89_debug_priv_stations_get(struct rtw89_dev *rtwdev, 4155 struct rtw89_debugfs_priv *debugfs_priv, 4156 char *buf, size_t bufsz) 4157 { 4158 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 4159 struct rtw89_debugfs_iter_data iter_data; 4160 char *p = buf, *end = buf + bufsz; 4161 u8 idx; 4162 4163 lockdep_assert_wiphy(rtwdev->hw->wiphy); 4164 4165 p += scnprintf(p, end - p, "map:\n"); 4166 p += scnprintf(p, end - p, "\tmac_id: %*ph\n", 4167 (int)sizeof(rtwdev->mac_id_map), 4168 rtwdev->mac_id_map); 4169 p += scnprintf(p, end - p, "\taddr_cam: %*ph\n", 4170 (int)sizeof(cam_info->addr_cam_map), 4171 cam_info->addr_cam_map); 4172 p += scnprintf(p, end - p, "\tbssid_cam: %*ph\n", 4173 (int)sizeof(cam_info->bssid_cam_map), 4174 cam_info->bssid_cam_map); 4175 p += scnprintf(p, end - p, "\tsec_cam: %*ph\n", 4176 (int)sizeof(cam_info->sec_cam_map), 4177 cam_info->sec_cam_map); 4178 p += scnprintf(p, end - p, "\tba_cam: %*ph\n", 4179 (int)sizeof(cam_info->ba_cam_map), 4180 cam_info->ba_cam_map); 4181 p += scnprintf(p, end - p, "\tpkt_ofld: %*ph\n", 4182 (int)sizeof(rtwdev->pkt_offload), 4183 rtwdev->pkt_offload); 4184 4185 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) { 4186 if (!(rtwdev->chip->support_bands & BIT(idx))) 4187 continue; 4188 p += rtw89_dump_pkt_offload(p, end - p, &rtwdev->scan_info.pkt_list[idx], 4189 "\t\t[SCAN %u]: ", idx); 4190 } 4191 4192 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4193 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw, 4194 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, &iter_data); 4195 p += iter_data.written_sz; 4196 4197 rtw89_debugfs_iter_data_setup(&iter_data, p, end - p); 4198 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, &iter_data); 4199 p += iter_data.written_sz; 4200 4201 return p - buf; 4202 } 4203 4204 static void rtw89_debug_disable_dm_cfg_bmap(struct rtw89_dev *rtwdev, u32 new) 4205 { 4206 struct rtw89_hal *hal = &rtwdev->hal; 4207 u32 old = hal->disabled_dm_bitmap; 4208 4209 if (new == old) 4210 return; 4211 4212 hal->disabled_dm_bitmap = new; 4213 4214 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Disable DM: 0x%x -> 0x%x\n", old, new); 4215 } 4216 4217 static void rtw89_debug_disable_dm_set_flag(struct rtw89_dev *rtwdev, u8 flag) 4218 { 4219 struct rtw89_hal *hal = &rtwdev->hal; 4220 u32 cur = hal->disabled_dm_bitmap; 4221 4222 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur | BIT(flag)); 4223 } 4224 4225 static void rtw89_debug_disable_dm_clr_flag(struct rtw89_dev *rtwdev, u8 flag) 4226 { 4227 struct rtw89_hal *hal = &rtwdev->hal; 4228 u32 cur = hal->disabled_dm_bitmap; 4229 4230 rtw89_debug_disable_dm_cfg_bmap(rtwdev, cur & ~BIT(flag)); 4231 } 4232 4233 #define DM_INFO(type) {RTW89_DM_ ## type, #type} 4234 4235 static const struct rtw89_disabled_dm_info { 4236 enum rtw89_dm_type type; 4237 const char *name; 4238 } rtw89_disabled_dm_infos[] = { 4239 DM_INFO(DYNAMIC_EDCCA), 4240 DM_INFO(THERMAL_PROTECT), 4241 DM_INFO(TAS), 4242 DM_INFO(MLO), 4243 }; 4244 4245 static ssize_t 4246 rtw89_debug_priv_disable_dm_get(struct rtw89_dev *rtwdev, 4247 struct rtw89_debugfs_priv *debugfs_priv, 4248 char *buf, size_t bufsz) 4249 { 4250 const struct rtw89_disabled_dm_info *info; 4251 struct rtw89_hal *hal = &rtwdev->hal; 4252 char *p = buf, *end = buf + bufsz; 4253 u32 disabled; 4254 int i; 4255 4256 p += scnprintf(p, end - p, "Disabled DM: 0x%x\n", 4257 hal->disabled_dm_bitmap); 4258 4259 for (i = 0; i < ARRAY_SIZE(rtw89_disabled_dm_infos); i++) { 4260 info = &rtw89_disabled_dm_infos[i]; 4261 disabled = BIT(info->type) & hal->disabled_dm_bitmap; 4262 4263 p += scnprintf(p, end - p, "[%d] %s: %c\n", info->type, 4264 info->name, 4265 disabled ? 'X' : 'O'); 4266 } 4267 4268 return p - buf; 4269 } 4270 4271 static ssize_t 4272 rtw89_debug_priv_disable_dm_set(struct rtw89_dev *rtwdev, 4273 struct rtw89_debugfs_priv *debugfs_priv, 4274 const char *buf, size_t count) 4275 { 4276 u32 conf; 4277 int ret; 4278 4279 ret = kstrtou32(buf, 0, &conf); 4280 if (ret) 4281 return -EINVAL; 4282 4283 rtw89_debug_disable_dm_cfg_bmap(rtwdev, conf); 4284 4285 return count; 4286 } 4287 4288 static void rtw89_debug_mlo_mode_set_mlsr(struct rtw89_dev *rtwdev, 4289 unsigned int link_id) 4290 { 4291 struct ieee80211_vif *vif; 4292 struct rtw89_vif *rtwvif; 4293 4294 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4295 vif = rtwvif_to_vif(rtwvif); 4296 if (!ieee80211_vif_is_mld(vif)) 4297 continue; 4298 4299 rtw89_core_mlsr_switch(rtwdev, rtwvif, link_id); 4300 } 4301 } 4302 4303 static ssize_t 4304 rtw89_debug_priv_mlo_mode_get(struct rtw89_dev *rtwdev, 4305 struct rtw89_debugfs_priv *debugfs_priv, 4306 char *buf, size_t bufsz) 4307 { 4308 bool mlo_dm_dis = rtwdev->hal.disabled_dm_bitmap & BIT(RTW89_DM_MLO); 4309 char *p = buf, *end = buf + bufsz; 4310 struct ieee80211_vif *vif; 4311 struct rtw89_vif *rtwvif; 4312 int count = 0; 4313 4314 p += scnprintf(p, end - p, "MLD(s) status: (MLO DM: %s)\n", 4315 str_disable_enable(mlo_dm_dis)); 4316 4317 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 4318 vif = rtwvif_to_vif(rtwvif); 4319 if (!ieee80211_vif_is_mld(vif)) 4320 continue; 4321 4322 p += scnprintf(p, end - p, 4323 "\t#%u: MLO mode %x, valid 0x%x, active 0x%x\n", 4324 count++, rtwvif->mlo_mode, vif->valid_links, 4325 vif->active_links); 4326 } 4327 4328 if (count == 0) 4329 p += scnprintf(p, end - p, "\t(None)\n"); 4330 4331 return p - buf; 4332 } 4333 4334 static ssize_t 4335 rtw89_debug_priv_mlo_mode_set(struct rtw89_dev *rtwdev, 4336 struct rtw89_debugfs_priv *debugfs_priv, 4337 const char *buf, size_t count) 4338 { 4339 u8 num, mlo_mode; 4340 u32 argv; 4341 4342 num = sscanf(buf, "%hhx %u", &mlo_mode, &argv); 4343 if (num != 2) 4344 return -EINVAL; 4345 4346 rtw89_debug_disable_dm_set_flag(rtwdev, RTW89_DM_MLO); 4347 4348 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Set MLO mode to %x\n", mlo_mode); 4349 4350 switch (mlo_mode) { 4351 case RTW89_MLO_MODE_MLSR: 4352 rtw89_debug_mlo_mode_set_mlsr(rtwdev, argv); 4353 break; 4354 default: 4355 rtw89_debug(rtwdev, RTW89_DBG_STATE, "Unsupported MLO mode\n"); 4356 rtw89_debug_disable_dm_clr_flag(rtwdev, RTW89_DM_MLO); 4357 4358 return -EOPNOTSUPP; 4359 } 4360 4361 return count; 4362 } 4363 4364 static ssize_t 4365 rtw89_debug_priv_beacon_info_get(struct rtw89_dev *rtwdev, 4366 struct rtw89_debugfs_priv *debugfs_priv, 4367 char *buf, size_t bufsz) 4368 { 4369 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat; 4370 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track; 4371 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat; 4372 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist; 4373 u16 upper, lower = bcn_stat->tbtt_tu_min; 4374 char *p = buf, *end = buf + bufsz; 4375 u16 *drift = bcn_stat->drift; 4376 u8 bcn_num = bcn_stat->num; 4377 u8 count; 4378 u8 i; 4379 4380 p += scnprintf(p, end - p, "[Beacon info]\n"); 4381 p += scnprintf(p, end - p, "count: %u\n", pkt_stat->beacon_nr); 4382 p += scnprintf(p, end - p, "interval: %u\n", bcn_track->beacon_int); 4383 p += scnprintf(p, end - p, "dtim: %u\n", bcn_track->dtim); 4384 p += scnprintf(p, end - p, "raw rssi: %lu\n", 4385 ewma_rssi_read(&rtwdev->phystat.bcn_rssi)); 4386 p += scnprintf(p, end - p, "hw rate: %u\n", pkt_stat->beacon_rate); 4387 p += scnprintf(p, end - p, "length: %u\n", pkt_stat->beacon_len); 4388 4389 p += scnprintf(p, end - p, "\n[Distribution]\n"); 4390 p += scnprintf(p, end - p, "tbtt\n"); 4391 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) { 4392 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1; 4393 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1) 4394 upper = max(upper, bcn_stat->tbtt_tu_max); 4395 4396 p += scnprintf(p, end - p, "%02u - %02u: %u\n", 4397 lower, upper, bcn_dist->bins[i]); 4398 4399 lower = upper + 1; 4400 } 4401 4402 p += scnprintf(p, end - p, "\ndrift\n"); 4403 4404 for (i = 0; i < bcn_num; i += count) { 4405 count = 1; 4406 while (i + count < bcn_num && drift[i] == drift[i + count]) 4407 count++; 4408 4409 p += scnprintf(p, end - p, "%u: %u\n", drift[i], count); 4410 } 4411 p += scnprintf(p, end - p, "\nlower bound: %u\n", bcn_dist->lower_bound); 4412 p += scnprintf(p, end - p, "upper bound: %u\n", bcn_dist->upper_bound); 4413 p += scnprintf(p, end - p, "outlier count: %u\n", bcn_dist->outlier_count); 4414 4415 p += scnprintf(p, end - p, "\n[Tracking]\n"); 4416 p += scnprintf(p, end - p, "tbtt offset: %u\n", bcn_track->tbtt_offset); 4417 p += scnprintf(p, end - p, "bcn timeout: %u\n", bcn_track->bcn_timeout); 4418 4419 return p - buf; 4420 } 4421 4422 #define rtw89_debug_priv_get(name, opts...) \ 4423 { \ 4424 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4425 .opt = { opts }, \ 4426 } 4427 4428 #define rtw89_debug_priv_set(name, opts...) \ 4429 { \ 4430 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4431 .opt = { opts }, \ 4432 } 4433 4434 #define rtw89_debug_priv_select_and_get(name, opts...) \ 4435 { \ 4436 .cb_write = rtw89_debug_priv_ ##name## _select, \ 4437 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4438 .opt = { opts }, \ 4439 } 4440 4441 #define rtw89_debug_priv_set_and_get(name, opts...) \ 4442 { \ 4443 .cb_write = rtw89_debug_priv_ ##name## _set, \ 4444 .cb_read = rtw89_debug_priv_ ##name## _get, \ 4445 .opt = { opts }, \ 4446 } 4447 4448 #define RSIZE_8K .rsize = 0x2000 4449 #define RSIZE_12K .rsize = 0x3000 4450 #define RSIZE_16K .rsize = 0x4000 4451 #define RSIZE_20K .rsize = 0x5000 4452 #define RSIZE_32K .rsize = 0x8000 4453 #define RSIZE_64K .rsize = 0x10000 4454 #define RSIZE_128K .rsize = 0x20000 4455 #define RSIZE_1M .rsize = 0x100000 4456 #define RLOCK .rlock = 1 4457 #define WLOCK .wlock = 1 4458 #define RWLOCK RLOCK, WLOCK 4459 4460 static const struct rtw89_debugfs rtw89_debugfs_templ = { 4461 .read_reg = rtw89_debug_priv_select_and_get(read_reg), 4462 .write_reg = rtw89_debug_priv_set(write_reg), 4463 .read_rf = rtw89_debug_priv_select_and_get(read_rf), 4464 .write_rf = rtw89_debug_priv_set(write_rf), 4465 .rf_reg_dump = rtw89_debug_priv_get(rf_reg_dump, RSIZE_8K), 4466 .txpwr_table = rtw89_debug_priv_get(txpwr_table, RSIZE_20K, RLOCK), 4467 .mac_reg_dump = rtw89_debug_priv_select_and_get(mac_reg_dump, RSIZE_128K), 4468 .mac_mem_dump = rtw89_debug_priv_select_and_get(mac_mem_dump, RSIZE_16K, RLOCK), 4469 .mac_dbg_port_dump = rtw89_debug_priv_select_and_get(mac_dbg_port_dump, RSIZE_1M), 4470 .send_h2c = rtw89_debug_priv_set(send_h2c), 4471 .early_h2c = rtw89_debug_priv_set_and_get(early_h2c, RWLOCK), 4472 .fw_crash = rtw89_debug_priv_set_and_get(fw_crash, WLOCK), 4473 .btc_info = rtw89_debug_priv_get(btc_info, RSIZE_12K), 4474 .btc_manual = rtw89_debug_priv_set(btc_manual), 4475 .fw_log_manual = rtw89_debug_priv_set(fw_log_manual, WLOCK), 4476 .phy_info = rtw89_debug_priv_get(phy_info), 4477 .stations = rtw89_debug_priv_get(stations, RLOCK), 4478 .disable_dm = rtw89_debug_priv_set_and_get(disable_dm, RWLOCK), 4479 .mlo_mode = rtw89_debug_priv_set_and_get(mlo_mode, RWLOCK), 4480 .beacon_info = rtw89_debug_priv_get(beacon_info), 4481 }; 4482 4483 #define rtw89_debugfs_add(name, mode, fopname, parent) \ 4484 do { \ 4485 struct rtw89_debugfs_priv *priv = &rtwdev->debugfs->name; \ 4486 priv->rtwdev = rtwdev; \ 4487 if (IS_ERR(debugfs_create_file(#name, mode, parent, priv, \ 4488 &file_ops_ ##fopname))) \ 4489 pr_debug("Unable to initialize debugfs:%s\n", #name); \ 4490 } while (0) 4491 4492 #define rtw89_debugfs_add_w(name) \ 4493 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir) 4494 #define rtw89_debugfs_add_rw(name) \ 4495 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir) 4496 #define rtw89_debugfs_add_r(name) \ 4497 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir) 4498 4499 static 4500 void rtw89_debugfs_add_sec0(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4501 { 4502 rtw89_debugfs_add_rw(read_reg); 4503 rtw89_debugfs_add_w(write_reg); 4504 rtw89_debugfs_add_rw(read_rf); 4505 rtw89_debugfs_add_w(write_rf); 4506 rtw89_debugfs_add_r(rf_reg_dump); 4507 rtw89_debugfs_add_r(txpwr_table); 4508 rtw89_debugfs_add_rw(mac_reg_dump); 4509 rtw89_debugfs_add_rw(mac_mem_dump); 4510 rtw89_debugfs_add_rw(mac_dbg_port_dump); 4511 } 4512 4513 static 4514 void rtw89_debugfs_add_sec1(struct rtw89_dev *rtwdev, struct dentry *debugfs_topdir) 4515 { 4516 rtw89_debugfs_add_w(send_h2c); 4517 rtw89_debugfs_add_rw(early_h2c); 4518 rtw89_debugfs_add_rw(fw_crash); 4519 rtw89_debugfs_add_r(btc_info); 4520 rtw89_debugfs_add_w(btc_manual); 4521 rtw89_debugfs_add_w(fw_log_manual); 4522 rtw89_debugfs_add_r(phy_info); 4523 rtw89_debugfs_add_r(stations); 4524 rtw89_debugfs_add_rw(disable_dm); 4525 rtw89_debugfs_add_rw(mlo_mode); 4526 rtw89_debugfs_add_r(beacon_info); 4527 } 4528 4529 void rtw89_debugfs_init(struct rtw89_dev *rtwdev) 4530 { 4531 struct dentry *debugfs_topdir; 4532 4533 rtwdev->debugfs = kmemdup(&rtw89_debugfs_templ, 4534 sizeof(rtw89_debugfs_templ), GFP_KERNEL); 4535 if (!rtwdev->debugfs) 4536 return; 4537 4538 debugfs_topdir = debugfs_create_dir("rtw89", 4539 rtwdev->hw->wiphy->debugfsdir); 4540 4541 rtw89_debugfs_add_sec0(rtwdev, debugfs_topdir); 4542 rtw89_debugfs_add_sec1(rtwdev, debugfs_topdir); 4543 } 4544 4545 void rtw89_debugfs_deinit(struct rtw89_dev *rtwdev) 4546 { 4547 kfree(rtwdev->debugfs); 4548 } 4549 #endif 4550 4551 #ifdef CONFIG_RTW89_DEBUGMSG 4552 void rtw89_debug(struct rtw89_dev *rtwdev, enum rtw89_debug_mask mask, 4553 const char *fmt, ...) 4554 { 4555 struct va_format vaf = { 4556 .fmt = fmt, 4557 }; 4558 4559 va_list args; 4560 4561 va_start(args, fmt); 4562 vaf.va = &args; 4563 4564 if (rtw89_debug_mask & mask) 4565 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf); 4566 4567 va_end(args); 4568 } 4569 EXPORT_SYMBOL(rtw89_debug); 4570 #endif 4571