1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 struct rtw89_mac_gen_def; 18 struct rtw89_phy_gen_def; 19 struct rtw89_efuse_block_cfg; 20 struct rtw89_fw_txpwr_track_cfg; 21 struct rtw89_phy_rfk_log_fmt; 22 23 extern const struct ieee80211_ops rtw89_ops; 24 25 #define MASKBYTE0 0xff 26 #define MASKBYTE1 0xff00 27 #define MASKBYTE2 0xff0000 28 #define MASKBYTE3 0xff000000 29 #define MASKBYTE4 0xff00000000ULL 30 #define MASKHWORD 0xffff0000 31 #define MASKLWORD 0x0000ffff 32 #define MASKDWORD 0xffffffff 33 #define RFREG_MASK 0xfffff 34 #define INV_RF_DATA 0xffffffff 35 36 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 37 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 38 #define CFO_TRACK_MAX_USER 64 39 #define MAX_RSSI 110 40 #define RSSI_FACTOR 1 41 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 42 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 43 #define DELTA_SWINGIDX_SIZE 30 44 45 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 46 #define RTW89_RADIOTAP_ROOM_EHT \ 47 (sizeof(struct ieee80211_radiotap_tlv) + \ 48 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 49 sizeof(struct ieee80211_radiotap_tlv) + \ 50 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 51 #define RTW89_RADIOTAP_ROOM \ 52 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 53 54 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 55 #define RTW89_HTC_VARIANT_HE 3 56 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 57 #define RTW89_HTC_VARIANT_HE_CID_OM 1 58 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 59 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 60 61 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 62 enum htc_om_channel_width { 63 HTC_OM_CHANNEL_WIDTH_20 = 0, 64 HTC_OM_CHANNEL_WIDTH_40 = 1, 65 HTC_OM_CHANNEL_WIDTH_80 = 2, 66 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 67 }; 68 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 69 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 70 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 71 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 72 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 73 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 74 75 #define RTW89_TF_PAD GENMASK(11, 0) 76 #define RTW89_TF_BASIC_USER_INFO_SZ 6 77 78 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 79 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 80 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 81 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 82 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 83 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 84 85 enum rtw89_subband { 86 RTW89_CH_2G = 0, 87 RTW89_CH_5G_BAND_1 = 1, 88 /* RTW89_CH_5G_BAND_2 = 2, unused */ 89 RTW89_CH_5G_BAND_3 = 3, 90 RTW89_CH_5G_BAND_4 = 4, 91 92 RTW89_CH_6G_BAND_IDX0, /* Low */ 93 RTW89_CH_6G_BAND_IDX1, /* Low */ 94 RTW89_CH_6G_BAND_IDX2, /* Mid */ 95 RTW89_CH_6G_BAND_IDX3, /* Mid */ 96 RTW89_CH_6G_BAND_IDX4, /* High */ 97 RTW89_CH_6G_BAND_IDX5, /* High */ 98 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 99 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 100 101 RTW89_SUBBAND_NR, 102 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 103 }; 104 105 enum rtw89_gain_offset { 106 RTW89_GAIN_OFFSET_2G_CCK, 107 RTW89_GAIN_OFFSET_2G_OFDM, 108 RTW89_GAIN_OFFSET_5G_LOW, 109 RTW89_GAIN_OFFSET_5G_MID, 110 RTW89_GAIN_OFFSET_5G_HIGH, 111 RTW89_GAIN_OFFSET_6G_L0, 112 RTW89_GAIN_OFFSET_6G_L1, 113 RTW89_GAIN_OFFSET_6G_M0, 114 RTW89_GAIN_OFFSET_6G_M1, 115 RTW89_GAIN_OFFSET_6G_H0, 116 RTW89_GAIN_OFFSET_6G_H1, 117 RTW89_GAIN_OFFSET_6G_UH0, 118 RTW89_GAIN_OFFSET_6G_UH1, 119 120 RTW89_GAIN_OFFSET_NR, 121 }; 122 123 enum rtw89_hci_type { 124 RTW89_HCI_TYPE_PCIE, 125 RTW89_HCI_TYPE_USB, 126 RTW89_HCI_TYPE_SDIO, 127 }; 128 129 enum rtw89_core_chip_id { 130 RTL8852A, 131 RTL8852B, 132 RTL8852C, 133 RTL8851B, 134 RTL8922A, 135 }; 136 137 enum rtw89_chip_gen { 138 RTW89_CHIP_AX, 139 RTW89_CHIP_BE, 140 141 RTW89_CHIP_GEN_NUM, 142 }; 143 144 enum rtw89_cv { 145 CHIP_CAV, 146 CHIP_CBV, 147 CHIP_CCV, 148 CHIP_CDV, 149 CHIP_CEV, 150 CHIP_CFV, 151 CHIP_CV_MAX, 152 CHIP_CV_INVALID = CHIP_CV_MAX, 153 }; 154 155 enum rtw89_bacam_ver { 156 RTW89_BACAM_V0, 157 RTW89_BACAM_V1, 158 159 RTW89_BACAM_V0_EXT = 99, 160 }; 161 162 enum rtw89_core_tx_type { 163 RTW89_CORE_TX_TYPE_DATA, 164 RTW89_CORE_TX_TYPE_MGMT, 165 RTW89_CORE_TX_TYPE_FWCMD, 166 }; 167 168 enum rtw89_core_rx_type { 169 RTW89_CORE_RX_TYPE_WIFI = 0, 170 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 171 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 172 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 173 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 174 RTW89_CORE_RX_TYPE_SS2FW = 5, 175 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 176 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 177 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 178 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 179 RTW89_CORE_RX_TYPE_C2H = 10, 180 RTW89_CORE_RX_TYPE_CSI = 11, 181 RTW89_CORE_RX_TYPE_CQI = 12, 182 RTW89_CORE_RX_TYPE_H2C = 13, 183 RTW89_CORE_RX_TYPE_FWDL = 14, 184 }; 185 186 enum rtw89_txq_flags { 187 RTW89_TXQ_F_AMPDU = 0, 188 RTW89_TXQ_F_BLOCK_BA = 1, 189 RTW89_TXQ_F_FORBID_BA = 2, 190 }; 191 192 enum rtw89_net_type { 193 RTW89_NET_TYPE_NO_LINK = 0, 194 RTW89_NET_TYPE_AD_HOC = 1, 195 RTW89_NET_TYPE_INFRA = 2, 196 RTW89_NET_TYPE_AP_MODE = 3, 197 }; 198 199 enum rtw89_wifi_role { 200 RTW89_WIFI_ROLE_NONE, 201 RTW89_WIFI_ROLE_STATION, 202 RTW89_WIFI_ROLE_AP, 203 RTW89_WIFI_ROLE_AP_VLAN, 204 RTW89_WIFI_ROLE_ADHOC, 205 RTW89_WIFI_ROLE_ADHOC_MASTER, 206 RTW89_WIFI_ROLE_MESH_POINT, 207 RTW89_WIFI_ROLE_MONITOR, 208 RTW89_WIFI_ROLE_P2P_DEVICE, 209 RTW89_WIFI_ROLE_P2P_CLIENT, 210 RTW89_WIFI_ROLE_P2P_GO, 211 RTW89_WIFI_ROLE_NAN, 212 RTW89_WIFI_ROLE_MLME_MAX 213 }; 214 215 enum rtw89_upd_mode { 216 RTW89_ROLE_CREATE, 217 RTW89_ROLE_REMOVE, 218 RTW89_ROLE_TYPE_CHANGE, 219 RTW89_ROLE_INFO_CHANGE, 220 RTW89_ROLE_CON_DISCONN, 221 RTW89_ROLE_BAND_SW, 222 RTW89_ROLE_FW_RESTORE, 223 }; 224 225 enum rtw89_self_role { 226 RTW89_SELF_ROLE_CLIENT, 227 RTW89_SELF_ROLE_AP, 228 RTW89_SELF_ROLE_AP_CLIENT 229 }; 230 231 enum rtw89_msk_sO_el { 232 RTW89_NO_MSK, 233 RTW89_SMA, 234 RTW89_TMA, 235 RTW89_BSSID 236 }; 237 238 enum rtw89_sch_tx_sel { 239 RTW89_SCH_TX_SEL_ALL, 240 RTW89_SCH_TX_SEL_HIQ, 241 RTW89_SCH_TX_SEL_MG0, 242 RTW89_SCH_TX_SEL_MACID, 243 }; 244 245 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 246 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 247 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 248 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 249 */ 250 enum rtw89_add_cam_sec_mode { 251 RTW89_ADDR_CAM_SEC_NONE = 0, 252 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 253 RTW89_ADDR_CAM_SEC_NORMAL = 2, 254 RTW89_ADDR_CAM_SEC_4GROUP = 3, 255 }; 256 257 enum rtw89_sec_key_type { 258 RTW89_SEC_KEY_TYPE_NONE = 0, 259 RTW89_SEC_KEY_TYPE_WEP40 = 1, 260 RTW89_SEC_KEY_TYPE_WEP104 = 2, 261 RTW89_SEC_KEY_TYPE_TKIP = 3, 262 RTW89_SEC_KEY_TYPE_WAPI = 4, 263 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 264 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 265 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 266 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 267 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 268 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 269 }; 270 271 enum rtw89_port { 272 RTW89_PORT_0 = 0, 273 RTW89_PORT_1 = 1, 274 RTW89_PORT_2 = 2, 275 RTW89_PORT_3 = 3, 276 RTW89_PORT_4 = 4, 277 RTW89_PORT_NUM 278 }; 279 280 enum rtw89_band { 281 RTW89_BAND_2G = 0, 282 RTW89_BAND_5G = 1, 283 RTW89_BAND_6G = 2, 284 RTW89_BAND_NUM, 285 }; 286 287 enum rtw89_hw_rate { 288 RTW89_HW_RATE_CCK1 = 0x0, 289 RTW89_HW_RATE_CCK2 = 0x1, 290 RTW89_HW_RATE_CCK5_5 = 0x2, 291 RTW89_HW_RATE_CCK11 = 0x3, 292 RTW89_HW_RATE_OFDM6 = 0x4, 293 RTW89_HW_RATE_OFDM9 = 0x5, 294 RTW89_HW_RATE_OFDM12 = 0x6, 295 RTW89_HW_RATE_OFDM18 = 0x7, 296 RTW89_HW_RATE_OFDM24 = 0x8, 297 RTW89_HW_RATE_OFDM36 = 0x9, 298 RTW89_HW_RATE_OFDM48 = 0xA, 299 RTW89_HW_RATE_OFDM54 = 0xB, 300 RTW89_HW_RATE_MCS0 = 0x80, 301 RTW89_HW_RATE_MCS1 = 0x81, 302 RTW89_HW_RATE_MCS2 = 0x82, 303 RTW89_HW_RATE_MCS3 = 0x83, 304 RTW89_HW_RATE_MCS4 = 0x84, 305 RTW89_HW_RATE_MCS5 = 0x85, 306 RTW89_HW_RATE_MCS6 = 0x86, 307 RTW89_HW_RATE_MCS7 = 0x87, 308 RTW89_HW_RATE_MCS8 = 0x88, 309 RTW89_HW_RATE_MCS9 = 0x89, 310 RTW89_HW_RATE_MCS10 = 0x8A, 311 RTW89_HW_RATE_MCS11 = 0x8B, 312 RTW89_HW_RATE_MCS12 = 0x8C, 313 RTW89_HW_RATE_MCS13 = 0x8D, 314 RTW89_HW_RATE_MCS14 = 0x8E, 315 RTW89_HW_RATE_MCS15 = 0x8F, 316 RTW89_HW_RATE_MCS16 = 0x90, 317 RTW89_HW_RATE_MCS17 = 0x91, 318 RTW89_HW_RATE_MCS18 = 0x92, 319 RTW89_HW_RATE_MCS19 = 0x93, 320 RTW89_HW_RATE_MCS20 = 0x94, 321 RTW89_HW_RATE_MCS21 = 0x95, 322 RTW89_HW_RATE_MCS22 = 0x96, 323 RTW89_HW_RATE_MCS23 = 0x97, 324 RTW89_HW_RATE_MCS24 = 0x98, 325 RTW89_HW_RATE_MCS25 = 0x99, 326 RTW89_HW_RATE_MCS26 = 0x9A, 327 RTW89_HW_RATE_MCS27 = 0x9B, 328 RTW89_HW_RATE_MCS28 = 0x9C, 329 RTW89_HW_RATE_MCS29 = 0x9D, 330 RTW89_HW_RATE_MCS30 = 0x9E, 331 RTW89_HW_RATE_MCS31 = 0x9F, 332 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 333 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 334 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 335 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 336 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 337 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 338 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 339 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 340 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 341 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 342 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 343 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 344 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 345 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 346 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 347 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 348 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 349 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 350 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 351 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 352 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 353 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 354 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 355 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 356 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 357 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 358 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 359 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 360 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 361 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 362 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 363 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 364 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 365 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 366 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 367 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 368 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 369 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 370 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 371 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 372 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 373 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 374 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 375 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 376 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 377 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 378 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 379 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 380 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 381 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 382 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 383 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 384 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 385 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 386 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 387 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 388 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 389 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 390 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 391 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 392 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 393 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 394 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 395 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 396 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 397 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 398 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 399 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 400 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 401 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 402 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 403 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 404 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 405 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 406 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 407 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 408 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 409 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 410 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 411 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 412 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 413 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 414 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 415 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 416 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 417 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 418 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 419 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 420 421 RTW89_HW_RATE_V1_MCS0 = 0x100, 422 RTW89_HW_RATE_V1_MCS1 = 0x101, 423 RTW89_HW_RATE_V1_MCS2 = 0x102, 424 RTW89_HW_RATE_V1_MCS3 = 0x103, 425 RTW89_HW_RATE_V1_MCS4 = 0x104, 426 RTW89_HW_RATE_V1_MCS5 = 0x105, 427 RTW89_HW_RATE_V1_MCS6 = 0x106, 428 RTW89_HW_RATE_V1_MCS7 = 0x107, 429 RTW89_HW_RATE_V1_MCS8 = 0x108, 430 RTW89_HW_RATE_V1_MCS9 = 0x109, 431 RTW89_HW_RATE_V1_MCS10 = 0x10A, 432 RTW89_HW_RATE_V1_MCS11 = 0x10B, 433 RTW89_HW_RATE_V1_MCS12 = 0x10C, 434 RTW89_HW_RATE_V1_MCS13 = 0x10D, 435 RTW89_HW_RATE_V1_MCS14 = 0x10E, 436 RTW89_HW_RATE_V1_MCS15 = 0x10F, 437 RTW89_HW_RATE_V1_MCS16 = 0x110, 438 RTW89_HW_RATE_V1_MCS17 = 0x111, 439 RTW89_HW_RATE_V1_MCS18 = 0x112, 440 RTW89_HW_RATE_V1_MCS19 = 0x113, 441 RTW89_HW_RATE_V1_MCS20 = 0x114, 442 RTW89_HW_RATE_V1_MCS21 = 0x115, 443 RTW89_HW_RATE_V1_MCS22 = 0x116, 444 RTW89_HW_RATE_V1_MCS23 = 0x117, 445 RTW89_HW_RATE_V1_MCS24 = 0x118, 446 RTW89_HW_RATE_V1_MCS25 = 0x119, 447 RTW89_HW_RATE_V1_MCS26 = 0x11A, 448 RTW89_HW_RATE_V1_MCS27 = 0x11B, 449 RTW89_HW_RATE_V1_MCS28 = 0x11C, 450 RTW89_HW_RATE_V1_MCS29 = 0x11D, 451 RTW89_HW_RATE_V1_MCS30 = 0x11E, 452 RTW89_HW_RATE_V1_MCS31 = 0x11F, 453 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 454 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 455 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 456 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 465 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 466 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 467 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 468 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 477 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 478 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 479 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 480 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 489 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 490 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 491 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 492 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 501 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 502 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 503 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 504 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 513 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 514 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 515 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 516 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 525 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 526 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 527 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 528 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 537 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 538 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 539 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 540 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 549 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 550 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 551 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 552 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 565 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 566 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 567 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 568 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 579 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 580 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 581 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 582 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 593 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 594 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 595 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 596 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 607 608 RTW89_HW_RATE_NR, 609 RTW89_HW_RATE_INVAL, 610 611 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 612 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 613 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 614 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 615 }; 616 617 /* 2G channels, 618 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 619 */ 620 #define RTW89_2G_CH_NUM 14 621 622 /* 5G channels, 623 * 36, 38, 40, 42, 44, 46, 48, 50, 624 * 52, 54, 56, 58, 60, 62, 64, 625 * 100, 102, 104, 106, 108, 110, 112, 114, 626 * 116, 118, 120, 122, 124, 126, 128, 130, 627 * 132, 134, 136, 138, 140, 142, 144, 628 * 149, 151, 153, 155, 157, 159, 161, 163, 629 * 165, 167, 169, 171, 173, 175, 177 630 */ 631 #define RTW89_5G_CH_NUM 53 632 633 /* 6G channels, 634 * 1, 3, 5, 7, 9, 11, 13, 15, 635 * 17, 19, 21, 23, 25, 27, 29, 33, 636 * 35, 37, 39, 41, 43, 45, 47, 49, 637 * 51, 53, 55, 57, 59, 61, 65, 67, 638 * 69, 71, 73, 75, 77, 79, 81, 83, 639 * 85, 87, 89, 91, 93, 97, 99, 101, 640 * 103, 105, 107, 109, 111, 113, 115, 117, 641 * 119, 121, 123, 125, 129, 131, 133, 135, 642 * 137, 139, 141, 143, 145, 147, 149, 151, 643 * 153, 155, 157, 161, 163, 165, 167, 169, 644 * 171, 173, 175, 177, 179, 181, 183, 185, 645 * 187, 189, 193, 195, 197, 199, 201, 203, 646 * 205, 207, 209, 211, 213, 215, 217, 219, 647 * 221, 225, 227, 229, 231, 233, 235, 237, 648 * 239, 241, 243, 245, 247, 249, 251, 253, 649 */ 650 #define RTW89_6G_CH_NUM 120 651 652 enum rtw89_rate_section { 653 RTW89_RS_CCK, 654 RTW89_RS_OFDM, 655 RTW89_RS_MCS, /* for HT/VHT/HE */ 656 RTW89_RS_HEDCM, 657 RTW89_RS_OFFSET, 658 RTW89_RS_NUM, 659 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 660 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 661 }; 662 663 enum rtw89_rate_offset_indexes { 664 RTW89_RATE_OFFSET_HE, 665 RTW89_RATE_OFFSET_VHT, 666 RTW89_RATE_OFFSET_HT, 667 RTW89_RATE_OFFSET_OFDM, 668 RTW89_RATE_OFFSET_CCK, 669 RTW89_RATE_OFFSET_DLRU_EHT, 670 RTW89_RATE_OFFSET_DLRU_HE, 671 RTW89_RATE_OFFSET_EHT, 672 __RTW89_RATE_OFFSET_NUM, 673 674 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 675 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 676 }; 677 678 enum rtw89_rate_num { 679 RTW89_RATE_CCK_NUM = 4, 680 RTW89_RATE_OFDM_NUM = 8, 681 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 682 683 RTW89_RATE_MCS_NUM_AX = 12, 684 RTW89_RATE_MCS_NUM_BE = 16, 685 __RTW89_RATE_MCS_NUM = 16, 686 }; 687 688 enum rtw89_nss { 689 RTW89_NSS_1 = 0, 690 RTW89_NSS_2 = 1, 691 /* HE DCM only support 1ss and 2ss */ 692 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 693 RTW89_NSS_3 = 2, 694 RTW89_NSS_4 = 3, 695 RTW89_NSS_NUM, 696 }; 697 698 enum rtw89_ntx { 699 RTW89_1TX = 0, 700 RTW89_2TX = 1, 701 RTW89_NTX_NUM, 702 }; 703 704 enum rtw89_beamforming_type { 705 RTW89_NONBF = 0, 706 RTW89_BF = 1, 707 RTW89_BF_NUM, 708 }; 709 710 enum rtw89_ofdma_type { 711 RTW89_NON_OFDMA = 0, 712 RTW89_OFDMA = 1, 713 RTW89_OFDMA_NUM, 714 }; 715 716 enum rtw89_regulation_type { 717 RTW89_WW = 0, 718 RTW89_ETSI = 1, 719 RTW89_FCC = 2, 720 RTW89_MKK = 3, 721 RTW89_NA = 4, 722 RTW89_IC = 5, 723 RTW89_KCC = 6, 724 RTW89_ACMA = 7, 725 RTW89_NCC = 8, 726 RTW89_MEXICO = 9, 727 RTW89_CHILE = 10, 728 RTW89_UKRAINE = 11, 729 RTW89_CN = 12, 730 RTW89_QATAR = 13, 731 RTW89_UK = 14, 732 RTW89_THAILAND = 15, 733 RTW89_REGD_NUM, 734 }; 735 736 enum rtw89_reg_6ghz_power { 737 RTW89_REG_6GHZ_POWER_VLP = 0, 738 RTW89_REG_6GHZ_POWER_LPI = 1, 739 RTW89_REG_6GHZ_POWER_STD = 2, 740 741 NUM_OF_RTW89_REG_6GHZ_POWER, 742 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 743 }; 744 745 enum rtw89_fw_pkt_ofld_type { 746 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 747 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 748 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 749 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 750 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 751 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 752 RTW89_PKT_OFLD_TYPE_NDP = 6, 753 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 754 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 755 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 756 RTW89_PKT_OFLD_TYPE_NUM, 757 }; 758 759 struct rtw89_txpwr_byrate { 760 s8 cck[RTW89_RATE_CCK_NUM]; 761 s8 ofdm[RTW89_RATE_OFDM_NUM]; 762 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 763 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 764 s8 offset[__RTW89_RATE_OFFSET_NUM]; 765 s8 trap; 766 }; 767 768 struct rtw89_rate_desc { 769 enum rtw89_nss nss; 770 enum rtw89_rate_section rs; 771 enum rtw89_ofdma_type ofdma; 772 u8 idx; 773 }; 774 775 #define PHY_STS_HDR_LEN 8 776 #define RF_PATH_MAX 4 777 #define RTW89_MAX_PPDU_CNT 8 778 struct rtw89_rx_phy_ppdu { 779 void *buf; 780 u32 len; 781 u8 rssi_avg; 782 u8 rssi[RF_PATH_MAX]; 783 u8 mac_id; 784 u8 chan_idx; 785 u8 ie; 786 u16 rate; 787 struct { 788 bool has; 789 u8 avg_snr; 790 u8 evm_max; 791 u8 evm_min; 792 } ofdm; 793 bool to_self; 794 bool valid; 795 }; 796 797 enum rtw89_mac_idx { 798 RTW89_MAC_0 = 0, 799 RTW89_MAC_1 = 1, 800 }; 801 802 enum rtw89_phy_idx { 803 RTW89_PHY_0 = 0, 804 RTW89_PHY_1 = 1, 805 RTW89_PHY_MAX 806 }; 807 808 enum rtw89_sub_entity_idx { 809 RTW89_SUB_ENTITY_0 = 0, 810 RTW89_SUB_ENTITY_1 = 1, 811 812 NUM_OF_RTW89_SUB_ENTITY, 813 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 814 }; 815 816 enum rtw89_rf_path { 817 RF_PATH_A = 0, 818 RF_PATH_B = 1, 819 RF_PATH_C = 2, 820 RF_PATH_D = 3, 821 RF_PATH_AB, 822 RF_PATH_AC, 823 RF_PATH_AD, 824 RF_PATH_BC, 825 RF_PATH_BD, 826 RF_PATH_CD, 827 RF_PATH_ABC, 828 RF_PATH_ABD, 829 RF_PATH_ACD, 830 RF_PATH_BCD, 831 RF_PATH_ABCD, 832 }; 833 834 enum rtw89_rf_path_bit { 835 RF_A = BIT(0), 836 RF_B = BIT(1), 837 RF_C = BIT(2), 838 RF_D = BIT(3), 839 840 RF_AB = (RF_A | RF_B), 841 RF_AC = (RF_A | RF_C), 842 RF_AD = (RF_A | RF_D), 843 RF_BC = (RF_B | RF_C), 844 RF_BD = (RF_B | RF_D), 845 RF_CD = (RF_C | RF_D), 846 847 RF_ABC = (RF_A | RF_B | RF_C), 848 RF_ABD = (RF_A | RF_B | RF_D), 849 RF_ACD = (RF_A | RF_C | RF_D), 850 RF_BCD = (RF_B | RF_C | RF_D), 851 852 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 853 }; 854 855 enum rtw89_bandwidth { 856 RTW89_CHANNEL_WIDTH_20 = 0, 857 RTW89_CHANNEL_WIDTH_40 = 1, 858 RTW89_CHANNEL_WIDTH_80 = 2, 859 RTW89_CHANNEL_WIDTH_160 = 3, 860 RTW89_CHANNEL_WIDTH_320 = 4, 861 862 /* keep index order above */ 863 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 864 865 RTW89_CHANNEL_WIDTH_80_80 = 5, 866 RTW89_CHANNEL_WIDTH_5 = 6, 867 RTW89_CHANNEL_WIDTH_10 = 7, 868 }; 869 870 enum rtw89_ps_mode { 871 RTW89_PS_MODE_NONE = 0, 872 RTW89_PS_MODE_RFOFF = 1, 873 RTW89_PS_MODE_CLK_GATED = 2, 874 RTW89_PS_MODE_PWR_GATED = 3, 875 }; 876 877 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 878 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 879 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 880 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 881 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 882 883 enum rtw89_ru_bandwidth { 884 RTW89_RU26 = 0, 885 RTW89_RU52 = 1, 886 RTW89_RU106 = 2, 887 RTW89_RU52_26 = 3, 888 RTW89_RU106_26 = 4, 889 RTW89_RU_NUM, 890 }; 891 892 enum rtw89_sc_offset { 893 RTW89_SC_DONT_CARE = 0, 894 RTW89_SC_20_UPPER = 1, 895 RTW89_SC_20_LOWER = 2, 896 RTW89_SC_20_UPMOST = 3, 897 RTW89_SC_20_LOWEST = 4, 898 RTW89_SC_20_UP2X = 5, 899 RTW89_SC_20_LOW2X = 6, 900 RTW89_SC_20_UP3X = 7, 901 RTW89_SC_20_LOW3X = 8, 902 RTW89_SC_40_UPPER = 9, 903 RTW89_SC_40_LOWER = 10, 904 }; 905 906 enum rtw89_wow_flags { 907 RTW89_WOW_FLAG_EN_MAGIC_PKT, 908 RTW89_WOW_FLAG_EN_REKEY_PKT, 909 RTW89_WOW_FLAG_EN_DISCONNECT, 910 RTW89_WOW_FLAG_NUM, 911 }; 912 913 struct rtw89_chan { 914 u8 channel; 915 u8 primary_channel; 916 enum rtw89_band band_type; 917 enum rtw89_bandwidth band_width; 918 919 /* The follow-up are derived from the above. We must ensure that it 920 * is assigned correctly in rtw89_chan_create() if new one is added. 921 */ 922 u32 freq; 923 enum rtw89_subband subband_type; 924 enum rtw89_sc_offset pri_ch_idx; 925 u8 pri_sb_idx; 926 }; 927 928 struct rtw89_chan_rcd { 929 u8 prev_primary_channel; 930 enum rtw89_band prev_band_type; 931 bool band_changed; 932 }; 933 934 struct rtw89_channel_help_params { 935 u32 tx_en; 936 }; 937 938 struct rtw89_port_reg { 939 u32 port_cfg; 940 u32 tbtt_prohib; 941 u32 bcn_area; 942 u32 bcn_early; 943 u32 tbtt_early; 944 u32 tbtt_agg; 945 u32 bcn_space; 946 u32 bcn_forcetx; 947 u32 bcn_err_cnt; 948 u32 bcn_err_flag; 949 u32 dtim_ctrl; 950 u32 tbtt_shift; 951 u32 bcn_cnt_tmr; 952 u32 tsftr_l; 953 u32 tsftr_h; 954 u32 md_tsft; 955 u32 bss_color; 956 u32 mbssid; 957 u32 mbssid_drop; 958 u32 tsf_sync; 959 u32 hiq_win[RTW89_PORT_NUM]; 960 }; 961 962 struct rtw89_txwd_body { 963 __le32 dword0; 964 __le32 dword1; 965 __le32 dword2; 966 __le32 dword3; 967 __le32 dword4; 968 __le32 dword5; 969 } __packed; 970 971 struct rtw89_txwd_body_v1 { 972 __le32 dword0; 973 __le32 dword1; 974 __le32 dword2; 975 __le32 dword3; 976 __le32 dword4; 977 __le32 dword5; 978 __le32 dword6; 979 __le32 dword7; 980 } __packed; 981 982 struct rtw89_txwd_body_v2 { 983 __le32 dword0; 984 __le32 dword1; 985 __le32 dword2; 986 __le32 dword3; 987 __le32 dword4; 988 __le32 dword5; 989 __le32 dword6; 990 __le32 dword7; 991 } __packed; 992 993 struct rtw89_txwd_info { 994 __le32 dword0; 995 __le32 dword1; 996 __le32 dword2; 997 __le32 dword3; 998 __le32 dword4; 999 __le32 dword5; 1000 } __packed; 1001 1002 struct rtw89_txwd_info_v2 { 1003 __le32 dword0; 1004 __le32 dword1; 1005 __le32 dword2; 1006 __le32 dword3; 1007 __le32 dword4; 1008 __le32 dword5; 1009 __le32 dword6; 1010 __le32 dword7; 1011 } __packed; 1012 1013 struct rtw89_rx_desc_info { 1014 u16 pkt_size; 1015 u8 pkt_type; 1016 u8 drv_info_size; 1017 u8 phy_rpt_size; 1018 u8 hdr_cnv_size; 1019 u8 shift; 1020 u8 wl_hd_iv_len; 1021 bool long_rxdesc; 1022 bool bb_sel; 1023 bool mac_info_valid; 1024 u16 data_rate; 1025 u8 gi_ltf; 1026 u8 bw; 1027 u32 free_run_cnt; 1028 u8 user_id; 1029 bool sr_en; 1030 u8 ppdu_cnt; 1031 u8 ppdu_type; 1032 bool icv_err; 1033 bool crc32_err; 1034 bool hw_dec; 1035 bool sw_dec; 1036 bool addr1_match; 1037 u8 frag; 1038 u16 seq; 1039 u8 frame_type; 1040 u8 rx_pl_id; 1041 bool addr_cam_valid; 1042 u8 addr_cam_id; 1043 u8 sec_cam_id; 1044 u8 mac_id; 1045 u16 offset; 1046 u16 rxd_len; 1047 bool ready; 1048 }; 1049 1050 struct rtw89_rxdesc_short { 1051 __le32 dword0; 1052 __le32 dword1; 1053 __le32 dword2; 1054 __le32 dword3; 1055 } __packed; 1056 1057 struct rtw89_rxdesc_short_v2 { 1058 __le32 dword0; 1059 __le32 dword1; 1060 __le32 dword2; 1061 __le32 dword3; 1062 __le32 dword4; 1063 __le32 dword5; 1064 } __packed; 1065 1066 struct rtw89_rxdesc_long { 1067 __le32 dword0; 1068 __le32 dword1; 1069 __le32 dword2; 1070 __le32 dword3; 1071 __le32 dword4; 1072 __le32 dword5; 1073 __le32 dword6; 1074 __le32 dword7; 1075 } __packed; 1076 1077 struct rtw89_rxdesc_long_v2 { 1078 __le32 dword0; 1079 __le32 dword1; 1080 __le32 dword2; 1081 __le32 dword3; 1082 __le32 dword4; 1083 __le32 dword5; 1084 __le32 dword6; 1085 __le32 dword7; 1086 __le32 dword8; 1087 __le32 dword9; 1088 } __packed; 1089 1090 struct rtw89_tx_desc_info { 1091 u16 pkt_size; 1092 u8 wp_offset; 1093 u8 mac_id; 1094 u8 qsel; 1095 u8 ch_dma; 1096 u8 hdr_llc_len; 1097 bool is_bmc; 1098 bool en_wd_info; 1099 bool wd_page; 1100 bool use_rate; 1101 bool dis_data_fb; 1102 bool tid_indicate; 1103 bool agg_en; 1104 bool bk; 1105 u8 ampdu_density; 1106 u8 ampdu_num; 1107 bool sec_en; 1108 u8 addr_info_nr; 1109 u8 sec_keyid; 1110 u8 sec_type; 1111 u8 sec_cam_idx; 1112 u8 sec_seq[6]; 1113 u16 data_rate; 1114 u16 data_retry_lowest_rate; 1115 bool fw_dl; 1116 u16 seq; 1117 bool a_ctrl_bsr; 1118 u8 hw_ssn_sel; 1119 #define RTW89_MGMT_HW_SSN_SEL 1 1120 u8 hw_seq_mode; 1121 #define RTW89_MGMT_HW_SEQ_MODE 1 1122 bool hiq; 1123 u8 port; 1124 bool er_cap; 1125 }; 1126 1127 struct rtw89_core_tx_request { 1128 enum rtw89_core_tx_type tx_type; 1129 1130 struct sk_buff *skb; 1131 struct ieee80211_vif *vif; 1132 struct ieee80211_sta *sta; 1133 struct rtw89_tx_desc_info desc_info; 1134 }; 1135 1136 struct rtw89_txq { 1137 struct list_head list; 1138 unsigned long flags; 1139 int wait_cnt; 1140 }; 1141 1142 struct rtw89_mac_ax_gnt { 1143 u8 gnt_bt_sw_en; 1144 u8 gnt_bt; 1145 u8 gnt_wl_sw_en; 1146 u8 gnt_wl; 1147 } __packed; 1148 1149 #define RTW89_MAC_AX_COEX_GNT_NR 2 1150 struct rtw89_mac_ax_coex_gnt { 1151 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1152 }; 1153 1154 enum rtw89_btc_ncnt { 1155 BTC_NCNT_POWER_ON = 0x0, 1156 BTC_NCNT_POWER_OFF, 1157 BTC_NCNT_INIT_COEX, 1158 BTC_NCNT_SCAN_START, 1159 BTC_NCNT_SCAN_FINISH, 1160 BTC_NCNT_SPECIAL_PACKET, 1161 BTC_NCNT_SWITCH_BAND, 1162 BTC_NCNT_RFK_TIMEOUT, 1163 BTC_NCNT_SHOW_COEX_INFO, 1164 BTC_NCNT_ROLE_INFO, 1165 BTC_NCNT_CONTROL, 1166 BTC_NCNT_RADIO_STATE, 1167 BTC_NCNT_CUSTOMERIZE, 1168 BTC_NCNT_WL_RFK, 1169 BTC_NCNT_WL_STA, 1170 BTC_NCNT_FWINFO, 1171 BTC_NCNT_TIMER, 1172 BTC_NCNT_NUM 1173 }; 1174 1175 enum rtw89_btc_btinfo { 1176 BTC_BTINFO_L0 = 0, 1177 BTC_BTINFO_L1, 1178 BTC_BTINFO_L2, 1179 BTC_BTINFO_L3, 1180 BTC_BTINFO_H0, 1181 BTC_BTINFO_H1, 1182 BTC_BTINFO_H2, 1183 BTC_BTINFO_H3, 1184 BTC_BTINFO_MAX 1185 }; 1186 1187 enum rtw89_btc_dcnt { 1188 BTC_DCNT_RUN = 0x0, 1189 BTC_DCNT_CX_RUNINFO, 1190 BTC_DCNT_RPT, 1191 BTC_DCNT_RPT_HANG, 1192 BTC_DCNT_CYCLE, 1193 BTC_DCNT_CYCLE_HANG, 1194 BTC_DCNT_W1, 1195 BTC_DCNT_W1_HANG, 1196 BTC_DCNT_B1, 1197 BTC_DCNT_B1_HANG, 1198 BTC_DCNT_TDMA_NONSYNC, 1199 BTC_DCNT_SLOT_NONSYNC, 1200 BTC_DCNT_BTCNT_HANG, 1201 BTC_DCNT_WL_SLOT_DRIFT, 1202 BTC_DCNT_WL_STA_LAST, 1203 BTC_DCNT_BT_SLOT_DRIFT, 1204 BTC_DCNT_BT_SLOT_FLOOD, 1205 BTC_DCNT_FDDT_TRIG, 1206 BTC_DCNT_E2G, 1207 BTC_DCNT_E2G_HANG, 1208 BTC_DCNT_NUM 1209 }; 1210 1211 enum rtw89_btc_wl_state_cnt { 1212 BTC_WCNT_SCANAP = 0x0, 1213 BTC_WCNT_DHCP, 1214 BTC_WCNT_EAPOL, 1215 BTC_WCNT_ARP, 1216 BTC_WCNT_SCBDUPDATE, 1217 BTC_WCNT_RFK_REQ, 1218 BTC_WCNT_RFK_GO, 1219 BTC_WCNT_RFK_REJECT, 1220 BTC_WCNT_RFK_TIMEOUT, 1221 BTC_WCNT_CH_UPDATE, 1222 BTC_WCNT_NUM 1223 }; 1224 1225 enum rtw89_btc_bt_state_cnt { 1226 BTC_BCNT_RETRY = 0x0, 1227 BTC_BCNT_REINIT, 1228 BTC_BCNT_REENABLE, 1229 BTC_BCNT_SCBDREAD, 1230 BTC_BCNT_RELINK, 1231 BTC_BCNT_IGNOWL, 1232 BTC_BCNT_INQPAG, 1233 BTC_BCNT_INQ, 1234 BTC_BCNT_PAGE, 1235 BTC_BCNT_ROLESW, 1236 BTC_BCNT_AFH, 1237 BTC_BCNT_INFOUPDATE, 1238 BTC_BCNT_INFOSAME, 1239 BTC_BCNT_SCBDUPDATE, 1240 BTC_BCNT_HIPRI_TX, 1241 BTC_BCNT_HIPRI_RX, 1242 BTC_BCNT_LOPRI_TX, 1243 BTC_BCNT_LOPRI_RX, 1244 BTC_BCNT_POLUT, 1245 BTC_BCNT_RATECHG, 1246 BTC_BCNT_NUM 1247 }; 1248 1249 enum rtw89_btc_bt_profile { 1250 BTC_BT_NOPROFILE = 0, 1251 BTC_BT_HFP = BIT(0), 1252 BTC_BT_HID = BIT(1), 1253 BTC_BT_A2DP = BIT(2), 1254 BTC_BT_PAN = BIT(3), 1255 BTC_PROFILE_MAX = 4, 1256 }; 1257 1258 struct rtw89_btc_ant_info { 1259 u8 type; /* shared, dedicated */ 1260 u8 num; 1261 u8 isolation; 1262 1263 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1264 u8 diversity: 1; 1265 u8 btg_pos: 2; 1266 u8 stream_cnt: 4; 1267 }; 1268 1269 enum rtw89_tfc_dir { 1270 RTW89_TFC_UL, 1271 RTW89_TFC_DL, 1272 }; 1273 1274 struct rtw89_btc_wl_smap { 1275 u32 busy: 1; 1276 u32 scan: 1; 1277 u32 connecting: 1; 1278 u32 roaming: 1; 1279 u32 _4way: 1; 1280 u32 rf_off: 1; 1281 u32 lps: 2; 1282 u32 ips: 1; 1283 u32 init_ok: 1; 1284 u32 traffic_dir : 2; 1285 u32 rf_off_pre: 1; 1286 u32 lps_pre: 2; 1287 }; 1288 1289 enum rtw89_tfc_lv { 1290 RTW89_TFC_IDLE, 1291 RTW89_TFC_ULTRA_LOW, 1292 RTW89_TFC_LOW, 1293 RTW89_TFC_MID, 1294 RTW89_TFC_HIGH, 1295 }; 1296 1297 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1298 DECLARE_EWMA(tp, 10, 2); 1299 1300 struct rtw89_traffic_stats { 1301 /* units in bytes */ 1302 u64 tx_unicast; 1303 u64 rx_unicast; 1304 u32 tx_avg_len; 1305 u32 rx_avg_len; 1306 1307 /* count for packets */ 1308 u64 tx_cnt; 1309 u64 rx_cnt; 1310 1311 /* units in Mbps */ 1312 u32 tx_throughput; 1313 u32 rx_throughput; 1314 u32 tx_throughput_raw; 1315 u32 rx_throughput_raw; 1316 1317 u32 rx_tf_acc; 1318 u32 rx_tf_periodic; 1319 1320 enum rtw89_tfc_lv tx_tfc_lv; 1321 enum rtw89_tfc_lv rx_tfc_lv; 1322 struct ewma_tp tx_ewma_tp; 1323 struct ewma_tp rx_ewma_tp; 1324 1325 u16 tx_rate; 1326 u16 rx_rate; 1327 }; 1328 1329 struct rtw89_btc_statistic { 1330 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1331 struct rtw89_traffic_stats traffic; 1332 }; 1333 1334 #define BTC_WL_RSSI_THMAX 4 1335 1336 struct rtw89_btc_wl_link_info { 1337 struct rtw89_btc_statistic stat; 1338 enum rtw89_tfc_dir dir; 1339 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1340 u8 mac_addr[ETH_ALEN]; 1341 u8 busy; 1342 u8 ch; 1343 u8 bw; 1344 u8 band; 1345 u8 role; 1346 u8 pid; 1347 u8 phy; 1348 u8 dtim_period; 1349 u8 mode; 1350 1351 u8 mac_id; 1352 u8 tx_retry; 1353 1354 u32 bcn_period; 1355 u32 busy_t; 1356 u32 tx_time; 1357 u32 client_cnt; 1358 u32 rx_rate_drop_cnt; 1359 1360 u32 active: 1; 1361 u32 noa: 1; 1362 u32 client_ps: 1; 1363 u32 connected: 2; 1364 }; 1365 1366 union rtw89_btc_wl_state_map { 1367 u32 val; 1368 struct rtw89_btc_wl_smap map; 1369 }; 1370 1371 struct rtw89_btc_bt_hfp_desc { 1372 u32 exist: 1; 1373 u32 type: 2; 1374 u32 rsvd: 29; 1375 }; 1376 1377 struct rtw89_btc_bt_hid_desc { 1378 u32 exist: 1; 1379 u32 slot_info: 2; 1380 u32 pair_cnt: 2; 1381 u32 type: 8; 1382 u32 rsvd: 19; 1383 }; 1384 1385 struct rtw89_btc_bt_a2dp_desc { 1386 u8 exist: 1; 1387 u8 exist_last: 1; 1388 u8 play_latency: 1; 1389 u8 type: 3; 1390 u8 active: 1; 1391 u8 sink: 1; 1392 1393 u8 bitpool; 1394 u16 vendor_id; 1395 u32 device_name; 1396 u32 flush_time; 1397 }; 1398 1399 struct rtw89_btc_bt_pan_desc { 1400 u32 exist: 1; 1401 u32 type: 1; 1402 u32 active: 1; 1403 u32 rsvd: 29; 1404 }; 1405 1406 struct rtw89_btc_bt_rfk_info { 1407 u32 run: 1; 1408 u32 req: 1; 1409 u32 timeout: 1; 1410 u32 rsvd: 29; 1411 }; 1412 1413 union rtw89_btc_bt_rfk_info_map { 1414 u32 val; 1415 struct rtw89_btc_bt_rfk_info map; 1416 }; 1417 1418 struct rtw89_btc_bt_ver_info { 1419 u32 fw_coex; /* match with which coex_ver */ 1420 u32 fw; 1421 }; 1422 1423 struct rtw89_btc_bool_sta_chg { 1424 u32 now: 1; 1425 u32 last: 1; 1426 u32 remain: 1; 1427 u32 srvd: 29; 1428 }; 1429 1430 struct rtw89_btc_u8_sta_chg { 1431 u8 now; 1432 u8 last; 1433 u8 remain; 1434 u8 rsvd; 1435 }; 1436 1437 struct rtw89_btc_wl_scan_info { 1438 u8 band[RTW89_PHY_MAX]; 1439 u8 phy_map; 1440 u8 rsvd; 1441 }; 1442 1443 struct rtw89_btc_wl_dbcc_info { 1444 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1445 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1446 u8 real_band[RTW89_PHY_MAX]; 1447 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1448 }; 1449 1450 struct rtw89_btc_wl_active_role { 1451 u8 connected: 1; 1452 u8 pid: 3; 1453 u8 phy: 1; 1454 u8 noa: 1; 1455 u8 band: 2; 1456 1457 u8 client_ps: 1; 1458 u8 bw: 7; 1459 1460 u8 role; 1461 u8 ch; 1462 1463 u16 tx_lvl; 1464 u16 rx_lvl; 1465 u16 tx_rate; 1466 u16 rx_rate; 1467 }; 1468 1469 struct rtw89_btc_wl_active_role_v1 { 1470 u8 connected: 1; 1471 u8 pid: 3; 1472 u8 phy: 1; 1473 u8 noa: 1; 1474 u8 band: 2; 1475 1476 u8 client_ps: 1; 1477 u8 bw: 7; 1478 1479 u8 role; 1480 u8 ch; 1481 1482 u16 tx_lvl; 1483 u16 rx_lvl; 1484 u16 tx_rate; 1485 u16 rx_rate; 1486 1487 u32 noa_duration; /* ms */ 1488 }; 1489 1490 struct rtw89_btc_wl_active_role_v2 { 1491 u8 connected: 1; 1492 u8 pid: 3; 1493 u8 phy: 1; 1494 u8 noa: 1; 1495 u8 band: 2; 1496 1497 u8 client_ps: 1; 1498 u8 bw: 7; 1499 1500 u8 role; 1501 u8 ch; 1502 1503 u32 noa_duration; /* ms */ 1504 }; 1505 1506 struct rtw89_btc_wl_role_info_bpos { 1507 u16 none: 1; 1508 u16 station: 1; 1509 u16 ap: 1; 1510 u16 vap: 1; 1511 u16 adhoc: 1; 1512 u16 adhoc_master: 1; 1513 u16 mesh: 1; 1514 u16 moniter: 1; 1515 u16 p2p_device: 1; 1516 u16 p2p_gc: 1; 1517 u16 p2p_go: 1; 1518 u16 nan: 1; 1519 }; 1520 1521 struct rtw89_btc_wl_scc_ctrl { 1522 u8 null_role1; 1523 u8 null_role2; 1524 u8 ebt_null; /* if tx null at EBT slot */ 1525 }; 1526 1527 union rtw89_btc_wl_role_info_map { 1528 u16 val; 1529 struct rtw89_btc_wl_role_info_bpos role; 1530 }; 1531 1532 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1533 u8 connect_cnt; 1534 u8 link_mode; 1535 union rtw89_btc_wl_role_info_map role_map; 1536 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1537 }; 1538 1539 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1540 u8 connect_cnt; 1541 u8 link_mode; 1542 union rtw89_btc_wl_role_info_map role_map; 1543 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1544 u32 mrole_type; /* btc_wl_mrole_type */ 1545 u32 mrole_noa_duration; /* ms */ 1546 1547 u32 dbcc_en: 1; 1548 u32 dbcc_chg: 1; 1549 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1550 u32 link_mode_chg: 1; 1551 u32 rsvd: 27; 1552 }; 1553 1554 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1555 u8 connect_cnt; 1556 u8 link_mode; 1557 union rtw89_btc_wl_role_info_map role_map; 1558 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1559 u32 mrole_type; /* btc_wl_mrole_type */ 1560 u32 mrole_noa_duration; /* ms */ 1561 1562 u32 dbcc_en: 1; 1563 u32 dbcc_chg: 1; 1564 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1565 u32 link_mode_chg: 1; 1566 u32 rsvd: 27; 1567 }; 1568 1569 struct rtw89_btc_wl_ver_info { 1570 u32 fw_coex; /* match with which coex_ver */ 1571 u32 fw; 1572 u32 mac; 1573 u32 bb; 1574 u32 rf; 1575 }; 1576 1577 struct rtw89_btc_wl_afh_info { 1578 u8 en; 1579 u8 ch; 1580 u8 bw; 1581 u8 rsvd; 1582 } __packed; 1583 1584 struct rtw89_btc_wl_rfk_info { 1585 u32 state: 2; 1586 u32 path_map: 4; 1587 u32 phy_map: 2; 1588 u32 band: 2; 1589 u32 type: 8; 1590 u32 rsvd: 14; 1591 }; 1592 1593 struct rtw89_btc_bt_smap { 1594 u32 connect: 1; 1595 u32 ble_connect: 1; 1596 u32 acl_busy: 1; 1597 u32 sco_busy: 1; 1598 u32 mesh_busy: 1; 1599 u32 inq_pag: 1; 1600 }; 1601 1602 union rtw89_btc_bt_state_map { 1603 u32 val; 1604 struct rtw89_btc_bt_smap map; 1605 }; 1606 1607 #define BTC_BT_RSSI_THMAX 4 1608 #define BTC_BT_AFH_GROUP 12 1609 #define BTC_BT_AFH_LE_GROUP 5 1610 1611 struct rtw89_btc_bt_link_info { 1612 struct rtw89_btc_u8_sta_chg profile_cnt; 1613 struct rtw89_btc_bool_sta_chg multi_link; 1614 struct rtw89_btc_bool_sta_chg relink; 1615 struct rtw89_btc_bt_hfp_desc hfp_desc; 1616 struct rtw89_btc_bt_hid_desc hid_desc; 1617 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1618 struct rtw89_btc_bt_pan_desc pan_desc; 1619 union rtw89_btc_bt_state_map status; 1620 1621 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1622 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1623 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1624 u8 afh_map[BTC_BT_AFH_GROUP]; 1625 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1626 1627 u32 role_sw: 1; 1628 u32 slave_role: 1; 1629 u32 afh_update: 1; 1630 u32 cqddr: 1; 1631 u32 rssi: 8; 1632 u32 tx_3m: 1; 1633 u32 rsvd: 19; 1634 }; 1635 1636 struct rtw89_btc_3rdcx_info { 1637 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1638 u8 hw_coex; 1639 u16 rsvd; 1640 }; 1641 1642 struct rtw89_btc_dm_emap { 1643 u32 init: 1; 1644 u32 pta_owner: 1; 1645 u32 wl_rfk_timeout: 1; 1646 u32 bt_rfk_timeout: 1; 1647 u32 wl_fw_hang: 1; 1648 u32 cycle_hang: 1; 1649 u32 w1_hang: 1; 1650 u32 b1_hang: 1; 1651 u32 tdma_no_sync: 1; 1652 u32 slot_no_sync: 1; 1653 u32 wl_slot_drift: 1; 1654 u32 bt_slot_drift: 1; 1655 u32 role_num_mismatch: 1; 1656 u32 null1_tx_late: 1; 1657 u32 bt_afh_conflict: 1; 1658 u32 bt_leafh_conflict: 1; 1659 u32 bt_slot_flood: 1; 1660 u32 wl_e2g_hang: 1; 1661 u32 wl_ver_mismatch: 1; 1662 u32 bt_ver_mismatch: 1; 1663 }; 1664 1665 union rtw89_btc_dm_error_map { 1666 u32 val; 1667 struct rtw89_btc_dm_emap map; 1668 }; 1669 1670 struct rtw89_btc_rf_para { 1671 u32 tx_pwr_freerun; 1672 u32 rx_gain_freerun; 1673 u32 tx_pwr_perpkt; 1674 u32 rx_gain_perpkt; 1675 }; 1676 1677 struct rtw89_btc_wl_nhm { 1678 u8 instant_wl_nhm_dbm; 1679 u8 instant_wl_nhm_per_mhz; 1680 u16 valid_record_times; 1681 s8 record_pwr[16]; 1682 u8 record_ratio[16]; 1683 s8 pwr; /* dbm_per_MHz */ 1684 u8 ratio; 1685 u8 current_status; 1686 u8 refresh; 1687 bool start_flag; 1688 s8 pwr_max; 1689 s8 pwr_min; 1690 }; 1691 1692 struct rtw89_btc_wl_info { 1693 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1694 struct rtw89_btc_wl_rfk_info rfk_info; 1695 struct rtw89_btc_wl_ver_info ver_info; 1696 struct rtw89_btc_wl_afh_info afh_info; 1697 struct rtw89_btc_wl_role_info role_info; 1698 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1699 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1700 struct rtw89_btc_wl_scan_info scan_info; 1701 struct rtw89_btc_wl_dbcc_info dbcc_info; 1702 struct rtw89_btc_rf_para rf_para; 1703 struct rtw89_btc_wl_nhm nhm; 1704 union rtw89_btc_wl_state_map status; 1705 1706 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1707 u8 rssi_level; 1708 u8 cn_report; 1709 u8 coex_mode; 1710 1711 bool scbd_change; 1712 u32 scbd; 1713 }; 1714 1715 struct rtw89_btc_module { 1716 struct rtw89_btc_ant_info ant; 1717 u8 rfe_type; 1718 u8 cv; 1719 1720 u8 bt_solo: 1; 1721 u8 bt_pos: 1; 1722 u8 switch_type: 1; 1723 u8 wa_type: 3; 1724 1725 u8 kt_ver_adie; 1726 }; 1727 1728 #define RTW89_BTC_DM_MAXSTEP 30 1729 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1730 1731 struct rtw89_btc_dm_step { 1732 u16 step[RTW89_BTC_DM_MAXSTEP]; 1733 u8 step_pos; 1734 bool step_ov; 1735 }; 1736 1737 struct rtw89_btc_init_info { 1738 struct rtw89_btc_module module; 1739 u8 wl_guard_ch; 1740 1741 u8 wl_only: 1; 1742 u8 wl_init_ok: 1; 1743 u8 dbcc_en: 1; 1744 u8 cx_other: 1; 1745 u8 bt_only: 1; 1746 1747 u16 rsvd; 1748 }; 1749 1750 struct rtw89_btc_wl_tx_limit_para { 1751 u16 enable; 1752 u32 tx_time; /* unit: us */ 1753 u16 tx_retry; 1754 }; 1755 1756 enum rtw89_btc_bt_scan_type { 1757 BTC_SCAN_INQ = 0, 1758 BTC_SCAN_PAGE, 1759 BTC_SCAN_BLE, 1760 BTC_SCAN_INIT, 1761 BTC_SCAN_TV, 1762 BTC_SCAN_ADV, 1763 BTC_SCAN_MAX1, 1764 }; 1765 1766 enum rtw89_btc_ble_scan_type { 1767 CXSCAN_BG = 0, 1768 CXSCAN_INIT, 1769 CXSCAN_LE, 1770 CXSCAN_MAX 1771 }; 1772 1773 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1774 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1775 1776 struct rtw89_btc_bt_scan_info_v1 { 1777 __le16 win; 1778 __le16 intvl; 1779 __le32 flags; 1780 } __packed; 1781 1782 struct rtw89_btc_bt_scan_info_v2 { 1783 __le16 win; 1784 __le16 intvl; 1785 } __packed; 1786 1787 struct rtw89_btc_fbtc_btscan_v1 { 1788 u8 fver; /* btc_ver::fcxbtscan */ 1789 u8 rsvd; 1790 __le16 rsvd2; 1791 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1792 } __packed; 1793 1794 struct rtw89_btc_fbtc_btscan_v2 { 1795 u8 fver; /* btc_ver::fcxbtscan */ 1796 u8 type; 1797 __le16 rsvd2; 1798 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1799 } __packed; 1800 1801 union rtw89_btc_fbtc_btscan { 1802 struct rtw89_btc_fbtc_btscan_v1 v1; 1803 struct rtw89_btc_fbtc_btscan_v2 v2; 1804 }; 1805 1806 struct rtw89_btc_bt_info { 1807 struct rtw89_btc_bt_link_info link_info; 1808 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1809 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1810 struct rtw89_btc_bt_ver_info ver_info; 1811 struct rtw89_btc_bool_sta_chg enable; 1812 struct rtw89_btc_bool_sta_chg inq_pag; 1813 struct rtw89_btc_rf_para rf_para; 1814 union rtw89_btc_bt_rfk_info_map rfk_info; 1815 1816 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1817 u8 rssi_level; 1818 1819 u32 scbd; 1820 u32 feature; 1821 1822 u32 mbx_avl: 1; 1823 u32 whql_test: 1; 1824 u32 igno_wl: 1; 1825 u32 reinit: 1; 1826 u32 ble_scan_en: 1; 1827 u32 btg_type: 1; 1828 u32 inq: 1; 1829 u32 pag: 1; 1830 u32 run_patch_code: 1; 1831 u32 hi_lna_rx: 1; 1832 u32 scan_rx_low_pri: 1; 1833 u32 scan_info_update: 1; 1834 u32 lna_constrain: 3; 1835 u32 rsvd: 17; 1836 }; 1837 1838 struct rtw89_btc_cx { 1839 struct rtw89_btc_wl_info wl; 1840 struct rtw89_btc_bt_info bt; 1841 struct rtw89_btc_3rdcx_info other; 1842 u32 state_map; 1843 u32 cnt_bt[BTC_BCNT_NUM]; 1844 u32 cnt_wl[BTC_WCNT_NUM]; 1845 }; 1846 1847 struct rtw89_btc_fbtc_tdma { 1848 u8 type; /* btc_ver::fcxtdma */ 1849 u8 rxflctrl; 1850 u8 txpause; 1851 u8 wtgle_n; 1852 u8 leak_n; 1853 u8 ext_ctrl; 1854 u8 rxflctrl_role; 1855 u8 option_ctrl; 1856 } __packed; 1857 1858 struct rtw89_btc_fbtc_tdma_v3 { 1859 u8 fver; /* btc_ver::fcxtdma */ 1860 u8 rsvd; 1861 __le16 rsvd1; 1862 struct rtw89_btc_fbtc_tdma tdma; 1863 } __packed; 1864 1865 union rtw89_btc_fbtc_tdma_le32 { 1866 struct rtw89_btc_fbtc_tdma v1; 1867 struct rtw89_btc_fbtc_tdma_v3 v3; 1868 }; 1869 1870 #define CXMREG_MAX 30 1871 #define CXMREG_MAX_V2 20 1872 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1873 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1874 1875 enum rtw89_btc_bt_sta_counter { 1876 BTC_BCNT_RFK_REQ = 0, 1877 BTC_BCNT_RFK_GO = 1, 1878 BTC_BCNT_RFK_REJECT = 2, 1879 BTC_BCNT_RFK_FAIL = 3, 1880 BTC_BCNT_RFK_TIMEOUT = 4, 1881 BTC_BCNT_HI_TX = 5, 1882 BTC_BCNT_HI_RX = 6, 1883 BTC_BCNT_LO_TX = 7, 1884 BTC_BCNT_LO_RX = 8, 1885 BTC_BCNT_POLLUTED = 9, 1886 BTC_BCNT_STA_MAX 1887 }; 1888 1889 enum rtw89_btc_bt_sta_counter_v105 { 1890 BTC_BCNT_RFK_REQ_V105 = 0, 1891 BTC_BCNT_HI_TX_V105 = 1, 1892 BTC_BCNT_HI_RX_V105 = 2, 1893 BTC_BCNT_LO_TX_V105 = 3, 1894 BTC_BCNT_LO_RX_V105 = 4, 1895 BTC_BCNT_POLLUTED_V105 = 5, 1896 BTC_BCNT_STA_MAX_V105 1897 }; 1898 1899 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1900 u16 fver; /* btc_ver::fcxbtcrpt */ 1901 u16 rpt_cnt; /* tmr counters */ 1902 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1903 u32 wl_fw_cx_offload; 1904 u32 wl_fw_ver; 1905 u32 rpt_enable; 1906 u32 rpt_para; /* ms */ 1907 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1908 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1909 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1910 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1911 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1912 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1913 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1914 u32 c2h_cnt; /* fw send c2h counter */ 1915 u32 h2c_cnt; /* fw recv h2c counter */ 1916 } __packed; 1917 1918 struct rtw89_btc_fbtc_rpt_ctrl_info { 1919 __le32 cnt; /* fw report counter */ 1920 __le32 en; /* report map */ 1921 __le32 para; /* not used */ 1922 1923 __le32 cnt_c2h; /* fw send c2h counter */ 1924 __le32 cnt_h2c; /* fw recv h2c counter */ 1925 __le32 len_c2h; /* The total length of the last C2H */ 1926 1927 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1928 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1929 } __packed; 1930 1931 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1932 __le32 cx_ver; /* match which driver's coex version */ 1933 __le32 fw_ver; 1934 __le32 en; /* report map */ 1935 1936 __le16 cnt; /* fw report counter */ 1937 __le16 cnt_c2h; /* fw send c2h counter */ 1938 __le16 cnt_h2c; /* fw recv h2c counter */ 1939 __le16 len_c2h; /* The total length of the last C2H */ 1940 1941 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1942 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1943 } __packed; 1944 1945 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1946 __le32 cx_ver; /* match which driver's coex version */ 1947 __le32 cx_offload; 1948 __le32 fw_ver; 1949 } __packed; 1950 1951 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1952 __le32 cnt_empty; /* a2dp empty count */ 1953 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1954 __le32 cnt_tx; 1955 __le32 cnt_ack; 1956 __le32 cnt_nack; 1957 } __packed; 1958 1959 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1960 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1961 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1962 __le32 cnt_recv; /* fw recv mailbox counter */ 1963 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1964 } __packed; 1965 1966 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1967 u8 fver; 1968 u8 rsvd; 1969 __le16 rsvd1; 1970 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1971 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1972 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1973 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1974 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1975 } __packed; 1976 1977 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1978 u8 fver; 1979 u8 rsvd; 1980 __le16 rsvd1; 1981 1982 u8 gnt_val[RTW89_PHY_MAX][4]; 1983 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1984 1985 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1986 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1987 } __packed; 1988 1989 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1990 u8 fver; 1991 u8 rsvd; 1992 __le16 rsvd1; 1993 1994 u8 gnt_val[RTW89_PHY_MAX][4]; 1995 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1996 1997 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1998 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1999 } __packed; 2000 2001 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2002 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2003 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2004 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2005 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2006 }; 2007 2008 enum rtw89_fbtc_ext_ctrl_type { 2009 CXECTL_OFF = 0x0, /* tdma off */ 2010 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2011 CXECTL_EXT = 0x2, 2012 CXECTL_MAX 2013 }; 2014 2015 union rtw89_btc_fbtc_rxflct { 2016 u8 val; 2017 u8 type: 3; 2018 u8 tgln_n: 5; 2019 }; 2020 2021 enum rtw89_btc_cxst_state { 2022 CXST_OFF = 0x0, 2023 CXST_B2W = 0x1, 2024 CXST_W1 = 0x2, 2025 CXST_W2 = 0x3, 2026 CXST_W2B = 0x4, 2027 CXST_B1 = 0x5, 2028 CXST_B2 = 0x6, 2029 CXST_B3 = 0x7, 2030 CXST_B4 = 0x8, 2031 CXST_LK = 0x9, 2032 CXST_BLK = 0xa, 2033 CXST_E2G = 0xb, 2034 CXST_E5G = 0xc, 2035 CXST_EBT = 0xd, 2036 CXST_ENULL = 0xe, 2037 CXST_WLK = 0xf, 2038 CXST_W1FDD = 0x10, 2039 CXST_B1FDD = 0x11, 2040 CXST_MAX = 0x12, 2041 }; 2042 2043 enum rtw89_btc_cxevnt { 2044 CXEVNT_TDMA_ENTRY = 0x0, 2045 CXEVNT_WL_TMR, 2046 CXEVNT_B1_TMR, 2047 CXEVNT_B2_TMR, 2048 CXEVNT_B3_TMR, 2049 CXEVNT_B4_TMR, 2050 CXEVNT_W2B_TMR, 2051 CXEVNT_B2W_TMR, 2052 CXEVNT_BCN_EARLY, 2053 CXEVNT_A2DP_EMPTY, 2054 CXEVNT_LK_END, 2055 CXEVNT_RX_ISR, 2056 CXEVNT_RX_FC0, 2057 CXEVNT_RX_FC1, 2058 CXEVNT_BT_RELINK, 2059 CXEVNT_BT_RETRY, 2060 CXEVNT_E2G, 2061 CXEVNT_E5G, 2062 CXEVNT_EBT, 2063 CXEVNT_ENULL, 2064 CXEVNT_DRV_WLK, 2065 CXEVNT_BCN_OK, 2066 CXEVNT_BT_CHANGE, 2067 CXEVNT_EBT_EXTEND, 2068 CXEVNT_E2G_NULL1, 2069 CXEVNT_B1FDD_TMR, 2070 CXEVNT_MAX 2071 }; 2072 2073 enum { 2074 CXBCN_ALL = 0x0, 2075 CXBCN_ALL_OK, 2076 CXBCN_BT_SLOT, 2077 CXBCN_BT_OK, 2078 CXBCN_MAX 2079 }; 2080 2081 enum btc_slot_type { 2082 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2083 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2084 CXSTYPE_NUM, 2085 }; 2086 2087 enum { /* TIME */ 2088 CXT_BT = 0x0, 2089 CXT_WL = 0x1, 2090 CXT_MAX 2091 }; 2092 2093 enum { /* TIME-A2DP */ 2094 CXT_FLCTRL_OFF = 0x0, 2095 CXT_FLCTRL_ON = 0x1, 2096 CXT_FLCTRL_MAX 2097 }; 2098 2099 enum { /* STEP TYPE */ 2100 CXSTEP_NONE = 0x0, 2101 CXSTEP_EVNT = 0x1, 2102 CXSTEP_SLOT = 0x2, 2103 CXSTEP_MAX, 2104 }; 2105 2106 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2107 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2108 RPT_BT_AFH_SEQ_LE = 0x20 2109 }; 2110 2111 #define BTC_DBG_MAX1 32 2112 struct rtw89_btc_fbtc_gpio_dbg { 2113 u8 fver; /* btc_ver::fcxgpiodbg */ 2114 u8 rsvd; 2115 u16 rsvd2; 2116 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2117 u32 pre_state; /* the debug signal is 1 or 0 */ 2118 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2119 } __packed; 2120 2121 struct rtw89_btc_fbtc_mreg_val_v1 { 2122 u8 fver; /* btc_ver::fcxmreg */ 2123 u8 reg_num; 2124 __le16 rsvd; 2125 __le32 mreg_val[CXMREG_MAX]; 2126 } __packed; 2127 2128 struct rtw89_btc_fbtc_mreg_val_v2 { 2129 u8 fver; /* btc_ver::fcxmreg */ 2130 u8 reg_num; 2131 __le16 rsvd; 2132 __le32 mreg_val[CXMREG_MAX_V2]; 2133 } __packed; 2134 2135 union rtw89_btc_fbtc_mreg_val { 2136 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2137 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2138 }; 2139 2140 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2141 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2142 .offset = cpu_to_le32(__offset), } 2143 2144 struct rtw89_btc_fbtc_mreg { 2145 __le16 type; 2146 __le16 bytes; 2147 __le32 offset; 2148 } __packed; 2149 2150 struct rtw89_btc_fbtc_slot { 2151 __le16 dur; 2152 __le32 cxtbl; 2153 __le16 cxtype; 2154 } __packed; 2155 2156 struct rtw89_btc_fbtc_slots { 2157 u8 fver; /* btc_ver::fcxslots */ 2158 u8 tbl_num; 2159 __le16 rsvd; 2160 __le32 update_map; 2161 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2162 } __packed; 2163 2164 struct rtw89_btc_fbtc_step { 2165 u8 type; 2166 u8 val; 2167 __le16 difft; 2168 } __packed; 2169 2170 struct rtw89_btc_fbtc_steps_v2 { 2171 u8 fver; /* btc_ver::fcxstep */ 2172 u8 rsvd; 2173 __le16 cnt; 2174 __le16 pos_old; 2175 __le16 pos_new; 2176 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2177 } __packed; 2178 2179 struct rtw89_btc_fbtc_steps_v3 { 2180 u8 fver; 2181 u8 en; 2182 __le16 rsvd; 2183 __le32 cnt; 2184 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2185 } __packed; 2186 2187 union rtw89_btc_fbtc_steps_info { 2188 struct rtw89_btc_fbtc_steps_v2 v2; 2189 struct rtw89_btc_fbtc_steps_v3 v3; 2190 }; 2191 2192 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2193 u8 fver; /* btc_ver::fcxcysta */ 2194 u8 rsvd; 2195 __le16 cycles; /* total cycle number */ 2196 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2197 __le16 a2dpept; /* a2dp empty cnt */ 2198 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2199 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2200 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2201 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2202 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2203 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2204 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2205 __le16 tmax_a2dpept; /* max a2dp empty time */ 2206 __le16 tavg_lk; /* avg leak-slot time */ 2207 __le16 tmax_lk; /* max leak-slot time */ 2208 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2209 __le32 bcn_cnt[CXBCN_MAX]; 2210 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2211 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2212 __le32 skip_cnt; 2213 __le32 exception; 2214 __le32 except_cnt; 2215 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2216 } __packed; 2217 2218 struct rtw89_btc_fbtc_fdd_try_info { 2219 __le16 cycles[CXT_FLCTRL_MAX]; 2220 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2221 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2222 } __packed; 2223 2224 struct rtw89_btc_fbtc_cycle_time_info { 2225 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2226 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2227 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2228 } __packed; 2229 2230 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2231 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2232 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2233 } __packed; 2234 2235 struct rtw89_btc_fbtc_a2dp_trx_stat { 2236 u8 empty_cnt; 2237 u8 retry_cnt; 2238 u8 tx_rate; 2239 u8 tx_cnt; 2240 u8 ack_cnt; 2241 u8 nack_cnt; 2242 u8 rsvd1; 2243 u8 rsvd2; 2244 } __packed; 2245 2246 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2247 u8 empty_cnt; 2248 u8 retry_cnt; 2249 u8 tx_rate; 2250 u8 tx_cnt; 2251 u8 ack_cnt; 2252 u8 nack_cnt; 2253 u8 no_empty_cnt; 2254 u8 rsvd; 2255 } __packed; 2256 2257 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2258 __le16 cnt; /* a2dp empty cnt */ 2259 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2260 __le16 tavg; /* avg a2dp empty time */ 2261 __le16 tmax; /* max a2dp empty time */ 2262 } __packed; 2263 2264 struct rtw89_btc_fbtc_cycle_leak_info { 2265 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2266 __le16 tavg; /* avg leak-slot time */ 2267 __le16 tmax; /* max leak-slot time */ 2268 } __packed; 2269 2270 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2271 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2272 2273 struct rtw89_btc_fbtc_cycle_fddt_info { 2274 __le16 train_cycle; 2275 __le16 tp; 2276 2277 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2278 s8 bt_tx_power; /* decrease Tx power (dB) */ 2279 s8 bt_rx_gain; /* LNA constrain level */ 2280 u8 no_empty_cnt; 2281 2282 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2283 u8 cn; /* condition_num */ 2284 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2285 u8 train_result; /* refer to enum btc_fddt_check_map */ 2286 } __packed; 2287 2288 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2289 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2290 2291 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2292 __le16 train_cycle; 2293 __le16 tp; 2294 2295 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2296 s8 bt_tx_power; /* decrease Tx power (dB) */ 2297 s8 bt_rx_gain; /* LNA constrain level */ 2298 u8 no_empty_cnt; 2299 2300 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2301 u8 cn; /* condition_num */ 2302 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2303 u8 train_result; /* refer to enum btc_fddt_check_map */ 2304 } __packed; 2305 2306 struct rtw89_btc_fbtc_fddt_cell_status { 2307 s8 wl_tx_pwr; 2308 s8 bt_tx_pwr; 2309 s8 bt_rx_gain; 2310 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2311 } __packed; 2312 2313 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2314 u8 fver; 2315 u8 rsvd; 2316 __le16 cycles; /* total cycle number */ 2317 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2318 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2319 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2320 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2321 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2322 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2323 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2324 __le32 bcn_cnt[CXBCN_MAX]; 2325 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2326 __le32 skip_cnt; 2327 __le32 except_cnt; 2328 __le32 except_map; 2329 } __packed; 2330 2331 #define FDD_TRAIN_WL_DIRECTION 2 2332 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2333 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2334 2335 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2336 u8 fver; 2337 u8 rsvd; 2338 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2339 u8 except_cnt; 2340 2341 __le16 skip_cnt; 2342 __le16 cycles; /* total cycle number */ 2343 2344 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2345 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2346 __le16 bcn_cnt[CXBCN_MAX]; 2347 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2348 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2349 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2350 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2351 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2352 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2353 [FDD_TRAIN_WL_RSSI_LEVEL] 2354 [FDD_TRAIN_BT_RSSI_LEVEL]; 2355 __le32 except_map; 2356 } __packed; 2357 2358 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2359 u8 fver; 2360 u8 rsvd; 2361 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2362 u8 except_cnt; 2363 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2364 2365 __le16 skip_cnt; 2366 __le16 cycles; /* total cycle number */ 2367 2368 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2369 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2370 __le16 bcn_cnt[CXBCN_MAX]; 2371 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2372 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2373 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2374 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2375 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2376 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2377 [FDD_TRAIN_WL_RSSI_LEVEL] 2378 [FDD_TRAIN_BT_RSSI_LEVEL]; 2379 __le32 except_map; 2380 } __packed; 2381 2382 union rtw89_btc_fbtc_cysta_info { 2383 struct rtw89_btc_fbtc_cysta_v2 v2; 2384 struct rtw89_btc_fbtc_cysta_v3 v3; 2385 struct rtw89_btc_fbtc_cysta_v4 v4; 2386 struct rtw89_btc_fbtc_cysta_v5 v5; 2387 }; 2388 2389 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2390 u8 fver; /* btc_ver::fcxnullsta */ 2391 u8 rsvd; 2392 __le16 rsvd2; 2393 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2394 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2395 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2396 } __packed; 2397 2398 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2399 u8 fver; /* btc_ver::fcxnullsta */ 2400 u8 rsvd; 2401 __le16 rsvd2; 2402 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2403 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2404 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2405 } __packed; 2406 2407 union rtw89_btc_fbtc_cynullsta_info { 2408 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2409 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2410 }; 2411 2412 struct rtw89_btc_fbtc_btver { 2413 u8 fver; /* btc_ver::fcxbtver */ 2414 u8 rsvd; 2415 __le16 rsvd2; 2416 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2417 __le32 fw_ver; 2418 __le32 feature; 2419 } __packed; 2420 2421 struct rtw89_btc_fbtc_btafh { 2422 u8 fver; /* btc_ver::fcxbtafh */ 2423 u8 rsvd; 2424 __le16 rsvd2; 2425 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2426 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2427 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2428 } __packed; 2429 2430 struct rtw89_btc_fbtc_btafh_v2 { 2431 u8 fver; /* btc_ver::fcxbtafh */ 2432 u8 rsvd; 2433 u8 rsvd2; 2434 u8 map_type; 2435 u8 afh_l[4]; 2436 u8 afh_m[4]; 2437 u8 afh_h[4]; 2438 u8 afh_le_a[4]; 2439 u8 afh_le_b[4]; 2440 } __packed; 2441 2442 struct rtw89_btc_fbtc_btdevinfo { 2443 u8 fver; /* btc_ver::fcxbtdevinfo */ 2444 u8 rsvd; 2445 __le16 vendor_id; 2446 __le32 dev_name; /* only 24 bits valid */ 2447 __le32 flush_time; 2448 } __packed; 2449 2450 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2451 struct rtw89_btc_rf_trx_para { 2452 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2453 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2454 u8 bt_tx_power; /* decrease Tx power (dB) */ 2455 u8 bt_rx_gain; /* LNA constrain level */ 2456 }; 2457 2458 struct rtw89_btc_trx_info { 2459 u8 tx_lvl; 2460 u8 rx_lvl; 2461 u8 wl_rssi; 2462 u8 bt_rssi; 2463 2464 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2465 s8 rx_gain; /* rx gain table index (TBD.) */ 2466 s8 bt_tx_power; /* decrease Tx power (dB) */ 2467 s8 bt_rx_gain; /* LNA constrain level */ 2468 2469 u8 cn; /* condition_num */ 2470 s8 nhm; 2471 u8 bt_profile; 2472 u8 rsvd2; 2473 2474 u16 tx_rate; 2475 u16 rx_rate; 2476 2477 u32 tx_tp; 2478 u32 rx_tp; 2479 u32 rx_err_ratio; 2480 }; 2481 2482 struct rtw89_btc_dm { 2483 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2484 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2485 struct rtw89_btc_fbtc_tdma tdma; 2486 struct rtw89_btc_fbtc_tdma tdma_now; 2487 struct rtw89_mac_ax_coex_gnt gnt; 2488 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2489 struct rtw89_btc_rf_trx_para rf_trx_para; 2490 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2491 struct rtw89_btc_dm_step dm_step; 2492 struct rtw89_btc_wl_scc_ctrl wl_scc; 2493 struct rtw89_btc_trx_info trx_info; 2494 union rtw89_btc_dm_error_map error; 2495 u32 cnt_dm[BTC_DCNT_NUM]; 2496 u32 cnt_notify[BTC_NCNT_NUM]; 2497 2498 u32 update_slot_map; 2499 u32 set_ant_path; 2500 2501 u32 wl_only: 1; 2502 u32 wl_fw_cx_offload: 1; 2503 u32 freerun: 1; 2504 u32 fddt_train: 1; 2505 u32 wl_ps_ctrl: 2; 2506 u32 wl_mimo_ps: 1; 2507 u32 leak_ap: 1; 2508 u32 noisy_level: 3; 2509 u32 coex_info_map: 8; 2510 u32 bt_only: 1; 2511 u32 wl_btg_rx: 2; 2512 u32 trx_para_level: 8; 2513 u32 wl_stb_chg: 1; 2514 u32 pta_owner: 1; 2515 2516 u32 tdma_instant_excute: 1; 2517 u32 wl_btg_rx_rb: 2; 2518 2519 u16 slot_dur[CXST_MAX]; 2520 2521 u8 run_reason; 2522 u8 run_action; 2523 2524 u8 wl_pre_agc: 2; 2525 u8 wl_lna2: 1; 2526 u8 wl_pre_agc_rb: 2; 2527 }; 2528 2529 struct rtw89_btc_ctrl { 2530 u32 manual: 1; 2531 u32 igno_bt: 1; 2532 u32 always_freerun: 1; 2533 u32 trace_step: 16; 2534 u32 rsvd: 12; 2535 }; 2536 2537 struct rtw89_btc_dbg { 2538 /* cmd "rb" */ 2539 bool rb_done; 2540 u32 rb_val; 2541 }; 2542 2543 enum rtw89_btc_btf_fw_event { 2544 BTF_EVNT_RPT = 0, 2545 BTF_EVNT_BT_INFO = 1, 2546 BTF_EVNT_BT_SCBD = 2, 2547 BTF_EVNT_BT_REG = 3, 2548 BTF_EVNT_CX_RUNINFO = 4, 2549 BTF_EVNT_BT_PSD = 5, 2550 BTF_EVNT_BUF_OVERFLOW, 2551 BTF_EVNT_C2H_LOOPBACK, 2552 BTF_EVNT_MAX, 2553 }; 2554 2555 enum btf_fw_event_report { 2556 BTC_RPT_TYPE_CTRL = 0x0, 2557 BTC_RPT_TYPE_TDMA, 2558 BTC_RPT_TYPE_SLOT, 2559 BTC_RPT_TYPE_CYSTA, 2560 BTC_RPT_TYPE_STEP, 2561 BTC_RPT_TYPE_NULLSTA, 2562 BTC_RPT_TYPE_MREG, 2563 BTC_RPT_TYPE_GPIO_DBG, 2564 BTC_RPT_TYPE_BT_VER, 2565 BTC_RPT_TYPE_BT_SCAN, 2566 BTC_RPT_TYPE_BT_AFH, 2567 BTC_RPT_TYPE_BT_DEVICE, 2568 BTC_RPT_TYPE_TEST, 2569 BTC_RPT_TYPE_MAX = 31 2570 }; 2571 2572 enum rtw_btc_btf_reg_type { 2573 REG_MAC = 0x0, 2574 REG_BB = 0x1, 2575 REG_RF = 0x2, 2576 REG_BT_RF = 0x3, 2577 REG_BT_MODEM = 0x4, 2578 REG_BT_BLUEWIZE = 0x5, 2579 REG_BT_VENDOR = 0x6, 2580 REG_BT_LE = 0x7, 2581 REG_MAX_TYPE, 2582 }; 2583 2584 struct rtw89_btc_rpt_cmn_info { 2585 u32 rx_cnt; 2586 u32 rx_len; 2587 u32 req_len; /* expected rsp len */ 2588 u8 req_fver; /* expected rsp fver */ 2589 u8 rsp_fver; /* fver from fw */ 2590 u8 valid; 2591 } __packed; 2592 2593 union rtw89_btc_fbtc_btafh_info { 2594 struct rtw89_btc_fbtc_btafh v1; 2595 struct rtw89_btc_fbtc_btafh_v2 v2; 2596 }; 2597 2598 struct rtw89_btc_report_ctrl_state { 2599 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2600 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2601 }; 2602 2603 struct rtw89_btc_rpt_fbtc_tdma { 2604 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2605 union rtw89_btc_fbtc_tdma_le32 finfo; 2606 }; 2607 2608 struct rtw89_btc_rpt_fbtc_slots { 2609 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2610 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2611 }; 2612 2613 struct rtw89_btc_rpt_fbtc_cysta { 2614 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2615 union rtw89_btc_fbtc_cysta_info finfo; 2616 }; 2617 2618 struct rtw89_btc_rpt_fbtc_step { 2619 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2620 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2621 }; 2622 2623 struct rtw89_btc_rpt_fbtc_nullsta { 2624 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2625 union rtw89_btc_fbtc_cynullsta_info finfo; 2626 }; 2627 2628 struct rtw89_btc_rpt_fbtc_mreg { 2629 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2630 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2631 }; 2632 2633 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2634 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2635 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2636 }; 2637 2638 struct rtw89_btc_rpt_fbtc_btver { 2639 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2640 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2641 }; 2642 2643 struct rtw89_btc_rpt_fbtc_btscan { 2644 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2645 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2646 }; 2647 2648 struct rtw89_btc_rpt_fbtc_btafh { 2649 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2650 union rtw89_btc_fbtc_btafh_info finfo; 2651 }; 2652 2653 struct rtw89_btc_rpt_fbtc_btdev { 2654 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2655 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2656 }; 2657 2658 enum rtw89_btc_btfre_type { 2659 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2660 BTFRE_UNDEF_TYPE, 2661 BTFRE_EXCEPTION, 2662 BTFRE_MAX, 2663 }; 2664 2665 struct rtw89_btc_btf_fwinfo { 2666 u32 cnt_c2h; 2667 u32 cnt_h2c; 2668 u32 cnt_h2c_fail; 2669 u32 event[BTF_EVNT_MAX]; 2670 2671 u32 err[BTFRE_MAX]; 2672 u32 len_mismch; 2673 u32 fver_mismch; 2674 u32 rpt_en_map; 2675 2676 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2677 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2678 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2679 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2680 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2681 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2682 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2683 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2684 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2685 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2686 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2687 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2688 }; 2689 2690 struct rtw89_btc_ver { 2691 enum rtw89_core_chip_id chip_id; 2692 u32 fw_ver_code; 2693 2694 u8 fcxbtcrpt; 2695 u8 fcxtdma; 2696 u8 fcxslots; 2697 u8 fcxcysta; 2698 u8 fcxstep; 2699 u8 fcxnullsta; 2700 u8 fcxmreg; 2701 u8 fcxgpiodbg; 2702 u8 fcxbtver; 2703 u8 fcxbtscan; 2704 u8 fcxbtafh; 2705 u8 fcxbtdevinfo; 2706 u8 fwlrole; 2707 u8 frptmap; 2708 u8 fcxctrl; 2709 2710 u16 info_buf; 2711 u8 max_role_num; 2712 }; 2713 2714 #define RTW89_BTC_POLICY_MAXLEN 512 2715 2716 struct rtw89_btc { 2717 const struct rtw89_btc_ver *ver; 2718 2719 struct rtw89_btc_cx cx; 2720 struct rtw89_btc_dm dm; 2721 struct rtw89_btc_ctrl ctrl; 2722 struct rtw89_btc_module mdinfo; 2723 struct rtw89_btc_btf_fwinfo fwinfo; 2724 struct rtw89_btc_dbg dbg; 2725 2726 struct work_struct eapol_notify_work; 2727 struct work_struct arp_notify_work; 2728 struct work_struct dhcp_notify_work; 2729 struct work_struct icmp_notify_work; 2730 2731 u32 bt_req_len; 2732 2733 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2734 u16 policy_len; 2735 u16 policy_type; 2736 bool bt_req_en; 2737 bool update_policy_force; 2738 bool lps; 2739 }; 2740 2741 enum rtw89_btc_hmsg { 2742 RTW89_BTC_HMSG_TMR_EN = 0x0, 2743 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 2744 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 2745 RTW89_BTC_HMSG_FW_EV = 0x3, 2746 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 2747 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 2748 2749 NUM_OF_RTW89_BTC_HMSG, 2750 }; 2751 2752 enum rtw89_ra_mode { 2753 RTW89_RA_MODE_CCK = BIT(0), 2754 RTW89_RA_MODE_OFDM = BIT(1), 2755 RTW89_RA_MODE_HT = BIT(2), 2756 RTW89_RA_MODE_VHT = BIT(3), 2757 RTW89_RA_MODE_HE = BIT(4), 2758 RTW89_RA_MODE_EHT = BIT(5), 2759 }; 2760 2761 enum rtw89_ra_report_mode { 2762 RTW89_RA_RPT_MODE_LEGACY, 2763 RTW89_RA_RPT_MODE_HT, 2764 RTW89_RA_RPT_MODE_VHT, 2765 RTW89_RA_RPT_MODE_HE, 2766 RTW89_RA_RPT_MODE_EHT, 2767 }; 2768 2769 enum rtw89_dig_noisy_level { 2770 RTW89_DIG_NOISY_LEVEL0 = -1, 2771 RTW89_DIG_NOISY_LEVEL1 = 0, 2772 RTW89_DIG_NOISY_LEVEL2 = 1, 2773 RTW89_DIG_NOISY_LEVEL3 = 2, 2774 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2775 }; 2776 2777 enum rtw89_gi_ltf { 2778 RTW89_GILTF_LGI_4XHE32 = 0, 2779 RTW89_GILTF_SGI_4XHE08 = 1, 2780 RTW89_GILTF_2XHE16 = 2, 2781 RTW89_GILTF_2XHE08 = 3, 2782 RTW89_GILTF_1XHE16 = 4, 2783 RTW89_GILTF_1XHE08 = 5, 2784 RTW89_GILTF_MAX 2785 }; 2786 2787 enum rtw89_rx_frame_type { 2788 RTW89_RX_TYPE_MGNT = 0, 2789 RTW89_RX_TYPE_CTRL = 1, 2790 RTW89_RX_TYPE_DATA = 2, 2791 RTW89_RX_TYPE_RSVD = 3, 2792 }; 2793 2794 enum rtw89_efuse_block { 2795 RTW89_EFUSE_BLOCK_SYS = 0, 2796 RTW89_EFUSE_BLOCK_RF = 1, 2797 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 2798 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 2799 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 2800 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 2801 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 2802 RTW89_EFUSE_BLOCK_ADIE = 7, 2803 2804 RTW89_EFUSE_BLOCK_NUM, 2805 RTW89_EFUSE_BLOCK_IGNORE, 2806 }; 2807 2808 struct rtw89_ra_info { 2809 u8 is_dis_ra:1; 2810 /* Bit0 : CCK 2811 * Bit1 : OFDM 2812 * Bit2 : HT 2813 * Bit3 : VHT 2814 * Bit4 : HE 2815 * Bit5 : EHT 2816 */ 2817 u8 mode_ctrl:6; 2818 u8 bw_cap:3; /* enum rtw89_bandwidth */ 2819 u8 macid; 2820 u8 dcm_cap:1; 2821 u8 er_cap:1; 2822 u8 init_rate_lv:2; 2823 u8 upd_all:1; 2824 u8 en_sgi:1; 2825 u8 ldpc_cap:1; 2826 u8 stbc_cap:1; 2827 u8 ss_num:3; 2828 u8 giltf:3; 2829 u8 upd_bw_nss_mask:1; 2830 u8 upd_mask:1; 2831 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2832 /* BFee CSI */ 2833 u8 band_num; 2834 u8 ra_csi_rate_en:1; 2835 u8 fixed_csi_rate_en:1; 2836 u8 cr_tbl_sel:1; 2837 u8 fix_giltf_en:1; 2838 u8 fix_giltf:3; 2839 u8 rsvd2:1; 2840 u8 csi_mcs_ss_idx; 2841 u8 csi_mode:2; 2842 u8 csi_gi_ltf:3; 2843 u8 csi_bw:3; 2844 }; 2845 2846 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2847 #define RTW89_PPDU_MAC_INFO_SIZE 8 2848 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2849 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 2850 2851 #define RTW89_MAX_RX_AGG_NUM 64 2852 #define RTW89_MAX_TX_AGG_NUM 128 2853 2854 struct rtw89_ampdu_params { 2855 u16 agg_num; 2856 bool amsdu; 2857 }; 2858 2859 struct rtw89_ra_report { 2860 struct rate_info txrate; 2861 u32 bit_rate; 2862 u16 hw_rate; 2863 bool might_fallback_legacy; 2864 }; 2865 2866 DECLARE_EWMA(rssi, 10, 16); 2867 DECLARE_EWMA(evm, 10, 16); 2868 DECLARE_EWMA(snr, 10, 16); 2869 2870 struct rtw89_ba_cam_entry { 2871 struct list_head list; 2872 u8 tid; 2873 }; 2874 2875 #define RTW89_MAX_ADDR_CAM_NUM 128 2876 #define RTW89_MAX_BSSID_CAM_NUM 20 2877 #define RTW89_MAX_SEC_CAM_NUM 128 2878 #define RTW89_MAX_BA_CAM_NUM 8 2879 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2880 2881 struct rtw89_addr_cam_entry { 2882 u8 addr_cam_idx; 2883 u8 offset; 2884 u8 len; 2885 u8 valid : 1; 2886 u8 addr_mask : 6; 2887 u8 wapi : 1; 2888 u8 mask_sel : 2; 2889 u8 bssid_cam_idx: 6; 2890 2891 u8 sec_ent_mode; 2892 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2893 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2894 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2895 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2896 }; 2897 2898 struct rtw89_bssid_cam_entry { 2899 u8 bssid[ETH_ALEN]; 2900 u8 phy_idx; 2901 u8 bssid_cam_idx; 2902 u8 offset; 2903 u8 len; 2904 u8 valid : 1; 2905 u8 num; 2906 }; 2907 2908 struct rtw89_sec_cam_entry { 2909 u8 sec_cam_idx; 2910 u8 offset; 2911 u8 len; 2912 u8 type : 4; 2913 u8 ext_key : 1; 2914 u8 spp_mode : 1; 2915 /* 256 bits */ 2916 u8 key[32]; 2917 }; 2918 2919 struct rtw89_sta { 2920 u8 mac_id; 2921 bool disassoc; 2922 bool er_cap; 2923 struct rtw89_dev *rtwdev; 2924 struct rtw89_vif *rtwvif; 2925 struct rtw89_ra_info ra; 2926 struct rtw89_ra_report ra_report; 2927 int max_agg_wait; 2928 u8 prev_rssi; 2929 struct ewma_rssi avg_rssi; 2930 struct ewma_rssi rssi[RF_PATH_MAX]; 2931 struct ewma_snr avg_snr; 2932 struct ewma_evm evm_min[RF_PATH_MAX]; 2933 struct ewma_evm evm_max[RF_PATH_MAX]; 2934 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2935 struct ieee80211_rx_status rx_status; 2936 u16 rx_hw_rate; 2937 __le32 htc_template; 2938 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2939 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2940 struct list_head ba_cam_list; 2941 struct sk_buff_head roc_queue; 2942 2943 bool use_cfg_mask; 2944 struct cfg80211_bitrate_mask mask; 2945 2946 bool cctl_tx_time; 2947 u32 ampdu_max_time:4; 2948 bool cctl_tx_retry_limit; 2949 u32 data_tx_cnt_lmt:6; 2950 }; 2951 2952 struct rtw89_efuse { 2953 bool valid; 2954 bool power_k_valid; 2955 u8 xtal_cap; 2956 u8 addr[ETH_ALEN]; 2957 u8 rfe_type; 2958 char country_code[2]; 2959 }; 2960 2961 struct rtw89_phy_rate_pattern { 2962 u64 ra_mask; 2963 u16 rate; 2964 u8 ra_mode; 2965 bool enable; 2966 }; 2967 2968 struct rtw89_tx_wait_info { 2969 struct rcu_head rcu_head; 2970 struct completion completion; 2971 bool tx_done; 2972 }; 2973 2974 struct rtw89_tx_skb_data { 2975 struct rtw89_tx_wait_info __rcu *wait; 2976 u8 hci_priv[]; 2977 }; 2978 2979 #define RTW89_ROC_IDLE_TIMEOUT 500 2980 #define RTW89_ROC_TX_TIMEOUT 30 2981 enum rtw89_roc_state { 2982 RTW89_ROC_IDLE, 2983 RTW89_ROC_NORMAL, 2984 RTW89_ROC_MGMT, 2985 }; 2986 2987 struct rtw89_roc { 2988 struct ieee80211_channel chan; 2989 struct delayed_work roc_work; 2990 enum ieee80211_roc_type type; 2991 enum rtw89_roc_state state; 2992 int duration; 2993 }; 2994 2995 #define RTW89_P2P_MAX_NOA_NUM 2 2996 2997 struct rtw89_p2p_ie_head { 2998 u8 eid; 2999 u8 ie_len; 3000 u8 oui[3]; 3001 u8 oui_type; 3002 } __packed; 3003 3004 struct rtw89_noa_attr_head { 3005 u8 attr_type; 3006 __le16 attr_len; 3007 u8 index; 3008 u8 oppps_ctwindow; 3009 } __packed; 3010 3011 struct rtw89_p2p_noa_ie { 3012 struct rtw89_p2p_ie_head p2p_head; 3013 struct rtw89_noa_attr_head noa_head; 3014 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3015 } __packed; 3016 3017 struct rtw89_p2p_noa_setter { 3018 struct rtw89_p2p_noa_ie ie; 3019 u8 noa_count; 3020 u8 noa_index; 3021 }; 3022 3023 struct rtw89_vif { 3024 struct list_head list; 3025 struct rtw89_dev *rtwdev; 3026 struct rtw89_roc roc; 3027 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3028 enum rtw89_sub_entity_idx sub_entity_idx; 3029 enum rtw89_reg_6ghz_power reg_6ghz_power; 3030 3031 u8 mac_id; 3032 u8 port; 3033 u8 mac_addr[ETH_ALEN]; 3034 u8 bssid[ETH_ALEN]; 3035 u8 phy_idx; 3036 u8 mac_idx; 3037 u8 net_type; 3038 u8 wifi_role; 3039 u8 self_role; 3040 u8 wmm; 3041 u8 bcn_hit_cond; 3042 u8 hit_rule; 3043 u8 last_noa_nr; 3044 bool offchan; 3045 bool trigger; 3046 bool lsig_txop; 3047 u8 tgt_ind; 3048 u8 frm_tgt_ind; 3049 bool wowlan_pattern; 3050 bool wowlan_uc; 3051 bool wowlan_magic; 3052 bool is_hesta; 3053 bool last_a_ctrl; 3054 bool dyn_tb_bedge_en; 3055 bool pre_pwr_diff_en; 3056 bool pwr_diff_en; 3057 u8 def_tri_idx; 3058 u32 tdls_peer; 3059 struct work_struct update_beacon_work; 3060 struct rtw89_addr_cam_entry addr_cam; 3061 struct rtw89_bssid_cam_entry bssid_cam; 3062 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3063 struct rtw89_traffic_stats stats; 3064 struct rtw89_phy_rate_pattern rate_pattern; 3065 struct cfg80211_scan_request *scan_req; 3066 struct ieee80211_scan_ies *scan_ies; 3067 struct list_head general_pkt_list; 3068 struct rtw89_p2p_noa_setter p2p_noa; 3069 }; 3070 3071 enum rtw89_lv1_rcvy_step { 3072 RTW89_LV1_RCVY_STEP_1, 3073 RTW89_LV1_RCVY_STEP_2, 3074 }; 3075 3076 struct rtw89_hci_ops { 3077 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3078 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3079 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3080 void (*reset)(struct rtw89_dev *rtwdev); 3081 int (*start)(struct rtw89_dev *rtwdev); 3082 void (*stop)(struct rtw89_dev *rtwdev); 3083 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3084 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3085 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3086 3087 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3088 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3089 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3090 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3091 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3092 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3093 3094 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3095 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3096 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3097 int (*deinit)(struct rtw89_dev *rtwdev); 3098 3099 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3100 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3101 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3102 int (*napi_poll)(struct napi_struct *napi, int budget); 3103 3104 /* Deal with locks inside recovery_start and recovery_complete callbacks 3105 * by hci instance, and handle things which need to consider under SER. 3106 * e.g. turn on/off interrupts except for the one for halt notification. 3107 */ 3108 void (*recovery_start)(struct rtw89_dev *rtwdev); 3109 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3110 3111 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3112 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3113 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3114 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 3115 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3116 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3117 void (*disable_intr)(struct rtw89_dev *rtwdev); 3118 void (*enable_intr)(struct rtw89_dev *rtwdev); 3119 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3120 }; 3121 3122 struct rtw89_hci_info { 3123 const struct rtw89_hci_ops *ops; 3124 enum rtw89_hci_type type; 3125 u32 rpwm_addr; 3126 u32 cpwm_addr; 3127 bool paused; 3128 }; 3129 3130 struct rtw89_chip_ops { 3131 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3132 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3133 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3134 void (*bb_reset)(struct rtw89_dev *rtwdev, 3135 enum rtw89_phy_idx phy_idx); 3136 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3137 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3138 u32 addr, u32 mask); 3139 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3140 u32 addr, u32 mask, u32 data); 3141 void (*set_channel)(struct rtw89_dev *rtwdev, 3142 const struct rtw89_chan *chan, 3143 enum rtw89_mac_idx mac_idx, 3144 enum rtw89_phy_idx phy_idx); 3145 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3146 struct rtw89_channel_help_params *p, 3147 const struct rtw89_chan *chan, 3148 enum rtw89_mac_idx mac_idx, 3149 enum rtw89_phy_idx phy_idx); 3150 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3151 enum rtw89_efuse_block block); 3152 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3153 void (*fem_setup)(struct rtw89_dev *rtwdev); 3154 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3155 void (*rfk_init)(struct rtw89_dev *rtwdev); 3156 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3157 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3158 enum rtw89_phy_idx phy_idx); 3159 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3160 void (*rfk_track)(struct rtw89_dev *rtwdev); 3161 void (*power_trim)(struct rtw89_dev *rtwdev); 3162 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3163 const struct rtw89_chan *chan, 3164 enum rtw89_phy_idx phy_idx); 3165 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3166 enum rtw89_phy_idx phy_idx); 3167 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3168 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3169 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3170 enum rtw89_phy_idx phy_idx); 3171 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3172 struct rtw89_rx_phy_ppdu *phy_ppdu, 3173 struct ieee80211_rx_status *status); 3174 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3175 enum rtw89_phy_idx phy_idx); 3176 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3177 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3178 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3179 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3180 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3181 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3182 struct rtw89_rx_desc_info *desc_info, 3183 u8 *data, u32 data_offset); 3184 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3185 struct rtw89_tx_desc_info *desc_info, 3186 void *txdesc); 3187 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3188 struct rtw89_tx_desc_info *desc_info, 3189 void *txdesc); 3190 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3191 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3192 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3193 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3194 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3195 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3196 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3197 struct rtw89_vif *rtwvif, 3198 struct rtw89_sta *rtwsta); 3199 3200 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3201 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3202 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3203 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3204 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3205 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3206 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3207 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3208 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3209 }; 3210 3211 enum rtw89_dma_ch { 3212 RTW89_DMA_ACH0 = 0, 3213 RTW89_DMA_ACH1 = 1, 3214 RTW89_DMA_ACH2 = 2, 3215 RTW89_DMA_ACH3 = 3, 3216 RTW89_DMA_ACH4 = 4, 3217 RTW89_DMA_ACH5 = 5, 3218 RTW89_DMA_ACH6 = 6, 3219 RTW89_DMA_ACH7 = 7, 3220 RTW89_DMA_B0MG = 8, 3221 RTW89_DMA_B0HI = 9, 3222 RTW89_DMA_B1MG = 10, 3223 RTW89_DMA_B1HI = 11, 3224 RTW89_DMA_H2C = 12, 3225 RTW89_DMA_CH_NUM = 13 3226 }; 3227 3228 enum rtw89_qta_mode { 3229 RTW89_QTA_SCC, 3230 RTW89_QTA_DLFW, 3231 RTW89_QTA_WOW, 3232 3233 /* keep last */ 3234 RTW89_QTA_INVALID, 3235 }; 3236 3237 struct rtw89_hfc_ch_cfg { 3238 u16 min; 3239 u16 max; 3240 #define grp_0 0 3241 #define grp_1 1 3242 #define grp_num 2 3243 u8 grp; 3244 }; 3245 3246 struct rtw89_hfc_ch_info { 3247 u16 aval; 3248 u16 used; 3249 }; 3250 3251 struct rtw89_hfc_pub_cfg { 3252 u16 grp0; 3253 u16 grp1; 3254 u16 pub_max; 3255 u16 wp_thrd; 3256 }; 3257 3258 struct rtw89_hfc_pub_info { 3259 u16 g0_used; 3260 u16 g1_used; 3261 u16 g0_aval; 3262 u16 g1_aval; 3263 u16 pub_aval; 3264 u16 wp_aval; 3265 }; 3266 3267 struct rtw89_hfc_prec_cfg { 3268 u16 ch011_prec; 3269 u16 h2c_prec; 3270 u16 wp_ch07_prec; 3271 u16 wp_ch811_prec; 3272 u8 ch011_full_cond; 3273 u8 h2c_full_cond; 3274 u8 wp_ch07_full_cond; 3275 u8 wp_ch811_full_cond; 3276 }; 3277 3278 struct rtw89_hfc_param { 3279 bool en; 3280 bool h2c_en; 3281 u8 mode; 3282 const struct rtw89_hfc_ch_cfg *ch_cfg; 3283 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3284 struct rtw89_hfc_pub_cfg pub_cfg; 3285 struct rtw89_hfc_pub_info pub_info; 3286 struct rtw89_hfc_prec_cfg prec_cfg; 3287 }; 3288 3289 struct rtw89_hfc_param_ini { 3290 const struct rtw89_hfc_ch_cfg *ch_cfg; 3291 const struct rtw89_hfc_pub_cfg *pub_cfg; 3292 const struct rtw89_hfc_prec_cfg *prec_cfg; 3293 u8 mode; 3294 }; 3295 3296 struct rtw89_dle_size { 3297 u16 pge_size; 3298 u16 lnk_pge_num; 3299 u16 unlnk_pge_num; 3300 /* for WiFi 7 chips below */ 3301 u32 srt_ofst; 3302 }; 3303 3304 struct rtw89_wde_quota { 3305 u16 hif; 3306 u16 wcpu; 3307 u16 pkt_in; 3308 u16 cpu_io; 3309 }; 3310 3311 struct rtw89_ple_quota { 3312 u16 cma0_tx; 3313 u16 cma1_tx; 3314 u16 c2h; 3315 u16 h2c; 3316 u16 wcpu; 3317 u16 mpdu_proc; 3318 u16 cma0_dma; 3319 u16 cma1_dma; 3320 u16 bb_rpt; 3321 u16 wd_rel; 3322 u16 cpu_io; 3323 u16 tx_rpt; 3324 /* for WiFi 7 chips below */ 3325 u16 h2d; 3326 }; 3327 3328 struct rtw89_rsvd_quota { 3329 u16 mpdu_info_tbl; 3330 u16 b0_csi; 3331 u16 b1_csi; 3332 u16 b0_lmr; 3333 u16 b1_lmr; 3334 u16 b0_ftm; 3335 u16 b1_ftm; 3336 u16 b0_smr; 3337 u16 b1_smr; 3338 u16 others; 3339 }; 3340 3341 struct rtw89_dle_rsvd_size { 3342 u32 srt_ofst; 3343 u32 size; 3344 }; 3345 3346 struct rtw89_dle_mem { 3347 enum rtw89_qta_mode mode; 3348 const struct rtw89_dle_size *wde_size; 3349 const struct rtw89_dle_size *ple_size; 3350 const struct rtw89_wde_quota *wde_min_qt; 3351 const struct rtw89_wde_quota *wde_max_qt; 3352 const struct rtw89_ple_quota *ple_min_qt; 3353 const struct rtw89_ple_quota *ple_max_qt; 3354 /* for WiFi 7 chips below */ 3355 const struct rtw89_rsvd_quota *rsvd_qt; 3356 const struct rtw89_dle_rsvd_size *rsvd0_size; 3357 const struct rtw89_dle_rsvd_size *rsvd1_size; 3358 }; 3359 3360 struct rtw89_reg_def { 3361 u32 addr; 3362 u32 mask; 3363 }; 3364 3365 struct rtw89_reg2_def { 3366 u32 addr; 3367 u32 data; 3368 }; 3369 3370 struct rtw89_reg3_def { 3371 u32 addr; 3372 u32 mask; 3373 u32 data; 3374 }; 3375 3376 struct rtw89_reg5_def { 3377 u8 flag; /* recognized by parsers */ 3378 u8 path; 3379 u32 addr; 3380 u32 mask; 3381 u32 data; 3382 }; 3383 3384 struct rtw89_reg_imr { 3385 u32 addr; 3386 u32 clr; 3387 u32 set; 3388 }; 3389 3390 struct rtw89_phy_table { 3391 const struct rtw89_reg2_def *regs; 3392 u32 n_regs; 3393 enum rtw89_rf_path rf_path; 3394 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3395 enum rtw89_rf_path rf_path, void *data); 3396 }; 3397 3398 struct rtw89_txpwr_table { 3399 const void *data; 3400 u32 size; 3401 void (*load)(struct rtw89_dev *rtwdev, 3402 const struct rtw89_txpwr_table *tbl); 3403 }; 3404 3405 struct rtw89_txpwr_rule_2ghz { 3406 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3407 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3408 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3409 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3410 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3411 }; 3412 3413 struct rtw89_txpwr_rule_5ghz { 3414 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3415 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3416 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3417 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3418 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3419 }; 3420 3421 struct rtw89_txpwr_rule_6ghz { 3422 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3423 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3424 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3425 [RTW89_6G_CH_NUM]; 3426 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3427 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3428 [RTW89_6G_CH_NUM]; 3429 }; 3430 3431 struct rtw89_tx_shape { 3432 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3433 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3434 }; 3435 3436 struct rtw89_rfe_parms { 3437 const struct rtw89_txpwr_table *byr_tbl; 3438 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3439 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3440 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3441 struct rtw89_tx_shape tx_shape; 3442 }; 3443 3444 struct rtw89_rfe_parms_conf { 3445 const struct rtw89_rfe_parms *rfe_parms; 3446 u8 rfe_type; 3447 }; 3448 3449 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3450 3451 struct rtw89_txpwr_conf { 3452 u8 rfe_type; 3453 u8 ent_sz; 3454 u32 num_ents; 3455 const void *data; 3456 }; 3457 3458 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3459 3460 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3461 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3462 memcpy(&(entry), cursor, \ 3463 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3464 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3465 (cursor) += (conf)->ent_sz, \ 3466 memcpy(&(entry), cursor, \ 3467 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3468 3469 struct rtw89_txpwr_byrate_data { 3470 struct rtw89_txpwr_conf conf; 3471 struct rtw89_txpwr_table tbl; 3472 }; 3473 3474 struct rtw89_txpwr_lmt_2ghz_data { 3475 struct rtw89_txpwr_conf conf; 3476 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3477 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3478 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3479 }; 3480 3481 struct rtw89_txpwr_lmt_5ghz_data { 3482 struct rtw89_txpwr_conf conf; 3483 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3484 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3485 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3486 }; 3487 3488 struct rtw89_txpwr_lmt_6ghz_data { 3489 struct rtw89_txpwr_conf conf; 3490 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3491 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3492 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3493 [RTW89_6G_CH_NUM]; 3494 }; 3495 3496 struct rtw89_txpwr_lmt_ru_2ghz_data { 3497 struct rtw89_txpwr_conf conf; 3498 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3499 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3500 }; 3501 3502 struct rtw89_txpwr_lmt_ru_5ghz_data { 3503 struct rtw89_txpwr_conf conf; 3504 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3505 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3506 }; 3507 3508 struct rtw89_txpwr_lmt_ru_6ghz_data { 3509 struct rtw89_txpwr_conf conf; 3510 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3511 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3512 [RTW89_6G_CH_NUM]; 3513 }; 3514 3515 struct rtw89_tx_shape_lmt_data { 3516 struct rtw89_txpwr_conf conf; 3517 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3518 }; 3519 3520 struct rtw89_tx_shape_lmt_ru_data { 3521 struct rtw89_txpwr_conf conf; 3522 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3523 }; 3524 3525 struct rtw89_rfe_data { 3526 struct rtw89_txpwr_byrate_data byrate; 3527 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3528 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3529 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3530 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3531 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3532 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3533 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3534 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3535 struct rtw89_rfe_parms rfe_parms; 3536 }; 3537 3538 struct rtw89_page_regs { 3539 u32 hci_fc_ctrl; 3540 u32 ch_page_ctrl; 3541 u32 ach_page_ctrl; 3542 u32 ach_page_info; 3543 u32 pub_page_info3; 3544 u32 pub_page_ctrl1; 3545 u32 pub_page_ctrl2; 3546 u32 pub_page_info1; 3547 u32 pub_page_info2; 3548 u32 wp_page_ctrl1; 3549 u32 wp_page_ctrl2; 3550 u32 wp_page_info1; 3551 }; 3552 3553 struct rtw89_imr_info { 3554 u32 wdrls_imr_set; 3555 u32 wsec_imr_reg; 3556 u32 wsec_imr_set; 3557 u32 mpdu_tx_imr_set; 3558 u32 mpdu_rx_imr_set; 3559 u32 sta_sch_imr_set; 3560 u32 txpktctl_imr_b0_reg; 3561 u32 txpktctl_imr_b0_clr; 3562 u32 txpktctl_imr_b0_set; 3563 u32 txpktctl_imr_b1_reg; 3564 u32 txpktctl_imr_b1_clr; 3565 u32 txpktctl_imr_b1_set; 3566 u32 wde_imr_clr; 3567 u32 wde_imr_set; 3568 u32 ple_imr_clr; 3569 u32 ple_imr_set; 3570 u32 host_disp_imr_clr; 3571 u32 host_disp_imr_set; 3572 u32 cpu_disp_imr_clr; 3573 u32 cpu_disp_imr_set; 3574 u32 other_disp_imr_clr; 3575 u32 other_disp_imr_set; 3576 u32 bbrpt_com_err_imr_reg; 3577 u32 bbrpt_chinfo_err_imr_reg; 3578 u32 bbrpt_err_imr_set; 3579 u32 bbrpt_dfs_err_imr_reg; 3580 u32 ptcl_imr_clr; 3581 u32 ptcl_imr_set; 3582 u32 cdma_imr_0_reg; 3583 u32 cdma_imr_0_clr; 3584 u32 cdma_imr_0_set; 3585 u32 cdma_imr_1_reg; 3586 u32 cdma_imr_1_clr; 3587 u32 cdma_imr_1_set; 3588 u32 phy_intf_imr_reg; 3589 u32 phy_intf_imr_clr; 3590 u32 phy_intf_imr_set; 3591 u32 rmac_imr_reg; 3592 u32 rmac_imr_clr; 3593 u32 rmac_imr_set; 3594 u32 tmac_imr_reg; 3595 u32 tmac_imr_clr; 3596 u32 tmac_imr_set; 3597 }; 3598 3599 struct rtw89_imr_table { 3600 const struct rtw89_reg_imr *regs; 3601 u32 n_regs; 3602 }; 3603 3604 struct rtw89_xtal_info { 3605 u32 xcap_reg; 3606 u32 sc_xo_mask; 3607 u32 sc_xi_mask; 3608 }; 3609 3610 struct rtw89_rrsr_cfgs { 3611 struct rtw89_reg3_def ref_rate; 3612 struct rtw89_reg3_def rsc; 3613 }; 3614 3615 struct rtw89_dig_regs { 3616 u32 seg0_pd_reg; 3617 u32 pd_lower_bound_mask; 3618 u32 pd_spatial_reuse_en; 3619 u32 bmode_pd_reg; 3620 u32 bmode_cca_rssi_limit_en; 3621 u32 bmode_pd_lower_bound_reg; 3622 u32 bmode_rssi_nocca_low_th_mask; 3623 struct rtw89_reg_def p0_lna_init; 3624 struct rtw89_reg_def p1_lna_init; 3625 struct rtw89_reg_def p0_tia_init; 3626 struct rtw89_reg_def p1_tia_init; 3627 struct rtw89_reg_def p0_rxb_init; 3628 struct rtw89_reg_def p1_rxb_init; 3629 struct rtw89_reg_def p0_p20_pagcugc_en; 3630 struct rtw89_reg_def p0_s20_pagcugc_en; 3631 struct rtw89_reg_def p1_p20_pagcugc_en; 3632 struct rtw89_reg_def p1_s20_pagcugc_en; 3633 }; 3634 3635 struct rtw89_edcca_regs { 3636 u32 edcca_level; 3637 u32 edcca_mask; 3638 u32 edcca_p_mask; 3639 u32 ppdu_level; 3640 u32 ppdu_mask; 3641 u32 rpt_a; 3642 u32 rpt_b; 3643 u32 rpt_sel; 3644 u32 rpt_sel_mask; 3645 u32 rpt_sel_be; 3646 u32 rpt_sel_be_mask; 3647 u32 tx_collision_t2r_st; 3648 u32 tx_collision_t2r_st_mask; 3649 }; 3650 3651 struct rtw89_phy_ul_tb_info { 3652 bool dyn_tb_tri_en; 3653 u8 def_if_bandedge; 3654 }; 3655 3656 struct rtw89_antdiv_stats { 3657 struct ewma_rssi cck_rssi_avg; 3658 struct ewma_rssi ofdm_rssi_avg; 3659 struct ewma_rssi non_legacy_rssi_avg; 3660 u16 pkt_cnt_cck; 3661 u16 pkt_cnt_ofdm; 3662 u16 pkt_cnt_non_legacy; 3663 u32 evm; 3664 }; 3665 3666 struct rtw89_antdiv_info { 3667 struct rtw89_antdiv_stats target_stats; 3668 struct rtw89_antdiv_stats main_stats; 3669 struct rtw89_antdiv_stats aux_stats; 3670 u8 training_count; 3671 u8 rssi_pre; 3672 bool get_stats; 3673 }; 3674 3675 enum rtw89_chanctx_state { 3676 RTW89_CHANCTX_STATE_MCC_START, 3677 RTW89_CHANCTX_STATE_MCC_STOP, 3678 }; 3679 3680 enum rtw89_chanctx_callbacks { 3681 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 3682 RTW89_CHANCTX_CALLBACK_RFK, 3683 3684 NUM_OF_RTW89_CHANCTX_CALLBACKS, 3685 }; 3686 3687 struct rtw89_chanctx_listener { 3688 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 3689 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 3690 }; 3691 3692 struct rtw89_chip_info { 3693 enum rtw89_core_chip_id chip_id; 3694 enum rtw89_chip_gen chip_gen; 3695 const struct rtw89_chip_ops *ops; 3696 const struct rtw89_mac_gen_def *mac_def; 3697 const struct rtw89_phy_gen_def *phy_def; 3698 const char *fw_basename; 3699 u8 fw_format_max; 3700 bool try_ce_fw; 3701 u8 bbmcu_nr; 3702 u32 needed_fw_elms; 3703 u32 fifo_size; 3704 bool small_fifo_size; 3705 u32 dle_scc_rsvd_size; 3706 u16 max_amsdu_limit; 3707 bool dis_2g_40m_ul_ofdma; 3708 u32 rsvd_ple_ofst; 3709 const struct rtw89_hfc_param_ini *hfc_param_ini; 3710 const struct rtw89_dle_mem *dle_mem; 3711 u8 wde_qempty_acq_grpnum; 3712 u8 wde_qempty_mgq_grpsel; 3713 u32 rf_base_addr[2]; 3714 u8 support_chanctx_num; 3715 u8 support_bands; 3716 bool support_bw160; 3717 bool support_unii4; 3718 bool ul_tb_waveform_ctrl; 3719 bool ul_tb_pwr_diff; 3720 bool hw_sec_hdr; 3721 u8 rf_path_num; 3722 u8 tx_nss; 3723 u8 rx_nss; 3724 u8 acam_num; 3725 u8 bcam_num; 3726 u8 scam_num; 3727 u8 bacam_num; 3728 u8 bacam_dynamic_num; 3729 enum rtw89_bacam_ver bacam_ver; 3730 u8 ppdu_max_usr; 3731 3732 u8 sec_ctrl_efuse_size; 3733 u32 physical_efuse_size; 3734 u32 logical_efuse_size; 3735 u32 limit_efuse_size; 3736 u32 dav_phy_efuse_size; 3737 u32 dav_log_efuse_size; 3738 u32 phycap_addr; 3739 u32 phycap_size; 3740 const struct rtw89_efuse_block_cfg *efuse_blocks; 3741 3742 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3743 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3744 const struct rtw89_phy_table *bb_table; 3745 const struct rtw89_phy_table *bb_gain_table; 3746 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3747 const struct rtw89_phy_table *nctl_table; 3748 const struct rtw89_rfk_tbl *nctl_post_table; 3749 const struct rtw89_phy_dig_gain_table *dig_table; 3750 const struct rtw89_dig_regs *dig_regs; 3751 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3752 3753 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3754 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3755 const struct rtw89_rfe_parms *dflt_parms; 3756 const struct rtw89_chanctx_listener *chanctx_listener; 3757 3758 u8 txpwr_factor_rf; 3759 u8 txpwr_factor_mac; 3760 3761 u32 para_ver; 3762 u32 wlcx_desired; 3763 u8 btcx_desired; 3764 u8 scbd; 3765 u8 mailbox; 3766 3767 u8 afh_guard_ch; 3768 const u8 *wl_rssi_thres; 3769 const u8 *bt_rssi_thres; 3770 u8 rssi_tol; 3771 3772 u8 mon_reg_num; 3773 const struct rtw89_btc_fbtc_mreg *mon_reg; 3774 u8 rf_para_ulink_num; 3775 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3776 u8 rf_para_dlink_num; 3777 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3778 u8 ps_mode_supported; 3779 u8 low_power_hci_modes; 3780 3781 u32 h2c_cctl_func_id; 3782 u32 hci_func_en_addr; 3783 u32 h2c_desc_size; 3784 u32 txwd_body_size; 3785 u32 txwd_info_size; 3786 u32 h2c_ctrl_reg; 3787 const u32 *h2c_regs; 3788 struct rtw89_reg_def h2c_counter_reg; 3789 u32 c2h_ctrl_reg; 3790 const u32 *c2h_regs; 3791 struct rtw89_reg_def c2h_counter_reg; 3792 const struct rtw89_page_regs *page_regs; 3793 bool cfo_src_fd; 3794 bool cfo_hw_comp; 3795 const struct rtw89_reg_def *dcfo_comp; 3796 u8 dcfo_comp_sft; 3797 const struct rtw89_imr_info *imr_info; 3798 const struct rtw89_imr_table *imr_dmac_table; 3799 const struct rtw89_imr_table *imr_cmac_table; 3800 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3801 struct rtw89_reg_def bss_clr_vld; 3802 u32 bss_clr_map_reg; 3803 u32 dma_ch_mask; 3804 const struct rtw89_edcca_regs *edcca_regs; 3805 const struct wiphy_wowlan_support *wowlan_stub; 3806 const struct rtw89_xtal_info *xtal_info; 3807 }; 3808 3809 union rtw89_bus_info { 3810 const struct rtw89_pci_info *pci; 3811 }; 3812 3813 struct rtw89_driver_info { 3814 const struct rtw89_chip_info *chip; 3815 union rtw89_bus_info bus; 3816 }; 3817 3818 enum rtw89_hcifc_mode { 3819 RTW89_HCIFC_POH = 0, 3820 RTW89_HCIFC_STF = 1, 3821 RTW89_HCIFC_SDIO = 2, 3822 3823 /* keep last */ 3824 RTW89_HCIFC_MODE_INVALID, 3825 }; 3826 3827 struct rtw89_dle_info { 3828 const struct rtw89_rsvd_quota *rsvd_qt; 3829 enum rtw89_qta_mode qta_mode; 3830 u16 ple_pg_size; 3831 u16 ple_free_pg; 3832 u16 c0_rx_qta; 3833 u16 c1_rx_qta; 3834 }; 3835 3836 enum rtw89_host_rpr_mode { 3837 RTW89_RPR_MODE_POH = 0, 3838 RTW89_RPR_MODE_STF 3839 }; 3840 3841 #define RTW89_COMPLETION_BUF_SIZE 24 3842 #define RTW89_WAIT_COND_IDLE UINT_MAX 3843 3844 struct rtw89_completion_data { 3845 bool err; 3846 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3847 }; 3848 3849 struct rtw89_wait_info { 3850 atomic_t cond; 3851 struct completion completion; 3852 struct rtw89_completion_data data; 3853 }; 3854 3855 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3856 3857 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3858 { 3859 init_completion(&wait->completion); 3860 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3861 } 3862 3863 struct rtw89_mac_info { 3864 struct rtw89_dle_info dle_info; 3865 struct rtw89_hfc_param hfc_param; 3866 enum rtw89_qta_mode qta_mode; 3867 u8 rpwm_seq_num; 3868 u8 cpwm_seq_num; 3869 3870 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 3871 struct rtw89_wait_info fw_ofld_wait; 3872 }; 3873 3874 enum rtw89_fwdl_check_type { 3875 RTW89_FWDL_CHECK_FREERTOS_DONE, 3876 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 3877 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 3878 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 3879 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 3880 }; 3881 3882 enum rtw89_fw_type { 3883 RTW89_FW_NORMAL = 1, 3884 RTW89_FW_WOWLAN = 3, 3885 RTW89_FW_NORMAL_CE = 5, 3886 RTW89_FW_BBMCU0 = 64, 3887 RTW89_FW_BBMCU1 = 65, 3888 RTW89_FW_LOGFMT = 255, 3889 }; 3890 3891 enum rtw89_fw_feature { 3892 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3893 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3894 RTW89_FW_FEATURE_TX_WAKE, 3895 RTW89_FW_FEATURE_CRASH_TRIGGER, 3896 RTW89_FW_FEATURE_NO_PACKET_DROP, 3897 RTW89_FW_FEATURE_NO_DEEP_PS, 3898 RTW89_FW_FEATURE_NO_LPS_PG, 3899 RTW89_FW_FEATURE_BEACON_FILTER, 3900 }; 3901 3902 struct rtw89_fw_suit { 3903 enum rtw89_fw_type type; 3904 const u8 *data; 3905 u32 size; 3906 u8 major_ver; 3907 u8 minor_ver; 3908 u8 sub_ver; 3909 u8 sub_idex; 3910 u16 build_year; 3911 u16 build_mon; 3912 u16 build_date; 3913 u16 build_hour; 3914 u16 build_min; 3915 u8 cmd_ver; 3916 u8 hdr_ver; 3917 u32 commitid; 3918 }; 3919 3920 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3921 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3922 #define RTW89_FW_SUIT_VER_CODE(s) \ 3923 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3924 3925 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3926 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3927 (mfw_hdr)->ver.minor, \ 3928 (mfw_hdr)->ver.sub, \ 3929 (mfw_hdr)->ver.idx) 3930 3931 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3932 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 3933 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 3934 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 3935 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 3936 3937 struct rtw89_fw_req_info { 3938 const struct firmware *firmware; 3939 struct completion completion; 3940 }; 3941 3942 struct rtw89_fw_log { 3943 struct rtw89_fw_suit suit; 3944 bool enable; 3945 u32 last_fmt_id; 3946 u32 fmt_count; 3947 const __le32 *fmt_ids; 3948 const char *(*fmts)[]; 3949 }; 3950 3951 struct rtw89_fw_elm_info { 3952 struct rtw89_phy_table *bb_tbl; 3953 struct rtw89_phy_table *bb_gain; 3954 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 3955 struct rtw89_phy_table *rf_nctl; 3956 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 3957 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 3958 }; 3959 3960 struct rtw89_fw_info { 3961 struct rtw89_fw_req_info req; 3962 int fw_format; 3963 u8 h2c_seq; 3964 u8 rec_seq; 3965 u8 h2c_counter; 3966 u8 c2h_counter; 3967 struct rtw89_fw_suit normal; 3968 struct rtw89_fw_suit wowlan; 3969 struct rtw89_fw_suit bbmcu0; 3970 struct rtw89_fw_suit bbmcu1; 3971 struct rtw89_fw_log log; 3972 u32 feature_map; 3973 struct rtw89_fw_elm_info elm_info; 3974 }; 3975 3976 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3977 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3978 3979 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3980 ((_fw)->feature_map |= BIT(_fw_feature)) 3981 3982 struct rtw89_cam_info { 3983 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3984 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3985 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3986 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3987 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3988 }; 3989 3990 enum rtw89_sar_sources { 3991 RTW89_SAR_SOURCE_NONE, 3992 RTW89_SAR_SOURCE_COMMON, 3993 3994 RTW89_SAR_SOURCE_NR, 3995 }; 3996 3997 enum rtw89_sar_subband { 3998 RTW89_SAR_2GHZ_SUBBAND, 3999 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4000 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4001 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4002 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4003 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4004 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4005 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4006 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4007 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4008 4009 RTW89_SAR_SUBBAND_NR, 4010 }; 4011 4012 struct rtw89_sar_cfg_common { 4013 bool set[RTW89_SAR_SUBBAND_NR]; 4014 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4015 }; 4016 4017 struct rtw89_sar_info { 4018 /* used to decide how to acces SAR cfg union */ 4019 enum rtw89_sar_sources src; 4020 4021 /* reserved for different knids of SAR cfg struct. 4022 * supposed that a single cfg struct cannot handle various SAR sources. 4023 */ 4024 union { 4025 struct rtw89_sar_cfg_common cfg_common; 4026 }; 4027 }; 4028 4029 enum rtw89_tas_state { 4030 RTW89_TAS_STATE_DPR_OFF, 4031 RTW89_TAS_STATE_DPR_ON, 4032 RTW89_TAS_STATE_DPR_FORBID, 4033 }; 4034 4035 #define RTW89_TAS_MAX_WINDOW 50 4036 struct rtw89_tas_info { 4037 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4038 s32 total_txpwr; 4039 u8 cur_idx; 4040 s8 dpr_gap; 4041 s8 delta; 4042 enum rtw89_tas_state state; 4043 bool enable; 4044 }; 4045 4046 struct rtw89_chanctx_cfg { 4047 enum rtw89_sub_entity_idx idx; 4048 }; 4049 4050 enum rtw89_chanctx_changes { 4051 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4052 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4053 RTW89_CHANCTX_P2P_PS_CHANGE, 4054 RTW89_CHANCTX_BT_SLOT_CHANGE, 4055 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4056 4057 NUM_OF_RTW89_CHANCTX_CHANGES, 4058 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4059 }; 4060 4061 enum rtw89_entity_mode { 4062 RTW89_ENTITY_MODE_SCC, 4063 RTW89_ENTITY_MODE_MCC_PREPARE, 4064 RTW89_ENTITY_MODE_MCC, 4065 4066 NUM_OF_RTW89_ENTITY_MODE, 4067 RTW89_ENTITY_MODE_INVALID = NUM_OF_RTW89_ENTITY_MODE, 4068 }; 4069 4070 struct rtw89_sub_entity { 4071 struct cfg80211_chan_def chandef; 4072 struct rtw89_chan chan; 4073 struct rtw89_chan_rcd rcd; 4074 struct rtw89_chanctx_cfg *cfg; 4075 }; 4076 4077 struct rtw89_edcca_bak { 4078 u8 a; 4079 u8 p; 4080 u8 ppdu; 4081 u8 th_old; 4082 }; 4083 4084 enum rtw89_dm_type { 4085 RTW89_DM_DYNAMIC_EDCCA, 4086 }; 4087 4088 struct rtw89_hal { 4089 u32 rx_fltr; 4090 u8 cv; 4091 u8 acv; 4092 u32 antenna_tx; 4093 u32 antenna_rx; 4094 u8 tx_nss; 4095 u8 rx_nss; 4096 bool tx_path_diversity; 4097 bool ant_diversity; 4098 bool ant_diversity_fixed; 4099 bool support_cckpd; 4100 bool support_igi; 4101 atomic_t roc_entity_idx; 4102 4103 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4104 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4105 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4106 struct cfg80211_chan_def roc_chandef; 4107 4108 bool entity_active; 4109 bool entity_pause; 4110 enum rtw89_entity_mode entity_mode; 4111 4112 struct rtw89_edcca_bak edcca_bak; 4113 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4114 }; 4115 4116 #define RTW89_MAX_MAC_ID_NUM 128 4117 #define RTW89_MAX_PKT_OFLD_NUM 255 4118 4119 enum rtw89_flags { 4120 RTW89_FLAG_POWERON, 4121 RTW89_FLAG_DMAC_FUNC, 4122 RTW89_FLAG_CMAC0_FUNC, 4123 RTW89_FLAG_CMAC1_FUNC, 4124 RTW89_FLAG_FW_RDY, 4125 RTW89_FLAG_RUNNING, 4126 RTW89_FLAG_BFEE_MON, 4127 RTW89_FLAG_BFEE_EN, 4128 RTW89_FLAG_BFEE_TIMER_KEEP, 4129 RTW89_FLAG_NAPI_RUNNING, 4130 RTW89_FLAG_LEISURE_PS, 4131 RTW89_FLAG_LOW_POWER_MODE, 4132 RTW89_FLAG_INACTIVE_PS, 4133 RTW89_FLAG_CRASH_SIMULATING, 4134 RTW89_FLAG_SER_HANDLING, 4135 RTW89_FLAG_WOWLAN, 4136 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4137 RTW89_FLAG_CHANGING_INTERFACE, 4138 4139 NUM_OF_RTW89_FLAGS, 4140 }; 4141 4142 enum rtw89_pkt_drop_sel { 4143 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4144 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4145 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4146 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4147 RTW89_PKT_DROP_SEL_MACID_ALL, 4148 RTW89_PKT_DROP_SEL_MG0_ONCE, 4149 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4150 RTW89_PKT_DROP_SEL_HIQ_PORT, 4151 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4152 RTW89_PKT_DROP_SEL_BAND, 4153 RTW89_PKT_DROP_SEL_BAND_ONCE, 4154 RTW89_PKT_DROP_SEL_REL_MACID, 4155 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4156 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4157 }; 4158 4159 struct rtw89_pkt_drop_params { 4160 enum rtw89_pkt_drop_sel sel; 4161 enum rtw89_mac_idx mac_band; 4162 u8 macid; 4163 u8 port; 4164 u8 mbssid; 4165 bool tf_trs; 4166 u32 macid_band_sel[4]; 4167 }; 4168 4169 struct rtw89_pkt_stat { 4170 u16 beacon_nr; 4171 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4172 }; 4173 4174 DECLARE_EWMA(thermal, 4, 4); 4175 4176 struct rtw89_phy_stat { 4177 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4178 struct rtw89_pkt_stat cur_pkt_stat; 4179 struct rtw89_pkt_stat last_pkt_stat; 4180 }; 4181 4182 #define RTW89_DACK_PATH_NR 2 4183 #define RTW89_DACK_IDX_NR 2 4184 #define RTW89_DACK_MSBK_NR 16 4185 struct rtw89_dack_info { 4186 bool dack_done; 4187 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4188 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4189 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4190 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4191 u32 dack_cnt; 4192 bool addck_timeout[RTW89_DACK_PATH_NR]; 4193 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4194 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4195 }; 4196 4197 #define RTW89_IQK_CHS_NR 2 4198 #define RTW89_IQK_PATH_NR 4 4199 4200 struct rtw89_rfk_mcc_info { 4201 u8 ch[RTW89_IQK_CHS_NR]; 4202 u8 band[RTW89_IQK_CHS_NR]; 4203 u8 table_idx; 4204 }; 4205 4206 struct rtw89_lck_info { 4207 u8 thermal[RF_PATH_MAX]; 4208 }; 4209 4210 struct rtw89_rx_dck_info { 4211 u8 thermal[RF_PATH_MAX]; 4212 }; 4213 4214 struct rtw89_iqk_info { 4215 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4216 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4217 bool lok_fail[RTW89_IQK_PATH_NR]; 4218 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4219 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4220 u32 iqk_fail_cnt; 4221 bool is_iqk_init; 4222 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4223 u8 iqk_band[RTW89_IQK_PATH_NR]; 4224 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4225 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4226 u8 iqk_times; 4227 u8 version; 4228 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4229 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4230 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4231 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4232 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4233 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4234 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4235 bool is_nbiqk; 4236 bool iqk_fft_en; 4237 bool iqk_xym_en; 4238 bool iqk_sram_en; 4239 bool iqk_cfir_en; 4240 u32 syn1to2; 4241 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4242 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4243 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4244 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4245 }; 4246 4247 #define RTW89_DPK_RF_PATH 2 4248 #define RTW89_DPK_AVG_THERMAL_NUM 8 4249 #define RTW89_DPK_BKUP_NUM 2 4250 struct rtw89_dpk_bkup_para { 4251 enum rtw89_band band; 4252 enum rtw89_bandwidth bw; 4253 u8 ch; 4254 bool path_ok; 4255 u8 mdpd_en; 4256 u8 txagc_dpk; 4257 u8 ther_dpk; 4258 u8 gs; 4259 u16 pwsf; 4260 }; 4261 4262 struct rtw89_dpk_info { 4263 bool is_dpk_enable; 4264 bool is_dpk_reload_en; 4265 u8 dpk_gs[RTW89_PHY_MAX]; 4266 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4267 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4268 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4269 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4270 u8 cur_idx[RTW89_DPK_RF_PATH]; 4271 u8 cur_k_set; 4272 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4273 }; 4274 4275 struct rtw89_fem_info { 4276 bool elna_2g; 4277 bool elna_5g; 4278 bool epa_2g; 4279 bool epa_5g; 4280 bool epa_6g; 4281 }; 4282 4283 struct rtw89_phy_ch_info { 4284 u8 rssi_min; 4285 u16 rssi_min_macid; 4286 u8 pre_rssi_min; 4287 u8 rssi_max; 4288 u16 rssi_max_macid; 4289 u8 rxsc_160; 4290 u8 rxsc_80; 4291 u8 rxsc_40; 4292 u8 rxsc_20; 4293 u8 rxsc_l; 4294 u8 is_noisy; 4295 }; 4296 4297 struct rtw89_agc_gaincode_set { 4298 u8 lna_idx; 4299 u8 tia_idx; 4300 u8 rxb_idx; 4301 }; 4302 4303 #define IGI_RSSI_TH_NUM 5 4304 #define FA_TH_NUM 4 4305 #define LNA_GAIN_NUM 7 4306 #define TIA_GAIN_NUM 2 4307 struct rtw89_dig_info { 4308 struct rtw89_agc_gaincode_set cur_gaincode; 4309 bool force_gaincode_idx_en; 4310 struct rtw89_agc_gaincode_set force_gaincode; 4311 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4312 u16 fa_th[FA_TH_NUM]; 4313 u8 igi_rssi; 4314 u8 igi_fa_rssi; 4315 u8 fa_rssi_ofst; 4316 u8 dyn_igi_max; 4317 u8 dyn_igi_min; 4318 bool dyn_pd_th_en; 4319 u8 dyn_pd_th_max; 4320 u8 pd_low_th_ofst; 4321 u8 ib_pbk; 4322 s8 ib_pkpwr; 4323 s8 lna_gain_a[LNA_GAIN_NUM]; 4324 s8 lna_gain_g[LNA_GAIN_NUM]; 4325 s8 *lna_gain; 4326 s8 tia_gain_a[TIA_GAIN_NUM]; 4327 s8 tia_gain_g[TIA_GAIN_NUM]; 4328 s8 *tia_gain; 4329 bool is_linked_pre; 4330 bool bypass_dig; 4331 }; 4332 4333 enum rtw89_multi_cfo_mode { 4334 RTW89_PKT_BASED_AVG_MODE = 0, 4335 RTW89_ENTRY_BASED_AVG_MODE = 1, 4336 RTW89_TP_BASED_AVG_MODE = 2, 4337 }; 4338 4339 enum rtw89_phy_cfo_status { 4340 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4341 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4342 RTW89_PHY_DCFO_STATE_HOLD = 2, 4343 RTW89_PHY_DCFO_STATE_MAX 4344 }; 4345 4346 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4347 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4348 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4349 }; 4350 4351 struct rtw89_cfo_tracking_info { 4352 u16 cfo_timer_ms; 4353 bool cfo_trig_by_timer_en; 4354 enum rtw89_phy_cfo_status phy_cfo_status; 4355 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4356 u8 phy_cfo_trk_cnt; 4357 bool is_adjust; 4358 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4359 bool apply_compensation; 4360 u8 crystal_cap; 4361 u8 crystal_cap_default; 4362 u8 def_x_cap; 4363 s8 x_cap_ofst; 4364 u32 sta_cfo_tolerance; 4365 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4366 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4367 s32 cfo_avg_pre; 4368 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4369 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4370 s32 dcfo_avg; 4371 s32 dcfo_avg_pre; 4372 u32 packet_count; 4373 u32 packet_count_pre; 4374 s32 residual_cfo_acc; 4375 u8 phy_cfotrk_state; 4376 u8 phy_cfotrk_cnt; 4377 bool divergence_lock_en; 4378 u8 x_cap_lb; 4379 u8 x_cap_ub; 4380 u8 lock_cnt; 4381 }; 4382 4383 enum rtw89_tssi_alimk_band { 4384 TSSI_ALIMK_2G = 0, 4385 TSSI_ALIMK_5GL, 4386 TSSI_ALIMK_5GM, 4387 TSSI_ALIMK_5GH, 4388 TSSI_ALIMK_MAX 4389 }; 4390 4391 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4392 #define TSSI_TRIM_CH_GROUP_NUM 8 4393 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4394 4395 #define TSSI_CCK_CH_GROUP_NUM 6 4396 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4397 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4398 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4399 #define TSSI_MCS_CH_GROUP_NUM \ 4400 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4401 #define TSSI_MAX_CH_NUM 67 4402 #define TSSI_ALIMK_VALUE_NUM 8 4403 4404 struct rtw89_tssi_info { 4405 u8 thermal[RF_PATH_MAX]; 4406 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4407 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4408 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4409 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4410 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4411 s8 extra_ofst[RF_PATH_MAX]; 4412 bool tssi_tracking_check[RF_PATH_MAX]; 4413 u8 default_txagc_offset[RF_PATH_MAX]; 4414 u32 base_thermal[RF_PATH_MAX]; 4415 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4416 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4417 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4418 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4419 u32 tssi_alimk_time; 4420 }; 4421 4422 struct rtw89_power_trim_info { 4423 bool pg_thermal_trim; 4424 bool pg_pa_bias_trim; 4425 u8 thermal_trim[RF_PATH_MAX]; 4426 u8 pa_bias_trim[RF_PATH_MAX]; 4427 u8 pad_bias_trim[RF_PATH_MAX]; 4428 }; 4429 4430 struct rtw89_regd { 4431 char alpha2[3]; 4432 u8 txpwr_regd[RTW89_BAND_NUM]; 4433 }; 4434 4435 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4436 4437 struct rtw89_regulatory_info { 4438 const struct rtw89_regd *regd; 4439 enum rtw89_reg_6ghz_power reg_6ghz_power; 4440 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4441 }; 4442 4443 enum rtw89_ifs_clm_application { 4444 RTW89_IFS_CLM_INIT = 0, 4445 RTW89_IFS_CLM_BACKGROUND = 1, 4446 RTW89_IFS_CLM_ACS = 2, 4447 RTW89_IFS_CLM_DIG = 3, 4448 RTW89_IFS_CLM_TDMA_DIG = 4, 4449 RTW89_IFS_CLM_DBG = 5, 4450 RTW89_IFS_CLM_DBG_MANUAL = 6 4451 }; 4452 4453 enum rtw89_env_racing_lv { 4454 RTW89_RAC_RELEASE = 0, 4455 RTW89_RAC_LV_1 = 1, 4456 RTW89_RAC_LV_2 = 2, 4457 RTW89_RAC_LV_3 = 3, 4458 RTW89_RAC_LV_4 = 4, 4459 RTW89_RAC_MAX_NUM = 5 4460 }; 4461 4462 struct rtw89_ccx_para_info { 4463 enum rtw89_env_racing_lv rac_lv; 4464 u16 mntr_time; 4465 u8 nhm_manual_th_ofst; 4466 u8 nhm_manual_th0; 4467 enum rtw89_ifs_clm_application ifs_clm_app; 4468 u32 ifs_clm_manual_th_times; 4469 u32 ifs_clm_manual_th0; 4470 u8 fahm_manual_th_ofst; 4471 u8 fahm_manual_th0; 4472 u8 fahm_numer_opt; 4473 u8 fahm_denom_opt; 4474 }; 4475 4476 enum rtw89_ccx_edcca_opt_sc_idx { 4477 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4478 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4479 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4480 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4481 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4482 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4483 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4484 RTW89_CCX_EDCCA_SEG1_S3 = 7 4485 }; 4486 4487 enum rtw89_ccx_edcca_opt_bw_idx { 4488 RTW89_CCX_EDCCA_BW20_0 = 0, 4489 RTW89_CCX_EDCCA_BW20_1 = 1, 4490 RTW89_CCX_EDCCA_BW20_2 = 2, 4491 RTW89_CCX_EDCCA_BW20_3 = 3, 4492 RTW89_CCX_EDCCA_BW20_4 = 4, 4493 RTW89_CCX_EDCCA_BW20_5 = 5, 4494 RTW89_CCX_EDCCA_BW20_6 = 6, 4495 RTW89_CCX_EDCCA_BW20_7 = 7 4496 }; 4497 4498 #define RTW89_NHM_TH_NUM 11 4499 #define RTW89_FAHM_TH_NUM 11 4500 #define RTW89_NHM_RPT_NUM 12 4501 #define RTW89_FAHM_RPT_NUM 12 4502 #define RTW89_IFS_CLM_NUM 4 4503 struct rtw89_env_monitor_info { 4504 u8 ccx_watchdog_result; 4505 bool ccx_ongoing; 4506 u8 ccx_rac_lv; 4507 bool ccx_manual_ctrl; 4508 u16 ifs_clm_mntr_time; 4509 enum rtw89_ifs_clm_application ifs_clm_app; 4510 u16 ccx_period; 4511 u8 ccx_unit_idx; 4512 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4513 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4514 u16 ifs_clm_tx; 4515 u16 ifs_clm_edcca_excl_cca; 4516 u16 ifs_clm_ofdmfa; 4517 u16 ifs_clm_ofdmcca_excl_fa; 4518 u16 ifs_clm_cckfa; 4519 u16 ifs_clm_cckcca_excl_fa; 4520 u16 ifs_clm_total_ifs; 4521 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4522 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4523 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4524 u8 ifs_clm_tx_ratio; 4525 u8 ifs_clm_edcca_excl_cca_ratio; 4526 u8 ifs_clm_cck_fa_ratio; 4527 u8 ifs_clm_ofdm_fa_ratio; 4528 u8 ifs_clm_cck_cca_excl_fa_ratio; 4529 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4530 u16 ifs_clm_cck_fa_permil; 4531 u16 ifs_clm_ofdm_fa_permil; 4532 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4533 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4534 }; 4535 4536 enum rtw89_ser_rcvy_step { 4537 RTW89_SER_DRV_STOP_TX, 4538 RTW89_SER_DRV_STOP_RX, 4539 RTW89_SER_DRV_STOP_RUN, 4540 RTW89_SER_HAL_STOP_DMA, 4541 RTW89_SER_SUPPRESS_LOG, 4542 RTW89_NUM_OF_SER_FLAGS 4543 }; 4544 4545 struct rtw89_ser { 4546 u8 state; 4547 u8 alarm_event; 4548 bool prehandle_l1; 4549 4550 struct work_struct ser_hdl_work; 4551 struct delayed_work ser_alarm_work; 4552 const struct state_ent *st_tbl; 4553 const struct event_ent *ev_tbl; 4554 struct list_head msg_q; 4555 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4556 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4557 }; 4558 4559 enum rtw89_mac_ax_ps_mode { 4560 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4561 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4562 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4563 RTW89_MAC_AX_PS_MODE_MAX = 3, 4564 }; 4565 4566 enum rtw89_last_rpwm_mode { 4567 RTW89_LAST_RPWM_PS = 0x0, 4568 RTW89_LAST_RPWM_ACTIVE = 0x6, 4569 }; 4570 4571 struct rtw89_lps_parm { 4572 u8 macid; 4573 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4574 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4575 }; 4576 4577 struct rtw89_ppdu_sts_info { 4578 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4579 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4580 }; 4581 4582 struct rtw89_early_h2c { 4583 struct list_head list; 4584 u8 *h2c; 4585 u16 h2c_len; 4586 }; 4587 4588 struct rtw89_hw_scan_info { 4589 struct ieee80211_vif *scanning_vif; 4590 struct list_head pkt_list[NUM_NL80211_BANDS]; 4591 struct rtw89_chan op_chan; 4592 u32 last_chan_idx; 4593 }; 4594 4595 enum rtw89_phy_bb_gain_band { 4596 RTW89_BB_GAIN_BAND_2G = 0, 4597 RTW89_BB_GAIN_BAND_5G_L = 1, 4598 RTW89_BB_GAIN_BAND_5G_M = 2, 4599 RTW89_BB_GAIN_BAND_5G_H = 3, 4600 RTW89_BB_GAIN_BAND_6G_L = 4, 4601 RTW89_BB_GAIN_BAND_6G_M = 5, 4602 RTW89_BB_GAIN_BAND_6G_H = 6, 4603 RTW89_BB_GAIN_BAND_6G_UH = 7, 4604 4605 RTW89_BB_GAIN_BAND_NR, 4606 }; 4607 4608 enum rtw89_phy_bb_rxsc_num { 4609 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4610 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4611 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4612 }; 4613 4614 struct rtw89_phy_bb_gain_info { 4615 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4616 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4617 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4618 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4619 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4620 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4621 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4622 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4623 [RTW89_BB_RXSC_NUM_40]; 4624 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4625 [RTW89_BB_RXSC_NUM_80]; 4626 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4627 [RTW89_BB_RXSC_NUM_160]; 4628 }; 4629 4630 struct rtw89_phy_efuse_gain { 4631 bool offset_valid; 4632 bool comp_valid; 4633 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4634 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4635 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4636 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4637 }; 4638 4639 #define RTW89_MAX_PATTERN_NUM 18 4640 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4641 #define RTW89_MAX_PATTERN_SIZE 128 4642 4643 struct rtw89_wow_cam_info { 4644 bool r_w; 4645 u8 idx; 4646 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4647 u16 crc; 4648 bool negative_pattern_match; 4649 bool skip_mac_hdr; 4650 bool uc; 4651 bool mc; 4652 bool bc; 4653 bool valid; 4654 }; 4655 4656 struct rtw89_wow_param { 4657 struct ieee80211_vif *wow_vif; 4658 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4659 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4660 u8 pattern_cnt; 4661 }; 4662 4663 struct rtw89_mcc_limit { 4664 bool enable; 4665 u16 max_tob; /* TU; max time offset behind */ 4666 u16 max_toa; /* TU; max time offset ahead */ 4667 u16 max_dur; /* TU */ 4668 }; 4669 4670 struct rtw89_mcc_policy { 4671 u8 c2h_rpt; 4672 u8 tx_null_early; 4673 u8 dis_tx_null; 4674 u8 in_curr_ch; 4675 u8 dis_sw_retry; 4676 u8 sw_retry_count; 4677 }; 4678 4679 struct rtw89_mcc_role { 4680 struct rtw89_vif *rtwvif; 4681 struct rtw89_mcc_policy policy; 4682 struct rtw89_mcc_limit limit; 4683 4684 /* byte-array in LE order for FW */ 4685 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 4686 4687 u16 duration; /* TU */ 4688 u16 beacon_interval; /* TU */ 4689 bool is_2ghz; 4690 bool is_go; 4691 bool is_gc; 4692 }; 4693 4694 struct rtw89_mcc_bt_role { 4695 u16 duration; /* TU */ 4696 }; 4697 4698 struct rtw89_mcc_courtesy { 4699 bool enable; 4700 u8 slot_num; 4701 u8 macid_src; 4702 u8 macid_tgt; 4703 }; 4704 4705 enum rtw89_mcc_plan { 4706 RTW89_MCC_PLAN_TAIL_BT, 4707 RTW89_MCC_PLAN_MID_BT, 4708 RTW89_MCC_PLAN_NO_BT, 4709 4710 NUM_OF_RTW89_MCC_PLAN, 4711 }; 4712 4713 struct rtw89_mcc_pattern { 4714 s16 tob_ref; /* TU; time offset behind of reference role */ 4715 s16 toa_ref; /* TU; time offset ahead of reference role */ 4716 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 4717 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 4718 4719 enum rtw89_mcc_plan plan; 4720 struct rtw89_mcc_courtesy courtesy; 4721 }; 4722 4723 struct rtw89_mcc_sync { 4724 bool enable; 4725 u16 offset; /* TU */ 4726 u8 macid_src; 4727 u8 macid_tgt; 4728 }; 4729 4730 struct rtw89_mcc_config { 4731 struct rtw89_mcc_pattern pattern; 4732 struct rtw89_mcc_sync sync; 4733 u64 start_tsf; 4734 u16 mcc_interval; /* TU */ 4735 u16 beacon_offset; /* TU */ 4736 }; 4737 4738 enum rtw89_mcc_mode { 4739 RTW89_MCC_MODE_GO_STA, 4740 RTW89_MCC_MODE_GC_STA, 4741 }; 4742 4743 struct rtw89_mcc_info { 4744 struct rtw89_wait_info wait; 4745 4746 u8 group; 4747 enum rtw89_mcc_mode mode; 4748 struct rtw89_mcc_role role_ref; /* reference role */ 4749 struct rtw89_mcc_role role_aux; /* auxiliary role */ 4750 struct rtw89_mcc_bt_role bt_role; 4751 struct rtw89_mcc_config config; 4752 }; 4753 4754 struct rtw89_dev { 4755 struct ieee80211_hw *hw; 4756 struct device *dev; 4757 const struct ieee80211_ops *ops; 4758 4759 bool dbcc_en; 4760 struct rtw89_hw_scan_info scan_info; 4761 const struct rtw89_chip_info *chip; 4762 const struct rtw89_pci_info *pci_info; 4763 const struct rtw89_rfe_parms *rfe_parms; 4764 struct rtw89_hal hal; 4765 struct rtw89_mcc_info mcc; 4766 struct rtw89_mac_info mac; 4767 struct rtw89_fw_info fw; 4768 struct rtw89_hci_info hci; 4769 struct rtw89_efuse efuse; 4770 struct rtw89_traffic_stats stats; 4771 struct rtw89_rfe_data *rfe_data; 4772 4773 /* ensures exclusive access from mac80211 callbacks */ 4774 struct mutex mutex; 4775 struct list_head rtwvifs_list; 4776 /* used to protect rf read write */ 4777 struct mutex rf_mutex; 4778 struct workqueue_struct *txq_wq; 4779 struct work_struct txq_work; 4780 struct delayed_work txq_reinvoke_work; 4781 /* used to protect ba_list and forbid_ba_list */ 4782 spinlock_t ba_lock; 4783 /* txqs to setup ba session */ 4784 struct list_head ba_list; 4785 /* txqs to forbid ba session */ 4786 struct list_head forbid_ba_list; 4787 struct work_struct ba_work; 4788 /* used to protect rpwm */ 4789 spinlock_t rpwm_lock; 4790 4791 struct rtw89_cam_info cam_info; 4792 4793 struct sk_buff_head c2h_queue; 4794 struct work_struct c2h_work; 4795 struct work_struct ips_work; 4796 struct work_struct load_firmware_work; 4797 struct work_struct cancel_6ghz_probe_work; 4798 4799 struct list_head early_h2c_list; 4800 4801 struct rtw89_ser ser; 4802 4803 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4804 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 4805 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 4806 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 4807 4808 struct rtw89_phy_stat phystat; 4809 struct rtw89_dack_info dack; 4810 struct rtw89_iqk_info iqk; 4811 struct rtw89_dpk_info dpk; 4812 struct rtw89_rfk_mcc_info rfk_mcc; 4813 struct rtw89_lck_info lck; 4814 struct rtw89_rx_dck_info rx_dck; 4815 bool is_tssi_mode[RF_PATH_MAX]; 4816 bool is_bt_iqk_timeout; 4817 4818 struct rtw89_fem_info fem; 4819 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 4820 struct rtw89_tssi_info tssi; 4821 struct rtw89_power_trim_info pwr_trim; 4822 4823 struct rtw89_cfo_tracking_info cfo_tracking; 4824 struct rtw89_env_monitor_info env_monitor; 4825 struct rtw89_dig_info dig; 4826 struct rtw89_phy_ch_info ch_info; 4827 struct rtw89_phy_bb_gain_info bb_gain; 4828 struct rtw89_phy_efuse_gain efuse_gain; 4829 struct rtw89_phy_ul_tb_info ul_tb_info; 4830 struct rtw89_antdiv_info antdiv; 4831 4832 struct delayed_work track_work; 4833 struct delayed_work chanctx_work; 4834 struct delayed_work coex_act1_work; 4835 struct delayed_work coex_bt_devinfo_work; 4836 struct delayed_work coex_rfk_chk_work; 4837 struct delayed_work cfo_track_work; 4838 struct delayed_work forbid_ba_work; 4839 struct delayed_work roc_work; 4840 struct delayed_work antdiv_work; 4841 struct rtw89_ppdu_sts_info ppdu_sts; 4842 u8 total_sta_assoc; 4843 bool scanning; 4844 4845 struct rtw89_regulatory_info regulatory; 4846 struct rtw89_sar_info sar; 4847 struct rtw89_tas_info tas; 4848 4849 struct rtw89_btc btc; 4850 enum rtw89_ps_mode ps_mode; 4851 bool lps_enabled; 4852 4853 struct rtw89_wow_param wow; 4854 4855 /* napi structure */ 4856 struct net_device netdev; 4857 struct napi_struct napi; 4858 int napi_budget_countdown; 4859 4860 /* HCI related data, keep last */ 4861 u8 priv[] __aligned(sizeof(void *)); 4862 }; 4863 4864 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4865 struct rtw89_core_tx_request *tx_req) 4866 { 4867 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4868 } 4869 4870 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4871 { 4872 rtwdev->hci.ops->reset(rtwdev); 4873 } 4874 4875 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4876 { 4877 return rtwdev->hci.ops->start(rtwdev); 4878 } 4879 4880 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4881 { 4882 rtwdev->hci.ops->stop(rtwdev); 4883 } 4884 4885 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4886 { 4887 return rtwdev->hci.ops->deinit(rtwdev); 4888 } 4889 4890 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4891 { 4892 rtwdev->hci.ops->pause(rtwdev, pause); 4893 } 4894 4895 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4896 { 4897 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4898 } 4899 4900 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4901 { 4902 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4903 } 4904 4905 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4906 { 4907 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4908 } 4909 4910 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4911 { 4912 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4913 } 4914 4915 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 4916 { 4917 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 4918 } 4919 4920 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4921 bool drop) 4922 { 4923 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4924 return; 4925 4926 if (rtwdev->hci.ops->flush_queues) 4927 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4928 } 4929 4930 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4931 { 4932 if (rtwdev->hci.ops->recovery_start) 4933 rtwdev->hci.ops->recovery_start(rtwdev); 4934 } 4935 4936 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4937 { 4938 if (rtwdev->hci.ops->recovery_complete) 4939 rtwdev->hci.ops->recovery_complete(rtwdev); 4940 } 4941 4942 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4943 { 4944 if (rtwdev->hci.ops->enable_intr) 4945 rtwdev->hci.ops->enable_intr(rtwdev); 4946 } 4947 4948 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4949 { 4950 if (rtwdev->hci.ops->disable_intr) 4951 rtwdev->hci.ops->disable_intr(rtwdev); 4952 } 4953 4954 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4955 { 4956 if (rtwdev->hci.ops->ctrl_txdma_ch) 4957 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4958 } 4959 4960 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4961 { 4962 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4963 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4964 } 4965 4966 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4967 { 4968 if (rtwdev->hci.ops->ctrl_trxhci) 4969 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4970 } 4971 4972 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4973 { 4974 int ret = 0; 4975 4976 if (rtwdev->hci.ops->poll_txdma_ch) 4977 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4978 return ret; 4979 } 4980 4981 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4982 { 4983 if (rtwdev->hci.ops->clr_idx_all) 4984 rtwdev->hci.ops->clr_idx_all(rtwdev); 4985 } 4986 4987 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4988 { 4989 int ret = 0; 4990 4991 if (rtwdev->hci.ops->rst_bdram) 4992 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4993 return ret; 4994 } 4995 4996 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4997 { 4998 if (rtwdev->hci.ops->clear) 4999 rtwdev->hci.ops->clear(rtwdev, pdev); 5000 } 5001 5002 static inline 5003 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5004 { 5005 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5006 5007 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5008 } 5009 5010 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5011 { 5012 return rtwdev->hci.ops->read8(rtwdev, addr); 5013 } 5014 5015 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5016 { 5017 return rtwdev->hci.ops->read16(rtwdev, addr); 5018 } 5019 5020 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5021 { 5022 return rtwdev->hci.ops->read32(rtwdev, addr); 5023 } 5024 5025 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5026 { 5027 rtwdev->hci.ops->write8(rtwdev, addr, data); 5028 } 5029 5030 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5031 { 5032 rtwdev->hci.ops->write16(rtwdev, addr, data); 5033 } 5034 5035 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5036 { 5037 rtwdev->hci.ops->write32(rtwdev, addr, data); 5038 } 5039 5040 static inline void 5041 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5042 { 5043 u8 val; 5044 5045 val = rtw89_read8(rtwdev, addr); 5046 rtw89_write8(rtwdev, addr, val | bit); 5047 } 5048 5049 static inline void 5050 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5051 { 5052 u16 val; 5053 5054 val = rtw89_read16(rtwdev, addr); 5055 rtw89_write16(rtwdev, addr, val | bit); 5056 } 5057 5058 static inline void 5059 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5060 { 5061 u32 val; 5062 5063 val = rtw89_read32(rtwdev, addr); 5064 rtw89_write32(rtwdev, addr, val | bit); 5065 } 5066 5067 static inline void 5068 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5069 { 5070 u8 val; 5071 5072 val = rtw89_read8(rtwdev, addr); 5073 rtw89_write8(rtwdev, addr, val & ~bit); 5074 } 5075 5076 static inline void 5077 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5078 { 5079 u16 val; 5080 5081 val = rtw89_read16(rtwdev, addr); 5082 rtw89_write16(rtwdev, addr, val & ~bit); 5083 } 5084 5085 static inline void 5086 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5087 { 5088 u32 val; 5089 5090 val = rtw89_read32(rtwdev, addr); 5091 rtw89_write32(rtwdev, addr, val & ~bit); 5092 } 5093 5094 static inline u32 5095 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5096 { 5097 u32 shift = __ffs(mask); 5098 u32 orig; 5099 u32 ret; 5100 5101 orig = rtw89_read32(rtwdev, addr); 5102 ret = (orig & mask) >> shift; 5103 5104 return ret; 5105 } 5106 5107 static inline u16 5108 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5109 { 5110 u32 shift = __ffs(mask); 5111 u32 orig; 5112 u32 ret; 5113 5114 orig = rtw89_read16(rtwdev, addr); 5115 ret = (orig & mask) >> shift; 5116 5117 return ret; 5118 } 5119 5120 static inline u8 5121 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5122 { 5123 u32 shift = __ffs(mask); 5124 u32 orig; 5125 u32 ret; 5126 5127 orig = rtw89_read8(rtwdev, addr); 5128 ret = (orig & mask) >> shift; 5129 5130 return ret; 5131 } 5132 5133 static inline void 5134 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5135 { 5136 u32 shift = __ffs(mask); 5137 u32 orig; 5138 u32 set; 5139 5140 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5141 5142 orig = rtw89_read32(rtwdev, addr); 5143 set = (orig & ~mask) | ((data << shift) & mask); 5144 rtw89_write32(rtwdev, addr, set); 5145 } 5146 5147 static inline void 5148 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5149 { 5150 u32 shift; 5151 u16 orig, set; 5152 5153 mask &= 0xffff; 5154 shift = __ffs(mask); 5155 5156 orig = rtw89_read16(rtwdev, addr); 5157 set = (orig & ~mask) | ((data << shift) & mask); 5158 rtw89_write16(rtwdev, addr, set); 5159 } 5160 5161 static inline void 5162 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5163 { 5164 u32 shift; 5165 u8 orig, set; 5166 5167 mask &= 0xff; 5168 shift = __ffs(mask); 5169 5170 orig = rtw89_read8(rtwdev, addr); 5171 set = (orig & ~mask) | ((data << shift) & mask); 5172 rtw89_write8(rtwdev, addr, set); 5173 } 5174 5175 static inline u32 5176 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5177 u32 addr, u32 mask) 5178 { 5179 u32 val; 5180 5181 mutex_lock(&rtwdev->rf_mutex); 5182 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5183 mutex_unlock(&rtwdev->rf_mutex); 5184 5185 return val; 5186 } 5187 5188 static inline void 5189 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5190 u32 addr, u32 mask, u32 data) 5191 { 5192 mutex_lock(&rtwdev->rf_mutex); 5193 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5194 mutex_unlock(&rtwdev->rf_mutex); 5195 } 5196 5197 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5198 { 5199 void *p = rtwtxq; 5200 5201 return container_of(p, struct ieee80211_txq, drv_priv); 5202 } 5203 5204 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5205 struct ieee80211_txq *txq) 5206 { 5207 struct rtw89_txq *rtwtxq; 5208 5209 if (!txq) 5210 return; 5211 5212 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5213 INIT_LIST_HEAD(&rtwtxq->list); 5214 } 5215 5216 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5217 { 5218 void *p = rtwvif; 5219 5220 return container_of(p, struct ieee80211_vif, drv_priv); 5221 } 5222 5223 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5224 { 5225 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5226 } 5227 5228 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5229 { 5230 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5231 } 5232 5233 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5234 { 5235 void *p = rtwsta; 5236 5237 return container_of(p, struct ieee80211_sta, drv_priv); 5238 } 5239 5240 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5241 { 5242 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5243 } 5244 5245 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5246 { 5247 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5248 } 5249 5250 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5251 { 5252 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5253 return RATE_INFO_BW_160; 5254 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5255 return RATE_INFO_BW_80; 5256 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5257 return RATE_INFO_BW_40; 5258 else 5259 return RATE_INFO_BW_20; 5260 } 5261 5262 static inline 5263 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5264 { 5265 switch (hw_band) { 5266 default: 5267 case RTW89_BAND_2G: 5268 return NL80211_BAND_2GHZ; 5269 case RTW89_BAND_5G: 5270 return NL80211_BAND_5GHZ; 5271 case RTW89_BAND_6G: 5272 return NL80211_BAND_6GHZ; 5273 } 5274 } 5275 5276 static inline 5277 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5278 { 5279 switch (nl_band) { 5280 default: 5281 case NL80211_BAND_2GHZ: 5282 return RTW89_BAND_2G; 5283 case NL80211_BAND_5GHZ: 5284 return RTW89_BAND_5G; 5285 case NL80211_BAND_6GHZ: 5286 return RTW89_BAND_6G; 5287 } 5288 } 5289 5290 static inline 5291 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5292 { 5293 switch (width) { 5294 default: 5295 WARN(1, "Not support bandwidth %d\n", width); 5296 fallthrough; 5297 case NL80211_CHAN_WIDTH_20_NOHT: 5298 case NL80211_CHAN_WIDTH_20: 5299 return RTW89_CHANNEL_WIDTH_20; 5300 case NL80211_CHAN_WIDTH_40: 5301 return RTW89_CHANNEL_WIDTH_40; 5302 case NL80211_CHAN_WIDTH_80: 5303 return RTW89_CHANNEL_WIDTH_80; 5304 case NL80211_CHAN_WIDTH_160: 5305 return RTW89_CHANNEL_WIDTH_160; 5306 } 5307 } 5308 5309 static inline 5310 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5311 { 5312 switch (rua) { 5313 default: 5314 WARN(1, "Invalid RU allocation: %d\n", rua); 5315 fallthrough; 5316 case 0 ... 36: 5317 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5318 case 37 ... 52: 5319 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5320 case 53 ... 60: 5321 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5322 case 61 ... 64: 5323 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5324 case 65 ... 66: 5325 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5326 case 67: 5327 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5328 case 68: 5329 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5330 } 5331 } 5332 5333 static inline 5334 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5335 struct rtw89_sta *rtwsta) 5336 { 5337 if (rtwsta) { 5338 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5339 5340 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5341 return &rtwsta->addr_cam; 5342 } 5343 return &rtwvif->addr_cam; 5344 } 5345 5346 static inline 5347 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5348 struct rtw89_sta *rtwsta) 5349 { 5350 if (rtwsta) { 5351 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5352 5353 if (sta->tdls) 5354 return &rtwsta->bssid_cam; 5355 } 5356 return &rtwvif->bssid_cam; 5357 } 5358 5359 static inline 5360 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5361 struct rtw89_channel_help_params *p, 5362 const struct rtw89_chan *chan, 5363 enum rtw89_mac_idx mac_idx, 5364 enum rtw89_phy_idx phy_idx) 5365 { 5366 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5367 mac_idx, phy_idx); 5368 } 5369 5370 static inline 5371 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 5372 struct rtw89_channel_help_params *p, 5373 const struct rtw89_chan *chan, 5374 enum rtw89_mac_idx mac_idx, 5375 enum rtw89_phy_idx phy_idx) 5376 { 5377 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 5378 mac_idx, phy_idx); 5379 } 5380 5381 static inline 5382 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 5383 enum rtw89_sub_entity_idx idx) 5384 { 5385 struct rtw89_hal *hal = &rtwdev->hal; 5386 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 5387 5388 if (roc_idx == idx) 5389 return &hal->roc_chandef; 5390 5391 return &hal->sub[idx].chandef; 5392 } 5393 5394 static inline 5395 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 5396 enum rtw89_sub_entity_idx idx) 5397 { 5398 struct rtw89_hal *hal = &rtwdev->hal; 5399 5400 return &hal->sub[idx].chan; 5401 } 5402 5403 static inline 5404 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 5405 enum rtw89_sub_entity_idx idx) 5406 { 5407 struct rtw89_hal *hal = &rtwdev->hal; 5408 5409 return &hal->sub[idx].rcd; 5410 } 5411 5412 static inline 5413 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 5414 { 5415 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 5416 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 5417 5418 if (rtwvif) 5419 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 5420 else 5421 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5422 } 5423 5424 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 5425 { 5426 const struct rtw89_chip_info *chip = rtwdev->chip; 5427 5428 if (chip->ops->fem_setup) 5429 chip->ops->fem_setup(rtwdev); 5430 } 5431 5432 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 5433 { 5434 const struct rtw89_chip_info *chip = rtwdev->chip; 5435 5436 if (chip->ops->rfe_gpio) 5437 chip->ops->rfe_gpio(rtwdev); 5438 } 5439 5440 static inline 5441 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5442 { 5443 const struct rtw89_chip_info *chip = rtwdev->chip; 5444 5445 if (chip->ops->bb_preinit) 5446 chip->ops->bb_preinit(rtwdev, phy_idx); 5447 } 5448 5449 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 5450 { 5451 const struct rtw89_chip_info *chip = rtwdev->chip; 5452 5453 if (chip->ops->bb_sethw) 5454 chip->ops->bb_sethw(rtwdev); 5455 } 5456 5457 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 5458 { 5459 const struct rtw89_chip_info *chip = rtwdev->chip; 5460 5461 if (chip->ops->rfk_init) 5462 chip->ops->rfk_init(rtwdev); 5463 } 5464 5465 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 5466 { 5467 const struct rtw89_chip_info *chip = rtwdev->chip; 5468 5469 if (chip->ops->rfk_channel) 5470 chip->ops->rfk_channel(rtwdev); 5471 } 5472 5473 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 5474 enum rtw89_phy_idx phy_idx) 5475 { 5476 const struct rtw89_chip_info *chip = rtwdev->chip; 5477 5478 if (chip->ops->rfk_band_changed) 5479 chip->ops->rfk_band_changed(rtwdev, phy_idx); 5480 } 5481 5482 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 5483 { 5484 const struct rtw89_chip_info *chip = rtwdev->chip; 5485 5486 if (chip->ops->rfk_scan) 5487 chip->ops->rfk_scan(rtwdev, start); 5488 } 5489 5490 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 5491 { 5492 const struct rtw89_chip_info *chip = rtwdev->chip; 5493 5494 if (chip->ops->rfk_track) 5495 chip->ops->rfk_track(rtwdev); 5496 } 5497 5498 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 5499 { 5500 const struct rtw89_chip_info *chip = rtwdev->chip; 5501 5502 if (chip->ops->set_txpwr_ctrl) 5503 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 5504 } 5505 5506 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 5507 { 5508 const struct rtw89_chip_info *chip = rtwdev->chip; 5509 5510 if (chip->ops->power_trim) 5511 chip->ops->power_trim(rtwdev); 5512 } 5513 5514 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 5515 enum rtw89_phy_idx phy_idx) 5516 { 5517 const struct rtw89_chip_info *chip = rtwdev->chip; 5518 5519 if (chip->ops->init_txpwr_unit) 5520 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 5521 } 5522 5523 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 5524 enum rtw89_rf_path rf_path) 5525 { 5526 const struct rtw89_chip_info *chip = rtwdev->chip; 5527 5528 if (!chip->ops->get_thermal) 5529 return 0x10; 5530 5531 return chip->ops->get_thermal(rtwdev, rf_path); 5532 } 5533 5534 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 5535 struct rtw89_rx_phy_ppdu *phy_ppdu, 5536 struct ieee80211_rx_status *status) 5537 { 5538 const struct rtw89_chip_info *chip = rtwdev->chip; 5539 5540 if (chip->ops->query_ppdu) 5541 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 5542 } 5543 5544 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 5545 enum rtw89_phy_idx phy_idx) 5546 { 5547 const struct rtw89_chip_info *chip = rtwdev->chip; 5548 5549 if (chip->ops->ctrl_nbtg_bt_tx) 5550 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 5551 } 5552 5553 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 5554 { 5555 const struct rtw89_chip_info *chip = rtwdev->chip; 5556 5557 if (chip->ops->cfg_txrx_path) 5558 chip->ops->cfg_txrx_path(rtwdev); 5559 } 5560 5561 static inline 5562 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5563 struct ieee80211_vif *vif) 5564 { 5565 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5566 const struct rtw89_chip_info *chip = rtwdev->chip; 5567 5568 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5569 return; 5570 5571 if (chip->ops->set_txpwr_ul_tb_offset) 5572 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5573 } 5574 5575 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 5576 const struct rtw89_txpwr_table *tbl) 5577 { 5578 tbl->load(rtwdev, tbl); 5579 } 5580 5581 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 5582 { 5583 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 5584 5585 return regd->txpwr_regd[band]; 5586 } 5587 5588 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 5589 enum rtw89_phy_idx phy_idx) 5590 { 5591 const struct rtw89_chip_info *chip = rtwdev->chip; 5592 5593 if (chip->ops->ctrl_btg_bt_rx) 5594 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 5595 } 5596 5597 static inline 5598 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 5599 struct rtw89_rx_desc_info *desc_info, 5600 u8 *data, u32 data_offset) 5601 { 5602 const struct rtw89_chip_info *chip = rtwdev->chip; 5603 5604 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 5605 } 5606 5607 static inline 5608 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 5609 struct rtw89_tx_desc_info *desc_info, 5610 void *txdesc) 5611 { 5612 const struct rtw89_chip_info *chip = rtwdev->chip; 5613 5614 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 5615 } 5616 5617 static inline 5618 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 5619 struct rtw89_tx_desc_info *desc_info, 5620 void *txdesc) 5621 { 5622 const struct rtw89_chip_info *chip = rtwdev->chip; 5623 5624 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 5625 } 5626 5627 static inline 5628 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5629 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5630 { 5631 const struct rtw89_chip_info *chip = rtwdev->chip; 5632 5633 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 5634 } 5635 5636 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5637 { 5638 const struct rtw89_chip_info *chip = rtwdev->chip; 5639 5640 chip->ops->cfg_ctrl_path(rtwdev, wl); 5641 } 5642 5643 static inline 5644 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 5645 u32 *tx_en, enum rtw89_sch_tx_sel sel) 5646 { 5647 const struct rtw89_chip_info *chip = rtwdev->chip; 5648 5649 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 5650 } 5651 5652 static inline 5653 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 5654 { 5655 const struct rtw89_chip_info *chip = rtwdev->chip; 5656 5657 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 5658 } 5659 5660 static inline 5661 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 5662 struct rtw89_vif *rtwvif, 5663 struct rtw89_sta *rtwsta) 5664 { 5665 const struct rtw89_chip_info *chip = rtwdev->chip; 5666 5667 if (!chip->ops->h2c_dctl_sec_cam) 5668 return 0; 5669 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 5670 } 5671 5672 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 5673 { 5674 __le16 fc = hdr->frame_control; 5675 5676 if (ieee80211_has_tods(fc)) 5677 return hdr->addr1; 5678 else if (ieee80211_has_fromds(fc)) 5679 return hdr->addr2; 5680 else 5681 return hdr->addr3; 5682 } 5683 5684 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 5685 { 5686 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5687 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 5688 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 5689 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5690 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 5691 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 5692 return true; 5693 return false; 5694 } 5695 5696 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 5697 enum rtw89_fw_type type) 5698 { 5699 struct rtw89_fw_info *fw_info = &rtwdev->fw; 5700 5701 switch (type) { 5702 case RTW89_FW_WOWLAN: 5703 return &fw_info->wowlan; 5704 case RTW89_FW_LOGFMT: 5705 return &fw_info->log.suit; 5706 case RTW89_FW_BBMCU0: 5707 return &fw_info->bbmcu0; 5708 case RTW89_FW_BBMCU1: 5709 return &fw_info->bbmcu1; 5710 default: 5711 break; 5712 } 5713 5714 return &fw_info->normal; 5715 } 5716 5717 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 5718 unsigned int length) 5719 { 5720 struct sk_buff *skb; 5721 5722 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 5723 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 5724 if (!skb) 5725 return NULL; 5726 5727 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 5728 return skb; 5729 } 5730 5731 return dev_alloc_skb(length); 5732 } 5733 5734 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 5735 struct rtw89_tx_skb_data *skb_data, 5736 bool tx_done) 5737 { 5738 struct rtw89_tx_wait_info *wait; 5739 5740 rcu_read_lock(); 5741 5742 wait = rcu_dereference(skb_data->wait); 5743 if (!wait) 5744 goto out; 5745 5746 wait->tx_done = tx_done; 5747 complete(&wait->completion); 5748 5749 out: 5750 rcu_read_unlock(); 5751 } 5752 5753 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5754 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 5755 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 5756 struct sk_buff *skb, bool fwdl); 5757 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 5758 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5759 int qsel, unsigned int timeout); 5760 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 5761 struct rtw89_tx_desc_info *desc_info, 5762 void *txdesc); 5763 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 5764 struct rtw89_tx_desc_info *desc_info, 5765 void *txdesc); 5766 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 5767 struct rtw89_tx_desc_info *desc_info, 5768 void *txdesc); 5769 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 5770 struct rtw89_tx_desc_info *desc_info, 5771 void *txdesc); 5772 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 5773 struct rtw89_tx_desc_info *desc_info, 5774 void *txdesc); 5775 void rtw89_core_rx(struct rtw89_dev *rtwdev, 5776 struct rtw89_rx_desc_info *desc_info, 5777 struct sk_buff *skb); 5778 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 5779 struct rtw89_rx_desc_info *desc_info, 5780 u8 *data, u32 data_offset); 5781 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 5782 struct rtw89_rx_desc_info *desc_info, 5783 u8 *data, u32 data_offset); 5784 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 5785 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 5786 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 5787 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 5788 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 5789 struct ieee80211_vif *vif, 5790 struct ieee80211_sta *sta); 5791 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 5792 struct ieee80211_vif *vif, 5793 struct ieee80211_sta *sta); 5794 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 5795 struct ieee80211_vif *vif, 5796 struct ieee80211_sta *sta); 5797 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 5798 struct ieee80211_vif *vif, 5799 struct ieee80211_sta *sta); 5800 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 5801 struct ieee80211_vif *vif, 5802 struct ieee80211_sta *sta); 5803 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5804 struct ieee80211_sta *sta, 5805 struct cfg80211_tid_config *tid_config); 5806 int rtw89_core_init(struct rtw89_dev *rtwdev); 5807 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 5808 int rtw89_core_register(struct rtw89_dev *rtwdev); 5809 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 5810 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5811 u32 bus_data_size, 5812 const struct rtw89_chip_info *chip); 5813 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 5814 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 5815 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 5816 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 5817 struct rtw89_chan *chan); 5818 void rtw89_set_channel(struct rtw89_dev *rtwdev); 5819 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5820 struct rtw89_chan *chan); 5821 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 5822 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 5823 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 5824 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 5825 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5826 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 5827 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5828 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 5829 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 5830 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 5831 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 5832 int rtw89_regd_init(struct rtw89_dev *rtwdev, 5833 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 5834 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 5835 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 5836 struct rtw89_traffic_stats *stats); 5837 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 5838 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5839 const struct rtw89_completion_data *data); 5840 int rtw89_core_start(struct rtw89_dev *rtwdev); 5841 void rtw89_core_stop(struct rtw89_dev *rtwdev); 5842 void rtw89_core_update_beacon_work(struct work_struct *work); 5843 void rtw89_roc_work(struct work_struct *work); 5844 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5845 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5846 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5847 const u8 *mac_addr, bool hw_scan); 5848 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5849 struct ieee80211_vif *vif, bool hw_scan); 5850 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 5851 struct rtw89_vif *rtwvif, bool active); 5852 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 5853 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 5854 5855 #endif 5856