1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 struct rtw89_mac_gen_def; 18 struct rtw89_phy_gen_def; 19 struct rtw89_efuse_block_cfg; 20 struct rtw89_h2c_rf_tssi; 21 struct rtw89_fw_txpwr_track_cfg; 22 struct rtw89_phy_rfk_log_fmt; 23 24 extern const struct ieee80211_ops rtw89_ops; 25 26 #define MASKBYTE0 0xff 27 #define MASKBYTE1 0xff00 28 #define MASKBYTE2 0xff0000 29 #define MASKBYTE3 0xff000000 30 #define MASKBYTE4 0xff00000000ULL 31 #define MASKHWORD 0xffff0000 32 #define MASKLWORD 0x0000ffff 33 #define MASKDWORD 0xffffffff 34 #define RFREG_MASK 0xfffff 35 #define INV_RF_DATA 0xffffffff 36 #define BYPASS_CR_DATA 0xbabecafe 37 38 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 39 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 40 #define CFO_TRACK_MAX_USER 64 41 #define MAX_RSSI 110 42 #define RSSI_FACTOR 1 43 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 44 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 45 #define DELTA_SWINGIDX_SIZE 30 46 47 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 48 #define RTW89_RADIOTAP_ROOM_EHT \ 49 (sizeof(struct ieee80211_radiotap_tlv) + \ 50 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 51 sizeof(struct ieee80211_radiotap_tlv) + \ 52 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 53 #define RTW89_RADIOTAP_ROOM \ 54 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 55 56 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 57 #define RTW89_HTC_VARIANT_HE 3 58 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 59 #define RTW89_HTC_VARIANT_HE_CID_OM 1 60 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 61 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 62 63 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 64 enum htc_om_channel_width { 65 HTC_OM_CHANNEL_WIDTH_20 = 0, 66 HTC_OM_CHANNEL_WIDTH_40 = 1, 67 HTC_OM_CHANNEL_WIDTH_80 = 2, 68 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 69 }; 70 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 71 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 72 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 73 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 74 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 75 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 76 77 #define RTW89_TF_PAD GENMASK(11, 0) 78 #define RTW89_TF_BASIC_USER_INFO_SZ 6 79 80 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 81 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 82 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 83 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 84 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 86 87 enum rtw89_subband { 88 RTW89_CH_2G = 0, 89 RTW89_CH_5G_BAND_1 = 1, 90 /* RTW89_CH_5G_BAND_2 = 2, unused */ 91 RTW89_CH_5G_BAND_3 = 3, 92 RTW89_CH_5G_BAND_4 = 4, 93 94 RTW89_CH_6G_BAND_IDX0, /* Low */ 95 RTW89_CH_6G_BAND_IDX1, /* Low */ 96 RTW89_CH_6G_BAND_IDX2, /* Mid */ 97 RTW89_CH_6G_BAND_IDX3, /* Mid */ 98 RTW89_CH_6G_BAND_IDX4, /* High */ 99 RTW89_CH_6G_BAND_IDX5, /* High */ 100 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 101 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 102 103 RTW89_SUBBAND_NR, 104 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 105 }; 106 107 enum rtw89_gain_offset { 108 RTW89_GAIN_OFFSET_2G_CCK, 109 RTW89_GAIN_OFFSET_2G_OFDM, 110 RTW89_GAIN_OFFSET_5G_LOW, 111 RTW89_GAIN_OFFSET_5G_MID, 112 RTW89_GAIN_OFFSET_5G_HIGH, 113 RTW89_GAIN_OFFSET_6G_L0, 114 RTW89_GAIN_OFFSET_6G_L1, 115 RTW89_GAIN_OFFSET_6G_M0, 116 RTW89_GAIN_OFFSET_6G_M1, 117 RTW89_GAIN_OFFSET_6G_H0, 118 RTW89_GAIN_OFFSET_6G_H1, 119 RTW89_GAIN_OFFSET_6G_UH0, 120 RTW89_GAIN_OFFSET_6G_UH1, 121 122 RTW89_GAIN_OFFSET_NR, 123 }; 124 125 enum rtw89_hci_type { 126 RTW89_HCI_TYPE_PCIE, 127 RTW89_HCI_TYPE_USB, 128 RTW89_HCI_TYPE_SDIO, 129 }; 130 131 enum rtw89_core_chip_id { 132 RTL8852A, 133 RTL8852B, 134 RTL8852C, 135 RTL8851B, 136 RTL8922A, 137 }; 138 139 enum rtw89_chip_gen { 140 RTW89_CHIP_AX, 141 RTW89_CHIP_BE, 142 143 RTW89_CHIP_GEN_NUM, 144 }; 145 146 enum rtw89_cv { 147 CHIP_CAV, 148 CHIP_CBV, 149 CHIP_CCV, 150 CHIP_CDV, 151 CHIP_CEV, 152 CHIP_CFV, 153 CHIP_CV_MAX, 154 CHIP_CV_INVALID = CHIP_CV_MAX, 155 }; 156 157 enum rtw89_bacam_ver { 158 RTW89_BACAM_V0, 159 RTW89_BACAM_V1, 160 161 RTW89_BACAM_V0_EXT = 99, 162 }; 163 164 enum rtw89_core_tx_type { 165 RTW89_CORE_TX_TYPE_DATA, 166 RTW89_CORE_TX_TYPE_MGMT, 167 RTW89_CORE_TX_TYPE_FWCMD, 168 }; 169 170 enum rtw89_core_rx_type { 171 RTW89_CORE_RX_TYPE_WIFI = 0, 172 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 173 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 174 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 175 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 176 RTW89_CORE_RX_TYPE_SS2FW = 5, 177 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 178 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 179 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 180 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 181 RTW89_CORE_RX_TYPE_C2H = 10, 182 RTW89_CORE_RX_TYPE_CSI = 11, 183 RTW89_CORE_RX_TYPE_CQI = 12, 184 RTW89_CORE_RX_TYPE_H2C = 13, 185 RTW89_CORE_RX_TYPE_FWDL = 14, 186 }; 187 188 enum rtw89_txq_flags { 189 RTW89_TXQ_F_AMPDU = 0, 190 RTW89_TXQ_F_BLOCK_BA = 1, 191 RTW89_TXQ_F_FORBID_BA = 2, 192 }; 193 194 enum rtw89_net_type { 195 RTW89_NET_TYPE_NO_LINK = 0, 196 RTW89_NET_TYPE_AD_HOC = 1, 197 RTW89_NET_TYPE_INFRA = 2, 198 RTW89_NET_TYPE_AP_MODE = 3, 199 }; 200 201 enum rtw89_wifi_role { 202 RTW89_WIFI_ROLE_NONE, 203 RTW89_WIFI_ROLE_STATION, 204 RTW89_WIFI_ROLE_AP, 205 RTW89_WIFI_ROLE_AP_VLAN, 206 RTW89_WIFI_ROLE_ADHOC, 207 RTW89_WIFI_ROLE_ADHOC_MASTER, 208 RTW89_WIFI_ROLE_MESH_POINT, 209 RTW89_WIFI_ROLE_MONITOR, 210 RTW89_WIFI_ROLE_P2P_DEVICE, 211 RTW89_WIFI_ROLE_P2P_CLIENT, 212 RTW89_WIFI_ROLE_P2P_GO, 213 RTW89_WIFI_ROLE_NAN, 214 RTW89_WIFI_ROLE_MLME_MAX 215 }; 216 217 enum rtw89_upd_mode { 218 RTW89_ROLE_CREATE, 219 RTW89_ROLE_REMOVE, 220 RTW89_ROLE_TYPE_CHANGE, 221 RTW89_ROLE_INFO_CHANGE, 222 RTW89_ROLE_CON_DISCONN, 223 RTW89_ROLE_BAND_SW, 224 RTW89_ROLE_FW_RESTORE, 225 }; 226 227 enum rtw89_self_role { 228 RTW89_SELF_ROLE_CLIENT, 229 RTW89_SELF_ROLE_AP, 230 RTW89_SELF_ROLE_AP_CLIENT 231 }; 232 233 enum rtw89_msk_sO_el { 234 RTW89_NO_MSK, 235 RTW89_SMA, 236 RTW89_TMA, 237 RTW89_BSSID 238 }; 239 240 enum rtw89_sch_tx_sel { 241 RTW89_SCH_TX_SEL_ALL, 242 RTW89_SCH_TX_SEL_HIQ, 243 RTW89_SCH_TX_SEL_MG0, 244 RTW89_SCH_TX_SEL_MACID, 245 }; 246 247 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 248 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 249 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 250 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 251 */ 252 enum rtw89_add_cam_sec_mode { 253 RTW89_ADDR_CAM_SEC_NONE = 0, 254 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 255 RTW89_ADDR_CAM_SEC_NORMAL = 2, 256 RTW89_ADDR_CAM_SEC_4GROUP = 3, 257 }; 258 259 enum rtw89_sec_key_type { 260 RTW89_SEC_KEY_TYPE_NONE = 0, 261 RTW89_SEC_KEY_TYPE_WEP40 = 1, 262 RTW89_SEC_KEY_TYPE_WEP104 = 2, 263 RTW89_SEC_KEY_TYPE_TKIP = 3, 264 RTW89_SEC_KEY_TYPE_WAPI = 4, 265 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 266 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 267 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 268 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 269 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 270 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 271 }; 272 273 enum rtw89_port { 274 RTW89_PORT_0 = 0, 275 RTW89_PORT_1 = 1, 276 RTW89_PORT_2 = 2, 277 RTW89_PORT_3 = 3, 278 RTW89_PORT_4 = 4, 279 RTW89_PORT_NUM 280 }; 281 282 enum rtw89_band { 283 RTW89_BAND_2G = 0, 284 RTW89_BAND_5G = 1, 285 RTW89_BAND_6G = 2, 286 RTW89_BAND_NUM, 287 }; 288 289 enum rtw89_hw_rate { 290 RTW89_HW_RATE_CCK1 = 0x0, 291 RTW89_HW_RATE_CCK2 = 0x1, 292 RTW89_HW_RATE_CCK5_5 = 0x2, 293 RTW89_HW_RATE_CCK11 = 0x3, 294 RTW89_HW_RATE_OFDM6 = 0x4, 295 RTW89_HW_RATE_OFDM9 = 0x5, 296 RTW89_HW_RATE_OFDM12 = 0x6, 297 RTW89_HW_RATE_OFDM18 = 0x7, 298 RTW89_HW_RATE_OFDM24 = 0x8, 299 RTW89_HW_RATE_OFDM36 = 0x9, 300 RTW89_HW_RATE_OFDM48 = 0xA, 301 RTW89_HW_RATE_OFDM54 = 0xB, 302 RTW89_HW_RATE_MCS0 = 0x80, 303 RTW89_HW_RATE_MCS1 = 0x81, 304 RTW89_HW_RATE_MCS2 = 0x82, 305 RTW89_HW_RATE_MCS3 = 0x83, 306 RTW89_HW_RATE_MCS4 = 0x84, 307 RTW89_HW_RATE_MCS5 = 0x85, 308 RTW89_HW_RATE_MCS6 = 0x86, 309 RTW89_HW_RATE_MCS7 = 0x87, 310 RTW89_HW_RATE_MCS8 = 0x88, 311 RTW89_HW_RATE_MCS9 = 0x89, 312 RTW89_HW_RATE_MCS10 = 0x8A, 313 RTW89_HW_RATE_MCS11 = 0x8B, 314 RTW89_HW_RATE_MCS12 = 0x8C, 315 RTW89_HW_RATE_MCS13 = 0x8D, 316 RTW89_HW_RATE_MCS14 = 0x8E, 317 RTW89_HW_RATE_MCS15 = 0x8F, 318 RTW89_HW_RATE_MCS16 = 0x90, 319 RTW89_HW_RATE_MCS17 = 0x91, 320 RTW89_HW_RATE_MCS18 = 0x92, 321 RTW89_HW_RATE_MCS19 = 0x93, 322 RTW89_HW_RATE_MCS20 = 0x94, 323 RTW89_HW_RATE_MCS21 = 0x95, 324 RTW89_HW_RATE_MCS22 = 0x96, 325 RTW89_HW_RATE_MCS23 = 0x97, 326 RTW89_HW_RATE_MCS24 = 0x98, 327 RTW89_HW_RATE_MCS25 = 0x99, 328 RTW89_HW_RATE_MCS26 = 0x9A, 329 RTW89_HW_RATE_MCS27 = 0x9B, 330 RTW89_HW_RATE_MCS28 = 0x9C, 331 RTW89_HW_RATE_MCS29 = 0x9D, 332 RTW89_HW_RATE_MCS30 = 0x9E, 333 RTW89_HW_RATE_MCS31 = 0x9F, 334 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 335 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 336 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 337 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 338 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 339 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 340 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 341 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 342 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 343 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 344 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 345 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 346 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 347 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 348 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 349 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 350 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 351 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 352 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 353 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 354 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 355 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 356 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 357 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 358 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 359 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 360 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 361 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 362 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 363 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 364 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 365 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 366 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 367 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 368 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 369 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 370 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 371 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 372 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 373 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 374 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 375 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 376 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 377 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 378 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 379 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 380 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 381 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 382 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 383 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 384 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 385 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 386 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 387 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 388 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 389 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 390 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 391 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 392 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 393 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 394 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 395 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 396 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 397 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 398 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 399 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 400 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 401 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 402 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 403 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 404 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 405 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 406 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 407 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 408 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 409 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 410 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 411 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 412 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 413 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 414 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 415 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 416 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 417 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 418 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 419 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 420 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 421 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 422 423 RTW89_HW_RATE_V1_MCS0 = 0x100, 424 RTW89_HW_RATE_V1_MCS1 = 0x101, 425 RTW89_HW_RATE_V1_MCS2 = 0x102, 426 RTW89_HW_RATE_V1_MCS3 = 0x103, 427 RTW89_HW_RATE_V1_MCS4 = 0x104, 428 RTW89_HW_RATE_V1_MCS5 = 0x105, 429 RTW89_HW_RATE_V1_MCS6 = 0x106, 430 RTW89_HW_RATE_V1_MCS7 = 0x107, 431 RTW89_HW_RATE_V1_MCS8 = 0x108, 432 RTW89_HW_RATE_V1_MCS9 = 0x109, 433 RTW89_HW_RATE_V1_MCS10 = 0x10A, 434 RTW89_HW_RATE_V1_MCS11 = 0x10B, 435 RTW89_HW_RATE_V1_MCS12 = 0x10C, 436 RTW89_HW_RATE_V1_MCS13 = 0x10D, 437 RTW89_HW_RATE_V1_MCS14 = 0x10E, 438 RTW89_HW_RATE_V1_MCS15 = 0x10F, 439 RTW89_HW_RATE_V1_MCS16 = 0x110, 440 RTW89_HW_RATE_V1_MCS17 = 0x111, 441 RTW89_HW_RATE_V1_MCS18 = 0x112, 442 RTW89_HW_RATE_V1_MCS19 = 0x113, 443 RTW89_HW_RATE_V1_MCS20 = 0x114, 444 RTW89_HW_RATE_V1_MCS21 = 0x115, 445 RTW89_HW_RATE_V1_MCS22 = 0x116, 446 RTW89_HW_RATE_V1_MCS23 = 0x117, 447 RTW89_HW_RATE_V1_MCS24 = 0x118, 448 RTW89_HW_RATE_V1_MCS25 = 0x119, 449 RTW89_HW_RATE_V1_MCS26 = 0x11A, 450 RTW89_HW_RATE_V1_MCS27 = 0x11B, 451 RTW89_HW_RATE_V1_MCS28 = 0x11C, 452 RTW89_HW_RATE_V1_MCS29 = 0x11D, 453 RTW89_HW_RATE_V1_MCS30 = 0x11E, 454 RTW89_HW_RATE_V1_MCS31 = 0x11F, 455 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 456 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 467 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 468 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 479 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 480 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 491 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 492 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 503 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 504 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 515 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 516 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 527 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 528 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 539 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 540 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 551 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 552 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 567 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 568 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 581 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 582 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 595 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 596 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 609 610 RTW89_HW_RATE_NR, 611 RTW89_HW_RATE_INVAL, 612 613 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 614 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 615 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 616 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 617 }; 618 619 /* 2G channels, 620 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 621 */ 622 #define RTW89_2G_CH_NUM 14 623 624 /* 5G channels, 625 * 36, 38, 40, 42, 44, 46, 48, 50, 626 * 52, 54, 56, 58, 60, 62, 64, 627 * 100, 102, 104, 106, 108, 110, 112, 114, 628 * 116, 118, 120, 122, 124, 126, 128, 130, 629 * 132, 134, 136, 138, 140, 142, 144, 630 * 149, 151, 153, 155, 157, 159, 161, 163, 631 * 165, 167, 169, 171, 173, 175, 177 632 */ 633 #define RTW89_5G_CH_NUM 53 634 635 /* 6G channels, 636 * 1, 3, 5, 7, 9, 11, 13, 15, 637 * 17, 19, 21, 23, 25, 27, 29, 33, 638 * 35, 37, 39, 41, 43, 45, 47, 49, 639 * 51, 53, 55, 57, 59, 61, 65, 67, 640 * 69, 71, 73, 75, 77, 79, 81, 83, 641 * 85, 87, 89, 91, 93, 97, 99, 101, 642 * 103, 105, 107, 109, 111, 113, 115, 117, 643 * 119, 121, 123, 125, 129, 131, 133, 135, 644 * 137, 139, 141, 143, 145, 147, 149, 151, 645 * 153, 155, 157, 161, 163, 165, 167, 169, 646 * 171, 173, 175, 177, 179, 181, 183, 185, 647 * 187, 189, 193, 195, 197, 199, 201, 203, 648 * 205, 207, 209, 211, 213, 215, 217, 219, 649 * 221, 225, 227, 229, 231, 233, 235, 237, 650 * 239, 241, 243, 245, 247, 249, 251, 253, 651 */ 652 #define RTW89_6G_CH_NUM 120 653 654 enum rtw89_rate_section { 655 RTW89_RS_CCK, 656 RTW89_RS_OFDM, 657 RTW89_RS_MCS, /* for HT/VHT/HE */ 658 RTW89_RS_HEDCM, 659 RTW89_RS_OFFSET, 660 RTW89_RS_NUM, 661 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 662 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 663 }; 664 665 enum rtw89_rate_offset_indexes { 666 RTW89_RATE_OFFSET_HE, 667 RTW89_RATE_OFFSET_VHT, 668 RTW89_RATE_OFFSET_HT, 669 RTW89_RATE_OFFSET_OFDM, 670 RTW89_RATE_OFFSET_CCK, 671 RTW89_RATE_OFFSET_DLRU_EHT, 672 RTW89_RATE_OFFSET_DLRU_HE, 673 RTW89_RATE_OFFSET_EHT, 674 __RTW89_RATE_OFFSET_NUM, 675 676 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 677 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 678 }; 679 680 enum rtw89_rate_num { 681 RTW89_RATE_CCK_NUM = 4, 682 RTW89_RATE_OFDM_NUM = 8, 683 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 684 685 RTW89_RATE_MCS_NUM_AX = 12, 686 RTW89_RATE_MCS_NUM_BE = 16, 687 __RTW89_RATE_MCS_NUM = 16, 688 }; 689 690 enum rtw89_nss { 691 RTW89_NSS_1 = 0, 692 RTW89_NSS_2 = 1, 693 /* HE DCM only support 1ss and 2ss */ 694 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 695 RTW89_NSS_3 = 2, 696 RTW89_NSS_4 = 3, 697 RTW89_NSS_NUM, 698 }; 699 700 enum rtw89_ntx { 701 RTW89_1TX = 0, 702 RTW89_2TX = 1, 703 RTW89_NTX_NUM, 704 }; 705 706 enum rtw89_beamforming_type { 707 RTW89_NONBF = 0, 708 RTW89_BF = 1, 709 RTW89_BF_NUM, 710 }; 711 712 enum rtw89_ofdma_type { 713 RTW89_NON_OFDMA = 0, 714 RTW89_OFDMA = 1, 715 RTW89_OFDMA_NUM, 716 }; 717 718 enum rtw89_regulation_type { 719 RTW89_WW = 0, 720 RTW89_ETSI = 1, 721 RTW89_FCC = 2, 722 RTW89_MKK = 3, 723 RTW89_NA = 4, 724 RTW89_IC = 5, 725 RTW89_KCC = 6, 726 RTW89_ACMA = 7, 727 RTW89_NCC = 8, 728 RTW89_MEXICO = 9, 729 RTW89_CHILE = 10, 730 RTW89_UKRAINE = 11, 731 RTW89_CN = 12, 732 RTW89_QATAR = 13, 733 RTW89_UK = 14, 734 RTW89_THAILAND = 15, 735 RTW89_REGD_NUM, 736 }; 737 738 enum rtw89_reg_6ghz_power { 739 RTW89_REG_6GHZ_POWER_VLP = 0, 740 RTW89_REG_6GHZ_POWER_LPI = 1, 741 RTW89_REG_6GHZ_POWER_STD = 2, 742 743 NUM_OF_RTW89_REG_6GHZ_POWER, 744 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 745 }; 746 747 enum rtw89_fw_pkt_ofld_type { 748 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 749 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 750 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 751 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 752 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 753 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 754 RTW89_PKT_OFLD_TYPE_NDP = 6, 755 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 756 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 757 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 758 RTW89_PKT_OFLD_TYPE_NUM, 759 }; 760 761 struct rtw89_txpwr_byrate { 762 s8 cck[RTW89_RATE_CCK_NUM]; 763 s8 ofdm[RTW89_RATE_OFDM_NUM]; 764 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 765 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 766 s8 offset[__RTW89_RATE_OFFSET_NUM]; 767 s8 trap; 768 }; 769 770 struct rtw89_rate_desc { 771 enum rtw89_nss nss; 772 enum rtw89_rate_section rs; 773 enum rtw89_ofdma_type ofdma; 774 u8 idx; 775 }; 776 777 #define PHY_STS_HDR_LEN 8 778 #define RF_PATH_MAX 4 779 #define RTW89_MAX_PPDU_CNT 8 780 struct rtw89_rx_phy_ppdu { 781 void *buf; 782 u32 len; 783 u8 rssi_avg; 784 u8 rssi[RF_PATH_MAX]; 785 u8 mac_id; 786 u8 chan_idx; 787 u8 ie; 788 u16 rate; 789 struct { 790 bool has; 791 u8 avg_snr; 792 u8 evm_max; 793 u8 evm_min; 794 } ofdm; 795 bool to_self; 796 bool valid; 797 }; 798 799 enum rtw89_mac_idx { 800 RTW89_MAC_0 = 0, 801 RTW89_MAC_1 = 1, 802 }; 803 804 enum rtw89_phy_idx { 805 RTW89_PHY_0 = 0, 806 RTW89_PHY_1 = 1, 807 RTW89_PHY_MAX 808 }; 809 810 enum rtw89_sub_entity_idx { 811 RTW89_SUB_ENTITY_0 = 0, 812 RTW89_SUB_ENTITY_1 = 1, 813 814 NUM_OF_RTW89_SUB_ENTITY, 815 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 816 }; 817 818 enum rtw89_rf_path { 819 RF_PATH_A = 0, 820 RF_PATH_B = 1, 821 RF_PATH_C = 2, 822 RF_PATH_D = 3, 823 RF_PATH_AB, 824 RF_PATH_AC, 825 RF_PATH_AD, 826 RF_PATH_BC, 827 RF_PATH_BD, 828 RF_PATH_CD, 829 RF_PATH_ABC, 830 RF_PATH_ABD, 831 RF_PATH_ACD, 832 RF_PATH_BCD, 833 RF_PATH_ABCD, 834 }; 835 836 enum rtw89_rf_path_bit { 837 RF_A = BIT(0), 838 RF_B = BIT(1), 839 RF_C = BIT(2), 840 RF_D = BIT(3), 841 842 RF_AB = (RF_A | RF_B), 843 RF_AC = (RF_A | RF_C), 844 RF_AD = (RF_A | RF_D), 845 RF_BC = (RF_B | RF_C), 846 RF_BD = (RF_B | RF_D), 847 RF_CD = (RF_C | RF_D), 848 849 RF_ABC = (RF_A | RF_B | RF_C), 850 RF_ABD = (RF_A | RF_B | RF_D), 851 RF_ACD = (RF_A | RF_C | RF_D), 852 RF_BCD = (RF_B | RF_C | RF_D), 853 854 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 855 }; 856 857 enum rtw89_bandwidth { 858 RTW89_CHANNEL_WIDTH_20 = 0, 859 RTW89_CHANNEL_WIDTH_40 = 1, 860 RTW89_CHANNEL_WIDTH_80 = 2, 861 RTW89_CHANNEL_WIDTH_160 = 3, 862 RTW89_CHANNEL_WIDTH_320 = 4, 863 864 /* keep index order above */ 865 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 866 867 RTW89_CHANNEL_WIDTH_80_80 = 5, 868 RTW89_CHANNEL_WIDTH_5 = 6, 869 RTW89_CHANNEL_WIDTH_10 = 7, 870 }; 871 872 enum rtw89_ps_mode { 873 RTW89_PS_MODE_NONE = 0, 874 RTW89_PS_MODE_RFOFF = 1, 875 RTW89_PS_MODE_CLK_GATED = 2, 876 RTW89_PS_MODE_PWR_GATED = 3, 877 }; 878 879 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 880 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 881 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 882 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 883 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 884 885 enum rtw89_ru_bandwidth { 886 RTW89_RU26 = 0, 887 RTW89_RU52 = 1, 888 RTW89_RU106 = 2, 889 RTW89_RU52_26 = 3, 890 RTW89_RU106_26 = 4, 891 RTW89_RU_NUM, 892 }; 893 894 enum rtw89_sc_offset { 895 RTW89_SC_DONT_CARE = 0, 896 RTW89_SC_20_UPPER = 1, 897 RTW89_SC_20_LOWER = 2, 898 RTW89_SC_20_UPMOST = 3, 899 RTW89_SC_20_LOWEST = 4, 900 RTW89_SC_20_UP2X = 5, 901 RTW89_SC_20_LOW2X = 6, 902 RTW89_SC_20_UP3X = 7, 903 RTW89_SC_20_LOW3X = 8, 904 RTW89_SC_40_UPPER = 9, 905 RTW89_SC_40_LOWER = 10, 906 }; 907 908 enum rtw89_wow_flags { 909 RTW89_WOW_FLAG_EN_MAGIC_PKT, 910 RTW89_WOW_FLAG_EN_REKEY_PKT, 911 RTW89_WOW_FLAG_EN_DISCONNECT, 912 RTW89_WOW_FLAG_NUM, 913 }; 914 915 struct rtw89_chan { 916 u8 channel; 917 u8 primary_channel; 918 enum rtw89_band band_type; 919 enum rtw89_bandwidth band_width; 920 921 /* The follow-up are derived from the above. We must ensure that it 922 * is assigned correctly in rtw89_chan_create() if new one is added. 923 */ 924 u32 freq; 925 enum rtw89_subband subband_type; 926 enum rtw89_sc_offset pri_ch_idx; 927 u8 pri_sb_idx; 928 }; 929 930 struct rtw89_chan_rcd { 931 u8 prev_primary_channel; 932 enum rtw89_band prev_band_type; 933 bool band_changed; 934 }; 935 936 struct rtw89_channel_help_params { 937 u32 tx_en; 938 }; 939 940 struct rtw89_port_reg { 941 u32 port_cfg; 942 u32 tbtt_prohib; 943 u32 bcn_area; 944 u32 bcn_early; 945 u32 tbtt_early; 946 u32 tbtt_agg; 947 u32 bcn_space; 948 u32 bcn_forcetx; 949 u32 bcn_err_cnt; 950 u32 bcn_err_flag; 951 u32 dtim_ctrl; 952 u32 tbtt_shift; 953 u32 bcn_cnt_tmr; 954 u32 tsftr_l; 955 u32 tsftr_h; 956 u32 md_tsft; 957 u32 bss_color; 958 u32 mbssid; 959 u32 mbssid_drop; 960 u32 tsf_sync; 961 u32 ptcl_dbg; 962 u32 ptcl_dbg_info; 963 u32 bcn_drop_all; 964 u32 hiq_win[RTW89_PORT_NUM]; 965 }; 966 967 struct rtw89_txwd_body { 968 __le32 dword0; 969 __le32 dword1; 970 __le32 dword2; 971 __le32 dword3; 972 __le32 dword4; 973 __le32 dword5; 974 } __packed; 975 976 struct rtw89_txwd_body_v1 { 977 __le32 dword0; 978 __le32 dword1; 979 __le32 dword2; 980 __le32 dword3; 981 __le32 dword4; 982 __le32 dword5; 983 __le32 dword6; 984 __le32 dword7; 985 } __packed; 986 987 struct rtw89_txwd_body_v2 { 988 __le32 dword0; 989 __le32 dword1; 990 __le32 dword2; 991 __le32 dword3; 992 __le32 dword4; 993 __le32 dword5; 994 __le32 dword6; 995 __le32 dword7; 996 } __packed; 997 998 struct rtw89_txwd_info { 999 __le32 dword0; 1000 __le32 dword1; 1001 __le32 dword2; 1002 __le32 dword3; 1003 __le32 dword4; 1004 __le32 dword5; 1005 } __packed; 1006 1007 struct rtw89_txwd_info_v2 { 1008 __le32 dword0; 1009 __le32 dword1; 1010 __le32 dword2; 1011 __le32 dword3; 1012 __le32 dword4; 1013 __le32 dword5; 1014 __le32 dword6; 1015 __le32 dword7; 1016 } __packed; 1017 1018 struct rtw89_rx_desc_info { 1019 u16 pkt_size; 1020 u8 pkt_type; 1021 u8 drv_info_size; 1022 u8 phy_rpt_size; 1023 u8 hdr_cnv_size; 1024 u8 shift; 1025 u8 wl_hd_iv_len; 1026 bool long_rxdesc; 1027 bool bb_sel; 1028 bool mac_info_valid; 1029 u16 data_rate; 1030 u8 gi_ltf; 1031 u8 bw; 1032 u32 free_run_cnt; 1033 u8 user_id; 1034 bool sr_en; 1035 u8 ppdu_cnt; 1036 u8 ppdu_type; 1037 bool icv_err; 1038 bool crc32_err; 1039 bool hw_dec; 1040 bool sw_dec; 1041 bool addr1_match; 1042 u8 frag; 1043 u16 seq; 1044 u8 frame_type; 1045 u8 rx_pl_id; 1046 bool addr_cam_valid; 1047 u8 addr_cam_id; 1048 u8 sec_cam_id; 1049 u8 mac_id; 1050 u16 offset; 1051 u16 rxd_len; 1052 bool ready; 1053 }; 1054 1055 struct rtw89_rxdesc_short { 1056 __le32 dword0; 1057 __le32 dword1; 1058 __le32 dword2; 1059 __le32 dword3; 1060 } __packed; 1061 1062 struct rtw89_rxdesc_short_v2 { 1063 __le32 dword0; 1064 __le32 dword1; 1065 __le32 dword2; 1066 __le32 dword3; 1067 __le32 dword4; 1068 __le32 dword5; 1069 } __packed; 1070 1071 struct rtw89_rxdesc_long { 1072 __le32 dword0; 1073 __le32 dword1; 1074 __le32 dword2; 1075 __le32 dword3; 1076 __le32 dword4; 1077 __le32 dword5; 1078 __le32 dword6; 1079 __le32 dword7; 1080 } __packed; 1081 1082 struct rtw89_rxdesc_long_v2 { 1083 __le32 dword0; 1084 __le32 dword1; 1085 __le32 dword2; 1086 __le32 dword3; 1087 __le32 dword4; 1088 __le32 dword5; 1089 __le32 dword6; 1090 __le32 dword7; 1091 __le32 dword8; 1092 __le32 dword9; 1093 } __packed; 1094 1095 struct rtw89_tx_desc_info { 1096 u16 pkt_size; 1097 u8 wp_offset; 1098 u8 mac_id; 1099 u8 qsel; 1100 u8 ch_dma; 1101 u8 hdr_llc_len; 1102 bool is_bmc; 1103 bool en_wd_info; 1104 bool wd_page; 1105 bool use_rate; 1106 bool dis_data_fb; 1107 bool tid_indicate; 1108 bool agg_en; 1109 bool bk; 1110 u8 ampdu_density; 1111 u8 ampdu_num; 1112 bool sec_en; 1113 u8 addr_info_nr; 1114 u8 sec_keyid; 1115 u8 sec_type; 1116 u8 sec_cam_idx; 1117 u8 sec_seq[6]; 1118 u16 data_rate; 1119 u16 data_retry_lowest_rate; 1120 bool fw_dl; 1121 u16 seq; 1122 bool a_ctrl_bsr; 1123 u8 hw_ssn_sel; 1124 #define RTW89_MGMT_HW_SSN_SEL 1 1125 u8 hw_seq_mode; 1126 #define RTW89_MGMT_HW_SEQ_MODE 1 1127 bool hiq; 1128 u8 port; 1129 bool er_cap; 1130 }; 1131 1132 struct rtw89_core_tx_request { 1133 enum rtw89_core_tx_type tx_type; 1134 1135 struct sk_buff *skb; 1136 struct ieee80211_vif *vif; 1137 struct ieee80211_sta *sta; 1138 struct rtw89_tx_desc_info desc_info; 1139 }; 1140 1141 struct rtw89_txq { 1142 struct list_head list; 1143 unsigned long flags; 1144 int wait_cnt; 1145 }; 1146 1147 struct rtw89_mac_ax_gnt { 1148 u8 gnt_bt_sw_en; 1149 u8 gnt_bt; 1150 u8 gnt_wl_sw_en; 1151 u8 gnt_wl; 1152 } __packed; 1153 1154 #define RTW89_MAC_AX_COEX_GNT_NR 2 1155 struct rtw89_mac_ax_coex_gnt { 1156 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1157 }; 1158 1159 enum rtw89_btc_ncnt { 1160 BTC_NCNT_POWER_ON = 0x0, 1161 BTC_NCNT_POWER_OFF, 1162 BTC_NCNT_INIT_COEX, 1163 BTC_NCNT_SCAN_START, 1164 BTC_NCNT_SCAN_FINISH, 1165 BTC_NCNT_SPECIAL_PACKET, 1166 BTC_NCNT_SWITCH_BAND, 1167 BTC_NCNT_RFK_TIMEOUT, 1168 BTC_NCNT_SHOW_COEX_INFO, 1169 BTC_NCNT_ROLE_INFO, 1170 BTC_NCNT_CONTROL, 1171 BTC_NCNT_RADIO_STATE, 1172 BTC_NCNT_CUSTOMERIZE, 1173 BTC_NCNT_WL_RFK, 1174 BTC_NCNT_WL_STA, 1175 BTC_NCNT_FWINFO, 1176 BTC_NCNT_TIMER, 1177 BTC_NCNT_NUM 1178 }; 1179 1180 enum rtw89_btc_btinfo { 1181 BTC_BTINFO_L0 = 0, 1182 BTC_BTINFO_L1, 1183 BTC_BTINFO_L2, 1184 BTC_BTINFO_L3, 1185 BTC_BTINFO_H0, 1186 BTC_BTINFO_H1, 1187 BTC_BTINFO_H2, 1188 BTC_BTINFO_H3, 1189 BTC_BTINFO_MAX 1190 }; 1191 1192 enum rtw89_btc_dcnt { 1193 BTC_DCNT_RUN = 0x0, 1194 BTC_DCNT_CX_RUNINFO, 1195 BTC_DCNT_RPT, 1196 BTC_DCNT_RPT_HANG, 1197 BTC_DCNT_CYCLE, 1198 BTC_DCNT_CYCLE_HANG, 1199 BTC_DCNT_W1, 1200 BTC_DCNT_W1_HANG, 1201 BTC_DCNT_B1, 1202 BTC_DCNT_B1_HANG, 1203 BTC_DCNT_TDMA_NONSYNC, 1204 BTC_DCNT_SLOT_NONSYNC, 1205 BTC_DCNT_BTCNT_HANG, 1206 BTC_DCNT_WL_SLOT_DRIFT, 1207 BTC_DCNT_WL_STA_LAST, 1208 BTC_DCNT_BT_SLOT_DRIFT, 1209 BTC_DCNT_BT_SLOT_FLOOD, 1210 BTC_DCNT_FDDT_TRIG, 1211 BTC_DCNT_E2G, 1212 BTC_DCNT_E2G_HANG, 1213 BTC_DCNT_NUM 1214 }; 1215 1216 enum rtw89_btc_wl_state_cnt { 1217 BTC_WCNT_SCANAP = 0x0, 1218 BTC_WCNT_DHCP, 1219 BTC_WCNT_EAPOL, 1220 BTC_WCNT_ARP, 1221 BTC_WCNT_SCBDUPDATE, 1222 BTC_WCNT_RFK_REQ, 1223 BTC_WCNT_RFK_GO, 1224 BTC_WCNT_RFK_REJECT, 1225 BTC_WCNT_RFK_TIMEOUT, 1226 BTC_WCNT_CH_UPDATE, 1227 BTC_WCNT_NUM 1228 }; 1229 1230 enum rtw89_btc_bt_state_cnt { 1231 BTC_BCNT_RETRY = 0x0, 1232 BTC_BCNT_REINIT, 1233 BTC_BCNT_REENABLE, 1234 BTC_BCNT_SCBDREAD, 1235 BTC_BCNT_RELINK, 1236 BTC_BCNT_IGNOWL, 1237 BTC_BCNT_INQPAG, 1238 BTC_BCNT_INQ, 1239 BTC_BCNT_PAGE, 1240 BTC_BCNT_ROLESW, 1241 BTC_BCNT_AFH, 1242 BTC_BCNT_INFOUPDATE, 1243 BTC_BCNT_INFOSAME, 1244 BTC_BCNT_SCBDUPDATE, 1245 BTC_BCNT_HIPRI_TX, 1246 BTC_BCNT_HIPRI_RX, 1247 BTC_BCNT_LOPRI_TX, 1248 BTC_BCNT_LOPRI_RX, 1249 BTC_BCNT_POLUT, 1250 BTC_BCNT_RATECHG, 1251 BTC_BCNT_NUM 1252 }; 1253 1254 enum rtw89_btc_bt_profile { 1255 BTC_BT_NOPROFILE = 0, 1256 BTC_BT_HFP = BIT(0), 1257 BTC_BT_HID = BIT(1), 1258 BTC_BT_A2DP = BIT(2), 1259 BTC_BT_PAN = BIT(3), 1260 BTC_PROFILE_MAX = 4, 1261 }; 1262 1263 struct rtw89_btc_ant_info { 1264 u8 type; /* shared, dedicated */ 1265 u8 num; 1266 u8 isolation; 1267 1268 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1269 u8 diversity: 1; 1270 u8 btg_pos: 2; 1271 u8 stream_cnt: 4; 1272 }; 1273 1274 enum rtw89_tfc_dir { 1275 RTW89_TFC_UL, 1276 RTW89_TFC_DL, 1277 }; 1278 1279 struct rtw89_btc_wl_smap { 1280 u32 busy: 1; 1281 u32 scan: 1; 1282 u32 connecting: 1; 1283 u32 roaming: 1; 1284 u32 _4way: 1; 1285 u32 rf_off: 1; 1286 u32 lps: 2; 1287 u32 ips: 1; 1288 u32 init_ok: 1; 1289 u32 traffic_dir : 2; 1290 u32 rf_off_pre: 1; 1291 u32 lps_pre: 2; 1292 }; 1293 1294 enum rtw89_tfc_lv { 1295 RTW89_TFC_IDLE, 1296 RTW89_TFC_ULTRA_LOW, 1297 RTW89_TFC_LOW, 1298 RTW89_TFC_MID, 1299 RTW89_TFC_HIGH, 1300 }; 1301 1302 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1303 DECLARE_EWMA(tp, 10, 2); 1304 1305 struct rtw89_traffic_stats { 1306 /* units in bytes */ 1307 u64 tx_unicast; 1308 u64 rx_unicast; 1309 u32 tx_avg_len; 1310 u32 rx_avg_len; 1311 1312 /* count for packets */ 1313 u64 tx_cnt; 1314 u64 rx_cnt; 1315 1316 /* units in Mbps */ 1317 u32 tx_throughput; 1318 u32 rx_throughput; 1319 u32 tx_throughput_raw; 1320 u32 rx_throughput_raw; 1321 1322 u32 rx_tf_acc; 1323 u32 rx_tf_periodic; 1324 1325 enum rtw89_tfc_lv tx_tfc_lv; 1326 enum rtw89_tfc_lv rx_tfc_lv; 1327 struct ewma_tp tx_ewma_tp; 1328 struct ewma_tp rx_ewma_tp; 1329 1330 u16 tx_rate; 1331 u16 rx_rate; 1332 }; 1333 1334 struct rtw89_btc_statistic { 1335 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1336 struct rtw89_traffic_stats traffic; 1337 }; 1338 1339 #define BTC_WL_RSSI_THMAX 4 1340 1341 struct rtw89_btc_wl_link_info { 1342 struct rtw89_btc_statistic stat; 1343 enum rtw89_tfc_dir dir; 1344 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1345 u8 mac_addr[ETH_ALEN]; 1346 u8 busy; 1347 u8 ch; 1348 u8 bw; 1349 u8 band; 1350 u8 role; 1351 u8 pid; 1352 u8 phy; 1353 u8 dtim_period; 1354 u8 mode; 1355 1356 u8 mac_id; 1357 u8 tx_retry; 1358 1359 u32 bcn_period; 1360 u32 busy_t; 1361 u32 tx_time; 1362 u32 client_cnt; 1363 u32 rx_rate_drop_cnt; 1364 1365 u32 active: 1; 1366 u32 noa: 1; 1367 u32 client_ps: 1; 1368 u32 connected: 2; 1369 }; 1370 1371 union rtw89_btc_wl_state_map { 1372 u32 val; 1373 struct rtw89_btc_wl_smap map; 1374 }; 1375 1376 struct rtw89_btc_bt_hfp_desc { 1377 u32 exist: 1; 1378 u32 type: 2; 1379 u32 rsvd: 29; 1380 }; 1381 1382 struct rtw89_btc_bt_hid_desc { 1383 u32 exist: 1; 1384 u32 slot_info: 2; 1385 u32 pair_cnt: 2; 1386 u32 type: 8; 1387 u32 rsvd: 19; 1388 }; 1389 1390 struct rtw89_btc_bt_a2dp_desc { 1391 u8 exist: 1; 1392 u8 exist_last: 1; 1393 u8 play_latency: 1; 1394 u8 type: 3; 1395 u8 active: 1; 1396 u8 sink: 1; 1397 1398 u8 bitpool; 1399 u16 vendor_id; 1400 u32 device_name; 1401 u32 flush_time; 1402 }; 1403 1404 struct rtw89_btc_bt_pan_desc { 1405 u32 exist: 1; 1406 u32 type: 1; 1407 u32 active: 1; 1408 u32 rsvd: 29; 1409 }; 1410 1411 struct rtw89_btc_bt_rfk_info { 1412 u32 run: 1; 1413 u32 req: 1; 1414 u32 timeout: 1; 1415 u32 rsvd: 29; 1416 }; 1417 1418 union rtw89_btc_bt_rfk_info_map { 1419 u32 val; 1420 struct rtw89_btc_bt_rfk_info map; 1421 }; 1422 1423 struct rtw89_btc_bt_ver_info { 1424 u32 fw_coex; /* match with which coex_ver */ 1425 u32 fw; 1426 }; 1427 1428 struct rtw89_btc_bool_sta_chg { 1429 u32 now: 1; 1430 u32 last: 1; 1431 u32 remain: 1; 1432 u32 srvd: 29; 1433 }; 1434 1435 struct rtw89_btc_u8_sta_chg { 1436 u8 now; 1437 u8 last; 1438 u8 remain; 1439 u8 rsvd; 1440 }; 1441 1442 struct rtw89_btc_wl_scan_info { 1443 u8 band[RTW89_PHY_MAX]; 1444 u8 phy_map; 1445 u8 rsvd; 1446 }; 1447 1448 struct rtw89_btc_wl_dbcc_info { 1449 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1450 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1451 u8 real_band[RTW89_PHY_MAX]; 1452 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1453 }; 1454 1455 struct rtw89_btc_wl_active_role { 1456 u8 connected: 1; 1457 u8 pid: 3; 1458 u8 phy: 1; 1459 u8 noa: 1; 1460 u8 band: 2; 1461 1462 u8 client_ps: 1; 1463 u8 bw: 7; 1464 1465 u8 role; 1466 u8 ch; 1467 1468 u16 tx_lvl; 1469 u16 rx_lvl; 1470 u16 tx_rate; 1471 u16 rx_rate; 1472 }; 1473 1474 struct rtw89_btc_wl_active_role_v1 { 1475 u8 connected: 1; 1476 u8 pid: 3; 1477 u8 phy: 1; 1478 u8 noa: 1; 1479 u8 band: 2; 1480 1481 u8 client_ps: 1; 1482 u8 bw: 7; 1483 1484 u8 role; 1485 u8 ch; 1486 1487 u16 tx_lvl; 1488 u16 rx_lvl; 1489 u16 tx_rate; 1490 u16 rx_rate; 1491 1492 u32 noa_duration; /* ms */ 1493 }; 1494 1495 struct rtw89_btc_wl_active_role_v2 { 1496 u8 connected: 1; 1497 u8 pid: 3; 1498 u8 phy: 1; 1499 u8 noa: 1; 1500 u8 band: 2; 1501 1502 u8 client_ps: 1; 1503 u8 bw: 7; 1504 1505 u8 role; 1506 u8 ch; 1507 1508 u32 noa_duration; /* ms */ 1509 }; 1510 1511 struct rtw89_btc_wl_role_info_bpos { 1512 u16 none: 1; 1513 u16 station: 1; 1514 u16 ap: 1; 1515 u16 vap: 1; 1516 u16 adhoc: 1; 1517 u16 adhoc_master: 1; 1518 u16 mesh: 1; 1519 u16 moniter: 1; 1520 u16 p2p_device: 1; 1521 u16 p2p_gc: 1; 1522 u16 p2p_go: 1; 1523 u16 nan: 1; 1524 }; 1525 1526 struct rtw89_btc_wl_scc_ctrl { 1527 u8 null_role1; 1528 u8 null_role2; 1529 u8 ebt_null; /* if tx null at EBT slot */ 1530 }; 1531 1532 union rtw89_btc_wl_role_info_map { 1533 u16 val; 1534 struct rtw89_btc_wl_role_info_bpos role; 1535 }; 1536 1537 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1538 u8 connect_cnt; 1539 u8 link_mode; 1540 union rtw89_btc_wl_role_info_map role_map; 1541 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1542 }; 1543 1544 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1545 u8 connect_cnt; 1546 u8 link_mode; 1547 union rtw89_btc_wl_role_info_map role_map; 1548 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1549 u32 mrole_type; /* btc_wl_mrole_type */ 1550 u32 mrole_noa_duration; /* ms */ 1551 1552 u32 dbcc_en: 1; 1553 u32 dbcc_chg: 1; 1554 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1555 u32 link_mode_chg: 1; 1556 u32 rsvd: 27; 1557 }; 1558 1559 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1560 u8 connect_cnt; 1561 u8 link_mode; 1562 union rtw89_btc_wl_role_info_map role_map; 1563 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1564 u32 mrole_type; /* btc_wl_mrole_type */ 1565 u32 mrole_noa_duration; /* ms */ 1566 1567 u32 dbcc_en: 1; 1568 u32 dbcc_chg: 1; 1569 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1570 u32 link_mode_chg: 1; 1571 u32 rsvd: 27; 1572 }; 1573 1574 struct rtw89_btc_wl_ver_info { 1575 u32 fw_coex; /* match with which coex_ver */ 1576 u32 fw; 1577 u32 mac; 1578 u32 bb; 1579 u32 rf; 1580 }; 1581 1582 struct rtw89_btc_wl_afh_info { 1583 u8 en; 1584 u8 ch; 1585 u8 bw; 1586 u8 rsvd; 1587 } __packed; 1588 1589 struct rtw89_btc_wl_rfk_info { 1590 u32 state: 2; 1591 u32 path_map: 4; 1592 u32 phy_map: 2; 1593 u32 band: 2; 1594 u32 type: 8; 1595 u32 rsvd: 14; 1596 }; 1597 1598 struct rtw89_btc_bt_smap { 1599 u32 connect: 1; 1600 u32 ble_connect: 1; 1601 u32 acl_busy: 1; 1602 u32 sco_busy: 1; 1603 u32 mesh_busy: 1; 1604 u32 inq_pag: 1; 1605 }; 1606 1607 union rtw89_btc_bt_state_map { 1608 u32 val; 1609 struct rtw89_btc_bt_smap map; 1610 }; 1611 1612 #define BTC_BT_RSSI_THMAX 4 1613 #define BTC_BT_AFH_GROUP 12 1614 #define BTC_BT_AFH_LE_GROUP 5 1615 1616 struct rtw89_btc_bt_link_info { 1617 struct rtw89_btc_u8_sta_chg profile_cnt; 1618 struct rtw89_btc_bool_sta_chg multi_link; 1619 struct rtw89_btc_bool_sta_chg relink; 1620 struct rtw89_btc_bt_hfp_desc hfp_desc; 1621 struct rtw89_btc_bt_hid_desc hid_desc; 1622 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1623 struct rtw89_btc_bt_pan_desc pan_desc; 1624 union rtw89_btc_bt_state_map status; 1625 1626 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1627 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1628 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1629 u8 afh_map[BTC_BT_AFH_GROUP]; 1630 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1631 1632 u32 role_sw: 1; 1633 u32 slave_role: 1; 1634 u32 afh_update: 1; 1635 u32 cqddr: 1; 1636 u32 rssi: 8; 1637 u32 tx_3m: 1; 1638 u32 rsvd: 19; 1639 }; 1640 1641 struct rtw89_btc_3rdcx_info { 1642 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1643 u8 hw_coex; 1644 u16 rsvd; 1645 }; 1646 1647 struct rtw89_btc_dm_emap { 1648 u32 init: 1; 1649 u32 pta_owner: 1; 1650 u32 wl_rfk_timeout: 1; 1651 u32 bt_rfk_timeout: 1; 1652 u32 wl_fw_hang: 1; 1653 u32 cycle_hang: 1; 1654 u32 w1_hang: 1; 1655 u32 b1_hang: 1; 1656 u32 tdma_no_sync: 1; 1657 u32 slot_no_sync: 1; 1658 u32 wl_slot_drift: 1; 1659 u32 bt_slot_drift: 1; 1660 u32 role_num_mismatch: 1; 1661 u32 null1_tx_late: 1; 1662 u32 bt_afh_conflict: 1; 1663 u32 bt_leafh_conflict: 1; 1664 u32 bt_slot_flood: 1; 1665 u32 wl_e2g_hang: 1; 1666 u32 wl_ver_mismatch: 1; 1667 u32 bt_ver_mismatch: 1; 1668 }; 1669 1670 union rtw89_btc_dm_error_map { 1671 u32 val; 1672 struct rtw89_btc_dm_emap map; 1673 }; 1674 1675 struct rtw89_btc_rf_para { 1676 u32 tx_pwr_freerun; 1677 u32 rx_gain_freerun; 1678 u32 tx_pwr_perpkt; 1679 u32 rx_gain_perpkt; 1680 }; 1681 1682 struct rtw89_btc_wl_nhm { 1683 u8 instant_wl_nhm_dbm; 1684 u8 instant_wl_nhm_per_mhz; 1685 u16 valid_record_times; 1686 s8 record_pwr[16]; 1687 u8 record_ratio[16]; 1688 s8 pwr; /* dbm_per_MHz */ 1689 u8 ratio; 1690 u8 current_status; 1691 u8 refresh; 1692 bool start_flag; 1693 s8 pwr_max; 1694 s8 pwr_min; 1695 }; 1696 1697 struct rtw89_btc_wl_info { 1698 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1699 struct rtw89_btc_wl_rfk_info rfk_info; 1700 struct rtw89_btc_wl_ver_info ver_info; 1701 struct rtw89_btc_wl_afh_info afh_info; 1702 struct rtw89_btc_wl_role_info role_info; 1703 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1704 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1705 struct rtw89_btc_wl_scan_info scan_info; 1706 struct rtw89_btc_wl_dbcc_info dbcc_info; 1707 struct rtw89_btc_rf_para rf_para; 1708 struct rtw89_btc_wl_nhm nhm; 1709 union rtw89_btc_wl_state_map status; 1710 1711 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1712 u8 rssi_level; 1713 u8 cn_report; 1714 u8 coex_mode; 1715 1716 bool scbd_change; 1717 u32 scbd; 1718 }; 1719 1720 struct rtw89_btc_module { 1721 struct rtw89_btc_ant_info ant; 1722 u8 rfe_type; 1723 u8 cv; 1724 1725 u8 bt_solo: 1; 1726 u8 bt_pos: 1; 1727 u8 switch_type: 1; 1728 u8 wa_type: 3; 1729 1730 u8 kt_ver_adie; 1731 }; 1732 1733 #define RTW89_BTC_DM_MAXSTEP 30 1734 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1735 1736 struct rtw89_btc_dm_step { 1737 u16 step[RTW89_BTC_DM_MAXSTEP]; 1738 u8 step_pos; 1739 bool step_ov; 1740 }; 1741 1742 struct rtw89_btc_init_info { 1743 struct rtw89_btc_module module; 1744 u8 wl_guard_ch; 1745 1746 u8 wl_only: 1; 1747 u8 wl_init_ok: 1; 1748 u8 dbcc_en: 1; 1749 u8 cx_other: 1; 1750 u8 bt_only: 1; 1751 1752 u16 rsvd; 1753 }; 1754 1755 struct rtw89_btc_wl_tx_limit_para { 1756 u16 enable; 1757 u32 tx_time; /* unit: us */ 1758 u16 tx_retry; 1759 }; 1760 1761 enum rtw89_btc_bt_scan_type { 1762 BTC_SCAN_INQ = 0, 1763 BTC_SCAN_PAGE, 1764 BTC_SCAN_BLE, 1765 BTC_SCAN_INIT, 1766 BTC_SCAN_TV, 1767 BTC_SCAN_ADV, 1768 BTC_SCAN_MAX1, 1769 }; 1770 1771 enum rtw89_btc_ble_scan_type { 1772 CXSCAN_BG = 0, 1773 CXSCAN_INIT, 1774 CXSCAN_LE, 1775 CXSCAN_MAX 1776 }; 1777 1778 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1779 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1780 1781 struct rtw89_btc_bt_scan_info_v1 { 1782 __le16 win; 1783 __le16 intvl; 1784 __le32 flags; 1785 } __packed; 1786 1787 struct rtw89_btc_bt_scan_info_v2 { 1788 __le16 win; 1789 __le16 intvl; 1790 } __packed; 1791 1792 struct rtw89_btc_fbtc_btscan_v1 { 1793 u8 fver; /* btc_ver::fcxbtscan */ 1794 u8 rsvd; 1795 __le16 rsvd2; 1796 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1797 } __packed; 1798 1799 struct rtw89_btc_fbtc_btscan_v2 { 1800 u8 fver; /* btc_ver::fcxbtscan */ 1801 u8 type; 1802 __le16 rsvd2; 1803 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1804 } __packed; 1805 1806 union rtw89_btc_fbtc_btscan { 1807 struct rtw89_btc_fbtc_btscan_v1 v1; 1808 struct rtw89_btc_fbtc_btscan_v2 v2; 1809 }; 1810 1811 struct rtw89_btc_bt_info { 1812 struct rtw89_btc_bt_link_info link_info; 1813 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1814 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1815 struct rtw89_btc_bt_ver_info ver_info; 1816 struct rtw89_btc_bool_sta_chg enable; 1817 struct rtw89_btc_bool_sta_chg inq_pag; 1818 struct rtw89_btc_rf_para rf_para; 1819 union rtw89_btc_bt_rfk_info_map rfk_info; 1820 1821 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1822 u8 rssi_level; 1823 1824 u32 scbd; 1825 u32 feature; 1826 1827 u32 mbx_avl: 1; 1828 u32 whql_test: 1; 1829 u32 igno_wl: 1; 1830 u32 reinit: 1; 1831 u32 ble_scan_en: 1; 1832 u32 btg_type: 1; 1833 u32 inq: 1; 1834 u32 pag: 1; 1835 u32 run_patch_code: 1; 1836 u32 hi_lna_rx: 1; 1837 u32 scan_rx_low_pri: 1; 1838 u32 scan_info_update: 1; 1839 u32 lna_constrain: 3; 1840 u32 rsvd: 17; 1841 }; 1842 1843 struct rtw89_btc_cx { 1844 struct rtw89_btc_wl_info wl; 1845 struct rtw89_btc_bt_info bt; 1846 struct rtw89_btc_3rdcx_info other; 1847 u32 state_map; 1848 u32 cnt_bt[BTC_BCNT_NUM]; 1849 u32 cnt_wl[BTC_WCNT_NUM]; 1850 }; 1851 1852 struct rtw89_btc_fbtc_tdma { 1853 u8 type; /* btc_ver::fcxtdma */ 1854 u8 rxflctrl; 1855 u8 txpause; 1856 u8 wtgle_n; 1857 u8 leak_n; 1858 u8 ext_ctrl; 1859 u8 rxflctrl_role; 1860 u8 option_ctrl; 1861 } __packed; 1862 1863 struct rtw89_btc_fbtc_tdma_v3 { 1864 u8 fver; /* btc_ver::fcxtdma */ 1865 u8 rsvd; 1866 __le16 rsvd1; 1867 struct rtw89_btc_fbtc_tdma tdma; 1868 } __packed; 1869 1870 union rtw89_btc_fbtc_tdma_le32 { 1871 struct rtw89_btc_fbtc_tdma v1; 1872 struct rtw89_btc_fbtc_tdma_v3 v3; 1873 }; 1874 1875 #define CXMREG_MAX 30 1876 #define CXMREG_MAX_V2 20 1877 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1878 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1879 1880 enum rtw89_btc_bt_sta_counter { 1881 BTC_BCNT_RFK_REQ = 0, 1882 BTC_BCNT_RFK_GO = 1, 1883 BTC_BCNT_RFK_REJECT = 2, 1884 BTC_BCNT_RFK_FAIL = 3, 1885 BTC_BCNT_RFK_TIMEOUT = 4, 1886 BTC_BCNT_HI_TX = 5, 1887 BTC_BCNT_HI_RX = 6, 1888 BTC_BCNT_LO_TX = 7, 1889 BTC_BCNT_LO_RX = 8, 1890 BTC_BCNT_POLLUTED = 9, 1891 BTC_BCNT_STA_MAX 1892 }; 1893 1894 enum rtw89_btc_bt_sta_counter_v105 { 1895 BTC_BCNT_RFK_REQ_V105 = 0, 1896 BTC_BCNT_HI_TX_V105 = 1, 1897 BTC_BCNT_HI_RX_V105 = 2, 1898 BTC_BCNT_LO_TX_V105 = 3, 1899 BTC_BCNT_LO_RX_V105 = 4, 1900 BTC_BCNT_POLLUTED_V105 = 5, 1901 BTC_BCNT_STA_MAX_V105 1902 }; 1903 1904 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1905 u16 fver; /* btc_ver::fcxbtcrpt */ 1906 u16 rpt_cnt; /* tmr counters */ 1907 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1908 u32 wl_fw_cx_offload; 1909 u32 wl_fw_ver; 1910 u32 rpt_enable; 1911 u32 rpt_para; /* ms */ 1912 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1913 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1914 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1915 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1916 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1917 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1918 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1919 u32 c2h_cnt; /* fw send c2h counter */ 1920 u32 h2c_cnt; /* fw recv h2c counter */ 1921 } __packed; 1922 1923 struct rtw89_btc_fbtc_rpt_ctrl_info { 1924 __le32 cnt; /* fw report counter */ 1925 __le32 en; /* report map */ 1926 __le32 para; /* not used */ 1927 1928 __le32 cnt_c2h; /* fw send c2h counter */ 1929 __le32 cnt_h2c; /* fw recv h2c counter */ 1930 __le32 len_c2h; /* The total length of the last C2H */ 1931 1932 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1933 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1934 } __packed; 1935 1936 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1937 __le32 cx_ver; /* match which driver's coex version */ 1938 __le32 fw_ver; 1939 __le32 en; /* report map */ 1940 1941 __le16 cnt; /* fw report counter */ 1942 __le16 cnt_c2h; /* fw send c2h counter */ 1943 __le16 cnt_h2c; /* fw recv h2c counter */ 1944 __le16 len_c2h; /* The total length of the last C2H */ 1945 1946 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1947 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1948 } __packed; 1949 1950 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1951 __le32 cx_ver; /* match which driver's coex version */ 1952 __le32 cx_offload; 1953 __le32 fw_ver; 1954 } __packed; 1955 1956 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1957 __le32 cnt_empty; /* a2dp empty count */ 1958 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1959 __le32 cnt_tx; 1960 __le32 cnt_ack; 1961 __le32 cnt_nack; 1962 } __packed; 1963 1964 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1965 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1966 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1967 __le32 cnt_recv; /* fw recv mailbox counter */ 1968 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1969 } __packed; 1970 1971 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1972 u8 fver; 1973 u8 rsvd; 1974 __le16 rsvd1; 1975 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1976 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1977 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1978 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1979 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1980 } __packed; 1981 1982 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1983 u8 fver; 1984 u8 rsvd; 1985 __le16 rsvd1; 1986 1987 u8 gnt_val[RTW89_PHY_MAX][4]; 1988 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1989 1990 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1991 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1992 } __packed; 1993 1994 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1995 u8 fver; 1996 u8 rsvd; 1997 __le16 rsvd1; 1998 1999 u8 gnt_val[RTW89_PHY_MAX][4]; 2000 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2001 2002 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2003 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2004 } __packed; 2005 2006 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2007 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2008 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2009 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2010 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2011 }; 2012 2013 enum rtw89_fbtc_ext_ctrl_type { 2014 CXECTL_OFF = 0x0, /* tdma off */ 2015 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2016 CXECTL_EXT = 0x2, 2017 CXECTL_MAX 2018 }; 2019 2020 union rtw89_btc_fbtc_rxflct { 2021 u8 val; 2022 u8 type: 3; 2023 u8 tgln_n: 5; 2024 }; 2025 2026 enum rtw89_btc_cxst_state { 2027 CXST_OFF = 0x0, 2028 CXST_B2W = 0x1, 2029 CXST_W1 = 0x2, 2030 CXST_W2 = 0x3, 2031 CXST_W2B = 0x4, 2032 CXST_B1 = 0x5, 2033 CXST_B2 = 0x6, 2034 CXST_B3 = 0x7, 2035 CXST_B4 = 0x8, 2036 CXST_LK = 0x9, 2037 CXST_BLK = 0xa, 2038 CXST_E2G = 0xb, 2039 CXST_E5G = 0xc, 2040 CXST_EBT = 0xd, 2041 CXST_ENULL = 0xe, 2042 CXST_WLK = 0xf, 2043 CXST_W1FDD = 0x10, 2044 CXST_B1FDD = 0x11, 2045 CXST_MAX = 0x12, 2046 }; 2047 2048 enum rtw89_btc_cxevnt { 2049 CXEVNT_TDMA_ENTRY = 0x0, 2050 CXEVNT_WL_TMR, 2051 CXEVNT_B1_TMR, 2052 CXEVNT_B2_TMR, 2053 CXEVNT_B3_TMR, 2054 CXEVNT_B4_TMR, 2055 CXEVNT_W2B_TMR, 2056 CXEVNT_B2W_TMR, 2057 CXEVNT_BCN_EARLY, 2058 CXEVNT_A2DP_EMPTY, 2059 CXEVNT_LK_END, 2060 CXEVNT_RX_ISR, 2061 CXEVNT_RX_FC0, 2062 CXEVNT_RX_FC1, 2063 CXEVNT_BT_RELINK, 2064 CXEVNT_BT_RETRY, 2065 CXEVNT_E2G, 2066 CXEVNT_E5G, 2067 CXEVNT_EBT, 2068 CXEVNT_ENULL, 2069 CXEVNT_DRV_WLK, 2070 CXEVNT_BCN_OK, 2071 CXEVNT_BT_CHANGE, 2072 CXEVNT_EBT_EXTEND, 2073 CXEVNT_E2G_NULL1, 2074 CXEVNT_B1FDD_TMR, 2075 CXEVNT_MAX 2076 }; 2077 2078 enum { 2079 CXBCN_ALL = 0x0, 2080 CXBCN_ALL_OK, 2081 CXBCN_BT_SLOT, 2082 CXBCN_BT_OK, 2083 CXBCN_MAX 2084 }; 2085 2086 enum btc_slot_type { 2087 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2088 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2089 CXSTYPE_NUM, 2090 }; 2091 2092 enum { /* TIME */ 2093 CXT_BT = 0x0, 2094 CXT_WL = 0x1, 2095 CXT_MAX 2096 }; 2097 2098 enum { /* TIME-A2DP */ 2099 CXT_FLCTRL_OFF = 0x0, 2100 CXT_FLCTRL_ON = 0x1, 2101 CXT_FLCTRL_MAX 2102 }; 2103 2104 enum { /* STEP TYPE */ 2105 CXSTEP_NONE = 0x0, 2106 CXSTEP_EVNT = 0x1, 2107 CXSTEP_SLOT = 0x2, 2108 CXSTEP_MAX, 2109 }; 2110 2111 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2112 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2113 RPT_BT_AFH_SEQ_LE = 0x20 2114 }; 2115 2116 #define BTC_DBG_MAX1 32 2117 struct rtw89_btc_fbtc_gpio_dbg { 2118 u8 fver; /* btc_ver::fcxgpiodbg */ 2119 u8 rsvd; 2120 u16 rsvd2; 2121 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2122 u32 pre_state; /* the debug signal is 1 or 0 */ 2123 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2124 } __packed; 2125 2126 struct rtw89_btc_fbtc_mreg_val_v1 { 2127 u8 fver; /* btc_ver::fcxmreg */ 2128 u8 reg_num; 2129 __le16 rsvd; 2130 __le32 mreg_val[CXMREG_MAX]; 2131 } __packed; 2132 2133 struct rtw89_btc_fbtc_mreg_val_v2 { 2134 u8 fver; /* btc_ver::fcxmreg */ 2135 u8 reg_num; 2136 __le16 rsvd; 2137 __le32 mreg_val[CXMREG_MAX_V2]; 2138 } __packed; 2139 2140 union rtw89_btc_fbtc_mreg_val { 2141 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2142 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2143 }; 2144 2145 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2146 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2147 .offset = cpu_to_le32(__offset), } 2148 2149 struct rtw89_btc_fbtc_mreg { 2150 __le16 type; 2151 __le16 bytes; 2152 __le32 offset; 2153 } __packed; 2154 2155 struct rtw89_btc_fbtc_slot { 2156 __le16 dur; 2157 __le32 cxtbl; 2158 __le16 cxtype; 2159 } __packed; 2160 2161 struct rtw89_btc_fbtc_slots { 2162 u8 fver; /* btc_ver::fcxslots */ 2163 u8 tbl_num; 2164 __le16 rsvd; 2165 __le32 update_map; 2166 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2167 } __packed; 2168 2169 struct rtw89_btc_fbtc_step { 2170 u8 type; 2171 u8 val; 2172 __le16 difft; 2173 } __packed; 2174 2175 struct rtw89_btc_fbtc_steps_v2 { 2176 u8 fver; /* btc_ver::fcxstep */ 2177 u8 rsvd; 2178 __le16 cnt; 2179 __le16 pos_old; 2180 __le16 pos_new; 2181 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2182 } __packed; 2183 2184 struct rtw89_btc_fbtc_steps_v3 { 2185 u8 fver; 2186 u8 en; 2187 __le16 rsvd; 2188 __le32 cnt; 2189 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2190 } __packed; 2191 2192 union rtw89_btc_fbtc_steps_info { 2193 struct rtw89_btc_fbtc_steps_v2 v2; 2194 struct rtw89_btc_fbtc_steps_v3 v3; 2195 }; 2196 2197 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2198 u8 fver; /* btc_ver::fcxcysta */ 2199 u8 rsvd; 2200 __le16 cycles; /* total cycle number */ 2201 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2202 __le16 a2dpept; /* a2dp empty cnt */ 2203 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2204 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2205 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2206 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2207 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2208 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2209 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2210 __le16 tmax_a2dpept; /* max a2dp empty time */ 2211 __le16 tavg_lk; /* avg leak-slot time */ 2212 __le16 tmax_lk; /* max leak-slot time */ 2213 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2214 __le32 bcn_cnt[CXBCN_MAX]; 2215 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2216 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2217 __le32 skip_cnt; 2218 __le32 exception; 2219 __le32 except_cnt; 2220 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2221 } __packed; 2222 2223 struct rtw89_btc_fbtc_fdd_try_info { 2224 __le16 cycles[CXT_FLCTRL_MAX]; 2225 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2226 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2227 } __packed; 2228 2229 struct rtw89_btc_fbtc_cycle_time_info { 2230 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2231 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2232 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2233 } __packed; 2234 2235 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2236 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2237 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2238 } __packed; 2239 2240 struct rtw89_btc_fbtc_a2dp_trx_stat { 2241 u8 empty_cnt; 2242 u8 retry_cnt; 2243 u8 tx_rate; 2244 u8 tx_cnt; 2245 u8 ack_cnt; 2246 u8 nack_cnt; 2247 u8 rsvd1; 2248 u8 rsvd2; 2249 } __packed; 2250 2251 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2252 u8 empty_cnt; 2253 u8 retry_cnt; 2254 u8 tx_rate; 2255 u8 tx_cnt; 2256 u8 ack_cnt; 2257 u8 nack_cnt; 2258 u8 no_empty_cnt; 2259 u8 rsvd; 2260 } __packed; 2261 2262 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2263 __le16 cnt; /* a2dp empty cnt */ 2264 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2265 __le16 tavg; /* avg a2dp empty time */ 2266 __le16 tmax; /* max a2dp empty time */ 2267 } __packed; 2268 2269 struct rtw89_btc_fbtc_cycle_leak_info { 2270 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2271 __le16 tavg; /* avg leak-slot time */ 2272 __le16 tmax; /* max leak-slot time */ 2273 } __packed; 2274 2275 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2276 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2277 2278 struct rtw89_btc_fbtc_cycle_fddt_info { 2279 __le16 train_cycle; 2280 __le16 tp; 2281 2282 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2283 s8 bt_tx_power; /* decrease Tx power (dB) */ 2284 s8 bt_rx_gain; /* LNA constrain level */ 2285 u8 no_empty_cnt; 2286 2287 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2288 u8 cn; /* condition_num */ 2289 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2290 u8 train_result; /* refer to enum btc_fddt_check_map */ 2291 } __packed; 2292 2293 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2294 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2295 2296 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2297 __le16 train_cycle; 2298 __le16 tp; 2299 2300 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2301 s8 bt_tx_power; /* decrease Tx power (dB) */ 2302 s8 bt_rx_gain; /* LNA constrain level */ 2303 u8 no_empty_cnt; 2304 2305 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2306 u8 cn; /* condition_num */ 2307 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2308 u8 train_result; /* refer to enum btc_fddt_check_map */ 2309 } __packed; 2310 2311 struct rtw89_btc_fbtc_fddt_cell_status { 2312 s8 wl_tx_pwr; 2313 s8 bt_tx_pwr; 2314 s8 bt_rx_gain; 2315 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2316 } __packed; 2317 2318 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2319 u8 fver; 2320 u8 rsvd; 2321 __le16 cycles; /* total cycle number */ 2322 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2323 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2324 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2325 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2326 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2327 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2328 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2329 __le32 bcn_cnt[CXBCN_MAX]; 2330 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2331 __le32 skip_cnt; 2332 __le32 except_cnt; 2333 __le32 except_map; 2334 } __packed; 2335 2336 #define FDD_TRAIN_WL_DIRECTION 2 2337 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2338 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2339 2340 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2341 u8 fver; 2342 u8 rsvd; 2343 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2344 u8 except_cnt; 2345 2346 __le16 skip_cnt; 2347 __le16 cycles; /* total cycle number */ 2348 2349 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2350 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2351 __le16 bcn_cnt[CXBCN_MAX]; 2352 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2353 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2354 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2355 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2356 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2357 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2358 [FDD_TRAIN_WL_RSSI_LEVEL] 2359 [FDD_TRAIN_BT_RSSI_LEVEL]; 2360 __le32 except_map; 2361 } __packed; 2362 2363 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2364 u8 fver; 2365 u8 rsvd; 2366 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2367 u8 except_cnt; 2368 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2369 2370 __le16 skip_cnt; 2371 __le16 cycles; /* total cycle number */ 2372 2373 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2374 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2375 __le16 bcn_cnt[CXBCN_MAX]; 2376 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2377 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2378 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2379 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2380 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2381 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2382 [FDD_TRAIN_WL_RSSI_LEVEL] 2383 [FDD_TRAIN_BT_RSSI_LEVEL]; 2384 __le32 except_map; 2385 } __packed; 2386 2387 union rtw89_btc_fbtc_cysta_info { 2388 struct rtw89_btc_fbtc_cysta_v2 v2; 2389 struct rtw89_btc_fbtc_cysta_v3 v3; 2390 struct rtw89_btc_fbtc_cysta_v4 v4; 2391 struct rtw89_btc_fbtc_cysta_v5 v5; 2392 }; 2393 2394 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2395 u8 fver; /* btc_ver::fcxnullsta */ 2396 u8 rsvd; 2397 __le16 rsvd2; 2398 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2399 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2400 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2401 } __packed; 2402 2403 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2404 u8 fver; /* btc_ver::fcxnullsta */ 2405 u8 rsvd; 2406 __le16 rsvd2; 2407 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2408 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2409 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2410 } __packed; 2411 2412 union rtw89_btc_fbtc_cynullsta_info { 2413 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2414 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2415 }; 2416 2417 struct rtw89_btc_fbtc_btver { 2418 u8 fver; /* btc_ver::fcxbtver */ 2419 u8 rsvd; 2420 __le16 rsvd2; 2421 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2422 __le32 fw_ver; 2423 __le32 feature; 2424 } __packed; 2425 2426 struct rtw89_btc_fbtc_btafh { 2427 u8 fver; /* btc_ver::fcxbtafh */ 2428 u8 rsvd; 2429 __le16 rsvd2; 2430 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2431 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2432 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2433 } __packed; 2434 2435 struct rtw89_btc_fbtc_btafh_v2 { 2436 u8 fver; /* btc_ver::fcxbtafh */ 2437 u8 rsvd; 2438 u8 rsvd2; 2439 u8 map_type; 2440 u8 afh_l[4]; 2441 u8 afh_m[4]; 2442 u8 afh_h[4]; 2443 u8 afh_le_a[4]; 2444 u8 afh_le_b[4]; 2445 } __packed; 2446 2447 struct rtw89_btc_fbtc_btdevinfo { 2448 u8 fver; /* btc_ver::fcxbtdevinfo */ 2449 u8 rsvd; 2450 __le16 vendor_id; 2451 __le32 dev_name; /* only 24 bits valid */ 2452 __le32 flush_time; 2453 } __packed; 2454 2455 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2456 struct rtw89_btc_rf_trx_para { 2457 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2458 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2459 u8 bt_tx_power; /* decrease Tx power (dB) */ 2460 u8 bt_rx_gain; /* LNA constrain level */ 2461 }; 2462 2463 struct rtw89_btc_trx_info { 2464 u8 tx_lvl; 2465 u8 rx_lvl; 2466 u8 wl_rssi; 2467 u8 bt_rssi; 2468 2469 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2470 s8 rx_gain; /* rx gain table index (TBD.) */ 2471 s8 bt_tx_power; /* decrease Tx power (dB) */ 2472 s8 bt_rx_gain; /* LNA constrain level */ 2473 2474 u8 cn; /* condition_num */ 2475 s8 nhm; 2476 u8 bt_profile; 2477 u8 rsvd2; 2478 2479 u16 tx_rate; 2480 u16 rx_rate; 2481 2482 u32 tx_tp; 2483 u32 rx_tp; 2484 u32 rx_err_ratio; 2485 }; 2486 2487 struct rtw89_btc_dm { 2488 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2489 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2490 struct rtw89_btc_fbtc_tdma tdma; 2491 struct rtw89_btc_fbtc_tdma tdma_now; 2492 struct rtw89_mac_ax_coex_gnt gnt; 2493 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2494 struct rtw89_btc_rf_trx_para rf_trx_para; 2495 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2496 struct rtw89_btc_dm_step dm_step; 2497 struct rtw89_btc_wl_scc_ctrl wl_scc; 2498 struct rtw89_btc_trx_info trx_info; 2499 union rtw89_btc_dm_error_map error; 2500 u32 cnt_dm[BTC_DCNT_NUM]; 2501 u32 cnt_notify[BTC_NCNT_NUM]; 2502 2503 u32 update_slot_map; 2504 u32 set_ant_path; 2505 2506 u32 wl_only: 1; 2507 u32 wl_fw_cx_offload: 1; 2508 u32 freerun: 1; 2509 u32 fddt_train: 1; 2510 u32 wl_ps_ctrl: 2; 2511 u32 wl_mimo_ps: 1; 2512 u32 leak_ap: 1; 2513 u32 noisy_level: 3; 2514 u32 coex_info_map: 8; 2515 u32 bt_only: 1; 2516 u32 wl_btg_rx: 2; 2517 u32 trx_para_level: 8; 2518 u32 wl_stb_chg: 1; 2519 u32 pta_owner: 1; 2520 2521 u32 tdma_instant_excute: 1; 2522 u32 wl_btg_rx_rb: 2; 2523 2524 u16 slot_dur[CXST_MAX]; 2525 2526 u8 run_reason; 2527 u8 run_action; 2528 2529 u8 wl_pre_agc: 2; 2530 u8 wl_lna2: 1; 2531 u8 wl_pre_agc_rb: 2; 2532 }; 2533 2534 struct rtw89_btc_ctrl { 2535 u32 manual: 1; 2536 u32 igno_bt: 1; 2537 u32 always_freerun: 1; 2538 u32 trace_step: 16; 2539 u32 rsvd: 12; 2540 }; 2541 2542 struct rtw89_btc_dbg { 2543 /* cmd "rb" */ 2544 bool rb_done; 2545 u32 rb_val; 2546 }; 2547 2548 enum rtw89_btc_btf_fw_event { 2549 BTF_EVNT_RPT = 0, 2550 BTF_EVNT_BT_INFO = 1, 2551 BTF_EVNT_BT_SCBD = 2, 2552 BTF_EVNT_BT_REG = 3, 2553 BTF_EVNT_CX_RUNINFO = 4, 2554 BTF_EVNT_BT_PSD = 5, 2555 BTF_EVNT_BUF_OVERFLOW, 2556 BTF_EVNT_C2H_LOOPBACK, 2557 BTF_EVNT_MAX, 2558 }; 2559 2560 enum btf_fw_event_report { 2561 BTC_RPT_TYPE_CTRL = 0x0, 2562 BTC_RPT_TYPE_TDMA, 2563 BTC_RPT_TYPE_SLOT, 2564 BTC_RPT_TYPE_CYSTA, 2565 BTC_RPT_TYPE_STEP, 2566 BTC_RPT_TYPE_NULLSTA, 2567 BTC_RPT_TYPE_MREG, 2568 BTC_RPT_TYPE_GPIO_DBG, 2569 BTC_RPT_TYPE_BT_VER, 2570 BTC_RPT_TYPE_BT_SCAN, 2571 BTC_RPT_TYPE_BT_AFH, 2572 BTC_RPT_TYPE_BT_DEVICE, 2573 BTC_RPT_TYPE_TEST, 2574 BTC_RPT_TYPE_MAX = 31 2575 }; 2576 2577 enum rtw_btc_btf_reg_type { 2578 REG_MAC = 0x0, 2579 REG_BB = 0x1, 2580 REG_RF = 0x2, 2581 REG_BT_RF = 0x3, 2582 REG_BT_MODEM = 0x4, 2583 REG_BT_BLUEWIZE = 0x5, 2584 REG_BT_VENDOR = 0x6, 2585 REG_BT_LE = 0x7, 2586 REG_MAX_TYPE, 2587 }; 2588 2589 struct rtw89_btc_rpt_cmn_info { 2590 u32 rx_cnt; 2591 u32 rx_len; 2592 u32 req_len; /* expected rsp len */ 2593 u8 req_fver; /* expected rsp fver */ 2594 u8 rsp_fver; /* fver from fw */ 2595 u8 valid; 2596 } __packed; 2597 2598 union rtw89_btc_fbtc_btafh_info { 2599 struct rtw89_btc_fbtc_btafh v1; 2600 struct rtw89_btc_fbtc_btafh_v2 v2; 2601 }; 2602 2603 struct rtw89_btc_report_ctrl_state { 2604 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2605 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2606 }; 2607 2608 struct rtw89_btc_rpt_fbtc_tdma { 2609 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2610 union rtw89_btc_fbtc_tdma_le32 finfo; 2611 }; 2612 2613 struct rtw89_btc_rpt_fbtc_slots { 2614 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2615 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2616 }; 2617 2618 struct rtw89_btc_rpt_fbtc_cysta { 2619 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2620 union rtw89_btc_fbtc_cysta_info finfo; 2621 }; 2622 2623 struct rtw89_btc_rpt_fbtc_step { 2624 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2625 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2626 }; 2627 2628 struct rtw89_btc_rpt_fbtc_nullsta { 2629 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2630 union rtw89_btc_fbtc_cynullsta_info finfo; 2631 }; 2632 2633 struct rtw89_btc_rpt_fbtc_mreg { 2634 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2635 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2636 }; 2637 2638 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2639 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2640 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2641 }; 2642 2643 struct rtw89_btc_rpt_fbtc_btver { 2644 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2645 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2646 }; 2647 2648 struct rtw89_btc_rpt_fbtc_btscan { 2649 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2650 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2651 }; 2652 2653 struct rtw89_btc_rpt_fbtc_btafh { 2654 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2655 union rtw89_btc_fbtc_btafh_info finfo; 2656 }; 2657 2658 struct rtw89_btc_rpt_fbtc_btdev { 2659 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2660 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2661 }; 2662 2663 enum rtw89_btc_btfre_type { 2664 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2665 BTFRE_UNDEF_TYPE, 2666 BTFRE_EXCEPTION, 2667 BTFRE_MAX, 2668 }; 2669 2670 struct rtw89_btc_btf_fwinfo { 2671 u32 cnt_c2h; 2672 u32 cnt_h2c; 2673 u32 cnt_h2c_fail; 2674 u32 event[BTF_EVNT_MAX]; 2675 2676 u32 err[BTFRE_MAX]; 2677 u32 len_mismch; 2678 u32 fver_mismch; 2679 u32 rpt_en_map; 2680 2681 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2682 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2683 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2684 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2685 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2686 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2687 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2688 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2689 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2690 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2691 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2692 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2693 }; 2694 2695 struct rtw89_btc_ver { 2696 enum rtw89_core_chip_id chip_id; 2697 u32 fw_ver_code; 2698 2699 u8 fcxbtcrpt; 2700 u8 fcxtdma; 2701 u8 fcxslots; 2702 u8 fcxcysta; 2703 u8 fcxstep; 2704 u8 fcxnullsta; 2705 u8 fcxmreg; 2706 u8 fcxgpiodbg; 2707 u8 fcxbtver; 2708 u8 fcxbtscan; 2709 u8 fcxbtafh; 2710 u8 fcxbtdevinfo; 2711 u8 fwlrole; 2712 u8 frptmap; 2713 u8 fcxctrl; 2714 2715 u16 info_buf; 2716 u8 max_role_num; 2717 }; 2718 2719 #define RTW89_BTC_POLICY_MAXLEN 512 2720 2721 struct rtw89_btc { 2722 const struct rtw89_btc_ver *ver; 2723 2724 struct rtw89_btc_cx cx; 2725 struct rtw89_btc_dm dm; 2726 struct rtw89_btc_ctrl ctrl; 2727 struct rtw89_btc_module mdinfo; 2728 struct rtw89_btc_btf_fwinfo fwinfo; 2729 struct rtw89_btc_dbg dbg; 2730 2731 struct work_struct eapol_notify_work; 2732 struct work_struct arp_notify_work; 2733 struct work_struct dhcp_notify_work; 2734 struct work_struct icmp_notify_work; 2735 2736 u32 bt_req_len; 2737 2738 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2739 u16 policy_len; 2740 u16 policy_type; 2741 bool bt_req_en; 2742 bool update_policy_force; 2743 bool lps; 2744 }; 2745 2746 enum rtw89_btc_hmsg { 2747 RTW89_BTC_HMSG_TMR_EN = 0x0, 2748 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 2749 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 2750 RTW89_BTC_HMSG_FW_EV = 0x3, 2751 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 2752 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 2753 2754 NUM_OF_RTW89_BTC_HMSG, 2755 }; 2756 2757 enum rtw89_ra_mode { 2758 RTW89_RA_MODE_CCK = BIT(0), 2759 RTW89_RA_MODE_OFDM = BIT(1), 2760 RTW89_RA_MODE_HT = BIT(2), 2761 RTW89_RA_MODE_VHT = BIT(3), 2762 RTW89_RA_MODE_HE = BIT(4), 2763 RTW89_RA_MODE_EHT = BIT(5), 2764 }; 2765 2766 enum rtw89_ra_report_mode { 2767 RTW89_RA_RPT_MODE_LEGACY, 2768 RTW89_RA_RPT_MODE_HT, 2769 RTW89_RA_RPT_MODE_VHT, 2770 RTW89_RA_RPT_MODE_HE, 2771 RTW89_RA_RPT_MODE_EHT, 2772 }; 2773 2774 enum rtw89_dig_noisy_level { 2775 RTW89_DIG_NOISY_LEVEL0 = -1, 2776 RTW89_DIG_NOISY_LEVEL1 = 0, 2777 RTW89_DIG_NOISY_LEVEL2 = 1, 2778 RTW89_DIG_NOISY_LEVEL3 = 2, 2779 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2780 }; 2781 2782 enum rtw89_gi_ltf { 2783 RTW89_GILTF_LGI_4XHE32 = 0, 2784 RTW89_GILTF_SGI_4XHE08 = 1, 2785 RTW89_GILTF_2XHE16 = 2, 2786 RTW89_GILTF_2XHE08 = 3, 2787 RTW89_GILTF_1XHE16 = 4, 2788 RTW89_GILTF_1XHE08 = 5, 2789 RTW89_GILTF_MAX 2790 }; 2791 2792 enum rtw89_rx_frame_type { 2793 RTW89_RX_TYPE_MGNT = 0, 2794 RTW89_RX_TYPE_CTRL = 1, 2795 RTW89_RX_TYPE_DATA = 2, 2796 RTW89_RX_TYPE_RSVD = 3, 2797 }; 2798 2799 enum rtw89_efuse_block { 2800 RTW89_EFUSE_BLOCK_SYS = 0, 2801 RTW89_EFUSE_BLOCK_RF = 1, 2802 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 2803 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 2804 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 2805 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 2806 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 2807 RTW89_EFUSE_BLOCK_ADIE = 7, 2808 2809 RTW89_EFUSE_BLOCK_NUM, 2810 RTW89_EFUSE_BLOCK_IGNORE, 2811 }; 2812 2813 struct rtw89_ra_info { 2814 u8 is_dis_ra:1; 2815 /* Bit0 : CCK 2816 * Bit1 : OFDM 2817 * Bit2 : HT 2818 * Bit3 : VHT 2819 * Bit4 : HE 2820 * Bit5 : EHT 2821 */ 2822 u8 mode_ctrl:6; 2823 u8 bw_cap:3; /* enum rtw89_bandwidth */ 2824 u8 macid; 2825 u8 dcm_cap:1; 2826 u8 er_cap:1; 2827 u8 init_rate_lv:2; 2828 u8 upd_all:1; 2829 u8 en_sgi:1; 2830 u8 ldpc_cap:1; 2831 u8 stbc_cap:1; 2832 u8 ss_num:3; 2833 u8 giltf:3; 2834 u8 upd_bw_nss_mask:1; 2835 u8 upd_mask:1; 2836 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2837 /* BFee CSI */ 2838 u8 band_num; 2839 u8 ra_csi_rate_en:1; 2840 u8 fixed_csi_rate_en:1; 2841 u8 cr_tbl_sel:1; 2842 u8 fix_giltf_en:1; 2843 u8 fix_giltf:3; 2844 u8 rsvd2:1; 2845 u8 csi_mcs_ss_idx; 2846 u8 csi_mode:2; 2847 u8 csi_gi_ltf:3; 2848 u8 csi_bw:3; 2849 }; 2850 2851 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2852 #define RTW89_PPDU_MAC_INFO_SIZE 8 2853 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2854 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 2855 2856 #define RTW89_MAX_RX_AGG_NUM 64 2857 #define RTW89_MAX_TX_AGG_NUM 128 2858 2859 struct rtw89_ampdu_params { 2860 u16 agg_num; 2861 bool amsdu; 2862 }; 2863 2864 struct rtw89_ra_report { 2865 struct rate_info txrate; 2866 u32 bit_rate; 2867 u16 hw_rate; 2868 bool might_fallback_legacy; 2869 }; 2870 2871 DECLARE_EWMA(rssi, 10, 16); 2872 DECLARE_EWMA(evm, 10, 16); 2873 DECLARE_EWMA(snr, 10, 16); 2874 2875 struct rtw89_ba_cam_entry { 2876 struct list_head list; 2877 u8 tid; 2878 }; 2879 2880 #define RTW89_MAX_ADDR_CAM_NUM 128 2881 #define RTW89_MAX_BSSID_CAM_NUM 20 2882 #define RTW89_MAX_SEC_CAM_NUM 128 2883 #define RTW89_MAX_BA_CAM_NUM 24 2884 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2885 2886 struct rtw89_addr_cam_entry { 2887 u8 addr_cam_idx; 2888 u8 offset; 2889 u8 len; 2890 u8 valid : 1; 2891 u8 addr_mask : 6; 2892 u8 wapi : 1; 2893 u8 mask_sel : 2; 2894 u8 bssid_cam_idx: 6; 2895 2896 u8 sec_ent_mode; 2897 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2898 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2899 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2900 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2901 }; 2902 2903 struct rtw89_bssid_cam_entry { 2904 u8 bssid[ETH_ALEN]; 2905 u8 phy_idx; 2906 u8 bssid_cam_idx; 2907 u8 offset; 2908 u8 len; 2909 u8 valid : 1; 2910 u8 num; 2911 }; 2912 2913 struct rtw89_sec_cam_entry { 2914 u8 sec_cam_idx; 2915 u8 offset; 2916 u8 len; 2917 u8 type : 4; 2918 u8 ext_key : 1; 2919 u8 spp_mode : 1; 2920 /* 256 bits */ 2921 u8 key[32]; 2922 }; 2923 2924 struct rtw89_sta { 2925 u8 mac_id; 2926 bool disassoc; 2927 bool er_cap; 2928 struct rtw89_dev *rtwdev; 2929 struct rtw89_vif *rtwvif; 2930 struct rtw89_ra_info ra; 2931 struct rtw89_ra_report ra_report; 2932 int max_agg_wait; 2933 u8 prev_rssi; 2934 struct ewma_rssi avg_rssi; 2935 struct ewma_rssi rssi[RF_PATH_MAX]; 2936 struct ewma_snr avg_snr; 2937 struct ewma_evm evm_min[RF_PATH_MAX]; 2938 struct ewma_evm evm_max[RF_PATH_MAX]; 2939 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2940 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 2941 struct ieee80211_rx_status rx_status; 2942 u16 rx_hw_rate; 2943 __le32 htc_template; 2944 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2945 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2946 struct list_head ba_cam_list; 2947 struct sk_buff_head roc_queue; 2948 2949 bool use_cfg_mask; 2950 struct cfg80211_bitrate_mask mask; 2951 2952 bool cctl_tx_time; 2953 u32 ampdu_max_time:4; 2954 bool cctl_tx_retry_limit; 2955 u32 data_tx_cnt_lmt:6; 2956 }; 2957 2958 struct rtw89_efuse { 2959 bool valid; 2960 bool power_k_valid; 2961 u8 xtal_cap; 2962 u8 addr[ETH_ALEN]; 2963 u8 rfe_type; 2964 char country_code[2]; 2965 }; 2966 2967 struct rtw89_phy_rate_pattern { 2968 u64 ra_mask; 2969 u16 rate; 2970 u8 ra_mode; 2971 bool enable; 2972 }; 2973 2974 struct rtw89_tx_wait_info { 2975 struct rcu_head rcu_head; 2976 struct completion completion; 2977 bool tx_done; 2978 }; 2979 2980 struct rtw89_tx_skb_data { 2981 struct rtw89_tx_wait_info __rcu *wait; 2982 u8 hci_priv[]; 2983 }; 2984 2985 #define RTW89_ROC_IDLE_TIMEOUT 500 2986 #define RTW89_ROC_TX_TIMEOUT 30 2987 enum rtw89_roc_state { 2988 RTW89_ROC_IDLE, 2989 RTW89_ROC_NORMAL, 2990 RTW89_ROC_MGMT, 2991 }; 2992 2993 struct rtw89_roc { 2994 struct ieee80211_channel chan; 2995 struct delayed_work roc_work; 2996 enum ieee80211_roc_type type; 2997 enum rtw89_roc_state state; 2998 int duration; 2999 }; 3000 3001 #define RTW89_P2P_MAX_NOA_NUM 2 3002 3003 struct rtw89_p2p_ie_head { 3004 u8 eid; 3005 u8 ie_len; 3006 u8 oui[3]; 3007 u8 oui_type; 3008 } __packed; 3009 3010 struct rtw89_noa_attr_head { 3011 u8 attr_type; 3012 __le16 attr_len; 3013 u8 index; 3014 u8 oppps_ctwindow; 3015 } __packed; 3016 3017 struct rtw89_p2p_noa_ie { 3018 struct rtw89_p2p_ie_head p2p_head; 3019 struct rtw89_noa_attr_head noa_head; 3020 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3021 } __packed; 3022 3023 struct rtw89_p2p_noa_setter { 3024 struct rtw89_p2p_noa_ie ie; 3025 u8 noa_count; 3026 u8 noa_index; 3027 }; 3028 3029 struct rtw89_vif { 3030 struct list_head list; 3031 struct rtw89_dev *rtwdev; 3032 struct rtw89_roc roc; 3033 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3034 enum rtw89_sub_entity_idx sub_entity_idx; 3035 enum rtw89_reg_6ghz_power reg_6ghz_power; 3036 3037 u8 mac_id; 3038 u8 port; 3039 u8 mac_addr[ETH_ALEN]; 3040 u8 bssid[ETH_ALEN]; 3041 u8 phy_idx; 3042 u8 mac_idx; 3043 u8 net_type; 3044 u8 wifi_role; 3045 u8 self_role; 3046 u8 wmm; 3047 u8 bcn_hit_cond; 3048 u8 hit_rule; 3049 u8 last_noa_nr; 3050 u64 sync_bcn_tsf; 3051 bool offchan; 3052 bool trigger; 3053 bool lsig_txop; 3054 u8 tgt_ind; 3055 u8 frm_tgt_ind; 3056 bool wowlan_pattern; 3057 bool wowlan_uc; 3058 bool wowlan_magic; 3059 bool is_hesta; 3060 bool last_a_ctrl; 3061 bool dyn_tb_bedge_en; 3062 bool pre_pwr_diff_en; 3063 bool pwr_diff_en; 3064 u8 def_tri_idx; 3065 u32 tdls_peer; 3066 struct work_struct update_beacon_work; 3067 struct rtw89_addr_cam_entry addr_cam; 3068 struct rtw89_bssid_cam_entry bssid_cam; 3069 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3070 struct rtw89_traffic_stats stats; 3071 struct rtw89_phy_rate_pattern rate_pattern; 3072 struct cfg80211_scan_request *scan_req; 3073 struct ieee80211_scan_ies *scan_ies; 3074 struct list_head general_pkt_list; 3075 struct rtw89_p2p_noa_setter p2p_noa; 3076 }; 3077 3078 enum rtw89_lv1_rcvy_step { 3079 RTW89_LV1_RCVY_STEP_1, 3080 RTW89_LV1_RCVY_STEP_2, 3081 }; 3082 3083 struct rtw89_hci_ops { 3084 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3085 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3086 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3087 void (*reset)(struct rtw89_dev *rtwdev); 3088 int (*start)(struct rtw89_dev *rtwdev); 3089 void (*stop)(struct rtw89_dev *rtwdev); 3090 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3091 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3092 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3093 3094 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3095 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3096 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3097 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3098 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3099 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3100 3101 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3102 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3103 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3104 int (*deinit)(struct rtw89_dev *rtwdev); 3105 3106 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3107 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3108 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3109 int (*napi_poll)(struct napi_struct *napi, int budget); 3110 3111 /* Deal with locks inside recovery_start and recovery_complete callbacks 3112 * by hci instance, and handle things which need to consider under SER. 3113 * e.g. turn on/off interrupts except for the one for halt notification. 3114 */ 3115 void (*recovery_start)(struct rtw89_dev *rtwdev); 3116 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3117 3118 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3119 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3120 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3121 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 3122 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3123 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3124 void (*disable_intr)(struct rtw89_dev *rtwdev); 3125 void (*enable_intr)(struct rtw89_dev *rtwdev); 3126 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3127 }; 3128 3129 struct rtw89_hci_info { 3130 const struct rtw89_hci_ops *ops; 3131 enum rtw89_hci_type type; 3132 u32 rpwm_addr; 3133 u32 cpwm_addr; 3134 bool paused; 3135 }; 3136 3137 struct rtw89_chip_ops { 3138 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3139 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3140 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3141 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3142 void (*bb_reset)(struct rtw89_dev *rtwdev, 3143 enum rtw89_phy_idx phy_idx); 3144 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3145 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3146 u32 addr, u32 mask); 3147 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3148 u32 addr, u32 mask, u32 data); 3149 void (*set_channel)(struct rtw89_dev *rtwdev, 3150 const struct rtw89_chan *chan, 3151 enum rtw89_mac_idx mac_idx, 3152 enum rtw89_phy_idx phy_idx); 3153 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3154 struct rtw89_channel_help_params *p, 3155 const struct rtw89_chan *chan, 3156 enum rtw89_mac_idx mac_idx, 3157 enum rtw89_phy_idx phy_idx); 3158 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3159 enum rtw89_efuse_block block); 3160 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3161 void (*fem_setup)(struct rtw89_dev *rtwdev); 3162 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3163 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3164 void (*rfk_init)(struct rtw89_dev *rtwdev); 3165 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3166 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3167 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3168 enum rtw89_phy_idx phy_idx); 3169 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3170 void (*rfk_track)(struct rtw89_dev *rtwdev); 3171 void (*power_trim)(struct rtw89_dev *rtwdev); 3172 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3173 const struct rtw89_chan *chan, 3174 enum rtw89_phy_idx phy_idx); 3175 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3176 enum rtw89_phy_idx phy_idx); 3177 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3178 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3179 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3180 enum rtw89_phy_idx phy_idx); 3181 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3182 struct rtw89_rx_phy_ppdu *phy_ppdu, 3183 struct ieee80211_rx_status *status); 3184 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3185 enum rtw89_phy_idx phy_idx); 3186 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3187 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3188 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3189 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3190 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3191 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3192 struct rtw89_rx_desc_info *desc_info, 3193 u8 *data, u32 data_offset); 3194 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3195 struct rtw89_tx_desc_info *desc_info, 3196 void *txdesc); 3197 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3198 struct rtw89_tx_desc_info *desc_info, 3199 void *txdesc); 3200 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3201 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3202 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3203 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3204 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3205 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3206 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3207 struct rtw89_vif *rtwvif, 3208 struct rtw89_sta *rtwsta); 3209 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3210 struct rtw89_vif *rtwvif, 3211 struct rtw89_sta *rtwsta); 3212 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3213 struct ieee80211_vif *vif, 3214 struct ieee80211_sta *sta); 3215 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3216 struct ieee80211_vif *vif, 3217 struct ieee80211_sta *sta); 3218 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3219 struct rtw89_vif *rtwvif, 3220 struct rtw89_sta *rtwsta); 3221 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3222 struct rtw89_vif *rtwvif); 3223 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3224 bool valid, struct ieee80211_ampdu_params *params); 3225 3226 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3227 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3228 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3229 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3230 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3231 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3232 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3233 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3234 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3235 }; 3236 3237 enum rtw89_dma_ch { 3238 RTW89_DMA_ACH0 = 0, 3239 RTW89_DMA_ACH1 = 1, 3240 RTW89_DMA_ACH2 = 2, 3241 RTW89_DMA_ACH3 = 3, 3242 RTW89_DMA_ACH4 = 4, 3243 RTW89_DMA_ACH5 = 5, 3244 RTW89_DMA_ACH6 = 6, 3245 RTW89_DMA_ACH7 = 7, 3246 RTW89_DMA_B0MG = 8, 3247 RTW89_DMA_B0HI = 9, 3248 RTW89_DMA_B1MG = 10, 3249 RTW89_DMA_B1HI = 11, 3250 RTW89_DMA_H2C = 12, 3251 RTW89_DMA_CH_NUM = 13 3252 }; 3253 3254 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3255 3256 enum rtw89_mlo_dbcc_mode { 3257 MLO_DBCC_NOT_SUPPORT = 1, 3258 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3259 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3260 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3261 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3262 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3263 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3264 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3265 DBCC_LEGACY = 0xffffffff, 3266 }; 3267 3268 enum rtw89_scan_be_operation { 3269 RTW89_SCAN_OP_STOP, 3270 RTW89_SCAN_OP_START, 3271 RTW89_SCAN_OP_SETPARM, 3272 RTW89_SCAN_OP_GETRPT, 3273 RTW89_SCAN_OP_NUM 3274 }; 3275 3276 enum rtw89_scan_be_mode { 3277 RTW89_SCAN_MODE_SA, 3278 RTW89_SCAN_MODE_MACC, 3279 RTW89_SCAN_MODE_NUM 3280 }; 3281 3282 enum rtw89_scan_be_opmode { 3283 RTW89_SCAN_OPMODE_NONE, 3284 RTW89_SCAN_OPMODE_TBTT, 3285 RTW89_SCAN_OPMODE_INTV, 3286 RTW89_SCAN_OPMODE_CNT, 3287 RTW89_SCAN_OPMODE_NUM, 3288 }; 3289 3290 struct rtw89_scan_option { 3291 bool enable; 3292 bool target_ch_mode; 3293 u8 num_macc_role; 3294 u8 num_opch; 3295 u8 repeat; 3296 u16 norm_pd; 3297 u16 slow_pd; 3298 u16 norm_cy; 3299 u8 opch_end; 3300 u64 prohib_chan; 3301 enum rtw89_phy_idx band; 3302 enum rtw89_scan_be_operation operation; 3303 enum rtw89_scan_be_mode scan_mode; 3304 enum rtw89_mlo_dbcc_mode mlo_mode; 3305 }; 3306 3307 enum rtw89_qta_mode { 3308 RTW89_QTA_SCC, 3309 RTW89_QTA_DBCC, 3310 RTW89_QTA_DLFW, 3311 RTW89_QTA_WOW, 3312 3313 /* keep last */ 3314 RTW89_QTA_INVALID, 3315 }; 3316 3317 struct rtw89_hfc_ch_cfg { 3318 u16 min; 3319 u16 max; 3320 #define grp_0 0 3321 #define grp_1 1 3322 #define grp_num 2 3323 u8 grp; 3324 }; 3325 3326 struct rtw89_hfc_ch_info { 3327 u16 aval; 3328 u16 used; 3329 }; 3330 3331 struct rtw89_hfc_pub_cfg { 3332 u16 grp0; 3333 u16 grp1; 3334 u16 pub_max; 3335 u16 wp_thrd; 3336 }; 3337 3338 struct rtw89_hfc_pub_info { 3339 u16 g0_used; 3340 u16 g1_used; 3341 u16 g0_aval; 3342 u16 g1_aval; 3343 u16 pub_aval; 3344 u16 wp_aval; 3345 }; 3346 3347 struct rtw89_hfc_prec_cfg { 3348 u16 ch011_prec; 3349 u16 h2c_prec; 3350 u16 wp_ch07_prec; 3351 u16 wp_ch811_prec; 3352 u8 ch011_full_cond; 3353 u8 h2c_full_cond; 3354 u8 wp_ch07_full_cond; 3355 u8 wp_ch811_full_cond; 3356 }; 3357 3358 struct rtw89_hfc_param { 3359 bool en; 3360 bool h2c_en; 3361 u8 mode; 3362 const struct rtw89_hfc_ch_cfg *ch_cfg; 3363 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3364 struct rtw89_hfc_pub_cfg pub_cfg; 3365 struct rtw89_hfc_pub_info pub_info; 3366 struct rtw89_hfc_prec_cfg prec_cfg; 3367 }; 3368 3369 struct rtw89_hfc_param_ini { 3370 const struct rtw89_hfc_ch_cfg *ch_cfg; 3371 const struct rtw89_hfc_pub_cfg *pub_cfg; 3372 const struct rtw89_hfc_prec_cfg *prec_cfg; 3373 u8 mode; 3374 }; 3375 3376 struct rtw89_dle_size { 3377 u16 pge_size; 3378 u16 lnk_pge_num; 3379 u16 unlnk_pge_num; 3380 /* for WiFi 7 chips below */ 3381 u32 srt_ofst; 3382 }; 3383 3384 struct rtw89_wde_quota { 3385 u16 hif; 3386 u16 wcpu; 3387 u16 pkt_in; 3388 u16 cpu_io; 3389 }; 3390 3391 struct rtw89_ple_quota { 3392 u16 cma0_tx; 3393 u16 cma1_tx; 3394 u16 c2h; 3395 u16 h2c; 3396 u16 wcpu; 3397 u16 mpdu_proc; 3398 u16 cma0_dma; 3399 u16 cma1_dma; 3400 u16 bb_rpt; 3401 u16 wd_rel; 3402 u16 cpu_io; 3403 u16 tx_rpt; 3404 /* for WiFi 7 chips below */ 3405 u16 h2d; 3406 }; 3407 3408 struct rtw89_rsvd_quota { 3409 u16 mpdu_info_tbl; 3410 u16 b0_csi; 3411 u16 b1_csi; 3412 u16 b0_lmr; 3413 u16 b1_lmr; 3414 u16 b0_ftm; 3415 u16 b1_ftm; 3416 u16 b0_smr; 3417 u16 b1_smr; 3418 u16 others; 3419 }; 3420 3421 struct rtw89_dle_rsvd_size { 3422 u32 srt_ofst; 3423 u32 size; 3424 }; 3425 3426 struct rtw89_dle_mem { 3427 enum rtw89_qta_mode mode; 3428 const struct rtw89_dle_size *wde_size; 3429 const struct rtw89_dle_size *ple_size; 3430 const struct rtw89_wde_quota *wde_min_qt; 3431 const struct rtw89_wde_quota *wde_max_qt; 3432 const struct rtw89_ple_quota *ple_min_qt; 3433 const struct rtw89_ple_quota *ple_max_qt; 3434 /* for WiFi 7 chips below */ 3435 const struct rtw89_rsvd_quota *rsvd_qt; 3436 const struct rtw89_dle_rsvd_size *rsvd0_size; 3437 const struct rtw89_dle_rsvd_size *rsvd1_size; 3438 }; 3439 3440 struct rtw89_reg_def { 3441 u32 addr; 3442 u32 mask; 3443 }; 3444 3445 struct rtw89_reg2_def { 3446 u32 addr; 3447 u32 data; 3448 }; 3449 3450 struct rtw89_reg3_def { 3451 u32 addr; 3452 u32 mask; 3453 u32 data; 3454 }; 3455 3456 struct rtw89_reg5_def { 3457 u8 flag; /* recognized by parsers */ 3458 u8 path; 3459 u32 addr; 3460 u32 mask; 3461 u32 data; 3462 }; 3463 3464 struct rtw89_reg_imr { 3465 u32 addr; 3466 u32 clr; 3467 u32 set; 3468 }; 3469 3470 struct rtw89_phy_table { 3471 const struct rtw89_reg2_def *regs; 3472 u32 n_regs; 3473 enum rtw89_rf_path rf_path; 3474 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3475 enum rtw89_rf_path rf_path, void *data); 3476 }; 3477 3478 struct rtw89_txpwr_table { 3479 const void *data; 3480 u32 size; 3481 void (*load)(struct rtw89_dev *rtwdev, 3482 const struct rtw89_txpwr_table *tbl); 3483 }; 3484 3485 struct rtw89_txpwr_rule_2ghz { 3486 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3487 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3488 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3489 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3490 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3491 }; 3492 3493 struct rtw89_txpwr_rule_5ghz { 3494 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3495 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3496 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3497 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3498 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3499 }; 3500 3501 struct rtw89_txpwr_rule_6ghz { 3502 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3503 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3504 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3505 [RTW89_6G_CH_NUM]; 3506 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3507 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3508 [RTW89_6G_CH_NUM]; 3509 }; 3510 3511 struct rtw89_tx_shape { 3512 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3513 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3514 }; 3515 3516 struct rtw89_rfe_parms { 3517 const struct rtw89_txpwr_table *byr_tbl; 3518 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3519 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3520 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3521 struct rtw89_tx_shape tx_shape; 3522 }; 3523 3524 struct rtw89_rfe_parms_conf { 3525 const struct rtw89_rfe_parms *rfe_parms; 3526 u8 rfe_type; 3527 }; 3528 3529 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3530 3531 struct rtw89_txpwr_conf { 3532 u8 rfe_type; 3533 u8 ent_sz; 3534 u32 num_ents; 3535 const void *data; 3536 }; 3537 3538 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3539 3540 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3541 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3542 memcpy(&(entry), cursor, \ 3543 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3544 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3545 (cursor) += (conf)->ent_sz, \ 3546 memcpy(&(entry), cursor, \ 3547 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3548 3549 struct rtw89_txpwr_byrate_data { 3550 struct rtw89_txpwr_conf conf; 3551 struct rtw89_txpwr_table tbl; 3552 }; 3553 3554 struct rtw89_txpwr_lmt_2ghz_data { 3555 struct rtw89_txpwr_conf conf; 3556 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3557 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3558 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3559 }; 3560 3561 struct rtw89_txpwr_lmt_5ghz_data { 3562 struct rtw89_txpwr_conf conf; 3563 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3564 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3565 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3566 }; 3567 3568 struct rtw89_txpwr_lmt_6ghz_data { 3569 struct rtw89_txpwr_conf conf; 3570 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3571 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3572 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3573 [RTW89_6G_CH_NUM]; 3574 }; 3575 3576 struct rtw89_txpwr_lmt_ru_2ghz_data { 3577 struct rtw89_txpwr_conf conf; 3578 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3579 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3580 }; 3581 3582 struct rtw89_txpwr_lmt_ru_5ghz_data { 3583 struct rtw89_txpwr_conf conf; 3584 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3585 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3586 }; 3587 3588 struct rtw89_txpwr_lmt_ru_6ghz_data { 3589 struct rtw89_txpwr_conf conf; 3590 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3591 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3592 [RTW89_6G_CH_NUM]; 3593 }; 3594 3595 struct rtw89_tx_shape_lmt_data { 3596 struct rtw89_txpwr_conf conf; 3597 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3598 }; 3599 3600 struct rtw89_tx_shape_lmt_ru_data { 3601 struct rtw89_txpwr_conf conf; 3602 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3603 }; 3604 3605 struct rtw89_rfe_data { 3606 struct rtw89_txpwr_byrate_data byrate; 3607 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3608 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3609 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3610 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3611 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3612 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3613 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3614 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3615 struct rtw89_rfe_parms rfe_parms; 3616 }; 3617 3618 struct rtw89_page_regs { 3619 u32 hci_fc_ctrl; 3620 u32 ch_page_ctrl; 3621 u32 ach_page_ctrl; 3622 u32 ach_page_info; 3623 u32 pub_page_info3; 3624 u32 pub_page_ctrl1; 3625 u32 pub_page_ctrl2; 3626 u32 pub_page_info1; 3627 u32 pub_page_info2; 3628 u32 wp_page_ctrl1; 3629 u32 wp_page_ctrl2; 3630 u32 wp_page_info1; 3631 }; 3632 3633 struct rtw89_imr_info { 3634 u32 wdrls_imr_set; 3635 u32 wsec_imr_reg; 3636 u32 wsec_imr_set; 3637 u32 mpdu_tx_imr_set; 3638 u32 mpdu_rx_imr_set; 3639 u32 sta_sch_imr_set; 3640 u32 txpktctl_imr_b0_reg; 3641 u32 txpktctl_imr_b0_clr; 3642 u32 txpktctl_imr_b0_set; 3643 u32 txpktctl_imr_b1_reg; 3644 u32 txpktctl_imr_b1_clr; 3645 u32 txpktctl_imr_b1_set; 3646 u32 wde_imr_clr; 3647 u32 wde_imr_set; 3648 u32 ple_imr_clr; 3649 u32 ple_imr_set; 3650 u32 host_disp_imr_clr; 3651 u32 host_disp_imr_set; 3652 u32 cpu_disp_imr_clr; 3653 u32 cpu_disp_imr_set; 3654 u32 other_disp_imr_clr; 3655 u32 other_disp_imr_set; 3656 u32 bbrpt_com_err_imr_reg; 3657 u32 bbrpt_chinfo_err_imr_reg; 3658 u32 bbrpt_err_imr_set; 3659 u32 bbrpt_dfs_err_imr_reg; 3660 u32 ptcl_imr_clr; 3661 u32 ptcl_imr_set; 3662 u32 cdma_imr_0_reg; 3663 u32 cdma_imr_0_clr; 3664 u32 cdma_imr_0_set; 3665 u32 cdma_imr_1_reg; 3666 u32 cdma_imr_1_clr; 3667 u32 cdma_imr_1_set; 3668 u32 phy_intf_imr_reg; 3669 u32 phy_intf_imr_clr; 3670 u32 phy_intf_imr_set; 3671 u32 rmac_imr_reg; 3672 u32 rmac_imr_clr; 3673 u32 rmac_imr_set; 3674 u32 tmac_imr_reg; 3675 u32 tmac_imr_clr; 3676 u32 tmac_imr_set; 3677 }; 3678 3679 struct rtw89_imr_table { 3680 const struct rtw89_reg_imr *regs; 3681 u32 n_regs; 3682 }; 3683 3684 struct rtw89_xtal_info { 3685 u32 xcap_reg; 3686 u32 sc_xo_mask; 3687 u32 sc_xi_mask; 3688 }; 3689 3690 struct rtw89_rrsr_cfgs { 3691 struct rtw89_reg3_def ref_rate; 3692 struct rtw89_reg3_def rsc; 3693 }; 3694 3695 struct rtw89_dig_regs { 3696 u32 seg0_pd_reg; 3697 u32 pd_lower_bound_mask; 3698 u32 pd_spatial_reuse_en; 3699 u32 bmode_pd_reg; 3700 u32 bmode_cca_rssi_limit_en; 3701 u32 bmode_pd_lower_bound_reg; 3702 u32 bmode_rssi_nocca_low_th_mask; 3703 struct rtw89_reg_def p0_lna_init; 3704 struct rtw89_reg_def p1_lna_init; 3705 struct rtw89_reg_def p0_tia_init; 3706 struct rtw89_reg_def p1_tia_init; 3707 struct rtw89_reg_def p0_rxb_init; 3708 struct rtw89_reg_def p1_rxb_init; 3709 struct rtw89_reg_def p0_p20_pagcugc_en; 3710 struct rtw89_reg_def p0_s20_pagcugc_en; 3711 struct rtw89_reg_def p1_p20_pagcugc_en; 3712 struct rtw89_reg_def p1_s20_pagcugc_en; 3713 }; 3714 3715 struct rtw89_edcca_regs { 3716 u32 edcca_level; 3717 u32 edcca_mask; 3718 u32 edcca_p_mask; 3719 u32 ppdu_level; 3720 u32 ppdu_mask; 3721 u32 rpt_a; 3722 u32 rpt_b; 3723 u32 rpt_sel; 3724 u32 rpt_sel_mask; 3725 u32 rpt_sel_be; 3726 u32 rpt_sel_be_mask; 3727 u32 tx_collision_t2r_st; 3728 u32 tx_collision_t2r_st_mask; 3729 }; 3730 3731 struct rtw89_phy_ul_tb_info { 3732 bool dyn_tb_tri_en; 3733 u8 def_if_bandedge; 3734 }; 3735 3736 struct rtw89_antdiv_stats { 3737 struct ewma_rssi cck_rssi_avg; 3738 struct ewma_rssi ofdm_rssi_avg; 3739 struct ewma_rssi non_legacy_rssi_avg; 3740 u16 pkt_cnt_cck; 3741 u16 pkt_cnt_ofdm; 3742 u16 pkt_cnt_non_legacy; 3743 u32 evm; 3744 }; 3745 3746 struct rtw89_antdiv_info { 3747 struct rtw89_antdiv_stats target_stats; 3748 struct rtw89_antdiv_stats main_stats; 3749 struct rtw89_antdiv_stats aux_stats; 3750 u8 training_count; 3751 u8 rssi_pre; 3752 bool get_stats; 3753 }; 3754 3755 enum rtw89_chanctx_state { 3756 RTW89_CHANCTX_STATE_MCC_START, 3757 RTW89_CHANCTX_STATE_MCC_STOP, 3758 }; 3759 3760 enum rtw89_chanctx_callbacks { 3761 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 3762 RTW89_CHANCTX_CALLBACK_RFK, 3763 3764 NUM_OF_RTW89_CHANCTX_CALLBACKS, 3765 }; 3766 3767 struct rtw89_chanctx_listener { 3768 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 3769 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 3770 }; 3771 3772 struct rtw89_chip_info { 3773 enum rtw89_core_chip_id chip_id; 3774 enum rtw89_chip_gen chip_gen; 3775 const struct rtw89_chip_ops *ops; 3776 const struct rtw89_mac_gen_def *mac_def; 3777 const struct rtw89_phy_gen_def *phy_def; 3778 const char *fw_basename; 3779 u8 fw_format_max; 3780 bool try_ce_fw; 3781 u8 bbmcu_nr; 3782 u32 needed_fw_elms; 3783 u32 fifo_size; 3784 bool small_fifo_size; 3785 u32 dle_scc_rsvd_size; 3786 u16 max_amsdu_limit; 3787 bool dis_2g_40m_ul_ofdma; 3788 u32 rsvd_ple_ofst; 3789 const struct rtw89_hfc_param_ini *hfc_param_ini; 3790 const struct rtw89_dle_mem *dle_mem; 3791 u8 wde_qempty_acq_grpnum; 3792 u8 wde_qempty_mgq_grpsel; 3793 u32 rf_base_addr[2]; 3794 u8 support_chanctx_num; 3795 u8 support_bands; 3796 u16 support_bandwidths; 3797 bool support_unii4; 3798 bool ul_tb_waveform_ctrl; 3799 bool ul_tb_pwr_diff; 3800 bool hw_sec_hdr; 3801 u8 rf_path_num; 3802 u8 tx_nss; 3803 u8 rx_nss; 3804 u8 acam_num; 3805 u8 bcam_num; 3806 u8 scam_num; 3807 u8 bacam_num; 3808 u8 bacam_dynamic_num; 3809 enum rtw89_bacam_ver bacam_ver; 3810 u8 ppdu_max_usr; 3811 3812 u8 sec_ctrl_efuse_size; 3813 u32 physical_efuse_size; 3814 u32 logical_efuse_size; 3815 u32 limit_efuse_size; 3816 u32 dav_phy_efuse_size; 3817 u32 dav_log_efuse_size; 3818 u32 phycap_addr; 3819 u32 phycap_size; 3820 const struct rtw89_efuse_block_cfg *efuse_blocks; 3821 3822 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3823 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3824 const struct rtw89_phy_table *bb_table; 3825 const struct rtw89_phy_table *bb_gain_table; 3826 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3827 const struct rtw89_phy_table *nctl_table; 3828 const struct rtw89_rfk_tbl *nctl_post_table; 3829 const struct rtw89_phy_dig_gain_table *dig_table; 3830 const struct rtw89_dig_regs *dig_regs; 3831 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3832 3833 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3834 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3835 const struct rtw89_rfe_parms *dflt_parms; 3836 const struct rtw89_chanctx_listener *chanctx_listener; 3837 3838 u8 txpwr_factor_rf; 3839 u8 txpwr_factor_mac; 3840 3841 u32 para_ver; 3842 u32 wlcx_desired; 3843 u8 btcx_desired; 3844 u8 scbd; 3845 u8 mailbox; 3846 3847 u8 afh_guard_ch; 3848 const u8 *wl_rssi_thres; 3849 const u8 *bt_rssi_thres; 3850 u8 rssi_tol; 3851 3852 u8 mon_reg_num; 3853 const struct rtw89_btc_fbtc_mreg *mon_reg; 3854 u8 rf_para_ulink_num; 3855 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3856 u8 rf_para_dlink_num; 3857 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3858 u8 ps_mode_supported; 3859 u8 low_power_hci_modes; 3860 3861 u32 h2c_cctl_func_id; 3862 u32 hci_func_en_addr; 3863 u32 h2c_desc_size; 3864 u32 txwd_body_size; 3865 u32 txwd_info_size; 3866 u32 h2c_ctrl_reg; 3867 const u32 *h2c_regs; 3868 struct rtw89_reg_def h2c_counter_reg; 3869 u32 c2h_ctrl_reg; 3870 const u32 *c2h_regs; 3871 struct rtw89_reg_def c2h_counter_reg; 3872 const struct rtw89_page_regs *page_regs; 3873 bool cfo_src_fd; 3874 bool cfo_hw_comp; 3875 const struct rtw89_reg_def *dcfo_comp; 3876 u8 dcfo_comp_sft; 3877 const struct rtw89_imr_info *imr_info; 3878 const struct rtw89_imr_table *imr_dmac_table; 3879 const struct rtw89_imr_table *imr_cmac_table; 3880 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3881 struct rtw89_reg_def bss_clr_vld; 3882 u32 bss_clr_map_reg; 3883 u32 dma_ch_mask; 3884 const struct rtw89_edcca_regs *edcca_regs; 3885 const struct wiphy_wowlan_support *wowlan_stub; 3886 const struct rtw89_xtal_info *xtal_info; 3887 }; 3888 3889 union rtw89_bus_info { 3890 const struct rtw89_pci_info *pci; 3891 }; 3892 3893 struct rtw89_driver_info { 3894 const struct rtw89_chip_info *chip; 3895 union rtw89_bus_info bus; 3896 }; 3897 3898 enum rtw89_hcifc_mode { 3899 RTW89_HCIFC_POH = 0, 3900 RTW89_HCIFC_STF = 1, 3901 RTW89_HCIFC_SDIO = 2, 3902 3903 /* keep last */ 3904 RTW89_HCIFC_MODE_INVALID, 3905 }; 3906 3907 struct rtw89_dle_info { 3908 const struct rtw89_rsvd_quota *rsvd_qt; 3909 enum rtw89_qta_mode qta_mode; 3910 u16 ple_pg_size; 3911 u16 ple_free_pg; 3912 u16 c0_rx_qta; 3913 u16 c1_rx_qta; 3914 }; 3915 3916 enum rtw89_host_rpr_mode { 3917 RTW89_RPR_MODE_POH = 0, 3918 RTW89_RPR_MODE_STF 3919 }; 3920 3921 #define RTW89_COMPLETION_BUF_SIZE 40 3922 #define RTW89_WAIT_COND_IDLE UINT_MAX 3923 3924 struct rtw89_completion_data { 3925 bool err; 3926 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3927 }; 3928 3929 struct rtw89_wait_info { 3930 atomic_t cond; 3931 struct completion completion; 3932 struct rtw89_completion_data data; 3933 }; 3934 3935 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3936 3937 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3938 { 3939 init_completion(&wait->completion); 3940 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3941 } 3942 3943 struct rtw89_mac_info { 3944 struct rtw89_dle_info dle_info; 3945 struct rtw89_hfc_param hfc_param; 3946 enum rtw89_qta_mode qta_mode; 3947 u8 rpwm_seq_num; 3948 u8 cpwm_seq_num; 3949 3950 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 3951 struct rtw89_wait_info fw_ofld_wait; 3952 }; 3953 3954 enum rtw89_fwdl_check_type { 3955 RTW89_FWDL_CHECK_FREERTOS_DONE, 3956 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 3957 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 3958 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 3959 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 3960 }; 3961 3962 enum rtw89_fw_type { 3963 RTW89_FW_NORMAL = 1, 3964 RTW89_FW_WOWLAN = 3, 3965 RTW89_FW_NORMAL_CE = 5, 3966 RTW89_FW_BBMCU0 = 64, 3967 RTW89_FW_BBMCU1 = 65, 3968 RTW89_FW_LOGFMT = 255, 3969 }; 3970 3971 enum rtw89_fw_feature { 3972 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3973 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3974 RTW89_FW_FEATURE_TX_WAKE, 3975 RTW89_FW_FEATURE_CRASH_TRIGGER, 3976 RTW89_FW_FEATURE_NO_PACKET_DROP, 3977 RTW89_FW_FEATURE_NO_DEEP_PS, 3978 RTW89_FW_FEATURE_NO_LPS_PG, 3979 RTW89_FW_FEATURE_BEACON_FILTER, 3980 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 3981 }; 3982 3983 struct rtw89_fw_suit { 3984 enum rtw89_fw_type type; 3985 const u8 *data; 3986 u32 size; 3987 u8 major_ver; 3988 u8 minor_ver; 3989 u8 sub_ver; 3990 u8 sub_idex; 3991 u16 build_year; 3992 u16 build_mon; 3993 u16 build_date; 3994 u16 build_hour; 3995 u16 build_min; 3996 u8 cmd_ver; 3997 u8 hdr_ver; 3998 u32 commitid; 3999 }; 4000 4001 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4002 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4003 #define RTW89_FW_SUIT_VER_CODE(s) \ 4004 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4005 4006 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4007 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4008 (mfw_hdr)->ver.minor, \ 4009 (mfw_hdr)->ver.sub, \ 4010 (mfw_hdr)->ver.idx) 4011 4012 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4013 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4014 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4015 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4016 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4017 4018 struct rtw89_fw_req_info { 4019 const struct firmware *firmware; 4020 struct completion completion; 4021 }; 4022 4023 struct rtw89_fw_log { 4024 struct rtw89_fw_suit suit; 4025 bool enable; 4026 u32 last_fmt_id; 4027 u32 fmt_count; 4028 const __le32 *fmt_ids; 4029 const char *(*fmts)[]; 4030 }; 4031 4032 struct rtw89_fw_elm_info { 4033 struct rtw89_phy_table *bb_tbl; 4034 struct rtw89_phy_table *bb_gain; 4035 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4036 struct rtw89_phy_table *rf_nctl; 4037 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4038 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4039 }; 4040 4041 enum rtw89_fw_mss_dev_type { 4042 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4043 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4044 }; 4045 4046 struct rtw89_fw_secure { 4047 bool secure_boot; 4048 u32 sb_sel_mgn; 4049 u8 mss_dev_type; 4050 u8 mss_cust_idx; 4051 u8 mss_key_num; 4052 }; 4053 4054 struct rtw89_fw_info { 4055 struct rtw89_fw_req_info req; 4056 int fw_format; 4057 u8 h2c_seq; 4058 u8 rec_seq; 4059 u8 h2c_counter; 4060 u8 c2h_counter; 4061 struct rtw89_fw_suit normal; 4062 struct rtw89_fw_suit wowlan; 4063 struct rtw89_fw_suit bbmcu0; 4064 struct rtw89_fw_suit bbmcu1; 4065 struct rtw89_fw_log log; 4066 u32 feature_map; 4067 struct rtw89_fw_elm_info elm_info; 4068 struct rtw89_fw_secure sec; 4069 }; 4070 4071 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4072 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4073 4074 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4075 ((_fw)->feature_map |= BIT(_fw_feature)) 4076 4077 struct rtw89_cam_info { 4078 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4079 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4080 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4081 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4082 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4083 }; 4084 4085 enum rtw89_sar_sources { 4086 RTW89_SAR_SOURCE_NONE, 4087 RTW89_SAR_SOURCE_COMMON, 4088 4089 RTW89_SAR_SOURCE_NR, 4090 }; 4091 4092 enum rtw89_sar_subband { 4093 RTW89_SAR_2GHZ_SUBBAND, 4094 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4095 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4096 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4097 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4098 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4099 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4100 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4101 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4102 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4103 4104 RTW89_SAR_SUBBAND_NR, 4105 }; 4106 4107 struct rtw89_sar_cfg_common { 4108 bool set[RTW89_SAR_SUBBAND_NR]; 4109 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4110 }; 4111 4112 struct rtw89_sar_info { 4113 /* used to decide how to acces SAR cfg union */ 4114 enum rtw89_sar_sources src; 4115 4116 /* reserved for different knids of SAR cfg struct. 4117 * supposed that a single cfg struct cannot handle various SAR sources. 4118 */ 4119 union { 4120 struct rtw89_sar_cfg_common cfg_common; 4121 }; 4122 }; 4123 4124 enum rtw89_tas_state { 4125 RTW89_TAS_STATE_DPR_OFF, 4126 RTW89_TAS_STATE_DPR_ON, 4127 RTW89_TAS_STATE_DPR_FORBID, 4128 }; 4129 4130 #define RTW89_TAS_MAX_WINDOW 50 4131 struct rtw89_tas_info { 4132 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4133 s32 total_txpwr; 4134 u8 cur_idx; 4135 s8 dpr_gap; 4136 s8 delta; 4137 enum rtw89_tas_state state; 4138 bool enable; 4139 }; 4140 4141 struct rtw89_chanctx_cfg { 4142 enum rtw89_sub_entity_idx idx; 4143 int ref_count; 4144 }; 4145 4146 enum rtw89_chanctx_changes { 4147 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4148 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4149 RTW89_CHANCTX_P2P_PS_CHANGE, 4150 RTW89_CHANCTX_BT_SLOT_CHANGE, 4151 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4152 4153 NUM_OF_RTW89_CHANCTX_CHANGES, 4154 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4155 }; 4156 4157 enum rtw89_entity_mode { 4158 RTW89_ENTITY_MODE_SCC, 4159 RTW89_ENTITY_MODE_MCC_PREPARE, 4160 RTW89_ENTITY_MODE_MCC, 4161 4162 NUM_OF_RTW89_ENTITY_MODE, 4163 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4164 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4165 }; 4166 4167 struct rtw89_sub_entity { 4168 struct cfg80211_chan_def chandef; 4169 struct rtw89_chan chan; 4170 struct rtw89_chan_rcd rcd; 4171 4172 /* only assigned when running with chanctx_ops */ 4173 struct rtw89_chanctx_cfg *cfg; 4174 }; 4175 4176 struct rtw89_edcca_bak { 4177 u8 a; 4178 u8 p; 4179 u8 ppdu; 4180 u8 th_old; 4181 }; 4182 4183 enum rtw89_dm_type { 4184 RTW89_DM_DYNAMIC_EDCCA, 4185 }; 4186 4187 struct rtw89_hal { 4188 u32 rx_fltr; 4189 u8 cv; 4190 u8 acv; 4191 u32 antenna_tx; 4192 u32 antenna_rx; 4193 u8 tx_nss; 4194 u8 rx_nss; 4195 bool tx_path_diversity; 4196 bool ant_diversity; 4197 bool ant_diversity_fixed; 4198 bool support_cckpd; 4199 bool support_igi; 4200 atomic_t roc_entity_idx; 4201 4202 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4203 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4204 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4205 struct cfg80211_chan_def roc_chandef; 4206 4207 bool entity_active; 4208 bool entity_pause; 4209 enum rtw89_entity_mode entity_mode; 4210 4211 struct rtw89_edcca_bak edcca_bak; 4212 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4213 }; 4214 4215 #define RTW89_MAX_MAC_ID_NUM 128 4216 #define RTW89_MAX_PKT_OFLD_NUM 255 4217 4218 enum rtw89_flags { 4219 RTW89_FLAG_POWERON, 4220 RTW89_FLAG_DMAC_FUNC, 4221 RTW89_FLAG_CMAC0_FUNC, 4222 RTW89_FLAG_CMAC1_FUNC, 4223 RTW89_FLAG_FW_RDY, 4224 RTW89_FLAG_RUNNING, 4225 RTW89_FLAG_PROBE_DONE, 4226 RTW89_FLAG_BFEE_MON, 4227 RTW89_FLAG_BFEE_EN, 4228 RTW89_FLAG_BFEE_TIMER_KEEP, 4229 RTW89_FLAG_NAPI_RUNNING, 4230 RTW89_FLAG_LEISURE_PS, 4231 RTW89_FLAG_LOW_POWER_MODE, 4232 RTW89_FLAG_INACTIVE_PS, 4233 RTW89_FLAG_CRASH_SIMULATING, 4234 RTW89_FLAG_SER_HANDLING, 4235 RTW89_FLAG_WOWLAN, 4236 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4237 RTW89_FLAG_CHANGING_INTERFACE, 4238 4239 NUM_OF_RTW89_FLAGS, 4240 }; 4241 4242 enum rtw89_pkt_drop_sel { 4243 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4244 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4245 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4246 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4247 RTW89_PKT_DROP_SEL_MACID_ALL, 4248 RTW89_PKT_DROP_SEL_MG0_ONCE, 4249 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4250 RTW89_PKT_DROP_SEL_HIQ_PORT, 4251 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4252 RTW89_PKT_DROP_SEL_BAND, 4253 RTW89_PKT_DROP_SEL_BAND_ONCE, 4254 RTW89_PKT_DROP_SEL_REL_MACID, 4255 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4256 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4257 }; 4258 4259 struct rtw89_pkt_drop_params { 4260 enum rtw89_pkt_drop_sel sel; 4261 enum rtw89_mac_idx mac_band; 4262 u8 macid; 4263 u8 port; 4264 u8 mbssid; 4265 bool tf_trs; 4266 u32 macid_band_sel[4]; 4267 }; 4268 4269 struct rtw89_pkt_stat { 4270 u16 beacon_nr; 4271 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4272 }; 4273 4274 DECLARE_EWMA(thermal, 4, 4); 4275 4276 struct rtw89_phy_stat { 4277 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4278 struct rtw89_pkt_stat cur_pkt_stat; 4279 struct rtw89_pkt_stat last_pkt_stat; 4280 }; 4281 4282 enum rtw89_rfk_report_state { 4283 RTW89_RFK_STATE_START = 0x0, 4284 RTW89_RFK_STATE_OK = 0x1, 4285 RTW89_RFK_STATE_FAIL = 0x2, 4286 RTW89_RFK_STATE_TIMEOUT = 0x3, 4287 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4288 }; 4289 4290 struct rtw89_rfk_wait_info { 4291 struct completion completion; 4292 ktime_t start_time; 4293 enum rtw89_rfk_report_state state; 4294 u8 version; 4295 }; 4296 4297 #define RTW89_DACK_PATH_NR 2 4298 #define RTW89_DACK_IDX_NR 2 4299 #define RTW89_DACK_MSBK_NR 16 4300 struct rtw89_dack_info { 4301 bool dack_done; 4302 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4303 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4304 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4305 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4306 u32 dack_cnt; 4307 bool addck_timeout[RTW89_DACK_PATH_NR]; 4308 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4309 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4310 }; 4311 4312 #define RTW89_RFK_CHS_NR 3 4313 4314 struct rtw89_rfk_mcc_info { 4315 u8 ch[RTW89_RFK_CHS_NR]; 4316 u8 band[RTW89_RFK_CHS_NR]; 4317 u8 bw[RTW89_RFK_CHS_NR]; 4318 u8 table_idx; 4319 }; 4320 4321 #define RTW89_IQK_CHS_NR 2 4322 #define RTW89_IQK_PATH_NR 4 4323 4324 struct rtw89_lck_info { 4325 u8 thermal[RF_PATH_MAX]; 4326 }; 4327 4328 struct rtw89_rx_dck_info { 4329 u8 thermal[RF_PATH_MAX]; 4330 }; 4331 4332 struct rtw89_iqk_info { 4333 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4334 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4335 bool lok_fail[RTW89_IQK_PATH_NR]; 4336 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4337 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4338 u32 iqk_fail_cnt; 4339 bool is_iqk_init; 4340 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4341 u8 iqk_band[RTW89_IQK_PATH_NR]; 4342 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4343 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4344 u8 iqk_times; 4345 u8 version; 4346 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4347 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4348 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4349 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4350 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4351 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4352 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4353 bool is_nbiqk; 4354 bool iqk_fft_en; 4355 bool iqk_xym_en; 4356 bool iqk_sram_en; 4357 bool iqk_cfir_en; 4358 u32 syn1to2; 4359 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4360 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4361 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4362 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4363 }; 4364 4365 #define RTW89_DPK_RF_PATH 2 4366 #define RTW89_DPK_AVG_THERMAL_NUM 8 4367 #define RTW89_DPK_BKUP_NUM 2 4368 struct rtw89_dpk_bkup_para { 4369 enum rtw89_band band; 4370 enum rtw89_bandwidth bw; 4371 u8 ch; 4372 bool path_ok; 4373 u8 mdpd_en; 4374 u8 txagc_dpk; 4375 u8 ther_dpk; 4376 u8 gs; 4377 u16 pwsf; 4378 }; 4379 4380 struct rtw89_dpk_info { 4381 bool is_dpk_enable; 4382 bool is_dpk_reload_en; 4383 u8 dpk_gs[RTW89_PHY_MAX]; 4384 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4385 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4386 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4387 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4388 u8 cur_idx[RTW89_DPK_RF_PATH]; 4389 u8 cur_k_set; 4390 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4391 }; 4392 4393 struct rtw89_fem_info { 4394 bool elna_2g; 4395 bool elna_5g; 4396 bool epa_2g; 4397 bool epa_5g; 4398 bool epa_6g; 4399 }; 4400 4401 struct rtw89_phy_ch_info { 4402 u8 rssi_min; 4403 u16 rssi_min_macid; 4404 u8 pre_rssi_min; 4405 u8 rssi_max; 4406 u16 rssi_max_macid; 4407 u8 rxsc_160; 4408 u8 rxsc_80; 4409 u8 rxsc_40; 4410 u8 rxsc_20; 4411 u8 rxsc_l; 4412 u8 is_noisy; 4413 }; 4414 4415 struct rtw89_agc_gaincode_set { 4416 u8 lna_idx; 4417 u8 tia_idx; 4418 u8 rxb_idx; 4419 }; 4420 4421 #define IGI_RSSI_TH_NUM 5 4422 #define FA_TH_NUM 4 4423 #define LNA_GAIN_NUM 7 4424 #define TIA_GAIN_NUM 2 4425 struct rtw89_dig_info { 4426 struct rtw89_agc_gaincode_set cur_gaincode; 4427 bool force_gaincode_idx_en; 4428 struct rtw89_agc_gaincode_set force_gaincode; 4429 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4430 u16 fa_th[FA_TH_NUM]; 4431 u8 igi_rssi; 4432 u8 igi_fa_rssi; 4433 u8 fa_rssi_ofst; 4434 u8 dyn_igi_max; 4435 u8 dyn_igi_min; 4436 bool dyn_pd_th_en; 4437 u8 dyn_pd_th_max; 4438 u8 pd_low_th_ofst; 4439 u8 ib_pbk; 4440 s8 ib_pkpwr; 4441 s8 lna_gain_a[LNA_GAIN_NUM]; 4442 s8 lna_gain_g[LNA_GAIN_NUM]; 4443 s8 *lna_gain; 4444 s8 tia_gain_a[TIA_GAIN_NUM]; 4445 s8 tia_gain_g[TIA_GAIN_NUM]; 4446 s8 *tia_gain; 4447 bool is_linked_pre; 4448 bool bypass_dig; 4449 }; 4450 4451 enum rtw89_multi_cfo_mode { 4452 RTW89_PKT_BASED_AVG_MODE = 0, 4453 RTW89_ENTRY_BASED_AVG_MODE = 1, 4454 RTW89_TP_BASED_AVG_MODE = 2, 4455 }; 4456 4457 enum rtw89_phy_cfo_status { 4458 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4459 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4460 RTW89_PHY_DCFO_STATE_HOLD = 2, 4461 RTW89_PHY_DCFO_STATE_MAX 4462 }; 4463 4464 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4465 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4466 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4467 }; 4468 4469 struct rtw89_cfo_tracking_info { 4470 u16 cfo_timer_ms; 4471 bool cfo_trig_by_timer_en; 4472 enum rtw89_phy_cfo_status phy_cfo_status; 4473 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4474 u8 phy_cfo_trk_cnt; 4475 bool is_adjust; 4476 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4477 bool apply_compensation; 4478 u8 crystal_cap; 4479 u8 crystal_cap_default; 4480 u8 def_x_cap; 4481 s8 x_cap_ofst; 4482 u32 sta_cfo_tolerance; 4483 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4484 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4485 s32 cfo_avg_pre; 4486 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4487 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4488 s32 dcfo_avg; 4489 s32 dcfo_avg_pre; 4490 u32 packet_count; 4491 u32 packet_count_pre; 4492 s32 residual_cfo_acc; 4493 u8 phy_cfotrk_state; 4494 u8 phy_cfotrk_cnt; 4495 bool divergence_lock_en; 4496 u8 x_cap_lb; 4497 u8 x_cap_ub; 4498 u8 lock_cnt; 4499 }; 4500 4501 enum rtw89_tssi_mode { 4502 RTW89_TSSI_NORMAL = 0, 4503 RTW89_TSSI_SCAN = 1, 4504 }; 4505 4506 enum rtw89_tssi_alimk_band { 4507 TSSI_ALIMK_2G = 0, 4508 TSSI_ALIMK_5GL, 4509 TSSI_ALIMK_5GM, 4510 TSSI_ALIMK_5GH, 4511 TSSI_ALIMK_MAX 4512 }; 4513 4514 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4515 #define TSSI_TRIM_CH_GROUP_NUM 8 4516 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4517 4518 #define TSSI_CCK_CH_GROUP_NUM 6 4519 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4520 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4521 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4522 #define TSSI_MCS_CH_GROUP_NUM \ 4523 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4524 #define TSSI_MAX_CH_NUM 67 4525 #define TSSI_ALIMK_VALUE_NUM 8 4526 4527 struct rtw89_tssi_info { 4528 u8 thermal[RF_PATH_MAX]; 4529 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4530 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4531 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4532 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4533 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4534 s8 extra_ofst[RF_PATH_MAX]; 4535 bool tssi_tracking_check[RF_PATH_MAX]; 4536 u8 default_txagc_offset[RF_PATH_MAX]; 4537 u32 base_thermal[RF_PATH_MAX]; 4538 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4539 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4540 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4541 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4542 u32 tssi_alimk_time; 4543 }; 4544 4545 struct rtw89_power_trim_info { 4546 bool pg_thermal_trim; 4547 bool pg_pa_bias_trim; 4548 u8 thermal_trim[RF_PATH_MAX]; 4549 u8 pa_bias_trim[RF_PATH_MAX]; 4550 u8 pad_bias_trim[RF_PATH_MAX]; 4551 }; 4552 4553 struct rtw89_regd { 4554 char alpha2[3]; 4555 u8 txpwr_regd[RTW89_BAND_NUM]; 4556 }; 4557 4558 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4559 4560 struct rtw89_regulatory_info { 4561 const struct rtw89_regd *regd; 4562 enum rtw89_reg_6ghz_power reg_6ghz_power; 4563 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4564 }; 4565 4566 enum rtw89_ifs_clm_application { 4567 RTW89_IFS_CLM_INIT = 0, 4568 RTW89_IFS_CLM_BACKGROUND = 1, 4569 RTW89_IFS_CLM_ACS = 2, 4570 RTW89_IFS_CLM_DIG = 3, 4571 RTW89_IFS_CLM_TDMA_DIG = 4, 4572 RTW89_IFS_CLM_DBG = 5, 4573 RTW89_IFS_CLM_DBG_MANUAL = 6 4574 }; 4575 4576 enum rtw89_env_racing_lv { 4577 RTW89_RAC_RELEASE = 0, 4578 RTW89_RAC_LV_1 = 1, 4579 RTW89_RAC_LV_2 = 2, 4580 RTW89_RAC_LV_3 = 3, 4581 RTW89_RAC_LV_4 = 4, 4582 RTW89_RAC_MAX_NUM = 5 4583 }; 4584 4585 struct rtw89_ccx_para_info { 4586 enum rtw89_env_racing_lv rac_lv; 4587 u16 mntr_time; 4588 u8 nhm_manual_th_ofst; 4589 u8 nhm_manual_th0; 4590 enum rtw89_ifs_clm_application ifs_clm_app; 4591 u32 ifs_clm_manual_th_times; 4592 u32 ifs_clm_manual_th0; 4593 u8 fahm_manual_th_ofst; 4594 u8 fahm_manual_th0; 4595 u8 fahm_numer_opt; 4596 u8 fahm_denom_opt; 4597 }; 4598 4599 enum rtw89_ccx_edcca_opt_sc_idx { 4600 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4601 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4602 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4603 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4604 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4605 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4606 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4607 RTW89_CCX_EDCCA_SEG1_S3 = 7 4608 }; 4609 4610 enum rtw89_ccx_edcca_opt_bw_idx { 4611 RTW89_CCX_EDCCA_BW20_0 = 0, 4612 RTW89_CCX_EDCCA_BW20_1 = 1, 4613 RTW89_CCX_EDCCA_BW20_2 = 2, 4614 RTW89_CCX_EDCCA_BW20_3 = 3, 4615 RTW89_CCX_EDCCA_BW20_4 = 4, 4616 RTW89_CCX_EDCCA_BW20_5 = 5, 4617 RTW89_CCX_EDCCA_BW20_6 = 6, 4618 RTW89_CCX_EDCCA_BW20_7 = 7 4619 }; 4620 4621 #define RTW89_NHM_TH_NUM 11 4622 #define RTW89_FAHM_TH_NUM 11 4623 #define RTW89_NHM_RPT_NUM 12 4624 #define RTW89_FAHM_RPT_NUM 12 4625 #define RTW89_IFS_CLM_NUM 4 4626 struct rtw89_env_monitor_info { 4627 u8 ccx_watchdog_result; 4628 bool ccx_ongoing; 4629 u8 ccx_rac_lv; 4630 bool ccx_manual_ctrl; 4631 u16 ifs_clm_mntr_time; 4632 enum rtw89_ifs_clm_application ifs_clm_app; 4633 u16 ccx_period; 4634 u8 ccx_unit_idx; 4635 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4636 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4637 u16 ifs_clm_tx; 4638 u16 ifs_clm_edcca_excl_cca; 4639 u16 ifs_clm_ofdmfa; 4640 u16 ifs_clm_ofdmcca_excl_fa; 4641 u16 ifs_clm_cckfa; 4642 u16 ifs_clm_cckcca_excl_fa; 4643 u16 ifs_clm_total_ifs; 4644 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4645 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4646 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4647 u8 ifs_clm_tx_ratio; 4648 u8 ifs_clm_edcca_excl_cca_ratio; 4649 u8 ifs_clm_cck_fa_ratio; 4650 u8 ifs_clm_ofdm_fa_ratio; 4651 u8 ifs_clm_cck_cca_excl_fa_ratio; 4652 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4653 u16 ifs_clm_cck_fa_permil; 4654 u16 ifs_clm_ofdm_fa_permil; 4655 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4656 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4657 }; 4658 4659 enum rtw89_ser_rcvy_step { 4660 RTW89_SER_DRV_STOP_TX, 4661 RTW89_SER_DRV_STOP_RX, 4662 RTW89_SER_DRV_STOP_RUN, 4663 RTW89_SER_HAL_STOP_DMA, 4664 RTW89_SER_SUPPRESS_LOG, 4665 RTW89_NUM_OF_SER_FLAGS 4666 }; 4667 4668 struct rtw89_ser { 4669 u8 state; 4670 u8 alarm_event; 4671 bool prehandle_l1; 4672 4673 struct work_struct ser_hdl_work; 4674 struct delayed_work ser_alarm_work; 4675 const struct state_ent *st_tbl; 4676 const struct event_ent *ev_tbl; 4677 struct list_head msg_q; 4678 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4679 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4680 }; 4681 4682 enum rtw89_mac_ax_ps_mode { 4683 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4684 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4685 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4686 RTW89_MAC_AX_PS_MODE_MAX = 3, 4687 }; 4688 4689 enum rtw89_last_rpwm_mode { 4690 RTW89_LAST_RPWM_PS = 0x0, 4691 RTW89_LAST_RPWM_ACTIVE = 0x6, 4692 }; 4693 4694 struct rtw89_lps_parm { 4695 u8 macid; 4696 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4697 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4698 }; 4699 4700 struct rtw89_ppdu_sts_info { 4701 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4702 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4703 }; 4704 4705 struct rtw89_early_h2c { 4706 struct list_head list; 4707 u8 *h2c; 4708 u16 h2c_len; 4709 }; 4710 4711 struct rtw89_hw_scan_info { 4712 struct ieee80211_vif *scanning_vif; 4713 struct list_head pkt_list[NUM_NL80211_BANDS]; 4714 struct rtw89_chan op_chan; 4715 bool abort; 4716 u32 last_chan_idx; 4717 }; 4718 4719 enum rtw89_phy_bb_gain_band { 4720 RTW89_BB_GAIN_BAND_2G = 0, 4721 RTW89_BB_GAIN_BAND_5G_L = 1, 4722 RTW89_BB_GAIN_BAND_5G_M = 2, 4723 RTW89_BB_GAIN_BAND_5G_H = 3, 4724 RTW89_BB_GAIN_BAND_6G_L = 4, 4725 RTW89_BB_GAIN_BAND_6G_M = 5, 4726 RTW89_BB_GAIN_BAND_6G_H = 6, 4727 RTW89_BB_GAIN_BAND_6G_UH = 7, 4728 4729 RTW89_BB_GAIN_BAND_NR, 4730 }; 4731 4732 enum rtw89_phy_gain_band_be { 4733 RTW89_BB_GAIN_BAND_2G_BE = 0, 4734 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 4735 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 4736 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 4737 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 4738 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 4739 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 4740 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 4741 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 4742 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 4743 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 4744 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 4745 4746 RTW89_BB_GAIN_BAND_NR_BE, 4747 }; 4748 4749 enum rtw89_phy_bb_bw_be { 4750 RTW89_BB_BW_20_40 = 0, 4751 RTW89_BB_BW_80_160_320 = 1, 4752 4753 RTW89_BB_BW_NR_BE, 4754 }; 4755 4756 enum rtw89_bw20_sc { 4757 RTW89_BW20_SC_20M = 1, 4758 RTW89_BW20_SC_40M = 2, 4759 RTW89_BW20_SC_80M = 4, 4760 RTW89_BW20_SC_160M = 8, 4761 RTW89_BW20_SC_320M = 16, 4762 }; 4763 4764 enum rtw89_cmac_table_bw { 4765 RTW89_CMAC_BW_20M = 0, 4766 RTW89_CMAC_BW_40M = 1, 4767 RTW89_CMAC_BW_80M = 2, 4768 RTW89_CMAC_BW_160M = 3, 4769 RTW89_CMAC_BW_320M = 4, 4770 4771 RTW89_CMAC_BW_NR, 4772 }; 4773 4774 enum rtw89_phy_bb_rxsc_num { 4775 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4776 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4777 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4778 }; 4779 4780 struct rtw89_phy_bb_gain_info { 4781 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4782 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4783 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4784 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4785 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4786 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4787 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4788 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4789 [RTW89_BB_RXSC_NUM_40]; 4790 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4791 [RTW89_BB_RXSC_NUM_80]; 4792 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4793 [RTW89_BB_RXSC_NUM_160]; 4794 }; 4795 4796 struct rtw89_phy_bb_gain_info_be { 4797 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 4798 [LNA_GAIN_NUM]; 4799 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 4800 [TIA_GAIN_NUM]; 4801 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4802 [RF_PATH_MAX][LNA_GAIN_NUM]; 4803 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4804 [RF_PATH_MAX][LNA_GAIN_NUM]; 4805 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4806 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 4807 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4808 [RTW89_BW20_SC_20M]; 4809 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4810 [RTW89_BW20_SC_40M]; 4811 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4812 [RTW89_BW20_SC_80M]; 4813 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4814 [RTW89_BW20_SC_160M]; 4815 }; 4816 4817 struct rtw89_phy_efuse_gain { 4818 bool offset_valid; 4819 bool comp_valid; 4820 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4821 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4822 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4823 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4824 }; 4825 4826 #define RTW89_MAX_PATTERN_NUM 18 4827 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4828 #define RTW89_MAX_PATTERN_SIZE 128 4829 4830 struct rtw89_wow_cam_info { 4831 bool r_w; 4832 u8 idx; 4833 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4834 u16 crc; 4835 bool negative_pattern_match; 4836 bool skip_mac_hdr; 4837 bool uc; 4838 bool mc; 4839 bool bc; 4840 bool valid; 4841 }; 4842 4843 struct rtw89_wow_param { 4844 struct ieee80211_vif *wow_vif; 4845 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4846 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4847 u8 pattern_cnt; 4848 }; 4849 4850 struct rtw89_mcc_limit { 4851 bool enable; 4852 u16 max_tob; /* TU; max time offset behind */ 4853 u16 max_toa; /* TU; max time offset ahead */ 4854 u16 max_dur; /* TU */ 4855 }; 4856 4857 struct rtw89_mcc_policy { 4858 u8 c2h_rpt; 4859 u8 tx_null_early; 4860 u8 dis_tx_null; 4861 u8 in_curr_ch; 4862 u8 dis_sw_retry; 4863 u8 sw_retry_count; 4864 }; 4865 4866 struct rtw89_mcc_role { 4867 struct rtw89_vif *rtwvif; 4868 struct rtw89_mcc_policy policy; 4869 struct rtw89_mcc_limit limit; 4870 4871 /* only valid when running with FW MRC mechanism */ 4872 u8 slot_idx; 4873 4874 /* byte-array in LE order for FW */ 4875 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 4876 4877 u16 duration; /* TU */ 4878 u16 beacon_interval; /* TU */ 4879 bool is_2ghz; 4880 bool is_go; 4881 bool is_gc; 4882 }; 4883 4884 struct rtw89_mcc_bt_role { 4885 u16 duration; /* TU */ 4886 }; 4887 4888 struct rtw89_mcc_courtesy { 4889 bool enable; 4890 u8 slot_num; 4891 u8 macid_src; 4892 u8 macid_tgt; 4893 }; 4894 4895 enum rtw89_mcc_plan { 4896 RTW89_MCC_PLAN_TAIL_BT, 4897 RTW89_MCC_PLAN_MID_BT, 4898 RTW89_MCC_PLAN_NO_BT, 4899 4900 NUM_OF_RTW89_MCC_PLAN, 4901 }; 4902 4903 struct rtw89_mcc_pattern { 4904 s16 tob_ref; /* TU; time offset behind of reference role */ 4905 s16 toa_ref; /* TU; time offset ahead of reference role */ 4906 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 4907 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 4908 4909 enum rtw89_mcc_plan plan; 4910 struct rtw89_mcc_courtesy courtesy; 4911 }; 4912 4913 struct rtw89_mcc_sync { 4914 bool enable; 4915 u16 offset; /* TU */ 4916 u8 macid_src; 4917 u8 band_src; 4918 u8 port_src; 4919 u8 macid_tgt; 4920 u8 band_tgt; 4921 u8 port_tgt; 4922 }; 4923 4924 struct rtw89_mcc_config { 4925 struct rtw89_mcc_pattern pattern; 4926 struct rtw89_mcc_sync sync; 4927 u64 start_tsf; 4928 u16 mcc_interval; /* TU */ 4929 u16 beacon_offset; /* TU */ 4930 }; 4931 4932 enum rtw89_mcc_mode { 4933 RTW89_MCC_MODE_GO_STA, 4934 RTW89_MCC_MODE_GC_STA, 4935 }; 4936 4937 struct rtw89_mcc_info { 4938 struct rtw89_wait_info wait; 4939 4940 u8 group; 4941 enum rtw89_mcc_mode mode; 4942 struct rtw89_mcc_role role_ref; /* reference role */ 4943 struct rtw89_mcc_role role_aux; /* auxiliary role */ 4944 struct rtw89_mcc_bt_role bt_role; 4945 struct rtw89_mcc_config config; 4946 }; 4947 4948 struct rtw89_dev { 4949 struct ieee80211_hw *hw; 4950 struct device *dev; 4951 const struct ieee80211_ops *ops; 4952 4953 bool dbcc_en; 4954 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 4955 struct rtw89_hw_scan_info scan_info; 4956 const struct rtw89_chip_info *chip; 4957 const struct rtw89_pci_info *pci_info; 4958 const struct rtw89_rfe_parms *rfe_parms; 4959 struct rtw89_hal hal; 4960 struct rtw89_mcc_info mcc; 4961 struct rtw89_mac_info mac; 4962 struct rtw89_fw_info fw; 4963 struct rtw89_hci_info hci; 4964 struct rtw89_efuse efuse; 4965 struct rtw89_traffic_stats stats; 4966 struct rtw89_rfe_data *rfe_data; 4967 4968 /* ensures exclusive access from mac80211 callbacks */ 4969 struct mutex mutex; 4970 struct list_head rtwvifs_list; 4971 /* used to protect rf read write */ 4972 struct mutex rf_mutex; 4973 struct workqueue_struct *txq_wq; 4974 struct work_struct txq_work; 4975 struct delayed_work txq_reinvoke_work; 4976 /* used to protect ba_list and forbid_ba_list */ 4977 spinlock_t ba_lock; 4978 /* txqs to setup ba session */ 4979 struct list_head ba_list; 4980 /* txqs to forbid ba session */ 4981 struct list_head forbid_ba_list; 4982 struct work_struct ba_work; 4983 /* used to protect rpwm */ 4984 spinlock_t rpwm_lock; 4985 4986 struct rtw89_cam_info cam_info; 4987 4988 struct sk_buff_head c2h_queue; 4989 struct work_struct c2h_work; 4990 struct work_struct ips_work; 4991 struct work_struct load_firmware_work; 4992 struct work_struct cancel_6ghz_probe_work; 4993 4994 struct list_head early_h2c_list; 4995 4996 struct rtw89_ser ser; 4997 4998 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4999 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5000 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5001 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5002 5003 struct rtw89_phy_stat phystat; 5004 struct rtw89_rfk_wait_info rfk_wait; 5005 struct rtw89_dack_info dack; 5006 struct rtw89_iqk_info iqk; 5007 struct rtw89_dpk_info dpk; 5008 struct rtw89_rfk_mcc_info rfk_mcc; 5009 struct rtw89_lck_info lck; 5010 struct rtw89_rx_dck_info rx_dck; 5011 bool is_tssi_mode[RF_PATH_MAX]; 5012 bool is_bt_iqk_timeout; 5013 5014 struct rtw89_fem_info fem; 5015 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5016 struct rtw89_tssi_info tssi; 5017 struct rtw89_power_trim_info pwr_trim; 5018 5019 struct rtw89_cfo_tracking_info cfo_tracking; 5020 struct rtw89_env_monitor_info env_monitor; 5021 struct rtw89_dig_info dig; 5022 struct rtw89_phy_ch_info ch_info; 5023 union { 5024 struct rtw89_phy_bb_gain_info ax; 5025 struct rtw89_phy_bb_gain_info_be be; 5026 } bb_gain; 5027 struct rtw89_phy_efuse_gain efuse_gain; 5028 struct rtw89_phy_ul_tb_info ul_tb_info; 5029 struct rtw89_antdiv_info antdiv; 5030 5031 struct delayed_work track_work; 5032 struct delayed_work chanctx_work; 5033 struct delayed_work coex_act1_work; 5034 struct delayed_work coex_bt_devinfo_work; 5035 struct delayed_work coex_rfk_chk_work; 5036 struct delayed_work cfo_track_work; 5037 struct delayed_work forbid_ba_work; 5038 struct delayed_work roc_work; 5039 struct delayed_work antdiv_work; 5040 struct rtw89_ppdu_sts_info ppdu_sts; 5041 u8 total_sta_assoc; 5042 bool scanning; 5043 5044 struct rtw89_regulatory_info regulatory; 5045 struct rtw89_sar_info sar; 5046 struct rtw89_tas_info tas; 5047 5048 struct rtw89_btc btc; 5049 enum rtw89_ps_mode ps_mode; 5050 bool lps_enabled; 5051 5052 struct rtw89_wow_param wow; 5053 5054 /* napi structure */ 5055 struct net_device netdev; 5056 struct napi_struct napi; 5057 int napi_budget_countdown; 5058 5059 /* HCI related data, keep last */ 5060 u8 priv[] __aligned(sizeof(void *)); 5061 }; 5062 5063 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5064 struct rtw89_core_tx_request *tx_req) 5065 { 5066 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5067 } 5068 5069 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5070 { 5071 rtwdev->hci.ops->reset(rtwdev); 5072 } 5073 5074 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5075 { 5076 return rtwdev->hci.ops->start(rtwdev); 5077 } 5078 5079 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5080 { 5081 rtwdev->hci.ops->stop(rtwdev); 5082 } 5083 5084 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5085 { 5086 return rtwdev->hci.ops->deinit(rtwdev); 5087 } 5088 5089 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5090 { 5091 rtwdev->hci.ops->pause(rtwdev, pause); 5092 } 5093 5094 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5095 { 5096 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5097 } 5098 5099 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5100 { 5101 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5102 } 5103 5104 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5105 { 5106 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5107 } 5108 5109 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5110 { 5111 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5112 } 5113 5114 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5115 { 5116 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5117 } 5118 5119 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5120 bool drop) 5121 { 5122 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5123 return; 5124 5125 if (rtwdev->hci.ops->flush_queues) 5126 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5127 } 5128 5129 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5130 { 5131 if (rtwdev->hci.ops->recovery_start) 5132 rtwdev->hci.ops->recovery_start(rtwdev); 5133 } 5134 5135 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5136 { 5137 if (rtwdev->hci.ops->recovery_complete) 5138 rtwdev->hci.ops->recovery_complete(rtwdev); 5139 } 5140 5141 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5142 { 5143 if (rtwdev->hci.ops->enable_intr) 5144 rtwdev->hci.ops->enable_intr(rtwdev); 5145 } 5146 5147 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5148 { 5149 if (rtwdev->hci.ops->disable_intr) 5150 rtwdev->hci.ops->disable_intr(rtwdev); 5151 } 5152 5153 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5154 { 5155 if (rtwdev->hci.ops->ctrl_txdma_ch) 5156 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5157 } 5158 5159 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5160 { 5161 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5162 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5163 } 5164 5165 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5166 { 5167 if (rtwdev->hci.ops->ctrl_trxhci) 5168 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5169 } 5170 5171 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 5172 { 5173 int ret = 0; 5174 5175 if (rtwdev->hci.ops->poll_txdma_ch) 5176 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 5177 return ret; 5178 } 5179 5180 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5181 { 5182 if (rtwdev->hci.ops->clr_idx_all) 5183 rtwdev->hci.ops->clr_idx_all(rtwdev); 5184 } 5185 5186 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 5187 { 5188 int ret = 0; 5189 5190 if (rtwdev->hci.ops->rst_bdram) 5191 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 5192 return ret; 5193 } 5194 5195 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 5196 { 5197 if (rtwdev->hci.ops->clear) 5198 rtwdev->hci.ops->clear(rtwdev, pdev); 5199 } 5200 5201 static inline 5202 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5203 { 5204 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5205 5206 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5207 } 5208 5209 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5210 { 5211 return rtwdev->hci.ops->read8(rtwdev, addr); 5212 } 5213 5214 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5215 { 5216 return rtwdev->hci.ops->read16(rtwdev, addr); 5217 } 5218 5219 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5220 { 5221 return rtwdev->hci.ops->read32(rtwdev, addr); 5222 } 5223 5224 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5225 { 5226 rtwdev->hci.ops->write8(rtwdev, addr, data); 5227 } 5228 5229 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5230 { 5231 rtwdev->hci.ops->write16(rtwdev, addr, data); 5232 } 5233 5234 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5235 { 5236 rtwdev->hci.ops->write32(rtwdev, addr, data); 5237 } 5238 5239 static inline void 5240 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5241 { 5242 u8 val; 5243 5244 val = rtw89_read8(rtwdev, addr); 5245 rtw89_write8(rtwdev, addr, val | bit); 5246 } 5247 5248 static inline void 5249 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5250 { 5251 u16 val; 5252 5253 val = rtw89_read16(rtwdev, addr); 5254 rtw89_write16(rtwdev, addr, val | bit); 5255 } 5256 5257 static inline void 5258 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5259 { 5260 u32 val; 5261 5262 val = rtw89_read32(rtwdev, addr); 5263 rtw89_write32(rtwdev, addr, val | bit); 5264 } 5265 5266 static inline void 5267 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5268 { 5269 u8 val; 5270 5271 val = rtw89_read8(rtwdev, addr); 5272 rtw89_write8(rtwdev, addr, val & ~bit); 5273 } 5274 5275 static inline void 5276 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5277 { 5278 u16 val; 5279 5280 val = rtw89_read16(rtwdev, addr); 5281 rtw89_write16(rtwdev, addr, val & ~bit); 5282 } 5283 5284 static inline void 5285 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5286 { 5287 u32 val; 5288 5289 val = rtw89_read32(rtwdev, addr); 5290 rtw89_write32(rtwdev, addr, val & ~bit); 5291 } 5292 5293 static inline u32 5294 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5295 { 5296 u32 shift = __ffs(mask); 5297 u32 orig; 5298 u32 ret; 5299 5300 orig = rtw89_read32(rtwdev, addr); 5301 ret = (orig & mask) >> shift; 5302 5303 return ret; 5304 } 5305 5306 static inline u16 5307 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5308 { 5309 u32 shift = __ffs(mask); 5310 u32 orig; 5311 u32 ret; 5312 5313 orig = rtw89_read16(rtwdev, addr); 5314 ret = (orig & mask) >> shift; 5315 5316 return ret; 5317 } 5318 5319 static inline u8 5320 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5321 { 5322 u32 shift = __ffs(mask); 5323 u32 orig; 5324 u32 ret; 5325 5326 orig = rtw89_read8(rtwdev, addr); 5327 ret = (orig & mask) >> shift; 5328 5329 return ret; 5330 } 5331 5332 static inline void 5333 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5334 { 5335 u32 shift = __ffs(mask); 5336 u32 orig; 5337 u32 set; 5338 5339 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5340 5341 orig = rtw89_read32(rtwdev, addr); 5342 set = (orig & ~mask) | ((data << shift) & mask); 5343 rtw89_write32(rtwdev, addr, set); 5344 } 5345 5346 static inline void 5347 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5348 { 5349 u32 shift; 5350 u16 orig, set; 5351 5352 mask &= 0xffff; 5353 shift = __ffs(mask); 5354 5355 orig = rtw89_read16(rtwdev, addr); 5356 set = (orig & ~mask) | ((data << shift) & mask); 5357 rtw89_write16(rtwdev, addr, set); 5358 } 5359 5360 static inline void 5361 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5362 { 5363 u32 shift; 5364 u8 orig, set; 5365 5366 mask &= 0xff; 5367 shift = __ffs(mask); 5368 5369 orig = rtw89_read8(rtwdev, addr); 5370 set = (orig & ~mask) | ((data << shift) & mask); 5371 rtw89_write8(rtwdev, addr, set); 5372 } 5373 5374 static inline u32 5375 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5376 u32 addr, u32 mask) 5377 { 5378 u32 val; 5379 5380 mutex_lock(&rtwdev->rf_mutex); 5381 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5382 mutex_unlock(&rtwdev->rf_mutex); 5383 5384 return val; 5385 } 5386 5387 static inline void 5388 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5389 u32 addr, u32 mask, u32 data) 5390 { 5391 mutex_lock(&rtwdev->rf_mutex); 5392 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5393 mutex_unlock(&rtwdev->rf_mutex); 5394 } 5395 5396 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5397 { 5398 void *p = rtwtxq; 5399 5400 return container_of(p, struct ieee80211_txq, drv_priv); 5401 } 5402 5403 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5404 struct ieee80211_txq *txq) 5405 { 5406 struct rtw89_txq *rtwtxq; 5407 5408 if (!txq) 5409 return; 5410 5411 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5412 INIT_LIST_HEAD(&rtwtxq->list); 5413 } 5414 5415 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5416 { 5417 void *p = rtwvif; 5418 5419 return container_of(p, struct ieee80211_vif, drv_priv); 5420 } 5421 5422 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5423 { 5424 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5425 } 5426 5427 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5428 { 5429 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5430 } 5431 5432 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5433 { 5434 void *p = rtwsta; 5435 5436 return container_of(p, struct ieee80211_sta, drv_priv); 5437 } 5438 5439 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5440 { 5441 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5442 } 5443 5444 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5445 { 5446 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5447 } 5448 5449 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5450 { 5451 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5452 return RATE_INFO_BW_160; 5453 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5454 return RATE_INFO_BW_80; 5455 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5456 return RATE_INFO_BW_40; 5457 else 5458 return RATE_INFO_BW_20; 5459 } 5460 5461 static inline 5462 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5463 { 5464 switch (hw_band) { 5465 default: 5466 case RTW89_BAND_2G: 5467 return NL80211_BAND_2GHZ; 5468 case RTW89_BAND_5G: 5469 return NL80211_BAND_5GHZ; 5470 case RTW89_BAND_6G: 5471 return NL80211_BAND_6GHZ; 5472 } 5473 } 5474 5475 static inline 5476 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5477 { 5478 switch (nl_band) { 5479 default: 5480 case NL80211_BAND_2GHZ: 5481 return RTW89_BAND_2G; 5482 case NL80211_BAND_5GHZ: 5483 return RTW89_BAND_5G; 5484 case NL80211_BAND_6GHZ: 5485 return RTW89_BAND_6G; 5486 } 5487 } 5488 5489 static inline 5490 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5491 { 5492 switch (width) { 5493 default: 5494 WARN(1, "Not support bandwidth %d\n", width); 5495 fallthrough; 5496 case NL80211_CHAN_WIDTH_20_NOHT: 5497 case NL80211_CHAN_WIDTH_20: 5498 return RTW89_CHANNEL_WIDTH_20; 5499 case NL80211_CHAN_WIDTH_40: 5500 return RTW89_CHANNEL_WIDTH_40; 5501 case NL80211_CHAN_WIDTH_80: 5502 return RTW89_CHANNEL_WIDTH_80; 5503 case NL80211_CHAN_WIDTH_160: 5504 return RTW89_CHANNEL_WIDTH_160; 5505 } 5506 } 5507 5508 static inline 5509 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5510 { 5511 switch (rua) { 5512 default: 5513 WARN(1, "Invalid RU allocation: %d\n", rua); 5514 fallthrough; 5515 case 0 ... 36: 5516 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5517 case 37 ... 52: 5518 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5519 case 53 ... 60: 5520 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5521 case 61 ... 64: 5522 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5523 case 65 ... 66: 5524 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5525 case 67: 5526 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5527 case 68: 5528 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5529 } 5530 } 5531 5532 static inline 5533 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5534 struct rtw89_sta *rtwsta) 5535 { 5536 if (rtwsta) { 5537 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5538 5539 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5540 return &rtwsta->addr_cam; 5541 } 5542 return &rtwvif->addr_cam; 5543 } 5544 5545 static inline 5546 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5547 struct rtw89_sta *rtwsta) 5548 { 5549 if (rtwsta) { 5550 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5551 5552 if (sta->tdls) 5553 return &rtwsta->bssid_cam; 5554 } 5555 return &rtwvif->bssid_cam; 5556 } 5557 5558 static inline 5559 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5560 struct rtw89_channel_help_params *p, 5561 const struct rtw89_chan *chan, 5562 enum rtw89_mac_idx mac_idx, 5563 enum rtw89_phy_idx phy_idx) 5564 { 5565 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5566 mac_idx, phy_idx); 5567 } 5568 5569 static inline 5570 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 5571 struct rtw89_channel_help_params *p, 5572 const struct rtw89_chan *chan, 5573 enum rtw89_mac_idx mac_idx, 5574 enum rtw89_phy_idx phy_idx) 5575 { 5576 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 5577 mac_idx, phy_idx); 5578 } 5579 5580 static inline 5581 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 5582 enum rtw89_sub_entity_idx idx) 5583 { 5584 struct rtw89_hal *hal = &rtwdev->hal; 5585 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 5586 5587 if (roc_idx == idx) 5588 return &hal->roc_chandef; 5589 5590 return &hal->sub[idx].chandef; 5591 } 5592 5593 static inline 5594 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 5595 enum rtw89_sub_entity_idx idx) 5596 { 5597 struct rtw89_hal *hal = &rtwdev->hal; 5598 5599 return &hal->sub[idx].chan; 5600 } 5601 5602 static inline 5603 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 5604 enum rtw89_sub_entity_idx idx) 5605 { 5606 struct rtw89_hal *hal = &rtwdev->hal; 5607 5608 return &hal->sub[idx].rcd; 5609 } 5610 5611 static inline 5612 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 5613 { 5614 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 5615 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 5616 5617 if (rtwvif) 5618 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 5619 else 5620 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5621 } 5622 5623 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 5624 { 5625 const struct rtw89_chip_info *chip = rtwdev->chip; 5626 5627 if (chip->ops->fem_setup) 5628 chip->ops->fem_setup(rtwdev); 5629 } 5630 5631 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 5632 { 5633 const struct rtw89_chip_info *chip = rtwdev->chip; 5634 5635 if (chip->ops->rfe_gpio) 5636 chip->ops->rfe_gpio(rtwdev); 5637 } 5638 5639 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 5640 { 5641 const struct rtw89_chip_info *chip = rtwdev->chip; 5642 5643 if (chip->ops->rfk_hw_init) 5644 chip->ops->rfk_hw_init(rtwdev); 5645 } 5646 5647 static inline 5648 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5649 { 5650 const struct rtw89_chip_info *chip = rtwdev->chip; 5651 5652 if (chip->ops->bb_preinit) 5653 chip->ops->bb_preinit(rtwdev, phy_idx); 5654 } 5655 5656 static inline 5657 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 5658 { 5659 const struct rtw89_chip_info *chip = rtwdev->chip; 5660 5661 if (!chip->ops->bb_postinit) 5662 return; 5663 5664 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 5665 5666 if (rtwdev->dbcc_en) 5667 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 5668 } 5669 5670 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 5671 { 5672 const struct rtw89_chip_info *chip = rtwdev->chip; 5673 5674 if (chip->ops->bb_sethw) 5675 chip->ops->bb_sethw(rtwdev); 5676 } 5677 5678 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 5679 { 5680 const struct rtw89_chip_info *chip = rtwdev->chip; 5681 5682 if (chip->ops->rfk_init) 5683 chip->ops->rfk_init(rtwdev); 5684 } 5685 5686 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 5687 { 5688 const struct rtw89_chip_info *chip = rtwdev->chip; 5689 5690 if (chip->ops->rfk_init_late) 5691 chip->ops->rfk_init_late(rtwdev); 5692 } 5693 5694 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 5695 { 5696 const struct rtw89_chip_info *chip = rtwdev->chip; 5697 5698 if (chip->ops->rfk_channel) 5699 chip->ops->rfk_channel(rtwdev); 5700 } 5701 5702 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 5703 enum rtw89_phy_idx phy_idx) 5704 { 5705 const struct rtw89_chip_info *chip = rtwdev->chip; 5706 5707 if (chip->ops->rfk_band_changed) 5708 chip->ops->rfk_band_changed(rtwdev, phy_idx); 5709 } 5710 5711 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 5712 { 5713 const struct rtw89_chip_info *chip = rtwdev->chip; 5714 5715 if (chip->ops->rfk_scan) 5716 chip->ops->rfk_scan(rtwdev, start); 5717 } 5718 5719 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 5720 { 5721 const struct rtw89_chip_info *chip = rtwdev->chip; 5722 5723 if (chip->ops->rfk_track) 5724 chip->ops->rfk_track(rtwdev); 5725 } 5726 5727 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 5728 { 5729 const struct rtw89_chip_info *chip = rtwdev->chip; 5730 5731 if (chip->ops->set_txpwr_ctrl) 5732 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 5733 } 5734 5735 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 5736 { 5737 const struct rtw89_chip_info *chip = rtwdev->chip; 5738 5739 if (chip->ops->power_trim) 5740 chip->ops->power_trim(rtwdev); 5741 } 5742 5743 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 5744 enum rtw89_phy_idx phy_idx) 5745 { 5746 const struct rtw89_chip_info *chip = rtwdev->chip; 5747 5748 if (chip->ops->init_txpwr_unit) 5749 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 5750 } 5751 5752 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 5753 enum rtw89_rf_path rf_path) 5754 { 5755 const struct rtw89_chip_info *chip = rtwdev->chip; 5756 5757 if (!chip->ops->get_thermal) 5758 return 0x10; 5759 5760 return chip->ops->get_thermal(rtwdev, rf_path); 5761 } 5762 5763 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 5764 struct rtw89_rx_phy_ppdu *phy_ppdu, 5765 struct ieee80211_rx_status *status) 5766 { 5767 const struct rtw89_chip_info *chip = rtwdev->chip; 5768 5769 if (chip->ops->query_ppdu) 5770 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 5771 } 5772 5773 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 5774 enum rtw89_phy_idx phy_idx) 5775 { 5776 const struct rtw89_chip_info *chip = rtwdev->chip; 5777 5778 if (chip->ops->ctrl_nbtg_bt_tx) 5779 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 5780 } 5781 5782 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 5783 { 5784 const struct rtw89_chip_info *chip = rtwdev->chip; 5785 5786 if (chip->ops->cfg_txrx_path) 5787 chip->ops->cfg_txrx_path(rtwdev); 5788 } 5789 5790 static inline 5791 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5792 struct ieee80211_vif *vif) 5793 { 5794 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5795 const struct rtw89_chip_info *chip = rtwdev->chip; 5796 5797 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5798 return; 5799 5800 if (chip->ops->set_txpwr_ul_tb_offset) 5801 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5802 } 5803 5804 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 5805 const struct rtw89_txpwr_table *tbl) 5806 { 5807 tbl->load(rtwdev, tbl); 5808 } 5809 5810 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 5811 { 5812 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 5813 5814 return regd->txpwr_regd[band]; 5815 } 5816 5817 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 5818 enum rtw89_phy_idx phy_idx) 5819 { 5820 const struct rtw89_chip_info *chip = rtwdev->chip; 5821 5822 if (chip->ops->ctrl_btg_bt_rx) 5823 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 5824 } 5825 5826 static inline 5827 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 5828 struct rtw89_rx_desc_info *desc_info, 5829 u8 *data, u32 data_offset) 5830 { 5831 const struct rtw89_chip_info *chip = rtwdev->chip; 5832 5833 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 5834 } 5835 5836 static inline 5837 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 5838 struct rtw89_tx_desc_info *desc_info, 5839 void *txdesc) 5840 { 5841 const struct rtw89_chip_info *chip = rtwdev->chip; 5842 5843 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 5844 } 5845 5846 static inline 5847 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 5848 struct rtw89_tx_desc_info *desc_info, 5849 void *txdesc) 5850 { 5851 const struct rtw89_chip_info *chip = rtwdev->chip; 5852 5853 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 5854 } 5855 5856 static inline 5857 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5858 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5859 { 5860 const struct rtw89_chip_info *chip = rtwdev->chip; 5861 5862 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 5863 } 5864 5865 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5866 { 5867 const struct rtw89_chip_info *chip = rtwdev->chip; 5868 5869 chip->ops->cfg_ctrl_path(rtwdev, wl); 5870 } 5871 5872 static inline 5873 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 5874 u32 *tx_en, enum rtw89_sch_tx_sel sel) 5875 { 5876 const struct rtw89_chip_info *chip = rtwdev->chip; 5877 5878 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 5879 } 5880 5881 static inline 5882 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 5883 { 5884 const struct rtw89_chip_info *chip = rtwdev->chip; 5885 5886 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 5887 } 5888 5889 static inline 5890 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 5891 struct rtw89_vif *rtwvif, 5892 struct rtw89_sta *rtwsta) 5893 { 5894 const struct rtw89_chip_info *chip = rtwdev->chip; 5895 5896 if (!chip->ops->h2c_dctl_sec_cam) 5897 return 0; 5898 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 5899 } 5900 5901 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 5902 { 5903 __le16 fc = hdr->frame_control; 5904 5905 if (ieee80211_has_tods(fc)) 5906 return hdr->addr1; 5907 else if (ieee80211_has_fromds(fc)) 5908 return hdr->addr2; 5909 else 5910 return hdr->addr3; 5911 } 5912 5913 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 5914 { 5915 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5916 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 5917 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 5918 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5919 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 5920 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 5921 return true; 5922 return false; 5923 } 5924 5925 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 5926 enum rtw89_fw_type type) 5927 { 5928 struct rtw89_fw_info *fw_info = &rtwdev->fw; 5929 5930 switch (type) { 5931 case RTW89_FW_WOWLAN: 5932 return &fw_info->wowlan; 5933 case RTW89_FW_LOGFMT: 5934 return &fw_info->log.suit; 5935 case RTW89_FW_BBMCU0: 5936 return &fw_info->bbmcu0; 5937 case RTW89_FW_BBMCU1: 5938 return &fw_info->bbmcu1; 5939 default: 5940 break; 5941 } 5942 5943 return &fw_info->normal; 5944 } 5945 5946 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 5947 unsigned int length) 5948 { 5949 struct sk_buff *skb; 5950 5951 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 5952 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 5953 if (!skb) 5954 return NULL; 5955 5956 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 5957 return skb; 5958 } 5959 5960 return dev_alloc_skb(length); 5961 } 5962 5963 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 5964 struct rtw89_tx_skb_data *skb_data, 5965 bool tx_done) 5966 { 5967 struct rtw89_tx_wait_info *wait; 5968 5969 rcu_read_lock(); 5970 5971 wait = rcu_dereference(skb_data->wait); 5972 if (!wait) 5973 goto out; 5974 5975 wait->tx_done = tx_done; 5976 complete(&wait->completion); 5977 5978 out: 5979 rcu_read_unlock(); 5980 } 5981 5982 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 5983 { 5984 switch (rtwdev->mlo_dbcc_mode) { 5985 case MLO_1_PLUS_1_1RF: 5986 case MLO_1_PLUS_1_2RF: 5987 case DBCC_LEGACY: 5988 return true; 5989 default: 5990 return false; 5991 } 5992 } 5993 5994 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5995 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 5996 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 5997 struct sk_buff *skb, bool fwdl); 5998 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 5999 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6000 int qsel, unsigned int timeout); 6001 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6002 struct rtw89_tx_desc_info *desc_info, 6003 void *txdesc); 6004 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6005 struct rtw89_tx_desc_info *desc_info, 6006 void *txdesc); 6007 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6008 struct rtw89_tx_desc_info *desc_info, 6009 void *txdesc); 6010 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6011 struct rtw89_tx_desc_info *desc_info, 6012 void *txdesc); 6013 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6014 struct rtw89_tx_desc_info *desc_info, 6015 void *txdesc); 6016 void rtw89_core_rx(struct rtw89_dev *rtwdev, 6017 struct rtw89_rx_desc_info *desc_info, 6018 struct sk_buff *skb); 6019 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 6020 struct rtw89_rx_desc_info *desc_info, 6021 u8 *data, u32 data_offset); 6022 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 6023 struct rtw89_rx_desc_info *desc_info, 6024 u8 *data, u32 data_offset); 6025 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 6026 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 6027 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 6028 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 6029 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 6030 struct ieee80211_vif *vif, 6031 struct ieee80211_sta *sta); 6032 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 6033 struct ieee80211_vif *vif, 6034 struct ieee80211_sta *sta); 6035 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 6036 struct ieee80211_vif *vif, 6037 struct ieee80211_sta *sta); 6038 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 6039 struct ieee80211_vif *vif, 6040 struct ieee80211_sta *sta); 6041 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 6042 struct ieee80211_vif *vif, 6043 struct ieee80211_sta *sta); 6044 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6045 struct ieee80211_sta *sta, 6046 struct cfg80211_tid_config *tid_config); 6047 int rtw89_core_init(struct rtw89_dev *rtwdev); 6048 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 6049 int rtw89_core_register(struct rtw89_dev *rtwdev); 6050 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 6051 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6052 u32 bus_data_size, 6053 const struct rtw89_chip_info *chip); 6054 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 6055 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 6056 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 6057 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 6058 struct rtw89_chan *chan); 6059 int rtw89_set_channel(struct rtw89_dev *rtwdev); 6060 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6061 struct rtw89_chan *chan); 6062 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 6063 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 6064 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 6065 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 6066 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6067 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 6068 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6069 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 6070 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 6071 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 6072 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 6073 int rtw89_regd_init(struct rtw89_dev *rtwdev, 6074 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 6075 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 6076 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 6077 struct rtw89_traffic_stats *stats); 6078 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 6079 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6080 const struct rtw89_completion_data *data); 6081 int rtw89_core_start(struct rtw89_dev *rtwdev); 6082 void rtw89_core_stop(struct rtw89_dev *rtwdev); 6083 void rtw89_core_update_beacon_work(struct work_struct *work); 6084 void rtw89_roc_work(struct work_struct *work); 6085 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6086 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6087 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6088 const u8 *mac_addr, bool hw_scan); 6089 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6090 struct ieee80211_vif *vif, bool hw_scan); 6091 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 6092 struct rtw89_vif *rtwvif, bool active); 6093 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 6094 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 6095 6096 #endif 6097