1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_efuse_block_cfg; 21 struct rtw89_h2c_rf_tssi; 22 struct rtw89_fw_txpwr_track_cfg; 23 struct rtw89_phy_rfk_log_fmt; 24 struct rtw89_debugfs; 25 26 extern const struct ieee80211_ops rtw89_ops; 27 28 #define MASKBYTE0 0xff 29 #define MASKBYTE1 0xff00 30 #define MASKBYTE2 0xff0000 31 #define MASKBYTE3 0xff000000 32 #define MASKBYTE4 0xff00000000ULL 33 #define MASKHWORD 0xffff0000 34 #define MASKLWORD 0x0000ffff 35 #define MASKDWORD 0xffffffff 36 #define RFREG_MASK 0xfffff 37 #define INV_RF_DATA 0xffffffff 38 #define BYPASS_CR_DATA 0xbabecafe 39 40 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 41 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 42 #define CFO_TRACK_MAX_USER 64 43 #define MAX_RSSI 110 44 #define RSSI_FACTOR 1 45 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 46 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 47 #define DELTA_SWINGIDX_SIZE 30 48 49 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 50 #define RTW89_RADIOTAP_ROOM_EHT \ 51 (sizeof(struct ieee80211_radiotap_tlv) + \ 52 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 53 sizeof(struct ieee80211_radiotap_tlv) + \ 54 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 55 #define RTW89_RADIOTAP_ROOM \ 56 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 57 58 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 59 #define RTW89_HTC_VARIANT_HE 3 60 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 61 #define RTW89_HTC_VARIANT_HE_CID_OM 1 62 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 63 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 64 65 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 66 enum htc_om_channel_width { 67 HTC_OM_CHANNEL_WIDTH_20 = 0, 68 HTC_OM_CHANNEL_WIDTH_40 = 1, 69 HTC_OM_CHANNEL_WIDTH_80 = 2, 70 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 71 }; 72 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 73 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 74 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 75 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 76 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 77 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 78 79 #define RTW89_TF_PAD GENMASK(11, 0) 80 #define RTW89_TF_BASIC_USER_INFO_SZ 6 81 82 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 83 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 84 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 86 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 87 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 88 89 enum rtw89_subband { 90 RTW89_CH_2G = 0, 91 RTW89_CH_5G_BAND_1 = 1, 92 /* RTW89_CH_5G_BAND_2 = 2, unused */ 93 RTW89_CH_5G_BAND_3 = 3, 94 RTW89_CH_5G_BAND_4 = 4, 95 96 RTW89_CH_6G_BAND_IDX0, /* Low */ 97 RTW89_CH_6G_BAND_IDX1, /* Low */ 98 RTW89_CH_6G_BAND_IDX2, /* Mid */ 99 RTW89_CH_6G_BAND_IDX3, /* Mid */ 100 RTW89_CH_6G_BAND_IDX4, /* High */ 101 RTW89_CH_6G_BAND_IDX5, /* High */ 102 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 103 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 104 105 RTW89_SUBBAND_NR, 106 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 107 }; 108 109 enum rtw89_gain_offset { 110 RTW89_GAIN_OFFSET_2G_CCK, 111 RTW89_GAIN_OFFSET_2G_OFDM, 112 RTW89_GAIN_OFFSET_5G_LOW, 113 RTW89_GAIN_OFFSET_5G_MID, 114 RTW89_GAIN_OFFSET_5G_HIGH, 115 RTW89_GAIN_OFFSET_6G_L0, 116 RTW89_GAIN_OFFSET_6G_L1, 117 RTW89_GAIN_OFFSET_6G_M0, 118 RTW89_GAIN_OFFSET_6G_M1, 119 RTW89_GAIN_OFFSET_6G_H0, 120 RTW89_GAIN_OFFSET_6G_H1, 121 RTW89_GAIN_OFFSET_6G_UH0, 122 RTW89_GAIN_OFFSET_6G_UH1, 123 124 RTW89_GAIN_OFFSET_NR, 125 }; 126 127 enum rtw89_hci_type { 128 RTW89_HCI_TYPE_PCIE, 129 RTW89_HCI_TYPE_USB, 130 RTW89_HCI_TYPE_SDIO, 131 }; 132 133 enum rtw89_core_chip_id { 134 RTL8852A, 135 RTL8852B, 136 RTL8852BT, 137 RTL8852C, 138 RTL8851B, 139 RTL8922A, 140 }; 141 142 enum rtw89_chip_gen { 143 RTW89_CHIP_AX, 144 RTW89_CHIP_BE, 145 146 RTW89_CHIP_GEN_NUM, 147 }; 148 149 enum rtw89_cv { 150 CHIP_CAV, 151 CHIP_CBV, 152 CHIP_CCV, 153 CHIP_CDV, 154 CHIP_CEV, 155 CHIP_CFV, 156 CHIP_CV_MAX, 157 CHIP_CV_INVALID = CHIP_CV_MAX, 158 }; 159 160 enum rtw89_bacam_ver { 161 RTW89_BACAM_V0, 162 RTW89_BACAM_V1, 163 164 RTW89_BACAM_V0_EXT = 99, 165 }; 166 167 enum rtw89_core_tx_type { 168 RTW89_CORE_TX_TYPE_DATA, 169 RTW89_CORE_TX_TYPE_MGMT, 170 RTW89_CORE_TX_TYPE_FWCMD, 171 }; 172 173 enum rtw89_core_rx_type { 174 RTW89_CORE_RX_TYPE_WIFI = 0, 175 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 176 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 177 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 178 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 179 RTW89_CORE_RX_TYPE_SS2FW = 5, 180 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 181 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 182 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 183 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 184 RTW89_CORE_RX_TYPE_C2H = 10, 185 RTW89_CORE_RX_TYPE_CSI = 11, 186 RTW89_CORE_RX_TYPE_CQI = 12, 187 RTW89_CORE_RX_TYPE_H2C = 13, 188 RTW89_CORE_RX_TYPE_FWDL = 14, 189 }; 190 191 enum rtw89_txq_flags { 192 RTW89_TXQ_F_AMPDU = 0, 193 RTW89_TXQ_F_BLOCK_BA = 1, 194 RTW89_TXQ_F_FORBID_BA = 2, 195 }; 196 197 enum rtw89_net_type { 198 RTW89_NET_TYPE_NO_LINK = 0, 199 RTW89_NET_TYPE_AD_HOC = 1, 200 RTW89_NET_TYPE_INFRA = 2, 201 RTW89_NET_TYPE_AP_MODE = 3, 202 }; 203 204 enum rtw89_wifi_role { 205 RTW89_WIFI_ROLE_NONE, 206 RTW89_WIFI_ROLE_STATION, 207 RTW89_WIFI_ROLE_AP, 208 RTW89_WIFI_ROLE_AP_VLAN, 209 RTW89_WIFI_ROLE_ADHOC, 210 RTW89_WIFI_ROLE_ADHOC_MASTER, 211 RTW89_WIFI_ROLE_MESH_POINT, 212 RTW89_WIFI_ROLE_MONITOR, 213 RTW89_WIFI_ROLE_P2P_DEVICE, 214 RTW89_WIFI_ROLE_P2P_CLIENT, 215 RTW89_WIFI_ROLE_P2P_GO, 216 RTW89_WIFI_ROLE_NAN, 217 RTW89_WIFI_ROLE_MLME_MAX 218 }; 219 220 enum rtw89_upd_mode { 221 RTW89_ROLE_CREATE, 222 RTW89_ROLE_REMOVE, 223 RTW89_ROLE_TYPE_CHANGE, 224 RTW89_ROLE_INFO_CHANGE, 225 RTW89_ROLE_CON_DISCONN, 226 RTW89_ROLE_BAND_SW, 227 RTW89_ROLE_FW_RESTORE, 228 }; 229 230 enum rtw89_self_role { 231 RTW89_SELF_ROLE_CLIENT, 232 RTW89_SELF_ROLE_AP, 233 RTW89_SELF_ROLE_AP_CLIENT 234 }; 235 236 enum rtw89_msk_sO_el { 237 RTW89_NO_MSK, 238 RTW89_SMA, 239 RTW89_TMA, 240 RTW89_BSSID 241 }; 242 243 enum rtw89_sch_tx_sel { 244 RTW89_SCH_TX_SEL_ALL, 245 RTW89_SCH_TX_SEL_HIQ, 246 RTW89_SCH_TX_SEL_MG0, 247 RTW89_SCH_TX_SEL_MACID, 248 }; 249 250 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 251 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 252 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 253 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 254 */ 255 enum rtw89_add_cam_sec_mode { 256 RTW89_ADDR_CAM_SEC_NONE = 0, 257 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 258 RTW89_ADDR_CAM_SEC_NORMAL = 2, 259 RTW89_ADDR_CAM_SEC_4GROUP = 3, 260 }; 261 262 enum rtw89_sec_key_type { 263 RTW89_SEC_KEY_TYPE_NONE = 0, 264 RTW89_SEC_KEY_TYPE_WEP40 = 1, 265 RTW89_SEC_KEY_TYPE_WEP104 = 2, 266 RTW89_SEC_KEY_TYPE_TKIP = 3, 267 RTW89_SEC_KEY_TYPE_WAPI = 4, 268 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 269 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 270 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 271 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 272 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 273 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 274 }; 275 276 enum rtw89_port { 277 RTW89_PORT_0 = 0, 278 RTW89_PORT_1 = 1, 279 RTW89_PORT_2 = 2, 280 RTW89_PORT_3 = 3, 281 RTW89_PORT_4 = 4, 282 RTW89_PORT_NUM 283 }; 284 285 enum rtw89_band { 286 RTW89_BAND_2G = 0, 287 RTW89_BAND_5G = 1, 288 RTW89_BAND_6G = 2, 289 RTW89_BAND_NUM, 290 }; 291 292 enum rtw89_hw_rate { 293 RTW89_HW_RATE_CCK1 = 0x0, 294 RTW89_HW_RATE_CCK2 = 0x1, 295 RTW89_HW_RATE_CCK5_5 = 0x2, 296 RTW89_HW_RATE_CCK11 = 0x3, 297 RTW89_HW_RATE_OFDM6 = 0x4, 298 RTW89_HW_RATE_OFDM9 = 0x5, 299 RTW89_HW_RATE_OFDM12 = 0x6, 300 RTW89_HW_RATE_OFDM18 = 0x7, 301 RTW89_HW_RATE_OFDM24 = 0x8, 302 RTW89_HW_RATE_OFDM36 = 0x9, 303 RTW89_HW_RATE_OFDM48 = 0xA, 304 RTW89_HW_RATE_OFDM54 = 0xB, 305 RTW89_HW_RATE_MCS0 = 0x80, 306 RTW89_HW_RATE_MCS1 = 0x81, 307 RTW89_HW_RATE_MCS2 = 0x82, 308 RTW89_HW_RATE_MCS3 = 0x83, 309 RTW89_HW_RATE_MCS4 = 0x84, 310 RTW89_HW_RATE_MCS5 = 0x85, 311 RTW89_HW_RATE_MCS6 = 0x86, 312 RTW89_HW_RATE_MCS7 = 0x87, 313 RTW89_HW_RATE_MCS8 = 0x88, 314 RTW89_HW_RATE_MCS9 = 0x89, 315 RTW89_HW_RATE_MCS10 = 0x8A, 316 RTW89_HW_RATE_MCS11 = 0x8B, 317 RTW89_HW_RATE_MCS12 = 0x8C, 318 RTW89_HW_RATE_MCS13 = 0x8D, 319 RTW89_HW_RATE_MCS14 = 0x8E, 320 RTW89_HW_RATE_MCS15 = 0x8F, 321 RTW89_HW_RATE_MCS16 = 0x90, 322 RTW89_HW_RATE_MCS17 = 0x91, 323 RTW89_HW_RATE_MCS18 = 0x92, 324 RTW89_HW_RATE_MCS19 = 0x93, 325 RTW89_HW_RATE_MCS20 = 0x94, 326 RTW89_HW_RATE_MCS21 = 0x95, 327 RTW89_HW_RATE_MCS22 = 0x96, 328 RTW89_HW_RATE_MCS23 = 0x97, 329 RTW89_HW_RATE_MCS24 = 0x98, 330 RTW89_HW_RATE_MCS25 = 0x99, 331 RTW89_HW_RATE_MCS26 = 0x9A, 332 RTW89_HW_RATE_MCS27 = 0x9B, 333 RTW89_HW_RATE_MCS28 = 0x9C, 334 RTW89_HW_RATE_MCS29 = 0x9D, 335 RTW89_HW_RATE_MCS30 = 0x9E, 336 RTW89_HW_RATE_MCS31 = 0x9F, 337 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 338 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 339 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 340 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 341 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 342 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 343 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 344 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 345 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 346 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 347 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 348 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 349 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 350 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 351 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 352 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 353 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 354 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 355 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 356 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 357 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 358 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 359 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 360 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 361 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 362 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 363 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 364 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 365 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 366 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 367 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 368 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 369 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 370 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 371 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 372 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 373 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 374 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 375 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 376 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 377 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 378 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 379 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 380 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 381 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 382 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 383 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 384 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 385 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 386 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 387 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 388 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 389 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 390 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 391 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 392 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 393 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 394 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 395 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 396 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 397 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 398 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 399 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 400 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 401 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 402 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 403 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 404 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 405 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 406 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 407 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 408 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 409 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 410 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 411 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 412 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 413 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 414 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 415 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 416 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 417 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 418 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 419 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 420 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 421 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 422 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 423 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 424 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 425 426 RTW89_HW_RATE_V1_MCS0 = 0x100, 427 RTW89_HW_RATE_V1_MCS1 = 0x101, 428 RTW89_HW_RATE_V1_MCS2 = 0x102, 429 RTW89_HW_RATE_V1_MCS3 = 0x103, 430 RTW89_HW_RATE_V1_MCS4 = 0x104, 431 RTW89_HW_RATE_V1_MCS5 = 0x105, 432 RTW89_HW_RATE_V1_MCS6 = 0x106, 433 RTW89_HW_RATE_V1_MCS7 = 0x107, 434 RTW89_HW_RATE_V1_MCS8 = 0x108, 435 RTW89_HW_RATE_V1_MCS9 = 0x109, 436 RTW89_HW_RATE_V1_MCS10 = 0x10A, 437 RTW89_HW_RATE_V1_MCS11 = 0x10B, 438 RTW89_HW_RATE_V1_MCS12 = 0x10C, 439 RTW89_HW_RATE_V1_MCS13 = 0x10D, 440 RTW89_HW_RATE_V1_MCS14 = 0x10E, 441 RTW89_HW_RATE_V1_MCS15 = 0x10F, 442 RTW89_HW_RATE_V1_MCS16 = 0x110, 443 RTW89_HW_RATE_V1_MCS17 = 0x111, 444 RTW89_HW_RATE_V1_MCS18 = 0x112, 445 RTW89_HW_RATE_V1_MCS19 = 0x113, 446 RTW89_HW_RATE_V1_MCS20 = 0x114, 447 RTW89_HW_RATE_V1_MCS21 = 0x115, 448 RTW89_HW_RATE_V1_MCS22 = 0x116, 449 RTW89_HW_RATE_V1_MCS23 = 0x117, 450 RTW89_HW_RATE_V1_MCS24 = 0x118, 451 RTW89_HW_RATE_V1_MCS25 = 0x119, 452 RTW89_HW_RATE_V1_MCS26 = 0x11A, 453 RTW89_HW_RATE_V1_MCS27 = 0x11B, 454 RTW89_HW_RATE_V1_MCS28 = 0x11C, 455 RTW89_HW_RATE_V1_MCS29 = 0x11D, 456 RTW89_HW_RATE_V1_MCS30 = 0x11E, 457 RTW89_HW_RATE_V1_MCS31 = 0x11F, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 469 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 481 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 493 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 505 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 517 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 529 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 541 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 553 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 583 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 597 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 611 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 612 613 RTW89_HW_RATE_NR, 614 RTW89_HW_RATE_INVAL, 615 616 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 617 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 618 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 619 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 620 }; 621 622 /* 2G channels, 623 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 624 */ 625 #define RTW89_2G_CH_NUM 14 626 627 /* 5G channels, 628 * 36, 38, 40, 42, 44, 46, 48, 50, 629 * 52, 54, 56, 58, 60, 62, 64, 630 * 100, 102, 104, 106, 108, 110, 112, 114, 631 * 116, 118, 120, 122, 124, 126, 128, 130, 632 * 132, 134, 136, 138, 140, 142, 144, 633 * 149, 151, 153, 155, 157, 159, 161, 163, 634 * 165, 167, 169, 171, 173, 175, 177 635 */ 636 #define RTW89_5G_CH_NUM 53 637 638 /* 6G channels, 639 * 1, 3, 5, 7, 9, 11, 13, 15, 640 * 17, 19, 21, 23, 25, 27, 29, 33, 641 * 35, 37, 39, 41, 43, 45, 47, 49, 642 * 51, 53, 55, 57, 59, 61, 65, 67, 643 * 69, 71, 73, 75, 77, 79, 81, 83, 644 * 85, 87, 89, 91, 93, 97, 99, 101, 645 * 103, 105, 107, 109, 111, 113, 115, 117, 646 * 119, 121, 123, 125, 129, 131, 133, 135, 647 * 137, 139, 141, 143, 145, 147, 149, 151, 648 * 153, 155, 157, 161, 163, 165, 167, 169, 649 * 171, 173, 175, 177, 179, 181, 183, 185, 650 * 187, 189, 193, 195, 197, 199, 201, 203, 651 * 205, 207, 209, 211, 213, 215, 217, 219, 652 * 221, 225, 227, 229, 231, 233, 235, 237, 653 * 239, 241, 243, 245, 247, 249, 251, 253, 654 */ 655 #define RTW89_6G_CH_NUM 120 656 657 enum rtw89_rate_section { 658 RTW89_RS_CCK, 659 RTW89_RS_OFDM, 660 RTW89_RS_MCS, /* for HT/VHT/HE */ 661 RTW89_RS_HEDCM, 662 RTW89_RS_OFFSET, 663 RTW89_RS_NUM, 664 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 665 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 666 }; 667 668 enum rtw89_rate_offset_indexes { 669 RTW89_RATE_OFFSET_HE, 670 RTW89_RATE_OFFSET_VHT, 671 RTW89_RATE_OFFSET_HT, 672 RTW89_RATE_OFFSET_OFDM, 673 RTW89_RATE_OFFSET_CCK, 674 RTW89_RATE_OFFSET_DLRU_EHT, 675 RTW89_RATE_OFFSET_DLRU_HE, 676 RTW89_RATE_OFFSET_EHT, 677 __RTW89_RATE_OFFSET_NUM, 678 679 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 680 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 681 }; 682 683 enum rtw89_rate_num { 684 RTW89_RATE_CCK_NUM = 4, 685 RTW89_RATE_OFDM_NUM = 8, 686 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 687 688 RTW89_RATE_MCS_NUM_AX = 12, 689 RTW89_RATE_MCS_NUM_BE = 16, 690 __RTW89_RATE_MCS_NUM = 16, 691 }; 692 693 enum rtw89_nss { 694 RTW89_NSS_1 = 0, 695 RTW89_NSS_2 = 1, 696 /* HE DCM only support 1ss and 2ss */ 697 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 698 RTW89_NSS_3 = 2, 699 RTW89_NSS_4 = 3, 700 RTW89_NSS_NUM, 701 }; 702 703 enum rtw89_ntx { 704 RTW89_1TX = 0, 705 RTW89_2TX = 1, 706 RTW89_NTX_NUM, 707 }; 708 709 enum rtw89_beamforming_type { 710 RTW89_NONBF = 0, 711 RTW89_BF = 1, 712 RTW89_BF_NUM, 713 }; 714 715 enum rtw89_ofdma_type { 716 RTW89_NON_OFDMA = 0, 717 RTW89_OFDMA = 1, 718 RTW89_OFDMA_NUM, 719 }; 720 721 enum rtw89_regulation_type { 722 RTW89_WW = 0, 723 RTW89_ETSI = 1, 724 RTW89_FCC = 2, 725 RTW89_MKK = 3, 726 RTW89_NA = 4, 727 RTW89_IC = 5, 728 RTW89_KCC = 6, 729 RTW89_ACMA = 7, 730 RTW89_NCC = 8, 731 RTW89_MEXICO = 9, 732 RTW89_CHILE = 10, 733 RTW89_UKRAINE = 11, 734 RTW89_CN = 12, 735 RTW89_QATAR = 13, 736 RTW89_UK = 14, 737 RTW89_THAILAND = 15, 738 RTW89_REGD_NUM, 739 }; 740 741 enum rtw89_reg_6ghz_power { 742 RTW89_REG_6GHZ_POWER_VLP = 0, 743 RTW89_REG_6GHZ_POWER_LPI = 1, 744 RTW89_REG_6GHZ_POWER_STD = 2, 745 746 NUM_OF_RTW89_REG_6GHZ_POWER, 747 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 748 }; 749 750 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 751 752 /* calculate based on ieee80211 Transmit Power Envelope */ 753 struct rtw89_reg_6ghz_tpe { 754 bool valid; 755 s8 constraint; /* unit: dBm */ 756 }; 757 758 enum rtw89_fw_pkt_ofld_type { 759 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 760 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 761 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 762 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 763 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 764 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 765 RTW89_PKT_OFLD_TYPE_NDP = 6, 766 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 767 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 768 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 769 RTW89_PKT_OFLD_TYPE_NUM, 770 }; 771 772 struct rtw89_txpwr_byrate { 773 s8 cck[RTW89_RATE_CCK_NUM]; 774 s8 ofdm[RTW89_RATE_OFDM_NUM]; 775 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 776 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 777 s8 offset[__RTW89_RATE_OFFSET_NUM]; 778 s8 trap; 779 }; 780 781 struct rtw89_rate_desc { 782 enum rtw89_nss nss; 783 enum rtw89_rate_section rs; 784 enum rtw89_ofdma_type ofdma; 785 u8 idx; 786 }; 787 788 #define PHY_STS_HDR_LEN 8 789 #define RF_PATH_MAX 4 790 #define RTW89_MAX_PPDU_CNT 8 791 struct rtw89_rx_phy_ppdu { 792 void *buf; 793 u32 len; 794 u8 rssi_avg; 795 u8 rssi[RF_PATH_MAX]; 796 u8 mac_id; 797 u8 chan_idx; 798 u8 ie; 799 u16 rate; 800 u8 rpl_avg; 801 u8 rpl_path[RF_PATH_MAX]; 802 u8 rpl_fd[RF_PATH_MAX]; 803 u8 bw_idx; 804 u8 rx_path_en; 805 struct { 806 bool has; 807 u8 avg_snr; 808 u8 evm_max; 809 u8 evm_min; 810 } ofdm; 811 bool has_data; 812 bool has_bcn; 813 bool ldpc; 814 bool stbc; 815 bool to_self; 816 bool valid; 817 bool hdr_2_en; 818 }; 819 820 enum rtw89_mac_idx { 821 RTW89_MAC_0 = 0, 822 RTW89_MAC_1 = 1, 823 RTW89_MAC_NUM, 824 }; 825 826 enum rtw89_phy_idx { 827 RTW89_PHY_0 = 0, 828 RTW89_PHY_1 = 1, 829 RTW89_PHY_MAX 830 }; 831 832 #define __RTW89_MLD_MAX_LINK_NUM 2 833 834 enum rtw89_chanctx_idx { 835 RTW89_CHANCTX_0 = 0, 836 RTW89_CHANCTX_1 = 1, 837 838 NUM_OF_RTW89_CHANCTX, 839 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 840 }; 841 842 enum rtw89_rf_path { 843 RF_PATH_A = 0, 844 RF_PATH_B = 1, 845 RF_PATH_C = 2, 846 RF_PATH_D = 3, 847 RF_PATH_AB, 848 RF_PATH_AC, 849 RF_PATH_AD, 850 RF_PATH_BC, 851 RF_PATH_BD, 852 RF_PATH_CD, 853 RF_PATH_ABC, 854 RF_PATH_ABD, 855 RF_PATH_ACD, 856 RF_PATH_BCD, 857 RF_PATH_ABCD, 858 }; 859 860 enum rtw89_rf_path_bit { 861 RF_A = BIT(0), 862 RF_B = BIT(1), 863 RF_C = BIT(2), 864 RF_D = BIT(3), 865 866 RF_AB = (RF_A | RF_B), 867 RF_AC = (RF_A | RF_C), 868 RF_AD = (RF_A | RF_D), 869 RF_BC = (RF_B | RF_C), 870 RF_BD = (RF_B | RF_D), 871 RF_CD = (RF_C | RF_D), 872 873 RF_ABC = (RF_A | RF_B | RF_C), 874 RF_ABD = (RF_A | RF_B | RF_D), 875 RF_ACD = (RF_A | RF_C | RF_D), 876 RF_BCD = (RF_B | RF_C | RF_D), 877 878 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 879 }; 880 881 enum rtw89_bandwidth { 882 RTW89_CHANNEL_WIDTH_20 = 0, 883 RTW89_CHANNEL_WIDTH_40 = 1, 884 RTW89_CHANNEL_WIDTH_80 = 2, 885 RTW89_CHANNEL_WIDTH_160 = 3, 886 RTW89_CHANNEL_WIDTH_320 = 4, 887 888 /* keep index order above */ 889 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 890 891 RTW89_CHANNEL_WIDTH_80_80 = 5, 892 RTW89_CHANNEL_WIDTH_5 = 6, 893 RTW89_CHANNEL_WIDTH_10 = 7, 894 }; 895 896 enum rtw89_ps_mode { 897 RTW89_PS_MODE_NONE = 0, 898 RTW89_PS_MODE_RFOFF = 1, 899 RTW89_PS_MODE_CLK_GATED = 2, 900 RTW89_PS_MODE_PWR_GATED = 3, 901 }; 902 903 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 904 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 905 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 906 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 907 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 908 909 enum rtw89_pe_duration { 910 RTW89_PE_DURATION_0 = 0, 911 RTW89_PE_DURATION_8 = 1, 912 RTW89_PE_DURATION_16 = 2, 913 RTW89_PE_DURATION_16_20 = 3, 914 }; 915 916 enum rtw89_ru_bandwidth { 917 RTW89_RU26 = 0, 918 RTW89_RU52 = 1, 919 RTW89_RU106 = 2, 920 RTW89_RU52_26 = 3, 921 RTW89_RU106_26 = 4, 922 RTW89_RU_NUM, 923 }; 924 925 enum rtw89_sc_offset { 926 RTW89_SC_DONT_CARE = 0, 927 RTW89_SC_20_UPPER = 1, 928 RTW89_SC_20_LOWER = 2, 929 RTW89_SC_20_UPMOST = 3, 930 RTW89_SC_20_LOWEST = 4, 931 RTW89_SC_20_UP2X = 5, 932 RTW89_SC_20_LOW2X = 6, 933 RTW89_SC_20_UP3X = 7, 934 RTW89_SC_20_LOW3X = 8, 935 RTW89_SC_40_UPPER = 9, 936 RTW89_SC_40_LOWER = 10, 937 }; 938 939 /* only mgd features can be added to the enum */ 940 enum rtw89_wow_flags { 941 RTW89_WOW_FLAG_EN_MAGIC_PKT, 942 RTW89_WOW_FLAG_EN_REKEY_PKT, 943 RTW89_WOW_FLAG_EN_DISCONNECT, 944 RTW89_WOW_FLAG_EN_PATTERN, 945 RTW89_WOW_FLAG_NUM, 946 }; 947 948 struct rtw89_chan { 949 u8 channel; 950 u8 primary_channel; 951 enum rtw89_band band_type; 952 enum rtw89_bandwidth band_width; 953 954 /* The follow-up are derived from the above. We must ensure that it 955 * is assigned correctly in rtw89_chan_create() if new one is added. 956 */ 957 u32 freq; 958 enum rtw89_subband subband_type; 959 enum rtw89_sc_offset pri_ch_idx; 960 u8 pri_sb_idx; 961 }; 962 963 struct rtw89_chan_rcd { 964 u8 prev_primary_channel; 965 enum rtw89_band prev_band_type; 966 bool band_changed; 967 }; 968 969 struct rtw89_channel_help_params { 970 u32 tx_en; 971 }; 972 973 struct rtw89_port_reg { 974 u32 port_cfg; 975 u32 tbtt_prohib; 976 u32 bcn_area; 977 u32 bcn_early; 978 u32 tbtt_early; 979 u32 tbtt_agg; 980 u32 bcn_space; 981 u32 bcn_forcetx; 982 u32 bcn_err_cnt; 983 u32 bcn_err_flag; 984 u32 dtim_ctrl; 985 u32 tbtt_shift; 986 u32 bcn_cnt_tmr; 987 u32 tsftr_l; 988 u32 tsftr_h; 989 u32 md_tsft; 990 u32 bss_color; 991 u32 mbssid; 992 u32 mbssid_drop; 993 u32 tsf_sync; 994 u32 ptcl_dbg; 995 u32 ptcl_dbg_info; 996 u32 bcn_drop_all; 997 u32 hiq_win[RTW89_PORT_NUM]; 998 }; 999 1000 struct rtw89_txwd_body { 1001 __le32 dword0; 1002 __le32 dword1; 1003 __le32 dword2; 1004 __le32 dword3; 1005 __le32 dword4; 1006 __le32 dword5; 1007 } __packed; 1008 1009 struct rtw89_txwd_body_v1 { 1010 __le32 dword0; 1011 __le32 dword1; 1012 __le32 dword2; 1013 __le32 dword3; 1014 __le32 dword4; 1015 __le32 dword5; 1016 __le32 dword6; 1017 __le32 dword7; 1018 } __packed; 1019 1020 struct rtw89_txwd_body_v2 { 1021 __le32 dword0; 1022 __le32 dword1; 1023 __le32 dword2; 1024 __le32 dword3; 1025 __le32 dword4; 1026 __le32 dword5; 1027 __le32 dword6; 1028 __le32 dword7; 1029 } __packed; 1030 1031 struct rtw89_txwd_info { 1032 __le32 dword0; 1033 __le32 dword1; 1034 __le32 dword2; 1035 __le32 dword3; 1036 __le32 dword4; 1037 __le32 dword5; 1038 } __packed; 1039 1040 struct rtw89_txwd_info_v2 { 1041 __le32 dword0; 1042 __le32 dword1; 1043 __le32 dword2; 1044 __le32 dword3; 1045 __le32 dword4; 1046 __le32 dword5; 1047 __le32 dword6; 1048 __le32 dword7; 1049 } __packed; 1050 1051 struct rtw89_rx_desc_info { 1052 u16 pkt_size; 1053 u8 pkt_type; 1054 u8 drv_info_size; 1055 u8 phy_rpt_size; 1056 u8 hdr_cnv_size; 1057 u8 shift; 1058 u8 wl_hd_iv_len; 1059 bool long_rxdesc; 1060 bool bb_sel; 1061 bool mac_info_valid; 1062 u16 data_rate; 1063 u8 gi_ltf; 1064 u8 bw; 1065 u32 free_run_cnt; 1066 u8 user_id; 1067 bool sr_en; 1068 u8 ppdu_cnt; 1069 u8 ppdu_type; 1070 bool icv_err; 1071 bool crc32_err; 1072 bool hw_dec; 1073 bool sw_dec; 1074 bool addr1_match; 1075 u8 frag; 1076 u16 seq; 1077 u8 frame_type; 1078 u8 rx_pl_id; 1079 bool addr_cam_valid; 1080 u8 addr_cam_id; 1081 u8 sec_cam_id; 1082 u8 mac_id; 1083 u16 offset; 1084 u16 rxd_len; 1085 bool ready; 1086 }; 1087 1088 struct rtw89_rxdesc_short { 1089 __le32 dword0; 1090 __le32 dword1; 1091 __le32 dword2; 1092 __le32 dword3; 1093 } __packed; 1094 1095 struct rtw89_rxdesc_short_v2 { 1096 __le32 dword0; 1097 __le32 dword1; 1098 __le32 dword2; 1099 __le32 dword3; 1100 __le32 dword4; 1101 __le32 dword5; 1102 } __packed; 1103 1104 struct rtw89_rxdesc_long { 1105 __le32 dword0; 1106 __le32 dword1; 1107 __le32 dword2; 1108 __le32 dword3; 1109 __le32 dword4; 1110 __le32 dword5; 1111 __le32 dword6; 1112 __le32 dword7; 1113 } __packed; 1114 1115 struct rtw89_rxdesc_long_v2 { 1116 __le32 dword0; 1117 __le32 dword1; 1118 __le32 dword2; 1119 __le32 dword3; 1120 __le32 dword4; 1121 __le32 dword5; 1122 __le32 dword6; 1123 __le32 dword7; 1124 __le32 dword8; 1125 __le32 dword9; 1126 } __packed; 1127 1128 struct rtw89_tx_desc_info { 1129 u16 pkt_size; 1130 u8 wp_offset; 1131 u8 mac_id; 1132 u8 qsel; 1133 u8 ch_dma; 1134 u8 hdr_llc_len; 1135 bool is_bmc; 1136 bool en_wd_info; 1137 bool wd_page; 1138 bool use_rate; 1139 bool dis_data_fb; 1140 bool tid_indicate; 1141 bool agg_en; 1142 bool bk; 1143 u8 ampdu_density; 1144 u8 ampdu_num; 1145 bool sec_en; 1146 u8 addr_info_nr; 1147 u8 sec_keyid; 1148 u8 sec_type; 1149 u8 sec_cam_idx; 1150 u8 sec_seq[6]; 1151 u16 data_rate; 1152 u16 data_retry_lowest_rate; 1153 bool fw_dl; 1154 u16 seq; 1155 bool a_ctrl_bsr; 1156 u8 hw_ssn_sel; 1157 #define RTW89_MGMT_HW_SSN_SEL 1 1158 u8 hw_seq_mode; 1159 #define RTW89_MGMT_HW_SEQ_MODE 1 1160 bool hiq; 1161 u8 port; 1162 bool er_cap; 1163 bool stbc; 1164 bool ldpc; 1165 }; 1166 1167 struct rtw89_core_tx_request { 1168 enum rtw89_core_tx_type tx_type; 1169 1170 struct sk_buff *skb; 1171 struct rtw89_vif_link *rtwvif_link; 1172 struct rtw89_sta_link *rtwsta_link; 1173 struct rtw89_tx_desc_info desc_info; 1174 }; 1175 1176 struct rtw89_txq { 1177 struct list_head list; 1178 unsigned long flags; 1179 int wait_cnt; 1180 }; 1181 1182 struct rtw89_mac_ax_gnt { 1183 u8 gnt_bt_sw_en; 1184 u8 gnt_bt; 1185 u8 gnt_wl_sw_en; 1186 u8 gnt_wl; 1187 } __packed; 1188 1189 struct rtw89_mac_ax_wl_act { 1190 u8 wlan_act_en; 1191 u8 wlan_act; 1192 }; 1193 1194 #define RTW89_MAC_AX_COEX_GNT_NR 2 1195 struct rtw89_mac_ax_coex_gnt { 1196 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1197 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1198 }; 1199 1200 enum rtw89_btc_ncnt { 1201 BTC_NCNT_POWER_ON = 0x0, 1202 BTC_NCNT_POWER_OFF, 1203 BTC_NCNT_INIT_COEX, 1204 BTC_NCNT_SCAN_START, 1205 BTC_NCNT_SCAN_FINISH, 1206 BTC_NCNT_SPECIAL_PACKET, 1207 BTC_NCNT_SWITCH_BAND, 1208 BTC_NCNT_RFK_TIMEOUT, 1209 BTC_NCNT_SHOW_COEX_INFO, 1210 BTC_NCNT_ROLE_INFO, 1211 BTC_NCNT_CONTROL, 1212 BTC_NCNT_RADIO_STATE, 1213 BTC_NCNT_CUSTOMERIZE, 1214 BTC_NCNT_WL_RFK, 1215 BTC_NCNT_WL_STA, 1216 BTC_NCNT_WL_STA_LAST, 1217 BTC_NCNT_FWINFO, 1218 BTC_NCNT_TIMER, 1219 BTC_NCNT_SWITCH_CHBW, 1220 BTC_NCNT_RESUME_DL_FW, 1221 BTC_NCNT_COUNTRYCODE, 1222 BTC_NCNT_NUM, 1223 }; 1224 1225 enum rtw89_btc_btinfo { 1226 BTC_BTINFO_L0 = 0, 1227 BTC_BTINFO_L1, 1228 BTC_BTINFO_L2, 1229 BTC_BTINFO_L3, 1230 BTC_BTINFO_H0, 1231 BTC_BTINFO_H1, 1232 BTC_BTINFO_H2, 1233 BTC_BTINFO_H3, 1234 BTC_BTINFO_MAX 1235 }; 1236 1237 enum rtw89_btc_dcnt { 1238 BTC_DCNT_RUN = 0x0, 1239 BTC_DCNT_CX_RUNINFO, 1240 BTC_DCNT_RPT, 1241 BTC_DCNT_RPT_HANG, 1242 BTC_DCNT_CYCLE, 1243 BTC_DCNT_CYCLE_HANG, 1244 BTC_DCNT_W1, 1245 BTC_DCNT_W1_HANG, 1246 BTC_DCNT_B1, 1247 BTC_DCNT_B1_HANG, 1248 BTC_DCNT_TDMA_NONSYNC, 1249 BTC_DCNT_SLOT_NONSYNC, 1250 BTC_DCNT_BTCNT_HANG, 1251 BTC_DCNT_BTTX_HANG, 1252 BTC_DCNT_WL_SLOT_DRIFT, 1253 BTC_DCNT_WL_STA_LAST, 1254 BTC_DCNT_BT_SLOT_DRIFT, 1255 BTC_DCNT_BT_SLOT_FLOOD, 1256 BTC_DCNT_FDDT_TRIG, 1257 BTC_DCNT_E2G, 1258 BTC_DCNT_E2G_HANG, 1259 BTC_DCNT_WL_FW_VER_MATCH, 1260 BTC_DCNT_NULL_TX_FAIL, 1261 BTC_DCNT_WL_STA_NTFY, 1262 BTC_DCNT_NUM, 1263 }; 1264 1265 enum rtw89_btc_wl_state_cnt { 1266 BTC_WCNT_SCANAP = 0x0, 1267 BTC_WCNT_DHCP, 1268 BTC_WCNT_EAPOL, 1269 BTC_WCNT_ARP, 1270 BTC_WCNT_SCBDUPDATE, 1271 BTC_WCNT_RFK_REQ, 1272 BTC_WCNT_RFK_GO, 1273 BTC_WCNT_RFK_REJECT, 1274 BTC_WCNT_RFK_TIMEOUT, 1275 BTC_WCNT_CH_UPDATE, 1276 BTC_WCNT_DBCC_ALL_2G, 1277 BTC_WCNT_DBCC_CHG, 1278 BTC_WCNT_RX_OK_LAST, 1279 BTC_WCNT_RX_OK_LAST2S, 1280 BTC_WCNT_RX_ERR_LAST, 1281 BTC_WCNT_RX_ERR_LAST2S, 1282 BTC_WCNT_RX_LAST, 1283 BTC_WCNT_NUM 1284 }; 1285 1286 enum rtw89_btc_bt_state_cnt { 1287 BTC_BCNT_RETRY = 0x0, 1288 BTC_BCNT_REINIT, 1289 BTC_BCNT_REENABLE, 1290 BTC_BCNT_SCBDREAD, 1291 BTC_BCNT_RELINK, 1292 BTC_BCNT_IGNOWL, 1293 BTC_BCNT_INQPAG, 1294 BTC_BCNT_INQ, 1295 BTC_BCNT_PAGE, 1296 BTC_BCNT_ROLESW, 1297 BTC_BCNT_AFH, 1298 BTC_BCNT_INFOUPDATE, 1299 BTC_BCNT_INFOSAME, 1300 BTC_BCNT_SCBDUPDATE, 1301 BTC_BCNT_HIPRI_TX, 1302 BTC_BCNT_HIPRI_RX, 1303 BTC_BCNT_LOPRI_TX, 1304 BTC_BCNT_LOPRI_RX, 1305 BTC_BCNT_POLUT, 1306 BTC_BCNT_POLUT_NOW, 1307 BTC_BCNT_POLUT_DIFF, 1308 BTC_BCNT_RATECHG, 1309 BTC_BCNT_NUM, 1310 }; 1311 1312 enum rtw89_btc_bt_profile { 1313 BTC_BT_NOPROFILE = 0, 1314 BTC_BT_HFP = BIT(0), 1315 BTC_BT_HID = BIT(1), 1316 BTC_BT_A2DP = BIT(2), 1317 BTC_BT_PAN = BIT(3), 1318 BTC_PROFILE_MAX = 4, 1319 }; 1320 1321 struct rtw89_btc_ant_info { 1322 u8 type; /* shared, dedicated */ 1323 u8 num; 1324 u8 isolation; 1325 1326 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1327 u8 diversity: 1; 1328 u8 btg_pos: 2; 1329 u8 stream_cnt: 4; 1330 }; 1331 1332 struct rtw89_btc_ant_info_v7 { 1333 u8 type; /* shared, dedicated(non-shared) */ 1334 u8 num; /* antenna count */ 1335 u8 isolation; 1336 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1337 1338 u8 diversity; /* only for wifi use 1-antenna */ 1339 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1340 u8 stream_cnt; /* spatial_stream count */ 1341 u8 rsvd; 1342 } __packed; 1343 1344 enum rtw89_tfc_dir { 1345 RTW89_TFC_UL, 1346 RTW89_TFC_DL, 1347 }; 1348 1349 struct rtw89_btc_wl_smap { 1350 u32 busy: 1; 1351 u32 scan: 1; 1352 u32 connecting: 1; 1353 u32 roaming: 1; 1354 u32 dbccing: 1; 1355 u32 _4way: 1; 1356 u32 rf_off: 1; 1357 u32 lps: 2; 1358 u32 ips: 1; 1359 u32 init_ok: 1; 1360 u32 traffic_dir : 2; 1361 u32 rf_off_pre: 1; 1362 u32 lps_pre: 2; 1363 u32 lps_exiting: 1; 1364 u32 emlsr: 1; 1365 }; 1366 1367 enum rtw89_tfc_lv { 1368 RTW89_TFC_IDLE, 1369 RTW89_TFC_ULTRA_LOW, 1370 RTW89_TFC_LOW, 1371 RTW89_TFC_MID, 1372 RTW89_TFC_HIGH, 1373 }; 1374 1375 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1376 DECLARE_EWMA(tp, 10, 2); 1377 1378 struct rtw89_traffic_stats { 1379 /* units in bytes */ 1380 u64 tx_unicast; 1381 u64 rx_unicast; 1382 u32 tx_avg_len; 1383 u32 rx_avg_len; 1384 1385 /* count for packets */ 1386 u64 tx_cnt; 1387 u64 rx_cnt; 1388 1389 /* units in Mbps */ 1390 u32 tx_throughput; 1391 u32 rx_throughput; 1392 u32 tx_throughput_raw; 1393 u32 rx_throughput_raw; 1394 1395 u32 rx_tf_acc; 1396 u32 rx_tf_periodic; 1397 1398 enum rtw89_tfc_lv tx_tfc_lv; 1399 enum rtw89_tfc_lv rx_tfc_lv; 1400 struct ewma_tp tx_ewma_tp; 1401 struct ewma_tp rx_ewma_tp; 1402 1403 u16 tx_rate; 1404 u16 rx_rate; 1405 }; 1406 1407 struct rtw89_btc_chdef { 1408 u8 center_ch; 1409 u8 band; 1410 u8 chan; 1411 enum rtw89_sc_offset offset; 1412 enum rtw89_bandwidth bw; 1413 }; 1414 1415 struct rtw89_btc_statistic { 1416 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1417 struct rtw89_traffic_stats traffic; 1418 }; 1419 1420 #define BTC_WL_RSSI_THMAX 4 1421 1422 struct rtw89_btc_wl_link_info { 1423 struct rtw89_btc_chdef chdef; 1424 struct rtw89_btc_statistic stat; 1425 enum rtw89_tfc_dir dir; 1426 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1427 u8 mac_addr[ETH_ALEN]; 1428 u8 busy; 1429 u8 ch; 1430 u8 bw; 1431 u8 band; 1432 u8 role; 1433 u8 pid; 1434 u8 phy; 1435 u8 dtim_period; 1436 u8 mode; 1437 u8 tx_1ss_limit; 1438 1439 u8 mac_id; 1440 u8 tx_retry; 1441 1442 u32 bcn_period; 1443 u32 busy_t; 1444 u32 tx_time; 1445 u32 client_cnt; 1446 u32 rx_rate_drop_cnt; 1447 u32 noa_duration; 1448 1449 u32 active: 1; 1450 u32 noa: 1; 1451 u32 client_ps: 1; 1452 u32 connected: 2; 1453 }; 1454 1455 union rtw89_btc_wl_state_map { 1456 u32 val; 1457 struct rtw89_btc_wl_smap map; 1458 }; 1459 1460 struct rtw89_btc_bt_hfp_desc { 1461 u32 exist: 1; 1462 u32 type: 2; 1463 u32 rsvd: 29; 1464 }; 1465 1466 struct rtw89_btc_bt_hid_desc { 1467 u32 exist: 1; 1468 u32 slot_info: 2; 1469 u32 pair_cnt: 2; 1470 u32 type: 8; 1471 u32 rsvd: 19; 1472 }; 1473 1474 struct rtw89_btc_bt_a2dp_desc { 1475 u8 exist: 1; 1476 u8 exist_last: 1; 1477 u8 play_latency: 1; 1478 u8 type: 3; 1479 u8 active: 1; 1480 u8 sink: 1; 1481 u32 handle_update: 1; 1482 u32 devinfo_query: 1; 1483 u32 no_empty_streak_2s: 8; 1484 u32 no_empty_streak_max: 8; 1485 u32 rsvd: 6; 1486 1487 u8 bitpool; 1488 u16 vendor_id; 1489 u32 device_name; 1490 u32 flush_time; 1491 }; 1492 1493 struct rtw89_btc_bt_pan_desc { 1494 u32 exist: 1; 1495 u32 type: 1; 1496 u32 active: 1; 1497 u32 rsvd: 29; 1498 }; 1499 1500 struct rtw89_btc_bt_rfk_info { 1501 u32 run: 1; 1502 u32 req: 1; 1503 u32 timeout: 1; 1504 u32 rsvd: 29; 1505 }; 1506 1507 union rtw89_btc_bt_rfk_info_map { 1508 u32 val; 1509 struct rtw89_btc_bt_rfk_info map; 1510 }; 1511 1512 struct rtw89_btc_bt_ver_info { 1513 u32 fw_coex; /* match with which coex_ver */ 1514 u32 fw; 1515 }; 1516 1517 struct rtw89_btc_bool_sta_chg { 1518 u32 now: 1; 1519 u32 last: 1; 1520 u32 remain: 1; 1521 u32 srvd: 29; 1522 }; 1523 1524 struct rtw89_btc_u8_sta_chg { 1525 u8 now; 1526 u8 last; 1527 u8 remain; 1528 u8 rsvd; 1529 }; 1530 1531 struct rtw89_btc_wl_scan_info { 1532 u8 band[RTW89_PHY_MAX]; 1533 u8 phy_map; 1534 u8 rsvd; 1535 }; 1536 1537 struct rtw89_btc_wl_dbcc_info { 1538 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1539 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1540 u8 real_band[RTW89_PHY_MAX]; 1541 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1542 }; 1543 1544 struct rtw89_btc_wl_active_role { 1545 u8 connected: 1; 1546 u8 pid: 3; 1547 u8 phy: 1; 1548 u8 noa: 1; 1549 u8 band: 2; 1550 1551 u8 client_ps: 1; 1552 u8 bw: 7; 1553 1554 u8 role; 1555 u8 ch; 1556 1557 u16 tx_lvl; 1558 u16 rx_lvl; 1559 u16 tx_rate; 1560 u16 rx_rate; 1561 }; 1562 1563 struct rtw89_btc_wl_active_role_v1 { 1564 u8 connected: 1; 1565 u8 pid: 3; 1566 u8 phy: 1; 1567 u8 noa: 1; 1568 u8 band: 2; 1569 1570 u8 client_ps: 1; 1571 u8 bw: 7; 1572 1573 u8 role; 1574 u8 ch; 1575 1576 u16 tx_lvl; 1577 u16 rx_lvl; 1578 u16 tx_rate; 1579 u16 rx_rate; 1580 1581 u32 noa_duration; /* ms */ 1582 }; 1583 1584 struct rtw89_btc_wl_active_role_v2 { 1585 u8 connected: 1; 1586 u8 pid: 3; 1587 u8 phy: 1; 1588 u8 noa: 1; 1589 u8 band: 2; 1590 1591 u8 client_ps: 1; 1592 u8 bw: 7; 1593 1594 u8 role; 1595 u8 ch; 1596 1597 u32 noa_duration; /* ms */ 1598 }; 1599 1600 struct rtw89_btc_wl_active_role_v7 { 1601 u8 connected; 1602 u8 pid; 1603 u8 phy; 1604 u8 noa; 1605 1606 u8 band; 1607 u8 client_ps; 1608 u8 bw; 1609 u8 role; 1610 1611 u8 ch; 1612 u8 noa_dur; 1613 u8 client_cnt; 1614 u8 rsvd2; 1615 } __packed; 1616 1617 struct rtw89_btc_wl_role_info_bpos { 1618 u16 none: 1; 1619 u16 station: 1; 1620 u16 ap: 1; 1621 u16 vap: 1; 1622 u16 adhoc: 1; 1623 u16 adhoc_master: 1; 1624 u16 mesh: 1; 1625 u16 moniter: 1; 1626 u16 p2p_device: 1; 1627 u16 p2p_gc: 1; 1628 u16 p2p_go: 1; 1629 u16 nan: 1; 1630 }; 1631 1632 struct rtw89_btc_wl_scc_ctrl { 1633 u8 null_role1; 1634 u8 null_role2; 1635 u8 ebt_null; /* if tx null at EBT slot */ 1636 }; 1637 1638 union rtw89_btc_wl_role_info_map { 1639 u16 val; 1640 struct rtw89_btc_wl_role_info_bpos role; 1641 }; 1642 1643 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1644 u8 connect_cnt; 1645 u8 link_mode; 1646 union rtw89_btc_wl_role_info_map role_map; 1647 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1648 }; 1649 1650 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1651 u8 connect_cnt; 1652 u8 link_mode; 1653 union rtw89_btc_wl_role_info_map role_map; 1654 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1655 u32 mrole_type; /* btc_wl_mrole_type */ 1656 u32 mrole_noa_duration; /* ms */ 1657 1658 u32 dbcc_en: 1; 1659 u32 dbcc_chg: 1; 1660 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1661 u32 link_mode_chg: 1; 1662 u32 rsvd: 27; 1663 }; 1664 1665 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1666 u8 connect_cnt; 1667 u8 link_mode; 1668 union rtw89_btc_wl_role_info_map role_map; 1669 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1670 u32 mrole_type; /* btc_wl_mrole_type */ 1671 u32 mrole_noa_duration; /* ms */ 1672 1673 u32 dbcc_en: 1; 1674 u32 dbcc_chg: 1; 1675 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1676 u32 link_mode_chg: 1; 1677 u32 rsvd: 27; 1678 }; 1679 1680 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1681 u8 connected; 1682 u8 pid; 1683 u8 phy; 1684 u8 noa; 1685 1686 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1687 u8 active; /* 0:rlink is under doze */ 1688 u8 bw; /* enum channel_width */ 1689 u8 role; /*enum role_type */ 1690 1691 u8 ch; 1692 u8 noa_dur; /* ms */ 1693 u8 client_cnt; /* for Role = P2P-Go/AP */ 1694 u8 mode; /* wifi protocol */ 1695 } __packed; 1696 1697 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1698 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1699 u8 connect_cnt; 1700 u8 link_mode; 1701 u8 link_mode_chg; 1702 u8 p2p_2g; 1703 1704 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1705 1706 u32 role_map; 1707 u32 mrole_type; /* btc_wl_mrole_type */ 1708 u32 mrole_noa_duration; /* ms */ 1709 u32 dbcc_en; 1710 u32 dbcc_chg; 1711 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1712 } __packed; 1713 1714 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1715 u8 connect_cnt; 1716 u8 link_mode; 1717 u8 link_mode_chg; 1718 u8 p2p_2g; 1719 1720 u8 pta_req_band; 1721 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1722 u8 dbcc_chg; 1723 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1724 1725 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1726 1727 u32 role_map; 1728 u32 mrole_type; /* btc_wl_mrole_type */ 1729 u32 mrole_noa_duration; /* ms */ 1730 } __packed; 1731 1732 struct rtw89_btc_wl_ver_info { 1733 u32 fw_coex; /* match with which coex_ver */ 1734 u32 fw; 1735 u32 mac; 1736 u32 bb; 1737 u32 rf; 1738 }; 1739 1740 struct rtw89_btc_wl_afh_info { 1741 u8 en; 1742 u8 ch; 1743 u8 bw; 1744 u8 rsvd; 1745 } __packed; 1746 1747 struct rtw89_btc_wl_rfk_info { 1748 u32 state: 2; 1749 u32 path_map: 4; 1750 u32 phy_map: 2; 1751 u32 band: 2; 1752 u32 type: 8; 1753 u32 rsvd: 14; 1754 1755 u32 start_time; 1756 u32 proc_time; 1757 }; 1758 1759 struct rtw89_btc_bt_smap { 1760 u32 connect: 1; 1761 u32 ble_connect: 1; 1762 u32 acl_busy: 1; 1763 u32 sco_busy: 1; 1764 u32 mesh_busy: 1; 1765 u32 inq_pag: 1; 1766 }; 1767 1768 union rtw89_btc_bt_state_map { 1769 u32 val; 1770 struct rtw89_btc_bt_smap map; 1771 }; 1772 1773 #define BTC_BT_RSSI_THMAX 4 1774 #define BTC_BT_AFH_GROUP 12 1775 #define BTC_BT_AFH_LE_GROUP 5 1776 1777 struct rtw89_btc_bt_link_info { 1778 struct rtw89_btc_u8_sta_chg profile_cnt; 1779 struct rtw89_btc_bool_sta_chg multi_link; 1780 struct rtw89_btc_bool_sta_chg relink; 1781 struct rtw89_btc_bt_hfp_desc hfp_desc; 1782 struct rtw89_btc_bt_hid_desc hid_desc; 1783 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1784 struct rtw89_btc_bt_pan_desc pan_desc; 1785 union rtw89_btc_bt_state_map status; 1786 1787 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1788 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1789 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1790 u8 afh_map[BTC_BT_AFH_GROUP]; 1791 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1792 1793 u32 role_sw: 1; 1794 u32 slave_role: 1; 1795 u32 afh_update: 1; 1796 u32 cqddr: 1; 1797 u32 rssi: 8; 1798 u32 tx_3m: 1; 1799 u32 rsvd: 19; 1800 }; 1801 1802 struct rtw89_btc_3rdcx_info { 1803 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1804 u8 hw_coex; 1805 u16 rsvd; 1806 }; 1807 1808 struct rtw89_btc_dm_emap { 1809 u32 init: 1; 1810 u32 pta_owner: 1; 1811 u32 wl_rfk_timeout: 1; 1812 u32 bt_rfk_timeout: 1; 1813 u32 wl_fw_hang: 1; 1814 u32 cycle_hang: 1; 1815 u32 w1_hang: 1; 1816 u32 b1_hang: 1; 1817 u32 tdma_no_sync: 1; 1818 u32 slot_no_sync: 1; 1819 u32 wl_slot_drift: 1; 1820 u32 bt_slot_drift: 1; 1821 u32 role_num_mismatch: 1; 1822 u32 null1_tx_late: 1; 1823 u32 bt_afh_conflict: 1; 1824 u32 bt_leafh_conflict: 1; 1825 u32 bt_slot_flood: 1; 1826 u32 wl_e2g_hang: 1; 1827 u32 wl_ver_mismatch: 1; 1828 u32 bt_ver_mismatch: 1; 1829 u32 rfe_type0: 1; 1830 u32 h2c_buffer_over: 1; 1831 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1832 u32 wl_no_sta_ntfy: 1; 1833 1834 u32 h2c_bmap_mismatch: 1; 1835 u32 c2h_bmap_mismatch: 1; 1836 u32 h2c_struct_invalid: 1; 1837 u32 c2h_struct_invalid: 1; 1838 u32 h2c_c2h_buffer_mismatch: 1; 1839 }; 1840 1841 union rtw89_btc_dm_error_map { 1842 u32 val; 1843 struct rtw89_btc_dm_emap map; 1844 }; 1845 1846 struct rtw89_btc_rf_para { 1847 u32 tx_pwr_freerun; 1848 u32 rx_gain_freerun; 1849 u32 tx_pwr_perpkt; 1850 u32 rx_gain_perpkt; 1851 }; 1852 1853 struct rtw89_btc_wl_nhm { 1854 u8 instant_wl_nhm_dbm; 1855 u8 instant_wl_nhm_per_mhz; 1856 u16 valid_record_times; 1857 s8 record_pwr[16]; 1858 u8 record_ratio[16]; 1859 s8 pwr; /* dbm_per_MHz */ 1860 u8 ratio; 1861 u8 current_status; 1862 u8 refresh; 1863 bool start_flag; 1864 s8 pwr_max; 1865 s8 pwr_min; 1866 }; 1867 1868 struct rtw89_btc_wl_info { 1869 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1870 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1871 struct rtw89_btc_wl_rfk_info rfk_info; 1872 struct rtw89_btc_wl_ver_info ver_info; 1873 struct rtw89_btc_wl_afh_info afh_info; 1874 struct rtw89_btc_wl_role_info role_info; 1875 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1876 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1877 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1878 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1879 struct rtw89_btc_wl_scan_info scan_info; 1880 struct rtw89_btc_wl_dbcc_info dbcc_info; 1881 struct rtw89_btc_rf_para rf_para; 1882 struct rtw89_btc_wl_nhm nhm; 1883 union rtw89_btc_wl_state_map status; 1884 1885 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1886 u8 rssi_level; 1887 u8 cn_report; 1888 u8 coex_mode; 1889 u8 pta_req_mac; 1890 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */ 1891 1892 bool is_5g_hi_channel; 1893 bool pta_reg_mac_chg; 1894 bool bg_mode; 1895 bool he_mode; 1896 bool scbd_change; 1897 bool fw_ver_mismatch; 1898 bool client_cnt_inc_2g; 1899 u32 scbd; 1900 }; 1901 1902 struct rtw89_btc_module { 1903 struct rtw89_btc_ant_info ant; 1904 u8 rfe_type; 1905 u8 cv; 1906 1907 u8 bt_solo: 1; 1908 u8 bt_pos: 1; 1909 u8 switch_type: 1; 1910 u8 wa_type: 3; 1911 1912 u8 kt_ver_adie; 1913 }; 1914 1915 struct rtw89_btc_module_v7 { 1916 u8 rfe_type; 1917 u8 kt_ver; 1918 u8 bt_solo; 1919 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1920 1921 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1922 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1923 u8 kt_ver_adie; 1924 u8 rsvd; 1925 1926 struct rtw89_btc_ant_info_v7 ant; 1927 } __packed; 1928 1929 union rtw89_btc_module_info { 1930 struct rtw89_btc_module md; 1931 struct rtw89_btc_module_v7 md_v7; 1932 }; 1933 1934 #define RTW89_BTC_DM_MAXSTEP 30 1935 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1936 1937 struct rtw89_btc_dm_step { 1938 u16 step[RTW89_BTC_DM_MAXSTEP]; 1939 u8 step_pos; 1940 bool step_ov; 1941 }; 1942 1943 struct rtw89_btc_init_info { 1944 struct rtw89_btc_module module; 1945 u8 wl_guard_ch; 1946 1947 u8 wl_only: 1; 1948 u8 wl_init_ok: 1; 1949 u8 dbcc_en: 1; 1950 u8 cx_other: 1; 1951 u8 bt_only: 1; 1952 1953 u16 rsvd; 1954 }; 1955 1956 struct rtw89_btc_init_info_v7 { 1957 u8 wl_guard_ch; 1958 u8 wl_only; 1959 u8 wl_init_ok; 1960 u8 rsvd3; 1961 1962 u8 cx_other; 1963 u8 bt_only; 1964 u8 pta_mode; 1965 u8 pta_direction; 1966 1967 struct rtw89_btc_module_v7 module; 1968 } __packed; 1969 1970 union rtw89_btc_init_info_u { 1971 struct rtw89_btc_init_info init; 1972 struct rtw89_btc_init_info_v7 init_v7; 1973 }; 1974 1975 struct rtw89_btc_wl_tx_limit_para { 1976 u16 enable; 1977 u32 tx_time; /* unit: us */ 1978 u16 tx_retry; 1979 }; 1980 1981 enum rtw89_btc_bt_scan_type { 1982 BTC_SCAN_INQ = 0, 1983 BTC_SCAN_PAGE, 1984 BTC_SCAN_BLE, 1985 BTC_SCAN_INIT, 1986 BTC_SCAN_TV, 1987 BTC_SCAN_ADV, 1988 BTC_SCAN_MAX1, 1989 }; 1990 1991 enum rtw89_btc_ble_scan_type { 1992 CXSCAN_BG = 0, 1993 CXSCAN_INIT, 1994 CXSCAN_LE, 1995 CXSCAN_MAX 1996 }; 1997 1998 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1999 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2000 2001 struct rtw89_btc_bt_scan_info_v1 { 2002 __le16 win; 2003 __le16 intvl; 2004 __le32 flags; 2005 } __packed; 2006 2007 struct rtw89_btc_bt_scan_info_v2 { 2008 __le16 win; 2009 __le16 intvl; 2010 } __packed; 2011 2012 struct rtw89_btc_fbtc_btscan_v1 { 2013 u8 fver; /* btc_ver::fcxbtscan */ 2014 u8 rsvd; 2015 __le16 rsvd2; 2016 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2017 } __packed; 2018 2019 struct rtw89_btc_fbtc_btscan_v2 { 2020 u8 fver; /* btc_ver::fcxbtscan */ 2021 u8 type; 2022 __le16 rsvd2; 2023 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2024 } __packed; 2025 2026 struct rtw89_btc_fbtc_btscan_v7 { 2027 u8 fver; /* btc_ver::fcxbtscan */ 2028 u8 type; 2029 u8 rsvd0; 2030 u8 rsvd1; 2031 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2032 } __packed; 2033 2034 union rtw89_btc_fbtc_btscan { 2035 struct rtw89_btc_fbtc_btscan_v1 v1; 2036 struct rtw89_btc_fbtc_btscan_v2 v2; 2037 struct rtw89_btc_fbtc_btscan_v7 v7; 2038 }; 2039 2040 struct rtw89_btc_bt_info { 2041 struct rtw89_btc_bt_link_info link_info; 2042 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2043 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2044 struct rtw89_btc_bt_ver_info ver_info; 2045 struct rtw89_btc_bool_sta_chg enable; 2046 struct rtw89_btc_bool_sta_chg inq_pag; 2047 struct rtw89_btc_rf_para rf_para; 2048 union rtw89_btc_bt_rfk_info_map rfk_info; 2049 2050 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2051 u8 rssi_level; 2052 2053 u32 scbd; 2054 u32 feature; 2055 2056 u32 mbx_avl: 1; 2057 u32 whql_test: 1; 2058 u32 igno_wl: 1; 2059 u32 reinit: 1; 2060 u32 ble_scan_en: 1; 2061 u32 btg_type: 1; 2062 u32 inq: 1; 2063 u32 pag: 1; 2064 u32 run_patch_code: 1; 2065 u32 hi_lna_rx: 1; 2066 u32 scan_rx_low_pri: 1; 2067 u32 scan_info_update: 1; 2068 u32 lna_constrain: 3; 2069 u32 rsvd: 17; 2070 }; 2071 2072 struct rtw89_btc_cx { 2073 struct rtw89_btc_wl_info wl; 2074 struct rtw89_btc_bt_info bt; 2075 struct rtw89_btc_3rdcx_info other; 2076 u32 state_map; 2077 u32 cnt_bt[BTC_BCNT_NUM]; 2078 u32 cnt_wl[BTC_WCNT_NUM]; 2079 }; 2080 2081 struct rtw89_btc_fbtc_tdma { 2082 u8 type; /* btc_ver::fcxtdma */ 2083 u8 rxflctrl; 2084 u8 txpause; 2085 u8 wtgle_n; 2086 u8 leak_n; 2087 u8 ext_ctrl; 2088 u8 rxflctrl_role; 2089 u8 option_ctrl; 2090 } __packed; 2091 2092 struct rtw89_btc_fbtc_tdma_v3 { 2093 u8 fver; /* btc_ver::fcxtdma */ 2094 u8 rsvd; 2095 __le16 rsvd1; 2096 struct rtw89_btc_fbtc_tdma tdma; 2097 } __packed; 2098 2099 union rtw89_btc_fbtc_tdma_le32 { 2100 struct rtw89_btc_fbtc_tdma v1; 2101 struct rtw89_btc_fbtc_tdma_v3 v3; 2102 }; 2103 2104 #define CXMREG_MAX 30 2105 #define CXMREG_MAX_V2 20 2106 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2107 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2108 2109 enum rtw89_btc_bt_sta_counter { 2110 BTC_BCNT_RFK_REQ = 0, 2111 BTC_BCNT_RFK_GO = 1, 2112 BTC_BCNT_RFK_REJECT = 2, 2113 BTC_BCNT_RFK_FAIL = 3, 2114 BTC_BCNT_RFK_TIMEOUT = 4, 2115 BTC_BCNT_HI_TX = 5, 2116 BTC_BCNT_HI_RX = 6, 2117 BTC_BCNT_LO_TX = 7, 2118 BTC_BCNT_LO_RX = 8, 2119 BTC_BCNT_POLLUTED = 9, 2120 BTC_BCNT_STA_MAX 2121 }; 2122 2123 enum rtw89_btc_bt_sta_counter_v105 { 2124 BTC_BCNT_RFK_REQ_V105 = 0, 2125 BTC_BCNT_HI_TX_V105 = 1, 2126 BTC_BCNT_HI_RX_V105 = 2, 2127 BTC_BCNT_LO_TX_V105 = 3, 2128 BTC_BCNT_LO_RX_V105 = 4, 2129 BTC_BCNT_POLLUTED_V105 = 5, 2130 BTC_BCNT_STA_MAX_V105 2131 }; 2132 2133 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2134 u16 fver; /* btc_ver::fcxbtcrpt */ 2135 u16 rpt_cnt; /* tmr counters */ 2136 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2137 u32 wl_fw_cx_offload; 2138 u32 wl_fw_ver; 2139 u32 rpt_enable; 2140 u32 rpt_para; /* ms */ 2141 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2142 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2143 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2144 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2145 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2146 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2147 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2148 u32 c2h_cnt; /* fw send c2h counter */ 2149 u32 h2c_cnt; /* fw recv h2c counter */ 2150 } __packed; 2151 2152 struct rtw89_btc_fbtc_rpt_ctrl_info { 2153 __le32 cnt; /* fw report counter */ 2154 __le32 en; /* report map */ 2155 __le32 para; /* not used */ 2156 2157 __le32 cnt_c2h; /* fw send c2h counter */ 2158 __le32 cnt_h2c; /* fw recv h2c counter */ 2159 __le32 len_c2h; /* The total length of the last C2H */ 2160 2161 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2162 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2163 } __packed; 2164 2165 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2166 __le32 cx_ver; /* match which driver's coex version */ 2167 __le32 fw_ver; 2168 __le32 en; /* report map */ 2169 2170 __le16 cnt; /* fw report counter */ 2171 __le16 cnt_c2h; /* fw send c2h counter */ 2172 __le16 cnt_h2c; /* fw recv h2c counter */ 2173 __le16 len_c2h; /* The total length of the last C2H */ 2174 2175 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2176 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2177 } __packed; 2178 2179 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2180 __le16 cnt; /* fw report counter */ 2181 __le16 cnt_c2h; /* fw send c2h counter */ 2182 __le16 cnt_h2c; /* fw recv h2c counter */ 2183 __le16 len_c2h; /* The total length of the last C2H */ 2184 2185 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2186 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2187 2188 __le32 cx_ver; /* match which driver's coex version */ 2189 __le32 fw_ver; 2190 __le32 en; /* report map */ 2191 } __packed; 2192 2193 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2194 __le32 cx_ver; /* match which driver's coex version */ 2195 __le32 cx_offload; 2196 __le32 fw_ver; 2197 } __packed; 2198 2199 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2200 __le32 cnt_empty; /* a2dp empty count */ 2201 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2202 __le32 cnt_tx; 2203 __le32 cnt_ack; 2204 __le32 cnt_nack; 2205 } __packed; 2206 2207 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2208 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2209 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2210 __le32 cnt_recv; /* fw recv mailbox counter */ 2211 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2212 } __packed; 2213 2214 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2215 u8 fver; 2216 u8 rsvd; 2217 __le16 rsvd1; 2218 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2219 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2220 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2221 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2222 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2223 } __packed; 2224 2225 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2226 u8 fver; 2227 u8 rsvd; 2228 __le16 rsvd1; 2229 2230 u8 gnt_val[RTW89_PHY_MAX][4]; 2231 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2232 2233 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2234 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2235 } __packed; 2236 2237 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2238 u8 fver; 2239 u8 rsvd; 2240 __le16 rsvd1; 2241 2242 u8 gnt_val[RTW89_PHY_MAX][4]; 2243 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2244 2245 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2246 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2247 } __packed; 2248 2249 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2250 u8 fver; 2251 u8 rsvd0; 2252 u8 rsvd1; 2253 u8 rsvd2; 2254 2255 u8 gnt_val[RTW89_PHY_MAX][4]; 2256 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2257 2258 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2259 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2260 } __packed; 2261 2262 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2263 u8 fver; 2264 u8 rsvd0; 2265 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2266 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2267 2268 u8 gnt_val[RTW89_PHY_MAX][4]; 2269 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2270 2271 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2272 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2273 } __packed; 2274 2275 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2276 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2277 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2278 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2279 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2280 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2281 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2282 }; 2283 2284 enum rtw89_fbtc_ext_ctrl_type { 2285 CXECTL_OFF = 0x0, /* tdma off */ 2286 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2287 CXECTL_EXT = 0x2, 2288 CXECTL_MAX 2289 }; 2290 2291 union rtw89_btc_fbtc_rxflct { 2292 u8 val; 2293 u8 type: 3; 2294 u8 tgln_n: 5; 2295 }; 2296 2297 enum rtw89_btc_cxst_state { 2298 CXST_OFF = 0x0, 2299 CXST_B2W = 0x1, 2300 CXST_W1 = 0x2, 2301 CXST_W2 = 0x3, 2302 CXST_W2B = 0x4, 2303 CXST_B1 = 0x5, 2304 CXST_B2 = 0x6, 2305 CXST_B3 = 0x7, 2306 CXST_B4 = 0x8, 2307 CXST_LK = 0x9, 2308 CXST_BLK = 0xa, 2309 CXST_E2G = 0xb, 2310 CXST_E5G = 0xc, 2311 CXST_EBT = 0xd, 2312 CXST_ENULL = 0xe, 2313 CXST_WLK = 0xf, 2314 CXST_W1FDD = 0x10, 2315 CXST_B1FDD = 0x11, 2316 CXST_MAX = 0x12, 2317 }; 2318 2319 enum rtw89_btc_cxevnt { 2320 CXEVNT_TDMA_ENTRY = 0x0, 2321 CXEVNT_WL_TMR, 2322 CXEVNT_B1_TMR, 2323 CXEVNT_B2_TMR, 2324 CXEVNT_B3_TMR, 2325 CXEVNT_B4_TMR, 2326 CXEVNT_W2B_TMR, 2327 CXEVNT_B2W_TMR, 2328 CXEVNT_BCN_EARLY, 2329 CXEVNT_A2DP_EMPTY, 2330 CXEVNT_LK_END, 2331 CXEVNT_RX_ISR, 2332 CXEVNT_RX_FC0, 2333 CXEVNT_RX_FC1, 2334 CXEVNT_BT_RELINK, 2335 CXEVNT_BT_RETRY, 2336 CXEVNT_E2G, 2337 CXEVNT_E5G, 2338 CXEVNT_EBT, 2339 CXEVNT_ENULL, 2340 CXEVNT_DRV_WLK, 2341 CXEVNT_BCN_OK, 2342 CXEVNT_BT_CHANGE, 2343 CXEVNT_EBT_EXTEND, 2344 CXEVNT_E2G_NULL1, 2345 CXEVNT_B1FDD_TMR, 2346 CXEVNT_MAX 2347 }; 2348 2349 enum { 2350 CXBCN_ALL = 0x0, 2351 CXBCN_ALL_OK, 2352 CXBCN_BT_SLOT, 2353 CXBCN_BT_OK, 2354 CXBCN_MAX 2355 }; 2356 2357 enum btc_slot_type { 2358 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2359 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2360 CXSTYPE_NUM, 2361 }; 2362 2363 enum { /* TIME */ 2364 CXT_BT = 0x0, 2365 CXT_WL = 0x1, 2366 CXT_MAX 2367 }; 2368 2369 enum { /* TIME-A2DP */ 2370 CXT_FLCTRL_OFF = 0x0, 2371 CXT_FLCTRL_ON = 0x1, 2372 CXT_FLCTRL_MAX 2373 }; 2374 2375 enum { /* STEP TYPE */ 2376 CXSTEP_NONE = 0x0, 2377 CXSTEP_EVNT = 0x1, 2378 CXSTEP_SLOT = 0x2, 2379 CXSTEP_MAX, 2380 }; 2381 2382 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2383 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2384 RPT_BT_AFH_SEQ_LE = 0x20 2385 }; 2386 2387 #define BTC_DBG_MAX1 32 2388 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2389 u8 fver; /* btc_ver::fcxgpiodbg */ 2390 u8 rsvd; 2391 __le16 rsvd2; 2392 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2393 __le32 pre_state; /* the debug signal is 1 or 0 */ 2394 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2395 } __packed; 2396 2397 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2398 u8 fver; 2399 u8 rsvd0; 2400 u8 rsvd1; 2401 u8 rsvd2; 2402 2403 u8 gpio_map[BTC_DBG_MAX1]; 2404 2405 __le32 en_map; 2406 __le32 pre_state; 2407 } __packed; 2408 2409 union rtw89_btc_fbtc_gpio_dbg { 2410 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2411 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2412 }; 2413 2414 struct rtw89_btc_fbtc_mreg_val_v1 { 2415 u8 fver; /* btc_ver::fcxmreg */ 2416 u8 reg_num; 2417 __le16 rsvd; 2418 __le32 mreg_val[CXMREG_MAX]; 2419 } __packed; 2420 2421 struct rtw89_btc_fbtc_mreg_val_v2 { 2422 u8 fver; /* btc_ver::fcxmreg */ 2423 u8 reg_num; 2424 __le16 rsvd; 2425 __le32 mreg_val[CXMREG_MAX_V2]; 2426 } __packed; 2427 2428 struct rtw89_btc_fbtc_mreg_val_v7 { 2429 u8 fver; 2430 u8 reg_num; 2431 u8 rsvd0; 2432 u8 rsvd1; 2433 __le32 mreg_val[CXMREG_MAX_V2]; 2434 } __packed; 2435 2436 union rtw89_btc_fbtc_mreg_val { 2437 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2438 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2439 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2440 }; 2441 2442 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2443 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2444 .offset = cpu_to_le32(__offset), } 2445 2446 struct rtw89_btc_fbtc_mreg { 2447 __le16 type; 2448 __le16 bytes; 2449 __le32 offset; 2450 } __packed; 2451 2452 struct rtw89_btc_fbtc_slot { 2453 __le16 dur; 2454 __le32 cxtbl; 2455 __le16 cxtype; 2456 } __packed; 2457 2458 struct rtw89_btc_fbtc_slots { 2459 u8 fver; /* btc_ver::fcxslots */ 2460 u8 tbl_num; 2461 __le16 rsvd; 2462 __le32 update_map; 2463 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2464 } __packed; 2465 2466 struct rtw89_btc_fbtc_slot_v7 { 2467 __le16 dur; /* slot duration */ 2468 __le16 cxtype; 2469 __le32 cxtbl; 2470 } __packed; 2471 2472 struct rtw89_btc_fbtc_slot_u16 { 2473 __le16 dur; /* slot duration */ 2474 __le16 cxtype; 2475 __le16 cxtbl_l16; /* coex table [15:0] */ 2476 __le16 cxtbl_h16; /* coex table [31:16] */ 2477 } __packed; 2478 2479 struct rtw89_btc_fbtc_1slot_v7 { 2480 u8 fver; 2481 u8 sid; /* slot id */ 2482 __le16 rsvd; 2483 struct rtw89_btc_fbtc_slot_v7 slot; 2484 } __packed; 2485 2486 struct rtw89_btc_fbtc_slots_v7 { 2487 u8 fver; 2488 u8 slot_cnt; 2489 u8 rsvd0; 2490 u8 rsvd1; 2491 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2492 __le32 update_map; 2493 } __packed; 2494 2495 union rtw89_btc_fbtc_slots_info { 2496 struct rtw89_btc_fbtc_slots v1; 2497 struct rtw89_btc_fbtc_slots_v7 v7; 2498 } __packed; 2499 2500 struct rtw89_btc_fbtc_step { 2501 u8 type; 2502 u8 val; 2503 __le16 difft; 2504 } __packed; 2505 2506 struct rtw89_btc_fbtc_steps_v2 { 2507 u8 fver; /* btc_ver::fcxstep */ 2508 u8 rsvd; 2509 __le16 cnt; 2510 __le16 pos_old; 2511 __le16 pos_new; 2512 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2513 } __packed; 2514 2515 struct rtw89_btc_fbtc_steps_v3 { 2516 u8 fver; 2517 u8 en; 2518 __le16 rsvd; 2519 __le32 cnt; 2520 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2521 } __packed; 2522 2523 union rtw89_btc_fbtc_steps_info { 2524 struct rtw89_btc_fbtc_steps_v2 v2; 2525 struct rtw89_btc_fbtc_steps_v3 v3; 2526 }; 2527 2528 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2529 u8 fver; /* btc_ver::fcxcysta */ 2530 u8 rsvd; 2531 __le16 cycles; /* total cycle number */ 2532 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2533 __le16 a2dpept; /* a2dp empty cnt */ 2534 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2535 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2536 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2537 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2538 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2539 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2540 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2541 __le16 tmax_a2dpept; /* max a2dp empty time */ 2542 __le16 tavg_lk; /* avg leak-slot time */ 2543 __le16 tmax_lk; /* max leak-slot time */ 2544 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2545 __le32 bcn_cnt[CXBCN_MAX]; 2546 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2547 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2548 __le32 skip_cnt; 2549 __le32 exception; 2550 __le32 except_cnt; 2551 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2552 } __packed; 2553 2554 struct rtw89_btc_fbtc_fdd_try_info { 2555 __le16 cycles[CXT_FLCTRL_MAX]; 2556 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2557 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2558 } __packed; 2559 2560 struct rtw89_btc_fbtc_cycle_time_info { 2561 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2562 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2563 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2564 } __packed; 2565 2566 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2567 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2568 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2569 } __packed; 2570 2571 struct rtw89_btc_fbtc_a2dp_trx_stat { 2572 u8 empty_cnt; 2573 u8 retry_cnt; 2574 u8 tx_rate; 2575 u8 tx_cnt; 2576 u8 ack_cnt; 2577 u8 nack_cnt; 2578 u8 rsvd1; 2579 u8 rsvd2; 2580 } __packed; 2581 2582 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2583 u8 empty_cnt; 2584 u8 retry_cnt; 2585 u8 tx_rate; 2586 u8 tx_cnt; 2587 u8 ack_cnt; 2588 u8 nack_cnt; 2589 u8 no_empty_cnt; 2590 u8 rsvd; 2591 } __packed; 2592 2593 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2594 __le16 cnt; /* a2dp empty cnt */ 2595 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2596 __le16 tavg; /* avg a2dp empty time */ 2597 __le16 tmax; /* max a2dp empty time */ 2598 } __packed; 2599 2600 struct rtw89_btc_fbtc_cycle_leak_info { 2601 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2602 __le16 tavg; /* avg leak-slot time */ 2603 __le16 tmax; /* max leak-slot time */ 2604 } __packed; 2605 2606 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2607 __le16 tavg; 2608 __le16 tamx; 2609 __le32 cnt_rximr; 2610 } __packed; 2611 2612 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2613 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2614 2615 struct rtw89_btc_fbtc_cycle_fddt_info { 2616 __le16 train_cycle; 2617 __le16 tp; 2618 2619 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2620 s8 bt_tx_power; /* decrease Tx power (dB) */ 2621 s8 bt_rx_gain; /* LNA constrain level */ 2622 u8 no_empty_cnt; 2623 2624 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2625 u8 cn; /* condition_num */ 2626 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2627 u8 train_result; /* refer to enum btc_fddt_check_map */ 2628 } __packed; 2629 2630 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2631 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2632 2633 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2634 __le16 train_cycle; 2635 __le16 tp; 2636 2637 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2638 s8 bt_tx_power; /* decrease Tx power (dB) */ 2639 s8 bt_rx_gain; /* LNA constrain level */ 2640 u8 no_empty_cnt; 2641 2642 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2643 u8 cn; /* condition_num */ 2644 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2645 u8 train_result; /* refer to enum btc_fddt_check_map */ 2646 } __packed; 2647 2648 struct rtw89_btc_fbtc_fddt_cell_status { 2649 s8 wl_tx_pwr; 2650 s8 bt_tx_pwr; 2651 s8 bt_rx_gain; 2652 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2653 } __packed; 2654 2655 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2656 u8 fver; 2657 u8 rsvd; 2658 __le16 cycles; /* total cycle number */ 2659 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2660 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2661 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2662 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2663 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2664 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2665 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2666 __le32 bcn_cnt[CXBCN_MAX]; 2667 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2668 __le32 skip_cnt; 2669 __le32 except_cnt; 2670 __le32 except_map; 2671 } __packed; 2672 2673 #define FDD_TRAIN_WL_DIRECTION 2 2674 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2675 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2676 2677 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2678 u8 fver; 2679 u8 rsvd; 2680 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2681 u8 except_cnt; 2682 2683 __le16 skip_cnt; 2684 __le16 cycles; /* total cycle number */ 2685 2686 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2687 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2688 __le16 bcn_cnt[CXBCN_MAX]; 2689 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2690 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2691 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2692 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2693 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2694 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2695 [FDD_TRAIN_WL_RSSI_LEVEL] 2696 [FDD_TRAIN_BT_RSSI_LEVEL]; 2697 __le32 except_map; 2698 } __packed; 2699 2700 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2701 u8 fver; 2702 u8 rsvd; 2703 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2704 u8 except_cnt; 2705 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2706 2707 __le16 skip_cnt; 2708 __le16 cycles; /* total cycle number */ 2709 2710 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2711 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2712 __le16 bcn_cnt[CXBCN_MAX]; 2713 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2714 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2715 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2716 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2717 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2718 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2719 [FDD_TRAIN_WL_RSSI_LEVEL] 2720 [FDD_TRAIN_BT_RSSI_LEVEL]; 2721 __le32 except_map; 2722 } __packed; 2723 2724 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2725 u8 fver; 2726 u8 rsvd; 2727 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2728 u8 except_cnt; 2729 2730 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2731 2732 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2733 2734 __le16 skip_cnt; 2735 __le16 cycles; /* total cycle number */ 2736 2737 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2738 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2739 __le16 bcn_cnt[CXBCN_MAX]; 2740 2741 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2742 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2743 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2744 2745 __le32 except_map; 2746 } __packed; 2747 2748 union rtw89_btc_fbtc_cysta_info { 2749 struct rtw89_btc_fbtc_cysta_v2 v2; 2750 struct rtw89_btc_fbtc_cysta_v3 v3; 2751 struct rtw89_btc_fbtc_cysta_v4 v4; 2752 struct rtw89_btc_fbtc_cysta_v5 v5; 2753 struct rtw89_btc_fbtc_cysta_v7 v7; 2754 }; 2755 2756 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2757 u8 fver; /* btc_ver::fcxnullsta */ 2758 u8 rsvd; 2759 __le16 rsvd2; 2760 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2761 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2762 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2763 } __packed; 2764 2765 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2766 u8 fver; /* btc_ver::fcxnullsta */ 2767 u8 rsvd; 2768 __le16 rsvd2; 2769 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2770 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2771 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2772 } __packed; 2773 2774 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2775 u8 fver; 2776 u8 rsvd0; 2777 u8 rsvd1; 2778 u8 rsvd2; 2779 2780 __le32 tmax[2]; 2781 __le32 tavg[2]; 2782 __le32 result[2][5]; 2783 } __packed; 2784 2785 union rtw89_btc_fbtc_cynullsta_info { 2786 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2787 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2788 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2789 }; 2790 2791 struct rtw89_btc_fbtc_btver_v1 { 2792 u8 fver; /* btc_ver::fcxbtver */ 2793 u8 rsvd; 2794 __le16 rsvd2; 2795 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2796 __le32 fw_ver; 2797 __le32 feature; 2798 } __packed; 2799 2800 struct rtw89_btc_fbtc_btver_v7 { 2801 u8 fver; 2802 u8 rsvd0; 2803 u8 rsvd1; 2804 u8 rsvd2; 2805 2806 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2807 __le32 fw_ver; 2808 __le32 feature; 2809 } __packed; 2810 2811 union rtw89_btc_fbtc_btver { 2812 struct rtw89_btc_fbtc_btver_v1 v1; 2813 struct rtw89_btc_fbtc_btver_v7 v7; 2814 } __packed; 2815 2816 struct rtw89_btc_fbtc_btafh { 2817 u8 fver; /* btc_ver::fcxbtafh */ 2818 u8 rsvd; 2819 __le16 rsvd2; 2820 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2821 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2822 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2823 } __packed; 2824 2825 struct rtw89_btc_fbtc_btafh_v2 { 2826 u8 fver; /* btc_ver::fcxbtafh */ 2827 u8 rsvd; 2828 u8 rsvd2; 2829 u8 map_type; 2830 u8 afh_l[4]; 2831 u8 afh_m[4]; 2832 u8 afh_h[4]; 2833 u8 afh_le_a[4]; 2834 u8 afh_le_b[4]; 2835 } __packed; 2836 2837 struct rtw89_btc_fbtc_btafh_v7 { 2838 u8 fver; 2839 u8 map_type; 2840 u8 rsvd0; 2841 u8 rsvd1; 2842 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2843 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2844 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2845 u8 afh_le_a[4]; 2846 u8 afh_le_b[4]; 2847 } __packed; 2848 2849 struct rtw89_btc_fbtc_btdevinfo { 2850 u8 fver; /* btc_ver::fcxbtdevinfo */ 2851 u8 rsvd; 2852 __le16 vendor_id; 2853 __le32 dev_name; /* only 24 bits valid */ 2854 __le32 flush_time; 2855 } __packed; 2856 2857 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2858 struct rtw89_btc_rf_trx_para { 2859 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2860 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2861 u8 bt_tx_power; /* decrease Tx power (dB) */ 2862 u8 bt_rx_gain; /* LNA constrain level */ 2863 }; 2864 2865 struct rtw89_btc_trx_info { 2866 u8 tx_lvl; 2867 u8 rx_lvl; 2868 u8 wl_rssi; 2869 u8 bt_rssi; 2870 2871 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2872 s8 rx_gain; /* rx gain table index (TBD.) */ 2873 s8 bt_tx_power; /* decrease Tx power (dB) */ 2874 s8 bt_rx_gain; /* LNA constrain level */ 2875 2876 u8 cn; /* condition_num */ 2877 s8 nhm; 2878 u8 bt_profile; 2879 u8 rsvd2; 2880 2881 u16 tx_rate; 2882 u16 rx_rate; 2883 2884 u32 tx_tp; 2885 u32 rx_tp; 2886 u32 rx_err_ratio; 2887 }; 2888 2889 union rtw89_btc_fbtc_slot_u { 2890 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2891 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2892 }; 2893 2894 struct rtw89_btc_dm { 2895 union rtw89_btc_fbtc_slot_u slot; 2896 union rtw89_btc_fbtc_slot_u slot_now; 2897 struct rtw89_btc_fbtc_tdma tdma; 2898 struct rtw89_btc_fbtc_tdma tdma_now; 2899 struct rtw89_mac_ax_coex_gnt gnt; 2900 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2901 struct rtw89_btc_rf_trx_para rf_trx_para; 2902 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2903 struct rtw89_btc_dm_step dm_step; 2904 struct rtw89_btc_wl_scc_ctrl wl_scc; 2905 struct rtw89_btc_trx_info trx_info; 2906 union rtw89_btc_dm_error_map error; 2907 u32 cnt_dm[BTC_DCNT_NUM]; 2908 u32 cnt_notify[BTC_NCNT_NUM]; 2909 2910 u32 update_slot_map; 2911 u32 set_ant_path; 2912 u32 e2g_slot_limit; 2913 u32 e2g_slot_nulltx_time; 2914 2915 u32 wl_only: 1; 2916 u32 wl_fw_cx_offload: 1; 2917 u32 freerun: 1; 2918 u32 fddt_train: 1; 2919 u32 wl_ps_ctrl: 2; 2920 u32 wl_mimo_ps: 1; 2921 u32 leak_ap: 1; 2922 u32 noisy_level: 3; 2923 u32 coex_info_map: 8; 2924 u32 bt_only: 1; 2925 u32 wl_btg_rx: 2; 2926 u32 trx_para_level: 8; 2927 u32 wl_stb_chg: 1; 2928 u32 pta_owner: 1; 2929 2930 u32 tdma_instant_excute: 1; 2931 u32 wl_btg_rx_rb: 2; 2932 2933 u16 slot_dur[CXST_MAX]; 2934 u16 bt_slot_flood; 2935 2936 u8 run_reason; 2937 u8 run_action; 2938 2939 u8 wl_pre_agc: 2; 2940 u8 wl_lna2: 1; 2941 u8 freerun_chk: 1; 2942 u8 wl_pre_agc_rb: 2; 2943 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2944 u8 slot_req_more: 1; 2945 }; 2946 2947 struct rtw89_btc_ctrl { 2948 u32 manual: 1; 2949 u32 igno_bt: 1; 2950 u32 always_freerun: 1; 2951 u32 trace_step: 16; 2952 u32 rsvd: 12; 2953 }; 2954 2955 struct rtw89_btc_ctrl_v7 { 2956 u8 manual; 2957 u8 igno_bt; 2958 u8 always_freerun; 2959 u8 rsvd; 2960 } __packed; 2961 2962 union rtw89_btc_ctrl_list { 2963 struct rtw89_btc_ctrl ctrl; 2964 struct rtw89_btc_ctrl_v7 ctrl_v7; 2965 }; 2966 2967 struct rtw89_btc_dbg { 2968 /* cmd "rb" */ 2969 bool rb_done; 2970 u32 rb_val; 2971 }; 2972 2973 enum rtw89_btc_btf_fw_event { 2974 BTF_EVNT_RPT = 0, 2975 BTF_EVNT_BT_INFO = 1, 2976 BTF_EVNT_BT_SCBD = 2, 2977 BTF_EVNT_BT_REG = 3, 2978 BTF_EVNT_CX_RUNINFO = 4, 2979 BTF_EVNT_BT_PSD = 5, 2980 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 2981 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 2982 BTF_EVNT_BUF_OVERFLOW, 2983 BTF_EVNT_C2H_LOOPBACK, 2984 BTF_EVNT_MAX, 2985 }; 2986 2987 enum btf_fw_event_report { 2988 BTC_RPT_TYPE_CTRL = 0x0, 2989 BTC_RPT_TYPE_TDMA, 2990 BTC_RPT_TYPE_SLOT, 2991 BTC_RPT_TYPE_CYSTA, 2992 BTC_RPT_TYPE_STEP, 2993 BTC_RPT_TYPE_NULLSTA, 2994 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 2995 BTC_RPT_TYPE_MREG, 2996 BTC_RPT_TYPE_GPIO_DBG, 2997 BTC_RPT_TYPE_BT_VER, 2998 BTC_RPT_TYPE_BT_SCAN, 2999 BTC_RPT_TYPE_BT_AFH, 3000 BTC_RPT_TYPE_BT_DEVICE, 3001 BTC_RPT_TYPE_TEST, 3002 BTC_RPT_TYPE_MAX = 31, 3003 3004 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3005 __BTC_RPT_TYPE_V0_MAX = 12, 3006 }; 3007 3008 enum rtw_btc_btf_reg_type { 3009 REG_MAC = 0x0, 3010 REG_BB = 0x1, 3011 REG_RF = 0x2, 3012 REG_BT_RF = 0x3, 3013 REG_BT_MODEM = 0x4, 3014 REG_BT_BLUEWIZE = 0x5, 3015 REG_BT_VENDOR = 0x6, 3016 REG_BT_LE = 0x7, 3017 REG_MAX_TYPE, 3018 }; 3019 3020 struct rtw89_btc_rpt_cmn_info { 3021 u32 rx_cnt; 3022 u32 rx_len; 3023 u32 req_len; /* expected rsp len */ 3024 u8 req_fver; /* expected rsp fver */ 3025 u8 rsp_fver; /* fver from fw */ 3026 u8 valid; 3027 } __packed; 3028 3029 union rtw89_btc_fbtc_btafh_info { 3030 struct rtw89_btc_fbtc_btafh v1; 3031 struct rtw89_btc_fbtc_btafh_v2 v2; 3032 }; 3033 3034 struct rtw89_btc_report_ctrl_state { 3035 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3036 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3037 }; 3038 3039 struct rtw89_btc_rpt_fbtc_tdma { 3040 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3041 union rtw89_btc_fbtc_tdma_le32 finfo; 3042 }; 3043 3044 struct rtw89_btc_rpt_fbtc_slots { 3045 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3046 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3047 }; 3048 3049 struct rtw89_btc_rpt_fbtc_cysta { 3050 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3051 union rtw89_btc_fbtc_cysta_info finfo; 3052 }; 3053 3054 struct rtw89_btc_rpt_fbtc_step { 3055 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3056 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3057 }; 3058 3059 struct rtw89_btc_rpt_fbtc_nullsta { 3060 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3061 union rtw89_btc_fbtc_cynullsta_info finfo; 3062 }; 3063 3064 struct rtw89_btc_rpt_fbtc_mreg { 3065 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3066 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3067 }; 3068 3069 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3070 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3071 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3072 }; 3073 3074 struct rtw89_btc_rpt_fbtc_btver { 3075 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3076 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3077 }; 3078 3079 struct rtw89_btc_rpt_fbtc_btscan { 3080 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3081 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3082 }; 3083 3084 struct rtw89_btc_rpt_fbtc_btafh { 3085 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3086 union rtw89_btc_fbtc_btafh_info finfo; 3087 }; 3088 3089 struct rtw89_btc_rpt_fbtc_btdev { 3090 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3091 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3092 }; 3093 3094 enum rtw89_btc_btfre_type { 3095 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3096 BTFRE_UNDEF_TYPE, 3097 BTFRE_EXCEPTION, 3098 BTFRE_MAX, 3099 }; 3100 3101 struct rtw89_btc_btf_fwinfo { 3102 u32 cnt_c2h; 3103 u32 cnt_h2c; 3104 u32 cnt_h2c_fail; 3105 u32 event[BTF_EVNT_MAX]; 3106 3107 u32 err[BTFRE_MAX]; 3108 u32 len_mismch; 3109 u32 fver_mismch; 3110 u32 rpt_en_map; 3111 3112 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3113 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3114 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3115 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3116 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3117 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3118 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3119 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3120 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3121 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3122 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3123 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3124 }; 3125 3126 struct rtw89_btc_ver { 3127 enum rtw89_core_chip_id chip_id; 3128 u32 fw_ver_code; 3129 3130 u8 fcxbtcrpt; 3131 u8 fcxtdma; 3132 u8 fcxslots; 3133 u8 fcxcysta; 3134 u8 fcxstep; 3135 u8 fcxnullsta; 3136 u8 fcxmreg; 3137 u8 fcxgpiodbg; 3138 u8 fcxbtver; 3139 u8 fcxbtscan; 3140 u8 fcxbtafh; 3141 u8 fcxbtdevinfo; 3142 u8 fwlrole; 3143 u8 frptmap; 3144 u8 fcxctrl; 3145 u8 fcxinit; 3146 3147 u8 fwevntrptl; 3148 u8 fwc2hfunc; 3149 u8 drvinfo_type; 3150 u16 info_buf; 3151 u8 max_role_num; 3152 }; 3153 3154 #define RTW89_BTC_POLICY_MAXLEN 512 3155 3156 struct rtw89_btc { 3157 const struct rtw89_btc_ver *ver; 3158 3159 struct rtw89_btc_cx cx; 3160 struct rtw89_btc_dm dm; 3161 union rtw89_btc_ctrl_list ctrl; 3162 union rtw89_btc_module_info mdinfo; 3163 struct rtw89_btc_btf_fwinfo fwinfo; 3164 struct rtw89_btc_dbg dbg; 3165 3166 struct work_struct eapol_notify_work; 3167 struct work_struct arp_notify_work; 3168 struct work_struct dhcp_notify_work; 3169 struct work_struct icmp_notify_work; 3170 3171 u32 bt_req_len; 3172 3173 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3174 u8 ant_type; 3175 u8 btg_pos; 3176 u16 policy_len; 3177 u16 policy_type; 3178 u32 hubmsg_cnt; 3179 bool bt_req_en; 3180 bool update_policy_force; 3181 bool lps; 3182 bool manual_ctrl; 3183 }; 3184 3185 enum rtw89_btc_hmsg { 3186 RTW89_BTC_HMSG_TMR_EN = 0x0, 3187 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3188 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3189 RTW89_BTC_HMSG_FW_EV = 0x3, 3190 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3191 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3192 3193 NUM_OF_RTW89_BTC_HMSG, 3194 }; 3195 3196 enum rtw89_ra_mode { 3197 RTW89_RA_MODE_CCK = BIT(0), 3198 RTW89_RA_MODE_OFDM = BIT(1), 3199 RTW89_RA_MODE_HT = BIT(2), 3200 RTW89_RA_MODE_VHT = BIT(3), 3201 RTW89_RA_MODE_HE = BIT(4), 3202 RTW89_RA_MODE_EHT = BIT(5), 3203 }; 3204 3205 enum rtw89_ra_report_mode { 3206 RTW89_RA_RPT_MODE_LEGACY, 3207 RTW89_RA_RPT_MODE_HT, 3208 RTW89_RA_RPT_MODE_VHT, 3209 RTW89_RA_RPT_MODE_HE, 3210 RTW89_RA_RPT_MODE_EHT, 3211 }; 3212 3213 enum rtw89_dig_noisy_level { 3214 RTW89_DIG_NOISY_LEVEL0 = -1, 3215 RTW89_DIG_NOISY_LEVEL1 = 0, 3216 RTW89_DIG_NOISY_LEVEL2 = 1, 3217 RTW89_DIG_NOISY_LEVEL3 = 2, 3218 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3219 }; 3220 3221 enum rtw89_gi_ltf { 3222 RTW89_GILTF_LGI_4XHE32 = 0, 3223 RTW89_GILTF_SGI_4XHE08 = 1, 3224 RTW89_GILTF_2XHE16 = 2, 3225 RTW89_GILTF_2XHE08 = 3, 3226 RTW89_GILTF_1XHE16 = 4, 3227 RTW89_GILTF_1XHE08 = 5, 3228 RTW89_GILTF_MAX 3229 }; 3230 3231 enum rtw89_rx_frame_type { 3232 RTW89_RX_TYPE_MGNT = 0, 3233 RTW89_RX_TYPE_CTRL = 1, 3234 RTW89_RX_TYPE_DATA = 2, 3235 RTW89_RX_TYPE_RSVD = 3, 3236 }; 3237 3238 enum rtw89_efuse_block { 3239 RTW89_EFUSE_BLOCK_SYS = 0, 3240 RTW89_EFUSE_BLOCK_RF = 1, 3241 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3242 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3243 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3244 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3245 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3246 RTW89_EFUSE_BLOCK_ADIE = 7, 3247 3248 RTW89_EFUSE_BLOCK_NUM, 3249 RTW89_EFUSE_BLOCK_IGNORE, 3250 }; 3251 3252 struct rtw89_ra_info { 3253 u8 is_dis_ra:1; 3254 /* Bit0 : CCK 3255 * Bit1 : OFDM 3256 * Bit2 : HT 3257 * Bit3 : VHT 3258 * Bit4 : HE 3259 * Bit5 : EHT 3260 */ 3261 u8 mode_ctrl:6; 3262 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3263 u8 macid; 3264 u8 dcm_cap:1; 3265 u8 er_cap:1; 3266 u8 init_rate_lv:2; 3267 u8 upd_all:1; 3268 u8 en_sgi:1; 3269 u8 ldpc_cap:1; 3270 u8 stbc_cap:1; 3271 u8 ss_num:3; 3272 u8 giltf:3; 3273 u8 upd_bw_nss_mask:1; 3274 u8 upd_mask:1; 3275 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3276 /* BFee CSI */ 3277 u8 band_num; 3278 u8 ra_csi_rate_en:1; 3279 u8 fixed_csi_rate_en:1; 3280 u8 cr_tbl_sel:1; 3281 u8 fix_giltf_en:1; 3282 u8 fix_giltf:3; 3283 u8 rsvd2:1; 3284 u8 csi_mcs_ss_idx; 3285 u8 csi_mode:2; 3286 u8 csi_gi_ltf:3; 3287 u8 csi_bw:3; 3288 }; 3289 3290 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3291 #define RTW89_PPDU_MAC_INFO_SIZE 8 3292 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3293 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3294 3295 #define RTW89_MAX_RX_AGG_NUM 64 3296 #define RTW89_MAX_TX_AGG_NUM 128 3297 3298 struct rtw89_ampdu_params { 3299 u16 agg_num; 3300 bool amsdu; 3301 }; 3302 3303 struct rtw89_ra_report { 3304 struct rate_info txrate; 3305 u32 bit_rate; 3306 u16 hw_rate; 3307 bool might_fallback_legacy; 3308 }; 3309 3310 DECLARE_EWMA(rssi, 10, 16); 3311 DECLARE_EWMA(evm, 10, 16); 3312 DECLARE_EWMA(snr, 10, 16); 3313 3314 struct rtw89_ba_cam_entry { 3315 struct list_head list; 3316 u8 tid; 3317 }; 3318 3319 #define RTW89_MAX_ADDR_CAM_NUM 128 3320 #define RTW89_MAX_BSSID_CAM_NUM 20 3321 #define RTW89_MAX_SEC_CAM_NUM 128 3322 #define RTW89_MAX_BA_CAM_NUM 24 3323 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3324 3325 struct rtw89_addr_cam_entry { 3326 u8 addr_cam_idx; 3327 u8 offset; 3328 u8 len; 3329 u8 valid : 1; 3330 u8 addr_mask : 6; 3331 u8 wapi : 1; 3332 u8 mask_sel : 2; 3333 u8 bssid_cam_idx: 6; 3334 3335 u8 sec_ent_mode; 3336 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3337 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3338 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3339 }; 3340 3341 struct rtw89_bssid_cam_entry { 3342 u8 bssid[ETH_ALEN]; 3343 u8 phy_idx; 3344 u8 bssid_cam_idx; 3345 u8 offset; 3346 u8 len; 3347 u8 valid : 1; 3348 u8 num; 3349 }; 3350 3351 struct rtw89_sec_cam_entry { 3352 u8 sec_cam_idx; 3353 u8 offset; 3354 u8 len; 3355 u8 type : 4; 3356 u8 ext_key : 1; 3357 u8 spp_mode : 1; 3358 /* 256 bits */ 3359 u8 key[32]; 3360 }; 3361 3362 struct rtw89_sta_link { 3363 struct rtw89_sta *rtwsta; 3364 unsigned int link_id; 3365 3366 u8 mac_id; 3367 bool er_cap; 3368 struct rtw89_vif_link *rtwvif_link; 3369 struct rtw89_ra_info ra; 3370 struct rtw89_ra_report ra_report; 3371 int max_agg_wait; 3372 u8 prev_rssi; 3373 struct ewma_rssi avg_rssi; 3374 struct ewma_rssi rssi[RF_PATH_MAX]; 3375 struct ewma_snr avg_snr; 3376 struct ewma_evm evm_1ss; 3377 struct ewma_evm evm_min[RF_PATH_MAX]; 3378 struct ewma_evm evm_max[RF_PATH_MAX]; 3379 struct ieee80211_rx_status rx_status; 3380 u16 rx_hw_rate; 3381 __le32 htc_template; 3382 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3383 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3384 struct list_head ba_cam_list; 3385 3386 bool use_cfg_mask; 3387 struct cfg80211_bitrate_mask mask; 3388 3389 bool cctl_tx_time; 3390 u32 ampdu_max_time:4; 3391 bool cctl_tx_retry_limit; 3392 u32 data_tx_cnt_lmt:6; 3393 }; 3394 3395 struct rtw89_efuse { 3396 bool valid; 3397 bool power_k_valid; 3398 u8 xtal_cap; 3399 u8 addr[ETH_ALEN]; 3400 u8 rfe_type; 3401 char country_code[2]; 3402 }; 3403 3404 struct rtw89_phy_rate_pattern { 3405 u64 ra_mask; 3406 u16 rate; 3407 u8 ra_mode; 3408 bool enable; 3409 }; 3410 3411 struct rtw89_tx_wait_info { 3412 struct rcu_head rcu_head; 3413 struct completion completion; 3414 bool tx_done; 3415 }; 3416 3417 struct rtw89_tx_skb_data { 3418 struct rtw89_tx_wait_info __rcu *wait; 3419 u8 hci_priv[]; 3420 }; 3421 3422 #define RTW89_ROC_IDLE_TIMEOUT 500 3423 #define RTW89_ROC_TX_TIMEOUT 30 3424 enum rtw89_roc_state { 3425 RTW89_ROC_IDLE, 3426 RTW89_ROC_NORMAL, 3427 RTW89_ROC_MGMT, 3428 }; 3429 3430 struct rtw89_roc { 3431 struct ieee80211_channel chan; 3432 struct delayed_work roc_work; 3433 enum ieee80211_roc_type type; 3434 enum rtw89_roc_state state; 3435 int duration; 3436 }; 3437 3438 #define RTW89_P2P_MAX_NOA_NUM 2 3439 3440 struct rtw89_p2p_ie_head { 3441 u8 eid; 3442 u8 ie_len; 3443 u8 oui[3]; 3444 u8 oui_type; 3445 } __packed; 3446 3447 struct rtw89_noa_attr_head { 3448 u8 attr_type; 3449 __le16 attr_len; 3450 u8 index; 3451 u8 oppps_ctwindow; 3452 } __packed; 3453 3454 struct rtw89_p2p_noa_ie { 3455 struct rtw89_p2p_ie_head p2p_head; 3456 struct rtw89_noa_attr_head noa_head; 3457 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3458 } __packed; 3459 3460 struct rtw89_p2p_noa_setter { 3461 struct rtw89_p2p_noa_ie ie; 3462 u8 noa_count; 3463 u8 noa_index; 3464 }; 3465 3466 struct rtw89_vif_link { 3467 struct rtw89_vif *rtwvif; 3468 unsigned int link_id; 3469 3470 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3471 enum rtw89_chanctx_idx chanctx_idx; 3472 enum rtw89_reg_6ghz_power reg_6ghz_power; 3473 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3474 3475 u8 mac_id; 3476 u8 port; 3477 u8 mac_addr[ETH_ALEN]; 3478 u8 bssid[ETH_ALEN]; 3479 u8 phy_idx; 3480 u8 mac_idx; 3481 u8 net_type; 3482 u8 wifi_role; 3483 u8 self_role; 3484 u8 wmm; 3485 u8 bcn_hit_cond; 3486 u8 hit_rule; 3487 u8 last_noa_nr; 3488 u64 sync_bcn_tsf; 3489 bool trigger; 3490 bool lsig_txop; 3491 u8 tgt_ind; 3492 u8 frm_tgt_ind; 3493 bool wowlan_pattern; 3494 bool wowlan_uc; 3495 bool wowlan_magic; 3496 bool is_hesta; 3497 bool last_a_ctrl; 3498 bool dyn_tb_bedge_en; 3499 bool pre_pwr_diff_en; 3500 bool pwr_diff_en; 3501 u8 def_tri_idx; 3502 struct work_struct update_beacon_work; 3503 struct rtw89_addr_cam_entry addr_cam; 3504 struct rtw89_bssid_cam_entry bssid_cam; 3505 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3506 struct rtw89_phy_rate_pattern rate_pattern; 3507 struct list_head general_pkt_list; 3508 struct rtw89_p2p_noa_setter p2p_noa; 3509 }; 3510 3511 enum rtw89_lv1_rcvy_step { 3512 RTW89_LV1_RCVY_STEP_1, 3513 RTW89_LV1_RCVY_STEP_2, 3514 }; 3515 3516 struct rtw89_hci_ops { 3517 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3518 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3519 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3520 void (*reset)(struct rtw89_dev *rtwdev); 3521 int (*start)(struct rtw89_dev *rtwdev); 3522 void (*stop)(struct rtw89_dev *rtwdev); 3523 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3524 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3525 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3526 3527 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3528 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3529 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3530 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3531 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3532 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3533 3534 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3535 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3536 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3537 int (*deinit)(struct rtw89_dev *rtwdev); 3538 3539 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3540 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3541 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3542 int (*napi_poll)(struct napi_struct *napi, int budget); 3543 3544 /* Deal with locks inside recovery_start and recovery_complete callbacks 3545 * by hci instance, and handle things which need to consider under SER. 3546 * e.g. turn on/off interrupts except for the one for halt notification. 3547 */ 3548 void (*recovery_start)(struct rtw89_dev *rtwdev); 3549 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3550 3551 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3552 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3553 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3554 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3555 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3556 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3557 void (*disable_intr)(struct rtw89_dev *rtwdev); 3558 void (*enable_intr)(struct rtw89_dev *rtwdev); 3559 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3560 }; 3561 3562 struct rtw89_hci_info { 3563 const struct rtw89_hci_ops *ops; 3564 enum rtw89_hci_type type; 3565 u32 rpwm_addr; 3566 u32 cpwm_addr; 3567 bool paused; 3568 }; 3569 3570 struct rtw89_chip_ops { 3571 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3572 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3573 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3574 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3575 void (*bb_reset)(struct rtw89_dev *rtwdev, 3576 enum rtw89_phy_idx phy_idx); 3577 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3578 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3579 u32 addr, u32 mask); 3580 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3581 u32 addr, u32 mask, u32 data); 3582 void (*set_channel)(struct rtw89_dev *rtwdev, 3583 const struct rtw89_chan *chan, 3584 enum rtw89_mac_idx mac_idx, 3585 enum rtw89_phy_idx phy_idx); 3586 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3587 struct rtw89_channel_help_params *p, 3588 const struct rtw89_chan *chan, 3589 enum rtw89_mac_idx mac_idx, 3590 enum rtw89_phy_idx phy_idx); 3591 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3592 enum rtw89_efuse_block block); 3593 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3594 void (*fem_setup)(struct rtw89_dev *rtwdev); 3595 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3596 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3597 void (*rfk_init)(struct rtw89_dev *rtwdev); 3598 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3599 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3600 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3601 enum rtw89_phy_idx phy_idx, 3602 const struct rtw89_chan *chan); 3603 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3604 bool start); 3605 void (*rfk_track)(struct rtw89_dev *rtwdev); 3606 void (*power_trim)(struct rtw89_dev *rtwdev); 3607 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3608 const struct rtw89_chan *chan, 3609 enum rtw89_phy_idx phy_idx); 3610 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3611 enum rtw89_phy_idx phy_idx); 3612 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3613 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3614 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3615 enum rtw89_phy_idx phy_idx); 3616 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3617 struct rtw89_rx_phy_ppdu *phy_ppdu, 3618 struct ieee80211_rx_status *status); 3619 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3620 struct rtw89_rx_phy_ppdu *phy_ppdu); 3621 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3622 enum rtw89_phy_idx phy_idx); 3623 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3624 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3625 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3626 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3627 enum rtw89_phy_idx phy_idx); 3628 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3629 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3630 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3631 struct rtw89_rx_desc_info *desc_info, 3632 u8 *data, u32 data_offset); 3633 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3634 struct rtw89_tx_desc_info *desc_info, 3635 void *txdesc); 3636 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3637 struct rtw89_tx_desc_info *desc_info, 3638 void *txdesc); 3639 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3640 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3641 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3642 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3643 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3644 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3645 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3646 struct rtw89_vif_link *rtwvif_link, 3647 struct rtw89_sta_link *rtwsta_link); 3648 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3649 struct rtw89_vif_link *rtwvif_link, 3650 struct rtw89_sta_link *rtwsta_link); 3651 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3652 struct rtw89_vif_link *rtwvif_link, 3653 struct rtw89_sta_link *rtwsta_link); 3654 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3655 struct rtw89_vif_link *rtwvif_link, 3656 struct rtw89_sta_link *rtwsta_link); 3657 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3658 struct rtw89_vif_link *rtwvif_link, 3659 struct rtw89_sta_link *rtwsta_link); 3660 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3661 struct rtw89_vif_link *rtwvif_link); 3662 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3663 struct rtw89_vif_link *rtwvif_link, 3664 struct rtw89_sta_link *rtwsta_link, 3665 bool valid, struct ieee80211_ampdu_params *params); 3666 3667 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3668 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3669 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3670 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3671 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3672 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3673 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3674 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3675 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3676 }; 3677 3678 enum rtw89_dma_ch { 3679 RTW89_DMA_ACH0 = 0, 3680 RTW89_DMA_ACH1 = 1, 3681 RTW89_DMA_ACH2 = 2, 3682 RTW89_DMA_ACH3 = 3, 3683 RTW89_DMA_ACH4 = 4, 3684 RTW89_DMA_ACH5 = 5, 3685 RTW89_DMA_ACH6 = 6, 3686 RTW89_DMA_ACH7 = 7, 3687 RTW89_DMA_B0MG = 8, 3688 RTW89_DMA_B0HI = 9, 3689 RTW89_DMA_B1MG = 10, 3690 RTW89_DMA_B1HI = 11, 3691 RTW89_DMA_H2C = 12, 3692 RTW89_DMA_CH_NUM = 13 3693 }; 3694 3695 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3696 3697 enum rtw89_mlo_dbcc_mode { 3698 MLO_DBCC_NOT_SUPPORT = 1, 3699 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3700 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3701 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3702 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3703 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3704 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3705 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3706 DBCC_LEGACY = 0xffffffff, 3707 }; 3708 3709 enum rtw89_scan_be_operation { 3710 RTW89_SCAN_OP_STOP, 3711 RTW89_SCAN_OP_START, 3712 RTW89_SCAN_OP_SETPARM, 3713 RTW89_SCAN_OP_GETRPT, 3714 RTW89_SCAN_OP_NUM 3715 }; 3716 3717 enum rtw89_scan_be_mode { 3718 RTW89_SCAN_MODE_SA, 3719 RTW89_SCAN_MODE_MACC, 3720 RTW89_SCAN_MODE_NUM 3721 }; 3722 3723 enum rtw89_scan_be_opmode { 3724 RTW89_SCAN_OPMODE_NONE, 3725 RTW89_SCAN_OPMODE_TBTT, 3726 RTW89_SCAN_OPMODE_INTV, 3727 RTW89_SCAN_OPMODE_CNT, 3728 RTW89_SCAN_OPMODE_NUM, 3729 }; 3730 3731 struct rtw89_scan_option { 3732 bool enable; 3733 bool target_ch_mode; 3734 u8 num_macc_role; 3735 u8 num_opch; 3736 u8 repeat; 3737 u16 norm_pd; 3738 u16 slow_pd; 3739 u16 norm_cy; 3740 u8 opch_end; 3741 u16 delay; 3742 u64 prohib_chan; 3743 enum rtw89_phy_idx band; 3744 enum rtw89_scan_be_operation operation; 3745 enum rtw89_scan_be_mode scan_mode; 3746 enum rtw89_mlo_dbcc_mode mlo_mode; 3747 }; 3748 3749 enum rtw89_qta_mode { 3750 RTW89_QTA_SCC, 3751 RTW89_QTA_DBCC, 3752 RTW89_QTA_DLFW, 3753 RTW89_QTA_WOW, 3754 3755 /* keep last */ 3756 RTW89_QTA_INVALID, 3757 }; 3758 3759 struct rtw89_hfc_ch_cfg { 3760 u16 min; 3761 u16 max; 3762 #define grp_0 0 3763 #define grp_1 1 3764 #define grp_num 2 3765 u8 grp; 3766 }; 3767 3768 struct rtw89_hfc_ch_info { 3769 u16 aval; 3770 u16 used; 3771 }; 3772 3773 struct rtw89_hfc_pub_cfg { 3774 u16 grp0; 3775 u16 grp1; 3776 u16 pub_max; 3777 u16 wp_thrd; 3778 }; 3779 3780 struct rtw89_hfc_pub_info { 3781 u16 g0_used; 3782 u16 g1_used; 3783 u16 g0_aval; 3784 u16 g1_aval; 3785 u16 pub_aval; 3786 u16 wp_aval; 3787 }; 3788 3789 struct rtw89_hfc_prec_cfg { 3790 u16 ch011_prec; 3791 u16 h2c_prec; 3792 u16 wp_ch07_prec; 3793 u16 wp_ch811_prec; 3794 u8 ch011_full_cond; 3795 u8 h2c_full_cond; 3796 u8 wp_ch07_full_cond; 3797 u8 wp_ch811_full_cond; 3798 }; 3799 3800 struct rtw89_hfc_param { 3801 bool en; 3802 bool h2c_en; 3803 u8 mode; 3804 const struct rtw89_hfc_ch_cfg *ch_cfg; 3805 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3806 struct rtw89_hfc_pub_cfg pub_cfg; 3807 struct rtw89_hfc_pub_info pub_info; 3808 struct rtw89_hfc_prec_cfg prec_cfg; 3809 }; 3810 3811 struct rtw89_hfc_param_ini { 3812 const struct rtw89_hfc_ch_cfg *ch_cfg; 3813 const struct rtw89_hfc_pub_cfg *pub_cfg; 3814 const struct rtw89_hfc_prec_cfg *prec_cfg; 3815 u8 mode; 3816 }; 3817 3818 struct rtw89_dle_size { 3819 u16 pge_size; 3820 u16 lnk_pge_num; 3821 u16 unlnk_pge_num; 3822 /* for WiFi 7 chips below */ 3823 u32 srt_ofst; 3824 }; 3825 3826 struct rtw89_wde_quota { 3827 u16 hif; 3828 u16 wcpu; 3829 u16 pkt_in; 3830 u16 cpu_io; 3831 }; 3832 3833 struct rtw89_ple_quota { 3834 u16 cma0_tx; 3835 u16 cma1_tx; 3836 u16 c2h; 3837 u16 h2c; 3838 u16 wcpu; 3839 u16 mpdu_proc; 3840 u16 cma0_dma; 3841 u16 cma1_dma; 3842 u16 bb_rpt; 3843 u16 wd_rel; 3844 u16 cpu_io; 3845 u16 tx_rpt; 3846 /* for WiFi 7 chips below */ 3847 u16 h2d; 3848 }; 3849 3850 struct rtw89_rsvd_quota { 3851 u16 mpdu_info_tbl; 3852 u16 b0_csi; 3853 u16 b1_csi; 3854 u16 b0_lmr; 3855 u16 b1_lmr; 3856 u16 b0_ftm; 3857 u16 b1_ftm; 3858 u16 b0_smr; 3859 u16 b1_smr; 3860 u16 others; 3861 }; 3862 3863 struct rtw89_dle_rsvd_size { 3864 u32 srt_ofst; 3865 u32 size; 3866 }; 3867 3868 struct rtw89_dle_mem { 3869 enum rtw89_qta_mode mode; 3870 const struct rtw89_dle_size *wde_size; 3871 const struct rtw89_dle_size *ple_size; 3872 const struct rtw89_wde_quota *wde_min_qt; 3873 const struct rtw89_wde_quota *wde_max_qt; 3874 const struct rtw89_ple_quota *ple_min_qt; 3875 const struct rtw89_ple_quota *ple_max_qt; 3876 /* for WiFi 7 chips below */ 3877 const struct rtw89_rsvd_quota *rsvd_qt; 3878 const struct rtw89_dle_rsvd_size *rsvd0_size; 3879 const struct rtw89_dle_rsvd_size *rsvd1_size; 3880 }; 3881 3882 struct rtw89_reg_def { 3883 u32 addr; 3884 u32 mask; 3885 }; 3886 3887 struct rtw89_reg2_def { 3888 u32 addr; 3889 u32 data; 3890 }; 3891 3892 struct rtw89_reg3_def { 3893 u32 addr; 3894 u32 mask; 3895 u32 data; 3896 }; 3897 3898 struct rtw89_reg5_def { 3899 u8 flag; /* recognized by parsers */ 3900 u8 path; 3901 u32 addr; 3902 u32 mask; 3903 u32 data; 3904 }; 3905 3906 struct rtw89_reg_imr { 3907 u32 addr; 3908 u32 clr; 3909 u32 set; 3910 }; 3911 3912 struct rtw89_phy_table { 3913 const struct rtw89_reg2_def *regs; 3914 u32 n_regs; 3915 enum rtw89_rf_path rf_path; 3916 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3917 enum rtw89_rf_path rf_path, void *data); 3918 }; 3919 3920 struct rtw89_txpwr_table { 3921 const void *data; 3922 u32 size; 3923 void (*load)(struct rtw89_dev *rtwdev, 3924 const struct rtw89_txpwr_table *tbl); 3925 }; 3926 3927 struct rtw89_txpwr_rule_2ghz { 3928 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3929 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3930 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3931 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3932 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3933 }; 3934 3935 struct rtw89_txpwr_rule_5ghz { 3936 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3937 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3938 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3939 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3940 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3941 }; 3942 3943 struct rtw89_txpwr_rule_6ghz { 3944 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3945 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3946 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3947 [RTW89_6G_CH_NUM]; 3948 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3949 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3950 [RTW89_6G_CH_NUM]; 3951 }; 3952 3953 struct rtw89_tx_shape { 3954 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3955 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3956 }; 3957 3958 struct rtw89_rfe_parms { 3959 const struct rtw89_txpwr_table *byr_tbl; 3960 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3961 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3962 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3963 struct rtw89_tx_shape tx_shape; 3964 }; 3965 3966 struct rtw89_rfe_parms_conf { 3967 const struct rtw89_rfe_parms *rfe_parms; 3968 u8 rfe_type; 3969 }; 3970 3971 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3972 3973 struct rtw89_txpwr_conf { 3974 u8 rfe_type; 3975 u8 ent_sz; 3976 u32 num_ents; 3977 const void *data; 3978 }; 3979 3980 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 3981 const struct rtw89_txpwr_conf *conf) 3982 { 3983 u8 valid_size = min(size, conf->ent_sz); 3984 3985 memcpy(entry, cursor, valid_size); 3986 return true; 3987 } 3988 3989 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3990 3991 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3992 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 3993 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3994 (cursor) += (conf)->ent_sz) \ 3995 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 3996 3997 struct rtw89_txpwr_byrate_data { 3998 struct rtw89_txpwr_conf conf; 3999 struct rtw89_txpwr_table tbl; 4000 }; 4001 4002 struct rtw89_txpwr_lmt_2ghz_data { 4003 struct rtw89_txpwr_conf conf; 4004 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4005 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4006 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4007 }; 4008 4009 struct rtw89_txpwr_lmt_5ghz_data { 4010 struct rtw89_txpwr_conf conf; 4011 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4012 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4013 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4014 }; 4015 4016 struct rtw89_txpwr_lmt_6ghz_data { 4017 struct rtw89_txpwr_conf conf; 4018 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4019 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4020 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4021 [RTW89_6G_CH_NUM]; 4022 }; 4023 4024 struct rtw89_txpwr_lmt_ru_2ghz_data { 4025 struct rtw89_txpwr_conf conf; 4026 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4027 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4028 }; 4029 4030 struct rtw89_txpwr_lmt_ru_5ghz_data { 4031 struct rtw89_txpwr_conf conf; 4032 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4033 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4034 }; 4035 4036 struct rtw89_txpwr_lmt_ru_6ghz_data { 4037 struct rtw89_txpwr_conf conf; 4038 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4039 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4040 [RTW89_6G_CH_NUM]; 4041 }; 4042 4043 struct rtw89_tx_shape_lmt_data { 4044 struct rtw89_txpwr_conf conf; 4045 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4046 }; 4047 4048 struct rtw89_tx_shape_lmt_ru_data { 4049 struct rtw89_txpwr_conf conf; 4050 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4051 }; 4052 4053 struct rtw89_rfe_data { 4054 struct rtw89_txpwr_byrate_data byrate; 4055 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4056 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4057 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4058 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4059 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4060 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4061 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4062 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4063 struct rtw89_rfe_parms rfe_parms; 4064 }; 4065 4066 struct rtw89_page_regs { 4067 u32 hci_fc_ctrl; 4068 u32 ch_page_ctrl; 4069 u32 ach_page_ctrl; 4070 u32 ach_page_info; 4071 u32 pub_page_info3; 4072 u32 pub_page_ctrl1; 4073 u32 pub_page_ctrl2; 4074 u32 pub_page_info1; 4075 u32 pub_page_info2; 4076 u32 wp_page_ctrl1; 4077 u32 wp_page_ctrl2; 4078 u32 wp_page_info1; 4079 }; 4080 4081 struct rtw89_imr_info { 4082 u32 wdrls_imr_set; 4083 u32 wsec_imr_reg; 4084 u32 wsec_imr_set; 4085 u32 mpdu_tx_imr_set; 4086 u32 mpdu_rx_imr_set; 4087 u32 sta_sch_imr_set; 4088 u32 txpktctl_imr_b0_reg; 4089 u32 txpktctl_imr_b0_clr; 4090 u32 txpktctl_imr_b0_set; 4091 u32 txpktctl_imr_b1_reg; 4092 u32 txpktctl_imr_b1_clr; 4093 u32 txpktctl_imr_b1_set; 4094 u32 wde_imr_clr; 4095 u32 wde_imr_set; 4096 u32 ple_imr_clr; 4097 u32 ple_imr_set; 4098 u32 host_disp_imr_clr; 4099 u32 host_disp_imr_set; 4100 u32 cpu_disp_imr_clr; 4101 u32 cpu_disp_imr_set; 4102 u32 other_disp_imr_clr; 4103 u32 other_disp_imr_set; 4104 u32 bbrpt_com_err_imr_reg; 4105 u32 bbrpt_chinfo_err_imr_reg; 4106 u32 bbrpt_err_imr_set; 4107 u32 bbrpt_dfs_err_imr_reg; 4108 u32 ptcl_imr_clr; 4109 u32 ptcl_imr_set; 4110 u32 cdma_imr_0_reg; 4111 u32 cdma_imr_0_clr; 4112 u32 cdma_imr_0_set; 4113 u32 cdma_imr_1_reg; 4114 u32 cdma_imr_1_clr; 4115 u32 cdma_imr_1_set; 4116 u32 phy_intf_imr_reg; 4117 u32 phy_intf_imr_clr; 4118 u32 phy_intf_imr_set; 4119 u32 rmac_imr_reg; 4120 u32 rmac_imr_clr; 4121 u32 rmac_imr_set; 4122 u32 tmac_imr_reg; 4123 u32 tmac_imr_clr; 4124 u32 tmac_imr_set; 4125 }; 4126 4127 struct rtw89_imr_table { 4128 const struct rtw89_reg_imr *regs; 4129 u32 n_regs; 4130 }; 4131 4132 struct rtw89_xtal_info { 4133 u32 xcap_reg; 4134 u32 sc_xo_mask; 4135 u32 sc_xi_mask; 4136 }; 4137 4138 struct rtw89_rrsr_cfgs { 4139 struct rtw89_reg3_def ref_rate; 4140 struct rtw89_reg3_def rsc; 4141 }; 4142 4143 struct rtw89_rfkill_regs { 4144 struct rtw89_reg3_def pinmux; 4145 struct rtw89_reg3_def mode; 4146 }; 4147 4148 struct rtw89_dig_regs { 4149 u32 seg0_pd_reg; 4150 u32 pd_lower_bound_mask; 4151 u32 pd_spatial_reuse_en; 4152 u32 bmode_pd_reg; 4153 u32 bmode_cca_rssi_limit_en; 4154 u32 bmode_pd_lower_bound_reg; 4155 u32 bmode_rssi_nocca_low_th_mask; 4156 struct rtw89_reg_def p0_lna_init; 4157 struct rtw89_reg_def p1_lna_init; 4158 struct rtw89_reg_def p0_tia_init; 4159 struct rtw89_reg_def p1_tia_init; 4160 struct rtw89_reg_def p0_rxb_init; 4161 struct rtw89_reg_def p1_rxb_init; 4162 struct rtw89_reg_def p0_p20_pagcugc_en; 4163 struct rtw89_reg_def p0_s20_pagcugc_en; 4164 struct rtw89_reg_def p1_p20_pagcugc_en; 4165 struct rtw89_reg_def p1_s20_pagcugc_en; 4166 }; 4167 4168 struct rtw89_edcca_regs { 4169 u32 edcca_level; 4170 u32 edcca_mask; 4171 u32 edcca_p_mask; 4172 u32 ppdu_level; 4173 u32 ppdu_mask; 4174 u32 rpt_a; 4175 u32 rpt_b; 4176 u32 rpt_sel; 4177 u32 rpt_sel_mask; 4178 u32 rpt_sel_be; 4179 u32 rpt_sel_be_mask; 4180 u32 tx_collision_t2r_st; 4181 u32 tx_collision_t2r_st_mask; 4182 }; 4183 4184 struct rtw89_phy_ul_tb_info { 4185 bool dyn_tb_tri_en; 4186 u8 def_if_bandedge; 4187 }; 4188 4189 struct rtw89_antdiv_stats { 4190 struct ewma_rssi cck_rssi_avg; 4191 struct ewma_rssi ofdm_rssi_avg; 4192 struct ewma_rssi non_legacy_rssi_avg; 4193 u16 pkt_cnt_cck; 4194 u16 pkt_cnt_ofdm; 4195 u16 pkt_cnt_non_legacy; 4196 u32 evm; 4197 }; 4198 4199 struct rtw89_antdiv_info { 4200 struct rtw89_antdiv_stats target_stats; 4201 struct rtw89_antdiv_stats main_stats; 4202 struct rtw89_antdiv_stats aux_stats; 4203 u8 training_count; 4204 u8 rssi_pre; 4205 bool get_stats; 4206 }; 4207 4208 enum rtw89_chanctx_state { 4209 RTW89_CHANCTX_STATE_MCC_START, 4210 RTW89_CHANCTX_STATE_MCC_STOP, 4211 }; 4212 4213 enum rtw89_chanctx_callbacks { 4214 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4215 RTW89_CHANCTX_CALLBACK_RFK, 4216 4217 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4218 }; 4219 4220 struct rtw89_chanctx_listener { 4221 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4222 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4223 }; 4224 4225 struct rtw89_chip_info { 4226 enum rtw89_core_chip_id chip_id; 4227 enum rtw89_chip_gen chip_gen; 4228 const struct rtw89_chip_ops *ops; 4229 const struct rtw89_mac_gen_def *mac_def; 4230 const struct rtw89_phy_gen_def *phy_def; 4231 const char *fw_basename; 4232 u8 fw_format_max; 4233 bool try_ce_fw; 4234 u8 bbmcu_nr; 4235 u32 needed_fw_elms; 4236 u32 fifo_size; 4237 bool small_fifo_size; 4238 u32 dle_scc_rsvd_size; 4239 u16 max_amsdu_limit; 4240 bool dis_2g_40m_ul_ofdma; 4241 u32 rsvd_ple_ofst; 4242 const struct rtw89_hfc_param_ini *hfc_param_ini; 4243 const struct rtw89_dle_mem *dle_mem; 4244 u8 wde_qempty_acq_grpnum; 4245 u8 wde_qempty_mgq_grpsel; 4246 u32 rf_base_addr[2]; 4247 u8 support_macid_num; 4248 u8 support_link_num; 4249 u8 support_chanctx_num; 4250 u8 support_bands; 4251 u16 support_bandwidths; 4252 bool support_unii4; 4253 bool support_rnr; 4254 bool ul_tb_waveform_ctrl; 4255 bool ul_tb_pwr_diff; 4256 bool hw_sec_hdr; 4257 bool hw_mgmt_tx_encrypt; 4258 u8 rf_path_num; 4259 u8 tx_nss; 4260 u8 rx_nss; 4261 u8 acam_num; 4262 u8 bcam_num; 4263 u8 scam_num; 4264 u8 bacam_num; 4265 u8 bacam_dynamic_num; 4266 enum rtw89_bacam_ver bacam_ver; 4267 u8 ppdu_max_usr; 4268 4269 u8 sec_ctrl_efuse_size; 4270 u32 physical_efuse_size; 4271 u32 logical_efuse_size; 4272 u32 limit_efuse_size; 4273 u32 dav_phy_efuse_size; 4274 u32 dav_log_efuse_size; 4275 u32 phycap_addr; 4276 u32 phycap_size; 4277 const struct rtw89_efuse_block_cfg *efuse_blocks; 4278 4279 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4280 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4281 const struct rtw89_phy_table *bb_table; 4282 const struct rtw89_phy_table *bb_gain_table; 4283 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4284 const struct rtw89_phy_table *nctl_table; 4285 const struct rtw89_rfk_tbl *nctl_post_table; 4286 const struct rtw89_phy_dig_gain_table *dig_table; 4287 const struct rtw89_dig_regs *dig_regs; 4288 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4289 4290 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4291 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4292 const struct rtw89_rfe_parms *dflt_parms; 4293 const struct rtw89_chanctx_listener *chanctx_listener; 4294 4295 u8 txpwr_factor_rf; 4296 u8 txpwr_factor_mac; 4297 4298 u32 para_ver; 4299 u32 wlcx_desired; 4300 u8 btcx_desired; 4301 u8 scbd; 4302 u8 mailbox; 4303 4304 u8 afh_guard_ch; 4305 const u8 *wl_rssi_thres; 4306 const u8 *bt_rssi_thres; 4307 u8 rssi_tol; 4308 4309 u8 mon_reg_num; 4310 const struct rtw89_btc_fbtc_mreg *mon_reg; 4311 u8 rf_para_ulink_num; 4312 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4313 u8 rf_para_dlink_num; 4314 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4315 u8 ps_mode_supported; 4316 u8 low_power_hci_modes; 4317 4318 u32 h2c_cctl_func_id; 4319 u32 hci_func_en_addr; 4320 u32 h2c_desc_size; 4321 u32 txwd_body_size; 4322 u32 txwd_info_size; 4323 u32 h2c_ctrl_reg; 4324 const u32 *h2c_regs; 4325 struct rtw89_reg_def h2c_counter_reg; 4326 u32 c2h_ctrl_reg; 4327 const u32 *c2h_regs; 4328 struct rtw89_reg_def c2h_counter_reg; 4329 const struct rtw89_page_regs *page_regs; 4330 const u32 *wow_reason_reg; 4331 bool cfo_src_fd; 4332 bool cfo_hw_comp; 4333 const struct rtw89_reg_def *dcfo_comp; 4334 u8 dcfo_comp_sft; 4335 const struct rtw89_imr_info *imr_info; 4336 const struct rtw89_imr_table *imr_dmac_table; 4337 const struct rtw89_imr_table *imr_cmac_table; 4338 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4339 struct rtw89_reg_def bss_clr_vld; 4340 u32 bss_clr_map_reg; 4341 const struct rtw89_rfkill_regs *rfkill_init; 4342 struct rtw89_reg_def rfkill_get; 4343 u32 dma_ch_mask; 4344 const struct rtw89_edcca_regs *edcca_regs; 4345 const struct wiphy_wowlan_support *wowlan_stub; 4346 const struct rtw89_xtal_info *xtal_info; 4347 }; 4348 4349 union rtw89_bus_info { 4350 const struct rtw89_pci_info *pci; 4351 }; 4352 4353 struct rtw89_driver_info { 4354 const struct rtw89_chip_info *chip; 4355 const struct dmi_system_id *quirks; 4356 union rtw89_bus_info bus; 4357 }; 4358 4359 enum rtw89_hcifc_mode { 4360 RTW89_HCIFC_POH = 0, 4361 RTW89_HCIFC_STF = 1, 4362 RTW89_HCIFC_SDIO = 2, 4363 4364 /* keep last */ 4365 RTW89_HCIFC_MODE_INVALID, 4366 }; 4367 4368 struct rtw89_dle_info { 4369 const struct rtw89_rsvd_quota *rsvd_qt; 4370 enum rtw89_qta_mode qta_mode; 4371 u16 ple_pg_size; 4372 u16 ple_free_pg; 4373 u16 c0_rx_qta; 4374 u16 c1_rx_qta; 4375 }; 4376 4377 enum rtw89_host_rpr_mode { 4378 RTW89_RPR_MODE_POH = 0, 4379 RTW89_RPR_MODE_STF 4380 }; 4381 4382 #define RTW89_COMPLETION_BUF_SIZE 40 4383 #define RTW89_WAIT_COND_IDLE UINT_MAX 4384 4385 struct rtw89_completion_data { 4386 bool err; 4387 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4388 }; 4389 4390 struct rtw89_wait_info { 4391 atomic_t cond; 4392 struct completion completion; 4393 struct rtw89_completion_data data; 4394 }; 4395 4396 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4397 4398 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4399 { 4400 init_completion(&wait->completion); 4401 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4402 } 4403 4404 struct rtw89_mac_info { 4405 struct rtw89_dle_info dle_info; 4406 struct rtw89_hfc_param hfc_param; 4407 enum rtw89_qta_mode qta_mode; 4408 u8 rpwm_seq_num; 4409 u8 cpwm_seq_num; 4410 4411 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4412 struct rtw89_wait_info fw_ofld_wait; 4413 /* see RTW89_PS_WAIT_COND series for wait condition */ 4414 struct rtw89_wait_info ps_wait; 4415 }; 4416 4417 enum rtw89_fwdl_check_type { 4418 RTW89_FWDL_CHECK_FREERTOS_DONE, 4419 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4420 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4421 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4422 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4423 }; 4424 4425 enum rtw89_fw_type { 4426 RTW89_FW_NORMAL = 1, 4427 RTW89_FW_WOWLAN = 3, 4428 RTW89_FW_NORMAL_CE = 5, 4429 RTW89_FW_BBMCU0 = 64, 4430 RTW89_FW_BBMCU1 = 65, 4431 RTW89_FW_LOGFMT = 255, 4432 }; 4433 4434 enum rtw89_fw_feature { 4435 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4436 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4437 RTW89_FW_FEATURE_TX_WAKE, 4438 RTW89_FW_FEATURE_CRASH_TRIGGER, 4439 RTW89_FW_FEATURE_NO_PACKET_DROP, 4440 RTW89_FW_FEATURE_NO_DEEP_PS, 4441 RTW89_FW_FEATURE_NO_LPS_PG, 4442 RTW89_FW_FEATURE_BEACON_FILTER, 4443 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4444 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4445 RTW89_FW_FEATURE_WOW_REASON_V1, 4446 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4447 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4448 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4449 }; 4450 4451 struct rtw89_fw_suit { 4452 enum rtw89_fw_type type; 4453 const u8 *data; 4454 u32 size; 4455 u8 major_ver; 4456 u8 minor_ver; 4457 u8 sub_ver; 4458 u8 sub_idex; 4459 u16 build_year; 4460 u16 build_mon; 4461 u16 build_date; 4462 u16 build_hour; 4463 u16 build_min; 4464 u8 cmd_ver; 4465 u8 hdr_ver; 4466 u32 commitid; 4467 }; 4468 4469 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4470 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4471 #define RTW89_FW_SUIT_VER_CODE(s) \ 4472 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4473 4474 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4475 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4476 (mfw_hdr)->ver.minor, \ 4477 (mfw_hdr)->ver.sub, \ 4478 (mfw_hdr)->ver.idx) 4479 4480 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4481 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4482 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4483 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4484 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4485 4486 struct rtw89_fw_req_info { 4487 const struct firmware *firmware; 4488 struct completion completion; 4489 }; 4490 4491 struct rtw89_fw_log { 4492 struct rtw89_fw_suit suit; 4493 bool enable; 4494 u32 last_fmt_id; 4495 u32 fmt_count; 4496 const __le32 *fmt_ids; 4497 const char *(*fmts)[]; 4498 }; 4499 4500 struct rtw89_fw_elm_info { 4501 struct rtw89_phy_table *bb_tbl; 4502 struct rtw89_phy_table *bb_gain; 4503 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4504 struct rtw89_phy_table *rf_nctl; 4505 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4506 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4507 }; 4508 4509 enum rtw89_fw_mss_dev_type { 4510 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4511 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4512 }; 4513 4514 struct rtw89_fw_secure { 4515 bool secure_boot; 4516 u32 sb_sel_mgn; 4517 u8 mss_dev_type; 4518 u8 mss_cust_idx; 4519 u8 mss_key_num; 4520 }; 4521 4522 struct rtw89_fw_info { 4523 struct rtw89_fw_req_info req; 4524 int fw_format; 4525 u8 h2c_seq; 4526 u8 rec_seq; 4527 u8 h2c_counter; 4528 u8 c2h_counter; 4529 struct rtw89_fw_suit normal; 4530 struct rtw89_fw_suit wowlan; 4531 struct rtw89_fw_suit bbmcu0; 4532 struct rtw89_fw_suit bbmcu1; 4533 struct rtw89_fw_log log; 4534 u32 feature_map; 4535 struct rtw89_fw_elm_info elm_info; 4536 struct rtw89_fw_secure sec; 4537 }; 4538 4539 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4540 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4541 4542 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4543 ((_fw)->feature_map |= BIT(_fw_feature)) 4544 4545 struct rtw89_cam_info { 4546 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4547 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4548 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4549 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4550 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4551 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4552 }; 4553 4554 enum rtw89_sar_sources { 4555 RTW89_SAR_SOURCE_NONE, 4556 RTW89_SAR_SOURCE_COMMON, 4557 4558 RTW89_SAR_SOURCE_NR, 4559 }; 4560 4561 enum rtw89_sar_subband { 4562 RTW89_SAR_2GHZ_SUBBAND, 4563 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4564 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4565 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4566 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4567 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4568 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4569 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4570 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4571 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4572 4573 RTW89_SAR_SUBBAND_NR, 4574 }; 4575 4576 struct rtw89_sar_cfg_common { 4577 bool set[RTW89_SAR_SUBBAND_NR]; 4578 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4579 }; 4580 4581 struct rtw89_sar_info { 4582 /* used to decide how to acces SAR cfg union */ 4583 enum rtw89_sar_sources src; 4584 4585 /* reserved for different knids of SAR cfg struct. 4586 * supposed that a single cfg struct cannot handle various SAR sources. 4587 */ 4588 union { 4589 struct rtw89_sar_cfg_common cfg_common; 4590 }; 4591 }; 4592 4593 enum rtw89_tas_state { 4594 RTW89_TAS_STATE_DPR_OFF, 4595 RTW89_TAS_STATE_DPR_ON, 4596 RTW89_TAS_STATE_DPR_FORBID, 4597 }; 4598 4599 #define RTW89_TAS_MAX_WINDOW 50 4600 struct rtw89_tas_info { 4601 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4602 s32 total_txpwr; 4603 u8 cur_idx; 4604 s8 dpr_gap; 4605 s8 delta; 4606 enum rtw89_tas_state state; 4607 bool enable; 4608 }; 4609 4610 struct rtw89_chanctx_cfg { 4611 enum rtw89_chanctx_idx idx; 4612 int ref_count; 4613 }; 4614 4615 enum rtw89_chanctx_changes { 4616 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4617 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4618 RTW89_CHANCTX_P2P_PS_CHANGE, 4619 RTW89_CHANCTX_BT_SLOT_CHANGE, 4620 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4621 4622 NUM_OF_RTW89_CHANCTX_CHANGES, 4623 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4624 }; 4625 4626 enum rtw89_entity_mode { 4627 RTW89_ENTITY_MODE_SCC, 4628 RTW89_ENTITY_MODE_MCC_PREPARE, 4629 RTW89_ENTITY_MODE_MCC, 4630 4631 NUM_OF_RTW89_ENTITY_MODE, 4632 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4633 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4634 }; 4635 4636 struct rtw89_chanctx { 4637 struct cfg80211_chan_def chandef; 4638 struct rtw89_chan chan; 4639 struct rtw89_chan_rcd rcd; 4640 4641 /* only assigned when running with chanctx_ops */ 4642 struct rtw89_chanctx_cfg *cfg; 4643 }; 4644 4645 struct rtw89_edcca_bak { 4646 u8 a; 4647 u8 p; 4648 u8 ppdu; 4649 u8 th_old; 4650 }; 4651 4652 enum rtw89_dm_type { 4653 RTW89_DM_DYNAMIC_EDCCA, 4654 }; 4655 4656 struct rtw89_hal { 4657 u32 rx_fltr; 4658 u8 cv; 4659 u8 acv; 4660 u32 antenna_tx; 4661 u32 antenna_rx; 4662 u8 tx_nss; 4663 u8 rx_nss; 4664 bool tx_path_diversity; 4665 bool ant_diversity; 4666 bool ant_diversity_fixed; 4667 bool support_cckpd; 4668 bool support_igi; 4669 atomic_t roc_chanctx_idx; 4670 4671 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4672 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4673 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4674 struct cfg80211_chan_def roc_chandef; 4675 4676 bool entity_active[RTW89_PHY_MAX]; 4677 bool entity_pause; 4678 enum rtw89_entity_mode entity_mode; 4679 4680 struct rtw89_edcca_bak edcca_bak; 4681 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4682 }; 4683 4684 #define RTW89_MAX_MAC_ID_NUM 128 4685 #define RTW89_MAX_PKT_OFLD_NUM 255 4686 4687 enum rtw89_flags { 4688 RTW89_FLAG_POWERON, 4689 RTW89_FLAG_DMAC_FUNC, 4690 RTW89_FLAG_CMAC0_FUNC, 4691 RTW89_FLAG_CMAC1_FUNC, 4692 RTW89_FLAG_FW_RDY, 4693 RTW89_FLAG_RUNNING, 4694 RTW89_FLAG_PROBE_DONE, 4695 RTW89_FLAG_BFEE_MON, 4696 RTW89_FLAG_BFEE_EN, 4697 RTW89_FLAG_BFEE_TIMER_KEEP, 4698 RTW89_FLAG_NAPI_RUNNING, 4699 RTW89_FLAG_LEISURE_PS, 4700 RTW89_FLAG_LOW_POWER_MODE, 4701 RTW89_FLAG_INACTIVE_PS, 4702 RTW89_FLAG_CRASH_SIMULATING, 4703 RTW89_FLAG_SER_HANDLING, 4704 RTW89_FLAG_WOWLAN, 4705 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4706 RTW89_FLAG_CHANGING_INTERFACE, 4707 RTW89_FLAG_HW_RFKILL_STATE, 4708 4709 NUM_OF_RTW89_FLAGS, 4710 }; 4711 4712 enum rtw89_quirks { 4713 RTW89_QUIRK_PCI_BER, 4714 4715 NUM_OF_RTW89_QUIRKS, 4716 }; 4717 4718 enum rtw89_pkt_drop_sel { 4719 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4720 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4721 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4722 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4723 RTW89_PKT_DROP_SEL_MACID_ALL, 4724 RTW89_PKT_DROP_SEL_MG0_ONCE, 4725 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4726 RTW89_PKT_DROP_SEL_HIQ_PORT, 4727 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4728 RTW89_PKT_DROP_SEL_BAND, 4729 RTW89_PKT_DROP_SEL_BAND_ONCE, 4730 RTW89_PKT_DROP_SEL_REL_MACID, 4731 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4732 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4733 }; 4734 4735 struct rtw89_pkt_drop_params { 4736 enum rtw89_pkt_drop_sel sel; 4737 enum rtw89_mac_idx mac_band; 4738 u8 macid; 4739 u8 port; 4740 u8 mbssid; 4741 bool tf_trs; 4742 u32 macid_band_sel[4]; 4743 }; 4744 4745 struct rtw89_pkt_stat { 4746 u16 beacon_nr; 4747 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4748 }; 4749 4750 DECLARE_EWMA(thermal, 4, 4); 4751 4752 struct rtw89_phy_stat { 4753 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4754 struct ewma_rssi bcn_rssi; 4755 struct rtw89_pkt_stat cur_pkt_stat; 4756 struct rtw89_pkt_stat last_pkt_stat; 4757 }; 4758 4759 enum rtw89_rfk_report_state { 4760 RTW89_RFK_STATE_START = 0x0, 4761 RTW89_RFK_STATE_OK = 0x1, 4762 RTW89_RFK_STATE_FAIL = 0x2, 4763 RTW89_RFK_STATE_TIMEOUT = 0x3, 4764 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4765 }; 4766 4767 struct rtw89_rfk_wait_info { 4768 struct completion completion; 4769 ktime_t start_time; 4770 enum rtw89_rfk_report_state state; 4771 u8 version; 4772 }; 4773 4774 #define RTW89_DACK_PATH_NR 2 4775 #define RTW89_DACK_IDX_NR 2 4776 #define RTW89_DACK_MSBK_NR 16 4777 struct rtw89_dack_info { 4778 bool dack_done; 4779 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4780 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4781 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4782 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4783 u32 dack_cnt; 4784 bool addck_timeout[RTW89_DACK_PATH_NR]; 4785 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4786 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4787 }; 4788 4789 enum rtw89_rfk_chs_nrs { 4790 __RTW89_RFK_CHS_NR_V0 = 2, 4791 __RTW89_RFK_CHS_NR_V1 = 3, 4792 4793 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 4794 }; 4795 4796 struct rtw89_rfk_mcc_info { 4797 u8 ch[RTW89_RFK_CHS_NR]; 4798 u8 band[RTW89_RFK_CHS_NR]; 4799 u8 bw[RTW89_RFK_CHS_NR]; 4800 u8 table_idx; 4801 }; 4802 4803 #define RTW89_IQK_CHS_NR 2 4804 #define RTW89_IQK_PATH_NR 4 4805 4806 struct rtw89_lck_info { 4807 u8 thermal[RF_PATH_MAX]; 4808 }; 4809 4810 struct rtw89_rx_dck_info { 4811 u8 thermal[RF_PATH_MAX]; 4812 }; 4813 4814 struct rtw89_iqk_info { 4815 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4816 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4817 bool lok_fail[RTW89_IQK_PATH_NR]; 4818 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4819 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4820 u32 iqk_fail_cnt; 4821 bool is_iqk_init; 4822 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4823 u8 iqk_band[RTW89_IQK_PATH_NR]; 4824 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4825 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4826 u8 iqk_times; 4827 u8 version; 4828 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4829 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4830 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4831 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4832 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4833 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4834 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4835 bool is_nbiqk; 4836 bool iqk_fft_en; 4837 bool iqk_xym_en; 4838 bool iqk_sram_en; 4839 bool iqk_cfir_en; 4840 u32 syn1to2; 4841 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4842 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4843 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4844 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4845 }; 4846 4847 #define RTW89_DPK_RF_PATH 2 4848 #define RTW89_DPK_AVG_THERMAL_NUM 8 4849 #define RTW89_DPK_BKUP_NUM 2 4850 struct rtw89_dpk_bkup_para { 4851 enum rtw89_band band; 4852 enum rtw89_bandwidth bw; 4853 u8 ch; 4854 bool path_ok; 4855 u8 mdpd_en; 4856 u8 txagc_dpk; 4857 u8 ther_dpk; 4858 u8 gs; 4859 u16 pwsf; 4860 }; 4861 4862 struct rtw89_dpk_info { 4863 bool is_dpk_enable; 4864 bool is_dpk_reload_en; 4865 u8 dpk_gs[RTW89_PHY_MAX]; 4866 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4867 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4868 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4869 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4870 u8 cur_idx[RTW89_DPK_RF_PATH]; 4871 u8 cur_k_set; 4872 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4873 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 4874 u32 dpk_order[RTW89_DPK_RF_PATH]; 4875 }; 4876 4877 struct rtw89_fem_info { 4878 bool elna_2g; 4879 bool elna_5g; 4880 bool epa_2g; 4881 bool epa_5g; 4882 bool epa_6g; 4883 }; 4884 4885 struct rtw89_phy_ch_info { 4886 u8 rssi_min; 4887 u16 rssi_min_macid; 4888 u8 pre_rssi_min; 4889 u8 rssi_max; 4890 u16 rssi_max_macid; 4891 u8 rxsc_160; 4892 u8 rxsc_80; 4893 u8 rxsc_40; 4894 u8 rxsc_20; 4895 u8 rxsc_l; 4896 u8 is_noisy; 4897 }; 4898 4899 struct rtw89_agc_gaincode_set { 4900 u8 lna_idx; 4901 u8 tia_idx; 4902 u8 rxb_idx; 4903 }; 4904 4905 #define IGI_RSSI_TH_NUM 5 4906 #define FA_TH_NUM 4 4907 #define LNA_GAIN_NUM 7 4908 #define TIA_GAIN_NUM 2 4909 struct rtw89_dig_info { 4910 struct rtw89_agc_gaincode_set cur_gaincode; 4911 bool force_gaincode_idx_en; 4912 struct rtw89_agc_gaincode_set force_gaincode; 4913 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4914 u16 fa_th[FA_TH_NUM]; 4915 u8 igi_rssi; 4916 u8 igi_fa_rssi; 4917 u8 fa_rssi_ofst; 4918 u8 dyn_igi_max; 4919 u8 dyn_igi_min; 4920 bool dyn_pd_th_en; 4921 u8 dyn_pd_th_max; 4922 u8 pd_low_th_ofst; 4923 u8 ib_pbk; 4924 s8 ib_pkpwr; 4925 s8 lna_gain_a[LNA_GAIN_NUM]; 4926 s8 lna_gain_g[LNA_GAIN_NUM]; 4927 s8 *lna_gain; 4928 s8 tia_gain_a[TIA_GAIN_NUM]; 4929 s8 tia_gain_g[TIA_GAIN_NUM]; 4930 s8 *tia_gain; 4931 bool is_linked_pre; 4932 bool bypass_dig; 4933 }; 4934 4935 enum rtw89_multi_cfo_mode { 4936 RTW89_PKT_BASED_AVG_MODE = 0, 4937 RTW89_ENTRY_BASED_AVG_MODE = 1, 4938 RTW89_TP_BASED_AVG_MODE = 2, 4939 }; 4940 4941 enum rtw89_phy_cfo_status { 4942 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4943 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4944 RTW89_PHY_DCFO_STATE_HOLD = 2, 4945 RTW89_PHY_DCFO_STATE_MAX 4946 }; 4947 4948 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4949 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4950 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4951 }; 4952 4953 struct rtw89_cfo_tracking_info { 4954 u16 cfo_timer_ms; 4955 bool cfo_trig_by_timer_en; 4956 enum rtw89_phy_cfo_status phy_cfo_status; 4957 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4958 u8 phy_cfo_trk_cnt; 4959 bool is_adjust; 4960 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4961 bool apply_compensation; 4962 u8 crystal_cap; 4963 u8 crystal_cap_default; 4964 u8 def_x_cap; 4965 s8 x_cap_ofst; 4966 u32 sta_cfo_tolerance; 4967 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4968 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4969 s32 cfo_avg_pre; 4970 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4971 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4972 s32 dcfo_avg; 4973 s32 dcfo_avg_pre; 4974 u32 packet_count; 4975 u32 packet_count_pre; 4976 s32 residual_cfo_acc; 4977 u8 phy_cfotrk_state; 4978 u8 phy_cfotrk_cnt; 4979 bool divergence_lock_en; 4980 u8 x_cap_lb; 4981 u8 x_cap_ub; 4982 u8 lock_cnt; 4983 }; 4984 4985 enum rtw89_tssi_mode { 4986 RTW89_TSSI_NORMAL = 0, 4987 RTW89_TSSI_SCAN = 1, 4988 }; 4989 4990 enum rtw89_tssi_alimk_band { 4991 TSSI_ALIMK_2G = 0, 4992 TSSI_ALIMK_5GL, 4993 TSSI_ALIMK_5GM, 4994 TSSI_ALIMK_5GH, 4995 TSSI_ALIMK_MAX 4996 }; 4997 4998 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4999 #define TSSI_TRIM_CH_GROUP_NUM 8 5000 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5001 5002 #define TSSI_CCK_CH_GROUP_NUM 6 5003 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5004 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5005 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5006 #define TSSI_MCS_CH_GROUP_NUM \ 5007 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5008 #define TSSI_MAX_CH_NUM 67 5009 #define TSSI_ALIMK_VALUE_NUM 8 5010 5011 struct rtw89_tssi_info { 5012 u8 thermal[RF_PATH_MAX]; 5013 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5014 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5015 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5016 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5017 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5018 s8 extra_ofst[RF_PATH_MAX]; 5019 bool tssi_tracking_check[RF_PATH_MAX]; 5020 u8 default_txagc_offset[RF_PATH_MAX]; 5021 u32 base_thermal[RF_PATH_MAX]; 5022 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5023 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5024 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5025 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5026 u32 tssi_alimk_time; 5027 }; 5028 5029 struct rtw89_power_trim_info { 5030 bool pg_thermal_trim; 5031 bool pg_pa_bias_trim; 5032 u8 thermal_trim[RF_PATH_MAX]; 5033 u8 pa_bias_trim[RF_PATH_MAX]; 5034 u8 pad_bias_trim[RF_PATH_MAX]; 5035 }; 5036 5037 struct rtw89_regd { 5038 char alpha2[3]; 5039 u8 txpwr_regd[RTW89_BAND_NUM]; 5040 }; 5041 5042 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5043 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5044 #define RTW89_5GHZ_UNII4_START_INDEX 25 5045 5046 struct rtw89_regulatory_info { 5047 const struct rtw89_regd *regd; 5048 enum rtw89_reg_6ghz_power reg_6ghz_power; 5049 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5050 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5051 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5052 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5053 }; 5054 5055 enum rtw89_ifs_clm_application { 5056 RTW89_IFS_CLM_INIT = 0, 5057 RTW89_IFS_CLM_BACKGROUND = 1, 5058 RTW89_IFS_CLM_ACS = 2, 5059 RTW89_IFS_CLM_DIG = 3, 5060 RTW89_IFS_CLM_TDMA_DIG = 4, 5061 RTW89_IFS_CLM_DBG = 5, 5062 RTW89_IFS_CLM_DBG_MANUAL = 6 5063 }; 5064 5065 enum rtw89_env_racing_lv { 5066 RTW89_RAC_RELEASE = 0, 5067 RTW89_RAC_LV_1 = 1, 5068 RTW89_RAC_LV_2 = 2, 5069 RTW89_RAC_LV_3 = 3, 5070 RTW89_RAC_LV_4 = 4, 5071 RTW89_RAC_MAX_NUM = 5 5072 }; 5073 5074 struct rtw89_ccx_para_info { 5075 enum rtw89_env_racing_lv rac_lv; 5076 u16 mntr_time; 5077 u8 nhm_manual_th_ofst; 5078 u8 nhm_manual_th0; 5079 enum rtw89_ifs_clm_application ifs_clm_app; 5080 u32 ifs_clm_manual_th_times; 5081 u32 ifs_clm_manual_th0; 5082 u8 fahm_manual_th_ofst; 5083 u8 fahm_manual_th0; 5084 u8 fahm_numer_opt; 5085 u8 fahm_denom_opt; 5086 }; 5087 5088 enum rtw89_ccx_edcca_opt_sc_idx { 5089 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5090 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5091 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5092 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5093 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5094 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5095 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5096 RTW89_CCX_EDCCA_SEG1_S3 = 7 5097 }; 5098 5099 enum rtw89_ccx_edcca_opt_bw_idx { 5100 RTW89_CCX_EDCCA_BW20_0 = 0, 5101 RTW89_CCX_EDCCA_BW20_1 = 1, 5102 RTW89_CCX_EDCCA_BW20_2 = 2, 5103 RTW89_CCX_EDCCA_BW20_3 = 3, 5104 RTW89_CCX_EDCCA_BW20_4 = 4, 5105 RTW89_CCX_EDCCA_BW20_5 = 5, 5106 RTW89_CCX_EDCCA_BW20_6 = 6, 5107 RTW89_CCX_EDCCA_BW20_7 = 7 5108 }; 5109 5110 #define RTW89_NHM_TH_NUM 11 5111 #define RTW89_FAHM_TH_NUM 11 5112 #define RTW89_NHM_RPT_NUM 12 5113 #define RTW89_FAHM_RPT_NUM 12 5114 #define RTW89_IFS_CLM_NUM 4 5115 struct rtw89_env_monitor_info { 5116 u8 ccx_watchdog_result; 5117 bool ccx_ongoing; 5118 u8 ccx_rac_lv; 5119 bool ccx_manual_ctrl; 5120 u16 ifs_clm_mntr_time; 5121 enum rtw89_ifs_clm_application ifs_clm_app; 5122 u16 ccx_period; 5123 u8 ccx_unit_idx; 5124 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5125 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5126 u16 ifs_clm_tx; 5127 u16 ifs_clm_edcca_excl_cca; 5128 u16 ifs_clm_ofdmfa; 5129 u16 ifs_clm_ofdmcca_excl_fa; 5130 u16 ifs_clm_cckfa; 5131 u16 ifs_clm_cckcca_excl_fa; 5132 u16 ifs_clm_total_ifs; 5133 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5134 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5135 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5136 u8 ifs_clm_tx_ratio; 5137 u8 ifs_clm_edcca_excl_cca_ratio; 5138 u8 ifs_clm_cck_fa_ratio; 5139 u8 ifs_clm_ofdm_fa_ratio; 5140 u8 ifs_clm_cck_cca_excl_fa_ratio; 5141 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5142 u16 ifs_clm_cck_fa_permil; 5143 u16 ifs_clm_ofdm_fa_permil; 5144 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5145 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5146 }; 5147 5148 enum rtw89_ser_rcvy_step { 5149 RTW89_SER_DRV_STOP_TX, 5150 RTW89_SER_DRV_STOP_RX, 5151 RTW89_SER_DRV_STOP_RUN, 5152 RTW89_SER_HAL_STOP_DMA, 5153 RTW89_SER_SUPPRESS_LOG, 5154 RTW89_NUM_OF_SER_FLAGS 5155 }; 5156 5157 struct rtw89_ser { 5158 u8 state; 5159 u8 alarm_event; 5160 bool prehandle_l1; 5161 5162 struct work_struct ser_hdl_work; 5163 struct delayed_work ser_alarm_work; 5164 const struct state_ent *st_tbl; 5165 const struct event_ent *ev_tbl; 5166 struct list_head msg_q; 5167 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5168 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5169 }; 5170 5171 enum rtw89_mac_ax_ps_mode { 5172 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5173 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5174 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5175 RTW89_MAC_AX_PS_MODE_MAX = 3, 5176 }; 5177 5178 enum rtw89_last_rpwm_mode { 5179 RTW89_LAST_RPWM_PS = 0x0, 5180 RTW89_LAST_RPWM_ACTIVE = 0x6, 5181 }; 5182 5183 struct rtw89_lps_parm { 5184 u8 macid; 5185 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5186 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5187 }; 5188 5189 struct rtw89_ppdu_sts_info { 5190 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 5191 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 5192 }; 5193 5194 struct rtw89_early_h2c { 5195 struct list_head list; 5196 u8 *h2c; 5197 u16 h2c_len; 5198 }; 5199 5200 struct rtw89_hw_scan_info { 5201 struct rtw89_vif_link *scanning_vif; 5202 struct list_head pkt_list[NUM_NL80211_BANDS]; 5203 struct rtw89_chan op_chan; 5204 bool abort; 5205 u32 last_chan_idx; 5206 }; 5207 5208 enum rtw89_phy_bb_gain_band { 5209 RTW89_BB_GAIN_BAND_2G = 0, 5210 RTW89_BB_GAIN_BAND_5G_L = 1, 5211 RTW89_BB_GAIN_BAND_5G_M = 2, 5212 RTW89_BB_GAIN_BAND_5G_H = 3, 5213 RTW89_BB_GAIN_BAND_6G_L = 4, 5214 RTW89_BB_GAIN_BAND_6G_M = 5, 5215 RTW89_BB_GAIN_BAND_6G_H = 6, 5216 RTW89_BB_GAIN_BAND_6G_UH = 7, 5217 5218 RTW89_BB_GAIN_BAND_NR, 5219 }; 5220 5221 enum rtw89_phy_gain_band_be { 5222 RTW89_BB_GAIN_BAND_2G_BE = 0, 5223 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5224 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5225 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5226 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5227 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5228 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5229 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5230 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5231 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5232 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5233 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5234 5235 RTW89_BB_GAIN_BAND_NR_BE, 5236 }; 5237 5238 enum rtw89_phy_bb_bw_be { 5239 RTW89_BB_BW_20_40 = 0, 5240 RTW89_BB_BW_80_160_320 = 1, 5241 5242 RTW89_BB_BW_NR_BE, 5243 }; 5244 5245 enum rtw89_bw20_sc { 5246 RTW89_BW20_SC_20M = 1, 5247 RTW89_BW20_SC_40M = 2, 5248 RTW89_BW20_SC_80M = 4, 5249 RTW89_BW20_SC_160M = 8, 5250 RTW89_BW20_SC_320M = 16, 5251 }; 5252 5253 enum rtw89_cmac_table_bw { 5254 RTW89_CMAC_BW_20M = 0, 5255 RTW89_CMAC_BW_40M = 1, 5256 RTW89_CMAC_BW_80M = 2, 5257 RTW89_CMAC_BW_160M = 3, 5258 RTW89_CMAC_BW_320M = 4, 5259 5260 RTW89_CMAC_BW_NR, 5261 }; 5262 5263 enum rtw89_phy_bb_rxsc_num { 5264 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5265 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5266 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5267 }; 5268 5269 struct rtw89_phy_bb_gain_info { 5270 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5271 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5272 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5273 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5274 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5275 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5276 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5277 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5278 [RTW89_BB_RXSC_NUM_40]; 5279 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5280 [RTW89_BB_RXSC_NUM_80]; 5281 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5282 [RTW89_BB_RXSC_NUM_160]; 5283 }; 5284 5285 struct rtw89_phy_bb_gain_info_be { 5286 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5287 [LNA_GAIN_NUM]; 5288 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5289 [TIA_GAIN_NUM]; 5290 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5291 [RF_PATH_MAX][LNA_GAIN_NUM]; 5292 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5293 [RF_PATH_MAX][LNA_GAIN_NUM]; 5294 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5295 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5296 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5297 [RTW89_BW20_SC_20M]; 5298 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5299 [RTW89_BW20_SC_40M]; 5300 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5301 [RTW89_BW20_SC_80M]; 5302 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5303 [RTW89_BW20_SC_160M]; 5304 }; 5305 5306 struct rtw89_phy_efuse_gain { 5307 bool offset_valid; 5308 bool comp_valid; 5309 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5310 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5311 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5312 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5313 }; 5314 5315 #define RTW89_MAX_PATTERN_NUM 18 5316 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5317 #define RTW89_MAX_PATTERN_SIZE 128 5318 5319 struct rtw89_wow_cam_info { 5320 bool r_w; 5321 u8 idx; 5322 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5323 u16 crc; 5324 bool negative_pattern_match; 5325 bool skip_mac_hdr; 5326 bool uc; 5327 bool mc; 5328 bool bc; 5329 bool valid; 5330 }; 5331 5332 struct rtw89_wow_key_info { 5333 u8 ptk_tx_iv[8]; 5334 u8 valid_check; 5335 u8 symbol_check_en; 5336 u8 gtk_keyidx; 5337 u8 rsvd[5]; 5338 u8 ptk_rx_iv[8]; 5339 u8 gtk_rx_iv[4][8]; 5340 } __packed; 5341 5342 struct rtw89_wow_gtk_info { 5343 u8 kck[32]; 5344 u8 kek[32]; 5345 u8 tk1[16]; 5346 u8 txmickey[8]; 5347 u8 rxmickey[8]; 5348 __le32 igtk_keyid; 5349 __le64 ipn; 5350 u8 igtk[2][32]; 5351 u8 psk[32]; 5352 } __packed; 5353 5354 struct rtw89_wow_aoac_report { 5355 u8 rpt_ver; 5356 u8 sec_type; 5357 u8 key_idx; 5358 u8 pattern_idx; 5359 u8 rekey_ok; 5360 u8 ptk_tx_iv[8]; 5361 u8 eapol_key_replay_count[8]; 5362 u8 gtk[32]; 5363 u8 ptk_rx_iv[8]; 5364 u8 gtk_rx_iv[4][8]; 5365 u64 igtk_key_id; 5366 u64 igtk_ipn; 5367 u8 igtk[32]; 5368 u8 csa_pri_ch; 5369 u8 csa_bw; 5370 u8 csa_ch_offset; 5371 u8 csa_chsw_failed; 5372 u8 csa_ch_band; 5373 }; 5374 5375 struct rtw89_wow_param { 5376 struct rtw89_vif_link *rtwvif_link; 5377 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5378 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5379 struct rtw89_wow_key_info key_info; 5380 struct rtw89_wow_gtk_info gtk_info; 5381 struct rtw89_wow_aoac_report aoac_rpt; 5382 u8 pattern_cnt; 5383 u8 ptk_alg; 5384 u8 gtk_alg; 5385 u8 ptk_keyidx; 5386 u8 akm; 5387 5388 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5389 struct rtw89_wait_info wait; 5390 5391 bool pno_inited; 5392 struct list_head pno_pkt_list; 5393 struct cfg80211_sched_scan_request *nd_config; 5394 }; 5395 5396 struct rtw89_mcc_limit { 5397 bool enable; 5398 u16 max_tob; /* TU; max time offset behind */ 5399 u16 max_toa; /* TU; max time offset ahead */ 5400 u16 max_dur; /* TU */ 5401 }; 5402 5403 struct rtw89_mcc_policy { 5404 u8 c2h_rpt; 5405 u8 tx_null_early; 5406 u8 dis_tx_null; 5407 u8 in_curr_ch; 5408 u8 dis_sw_retry; 5409 u8 sw_retry_count; 5410 }; 5411 5412 struct rtw89_mcc_role { 5413 struct rtw89_vif_link *rtwvif_link; 5414 struct rtw89_mcc_policy policy; 5415 struct rtw89_mcc_limit limit; 5416 5417 /* only valid when running with FW MRC mechanism */ 5418 u8 slot_idx; 5419 5420 /* byte-array in LE order for FW */ 5421 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5422 5423 u16 duration; /* TU */ 5424 u16 beacon_interval; /* TU */ 5425 bool is_2ghz; 5426 bool is_go; 5427 bool is_gc; 5428 }; 5429 5430 struct rtw89_mcc_bt_role { 5431 u16 duration; /* TU */ 5432 }; 5433 5434 struct rtw89_mcc_courtesy { 5435 bool enable; 5436 u8 slot_num; 5437 u8 macid_src; 5438 u8 macid_tgt; 5439 }; 5440 5441 enum rtw89_mcc_plan { 5442 RTW89_MCC_PLAN_TAIL_BT, 5443 RTW89_MCC_PLAN_MID_BT, 5444 RTW89_MCC_PLAN_NO_BT, 5445 5446 NUM_OF_RTW89_MCC_PLAN, 5447 }; 5448 5449 struct rtw89_mcc_pattern { 5450 s16 tob_ref; /* TU; time offset behind of reference role */ 5451 s16 toa_ref; /* TU; time offset ahead of reference role */ 5452 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5453 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5454 5455 enum rtw89_mcc_plan plan; 5456 struct rtw89_mcc_courtesy courtesy; 5457 }; 5458 5459 struct rtw89_mcc_sync { 5460 bool enable; 5461 u16 offset; /* TU */ 5462 u8 macid_src; 5463 u8 band_src; 5464 u8 port_src; 5465 u8 macid_tgt; 5466 u8 band_tgt; 5467 u8 port_tgt; 5468 }; 5469 5470 struct rtw89_mcc_config { 5471 struct rtw89_mcc_pattern pattern; 5472 struct rtw89_mcc_sync sync; 5473 u64 start_tsf; 5474 u16 mcc_interval; /* TU */ 5475 u16 beacon_offset; /* TU */ 5476 }; 5477 5478 enum rtw89_mcc_mode { 5479 RTW89_MCC_MODE_GO_STA, 5480 RTW89_MCC_MODE_GC_STA, 5481 }; 5482 5483 struct rtw89_mcc_info { 5484 struct rtw89_wait_info wait; 5485 5486 u8 group; 5487 enum rtw89_mcc_mode mode; 5488 struct rtw89_mcc_role role_ref; /* reference role */ 5489 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5490 struct rtw89_mcc_bt_role bt_role; 5491 struct rtw89_mcc_config config; 5492 }; 5493 5494 struct rtw89_dev { 5495 struct ieee80211_hw *hw; 5496 struct device *dev; 5497 const struct ieee80211_ops *ops; 5498 5499 bool dbcc_en; 5500 bool support_mlo; 5501 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5502 struct rtw89_hw_scan_info scan_info; 5503 const struct rtw89_chip_info *chip; 5504 const struct rtw89_pci_info *pci_info; 5505 const struct rtw89_rfe_parms *rfe_parms; 5506 struct rtw89_hal hal; 5507 struct rtw89_mcc_info mcc; 5508 struct rtw89_mac_info mac; 5509 struct rtw89_fw_info fw; 5510 struct rtw89_hci_info hci; 5511 struct rtw89_efuse efuse; 5512 struct rtw89_traffic_stats stats; 5513 struct rtw89_rfe_data *rfe_data; 5514 5515 /* ensures exclusive access from mac80211 callbacks */ 5516 struct mutex mutex; 5517 struct list_head rtwvifs_list; 5518 /* used to protect rf read write */ 5519 struct mutex rf_mutex; 5520 struct workqueue_struct *txq_wq; 5521 struct work_struct txq_work; 5522 struct delayed_work txq_reinvoke_work; 5523 /* used to protect ba_list and forbid_ba_list */ 5524 spinlock_t ba_lock; 5525 /* txqs to setup ba session */ 5526 struct list_head ba_list; 5527 /* txqs to forbid ba session */ 5528 struct list_head forbid_ba_list; 5529 struct work_struct ba_work; 5530 /* used to protect rpwm */ 5531 spinlock_t rpwm_lock; 5532 5533 struct rtw89_cam_info cam_info; 5534 5535 struct sk_buff_head c2h_queue; 5536 struct work_struct c2h_work; 5537 struct work_struct ips_work; 5538 struct work_struct load_firmware_work; 5539 struct work_struct cancel_6ghz_probe_work; 5540 5541 struct list_head early_h2c_list; 5542 5543 struct rtw89_ser ser; 5544 5545 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5546 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5547 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5548 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5549 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5550 5551 struct rtw89_phy_stat phystat; 5552 struct rtw89_rfk_wait_info rfk_wait; 5553 struct rtw89_dack_info dack; 5554 struct rtw89_iqk_info iqk; 5555 struct rtw89_dpk_info dpk; 5556 struct rtw89_rfk_mcc_info rfk_mcc; 5557 struct rtw89_lck_info lck; 5558 struct rtw89_rx_dck_info rx_dck; 5559 bool is_tssi_mode[RF_PATH_MAX]; 5560 bool is_bt_iqk_timeout; 5561 5562 struct rtw89_fem_info fem; 5563 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5564 struct rtw89_tssi_info tssi; 5565 struct rtw89_power_trim_info pwr_trim; 5566 5567 struct rtw89_cfo_tracking_info cfo_tracking; 5568 struct rtw89_env_monitor_info env_monitor; 5569 struct rtw89_dig_info dig; 5570 struct rtw89_phy_ch_info ch_info; 5571 union { 5572 struct rtw89_phy_bb_gain_info ax; 5573 struct rtw89_phy_bb_gain_info_be be; 5574 } bb_gain; 5575 struct rtw89_phy_efuse_gain efuse_gain; 5576 struct rtw89_phy_ul_tb_info ul_tb_info; 5577 struct rtw89_antdiv_info antdiv; 5578 5579 struct delayed_work track_work; 5580 struct delayed_work chanctx_work; 5581 struct delayed_work coex_act1_work; 5582 struct delayed_work coex_bt_devinfo_work; 5583 struct delayed_work coex_rfk_chk_work; 5584 struct delayed_work cfo_track_work; 5585 struct delayed_work forbid_ba_work; 5586 struct delayed_work roc_work; 5587 struct delayed_work antdiv_work; 5588 struct rtw89_ppdu_sts_info ppdu_sts; 5589 u8 total_sta_assoc; 5590 bool scanning; 5591 5592 struct rtw89_regulatory_info regulatory; 5593 struct rtw89_sar_info sar; 5594 struct rtw89_tas_info tas; 5595 5596 struct rtw89_btc btc; 5597 enum rtw89_ps_mode ps_mode; 5598 bool lps_enabled; 5599 5600 struct rtw89_wow_param wow; 5601 5602 /* napi structure */ 5603 struct net_device *netdev; 5604 struct napi_struct napi; 5605 int napi_budget_countdown; 5606 5607 struct rtw89_debugfs *debugfs; 5608 5609 /* HCI related data, keep last */ 5610 u8 priv[] __aligned(sizeof(void *)); 5611 }; 5612 5613 struct rtw89_vif { 5614 struct rtw89_dev *rtwdev; 5615 struct list_head list; 5616 5617 u8 mac_addr[ETH_ALEN]; 5618 __be32 ip_addr; 5619 5620 struct rtw89_traffic_stats stats; 5621 u32 tdls_peer; 5622 5623 struct ieee80211_scan_ies *scan_ies; 5624 struct cfg80211_scan_request *scan_req; 5625 5626 struct rtw89_roc roc; 5627 bool offchan; 5628 5629 u8 links_inst_valid_num; 5630 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5631 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5632 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 5633 }; 5634 5635 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 5636 const struct rtw89_vif *rtwvif, 5637 unsigned int link_id) 5638 { 5639 *rtwvif_link = rtwvif->links[link_id]; 5640 return !!*rtwvif_link; 5641 } 5642 5643 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 5644 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5645 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 5646 5647 struct rtw89_sta { 5648 struct rtw89_dev *rtwdev; 5649 struct rtw89_vif *rtwvif; 5650 5651 bool disassoc; 5652 5653 struct sk_buff_head roc_queue; 5654 5655 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 5656 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 5657 5658 u8 links_inst_valid_num; 5659 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5660 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5661 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 5662 }; 5663 5664 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 5665 const struct rtw89_sta *rtwsta, 5666 unsigned int link_id) 5667 { 5668 *rtwsta_link = rtwsta->links[link_id]; 5669 return !!*rtwsta_link; 5670 } 5671 5672 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 5673 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5674 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 5675 5676 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 5677 { 5678 /* const after init, so no need to check if active first */ 5679 return rtwvif->links_inst[0].mac_id; 5680 } 5681 5682 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 5683 { 5684 /* const after init, so no need to check if active first */ 5685 return rtwvif->links_inst[0].port; 5686 } 5687 5688 static inline struct rtw89_vif_link * 5689 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 5690 { 5691 if (index >= rtwvif->links_inst_valid_num || 5692 !test_bit(index, rtwvif->links_inst_map)) 5693 return NULL; 5694 return &rtwvif->links_inst[index]; 5695 } 5696 5697 static inline 5698 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 5699 { 5700 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5701 5702 return rtwvif_link - rtwvif->links_inst; 5703 } 5704 5705 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 5706 { 5707 /* const after init, so no need to check if active first */ 5708 return rtwsta->links_inst[0].mac_id; 5709 } 5710 5711 static inline struct rtw89_sta_link * 5712 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 5713 { 5714 if (index >= rtwsta->links_inst_valid_num || 5715 !test_bit(index, rtwsta->links_inst_map)) 5716 return NULL; 5717 return &rtwsta->links_inst[index]; 5718 } 5719 5720 static inline 5721 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 5722 { 5723 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5724 5725 return rtwsta_link - rtwsta->links_inst; 5726 } 5727 5728 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5729 struct rtw89_core_tx_request *tx_req) 5730 { 5731 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5732 } 5733 5734 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5735 { 5736 rtwdev->hci.ops->reset(rtwdev); 5737 } 5738 5739 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5740 { 5741 return rtwdev->hci.ops->start(rtwdev); 5742 } 5743 5744 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5745 { 5746 rtwdev->hci.ops->stop(rtwdev); 5747 } 5748 5749 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5750 { 5751 return rtwdev->hci.ops->deinit(rtwdev); 5752 } 5753 5754 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5755 { 5756 rtwdev->hci.ops->pause(rtwdev, pause); 5757 } 5758 5759 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5760 { 5761 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5762 } 5763 5764 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5765 { 5766 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5767 } 5768 5769 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5770 { 5771 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5772 } 5773 5774 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5775 { 5776 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5777 } 5778 5779 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5780 { 5781 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5782 } 5783 5784 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5785 bool drop) 5786 { 5787 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5788 return; 5789 5790 if (rtwdev->hci.ops->flush_queues) 5791 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5792 } 5793 5794 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5795 { 5796 if (rtwdev->hci.ops->recovery_start) 5797 rtwdev->hci.ops->recovery_start(rtwdev); 5798 } 5799 5800 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5801 { 5802 if (rtwdev->hci.ops->recovery_complete) 5803 rtwdev->hci.ops->recovery_complete(rtwdev); 5804 } 5805 5806 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5807 { 5808 if (rtwdev->hci.ops->enable_intr) 5809 rtwdev->hci.ops->enable_intr(rtwdev); 5810 } 5811 5812 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5813 { 5814 if (rtwdev->hci.ops->disable_intr) 5815 rtwdev->hci.ops->disable_intr(rtwdev); 5816 } 5817 5818 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5819 { 5820 if (rtwdev->hci.ops->ctrl_txdma_ch) 5821 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5822 } 5823 5824 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5825 { 5826 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5827 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5828 } 5829 5830 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5831 { 5832 if (rtwdev->hci.ops->ctrl_trxhci) 5833 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5834 } 5835 5836 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5837 { 5838 int ret = 0; 5839 5840 if (rtwdev->hci.ops->poll_txdma_ch_idle) 5841 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 5842 return ret; 5843 } 5844 5845 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5846 { 5847 if (rtwdev->hci.ops->clr_idx_all) 5848 rtwdev->hci.ops->clr_idx_all(rtwdev); 5849 } 5850 5851 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 5852 { 5853 int ret = 0; 5854 5855 if (rtwdev->hci.ops->rst_bdram) 5856 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 5857 return ret; 5858 } 5859 5860 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 5861 { 5862 if (rtwdev->hci.ops->clear) 5863 rtwdev->hci.ops->clear(rtwdev, pdev); 5864 } 5865 5866 static inline 5867 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5868 { 5869 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5870 5871 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5872 } 5873 5874 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5875 { 5876 return rtwdev->hci.ops->read8(rtwdev, addr); 5877 } 5878 5879 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5880 { 5881 return rtwdev->hci.ops->read16(rtwdev, addr); 5882 } 5883 5884 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5885 { 5886 return rtwdev->hci.ops->read32(rtwdev, addr); 5887 } 5888 5889 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5890 { 5891 rtwdev->hci.ops->write8(rtwdev, addr, data); 5892 } 5893 5894 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5895 { 5896 rtwdev->hci.ops->write16(rtwdev, addr, data); 5897 } 5898 5899 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5900 { 5901 rtwdev->hci.ops->write32(rtwdev, addr, data); 5902 } 5903 5904 static inline void 5905 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5906 { 5907 u8 val; 5908 5909 val = rtw89_read8(rtwdev, addr); 5910 rtw89_write8(rtwdev, addr, val | bit); 5911 } 5912 5913 static inline void 5914 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5915 { 5916 u16 val; 5917 5918 val = rtw89_read16(rtwdev, addr); 5919 rtw89_write16(rtwdev, addr, val | bit); 5920 } 5921 5922 static inline void 5923 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5924 { 5925 u32 val; 5926 5927 val = rtw89_read32(rtwdev, addr); 5928 rtw89_write32(rtwdev, addr, val | bit); 5929 } 5930 5931 static inline void 5932 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5933 { 5934 u8 val; 5935 5936 val = rtw89_read8(rtwdev, addr); 5937 rtw89_write8(rtwdev, addr, val & ~bit); 5938 } 5939 5940 static inline void 5941 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5942 { 5943 u16 val; 5944 5945 val = rtw89_read16(rtwdev, addr); 5946 rtw89_write16(rtwdev, addr, val & ~bit); 5947 } 5948 5949 static inline void 5950 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5951 { 5952 u32 val; 5953 5954 val = rtw89_read32(rtwdev, addr); 5955 rtw89_write32(rtwdev, addr, val & ~bit); 5956 } 5957 5958 static inline u32 5959 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5960 { 5961 u32 shift = __ffs(mask); 5962 u32 orig; 5963 u32 ret; 5964 5965 orig = rtw89_read32(rtwdev, addr); 5966 ret = (orig & mask) >> shift; 5967 5968 return ret; 5969 } 5970 5971 static inline u16 5972 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5973 { 5974 u32 shift = __ffs(mask); 5975 u32 orig; 5976 u32 ret; 5977 5978 orig = rtw89_read16(rtwdev, addr); 5979 ret = (orig & mask) >> shift; 5980 5981 return ret; 5982 } 5983 5984 static inline u8 5985 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5986 { 5987 u32 shift = __ffs(mask); 5988 u32 orig; 5989 u32 ret; 5990 5991 orig = rtw89_read8(rtwdev, addr); 5992 ret = (orig & mask) >> shift; 5993 5994 return ret; 5995 } 5996 5997 static inline void 5998 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5999 { 6000 u32 shift = __ffs(mask); 6001 u32 orig; 6002 u32 set; 6003 6004 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6005 6006 orig = rtw89_read32(rtwdev, addr); 6007 set = (orig & ~mask) | ((data << shift) & mask); 6008 rtw89_write32(rtwdev, addr, set); 6009 } 6010 6011 static inline void 6012 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6013 { 6014 u32 shift; 6015 u16 orig, set; 6016 6017 mask &= 0xffff; 6018 shift = __ffs(mask); 6019 6020 orig = rtw89_read16(rtwdev, addr); 6021 set = (orig & ~mask) | ((data << shift) & mask); 6022 rtw89_write16(rtwdev, addr, set); 6023 } 6024 6025 static inline void 6026 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6027 { 6028 u32 shift; 6029 u8 orig, set; 6030 6031 mask &= 0xff; 6032 shift = __ffs(mask); 6033 6034 orig = rtw89_read8(rtwdev, addr); 6035 set = (orig & ~mask) | ((data << shift) & mask); 6036 rtw89_write8(rtwdev, addr, set); 6037 } 6038 6039 static inline u32 6040 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6041 u32 addr, u32 mask) 6042 { 6043 u32 val; 6044 6045 mutex_lock(&rtwdev->rf_mutex); 6046 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6047 mutex_unlock(&rtwdev->rf_mutex); 6048 6049 return val; 6050 } 6051 6052 static inline void 6053 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6054 u32 addr, u32 mask, u32 data) 6055 { 6056 mutex_lock(&rtwdev->rf_mutex); 6057 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6058 mutex_unlock(&rtwdev->rf_mutex); 6059 } 6060 6061 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6062 { 6063 void *p = rtwtxq; 6064 6065 return container_of(p, struct ieee80211_txq, drv_priv); 6066 } 6067 6068 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6069 struct ieee80211_txq *txq) 6070 { 6071 struct rtw89_txq *rtwtxq; 6072 6073 if (!txq) 6074 return; 6075 6076 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6077 INIT_LIST_HEAD(&rtwtxq->list); 6078 } 6079 6080 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6081 { 6082 void *p = rtwvif; 6083 6084 return container_of(p, struct ieee80211_vif, drv_priv); 6085 } 6086 6087 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6088 { 6089 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6090 } 6091 6092 static inline 6093 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6094 { 6095 return rtwvif_to_vif(rtwvif_link->rtwvif); 6096 } 6097 6098 static inline 6099 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6100 { 6101 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6102 } 6103 6104 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6105 { 6106 return (struct rtw89_vif *)vif->drv_priv; 6107 } 6108 6109 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6110 { 6111 return vif ? vif_to_rtwvif(vif) : NULL; 6112 } 6113 6114 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6115 { 6116 void *p = rtwsta; 6117 6118 return container_of(p, struct ieee80211_sta, drv_priv); 6119 } 6120 6121 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6122 { 6123 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6124 } 6125 6126 static inline 6127 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6128 { 6129 return rtwsta_to_sta(rtwsta_link->rtwsta); 6130 } 6131 6132 static inline 6133 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6134 { 6135 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6136 } 6137 6138 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6139 { 6140 return (struct rtw89_sta *)sta->drv_priv; 6141 } 6142 6143 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6144 { 6145 return sta ? sta_to_rtwsta(sta) : NULL; 6146 } 6147 6148 static inline struct ieee80211_bss_conf * 6149 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6150 { 6151 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6152 struct ieee80211_bss_conf *bss_conf; 6153 6154 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6155 if (unlikely(!bss_conf)) { 6156 *nolink = true; 6157 return &vif->bss_conf; 6158 } 6159 6160 *nolink = false; 6161 return bss_conf; 6162 } 6163 6164 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6165 ({ \ 6166 typeof(rtwvif_link) p = rtwvif_link; \ 6167 struct ieee80211_bss_conf *bss_conf; \ 6168 bool nolink; \ 6169 \ 6170 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6171 if (unlikely(nolink) && (assert)) \ 6172 rtw89_err(p->rtwvif->rtwdev, \ 6173 "%s: cannot find exact bss_conf for link_id %u\n",\ 6174 __func__, p->link_id); \ 6175 bss_conf; \ 6176 }) 6177 6178 static inline struct ieee80211_link_sta * 6179 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6180 { 6181 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6182 struct ieee80211_link_sta *link_sta; 6183 6184 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6185 if (unlikely(!link_sta)) { 6186 *nolink = true; 6187 return &sta->deflink; 6188 } 6189 6190 *nolink = false; 6191 return link_sta; 6192 } 6193 6194 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6195 ({ \ 6196 typeof(rtwsta_link) p = rtwsta_link; \ 6197 struct ieee80211_link_sta *link_sta; \ 6198 bool nolink; \ 6199 \ 6200 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6201 if (unlikely(nolink) && (assert)) \ 6202 rtw89_err(p->rtwsta->rtwdev, \ 6203 "%s: cannot find exact link_sta for link_id %u\n",\ 6204 __func__, p->link_id); \ 6205 link_sta; \ 6206 }) 6207 6208 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6209 { 6210 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6211 return RATE_INFO_BW_160; 6212 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6213 return RATE_INFO_BW_80; 6214 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6215 return RATE_INFO_BW_40; 6216 else 6217 return RATE_INFO_BW_20; 6218 } 6219 6220 static inline 6221 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6222 { 6223 switch (hw_band) { 6224 default: 6225 case RTW89_BAND_2G: 6226 return NL80211_BAND_2GHZ; 6227 case RTW89_BAND_5G: 6228 return NL80211_BAND_5GHZ; 6229 case RTW89_BAND_6G: 6230 return NL80211_BAND_6GHZ; 6231 } 6232 } 6233 6234 static inline 6235 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6236 { 6237 switch (nl_band) { 6238 default: 6239 case NL80211_BAND_2GHZ: 6240 return RTW89_BAND_2G; 6241 case NL80211_BAND_5GHZ: 6242 return RTW89_BAND_5G; 6243 case NL80211_BAND_6GHZ: 6244 return RTW89_BAND_6G; 6245 } 6246 } 6247 6248 static inline 6249 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6250 { 6251 switch (width) { 6252 default: 6253 WARN(1, "Not support bandwidth %d\n", width); 6254 fallthrough; 6255 case NL80211_CHAN_WIDTH_20_NOHT: 6256 case NL80211_CHAN_WIDTH_20: 6257 return RTW89_CHANNEL_WIDTH_20; 6258 case NL80211_CHAN_WIDTH_40: 6259 return RTW89_CHANNEL_WIDTH_40; 6260 case NL80211_CHAN_WIDTH_80: 6261 return RTW89_CHANNEL_WIDTH_80; 6262 case NL80211_CHAN_WIDTH_160: 6263 return RTW89_CHANNEL_WIDTH_160; 6264 } 6265 } 6266 6267 static inline 6268 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6269 { 6270 switch (rua) { 6271 default: 6272 WARN(1, "Invalid RU allocation: %d\n", rua); 6273 fallthrough; 6274 case 0 ... 36: 6275 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6276 case 37 ... 52: 6277 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6278 case 53 ... 60: 6279 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6280 case 61 ... 64: 6281 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6282 case 65 ... 66: 6283 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6284 case 67: 6285 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6286 case 68: 6287 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6288 } 6289 } 6290 6291 static inline 6292 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6293 struct rtw89_sta_link *rtwsta_link) 6294 { 6295 if (rtwsta_link) { 6296 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6297 6298 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6299 return &rtwsta_link->addr_cam; 6300 } 6301 return &rtwvif_link->addr_cam; 6302 } 6303 6304 static inline 6305 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6306 struct rtw89_sta_link *rtwsta_link) 6307 { 6308 if (rtwsta_link) { 6309 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6310 6311 if (sta->tdls) 6312 return &rtwsta_link->bssid_cam; 6313 } 6314 return &rtwvif_link->bssid_cam; 6315 } 6316 6317 static inline 6318 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6319 struct rtw89_channel_help_params *p, 6320 const struct rtw89_chan *chan, 6321 enum rtw89_mac_idx mac_idx, 6322 enum rtw89_phy_idx phy_idx) 6323 { 6324 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6325 mac_idx, phy_idx); 6326 } 6327 6328 static inline 6329 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6330 struct rtw89_channel_help_params *p, 6331 const struct rtw89_chan *chan, 6332 enum rtw89_mac_idx mac_idx, 6333 enum rtw89_phy_idx phy_idx) 6334 { 6335 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6336 mac_idx, phy_idx); 6337 } 6338 6339 static inline 6340 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6341 enum rtw89_chanctx_idx idx) 6342 { 6343 struct rtw89_hal *hal = &rtwdev->hal; 6344 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6345 6346 if (roc_idx == idx) 6347 return &hal->roc_chandef; 6348 6349 return &hal->chanctx[idx].chandef; 6350 } 6351 6352 static inline 6353 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6354 enum rtw89_chanctx_idx idx) 6355 { 6356 struct rtw89_hal *hal = &rtwdev->hal; 6357 6358 return &hal->chanctx[idx].chan; 6359 } 6360 6361 static inline 6362 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6363 enum rtw89_chanctx_idx idx) 6364 { 6365 struct rtw89_hal *hal = &rtwdev->hal; 6366 6367 return &hal->chanctx[idx].rcd; 6368 } 6369 6370 static inline 6371 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6372 { 6373 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6374 6375 if (rtwvif_link) 6376 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6377 else 6378 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6379 } 6380 6381 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6382 { 6383 const struct rtw89_chip_info *chip = rtwdev->chip; 6384 6385 if (chip->ops->fem_setup) 6386 chip->ops->fem_setup(rtwdev); 6387 } 6388 6389 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6390 { 6391 const struct rtw89_chip_info *chip = rtwdev->chip; 6392 6393 if (chip->ops->rfe_gpio) 6394 chip->ops->rfe_gpio(rtwdev); 6395 } 6396 6397 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6398 { 6399 const struct rtw89_chip_info *chip = rtwdev->chip; 6400 6401 if (chip->ops->rfk_hw_init) 6402 chip->ops->rfk_hw_init(rtwdev); 6403 } 6404 6405 static inline 6406 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6407 { 6408 const struct rtw89_chip_info *chip = rtwdev->chip; 6409 6410 if (chip->ops->bb_preinit) 6411 chip->ops->bb_preinit(rtwdev, phy_idx); 6412 } 6413 6414 static inline 6415 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6416 { 6417 const struct rtw89_chip_info *chip = rtwdev->chip; 6418 6419 if (!chip->ops->bb_postinit) 6420 return; 6421 6422 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6423 6424 if (rtwdev->dbcc_en) 6425 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6426 } 6427 6428 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6429 { 6430 const struct rtw89_chip_info *chip = rtwdev->chip; 6431 6432 if (chip->ops->bb_sethw) 6433 chip->ops->bb_sethw(rtwdev); 6434 } 6435 6436 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6437 { 6438 const struct rtw89_chip_info *chip = rtwdev->chip; 6439 6440 if (chip->ops->rfk_init) 6441 chip->ops->rfk_init(rtwdev); 6442 } 6443 6444 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6445 { 6446 const struct rtw89_chip_info *chip = rtwdev->chip; 6447 6448 if (chip->ops->rfk_init_late) 6449 chip->ops->rfk_init_late(rtwdev); 6450 } 6451 6452 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6453 struct rtw89_vif_link *rtwvif_link) 6454 { 6455 const struct rtw89_chip_info *chip = rtwdev->chip; 6456 6457 if (chip->ops->rfk_channel) 6458 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6459 } 6460 6461 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6462 enum rtw89_phy_idx phy_idx, 6463 const struct rtw89_chan *chan) 6464 { 6465 const struct rtw89_chip_info *chip = rtwdev->chip; 6466 6467 if (chip->ops->rfk_band_changed) 6468 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6469 } 6470 6471 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6472 struct rtw89_vif_link *rtwvif_link, bool start) 6473 { 6474 const struct rtw89_chip_info *chip = rtwdev->chip; 6475 6476 if (chip->ops->rfk_scan) 6477 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6478 } 6479 6480 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6481 { 6482 const struct rtw89_chip_info *chip = rtwdev->chip; 6483 6484 if (chip->ops->rfk_track) 6485 chip->ops->rfk_track(rtwdev); 6486 } 6487 6488 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6489 { 6490 const struct rtw89_chip_info *chip = rtwdev->chip; 6491 6492 if (!chip->ops->set_txpwr_ctrl) 6493 return; 6494 6495 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6496 if (rtwdev->dbcc_en) 6497 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6498 } 6499 6500 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6501 { 6502 const struct rtw89_chip_info *chip = rtwdev->chip; 6503 6504 if (chip->ops->power_trim) 6505 chip->ops->power_trim(rtwdev); 6506 } 6507 6508 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6509 enum rtw89_phy_idx phy_idx) 6510 { 6511 const struct rtw89_chip_info *chip = rtwdev->chip; 6512 6513 if (chip->ops->init_txpwr_unit) 6514 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6515 } 6516 6517 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6518 { 6519 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6520 if (rtwdev->dbcc_en) 6521 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6522 } 6523 6524 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6525 enum rtw89_rf_path rf_path) 6526 { 6527 const struct rtw89_chip_info *chip = rtwdev->chip; 6528 6529 if (!chip->ops->get_thermal) 6530 return 0x10; 6531 6532 return chip->ops->get_thermal(rtwdev, rf_path); 6533 } 6534 6535 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6536 struct rtw89_rx_phy_ppdu *phy_ppdu, 6537 struct ieee80211_rx_status *status) 6538 { 6539 const struct rtw89_chip_info *chip = rtwdev->chip; 6540 6541 if (chip->ops->query_ppdu) 6542 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6543 } 6544 6545 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 6546 struct rtw89_rx_phy_ppdu *phy_ppdu) 6547 { 6548 const struct rtw89_chip_info *chip = rtwdev->chip; 6549 6550 if (chip->ops->convert_rpl_to_rssi) 6551 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 6552 } 6553 6554 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6555 enum rtw89_phy_idx phy_idx) 6556 { 6557 const struct rtw89_chip_info *chip = rtwdev->chip; 6558 6559 if (chip->ops->ctrl_nbtg_bt_tx) 6560 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6561 } 6562 6563 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6564 { 6565 const struct rtw89_chip_info *chip = rtwdev->chip; 6566 6567 if (chip->ops->cfg_txrx_path) 6568 chip->ops->cfg_txrx_path(rtwdev); 6569 } 6570 6571 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 6572 enum rtw89_phy_idx phy_idx) 6573 { 6574 const struct rtw89_chip_info *chip = rtwdev->chip; 6575 6576 if (chip->ops->digital_pwr_comp) 6577 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 6578 } 6579 6580 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6581 const struct rtw89_txpwr_table *tbl) 6582 { 6583 tbl->load(rtwdev, tbl); 6584 } 6585 6586 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6587 { 6588 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6589 6590 return regd->txpwr_regd[band]; 6591 } 6592 6593 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6594 enum rtw89_phy_idx phy_idx) 6595 { 6596 const struct rtw89_chip_info *chip = rtwdev->chip; 6597 6598 if (chip->ops->ctrl_btg_bt_rx) 6599 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6600 } 6601 6602 static inline 6603 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6604 struct rtw89_rx_desc_info *desc_info, 6605 u8 *data, u32 data_offset) 6606 { 6607 const struct rtw89_chip_info *chip = rtwdev->chip; 6608 6609 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6610 } 6611 6612 static inline 6613 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6614 struct rtw89_tx_desc_info *desc_info, 6615 void *txdesc) 6616 { 6617 const struct rtw89_chip_info *chip = rtwdev->chip; 6618 6619 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6620 } 6621 6622 static inline 6623 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6624 struct rtw89_tx_desc_info *desc_info, 6625 void *txdesc) 6626 { 6627 const struct rtw89_chip_info *chip = rtwdev->chip; 6628 6629 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6630 } 6631 6632 static inline 6633 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6634 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6635 { 6636 const struct rtw89_chip_info *chip = rtwdev->chip; 6637 6638 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6639 } 6640 6641 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6642 { 6643 const struct rtw89_chip_info *chip = rtwdev->chip; 6644 6645 chip->ops->cfg_ctrl_path(rtwdev, wl); 6646 } 6647 6648 static inline 6649 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6650 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6651 { 6652 const struct rtw89_chip_info *chip = rtwdev->chip; 6653 6654 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6655 } 6656 6657 static inline 6658 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6659 { 6660 const struct rtw89_chip_info *chip = rtwdev->chip; 6661 6662 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6663 } 6664 6665 static inline 6666 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6667 struct rtw89_vif_link *rtwvif_link, 6668 struct rtw89_sta_link *rtwsta_link) 6669 { 6670 const struct rtw89_chip_info *chip = rtwdev->chip; 6671 6672 if (!chip->ops->h2c_dctl_sec_cam) 6673 return 0; 6674 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 6675 } 6676 6677 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6678 { 6679 __le16 fc = hdr->frame_control; 6680 6681 if (ieee80211_has_tods(fc)) 6682 return hdr->addr1; 6683 else if (ieee80211_has_fromds(fc)) 6684 return hdr->addr2; 6685 else 6686 return hdr->addr3; 6687 } 6688 6689 static inline 6690 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 6691 { 6692 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6693 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6694 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 6695 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6696 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 6697 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6698 return true; 6699 return false; 6700 } 6701 6702 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6703 enum rtw89_fw_type type) 6704 { 6705 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6706 6707 switch (type) { 6708 case RTW89_FW_WOWLAN: 6709 return &fw_info->wowlan; 6710 case RTW89_FW_LOGFMT: 6711 return &fw_info->log.suit; 6712 case RTW89_FW_BBMCU0: 6713 return &fw_info->bbmcu0; 6714 case RTW89_FW_BBMCU1: 6715 return &fw_info->bbmcu1; 6716 default: 6717 break; 6718 } 6719 6720 return &fw_info->normal; 6721 } 6722 6723 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6724 unsigned int length) 6725 { 6726 struct sk_buff *skb; 6727 6728 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6729 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6730 if (!skb) 6731 return NULL; 6732 6733 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6734 return skb; 6735 } 6736 6737 return dev_alloc_skb(length); 6738 } 6739 6740 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6741 struct rtw89_tx_skb_data *skb_data, 6742 bool tx_done) 6743 { 6744 struct rtw89_tx_wait_info *wait; 6745 6746 rcu_read_lock(); 6747 6748 wait = rcu_dereference(skb_data->wait); 6749 if (!wait) 6750 goto out; 6751 6752 wait->tx_done = tx_done; 6753 complete(&wait->completion); 6754 6755 out: 6756 rcu_read_unlock(); 6757 } 6758 6759 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6760 { 6761 switch (rtwdev->mlo_dbcc_mode) { 6762 case MLO_1_PLUS_1_1RF: 6763 case MLO_1_PLUS_1_2RF: 6764 case DBCC_LEGACY: 6765 return true; 6766 default: 6767 return false; 6768 } 6769 } 6770 6771 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 6772 { 6773 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6774 6775 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 6776 return true; 6777 6778 return false; 6779 } 6780 6781 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6782 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6783 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6784 struct sk_buff *skb, bool fwdl); 6785 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6786 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6787 int qsel, unsigned int timeout); 6788 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6789 struct rtw89_tx_desc_info *desc_info, 6790 void *txdesc); 6791 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6792 struct rtw89_tx_desc_info *desc_info, 6793 void *txdesc); 6794 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6795 struct rtw89_tx_desc_info *desc_info, 6796 void *txdesc); 6797 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6798 struct rtw89_tx_desc_info *desc_info, 6799 void *txdesc); 6800 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6801 struct rtw89_tx_desc_info *desc_info, 6802 void *txdesc); 6803 void rtw89_core_rx(struct rtw89_dev *rtwdev, 6804 struct rtw89_rx_desc_info *desc_info, 6805 struct sk_buff *skb); 6806 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 6807 struct rtw89_rx_desc_info *desc_info, 6808 u8 *data, u32 data_offset); 6809 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 6810 struct rtw89_rx_desc_info *desc_info, 6811 u8 *data, u32 data_offset); 6812 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 6813 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 6814 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 6815 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 6816 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 6817 struct rtw89_vif_link *rtwvif_link, 6818 struct rtw89_sta_link *rtwsta_link); 6819 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 6820 struct rtw89_vif_link *rtwvif_link, 6821 struct rtw89_sta_link *rtwsta_link); 6822 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 6823 struct rtw89_vif_link *rtwvif_link, 6824 struct rtw89_sta_link *rtwsta_link); 6825 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 6826 struct rtw89_vif_link *rtwvif_link, 6827 struct rtw89_sta_link *rtwsta_link); 6828 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 6829 struct rtw89_vif_link *rtwvif_link, 6830 struct rtw89_sta_link *rtwsta_link); 6831 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6832 struct ieee80211_sta *sta, 6833 struct cfg80211_tid_config *tid_config); 6834 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 6835 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 6836 int rtw89_core_init(struct rtw89_dev *rtwdev); 6837 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 6838 int rtw89_core_register(struct rtw89_dev *rtwdev); 6839 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 6840 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6841 u32 bus_data_size, 6842 const struct rtw89_chip_info *chip); 6843 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 6844 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 6845 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 6846 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6847 u8 mac_id, u8 port); 6848 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6849 struct rtw89_sta *rtwsta, u8 mac_id); 6850 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 6851 unsigned int link_id); 6852 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 6853 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 6854 unsigned int link_id); 6855 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 6856 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 6857 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 6858 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 6859 struct rtw89_chan *chan); 6860 int rtw89_set_channel(struct rtw89_dev *rtwdev); 6861 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 6862 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 6863 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 6864 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 6865 struct rtw89_sta_link *rtwsta_link, u8 tid, 6866 u8 *cam_idx); 6867 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 6868 struct rtw89_sta_link *rtwsta_link, u8 tid, 6869 u8 *cam_idx); 6870 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 6871 struct ieee80211_sta *sta); 6872 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 6873 struct ieee80211_sta *sta); 6874 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 6875 struct ieee80211_sta *sta); 6876 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 6877 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 6878 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 6879 struct rtw89_vif_link *rtwvif_link); 6880 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 6881 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 6882 int rtw89_regd_init(struct rtw89_dev *rtwdev, 6883 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 6884 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 6885 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 6886 struct rtw89_traffic_stats *stats); 6887 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 6888 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6889 const struct rtw89_completion_data *data); 6890 int rtw89_core_start(struct rtw89_dev *rtwdev); 6891 void rtw89_core_stop(struct rtw89_dev *rtwdev); 6892 void rtw89_core_update_beacon_work(struct work_struct *work); 6893 void rtw89_roc_work(struct work_struct *work); 6894 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6895 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6896 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 6897 const u8 *mac_addr, bool hw_scan); 6898 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6899 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 6900 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 6901 bool active); 6902 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 6903 struct rtw89_vif_link *rtwvif_link, 6904 struct ieee80211_bss_conf *bss_conf); 6905 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 6906 6907 #endif 6908