1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_efuse_block_cfg; 21 struct rtw89_h2c_rf_tssi; 22 struct rtw89_fw_txpwr_track_cfg; 23 struct rtw89_phy_rfk_log_fmt; 24 25 extern const struct ieee80211_ops rtw89_ops; 26 27 #define MASKBYTE0 0xff 28 #define MASKBYTE1 0xff00 29 #define MASKBYTE2 0xff0000 30 #define MASKBYTE3 0xff000000 31 #define MASKBYTE4 0xff00000000ULL 32 #define MASKHWORD 0xffff0000 33 #define MASKLWORD 0x0000ffff 34 #define MASKDWORD 0xffffffff 35 #define RFREG_MASK 0xfffff 36 #define INV_RF_DATA 0xffffffff 37 #define BYPASS_CR_DATA 0xbabecafe 38 39 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 40 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 41 #define CFO_TRACK_MAX_USER 64 42 #define MAX_RSSI 110 43 #define RSSI_FACTOR 1 44 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 45 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 46 #define DELTA_SWINGIDX_SIZE 30 47 48 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 49 #define RTW89_RADIOTAP_ROOM_EHT \ 50 (sizeof(struct ieee80211_radiotap_tlv) + \ 51 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 52 sizeof(struct ieee80211_radiotap_tlv) + \ 53 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 54 #define RTW89_RADIOTAP_ROOM \ 55 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 56 57 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 58 #define RTW89_HTC_VARIANT_HE 3 59 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 60 #define RTW89_HTC_VARIANT_HE_CID_OM 1 61 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 62 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 63 64 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 65 enum htc_om_channel_width { 66 HTC_OM_CHANNEL_WIDTH_20 = 0, 67 HTC_OM_CHANNEL_WIDTH_40 = 1, 68 HTC_OM_CHANNEL_WIDTH_80 = 2, 69 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 70 }; 71 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 72 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 73 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 74 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 75 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 76 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 77 78 #define RTW89_TF_PAD GENMASK(11, 0) 79 #define RTW89_TF_BASIC_USER_INFO_SZ 6 80 81 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 82 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 83 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 84 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 85 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 86 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 87 88 enum rtw89_subband { 89 RTW89_CH_2G = 0, 90 RTW89_CH_5G_BAND_1 = 1, 91 /* RTW89_CH_5G_BAND_2 = 2, unused */ 92 RTW89_CH_5G_BAND_3 = 3, 93 RTW89_CH_5G_BAND_4 = 4, 94 95 RTW89_CH_6G_BAND_IDX0, /* Low */ 96 RTW89_CH_6G_BAND_IDX1, /* Low */ 97 RTW89_CH_6G_BAND_IDX2, /* Mid */ 98 RTW89_CH_6G_BAND_IDX3, /* Mid */ 99 RTW89_CH_6G_BAND_IDX4, /* High */ 100 RTW89_CH_6G_BAND_IDX5, /* High */ 101 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 102 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 103 104 RTW89_SUBBAND_NR, 105 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 106 }; 107 108 enum rtw89_gain_offset { 109 RTW89_GAIN_OFFSET_2G_CCK, 110 RTW89_GAIN_OFFSET_2G_OFDM, 111 RTW89_GAIN_OFFSET_5G_LOW, 112 RTW89_GAIN_OFFSET_5G_MID, 113 RTW89_GAIN_OFFSET_5G_HIGH, 114 RTW89_GAIN_OFFSET_6G_L0, 115 RTW89_GAIN_OFFSET_6G_L1, 116 RTW89_GAIN_OFFSET_6G_M0, 117 RTW89_GAIN_OFFSET_6G_M1, 118 RTW89_GAIN_OFFSET_6G_H0, 119 RTW89_GAIN_OFFSET_6G_H1, 120 RTW89_GAIN_OFFSET_6G_UH0, 121 RTW89_GAIN_OFFSET_6G_UH1, 122 123 RTW89_GAIN_OFFSET_NR, 124 }; 125 126 enum rtw89_hci_type { 127 RTW89_HCI_TYPE_PCIE, 128 RTW89_HCI_TYPE_USB, 129 RTW89_HCI_TYPE_SDIO, 130 }; 131 132 enum rtw89_core_chip_id { 133 RTL8852A, 134 RTL8852B, 135 RTL8852BT, 136 RTL8852C, 137 RTL8851B, 138 RTL8922A, 139 }; 140 141 enum rtw89_chip_gen { 142 RTW89_CHIP_AX, 143 RTW89_CHIP_BE, 144 145 RTW89_CHIP_GEN_NUM, 146 }; 147 148 enum rtw89_cv { 149 CHIP_CAV, 150 CHIP_CBV, 151 CHIP_CCV, 152 CHIP_CDV, 153 CHIP_CEV, 154 CHIP_CFV, 155 CHIP_CV_MAX, 156 CHIP_CV_INVALID = CHIP_CV_MAX, 157 }; 158 159 enum rtw89_bacam_ver { 160 RTW89_BACAM_V0, 161 RTW89_BACAM_V1, 162 163 RTW89_BACAM_V0_EXT = 99, 164 }; 165 166 enum rtw89_core_tx_type { 167 RTW89_CORE_TX_TYPE_DATA, 168 RTW89_CORE_TX_TYPE_MGMT, 169 RTW89_CORE_TX_TYPE_FWCMD, 170 }; 171 172 enum rtw89_core_rx_type { 173 RTW89_CORE_RX_TYPE_WIFI = 0, 174 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 175 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 176 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 177 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 178 RTW89_CORE_RX_TYPE_SS2FW = 5, 179 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 180 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 181 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 182 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 183 RTW89_CORE_RX_TYPE_C2H = 10, 184 RTW89_CORE_RX_TYPE_CSI = 11, 185 RTW89_CORE_RX_TYPE_CQI = 12, 186 RTW89_CORE_RX_TYPE_H2C = 13, 187 RTW89_CORE_RX_TYPE_FWDL = 14, 188 }; 189 190 enum rtw89_txq_flags { 191 RTW89_TXQ_F_AMPDU = 0, 192 RTW89_TXQ_F_BLOCK_BA = 1, 193 RTW89_TXQ_F_FORBID_BA = 2, 194 }; 195 196 enum rtw89_net_type { 197 RTW89_NET_TYPE_NO_LINK = 0, 198 RTW89_NET_TYPE_AD_HOC = 1, 199 RTW89_NET_TYPE_INFRA = 2, 200 RTW89_NET_TYPE_AP_MODE = 3, 201 }; 202 203 enum rtw89_wifi_role { 204 RTW89_WIFI_ROLE_NONE, 205 RTW89_WIFI_ROLE_STATION, 206 RTW89_WIFI_ROLE_AP, 207 RTW89_WIFI_ROLE_AP_VLAN, 208 RTW89_WIFI_ROLE_ADHOC, 209 RTW89_WIFI_ROLE_ADHOC_MASTER, 210 RTW89_WIFI_ROLE_MESH_POINT, 211 RTW89_WIFI_ROLE_MONITOR, 212 RTW89_WIFI_ROLE_P2P_DEVICE, 213 RTW89_WIFI_ROLE_P2P_CLIENT, 214 RTW89_WIFI_ROLE_P2P_GO, 215 RTW89_WIFI_ROLE_NAN, 216 RTW89_WIFI_ROLE_MLME_MAX 217 }; 218 219 enum rtw89_upd_mode { 220 RTW89_ROLE_CREATE, 221 RTW89_ROLE_REMOVE, 222 RTW89_ROLE_TYPE_CHANGE, 223 RTW89_ROLE_INFO_CHANGE, 224 RTW89_ROLE_CON_DISCONN, 225 RTW89_ROLE_BAND_SW, 226 RTW89_ROLE_FW_RESTORE, 227 }; 228 229 enum rtw89_self_role { 230 RTW89_SELF_ROLE_CLIENT, 231 RTW89_SELF_ROLE_AP, 232 RTW89_SELF_ROLE_AP_CLIENT 233 }; 234 235 enum rtw89_msk_sO_el { 236 RTW89_NO_MSK, 237 RTW89_SMA, 238 RTW89_TMA, 239 RTW89_BSSID 240 }; 241 242 enum rtw89_sch_tx_sel { 243 RTW89_SCH_TX_SEL_ALL, 244 RTW89_SCH_TX_SEL_HIQ, 245 RTW89_SCH_TX_SEL_MG0, 246 RTW89_SCH_TX_SEL_MACID, 247 }; 248 249 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 250 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 251 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 252 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 253 */ 254 enum rtw89_add_cam_sec_mode { 255 RTW89_ADDR_CAM_SEC_NONE = 0, 256 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 257 RTW89_ADDR_CAM_SEC_NORMAL = 2, 258 RTW89_ADDR_CAM_SEC_4GROUP = 3, 259 }; 260 261 enum rtw89_sec_key_type { 262 RTW89_SEC_KEY_TYPE_NONE = 0, 263 RTW89_SEC_KEY_TYPE_WEP40 = 1, 264 RTW89_SEC_KEY_TYPE_WEP104 = 2, 265 RTW89_SEC_KEY_TYPE_TKIP = 3, 266 RTW89_SEC_KEY_TYPE_WAPI = 4, 267 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 268 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 269 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 270 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 271 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 272 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 273 }; 274 275 enum rtw89_port { 276 RTW89_PORT_0 = 0, 277 RTW89_PORT_1 = 1, 278 RTW89_PORT_2 = 2, 279 RTW89_PORT_3 = 3, 280 RTW89_PORT_4 = 4, 281 RTW89_PORT_NUM 282 }; 283 284 enum rtw89_band { 285 RTW89_BAND_2G = 0, 286 RTW89_BAND_5G = 1, 287 RTW89_BAND_6G = 2, 288 RTW89_BAND_NUM, 289 }; 290 291 enum rtw89_hw_rate { 292 RTW89_HW_RATE_CCK1 = 0x0, 293 RTW89_HW_RATE_CCK2 = 0x1, 294 RTW89_HW_RATE_CCK5_5 = 0x2, 295 RTW89_HW_RATE_CCK11 = 0x3, 296 RTW89_HW_RATE_OFDM6 = 0x4, 297 RTW89_HW_RATE_OFDM9 = 0x5, 298 RTW89_HW_RATE_OFDM12 = 0x6, 299 RTW89_HW_RATE_OFDM18 = 0x7, 300 RTW89_HW_RATE_OFDM24 = 0x8, 301 RTW89_HW_RATE_OFDM36 = 0x9, 302 RTW89_HW_RATE_OFDM48 = 0xA, 303 RTW89_HW_RATE_OFDM54 = 0xB, 304 RTW89_HW_RATE_MCS0 = 0x80, 305 RTW89_HW_RATE_MCS1 = 0x81, 306 RTW89_HW_RATE_MCS2 = 0x82, 307 RTW89_HW_RATE_MCS3 = 0x83, 308 RTW89_HW_RATE_MCS4 = 0x84, 309 RTW89_HW_RATE_MCS5 = 0x85, 310 RTW89_HW_RATE_MCS6 = 0x86, 311 RTW89_HW_RATE_MCS7 = 0x87, 312 RTW89_HW_RATE_MCS8 = 0x88, 313 RTW89_HW_RATE_MCS9 = 0x89, 314 RTW89_HW_RATE_MCS10 = 0x8A, 315 RTW89_HW_RATE_MCS11 = 0x8B, 316 RTW89_HW_RATE_MCS12 = 0x8C, 317 RTW89_HW_RATE_MCS13 = 0x8D, 318 RTW89_HW_RATE_MCS14 = 0x8E, 319 RTW89_HW_RATE_MCS15 = 0x8F, 320 RTW89_HW_RATE_MCS16 = 0x90, 321 RTW89_HW_RATE_MCS17 = 0x91, 322 RTW89_HW_RATE_MCS18 = 0x92, 323 RTW89_HW_RATE_MCS19 = 0x93, 324 RTW89_HW_RATE_MCS20 = 0x94, 325 RTW89_HW_RATE_MCS21 = 0x95, 326 RTW89_HW_RATE_MCS22 = 0x96, 327 RTW89_HW_RATE_MCS23 = 0x97, 328 RTW89_HW_RATE_MCS24 = 0x98, 329 RTW89_HW_RATE_MCS25 = 0x99, 330 RTW89_HW_RATE_MCS26 = 0x9A, 331 RTW89_HW_RATE_MCS27 = 0x9B, 332 RTW89_HW_RATE_MCS28 = 0x9C, 333 RTW89_HW_RATE_MCS29 = 0x9D, 334 RTW89_HW_RATE_MCS30 = 0x9E, 335 RTW89_HW_RATE_MCS31 = 0x9F, 336 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 337 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 338 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 339 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 340 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 341 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 342 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 343 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 344 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 345 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 346 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 347 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 348 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 349 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 350 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 351 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 352 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 353 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 354 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 355 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 356 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 357 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 358 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 359 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 360 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 361 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 362 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 363 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 364 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 365 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 366 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 367 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 368 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 369 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 370 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 371 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 372 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 373 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 374 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 375 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 376 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 377 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 378 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 379 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 380 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 381 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 382 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 383 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 384 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 385 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 386 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 387 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 388 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 389 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 390 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 391 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 392 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 393 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 394 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 395 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 396 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 397 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 398 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 399 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 400 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 401 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 402 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 403 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 404 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 405 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 406 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 407 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 408 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 409 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 410 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 411 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 412 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 413 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 414 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 415 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 416 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 417 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 418 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 419 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 420 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 421 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 422 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 423 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 424 425 RTW89_HW_RATE_V1_MCS0 = 0x100, 426 RTW89_HW_RATE_V1_MCS1 = 0x101, 427 RTW89_HW_RATE_V1_MCS2 = 0x102, 428 RTW89_HW_RATE_V1_MCS3 = 0x103, 429 RTW89_HW_RATE_V1_MCS4 = 0x104, 430 RTW89_HW_RATE_V1_MCS5 = 0x105, 431 RTW89_HW_RATE_V1_MCS6 = 0x106, 432 RTW89_HW_RATE_V1_MCS7 = 0x107, 433 RTW89_HW_RATE_V1_MCS8 = 0x108, 434 RTW89_HW_RATE_V1_MCS9 = 0x109, 435 RTW89_HW_RATE_V1_MCS10 = 0x10A, 436 RTW89_HW_RATE_V1_MCS11 = 0x10B, 437 RTW89_HW_RATE_V1_MCS12 = 0x10C, 438 RTW89_HW_RATE_V1_MCS13 = 0x10D, 439 RTW89_HW_RATE_V1_MCS14 = 0x10E, 440 RTW89_HW_RATE_V1_MCS15 = 0x10F, 441 RTW89_HW_RATE_V1_MCS16 = 0x110, 442 RTW89_HW_RATE_V1_MCS17 = 0x111, 443 RTW89_HW_RATE_V1_MCS18 = 0x112, 444 RTW89_HW_RATE_V1_MCS19 = 0x113, 445 RTW89_HW_RATE_V1_MCS20 = 0x114, 446 RTW89_HW_RATE_V1_MCS21 = 0x115, 447 RTW89_HW_RATE_V1_MCS22 = 0x116, 448 RTW89_HW_RATE_V1_MCS23 = 0x117, 449 RTW89_HW_RATE_V1_MCS24 = 0x118, 450 RTW89_HW_RATE_V1_MCS25 = 0x119, 451 RTW89_HW_RATE_V1_MCS26 = 0x11A, 452 RTW89_HW_RATE_V1_MCS27 = 0x11B, 453 RTW89_HW_RATE_V1_MCS28 = 0x11C, 454 RTW89_HW_RATE_V1_MCS29 = 0x11D, 455 RTW89_HW_RATE_V1_MCS30 = 0x11E, 456 RTW89_HW_RATE_V1_MCS31 = 0x11F, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 611 612 RTW89_HW_RATE_NR, 613 RTW89_HW_RATE_INVAL, 614 615 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 616 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 617 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 618 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 619 }; 620 621 /* 2G channels, 622 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 623 */ 624 #define RTW89_2G_CH_NUM 14 625 626 /* 5G channels, 627 * 36, 38, 40, 42, 44, 46, 48, 50, 628 * 52, 54, 56, 58, 60, 62, 64, 629 * 100, 102, 104, 106, 108, 110, 112, 114, 630 * 116, 118, 120, 122, 124, 126, 128, 130, 631 * 132, 134, 136, 138, 140, 142, 144, 632 * 149, 151, 153, 155, 157, 159, 161, 163, 633 * 165, 167, 169, 171, 173, 175, 177 634 */ 635 #define RTW89_5G_CH_NUM 53 636 637 /* 6G channels, 638 * 1, 3, 5, 7, 9, 11, 13, 15, 639 * 17, 19, 21, 23, 25, 27, 29, 33, 640 * 35, 37, 39, 41, 43, 45, 47, 49, 641 * 51, 53, 55, 57, 59, 61, 65, 67, 642 * 69, 71, 73, 75, 77, 79, 81, 83, 643 * 85, 87, 89, 91, 93, 97, 99, 101, 644 * 103, 105, 107, 109, 111, 113, 115, 117, 645 * 119, 121, 123, 125, 129, 131, 133, 135, 646 * 137, 139, 141, 143, 145, 147, 149, 151, 647 * 153, 155, 157, 161, 163, 165, 167, 169, 648 * 171, 173, 175, 177, 179, 181, 183, 185, 649 * 187, 189, 193, 195, 197, 199, 201, 203, 650 * 205, 207, 209, 211, 213, 215, 217, 219, 651 * 221, 225, 227, 229, 231, 233, 235, 237, 652 * 239, 241, 243, 245, 247, 249, 251, 253, 653 */ 654 #define RTW89_6G_CH_NUM 120 655 656 enum rtw89_rate_section { 657 RTW89_RS_CCK, 658 RTW89_RS_OFDM, 659 RTW89_RS_MCS, /* for HT/VHT/HE */ 660 RTW89_RS_HEDCM, 661 RTW89_RS_OFFSET, 662 RTW89_RS_NUM, 663 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 664 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 665 }; 666 667 enum rtw89_rate_offset_indexes { 668 RTW89_RATE_OFFSET_HE, 669 RTW89_RATE_OFFSET_VHT, 670 RTW89_RATE_OFFSET_HT, 671 RTW89_RATE_OFFSET_OFDM, 672 RTW89_RATE_OFFSET_CCK, 673 RTW89_RATE_OFFSET_DLRU_EHT, 674 RTW89_RATE_OFFSET_DLRU_HE, 675 RTW89_RATE_OFFSET_EHT, 676 __RTW89_RATE_OFFSET_NUM, 677 678 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 679 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 680 }; 681 682 enum rtw89_rate_num { 683 RTW89_RATE_CCK_NUM = 4, 684 RTW89_RATE_OFDM_NUM = 8, 685 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 686 687 RTW89_RATE_MCS_NUM_AX = 12, 688 RTW89_RATE_MCS_NUM_BE = 16, 689 __RTW89_RATE_MCS_NUM = 16, 690 }; 691 692 enum rtw89_nss { 693 RTW89_NSS_1 = 0, 694 RTW89_NSS_2 = 1, 695 /* HE DCM only support 1ss and 2ss */ 696 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 697 RTW89_NSS_3 = 2, 698 RTW89_NSS_4 = 3, 699 RTW89_NSS_NUM, 700 }; 701 702 enum rtw89_ntx { 703 RTW89_1TX = 0, 704 RTW89_2TX = 1, 705 RTW89_NTX_NUM, 706 }; 707 708 enum rtw89_beamforming_type { 709 RTW89_NONBF = 0, 710 RTW89_BF = 1, 711 RTW89_BF_NUM, 712 }; 713 714 enum rtw89_ofdma_type { 715 RTW89_NON_OFDMA = 0, 716 RTW89_OFDMA = 1, 717 RTW89_OFDMA_NUM, 718 }; 719 720 enum rtw89_regulation_type { 721 RTW89_WW = 0, 722 RTW89_ETSI = 1, 723 RTW89_FCC = 2, 724 RTW89_MKK = 3, 725 RTW89_NA = 4, 726 RTW89_IC = 5, 727 RTW89_KCC = 6, 728 RTW89_ACMA = 7, 729 RTW89_NCC = 8, 730 RTW89_MEXICO = 9, 731 RTW89_CHILE = 10, 732 RTW89_UKRAINE = 11, 733 RTW89_CN = 12, 734 RTW89_QATAR = 13, 735 RTW89_UK = 14, 736 RTW89_THAILAND = 15, 737 RTW89_REGD_NUM, 738 }; 739 740 enum rtw89_reg_6ghz_power { 741 RTW89_REG_6GHZ_POWER_VLP = 0, 742 RTW89_REG_6GHZ_POWER_LPI = 1, 743 RTW89_REG_6GHZ_POWER_STD = 2, 744 745 NUM_OF_RTW89_REG_6GHZ_POWER, 746 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 747 }; 748 749 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 750 751 /* calculate based on ieee80211 Transmit Power Envelope */ 752 struct rtw89_reg_6ghz_tpe { 753 bool valid; 754 s8 constraint; /* unit: dBm */ 755 }; 756 757 enum rtw89_fw_pkt_ofld_type { 758 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 759 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 760 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 761 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 762 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 763 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 764 RTW89_PKT_OFLD_TYPE_NDP = 6, 765 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 766 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 767 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 768 RTW89_PKT_OFLD_TYPE_NUM, 769 }; 770 771 struct rtw89_txpwr_byrate { 772 s8 cck[RTW89_RATE_CCK_NUM]; 773 s8 ofdm[RTW89_RATE_OFDM_NUM]; 774 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 775 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 776 s8 offset[__RTW89_RATE_OFFSET_NUM]; 777 s8 trap; 778 }; 779 780 struct rtw89_rate_desc { 781 enum rtw89_nss nss; 782 enum rtw89_rate_section rs; 783 enum rtw89_ofdma_type ofdma; 784 u8 idx; 785 }; 786 787 #define PHY_STS_HDR_LEN 8 788 #define RF_PATH_MAX 4 789 #define RTW89_MAX_PPDU_CNT 8 790 struct rtw89_rx_phy_ppdu { 791 void *buf; 792 u32 len; 793 u8 rssi_avg; 794 u8 rssi[RF_PATH_MAX]; 795 u8 mac_id; 796 u8 chan_idx; 797 u8 ie; 798 u16 rate; 799 struct { 800 bool has; 801 u8 avg_snr; 802 u8 evm_max; 803 u8 evm_min; 804 } ofdm; 805 bool ldpc; 806 bool stbc; 807 bool to_self; 808 bool valid; 809 }; 810 811 enum rtw89_mac_idx { 812 RTW89_MAC_0 = 0, 813 RTW89_MAC_1 = 1, 814 RTW89_MAC_NUM, 815 }; 816 817 enum rtw89_phy_idx { 818 RTW89_PHY_0 = 0, 819 RTW89_PHY_1 = 1, 820 RTW89_PHY_MAX 821 }; 822 823 enum rtw89_sub_entity_idx { 824 RTW89_SUB_ENTITY_0 = 0, 825 RTW89_SUB_ENTITY_1 = 1, 826 827 NUM_OF_RTW89_SUB_ENTITY, 828 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 829 }; 830 831 enum rtw89_rf_path { 832 RF_PATH_A = 0, 833 RF_PATH_B = 1, 834 RF_PATH_C = 2, 835 RF_PATH_D = 3, 836 RF_PATH_AB, 837 RF_PATH_AC, 838 RF_PATH_AD, 839 RF_PATH_BC, 840 RF_PATH_BD, 841 RF_PATH_CD, 842 RF_PATH_ABC, 843 RF_PATH_ABD, 844 RF_PATH_ACD, 845 RF_PATH_BCD, 846 RF_PATH_ABCD, 847 }; 848 849 enum rtw89_rf_path_bit { 850 RF_A = BIT(0), 851 RF_B = BIT(1), 852 RF_C = BIT(2), 853 RF_D = BIT(3), 854 855 RF_AB = (RF_A | RF_B), 856 RF_AC = (RF_A | RF_C), 857 RF_AD = (RF_A | RF_D), 858 RF_BC = (RF_B | RF_C), 859 RF_BD = (RF_B | RF_D), 860 RF_CD = (RF_C | RF_D), 861 862 RF_ABC = (RF_A | RF_B | RF_C), 863 RF_ABD = (RF_A | RF_B | RF_D), 864 RF_ACD = (RF_A | RF_C | RF_D), 865 RF_BCD = (RF_B | RF_C | RF_D), 866 867 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 868 }; 869 870 enum rtw89_bandwidth { 871 RTW89_CHANNEL_WIDTH_20 = 0, 872 RTW89_CHANNEL_WIDTH_40 = 1, 873 RTW89_CHANNEL_WIDTH_80 = 2, 874 RTW89_CHANNEL_WIDTH_160 = 3, 875 RTW89_CHANNEL_WIDTH_320 = 4, 876 877 /* keep index order above */ 878 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 879 880 RTW89_CHANNEL_WIDTH_80_80 = 5, 881 RTW89_CHANNEL_WIDTH_5 = 6, 882 RTW89_CHANNEL_WIDTH_10 = 7, 883 }; 884 885 enum rtw89_ps_mode { 886 RTW89_PS_MODE_NONE = 0, 887 RTW89_PS_MODE_RFOFF = 1, 888 RTW89_PS_MODE_CLK_GATED = 2, 889 RTW89_PS_MODE_PWR_GATED = 3, 890 }; 891 892 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 893 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 894 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 895 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 896 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 897 898 enum rtw89_pe_duration { 899 RTW89_PE_DURATION_0 = 0, 900 RTW89_PE_DURATION_8 = 1, 901 RTW89_PE_DURATION_16 = 2, 902 RTW89_PE_DURATION_16_20 = 3, 903 }; 904 905 enum rtw89_ru_bandwidth { 906 RTW89_RU26 = 0, 907 RTW89_RU52 = 1, 908 RTW89_RU106 = 2, 909 RTW89_RU52_26 = 3, 910 RTW89_RU106_26 = 4, 911 RTW89_RU_NUM, 912 }; 913 914 enum rtw89_sc_offset { 915 RTW89_SC_DONT_CARE = 0, 916 RTW89_SC_20_UPPER = 1, 917 RTW89_SC_20_LOWER = 2, 918 RTW89_SC_20_UPMOST = 3, 919 RTW89_SC_20_LOWEST = 4, 920 RTW89_SC_20_UP2X = 5, 921 RTW89_SC_20_LOW2X = 6, 922 RTW89_SC_20_UP3X = 7, 923 RTW89_SC_20_LOW3X = 8, 924 RTW89_SC_40_UPPER = 9, 925 RTW89_SC_40_LOWER = 10, 926 }; 927 928 enum rtw89_wow_flags { 929 RTW89_WOW_FLAG_EN_MAGIC_PKT, 930 RTW89_WOW_FLAG_EN_REKEY_PKT, 931 RTW89_WOW_FLAG_EN_DISCONNECT, 932 RTW89_WOW_FLAG_NUM, 933 }; 934 935 struct rtw89_chan { 936 u8 channel; 937 u8 primary_channel; 938 enum rtw89_band band_type; 939 enum rtw89_bandwidth band_width; 940 941 /* The follow-up are derived from the above. We must ensure that it 942 * is assigned correctly in rtw89_chan_create() if new one is added. 943 */ 944 u32 freq; 945 enum rtw89_subband subband_type; 946 enum rtw89_sc_offset pri_ch_idx; 947 u8 pri_sb_idx; 948 }; 949 950 struct rtw89_chan_rcd { 951 u8 prev_primary_channel; 952 enum rtw89_band prev_band_type; 953 bool band_changed; 954 }; 955 956 struct rtw89_channel_help_params { 957 u32 tx_en; 958 }; 959 960 struct rtw89_port_reg { 961 u32 port_cfg; 962 u32 tbtt_prohib; 963 u32 bcn_area; 964 u32 bcn_early; 965 u32 tbtt_early; 966 u32 tbtt_agg; 967 u32 bcn_space; 968 u32 bcn_forcetx; 969 u32 bcn_err_cnt; 970 u32 bcn_err_flag; 971 u32 dtim_ctrl; 972 u32 tbtt_shift; 973 u32 bcn_cnt_tmr; 974 u32 tsftr_l; 975 u32 tsftr_h; 976 u32 md_tsft; 977 u32 bss_color; 978 u32 mbssid; 979 u32 mbssid_drop; 980 u32 tsf_sync; 981 u32 ptcl_dbg; 982 u32 ptcl_dbg_info; 983 u32 bcn_drop_all; 984 u32 hiq_win[RTW89_PORT_NUM]; 985 }; 986 987 struct rtw89_txwd_body { 988 __le32 dword0; 989 __le32 dword1; 990 __le32 dword2; 991 __le32 dword3; 992 __le32 dword4; 993 __le32 dword5; 994 } __packed; 995 996 struct rtw89_txwd_body_v1 { 997 __le32 dword0; 998 __le32 dword1; 999 __le32 dword2; 1000 __le32 dword3; 1001 __le32 dword4; 1002 __le32 dword5; 1003 __le32 dword6; 1004 __le32 dword7; 1005 } __packed; 1006 1007 struct rtw89_txwd_body_v2 { 1008 __le32 dword0; 1009 __le32 dword1; 1010 __le32 dword2; 1011 __le32 dword3; 1012 __le32 dword4; 1013 __le32 dword5; 1014 __le32 dword6; 1015 __le32 dword7; 1016 } __packed; 1017 1018 struct rtw89_txwd_info { 1019 __le32 dword0; 1020 __le32 dword1; 1021 __le32 dword2; 1022 __le32 dword3; 1023 __le32 dword4; 1024 __le32 dword5; 1025 } __packed; 1026 1027 struct rtw89_txwd_info_v2 { 1028 __le32 dword0; 1029 __le32 dword1; 1030 __le32 dword2; 1031 __le32 dword3; 1032 __le32 dword4; 1033 __le32 dword5; 1034 __le32 dword6; 1035 __le32 dword7; 1036 } __packed; 1037 1038 struct rtw89_rx_desc_info { 1039 u16 pkt_size; 1040 u8 pkt_type; 1041 u8 drv_info_size; 1042 u8 phy_rpt_size; 1043 u8 hdr_cnv_size; 1044 u8 shift; 1045 u8 wl_hd_iv_len; 1046 bool long_rxdesc; 1047 bool bb_sel; 1048 bool mac_info_valid; 1049 u16 data_rate; 1050 u8 gi_ltf; 1051 u8 bw; 1052 u32 free_run_cnt; 1053 u8 user_id; 1054 bool sr_en; 1055 u8 ppdu_cnt; 1056 u8 ppdu_type; 1057 bool icv_err; 1058 bool crc32_err; 1059 bool hw_dec; 1060 bool sw_dec; 1061 bool addr1_match; 1062 u8 frag; 1063 u16 seq; 1064 u8 frame_type; 1065 u8 rx_pl_id; 1066 bool addr_cam_valid; 1067 u8 addr_cam_id; 1068 u8 sec_cam_id; 1069 u8 mac_id; 1070 u16 offset; 1071 u16 rxd_len; 1072 bool ready; 1073 }; 1074 1075 struct rtw89_rxdesc_short { 1076 __le32 dword0; 1077 __le32 dword1; 1078 __le32 dword2; 1079 __le32 dword3; 1080 } __packed; 1081 1082 struct rtw89_rxdesc_short_v2 { 1083 __le32 dword0; 1084 __le32 dword1; 1085 __le32 dword2; 1086 __le32 dword3; 1087 __le32 dword4; 1088 __le32 dword5; 1089 } __packed; 1090 1091 struct rtw89_rxdesc_long { 1092 __le32 dword0; 1093 __le32 dword1; 1094 __le32 dword2; 1095 __le32 dword3; 1096 __le32 dword4; 1097 __le32 dword5; 1098 __le32 dword6; 1099 __le32 dword7; 1100 } __packed; 1101 1102 struct rtw89_rxdesc_long_v2 { 1103 __le32 dword0; 1104 __le32 dword1; 1105 __le32 dword2; 1106 __le32 dword3; 1107 __le32 dword4; 1108 __le32 dword5; 1109 __le32 dword6; 1110 __le32 dword7; 1111 __le32 dword8; 1112 __le32 dword9; 1113 } __packed; 1114 1115 struct rtw89_tx_desc_info { 1116 u16 pkt_size; 1117 u8 wp_offset; 1118 u8 mac_id; 1119 u8 qsel; 1120 u8 ch_dma; 1121 u8 hdr_llc_len; 1122 bool is_bmc; 1123 bool en_wd_info; 1124 bool wd_page; 1125 bool use_rate; 1126 bool dis_data_fb; 1127 bool tid_indicate; 1128 bool agg_en; 1129 bool bk; 1130 u8 ampdu_density; 1131 u8 ampdu_num; 1132 bool sec_en; 1133 u8 addr_info_nr; 1134 u8 sec_keyid; 1135 u8 sec_type; 1136 u8 sec_cam_idx; 1137 u8 sec_seq[6]; 1138 u16 data_rate; 1139 u16 data_retry_lowest_rate; 1140 bool fw_dl; 1141 u16 seq; 1142 bool a_ctrl_bsr; 1143 u8 hw_ssn_sel; 1144 #define RTW89_MGMT_HW_SSN_SEL 1 1145 u8 hw_seq_mode; 1146 #define RTW89_MGMT_HW_SEQ_MODE 1 1147 bool hiq; 1148 u8 port; 1149 bool er_cap; 1150 bool stbc; 1151 bool ldpc; 1152 }; 1153 1154 struct rtw89_core_tx_request { 1155 enum rtw89_core_tx_type tx_type; 1156 1157 struct sk_buff *skb; 1158 struct ieee80211_vif *vif; 1159 struct ieee80211_sta *sta; 1160 struct rtw89_tx_desc_info desc_info; 1161 }; 1162 1163 struct rtw89_txq { 1164 struct list_head list; 1165 unsigned long flags; 1166 int wait_cnt; 1167 }; 1168 1169 struct rtw89_mac_ax_gnt { 1170 u8 gnt_bt_sw_en; 1171 u8 gnt_bt; 1172 u8 gnt_wl_sw_en; 1173 u8 gnt_wl; 1174 } __packed; 1175 1176 struct rtw89_mac_ax_wl_act { 1177 u8 wlan_act_en; 1178 u8 wlan_act; 1179 }; 1180 1181 #define RTW89_MAC_AX_COEX_GNT_NR 2 1182 struct rtw89_mac_ax_coex_gnt { 1183 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1184 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1185 }; 1186 1187 enum rtw89_btc_ncnt { 1188 BTC_NCNT_POWER_ON = 0x0, 1189 BTC_NCNT_POWER_OFF, 1190 BTC_NCNT_INIT_COEX, 1191 BTC_NCNT_SCAN_START, 1192 BTC_NCNT_SCAN_FINISH, 1193 BTC_NCNT_SPECIAL_PACKET, 1194 BTC_NCNT_SWITCH_BAND, 1195 BTC_NCNT_RFK_TIMEOUT, 1196 BTC_NCNT_SHOW_COEX_INFO, 1197 BTC_NCNT_ROLE_INFO, 1198 BTC_NCNT_CONTROL, 1199 BTC_NCNT_RADIO_STATE, 1200 BTC_NCNT_CUSTOMERIZE, 1201 BTC_NCNT_WL_RFK, 1202 BTC_NCNT_WL_STA, 1203 BTC_NCNT_WL_STA_LAST, 1204 BTC_NCNT_FWINFO, 1205 BTC_NCNT_TIMER, 1206 BTC_NCNT_SWITCH_CHBW, 1207 BTC_NCNT_RESUME_DL_FW, 1208 BTC_NCNT_COUNTRYCODE, 1209 BTC_NCNT_NUM, 1210 }; 1211 1212 enum rtw89_btc_btinfo { 1213 BTC_BTINFO_L0 = 0, 1214 BTC_BTINFO_L1, 1215 BTC_BTINFO_L2, 1216 BTC_BTINFO_L3, 1217 BTC_BTINFO_H0, 1218 BTC_BTINFO_H1, 1219 BTC_BTINFO_H2, 1220 BTC_BTINFO_H3, 1221 BTC_BTINFO_MAX 1222 }; 1223 1224 enum rtw89_btc_dcnt { 1225 BTC_DCNT_RUN = 0x0, 1226 BTC_DCNT_CX_RUNINFO, 1227 BTC_DCNT_RPT, 1228 BTC_DCNT_RPT_HANG, 1229 BTC_DCNT_CYCLE, 1230 BTC_DCNT_CYCLE_HANG, 1231 BTC_DCNT_W1, 1232 BTC_DCNT_W1_HANG, 1233 BTC_DCNT_B1, 1234 BTC_DCNT_B1_HANG, 1235 BTC_DCNT_TDMA_NONSYNC, 1236 BTC_DCNT_SLOT_NONSYNC, 1237 BTC_DCNT_BTCNT_HANG, 1238 BTC_DCNT_BTTX_HANG, 1239 BTC_DCNT_WL_SLOT_DRIFT, 1240 BTC_DCNT_WL_STA_LAST, 1241 BTC_DCNT_BT_SLOT_DRIFT, 1242 BTC_DCNT_BT_SLOT_FLOOD, 1243 BTC_DCNT_FDDT_TRIG, 1244 BTC_DCNT_E2G, 1245 BTC_DCNT_E2G_HANG, 1246 BTC_DCNT_WL_FW_VER_MATCH, 1247 BTC_DCNT_NULL_TX_FAIL, 1248 BTC_DCNT_WL_STA_NTFY, 1249 BTC_DCNT_NUM, 1250 }; 1251 1252 enum rtw89_btc_wl_state_cnt { 1253 BTC_WCNT_SCANAP = 0x0, 1254 BTC_WCNT_DHCP, 1255 BTC_WCNT_EAPOL, 1256 BTC_WCNT_ARP, 1257 BTC_WCNT_SCBDUPDATE, 1258 BTC_WCNT_RFK_REQ, 1259 BTC_WCNT_RFK_GO, 1260 BTC_WCNT_RFK_REJECT, 1261 BTC_WCNT_RFK_TIMEOUT, 1262 BTC_WCNT_CH_UPDATE, 1263 BTC_WCNT_DBCC_ALL_2G, 1264 BTC_WCNT_DBCC_CHG, 1265 BTC_WCNT_RX_OK_LAST, 1266 BTC_WCNT_RX_OK_LAST2S, 1267 BTC_WCNT_RX_ERR_LAST, 1268 BTC_WCNT_RX_ERR_LAST2S, 1269 BTC_WCNT_RX_LAST, 1270 BTC_WCNT_NUM 1271 }; 1272 1273 enum rtw89_btc_bt_state_cnt { 1274 BTC_BCNT_RETRY = 0x0, 1275 BTC_BCNT_REINIT, 1276 BTC_BCNT_REENABLE, 1277 BTC_BCNT_SCBDREAD, 1278 BTC_BCNT_RELINK, 1279 BTC_BCNT_IGNOWL, 1280 BTC_BCNT_INQPAG, 1281 BTC_BCNT_INQ, 1282 BTC_BCNT_PAGE, 1283 BTC_BCNT_ROLESW, 1284 BTC_BCNT_AFH, 1285 BTC_BCNT_INFOUPDATE, 1286 BTC_BCNT_INFOSAME, 1287 BTC_BCNT_SCBDUPDATE, 1288 BTC_BCNT_HIPRI_TX, 1289 BTC_BCNT_HIPRI_RX, 1290 BTC_BCNT_LOPRI_TX, 1291 BTC_BCNT_LOPRI_RX, 1292 BTC_BCNT_POLUT, 1293 BTC_BCNT_POLUT_NOW, 1294 BTC_BCNT_POLUT_DIFF, 1295 BTC_BCNT_RATECHG, 1296 BTC_BCNT_NUM, 1297 }; 1298 1299 enum rtw89_btc_bt_profile { 1300 BTC_BT_NOPROFILE = 0, 1301 BTC_BT_HFP = BIT(0), 1302 BTC_BT_HID = BIT(1), 1303 BTC_BT_A2DP = BIT(2), 1304 BTC_BT_PAN = BIT(3), 1305 BTC_PROFILE_MAX = 4, 1306 }; 1307 1308 struct rtw89_btc_ant_info { 1309 u8 type; /* shared, dedicated */ 1310 u8 num; 1311 u8 isolation; 1312 1313 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1314 u8 diversity: 1; 1315 u8 btg_pos: 2; 1316 u8 stream_cnt: 4; 1317 }; 1318 1319 struct rtw89_btc_ant_info_v7 { 1320 u8 type; /* shared, dedicated(non-shared) */ 1321 u8 num; /* antenna count */ 1322 u8 isolation; 1323 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1324 1325 u8 diversity; /* only for wifi use 1-antenna */ 1326 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1327 u8 stream_cnt; /* spatial_stream count */ 1328 u8 rsvd; 1329 } __packed; 1330 1331 enum rtw89_tfc_dir { 1332 RTW89_TFC_UL, 1333 RTW89_TFC_DL, 1334 }; 1335 1336 struct rtw89_btc_wl_smap { 1337 u32 busy: 1; 1338 u32 scan: 1; 1339 u32 connecting: 1; 1340 u32 roaming: 1; 1341 u32 dbccing: 1; 1342 u32 transacting: 1; 1343 u32 _4way: 1; 1344 u32 rf_off: 1; 1345 u32 lps: 2; 1346 u32 ips: 1; 1347 u32 init_ok: 1; 1348 u32 traffic_dir : 2; 1349 u32 rf_off_pre: 1; 1350 u32 lps_pre: 2; 1351 u32 lps_exiting: 1; 1352 u32 emlsr: 1; 1353 }; 1354 1355 enum rtw89_tfc_lv { 1356 RTW89_TFC_IDLE, 1357 RTW89_TFC_ULTRA_LOW, 1358 RTW89_TFC_LOW, 1359 RTW89_TFC_MID, 1360 RTW89_TFC_HIGH, 1361 }; 1362 1363 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1364 DECLARE_EWMA(tp, 10, 2); 1365 1366 struct rtw89_traffic_stats { 1367 /* units in bytes */ 1368 u64 tx_unicast; 1369 u64 rx_unicast; 1370 u32 tx_avg_len; 1371 u32 rx_avg_len; 1372 1373 /* count for packets */ 1374 u64 tx_cnt; 1375 u64 rx_cnt; 1376 1377 /* units in Mbps */ 1378 u32 tx_throughput; 1379 u32 rx_throughput; 1380 u32 tx_throughput_raw; 1381 u32 rx_throughput_raw; 1382 1383 u32 rx_tf_acc; 1384 u32 rx_tf_periodic; 1385 1386 enum rtw89_tfc_lv tx_tfc_lv; 1387 enum rtw89_tfc_lv rx_tfc_lv; 1388 struct ewma_tp tx_ewma_tp; 1389 struct ewma_tp rx_ewma_tp; 1390 1391 u16 tx_rate; 1392 u16 rx_rate; 1393 }; 1394 1395 struct rtw89_btc_chdef { 1396 u8 center_ch; 1397 u8 band; 1398 u8 chan; 1399 enum rtw89_sc_offset offset; 1400 enum rtw89_bandwidth bw; 1401 }; 1402 1403 struct rtw89_btc_statistic { 1404 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1405 struct rtw89_traffic_stats traffic; 1406 }; 1407 1408 #define BTC_WL_RSSI_THMAX 4 1409 1410 struct rtw89_btc_wl_link_info { 1411 struct rtw89_btc_chdef chdef; 1412 struct rtw89_btc_statistic stat; 1413 enum rtw89_tfc_dir dir; 1414 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1415 u8 mac_addr[ETH_ALEN]; 1416 u8 busy; 1417 u8 ch; 1418 u8 bw; 1419 u8 band; 1420 u8 role; 1421 u8 pid; 1422 u8 phy; 1423 u8 dtim_period; 1424 u8 mode; 1425 u8 tx_1ss_limit; 1426 1427 u8 mac_id; 1428 u8 tx_retry; 1429 1430 u32 bcn_period; 1431 u32 busy_t; 1432 u32 tx_time; 1433 u32 client_cnt; 1434 u32 rx_rate_drop_cnt; 1435 u32 noa_duration; 1436 1437 u32 active: 1; 1438 u32 noa: 1; 1439 u32 client_ps: 1; 1440 u32 connected: 2; 1441 }; 1442 1443 union rtw89_btc_wl_state_map { 1444 u32 val; 1445 struct rtw89_btc_wl_smap map; 1446 }; 1447 1448 struct rtw89_btc_bt_hfp_desc { 1449 u32 exist: 1; 1450 u32 type: 2; 1451 u32 rsvd: 29; 1452 }; 1453 1454 struct rtw89_btc_bt_hid_desc { 1455 u32 exist: 1; 1456 u32 slot_info: 2; 1457 u32 pair_cnt: 2; 1458 u32 type: 8; 1459 u32 rsvd: 19; 1460 }; 1461 1462 struct rtw89_btc_bt_a2dp_desc { 1463 u8 exist: 1; 1464 u8 exist_last: 1; 1465 u8 play_latency: 1; 1466 u8 type: 3; 1467 u8 active: 1; 1468 u8 sink: 1; 1469 u32 handle_update: 1; 1470 u32 devinfo_query: 1; 1471 u32 no_empty_streak_2s: 8; 1472 u32 no_empty_streak_max: 8; 1473 u32 rsvd: 6; 1474 1475 u8 bitpool; 1476 u16 vendor_id; 1477 u32 device_name; 1478 u32 flush_time; 1479 }; 1480 1481 struct rtw89_btc_bt_pan_desc { 1482 u32 exist: 1; 1483 u32 type: 1; 1484 u32 active: 1; 1485 u32 rsvd: 29; 1486 }; 1487 1488 struct rtw89_btc_bt_rfk_info { 1489 u32 run: 1; 1490 u32 req: 1; 1491 u32 timeout: 1; 1492 u32 rsvd: 29; 1493 }; 1494 1495 union rtw89_btc_bt_rfk_info_map { 1496 u32 val; 1497 struct rtw89_btc_bt_rfk_info map; 1498 }; 1499 1500 struct rtw89_btc_bt_ver_info { 1501 u32 fw_coex; /* match with which coex_ver */ 1502 u32 fw; 1503 }; 1504 1505 struct rtw89_btc_bool_sta_chg { 1506 u32 now: 1; 1507 u32 last: 1; 1508 u32 remain: 1; 1509 u32 srvd: 29; 1510 }; 1511 1512 struct rtw89_btc_u8_sta_chg { 1513 u8 now; 1514 u8 last; 1515 u8 remain; 1516 u8 rsvd; 1517 }; 1518 1519 struct rtw89_btc_wl_scan_info { 1520 u8 band[RTW89_PHY_MAX]; 1521 u8 phy_map; 1522 u8 rsvd; 1523 }; 1524 1525 struct rtw89_btc_wl_dbcc_info { 1526 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1527 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1528 u8 real_band[RTW89_PHY_MAX]; 1529 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1530 }; 1531 1532 struct rtw89_btc_wl_active_role { 1533 u8 connected: 1; 1534 u8 pid: 3; 1535 u8 phy: 1; 1536 u8 noa: 1; 1537 u8 band: 2; 1538 1539 u8 client_ps: 1; 1540 u8 bw: 7; 1541 1542 u8 role; 1543 u8 ch; 1544 1545 u16 tx_lvl; 1546 u16 rx_lvl; 1547 u16 tx_rate; 1548 u16 rx_rate; 1549 }; 1550 1551 struct rtw89_btc_wl_active_role_v1 { 1552 u8 connected: 1; 1553 u8 pid: 3; 1554 u8 phy: 1; 1555 u8 noa: 1; 1556 u8 band: 2; 1557 1558 u8 client_ps: 1; 1559 u8 bw: 7; 1560 1561 u8 role; 1562 u8 ch; 1563 1564 u16 tx_lvl; 1565 u16 rx_lvl; 1566 u16 tx_rate; 1567 u16 rx_rate; 1568 1569 u32 noa_duration; /* ms */ 1570 }; 1571 1572 struct rtw89_btc_wl_active_role_v2 { 1573 u8 connected: 1; 1574 u8 pid: 3; 1575 u8 phy: 1; 1576 u8 noa: 1; 1577 u8 band: 2; 1578 1579 u8 client_ps: 1; 1580 u8 bw: 7; 1581 1582 u8 role; 1583 u8 ch; 1584 1585 u32 noa_duration; /* ms */ 1586 }; 1587 1588 struct rtw89_btc_wl_role_info_bpos { 1589 u16 none: 1; 1590 u16 station: 1; 1591 u16 ap: 1; 1592 u16 vap: 1; 1593 u16 adhoc: 1; 1594 u16 adhoc_master: 1; 1595 u16 mesh: 1; 1596 u16 moniter: 1; 1597 u16 p2p_device: 1; 1598 u16 p2p_gc: 1; 1599 u16 p2p_go: 1; 1600 u16 nan: 1; 1601 }; 1602 1603 struct rtw89_btc_wl_scc_ctrl { 1604 u8 null_role1; 1605 u8 null_role2; 1606 u8 ebt_null; /* if tx null at EBT slot */ 1607 }; 1608 1609 union rtw89_btc_wl_role_info_map { 1610 u16 val; 1611 struct rtw89_btc_wl_role_info_bpos role; 1612 }; 1613 1614 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1615 u8 connect_cnt; 1616 u8 link_mode; 1617 union rtw89_btc_wl_role_info_map role_map; 1618 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1619 }; 1620 1621 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1622 u8 connect_cnt; 1623 u8 link_mode; 1624 union rtw89_btc_wl_role_info_map role_map; 1625 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1626 u32 mrole_type; /* btc_wl_mrole_type */ 1627 u32 mrole_noa_duration; /* ms */ 1628 1629 u32 dbcc_en: 1; 1630 u32 dbcc_chg: 1; 1631 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1632 u32 link_mode_chg: 1; 1633 u32 rsvd: 27; 1634 }; 1635 1636 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1637 u8 connect_cnt; 1638 u8 link_mode; 1639 union rtw89_btc_wl_role_info_map role_map; 1640 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1641 u32 mrole_type; /* btc_wl_mrole_type */ 1642 u32 mrole_noa_duration; /* ms */ 1643 1644 u32 dbcc_en: 1; 1645 u32 dbcc_chg: 1; 1646 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1647 u32 link_mode_chg: 1; 1648 u32 rsvd: 27; 1649 }; 1650 1651 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1652 u8 connected; 1653 u8 pid; 1654 u8 phy; 1655 u8 noa; 1656 1657 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1658 u8 active; /* 0:rlink is under doze */ 1659 u8 bw; /* enum channel_width */ 1660 u8 role; /*enum role_type */ 1661 1662 u8 ch; 1663 u8 noa_dur; /* ms */ 1664 u8 client_cnt; /* for Role = P2P-Go/AP */ 1665 u8 mode; /* wifi protocol */ 1666 } __packed; 1667 1668 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1669 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1670 u8 connect_cnt; 1671 u8 link_mode; 1672 u8 link_mode_chg; 1673 u8 p2p_2g; 1674 1675 u8 pta_req_band; 1676 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1677 u8 dbcc_chg; 1678 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1679 1680 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1681 1682 u32 role_map; 1683 u32 mrole_type; /* btc_wl_mrole_type */ 1684 u32 mrole_noa_duration; /* ms */ 1685 } __packed; 1686 1687 struct rtw89_btc_wl_ver_info { 1688 u32 fw_coex; /* match with which coex_ver */ 1689 u32 fw; 1690 u32 mac; 1691 u32 bb; 1692 u32 rf; 1693 }; 1694 1695 struct rtw89_btc_wl_afh_info { 1696 u8 en; 1697 u8 ch; 1698 u8 bw; 1699 u8 rsvd; 1700 } __packed; 1701 1702 struct rtw89_btc_wl_rfk_info { 1703 u32 state: 2; 1704 u32 path_map: 4; 1705 u32 phy_map: 2; 1706 u32 band: 2; 1707 u32 type: 8; 1708 u32 rsvd: 14; 1709 1710 u32 start_time; 1711 u32 proc_time; 1712 }; 1713 1714 struct rtw89_btc_bt_smap { 1715 u32 connect: 1; 1716 u32 ble_connect: 1; 1717 u32 acl_busy: 1; 1718 u32 sco_busy: 1; 1719 u32 mesh_busy: 1; 1720 u32 inq_pag: 1; 1721 }; 1722 1723 union rtw89_btc_bt_state_map { 1724 u32 val; 1725 struct rtw89_btc_bt_smap map; 1726 }; 1727 1728 #define BTC_BT_RSSI_THMAX 4 1729 #define BTC_BT_AFH_GROUP 12 1730 #define BTC_BT_AFH_LE_GROUP 5 1731 1732 struct rtw89_btc_bt_link_info { 1733 struct rtw89_btc_u8_sta_chg profile_cnt; 1734 struct rtw89_btc_bool_sta_chg multi_link; 1735 struct rtw89_btc_bool_sta_chg relink; 1736 struct rtw89_btc_bt_hfp_desc hfp_desc; 1737 struct rtw89_btc_bt_hid_desc hid_desc; 1738 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1739 struct rtw89_btc_bt_pan_desc pan_desc; 1740 union rtw89_btc_bt_state_map status; 1741 1742 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1743 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1744 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1745 u8 afh_map[BTC_BT_AFH_GROUP]; 1746 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1747 1748 u32 role_sw: 1; 1749 u32 slave_role: 1; 1750 u32 afh_update: 1; 1751 u32 cqddr: 1; 1752 u32 rssi: 8; 1753 u32 tx_3m: 1; 1754 u32 rsvd: 19; 1755 }; 1756 1757 struct rtw89_btc_3rdcx_info { 1758 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1759 u8 hw_coex; 1760 u16 rsvd; 1761 }; 1762 1763 struct rtw89_btc_dm_emap { 1764 u32 init: 1; 1765 u32 pta_owner: 1; 1766 u32 wl_rfk_timeout: 1; 1767 u32 bt_rfk_timeout: 1; 1768 u32 wl_fw_hang: 1; 1769 u32 cycle_hang: 1; 1770 u32 w1_hang: 1; 1771 u32 b1_hang: 1; 1772 u32 tdma_no_sync: 1; 1773 u32 slot_no_sync: 1; 1774 u32 wl_slot_drift: 1; 1775 u32 bt_slot_drift: 1; 1776 u32 role_num_mismatch: 1; 1777 u32 null1_tx_late: 1; 1778 u32 bt_afh_conflict: 1; 1779 u32 bt_leafh_conflict: 1; 1780 u32 bt_slot_flood: 1; 1781 u32 wl_e2g_hang: 1; 1782 u32 wl_ver_mismatch: 1; 1783 u32 bt_ver_mismatch: 1; 1784 u32 rfe_type0: 1; 1785 u32 h2c_buffer_over: 1; 1786 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1787 u32 wl_no_sta_ntfy: 1; 1788 1789 u32 h2c_bmap_mismatch: 1; 1790 u32 c2h_bmap_mismatch: 1; 1791 u32 h2c_struct_invalid: 1; 1792 u32 c2h_struct_invalid: 1; 1793 u32 h2c_c2h_buffer_mismatch: 1; 1794 }; 1795 1796 union rtw89_btc_dm_error_map { 1797 u32 val; 1798 struct rtw89_btc_dm_emap map; 1799 }; 1800 1801 struct rtw89_btc_rf_para { 1802 u32 tx_pwr_freerun; 1803 u32 rx_gain_freerun; 1804 u32 tx_pwr_perpkt; 1805 u32 rx_gain_perpkt; 1806 }; 1807 1808 struct rtw89_btc_wl_nhm { 1809 u8 instant_wl_nhm_dbm; 1810 u8 instant_wl_nhm_per_mhz; 1811 u16 valid_record_times; 1812 s8 record_pwr[16]; 1813 u8 record_ratio[16]; 1814 s8 pwr; /* dbm_per_MHz */ 1815 u8 ratio; 1816 u8 current_status; 1817 u8 refresh; 1818 bool start_flag; 1819 s8 pwr_max; 1820 s8 pwr_min; 1821 }; 1822 1823 struct rtw89_btc_wl_info { 1824 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1825 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1826 struct rtw89_btc_wl_rfk_info rfk_info; 1827 struct rtw89_btc_wl_ver_info ver_info; 1828 struct rtw89_btc_wl_afh_info afh_info; 1829 struct rtw89_btc_wl_role_info role_info; 1830 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1831 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1832 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1833 struct rtw89_btc_wl_scan_info scan_info; 1834 struct rtw89_btc_wl_dbcc_info dbcc_info; 1835 struct rtw89_btc_rf_para rf_para; 1836 struct rtw89_btc_wl_nhm nhm; 1837 union rtw89_btc_wl_state_map status; 1838 1839 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1840 u8 rssi_level; 1841 u8 cn_report; 1842 u8 coex_mode; 1843 u8 pta_req_mac; 1844 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */ 1845 1846 bool is_5g_hi_channel; 1847 bool pta_reg_mac_chg; 1848 bool bg_mode; 1849 bool scbd_change; 1850 bool fw_ver_mismatch; 1851 u32 scbd; 1852 }; 1853 1854 struct rtw89_btc_module { 1855 struct rtw89_btc_ant_info ant; 1856 u8 rfe_type; 1857 u8 cv; 1858 1859 u8 bt_solo: 1; 1860 u8 bt_pos: 1; 1861 u8 switch_type: 1; 1862 u8 wa_type: 3; 1863 1864 u8 kt_ver_adie; 1865 }; 1866 1867 struct rtw89_btc_module_v7 { 1868 u8 rfe_type; 1869 u8 kt_ver; 1870 u8 bt_solo; 1871 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1872 1873 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1874 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1875 u8 kt_ver_adie; 1876 u8 rsvd; 1877 1878 struct rtw89_btc_ant_info_v7 ant; 1879 } __packed; 1880 1881 union rtw89_btc_module_info { 1882 struct rtw89_btc_module md; 1883 struct rtw89_btc_module_v7 md_v7; 1884 }; 1885 1886 #define RTW89_BTC_DM_MAXSTEP 30 1887 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1888 1889 struct rtw89_btc_dm_step { 1890 u16 step[RTW89_BTC_DM_MAXSTEP]; 1891 u8 step_pos; 1892 bool step_ov; 1893 }; 1894 1895 struct rtw89_btc_init_info { 1896 struct rtw89_btc_module module; 1897 u8 wl_guard_ch; 1898 1899 u8 wl_only: 1; 1900 u8 wl_init_ok: 1; 1901 u8 dbcc_en: 1; 1902 u8 cx_other: 1; 1903 u8 bt_only: 1; 1904 1905 u16 rsvd; 1906 }; 1907 1908 struct rtw89_btc_init_info_v7 { 1909 u8 wl_guard_ch; 1910 u8 wl_only; 1911 u8 wl_init_ok; 1912 u8 rsvd3; 1913 1914 u8 cx_other; 1915 u8 bt_only; 1916 u8 pta_mode; 1917 u8 pta_direction; 1918 1919 struct rtw89_btc_module_v7 module; 1920 } __packed; 1921 1922 union rtw89_btc_init_info_u { 1923 struct rtw89_btc_init_info init; 1924 struct rtw89_btc_init_info_v7 init_v7; 1925 }; 1926 1927 struct rtw89_btc_wl_tx_limit_para { 1928 u16 enable; 1929 u32 tx_time; /* unit: us */ 1930 u16 tx_retry; 1931 }; 1932 1933 enum rtw89_btc_bt_scan_type { 1934 BTC_SCAN_INQ = 0, 1935 BTC_SCAN_PAGE, 1936 BTC_SCAN_BLE, 1937 BTC_SCAN_INIT, 1938 BTC_SCAN_TV, 1939 BTC_SCAN_ADV, 1940 BTC_SCAN_MAX1, 1941 }; 1942 1943 enum rtw89_btc_ble_scan_type { 1944 CXSCAN_BG = 0, 1945 CXSCAN_INIT, 1946 CXSCAN_LE, 1947 CXSCAN_MAX 1948 }; 1949 1950 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1951 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1952 1953 struct rtw89_btc_bt_scan_info_v1 { 1954 __le16 win; 1955 __le16 intvl; 1956 __le32 flags; 1957 } __packed; 1958 1959 struct rtw89_btc_bt_scan_info_v2 { 1960 __le16 win; 1961 __le16 intvl; 1962 } __packed; 1963 1964 struct rtw89_btc_fbtc_btscan_v1 { 1965 u8 fver; /* btc_ver::fcxbtscan */ 1966 u8 rsvd; 1967 __le16 rsvd2; 1968 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1969 } __packed; 1970 1971 struct rtw89_btc_fbtc_btscan_v2 { 1972 u8 fver; /* btc_ver::fcxbtscan */ 1973 u8 type; 1974 __le16 rsvd2; 1975 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1976 } __packed; 1977 1978 struct rtw89_btc_fbtc_btscan_v7 { 1979 u8 fver; /* btc_ver::fcxbtscan */ 1980 u8 type; 1981 u8 rsvd0; 1982 u8 rsvd1; 1983 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1984 } __packed; 1985 1986 union rtw89_btc_fbtc_btscan { 1987 struct rtw89_btc_fbtc_btscan_v1 v1; 1988 struct rtw89_btc_fbtc_btscan_v2 v2; 1989 struct rtw89_btc_fbtc_btscan_v7 v7; 1990 }; 1991 1992 struct rtw89_btc_bt_info { 1993 struct rtw89_btc_bt_link_info link_info; 1994 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1995 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1996 struct rtw89_btc_bt_ver_info ver_info; 1997 struct rtw89_btc_bool_sta_chg enable; 1998 struct rtw89_btc_bool_sta_chg inq_pag; 1999 struct rtw89_btc_rf_para rf_para; 2000 union rtw89_btc_bt_rfk_info_map rfk_info; 2001 2002 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2003 u8 rssi_level; 2004 2005 u32 scbd; 2006 u32 feature; 2007 2008 u32 mbx_avl: 1; 2009 u32 whql_test: 1; 2010 u32 igno_wl: 1; 2011 u32 reinit: 1; 2012 u32 ble_scan_en: 1; 2013 u32 btg_type: 1; 2014 u32 inq: 1; 2015 u32 pag: 1; 2016 u32 run_patch_code: 1; 2017 u32 hi_lna_rx: 1; 2018 u32 scan_rx_low_pri: 1; 2019 u32 scan_info_update: 1; 2020 u32 lna_constrain: 3; 2021 u32 rsvd: 17; 2022 }; 2023 2024 struct rtw89_btc_cx { 2025 struct rtw89_btc_wl_info wl; 2026 struct rtw89_btc_bt_info bt; 2027 struct rtw89_btc_3rdcx_info other; 2028 u32 state_map; 2029 u32 cnt_bt[BTC_BCNT_NUM]; 2030 u32 cnt_wl[BTC_WCNT_NUM]; 2031 }; 2032 2033 struct rtw89_btc_fbtc_tdma { 2034 u8 type; /* btc_ver::fcxtdma */ 2035 u8 rxflctrl; 2036 u8 txpause; 2037 u8 wtgle_n; 2038 u8 leak_n; 2039 u8 ext_ctrl; 2040 u8 rxflctrl_role; 2041 u8 option_ctrl; 2042 } __packed; 2043 2044 struct rtw89_btc_fbtc_tdma_v3 { 2045 u8 fver; /* btc_ver::fcxtdma */ 2046 u8 rsvd; 2047 __le16 rsvd1; 2048 struct rtw89_btc_fbtc_tdma tdma; 2049 } __packed; 2050 2051 union rtw89_btc_fbtc_tdma_le32 { 2052 struct rtw89_btc_fbtc_tdma v1; 2053 struct rtw89_btc_fbtc_tdma_v3 v3; 2054 }; 2055 2056 #define CXMREG_MAX 30 2057 #define CXMREG_MAX_V2 20 2058 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2059 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2060 2061 enum rtw89_btc_bt_sta_counter { 2062 BTC_BCNT_RFK_REQ = 0, 2063 BTC_BCNT_RFK_GO = 1, 2064 BTC_BCNT_RFK_REJECT = 2, 2065 BTC_BCNT_RFK_FAIL = 3, 2066 BTC_BCNT_RFK_TIMEOUT = 4, 2067 BTC_BCNT_HI_TX = 5, 2068 BTC_BCNT_HI_RX = 6, 2069 BTC_BCNT_LO_TX = 7, 2070 BTC_BCNT_LO_RX = 8, 2071 BTC_BCNT_POLLUTED = 9, 2072 BTC_BCNT_STA_MAX 2073 }; 2074 2075 enum rtw89_btc_bt_sta_counter_v105 { 2076 BTC_BCNT_RFK_REQ_V105 = 0, 2077 BTC_BCNT_HI_TX_V105 = 1, 2078 BTC_BCNT_HI_RX_V105 = 2, 2079 BTC_BCNT_LO_TX_V105 = 3, 2080 BTC_BCNT_LO_RX_V105 = 4, 2081 BTC_BCNT_POLLUTED_V105 = 5, 2082 BTC_BCNT_STA_MAX_V105 2083 }; 2084 2085 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2086 u16 fver; /* btc_ver::fcxbtcrpt */ 2087 u16 rpt_cnt; /* tmr counters */ 2088 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2089 u32 wl_fw_cx_offload; 2090 u32 wl_fw_ver; 2091 u32 rpt_enable; 2092 u32 rpt_para; /* ms */ 2093 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2094 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2095 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2096 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2097 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2098 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2099 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2100 u32 c2h_cnt; /* fw send c2h counter */ 2101 u32 h2c_cnt; /* fw recv h2c counter */ 2102 } __packed; 2103 2104 struct rtw89_btc_fbtc_rpt_ctrl_info { 2105 __le32 cnt; /* fw report counter */ 2106 __le32 en; /* report map */ 2107 __le32 para; /* not used */ 2108 2109 __le32 cnt_c2h; /* fw send c2h counter */ 2110 __le32 cnt_h2c; /* fw recv h2c counter */ 2111 __le32 len_c2h; /* The total length of the last C2H */ 2112 2113 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2114 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2115 } __packed; 2116 2117 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2118 __le32 cx_ver; /* match which driver's coex version */ 2119 __le32 fw_ver; 2120 __le32 en; /* report map */ 2121 2122 __le16 cnt; /* fw report counter */ 2123 __le16 cnt_c2h; /* fw send c2h counter */ 2124 __le16 cnt_h2c; /* fw recv h2c counter */ 2125 __le16 len_c2h; /* The total length of the last C2H */ 2126 2127 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2128 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2129 } __packed; 2130 2131 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2132 __le16 cnt; /* fw report counter */ 2133 __le16 cnt_c2h; /* fw send c2h counter */ 2134 __le16 cnt_h2c; /* fw recv h2c counter */ 2135 __le16 len_c2h; /* The total length of the last C2H */ 2136 2137 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2138 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2139 2140 __le32 cx_ver; /* match which driver's coex version */ 2141 __le32 fw_ver; 2142 __le32 en; /* report map */ 2143 } __packed; 2144 2145 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2146 __le32 cx_ver; /* match which driver's coex version */ 2147 __le32 cx_offload; 2148 __le32 fw_ver; 2149 } __packed; 2150 2151 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2152 __le32 cnt_empty; /* a2dp empty count */ 2153 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2154 __le32 cnt_tx; 2155 __le32 cnt_ack; 2156 __le32 cnt_nack; 2157 } __packed; 2158 2159 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2160 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2161 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2162 __le32 cnt_recv; /* fw recv mailbox counter */ 2163 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2164 } __packed; 2165 2166 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2167 u8 fver; 2168 u8 rsvd; 2169 __le16 rsvd1; 2170 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2171 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2172 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2173 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2174 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2175 } __packed; 2176 2177 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2178 u8 fver; 2179 u8 rsvd; 2180 __le16 rsvd1; 2181 2182 u8 gnt_val[RTW89_PHY_MAX][4]; 2183 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2184 2185 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2186 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2187 } __packed; 2188 2189 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2190 u8 fver; 2191 u8 rsvd; 2192 __le16 rsvd1; 2193 2194 u8 gnt_val[RTW89_PHY_MAX][4]; 2195 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2196 2197 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2198 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2199 } __packed; 2200 2201 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2202 u8 fver; 2203 u8 rsvd0; 2204 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2205 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2206 2207 u8 gnt_val[RTW89_PHY_MAX][4]; 2208 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2209 2210 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2211 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2212 } __packed; 2213 2214 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2215 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2216 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2217 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2218 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2219 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2220 }; 2221 2222 enum rtw89_fbtc_ext_ctrl_type { 2223 CXECTL_OFF = 0x0, /* tdma off */ 2224 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2225 CXECTL_EXT = 0x2, 2226 CXECTL_MAX 2227 }; 2228 2229 union rtw89_btc_fbtc_rxflct { 2230 u8 val; 2231 u8 type: 3; 2232 u8 tgln_n: 5; 2233 }; 2234 2235 enum rtw89_btc_cxst_state { 2236 CXST_OFF = 0x0, 2237 CXST_B2W = 0x1, 2238 CXST_W1 = 0x2, 2239 CXST_W2 = 0x3, 2240 CXST_W2B = 0x4, 2241 CXST_B1 = 0x5, 2242 CXST_B2 = 0x6, 2243 CXST_B3 = 0x7, 2244 CXST_B4 = 0x8, 2245 CXST_LK = 0x9, 2246 CXST_BLK = 0xa, 2247 CXST_E2G = 0xb, 2248 CXST_E5G = 0xc, 2249 CXST_EBT = 0xd, 2250 CXST_ENULL = 0xe, 2251 CXST_WLK = 0xf, 2252 CXST_W1FDD = 0x10, 2253 CXST_B1FDD = 0x11, 2254 CXST_MAX = 0x12, 2255 }; 2256 2257 enum rtw89_btc_cxevnt { 2258 CXEVNT_TDMA_ENTRY = 0x0, 2259 CXEVNT_WL_TMR, 2260 CXEVNT_B1_TMR, 2261 CXEVNT_B2_TMR, 2262 CXEVNT_B3_TMR, 2263 CXEVNT_B4_TMR, 2264 CXEVNT_W2B_TMR, 2265 CXEVNT_B2W_TMR, 2266 CXEVNT_BCN_EARLY, 2267 CXEVNT_A2DP_EMPTY, 2268 CXEVNT_LK_END, 2269 CXEVNT_RX_ISR, 2270 CXEVNT_RX_FC0, 2271 CXEVNT_RX_FC1, 2272 CXEVNT_BT_RELINK, 2273 CXEVNT_BT_RETRY, 2274 CXEVNT_E2G, 2275 CXEVNT_E5G, 2276 CXEVNT_EBT, 2277 CXEVNT_ENULL, 2278 CXEVNT_DRV_WLK, 2279 CXEVNT_BCN_OK, 2280 CXEVNT_BT_CHANGE, 2281 CXEVNT_EBT_EXTEND, 2282 CXEVNT_E2G_NULL1, 2283 CXEVNT_B1FDD_TMR, 2284 CXEVNT_MAX 2285 }; 2286 2287 enum { 2288 CXBCN_ALL = 0x0, 2289 CXBCN_ALL_OK, 2290 CXBCN_BT_SLOT, 2291 CXBCN_BT_OK, 2292 CXBCN_MAX 2293 }; 2294 2295 enum btc_slot_type { 2296 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2297 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2298 CXSTYPE_NUM, 2299 }; 2300 2301 enum { /* TIME */ 2302 CXT_BT = 0x0, 2303 CXT_WL = 0x1, 2304 CXT_MAX 2305 }; 2306 2307 enum { /* TIME-A2DP */ 2308 CXT_FLCTRL_OFF = 0x0, 2309 CXT_FLCTRL_ON = 0x1, 2310 CXT_FLCTRL_MAX 2311 }; 2312 2313 enum { /* STEP TYPE */ 2314 CXSTEP_NONE = 0x0, 2315 CXSTEP_EVNT = 0x1, 2316 CXSTEP_SLOT = 0x2, 2317 CXSTEP_MAX, 2318 }; 2319 2320 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2321 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2322 RPT_BT_AFH_SEQ_LE = 0x20 2323 }; 2324 2325 #define BTC_DBG_MAX1 32 2326 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2327 u8 fver; /* btc_ver::fcxgpiodbg */ 2328 u8 rsvd; 2329 __le16 rsvd2; 2330 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2331 __le32 pre_state; /* the debug signal is 1 or 0 */ 2332 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2333 } __packed; 2334 2335 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2336 u8 fver; 2337 u8 rsvd0; 2338 u8 rsvd1; 2339 u8 rsvd2; 2340 2341 u8 gpio_map[BTC_DBG_MAX1]; 2342 2343 __le32 en_map; 2344 __le32 pre_state; 2345 } __packed; 2346 2347 union rtw89_btc_fbtc_gpio_dbg { 2348 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2349 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2350 }; 2351 2352 struct rtw89_btc_fbtc_mreg_val_v1 { 2353 u8 fver; /* btc_ver::fcxmreg */ 2354 u8 reg_num; 2355 __le16 rsvd; 2356 __le32 mreg_val[CXMREG_MAX]; 2357 } __packed; 2358 2359 struct rtw89_btc_fbtc_mreg_val_v2 { 2360 u8 fver; /* btc_ver::fcxmreg */ 2361 u8 reg_num; 2362 __le16 rsvd; 2363 __le32 mreg_val[CXMREG_MAX_V2]; 2364 } __packed; 2365 2366 struct rtw89_btc_fbtc_mreg_val_v7 { 2367 u8 fver; 2368 u8 reg_num; 2369 u8 rsvd0; 2370 u8 rsvd1; 2371 __le32 mreg_val[CXMREG_MAX_V2]; 2372 } __packed; 2373 2374 union rtw89_btc_fbtc_mreg_val { 2375 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2376 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2377 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2378 }; 2379 2380 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2381 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2382 .offset = cpu_to_le32(__offset), } 2383 2384 struct rtw89_btc_fbtc_mreg { 2385 __le16 type; 2386 __le16 bytes; 2387 __le32 offset; 2388 } __packed; 2389 2390 struct rtw89_btc_fbtc_slot { 2391 __le16 dur; 2392 __le32 cxtbl; 2393 __le16 cxtype; 2394 } __packed; 2395 2396 struct rtw89_btc_fbtc_slots { 2397 u8 fver; /* btc_ver::fcxslots */ 2398 u8 tbl_num; 2399 __le16 rsvd; 2400 __le32 update_map; 2401 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2402 } __packed; 2403 2404 struct rtw89_btc_fbtc_slot_v7 { 2405 __le16 dur; /* slot duration */ 2406 __le16 cxtype; 2407 __le32 cxtbl; 2408 } __packed; 2409 2410 struct rtw89_btc_fbtc_slot_u16 { 2411 __le16 dur; /* slot duration */ 2412 __le16 cxtype; 2413 __le16 cxtbl_l16; /* coex table [15:0] */ 2414 __le16 cxtbl_h16; /* coex table [31:16] */ 2415 } __packed; 2416 2417 struct rtw89_btc_fbtc_1slot_v7 { 2418 u8 fver; 2419 u8 sid; /* slot id */ 2420 __le16 rsvd; 2421 struct rtw89_btc_fbtc_slot_v7 slot; 2422 } __packed; 2423 2424 struct rtw89_btc_fbtc_slots_v7 { 2425 u8 fver; 2426 u8 slot_cnt; 2427 u8 rsvd0; 2428 u8 rsvd1; 2429 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2430 __le32 update_map; 2431 } __packed; 2432 2433 union rtw89_btc_fbtc_slots_info { 2434 struct rtw89_btc_fbtc_slots v1; 2435 struct rtw89_btc_fbtc_slots_v7 v7; 2436 } __packed; 2437 2438 struct rtw89_btc_fbtc_step { 2439 u8 type; 2440 u8 val; 2441 __le16 difft; 2442 } __packed; 2443 2444 struct rtw89_btc_fbtc_steps_v2 { 2445 u8 fver; /* btc_ver::fcxstep */ 2446 u8 rsvd; 2447 __le16 cnt; 2448 __le16 pos_old; 2449 __le16 pos_new; 2450 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2451 } __packed; 2452 2453 struct rtw89_btc_fbtc_steps_v3 { 2454 u8 fver; 2455 u8 en; 2456 __le16 rsvd; 2457 __le32 cnt; 2458 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2459 } __packed; 2460 2461 union rtw89_btc_fbtc_steps_info { 2462 struct rtw89_btc_fbtc_steps_v2 v2; 2463 struct rtw89_btc_fbtc_steps_v3 v3; 2464 }; 2465 2466 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2467 u8 fver; /* btc_ver::fcxcysta */ 2468 u8 rsvd; 2469 __le16 cycles; /* total cycle number */ 2470 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2471 __le16 a2dpept; /* a2dp empty cnt */ 2472 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2473 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2474 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2475 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2476 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2477 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2478 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2479 __le16 tmax_a2dpept; /* max a2dp empty time */ 2480 __le16 tavg_lk; /* avg leak-slot time */ 2481 __le16 tmax_lk; /* max leak-slot time */ 2482 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2483 __le32 bcn_cnt[CXBCN_MAX]; 2484 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2485 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2486 __le32 skip_cnt; 2487 __le32 exception; 2488 __le32 except_cnt; 2489 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2490 } __packed; 2491 2492 struct rtw89_btc_fbtc_fdd_try_info { 2493 __le16 cycles[CXT_FLCTRL_MAX]; 2494 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2495 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2496 } __packed; 2497 2498 struct rtw89_btc_fbtc_cycle_time_info { 2499 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2500 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2501 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2502 } __packed; 2503 2504 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2505 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2506 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2507 } __packed; 2508 2509 struct rtw89_btc_fbtc_a2dp_trx_stat { 2510 u8 empty_cnt; 2511 u8 retry_cnt; 2512 u8 tx_rate; 2513 u8 tx_cnt; 2514 u8 ack_cnt; 2515 u8 nack_cnt; 2516 u8 rsvd1; 2517 u8 rsvd2; 2518 } __packed; 2519 2520 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2521 u8 empty_cnt; 2522 u8 retry_cnt; 2523 u8 tx_rate; 2524 u8 tx_cnt; 2525 u8 ack_cnt; 2526 u8 nack_cnt; 2527 u8 no_empty_cnt; 2528 u8 rsvd; 2529 } __packed; 2530 2531 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2532 __le16 cnt; /* a2dp empty cnt */ 2533 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2534 __le16 tavg; /* avg a2dp empty time */ 2535 __le16 tmax; /* max a2dp empty time */ 2536 } __packed; 2537 2538 struct rtw89_btc_fbtc_cycle_leak_info { 2539 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2540 __le16 tavg; /* avg leak-slot time */ 2541 __le16 tmax; /* max leak-slot time */ 2542 } __packed; 2543 2544 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2545 __le16 tavg; 2546 __le16 tamx; 2547 __le32 cnt_rximr; 2548 } __packed; 2549 2550 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2551 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2552 2553 struct rtw89_btc_fbtc_cycle_fddt_info { 2554 __le16 train_cycle; 2555 __le16 tp; 2556 2557 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2558 s8 bt_tx_power; /* decrease Tx power (dB) */ 2559 s8 bt_rx_gain; /* LNA constrain level */ 2560 u8 no_empty_cnt; 2561 2562 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2563 u8 cn; /* condition_num */ 2564 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2565 u8 train_result; /* refer to enum btc_fddt_check_map */ 2566 } __packed; 2567 2568 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2569 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2570 2571 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2572 __le16 train_cycle; 2573 __le16 tp; 2574 2575 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2576 s8 bt_tx_power; /* decrease Tx power (dB) */ 2577 s8 bt_rx_gain; /* LNA constrain level */ 2578 u8 no_empty_cnt; 2579 2580 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2581 u8 cn; /* condition_num */ 2582 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2583 u8 train_result; /* refer to enum btc_fddt_check_map */ 2584 } __packed; 2585 2586 struct rtw89_btc_fbtc_fddt_cell_status { 2587 s8 wl_tx_pwr; 2588 s8 bt_tx_pwr; 2589 s8 bt_rx_gain; 2590 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2591 } __packed; 2592 2593 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2594 u8 fver; 2595 u8 rsvd; 2596 __le16 cycles; /* total cycle number */ 2597 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2598 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2599 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2600 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2601 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2602 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2603 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2604 __le32 bcn_cnt[CXBCN_MAX]; 2605 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2606 __le32 skip_cnt; 2607 __le32 except_cnt; 2608 __le32 except_map; 2609 } __packed; 2610 2611 #define FDD_TRAIN_WL_DIRECTION 2 2612 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2613 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2614 2615 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2616 u8 fver; 2617 u8 rsvd; 2618 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2619 u8 except_cnt; 2620 2621 __le16 skip_cnt; 2622 __le16 cycles; /* total cycle number */ 2623 2624 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2625 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2626 __le16 bcn_cnt[CXBCN_MAX]; 2627 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2628 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2629 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2630 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2631 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2632 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2633 [FDD_TRAIN_WL_RSSI_LEVEL] 2634 [FDD_TRAIN_BT_RSSI_LEVEL]; 2635 __le32 except_map; 2636 } __packed; 2637 2638 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2639 u8 fver; 2640 u8 rsvd; 2641 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2642 u8 except_cnt; 2643 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2644 2645 __le16 skip_cnt; 2646 __le16 cycles; /* total cycle number */ 2647 2648 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2649 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2650 __le16 bcn_cnt[CXBCN_MAX]; 2651 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2652 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2653 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2654 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2655 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2656 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2657 [FDD_TRAIN_WL_RSSI_LEVEL] 2658 [FDD_TRAIN_BT_RSSI_LEVEL]; 2659 __le32 except_map; 2660 } __packed; 2661 2662 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2663 u8 fver; 2664 u8 rsvd; 2665 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2666 u8 except_cnt; 2667 2668 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2669 2670 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2671 2672 __le16 skip_cnt; 2673 __le16 cycles; /* total cycle number */ 2674 2675 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2676 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2677 __le16 bcn_cnt[CXBCN_MAX]; 2678 2679 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2680 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2681 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2682 2683 __le32 except_map; 2684 } __packed; 2685 2686 union rtw89_btc_fbtc_cysta_info { 2687 struct rtw89_btc_fbtc_cysta_v2 v2; 2688 struct rtw89_btc_fbtc_cysta_v3 v3; 2689 struct rtw89_btc_fbtc_cysta_v4 v4; 2690 struct rtw89_btc_fbtc_cysta_v5 v5; 2691 struct rtw89_btc_fbtc_cysta_v7 v7; 2692 }; 2693 2694 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2695 u8 fver; /* btc_ver::fcxnullsta */ 2696 u8 rsvd; 2697 __le16 rsvd2; 2698 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2699 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2700 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2701 } __packed; 2702 2703 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2704 u8 fver; /* btc_ver::fcxnullsta */ 2705 u8 rsvd; 2706 __le16 rsvd2; 2707 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2708 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2709 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2710 } __packed; 2711 2712 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2713 u8 fver; 2714 u8 rsvd0; 2715 u8 rsvd1; 2716 u8 rsvd2; 2717 2718 __le32 tmax[2]; 2719 __le32 tavg[2]; 2720 __le32 result[2][5]; 2721 } __packed; 2722 2723 union rtw89_btc_fbtc_cynullsta_info { 2724 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2725 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2726 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2727 }; 2728 2729 struct rtw89_btc_fbtc_btver_v1 { 2730 u8 fver; /* btc_ver::fcxbtver */ 2731 u8 rsvd; 2732 __le16 rsvd2; 2733 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2734 __le32 fw_ver; 2735 __le32 feature; 2736 } __packed; 2737 2738 struct rtw89_btc_fbtc_btver_v7 { 2739 u8 fver; 2740 u8 rsvd0; 2741 u8 rsvd1; 2742 u8 rsvd2; 2743 2744 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2745 __le32 fw_ver; 2746 __le32 feature; 2747 } __packed; 2748 2749 union rtw89_btc_fbtc_btver { 2750 struct rtw89_btc_fbtc_btver_v1 v1; 2751 struct rtw89_btc_fbtc_btver_v7 v7; 2752 } __packed; 2753 2754 struct rtw89_btc_fbtc_btafh { 2755 u8 fver; /* btc_ver::fcxbtafh */ 2756 u8 rsvd; 2757 __le16 rsvd2; 2758 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2759 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2760 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2761 } __packed; 2762 2763 struct rtw89_btc_fbtc_btafh_v2 { 2764 u8 fver; /* btc_ver::fcxbtafh */ 2765 u8 rsvd; 2766 u8 rsvd2; 2767 u8 map_type; 2768 u8 afh_l[4]; 2769 u8 afh_m[4]; 2770 u8 afh_h[4]; 2771 u8 afh_le_a[4]; 2772 u8 afh_le_b[4]; 2773 } __packed; 2774 2775 struct rtw89_btc_fbtc_btafh_v7 { 2776 u8 fver; 2777 u8 map_type; 2778 u8 rsvd0; 2779 u8 rsvd1; 2780 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2781 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2782 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2783 u8 afh_le_a[4]; 2784 u8 afh_le_b[4]; 2785 } __packed; 2786 2787 struct rtw89_btc_fbtc_btdevinfo { 2788 u8 fver; /* btc_ver::fcxbtdevinfo */ 2789 u8 rsvd; 2790 __le16 vendor_id; 2791 __le32 dev_name; /* only 24 bits valid */ 2792 __le32 flush_time; 2793 } __packed; 2794 2795 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2796 struct rtw89_btc_rf_trx_para { 2797 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2798 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2799 u8 bt_tx_power; /* decrease Tx power (dB) */ 2800 u8 bt_rx_gain; /* LNA constrain level */ 2801 }; 2802 2803 struct rtw89_btc_trx_info { 2804 u8 tx_lvl; 2805 u8 rx_lvl; 2806 u8 wl_rssi; 2807 u8 bt_rssi; 2808 2809 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2810 s8 rx_gain; /* rx gain table index (TBD.) */ 2811 s8 bt_tx_power; /* decrease Tx power (dB) */ 2812 s8 bt_rx_gain; /* LNA constrain level */ 2813 2814 u8 cn; /* condition_num */ 2815 s8 nhm; 2816 u8 bt_profile; 2817 u8 rsvd2; 2818 2819 u16 tx_rate; 2820 u16 rx_rate; 2821 2822 u32 tx_tp; 2823 u32 rx_tp; 2824 u32 rx_err_ratio; 2825 }; 2826 2827 union rtw89_btc_fbtc_slot_u { 2828 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2829 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2830 }; 2831 2832 struct rtw89_btc_dm { 2833 union rtw89_btc_fbtc_slot_u slot; 2834 union rtw89_btc_fbtc_slot_u slot_now; 2835 struct rtw89_btc_fbtc_tdma tdma; 2836 struct rtw89_btc_fbtc_tdma tdma_now; 2837 struct rtw89_mac_ax_coex_gnt gnt; 2838 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2839 struct rtw89_btc_rf_trx_para rf_trx_para; 2840 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2841 struct rtw89_btc_dm_step dm_step; 2842 struct rtw89_btc_wl_scc_ctrl wl_scc; 2843 struct rtw89_btc_trx_info trx_info; 2844 union rtw89_btc_dm_error_map error; 2845 u32 cnt_dm[BTC_DCNT_NUM]; 2846 u32 cnt_notify[BTC_NCNT_NUM]; 2847 2848 u32 update_slot_map; 2849 u32 set_ant_path; 2850 u32 e2g_slot_limit; 2851 u32 e2g_slot_nulltx_time; 2852 2853 u32 wl_only: 1; 2854 u32 wl_fw_cx_offload: 1; 2855 u32 freerun: 1; 2856 u32 fddt_train: 1; 2857 u32 wl_ps_ctrl: 2; 2858 u32 wl_mimo_ps: 1; 2859 u32 leak_ap: 1; 2860 u32 noisy_level: 3; 2861 u32 coex_info_map: 8; 2862 u32 bt_only: 1; 2863 u32 wl_btg_rx: 2; 2864 u32 trx_para_level: 8; 2865 u32 wl_stb_chg: 1; 2866 u32 pta_owner: 1; 2867 2868 u32 tdma_instant_excute: 1; 2869 u32 wl_btg_rx_rb: 2; 2870 2871 u16 slot_dur[CXST_MAX]; 2872 u16 bt_slot_flood; 2873 2874 u8 run_reason; 2875 u8 run_action; 2876 2877 u8 wl_pre_agc: 2; 2878 u8 wl_lna2: 1; 2879 u8 wl_pre_agc_rb: 2; 2880 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2881 u8 slot_req_more: 1; 2882 }; 2883 2884 struct rtw89_btc_ctrl { 2885 u32 manual: 1; 2886 u32 igno_bt: 1; 2887 u32 always_freerun: 1; 2888 u32 trace_step: 16; 2889 u32 rsvd: 12; 2890 }; 2891 2892 struct rtw89_btc_ctrl_v7 { 2893 u8 manual; 2894 u8 igno_bt; 2895 u8 always_freerun; 2896 u8 rsvd; 2897 } __packed; 2898 2899 union rtw89_btc_ctrl_list { 2900 struct rtw89_btc_ctrl ctrl; 2901 struct rtw89_btc_ctrl_v7 ctrl_v7; 2902 }; 2903 2904 struct rtw89_btc_dbg { 2905 /* cmd "rb" */ 2906 bool rb_done; 2907 u32 rb_val; 2908 }; 2909 2910 enum rtw89_btc_btf_fw_event { 2911 BTF_EVNT_RPT = 0, 2912 BTF_EVNT_BT_INFO = 1, 2913 BTF_EVNT_BT_SCBD = 2, 2914 BTF_EVNT_BT_REG = 3, 2915 BTF_EVNT_CX_RUNINFO = 4, 2916 BTF_EVNT_BT_PSD = 5, 2917 BTF_EVNT_BUF_OVERFLOW, 2918 BTF_EVNT_C2H_LOOPBACK, 2919 BTF_EVNT_MAX, 2920 }; 2921 2922 enum btf_fw_event_report { 2923 BTC_RPT_TYPE_CTRL = 0x0, 2924 BTC_RPT_TYPE_TDMA, 2925 BTC_RPT_TYPE_SLOT, 2926 BTC_RPT_TYPE_CYSTA, 2927 BTC_RPT_TYPE_STEP, 2928 BTC_RPT_TYPE_NULLSTA, 2929 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 2930 BTC_RPT_TYPE_MREG, 2931 BTC_RPT_TYPE_GPIO_DBG, 2932 BTC_RPT_TYPE_BT_VER, 2933 BTC_RPT_TYPE_BT_SCAN, 2934 BTC_RPT_TYPE_BT_AFH, 2935 BTC_RPT_TYPE_BT_DEVICE, 2936 BTC_RPT_TYPE_TEST, 2937 BTC_RPT_TYPE_MAX = 31, 2938 2939 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 2940 __BTC_RPT_TYPE_V0_MAX = 12, 2941 }; 2942 2943 enum rtw_btc_btf_reg_type { 2944 REG_MAC = 0x0, 2945 REG_BB = 0x1, 2946 REG_RF = 0x2, 2947 REG_BT_RF = 0x3, 2948 REG_BT_MODEM = 0x4, 2949 REG_BT_BLUEWIZE = 0x5, 2950 REG_BT_VENDOR = 0x6, 2951 REG_BT_LE = 0x7, 2952 REG_MAX_TYPE, 2953 }; 2954 2955 struct rtw89_btc_rpt_cmn_info { 2956 u32 rx_cnt; 2957 u32 rx_len; 2958 u32 req_len; /* expected rsp len */ 2959 u8 req_fver; /* expected rsp fver */ 2960 u8 rsp_fver; /* fver from fw */ 2961 u8 valid; 2962 } __packed; 2963 2964 union rtw89_btc_fbtc_btafh_info { 2965 struct rtw89_btc_fbtc_btafh v1; 2966 struct rtw89_btc_fbtc_btafh_v2 v2; 2967 }; 2968 2969 struct rtw89_btc_report_ctrl_state { 2970 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2971 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2972 }; 2973 2974 struct rtw89_btc_rpt_fbtc_tdma { 2975 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2976 union rtw89_btc_fbtc_tdma_le32 finfo; 2977 }; 2978 2979 struct rtw89_btc_rpt_fbtc_slots { 2980 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2981 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 2982 }; 2983 2984 struct rtw89_btc_rpt_fbtc_cysta { 2985 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2986 union rtw89_btc_fbtc_cysta_info finfo; 2987 }; 2988 2989 struct rtw89_btc_rpt_fbtc_step { 2990 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2991 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2992 }; 2993 2994 struct rtw89_btc_rpt_fbtc_nullsta { 2995 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2996 union rtw89_btc_fbtc_cynullsta_info finfo; 2997 }; 2998 2999 struct rtw89_btc_rpt_fbtc_mreg { 3000 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3001 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3002 }; 3003 3004 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3005 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3006 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3007 }; 3008 3009 struct rtw89_btc_rpt_fbtc_btver { 3010 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3011 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3012 }; 3013 3014 struct rtw89_btc_rpt_fbtc_btscan { 3015 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3016 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3017 }; 3018 3019 struct rtw89_btc_rpt_fbtc_btafh { 3020 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3021 union rtw89_btc_fbtc_btafh_info finfo; 3022 }; 3023 3024 struct rtw89_btc_rpt_fbtc_btdev { 3025 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3026 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3027 }; 3028 3029 enum rtw89_btc_btfre_type { 3030 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3031 BTFRE_UNDEF_TYPE, 3032 BTFRE_EXCEPTION, 3033 BTFRE_MAX, 3034 }; 3035 3036 struct rtw89_btc_btf_fwinfo { 3037 u32 cnt_c2h; 3038 u32 cnt_h2c; 3039 u32 cnt_h2c_fail; 3040 u32 event[BTF_EVNT_MAX]; 3041 3042 u32 err[BTFRE_MAX]; 3043 u32 len_mismch; 3044 u32 fver_mismch; 3045 u32 rpt_en_map; 3046 3047 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3048 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3049 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3050 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3051 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3052 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3053 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3054 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3055 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3056 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3057 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3058 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3059 }; 3060 3061 struct rtw89_btc_ver { 3062 enum rtw89_core_chip_id chip_id; 3063 u32 fw_ver_code; 3064 3065 u8 fcxbtcrpt; 3066 u8 fcxtdma; 3067 u8 fcxslots; 3068 u8 fcxcysta; 3069 u8 fcxstep; 3070 u8 fcxnullsta; 3071 u8 fcxmreg; 3072 u8 fcxgpiodbg; 3073 u8 fcxbtver; 3074 u8 fcxbtscan; 3075 u8 fcxbtafh; 3076 u8 fcxbtdevinfo; 3077 u8 fwlrole; 3078 u8 frptmap; 3079 u8 fcxctrl; 3080 u8 fcxinit; 3081 3082 u8 fwevntrptl; 3083 u8 drvinfo_type; 3084 u16 info_buf; 3085 u8 max_role_num; 3086 }; 3087 3088 #define RTW89_BTC_POLICY_MAXLEN 512 3089 3090 struct rtw89_btc { 3091 const struct rtw89_btc_ver *ver; 3092 3093 struct rtw89_btc_cx cx; 3094 struct rtw89_btc_dm dm; 3095 union rtw89_btc_ctrl_list ctrl; 3096 union rtw89_btc_module_info mdinfo; 3097 struct rtw89_btc_btf_fwinfo fwinfo; 3098 struct rtw89_btc_dbg dbg; 3099 3100 struct work_struct eapol_notify_work; 3101 struct work_struct arp_notify_work; 3102 struct work_struct dhcp_notify_work; 3103 struct work_struct icmp_notify_work; 3104 3105 u32 bt_req_len; 3106 3107 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3108 u8 ant_type; 3109 u8 btg_pos; 3110 u16 policy_len; 3111 u16 policy_type; 3112 u32 hubmsg_cnt; 3113 bool bt_req_en; 3114 bool update_policy_force; 3115 bool lps; 3116 bool manual_ctrl; 3117 }; 3118 3119 enum rtw89_btc_hmsg { 3120 RTW89_BTC_HMSG_TMR_EN = 0x0, 3121 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3122 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3123 RTW89_BTC_HMSG_FW_EV = 0x3, 3124 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3125 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3126 3127 NUM_OF_RTW89_BTC_HMSG, 3128 }; 3129 3130 enum rtw89_ra_mode { 3131 RTW89_RA_MODE_CCK = BIT(0), 3132 RTW89_RA_MODE_OFDM = BIT(1), 3133 RTW89_RA_MODE_HT = BIT(2), 3134 RTW89_RA_MODE_VHT = BIT(3), 3135 RTW89_RA_MODE_HE = BIT(4), 3136 RTW89_RA_MODE_EHT = BIT(5), 3137 }; 3138 3139 enum rtw89_ra_report_mode { 3140 RTW89_RA_RPT_MODE_LEGACY, 3141 RTW89_RA_RPT_MODE_HT, 3142 RTW89_RA_RPT_MODE_VHT, 3143 RTW89_RA_RPT_MODE_HE, 3144 RTW89_RA_RPT_MODE_EHT, 3145 }; 3146 3147 enum rtw89_dig_noisy_level { 3148 RTW89_DIG_NOISY_LEVEL0 = -1, 3149 RTW89_DIG_NOISY_LEVEL1 = 0, 3150 RTW89_DIG_NOISY_LEVEL2 = 1, 3151 RTW89_DIG_NOISY_LEVEL3 = 2, 3152 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3153 }; 3154 3155 enum rtw89_gi_ltf { 3156 RTW89_GILTF_LGI_4XHE32 = 0, 3157 RTW89_GILTF_SGI_4XHE08 = 1, 3158 RTW89_GILTF_2XHE16 = 2, 3159 RTW89_GILTF_2XHE08 = 3, 3160 RTW89_GILTF_1XHE16 = 4, 3161 RTW89_GILTF_1XHE08 = 5, 3162 RTW89_GILTF_MAX 3163 }; 3164 3165 enum rtw89_rx_frame_type { 3166 RTW89_RX_TYPE_MGNT = 0, 3167 RTW89_RX_TYPE_CTRL = 1, 3168 RTW89_RX_TYPE_DATA = 2, 3169 RTW89_RX_TYPE_RSVD = 3, 3170 }; 3171 3172 enum rtw89_efuse_block { 3173 RTW89_EFUSE_BLOCK_SYS = 0, 3174 RTW89_EFUSE_BLOCK_RF = 1, 3175 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3176 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3177 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3178 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3179 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3180 RTW89_EFUSE_BLOCK_ADIE = 7, 3181 3182 RTW89_EFUSE_BLOCK_NUM, 3183 RTW89_EFUSE_BLOCK_IGNORE, 3184 }; 3185 3186 struct rtw89_ra_info { 3187 u8 is_dis_ra:1; 3188 /* Bit0 : CCK 3189 * Bit1 : OFDM 3190 * Bit2 : HT 3191 * Bit3 : VHT 3192 * Bit4 : HE 3193 * Bit5 : EHT 3194 */ 3195 u8 mode_ctrl:6; 3196 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3197 u8 macid; 3198 u8 dcm_cap:1; 3199 u8 er_cap:1; 3200 u8 init_rate_lv:2; 3201 u8 upd_all:1; 3202 u8 en_sgi:1; 3203 u8 ldpc_cap:1; 3204 u8 stbc_cap:1; 3205 u8 ss_num:3; 3206 u8 giltf:3; 3207 u8 upd_bw_nss_mask:1; 3208 u8 upd_mask:1; 3209 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3210 /* BFee CSI */ 3211 u8 band_num; 3212 u8 ra_csi_rate_en:1; 3213 u8 fixed_csi_rate_en:1; 3214 u8 cr_tbl_sel:1; 3215 u8 fix_giltf_en:1; 3216 u8 fix_giltf:3; 3217 u8 rsvd2:1; 3218 u8 csi_mcs_ss_idx; 3219 u8 csi_mode:2; 3220 u8 csi_gi_ltf:3; 3221 u8 csi_bw:3; 3222 }; 3223 3224 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3225 #define RTW89_PPDU_MAC_INFO_SIZE 8 3226 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3227 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3228 3229 #define RTW89_MAX_RX_AGG_NUM 64 3230 #define RTW89_MAX_TX_AGG_NUM 128 3231 3232 struct rtw89_ampdu_params { 3233 u16 agg_num; 3234 bool amsdu; 3235 }; 3236 3237 struct rtw89_ra_report { 3238 struct rate_info txrate; 3239 u32 bit_rate; 3240 u16 hw_rate; 3241 bool might_fallback_legacy; 3242 }; 3243 3244 DECLARE_EWMA(rssi, 10, 16); 3245 DECLARE_EWMA(evm, 10, 16); 3246 DECLARE_EWMA(snr, 10, 16); 3247 3248 struct rtw89_ba_cam_entry { 3249 struct list_head list; 3250 u8 tid; 3251 }; 3252 3253 #define RTW89_MAX_ADDR_CAM_NUM 128 3254 #define RTW89_MAX_BSSID_CAM_NUM 20 3255 #define RTW89_MAX_SEC_CAM_NUM 128 3256 #define RTW89_MAX_BA_CAM_NUM 24 3257 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3258 3259 struct rtw89_addr_cam_entry { 3260 u8 addr_cam_idx; 3261 u8 offset; 3262 u8 len; 3263 u8 valid : 1; 3264 u8 addr_mask : 6; 3265 u8 wapi : 1; 3266 u8 mask_sel : 2; 3267 u8 bssid_cam_idx: 6; 3268 3269 u8 sec_ent_mode; 3270 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3271 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3272 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3273 }; 3274 3275 struct rtw89_bssid_cam_entry { 3276 u8 bssid[ETH_ALEN]; 3277 u8 phy_idx; 3278 u8 bssid_cam_idx; 3279 u8 offset; 3280 u8 len; 3281 u8 valid : 1; 3282 u8 num; 3283 }; 3284 3285 struct rtw89_sec_cam_entry { 3286 u8 sec_cam_idx; 3287 u8 offset; 3288 u8 len; 3289 u8 type : 4; 3290 u8 ext_key : 1; 3291 u8 spp_mode : 1; 3292 /* 256 bits */ 3293 u8 key[32]; 3294 }; 3295 3296 struct rtw89_sta { 3297 u8 mac_id; 3298 bool disassoc; 3299 bool er_cap; 3300 struct rtw89_dev *rtwdev; 3301 struct rtw89_vif *rtwvif; 3302 struct rtw89_ra_info ra; 3303 struct rtw89_ra_report ra_report; 3304 int max_agg_wait; 3305 u8 prev_rssi; 3306 struct ewma_rssi avg_rssi; 3307 struct ewma_rssi rssi[RF_PATH_MAX]; 3308 struct ewma_snr avg_snr; 3309 struct ewma_evm evm_min[RF_PATH_MAX]; 3310 struct ewma_evm evm_max[RF_PATH_MAX]; 3311 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 3312 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 3313 struct ieee80211_rx_status rx_status; 3314 u16 rx_hw_rate; 3315 __le32 htc_template; 3316 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3317 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3318 struct list_head ba_cam_list; 3319 struct sk_buff_head roc_queue; 3320 3321 bool use_cfg_mask; 3322 struct cfg80211_bitrate_mask mask; 3323 3324 bool cctl_tx_time; 3325 u32 ampdu_max_time:4; 3326 bool cctl_tx_retry_limit; 3327 u32 data_tx_cnt_lmt:6; 3328 }; 3329 3330 struct rtw89_efuse { 3331 bool valid; 3332 bool power_k_valid; 3333 u8 xtal_cap; 3334 u8 addr[ETH_ALEN]; 3335 u8 rfe_type; 3336 char country_code[2]; 3337 }; 3338 3339 struct rtw89_phy_rate_pattern { 3340 u64 ra_mask; 3341 u16 rate; 3342 u8 ra_mode; 3343 bool enable; 3344 }; 3345 3346 struct rtw89_tx_wait_info { 3347 struct rcu_head rcu_head; 3348 struct completion completion; 3349 bool tx_done; 3350 }; 3351 3352 struct rtw89_tx_skb_data { 3353 struct rtw89_tx_wait_info __rcu *wait; 3354 u8 hci_priv[]; 3355 }; 3356 3357 #define RTW89_ROC_IDLE_TIMEOUT 500 3358 #define RTW89_ROC_TX_TIMEOUT 30 3359 enum rtw89_roc_state { 3360 RTW89_ROC_IDLE, 3361 RTW89_ROC_NORMAL, 3362 RTW89_ROC_MGMT, 3363 }; 3364 3365 struct rtw89_roc { 3366 struct ieee80211_channel chan; 3367 struct delayed_work roc_work; 3368 enum ieee80211_roc_type type; 3369 enum rtw89_roc_state state; 3370 int duration; 3371 }; 3372 3373 #define RTW89_P2P_MAX_NOA_NUM 2 3374 3375 struct rtw89_p2p_ie_head { 3376 u8 eid; 3377 u8 ie_len; 3378 u8 oui[3]; 3379 u8 oui_type; 3380 } __packed; 3381 3382 struct rtw89_noa_attr_head { 3383 u8 attr_type; 3384 __le16 attr_len; 3385 u8 index; 3386 u8 oppps_ctwindow; 3387 } __packed; 3388 3389 struct rtw89_p2p_noa_ie { 3390 struct rtw89_p2p_ie_head p2p_head; 3391 struct rtw89_noa_attr_head noa_head; 3392 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3393 } __packed; 3394 3395 struct rtw89_p2p_noa_setter { 3396 struct rtw89_p2p_noa_ie ie; 3397 u8 noa_count; 3398 u8 noa_index; 3399 }; 3400 3401 struct rtw89_vif { 3402 struct list_head list; 3403 struct rtw89_dev *rtwdev; 3404 struct rtw89_roc roc; 3405 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3406 enum rtw89_sub_entity_idx sub_entity_idx; 3407 enum rtw89_reg_6ghz_power reg_6ghz_power; 3408 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3409 3410 u8 mac_id; 3411 u8 port; 3412 u8 mac_addr[ETH_ALEN]; 3413 u8 bssid[ETH_ALEN]; 3414 __be32 ip_addr; 3415 u8 phy_idx; 3416 u8 mac_idx; 3417 u8 net_type; 3418 u8 wifi_role; 3419 u8 self_role; 3420 u8 wmm; 3421 u8 bcn_hit_cond; 3422 u8 hit_rule; 3423 u8 last_noa_nr; 3424 u64 sync_bcn_tsf; 3425 bool offchan; 3426 bool trigger; 3427 bool lsig_txop; 3428 u8 tgt_ind; 3429 u8 frm_tgt_ind; 3430 bool wowlan_pattern; 3431 bool wowlan_uc; 3432 bool wowlan_magic; 3433 bool is_hesta; 3434 bool last_a_ctrl; 3435 bool dyn_tb_bedge_en; 3436 bool pre_pwr_diff_en; 3437 bool pwr_diff_en; 3438 u8 def_tri_idx; 3439 u32 tdls_peer; 3440 struct work_struct update_beacon_work; 3441 struct rtw89_addr_cam_entry addr_cam; 3442 struct rtw89_bssid_cam_entry bssid_cam; 3443 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3444 struct rtw89_traffic_stats stats; 3445 struct rtw89_phy_rate_pattern rate_pattern; 3446 struct cfg80211_scan_request *scan_req; 3447 struct ieee80211_scan_ies *scan_ies; 3448 struct list_head general_pkt_list; 3449 struct rtw89_p2p_noa_setter p2p_noa; 3450 }; 3451 3452 enum rtw89_lv1_rcvy_step { 3453 RTW89_LV1_RCVY_STEP_1, 3454 RTW89_LV1_RCVY_STEP_2, 3455 }; 3456 3457 struct rtw89_hci_ops { 3458 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3459 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3460 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3461 void (*reset)(struct rtw89_dev *rtwdev); 3462 int (*start)(struct rtw89_dev *rtwdev); 3463 void (*stop)(struct rtw89_dev *rtwdev); 3464 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3465 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3466 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3467 3468 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3469 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3470 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3471 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3472 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3473 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3474 3475 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3476 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3477 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3478 int (*deinit)(struct rtw89_dev *rtwdev); 3479 3480 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3481 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3482 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3483 int (*napi_poll)(struct napi_struct *napi, int budget); 3484 3485 /* Deal with locks inside recovery_start and recovery_complete callbacks 3486 * by hci instance, and handle things which need to consider under SER. 3487 * e.g. turn on/off interrupts except for the one for halt notification. 3488 */ 3489 void (*recovery_start)(struct rtw89_dev *rtwdev); 3490 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3491 3492 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3493 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3494 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3495 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3496 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3497 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3498 void (*disable_intr)(struct rtw89_dev *rtwdev); 3499 void (*enable_intr)(struct rtw89_dev *rtwdev); 3500 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3501 }; 3502 3503 struct rtw89_hci_info { 3504 const struct rtw89_hci_ops *ops; 3505 enum rtw89_hci_type type; 3506 u32 rpwm_addr; 3507 u32 cpwm_addr; 3508 bool paused; 3509 }; 3510 3511 struct rtw89_chip_ops { 3512 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3513 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3514 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3515 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3516 void (*bb_reset)(struct rtw89_dev *rtwdev, 3517 enum rtw89_phy_idx phy_idx); 3518 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3519 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3520 u32 addr, u32 mask); 3521 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3522 u32 addr, u32 mask, u32 data); 3523 void (*set_channel)(struct rtw89_dev *rtwdev, 3524 const struct rtw89_chan *chan, 3525 enum rtw89_mac_idx mac_idx, 3526 enum rtw89_phy_idx phy_idx); 3527 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3528 struct rtw89_channel_help_params *p, 3529 const struct rtw89_chan *chan, 3530 enum rtw89_mac_idx mac_idx, 3531 enum rtw89_phy_idx phy_idx); 3532 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3533 enum rtw89_efuse_block block); 3534 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3535 void (*fem_setup)(struct rtw89_dev *rtwdev); 3536 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3537 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3538 void (*rfk_init)(struct rtw89_dev *rtwdev); 3539 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3540 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3541 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3542 enum rtw89_phy_idx phy_idx); 3543 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3544 void (*rfk_track)(struct rtw89_dev *rtwdev); 3545 void (*power_trim)(struct rtw89_dev *rtwdev); 3546 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3547 const struct rtw89_chan *chan, 3548 enum rtw89_phy_idx phy_idx); 3549 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3550 enum rtw89_phy_idx phy_idx); 3551 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3552 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3553 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3554 enum rtw89_phy_idx phy_idx); 3555 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3556 struct rtw89_rx_phy_ppdu *phy_ppdu, 3557 struct ieee80211_rx_status *status); 3558 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3559 enum rtw89_phy_idx phy_idx); 3560 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3561 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3562 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3563 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3564 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3565 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3566 struct rtw89_rx_desc_info *desc_info, 3567 u8 *data, u32 data_offset); 3568 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3569 struct rtw89_tx_desc_info *desc_info, 3570 void *txdesc); 3571 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3572 struct rtw89_tx_desc_info *desc_info, 3573 void *txdesc); 3574 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3575 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3576 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3577 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3578 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3579 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3580 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3581 struct rtw89_vif *rtwvif, 3582 struct rtw89_sta *rtwsta); 3583 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3584 struct rtw89_vif *rtwvif, 3585 struct rtw89_sta *rtwsta); 3586 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3587 struct ieee80211_vif *vif, 3588 struct ieee80211_sta *sta); 3589 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3590 struct ieee80211_vif *vif, 3591 struct ieee80211_sta *sta); 3592 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3593 struct rtw89_vif *rtwvif, 3594 struct rtw89_sta *rtwsta); 3595 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3596 struct rtw89_vif *rtwvif); 3597 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3598 bool valid, struct ieee80211_ampdu_params *params); 3599 3600 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3601 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3602 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3603 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3604 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3605 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3606 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3607 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3608 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3609 }; 3610 3611 enum rtw89_dma_ch { 3612 RTW89_DMA_ACH0 = 0, 3613 RTW89_DMA_ACH1 = 1, 3614 RTW89_DMA_ACH2 = 2, 3615 RTW89_DMA_ACH3 = 3, 3616 RTW89_DMA_ACH4 = 4, 3617 RTW89_DMA_ACH5 = 5, 3618 RTW89_DMA_ACH6 = 6, 3619 RTW89_DMA_ACH7 = 7, 3620 RTW89_DMA_B0MG = 8, 3621 RTW89_DMA_B0HI = 9, 3622 RTW89_DMA_B1MG = 10, 3623 RTW89_DMA_B1HI = 11, 3624 RTW89_DMA_H2C = 12, 3625 RTW89_DMA_CH_NUM = 13 3626 }; 3627 3628 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3629 3630 enum rtw89_mlo_dbcc_mode { 3631 MLO_DBCC_NOT_SUPPORT = 1, 3632 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3633 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3634 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3635 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3636 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3637 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3638 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3639 DBCC_LEGACY = 0xffffffff, 3640 }; 3641 3642 enum rtw89_scan_be_operation { 3643 RTW89_SCAN_OP_STOP, 3644 RTW89_SCAN_OP_START, 3645 RTW89_SCAN_OP_SETPARM, 3646 RTW89_SCAN_OP_GETRPT, 3647 RTW89_SCAN_OP_NUM 3648 }; 3649 3650 enum rtw89_scan_be_mode { 3651 RTW89_SCAN_MODE_SA, 3652 RTW89_SCAN_MODE_MACC, 3653 RTW89_SCAN_MODE_NUM 3654 }; 3655 3656 enum rtw89_scan_be_opmode { 3657 RTW89_SCAN_OPMODE_NONE, 3658 RTW89_SCAN_OPMODE_TBTT, 3659 RTW89_SCAN_OPMODE_INTV, 3660 RTW89_SCAN_OPMODE_CNT, 3661 RTW89_SCAN_OPMODE_NUM, 3662 }; 3663 3664 struct rtw89_scan_option { 3665 bool enable; 3666 bool target_ch_mode; 3667 u8 num_macc_role; 3668 u8 num_opch; 3669 u8 repeat; 3670 u16 norm_pd; 3671 u16 slow_pd; 3672 u16 norm_cy; 3673 u8 opch_end; 3674 u64 prohib_chan; 3675 enum rtw89_phy_idx band; 3676 enum rtw89_scan_be_operation operation; 3677 enum rtw89_scan_be_mode scan_mode; 3678 enum rtw89_mlo_dbcc_mode mlo_mode; 3679 }; 3680 3681 enum rtw89_qta_mode { 3682 RTW89_QTA_SCC, 3683 RTW89_QTA_DBCC, 3684 RTW89_QTA_DLFW, 3685 RTW89_QTA_WOW, 3686 3687 /* keep last */ 3688 RTW89_QTA_INVALID, 3689 }; 3690 3691 struct rtw89_hfc_ch_cfg { 3692 u16 min; 3693 u16 max; 3694 #define grp_0 0 3695 #define grp_1 1 3696 #define grp_num 2 3697 u8 grp; 3698 }; 3699 3700 struct rtw89_hfc_ch_info { 3701 u16 aval; 3702 u16 used; 3703 }; 3704 3705 struct rtw89_hfc_pub_cfg { 3706 u16 grp0; 3707 u16 grp1; 3708 u16 pub_max; 3709 u16 wp_thrd; 3710 }; 3711 3712 struct rtw89_hfc_pub_info { 3713 u16 g0_used; 3714 u16 g1_used; 3715 u16 g0_aval; 3716 u16 g1_aval; 3717 u16 pub_aval; 3718 u16 wp_aval; 3719 }; 3720 3721 struct rtw89_hfc_prec_cfg { 3722 u16 ch011_prec; 3723 u16 h2c_prec; 3724 u16 wp_ch07_prec; 3725 u16 wp_ch811_prec; 3726 u8 ch011_full_cond; 3727 u8 h2c_full_cond; 3728 u8 wp_ch07_full_cond; 3729 u8 wp_ch811_full_cond; 3730 }; 3731 3732 struct rtw89_hfc_param { 3733 bool en; 3734 bool h2c_en; 3735 u8 mode; 3736 const struct rtw89_hfc_ch_cfg *ch_cfg; 3737 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3738 struct rtw89_hfc_pub_cfg pub_cfg; 3739 struct rtw89_hfc_pub_info pub_info; 3740 struct rtw89_hfc_prec_cfg prec_cfg; 3741 }; 3742 3743 struct rtw89_hfc_param_ini { 3744 const struct rtw89_hfc_ch_cfg *ch_cfg; 3745 const struct rtw89_hfc_pub_cfg *pub_cfg; 3746 const struct rtw89_hfc_prec_cfg *prec_cfg; 3747 u8 mode; 3748 }; 3749 3750 struct rtw89_dle_size { 3751 u16 pge_size; 3752 u16 lnk_pge_num; 3753 u16 unlnk_pge_num; 3754 /* for WiFi 7 chips below */ 3755 u32 srt_ofst; 3756 }; 3757 3758 struct rtw89_wde_quota { 3759 u16 hif; 3760 u16 wcpu; 3761 u16 pkt_in; 3762 u16 cpu_io; 3763 }; 3764 3765 struct rtw89_ple_quota { 3766 u16 cma0_tx; 3767 u16 cma1_tx; 3768 u16 c2h; 3769 u16 h2c; 3770 u16 wcpu; 3771 u16 mpdu_proc; 3772 u16 cma0_dma; 3773 u16 cma1_dma; 3774 u16 bb_rpt; 3775 u16 wd_rel; 3776 u16 cpu_io; 3777 u16 tx_rpt; 3778 /* for WiFi 7 chips below */ 3779 u16 h2d; 3780 }; 3781 3782 struct rtw89_rsvd_quota { 3783 u16 mpdu_info_tbl; 3784 u16 b0_csi; 3785 u16 b1_csi; 3786 u16 b0_lmr; 3787 u16 b1_lmr; 3788 u16 b0_ftm; 3789 u16 b1_ftm; 3790 u16 b0_smr; 3791 u16 b1_smr; 3792 u16 others; 3793 }; 3794 3795 struct rtw89_dle_rsvd_size { 3796 u32 srt_ofst; 3797 u32 size; 3798 }; 3799 3800 struct rtw89_dle_mem { 3801 enum rtw89_qta_mode mode; 3802 const struct rtw89_dle_size *wde_size; 3803 const struct rtw89_dle_size *ple_size; 3804 const struct rtw89_wde_quota *wde_min_qt; 3805 const struct rtw89_wde_quota *wde_max_qt; 3806 const struct rtw89_ple_quota *ple_min_qt; 3807 const struct rtw89_ple_quota *ple_max_qt; 3808 /* for WiFi 7 chips below */ 3809 const struct rtw89_rsvd_quota *rsvd_qt; 3810 const struct rtw89_dle_rsvd_size *rsvd0_size; 3811 const struct rtw89_dle_rsvd_size *rsvd1_size; 3812 }; 3813 3814 struct rtw89_reg_def { 3815 u32 addr; 3816 u32 mask; 3817 }; 3818 3819 struct rtw89_reg2_def { 3820 u32 addr; 3821 u32 data; 3822 }; 3823 3824 struct rtw89_reg3_def { 3825 u32 addr; 3826 u32 mask; 3827 u32 data; 3828 }; 3829 3830 struct rtw89_reg5_def { 3831 u8 flag; /* recognized by parsers */ 3832 u8 path; 3833 u32 addr; 3834 u32 mask; 3835 u32 data; 3836 }; 3837 3838 struct rtw89_reg_imr { 3839 u32 addr; 3840 u32 clr; 3841 u32 set; 3842 }; 3843 3844 struct rtw89_phy_table { 3845 const struct rtw89_reg2_def *regs; 3846 u32 n_regs; 3847 enum rtw89_rf_path rf_path; 3848 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3849 enum rtw89_rf_path rf_path, void *data); 3850 }; 3851 3852 struct rtw89_txpwr_table { 3853 const void *data; 3854 u32 size; 3855 void (*load)(struct rtw89_dev *rtwdev, 3856 const struct rtw89_txpwr_table *tbl); 3857 }; 3858 3859 struct rtw89_txpwr_rule_2ghz { 3860 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3861 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3862 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3863 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3864 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3865 }; 3866 3867 struct rtw89_txpwr_rule_5ghz { 3868 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3869 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3870 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3871 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3872 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3873 }; 3874 3875 struct rtw89_txpwr_rule_6ghz { 3876 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3877 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3878 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3879 [RTW89_6G_CH_NUM]; 3880 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3881 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3882 [RTW89_6G_CH_NUM]; 3883 }; 3884 3885 struct rtw89_tx_shape { 3886 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3887 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3888 }; 3889 3890 struct rtw89_rfe_parms { 3891 const struct rtw89_txpwr_table *byr_tbl; 3892 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3893 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3894 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3895 struct rtw89_tx_shape tx_shape; 3896 }; 3897 3898 struct rtw89_rfe_parms_conf { 3899 const struct rtw89_rfe_parms *rfe_parms; 3900 u8 rfe_type; 3901 }; 3902 3903 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3904 3905 struct rtw89_txpwr_conf { 3906 u8 rfe_type; 3907 u8 ent_sz; 3908 u32 num_ents; 3909 const void *data; 3910 }; 3911 3912 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3913 3914 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3915 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3916 memcpy(&(entry), cursor, \ 3917 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3918 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3919 (cursor) += (conf)->ent_sz, \ 3920 memcpy(&(entry), cursor, \ 3921 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3922 3923 struct rtw89_txpwr_byrate_data { 3924 struct rtw89_txpwr_conf conf; 3925 struct rtw89_txpwr_table tbl; 3926 }; 3927 3928 struct rtw89_txpwr_lmt_2ghz_data { 3929 struct rtw89_txpwr_conf conf; 3930 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3931 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3932 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3933 }; 3934 3935 struct rtw89_txpwr_lmt_5ghz_data { 3936 struct rtw89_txpwr_conf conf; 3937 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3938 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3939 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3940 }; 3941 3942 struct rtw89_txpwr_lmt_6ghz_data { 3943 struct rtw89_txpwr_conf conf; 3944 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3945 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3946 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3947 [RTW89_6G_CH_NUM]; 3948 }; 3949 3950 struct rtw89_txpwr_lmt_ru_2ghz_data { 3951 struct rtw89_txpwr_conf conf; 3952 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3953 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3954 }; 3955 3956 struct rtw89_txpwr_lmt_ru_5ghz_data { 3957 struct rtw89_txpwr_conf conf; 3958 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3959 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3960 }; 3961 3962 struct rtw89_txpwr_lmt_ru_6ghz_data { 3963 struct rtw89_txpwr_conf conf; 3964 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3965 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3966 [RTW89_6G_CH_NUM]; 3967 }; 3968 3969 struct rtw89_tx_shape_lmt_data { 3970 struct rtw89_txpwr_conf conf; 3971 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3972 }; 3973 3974 struct rtw89_tx_shape_lmt_ru_data { 3975 struct rtw89_txpwr_conf conf; 3976 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3977 }; 3978 3979 struct rtw89_rfe_data { 3980 struct rtw89_txpwr_byrate_data byrate; 3981 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3982 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3983 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3984 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3985 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3986 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3987 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3988 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3989 struct rtw89_rfe_parms rfe_parms; 3990 }; 3991 3992 struct rtw89_page_regs { 3993 u32 hci_fc_ctrl; 3994 u32 ch_page_ctrl; 3995 u32 ach_page_ctrl; 3996 u32 ach_page_info; 3997 u32 pub_page_info3; 3998 u32 pub_page_ctrl1; 3999 u32 pub_page_ctrl2; 4000 u32 pub_page_info1; 4001 u32 pub_page_info2; 4002 u32 wp_page_ctrl1; 4003 u32 wp_page_ctrl2; 4004 u32 wp_page_info1; 4005 }; 4006 4007 struct rtw89_imr_info { 4008 u32 wdrls_imr_set; 4009 u32 wsec_imr_reg; 4010 u32 wsec_imr_set; 4011 u32 mpdu_tx_imr_set; 4012 u32 mpdu_rx_imr_set; 4013 u32 sta_sch_imr_set; 4014 u32 txpktctl_imr_b0_reg; 4015 u32 txpktctl_imr_b0_clr; 4016 u32 txpktctl_imr_b0_set; 4017 u32 txpktctl_imr_b1_reg; 4018 u32 txpktctl_imr_b1_clr; 4019 u32 txpktctl_imr_b1_set; 4020 u32 wde_imr_clr; 4021 u32 wde_imr_set; 4022 u32 ple_imr_clr; 4023 u32 ple_imr_set; 4024 u32 host_disp_imr_clr; 4025 u32 host_disp_imr_set; 4026 u32 cpu_disp_imr_clr; 4027 u32 cpu_disp_imr_set; 4028 u32 other_disp_imr_clr; 4029 u32 other_disp_imr_set; 4030 u32 bbrpt_com_err_imr_reg; 4031 u32 bbrpt_chinfo_err_imr_reg; 4032 u32 bbrpt_err_imr_set; 4033 u32 bbrpt_dfs_err_imr_reg; 4034 u32 ptcl_imr_clr; 4035 u32 ptcl_imr_set; 4036 u32 cdma_imr_0_reg; 4037 u32 cdma_imr_0_clr; 4038 u32 cdma_imr_0_set; 4039 u32 cdma_imr_1_reg; 4040 u32 cdma_imr_1_clr; 4041 u32 cdma_imr_1_set; 4042 u32 phy_intf_imr_reg; 4043 u32 phy_intf_imr_clr; 4044 u32 phy_intf_imr_set; 4045 u32 rmac_imr_reg; 4046 u32 rmac_imr_clr; 4047 u32 rmac_imr_set; 4048 u32 tmac_imr_reg; 4049 u32 tmac_imr_clr; 4050 u32 tmac_imr_set; 4051 }; 4052 4053 struct rtw89_imr_table { 4054 const struct rtw89_reg_imr *regs; 4055 u32 n_regs; 4056 }; 4057 4058 struct rtw89_xtal_info { 4059 u32 xcap_reg; 4060 u32 sc_xo_mask; 4061 u32 sc_xi_mask; 4062 }; 4063 4064 struct rtw89_rrsr_cfgs { 4065 struct rtw89_reg3_def ref_rate; 4066 struct rtw89_reg3_def rsc; 4067 }; 4068 4069 struct rtw89_dig_regs { 4070 u32 seg0_pd_reg; 4071 u32 pd_lower_bound_mask; 4072 u32 pd_spatial_reuse_en; 4073 u32 bmode_pd_reg; 4074 u32 bmode_cca_rssi_limit_en; 4075 u32 bmode_pd_lower_bound_reg; 4076 u32 bmode_rssi_nocca_low_th_mask; 4077 struct rtw89_reg_def p0_lna_init; 4078 struct rtw89_reg_def p1_lna_init; 4079 struct rtw89_reg_def p0_tia_init; 4080 struct rtw89_reg_def p1_tia_init; 4081 struct rtw89_reg_def p0_rxb_init; 4082 struct rtw89_reg_def p1_rxb_init; 4083 struct rtw89_reg_def p0_p20_pagcugc_en; 4084 struct rtw89_reg_def p0_s20_pagcugc_en; 4085 struct rtw89_reg_def p1_p20_pagcugc_en; 4086 struct rtw89_reg_def p1_s20_pagcugc_en; 4087 }; 4088 4089 struct rtw89_edcca_regs { 4090 u32 edcca_level; 4091 u32 edcca_mask; 4092 u32 edcca_p_mask; 4093 u32 ppdu_level; 4094 u32 ppdu_mask; 4095 u32 rpt_a; 4096 u32 rpt_b; 4097 u32 rpt_sel; 4098 u32 rpt_sel_mask; 4099 u32 rpt_sel_be; 4100 u32 rpt_sel_be_mask; 4101 u32 tx_collision_t2r_st; 4102 u32 tx_collision_t2r_st_mask; 4103 }; 4104 4105 struct rtw89_phy_ul_tb_info { 4106 bool dyn_tb_tri_en; 4107 u8 def_if_bandedge; 4108 }; 4109 4110 struct rtw89_antdiv_stats { 4111 struct ewma_rssi cck_rssi_avg; 4112 struct ewma_rssi ofdm_rssi_avg; 4113 struct ewma_rssi non_legacy_rssi_avg; 4114 u16 pkt_cnt_cck; 4115 u16 pkt_cnt_ofdm; 4116 u16 pkt_cnt_non_legacy; 4117 u32 evm; 4118 }; 4119 4120 struct rtw89_antdiv_info { 4121 struct rtw89_antdiv_stats target_stats; 4122 struct rtw89_antdiv_stats main_stats; 4123 struct rtw89_antdiv_stats aux_stats; 4124 u8 training_count; 4125 u8 rssi_pre; 4126 bool get_stats; 4127 }; 4128 4129 enum rtw89_chanctx_state { 4130 RTW89_CHANCTX_STATE_MCC_START, 4131 RTW89_CHANCTX_STATE_MCC_STOP, 4132 }; 4133 4134 enum rtw89_chanctx_callbacks { 4135 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4136 RTW89_CHANCTX_CALLBACK_RFK, 4137 4138 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4139 }; 4140 4141 struct rtw89_chanctx_listener { 4142 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4143 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4144 }; 4145 4146 struct rtw89_chip_info { 4147 enum rtw89_core_chip_id chip_id; 4148 enum rtw89_chip_gen chip_gen; 4149 const struct rtw89_chip_ops *ops; 4150 const struct rtw89_mac_gen_def *mac_def; 4151 const struct rtw89_phy_gen_def *phy_def; 4152 const char *fw_basename; 4153 u8 fw_format_max; 4154 bool try_ce_fw; 4155 u8 bbmcu_nr; 4156 u32 needed_fw_elms; 4157 u32 fifo_size; 4158 bool small_fifo_size; 4159 u32 dle_scc_rsvd_size; 4160 u16 max_amsdu_limit; 4161 bool dis_2g_40m_ul_ofdma; 4162 u32 rsvd_ple_ofst; 4163 const struct rtw89_hfc_param_ini *hfc_param_ini; 4164 const struct rtw89_dle_mem *dle_mem; 4165 u8 wde_qempty_acq_grpnum; 4166 u8 wde_qempty_mgq_grpsel; 4167 u32 rf_base_addr[2]; 4168 u8 support_macid_num; 4169 u8 support_chanctx_num; 4170 u8 support_bands; 4171 u16 support_bandwidths; 4172 bool support_unii4; 4173 bool support_rnr; 4174 bool ul_tb_waveform_ctrl; 4175 bool ul_tb_pwr_diff; 4176 bool hw_sec_hdr; 4177 u8 rf_path_num; 4178 u8 tx_nss; 4179 u8 rx_nss; 4180 u8 acam_num; 4181 u8 bcam_num; 4182 u8 scam_num; 4183 u8 bacam_num; 4184 u8 bacam_dynamic_num; 4185 enum rtw89_bacam_ver bacam_ver; 4186 u8 ppdu_max_usr; 4187 4188 u8 sec_ctrl_efuse_size; 4189 u32 physical_efuse_size; 4190 u32 logical_efuse_size; 4191 u32 limit_efuse_size; 4192 u32 dav_phy_efuse_size; 4193 u32 dav_log_efuse_size; 4194 u32 phycap_addr; 4195 u32 phycap_size; 4196 const struct rtw89_efuse_block_cfg *efuse_blocks; 4197 4198 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4199 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4200 const struct rtw89_phy_table *bb_table; 4201 const struct rtw89_phy_table *bb_gain_table; 4202 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4203 const struct rtw89_phy_table *nctl_table; 4204 const struct rtw89_rfk_tbl *nctl_post_table; 4205 const struct rtw89_phy_dig_gain_table *dig_table; 4206 const struct rtw89_dig_regs *dig_regs; 4207 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4208 4209 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4210 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4211 const struct rtw89_rfe_parms *dflt_parms; 4212 const struct rtw89_chanctx_listener *chanctx_listener; 4213 4214 u8 txpwr_factor_rf; 4215 u8 txpwr_factor_mac; 4216 4217 u32 para_ver; 4218 u32 wlcx_desired; 4219 u8 btcx_desired; 4220 u8 scbd; 4221 u8 mailbox; 4222 4223 u8 afh_guard_ch; 4224 const u8 *wl_rssi_thres; 4225 const u8 *bt_rssi_thres; 4226 u8 rssi_tol; 4227 4228 u8 mon_reg_num; 4229 const struct rtw89_btc_fbtc_mreg *mon_reg; 4230 u8 rf_para_ulink_num; 4231 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4232 u8 rf_para_dlink_num; 4233 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4234 u8 ps_mode_supported; 4235 u8 low_power_hci_modes; 4236 4237 u32 h2c_cctl_func_id; 4238 u32 hci_func_en_addr; 4239 u32 h2c_desc_size; 4240 u32 txwd_body_size; 4241 u32 txwd_info_size; 4242 u32 h2c_ctrl_reg; 4243 const u32 *h2c_regs; 4244 struct rtw89_reg_def h2c_counter_reg; 4245 u32 c2h_ctrl_reg; 4246 const u32 *c2h_regs; 4247 struct rtw89_reg_def c2h_counter_reg; 4248 const struct rtw89_page_regs *page_regs; 4249 const u32 *wow_reason_reg; 4250 bool cfo_src_fd; 4251 bool cfo_hw_comp; 4252 const struct rtw89_reg_def *dcfo_comp; 4253 u8 dcfo_comp_sft; 4254 const struct rtw89_imr_info *imr_info; 4255 const struct rtw89_imr_table *imr_dmac_table; 4256 const struct rtw89_imr_table *imr_cmac_table; 4257 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4258 struct rtw89_reg_def bss_clr_vld; 4259 u32 bss_clr_map_reg; 4260 u32 dma_ch_mask; 4261 const struct rtw89_edcca_regs *edcca_regs; 4262 const struct wiphy_wowlan_support *wowlan_stub; 4263 const struct rtw89_xtal_info *xtal_info; 4264 }; 4265 4266 union rtw89_bus_info { 4267 const struct rtw89_pci_info *pci; 4268 }; 4269 4270 struct rtw89_driver_info { 4271 const struct rtw89_chip_info *chip; 4272 const struct dmi_system_id *quirks; 4273 union rtw89_bus_info bus; 4274 }; 4275 4276 enum rtw89_hcifc_mode { 4277 RTW89_HCIFC_POH = 0, 4278 RTW89_HCIFC_STF = 1, 4279 RTW89_HCIFC_SDIO = 2, 4280 4281 /* keep last */ 4282 RTW89_HCIFC_MODE_INVALID, 4283 }; 4284 4285 struct rtw89_dle_info { 4286 const struct rtw89_rsvd_quota *rsvd_qt; 4287 enum rtw89_qta_mode qta_mode; 4288 u16 ple_pg_size; 4289 u16 ple_free_pg; 4290 u16 c0_rx_qta; 4291 u16 c1_rx_qta; 4292 }; 4293 4294 enum rtw89_host_rpr_mode { 4295 RTW89_RPR_MODE_POH = 0, 4296 RTW89_RPR_MODE_STF 4297 }; 4298 4299 #define RTW89_COMPLETION_BUF_SIZE 40 4300 #define RTW89_WAIT_COND_IDLE UINT_MAX 4301 4302 struct rtw89_completion_data { 4303 bool err; 4304 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4305 }; 4306 4307 struct rtw89_wait_info { 4308 atomic_t cond; 4309 struct completion completion; 4310 struct rtw89_completion_data data; 4311 }; 4312 4313 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4314 4315 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4316 { 4317 init_completion(&wait->completion); 4318 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4319 } 4320 4321 struct rtw89_mac_info { 4322 struct rtw89_dle_info dle_info; 4323 struct rtw89_hfc_param hfc_param; 4324 enum rtw89_qta_mode qta_mode; 4325 u8 rpwm_seq_num; 4326 u8 cpwm_seq_num; 4327 4328 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4329 struct rtw89_wait_info fw_ofld_wait; 4330 }; 4331 4332 enum rtw89_fwdl_check_type { 4333 RTW89_FWDL_CHECK_FREERTOS_DONE, 4334 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4335 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4336 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4337 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4338 }; 4339 4340 enum rtw89_fw_type { 4341 RTW89_FW_NORMAL = 1, 4342 RTW89_FW_WOWLAN = 3, 4343 RTW89_FW_NORMAL_CE = 5, 4344 RTW89_FW_BBMCU0 = 64, 4345 RTW89_FW_BBMCU1 = 65, 4346 RTW89_FW_LOGFMT = 255, 4347 }; 4348 4349 enum rtw89_fw_feature { 4350 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4351 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4352 RTW89_FW_FEATURE_TX_WAKE, 4353 RTW89_FW_FEATURE_CRASH_TRIGGER, 4354 RTW89_FW_FEATURE_NO_PACKET_DROP, 4355 RTW89_FW_FEATURE_NO_DEEP_PS, 4356 RTW89_FW_FEATURE_NO_LPS_PG, 4357 RTW89_FW_FEATURE_BEACON_FILTER, 4358 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4359 RTW89_FW_FEATURE_WOW_REASON_V1, 4360 }; 4361 4362 struct rtw89_fw_suit { 4363 enum rtw89_fw_type type; 4364 const u8 *data; 4365 u32 size; 4366 u8 major_ver; 4367 u8 minor_ver; 4368 u8 sub_ver; 4369 u8 sub_idex; 4370 u16 build_year; 4371 u16 build_mon; 4372 u16 build_date; 4373 u16 build_hour; 4374 u16 build_min; 4375 u8 cmd_ver; 4376 u8 hdr_ver; 4377 u32 commitid; 4378 }; 4379 4380 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4381 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4382 #define RTW89_FW_SUIT_VER_CODE(s) \ 4383 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4384 4385 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4386 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4387 (mfw_hdr)->ver.minor, \ 4388 (mfw_hdr)->ver.sub, \ 4389 (mfw_hdr)->ver.idx) 4390 4391 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4392 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4393 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4394 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4395 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4396 4397 struct rtw89_fw_req_info { 4398 const struct firmware *firmware; 4399 struct completion completion; 4400 }; 4401 4402 struct rtw89_fw_log { 4403 struct rtw89_fw_suit suit; 4404 bool enable; 4405 u32 last_fmt_id; 4406 u32 fmt_count; 4407 const __le32 *fmt_ids; 4408 const char *(*fmts)[]; 4409 }; 4410 4411 struct rtw89_fw_elm_info { 4412 struct rtw89_phy_table *bb_tbl; 4413 struct rtw89_phy_table *bb_gain; 4414 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4415 struct rtw89_phy_table *rf_nctl; 4416 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4417 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4418 }; 4419 4420 enum rtw89_fw_mss_dev_type { 4421 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4422 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4423 }; 4424 4425 struct rtw89_fw_secure { 4426 bool secure_boot; 4427 u32 sb_sel_mgn; 4428 u8 mss_dev_type; 4429 u8 mss_cust_idx; 4430 u8 mss_key_num; 4431 }; 4432 4433 struct rtw89_fw_info { 4434 struct rtw89_fw_req_info req; 4435 int fw_format; 4436 u8 h2c_seq; 4437 u8 rec_seq; 4438 u8 h2c_counter; 4439 u8 c2h_counter; 4440 struct rtw89_fw_suit normal; 4441 struct rtw89_fw_suit wowlan; 4442 struct rtw89_fw_suit bbmcu0; 4443 struct rtw89_fw_suit bbmcu1; 4444 struct rtw89_fw_log log; 4445 u32 feature_map; 4446 struct rtw89_fw_elm_info elm_info; 4447 struct rtw89_fw_secure sec; 4448 }; 4449 4450 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4451 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4452 4453 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4454 ((_fw)->feature_map |= BIT(_fw_feature)) 4455 4456 struct rtw89_cam_info { 4457 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4458 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4459 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4460 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4461 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4462 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4463 }; 4464 4465 enum rtw89_sar_sources { 4466 RTW89_SAR_SOURCE_NONE, 4467 RTW89_SAR_SOURCE_COMMON, 4468 4469 RTW89_SAR_SOURCE_NR, 4470 }; 4471 4472 enum rtw89_sar_subband { 4473 RTW89_SAR_2GHZ_SUBBAND, 4474 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4475 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4476 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4477 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4478 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4479 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4480 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4481 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4482 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4483 4484 RTW89_SAR_SUBBAND_NR, 4485 }; 4486 4487 struct rtw89_sar_cfg_common { 4488 bool set[RTW89_SAR_SUBBAND_NR]; 4489 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4490 }; 4491 4492 struct rtw89_sar_info { 4493 /* used to decide how to acces SAR cfg union */ 4494 enum rtw89_sar_sources src; 4495 4496 /* reserved for different knids of SAR cfg struct. 4497 * supposed that a single cfg struct cannot handle various SAR sources. 4498 */ 4499 union { 4500 struct rtw89_sar_cfg_common cfg_common; 4501 }; 4502 }; 4503 4504 enum rtw89_tas_state { 4505 RTW89_TAS_STATE_DPR_OFF, 4506 RTW89_TAS_STATE_DPR_ON, 4507 RTW89_TAS_STATE_DPR_FORBID, 4508 }; 4509 4510 #define RTW89_TAS_MAX_WINDOW 50 4511 struct rtw89_tas_info { 4512 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4513 s32 total_txpwr; 4514 u8 cur_idx; 4515 s8 dpr_gap; 4516 s8 delta; 4517 enum rtw89_tas_state state; 4518 bool enable; 4519 }; 4520 4521 struct rtw89_chanctx_cfg { 4522 enum rtw89_sub_entity_idx idx; 4523 int ref_count; 4524 }; 4525 4526 enum rtw89_chanctx_changes { 4527 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4528 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4529 RTW89_CHANCTX_P2P_PS_CHANGE, 4530 RTW89_CHANCTX_BT_SLOT_CHANGE, 4531 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4532 4533 NUM_OF_RTW89_CHANCTX_CHANGES, 4534 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4535 }; 4536 4537 enum rtw89_entity_mode { 4538 RTW89_ENTITY_MODE_SCC, 4539 RTW89_ENTITY_MODE_MCC_PREPARE, 4540 RTW89_ENTITY_MODE_MCC, 4541 4542 NUM_OF_RTW89_ENTITY_MODE, 4543 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4544 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4545 }; 4546 4547 struct rtw89_sub_entity { 4548 struct cfg80211_chan_def chandef; 4549 struct rtw89_chan chan; 4550 struct rtw89_chan_rcd rcd; 4551 4552 /* only assigned when running with chanctx_ops */ 4553 struct rtw89_chanctx_cfg *cfg; 4554 }; 4555 4556 struct rtw89_edcca_bak { 4557 u8 a; 4558 u8 p; 4559 u8 ppdu; 4560 u8 th_old; 4561 }; 4562 4563 enum rtw89_dm_type { 4564 RTW89_DM_DYNAMIC_EDCCA, 4565 }; 4566 4567 struct rtw89_hal { 4568 u32 rx_fltr; 4569 u8 cv; 4570 u8 acv; 4571 u32 antenna_tx; 4572 u32 antenna_rx; 4573 u8 tx_nss; 4574 u8 rx_nss; 4575 bool tx_path_diversity; 4576 bool ant_diversity; 4577 bool ant_diversity_fixed; 4578 bool support_cckpd; 4579 bool support_igi; 4580 atomic_t roc_entity_idx; 4581 4582 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4583 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4584 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4585 struct cfg80211_chan_def roc_chandef; 4586 4587 bool entity_active; 4588 bool entity_pause; 4589 enum rtw89_entity_mode entity_mode; 4590 4591 struct rtw89_edcca_bak edcca_bak; 4592 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4593 }; 4594 4595 #define RTW89_MAX_MAC_ID_NUM 128 4596 #define RTW89_MAX_PKT_OFLD_NUM 255 4597 4598 enum rtw89_flags { 4599 RTW89_FLAG_POWERON, 4600 RTW89_FLAG_DMAC_FUNC, 4601 RTW89_FLAG_CMAC0_FUNC, 4602 RTW89_FLAG_CMAC1_FUNC, 4603 RTW89_FLAG_FW_RDY, 4604 RTW89_FLAG_RUNNING, 4605 RTW89_FLAG_PROBE_DONE, 4606 RTW89_FLAG_BFEE_MON, 4607 RTW89_FLAG_BFEE_EN, 4608 RTW89_FLAG_BFEE_TIMER_KEEP, 4609 RTW89_FLAG_NAPI_RUNNING, 4610 RTW89_FLAG_LEISURE_PS, 4611 RTW89_FLAG_LOW_POWER_MODE, 4612 RTW89_FLAG_INACTIVE_PS, 4613 RTW89_FLAG_CRASH_SIMULATING, 4614 RTW89_FLAG_SER_HANDLING, 4615 RTW89_FLAG_WOWLAN, 4616 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4617 RTW89_FLAG_CHANGING_INTERFACE, 4618 4619 NUM_OF_RTW89_FLAGS, 4620 }; 4621 4622 enum rtw89_quirks { 4623 RTW89_QUIRK_PCI_BER, 4624 4625 NUM_OF_RTW89_QUIRKS, 4626 }; 4627 4628 enum rtw89_pkt_drop_sel { 4629 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4630 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4631 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4632 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4633 RTW89_PKT_DROP_SEL_MACID_ALL, 4634 RTW89_PKT_DROP_SEL_MG0_ONCE, 4635 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4636 RTW89_PKT_DROP_SEL_HIQ_PORT, 4637 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4638 RTW89_PKT_DROP_SEL_BAND, 4639 RTW89_PKT_DROP_SEL_BAND_ONCE, 4640 RTW89_PKT_DROP_SEL_REL_MACID, 4641 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4642 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4643 }; 4644 4645 struct rtw89_pkt_drop_params { 4646 enum rtw89_pkt_drop_sel sel; 4647 enum rtw89_mac_idx mac_band; 4648 u8 macid; 4649 u8 port; 4650 u8 mbssid; 4651 bool tf_trs; 4652 u32 macid_band_sel[4]; 4653 }; 4654 4655 struct rtw89_pkt_stat { 4656 u16 beacon_nr; 4657 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4658 }; 4659 4660 DECLARE_EWMA(thermal, 4, 4); 4661 4662 struct rtw89_phy_stat { 4663 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4664 struct rtw89_pkt_stat cur_pkt_stat; 4665 struct rtw89_pkt_stat last_pkt_stat; 4666 }; 4667 4668 enum rtw89_rfk_report_state { 4669 RTW89_RFK_STATE_START = 0x0, 4670 RTW89_RFK_STATE_OK = 0x1, 4671 RTW89_RFK_STATE_FAIL = 0x2, 4672 RTW89_RFK_STATE_TIMEOUT = 0x3, 4673 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4674 }; 4675 4676 struct rtw89_rfk_wait_info { 4677 struct completion completion; 4678 ktime_t start_time; 4679 enum rtw89_rfk_report_state state; 4680 u8 version; 4681 }; 4682 4683 #define RTW89_DACK_PATH_NR 2 4684 #define RTW89_DACK_IDX_NR 2 4685 #define RTW89_DACK_MSBK_NR 16 4686 struct rtw89_dack_info { 4687 bool dack_done; 4688 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4689 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4690 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4691 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4692 u32 dack_cnt; 4693 bool addck_timeout[RTW89_DACK_PATH_NR]; 4694 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4695 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4696 }; 4697 4698 enum rtw89_rfk_chs_nrs { 4699 __RTW89_RFK_CHS_NR_V0 = 2, 4700 __RTW89_RFK_CHS_NR_V1 = 3, 4701 4702 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 4703 }; 4704 4705 struct rtw89_rfk_mcc_info { 4706 u8 ch[RTW89_RFK_CHS_NR]; 4707 u8 band[RTW89_RFK_CHS_NR]; 4708 u8 bw[RTW89_RFK_CHS_NR]; 4709 u8 table_idx; 4710 }; 4711 4712 #define RTW89_IQK_CHS_NR 2 4713 #define RTW89_IQK_PATH_NR 4 4714 4715 struct rtw89_lck_info { 4716 u8 thermal[RF_PATH_MAX]; 4717 }; 4718 4719 struct rtw89_rx_dck_info { 4720 u8 thermal[RF_PATH_MAX]; 4721 }; 4722 4723 struct rtw89_iqk_info { 4724 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4725 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4726 bool lok_fail[RTW89_IQK_PATH_NR]; 4727 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4728 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4729 u32 iqk_fail_cnt; 4730 bool is_iqk_init; 4731 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4732 u8 iqk_band[RTW89_IQK_PATH_NR]; 4733 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4734 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4735 u8 iqk_times; 4736 u8 version; 4737 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4738 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4739 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4740 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4741 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4742 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4743 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4744 bool is_nbiqk; 4745 bool iqk_fft_en; 4746 bool iqk_xym_en; 4747 bool iqk_sram_en; 4748 bool iqk_cfir_en; 4749 u32 syn1to2; 4750 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4751 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4752 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4753 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4754 }; 4755 4756 #define RTW89_DPK_RF_PATH 2 4757 #define RTW89_DPK_AVG_THERMAL_NUM 8 4758 #define RTW89_DPK_BKUP_NUM 2 4759 struct rtw89_dpk_bkup_para { 4760 enum rtw89_band band; 4761 enum rtw89_bandwidth bw; 4762 u8 ch; 4763 bool path_ok; 4764 u8 mdpd_en; 4765 u8 txagc_dpk; 4766 u8 ther_dpk; 4767 u8 gs; 4768 u16 pwsf; 4769 }; 4770 4771 struct rtw89_dpk_info { 4772 bool is_dpk_enable; 4773 bool is_dpk_reload_en; 4774 u8 dpk_gs[RTW89_PHY_MAX]; 4775 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4776 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4777 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4778 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4779 u8 cur_idx[RTW89_DPK_RF_PATH]; 4780 u8 cur_k_set; 4781 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4782 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 4783 u32 dpk_order[RTW89_DPK_RF_PATH]; 4784 }; 4785 4786 struct rtw89_fem_info { 4787 bool elna_2g; 4788 bool elna_5g; 4789 bool epa_2g; 4790 bool epa_5g; 4791 bool epa_6g; 4792 }; 4793 4794 struct rtw89_phy_ch_info { 4795 u8 rssi_min; 4796 u16 rssi_min_macid; 4797 u8 pre_rssi_min; 4798 u8 rssi_max; 4799 u16 rssi_max_macid; 4800 u8 rxsc_160; 4801 u8 rxsc_80; 4802 u8 rxsc_40; 4803 u8 rxsc_20; 4804 u8 rxsc_l; 4805 u8 is_noisy; 4806 }; 4807 4808 struct rtw89_agc_gaincode_set { 4809 u8 lna_idx; 4810 u8 tia_idx; 4811 u8 rxb_idx; 4812 }; 4813 4814 #define IGI_RSSI_TH_NUM 5 4815 #define FA_TH_NUM 4 4816 #define LNA_GAIN_NUM 7 4817 #define TIA_GAIN_NUM 2 4818 struct rtw89_dig_info { 4819 struct rtw89_agc_gaincode_set cur_gaincode; 4820 bool force_gaincode_idx_en; 4821 struct rtw89_agc_gaincode_set force_gaincode; 4822 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4823 u16 fa_th[FA_TH_NUM]; 4824 u8 igi_rssi; 4825 u8 igi_fa_rssi; 4826 u8 fa_rssi_ofst; 4827 u8 dyn_igi_max; 4828 u8 dyn_igi_min; 4829 bool dyn_pd_th_en; 4830 u8 dyn_pd_th_max; 4831 u8 pd_low_th_ofst; 4832 u8 ib_pbk; 4833 s8 ib_pkpwr; 4834 s8 lna_gain_a[LNA_GAIN_NUM]; 4835 s8 lna_gain_g[LNA_GAIN_NUM]; 4836 s8 *lna_gain; 4837 s8 tia_gain_a[TIA_GAIN_NUM]; 4838 s8 tia_gain_g[TIA_GAIN_NUM]; 4839 s8 *tia_gain; 4840 bool is_linked_pre; 4841 bool bypass_dig; 4842 }; 4843 4844 enum rtw89_multi_cfo_mode { 4845 RTW89_PKT_BASED_AVG_MODE = 0, 4846 RTW89_ENTRY_BASED_AVG_MODE = 1, 4847 RTW89_TP_BASED_AVG_MODE = 2, 4848 }; 4849 4850 enum rtw89_phy_cfo_status { 4851 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4852 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4853 RTW89_PHY_DCFO_STATE_HOLD = 2, 4854 RTW89_PHY_DCFO_STATE_MAX 4855 }; 4856 4857 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4858 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4859 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4860 }; 4861 4862 struct rtw89_cfo_tracking_info { 4863 u16 cfo_timer_ms; 4864 bool cfo_trig_by_timer_en; 4865 enum rtw89_phy_cfo_status phy_cfo_status; 4866 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4867 u8 phy_cfo_trk_cnt; 4868 bool is_adjust; 4869 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4870 bool apply_compensation; 4871 u8 crystal_cap; 4872 u8 crystal_cap_default; 4873 u8 def_x_cap; 4874 s8 x_cap_ofst; 4875 u32 sta_cfo_tolerance; 4876 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4877 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4878 s32 cfo_avg_pre; 4879 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4880 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4881 s32 dcfo_avg; 4882 s32 dcfo_avg_pre; 4883 u32 packet_count; 4884 u32 packet_count_pre; 4885 s32 residual_cfo_acc; 4886 u8 phy_cfotrk_state; 4887 u8 phy_cfotrk_cnt; 4888 bool divergence_lock_en; 4889 u8 x_cap_lb; 4890 u8 x_cap_ub; 4891 u8 lock_cnt; 4892 }; 4893 4894 enum rtw89_tssi_mode { 4895 RTW89_TSSI_NORMAL = 0, 4896 RTW89_TSSI_SCAN = 1, 4897 }; 4898 4899 enum rtw89_tssi_alimk_band { 4900 TSSI_ALIMK_2G = 0, 4901 TSSI_ALIMK_5GL, 4902 TSSI_ALIMK_5GM, 4903 TSSI_ALIMK_5GH, 4904 TSSI_ALIMK_MAX 4905 }; 4906 4907 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4908 #define TSSI_TRIM_CH_GROUP_NUM 8 4909 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4910 4911 #define TSSI_CCK_CH_GROUP_NUM 6 4912 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4913 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4914 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4915 #define TSSI_MCS_CH_GROUP_NUM \ 4916 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4917 #define TSSI_MAX_CH_NUM 67 4918 #define TSSI_ALIMK_VALUE_NUM 8 4919 4920 struct rtw89_tssi_info { 4921 u8 thermal[RF_PATH_MAX]; 4922 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4923 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4924 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4925 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4926 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4927 s8 extra_ofst[RF_PATH_MAX]; 4928 bool tssi_tracking_check[RF_PATH_MAX]; 4929 u8 default_txagc_offset[RF_PATH_MAX]; 4930 u32 base_thermal[RF_PATH_MAX]; 4931 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4932 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4933 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4934 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4935 u32 tssi_alimk_time; 4936 }; 4937 4938 struct rtw89_power_trim_info { 4939 bool pg_thermal_trim; 4940 bool pg_pa_bias_trim; 4941 u8 thermal_trim[RF_PATH_MAX]; 4942 u8 pa_bias_trim[RF_PATH_MAX]; 4943 u8 pad_bias_trim[RF_PATH_MAX]; 4944 }; 4945 4946 struct rtw89_regd { 4947 char alpha2[3]; 4948 u8 txpwr_regd[RTW89_BAND_NUM]; 4949 }; 4950 4951 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4952 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 4953 #define RTW89_5GHZ_UNII4_START_INDEX 25 4954 4955 struct rtw89_regulatory_info { 4956 const struct rtw89_regd *regd; 4957 enum rtw89_reg_6ghz_power reg_6ghz_power; 4958 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 4959 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 4960 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4961 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 4962 }; 4963 4964 enum rtw89_ifs_clm_application { 4965 RTW89_IFS_CLM_INIT = 0, 4966 RTW89_IFS_CLM_BACKGROUND = 1, 4967 RTW89_IFS_CLM_ACS = 2, 4968 RTW89_IFS_CLM_DIG = 3, 4969 RTW89_IFS_CLM_TDMA_DIG = 4, 4970 RTW89_IFS_CLM_DBG = 5, 4971 RTW89_IFS_CLM_DBG_MANUAL = 6 4972 }; 4973 4974 enum rtw89_env_racing_lv { 4975 RTW89_RAC_RELEASE = 0, 4976 RTW89_RAC_LV_1 = 1, 4977 RTW89_RAC_LV_2 = 2, 4978 RTW89_RAC_LV_3 = 3, 4979 RTW89_RAC_LV_4 = 4, 4980 RTW89_RAC_MAX_NUM = 5 4981 }; 4982 4983 struct rtw89_ccx_para_info { 4984 enum rtw89_env_racing_lv rac_lv; 4985 u16 mntr_time; 4986 u8 nhm_manual_th_ofst; 4987 u8 nhm_manual_th0; 4988 enum rtw89_ifs_clm_application ifs_clm_app; 4989 u32 ifs_clm_manual_th_times; 4990 u32 ifs_clm_manual_th0; 4991 u8 fahm_manual_th_ofst; 4992 u8 fahm_manual_th0; 4993 u8 fahm_numer_opt; 4994 u8 fahm_denom_opt; 4995 }; 4996 4997 enum rtw89_ccx_edcca_opt_sc_idx { 4998 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4999 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5000 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5001 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5002 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5003 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5004 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5005 RTW89_CCX_EDCCA_SEG1_S3 = 7 5006 }; 5007 5008 enum rtw89_ccx_edcca_opt_bw_idx { 5009 RTW89_CCX_EDCCA_BW20_0 = 0, 5010 RTW89_CCX_EDCCA_BW20_1 = 1, 5011 RTW89_CCX_EDCCA_BW20_2 = 2, 5012 RTW89_CCX_EDCCA_BW20_3 = 3, 5013 RTW89_CCX_EDCCA_BW20_4 = 4, 5014 RTW89_CCX_EDCCA_BW20_5 = 5, 5015 RTW89_CCX_EDCCA_BW20_6 = 6, 5016 RTW89_CCX_EDCCA_BW20_7 = 7 5017 }; 5018 5019 #define RTW89_NHM_TH_NUM 11 5020 #define RTW89_FAHM_TH_NUM 11 5021 #define RTW89_NHM_RPT_NUM 12 5022 #define RTW89_FAHM_RPT_NUM 12 5023 #define RTW89_IFS_CLM_NUM 4 5024 struct rtw89_env_monitor_info { 5025 u8 ccx_watchdog_result; 5026 bool ccx_ongoing; 5027 u8 ccx_rac_lv; 5028 bool ccx_manual_ctrl; 5029 u16 ifs_clm_mntr_time; 5030 enum rtw89_ifs_clm_application ifs_clm_app; 5031 u16 ccx_period; 5032 u8 ccx_unit_idx; 5033 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5034 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5035 u16 ifs_clm_tx; 5036 u16 ifs_clm_edcca_excl_cca; 5037 u16 ifs_clm_ofdmfa; 5038 u16 ifs_clm_ofdmcca_excl_fa; 5039 u16 ifs_clm_cckfa; 5040 u16 ifs_clm_cckcca_excl_fa; 5041 u16 ifs_clm_total_ifs; 5042 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5043 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5044 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5045 u8 ifs_clm_tx_ratio; 5046 u8 ifs_clm_edcca_excl_cca_ratio; 5047 u8 ifs_clm_cck_fa_ratio; 5048 u8 ifs_clm_ofdm_fa_ratio; 5049 u8 ifs_clm_cck_cca_excl_fa_ratio; 5050 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5051 u16 ifs_clm_cck_fa_permil; 5052 u16 ifs_clm_ofdm_fa_permil; 5053 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5054 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5055 }; 5056 5057 enum rtw89_ser_rcvy_step { 5058 RTW89_SER_DRV_STOP_TX, 5059 RTW89_SER_DRV_STOP_RX, 5060 RTW89_SER_DRV_STOP_RUN, 5061 RTW89_SER_HAL_STOP_DMA, 5062 RTW89_SER_SUPPRESS_LOG, 5063 RTW89_NUM_OF_SER_FLAGS 5064 }; 5065 5066 struct rtw89_ser { 5067 u8 state; 5068 u8 alarm_event; 5069 bool prehandle_l1; 5070 5071 struct work_struct ser_hdl_work; 5072 struct delayed_work ser_alarm_work; 5073 const struct state_ent *st_tbl; 5074 const struct event_ent *ev_tbl; 5075 struct list_head msg_q; 5076 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5077 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5078 }; 5079 5080 enum rtw89_mac_ax_ps_mode { 5081 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5082 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5083 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5084 RTW89_MAC_AX_PS_MODE_MAX = 3, 5085 }; 5086 5087 enum rtw89_last_rpwm_mode { 5088 RTW89_LAST_RPWM_PS = 0x0, 5089 RTW89_LAST_RPWM_ACTIVE = 0x6, 5090 }; 5091 5092 struct rtw89_lps_parm { 5093 u8 macid; 5094 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5095 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5096 }; 5097 5098 struct rtw89_ppdu_sts_info { 5099 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 5100 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 5101 }; 5102 5103 struct rtw89_early_h2c { 5104 struct list_head list; 5105 u8 *h2c; 5106 u16 h2c_len; 5107 }; 5108 5109 struct rtw89_hw_scan_info { 5110 struct ieee80211_vif *scanning_vif; 5111 struct list_head pkt_list[NUM_NL80211_BANDS]; 5112 struct rtw89_chan op_chan; 5113 bool abort; 5114 u32 last_chan_idx; 5115 }; 5116 5117 enum rtw89_phy_bb_gain_band { 5118 RTW89_BB_GAIN_BAND_2G = 0, 5119 RTW89_BB_GAIN_BAND_5G_L = 1, 5120 RTW89_BB_GAIN_BAND_5G_M = 2, 5121 RTW89_BB_GAIN_BAND_5G_H = 3, 5122 RTW89_BB_GAIN_BAND_6G_L = 4, 5123 RTW89_BB_GAIN_BAND_6G_M = 5, 5124 RTW89_BB_GAIN_BAND_6G_H = 6, 5125 RTW89_BB_GAIN_BAND_6G_UH = 7, 5126 5127 RTW89_BB_GAIN_BAND_NR, 5128 }; 5129 5130 enum rtw89_phy_gain_band_be { 5131 RTW89_BB_GAIN_BAND_2G_BE = 0, 5132 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5133 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5134 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5135 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5136 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5137 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5138 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5139 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5140 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5141 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5142 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5143 5144 RTW89_BB_GAIN_BAND_NR_BE, 5145 }; 5146 5147 enum rtw89_phy_bb_bw_be { 5148 RTW89_BB_BW_20_40 = 0, 5149 RTW89_BB_BW_80_160_320 = 1, 5150 5151 RTW89_BB_BW_NR_BE, 5152 }; 5153 5154 enum rtw89_bw20_sc { 5155 RTW89_BW20_SC_20M = 1, 5156 RTW89_BW20_SC_40M = 2, 5157 RTW89_BW20_SC_80M = 4, 5158 RTW89_BW20_SC_160M = 8, 5159 RTW89_BW20_SC_320M = 16, 5160 }; 5161 5162 enum rtw89_cmac_table_bw { 5163 RTW89_CMAC_BW_20M = 0, 5164 RTW89_CMAC_BW_40M = 1, 5165 RTW89_CMAC_BW_80M = 2, 5166 RTW89_CMAC_BW_160M = 3, 5167 RTW89_CMAC_BW_320M = 4, 5168 5169 RTW89_CMAC_BW_NR, 5170 }; 5171 5172 enum rtw89_phy_bb_rxsc_num { 5173 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5174 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5175 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5176 }; 5177 5178 struct rtw89_phy_bb_gain_info { 5179 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5180 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5181 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5182 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5183 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5184 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5185 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5186 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5187 [RTW89_BB_RXSC_NUM_40]; 5188 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5189 [RTW89_BB_RXSC_NUM_80]; 5190 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5191 [RTW89_BB_RXSC_NUM_160]; 5192 }; 5193 5194 struct rtw89_phy_bb_gain_info_be { 5195 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5196 [LNA_GAIN_NUM]; 5197 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5198 [TIA_GAIN_NUM]; 5199 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5200 [RF_PATH_MAX][LNA_GAIN_NUM]; 5201 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5202 [RF_PATH_MAX][LNA_GAIN_NUM]; 5203 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5204 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5205 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5206 [RTW89_BW20_SC_20M]; 5207 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5208 [RTW89_BW20_SC_40M]; 5209 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5210 [RTW89_BW20_SC_80M]; 5211 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5212 [RTW89_BW20_SC_160M]; 5213 }; 5214 5215 struct rtw89_phy_efuse_gain { 5216 bool offset_valid; 5217 bool comp_valid; 5218 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5219 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5220 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5221 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5222 }; 5223 5224 #define RTW89_MAX_PATTERN_NUM 18 5225 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5226 #define RTW89_MAX_PATTERN_SIZE 128 5227 5228 struct rtw89_wow_cam_info { 5229 bool r_w; 5230 u8 idx; 5231 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5232 u16 crc; 5233 bool negative_pattern_match; 5234 bool skip_mac_hdr; 5235 bool uc; 5236 bool mc; 5237 bool bc; 5238 bool valid; 5239 }; 5240 5241 struct rtw89_wow_key_info { 5242 u8 ptk_tx_iv[8]; 5243 u8 valid_check; 5244 u8 symbol_check_en; 5245 u8 gtk_keyidx; 5246 u8 rsvd[5]; 5247 u8 ptk_rx_iv[8]; 5248 u8 gtk_rx_iv[4][8]; 5249 } __packed; 5250 5251 struct rtw89_wow_gtk_info { 5252 u8 kck[32]; 5253 u8 kek[32]; 5254 u8 tk1[16]; 5255 u8 txmickey[8]; 5256 u8 rxmickey[8]; 5257 __le32 igtk_keyid; 5258 __le64 ipn; 5259 u8 igtk[2][32]; 5260 u8 psk[32]; 5261 } __packed; 5262 5263 struct rtw89_wow_aoac_report { 5264 u8 rpt_ver; 5265 u8 sec_type; 5266 u8 key_idx; 5267 u8 pattern_idx; 5268 u8 rekey_ok; 5269 u8 ptk_tx_iv[8]; 5270 u8 eapol_key_replay_count[8]; 5271 u8 gtk[32]; 5272 u8 ptk_rx_iv[8]; 5273 u8 gtk_rx_iv[4][8]; 5274 u64 igtk_key_id; 5275 u64 igtk_ipn; 5276 u8 igtk[32]; 5277 u8 csa_pri_ch; 5278 u8 csa_bw; 5279 u8 csa_ch_offset; 5280 u8 csa_chsw_failed; 5281 u8 csa_ch_band; 5282 }; 5283 5284 struct rtw89_wow_param { 5285 struct ieee80211_vif *wow_vif; 5286 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5287 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5288 struct rtw89_wow_key_info key_info; 5289 struct rtw89_wow_gtk_info gtk_info; 5290 struct rtw89_wow_aoac_report aoac_rpt; 5291 u8 pattern_cnt; 5292 u8 ptk_alg; 5293 u8 gtk_alg; 5294 u8 ptk_keyidx; 5295 u8 akm; 5296 }; 5297 5298 struct rtw89_mcc_limit { 5299 bool enable; 5300 u16 max_tob; /* TU; max time offset behind */ 5301 u16 max_toa; /* TU; max time offset ahead */ 5302 u16 max_dur; /* TU */ 5303 }; 5304 5305 struct rtw89_mcc_policy { 5306 u8 c2h_rpt; 5307 u8 tx_null_early; 5308 u8 dis_tx_null; 5309 u8 in_curr_ch; 5310 u8 dis_sw_retry; 5311 u8 sw_retry_count; 5312 }; 5313 5314 struct rtw89_mcc_role { 5315 struct rtw89_vif *rtwvif; 5316 struct rtw89_mcc_policy policy; 5317 struct rtw89_mcc_limit limit; 5318 5319 /* only valid when running with FW MRC mechanism */ 5320 u8 slot_idx; 5321 5322 /* byte-array in LE order for FW */ 5323 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5324 5325 u16 duration; /* TU */ 5326 u16 beacon_interval; /* TU */ 5327 bool is_2ghz; 5328 bool is_go; 5329 bool is_gc; 5330 }; 5331 5332 struct rtw89_mcc_bt_role { 5333 u16 duration; /* TU */ 5334 }; 5335 5336 struct rtw89_mcc_courtesy { 5337 bool enable; 5338 u8 slot_num; 5339 u8 macid_src; 5340 u8 macid_tgt; 5341 }; 5342 5343 enum rtw89_mcc_plan { 5344 RTW89_MCC_PLAN_TAIL_BT, 5345 RTW89_MCC_PLAN_MID_BT, 5346 RTW89_MCC_PLAN_NO_BT, 5347 5348 NUM_OF_RTW89_MCC_PLAN, 5349 }; 5350 5351 struct rtw89_mcc_pattern { 5352 s16 tob_ref; /* TU; time offset behind of reference role */ 5353 s16 toa_ref; /* TU; time offset ahead of reference role */ 5354 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5355 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5356 5357 enum rtw89_mcc_plan plan; 5358 struct rtw89_mcc_courtesy courtesy; 5359 }; 5360 5361 struct rtw89_mcc_sync { 5362 bool enable; 5363 u16 offset; /* TU */ 5364 u8 macid_src; 5365 u8 band_src; 5366 u8 port_src; 5367 u8 macid_tgt; 5368 u8 band_tgt; 5369 u8 port_tgt; 5370 }; 5371 5372 struct rtw89_mcc_config { 5373 struct rtw89_mcc_pattern pattern; 5374 struct rtw89_mcc_sync sync; 5375 u64 start_tsf; 5376 u16 mcc_interval; /* TU */ 5377 u16 beacon_offset; /* TU */ 5378 }; 5379 5380 enum rtw89_mcc_mode { 5381 RTW89_MCC_MODE_GO_STA, 5382 RTW89_MCC_MODE_GC_STA, 5383 }; 5384 5385 struct rtw89_mcc_info { 5386 struct rtw89_wait_info wait; 5387 5388 u8 group; 5389 enum rtw89_mcc_mode mode; 5390 struct rtw89_mcc_role role_ref; /* reference role */ 5391 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5392 struct rtw89_mcc_bt_role bt_role; 5393 struct rtw89_mcc_config config; 5394 }; 5395 5396 struct rtw89_dev { 5397 struct ieee80211_hw *hw; 5398 struct device *dev; 5399 const struct ieee80211_ops *ops; 5400 5401 bool dbcc_en; 5402 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5403 struct rtw89_hw_scan_info scan_info; 5404 const struct rtw89_chip_info *chip; 5405 const struct rtw89_pci_info *pci_info; 5406 const struct rtw89_rfe_parms *rfe_parms; 5407 struct rtw89_hal hal; 5408 struct rtw89_mcc_info mcc; 5409 struct rtw89_mac_info mac; 5410 struct rtw89_fw_info fw; 5411 struct rtw89_hci_info hci; 5412 struct rtw89_efuse efuse; 5413 struct rtw89_traffic_stats stats; 5414 struct rtw89_rfe_data *rfe_data; 5415 5416 /* ensures exclusive access from mac80211 callbacks */ 5417 struct mutex mutex; 5418 struct list_head rtwvifs_list; 5419 /* used to protect rf read write */ 5420 struct mutex rf_mutex; 5421 struct workqueue_struct *txq_wq; 5422 struct work_struct txq_work; 5423 struct delayed_work txq_reinvoke_work; 5424 /* used to protect ba_list and forbid_ba_list */ 5425 spinlock_t ba_lock; 5426 /* txqs to setup ba session */ 5427 struct list_head ba_list; 5428 /* txqs to forbid ba session */ 5429 struct list_head forbid_ba_list; 5430 struct work_struct ba_work; 5431 /* used to protect rpwm */ 5432 spinlock_t rpwm_lock; 5433 5434 struct rtw89_cam_info cam_info; 5435 5436 struct sk_buff_head c2h_queue; 5437 struct work_struct c2h_work; 5438 struct work_struct ips_work; 5439 struct work_struct load_firmware_work; 5440 struct work_struct cancel_6ghz_probe_work; 5441 5442 struct list_head early_h2c_list; 5443 5444 struct rtw89_ser ser; 5445 5446 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5447 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5448 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5449 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5450 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5451 5452 struct rtw89_phy_stat phystat; 5453 struct rtw89_rfk_wait_info rfk_wait; 5454 struct rtw89_dack_info dack; 5455 struct rtw89_iqk_info iqk; 5456 struct rtw89_dpk_info dpk; 5457 struct rtw89_rfk_mcc_info rfk_mcc; 5458 struct rtw89_lck_info lck; 5459 struct rtw89_rx_dck_info rx_dck; 5460 bool is_tssi_mode[RF_PATH_MAX]; 5461 bool is_bt_iqk_timeout; 5462 5463 struct rtw89_fem_info fem; 5464 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5465 struct rtw89_tssi_info tssi; 5466 struct rtw89_power_trim_info pwr_trim; 5467 5468 struct rtw89_cfo_tracking_info cfo_tracking; 5469 struct rtw89_env_monitor_info env_monitor; 5470 struct rtw89_dig_info dig; 5471 struct rtw89_phy_ch_info ch_info; 5472 union { 5473 struct rtw89_phy_bb_gain_info ax; 5474 struct rtw89_phy_bb_gain_info_be be; 5475 } bb_gain; 5476 struct rtw89_phy_efuse_gain efuse_gain; 5477 struct rtw89_phy_ul_tb_info ul_tb_info; 5478 struct rtw89_antdiv_info antdiv; 5479 5480 struct delayed_work track_work; 5481 struct delayed_work chanctx_work; 5482 struct delayed_work coex_act1_work; 5483 struct delayed_work coex_bt_devinfo_work; 5484 struct delayed_work coex_rfk_chk_work; 5485 struct delayed_work cfo_track_work; 5486 struct delayed_work forbid_ba_work; 5487 struct delayed_work roc_work; 5488 struct delayed_work antdiv_work; 5489 struct rtw89_ppdu_sts_info ppdu_sts; 5490 u8 total_sta_assoc; 5491 bool scanning; 5492 5493 struct rtw89_regulatory_info regulatory; 5494 struct rtw89_sar_info sar; 5495 struct rtw89_tas_info tas; 5496 5497 struct rtw89_btc btc; 5498 enum rtw89_ps_mode ps_mode; 5499 bool lps_enabled; 5500 5501 struct rtw89_wow_param wow; 5502 5503 /* napi structure */ 5504 struct net_device *netdev; 5505 struct napi_struct napi; 5506 int napi_budget_countdown; 5507 5508 /* HCI related data, keep last */ 5509 u8 priv[] __aligned(sizeof(void *)); 5510 }; 5511 5512 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5513 struct rtw89_core_tx_request *tx_req) 5514 { 5515 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5516 } 5517 5518 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5519 { 5520 rtwdev->hci.ops->reset(rtwdev); 5521 } 5522 5523 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5524 { 5525 return rtwdev->hci.ops->start(rtwdev); 5526 } 5527 5528 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5529 { 5530 rtwdev->hci.ops->stop(rtwdev); 5531 } 5532 5533 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5534 { 5535 return rtwdev->hci.ops->deinit(rtwdev); 5536 } 5537 5538 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5539 { 5540 rtwdev->hci.ops->pause(rtwdev, pause); 5541 } 5542 5543 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5544 { 5545 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5546 } 5547 5548 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5549 { 5550 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5551 } 5552 5553 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5554 { 5555 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5556 } 5557 5558 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5559 { 5560 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5561 } 5562 5563 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5564 { 5565 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5566 } 5567 5568 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5569 bool drop) 5570 { 5571 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5572 return; 5573 5574 if (rtwdev->hci.ops->flush_queues) 5575 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5576 } 5577 5578 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5579 { 5580 if (rtwdev->hci.ops->recovery_start) 5581 rtwdev->hci.ops->recovery_start(rtwdev); 5582 } 5583 5584 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5585 { 5586 if (rtwdev->hci.ops->recovery_complete) 5587 rtwdev->hci.ops->recovery_complete(rtwdev); 5588 } 5589 5590 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5591 { 5592 if (rtwdev->hci.ops->enable_intr) 5593 rtwdev->hci.ops->enable_intr(rtwdev); 5594 } 5595 5596 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5597 { 5598 if (rtwdev->hci.ops->disable_intr) 5599 rtwdev->hci.ops->disable_intr(rtwdev); 5600 } 5601 5602 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5603 { 5604 if (rtwdev->hci.ops->ctrl_txdma_ch) 5605 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5606 } 5607 5608 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5609 { 5610 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5611 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5612 } 5613 5614 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5615 { 5616 if (rtwdev->hci.ops->ctrl_trxhci) 5617 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5618 } 5619 5620 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5621 { 5622 int ret = 0; 5623 5624 if (rtwdev->hci.ops->poll_txdma_ch_idle) 5625 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 5626 return ret; 5627 } 5628 5629 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5630 { 5631 if (rtwdev->hci.ops->clr_idx_all) 5632 rtwdev->hci.ops->clr_idx_all(rtwdev); 5633 } 5634 5635 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 5636 { 5637 int ret = 0; 5638 5639 if (rtwdev->hci.ops->rst_bdram) 5640 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 5641 return ret; 5642 } 5643 5644 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 5645 { 5646 if (rtwdev->hci.ops->clear) 5647 rtwdev->hci.ops->clear(rtwdev, pdev); 5648 } 5649 5650 static inline 5651 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5652 { 5653 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5654 5655 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5656 } 5657 5658 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5659 { 5660 return rtwdev->hci.ops->read8(rtwdev, addr); 5661 } 5662 5663 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5664 { 5665 return rtwdev->hci.ops->read16(rtwdev, addr); 5666 } 5667 5668 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5669 { 5670 return rtwdev->hci.ops->read32(rtwdev, addr); 5671 } 5672 5673 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5674 { 5675 rtwdev->hci.ops->write8(rtwdev, addr, data); 5676 } 5677 5678 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5679 { 5680 rtwdev->hci.ops->write16(rtwdev, addr, data); 5681 } 5682 5683 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5684 { 5685 rtwdev->hci.ops->write32(rtwdev, addr, data); 5686 } 5687 5688 static inline void 5689 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5690 { 5691 u8 val; 5692 5693 val = rtw89_read8(rtwdev, addr); 5694 rtw89_write8(rtwdev, addr, val | bit); 5695 } 5696 5697 static inline void 5698 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5699 { 5700 u16 val; 5701 5702 val = rtw89_read16(rtwdev, addr); 5703 rtw89_write16(rtwdev, addr, val | bit); 5704 } 5705 5706 static inline void 5707 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5708 { 5709 u32 val; 5710 5711 val = rtw89_read32(rtwdev, addr); 5712 rtw89_write32(rtwdev, addr, val | bit); 5713 } 5714 5715 static inline void 5716 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5717 { 5718 u8 val; 5719 5720 val = rtw89_read8(rtwdev, addr); 5721 rtw89_write8(rtwdev, addr, val & ~bit); 5722 } 5723 5724 static inline void 5725 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5726 { 5727 u16 val; 5728 5729 val = rtw89_read16(rtwdev, addr); 5730 rtw89_write16(rtwdev, addr, val & ~bit); 5731 } 5732 5733 static inline void 5734 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5735 { 5736 u32 val; 5737 5738 val = rtw89_read32(rtwdev, addr); 5739 rtw89_write32(rtwdev, addr, val & ~bit); 5740 } 5741 5742 static inline u32 5743 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5744 { 5745 u32 shift = __ffs(mask); 5746 u32 orig; 5747 u32 ret; 5748 5749 orig = rtw89_read32(rtwdev, addr); 5750 ret = (orig & mask) >> shift; 5751 5752 return ret; 5753 } 5754 5755 static inline u16 5756 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5757 { 5758 u32 shift = __ffs(mask); 5759 u32 orig; 5760 u32 ret; 5761 5762 orig = rtw89_read16(rtwdev, addr); 5763 ret = (orig & mask) >> shift; 5764 5765 return ret; 5766 } 5767 5768 static inline u8 5769 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5770 { 5771 u32 shift = __ffs(mask); 5772 u32 orig; 5773 u32 ret; 5774 5775 orig = rtw89_read8(rtwdev, addr); 5776 ret = (orig & mask) >> shift; 5777 5778 return ret; 5779 } 5780 5781 static inline void 5782 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5783 { 5784 u32 shift = __ffs(mask); 5785 u32 orig; 5786 u32 set; 5787 5788 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5789 5790 orig = rtw89_read32(rtwdev, addr); 5791 set = (orig & ~mask) | ((data << shift) & mask); 5792 rtw89_write32(rtwdev, addr, set); 5793 } 5794 5795 static inline void 5796 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5797 { 5798 u32 shift; 5799 u16 orig, set; 5800 5801 mask &= 0xffff; 5802 shift = __ffs(mask); 5803 5804 orig = rtw89_read16(rtwdev, addr); 5805 set = (orig & ~mask) | ((data << shift) & mask); 5806 rtw89_write16(rtwdev, addr, set); 5807 } 5808 5809 static inline void 5810 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5811 { 5812 u32 shift; 5813 u8 orig, set; 5814 5815 mask &= 0xff; 5816 shift = __ffs(mask); 5817 5818 orig = rtw89_read8(rtwdev, addr); 5819 set = (orig & ~mask) | ((data << shift) & mask); 5820 rtw89_write8(rtwdev, addr, set); 5821 } 5822 5823 static inline u32 5824 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5825 u32 addr, u32 mask) 5826 { 5827 u32 val; 5828 5829 mutex_lock(&rtwdev->rf_mutex); 5830 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5831 mutex_unlock(&rtwdev->rf_mutex); 5832 5833 return val; 5834 } 5835 5836 static inline void 5837 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5838 u32 addr, u32 mask, u32 data) 5839 { 5840 mutex_lock(&rtwdev->rf_mutex); 5841 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5842 mutex_unlock(&rtwdev->rf_mutex); 5843 } 5844 5845 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5846 { 5847 void *p = rtwtxq; 5848 5849 return container_of(p, struct ieee80211_txq, drv_priv); 5850 } 5851 5852 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5853 struct ieee80211_txq *txq) 5854 { 5855 struct rtw89_txq *rtwtxq; 5856 5857 if (!txq) 5858 return; 5859 5860 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5861 INIT_LIST_HEAD(&rtwtxq->list); 5862 } 5863 5864 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5865 { 5866 void *p = rtwvif; 5867 5868 return container_of(p, struct ieee80211_vif, drv_priv); 5869 } 5870 5871 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5872 { 5873 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5874 } 5875 5876 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5877 { 5878 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5879 } 5880 5881 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5882 { 5883 void *p = rtwsta; 5884 5885 return container_of(p, struct ieee80211_sta, drv_priv); 5886 } 5887 5888 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5889 { 5890 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5891 } 5892 5893 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5894 { 5895 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5896 } 5897 5898 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5899 { 5900 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5901 return RATE_INFO_BW_160; 5902 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5903 return RATE_INFO_BW_80; 5904 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5905 return RATE_INFO_BW_40; 5906 else 5907 return RATE_INFO_BW_20; 5908 } 5909 5910 static inline 5911 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5912 { 5913 switch (hw_band) { 5914 default: 5915 case RTW89_BAND_2G: 5916 return NL80211_BAND_2GHZ; 5917 case RTW89_BAND_5G: 5918 return NL80211_BAND_5GHZ; 5919 case RTW89_BAND_6G: 5920 return NL80211_BAND_6GHZ; 5921 } 5922 } 5923 5924 static inline 5925 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5926 { 5927 switch (nl_band) { 5928 default: 5929 case NL80211_BAND_2GHZ: 5930 return RTW89_BAND_2G; 5931 case NL80211_BAND_5GHZ: 5932 return RTW89_BAND_5G; 5933 case NL80211_BAND_6GHZ: 5934 return RTW89_BAND_6G; 5935 } 5936 } 5937 5938 static inline 5939 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5940 { 5941 switch (width) { 5942 default: 5943 WARN(1, "Not support bandwidth %d\n", width); 5944 fallthrough; 5945 case NL80211_CHAN_WIDTH_20_NOHT: 5946 case NL80211_CHAN_WIDTH_20: 5947 return RTW89_CHANNEL_WIDTH_20; 5948 case NL80211_CHAN_WIDTH_40: 5949 return RTW89_CHANNEL_WIDTH_40; 5950 case NL80211_CHAN_WIDTH_80: 5951 return RTW89_CHANNEL_WIDTH_80; 5952 case NL80211_CHAN_WIDTH_160: 5953 return RTW89_CHANNEL_WIDTH_160; 5954 } 5955 } 5956 5957 static inline 5958 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5959 { 5960 switch (rua) { 5961 default: 5962 WARN(1, "Invalid RU allocation: %d\n", rua); 5963 fallthrough; 5964 case 0 ... 36: 5965 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5966 case 37 ... 52: 5967 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5968 case 53 ... 60: 5969 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5970 case 61 ... 64: 5971 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5972 case 65 ... 66: 5973 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5974 case 67: 5975 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5976 case 68: 5977 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5978 } 5979 } 5980 5981 static inline 5982 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5983 struct rtw89_sta *rtwsta) 5984 { 5985 if (rtwsta) { 5986 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5987 5988 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5989 return &rtwsta->addr_cam; 5990 } 5991 return &rtwvif->addr_cam; 5992 } 5993 5994 static inline 5995 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5996 struct rtw89_sta *rtwsta) 5997 { 5998 if (rtwsta) { 5999 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 6000 6001 if (sta->tdls) 6002 return &rtwsta->bssid_cam; 6003 } 6004 return &rtwvif->bssid_cam; 6005 } 6006 6007 static inline 6008 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6009 struct rtw89_channel_help_params *p, 6010 const struct rtw89_chan *chan, 6011 enum rtw89_mac_idx mac_idx, 6012 enum rtw89_phy_idx phy_idx) 6013 { 6014 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6015 mac_idx, phy_idx); 6016 } 6017 6018 static inline 6019 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6020 struct rtw89_channel_help_params *p, 6021 const struct rtw89_chan *chan, 6022 enum rtw89_mac_idx mac_idx, 6023 enum rtw89_phy_idx phy_idx) 6024 { 6025 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6026 mac_idx, phy_idx); 6027 } 6028 6029 static inline 6030 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6031 enum rtw89_sub_entity_idx idx) 6032 { 6033 struct rtw89_hal *hal = &rtwdev->hal; 6034 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 6035 6036 if (roc_idx == idx) 6037 return &hal->roc_chandef; 6038 6039 return &hal->sub[idx].chandef; 6040 } 6041 6042 static inline 6043 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6044 enum rtw89_sub_entity_idx idx) 6045 { 6046 struct rtw89_hal *hal = &rtwdev->hal; 6047 6048 return &hal->sub[idx].chan; 6049 } 6050 6051 static inline 6052 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6053 enum rtw89_sub_entity_idx idx) 6054 { 6055 struct rtw89_hal *hal = &rtwdev->hal; 6056 6057 return &hal->sub[idx].rcd; 6058 } 6059 6060 static inline 6061 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6062 { 6063 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 6064 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 6065 6066 if (rtwvif) 6067 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 6068 else 6069 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 6070 } 6071 6072 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6073 { 6074 const struct rtw89_chip_info *chip = rtwdev->chip; 6075 6076 if (chip->ops->fem_setup) 6077 chip->ops->fem_setup(rtwdev); 6078 } 6079 6080 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6081 { 6082 const struct rtw89_chip_info *chip = rtwdev->chip; 6083 6084 if (chip->ops->rfe_gpio) 6085 chip->ops->rfe_gpio(rtwdev); 6086 } 6087 6088 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6089 { 6090 const struct rtw89_chip_info *chip = rtwdev->chip; 6091 6092 if (chip->ops->rfk_hw_init) 6093 chip->ops->rfk_hw_init(rtwdev); 6094 } 6095 6096 static inline 6097 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6098 { 6099 const struct rtw89_chip_info *chip = rtwdev->chip; 6100 6101 if (chip->ops->bb_preinit) 6102 chip->ops->bb_preinit(rtwdev, phy_idx); 6103 } 6104 6105 static inline 6106 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6107 { 6108 const struct rtw89_chip_info *chip = rtwdev->chip; 6109 6110 if (!chip->ops->bb_postinit) 6111 return; 6112 6113 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6114 6115 if (rtwdev->dbcc_en) 6116 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6117 } 6118 6119 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6120 { 6121 const struct rtw89_chip_info *chip = rtwdev->chip; 6122 6123 if (chip->ops->bb_sethw) 6124 chip->ops->bb_sethw(rtwdev); 6125 } 6126 6127 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6128 { 6129 const struct rtw89_chip_info *chip = rtwdev->chip; 6130 6131 if (chip->ops->rfk_init) 6132 chip->ops->rfk_init(rtwdev); 6133 } 6134 6135 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6136 { 6137 const struct rtw89_chip_info *chip = rtwdev->chip; 6138 6139 if (chip->ops->rfk_init_late) 6140 chip->ops->rfk_init_late(rtwdev); 6141 } 6142 6143 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 6144 { 6145 const struct rtw89_chip_info *chip = rtwdev->chip; 6146 6147 if (chip->ops->rfk_channel) 6148 chip->ops->rfk_channel(rtwdev); 6149 } 6150 6151 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6152 enum rtw89_phy_idx phy_idx) 6153 { 6154 const struct rtw89_chip_info *chip = rtwdev->chip; 6155 6156 if (chip->ops->rfk_band_changed) 6157 chip->ops->rfk_band_changed(rtwdev, phy_idx); 6158 } 6159 6160 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 6161 { 6162 const struct rtw89_chip_info *chip = rtwdev->chip; 6163 6164 if (chip->ops->rfk_scan) 6165 chip->ops->rfk_scan(rtwdev, start); 6166 } 6167 6168 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6169 { 6170 const struct rtw89_chip_info *chip = rtwdev->chip; 6171 6172 if (chip->ops->rfk_track) 6173 chip->ops->rfk_track(rtwdev); 6174 } 6175 6176 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6177 { 6178 const struct rtw89_chip_info *chip = rtwdev->chip; 6179 6180 if (chip->ops->set_txpwr_ctrl) 6181 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6182 } 6183 6184 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6185 { 6186 const struct rtw89_chip_info *chip = rtwdev->chip; 6187 6188 if (chip->ops->power_trim) 6189 chip->ops->power_trim(rtwdev); 6190 } 6191 6192 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6193 enum rtw89_phy_idx phy_idx) 6194 { 6195 const struct rtw89_chip_info *chip = rtwdev->chip; 6196 6197 if (chip->ops->init_txpwr_unit) 6198 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6199 } 6200 6201 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6202 enum rtw89_rf_path rf_path) 6203 { 6204 const struct rtw89_chip_info *chip = rtwdev->chip; 6205 6206 if (!chip->ops->get_thermal) 6207 return 0x10; 6208 6209 return chip->ops->get_thermal(rtwdev, rf_path); 6210 } 6211 6212 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6213 struct rtw89_rx_phy_ppdu *phy_ppdu, 6214 struct ieee80211_rx_status *status) 6215 { 6216 const struct rtw89_chip_info *chip = rtwdev->chip; 6217 6218 if (chip->ops->query_ppdu) 6219 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6220 } 6221 6222 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6223 enum rtw89_phy_idx phy_idx) 6224 { 6225 const struct rtw89_chip_info *chip = rtwdev->chip; 6226 6227 if (chip->ops->ctrl_nbtg_bt_tx) 6228 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6229 } 6230 6231 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6232 { 6233 const struct rtw89_chip_info *chip = rtwdev->chip; 6234 6235 if (chip->ops->cfg_txrx_path) 6236 chip->ops->cfg_txrx_path(rtwdev); 6237 } 6238 6239 static inline 6240 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 6241 struct ieee80211_vif *vif) 6242 { 6243 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6244 const struct rtw89_chip_info *chip = rtwdev->chip; 6245 6246 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 6247 return; 6248 6249 if (chip->ops->set_txpwr_ul_tb_offset) 6250 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 6251 } 6252 6253 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6254 const struct rtw89_txpwr_table *tbl) 6255 { 6256 tbl->load(rtwdev, tbl); 6257 } 6258 6259 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6260 { 6261 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6262 6263 return regd->txpwr_regd[band]; 6264 } 6265 6266 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6267 enum rtw89_phy_idx phy_idx) 6268 { 6269 const struct rtw89_chip_info *chip = rtwdev->chip; 6270 6271 if (chip->ops->ctrl_btg_bt_rx) 6272 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6273 } 6274 6275 static inline 6276 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6277 struct rtw89_rx_desc_info *desc_info, 6278 u8 *data, u32 data_offset) 6279 { 6280 const struct rtw89_chip_info *chip = rtwdev->chip; 6281 6282 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6283 } 6284 6285 static inline 6286 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6287 struct rtw89_tx_desc_info *desc_info, 6288 void *txdesc) 6289 { 6290 const struct rtw89_chip_info *chip = rtwdev->chip; 6291 6292 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6293 } 6294 6295 static inline 6296 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6297 struct rtw89_tx_desc_info *desc_info, 6298 void *txdesc) 6299 { 6300 const struct rtw89_chip_info *chip = rtwdev->chip; 6301 6302 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6303 } 6304 6305 static inline 6306 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6307 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6308 { 6309 const struct rtw89_chip_info *chip = rtwdev->chip; 6310 6311 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6312 } 6313 6314 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6315 { 6316 const struct rtw89_chip_info *chip = rtwdev->chip; 6317 6318 chip->ops->cfg_ctrl_path(rtwdev, wl); 6319 } 6320 6321 static inline 6322 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6323 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6324 { 6325 const struct rtw89_chip_info *chip = rtwdev->chip; 6326 6327 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6328 } 6329 6330 static inline 6331 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6332 { 6333 const struct rtw89_chip_info *chip = rtwdev->chip; 6334 6335 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6336 } 6337 6338 static inline 6339 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6340 struct rtw89_vif *rtwvif, 6341 struct rtw89_sta *rtwsta) 6342 { 6343 const struct rtw89_chip_info *chip = rtwdev->chip; 6344 6345 if (!chip->ops->h2c_dctl_sec_cam) 6346 return 0; 6347 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 6348 } 6349 6350 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6351 { 6352 __le16 fc = hdr->frame_control; 6353 6354 if (ieee80211_has_tods(fc)) 6355 return hdr->addr1; 6356 else if (ieee80211_has_fromds(fc)) 6357 return hdr->addr2; 6358 else 6359 return hdr->addr3; 6360 } 6361 6362 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 6363 { 6364 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6365 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6366 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 6367 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6368 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 6369 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6370 return true; 6371 return false; 6372 } 6373 6374 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6375 enum rtw89_fw_type type) 6376 { 6377 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6378 6379 switch (type) { 6380 case RTW89_FW_WOWLAN: 6381 return &fw_info->wowlan; 6382 case RTW89_FW_LOGFMT: 6383 return &fw_info->log.suit; 6384 case RTW89_FW_BBMCU0: 6385 return &fw_info->bbmcu0; 6386 case RTW89_FW_BBMCU1: 6387 return &fw_info->bbmcu1; 6388 default: 6389 break; 6390 } 6391 6392 return &fw_info->normal; 6393 } 6394 6395 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6396 unsigned int length) 6397 { 6398 struct sk_buff *skb; 6399 6400 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6401 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6402 if (!skb) 6403 return NULL; 6404 6405 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6406 return skb; 6407 } 6408 6409 return dev_alloc_skb(length); 6410 } 6411 6412 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6413 struct rtw89_tx_skb_data *skb_data, 6414 bool tx_done) 6415 { 6416 struct rtw89_tx_wait_info *wait; 6417 6418 rcu_read_lock(); 6419 6420 wait = rcu_dereference(skb_data->wait); 6421 if (!wait) 6422 goto out; 6423 6424 wait->tx_done = tx_done; 6425 complete(&wait->completion); 6426 6427 out: 6428 rcu_read_unlock(); 6429 } 6430 6431 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6432 { 6433 switch (rtwdev->mlo_dbcc_mode) { 6434 case MLO_1_PLUS_1_1RF: 6435 case MLO_1_PLUS_1_2RF: 6436 case DBCC_LEGACY: 6437 return true; 6438 default: 6439 return false; 6440 } 6441 } 6442 6443 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 6444 { 6445 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6446 6447 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 6448 return true; 6449 6450 return false; 6451 } 6452 6453 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6454 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6455 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6456 struct sk_buff *skb, bool fwdl); 6457 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6458 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6459 int qsel, unsigned int timeout); 6460 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6461 struct rtw89_tx_desc_info *desc_info, 6462 void *txdesc); 6463 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6464 struct rtw89_tx_desc_info *desc_info, 6465 void *txdesc); 6466 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6467 struct rtw89_tx_desc_info *desc_info, 6468 void *txdesc); 6469 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6470 struct rtw89_tx_desc_info *desc_info, 6471 void *txdesc); 6472 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6473 struct rtw89_tx_desc_info *desc_info, 6474 void *txdesc); 6475 void rtw89_core_rx(struct rtw89_dev *rtwdev, 6476 struct rtw89_rx_desc_info *desc_info, 6477 struct sk_buff *skb); 6478 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 6479 struct rtw89_rx_desc_info *desc_info, 6480 u8 *data, u32 data_offset); 6481 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 6482 struct rtw89_rx_desc_info *desc_info, 6483 u8 *data, u32 data_offset); 6484 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 6485 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 6486 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 6487 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 6488 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 6489 struct ieee80211_vif *vif, 6490 struct ieee80211_sta *sta); 6491 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 6492 struct ieee80211_vif *vif, 6493 struct ieee80211_sta *sta); 6494 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 6495 struct ieee80211_vif *vif, 6496 struct ieee80211_sta *sta); 6497 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 6498 struct ieee80211_vif *vif, 6499 struct ieee80211_sta *sta); 6500 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 6501 struct ieee80211_vif *vif, 6502 struct ieee80211_sta *sta); 6503 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6504 struct ieee80211_sta *sta, 6505 struct cfg80211_tid_config *tid_config); 6506 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 6507 int rtw89_core_init(struct rtw89_dev *rtwdev); 6508 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 6509 int rtw89_core_register(struct rtw89_dev *rtwdev); 6510 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 6511 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6512 u32 bus_data_size, 6513 const struct rtw89_chip_info *chip); 6514 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 6515 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 6516 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 6517 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 6518 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 6519 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 6520 struct rtw89_chan *chan); 6521 int rtw89_set_channel(struct rtw89_dev *rtwdev); 6522 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6523 struct rtw89_chan *chan); 6524 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 6525 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 6526 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 6527 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 6528 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6529 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 6530 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6531 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 6532 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 6533 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 6534 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 6535 int rtw89_regd_init(struct rtw89_dev *rtwdev, 6536 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 6537 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 6538 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 6539 struct rtw89_traffic_stats *stats); 6540 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 6541 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6542 const struct rtw89_completion_data *data); 6543 int rtw89_core_start(struct rtw89_dev *rtwdev); 6544 void rtw89_core_stop(struct rtw89_dev *rtwdev); 6545 void rtw89_core_update_beacon_work(struct work_struct *work); 6546 void rtw89_roc_work(struct work_struct *work); 6547 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6548 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6549 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6550 const u8 *mac_addr, bool hw_scan); 6551 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6552 struct ieee80211_vif *vif, bool hw_scan); 6553 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6554 bool active); 6555 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 6556 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 6557 6558 #endif 6559