1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_fw_blacklist; 21 struct rtw89_efuse_block_cfg; 22 struct rtw89_h2c_rf_tssi; 23 struct rtw89_fw_txpwr_track_cfg; 24 struct rtw89_phy_rfk_log_fmt; 25 struct rtw89_debugfs; 26 struct rtw89_regd_data; 27 28 extern const struct ieee80211_ops rtw89_ops; 29 30 #define MASKBYTE0 0xff 31 #define MASKBYTE1 0xff00 32 #define MASKBYTE2 0xff0000 33 #define MASKBYTE3 0xff000000 34 #define MASKBYTE4 0xff00000000ULL 35 #define MASKHWORD 0xffff0000 36 #define MASKLWORD 0x0000ffff 37 #define MASKDWORD 0xffffffff 38 #define RFREG_MASK 0xfffff 39 #define INV_RF_DATA 0xffffffff 40 #define BYPASS_CR_DATA 0xbabecafe 41 42 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 43 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 44 #define CFO_TRACK_MAX_USER 64 45 #define MAX_RSSI 110 46 #define RSSI_FACTOR 1 47 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 48 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 49 #define DELTA_SWINGIDX_SIZE 30 50 51 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 52 #define RTW89_RADIOTAP_ROOM_EHT \ 53 (sizeof(struct ieee80211_radiotap_tlv) + \ 54 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 55 sizeof(struct ieee80211_radiotap_tlv) + \ 56 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 57 #define RTW89_RADIOTAP_ROOM \ 58 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 59 60 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 61 #define RTW89_HTC_VARIANT_HE 3 62 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 63 #define RTW89_HTC_VARIANT_HE_CID_OM 1 64 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 65 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 66 67 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 68 enum htc_om_channel_width { 69 HTC_OM_CHANNEL_WIDTH_20 = 0, 70 HTC_OM_CHANNEL_WIDTH_40 = 1, 71 HTC_OM_CHANNEL_WIDTH_80 = 2, 72 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 73 }; 74 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 75 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 76 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 77 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 78 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 79 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 80 81 #define RTW89_TF_PAD GENMASK(11, 0) 82 #define RTW89_TF_BASIC_USER_INFO_SZ 6 83 84 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 86 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 87 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 88 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 89 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 90 91 enum rtw89_subband { 92 RTW89_CH_2G = 0, 93 RTW89_CH_5G_BAND_1 = 1, 94 /* RTW89_CH_5G_BAND_2 = 2, unused */ 95 RTW89_CH_5G_BAND_3 = 3, 96 RTW89_CH_5G_BAND_4 = 4, 97 98 RTW89_CH_6G_BAND_IDX0, /* Low */ 99 RTW89_CH_6G_BAND_IDX1, /* Low */ 100 RTW89_CH_6G_BAND_IDX2, /* Mid */ 101 RTW89_CH_6G_BAND_IDX3, /* Mid */ 102 RTW89_CH_6G_BAND_IDX4, /* High */ 103 RTW89_CH_6G_BAND_IDX5, /* High */ 104 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 105 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 106 107 RTW89_SUBBAND_NR, 108 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 109 }; 110 111 enum rtw89_gain_offset { 112 RTW89_GAIN_OFFSET_2G_CCK, 113 RTW89_GAIN_OFFSET_2G_OFDM, 114 RTW89_GAIN_OFFSET_5G_LOW, 115 RTW89_GAIN_OFFSET_5G_MID, 116 RTW89_GAIN_OFFSET_5G_HIGH, 117 RTW89_GAIN_OFFSET_6G_L0, 118 RTW89_GAIN_OFFSET_6G_L1, 119 RTW89_GAIN_OFFSET_6G_M0, 120 RTW89_GAIN_OFFSET_6G_M1, 121 RTW89_GAIN_OFFSET_6G_H0, 122 RTW89_GAIN_OFFSET_6G_H1, 123 RTW89_GAIN_OFFSET_6G_UH0, 124 RTW89_GAIN_OFFSET_6G_UH1, 125 126 RTW89_GAIN_OFFSET_NR, 127 }; 128 129 enum rtw89_hci_type { 130 RTW89_HCI_TYPE_PCIE, 131 RTW89_HCI_TYPE_USB, 132 RTW89_HCI_TYPE_SDIO, 133 }; 134 135 enum rtw89_core_chip_id { 136 RTL8852A, 137 RTL8852B, 138 RTL8852BT, 139 RTL8852C, 140 RTL8851B, 141 RTL8922A, 142 }; 143 144 enum rtw89_chip_gen { 145 RTW89_CHIP_AX, 146 RTW89_CHIP_BE, 147 148 RTW89_CHIP_GEN_NUM, 149 }; 150 151 enum rtw89_cv { 152 CHIP_CAV, 153 CHIP_CBV, 154 CHIP_CCV, 155 CHIP_CDV, 156 CHIP_CEV, 157 CHIP_CFV, 158 CHIP_CV_MAX, 159 CHIP_CV_INVALID = CHIP_CV_MAX, 160 }; 161 162 enum rtw89_bacam_ver { 163 RTW89_BACAM_V0, 164 RTW89_BACAM_V1, 165 166 RTW89_BACAM_V0_EXT = 99, 167 }; 168 169 enum rtw89_core_tx_type { 170 RTW89_CORE_TX_TYPE_DATA, 171 RTW89_CORE_TX_TYPE_MGMT, 172 RTW89_CORE_TX_TYPE_FWCMD, 173 }; 174 175 enum rtw89_core_rx_type { 176 RTW89_CORE_RX_TYPE_WIFI = 0, 177 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 178 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 179 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 180 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 181 RTW89_CORE_RX_TYPE_SS2FW = 5, 182 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 183 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 184 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 185 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 186 RTW89_CORE_RX_TYPE_C2H = 10, 187 RTW89_CORE_RX_TYPE_CSI = 11, 188 RTW89_CORE_RX_TYPE_CQI = 12, 189 RTW89_CORE_RX_TYPE_H2C = 13, 190 RTW89_CORE_RX_TYPE_FWDL = 14, 191 }; 192 193 enum rtw89_txq_flags { 194 RTW89_TXQ_F_AMPDU = 0, 195 RTW89_TXQ_F_BLOCK_BA = 1, 196 RTW89_TXQ_F_FORBID_BA = 2, 197 }; 198 199 enum rtw89_net_type { 200 RTW89_NET_TYPE_NO_LINK = 0, 201 RTW89_NET_TYPE_AD_HOC = 1, 202 RTW89_NET_TYPE_INFRA = 2, 203 RTW89_NET_TYPE_AP_MODE = 3, 204 }; 205 206 enum rtw89_wifi_role { 207 RTW89_WIFI_ROLE_NONE, 208 RTW89_WIFI_ROLE_STATION, 209 RTW89_WIFI_ROLE_AP, 210 RTW89_WIFI_ROLE_AP_VLAN, 211 RTW89_WIFI_ROLE_ADHOC, 212 RTW89_WIFI_ROLE_ADHOC_MASTER, 213 RTW89_WIFI_ROLE_MESH_POINT, 214 RTW89_WIFI_ROLE_MONITOR, 215 RTW89_WIFI_ROLE_P2P_DEVICE, 216 RTW89_WIFI_ROLE_P2P_CLIENT, 217 RTW89_WIFI_ROLE_P2P_GO, 218 RTW89_WIFI_ROLE_NAN, 219 RTW89_WIFI_ROLE_MLME_MAX 220 }; 221 222 enum rtw89_upd_mode { 223 RTW89_ROLE_CREATE, 224 RTW89_ROLE_REMOVE, 225 RTW89_ROLE_TYPE_CHANGE, 226 RTW89_ROLE_INFO_CHANGE, 227 RTW89_ROLE_CON_DISCONN, 228 RTW89_ROLE_BAND_SW, 229 RTW89_ROLE_FW_RESTORE, 230 }; 231 232 enum rtw89_self_role { 233 RTW89_SELF_ROLE_CLIENT, 234 RTW89_SELF_ROLE_AP, 235 RTW89_SELF_ROLE_AP_CLIENT 236 }; 237 238 enum rtw89_msk_sO_el { 239 RTW89_NO_MSK, 240 RTW89_SMA, 241 RTW89_TMA, 242 RTW89_BSSID 243 }; 244 245 enum rtw89_sch_tx_sel { 246 RTW89_SCH_TX_SEL_ALL, 247 RTW89_SCH_TX_SEL_HIQ, 248 RTW89_SCH_TX_SEL_MG0, 249 RTW89_SCH_TX_SEL_MACID, 250 }; 251 252 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 253 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 254 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 255 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 256 */ 257 enum rtw89_add_cam_sec_mode { 258 RTW89_ADDR_CAM_SEC_NONE = 0, 259 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 260 RTW89_ADDR_CAM_SEC_NORMAL = 2, 261 RTW89_ADDR_CAM_SEC_4GROUP = 3, 262 }; 263 264 enum rtw89_sec_key_type { 265 RTW89_SEC_KEY_TYPE_NONE = 0, 266 RTW89_SEC_KEY_TYPE_WEP40 = 1, 267 RTW89_SEC_KEY_TYPE_WEP104 = 2, 268 RTW89_SEC_KEY_TYPE_TKIP = 3, 269 RTW89_SEC_KEY_TYPE_WAPI = 4, 270 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 271 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 272 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 273 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 274 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 275 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 276 }; 277 278 enum rtw89_port { 279 RTW89_PORT_0 = 0, 280 RTW89_PORT_1 = 1, 281 RTW89_PORT_2 = 2, 282 RTW89_PORT_3 = 3, 283 RTW89_PORT_4 = 4, 284 RTW89_PORT_NUM 285 }; 286 287 enum rtw89_band { 288 RTW89_BAND_2G = 0, 289 RTW89_BAND_5G = 1, 290 RTW89_BAND_6G = 2, 291 RTW89_BAND_NUM, 292 }; 293 294 enum rtw89_hw_rate { 295 RTW89_HW_RATE_CCK1 = 0x0, 296 RTW89_HW_RATE_CCK2 = 0x1, 297 RTW89_HW_RATE_CCK5_5 = 0x2, 298 RTW89_HW_RATE_CCK11 = 0x3, 299 RTW89_HW_RATE_OFDM6 = 0x4, 300 RTW89_HW_RATE_OFDM9 = 0x5, 301 RTW89_HW_RATE_OFDM12 = 0x6, 302 RTW89_HW_RATE_OFDM18 = 0x7, 303 RTW89_HW_RATE_OFDM24 = 0x8, 304 RTW89_HW_RATE_OFDM36 = 0x9, 305 RTW89_HW_RATE_OFDM48 = 0xA, 306 RTW89_HW_RATE_OFDM54 = 0xB, 307 RTW89_HW_RATE_MCS0 = 0x80, 308 RTW89_HW_RATE_MCS1 = 0x81, 309 RTW89_HW_RATE_MCS2 = 0x82, 310 RTW89_HW_RATE_MCS3 = 0x83, 311 RTW89_HW_RATE_MCS4 = 0x84, 312 RTW89_HW_RATE_MCS5 = 0x85, 313 RTW89_HW_RATE_MCS6 = 0x86, 314 RTW89_HW_RATE_MCS7 = 0x87, 315 RTW89_HW_RATE_MCS8 = 0x88, 316 RTW89_HW_RATE_MCS9 = 0x89, 317 RTW89_HW_RATE_MCS10 = 0x8A, 318 RTW89_HW_RATE_MCS11 = 0x8B, 319 RTW89_HW_RATE_MCS12 = 0x8C, 320 RTW89_HW_RATE_MCS13 = 0x8D, 321 RTW89_HW_RATE_MCS14 = 0x8E, 322 RTW89_HW_RATE_MCS15 = 0x8F, 323 RTW89_HW_RATE_MCS16 = 0x90, 324 RTW89_HW_RATE_MCS17 = 0x91, 325 RTW89_HW_RATE_MCS18 = 0x92, 326 RTW89_HW_RATE_MCS19 = 0x93, 327 RTW89_HW_RATE_MCS20 = 0x94, 328 RTW89_HW_RATE_MCS21 = 0x95, 329 RTW89_HW_RATE_MCS22 = 0x96, 330 RTW89_HW_RATE_MCS23 = 0x97, 331 RTW89_HW_RATE_MCS24 = 0x98, 332 RTW89_HW_RATE_MCS25 = 0x99, 333 RTW89_HW_RATE_MCS26 = 0x9A, 334 RTW89_HW_RATE_MCS27 = 0x9B, 335 RTW89_HW_RATE_MCS28 = 0x9C, 336 RTW89_HW_RATE_MCS29 = 0x9D, 337 RTW89_HW_RATE_MCS30 = 0x9E, 338 RTW89_HW_RATE_MCS31 = 0x9F, 339 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 340 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 341 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 342 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 343 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 344 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 345 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 346 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 347 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 348 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 349 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 350 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 351 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 352 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 353 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 354 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 355 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 356 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 357 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 358 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 359 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 360 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 361 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 362 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 363 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 364 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 365 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 366 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 367 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 368 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 369 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 370 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 371 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 372 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 373 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 374 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 375 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 376 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 377 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 378 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 379 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 380 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 381 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 382 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 383 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 384 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 385 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 386 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 387 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 388 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 389 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 390 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 391 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 392 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 393 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 394 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 395 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 396 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 397 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 398 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 399 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 400 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 401 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 402 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 403 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 404 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 405 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 406 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 407 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 408 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 409 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 410 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 411 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 412 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 413 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 414 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 415 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 416 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 417 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 418 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 419 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 420 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 421 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 422 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 423 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 424 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 425 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 426 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 427 428 RTW89_HW_RATE_V1_MCS0 = 0x100, 429 RTW89_HW_RATE_V1_MCS1 = 0x101, 430 RTW89_HW_RATE_V1_MCS2 = 0x102, 431 RTW89_HW_RATE_V1_MCS3 = 0x103, 432 RTW89_HW_RATE_V1_MCS4 = 0x104, 433 RTW89_HW_RATE_V1_MCS5 = 0x105, 434 RTW89_HW_RATE_V1_MCS6 = 0x106, 435 RTW89_HW_RATE_V1_MCS7 = 0x107, 436 RTW89_HW_RATE_V1_MCS8 = 0x108, 437 RTW89_HW_RATE_V1_MCS9 = 0x109, 438 RTW89_HW_RATE_V1_MCS10 = 0x10A, 439 RTW89_HW_RATE_V1_MCS11 = 0x10B, 440 RTW89_HW_RATE_V1_MCS12 = 0x10C, 441 RTW89_HW_RATE_V1_MCS13 = 0x10D, 442 RTW89_HW_RATE_V1_MCS14 = 0x10E, 443 RTW89_HW_RATE_V1_MCS15 = 0x10F, 444 RTW89_HW_RATE_V1_MCS16 = 0x110, 445 RTW89_HW_RATE_V1_MCS17 = 0x111, 446 RTW89_HW_RATE_V1_MCS18 = 0x112, 447 RTW89_HW_RATE_V1_MCS19 = 0x113, 448 RTW89_HW_RATE_V1_MCS20 = 0x114, 449 RTW89_HW_RATE_V1_MCS21 = 0x115, 450 RTW89_HW_RATE_V1_MCS22 = 0x116, 451 RTW89_HW_RATE_V1_MCS23 = 0x117, 452 RTW89_HW_RATE_V1_MCS24 = 0x118, 453 RTW89_HW_RATE_V1_MCS25 = 0x119, 454 RTW89_HW_RATE_V1_MCS26 = 0x11A, 455 RTW89_HW_RATE_V1_MCS27 = 0x11B, 456 RTW89_HW_RATE_V1_MCS28 = 0x11C, 457 RTW89_HW_RATE_V1_MCS29 = 0x11D, 458 RTW89_HW_RATE_V1_MCS30 = 0x11E, 459 RTW89_HW_RATE_V1_MCS31 = 0x11F, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 469 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 470 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 471 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 481 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 482 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 483 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 493 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 494 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 495 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 505 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 506 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 507 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 517 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 518 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 519 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 529 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 530 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 531 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 541 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 542 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 543 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 553 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 554 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 555 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 570 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 571 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 583 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 584 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 585 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 597 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 598 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 599 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 611 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 612 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 613 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 614 615 RTW89_HW_RATE_NR, 616 RTW89_HW_RATE_INVAL, 617 618 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 619 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 620 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 621 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 622 }; 623 624 /* 2G channels, 625 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 626 */ 627 #define RTW89_2G_CH_NUM 14 628 629 /* 5G channels, 630 * 36, 38, 40, 42, 44, 46, 48, 50, 631 * 52, 54, 56, 58, 60, 62, 64, 632 * 100, 102, 104, 106, 108, 110, 112, 114, 633 * 116, 118, 120, 122, 124, 126, 128, 130, 634 * 132, 134, 136, 138, 140, 142, 144, 635 * 149, 151, 153, 155, 157, 159, 161, 163, 636 * 165, 167, 169, 171, 173, 175, 177 637 */ 638 #define RTW89_5G_CH_NUM 53 639 640 /* 6G channels, 641 * 1, 3, 5, 7, 9, 11, 13, 15, 642 * 17, 19, 21, 23, 25, 27, 29, 33, 643 * 35, 37, 39, 41, 43, 45, 47, 49, 644 * 51, 53, 55, 57, 59, 61, 65, 67, 645 * 69, 71, 73, 75, 77, 79, 81, 83, 646 * 85, 87, 89, 91, 93, 97, 99, 101, 647 * 103, 105, 107, 109, 111, 113, 115, 117, 648 * 119, 121, 123, 125, 129, 131, 133, 135, 649 * 137, 139, 141, 143, 145, 147, 149, 151, 650 * 153, 155, 157, 161, 163, 165, 167, 169, 651 * 171, 173, 175, 177, 179, 181, 183, 185, 652 * 187, 189, 193, 195, 197, 199, 201, 203, 653 * 205, 207, 209, 211, 213, 215, 217, 219, 654 * 221, 225, 227, 229, 231, 233, 235, 237, 655 * 239, 241, 243, 245, 247, 249, 251, 253, 656 */ 657 #define RTW89_6G_CH_NUM 120 658 659 enum rtw89_rate_section { 660 RTW89_RS_CCK, 661 RTW89_RS_OFDM, 662 RTW89_RS_MCS, /* for HT/VHT/HE */ 663 RTW89_RS_HEDCM, 664 RTW89_RS_OFFSET, 665 RTW89_RS_NUM, 666 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 667 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 668 }; 669 670 enum rtw89_rate_offset_indexes { 671 RTW89_RATE_OFFSET_HE, 672 RTW89_RATE_OFFSET_VHT, 673 RTW89_RATE_OFFSET_HT, 674 RTW89_RATE_OFFSET_OFDM, 675 RTW89_RATE_OFFSET_CCK, 676 RTW89_RATE_OFFSET_DLRU_EHT, 677 RTW89_RATE_OFFSET_DLRU_HE, 678 RTW89_RATE_OFFSET_EHT, 679 __RTW89_RATE_OFFSET_NUM, 680 681 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 682 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 683 }; 684 685 enum rtw89_rate_num { 686 RTW89_RATE_CCK_NUM = 4, 687 RTW89_RATE_OFDM_NUM = 8, 688 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 689 690 RTW89_RATE_MCS_NUM_AX = 12, 691 RTW89_RATE_MCS_NUM_BE = 16, 692 __RTW89_RATE_MCS_NUM = 16, 693 }; 694 695 enum rtw89_nss { 696 RTW89_NSS_1 = 0, 697 RTW89_NSS_2 = 1, 698 /* HE DCM only support 1ss and 2ss */ 699 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 700 RTW89_NSS_3 = 2, 701 RTW89_NSS_4 = 3, 702 RTW89_NSS_NUM, 703 }; 704 705 enum rtw89_ntx { 706 RTW89_1TX = 0, 707 RTW89_2TX = 1, 708 RTW89_NTX_NUM, 709 }; 710 711 enum rtw89_beamforming_type { 712 RTW89_NONBF = 0, 713 RTW89_BF = 1, 714 RTW89_BF_NUM, 715 }; 716 717 enum rtw89_ofdma_type { 718 RTW89_NON_OFDMA = 0, 719 RTW89_OFDMA = 1, 720 RTW89_OFDMA_NUM, 721 }; 722 723 /* neither insert new in the middle, nor change any given definition */ 724 enum rtw89_regulation_type { 725 RTW89_WW = 0, 726 RTW89_ETSI = 1, 727 RTW89_FCC = 2, 728 RTW89_MKK = 3, 729 RTW89_NA = 4, 730 RTW89_IC = 5, 731 RTW89_KCC = 6, 732 RTW89_ACMA = 7, 733 RTW89_NCC = 8, 734 RTW89_MEXICO = 9, 735 RTW89_CHILE = 10, 736 RTW89_UKRAINE = 11, 737 RTW89_CN = 12, 738 RTW89_QATAR = 13, 739 RTW89_UK = 14, 740 RTW89_THAILAND = 15, 741 RTW89_REGD_NUM, 742 }; 743 744 enum rtw89_reg_6ghz_power { 745 RTW89_REG_6GHZ_POWER_VLP = 0, 746 RTW89_REG_6GHZ_POWER_LPI = 1, 747 RTW89_REG_6GHZ_POWER_STD = 2, 748 749 NUM_OF_RTW89_REG_6GHZ_POWER, 750 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 751 }; 752 753 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 754 755 /* calculate based on ieee80211 Transmit Power Envelope */ 756 struct rtw89_reg_6ghz_tpe { 757 bool valid; 758 s8 constraint; /* unit: dBm */ 759 }; 760 761 enum rtw89_fw_pkt_ofld_type { 762 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 763 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 764 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 765 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 766 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 767 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 768 RTW89_PKT_OFLD_TYPE_NDP = 6, 769 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 770 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 771 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 772 RTW89_PKT_OFLD_TYPE_NUM, 773 }; 774 775 struct rtw89_txpwr_byrate { 776 s8 cck[RTW89_RATE_CCK_NUM]; 777 s8 ofdm[RTW89_RATE_OFDM_NUM]; 778 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 779 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 780 s8 offset[__RTW89_RATE_OFFSET_NUM]; 781 s8 trap; 782 }; 783 784 struct rtw89_rate_desc { 785 enum rtw89_nss nss; 786 enum rtw89_rate_section rs; 787 enum rtw89_ofdma_type ofdma; 788 u8 idx; 789 }; 790 791 #define PHY_STS_HDR_LEN 8 792 #define RF_PATH_MAX 4 793 #define RTW89_MAX_PPDU_CNT 8 794 struct rtw89_rx_phy_ppdu { 795 void *buf; 796 u32 len; 797 u8 rssi_avg; 798 u8 rssi[RF_PATH_MAX]; 799 u8 mac_id; 800 u8 chan_idx; 801 u8 phy_idx; 802 u8 ie; 803 u16 rate; 804 u8 rpl_avg; 805 u8 rpl_path[RF_PATH_MAX]; 806 u8 rpl_fd[RF_PATH_MAX]; 807 u8 bw_idx; 808 u8 rx_path_en; 809 struct { 810 bool has; 811 u8 avg_snr; 812 u8 evm_max; 813 u8 evm_min; 814 } ofdm; 815 bool has_data; 816 bool has_bcn; 817 bool ldpc; 818 bool stbc; 819 bool to_self; 820 bool valid; 821 bool hdr_2_en; 822 }; 823 824 enum rtw89_mac_idx { 825 RTW89_MAC_0 = 0, 826 RTW89_MAC_1 = 1, 827 RTW89_MAC_NUM, 828 }; 829 830 enum rtw89_phy_idx { 831 RTW89_PHY_0 = 0, 832 RTW89_PHY_1 = 1, 833 RTW89_PHY_NUM, 834 }; 835 836 #define __RTW89_MLD_MAX_LINK_NUM 2 837 #define RTW89_MLD_NON_STA_LINK_NUM 1 838 839 enum rtw89_chanctx_idx { 840 RTW89_CHANCTX_0 = 0, 841 RTW89_CHANCTX_1 = 1, 842 843 NUM_OF_RTW89_CHANCTX, 844 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 845 }; 846 847 enum rtw89_rf_path { 848 RF_PATH_A = 0, 849 RF_PATH_B = 1, 850 RF_PATH_C = 2, 851 RF_PATH_D = 3, 852 RF_PATH_AB, 853 RF_PATH_AC, 854 RF_PATH_AD, 855 RF_PATH_BC, 856 RF_PATH_BD, 857 RF_PATH_CD, 858 RF_PATH_ABC, 859 RF_PATH_ABD, 860 RF_PATH_ACD, 861 RF_PATH_BCD, 862 RF_PATH_ABCD, 863 }; 864 865 enum rtw89_rf_path_bit { 866 RF_A = BIT(0), 867 RF_B = BIT(1), 868 RF_C = BIT(2), 869 RF_D = BIT(3), 870 871 RF_AB = (RF_A | RF_B), 872 RF_AC = (RF_A | RF_C), 873 RF_AD = (RF_A | RF_D), 874 RF_BC = (RF_B | RF_C), 875 RF_BD = (RF_B | RF_D), 876 RF_CD = (RF_C | RF_D), 877 878 RF_ABC = (RF_A | RF_B | RF_C), 879 RF_ABD = (RF_A | RF_B | RF_D), 880 RF_ACD = (RF_A | RF_C | RF_D), 881 RF_BCD = (RF_B | RF_C | RF_D), 882 883 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 884 }; 885 886 enum rtw89_bandwidth { 887 RTW89_CHANNEL_WIDTH_20 = 0, 888 RTW89_CHANNEL_WIDTH_40 = 1, 889 RTW89_CHANNEL_WIDTH_80 = 2, 890 RTW89_CHANNEL_WIDTH_160 = 3, 891 RTW89_CHANNEL_WIDTH_320 = 4, 892 893 /* keep index order above */ 894 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 895 896 RTW89_CHANNEL_WIDTH_80_80 = 5, 897 RTW89_CHANNEL_WIDTH_5 = 6, 898 RTW89_CHANNEL_WIDTH_10 = 7, 899 }; 900 901 enum rtw89_ps_mode { 902 RTW89_PS_MODE_NONE = 0, 903 RTW89_PS_MODE_RFOFF = 1, 904 RTW89_PS_MODE_CLK_GATED = 2, 905 RTW89_PS_MODE_PWR_GATED = 3, 906 }; 907 908 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 909 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 910 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 911 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 912 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 913 914 enum rtw89_pe_duration { 915 RTW89_PE_DURATION_0 = 0, 916 RTW89_PE_DURATION_8 = 1, 917 RTW89_PE_DURATION_16 = 2, 918 RTW89_PE_DURATION_16_20 = 3, 919 }; 920 921 enum rtw89_ru_bandwidth { 922 RTW89_RU26 = 0, 923 RTW89_RU52 = 1, 924 RTW89_RU106 = 2, 925 RTW89_RU52_26 = 3, 926 RTW89_RU106_26 = 4, 927 RTW89_RU_NUM, 928 }; 929 930 enum rtw89_sc_offset { 931 RTW89_SC_DONT_CARE = 0, 932 RTW89_SC_20_UPPER = 1, 933 RTW89_SC_20_LOWER = 2, 934 RTW89_SC_20_UPMOST = 3, 935 RTW89_SC_20_LOWEST = 4, 936 RTW89_SC_20_UP2X = 5, 937 RTW89_SC_20_LOW2X = 6, 938 RTW89_SC_20_UP3X = 7, 939 RTW89_SC_20_LOW3X = 8, 940 RTW89_SC_40_UPPER = 9, 941 RTW89_SC_40_LOWER = 10, 942 }; 943 944 /* only mgd features can be added to the enum */ 945 enum rtw89_wow_flags { 946 RTW89_WOW_FLAG_EN_MAGIC_PKT, 947 RTW89_WOW_FLAG_EN_REKEY_PKT, 948 RTW89_WOW_FLAG_EN_DISCONNECT, 949 RTW89_WOW_FLAG_EN_PATTERN, 950 RTW89_WOW_FLAG_NUM, 951 }; 952 953 struct rtw89_chan { 954 u8 channel; 955 u8 primary_channel; 956 enum rtw89_band band_type; 957 enum rtw89_bandwidth band_width; 958 959 /* The follow-up are derived from the above. We must ensure that it 960 * is assigned correctly in rtw89_chan_create() if new one is added. 961 */ 962 u32 freq; 963 enum rtw89_subband subband_type; 964 enum rtw89_sc_offset pri_ch_idx; 965 u8 pri_sb_idx; 966 }; 967 968 struct rtw89_chan_rcd { 969 u8 prev_primary_channel; 970 enum rtw89_band prev_band_type; 971 bool band_changed; 972 }; 973 974 struct rtw89_channel_help_params { 975 u32 tx_en; 976 }; 977 978 struct rtw89_port_reg { 979 u32 port_cfg; 980 u32 tbtt_prohib; 981 u32 bcn_area; 982 u32 bcn_early; 983 u32 tbtt_early; 984 u32 tbtt_agg; 985 u32 bcn_space; 986 u32 bcn_forcetx; 987 u32 bcn_err_cnt; 988 u32 bcn_err_flag; 989 u32 dtim_ctrl; 990 u32 tbtt_shift; 991 u32 bcn_cnt_tmr; 992 u32 tsftr_l; 993 u32 tsftr_h; 994 u32 md_tsft; 995 u32 bss_color; 996 u32 mbssid; 997 u32 mbssid_drop; 998 u32 tsf_sync; 999 u32 ptcl_dbg; 1000 u32 ptcl_dbg_info; 1001 u32 bcn_drop_all; 1002 u32 hiq_win[RTW89_PORT_NUM]; 1003 }; 1004 1005 struct rtw89_txwd_body { 1006 __le32 dword0; 1007 __le32 dword1; 1008 __le32 dword2; 1009 __le32 dword3; 1010 __le32 dword4; 1011 __le32 dword5; 1012 } __packed; 1013 1014 struct rtw89_txwd_body_v1 { 1015 __le32 dword0; 1016 __le32 dword1; 1017 __le32 dword2; 1018 __le32 dword3; 1019 __le32 dword4; 1020 __le32 dword5; 1021 __le32 dword6; 1022 __le32 dword7; 1023 } __packed; 1024 1025 struct rtw89_txwd_body_v2 { 1026 __le32 dword0; 1027 __le32 dword1; 1028 __le32 dword2; 1029 __le32 dword3; 1030 __le32 dword4; 1031 __le32 dword5; 1032 __le32 dword6; 1033 __le32 dword7; 1034 } __packed; 1035 1036 struct rtw89_txwd_info { 1037 __le32 dword0; 1038 __le32 dword1; 1039 __le32 dword2; 1040 __le32 dword3; 1041 __le32 dword4; 1042 __le32 dword5; 1043 } __packed; 1044 1045 struct rtw89_txwd_info_v2 { 1046 __le32 dword0; 1047 __le32 dword1; 1048 __le32 dword2; 1049 __le32 dword3; 1050 __le32 dword4; 1051 __le32 dword5; 1052 __le32 dword6; 1053 __le32 dword7; 1054 } __packed; 1055 1056 struct rtw89_rx_desc_info { 1057 u16 pkt_size; 1058 u8 pkt_type; 1059 u8 drv_info_size; 1060 u8 phy_rpt_size; 1061 u8 hdr_cnv_size; 1062 u8 shift; 1063 u8 wl_hd_iv_len; 1064 bool long_rxdesc; 1065 bool bb_sel; 1066 bool mac_info_valid; 1067 u16 data_rate; 1068 u8 gi_ltf; 1069 u8 bw; 1070 u32 free_run_cnt; 1071 u8 user_id; 1072 bool sr_en; 1073 u8 ppdu_cnt; 1074 u8 ppdu_type; 1075 bool icv_err; 1076 bool crc32_err; 1077 bool hw_dec; 1078 bool sw_dec; 1079 bool addr1_match; 1080 u8 frag; 1081 u16 seq; 1082 u8 frame_type; 1083 u8 rx_pl_id; 1084 bool addr_cam_valid; 1085 u8 addr_cam_id; 1086 u8 sec_cam_id; 1087 u8 mac_id; 1088 u16 offset; 1089 u16 rxd_len; 1090 bool ready; 1091 u16 rssi; 1092 }; 1093 1094 struct rtw89_rxdesc_short { 1095 __le32 dword0; 1096 __le32 dword1; 1097 __le32 dword2; 1098 __le32 dword3; 1099 } __packed; 1100 1101 struct rtw89_rxdesc_short_v2 { 1102 __le32 dword0; 1103 __le32 dword1; 1104 __le32 dword2; 1105 __le32 dword3; 1106 __le32 dword4; 1107 __le32 dword5; 1108 } __packed; 1109 1110 struct rtw89_rxdesc_long { 1111 __le32 dword0; 1112 __le32 dword1; 1113 __le32 dword2; 1114 __le32 dword3; 1115 __le32 dword4; 1116 __le32 dword5; 1117 __le32 dword6; 1118 __le32 dword7; 1119 } __packed; 1120 1121 struct rtw89_rxdesc_long_v2 { 1122 __le32 dword0; 1123 __le32 dword1; 1124 __le32 dword2; 1125 __le32 dword3; 1126 __le32 dword4; 1127 __le32 dword5; 1128 __le32 dword6; 1129 __le32 dword7; 1130 __le32 dword8; 1131 __le32 dword9; 1132 } __packed; 1133 1134 struct rtw89_rxdesc_phy_rpt_v2 { 1135 __le32 dword0; 1136 __le32 dword1; 1137 } __packed; 1138 1139 struct rtw89_tx_desc_info { 1140 u16 pkt_size; 1141 u8 wp_offset; 1142 u8 mac_id; 1143 u8 qsel; 1144 u8 ch_dma; 1145 u8 hdr_llc_len; 1146 bool is_bmc; 1147 bool en_wd_info; 1148 bool wd_page; 1149 bool use_rate; 1150 bool dis_data_fb; 1151 bool tid_indicate; 1152 bool agg_en; 1153 bool bk; 1154 u8 ampdu_density; 1155 u8 ampdu_num; 1156 bool sec_en; 1157 u8 addr_info_nr; 1158 u8 sec_keyid; 1159 u8 sec_type; 1160 u8 sec_cam_idx; 1161 u8 sec_seq[6]; 1162 u16 data_rate; 1163 u16 data_retry_lowest_rate; 1164 bool fw_dl; 1165 u16 seq; 1166 bool a_ctrl_bsr; 1167 u8 hw_ssn_sel; 1168 #define RTW89_MGMT_HW_SSN_SEL 1 1169 u8 hw_seq_mode; 1170 #define RTW89_MGMT_HW_SEQ_MODE 1 1171 bool hiq; 1172 u8 port; 1173 bool er_cap; 1174 bool stbc; 1175 bool ldpc; 1176 bool upd_wlan_hdr; 1177 bool mlo; 1178 bool sw_mld; 1179 }; 1180 1181 struct rtw89_core_tx_request { 1182 enum rtw89_core_tx_type tx_type; 1183 1184 struct sk_buff *skb; 1185 struct ieee80211_vif *vif; 1186 struct ieee80211_sta *sta; 1187 struct rtw89_vif_link *rtwvif_link; 1188 struct rtw89_sta_link *rtwsta_link; 1189 struct rtw89_tx_desc_info desc_info; 1190 }; 1191 1192 struct rtw89_txq { 1193 struct list_head list; 1194 unsigned long flags; 1195 int wait_cnt; 1196 }; 1197 1198 struct rtw89_mac_ax_gnt { 1199 u8 gnt_bt_sw_en; 1200 u8 gnt_bt; 1201 u8 gnt_wl_sw_en; 1202 u8 gnt_wl; 1203 } __packed; 1204 1205 struct rtw89_mac_ax_wl_act { 1206 u8 wlan_act_en; 1207 u8 wlan_act; 1208 }; 1209 1210 #define RTW89_MAC_AX_COEX_GNT_NR 2 1211 struct rtw89_mac_ax_coex_gnt { 1212 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1213 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1214 }; 1215 1216 enum rtw89_btc_ncnt { 1217 BTC_NCNT_POWER_ON = 0x0, 1218 BTC_NCNT_POWER_OFF, 1219 BTC_NCNT_INIT_COEX, 1220 BTC_NCNT_SCAN_START, 1221 BTC_NCNT_SCAN_FINISH, 1222 BTC_NCNT_SPECIAL_PACKET, 1223 BTC_NCNT_SWITCH_BAND, 1224 BTC_NCNT_RFK_TIMEOUT, 1225 BTC_NCNT_SHOW_COEX_INFO, 1226 BTC_NCNT_ROLE_INFO, 1227 BTC_NCNT_CONTROL, 1228 BTC_NCNT_RADIO_STATE, 1229 BTC_NCNT_CUSTOMERIZE, 1230 BTC_NCNT_WL_RFK, 1231 BTC_NCNT_WL_STA, 1232 BTC_NCNT_WL_STA_LAST, 1233 BTC_NCNT_FWINFO, 1234 BTC_NCNT_TIMER, 1235 BTC_NCNT_SWITCH_CHBW, 1236 BTC_NCNT_RESUME_DL_FW, 1237 BTC_NCNT_COUNTRYCODE, 1238 BTC_NCNT_NUM, 1239 }; 1240 1241 enum rtw89_btc_btinfo { 1242 BTC_BTINFO_L0 = 0, 1243 BTC_BTINFO_L1, 1244 BTC_BTINFO_L2, 1245 BTC_BTINFO_L3, 1246 BTC_BTINFO_H0, 1247 BTC_BTINFO_H1, 1248 BTC_BTINFO_H2, 1249 BTC_BTINFO_H3, 1250 BTC_BTINFO_MAX 1251 }; 1252 1253 enum rtw89_btc_dcnt { 1254 BTC_DCNT_RUN = 0x0, 1255 BTC_DCNT_CX_RUNINFO, 1256 BTC_DCNT_RPT, 1257 BTC_DCNT_RPT_HANG, 1258 BTC_DCNT_CYCLE, 1259 BTC_DCNT_CYCLE_HANG, 1260 BTC_DCNT_W1, 1261 BTC_DCNT_W1_HANG, 1262 BTC_DCNT_B1, 1263 BTC_DCNT_B1_HANG, 1264 BTC_DCNT_TDMA_NONSYNC, 1265 BTC_DCNT_SLOT_NONSYNC, 1266 BTC_DCNT_BTCNT_HANG, 1267 BTC_DCNT_BTTX_HANG, 1268 BTC_DCNT_WL_SLOT_DRIFT, 1269 BTC_DCNT_WL_STA_LAST, 1270 BTC_DCNT_BT_SLOT_DRIFT, 1271 BTC_DCNT_BT_SLOT_FLOOD, 1272 BTC_DCNT_FDDT_TRIG, 1273 BTC_DCNT_E2G, 1274 BTC_DCNT_E2G_HANG, 1275 BTC_DCNT_WL_FW_VER_MATCH, 1276 BTC_DCNT_NULL_TX_FAIL, 1277 BTC_DCNT_WL_STA_NTFY, 1278 BTC_DCNT_NUM, 1279 }; 1280 1281 enum rtw89_btc_wl_state_cnt { 1282 BTC_WCNT_SCANAP = 0x0, 1283 BTC_WCNT_DHCP, 1284 BTC_WCNT_EAPOL, 1285 BTC_WCNT_ARP, 1286 BTC_WCNT_SCBDUPDATE, 1287 BTC_WCNT_RFK_REQ, 1288 BTC_WCNT_RFK_GO, 1289 BTC_WCNT_RFK_REJECT, 1290 BTC_WCNT_RFK_TIMEOUT, 1291 BTC_WCNT_CH_UPDATE, 1292 BTC_WCNT_DBCC_ALL_2G, 1293 BTC_WCNT_DBCC_CHG, 1294 BTC_WCNT_RX_OK_LAST, 1295 BTC_WCNT_RX_OK_LAST2S, 1296 BTC_WCNT_RX_ERR_LAST, 1297 BTC_WCNT_RX_ERR_LAST2S, 1298 BTC_WCNT_RX_LAST, 1299 BTC_WCNT_NUM 1300 }; 1301 1302 enum rtw89_btc_bt_state_cnt { 1303 BTC_BCNT_RETRY = 0x0, 1304 BTC_BCNT_REINIT, 1305 BTC_BCNT_REENABLE, 1306 BTC_BCNT_SCBDREAD, 1307 BTC_BCNT_RELINK, 1308 BTC_BCNT_IGNOWL, 1309 BTC_BCNT_INQPAG, 1310 BTC_BCNT_INQ, 1311 BTC_BCNT_PAGE, 1312 BTC_BCNT_ROLESW, 1313 BTC_BCNT_AFH, 1314 BTC_BCNT_INFOUPDATE, 1315 BTC_BCNT_INFOSAME, 1316 BTC_BCNT_SCBDUPDATE, 1317 BTC_BCNT_HIPRI_TX, 1318 BTC_BCNT_HIPRI_RX, 1319 BTC_BCNT_LOPRI_TX, 1320 BTC_BCNT_LOPRI_RX, 1321 BTC_BCNT_POLUT, 1322 BTC_BCNT_POLUT_NOW, 1323 BTC_BCNT_POLUT_DIFF, 1324 BTC_BCNT_RATECHG, 1325 BTC_BCNT_NUM, 1326 }; 1327 1328 enum rtw89_btc_bt_profile { 1329 BTC_BT_NOPROFILE = 0, 1330 BTC_BT_HFP = BIT(0), 1331 BTC_BT_HID = BIT(1), 1332 BTC_BT_A2DP = BIT(2), 1333 BTC_BT_PAN = BIT(3), 1334 BTC_PROFILE_MAX = 4, 1335 }; 1336 1337 struct rtw89_btc_ant_info { 1338 u8 type; /* shared, dedicated */ 1339 u8 num; 1340 u8 isolation; 1341 1342 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1343 u8 diversity: 1; 1344 u8 btg_pos: 2; 1345 u8 stream_cnt: 4; 1346 }; 1347 1348 struct rtw89_btc_ant_info_v7 { 1349 u8 type; /* shared, dedicated(non-shared) */ 1350 u8 num; /* antenna count */ 1351 u8 isolation; 1352 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1353 1354 u8 diversity; /* only for wifi use 1-antenna */ 1355 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1356 u8 stream_cnt; /* spatial_stream count */ 1357 u8 rsvd; 1358 } __packed; 1359 1360 enum rtw89_tfc_dir { 1361 RTW89_TFC_UL, 1362 RTW89_TFC_DL, 1363 }; 1364 1365 struct rtw89_btc_wl_smap { 1366 u32 busy: 1; 1367 u32 scan: 1; 1368 u32 connecting: 1; 1369 u32 roaming: 1; 1370 u32 dbccing: 1; 1371 u32 _4way: 1; 1372 u32 rf_off: 1; 1373 u32 lps: 2; 1374 u32 ips: 1; 1375 u32 init_ok: 1; 1376 u32 traffic_dir : 2; 1377 u32 rf_off_pre: 1; 1378 u32 lps_pre: 2; 1379 u32 lps_exiting: 1; 1380 u32 emlsr: 1; 1381 }; 1382 1383 enum rtw89_tfc_lv { 1384 RTW89_TFC_IDLE, 1385 RTW89_TFC_ULTRA_LOW, 1386 RTW89_TFC_LOW, 1387 RTW89_TFC_MID, 1388 RTW89_TFC_HIGH, 1389 }; 1390 1391 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1392 DECLARE_EWMA(tp, 10, 2); 1393 1394 struct rtw89_traffic_stats { 1395 /* units in bytes */ 1396 u64 tx_unicast; 1397 u64 rx_unicast; 1398 u32 tx_avg_len; 1399 u32 rx_avg_len; 1400 1401 /* count for packets */ 1402 u64 tx_cnt; 1403 u64 rx_cnt; 1404 1405 /* units in Mbps */ 1406 u32 tx_throughput; 1407 u32 rx_throughput; 1408 u32 tx_throughput_raw; 1409 u32 rx_throughput_raw; 1410 1411 u32 rx_tf_acc; 1412 u32 rx_tf_periodic; 1413 1414 enum rtw89_tfc_lv tx_tfc_lv; 1415 enum rtw89_tfc_lv rx_tfc_lv; 1416 struct ewma_tp tx_ewma_tp; 1417 struct ewma_tp rx_ewma_tp; 1418 1419 u16 tx_rate; 1420 u16 rx_rate; 1421 }; 1422 1423 struct rtw89_btc_chdef { 1424 u8 center_ch; 1425 u8 band; 1426 u8 chan; 1427 enum rtw89_sc_offset offset; 1428 enum rtw89_bandwidth bw; 1429 }; 1430 1431 struct rtw89_btc_statistic { 1432 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1433 struct rtw89_traffic_stats traffic; 1434 }; 1435 1436 #define BTC_WL_RSSI_THMAX 4 1437 1438 struct rtw89_btc_wl_link_info { 1439 struct rtw89_btc_chdef chdef; 1440 struct rtw89_btc_statistic stat; 1441 enum rtw89_tfc_dir dir; 1442 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1443 u8 mac_addr[ETH_ALEN]; 1444 u8 busy; 1445 u8 ch; 1446 u8 bw; 1447 u8 band; 1448 u8 role; 1449 u8 pid; 1450 u8 phy; 1451 u8 dtim_period; 1452 u8 mode; 1453 u8 tx_1ss_limit; 1454 1455 u8 mac_id; 1456 u8 tx_retry; 1457 1458 u32 bcn_period; 1459 u32 busy_t; 1460 u32 tx_time; 1461 u32 client_cnt; 1462 u32 rx_rate_drop_cnt; 1463 u32 noa_duration; 1464 1465 u32 active: 1; 1466 u32 noa: 1; 1467 u32 client_ps: 1; 1468 u32 connected: 2; 1469 }; 1470 1471 union rtw89_btc_wl_state_map { 1472 u32 val; 1473 struct rtw89_btc_wl_smap map; 1474 }; 1475 1476 struct rtw89_btc_bt_hfp_desc { 1477 u32 exist: 1; 1478 u32 type: 2; 1479 u32 rsvd: 29; 1480 }; 1481 1482 struct rtw89_btc_bt_hid_desc { 1483 u32 exist: 1; 1484 u32 slot_info: 2; 1485 u32 pair_cnt: 2; 1486 u32 type: 8; 1487 u32 rsvd: 19; 1488 }; 1489 1490 struct rtw89_btc_bt_a2dp_desc { 1491 u8 exist: 1; 1492 u8 exist_last: 1; 1493 u8 play_latency: 1; 1494 u8 type: 3; 1495 u8 active: 1; 1496 u8 sink: 1; 1497 u32 handle_update: 1; 1498 u32 devinfo_query: 1; 1499 u32 no_empty_streak_2s: 8; 1500 u32 no_empty_streak_max: 8; 1501 u32 rsvd: 6; 1502 1503 u8 bitpool; 1504 u16 vendor_id; 1505 u32 device_name; 1506 u32 flush_time; 1507 }; 1508 1509 struct rtw89_btc_bt_pan_desc { 1510 u32 exist: 1; 1511 u32 type: 1; 1512 u32 active: 1; 1513 u32 rsvd: 29; 1514 }; 1515 1516 struct rtw89_btc_bt_rfk_info { 1517 u32 run: 1; 1518 u32 req: 1; 1519 u32 timeout: 1; 1520 u32 rsvd: 29; 1521 }; 1522 1523 union rtw89_btc_bt_rfk_info_map { 1524 u32 val; 1525 struct rtw89_btc_bt_rfk_info map; 1526 }; 1527 1528 struct rtw89_btc_bt_ver_info { 1529 u32 fw_coex; /* match with which coex_ver */ 1530 u32 fw; 1531 }; 1532 1533 struct rtw89_btc_bool_sta_chg { 1534 u32 now: 1; 1535 u32 last: 1; 1536 u32 remain: 1; 1537 u32 srvd: 29; 1538 }; 1539 1540 struct rtw89_btc_u8_sta_chg { 1541 u8 now; 1542 u8 last; 1543 u8 remain; 1544 u8 rsvd; 1545 }; 1546 1547 struct rtw89_btc_wl_scan_info { 1548 u8 band[RTW89_PHY_NUM]; 1549 u8 phy_map; 1550 u8 rsvd; 1551 }; 1552 1553 struct rtw89_btc_wl_dbcc_info { 1554 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1555 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1556 u8 real_band[RTW89_PHY_NUM]; 1557 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1558 }; 1559 1560 struct rtw89_btc_wl_active_role { 1561 u8 connected: 1; 1562 u8 pid: 3; 1563 u8 phy: 1; 1564 u8 noa: 1; 1565 u8 band: 2; 1566 1567 u8 client_ps: 1; 1568 u8 bw: 7; 1569 1570 u8 role; 1571 u8 ch; 1572 1573 u16 tx_lvl; 1574 u16 rx_lvl; 1575 u16 tx_rate; 1576 u16 rx_rate; 1577 }; 1578 1579 struct rtw89_btc_wl_active_role_v1 { 1580 u8 connected: 1; 1581 u8 pid: 3; 1582 u8 phy: 1; 1583 u8 noa: 1; 1584 u8 band: 2; 1585 1586 u8 client_ps: 1; 1587 u8 bw: 7; 1588 1589 u8 role; 1590 u8 ch; 1591 1592 u16 tx_lvl; 1593 u16 rx_lvl; 1594 u16 tx_rate; 1595 u16 rx_rate; 1596 1597 u32 noa_duration; /* ms */ 1598 }; 1599 1600 struct rtw89_btc_wl_active_role_v2 { 1601 u8 connected: 1; 1602 u8 pid: 3; 1603 u8 phy: 1; 1604 u8 noa: 1; 1605 u8 band: 2; 1606 1607 u8 client_ps: 1; 1608 u8 bw: 7; 1609 1610 u8 role; 1611 u8 ch; 1612 1613 u32 noa_duration; /* ms */ 1614 }; 1615 1616 struct rtw89_btc_wl_active_role_v7 { 1617 u8 connected; 1618 u8 pid; 1619 u8 phy; 1620 u8 noa; 1621 1622 u8 band; 1623 u8 client_ps; 1624 u8 bw; 1625 u8 role; 1626 1627 u8 ch; 1628 u8 noa_dur; 1629 u8 client_cnt; 1630 u8 rsvd2; 1631 } __packed; 1632 1633 struct rtw89_btc_wl_role_info_bpos { 1634 u16 none: 1; 1635 u16 station: 1; 1636 u16 ap: 1; 1637 u16 vap: 1; 1638 u16 adhoc: 1; 1639 u16 adhoc_master: 1; 1640 u16 mesh: 1; 1641 u16 moniter: 1; 1642 u16 p2p_device: 1; 1643 u16 p2p_gc: 1; 1644 u16 p2p_go: 1; 1645 u16 nan: 1; 1646 }; 1647 1648 struct rtw89_btc_wl_scc_ctrl { 1649 u8 null_role1; 1650 u8 null_role2; 1651 u8 ebt_null; /* if tx null at EBT slot */ 1652 }; 1653 1654 union rtw89_btc_wl_role_info_map { 1655 u16 val; 1656 struct rtw89_btc_wl_role_info_bpos role; 1657 }; 1658 1659 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1660 u8 connect_cnt; 1661 u8 link_mode; 1662 union rtw89_btc_wl_role_info_map role_map; 1663 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1664 }; 1665 1666 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1667 u8 connect_cnt; 1668 u8 link_mode; 1669 union rtw89_btc_wl_role_info_map role_map; 1670 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1671 u32 mrole_type; /* btc_wl_mrole_type */ 1672 u32 mrole_noa_duration; /* ms */ 1673 1674 u32 dbcc_en: 1; 1675 u32 dbcc_chg: 1; 1676 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1677 u32 link_mode_chg: 1; 1678 u32 rsvd: 27; 1679 }; 1680 1681 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1682 u8 connect_cnt; 1683 u8 link_mode; 1684 union rtw89_btc_wl_role_info_map role_map; 1685 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1686 u32 mrole_type; /* btc_wl_mrole_type */ 1687 u32 mrole_noa_duration; /* ms */ 1688 1689 u32 dbcc_en: 1; 1690 u32 dbcc_chg: 1; 1691 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1692 u32 link_mode_chg: 1; 1693 u32 rsvd: 27; 1694 }; 1695 1696 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1697 u8 connected; 1698 u8 pid; 1699 u8 phy; 1700 u8 noa; 1701 1702 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1703 u8 active; /* 0:rlink is under doze */ 1704 u8 bw; /* enum channel_width */ 1705 u8 role; /*enum role_type */ 1706 1707 u8 ch; 1708 u8 noa_dur; /* ms */ 1709 u8 client_cnt; /* for Role = P2P-Go/AP */ 1710 u8 mode; /* wifi protocol */ 1711 } __packed; 1712 1713 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1714 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1715 u8 connect_cnt; 1716 u8 link_mode; 1717 u8 link_mode_chg; 1718 u8 p2p_2g; 1719 1720 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1721 1722 u32 role_map; 1723 u32 mrole_type; /* btc_wl_mrole_type */ 1724 u32 mrole_noa_duration; /* ms */ 1725 u32 dbcc_en; 1726 u32 dbcc_chg; 1727 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1728 } __packed; 1729 1730 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1731 u8 connect_cnt; 1732 u8 link_mode; 1733 u8 link_mode_chg; 1734 u8 p2p_2g; 1735 1736 u8 pta_req_band; 1737 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1738 u8 dbcc_chg; 1739 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1740 1741 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1742 1743 u32 role_map; 1744 u32 mrole_type; /* btc_wl_mrole_type */ 1745 u32 mrole_noa_duration; /* ms */ 1746 } __packed; 1747 1748 struct rtw89_btc_wl_ver_info { 1749 u32 fw_coex; /* match with which coex_ver */ 1750 u32 fw; 1751 u32 mac; 1752 u32 bb; 1753 u32 rf; 1754 }; 1755 1756 struct rtw89_btc_wl_afh_info { 1757 u8 en; 1758 u8 ch; 1759 u8 bw; 1760 u8 rsvd; 1761 } __packed; 1762 1763 struct rtw89_btc_wl_rfk_info { 1764 u32 state: 2; 1765 u32 path_map: 4; 1766 u32 phy_map: 2; 1767 u32 band: 2; 1768 u32 type: 8; 1769 u32 con_rfk: 1; 1770 u32 rsvd: 13; 1771 1772 u32 start_time; 1773 u32 proc_time; 1774 }; 1775 1776 struct rtw89_btc_bt_smap { 1777 u32 connect: 1; 1778 u32 ble_connect: 1; 1779 u32 acl_busy: 1; 1780 u32 sco_busy: 1; 1781 u32 mesh_busy: 1; 1782 u32 inq_pag: 1; 1783 }; 1784 1785 union rtw89_btc_bt_state_map { 1786 u32 val; 1787 struct rtw89_btc_bt_smap map; 1788 }; 1789 1790 #define BTC_BT_RSSI_THMAX 4 1791 #define BTC_BT_AFH_GROUP 12 1792 #define BTC_BT_AFH_LE_GROUP 5 1793 1794 struct rtw89_btc_bt_link_info { 1795 struct rtw89_btc_u8_sta_chg profile_cnt; 1796 struct rtw89_btc_bool_sta_chg multi_link; 1797 struct rtw89_btc_bool_sta_chg relink; 1798 struct rtw89_btc_bt_hfp_desc hfp_desc; 1799 struct rtw89_btc_bt_hid_desc hid_desc; 1800 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1801 struct rtw89_btc_bt_pan_desc pan_desc; 1802 union rtw89_btc_bt_state_map status; 1803 1804 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1805 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1806 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1807 u8 afh_map[BTC_BT_AFH_GROUP]; 1808 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1809 1810 u32 role_sw: 1; 1811 u32 slave_role: 1; 1812 u32 afh_update: 1; 1813 u32 cqddr: 1; 1814 u32 rssi: 8; 1815 u32 tx_3m: 1; 1816 u32 rsvd: 19; 1817 }; 1818 1819 struct rtw89_btc_3rdcx_info { 1820 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1821 u8 hw_coex; 1822 u16 rsvd; 1823 }; 1824 1825 struct rtw89_btc_dm_emap { 1826 u32 init: 1; 1827 u32 pta_owner: 1; 1828 u32 wl_rfk_timeout: 1; 1829 u32 bt_rfk_timeout: 1; 1830 u32 wl_fw_hang: 1; 1831 u32 cycle_hang: 1; 1832 u32 w1_hang: 1; 1833 u32 b1_hang: 1; 1834 u32 tdma_no_sync: 1; 1835 u32 slot_no_sync: 1; 1836 u32 wl_slot_drift: 1; 1837 u32 bt_slot_drift: 1; 1838 u32 role_num_mismatch: 1; 1839 u32 null1_tx_late: 1; 1840 u32 bt_afh_conflict: 1; 1841 u32 bt_leafh_conflict: 1; 1842 u32 bt_slot_flood: 1; 1843 u32 wl_e2g_hang: 1; 1844 u32 wl_ver_mismatch: 1; 1845 u32 bt_ver_mismatch: 1; 1846 u32 rfe_type0: 1; 1847 u32 h2c_buffer_over: 1; 1848 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1849 u32 wl_no_sta_ntfy: 1; 1850 1851 u32 h2c_bmap_mismatch: 1; 1852 u32 c2h_bmap_mismatch: 1; 1853 u32 h2c_struct_invalid: 1; 1854 u32 c2h_struct_invalid: 1; 1855 u32 h2c_c2h_buffer_mismatch: 1; 1856 }; 1857 1858 union rtw89_btc_dm_error_map { 1859 u32 val; 1860 struct rtw89_btc_dm_emap map; 1861 }; 1862 1863 struct rtw89_btc_rf_para { 1864 u32 tx_pwr_freerun; 1865 u32 rx_gain_freerun; 1866 u32 tx_pwr_perpkt; 1867 u32 rx_gain_perpkt; 1868 }; 1869 1870 struct rtw89_btc_wl_nhm { 1871 u8 instant_wl_nhm_dbm; 1872 u8 instant_wl_nhm_per_mhz; 1873 u16 valid_record_times; 1874 s8 record_pwr[16]; 1875 u8 record_ratio[16]; 1876 s8 pwr; /* dbm_per_MHz */ 1877 u8 ratio; 1878 u8 current_status; 1879 u8 refresh; 1880 bool start_flag; 1881 s8 pwr_max; 1882 s8 pwr_min; 1883 }; 1884 1885 struct rtw89_btc_wl_info { 1886 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1887 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1888 struct rtw89_btc_wl_rfk_info rfk_info; 1889 struct rtw89_btc_wl_ver_info ver_info; 1890 struct rtw89_btc_wl_afh_info afh_info; 1891 struct rtw89_btc_wl_role_info role_info; 1892 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1893 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1894 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1895 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1896 struct rtw89_btc_wl_scan_info scan_info; 1897 struct rtw89_btc_wl_dbcc_info dbcc_info; 1898 struct rtw89_btc_rf_para rf_para; 1899 struct rtw89_btc_wl_nhm nhm; 1900 union rtw89_btc_wl_state_map status; 1901 1902 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1903 u8 rssi_level; 1904 u8 cn_report; 1905 u8 coex_mode; 1906 u8 pta_req_mac; 1907 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 1908 1909 bool is_5g_hi_channel; 1910 bool pta_reg_mac_chg; 1911 bool bg_mode; 1912 bool he_mode; 1913 bool scbd_change; 1914 bool fw_ver_mismatch; 1915 bool client_cnt_inc_2g; 1916 u32 scbd; 1917 }; 1918 1919 struct rtw89_btc_module { 1920 struct rtw89_btc_ant_info ant; 1921 u8 rfe_type; 1922 u8 cv; 1923 1924 u8 bt_solo: 1; 1925 u8 bt_pos: 1; 1926 u8 switch_type: 1; 1927 u8 wa_type: 3; 1928 1929 u8 kt_ver_adie; 1930 }; 1931 1932 struct rtw89_btc_module_v7 { 1933 u8 rfe_type; 1934 u8 kt_ver; 1935 u8 bt_solo; 1936 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1937 1938 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1939 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1940 u8 kt_ver_adie; 1941 u8 rsvd; 1942 1943 struct rtw89_btc_ant_info_v7 ant; 1944 } __packed; 1945 1946 union rtw89_btc_module_info { 1947 struct rtw89_btc_module md; 1948 struct rtw89_btc_module_v7 md_v7; 1949 }; 1950 1951 #define RTW89_BTC_DM_MAXSTEP 30 1952 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1953 1954 struct rtw89_btc_dm_step { 1955 u16 step[RTW89_BTC_DM_MAXSTEP]; 1956 u8 step_pos; 1957 bool step_ov; 1958 }; 1959 1960 struct rtw89_btc_init_info { 1961 struct rtw89_btc_module module; 1962 u8 wl_guard_ch; 1963 1964 u8 wl_only: 1; 1965 u8 wl_init_ok: 1; 1966 u8 dbcc_en: 1; 1967 u8 cx_other: 1; 1968 u8 bt_only: 1; 1969 1970 u16 rsvd; 1971 }; 1972 1973 struct rtw89_btc_init_info_v7 { 1974 u8 wl_guard_ch; 1975 u8 wl_only; 1976 u8 wl_init_ok; 1977 u8 rsvd3; 1978 1979 u8 cx_other; 1980 u8 bt_only; 1981 u8 pta_mode; 1982 u8 pta_direction; 1983 1984 struct rtw89_btc_module_v7 module; 1985 } __packed; 1986 1987 union rtw89_btc_init_info_u { 1988 struct rtw89_btc_init_info init; 1989 struct rtw89_btc_init_info_v7 init_v7; 1990 }; 1991 1992 struct rtw89_btc_wl_tx_limit_para { 1993 u16 enable; 1994 u32 tx_time; /* unit: us */ 1995 u16 tx_retry; 1996 }; 1997 1998 enum rtw89_btc_bt_scan_type { 1999 BTC_SCAN_INQ = 0, 2000 BTC_SCAN_PAGE, 2001 BTC_SCAN_BLE, 2002 BTC_SCAN_INIT, 2003 BTC_SCAN_TV, 2004 BTC_SCAN_ADV, 2005 BTC_SCAN_MAX1, 2006 }; 2007 2008 enum rtw89_btc_ble_scan_type { 2009 CXSCAN_BG = 0, 2010 CXSCAN_INIT, 2011 CXSCAN_LE, 2012 CXSCAN_MAX 2013 }; 2014 2015 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2016 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2017 2018 struct rtw89_btc_bt_scan_info_v1 { 2019 __le16 win; 2020 __le16 intvl; 2021 __le32 flags; 2022 } __packed; 2023 2024 struct rtw89_btc_bt_scan_info_v2 { 2025 __le16 win; 2026 __le16 intvl; 2027 } __packed; 2028 2029 struct rtw89_btc_fbtc_btscan_v1 { 2030 u8 fver; /* btc_ver::fcxbtscan */ 2031 u8 rsvd; 2032 __le16 rsvd2; 2033 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2034 } __packed; 2035 2036 struct rtw89_btc_fbtc_btscan_v2 { 2037 u8 fver; /* btc_ver::fcxbtscan */ 2038 u8 type; 2039 __le16 rsvd2; 2040 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2041 } __packed; 2042 2043 struct rtw89_btc_fbtc_btscan_v7 { 2044 u8 fver; /* btc_ver::fcxbtscan */ 2045 u8 type; 2046 u8 rsvd0; 2047 u8 rsvd1; 2048 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2049 } __packed; 2050 2051 union rtw89_btc_fbtc_btscan { 2052 struct rtw89_btc_fbtc_btscan_v1 v1; 2053 struct rtw89_btc_fbtc_btscan_v2 v2; 2054 struct rtw89_btc_fbtc_btscan_v7 v7; 2055 }; 2056 2057 struct rtw89_btc_bt_info { 2058 struct rtw89_btc_bt_link_info link_info; 2059 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2060 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2061 struct rtw89_btc_bt_ver_info ver_info; 2062 struct rtw89_btc_bool_sta_chg enable; 2063 struct rtw89_btc_bool_sta_chg inq_pag; 2064 struct rtw89_btc_rf_para rf_para; 2065 union rtw89_btc_bt_rfk_info_map rfk_info; 2066 2067 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2068 u8 rssi_level; 2069 2070 u32 scbd; 2071 u32 feature; 2072 2073 u32 mbx_avl: 1; 2074 u32 whql_test: 1; 2075 u32 igno_wl: 1; 2076 u32 reinit: 1; 2077 u32 ble_scan_en: 1; 2078 u32 btg_type: 1; 2079 u32 inq: 1; 2080 u32 pag: 1; 2081 u32 run_patch_code: 1; 2082 u32 hi_lna_rx: 1; 2083 u32 scan_rx_low_pri: 1; 2084 u32 scan_info_update: 1; 2085 u32 lna_constrain: 3; 2086 u32 rsvd: 17; 2087 }; 2088 2089 struct rtw89_btc_cx { 2090 struct rtw89_btc_wl_info wl; 2091 struct rtw89_btc_bt_info bt; 2092 struct rtw89_btc_3rdcx_info other; 2093 u32 state_map; 2094 u32 cnt_bt[BTC_BCNT_NUM]; 2095 u32 cnt_wl[BTC_WCNT_NUM]; 2096 }; 2097 2098 struct rtw89_btc_fbtc_tdma { 2099 u8 type; /* btc_ver::fcxtdma */ 2100 u8 rxflctrl; 2101 u8 txpause; 2102 u8 wtgle_n; 2103 u8 leak_n; 2104 u8 ext_ctrl; 2105 u8 rxflctrl_role; 2106 u8 option_ctrl; 2107 } __packed; 2108 2109 struct rtw89_btc_fbtc_tdma_v3 { 2110 u8 fver; /* btc_ver::fcxtdma */ 2111 u8 rsvd; 2112 __le16 rsvd1; 2113 struct rtw89_btc_fbtc_tdma tdma; 2114 } __packed; 2115 2116 union rtw89_btc_fbtc_tdma_le32 { 2117 struct rtw89_btc_fbtc_tdma v1; 2118 struct rtw89_btc_fbtc_tdma_v3 v3; 2119 }; 2120 2121 #define CXMREG_MAX 30 2122 #define CXMREG_MAX_V2 20 2123 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2124 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2125 2126 enum rtw89_btc_bt_sta_counter { 2127 BTC_BCNT_RFK_REQ = 0, 2128 BTC_BCNT_RFK_GO = 1, 2129 BTC_BCNT_RFK_REJECT = 2, 2130 BTC_BCNT_RFK_FAIL = 3, 2131 BTC_BCNT_RFK_TIMEOUT = 4, 2132 BTC_BCNT_HI_TX = 5, 2133 BTC_BCNT_HI_RX = 6, 2134 BTC_BCNT_LO_TX = 7, 2135 BTC_BCNT_LO_RX = 8, 2136 BTC_BCNT_POLLUTED = 9, 2137 BTC_BCNT_STA_MAX 2138 }; 2139 2140 enum rtw89_btc_bt_sta_counter_v105 { 2141 BTC_BCNT_RFK_REQ_V105 = 0, 2142 BTC_BCNT_HI_TX_V105 = 1, 2143 BTC_BCNT_HI_RX_V105 = 2, 2144 BTC_BCNT_LO_TX_V105 = 3, 2145 BTC_BCNT_LO_RX_V105 = 4, 2146 BTC_BCNT_POLLUTED_V105 = 5, 2147 BTC_BCNT_STA_MAX_V105 2148 }; 2149 2150 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2151 u16 fver; /* btc_ver::fcxbtcrpt */ 2152 u16 rpt_cnt; /* tmr counters */ 2153 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2154 u32 wl_fw_cx_offload; 2155 u32 wl_fw_ver; 2156 u32 rpt_enable; 2157 u32 rpt_para; /* ms */ 2158 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2159 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2160 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2161 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2162 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2163 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2164 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2165 u32 c2h_cnt; /* fw send c2h counter */ 2166 u32 h2c_cnt; /* fw recv h2c counter */ 2167 } __packed; 2168 2169 struct rtw89_btc_fbtc_rpt_ctrl_info { 2170 __le32 cnt; /* fw report counter */ 2171 __le32 en; /* report map */ 2172 __le32 para; /* not used */ 2173 2174 __le32 cnt_c2h; /* fw send c2h counter */ 2175 __le32 cnt_h2c; /* fw recv h2c counter */ 2176 __le32 len_c2h; /* The total length of the last C2H */ 2177 2178 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2179 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2180 } __packed; 2181 2182 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2183 __le32 cx_ver; /* match which driver's coex version */ 2184 __le32 fw_ver; 2185 __le32 en; /* report map */ 2186 2187 __le16 cnt; /* fw report counter */ 2188 __le16 cnt_c2h; /* fw send c2h counter */ 2189 __le16 cnt_h2c; /* fw recv h2c counter */ 2190 __le16 len_c2h; /* The total length of the last C2H */ 2191 2192 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2193 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2194 } __packed; 2195 2196 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2197 __le16 cnt; /* fw report counter */ 2198 __le16 cnt_c2h; /* fw send c2h counter */ 2199 __le16 cnt_h2c; /* fw recv h2c counter */ 2200 __le16 len_c2h; /* The total length of the last C2H */ 2201 2202 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2203 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2204 2205 __le32 cx_ver; /* match which driver's coex version */ 2206 __le32 fw_ver; 2207 __le32 en; /* report map */ 2208 } __packed; 2209 2210 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2211 __le32 cx_ver; /* match which driver's coex version */ 2212 __le32 cx_offload; 2213 __le32 fw_ver; 2214 } __packed; 2215 2216 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2217 __le32 cnt_empty; /* a2dp empty count */ 2218 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2219 __le32 cnt_tx; 2220 __le32 cnt_ack; 2221 __le32 cnt_nack; 2222 } __packed; 2223 2224 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2225 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2226 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2227 __le32 cnt_recv; /* fw recv mailbox counter */ 2228 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2229 } __packed; 2230 2231 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2232 u8 fver; 2233 u8 rsvd; 2234 __le16 rsvd1; 2235 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2236 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2237 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2238 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2239 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2240 } __packed; 2241 2242 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2243 u8 fver; 2244 u8 rsvd; 2245 __le16 rsvd1; 2246 2247 u8 gnt_val[RTW89_PHY_NUM][4]; 2248 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2249 2250 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2251 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2252 } __packed; 2253 2254 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2255 u8 fver; 2256 u8 rsvd; 2257 __le16 rsvd1; 2258 2259 u8 gnt_val[RTW89_PHY_NUM][4]; 2260 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2261 2262 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2263 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2264 } __packed; 2265 2266 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2267 u8 fver; 2268 u8 rsvd0; 2269 u8 rsvd1; 2270 u8 rsvd2; 2271 2272 u8 gnt_val[RTW89_PHY_NUM][4]; 2273 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2274 2275 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2276 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2277 } __packed; 2278 2279 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2280 u8 fver; 2281 u8 rsvd0; 2282 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2283 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2284 2285 u8 gnt_val[RTW89_PHY_NUM][4]; 2286 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2287 2288 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2289 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2290 } __packed; 2291 2292 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2293 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2294 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2295 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2296 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2297 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2298 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2299 }; 2300 2301 enum rtw89_fbtc_ext_ctrl_type { 2302 CXECTL_OFF = 0x0, /* tdma off */ 2303 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2304 CXECTL_EXT = 0x2, 2305 CXECTL_MAX 2306 }; 2307 2308 union rtw89_btc_fbtc_rxflct { 2309 u8 val; 2310 u8 type: 3; 2311 u8 tgln_n: 5; 2312 }; 2313 2314 enum rtw89_btc_cxst_state { 2315 CXST_OFF = 0x0, 2316 CXST_B2W = 0x1, 2317 CXST_W1 = 0x2, 2318 CXST_W2 = 0x3, 2319 CXST_W2B = 0x4, 2320 CXST_B1 = 0x5, 2321 CXST_B2 = 0x6, 2322 CXST_B3 = 0x7, 2323 CXST_B4 = 0x8, 2324 CXST_LK = 0x9, 2325 CXST_BLK = 0xa, 2326 CXST_E2G = 0xb, 2327 CXST_E5G = 0xc, 2328 CXST_EBT = 0xd, 2329 CXST_ENULL = 0xe, 2330 CXST_WLK = 0xf, 2331 CXST_W1FDD = 0x10, 2332 CXST_B1FDD = 0x11, 2333 CXST_MAX = 0x12, 2334 }; 2335 2336 enum rtw89_btc_cxevnt { 2337 CXEVNT_TDMA_ENTRY = 0x0, 2338 CXEVNT_WL_TMR, 2339 CXEVNT_B1_TMR, 2340 CXEVNT_B2_TMR, 2341 CXEVNT_B3_TMR, 2342 CXEVNT_B4_TMR, 2343 CXEVNT_W2B_TMR, 2344 CXEVNT_B2W_TMR, 2345 CXEVNT_BCN_EARLY, 2346 CXEVNT_A2DP_EMPTY, 2347 CXEVNT_LK_END, 2348 CXEVNT_RX_ISR, 2349 CXEVNT_RX_FC0, 2350 CXEVNT_RX_FC1, 2351 CXEVNT_BT_RELINK, 2352 CXEVNT_BT_RETRY, 2353 CXEVNT_E2G, 2354 CXEVNT_E5G, 2355 CXEVNT_EBT, 2356 CXEVNT_ENULL, 2357 CXEVNT_DRV_WLK, 2358 CXEVNT_BCN_OK, 2359 CXEVNT_BT_CHANGE, 2360 CXEVNT_EBT_EXTEND, 2361 CXEVNT_E2G_NULL1, 2362 CXEVNT_B1FDD_TMR, 2363 CXEVNT_MAX 2364 }; 2365 2366 enum { 2367 CXBCN_ALL = 0x0, 2368 CXBCN_ALL_OK, 2369 CXBCN_BT_SLOT, 2370 CXBCN_BT_OK, 2371 CXBCN_MAX 2372 }; 2373 2374 enum btc_slot_type { 2375 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2376 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2377 CXSTYPE_NUM, 2378 }; 2379 2380 enum { /* TIME */ 2381 CXT_BT = 0x0, 2382 CXT_WL = 0x1, 2383 CXT_MAX 2384 }; 2385 2386 enum { /* TIME-A2DP */ 2387 CXT_FLCTRL_OFF = 0x0, 2388 CXT_FLCTRL_ON = 0x1, 2389 CXT_FLCTRL_MAX 2390 }; 2391 2392 enum { /* STEP TYPE */ 2393 CXSTEP_NONE = 0x0, 2394 CXSTEP_EVNT = 0x1, 2395 CXSTEP_SLOT = 0x2, 2396 CXSTEP_MAX, 2397 }; 2398 2399 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2400 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2401 RPT_BT_AFH_SEQ_LE = 0x20 2402 }; 2403 2404 #define BTC_DBG_MAX1 32 2405 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2406 u8 fver; /* btc_ver::fcxgpiodbg */ 2407 u8 rsvd; 2408 __le16 rsvd2; 2409 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2410 __le32 pre_state; /* the debug signal is 1 or 0 */ 2411 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2412 } __packed; 2413 2414 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2415 u8 fver; 2416 u8 rsvd0; 2417 u8 rsvd1; 2418 u8 rsvd2; 2419 2420 u8 gpio_map[BTC_DBG_MAX1]; 2421 2422 __le32 en_map; 2423 __le32 pre_state; 2424 } __packed; 2425 2426 union rtw89_btc_fbtc_gpio_dbg { 2427 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2428 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2429 }; 2430 2431 struct rtw89_btc_fbtc_mreg_val_v1 { 2432 u8 fver; /* btc_ver::fcxmreg */ 2433 u8 reg_num; 2434 __le16 rsvd; 2435 __le32 mreg_val[CXMREG_MAX]; 2436 } __packed; 2437 2438 struct rtw89_btc_fbtc_mreg_val_v2 { 2439 u8 fver; /* btc_ver::fcxmreg */ 2440 u8 reg_num; 2441 __le16 rsvd; 2442 __le32 mreg_val[CXMREG_MAX_V2]; 2443 } __packed; 2444 2445 struct rtw89_btc_fbtc_mreg_val_v7 { 2446 u8 fver; 2447 u8 reg_num; 2448 u8 rsvd0; 2449 u8 rsvd1; 2450 __le32 mreg_val[CXMREG_MAX_V2]; 2451 } __packed; 2452 2453 union rtw89_btc_fbtc_mreg_val { 2454 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2455 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2456 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2457 }; 2458 2459 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2460 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2461 .offset = cpu_to_le32(__offset), } 2462 2463 struct rtw89_btc_fbtc_mreg { 2464 __le16 type; 2465 __le16 bytes; 2466 __le32 offset; 2467 } __packed; 2468 2469 struct rtw89_btc_fbtc_slot { 2470 __le16 dur; 2471 __le32 cxtbl; 2472 __le16 cxtype; 2473 } __packed; 2474 2475 struct rtw89_btc_fbtc_slots { 2476 u8 fver; /* btc_ver::fcxslots */ 2477 u8 tbl_num; 2478 __le16 rsvd; 2479 __le32 update_map; 2480 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2481 } __packed; 2482 2483 struct rtw89_btc_fbtc_slot_v7 { 2484 __le16 dur; /* slot duration */ 2485 __le16 cxtype; 2486 __le32 cxtbl; 2487 } __packed; 2488 2489 struct rtw89_btc_fbtc_slot_u16 { 2490 __le16 dur; /* slot duration */ 2491 __le16 cxtype; 2492 __le16 cxtbl_l16; /* coex table [15:0] */ 2493 __le16 cxtbl_h16; /* coex table [31:16] */ 2494 } __packed; 2495 2496 struct rtw89_btc_fbtc_1slot_v7 { 2497 u8 fver; 2498 u8 sid; /* slot id */ 2499 __le16 rsvd; 2500 struct rtw89_btc_fbtc_slot_v7 slot; 2501 } __packed; 2502 2503 struct rtw89_btc_fbtc_slots_v7 { 2504 u8 fver; 2505 u8 slot_cnt; 2506 u8 rsvd0; 2507 u8 rsvd1; 2508 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2509 __le32 update_map; 2510 } __packed; 2511 2512 union rtw89_btc_fbtc_slots_info { 2513 struct rtw89_btc_fbtc_slots v1; 2514 struct rtw89_btc_fbtc_slots_v7 v7; 2515 } __packed; 2516 2517 struct rtw89_btc_fbtc_step { 2518 u8 type; 2519 u8 val; 2520 __le16 difft; 2521 } __packed; 2522 2523 struct rtw89_btc_fbtc_steps_v2 { 2524 u8 fver; /* btc_ver::fcxstep */ 2525 u8 rsvd; 2526 __le16 cnt; 2527 __le16 pos_old; 2528 __le16 pos_new; 2529 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2530 } __packed; 2531 2532 struct rtw89_btc_fbtc_steps_v3 { 2533 u8 fver; 2534 u8 en; 2535 __le16 rsvd; 2536 __le32 cnt; 2537 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2538 } __packed; 2539 2540 union rtw89_btc_fbtc_steps_info { 2541 struct rtw89_btc_fbtc_steps_v2 v2; 2542 struct rtw89_btc_fbtc_steps_v3 v3; 2543 }; 2544 2545 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2546 u8 fver; /* btc_ver::fcxcysta */ 2547 u8 rsvd; 2548 __le16 cycles; /* total cycle number */ 2549 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2550 __le16 a2dpept; /* a2dp empty cnt */ 2551 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2552 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2553 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2554 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2555 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2556 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2557 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2558 __le16 tmax_a2dpept; /* max a2dp empty time */ 2559 __le16 tavg_lk; /* avg leak-slot time */ 2560 __le16 tmax_lk; /* max leak-slot time */ 2561 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2562 __le32 bcn_cnt[CXBCN_MAX]; 2563 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2564 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2565 __le32 skip_cnt; 2566 __le32 exception; 2567 __le32 except_cnt; 2568 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2569 } __packed; 2570 2571 struct rtw89_btc_fbtc_fdd_try_info { 2572 __le16 cycles[CXT_FLCTRL_MAX]; 2573 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2574 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2575 } __packed; 2576 2577 struct rtw89_btc_fbtc_cycle_time_info { 2578 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2579 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2580 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2581 } __packed; 2582 2583 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2584 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2585 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2586 } __packed; 2587 2588 struct rtw89_btc_fbtc_a2dp_trx_stat { 2589 u8 empty_cnt; 2590 u8 retry_cnt; 2591 u8 tx_rate; 2592 u8 tx_cnt; 2593 u8 ack_cnt; 2594 u8 nack_cnt; 2595 u8 rsvd1; 2596 u8 rsvd2; 2597 } __packed; 2598 2599 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2600 u8 empty_cnt; 2601 u8 retry_cnt; 2602 u8 tx_rate; 2603 u8 tx_cnt; 2604 u8 ack_cnt; 2605 u8 nack_cnt; 2606 u8 no_empty_cnt; 2607 u8 rsvd; 2608 } __packed; 2609 2610 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2611 __le16 cnt; /* a2dp empty cnt */ 2612 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2613 __le16 tavg; /* avg a2dp empty time */ 2614 __le16 tmax; /* max a2dp empty time */ 2615 } __packed; 2616 2617 struct rtw89_btc_fbtc_cycle_leak_info { 2618 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2619 __le16 tavg; /* avg leak-slot time */ 2620 __le16 tmax; /* max leak-slot time */ 2621 } __packed; 2622 2623 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2624 __le16 tavg; 2625 __le16 tamx; 2626 __le32 cnt_rximr; 2627 } __packed; 2628 2629 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2630 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2631 2632 struct rtw89_btc_fbtc_cycle_fddt_info { 2633 __le16 train_cycle; 2634 __le16 tp; 2635 2636 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2637 s8 bt_tx_power; /* decrease Tx power (dB) */ 2638 s8 bt_rx_gain; /* LNA constrain level */ 2639 u8 no_empty_cnt; 2640 2641 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2642 u8 cn; /* condition_num */ 2643 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2644 u8 train_result; /* refer to enum btc_fddt_check_map */ 2645 } __packed; 2646 2647 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2648 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2649 2650 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2651 __le16 train_cycle; 2652 __le16 tp; 2653 2654 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2655 s8 bt_tx_power; /* decrease Tx power (dB) */ 2656 s8 bt_rx_gain; /* LNA constrain level */ 2657 u8 no_empty_cnt; 2658 2659 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2660 u8 cn; /* condition_num */ 2661 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2662 u8 train_result; /* refer to enum btc_fddt_check_map */ 2663 } __packed; 2664 2665 struct rtw89_btc_fbtc_fddt_cell_status { 2666 s8 wl_tx_pwr; 2667 s8 bt_tx_pwr; 2668 s8 bt_rx_gain; 2669 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2670 } __packed; 2671 2672 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2673 u8 fver; 2674 u8 rsvd; 2675 __le16 cycles; /* total cycle number */ 2676 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2677 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2678 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2679 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2680 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2681 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2682 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2683 __le32 bcn_cnt[CXBCN_MAX]; 2684 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2685 __le32 skip_cnt; 2686 __le32 except_cnt; 2687 __le32 except_map; 2688 } __packed; 2689 2690 #define FDD_TRAIN_WL_DIRECTION 2 2691 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2692 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2693 2694 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2695 u8 fver; 2696 u8 rsvd; 2697 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2698 u8 except_cnt; 2699 2700 __le16 skip_cnt; 2701 __le16 cycles; /* total cycle number */ 2702 2703 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2704 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2705 __le16 bcn_cnt[CXBCN_MAX]; 2706 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2707 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2708 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2709 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2710 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2711 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2712 [FDD_TRAIN_WL_RSSI_LEVEL] 2713 [FDD_TRAIN_BT_RSSI_LEVEL]; 2714 __le32 except_map; 2715 } __packed; 2716 2717 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2718 u8 fver; 2719 u8 rsvd; 2720 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2721 u8 except_cnt; 2722 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2723 2724 __le16 skip_cnt; 2725 __le16 cycles; /* total cycle number */ 2726 2727 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2728 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2729 __le16 bcn_cnt[CXBCN_MAX]; 2730 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2731 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2732 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2733 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2734 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2735 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2736 [FDD_TRAIN_WL_RSSI_LEVEL] 2737 [FDD_TRAIN_BT_RSSI_LEVEL]; 2738 __le32 except_map; 2739 } __packed; 2740 2741 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2742 u8 fver; 2743 u8 rsvd; 2744 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2745 u8 except_cnt; 2746 2747 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2748 2749 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2750 2751 __le16 skip_cnt; 2752 __le16 cycles; /* total cycle number */ 2753 2754 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2755 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2756 __le16 bcn_cnt[CXBCN_MAX]; 2757 2758 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2759 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2760 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2761 2762 __le32 except_map; 2763 } __packed; 2764 2765 union rtw89_btc_fbtc_cysta_info { 2766 struct rtw89_btc_fbtc_cysta_v2 v2; 2767 struct rtw89_btc_fbtc_cysta_v3 v3; 2768 struct rtw89_btc_fbtc_cysta_v4 v4; 2769 struct rtw89_btc_fbtc_cysta_v5 v5; 2770 struct rtw89_btc_fbtc_cysta_v7 v7; 2771 }; 2772 2773 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2774 u8 fver; /* btc_ver::fcxnullsta */ 2775 u8 rsvd; 2776 __le16 rsvd2; 2777 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2778 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2779 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2780 } __packed; 2781 2782 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2783 u8 fver; /* btc_ver::fcxnullsta */ 2784 u8 rsvd; 2785 __le16 rsvd2; 2786 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2787 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2788 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2789 } __packed; 2790 2791 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2792 u8 fver; 2793 u8 rsvd0; 2794 u8 rsvd1; 2795 u8 rsvd2; 2796 2797 __le32 tmax[2]; 2798 __le32 tavg[2]; 2799 __le32 result[2][5]; 2800 } __packed; 2801 2802 union rtw89_btc_fbtc_cynullsta_info { 2803 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2804 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2805 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2806 }; 2807 2808 struct rtw89_btc_fbtc_btver_v1 { 2809 u8 fver; /* btc_ver::fcxbtver */ 2810 u8 rsvd; 2811 __le16 rsvd2; 2812 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2813 __le32 fw_ver; 2814 __le32 feature; 2815 } __packed; 2816 2817 struct rtw89_btc_fbtc_btver_v7 { 2818 u8 fver; 2819 u8 rsvd0; 2820 u8 rsvd1; 2821 u8 rsvd2; 2822 2823 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2824 __le32 fw_ver; 2825 __le32 feature; 2826 } __packed; 2827 2828 union rtw89_btc_fbtc_btver { 2829 struct rtw89_btc_fbtc_btver_v1 v1; 2830 struct rtw89_btc_fbtc_btver_v7 v7; 2831 } __packed; 2832 2833 struct rtw89_btc_fbtc_btafh { 2834 u8 fver; /* btc_ver::fcxbtafh */ 2835 u8 rsvd; 2836 __le16 rsvd2; 2837 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2838 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2839 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2840 } __packed; 2841 2842 struct rtw89_btc_fbtc_btafh_v2 { 2843 u8 fver; /* btc_ver::fcxbtafh */ 2844 u8 rsvd; 2845 u8 rsvd2; 2846 u8 map_type; 2847 u8 afh_l[4]; 2848 u8 afh_m[4]; 2849 u8 afh_h[4]; 2850 u8 afh_le_a[4]; 2851 u8 afh_le_b[4]; 2852 } __packed; 2853 2854 struct rtw89_btc_fbtc_btafh_v7 { 2855 u8 fver; 2856 u8 map_type; 2857 u8 rsvd0; 2858 u8 rsvd1; 2859 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2860 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2861 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2862 u8 afh_le_a[4]; 2863 u8 afh_le_b[4]; 2864 } __packed; 2865 2866 struct rtw89_btc_fbtc_btdevinfo { 2867 u8 fver; /* btc_ver::fcxbtdevinfo */ 2868 u8 rsvd; 2869 __le16 vendor_id; 2870 __le32 dev_name; /* only 24 bits valid */ 2871 __le32 flush_time; 2872 } __packed; 2873 2874 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2875 struct rtw89_btc_rf_trx_para { 2876 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2877 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2878 u8 bt_tx_power; /* decrease Tx power (dB) */ 2879 u8 bt_rx_gain; /* LNA constrain level */ 2880 }; 2881 2882 struct rtw89_btc_trx_info { 2883 u8 tx_lvl; 2884 u8 rx_lvl; 2885 u8 wl_rssi; 2886 u8 bt_rssi; 2887 2888 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2889 s8 rx_gain; /* rx gain table index (TBD.) */ 2890 s8 bt_tx_power; /* decrease Tx power (dB) */ 2891 s8 bt_rx_gain; /* LNA constrain level */ 2892 2893 u8 cn; /* condition_num */ 2894 s8 nhm; 2895 u8 bt_profile; 2896 u8 rsvd2; 2897 2898 u16 tx_rate; 2899 u16 rx_rate; 2900 2901 u32 tx_tp; 2902 u32 rx_tp; 2903 u32 rx_err_ratio; 2904 }; 2905 2906 union rtw89_btc_fbtc_slot_u { 2907 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2908 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2909 }; 2910 2911 struct rtw89_btc_dm { 2912 union rtw89_btc_fbtc_slot_u slot; 2913 union rtw89_btc_fbtc_slot_u slot_now; 2914 struct rtw89_btc_fbtc_tdma tdma; 2915 struct rtw89_btc_fbtc_tdma tdma_now; 2916 struct rtw89_mac_ax_coex_gnt gnt; 2917 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2918 struct rtw89_btc_rf_trx_para rf_trx_para; 2919 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2920 struct rtw89_btc_dm_step dm_step; 2921 struct rtw89_btc_wl_scc_ctrl wl_scc; 2922 struct rtw89_btc_trx_info trx_info; 2923 union rtw89_btc_dm_error_map error; 2924 u32 cnt_dm[BTC_DCNT_NUM]; 2925 u32 cnt_notify[BTC_NCNT_NUM]; 2926 2927 u32 update_slot_map; 2928 u32 set_ant_path; 2929 u32 e2g_slot_limit; 2930 u32 e2g_slot_nulltx_time; 2931 2932 u32 wl_only: 1; 2933 u32 wl_fw_cx_offload: 1; 2934 u32 freerun: 1; 2935 u32 fddt_train: 1; 2936 u32 wl_ps_ctrl: 2; 2937 u32 wl_mimo_ps: 1; 2938 u32 leak_ap: 1; 2939 u32 noisy_level: 3; 2940 u32 coex_info_map: 8; 2941 u32 bt_only: 1; 2942 u32 wl_btg_rx: 2; 2943 u32 trx_para_level: 8; 2944 u32 wl_stb_chg: 1; 2945 u32 pta_owner: 1; 2946 2947 u32 tdma_instant_excute: 1; 2948 u32 wl_btg_rx_rb: 2; 2949 2950 u16 slot_dur[CXST_MAX]; 2951 u16 bt_slot_flood; 2952 2953 u8 run_reason; 2954 u8 run_action; 2955 2956 u8 wl_pre_agc: 2; 2957 u8 wl_lna2: 1; 2958 u8 freerun_chk: 1; 2959 u8 wl_pre_agc_rb: 2; 2960 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2961 u8 slot_req_more: 1; 2962 }; 2963 2964 struct rtw89_btc_ctrl { 2965 u32 manual: 1; 2966 u32 igno_bt: 1; 2967 u32 always_freerun: 1; 2968 u32 trace_step: 16; 2969 u32 rsvd: 12; 2970 }; 2971 2972 struct rtw89_btc_ctrl_v7 { 2973 u8 manual; 2974 u8 igno_bt; 2975 u8 always_freerun; 2976 u8 rsvd; 2977 } __packed; 2978 2979 union rtw89_btc_ctrl_list { 2980 struct rtw89_btc_ctrl ctrl; 2981 struct rtw89_btc_ctrl_v7 ctrl_v7; 2982 }; 2983 2984 struct rtw89_btc_dbg { 2985 /* cmd "rb" */ 2986 bool rb_done; 2987 u32 rb_val; 2988 }; 2989 2990 enum rtw89_btc_btf_fw_event { 2991 BTF_EVNT_RPT = 0, 2992 BTF_EVNT_BT_INFO = 1, 2993 BTF_EVNT_BT_SCBD = 2, 2994 BTF_EVNT_BT_REG = 3, 2995 BTF_EVNT_CX_RUNINFO = 4, 2996 BTF_EVNT_BT_PSD = 5, 2997 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 2998 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 2999 BTF_EVNT_BUF_OVERFLOW, 3000 BTF_EVNT_C2H_LOOPBACK, 3001 BTF_EVNT_MAX, 3002 }; 3003 3004 enum btf_fw_event_report { 3005 BTC_RPT_TYPE_CTRL = 0x0, 3006 BTC_RPT_TYPE_TDMA, 3007 BTC_RPT_TYPE_SLOT, 3008 BTC_RPT_TYPE_CYSTA, 3009 BTC_RPT_TYPE_STEP, 3010 BTC_RPT_TYPE_NULLSTA, 3011 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3012 BTC_RPT_TYPE_MREG, 3013 BTC_RPT_TYPE_GPIO_DBG, 3014 BTC_RPT_TYPE_BT_VER, 3015 BTC_RPT_TYPE_BT_SCAN, 3016 BTC_RPT_TYPE_BT_AFH, 3017 BTC_RPT_TYPE_BT_DEVICE, 3018 BTC_RPT_TYPE_TEST, 3019 BTC_RPT_TYPE_MAX = 31, 3020 3021 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3022 __BTC_RPT_TYPE_V0_MAX = 12, 3023 }; 3024 3025 enum rtw_btc_btf_reg_type { 3026 REG_MAC = 0x0, 3027 REG_BB = 0x1, 3028 REG_RF = 0x2, 3029 REG_BT_RF = 0x3, 3030 REG_BT_MODEM = 0x4, 3031 REG_BT_BLUEWIZE = 0x5, 3032 REG_BT_VENDOR = 0x6, 3033 REG_BT_LE = 0x7, 3034 REG_MAX_TYPE, 3035 }; 3036 3037 struct rtw89_btc_rpt_cmn_info { 3038 u32 rx_cnt; 3039 u32 rx_len; 3040 u32 req_len; /* expected rsp len */ 3041 u8 req_fver; /* expected rsp fver */ 3042 u8 rsp_fver; /* fver from fw */ 3043 u8 valid; 3044 } __packed; 3045 3046 union rtw89_btc_fbtc_btafh_info { 3047 struct rtw89_btc_fbtc_btafh v1; 3048 struct rtw89_btc_fbtc_btafh_v2 v2; 3049 struct rtw89_btc_fbtc_btafh_v7 v7; 3050 }; 3051 3052 struct rtw89_btc_report_ctrl_state { 3053 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3054 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3055 }; 3056 3057 struct rtw89_btc_rpt_fbtc_tdma { 3058 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3059 union rtw89_btc_fbtc_tdma_le32 finfo; 3060 }; 3061 3062 struct rtw89_btc_rpt_fbtc_slots { 3063 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3064 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3065 }; 3066 3067 struct rtw89_btc_rpt_fbtc_cysta { 3068 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3069 union rtw89_btc_fbtc_cysta_info finfo; 3070 }; 3071 3072 struct rtw89_btc_rpt_fbtc_step { 3073 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3074 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3075 }; 3076 3077 struct rtw89_btc_rpt_fbtc_nullsta { 3078 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3079 union rtw89_btc_fbtc_cynullsta_info finfo; 3080 }; 3081 3082 struct rtw89_btc_rpt_fbtc_mreg { 3083 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3084 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3085 }; 3086 3087 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3088 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3089 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3090 }; 3091 3092 struct rtw89_btc_rpt_fbtc_btver { 3093 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3094 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3095 }; 3096 3097 struct rtw89_btc_rpt_fbtc_btscan { 3098 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3099 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3100 }; 3101 3102 struct rtw89_btc_rpt_fbtc_btafh { 3103 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3104 union rtw89_btc_fbtc_btafh_info finfo; 3105 }; 3106 3107 struct rtw89_btc_rpt_fbtc_btdev { 3108 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3109 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3110 }; 3111 3112 enum rtw89_btc_btfre_type { 3113 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3114 BTFRE_UNDEF_TYPE, 3115 BTFRE_EXCEPTION, 3116 BTFRE_MAX, 3117 }; 3118 3119 struct rtw89_btc_btf_fwinfo { 3120 u32 cnt_c2h; 3121 u32 cnt_h2c; 3122 u32 cnt_h2c_fail; 3123 u32 event[BTF_EVNT_MAX]; 3124 3125 u32 err[BTFRE_MAX]; 3126 u32 len_mismch; 3127 u32 fver_mismch; 3128 u32 rpt_en_map; 3129 3130 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3131 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3132 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3133 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3134 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3135 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3136 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3137 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3138 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3139 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3140 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3141 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3142 }; 3143 3144 struct rtw89_btc_ver { 3145 enum rtw89_core_chip_id chip_id; 3146 u32 fw_ver_code; 3147 3148 u8 fcxbtcrpt; 3149 u8 fcxtdma; 3150 u8 fcxslots; 3151 u8 fcxcysta; 3152 u8 fcxstep; 3153 u8 fcxnullsta; 3154 u8 fcxmreg; 3155 u8 fcxgpiodbg; 3156 u8 fcxbtver; 3157 u8 fcxbtscan; 3158 u8 fcxbtafh; 3159 u8 fcxbtdevinfo; 3160 u8 fwlrole; 3161 u8 frptmap; 3162 u8 fcxctrl; 3163 u8 fcxinit; 3164 3165 u8 fwevntrptl; 3166 u8 fwc2hfunc; 3167 u8 drvinfo_type; 3168 u16 info_buf; 3169 u8 max_role_num; 3170 }; 3171 3172 #define RTW89_BTC_POLICY_MAXLEN 512 3173 3174 struct rtw89_btc { 3175 const struct rtw89_btc_ver *ver; 3176 3177 struct rtw89_btc_cx cx; 3178 struct rtw89_btc_dm dm; 3179 union rtw89_btc_ctrl_list ctrl; 3180 union rtw89_btc_module_info mdinfo; 3181 struct rtw89_btc_btf_fwinfo fwinfo; 3182 struct rtw89_btc_dbg dbg; 3183 3184 struct wiphy_work eapol_notify_work; 3185 struct wiphy_work arp_notify_work; 3186 struct wiphy_work dhcp_notify_work; 3187 struct wiphy_work icmp_notify_work; 3188 3189 u32 bt_req_len; 3190 3191 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3192 u8 ant_type; 3193 u8 btg_pos; 3194 u16 policy_len; 3195 u16 policy_type; 3196 u32 hubmsg_cnt; 3197 bool bt_req_en; 3198 bool update_policy_force; 3199 bool lps; 3200 bool manual_ctrl; 3201 }; 3202 3203 enum rtw89_btc_hmsg { 3204 RTW89_BTC_HMSG_TMR_EN = 0x0, 3205 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3206 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3207 RTW89_BTC_HMSG_FW_EV = 0x3, 3208 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3209 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3210 3211 NUM_OF_RTW89_BTC_HMSG, 3212 }; 3213 3214 enum rtw89_ra_mode { 3215 RTW89_RA_MODE_CCK = BIT(0), 3216 RTW89_RA_MODE_OFDM = BIT(1), 3217 RTW89_RA_MODE_HT = BIT(2), 3218 RTW89_RA_MODE_VHT = BIT(3), 3219 RTW89_RA_MODE_HE = BIT(4), 3220 RTW89_RA_MODE_EHT = BIT(5), 3221 }; 3222 3223 enum rtw89_ra_report_mode { 3224 RTW89_RA_RPT_MODE_LEGACY, 3225 RTW89_RA_RPT_MODE_HT, 3226 RTW89_RA_RPT_MODE_VHT, 3227 RTW89_RA_RPT_MODE_HE, 3228 RTW89_RA_RPT_MODE_EHT, 3229 }; 3230 3231 enum rtw89_dig_noisy_level { 3232 RTW89_DIG_NOISY_LEVEL0 = -1, 3233 RTW89_DIG_NOISY_LEVEL1 = 0, 3234 RTW89_DIG_NOISY_LEVEL2 = 1, 3235 RTW89_DIG_NOISY_LEVEL3 = 2, 3236 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3237 }; 3238 3239 enum rtw89_gi_ltf { 3240 RTW89_GILTF_LGI_4XHE32 = 0, 3241 RTW89_GILTF_SGI_4XHE08 = 1, 3242 RTW89_GILTF_2XHE16 = 2, 3243 RTW89_GILTF_2XHE08 = 3, 3244 RTW89_GILTF_1XHE16 = 4, 3245 RTW89_GILTF_1XHE08 = 5, 3246 RTW89_GILTF_MAX 3247 }; 3248 3249 enum rtw89_rx_frame_type { 3250 RTW89_RX_TYPE_MGNT = 0, 3251 RTW89_RX_TYPE_CTRL = 1, 3252 RTW89_RX_TYPE_DATA = 2, 3253 RTW89_RX_TYPE_RSVD = 3, 3254 }; 3255 3256 enum rtw89_efuse_block { 3257 RTW89_EFUSE_BLOCK_SYS = 0, 3258 RTW89_EFUSE_BLOCK_RF = 1, 3259 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3260 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3261 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3262 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3263 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3264 RTW89_EFUSE_BLOCK_ADIE = 7, 3265 3266 RTW89_EFUSE_BLOCK_NUM, 3267 RTW89_EFUSE_BLOCK_IGNORE, 3268 }; 3269 3270 struct rtw89_ra_info { 3271 u8 is_dis_ra:1; 3272 /* Bit0 : CCK 3273 * Bit1 : OFDM 3274 * Bit2 : HT 3275 * Bit3 : VHT 3276 * Bit4 : HE 3277 * Bit5 : EHT 3278 */ 3279 u8 mode_ctrl:6; 3280 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3281 u8 macid; 3282 u8 dcm_cap:1; 3283 u8 er_cap:1; 3284 u8 init_rate_lv:2; 3285 u8 upd_all:1; 3286 u8 en_sgi:1; 3287 u8 ldpc_cap:1; 3288 u8 stbc_cap:1; 3289 u8 ss_num:3; 3290 u8 giltf:3; 3291 u8 upd_bw_nss_mask:1; 3292 u8 upd_mask:1; 3293 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3294 /* BFee CSI */ 3295 u8 band_num; 3296 u8 ra_csi_rate_en:1; 3297 u8 fixed_csi_rate_en:1; 3298 u8 cr_tbl_sel:1; 3299 u8 fix_giltf_en:1; 3300 u8 fix_giltf:3; 3301 u8 rsvd2:1; 3302 u8 csi_mcs_ss_idx; 3303 u8 csi_mode:2; 3304 u8 csi_gi_ltf:3; 3305 u8 csi_bw:3; 3306 }; 3307 3308 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3309 #define RTW89_PPDU_MAC_INFO_SIZE 8 3310 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3311 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3312 3313 #define RTW89_MAX_RX_AGG_NUM 64 3314 #define RTW89_MAX_TX_AGG_NUM 128 3315 3316 struct rtw89_ampdu_params { 3317 u16 agg_num; 3318 bool amsdu; 3319 }; 3320 3321 struct rtw89_ra_report { 3322 struct rate_info txrate; 3323 u32 bit_rate; 3324 u16 hw_rate; 3325 bool might_fallback_legacy; 3326 }; 3327 3328 DECLARE_EWMA(rssi, 10, 16); 3329 DECLARE_EWMA(evm, 10, 16); 3330 DECLARE_EWMA(snr, 10, 16); 3331 3332 struct rtw89_ba_cam_entry { 3333 struct list_head list; 3334 u8 tid; 3335 }; 3336 3337 #define RTW89_MAX_ADDR_CAM_NUM 128 3338 #define RTW89_MAX_BSSID_CAM_NUM 20 3339 #define RTW89_MAX_SEC_CAM_NUM 128 3340 #define RTW89_MAX_BA_CAM_NUM 24 3341 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3342 3343 struct rtw89_addr_cam_entry { 3344 u8 addr_cam_idx; 3345 u8 offset; 3346 u8 len; 3347 u8 valid : 1; 3348 u8 addr_mask : 6; 3349 u8 wapi : 1; 3350 u8 mask_sel : 2; 3351 u8 bssid_cam_idx: 6; 3352 3353 u8 sec_ent_mode; 3354 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3355 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3356 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3357 }; 3358 3359 struct rtw89_bssid_cam_entry { 3360 u8 bssid[ETH_ALEN]; 3361 u8 phy_idx; 3362 u8 bssid_cam_idx; 3363 u8 offset; 3364 u8 len; 3365 u8 valid : 1; 3366 u8 num; 3367 }; 3368 3369 struct rtw89_sec_cam_entry { 3370 u8 sec_cam_idx; 3371 u8 offset; 3372 u8 len; 3373 u8 type : 4; 3374 u8 ext_key : 1; 3375 u8 spp_mode : 1; 3376 /* 256 bits */ 3377 u8 key[32]; 3378 3379 struct ieee80211_key_conf *key_conf; 3380 }; 3381 3382 struct rtw89_sta_link { 3383 struct rtw89_sta *rtwsta; 3384 struct list_head dlink_schd; 3385 unsigned int link_id; 3386 3387 u8 mac_id; 3388 bool er_cap; 3389 struct rtw89_vif_link *rtwvif_link; 3390 struct rtw89_ra_info ra; 3391 struct rtw89_ra_report ra_report; 3392 int max_agg_wait; 3393 u8 prev_rssi; 3394 struct ewma_rssi avg_rssi; 3395 struct ewma_rssi rssi[RF_PATH_MAX]; 3396 struct ewma_snr avg_snr; 3397 struct ewma_evm evm_1ss; 3398 struct ewma_evm evm_min[RF_PATH_MAX]; 3399 struct ewma_evm evm_max[RF_PATH_MAX]; 3400 struct ieee80211_rx_status rx_status; 3401 u16 rx_hw_rate; 3402 __le32 htc_template; 3403 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3404 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3405 struct list_head ba_cam_list; 3406 3407 bool use_cfg_mask; 3408 struct cfg80211_bitrate_mask mask; 3409 3410 bool cctl_tx_time; 3411 u32 ampdu_max_time:4; 3412 bool cctl_tx_retry_limit; 3413 u32 data_tx_cnt_lmt:6; 3414 }; 3415 3416 struct rtw89_efuse { 3417 bool valid; 3418 bool power_k_valid; 3419 u8 xtal_cap; 3420 u8 addr[ETH_ALEN]; 3421 u8 rfe_type; 3422 char country_code[2]; 3423 }; 3424 3425 struct rtw89_phy_rate_pattern { 3426 u64 ra_mask; 3427 u16 rate; 3428 u8 ra_mode; 3429 bool enable; 3430 }; 3431 3432 struct rtw89_tx_wait_info { 3433 struct rcu_head rcu_head; 3434 struct completion completion; 3435 bool tx_done; 3436 }; 3437 3438 struct rtw89_tx_skb_data { 3439 struct rtw89_tx_wait_info __rcu *wait; 3440 u8 hci_priv[]; 3441 }; 3442 3443 #define RTW89_ROC_IDLE_TIMEOUT 500 3444 #define RTW89_ROC_TX_TIMEOUT 30 3445 enum rtw89_roc_state { 3446 RTW89_ROC_IDLE, 3447 RTW89_ROC_NORMAL, 3448 RTW89_ROC_MGMT, 3449 }; 3450 3451 struct rtw89_roc { 3452 struct ieee80211_channel chan; 3453 struct wiphy_delayed_work roc_work; 3454 enum ieee80211_roc_type type; 3455 enum rtw89_roc_state state; 3456 int duration; 3457 unsigned int link_id; 3458 }; 3459 3460 #define RTW89_P2P_MAX_NOA_NUM 2 3461 3462 struct rtw89_p2p_ie_head { 3463 u8 eid; 3464 u8 ie_len; 3465 u8 oui[3]; 3466 u8 oui_type; 3467 } __packed; 3468 3469 struct rtw89_noa_attr_head { 3470 u8 attr_type; 3471 __le16 attr_len; 3472 u8 index; 3473 u8 oppps_ctwindow; 3474 } __packed; 3475 3476 struct rtw89_p2p_noa_ie { 3477 struct rtw89_p2p_ie_head p2p_head; 3478 struct rtw89_noa_attr_head noa_head; 3479 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3480 } __packed; 3481 3482 struct rtw89_p2p_noa_setter { 3483 struct rtw89_p2p_noa_ie ie; 3484 u8 noa_count; 3485 u8 noa_index; 3486 }; 3487 3488 struct rtw89_ps_noa_once_handler { 3489 bool in_duration; 3490 u64 tsf_begin; 3491 u64 tsf_end; 3492 struct wiphy_delayed_work set_work; 3493 struct wiphy_delayed_work clr_work; 3494 }; 3495 3496 struct rtw89_vif_link { 3497 struct rtw89_vif *rtwvif; 3498 struct list_head dlink_schd; 3499 unsigned int link_id; 3500 3501 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3502 enum rtw89_chanctx_idx chanctx_idx; 3503 enum rtw89_reg_6ghz_power reg_6ghz_power; 3504 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3505 3506 u8 mac_id; 3507 u8 port; 3508 u8 mac_addr[ETH_ALEN]; 3509 u8 bssid[ETH_ALEN]; 3510 u8 phy_idx; 3511 u8 mac_idx; 3512 u8 net_type; 3513 u8 wifi_role; 3514 u8 self_role; 3515 u8 wmm; 3516 u8 bcn_hit_cond; 3517 u8 bcn_bw_idx; 3518 u8 hit_rule; 3519 u8 last_noa_nr; 3520 u64 sync_bcn_tsf; 3521 bool rand_tsf_done; 3522 bool trigger; 3523 bool lsig_txop; 3524 u8 tgt_ind; 3525 u8 frm_tgt_ind; 3526 bool wowlan_pattern; 3527 bool wowlan_uc; 3528 bool wowlan_magic; 3529 bool is_hesta; 3530 bool last_a_ctrl; 3531 bool dyn_tb_bedge_en; 3532 bool pre_pwr_diff_en; 3533 bool pwr_diff_en; 3534 u8 def_tri_idx; 3535 struct wiphy_work update_beacon_work; 3536 struct rtw89_addr_cam_entry addr_cam; 3537 struct rtw89_bssid_cam_entry bssid_cam; 3538 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3539 struct rtw89_phy_rate_pattern rate_pattern; 3540 struct list_head general_pkt_list; 3541 struct rtw89_p2p_noa_setter p2p_noa; 3542 struct rtw89_ps_noa_once_handler noa_once; 3543 }; 3544 3545 enum rtw89_lv1_rcvy_step { 3546 RTW89_LV1_RCVY_STEP_1, 3547 RTW89_LV1_RCVY_STEP_2, 3548 }; 3549 3550 struct rtw89_hci_ops { 3551 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3552 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3553 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3554 void (*reset)(struct rtw89_dev *rtwdev); 3555 int (*start)(struct rtw89_dev *rtwdev); 3556 void (*stop)(struct rtw89_dev *rtwdev); 3557 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3558 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3559 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3560 3561 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3562 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3563 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3564 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3565 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3566 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3567 3568 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3569 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3570 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3571 int (*deinit)(struct rtw89_dev *rtwdev); 3572 3573 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3574 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3575 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3576 int (*napi_poll)(struct napi_struct *napi, int budget); 3577 3578 /* Deal with locks inside recovery_start and recovery_complete callbacks 3579 * by hci instance, and handle things which need to consider under SER. 3580 * e.g. turn on/off interrupts except for the one for halt notification. 3581 */ 3582 void (*recovery_start)(struct rtw89_dev *rtwdev); 3583 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3584 3585 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3586 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3587 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3588 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3589 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3590 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3591 void (*disable_intr)(struct rtw89_dev *rtwdev); 3592 void (*enable_intr)(struct rtw89_dev *rtwdev); 3593 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3594 }; 3595 3596 struct rtw89_hci_info { 3597 const struct rtw89_hci_ops *ops; 3598 enum rtw89_hci_type type; 3599 u32 rpwm_addr; 3600 u32 cpwm_addr; 3601 bool paused; 3602 }; 3603 3604 struct rtw89_chip_ops { 3605 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3606 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3607 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3608 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3609 void (*bb_reset)(struct rtw89_dev *rtwdev, 3610 enum rtw89_phy_idx phy_idx); 3611 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3612 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3613 u32 addr, u32 mask); 3614 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3615 u32 addr, u32 mask, u32 data); 3616 void (*set_channel)(struct rtw89_dev *rtwdev, 3617 const struct rtw89_chan *chan, 3618 enum rtw89_mac_idx mac_idx, 3619 enum rtw89_phy_idx phy_idx); 3620 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3621 struct rtw89_channel_help_params *p, 3622 const struct rtw89_chan *chan, 3623 enum rtw89_mac_idx mac_idx, 3624 enum rtw89_phy_idx phy_idx); 3625 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3626 enum rtw89_efuse_block block); 3627 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3628 void (*fem_setup)(struct rtw89_dev *rtwdev); 3629 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3630 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3631 void (*rfk_init)(struct rtw89_dev *rtwdev); 3632 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3633 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3634 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3635 enum rtw89_phy_idx phy_idx, 3636 const struct rtw89_chan *chan); 3637 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3638 bool start); 3639 void (*rfk_track)(struct rtw89_dev *rtwdev); 3640 void (*power_trim)(struct rtw89_dev *rtwdev); 3641 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3642 const struct rtw89_chan *chan, 3643 enum rtw89_phy_idx phy_idx); 3644 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3645 enum rtw89_phy_idx phy_idx); 3646 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3647 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3648 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3649 enum rtw89_phy_idx phy_idx); 3650 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3651 struct rtw89_rx_phy_ppdu *phy_ppdu, 3652 struct ieee80211_rx_status *status); 3653 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3654 struct rtw89_rx_phy_ppdu *phy_ppdu); 3655 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3656 struct rtw89_rx_desc_info *desc_info, 3657 struct ieee80211_rx_status *rx_status); 3658 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3659 enum rtw89_phy_idx phy_idx); 3660 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3661 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3662 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3663 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3664 enum rtw89_phy_idx phy_idx); 3665 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3666 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3667 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3668 struct rtw89_rx_desc_info *desc_info, 3669 u8 *data, u32 data_offset); 3670 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3671 struct rtw89_tx_desc_info *desc_info, 3672 void *txdesc); 3673 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3674 struct rtw89_tx_desc_info *desc_info, 3675 void *txdesc); 3676 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3677 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3678 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3679 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3680 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3681 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3682 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3683 struct rtw89_vif_link *rtwvif_link, 3684 struct rtw89_sta_link *rtwsta_link); 3685 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3686 struct rtw89_vif_link *rtwvif_link, 3687 struct rtw89_sta_link *rtwsta_link); 3688 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3689 struct rtw89_vif_link *rtwvif_link, 3690 struct rtw89_sta_link *rtwsta_link); 3691 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3692 struct rtw89_vif_link *rtwvif_link, 3693 struct rtw89_sta_link *rtwsta_link); 3694 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 3695 struct rtw89_sta_link *rtwsta_link); 3696 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3697 struct rtw89_vif_link *rtwvif_link, 3698 struct rtw89_sta_link *rtwsta_link); 3699 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3700 struct rtw89_vif_link *rtwvif_link); 3701 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3702 struct rtw89_vif_link *rtwvif_link, 3703 struct rtw89_sta_link *rtwsta_link, 3704 bool valid, struct ieee80211_ampdu_params *params); 3705 3706 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3707 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3708 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3709 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3710 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3711 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3712 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3713 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3714 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3715 }; 3716 3717 enum rtw89_dma_ch { 3718 RTW89_DMA_ACH0 = 0, 3719 RTW89_DMA_ACH1 = 1, 3720 RTW89_DMA_ACH2 = 2, 3721 RTW89_DMA_ACH3 = 3, 3722 RTW89_DMA_ACH4 = 4, 3723 RTW89_DMA_ACH5 = 5, 3724 RTW89_DMA_ACH6 = 6, 3725 RTW89_DMA_ACH7 = 7, 3726 RTW89_DMA_B0MG = 8, 3727 RTW89_DMA_B0HI = 9, 3728 RTW89_DMA_B1MG = 10, 3729 RTW89_DMA_B1HI = 11, 3730 RTW89_DMA_H2C = 12, 3731 RTW89_DMA_CH_NUM = 13 3732 }; 3733 3734 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3735 3736 enum rtw89_mlo_dbcc_mode { 3737 MLO_DBCC_NOT_SUPPORT = 1, 3738 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3739 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3740 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3741 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3742 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3743 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3744 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3745 DBCC_LEGACY = 0xffffffff, 3746 }; 3747 3748 enum rtw89_scan_be_operation { 3749 RTW89_SCAN_OP_STOP, 3750 RTW89_SCAN_OP_START, 3751 RTW89_SCAN_OP_SETPARM, 3752 RTW89_SCAN_OP_GETRPT, 3753 RTW89_SCAN_OP_NUM 3754 }; 3755 3756 enum rtw89_scan_be_mode { 3757 RTW89_SCAN_MODE_SA, 3758 RTW89_SCAN_MODE_MACC, 3759 RTW89_SCAN_MODE_NUM 3760 }; 3761 3762 enum rtw89_scan_be_opmode { 3763 RTW89_SCAN_OPMODE_NONE, 3764 RTW89_SCAN_OPMODE_TBTT, 3765 RTW89_SCAN_OPMODE_INTV, 3766 RTW89_SCAN_OPMODE_CNT, 3767 RTW89_SCAN_OPMODE_NUM, 3768 }; 3769 3770 struct rtw89_scan_option { 3771 bool enable; 3772 bool target_ch_mode; 3773 u8 num_macc_role; 3774 u8 num_opch; 3775 u8 repeat; 3776 u16 norm_pd; 3777 u16 slow_pd; 3778 u16 norm_cy; 3779 u8 opch_end; 3780 u16 delay; 3781 u64 prohib_chan; 3782 enum rtw89_phy_idx band; 3783 enum rtw89_scan_be_operation operation; 3784 enum rtw89_scan_be_mode scan_mode; 3785 enum rtw89_mlo_dbcc_mode mlo_mode; 3786 }; 3787 3788 enum rtw89_qta_mode { 3789 RTW89_QTA_SCC, 3790 RTW89_QTA_DBCC, 3791 RTW89_QTA_DLFW, 3792 RTW89_QTA_WOW, 3793 3794 /* keep last */ 3795 RTW89_QTA_INVALID, 3796 }; 3797 3798 struct rtw89_hfc_ch_cfg { 3799 u16 min; 3800 u16 max; 3801 #define grp_0 0 3802 #define grp_1 1 3803 #define grp_num 2 3804 u8 grp; 3805 }; 3806 3807 struct rtw89_hfc_ch_info { 3808 u16 aval; 3809 u16 used; 3810 }; 3811 3812 struct rtw89_hfc_pub_cfg { 3813 u16 grp0; 3814 u16 grp1; 3815 u16 pub_max; 3816 u16 wp_thrd; 3817 }; 3818 3819 struct rtw89_hfc_pub_info { 3820 u16 g0_used; 3821 u16 g1_used; 3822 u16 g0_aval; 3823 u16 g1_aval; 3824 u16 pub_aval; 3825 u16 wp_aval; 3826 }; 3827 3828 struct rtw89_hfc_prec_cfg { 3829 u16 ch011_prec; 3830 u16 h2c_prec; 3831 u16 wp_ch07_prec; 3832 u16 wp_ch811_prec; 3833 u8 ch011_full_cond; 3834 u8 h2c_full_cond; 3835 u8 wp_ch07_full_cond; 3836 u8 wp_ch811_full_cond; 3837 }; 3838 3839 struct rtw89_hfc_param { 3840 bool en; 3841 bool h2c_en; 3842 u8 mode; 3843 const struct rtw89_hfc_ch_cfg *ch_cfg; 3844 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3845 struct rtw89_hfc_pub_cfg pub_cfg; 3846 struct rtw89_hfc_pub_info pub_info; 3847 struct rtw89_hfc_prec_cfg prec_cfg; 3848 }; 3849 3850 struct rtw89_hfc_param_ini { 3851 const struct rtw89_hfc_ch_cfg *ch_cfg; 3852 const struct rtw89_hfc_pub_cfg *pub_cfg; 3853 const struct rtw89_hfc_prec_cfg *prec_cfg; 3854 u8 mode; 3855 }; 3856 3857 struct rtw89_dle_size { 3858 u16 pge_size; 3859 u16 lnk_pge_num; 3860 u16 unlnk_pge_num; 3861 /* for WiFi 7 chips below */ 3862 u32 srt_ofst; 3863 }; 3864 3865 struct rtw89_wde_quota { 3866 u16 hif; 3867 u16 wcpu; 3868 u16 pkt_in; 3869 u16 cpu_io; 3870 }; 3871 3872 struct rtw89_ple_quota { 3873 u16 cma0_tx; 3874 u16 cma1_tx; 3875 u16 c2h; 3876 u16 h2c; 3877 u16 wcpu; 3878 u16 mpdu_proc; 3879 u16 cma0_dma; 3880 u16 cma1_dma; 3881 u16 bb_rpt; 3882 u16 wd_rel; 3883 u16 cpu_io; 3884 u16 tx_rpt; 3885 /* for WiFi 7 chips below */ 3886 u16 h2d; 3887 }; 3888 3889 struct rtw89_rsvd_quota { 3890 u16 mpdu_info_tbl; 3891 u16 b0_csi; 3892 u16 b1_csi; 3893 u16 b0_lmr; 3894 u16 b1_lmr; 3895 u16 b0_ftm; 3896 u16 b1_ftm; 3897 u16 b0_smr; 3898 u16 b1_smr; 3899 u16 others; 3900 }; 3901 3902 struct rtw89_dle_rsvd_size { 3903 u32 srt_ofst; 3904 u32 size; 3905 }; 3906 3907 struct rtw89_dle_mem { 3908 enum rtw89_qta_mode mode; 3909 const struct rtw89_dle_size *wde_size; 3910 const struct rtw89_dle_size *ple_size; 3911 const struct rtw89_wde_quota *wde_min_qt; 3912 const struct rtw89_wde_quota *wde_max_qt; 3913 const struct rtw89_ple_quota *ple_min_qt; 3914 const struct rtw89_ple_quota *ple_max_qt; 3915 /* for WiFi 7 chips below */ 3916 const struct rtw89_rsvd_quota *rsvd_qt; 3917 const struct rtw89_dle_rsvd_size *rsvd0_size; 3918 const struct rtw89_dle_rsvd_size *rsvd1_size; 3919 }; 3920 3921 struct rtw89_reg_def { 3922 u32 addr; 3923 u32 mask; 3924 }; 3925 3926 struct rtw89_reg2_def { 3927 u32 addr; 3928 u32 data; 3929 }; 3930 3931 struct rtw89_reg3_def { 3932 u32 addr; 3933 u32 mask; 3934 u32 data; 3935 }; 3936 3937 struct rtw89_reg5_def { 3938 u8 flag; /* recognized by parsers */ 3939 u8 path; 3940 u32 addr; 3941 u32 mask; 3942 u32 data; 3943 }; 3944 3945 struct rtw89_reg_imr { 3946 u32 addr; 3947 u32 clr; 3948 u32 set; 3949 }; 3950 3951 struct rtw89_phy_table { 3952 const struct rtw89_reg2_def *regs; 3953 u32 n_regs; 3954 enum rtw89_rf_path rf_path; 3955 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3956 enum rtw89_rf_path rf_path, void *data); 3957 }; 3958 3959 struct rtw89_txpwr_table { 3960 const void *data; 3961 u32 size; 3962 void (*load)(struct rtw89_dev *rtwdev, 3963 const struct rtw89_txpwr_table *tbl); 3964 }; 3965 3966 struct rtw89_txpwr_rule_2ghz { 3967 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3968 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3969 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3970 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3971 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3972 }; 3973 3974 struct rtw89_txpwr_rule_5ghz { 3975 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3976 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3977 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3978 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3979 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3980 }; 3981 3982 struct rtw89_txpwr_rule_6ghz { 3983 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3984 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3985 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3986 [RTW89_6G_CH_NUM]; 3987 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3988 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3989 [RTW89_6G_CH_NUM]; 3990 }; 3991 3992 struct rtw89_tx_shape { 3993 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3994 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3995 }; 3996 3997 struct rtw89_rfe_parms { 3998 const struct rtw89_txpwr_table *byr_tbl; 3999 struct rtw89_txpwr_rule_2ghz rule_2ghz; 4000 struct rtw89_txpwr_rule_5ghz rule_5ghz; 4001 struct rtw89_txpwr_rule_6ghz rule_6ghz; 4002 struct rtw89_txpwr_rule_2ghz rule_da_2ghz; 4003 struct rtw89_txpwr_rule_5ghz rule_da_5ghz; 4004 struct rtw89_txpwr_rule_6ghz rule_da_6ghz; 4005 struct rtw89_tx_shape tx_shape; 4006 bool has_da; 4007 }; 4008 4009 struct rtw89_rfe_parms_conf { 4010 const struct rtw89_rfe_parms *rfe_parms; 4011 u8 rfe_type; 4012 }; 4013 4014 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 4015 4016 struct rtw89_txpwr_conf { 4017 u8 rfe_type; 4018 u8 ent_sz; 4019 u32 num_ents; 4020 const void *data; 4021 }; 4022 4023 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4024 const struct rtw89_txpwr_conf *conf) 4025 { 4026 u8 valid_size = min(size, conf->ent_sz); 4027 4028 memcpy(entry, cursor, valid_size); 4029 return true; 4030 } 4031 4032 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4033 4034 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4035 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4036 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4037 (cursor) += (conf)->ent_sz) \ 4038 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4039 4040 struct rtw89_txpwr_byrate_data { 4041 struct rtw89_txpwr_conf conf; 4042 struct rtw89_txpwr_table tbl; 4043 }; 4044 4045 struct rtw89_txpwr_lmt_2ghz_data { 4046 struct rtw89_txpwr_conf conf; 4047 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4048 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4049 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4050 }; 4051 4052 struct rtw89_txpwr_lmt_5ghz_data { 4053 struct rtw89_txpwr_conf conf; 4054 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4055 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4056 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4057 }; 4058 4059 struct rtw89_txpwr_lmt_6ghz_data { 4060 struct rtw89_txpwr_conf conf; 4061 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4062 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4063 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4064 [RTW89_6G_CH_NUM]; 4065 }; 4066 4067 struct rtw89_txpwr_lmt_ru_2ghz_data { 4068 struct rtw89_txpwr_conf conf; 4069 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4070 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4071 }; 4072 4073 struct rtw89_txpwr_lmt_ru_5ghz_data { 4074 struct rtw89_txpwr_conf conf; 4075 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4076 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4077 }; 4078 4079 struct rtw89_txpwr_lmt_ru_6ghz_data { 4080 struct rtw89_txpwr_conf conf; 4081 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4082 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4083 [RTW89_6G_CH_NUM]; 4084 }; 4085 4086 struct rtw89_tx_shape_lmt_data { 4087 struct rtw89_txpwr_conf conf; 4088 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4089 }; 4090 4091 struct rtw89_tx_shape_lmt_ru_data { 4092 struct rtw89_txpwr_conf conf; 4093 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4094 }; 4095 4096 struct rtw89_rfe_data { 4097 struct rtw89_txpwr_byrate_data byrate; 4098 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4099 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4100 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4101 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz; 4102 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz; 4103 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz; 4104 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4105 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4106 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4107 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz; 4108 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz; 4109 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz; 4110 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4111 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4112 struct rtw89_rfe_parms rfe_parms; 4113 }; 4114 4115 struct rtw89_page_regs { 4116 u32 hci_fc_ctrl; 4117 u32 ch_page_ctrl; 4118 u32 ach_page_ctrl; 4119 u32 ach_page_info; 4120 u32 pub_page_info3; 4121 u32 pub_page_ctrl1; 4122 u32 pub_page_ctrl2; 4123 u32 pub_page_info1; 4124 u32 pub_page_info2; 4125 u32 wp_page_ctrl1; 4126 u32 wp_page_ctrl2; 4127 u32 wp_page_info1; 4128 }; 4129 4130 struct rtw89_imr_info { 4131 u32 wdrls_imr_set; 4132 u32 wsec_imr_reg; 4133 u32 wsec_imr_set; 4134 u32 mpdu_tx_imr_set; 4135 u32 mpdu_rx_imr_set; 4136 u32 sta_sch_imr_set; 4137 u32 txpktctl_imr_b0_reg; 4138 u32 txpktctl_imr_b0_clr; 4139 u32 txpktctl_imr_b0_set; 4140 u32 txpktctl_imr_b1_reg; 4141 u32 txpktctl_imr_b1_clr; 4142 u32 txpktctl_imr_b1_set; 4143 u32 wde_imr_clr; 4144 u32 wde_imr_set; 4145 u32 ple_imr_clr; 4146 u32 ple_imr_set; 4147 u32 host_disp_imr_clr; 4148 u32 host_disp_imr_set; 4149 u32 cpu_disp_imr_clr; 4150 u32 cpu_disp_imr_set; 4151 u32 other_disp_imr_clr; 4152 u32 other_disp_imr_set; 4153 u32 bbrpt_com_err_imr_reg; 4154 u32 bbrpt_chinfo_err_imr_reg; 4155 u32 bbrpt_err_imr_set; 4156 u32 bbrpt_dfs_err_imr_reg; 4157 u32 ptcl_imr_clr; 4158 u32 ptcl_imr_set; 4159 u32 cdma_imr_0_reg; 4160 u32 cdma_imr_0_clr; 4161 u32 cdma_imr_0_set; 4162 u32 cdma_imr_1_reg; 4163 u32 cdma_imr_1_clr; 4164 u32 cdma_imr_1_set; 4165 u32 phy_intf_imr_reg; 4166 u32 phy_intf_imr_clr; 4167 u32 phy_intf_imr_set; 4168 u32 rmac_imr_reg; 4169 u32 rmac_imr_clr; 4170 u32 rmac_imr_set; 4171 u32 tmac_imr_reg; 4172 u32 tmac_imr_clr; 4173 u32 tmac_imr_set; 4174 }; 4175 4176 struct rtw89_imr_table { 4177 const struct rtw89_reg_imr *regs; 4178 u32 n_regs; 4179 }; 4180 4181 struct rtw89_xtal_info { 4182 u32 xcap_reg; 4183 u32 sc_xo_mask; 4184 u32 sc_xi_mask; 4185 }; 4186 4187 struct rtw89_rrsr_cfgs { 4188 struct rtw89_reg3_def ref_rate; 4189 struct rtw89_reg3_def rsc; 4190 }; 4191 4192 struct rtw89_rfkill_regs { 4193 struct rtw89_reg3_def pinmux; 4194 struct rtw89_reg3_def mode; 4195 }; 4196 4197 struct rtw89_dig_regs { 4198 u32 seg0_pd_reg; 4199 u32 pd_lower_bound_mask; 4200 u32 pd_spatial_reuse_en; 4201 u32 bmode_pd_reg; 4202 u32 bmode_cca_rssi_limit_en; 4203 u32 bmode_pd_lower_bound_reg; 4204 u32 bmode_rssi_nocca_low_th_mask; 4205 struct rtw89_reg_def p0_lna_init; 4206 struct rtw89_reg_def p1_lna_init; 4207 struct rtw89_reg_def p0_tia_init; 4208 struct rtw89_reg_def p1_tia_init; 4209 struct rtw89_reg_def p0_rxb_init; 4210 struct rtw89_reg_def p1_rxb_init; 4211 struct rtw89_reg_def p0_p20_pagcugc_en; 4212 struct rtw89_reg_def p0_s20_pagcugc_en; 4213 struct rtw89_reg_def p1_p20_pagcugc_en; 4214 struct rtw89_reg_def p1_s20_pagcugc_en; 4215 }; 4216 4217 struct rtw89_edcca_regs { 4218 u32 edcca_level; 4219 u32 edcca_mask; 4220 u32 edcca_p_mask; 4221 u32 ppdu_level; 4222 u32 ppdu_mask; 4223 struct rtw89_edcca_p_regs { 4224 u32 rpt_a; 4225 u32 rpt_b; 4226 u32 rpt_sel; 4227 u32 rpt_sel_mask; 4228 } p[RTW89_PHY_NUM]; 4229 u32 rpt_sel_be; 4230 u32 rpt_sel_be_mask; 4231 u32 tx_collision_t2r_st; 4232 u32 tx_collision_t2r_st_mask; 4233 }; 4234 4235 struct rtw89_phy_ul_tb_info { 4236 bool dyn_tb_tri_en; 4237 u8 def_if_bandedge; 4238 }; 4239 4240 struct rtw89_antdiv_stats { 4241 struct ewma_rssi cck_rssi_avg; 4242 struct ewma_rssi ofdm_rssi_avg; 4243 struct ewma_rssi non_legacy_rssi_avg; 4244 u16 pkt_cnt_cck; 4245 u16 pkt_cnt_ofdm; 4246 u16 pkt_cnt_non_legacy; 4247 u32 evm; 4248 }; 4249 4250 struct rtw89_antdiv_info { 4251 struct rtw89_antdiv_stats target_stats; 4252 struct rtw89_antdiv_stats main_stats; 4253 struct rtw89_antdiv_stats aux_stats; 4254 u8 training_count; 4255 u8 rssi_pre; 4256 bool get_stats; 4257 }; 4258 4259 enum rtw89_chanctx_state { 4260 RTW89_CHANCTX_STATE_MCC_START, 4261 RTW89_CHANCTX_STATE_MCC_STOP, 4262 }; 4263 4264 enum rtw89_chanctx_callbacks { 4265 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4266 RTW89_CHANCTX_CALLBACK_RFK, 4267 RTW89_CHANCTX_CALLBACK_TAS, 4268 4269 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4270 }; 4271 4272 struct rtw89_chanctx_listener { 4273 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4274 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4275 }; 4276 4277 struct rtw89_chip_info { 4278 enum rtw89_core_chip_id chip_id; 4279 enum rtw89_chip_gen chip_gen; 4280 const struct rtw89_chip_ops *ops; 4281 const struct rtw89_mac_gen_def *mac_def; 4282 const struct rtw89_phy_gen_def *phy_def; 4283 const char *fw_basename; 4284 u8 fw_format_max; 4285 bool try_ce_fw; 4286 u8 bbmcu_nr; 4287 u32 needed_fw_elms; 4288 const struct rtw89_fw_blacklist *fw_blacklist; 4289 u32 fifo_size; 4290 bool small_fifo_size; 4291 u32 dle_scc_rsvd_size; 4292 u16 max_amsdu_limit; 4293 bool dis_2g_40m_ul_ofdma; 4294 u32 rsvd_ple_ofst; 4295 const struct rtw89_hfc_param_ini *hfc_param_ini; 4296 const struct rtw89_dle_mem *dle_mem; 4297 u8 wde_qempty_acq_grpnum; 4298 u8 wde_qempty_mgq_grpsel; 4299 u32 rf_base_addr[2]; 4300 u8 thermal_th[2]; 4301 u8 support_macid_num; 4302 u8 support_link_num; 4303 u8 support_chanctx_num; 4304 u8 support_bands; 4305 u16 support_bandwidths; 4306 bool support_unii4; 4307 bool support_rnr; 4308 bool support_ant_gain; 4309 bool support_tas; 4310 bool support_sar_by_ant; 4311 bool ul_tb_waveform_ctrl; 4312 bool ul_tb_pwr_diff; 4313 bool rx_freq_frome_ie; 4314 bool hw_sec_hdr; 4315 bool hw_mgmt_tx_encrypt; 4316 bool hw_tkip_crypto; 4317 bool hw_mlo_bmc_crypto; 4318 u8 rf_path_num; 4319 u8 tx_nss; 4320 u8 rx_nss; 4321 u8 acam_num; 4322 u8 bcam_num; 4323 u8 scam_num; 4324 u8 bacam_num; 4325 u8 bacam_dynamic_num; 4326 enum rtw89_bacam_ver bacam_ver; 4327 u8 ppdu_max_usr; 4328 4329 u8 sec_ctrl_efuse_size; 4330 u32 physical_efuse_size; 4331 u32 logical_efuse_size; 4332 u32 limit_efuse_size; 4333 u32 dav_phy_efuse_size; 4334 u32 dav_log_efuse_size; 4335 u32 phycap_addr; 4336 u32 phycap_size; 4337 const struct rtw89_efuse_block_cfg *efuse_blocks; 4338 4339 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4340 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4341 const struct rtw89_phy_table *bb_table; 4342 const struct rtw89_phy_table *bb_gain_table; 4343 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4344 const struct rtw89_phy_table *nctl_table; 4345 const struct rtw89_rfk_tbl *nctl_post_table; 4346 const struct rtw89_phy_dig_gain_table *dig_table; 4347 const struct rtw89_dig_regs *dig_regs; 4348 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4349 4350 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4351 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4352 const struct rtw89_rfe_parms *dflt_parms; 4353 const struct rtw89_chanctx_listener *chanctx_listener; 4354 4355 u8 txpwr_factor_bb; 4356 u8 txpwr_factor_rf; 4357 u8 txpwr_factor_mac; 4358 4359 u32 para_ver; 4360 u32 wlcx_desired; 4361 u8 btcx_desired; 4362 u8 scbd; 4363 u8 mailbox; 4364 4365 u8 afh_guard_ch; 4366 const u8 *wl_rssi_thres; 4367 const u8 *bt_rssi_thres; 4368 u8 rssi_tol; 4369 4370 u8 mon_reg_num; 4371 const struct rtw89_btc_fbtc_mreg *mon_reg; 4372 u8 rf_para_ulink_num; 4373 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4374 u8 rf_para_dlink_num; 4375 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4376 u8 ps_mode_supported; 4377 u8 low_power_hci_modes; 4378 4379 u32 h2c_cctl_func_id; 4380 u32 hci_func_en_addr; 4381 u32 h2c_desc_size; 4382 u32 txwd_body_size; 4383 u32 txwd_info_size; 4384 u32 h2c_ctrl_reg; 4385 const u32 *h2c_regs; 4386 struct rtw89_reg_def h2c_counter_reg; 4387 u32 c2h_ctrl_reg; 4388 const u32 *c2h_regs; 4389 struct rtw89_reg_def c2h_counter_reg; 4390 const struct rtw89_page_regs *page_regs; 4391 const u32 *wow_reason_reg; 4392 bool cfo_src_fd; 4393 bool cfo_hw_comp; 4394 const struct rtw89_reg_def *dcfo_comp; 4395 u8 dcfo_comp_sft; 4396 const struct rtw89_imr_info *imr_info; 4397 const struct rtw89_imr_table *imr_dmac_table; 4398 const struct rtw89_imr_table *imr_cmac_table; 4399 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4400 struct rtw89_reg_def bss_clr_vld; 4401 u32 bss_clr_map_reg; 4402 const struct rtw89_rfkill_regs *rfkill_init; 4403 struct rtw89_reg_def rfkill_get; 4404 u32 dma_ch_mask; 4405 const struct rtw89_edcca_regs *edcca_regs; 4406 const struct wiphy_wowlan_support *wowlan_stub; 4407 const struct rtw89_xtal_info *xtal_info; 4408 }; 4409 4410 struct rtw89_chip_variant { 4411 bool no_mcs_12_13: 1; 4412 u32 fw_min_ver_code; 4413 }; 4414 4415 union rtw89_bus_info { 4416 const struct rtw89_pci_info *pci; 4417 }; 4418 4419 struct rtw89_driver_info { 4420 const struct rtw89_chip_info *chip; 4421 const struct rtw89_chip_variant *variant; 4422 const struct dmi_system_id *quirks; 4423 union rtw89_bus_info bus; 4424 }; 4425 4426 enum rtw89_hcifc_mode { 4427 RTW89_HCIFC_POH = 0, 4428 RTW89_HCIFC_STF = 1, 4429 RTW89_HCIFC_SDIO = 2, 4430 4431 /* keep last */ 4432 RTW89_HCIFC_MODE_INVALID, 4433 }; 4434 4435 struct rtw89_dle_info { 4436 const struct rtw89_rsvd_quota *rsvd_qt; 4437 enum rtw89_qta_mode qta_mode; 4438 u16 ple_pg_size; 4439 u16 ple_free_pg; 4440 u16 c0_rx_qta; 4441 u16 c1_rx_qta; 4442 }; 4443 4444 enum rtw89_host_rpr_mode { 4445 RTW89_RPR_MODE_POH = 0, 4446 RTW89_RPR_MODE_STF 4447 }; 4448 4449 #define RTW89_COMPLETION_BUF_SIZE 40 4450 #define RTW89_WAIT_COND_IDLE UINT_MAX 4451 4452 struct rtw89_completion_data { 4453 bool err; 4454 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4455 }; 4456 4457 struct rtw89_wait_info { 4458 atomic_t cond; 4459 struct completion completion; 4460 struct rtw89_completion_data data; 4461 }; 4462 4463 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4464 4465 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4466 { 4467 init_completion(&wait->completion); 4468 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4469 } 4470 4471 struct rtw89_mac_info { 4472 struct rtw89_dle_info dle_info; 4473 struct rtw89_hfc_param hfc_param; 4474 enum rtw89_qta_mode qta_mode; 4475 u8 rpwm_seq_num; 4476 u8 cpwm_seq_num; 4477 4478 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4479 struct rtw89_wait_info fw_ofld_wait; 4480 /* see RTW89_PS_WAIT_COND series for wait condition */ 4481 struct rtw89_wait_info ps_wait; 4482 }; 4483 4484 enum rtw89_fwdl_check_type { 4485 RTW89_FWDL_CHECK_FREERTOS_DONE, 4486 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4487 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4488 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4489 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4490 }; 4491 4492 enum rtw89_fw_type { 4493 RTW89_FW_NORMAL = 1, 4494 RTW89_FW_WOWLAN = 3, 4495 RTW89_FW_NORMAL_CE = 5, 4496 RTW89_FW_BBMCU0 = 64, 4497 RTW89_FW_BBMCU1 = 65, 4498 RTW89_FW_LOGFMT = 255, 4499 }; 4500 4501 enum rtw89_fw_feature { 4502 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4503 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4504 RTW89_FW_FEATURE_TX_WAKE, 4505 RTW89_FW_FEATURE_CRASH_TRIGGER, 4506 RTW89_FW_FEATURE_NO_PACKET_DROP, 4507 RTW89_FW_FEATURE_NO_DEEP_PS, 4508 RTW89_FW_FEATURE_NO_LPS_PG, 4509 RTW89_FW_FEATURE_BEACON_FILTER, 4510 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4511 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4512 RTW89_FW_FEATURE_WOW_REASON_V1, 4513 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4514 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4515 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4516 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4517 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4518 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4519 RTW89_FW_FEATURE_LPS_CH_INFO, 4520 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4521 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 4522 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1, 4523 }; 4524 4525 struct rtw89_fw_suit { 4526 enum rtw89_fw_type type; 4527 const u8 *data; 4528 u32 size; 4529 u8 major_ver; 4530 u8 minor_ver; 4531 u8 sub_ver; 4532 u8 sub_idex; 4533 u16 build_year; 4534 u16 build_mon; 4535 u16 build_date; 4536 u16 build_hour; 4537 u16 build_min; 4538 u8 cmd_ver; 4539 u8 hdr_ver; 4540 u32 commitid; 4541 }; 4542 4543 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4544 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4545 #define RTW89_FW_SUIT_VER_CODE(s) \ 4546 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4547 4548 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4549 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4550 (mfw_hdr)->ver.minor, \ 4551 (mfw_hdr)->ver.sub, \ 4552 (mfw_hdr)->ver.idx) 4553 4554 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4555 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4556 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4557 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4558 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4559 4560 struct rtw89_fw_req_info { 4561 const struct firmware *firmware; 4562 struct completion completion; 4563 }; 4564 4565 struct rtw89_fw_log { 4566 struct rtw89_fw_suit suit; 4567 bool enable; 4568 u32 last_fmt_id; 4569 u32 fmt_count; 4570 const __le32 *fmt_ids; 4571 const char *(*fmts)[]; 4572 }; 4573 4574 struct rtw89_fw_elm_info { 4575 struct rtw89_phy_table *bb_tbl; 4576 struct rtw89_phy_table *bb_gain; 4577 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4578 struct rtw89_phy_table *rf_nctl; 4579 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4580 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4581 const struct rtw89_regd_data *regd; 4582 }; 4583 4584 enum rtw89_fw_mss_dev_type { 4585 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4586 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4587 }; 4588 4589 struct rtw89_fw_secure { 4590 bool secure_boot: 1; 4591 bool can_mss_v1: 1; 4592 bool can_mss_v0: 1; 4593 u32 sb_sel_mgn; 4594 u8 mss_dev_type; 4595 u8 mss_cust_idx; 4596 u8 mss_key_num; 4597 u8 mss_idx; /* v0 */ 4598 }; 4599 4600 struct rtw89_fw_info { 4601 struct rtw89_fw_req_info req; 4602 int fw_format; 4603 u8 h2c_seq; 4604 u8 rec_seq; 4605 u8 h2c_counter; 4606 u8 c2h_counter; 4607 struct rtw89_fw_suit normal; 4608 struct rtw89_fw_suit wowlan; 4609 struct rtw89_fw_suit bbmcu0; 4610 struct rtw89_fw_suit bbmcu1; 4611 struct rtw89_fw_log log; 4612 u32 feature_map; 4613 struct rtw89_fw_elm_info elm_info; 4614 struct rtw89_fw_secure sec; 4615 }; 4616 4617 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4618 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4619 4620 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4621 ((_fw)->feature_map |= BIT(_fw_feature)) 4622 4623 struct rtw89_cam_info { 4624 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4625 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4626 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4627 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4628 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4629 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4630 }; 4631 4632 enum rtw89_sar_sources { 4633 RTW89_SAR_SOURCE_NONE, 4634 RTW89_SAR_SOURCE_COMMON, 4635 RTW89_SAR_SOURCE_ACPI, 4636 4637 RTW89_SAR_SOURCE_NR, 4638 }; 4639 4640 enum rtw89_sar_subband { 4641 RTW89_SAR_2GHZ_SUBBAND, 4642 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4643 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4644 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4645 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4646 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4647 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4648 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4649 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4650 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4651 4652 RTW89_SAR_SUBBAND_NR, 4653 }; 4654 4655 struct rtw89_sar_cfg_common { 4656 bool set[RTW89_SAR_SUBBAND_NR]; 4657 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4658 }; 4659 4660 enum rtw89_acpi_sar_subband { 4661 RTW89_ACPI_SAR_2GHZ_SUBBAND, 4662 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */ 4663 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */ 4664 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4665 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4666 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4667 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4668 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4669 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4670 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4671 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4672 4673 NUM_OF_RTW89_ACPI_SAR_SUBBAND, 4674 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1, 4675 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1, 4676 }; 4677 4678 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */ 4679 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX 4680 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN 4681 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6 4682 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1) 4683 4684 struct rtw89_sar_entry_from_acpi { 4685 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4686 }; 4687 4688 struct rtw89_sar_table_from_acpi { 4689 /* If this table is active, must fill all fields according to either 4690 * configuration in BIOS or some default values for SAR to work well. 4691 */ 4692 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM]; 4693 }; 4694 4695 struct rtw89_sar_indicator_from_acpi { 4696 bool enable_sync; 4697 unsigned int fields; 4698 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath); 4699 4700 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path. 4701 * Not design with pointers since addresses will be invalid after 4702 * sync content with local container instance. 4703 */ 4704 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4705 }; 4706 4707 struct rtw89_sar_cfg_acpi { 4708 u8 downgrade_2tx; 4709 unsigned int valid_num; 4710 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL]; 4711 struct rtw89_sar_indicator_from_acpi indicator; 4712 }; 4713 4714 struct rtw89_sar_info { 4715 /* used to decide how to access SAR cfg union */ 4716 enum rtw89_sar_sources src; 4717 4718 /* reserved for different knids of SAR cfg struct. 4719 * supposed that a single cfg struct cannot handle various SAR sources. 4720 */ 4721 union { 4722 struct rtw89_sar_cfg_common cfg_common; 4723 struct rtw89_sar_cfg_acpi cfg_acpi; 4724 }; 4725 }; 4726 4727 enum rtw89_ant_gain_subband { 4728 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4729 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4730 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4731 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4732 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4733 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4734 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4735 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4736 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4737 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4738 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4739 4740 RTW89_ANT_GAIN_SUBBAND_NR, 4741 }; 4742 4743 enum rtw89_ant_gain_domain_type { 4744 RTW89_ANT_GAIN_ETSI = 0, 4745 4746 RTW89_ANT_GAIN_DOMAIN_NUM, 4747 }; 4748 4749 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4750 struct rtw89_ant_gain_info { 4751 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4752 u32 regd_enabled; 4753 bool block_country; 4754 }; 4755 4756 struct rtw89_6ghz_span { 4757 enum rtw89_sar_subband sar_subband_low; 4758 enum rtw89_sar_subband sar_subband_high; 4759 enum rtw89_acpi_sar_subband acpi_sar_subband_low; 4760 enum rtw89_acpi_sar_subband acpi_sar_subband_high; 4761 enum rtw89_ant_gain_subband ant_gain_subband_low; 4762 enum rtw89_ant_gain_subband ant_gain_subband_high; 4763 }; 4764 4765 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4766 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high) 4767 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4768 4769 enum rtw89_tas_state { 4770 RTW89_TAS_STATE_DPR_OFF, 4771 RTW89_TAS_STATE_DPR_ON, 4772 RTW89_TAS_STATE_STATIC_SAR, 4773 }; 4774 4775 #define RTW89_TAS_TX_RATIO_WINDOW 6 4776 #define RTW89_TAS_TXPWR_WINDOW 180 4777 struct rtw89_tas_info { 4778 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 4779 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 4780 u8 enabled_countries; 4781 u8 txpwr_head_idx; 4782 u8 txpwr_tail_idx; 4783 u8 tx_ratio_idx; 4784 u16 total_tx_ratio; 4785 u64 total_txpwr; 4786 u64 instant_txpwr; 4787 u32 window_size; 4788 s8 dpr_on_threshold; 4789 s8 dpr_off_threshold; 4790 enum rtw89_tas_state backup_state; 4791 enum rtw89_tas_state state; 4792 bool keep_history; 4793 bool block_regd; 4794 bool enable; 4795 bool pause; 4796 }; 4797 4798 struct rtw89_chanctx_cfg { 4799 enum rtw89_chanctx_idx idx; 4800 int ref_count; 4801 }; 4802 4803 enum rtw89_chanctx_changes { 4804 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4805 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4806 RTW89_CHANCTX_P2P_PS_CHANGE, 4807 RTW89_CHANCTX_BT_SLOT_CHANGE, 4808 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4809 4810 NUM_OF_RTW89_CHANCTX_CHANGES, 4811 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4812 }; 4813 4814 enum rtw89_entity_mode { 4815 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4816 RTW89_ENTITY_MODE_MCC_PREPARE, 4817 RTW89_ENTITY_MODE_MCC, 4818 4819 NUM_OF_RTW89_ENTITY_MODE, 4820 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4821 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4822 }; 4823 4824 #define RTW89_MAX_INTERFACE_NUM 2 4825 4826 /* only valid when running with chanctx_ops */ 4827 struct rtw89_entity_mgnt { 4828 struct list_head active_list; 4829 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4830 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4831 [__RTW89_MLD_MAX_LINK_NUM]; 4832 }; 4833 4834 struct rtw89_chanctx { 4835 struct cfg80211_chan_def chandef; 4836 struct rtw89_chan chan; 4837 struct rtw89_chan_rcd rcd; 4838 4839 /* only assigned when running with chanctx_ops */ 4840 struct rtw89_chanctx_cfg *cfg; 4841 }; 4842 4843 struct rtw89_edcca_bak { 4844 u8 a; 4845 u8 p; 4846 u8 ppdu; 4847 u8 th_old; 4848 }; 4849 4850 enum rtw89_dm_type { 4851 RTW89_DM_DYNAMIC_EDCCA, 4852 RTW89_DM_THERMAL_PROTECT, 4853 RTW89_DM_TAS, 4854 RTW89_DM_MLO, 4855 }; 4856 4857 #define RTW89_THERMAL_PROT_LV_MAX 5 4858 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 4859 4860 struct rtw89_hal { 4861 u32 rx_fltr; 4862 u8 cv; 4863 u8 acv; 4864 u32 antenna_tx; 4865 u32 antenna_rx; 4866 u8 tx_nss; 4867 u8 rx_nss; 4868 bool tx_path_diversity; 4869 bool ant_diversity; 4870 bool ant_diversity_fixed; 4871 bool support_cckpd; 4872 bool support_igi; 4873 bool no_mcs_12_13; 4874 4875 atomic_t roc_chanctx_idx; 4876 u8 roc_link_index; 4877 4878 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4879 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4880 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4881 struct cfg80211_chan_def roc_chandef; 4882 4883 bool entity_active[RTW89_PHY_NUM]; 4884 bool entity_pause; 4885 enum rtw89_entity_mode entity_mode; 4886 struct rtw89_entity_mgnt entity_mgnt; 4887 4888 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4889 4890 u8 thermal_prot_th; 4891 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 4892 }; 4893 4894 #define RTW89_MAX_MAC_ID_NUM 128 4895 #define RTW89_MAX_PKT_OFLD_NUM 255 4896 4897 enum rtw89_flags { 4898 RTW89_FLAG_POWERON, 4899 RTW89_FLAG_DMAC_FUNC, 4900 RTW89_FLAG_CMAC0_FUNC, 4901 RTW89_FLAG_CMAC1_FUNC, 4902 RTW89_FLAG_FW_RDY, 4903 RTW89_FLAG_RUNNING, 4904 RTW89_FLAG_PROBE_DONE, 4905 RTW89_FLAG_BFEE_MON, 4906 RTW89_FLAG_BFEE_EN, 4907 RTW89_FLAG_BFEE_TIMER_KEEP, 4908 RTW89_FLAG_NAPI_RUNNING, 4909 RTW89_FLAG_LEISURE_PS, 4910 RTW89_FLAG_LOW_POWER_MODE, 4911 RTW89_FLAG_INACTIVE_PS, 4912 RTW89_FLAG_CRASH_SIMULATING, 4913 RTW89_FLAG_SER_HANDLING, 4914 RTW89_FLAG_WOWLAN, 4915 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4916 RTW89_FLAG_CHANGING_INTERFACE, 4917 RTW89_FLAG_HW_RFKILL_STATE, 4918 4919 NUM_OF_RTW89_FLAGS, 4920 }; 4921 4922 enum rtw89_quirks { 4923 RTW89_QUIRK_PCI_BER, 4924 RTW89_QUIRK_THERMAL_PROT_120C, 4925 RTW89_QUIRK_THERMAL_PROT_110C, 4926 4927 NUM_OF_RTW89_QUIRKS, 4928 }; 4929 4930 enum rtw89_custid { 4931 RTW89_CUSTID_NONE, 4932 RTW89_CUSTID_ACER, 4933 RTW89_CUSTID_AMD, 4934 RTW89_CUSTID_ASUS, 4935 RTW89_CUSTID_DELL, 4936 RTW89_CUSTID_HP, 4937 RTW89_CUSTID_LENOVO, 4938 }; 4939 4940 enum rtw89_pkt_drop_sel { 4941 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4942 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4943 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4944 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4945 RTW89_PKT_DROP_SEL_MACID_ALL, 4946 RTW89_PKT_DROP_SEL_MG0_ONCE, 4947 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4948 RTW89_PKT_DROP_SEL_HIQ_PORT, 4949 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4950 RTW89_PKT_DROP_SEL_BAND, 4951 RTW89_PKT_DROP_SEL_BAND_ONCE, 4952 RTW89_PKT_DROP_SEL_REL_MACID, 4953 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4954 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4955 }; 4956 4957 struct rtw89_pkt_drop_params { 4958 enum rtw89_pkt_drop_sel sel; 4959 enum rtw89_mac_idx mac_band; 4960 u8 macid; 4961 u8 port; 4962 u8 mbssid; 4963 bool tf_trs; 4964 u32 macid_band_sel[4]; 4965 }; 4966 4967 struct rtw89_pkt_stat { 4968 u16 beacon_nr; 4969 u8 beacon_rate; 4970 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4971 }; 4972 4973 DECLARE_EWMA(thermal, 4, 4); 4974 4975 struct rtw89_phy_stat { 4976 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4977 u8 last_thermal_max; 4978 struct ewma_rssi bcn_rssi; 4979 struct rtw89_pkt_stat cur_pkt_stat; 4980 struct rtw89_pkt_stat last_pkt_stat; 4981 }; 4982 4983 enum rtw89_rfk_report_state { 4984 RTW89_RFK_STATE_START = 0x0, 4985 RTW89_RFK_STATE_OK = 0x1, 4986 RTW89_RFK_STATE_FAIL = 0x2, 4987 RTW89_RFK_STATE_TIMEOUT = 0x3, 4988 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4989 }; 4990 4991 struct rtw89_rfk_wait_info { 4992 struct completion completion; 4993 ktime_t start_time; 4994 enum rtw89_rfk_report_state state; 4995 u8 version; 4996 }; 4997 4998 #define RTW89_DACK_PATH_NR 2 4999 #define RTW89_DACK_IDX_NR 2 5000 #define RTW89_DACK_MSBK_NR 16 5001 struct rtw89_dack_info { 5002 bool dack_done; 5003 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 5004 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5005 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5006 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5007 u32 dack_cnt; 5008 bool addck_timeout[RTW89_DACK_PATH_NR]; 5009 bool dadck_timeout[RTW89_DACK_PATH_NR]; 5010 bool msbk_timeout[RTW89_DACK_PATH_NR]; 5011 }; 5012 5013 enum rtw89_rfk_chs_nrs { 5014 __RTW89_RFK_CHS_NR_V0 = 2, 5015 __RTW89_RFK_CHS_NR_V1 = 3, 5016 5017 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 5018 }; 5019 5020 struct rtw89_rfk_mcc_info_data { 5021 u8 ch[RTW89_RFK_CHS_NR]; 5022 u8 band[RTW89_RFK_CHS_NR]; 5023 u8 bw[RTW89_RFK_CHS_NR]; 5024 u8 table_idx; 5025 }; 5026 5027 struct rtw89_rfk_mcc_info { 5028 struct rtw89_rfk_mcc_info_data data[2]; 5029 }; 5030 5031 #define RTW89_IQK_CHS_NR 2 5032 #define RTW89_IQK_PATH_NR 4 5033 5034 struct rtw89_lck_info { 5035 u8 thermal[RF_PATH_MAX]; 5036 }; 5037 5038 struct rtw89_rx_dck_info { 5039 u8 thermal[RF_PATH_MAX]; 5040 }; 5041 5042 struct rtw89_iqk_info { 5043 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5044 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5045 bool lok_fail[RTW89_IQK_PATH_NR]; 5046 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5047 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5048 u32 iqk_fail_cnt; 5049 bool is_iqk_init; 5050 u32 iqk_channel[RTW89_IQK_CHS_NR]; 5051 u8 iqk_band[RTW89_IQK_PATH_NR]; 5052 u8 iqk_ch[RTW89_IQK_PATH_NR]; 5053 u8 iqk_bw[RTW89_IQK_PATH_NR]; 5054 u8 iqk_times; 5055 u8 version; 5056 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 5057 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 5058 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 5059 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 5060 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 5061 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 5062 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 5063 bool is_nbiqk; 5064 bool iqk_fft_en; 5065 bool iqk_xym_en; 5066 bool iqk_sram_en; 5067 bool iqk_cfir_en; 5068 u32 syn1to2; 5069 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5070 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 5071 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5072 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5073 }; 5074 5075 #define RTW89_DPK_RF_PATH 2 5076 #define RTW89_DPK_AVG_THERMAL_NUM 8 5077 #define RTW89_DPK_BKUP_NUM 2 5078 struct rtw89_dpk_bkup_para { 5079 enum rtw89_band band; 5080 enum rtw89_bandwidth bw; 5081 u8 ch; 5082 bool path_ok; 5083 u8 mdpd_en; 5084 u8 txagc_dpk; 5085 u8 ther_dpk; 5086 u8 gs; 5087 u16 pwsf; 5088 }; 5089 5090 struct rtw89_dpk_info { 5091 bool is_dpk_enable; 5092 bool is_dpk_reload_en; 5093 u8 dpk_gs[RTW89_PHY_NUM]; 5094 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5095 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5096 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5097 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5098 u8 cur_idx[RTW89_DPK_RF_PATH]; 5099 u8 cur_k_set; 5100 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5101 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 5102 u32 dpk_order[RTW89_DPK_RF_PATH]; 5103 }; 5104 5105 struct rtw89_fem_info { 5106 bool elna_2g; 5107 bool elna_5g; 5108 bool epa_2g; 5109 bool epa_5g; 5110 bool epa_6g; 5111 }; 5112 5113 struct rtw89_phy_ch_info { 5114 u8 rssi_min; 5115 u16 rssi_min_macid; 5116 u8 pre_rssi_min; 5117 u8 rssi_max; 5118 u16 rssi_max_macid; 5119 u8 rxsc_160; 5120 u8 rxsc_80; 5121 u8 rxsc_40; 5122 u8 rxsc_20; 5123 u8 rxsc_l; 5124 u8 is_noisy; 5125 }; 5126 5127 struct rtw89_agc_gaincode_set { 5128 u8 lna_idx; 5129 u8 tia_idx; 5130 u8 rxb_idx; 5131 }; 5132 5133 #define IGI_RSSI_TH_NUM 5 5134 #define FA_TH_NUM 4 5135 #define TIA_LNA_OP1DB_NUM 8 5136 #define LNA_GAIN_NUM 7 5137 #define TIA_GAIN_NUM 2 5138 struct rtw89_dig_info { 5139 struct rtw89_agc_gaincode_set cur_gaincode; 5140 bool force_gaincode_idx_en; 5141 struct rtw89_agc_gaincode_set force_gaincode; 5142 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5143 u16 fa_th[FA_TH_NUM]; 5144 u8 igi_rssi; 5145 u8 igi_fa_rssi; 5146 u8 fa_rssi_ofst; 5147 u8 dyn_igi_max; 5148 u8 dyn_igi_min; 5149 bool dyn_pd_th_en; 5150 u8 dyn_pd_th_max; 5151 u8 pd_low_th_ofst; 5152 u8 ib_pbk; 5153 s8 ib_pkpwr; 5154 s8 lna_gain_a[LNA_GAIN_NUM]; 5155 s8 lna_gain_g[LNA_GAIN_NUM]; 5156 s8 *lna_gain; 5157 s8 tia_gain_a[TIA_GAIN_NUM]; 5158 s8 tia_gain_g[TIA_GAIN_NUM]; 5159 s8 *tia_gain; 5160 bool is_linked_pre; 5161 bool bypass_dig; 5162 }; 5163 5164 enum rtw89_multi_cfo_mode { 5165 RTW89_PKT_BASED_AVG_MODE = 0, 5166 RTW89_ENTRY_BASED_AVG_MODE = 1, 5167 RTW89_TP_BASED_AVG_MODE = 2, 5168 }; 5169 5170 enum rtw89_phy_cfo_status { 5171 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5172 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5173 RTW89_PHY_DCFO_STATE_HOLD = 2, 5174 RTW89_PHY_DCFO_STATE_MAX 5175 }; 5176 5177 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5178 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5179 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5180 }; 5181 5182 struct rtw89_cfo_tracking_info { 5183 u16 cfo_timer_ms; 5184 bool cfo_trig_by_timer_en; 5185 enum rtw89_phy_cfo_status phy_cfo_status; 5186 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5187 u8 phy_cfo_trk_cnt; 5188 bool is_adjust; 5189 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5190 bool apply_compensation; 5191 u8 crystal_cap; 5192 u8 crystal_cap_default; 5193 u8 def_x_cap; 5194 s8 x_cap_ofst; 5195 u32 sta_cfo_tolerance; 5196 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5197 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5198 s32 cfo_avg_pre; 5199 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5200 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5201 s32 dcfo_avg; 5202 s32 dcfo_avg_pre; 5203 u32 packet_count; 5204 u32 packet_count_pre; 5205 s32 residual_cfo_acc; 5206 u8 phy_cfotrk_state; 5207 u8 phy_cfotrk_cnt; 5208 bool divergence_lock_en; 5209 u8 x_cap_lb; 5210 u8 x_cap_ub; 5211 u8 lock_cnt; 5212 }; 5213 5214 enum rtw89_tssi_mode { 5215 RTW89_TSSI_NORMAL = 0, 5216 RTW89_TSSI_SCAN = 1, 5217 }; 5218 5219 enum rtw89_tssi_alimk_band { 5220 TSSI_ALIMK_2G = 0, 5221 TSSI_ALIMK_5GL, 5222 TSSI_ALIMK_5GM, 5223 TSSI_ALIMK_5GH, 5224 TSSI_ALIMK_MAX 5225 }; 5226 5227 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5228 #define TSSI_TRIM_CH_GROUP_NUM 8 5229 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5230 5231 #define TSSI_CCK_CH_GROUP_NUM 6 5232 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5233 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5234 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5235 #define TSSI_MCS_CH_GROUP_NUM \ 5236 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5237 #define TSSI_MAX_CH_NUM 67 5238 #define TSSI_ALIMK_VALUE_NUM 8 5239 5240 struct rtw89_tssi_info { 5241 u8 thermal[RF_PATH_MAX]; 5242 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5243 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5244 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5245 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5246 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5247 s8 extra_ofst[RF_PATH_MAX]; 5248 bool tssi_tracking_check[RF_PATH_MAX]; 5249 u8 default_txagc_offset[RF_PATH_MAX]; 5250 u32 base_thermal[RF_PATH_MAX]; 5251 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5252 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5253 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5254 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5255 u64 tssi_alimk_time; 5256 }; 5257 5258 struct rtw89_power_trim_info { 5259 bool pg_thermal_trim; 5260 bool pg_pa_bias_trim; 5261 u8 thermal_trim[RF_PATH_MAX]; 5262 u8 pa_bias_trim[RF_PATH_MAX]; 5263 u8 pad_bias_trim[RF_PATH_MAX]; 5264 }; 5265 5266 enum rtw89_regd_func { 5267 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 5268 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 5269 5270 NUM_OF_RTW89_REGD_FUNC, 5271 }; 5272 5273 struct rtw89_regd { 5274 char alpha2[3]; 5275 u8 txpwr_regd[RTW89_BAND_NUM]; 5276 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 5277 }; 5278 5279 struct rtw89_regd_data { 5280 unsigned int nr; 5281 struct rtw89_regd map[] __counted_by(nr); 5282 }; 5283 5284 struct rtw89_regd_ctrl { 5285 unsigned int nr; 5286 const struct rtw89_regd *map; 5287 }; 5288 5289 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5290 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5291 #define RTW89_5GHZ_UNII4_START_INDEX 25 5292 5293 struct rtw89_regulatory_info { 5294 struct rtw89_regd_ctrl ctrl; 5295 const struct rtw89_regd *regd; 5296 enum rtw89_reg_6ghz_power reg_6ghz_power; 5297 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5298 bool txpwr_uk_follow_etsi; 5299 5300 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5301 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5302 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5303 }; 5304 5305 enum rtw89_ifs_clm_application { 5306 RTW89_IFS_CLM_INIT = 0, 5307 RTW89_IFS_CLM_BACKGROUND = 1, 5308 RTW89_IFS_CLM_ACS = 2, 5309 RTW89_IFS_CLM_DIG = 3, 5310 RTW89_IFS_CLM_TDMA_DIG = 4, 5311 RTW89_IFS_CLM_DBG = 5, 5312 RTW89_IFS_CLM_DBG_MANUAL = 6 5313 }; 5314 5315 enum rtw89_env_racing_lv { 5316 RTW89_RAC_RELEASE = 0, 5317 RTW89_RAC_LV_1 = 1, 5318 RTW89_RAC_LV_2 = 2, 5319 RTW89_RAC_LV_3 = 3, 5320 RTW89_RAC_LV_4 = 4, 5321 RTW89_RAC_MAX_NUM = 5 5322 }; 5323 5324 struct rtw89_ccx_para_info { 5325 enum rtw89_env_racing_lv rac_lv; 5326 u16 mntr_time; 5327 u8 nhm_manual_th_ofst; 5328 u8 nhm_manual_th0; 5329 enum rtw89_ifs_clm_application ifs_clm_app; 5330 u32 ifs_clm_manual_th_times; 5331 u32 ifs_clm_manual_th0; 5332 u8 fahm_manual_th_ofst; 5333 u8 fahm_manual_th0; 5334 u8 fahm_numer_opt; 5335 u8 fahm_denom_opt; 5336 }; 5337 5338 enum rtw89_ccx_edcca_opt_sc_idx { 5339 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5340 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5341 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5342 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5343 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5344 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5345 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5346 RTW89_CCX_EDCCA_SEG1_S3 = 7 5347 }; 5348 5349 enum rtw89_ccx_edcca_opt_bw_idx { 5350 RTW89_CCX_EDCCA_BW20_0 = 0, 5351 RTW89_CCX_EDCCA_BW20_1 = 1, 5352 RTW89_CCX_EDCCA_BW20_2 = 2, 5353 RTW89_CCX_EDCCA_BW20_3 = 3, 5354 RTW89_CCX_EDCCA_BW20_4 = 4, 5355 RTW89_CCX_EDCCA_BW20_5 = 5, 5356 RTW89_CCX_EDCCA_BW20_6 = 6, 5357 RTW89_CCX_EDCCA_BW20_7 = 7 5358 }; 5359 5360 #define RTW89_NHM_TH_NUM 11 5361 #define RTW89_FAHM_TH_NUM 11 5362 #define RTW89_NHM_RPT_NUM 12 5363 #define RTW89_FAHM_RPT_NUM 12 5364 #define RTW89_IFS_CLM_NUM 4 5365 struct rtw89_env_monitor_info { 5366 u8 ccx_watchdog_result; 5367 bool ccx_ongoing; 5368 u8 ccx_rac_lv; 5369 bool ccx_manual_ctrl; 5370 u16 ifs_clm_mntr_time; 5371 enum rtw89_ifs_clm_application ifs_clm_app; 5372 u16 ccx_period; 5373 u8 ccx_unit_idx; 5374 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5375 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5376 u16 ifs_clm_tx; 5377 u16 ifs_clm_edcca_excl_cca; 5378 u16 ifs_clm_ofdmfa; 5379 u16 ifs_clm_ofdmcca_excl_fa; 5380 u16 ifs_clm_cckfa; 5381 u16 ifs_clm_cckcca_excl_fa; 5382 u16 ifs_clm_total_ifs; 5383 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5384 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5385 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5386 u8 ifs_clm_tx_ratio; 5387 u8 ifs_clm_edcca_excl_cca_ratio; 5388 u8 ifs_clm_cck_fa_ratio; 5389 u8 ifs_clm_ofdm_fa_ratio; 5390 u8 ifs_clm_cck_cca_excl_fa_ratio; 5391 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5392 u16 ifs_clm_cck_fa_permil; 5393 u16 ifs_clm_ofdm_fa_permil; 5394 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5395 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5396 }; 5397 5398 enum rtw89_ser_rcvy_step { 5399 RTW89_SER_DRV_STOP_TX, 5400 RTW89_SER_DRV_STOP_RX, 5401 RTW89_SER_DRV_STOP_RUN, 5402 RTW89_SER_HAL_STOP_DMA, 5403 RTW89_SER_SUPPRESS_LOG, 5404 RTW89_NUM_OF_SER_FLAGS 5405 }; 5406 5407 struct rtw89_ser { 5408 u8 state; 5409 u8 alarm_event; 5410 bool prehandle_l1; 5411 5412 struct work_struct ser_hdl_work; 5413 struct delayed_work ser_alarm_work; 5414 const struct state_ent *st_tbl; 5415 const struct event_ent *ev_tbl; 5416 struct list_head msg_q; 5417 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5418 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5419 }; 5420 5421 enum rtw89_mac_ax_ps_mode { 5422 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5423 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5424 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5425 RTW89_MAC_AX_PS_MODE_MAX = 3, 5426 }; 5427 5428 enum rtw89_last_rpwm_mode { 5429 RTW89_LAST_RPWM_PS = 0x0, 5430 RTW89_LAST_RPWM_ACTIVE = 0x6, 5431 }; 5432 5433 struct rtw89_lps_parm { 5434 u8 macid; 5435 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5436 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5437 }; 5438 5439 struct rtw89_ppdu_sts_info { 5440 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 5441 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 5442 }; 5443 5444 struct rtw89_early_h2c { 5445 struct list_head list; 5446 u8 *h2c; 5447 u16 h2c_len; 5448 }; 5449 5450 struct rtw89_hw_scan_info { 5451 struct rtw89_vif_link *scanning_vif; 5452 struct list_head pkt_list[NUM_NL80211_BANDS]; 5453 struct list_head chan_list; 5454 struct rtw89_chan op_chan; 5455 bool connected; 5456 bool abort; 5457 }; 5458 5459 enum rtw89_phy_bb_gain_band { 5460 RTW89_BB_GAIN_BAND_2G = 0, 5461 RTW89_BB_GAIN_BAND_5G_L = 1, 5462 RTW89_BB_GAIN_BAND_5G_M = 2, 5463 RTW89_BB_GAIN_BAND_5G_H = 3, 5464 RTW89_BB_GAIN_BAND_6G_L = 4, 5465 RTW89_BB_GAIN_BAND_6G_M = 5, 5466 RTW89_BB_GAIN_BAND_6G_H = 6, 5467 RTW89_BB_GAIN_BAND_6G_UH = 7, 5468 5469 RTW89_BB_GAIN_BAND_NR, 5470 }; 5471 5472 enum rtw89_phy_gain_band_be { 5473 RTW89_BB_GAIN_BAND_2G_BE = 0, 5474 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5475 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5476 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5477 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5478 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5479 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5480 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5481 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5482 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5483 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5484 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5485 5486 RTW89_BB_GAIN_BAND_NR_BE, 5487 }; 5488 5489 enum rtw89_phy_bb_bw_be { 5490 RTW89_BB_BW_20_40 = 0, 5491 RTW89_BB_BW_80_160_320 = 1, 5492 5493 RTW89_BB_BW_NR_BE, 5494 }; 5495 5496 enum rtw89_bw20_sc { 5497 RTW89_BW20_SC_20M = 1, 5498 RTW89_BW20_SC_40M = 2, 5499 RTW89_BW20_SC_80M = 4, 5500 RTW89_BW20_SC_160M = 8, 5501 RTW89_BW20_SC_320M = 16, 5502 }; 5503 5504 enum rtw89_cmac_table_bw { 5505 RTW89_CMAC_BW_20M = 0, 5506 RTW89_CMAC_BW_40M = 1, 5507 RTW89_CMAC_BW_80M = 2, 5508 RTW89_CMAC_BW_160M = 3, 5509 RTW89_CMAC_BW_320M = 4, 5510 5511 RTW89_CMAC_BW_NR, 5512 }; 5513 5514 enum rtw89_phy_bb_rxsc_num { 5515 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5516 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5517 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5518 }; 5519 5520 struct rtw89_phy_bb_gain_info { 5521 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5522 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5523 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5524 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5525 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5526 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5527 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5528 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5529 [RTW89_BB_RXSC_NUM_40]; 5530 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5531 [RTW89_BB_RXSC_NUM_80]; 5532 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5533 [RTW89_BB_RXSC_NUM_160]; 5534 }; 5535 5536 struct rtw89_phy_bb_gain_info_be { 5537 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5538 [LNA_GAIN_NUM]; 5539 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5540 [TIA_GAIN_NUM]; 5541 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5542 [RF_PATH_MAX][LNA_GAIN_NUM]; 5543 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5544 [RF_PATH_MAX][LNA_GAIN_NUM]; 5545 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5546 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5547 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5548 [RTW89_BW20_SC_20M]; 5549 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5550 [RTW89_BW20_SC_40M]; 5551 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5552 [RTW89_BW20_SC_80M]; 5553 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5554 [RTW89_BW20_SC_160M]; 5555 }; 5556 5557 struct rtw89_phy_efuse_gain { 5558 bool offset_valid; 5559 bool comp_valid; 5560 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5561 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5562 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5563 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5564 }; 5565 5566 #define RTW89_MAX_PATTERN_NUM 18 5567 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5568 #define RTW89_MAX_PATTERN_SIZE 128 5569 5570 struct rtw89_wow_cam_info { 5571 bool r_w; 5572 u8 idx; 5573 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5574 u16 crc; 5575 bool negative_pattern_match; 5576 bool skip_mac_hdr; 5577 bool uc; 5578 bool mc; 5579 bool bc; 5580 bool valid; 5581 }; 5582 5583 struct rtw89_wow_key_info { 5584 u8 ptk_tx_iv[8]; 5585 u8 valid_check; 5586 u8 symbol_check_en; 5587 u8 gtk_keyidx; 5588 u8 rsvd[5]; 5589 u8 ptk_rx_iv[8]; 5590 u8 gtk_rx_iv[4][8]; 5591 } __packed; 5592 5593 struct rtw89_wow_gtk_info { 5594 u8 kck[32]; 5595 u8 kek[32]; 5596 u8 tk1[16]; 5597 u8 txmickey[8]; 5598 u8 rxmickey[8]; 5599 __le32 igtk_keyid; 5600 __le64 ipn; 5601 u8 igtk[2][32]; 5602 u8 psk[32]; 5603 } __packed; 5604 5605 struct rtw89_wow_aoac_report { 5606 u8 rpt_ver; 5607 u8 sec_type; 5608 u8 key_idx; 5609 u8 pattern_idx; 5610 u8 rekey_ok; 5611 u8 ptk_tx_iv[8]; 5612 u8 eapol_key_replay_count[8]; 5613 u8 gtk[32]; 5614 u8 ptk_rx_iv[8]; 5615 u8 gtk_rx_iv[4][8]; 5616 u64 igtk_key_id; 5617 u64 igtk_ipn; 5618 u8 igtk[32]; 5619 u8 csa_pri_ch; 5620 u8 csa_bw; 5621 u8 csa_ch_offset; 5622 u8 csa_chsw_failed; 5623 u8 csa_ch_band; 5624 }; 5625 5626 struct rtw89_wow_param { 5627 struct rtw89_vif_link *rtwvif_link; 5628 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5629 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5630 struct rtw89_wow_key_info key_info; 5631 struct rtw89_wow_gtk_info gtk_info; 5632 struct rtw89_wow_aoac_report aoac_rpt; 5633 u8 pattern_cnt; 5634 u8 ptk_alg; 5635 u8 gtk_alg; 5636 u8 ptk_keyidx; 5637 u8 akm; 5638 5639 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5640 struct rtw89_wait_info wait; 5641 5642 bool pno_inited; 5643 struct list_head pno_pkt_list; 5644 struct cfg80211_sched_scan_request *nd_config; 5645 }; 5646 5647 struct rtw89_mcc_limit { 5648 bool enable; 5649 u16 max_tob; /* TU; max time offset behind */ 5650 u16 max_toa; /* TU; max time offset ahead */ 5651 u16 max_dur; /* TU */ 5652 }; 5653 5654 struct rtw89_mcc_policy { 5655 u8 c2h_rpt; 5656 u8 tx_null_early; 5657 u8 dis_tx_null; 5658 u8 in_curr_ch; 5659 u8 dis_sw_retry; 5660 u8 sw_retry_count; 5661 }; 5662 5663 struct rtw89_mcc_role { 5664 struct rtw89_vif_link *rtwvif_link; 5665 struct rtw89_mcc_policy policy; 5666 struct rtw89_mcc_limit limit; 5667 5668 const struct rtw89_mcc_courtesy_cfg *crtz; 5669 5670 /* only valid when running with FW MRC mechanism */ 5671 u8 slot_idx; 5672 5673 /* byte-array in LE order for FW */ 5674 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5675 5676 u16 duration; /* TU */ 5677 u16 beacon_interval; /* TU */ 5678 bool is_2ghz; 5679 bool is_go; 5680 bool is_gc; 5681 }; 5682 5683 struct rtw89_mcc_bt_role { 5684 u16 duration; /* TU */ 5685 }; 5686 5687 struct rtw89_mcc_courtesy_cfg { 5688 u8 slot_num; 5689 u8 macid_tgt; 5690 }; 5691 5692 struct rtw89_mcc_courtesy { 5693 struct rtw89_mcc_courtesy_cfg ref; 5694 struct rtw89_mcc_courtesy_cfg aux; 5695 }; 5696 5697 enum rtw89_mcc_plan { 5698 RTW89_MCC_PLAN_TAIL_BT, 5699 RTW89_MCC_PLAN_MID_BT, 5700 RTW89_MCC_PLAN_NO_BT, 5701 5702 NUM_OF_RTW89_MCC_PLAN, 5703 }; 5704 5705 struct rtw89_mcc_pattern { 5706 s16 tob_ref; /* TU; time offset behind of reference role */ 5707 s16 toa_ref; /* TU; time offset ahead of reference role */ 5708 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5709 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5710 5711 enum rtw89_mcc_plan plan; 5712 struct rtw89_mcc_courtesy courtesy; 5713 }; 5714 5715 struct rtw89_mcc_sync { 5716 bool enable; 5717 u16 offset; /* TU */ 5718 u8 macid_src; 5719 u8 band_src; 5720 u8 port_src; 5721 u8 macid_tgt; 5722 u8 band_tgt; 5723 u8 port_tgt; 5724 }; 5725 5726 struct rtw89_mcc_config { 5727 struct rtw89_mcc_pattern pattern; 5728 struct rtw89_mcc_sync sync; 5729 u64 start_tsf; 5730 u64 start_tsf_in_aux_domain; 5731 u16 mcc_interval; /* TU */ 5732 u16 beacon_offset; /* TU */ 5733 }; 5734 5735 enum rtw89_mcc_mode { 5736 RTW89_MCC_MODE_GO_STA, 5737 RTW89_MCC_MODE_GC_STA, 5738 }; 5739 5740 struct rtw89_mcc_info { 5741 struct rtw89_wait_info wait; 5742 5743 u8 group; 5744 enum rtw89_mcc_mode mode; 5745 struct rtw89_mcc_role role_ref; /* reference role */ 5746 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5747 struct rtw89_mcc_bt_role bt_role; 5748 struct rtw89_mcc_config config; 5749 }; 5750 5751 enum rtw89_mlo_mode { 5752 RTW89_MLO_MODE_MLSR = 0, 5753 5754 NUM_OF_RTW89_MLO_MODE, 5755 }; 5756 5757 struct rtw89_mlo_info { 5758 struct rtw89_wait_info wait; 5759 }; 5760 5761 struct rtw89_dev { 5762 struct ieee80211_hw *hw; 5763 struct device *dev; 5764 const struct ieee80211_ops *ops; 5765 5766 bool dbcc_en; 5767 bool support_mlo; 5768 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5769 struct rtw89_hw_scan_info scan_info; 5770 const struct rtw89_chip_info *chip; 5771 const struct rtw89_chip_variant *variant; 5772 const struct rtw89_pci_info *pci_info; 5773 const struct rtw89_rfe_parms *rfe_parms; 5774 struct rtw89_hal hal; 5775 struct rtw89_mcc_info mcc; 5776 struct rtw89_mlo_info mlo; 5777 struct rtw89_mac_info mac; 5778 struct rtw89_fw_info fw; 5779 struct rtw89_hci_info hci; 5780 struct rtw89_efuse efuse; 5781 struct rtw89_traffic_stats stats; 5782 struct rtw89_rfe_data *rfe_data; 5783 enum rtw89_custid custid; 5784 5785 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 5786 refcount_t refcount_ap_info; 5787 5788 struct list_head rtwvifs_list; 5789 /* used to protect rf read write */ 5790 struct mutex rf_mutex; 5791 struct workqueue_struct *txq_wq; 5792 struct work_struct txq_work; 5793 struct delayed_work txq_reinvoke_work; 5794 /* used to protect ba_list and forbid_ba_list */ 5795 spinlock_t ba_lock; 5796 /* txqs to setup ba session */ 5797 struct list_head ba_list; 5798 /* txqs to forbid ba session */ 5799 struct list_head forbid_ba_list; 5800 struct work_struct ba_work; 5801 /* used to protect rpwm */ 5802 spinlock_t rpwm_lock; 5803 5804 struct rtw89_cam_info cam_info; 5805 5806 struct sk_buff_head c2h_queue; 5807 struct wiphy_work c2h_work; 5808 struct wiphy_work ips_work; 5809 struct wiphy_work cancel_6ghz_probe_work; 5810 struct work_struct load_firmware_work; 5811 5812 struct list_head early_h2c_list; 5813 5814 struct rtw89_ser ser; 5815 5816 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5817 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5818 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5819 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5820 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5821 5822 struct rtw89_phy_stat phystat; 5823 struct rtw89_rfk_wait_info rfk_wait; 5824 struct rtw89_dack_info dack; 5825 struct rtw89_iqk_info iqk; 5826 struct rtw89_dpk_info dpk; 5827 struct rtw89_rfk_mcc_info rfk_mcc; 5828 struct rtw89_lck_info lck; 5829 struct rtw89_rx_dck_info rx_dck; 5830 bool is_tssi_mode[RF_PATH_MAX]; 5831 bool is_bt_iqk_timeout; 5832 5833 struct rtw89_fem_info fem; 5834 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5835 struct rtw89_tssi_info tssi; 5836 struct rtw89_power_trim_info pwr_trim; 5837 5838 struct rtw89_cfo_tracking_info cfo_tracking; 5839 union { 5840 struct rtw89_phy_bb_gain_info ax; 5841 struct rtw89_phy_bb_gain_info_be be; 5842 } bb_gain; 5843 struct rtw89_phy_efuse_gain efuse_gain; 5844 struct rtw89_phy_ul_tb_info ul_tb_info; 5845 struct rtw89_antdiv_info antdiv; 5846 5847 struct rtw89_bb_ctx { 5848 enum rtw89_phy_idx phy_idx; 5849 struct rtw89_env_monitor_info env_monitor; 5850 struct rtw89_dig_info dig; 5851 struct rtw89_phy_ch_info ch_info; 5852 struct rtw89_edcca_bak edcca_bak; 5853 } bbs[RTW89_PHY_NUM]; 5854 5855 struct wiphy_delayed_work track_work; 5856 struct wiphy_delayed_work chanctx_work; 5857 struct wiphy_delayed_work coex_act1_work; 5858 struct wiphy_delayed_work coex_bt_devinfo_work; 5859 struct wiphy_delayed_work coex_rfk_chk_work; 5860 struct wiphy_delayed_work cfo_track_work; 5861 struct delayed_work forbid_ba_work; 5862 struct wiphy_delayed_work antdiv_work; 5863 struct rtw89_ppdu_sts_info ppdu_sts; 5864 u8 total_sta_assoc; 5865 bool scanning; 5866 5867 struct rtw89_regulatory_info regulatory; 5868 struct rtw89_sar_info sar; 5869 struct rtw89_tas_info tas; 5870 struct rtw89_ant_gain_info ant_gain; 5871 5872 struct rtw89_btc btc; 5873 enum rtw89_ps_mode ps_mode; 5874 bool lps_enabled; 5875 5876 struct rtw89_wow_param wow; 5877 5878 /* napi structure */ 5879 struct net_device *netdev; 5880 struct napi_struct napi; 5881 int napi_budget_countdown; 5882 5883 struct rtw89_debugfs *debugfs; 5884 5885 /* HCI related data, keep last */ 5886 u8 priv[] __aligned(sizeof(void *)); 5887 }; 5888 5889 struct rtw89_link_conf_container { 5890 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 5891 }; 5892 5893 #define RTW89_VIF_IDLE_LINK_ID 0 5894 5895 struct rtw89_vif { 5896 struct rtw89_dev *rtwdev; 5897 struct list_head list; 5898 struct list_head mgnt_entry; 5899 struct rtw89_link_conf_container __rcu *snap_link_confs; 5900 5901 u8 mac_addr[ETH_ALEN]; 5902 __be32 ip_addr; 5903 5904 struct rtw89_traffic_stats stats; 5905 u32 tdls_peer; 5906 5907 struct ieee80211_scan_ies *scan_ies; 5908 struct cfg80211_scan_request *scan_req; 5909 5910 struct rtw89_roc roc; 5911 bool offchan; 5912 5913 enum rtw89_mlo_mode mlo_mode; 5914 5915 struct list_head dlink_pool; 5916 u8 links_inst_valid_num; 5917 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5918 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5919 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 5920 }; 5921 5922 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 5923 const struct rtw89_vif *rtwvif, 5924 unsigned int link_id) 5925 { 5926 *rtwvif_link = rtwvif->links[link_id]; 5927 return !!*rtwvif_link; 5928 } 5929 5930 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 5931 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5932 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 5933 5934 enum rtw89_sta_flags { 5935 RTW89_REMOTE_STA_IN_PS, 5936 5937 NUM_OF_RTW89_STA_FLAGS, 5938 }; 5939 5940 struct rtw89_sta { 5941 struct rtw89_dev *rtwdev; 5942 struct rtw89_vif *rtwvif; 5943 5944 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 5945 5946 bool disassoc; 5947 5948 struct sk_buff_head roc_queue; 5949 5950 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 5951 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 5952 5953 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 5954 5955 struct list_head dlink_pool; 5956 u8 links_inst_valid_num; 5957 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5958 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5959 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 5960 }; 5961 5962 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 5963 const struct rtw89_sta *rtwsta, 5964 unsigned int link_id) 5965 { 5966 *rtwsta_link = rtwsta->links[link_id]; 5967 return !!*rtwsta_link; 5968 } 5969 5970 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 5971 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5972 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 5973 5974 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 5975 { 5976 /* const after init, so no need to check if active first */ 5977 return rtwvif->links_inst[0].mac_id; 5978 } 5979 5980 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 5981 { 5982 /* const after init, so no need to check if active first */ 5983 return rtwvif->links_inst[0].port; 5984 } 5985 5986 static inline struct rtw89_vif_link * 5987 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 5988 { 5989 if (index >= rtwvif->links_inst_valid_num || 5990 !test_bit(index, rtwvif->links_inst_map)) 5991 return NULL; 5992 return &rtwvif->links_inst[index]; 5993 } 5994 5995 static inline 5996 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 5997 { 5998 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5999 6000 return rtwvif_link - rtwvif->links_inst; 6001 } 6002 6003 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 6004 { 6005 /* const after init, so no need to check if active first */ 6006 return rtwsta->links_inst[0].mac_id; 6007 } 6008 6009 static inline struct rtw89_sta_link * 6010 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 6011 { 6012 if (index >= rtwsta->links_inst_valid_num || 6013 !test_bit(index, rtwsta->links_inst_map)) 6014 return NULL; 6015 return &rtwsta->links_inst[index]; 6016 } 6017 6018 static inline 6019 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 6020 { 6021 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6022 6023 return rtwsta_link - rtwsta->links_inst; 6024 } 6025 6026 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 6027 { 6028 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6029 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6030 6031 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6032 rtwsta_link); 6033 } 6034 6035 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 6036 { 6037 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6038 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6039 6040 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6041 NULL); 6042 synchronize_rcu(); 6043 } 6044 6045 static inline struct rtw89_sta_link * 6046 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 6047 { 6048 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 6049 } 6050 6051 #define rtw89_get_designated_link(links_holder) \ 6052 ({ \ 6053 typeof(links_holder) p = links_holder; \ 6054 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 6055 }) 6056 6057 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 6058 struct rtw89_core_tx_request *tx_req) 6059 { 6060 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 6061 } 6062 6063 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 6064 { 6065 rtwdev->hci.ops->reset(rtwdev); 6066 } 6067 6068 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 6069 { 6070 return rtwdev->hci.ops->start(rtwdev); 6071 } 6072 6073 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 6074 { 6075 rtwdev->hci.ops->stop(rtwdev); 6076 } 6077 6078 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 6079 { 6080 return rtwdev->hci.ops->deinit(rtwdev); 6081 } 6082 6083 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 6084 { 6085 rtwdev->hci.ops->pause(rtwdev, pause); 6086 } 6087 6088 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 6089 { 6090 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 6091 } 6092 6093 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 6094 { 6095 rtwdev->hci.ops->recalc_int_mit(rtwdev); 6096 } 6097 6098 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 6099 { 6100 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 6101 } 6102 6103 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 6104 { 6105 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 6106 } 6107 6108 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 6109 { 6110 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 6111 } 6112 6113 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 6114 bool drop) 6115 { 6116 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6117 return; 6118 6119 if (rtwdev->hci.ops->flush_queues) 6120 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 6121 } 6122 6123 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 6124 { 6125 if (rtwdev->hci.ops->recovery_start) 6126 rtwdev->hci.ops->recovery_start(rtwdev); 6127 } 6128 6129 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 6130 { 6131 if (rtwdev->hci.ops->recovery_complete) 6132 rtwdev->hci.ops->recovery_complete(rtwdev); 6133 } 6134 6135 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 6136 { 6137 if (rtwdev->hci.ops->enable_intr) 6138 rtwdev->hci.ops->enable_intr(rtwdev); 6139 } 6140 6141 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 6142 { 6143 if (rtwdev->hci.ops->disable_intr) 6144 rtwdev->hci.ops->disable_intr(rtwdev); 6145 } 6146 6147 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 6148 { 6149 if (rtwdev->hci.ops->ctrl_txdma_ch) 6150 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 6151 } 6152 6153 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6154 { 6155 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6156 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6157 } 6158 6159 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6160 { 6161 if (rtwdev->hci.ops->ctrl_trxhci) 6162 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6163 } 6164 6165 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6166 { 6167 int ret = 0; 6168 6169 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6170 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6171 return ret; 6172 } 6173 6174 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6175 { 6176 if (rtwdev->hci.ops->clr_idx_all) 6177 rtwdev->hci.ops->clr_idx_all(rtwdev); 6178 } 6179 6180 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6181 { 6182 int ret = 0; 6183 6184 if (rtwdev->hci.ops->rst_bdram) 6185 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6186 return ret; 6187 } 6188 6189 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6190 { 6191 if (rtwdev->hci.ops->clear) 6192 rtwdev->hci.ops->clear(rtwdev, pdev); 6193 } 6194 6195 static inline 6196 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6197 { 6198 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6199 6200 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 6201 } 6202 6203 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6204 { 6205 return rtwdev->hci.ops->read8(rtwdev, addr); 6206 } 6207 6208 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6209 { 6210 return rtwdev->hci.ops->read16(rtwdev, addr); 6211 } 6212 6213 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6214 { 6215 return rtwdev->hci.ops->read32(rtwdev, addr); 6216 } 6217 6218 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6219 { 6220 rtwdev->hci.ops->write8(rtwdev, addr, data); 6221 } 6222 6223 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6224 { 6225 rtwdev->hci.ops->write16(rtwdev, addr, data); 6226 } 6227 6228 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6229 { 6230 rtwdev->hci.ops->write32(rtwdev, addr, data); 6231 } 6232 6233 static inline void 6234 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6235 { 6236 u8 val; 6237 6238 val = rtw89_read8(rtwdev, addr); 6239 rtw89_write8(rtwdev, addr, val | bit); 6240 } 6241 6242 static inline void 6243 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6244 { 6245 u16 val; 6246 6247 val = rtw89_read16(rtwdev, addr); 6248 rtw89_write16(rtwdev, addr, val | bit); 6249 } 6250 6251 static inline void 6252 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6253 { 6254 u32 val; 6255 6256 val = rtw89_read32(rtwdev, addr); 6257 rtw89_write32(rtwdev, addr, val | bit); 6258 } 6259 6260 static inline void 6261 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6262 { 6263 u8 val; 6264 6265 val = rtw89_read8(rtwdev, addr); 6266 rtw89_write8(rtwdev, addr, val & ~bit); 6267 } 6268 6269 static inline void 6270 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6271 { 6272 u16 val; 6273 6274 val = rtw89_read16(rtwdev, addr); 6275 rtw89_write16(rtwdev, addr, val & ~bit); 6276 } 6277 6278 static inline void 6279 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6280 { 6281 u32 val; 6282 6283 val = rtw89_read32(rtwdev, addr); 6284 rtw89_write32(rtwdev, addr, val & ~bit); 6285 } 6286 6287 static inline u32 6288 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6289 { 6290 u32 shift = __ffs(mask); 6291 u32 orig; 6292 u32 ret; 6293 6294 orig = rtw89_read32(rtwdev, addr); 6295 ret = (orig & mask) >> shift; 6296 6297 return ret; 6298 } 6299 6300 static inline u16 6301 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6302 { 6303 u32 shift = __ffs(mask); 6304 u32 orig; 6305 u32 ret; 6306 6307 orig = rtw89_read16(rtwdev, addr); 6308 ret = (orig & mask) >> shift; 6309 6310 return ret; 6311 } 6312 6313 static inline u8 6314 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6315 { 6316 u32 shift = __ffs(mask); 6317 u32 orig; 6318 u32 ret; 6319 6320 orig = rtw89_read8(rtwdev, addr); 6321 ret = (orig & mask) >> shift; 6322 6323 return ret; 6324 } 6325 6326 static inline void 6327 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6328 { 6329 u32 shift = __ffs(mask); 6330 u32 orig; 6331 u32 set; 6332 6333 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6334 6335 orig = rtw89_read32(rtwdev, addr); 6336 set = (orig & ~mask) | ((data << shift) & mask); 6337 rtw89_write32(rtwdev, addr, set); 6338 } 6339 6340 static inline void 6341 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6342 { 6343 u32 shift; 6344 u16 orig, set; 6345 6346 mask &= 0xffff; 6347 shift = __ffs(mask); 6348 6349 orig = rtw89_read16(rtwdev, addr); 6350 set = (orig & ~mask) | ((data << shift) & mask); 6351 rtw89_write16(rtwdev, addr, set); 6352 } 6353 6354 static inline void 6355 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6356 { 6357 u32 shift; 6358 u8 orig, set; 6359 6360 mask &= 0xff; 6361 shift = __ffs(mask); 6362 6363 orig = rtw89_read8(rtwdev, addr); 6364 set = (orig & ~mask) | ((data << shift) & mask); 6365 rtw89_write8(rtwdev, addr, set); 6366 } 6367 6368 static inline u32 6369 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6370 u32 addr, u32 mask) 6371 { 6372 u32 val; 6373 6374 mutex_lock(&rtwdev->rf_mutex); 6375 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6376 mutex_unlock(&rtwdev->rf_mutex); 6377 6378 return val; 6379 } 6380 6381 static inline void 6382 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6383 u32 addr, u32 mask, u32 data) 6384 { 6385 mutex_lock(&rtwdev->rf_mutex); 6386 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6387 mutex_unlock(&rtwdev->rf_mutex); 6388 } 6389 6390 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6391 { 6392 void *p = rtwtxq; 6393 6394 return container_of(p, struct ieee80211_txq, drv_priv); 6395 } 6396 6397 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6398 struct ieee80211_txq *txq) 6399 { 6400 struct rtw89_txq *rtwtxq; 6401 6402 if (!txq) 6403 return; 6404 6405 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6406 INIT_LIST_HEAD(&rtwtxq->list); 6407 } 6408 6409 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6410 { 6411 void *p = rtwvif; 6412 6413 return container_of(p, struct ieee80211_vif, drv_priv); 6414 } 6415 6416 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6417 { 6418 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6419 } 6420 6421 static inline 6422 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6423 { 6424 return rtwvif_to_vif(rtwvif_link->rtwvif); 6425 } 6426 6427 static inline 6428 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6429 { 6430 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6431 } 6432 6433 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6434 { 6435 return (struct rtw89_vif *)vif->drv_priv; 6436 } 6437 6438 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6439 { 6440 return vif ? vif_to_rtwvif(vif) : NULL; 6441 } 6442 6443 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6444 { 6445 void *p = rtwsta; 6446 6447 return container_of(p, struct ieee80211_sta, drv_priv); 6448 } 6449 6450 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6451 { 6452 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6453 } 6454 6455 static inline 6456 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6457 { 6458 return rtwsta_to_sta(rtwsta_link->rtwsta); 6459 } 6460 6461 static inline 6462 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6463 { 6464 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6465 } 6466 6467 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6468 { 6469 return (struct rtw89_sta *)sta->drv_priv; 6470 } 6471 6472 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6473 { 6474 return sta ? sta_to_rtwsta(sta) : NULL; 6475 } 6476 6477 static inline struct ieee80211_bss_conf * 6478 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6479 { 6480 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6481 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6482 struct rtw89_link_conf_container *snap; 6483 struct ieee80211_bss_conf *bss_conf; 6484 6485 snap = rcu_dereference(rtwvif->snap_link_confs); 6486 if (snap) { 6487 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6488 goto out; 6489 } 6490 6491 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6492 6493 out: 6494 if (unlikely(!bss_conf)) { 6495 *nolink = true; 6496 return &vif->bss_conf; 6497 } 6498 6499 *nolink = false; 6500 return bss_conf; 6501 } 6502 6503 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6504 ({ \ 6505 typeof(rtwvif_link) p = rtwvif_link; \ 6506 struct ieee80211_bss_conf *bss_conf; \ 6507 bool nolink; \ 6508 \ 6509 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6510 if (unlikely(nolink) && (assert)) \ 6511 rtw89_err(p->rtwvif->rtwdev, \ 6512 "%s: cannot find exact bss_conf for link_id %u\n",\ 6513 __func__, p->link_id); \ 6514 bss_conf; \ 6515 }) 6516 6517 static inline struct ieee80211_link_sta * 6518 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6519 { 6520 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6521 struct ieee80211_link_sta *link_sta; 6522 6523 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6524 if (unlikely(!link_sta)) { 6525 *nolink = true; 6526 return &sta->deflink; 6527 } 6528 6529 *nolink = false; 6530 return link_sta; 6531 } 6532 6533 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6534 ({ \ 6535 typeof(rtwsta_link) p = rtwsta_link; \ 6536 struct ieee80211_link_sta *link_sta; \ 6537 bool nolink; \ 6538 \ 6539 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6540 if (unlikely(nolink) && (assert)) \ 6541 rtw89_err(p->rtwsta->rtwdev, \ 6542 "%s: cannot find exact link_sta for link_id %u\n",\ 6543 __func__, p->link_id); \ 6544 link_sta; \ 6545 }) 6546 6547 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6548 { 6549 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6550 return RATE_INFO_BW_160; 6551 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6552 return RATE_INFO_BW_80; 6553 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6554 return RATE_INFO_BW_40; 6555 else 6556 return RATE_INFO_BW_20; 6557 } 6558 6559 static inline 6560 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6561 { 6562 switch (hw_band) { 6563 default: 6564 case RTW89_BAND_2G: 6565 return NL80211_BAND_2GHZ; 6566 case RTW89_BAND_5G: 6567 return NL80211_BAND_5GHZ; 6568 case RTW89_BAND_6G: 6569 return NL80211_BAND_6GHZ; 6570 } 6571 } 6572 6573 static inline 6574 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6575 { 6576 switch (nl_band) { 6577 default: 6578 case NL80211_BAND_2GHZ: 6579 return RTW89_BAND_2G; 6580 case NL80211_BAND_5GHZ: 6581 return RTW89_BAND_5G; 6582 case NL80211_BAND_6GHZ: 6583 return RTW89_BAND_6G; 6584 } 6585 } 6586 6587 static inline 6588 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6589 { 6590 switch (width) { 6591 default: 6592 WARN(1, "Not support bandwidth %d\n", width); 6593 fallthrough; 6594 case NL80211_CHAN_WIDTH_20_NOHT: 6595 case NL80211_CHAN_WIDTH_20: 6596 return RTW89_CHANNEL_WIDTH_20; 6597 case NL80211_CHAN_WIDTH_40: 6598 return RTW89_CHANNEL_WIDTH_40; 6599 case NL80211_CHAN_WIDTH_80: 6600 return RTW89_CHANNEL_WIDTH_80; 6601 case NL80211_CHAN_WIDTH_160: 6602 return RTW89_CHANNEL_WIDTH_160; 6603 } 6604 } 6605 6606 static inline 6607 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6608 { 6609 switch (rua) { 6610 default: 6611 WARN(1, "Invalid RU allocation: %d\n", rua); 6612 fallthrough; 6613 case 0 ... 36: 6614 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6615 case 37 ... 52: 6616 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6617 case 53 ... 60: 6618 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6619 case 61 ... 64: 6620 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6621 case 65 ... 66: 6622 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6623 case 67: 6624 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6625 case 68: 6626 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6627 } 6628 } 6629 6630 static inline 6631 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6632 struct rtw89_sta_link *rtwsta_link) 6633 { 6634 if (rtwsta_link) { 6635 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6636 6637 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6638 return &rtwsta_link->addr_cam; 6639 } 6640 return &rtwvif_link->addr_cam; 6641 } 6642 6643 static inline 6644 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6645 struct rtw89_sta_link *rtwsta_link) 6646 { 6647 if (rtwsta_link) { 6648 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6649 6650 if (sta->tdls) 6651 return &rtwsta_link->bssid_cam; 6652 } 6653 return &rtwvif_link->bssid_cam; 6654 } 6655 6656 static inline 6657 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6658 struct rtw89_channel_help_params *p, 6659 const struct rtw89_chan *chan, 6660 enum rtw89_mac_idx mac_idx, 6661 enum rtw89_phy_idx phy_idx) 6662 { 6663 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6664 mac_idx, phy_idx); 6665 } 6666 6667 static inline 6668 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6669 struct rtw89_channel_help_params *p, 6670 const struct rtw89_chan *chan, 6671 enum rtw89_mac_idx mac_idx, 6672 enum rtw89_phy_idx phy_idx) 6673 { 6674 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6675 mac_idx, phy_idx); 6676 } 6677 6678 static inline 6679 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6680 enum rtw89_chanctx_idx idx) 6681 { 6682 struct rtw89_hal *hal = &rtwdev->hal; 6683 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6684 6685 if (roc_idx == idx) 6686 return &hal->roc_chandef; 6687 6688 return &hal->chanctx[idx].chandef; 6689 } 6690 6691 static inline 6692 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6693 enum rtw89_chanctx_idx idx) 6694 { 6695 struct rtw89_hal *hal = &rtwdev->hal; 6696 6697 return &hal->chanctx[idx].chan; 6698 } 6699 6700 static inline 6701 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6702 enum rtw89_chanctx_idx idx) 6703 { 6704 struct rtw89_hal *hal = &rtwdev->hal; 6705 6706 return &hal->chanctx[idx].rcd; 6707 } 6708 6709 static inline 6710 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6711 { 6712 const struct rtw89_chanctx *chanctx = 6713 container_of_const(chan, struct rtw89_chanctx, chan); 6714 6715 return &chanctx->rcd; 6716 } 6717 6718 static inline 6719 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6720 { 6721 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6722 6723 if (rtwvif_link) 6724 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6725 else 6726 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6727 } 6728 6729 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6730 { 6731 const struct rtw89_chip_info *chip = rtwdev->chip; 6732 6733 if (chip->ops->fem_setup) 6734 chip->ops->fem_setup(rtwdev); 6735 } 6736 6737 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6738 { 6739 const struct rtw89_chip_info *chip = rtwdev->chip; 6740 6741 if (chip->ops->rfe_gpio) 6742 chip->ops->rfe_gpio(rtwdev); 6743 } 6744 6745 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6746 { 6747 const struct rtw89_chip_info *chip = rtwdev->chip; 6748 6749 if (chip->ops->rfk_hw_init) 6750 chip->ops->rfk_hw_init(rtwdev); 6751 } 6752 6753 static inline 6754 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6755 { 6756 const struct rtw89_chip_info *chip = rtwdev->chip; 6757 6758 if (chip->ops->bb_preinit) 6759 chip->ops->bb_preinit(rtwdev, phy_idx); 6760 } 6761 6762 static inline 6763 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6764 { 6765 const struct rtw89_chip_info *chip = rtwdev->chip; 6766 6767 if (!chip->ops->bb_postinit) 6768 return; 6769 6770 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6771 6772 if (rtwdev->dbcc_en) 6773 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6774 } 6775 6776 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6777 { 6778 const struct rtw89_chip_info *chip = rtwdev->chip; 6779 6780 if (chip->ops->bb_sethw) 6781 chip->ops->bb_sethw(rtwdev); 6782 } 6783 6784 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6785 { 6786 const struct rtw89_chip_info *chip = rtwdev->chip; 6787 6788 if (chip->ops->rfk_init) 6789 chip->ops->rfk_init(rtwdev); 6790 } 6791 6792 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6793 { 6794 const struct rtw89_chip_info *chip = rtwdev->chip; 6795 6796 if (chip->ops->rfk_init_late) 6797 chip->ops->rfk_init_late(rtwdev); 6798 } 6799 6800 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6801 struct rtw89_vif_link *rtwvif_link) 6802 { 6803 const struct rtw89_chip_info *chip = rtwdev->chip; 6804 6805 if (chip->ops->rfk_channel) 6806 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6807 } 6808 6809 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6810 enum rtw89_phy_idx phy_idx, 6811 const struct rtw89_chan *chan) 6812 { 6813 const struct rtw89_chip_info *chip = rtwdev->chip; 6814 6815 if (chip->ops->rfk_band_changed) 6816 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6817 } 6818 6819 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6820 struct rtw89_vif_link *rtwvif_link, bool start) 6821 { 6822 const struct rtw89_chip_info *chip = rtwdev->chip; 6823 6824 if (chip->ops->rfk_scan) 6825 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6826 } 6827 6828 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6829 { 6830 const struct rtw89_chip_info *chip = rtwdev->chip; 6831 6832 if (chip->ops->rfk_track) 6833 chip->ops->rfk_track(rtwdev); 6834 } 6835 6836 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6837 { 6838 const struct rtw89_chip_info *chip = rtwdev->chip; 6839 6840 if (!chip->ops->set_txpwr_ctrl) 6841 return; 6842 6843 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6844 if (rtwdev->dbcc_en) 6845 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6846 } 6847 6848 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6849 { 6850 const struct rtw89_chip_info *chip = rtwdev->chip; 6851 6852 if (chip->ops->power_trim) 6853 chip->ops->power_trim(rtwdev); 6854 } 6855 6856 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6857 enum rtw89_phy_idx phy_idx) 6858 { 6859 const struct rtw89_chip_info *chip = rtwdev->chip; 6860 6861 if (chip->ops->init_txpwr_unit) 6862 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6863 } 6864 6865 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6866 { 6867 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6868 if (rtwdev->dbcc_en) 6869 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6870 } 6871 6872 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6873 enum rtw89_rf_path rf_path) 6874 { 6875 const struct rtw89_chip_info *chip = rtwdev->chip; 6876 6877 if (!chip->ops->get_thermal) 6878 return 0x10; 6879 6880 return chip->ops->get_thermal(rtwdev, rf_path); 6881 } 6882 6883 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6884 struct rtw89_rx_phy_ppdu *phy_ppdu, 6885 struct ieee80211_rx_status *status) 6886 { 6887 const struct rtw89_chip_info *chip = rtwdev->chip; 6888 6889 if (chip->ops->query_ppdu) 6890 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6891 } 6892 6893 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 6894 struct rtw89_rx_phy_ppdu *phy_ppdu) 6895 { 6896 const struct rtw89_chip_info *chip = rtwdev->chip; 6897 6898 if (chip->ops->convert_rpl_to_rssi) 6899 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 6900 } 6901 6902 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 6903 struct rtw89_rx_desc_info *desc_info, 6904 struct ieee80211_rx_status *rx_status) 6905 { 6906 const struct rtw89_chip_info *chip = rtwdev->chip; 6907 6908 if (chip->ops->phy_rpt_to_rssi) 6909 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 6910 } 6911 6912 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6913 enum rtw89_phy_idx phy_idx) 6914 { 6915 const struct rtw89_chip_info *chip = rtwdev->chip; 6916 6917 if (chip->ops->ctrl_nbtg_bt_tx) 6918 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6919 } 6920 6921 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6922 { 6923 const struct rtw89_chip_info *chip = rtwdev->chip; 6924 6925 if (chip->ops->cfg_txrx_path) 6926 chip->ops->cfg_txrx_path(rtwdev); 6927 } 6928 6929 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 6930 enum rtw89_phy_idx phy_idx) 6931 { 6932 const struct rtw89_chip_info *chip = rtwdev->chip; 6933 6934 if (chip->ops->digital_pwr_comp) 6935 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 6936 } 6937 6938 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6939 const struct rtw89_txpwr_table *tbl) 6940 { 6941 tbl->load(rtwdev, tbl); 6942 } 6943 6944 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6945 { 6946 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 6947 const struct rtw89_regd *regd = regulatory->regd; 6948 u8 txpwr_regd = regd->txpwr_regd[band]; 6949 6950 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK) 6951 return RTW89_ETSI; 6952 6953 return txpwr_regd; 6954 } 6955 6956 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6957 enum rtw89_phy_idx phy_idx) 6958 { 6959 const struct rtw89_chip_info *chip = rtwdev->chip; 6960 6961 if (chip->ops->ctrl_btg_bt_rx) 6962 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6963 } 6964 6965 static inline 6966 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6967 struct rtw89_rx_desc_info *desc_info, 6968 u8 *data, u32 data_offset) 6969 { 6970 const struct rtw89_chip_info *chip = rtwdev->chip; 6971 6972 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6973 } 6974 6975 static inline 6976 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6977 struct rtw89_tx_desc_info *desc_info, 6978 void *txdesc) 6979 { 6980 const struct rtw89_chip_info *chip = rtwdev->chip; 6981 6982 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6983 } 6984 6985 static inline 6986 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6987 struct rtw89_tx_desc_info *desc_info, 6988 void *txdesc) 6989 { 6990 const struct rtw89_chip_info *chip = rtwdev->chip; 6991 6992 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6993 } 6994 6995 static inline 6996 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6997 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6998 { 6999 const struct rtw89_chip_info *chip = rtwdev->chip; 7000 7001 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 7002 } 7003 7004 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 7005 { 7006 const struct rtw89_chip_info *chip = rtwdev->chip; 7007 7008 chip->ops->cfg_ctrl_path(rtwdev, wl); 7009 } 7010 7011 static inline 7012 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 7013 u32 *tx_en, enum rtw89_sch_tx_sel sel) 7014 { 7015 const struct rtw89_chip_info *chip = rtwdev->chip; 7016 7017 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 7018 } 7019 7020 static inline 7021 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 7022 { 7023 const struct rtw89_chip_info *chip = rtwdev->chip; 7024 7025 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 7026 } 7027 7028 static inline 7029 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 7030 struct rtw89_vif_link *rtwvif_link, 7031 struct rtw89_sta_link *rtwsta_link) 7032 { 7033 const struct rtw89_chip_info *chip = rtwdev->chip; 7034 7035 if (!chip->ops->h2c_dctl_sec_cam) 7036 return 0; 7037 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 7038 } 7039 7040 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 7041 { 7042 __le16 fc = hdr->frame_control; 7043 7044 if (ieee80211_has_tods(fc)) 7045 return hdr->addr1; 7046 else if (ieee80211_has_fromds(fc)) 7047 return hdr->addr2; 7048 else 7049 return hdr->addr3; 7050 } 7051 7052 static inline 7053 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 7054 { 7055 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 7056 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 7057 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 7058 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 7059 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 7060 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 7061 return true; 7062 return false; 7063 } 7064 7065 static inline 7066 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 7067 { 7068 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 7069 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 7070 return true; 7071 7072 return false; 7073 } 7074 7075 static inline 7076 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 7077 { 7078 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 7079 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 7080 return true; 7081 7082 return false; 7083 } 7084 7085 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 7086 enum rtw89_fw_type type) 7087 { 7088 struct rtw89_fw_info *fw_info = &rtwdev->fw; 7089 7090 switch (type) { 7091 case RTW89_FW_WOWLAN: 7092 return &fw_info->wowlan; 7093 case RTW89_FW_LOGFMT: 7094 return &fw_info->log.suit; 7095 case RTW89_FW_BBMCU0: 7096 return &fw_info->bbmcu0; 7097 case RTW89_FW_BBMCU1: 7098 return &fw_info->bbmcu1; 7099 default: 7100 break; 7101 } 7102 7103 return &fw_info->normal; 7104 } 7105 7106 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 7107 unsigned int length) 7108 { 7109 struct sk_buff *skb; 7110 7111 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 7112 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 7113 if (!skb) 7114 return NULL; 7115 7116 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 7117 return skb; 7118 } 7119 7120 return dev_alloc_skb(length); 7121 } 7122 7123 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7124 struct rtw89_tx_skb_data *skb_data, 7125 bool tx_done) 7126 { 7127 struct rtw89_tx_wait_info *wait; 7128 7129 rcu_read_lock(); 7130 7131 wait = rcu_dereference(skb_data->wait); 7132 if (!wait) 7133 goto out; 7134 7135 wait->tx_done = tx_done; 7136 complete(&wait->completion); 7137 7138 out: 7139 rcu_read_unlock(); 7140 } 7141 7142 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 7143 { 7144 switch (rtwdev->mlo_dbcc_mode) { 7145 case MLO_1_PLUS_1_1RF: 7146 case MLO_1_PLUS_1_2RF: 7147 case DBCC_LEGACY: 7148 return true; 7149 default: 7150 return false; 7151 } 7152 } 7153 7154 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 7155 { 7156 if (!rtwdev->dbcc_en) 7157 return BIT(RTW89_PHY_0); 7158 7159 switch (rtwdev->mlo_dbcc_mode) { 7160 case MLO_0_PLUS_2_1RF: 7161 case MLO_0_PLUS_2_2RF: 7162 return BIT(RTW89_PHY_1); 7163 case MLO_1_PLUS_1_1RF: 7164 case MLO_1_PLUS_1_2RF: 7165 case MLO_2_PLUS_2_2RF: 7166 case DBCC_LEGACY: 7167 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 7168 case MLO_2_PLUS_0_1RF: 7169 case MLO_2_PLUS_0_2RF: 7170 default: 7171 return BIT(RTW89_PHY_0); 7172 } 7173 } 7174 7175 #define rtw89_for_each_active_bb(rtwdev, bb) \ 7176 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 7177 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 7178 if (__active_bb_bitmap & BIT(__phy_idx) && \ 7179 (bb = &rtwdev->bbs[__phy_idx])) 7180 7181 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 7182 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 7183 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 7184 if ((bb = &rtwdev->bbs[__phy_idx])) 7185 7186 static inline 7187 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 7188 enum rtw89_phy_idx phy_idx) 7189 { 7190 if (phy_idx >= RTW89_PHY_NUM) 7191 return &rtwdev->bbs[RTW89_PHY_0]; 7192 7193 return &rtwdev->bbs[phy_idx]; 7194 } 7195 7196 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7197 { 7198 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7199 7200 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7201 return true; 7202 7203 return false; 7204 } 7205 7206 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7207 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7208 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7209 struct sk_buff *skb, bool fwdl); 7210 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7211 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7212 int qsel, unsigned int timeout); 7213 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7214 struct rtw89_tx_desc_info *desc_info, 7215 void *txdesc); 7216 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7217 struct rtw89_tx_desc_info *desc_info, 7218 void *txdesc); 7219 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7220 struct rtw89_tx_desc_info *desc_info, 7221 void *txdesc); 7222 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7223 struct rtw89_tx_desc_info *desc_info, 7224 void *txdesc); 7225 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7226 struct rtw89_tx_desc_info *desc_info, 7227 void *txdesc); 7228 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7229 struct rtw89_rx_desc_info *desc_info, 7230 struct sk_buff *skb); 7231 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7232 struct rtw89_rx_desc_info *desc_info, 7233 u8 *data, u32 data_offset); 7234 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7235 struct rtw89_rx_desc_info *desc_info, 7236 u8 *data, u32 data_offset); 7237 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7238 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7239 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7240 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7241 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7242 struct rtw89_vif_link *rtwvif_link, 7243 struct rtw89_sta_link *rtwsta_link); 7244 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7245 struct rtw89_vif_link *rtwvif_link, 7246 struct rtw89_sta_link *rtwsta_link); 7247 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7248 struct rtw89_vif_link *rtwvif_link, 7249 struct rtw89_sta_link *rtwsta_link); 7250 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7251 struct rtw89_vif_link *rtwvif_link, 7252 struct rtw89_sta_link *rtwsta_link); 7253 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7254 struct rtw89_vif_link *rtwvif_link, 7255 struct rtw89_sta_link *rtwsta_link); 7256 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7257 struct ieee80211_sta *sta, 7258 struct cfg80211_tid_config *tid_config); 7259 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7260 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7261 int rtw89_core_init(struct rtw89_dev *rtwdev); 7262 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7263 int rtw89_core_register(struct rtw89_dev *rtwdev); 7264 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7265 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7266 u32 bus_data_size, 7267 const struct rtw89_chip_info *chip, 7268 const struct rtw89_chip_variant *variant); 7269 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7270 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7271 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7272 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7273 u8 mac_id, u8 port); 7274 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7275 struct rtw89_sta *rtwsta, u8 mac_id); 7276 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7277 unsigned int link_id); 7278 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7279 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7280 unsigned int link_id); 7281 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7282 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7283 const struct rtw89_6ghz_span * 7284 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7285 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7286 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7287 struct rtw89_chan *chan); 7288 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7289 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7290 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7291 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7292 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7293 struct rtw89_sta_link *rtwsta_link, u8 tid, 7294 u8 *cam_idx); 7295 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7296 struct rtw89_sta_link *rtwsta_link, u8 tid, 7297 u8 *cam_idx); 7298 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7299 struct ieee80211_sta *sta); 7300 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7301 struct ieee80211_sta *sta); 7302 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7303 struct ieee80211_sta *sta); 7304 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7305 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7306 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7307 struct rtw89_vif_link *rtwvif_link); 7308 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 7309 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7310 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7311 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 7312 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7313 struct rtw89_traffic_stats *stats); 7314 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 7315 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7316 const struct rtw89_completion_data *data); 7317 int rtw89_core_start(struct rtw89_dev *rtwdev); 7318 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7319 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7320 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 7321 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7322 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7323 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7324 const u8 *mac_addr, bool hw_scan); 7325 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7326 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7327 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7328 bool active); 7329 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7330 struct rtw89_vif_link *rtwvif_link, 7331 struct ieee80211_bss_conf *bss_conf); 7332 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7333 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7334 unsigned int link_id); 7335 7336 #endif 7337