1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_efuse_block_cfg; 21 struct rtw89_h2c_rf_tssi; 22 struct rtw89_fw_txpwr_track_cfg; 23 struct rtw89_phy_rfk_log_fmt; 24 25 extern const struct ieee80211_ops rtw89_ops; 26 27 #define MASKBYTE0 0xff 28 #define MASKBYTE1 0xff00 29 #define MASKBYTE2 0xff0000 30 #define MASKBYTE3 0xff000000 31 #define MASKBYTE4 0xff00000000ULL 32 #define MASKHWORD 0xffff0000 33 #define MASKLWORD 0x0000ffff 34 #define MASKDWORD 0xffffffff 35 #define RFREG_MASK 0xfffff 36 #define INV_RF_DATA 0xffffffff 37 #define BYPASS_CR_DATA 0xbabecafe 38 39 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 40 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 41 #define CFO_TRACK_MAX_USER 64 42 #define MAX_RSSI 110 43 #define RSSI_FACTOR 1 44 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 45 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 46 #define DELTA_SWINGIDX_SIZE 30 47 48 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 49 #define RTW89_RADIOTAP_ROOM_EHT \ 50 (sizeof(struct ieee80211_radiotap_tlv) + \ 51 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 52 sizeof(struct ieee80211_radiotap_tlv) + \ 53 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 54 #define RTW89_RADIOTAP_ROOM \ 55 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 56 57 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 58 #define RTW89_HTC_VARIANT_HE 3 59 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 60 #define RTW89_HTC_VARIANT_HE_CID_OM 1 61 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 62 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 63 64 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 65 enum htc_om_channel_width { 66 HTC_OM_CHANNEL_WIDTH_20 = 0, 67 HTC_OM_CHANNEL_WIDTH_40 = 1, 68 HTC_OM_CHANNEL_WIDTH_80 = 2, 69 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 70 }; 71 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 72 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 73 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 74 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 75 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 76 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 77 78 #define RTW89_TF_PAD GENMASK(11, 0) 79 #define RTW89_TF_BASIC_USER_INFO_SZ 6 80 81 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 82 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 83 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 84 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 85 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 86 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 87 88 enum rtw89_subband { 89 RTW89_CH_2G = 0, 90 RTW89_CH_5G_BAND_1 = 1, 91 /* RTW89_CH_5G_BAND_2 = 2, unused */ 92 RTW89_CH_5G_BAND_3 = 3, 93 RTW89_CH_5G_BAND_4 = 4, 94 95 RTW89_CH_6G_BAND_IDX0, /* Low */ 96 RTW89_CH_6G_BAND_IDX1, /* Low */ 97 RTW89_CH_6G_BAND_IDX2, /* Mid */ 98 RTW89_CH_6G_BAND_IDX3, /* Mid */ 99 RTW89_CH_6G_BAND_IDX4, /* High */ 100 RTW89_CH_6G_BAND_IDX5, /* High */ 101 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 102 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 103 104 RTW89_SUBBAND_NR, 105 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 106 }; 107 108 enum rtw89_gain_offset { 109 RTW89_GAIN_OFFSET_2G_CCK, 110 RTW89_GAIN_OFFSET_2G_OFDM, 111 RTW89_GAIN_OFFSET_5G_LOW, 112 RTW89_GAIN_OFFSET_5G_MID, 113 RTW89_GAIN_OFFSET_5G_HIGH, 114 RTW89_GAIN_OFFSET_6G_L0, 115 RTW89_GAIN_OFFSET_6G_L1, 116 RTW89_GAIN_OFFSET_6G_M0, 117 RTW89_GAIN_OFFSET_6G_M1, 118 RTW89_GAIN_OFFSET_6G_H0, 119 RTW89_GAIN_OFFSET_6G_H1, 120 RTW89_GAIN_OFFSET_6G_UH0, 121 RTW89_GAIN_OFFSET_6G_UH1, 122 123 RTW89_GAIN_OFFSET_NR, 124 }; 125 126 enum rtw89_hci_type { 127 RTW89_HCI_TYPE_PCIE, 128 RTW89_HCI_TYPE_USB, 129 RTW89_HCI_TYPE_SDIO, 130 }; 131 132 enum rtw89_core_chip_id { 133 RTL8852A, 134 RTL8852B, 135 RTL8852C, 136 RTL8851B, 137 RTL8922A, 138 }; 139 140 enum rtw89_chip_gen { 141 RTW89_CHIP_AX, 142 RTW89_CHIP_BE, 143 144 RTW89_CHIP_GEN_NUM, 145 }; 146 147 enum rtw89_cv { 148 CHIP_CAV, 149 CHIP_CBV, 150 CHIP_CCV, 151 CHIP_CDV, 152 CHIP_CEV, 153 CHIP_CFV, 154 CHIP_CV_MAX, 155 CHIP_CV_INVALID = CHIP_CV_MAX, 156 }; 157 158 enum rtw89_bacam_ver { 159 RTW89_BACAM_V0, 160 RTW89_BACAM_V1, 161 162 RTW89_BACAM_V0_EXT = 99, 163 }; 164 165 enum rtw89_core_tx_type { 166 RTW89_CORE_TX_TYPE_DATA, 167 RTW89_CORE_TX_TYPE_MGMT, 168 RTW89_CORE_TX_TYPE_FWCMD, 169 }; 170 171 enum rtw89_core_rx_type { 172 RTW89_CORE_RX_TYPE_WIFI = 0, 173 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 174 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 175 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 176 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 177 RTW89_CORE_RX_TYPE_SS2FW = 5, 178 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 179 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 180 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 181 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 182 RTW89_CORE_RX_TYPE_C2H = 10, 183 RTW89_CORE_RX_TYPE_CSI = 11, 184 RTW89_CORE_RX_TYPE_CQI = 12, 185 RTW89_CORE_RX_TYPE_H2C = 13, 186 RTW89_CORE_RX_TYPE_FWDL = 14, 187 }; 188 189 enum rtw89_txq_flags { 190 RTW89_TXQ_F_AMPDU = 0, 191 RTW89_TXQ_F_BLOCK_BA = 1, 192 RTW89_TXQ_F_FORBID_BA = 2, 193 }; 194 195 enum rtw89_net_type { 196 RTW89_NET_TYPE_NO_LINK = 0, 197 RTW89_NET_TYPE_AD_HOC = 1, 198 RTW89_NET_TYPE_INFRA = 2, 199 RTW89_NET_TYPE_AP_MODE = 3, 200 }; 201 202 enum rtw89_wifi_role { 203 RTW89_WIFI_ROLE_NONE, 204 RTW89_WIFI_ROLE_STATION, 205 RTW89_WIFI_ROLE_AP, 206 RTW89_WIFI_ROLE_AP_VLAN, 207 RTW89_WIFI_ROLE_ADHOC, 208 RTW89_WIFI_ROLE_ADHOC_MASTER, 209 RTW89_WIFI_ROLE_MESH_POINT, 210 RTW89_WIFI_ROLE_MONITOR, 211 RTW89_WIFI_ROLE_P2P_DEVICE, 212 RTW89_WIFI_ROLE_P2P_CLIENT, 213 RTW89_WIFI_ROLE_P2P_GO, 214 RTW89_WIFI_ROLE_NAN, 215 RTW89_WIFI_ROLE_MLME_MAX 216 }; 217 218 enum rtw89_upd_mode { 219 RTW89_ROLE_CREATE, 220 RTW89_ROLE_REMOVE, 221 RTW89_ROLE_TYPE_CHANGE, 222 RTW89_ROLE_INFO_CHANGE, 223 RTW89_ROLE_CON_DISCONN, 224 RTW89_ROLE_BAND_SW, 225 RTW89_ROLE_FW_RESTORE, 226 }; 227 228 enum rtw89_self_role { 229 RTW89_SELF_ROLE_CLIENT, 230 RTW89_SELF_ROLE_AP, 231 RTW89_SELF_ROLE_AP_CLIENT 232 }; 233 234 enum rtw89_msk_sO_el { 235 RTW89_NO_MSK, 236 RTW89_SMA, 237 RTW89_TMA, 238 RTW89_BSSID 239 }; 240 241 enum rtw89_sch_tx_sel { 242 RTW89_SCH_TX_SEL_ALL, 243 RTW89_SCH_TX_SEL_HIQ, 244 RTW89_SCH_TX_SEL_MG0, 245 RTW89_SCH_TX_SEL_MACID, 246 }; 247 248 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 249 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 250 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 251 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 252 */ 253 enum rtw89_add_cam_sec_mode { 254 RTW89_ADDR_CAM_SEC_NONE = 0, 255 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 256 RTW89_ADDR_CAM_SEC_NORMAL = 2, 257 RTW89_ADDR_CAM_SEC_4GROUP = 3, 258 }; 259 260 enum rtw89_sec_key_type { 261 RTW89_SEC_KEY_TYPE_NONE = 0, 262 RTW89_SEC_KEY_TYPE_WEP40 = 1, 263 RTW89_SEC_KEY_TYPE_WEP104 = 2, 264 RTW89_SEC_KEY_TYPE_TKIP = 3, 265 RTW89_SEC_KEY_TYPE_WAPI = 4, 266 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 267 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 268 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 269 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 270 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 271 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 272 }; 273 274 enum rtw89_port { 275 RTW89_PORT_0 = 0, 276 RTW89_PORT_1 = 1, 277 RTW89_PORT_2 = 2, 278 RTW89_PORT_3 = 3, 279 RTW89_PORT_4 = 4, 280 RTW89_PORT_NUM 281 }; 282 283 enum rtw89_band { 284 RTW89_BAND_2G = 0, 285 RTW89_BAND_5G = 1, 286 RTW89_BAND_6G = 2, 287 RTW89_BAND_NUM, 288 }; 289 290 enum rtw89_hw_rate { 291 RTW89_HW_RATE_CCK1 = 0x0, 292 RTW89_HW_RATE_CCK2 = 0x1, 293 RTW89_HW_RATE_CCK5_5 = 0x2, 294 RTW89_HW_RATE_CCK11 = 0x3, 295 RTW89_HW_RATE_OFDM6 = 0x4, 296 RTW89_HW_RATE_OFDM9 = 0x5, 297 RTW89_HW_RATE_OFDM12 = 0x6, 298 RTW89_HW_RATE_OFDM18 = 0x7, 299 RTW89_HW_RATE_OFDM24 = 0x8, 300 RTW89_HW_RATE_OFDM36 = 0x9, 301 RTW89_HW_RATE_OFDM48 = 0xA, 302 RTW89_HW_RATE_OFDM54 = 0xB, 303 RTW89_HW_RATE_MCS0 = 0x80, 304 RTW89_HW_RATE_MCS1 = 0x81, 305 RTW89_HW_RATE_MCS2 = 0x82, 306 RTW89_HW_RATE_MCS3 = 0x83, 307 RTW89_HW_RATE_MCS4 = 0x84, 308 RTW89_HW_RATE_MCS5 = 0x85, 309 RTW89_HW_RATE_MCS6 = 0x86, 310 RTW89_HW_RATE_MCS7 = 0x87, 311 RTW89_HW_RATE_MCS8 = 0x88, 312 RTW89_HW_RATE_MCS9 = 0x89, 313 RTW89_HW_RATE_MCS10 = 0x8A, 314 RTW89_HW_RATE_MCS11 = 0x8B, 315 RTW89_HW_RATE_MCS12 = 0x8C, 316 RTW89_HW_RATE_MCS13 = 0x8D, 317 RTW89_HW_RATE_MCS14 = 0x8E, 318 RTW89_HW_RATE_MCS15 = 0x8F, 319 RTW89_HW_RATE_MCS16 = 0x90, 320 RTW89_HW_RATE_MCS17 = 0x91, 321 RTW89_HW_RATE_MCS18 = 0x92, 322 RTW89_HW_RATE_MCS19 = 0x93, 323 RTW89_HW_RATE_MCS20 = 0x94, 324 RTW89_HW_RATE_MCS21 = 0x95, 325 RTW89_HW_RATE_MCS22 = 0x96, 326 RTW89_HW_RATE_MCS23 = 0x97, 327 RTW89_HW_RATE_MCS24 = 0x98, 328 RTW89_HW_RATE_MCS25 = 0x99, 329 RTW89_HW_RATE_MCS26 = 0x9A, 330 RTW89_HW_RATE_MCS27 = 0x9B, 331 RTW89_HW_RATE_MCS28 = 0x9C, 332 RTW89_HW_RATE_MCS29 = 0x9D, 333 RTW89_HW_RATE_MCS30 = 0x9E, 334 RTW89_HW_RATE_MCS31 = 0x9F, 335 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 336 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 337 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 338 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 339 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 340 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 341 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 342 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 343 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 344 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 345 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 346 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 347 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 348 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 349 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 350 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 351 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 352 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 353 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 354 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 355 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 356 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 357 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 358 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 359 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 360 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 361 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 362 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 363 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 364 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 365 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 366 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 367 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 368 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 369 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 370 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 371 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 372 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 373 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 374 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 375 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 376 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 377 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 378 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 379 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 380 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 381 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 382 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 383 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 384 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 385 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 386 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 387 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 388 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 389 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 390 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 391 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 392 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 393 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 394 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 395 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 396 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 397 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 398 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 399 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 400 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 401 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 402 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 403 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 404 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 405 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 406 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 407 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 408 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 409 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 410 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 411 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 412 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 413 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 414 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 415 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 416 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 417 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 418 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 419 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 420 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 421 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 422 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 423 424 RTW89_HW_RATE_V1_MCS0 = 0x100, 425 RTW89_HW_RATE_V1_MCS1 = 0x101, 426 RTW89_HW_RATE_V1_MCS2 = 0x102, 427 RTW89_HW_RATE_V1_MCS3 = 0x103, 428 RTW89_HW_RATE_V1_MCS4 = 0x104, 429 RTW89_HW_RATE_V1_MCS5 = 0x105, 430 RTW89_HW_RATE_V1_MCS6 = 0x106, 431 RTW89_HW_RATE_V1_MCS7 = 0x107, 432 RTW89_HW_RATE_V1_MCS8 = 0x108, 433 RTW89_HW_RATE_V1_MCS9 = 0x109, 434 RTW89_HW_RATE_V1_MCS10 = 0x10A, 435 RTW89_HW_RATE_V1_MCS11 = 0x10B, 436 RTW89_HW_RATE_V1_MCS12 = 0x10C, 437 RTW89_HW_RATE_V1_MCS13 = 0x10D, 438 RTW89_HW_RATE_V1_MCS14 = 0x10E, 439 RTW89_HW_RATE_V1_MCS15 = 0x10F, 440 RTW89_HW_RATE_V1_MCS16 = 0x110, 441 RTW89_HW_RATE_V1_MCS17 = 0x111, 442 RTW89_HW_RATE_V1_MCS18 = 0x112, 443 RTW89_HW_RATE_V1_MCS19 = 0x113, 444 RTW89_HW_RATE_V1_MCS20 = 0x114, 445 RTW89_HW_RATE_V1_MCS21 = 0x115, 446 RTW89_HW_RATE_V1_MCS22 = 0x116, 447 RTW89_HW_RATE_V1_MCS23 = 0x117, 448 RTW89_HW_RATE_V1_MCS24 = 0x118, 449 RTW89_HW_RATE_V1_MCS25 = 0x119, 450 RTW89_HW_RATE_V1_MCS26 = 0x11A, 451 RTW89_HW_RATE_V1_MCS27 = 0x11B, 452 RTW89_HW_RATE_V1_MCS28 = 0x11C, 453 RTW89_HW_RATE_V1_MCS29 = 0x11D, 454 RTW89_HW_RATE_V1_MCS30 = 0x11E, 455 RTW89_HW_RATE_V1_MCS31 = 0x11F, 456 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 468 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 480 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 492 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 504 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 516 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 528 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 540 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 552 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 568 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 582 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 596 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 610 611 RTW89_HW_RATE_NR, 612 RTW89_HW_RATE_INVAL, 613 614 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 615 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 616 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 617 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 618 }; 619 620 /* 2G channels, 621 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 622 */ 623 #define RTW89_2G_CH_NUM 14 624 625 /* 5G channels, 626 * 36, 38, 40, 42, 44, 46, 48, 50, 627 * 52, 54, 56, 58, 60, 62, 64, 628 * 100, 102, 104, 106, 108, 110, 112, 114, 629 * 116, 118, 120, 122, 124, 126, 128, 130, 630 * 132, 134, 136, 138, 140, 142, 144, 631 * 149, 151, 153, 155, 157, 159, 161, 163, 632 * 165, 167, 169, 171, 173, 175, 177 633 */ 634 #define RTW89_5G_CH_NUM 53 635 636 /* 6G channels, 637 * 1, 3, 5, 7, 9, 11, 13, 15, 638 * 17, 19, 21, 23, 25, 27, 29, 33, 639 * 35, 37, 39, 41, 43, 45, 47, 49, 640 * 51, 53, 55, 57, 59, 61, 65, 67, 641 * 69, 71, 73, 75, 77, 79, 81, 83, 642 * 85, 87, 89, 91, 93, 97, 99, 101, 643 * 103, 105, 107, 109, 111, 113, 115, 117, 644 * 119, 121, 123, 125, 129, 131, 133, 135, 645 * 137, 139, 141, 143, 145, 147, 149, 151, 646 * 153, 155, 157, 161, 163, 165, 167, 169, 647 * 171, 173, 175, 177, 179, 181, 183, 185, 648 * 187, 189, 193, 195, 197, 199, 201, 203, 649 * 205, 207, 209, 211, 213, 215, 217, 219, 650 * 221, 225, 227, 229, 231, 233, 235, 237, 651 * 239, 241, 243, 245, 247, 249, 251, 253, 652 */ 653 #define RTW89_6G_CH_NUM 120 654 655 enum rtw89_rate_section { 656 RTW89_RS_CCK, 657 RTW89_RS_OFDM, 658 RTW89_RS_MCS, /* for HT/VHT/HE */ 659 RTW89_RS_HEDCM, 660 RTW89_RS_OFFSET, 661 RTW89_RS_NUM, 662 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 663 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 664 }; 665 666 enum rtw89_rate_offset_indexes { 667 RTW89_RATE_OFFSET_HE, 668 RTW89_RATE_OFFSET_VHT, 669 RTW89_RATE_OFFSET_HT, 670 RTW89_RATE_OFFSET_OFDM, 671 RTW89_RATE_OFFSET_CCK, 672 RTW89_RATE_OFFSET_DLRU_EHT, 673 RTW89_RATE_OFFSET_DLRU_HE, 674 RTW89_RATE_OFFSET_EHT, 675 __RTW89_RATE_OFFSET_NUM, 676 677 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 678 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 679 }; 680 681 enum rtw89_rate_num { 682 RTW89_RATE_CCK_NUM = 4, 683 RTW89_RATE_OFDM_NUM = 8, 684 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 685 686 RTW89_RATE_MCS_NUM_AX = 12, 687 RTW89_RATE_MCS_NUM_BE = 16, 688 __RTW89_RATE_MCS_NUM = 16, 689 }; 690 691 enum rtw89_nss { 692 RTW89_NSS_1 = 0, 693 RTW89_NSS_2 = 1, 694 /* HE DCM only support 1ss and 2ss */ 695 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 696 RTW89_NSS_3 = 2, 697 RTW89_NSS_4 = 3, 698 RTW89_NSS_NUM, 699 }; 700 701 enum rtw89_ntx { 702 RTW89_1TX = 0, 703 RTW89_2TX = 1, 704 RTW89_NTX_NUM, 705 }; 706 707 enum rtw89_beamforming_type { 708 RTW89_NONBF = 0, 709 RTW89_BF = 1, 710 RTW89_BF_NUM, 711 }; 712 713 enum rtw89_ofdma_type { 714 RTW89_NON_OFDMA = 0, 715 RTW89_OFDMA = 1, 716 RTW89_OFDMA_NUM, 717 }; 718 719 enum rtw89_regulation_type { 720 RTW89_WW = 0, 721 RTW89_ETSI = 1, 722 RTW89_FCC = 2, 723 RTW89_MKK = 3, 724 RTW89_NA = 4, 725 RTW89_IC = 5, 726 RTW89_KCC = 6, 727 RTW89_ACMA = 7, 728 RTW89_NCC = 8, 729 RTW89_MEXICO = 9, 730 RTW89_CHILE = 10, 731 RTW89_UKRAINE = 11, 732 RTW89_CN = 12, 733 RTW89_QATAR = 13, 734 RTW89_UK = 14, 735 RTW89_THAILAND = 15, 736 RTW89_REGD_NUM, 737 }; 738 739 enum rtw89_reg_6ghz_power { 740 RTW89_REG_6GHZ_POWER_VLP = 0, 741 RTW89_REG_6GHZ_POWER_LPI = 1, 742 RTW89_REG_6GHZ_POWER_STD = 2, 743 744 NUM_OF_RTW89_REG_6GHZ_POWER, 745 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 746 }; 747 748 enum rtw89_fw_pkt_ofld_type { 749 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 750 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 751 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 752 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 753 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 754 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 755 RTW89_PKT_OFLD_TYPE_NDP = 6, 756 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 757 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 758 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 759 RTW89_PKT_OFLD_TYPE_NUM, 760 }; 761 762 struct rtw89_txpwr_byrate { 763 s8 cck[RTW89_RATE_CCK_NUM]; 764 s8 ofdm[RTW89_RATE_OFDM_NUM]; 765 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 766 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 767 s8 offset[__RTW89_RATE_OFFSET_NUM]; 768 s8 trap; 769 }; 770 771 struct rtw89_rate_desc { 772 enum rtw89_nss nss; 773 enum rtw89_rate_section rs; 774 enum rtw89_ofdma_type ofdma; 775 u8 idx; 776 }; 777 778 #define PHY_STS_HDR_LEN 8 779 #define RF_PATH_MAX 4 780 #define RTW89_MAX_PPDU_CNT 8 781 struct rtw89_rx_phy_ppdu { 782 void *buf; 783 u32 len; 784 u8 rssi_avg; 785 u8 rssi[RF_PATH_MAX]; 786 u8 mac_id; 787 u8 chan_idx; 788 u8 ie; 789 u16 rate; 790 struct { 791 bool has; 792 u8 avg_snr; 793 u8 evm_max; 794 u8 evm_min; 795 } ofdm; 796 bool ldpc; 797 bool stbc; 798 bool to_self; 799 bool valid; 800 }; 801 802 enum rtw89_mac_idx { 803 RTW89_MAC_0 = 0, 804 RTW89_MAC_1 = 1, 805 RTW89_MAC_NUM, 806 }; 807 808 enum rtw89_phy_idx { 809 RTW89_PHY_0 = 0, 810 RTW89_PHY_1 = 1, 811 RTW89_PHY_MAX 812 }; 813 814 enum rtw89_sub_entity_idx { 815 RTW89_SUB_ENTITY_0 = 0, 816 RTW89_SUB_ENTITY_1 = 1, 817 818 NUM_OF_RTW89_SUB_ENTITY, 819 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 820 }; 821 822 enum rtw89_rf_path { 823 RF_PATH_A = 0, 824 RF_PATH_B = 1, 825 RF_PATH_C = 2, 826 RF_PATH_D = 3, 827 RF_PATH_AB, 828 RF_PATH_AC, 829 RF_PATH_AD, 830 RF_PATH_BC, 831 RF_PATH_BD, 832 RF_PATH_CD, 833 RF_PATH_ABC, 834 RF_PATH_ABD, 835 RF_PATH_ACD, 836 RF_PATH_BCD, 837 RF_PATH_ABCD, 838 }; 839 840 enum rtw89_rf_path_bit { 841 RF_A = BIT(0), 842 RF_B = BIT(1), 843 RF_C = BIT(2), 844 RF_D = BIT(3), 845 846 RF_AB = (RF_A | RF_B), 847 RF_AC = (RF_A | RF_C), 848 RF_AD = (RF_A | RF_D), 849 RF_BC = (RF_B | RF_C), 850 RF_BD = (RF_B | RF_D), 851 RF_CD = (RF_C | RF_D), 852 853 RF_ABC = (RF_A | RF_B | RF_C), 854 RF_ABD = (RF_A | RF_B | RF_D), 855 RF_ACD = (RF_A | RF_C | RF_D), 856 RF_BCD = (RF_B | RF_C | RF_D), 857 858 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 859 }; 860 861 enum rtw89_bandwidth { 862 RTW89_CHANNEL_WIDTH_20 = 0, 863 RTW89_CHANNEL_WIDTH_40 = 1, 864 RTW89_CHANNEL_WIDTH_80 = 2, 865 RTW89_CHANNEL_WIDTH_160 = 3, 866 RTW89_CHANNEL_WIDTH_320 = 4, 867 868 /* keep index order above */ 869 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 870 871 RTW89_CHANNEL_WIDTH_80_80 = 5, 872 RTW89_CHANNEL_WIDTH_5 = 6, 873 RTW89_CHANNEL_WIDTH_10 = 7, 874 }; 875 876 enum rtw89_ps_mode { 877 RTW89_PS_MODE_NONE = 0, 878 RTW89_PS_MODE_RFOFF = 1, 879 RTW89_PS_MODE_CLK_GATED = 2, 880 RTW89_PS_MODE_PWR_GATED = 3, 881 }; 882 883 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 884 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 885 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 886 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 887 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 888 889 enum rtw89_pe_duration { 890 RTW89_PE_DURATION_0 = 0, 891 RTW89_PE_DURATION_8 = 1, 892 RTW89_PE_DURATION_16 = 2, 893 RTW89_PE_DURATION_16_20 = 3, 894 }; 895 896 enum rtw89_ru_bandwidth { 897 RTW89_RU26 = 0, 898 RTW89_RU52 = 1, 899 RTW89_RU106 = 2, 900 RTW89_RU52_26 = 3, 901 RTW89_RU106_26 = 4, 902 RTW89_RU_NUM, 903 }; 904 905 enum rtw89_sc_offset { 906 RTW89_SC_DONT_CARE = 0, 907 RTW89_SC_20_UPPER = 1, 908 RTW89_SC_20_LOWER = 2, 909 RTW89_SC_20_UPMOST = 3, 910 RTW89_SC_20_LOWEST = 4, 911 RTW89_SC_20_UP2X = 5, 912 RTW89_SC_20_LOW2X = 6, 913 RTW89_SC_20_UP3X = 7, 914 RTW89_SC_20_LOW3X = 8, 915 RTW89_SC_40_UPPER = 9, 916 RTW89_SC_40_LOWER = 10, 917 }; 918 919 enum rtw89_wow_flags { 920 RTW89_WOW_FLAG_EN_MAGIC_PKT, 921 RTW89_WOW_FLAG_EN_REKEY_PKT, 922 RTW89_WOW_FLAG_EN_DISCONNECT, 923 RTW89_WOW_FLAG_NUM, 924 }; 925 926 struct rtw89_chan { 927 u8 channel; 928 u8 primary_channel; 929 enum rtw89_band band_type; 930 enum rtw89_bandwidth band_width; 931 932 /* The follow-up are derived from the above. We must ensure that it 933 * is assigned correctly in rtw89_chan_create() if new one is added. 934 */ 935 u32 freq; 936 enum rtw89_subband subband_type; 937 enum rtw89_sc_offset pri_ch_idx; 938 u8 pri_sb_idx; 939 }; 940 941 struct rtw89_chan_rcd { 942 u8 prev_primary_channel; 943 enum rtw89_band prev_band_type; 944 bool band_changed; 945 }; 946 947 struct rtw89_channel_help_params { 948 u32 tx_en; 949 }; 950 951 struct rtw89_port_reg { 952 u32 port_cfg; 953 u32 tbtt_prohib; 954 u32 bcn_area; 955 u32 bcn_early; 956 u32 tbtt_early; 957 u32 tbtt_agg; 958 u32 bcn_space; 959 u32 bcn_forcetx; 960 u32 bcn_err_cnt; 961 u32 bcn_err_flag; 962 u32 dtim_ctrl; 963 u32 tbtt_shift; 964 u32 bcn_cnt_tmr; 965 u32 tsftr_l; 966 u32 tsftr_h; 967 u32 md_tsft; 968 u32 bss_color; 969 u32 mbssid; 970 u32 mbssid_drop; 971 u32 tsf_sync; 972 u32 ptcl_dbg; 973 u32 ptcl_dbg_info; 974 u32 bcn_drop_all; 975 u32 hiq_win[RTW89_PORT_NUM]; 976 }; 977 978 struct rtw89_txwd_body { 979 __le32 dword0; 980 __le32 dword1; 981 __le32 dword2; 982 __le32 dword3; 983 __le32 dword4; 984 __le32 dword5; 985 } __packed; 986 987 struct rtw89_txwd_body_v1 { 988 __le32 dword0; 989 __le32 dword1; 990 __le32 dword2; 991 __le32 dword3; 992 __le32 dword4; 993 __le32 dword5; 994 __le32 dword6; 995 __le32 dword7; 996 } __packed; 997 998 struct rtw89_txwd_body_v2 { 999 __le32 dword0; 1000 __le32 dword1; 1001 __le32 dword2; 1002 __le32 dword3; 1003 __le32 dword4; 1004 __le32 dword5; 1005 __le32 dword6; 1006 __le32 dword7; 1007 } __packed; 1008 1009 struct rtw89_txwd_info { 1010 __le32 dword0; 1011 __le32 dword1; 1012 __le32 dword2; 1013 __le32 dword3; 1014 __le32 dword4; 1015 __le32 dword5; 1016 } __packed; 1017 1018 struct rtw89_txwd_info_v2 { 1019 __le32 dword0; 1020 __le32 dword1; 1021 __le32 dword2; 1022 __le32 dword3; 1023 __le32 dword4; 1024 __le32 dword5; 1025 __le32 dword6; 1026 __le32 dword7; 1027 } __packed; 1028 1029 struct rtw89_rx_desc_info { 1030 u16 pkt_size; 1031 u8 pkt_type; 1032 u8 drv_info_size; 1033 u8 phy_rpt_size; 1034 u8 hdr_cnv_size; 1035 u8 shift; 1036 u8 wl_hd_iv_len; 1037 bool long_rxdesc; 1038 bool bb_sel; 1039 bool mac_info_valid; 1040 u16 data_rate; 1041 u8 gi_ltf; 1042 u8 bw; 1043 u32 free_run_cnt; 1044 u8 user_id; 1045 bool sr_en; 1046 u8 ppdu_cnt; 1047 u8 ppdu_type; 1048 bool icv_err; 1049 bool crc32_err; 1050 bool hw_dec; 1051 bool sw_dec; 1052 bool addr1_match; 1053 u8 frag; 1054 u16 seq; 1055 u8 frame_type; 1056 u8 rx_pl_id; 1057 bool addr_cam_valid; 1058 u8 addr_cam_id; 1059 u8 sec_cam_id; 1060 u8 mac_id; 1061 u16 offset; 1062 u16 rxd_len; 1063 bool ready; 1064 }; 1065 1066 struct rtw89_rxdesc_short { 1067 __le32 dword0; 1068 __le32 dword1; 1069 __le32 dword2; 1070 __le32 dword3; 1071 } __packed; 1072 1073 struct rtw89_rxdesc_short_v2 { 1074 __le32 dword0; 1075 __le32 dword1; 1076 __le32 dword2; 1077 __le32 dword3; 1078 __le32 dword4; 1079 __le32 dword5; 1080 } __packed; 1081 1082 struct rtw89_rxdesc_long { 1083 __le32 dword0; 1084 __le32 dword1; 1085 __le32 dword2; 1086 __le32 dword3; 1087 __le32 dword4; 1088 __le32 dword5; 1089 __le32 dword6; 1090 __le32 dword7; 1091 } __packed; 1092 1093 struct rtw89_rxdesc_long_v2 { 1094 __le32 dword0; 1095 __le32 dword1; 1096 __le32 dword2; 1097 __le32 dword3; 1098 __le32 dword4; 1099 __le32 dword5; 1100 __le32 dword6; 1101 __le32 dword7; 1102 __le32 dword8; 1103 __le32 dword9; 1104 } __packed; 1105 1106 struct rtw89_tx_desc_info { 1107 u16 pkt_size; 1108 u8 wp_offset; 1109 u8 mac_id; 1110 u8 qsel; 1111 u8 ch_dma; 1112 u8 hdr_llc_len; 1113 bool is_bmc; 1114 bool en_wd_info; 1115 bool wd_page; 1116 bool use_rate; 1117 bool dis_data_fb; 1118 bool tid_indicate; 1119 bool agg_en; 1120 bool bk; 1121 u8 ampdu_density; 1122 u8 ampdu_num; 1123 bool sec_en; 1124 u8 addr_info_nr; 1125 u8 sec_keyid; 1126 u8 sec_type; 1127 u8 sec_cam_idx; 1128 u8 sec_seq[6]; 1129 u16 data_rate; 1130 u16 data_retry_lowest_rate; 1131 bool fw_dl; 1132 u16 seq; 1133 bool a_ctrl_bsr; 1134 u8 hw_ssn_sel; 1135 #define RTW89_MGMT_HW_SSN_SEL 1 1136 u8 hw_seq_mode; 1137 #define RTW89_MGMT_HW_SEQ_MODE 1 1138 bool hiq; 1139 u8 port; 1140 bool er_cap; 1141 bool stbc; 1142 bool ldpc; 1143 }; 1144 1145 struct rtw89_core_tx_request { 1146 enum rtw89_core_tx_type tx_type; 1147 1148 struct sk_buff *skb; 1149 struct ieee80211_vif *vif; 1150 struct ieee80211_sta *sta; 1151 struct rtw89_tx_desc_info desc_info; 1152 }; 1153 1154 struct rtw89_txq { 1155 struct list_head list; 1156 unsigned long flags; 1157 int wait_cnt; 1158 }; 1159 1160 struct rtw89_mac_ax_gnt { 1161 u8 gnt_bt_sw_en; 1162 u8 gnt_bt; 1163 u8 gnt_wl_sw_en; 1164 u8 gnt_wl; 1165 } __packed; 1166 1167 struct rtw89_mac_ax_wl_act { 1168 u8 wlan_act_en; 1169 u8 wlan_act; 1170 }; 1171 1172 #define RTW89_MAC_AX_COEX_GNT_NR 2 1173 struct rtw89_mac_ax_coex_gnt { 1174 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1175 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1176 }; 1177 1178 enum rtw89_btc_ncnt { 1179 BTC_NCNT_POWER_ON = 0x0, 1180 BTC_NCNT_POWER_OFF, 1181 BTC_NCNT_INIT_COEX, 1182 BTC_NCNT_SCAN_START, 1183 BTC_NCNT_SCAN_FINISH, 1184 BTC_NCNT_SPECIAL_PACKET, 1185 BTC_NCNT_SWITCH_BAND, 1186 BTC_NCNT_RFK_TIMEOUT, 1187 BTC_NCNT_SHOW_COEX_INFO, 1188 BTC_NCNT_ROLE_INFO, 1189 BTC_NCNT_CONTROL, 1190 BTC_NCNT_RADIO_STATE, 1191 BTC_NCNT_CUSTOMERIZE, 1192 BTC_NCNT_WL_RFK, 1193 BTC_NCNT_WL_STA, 1194 BTC_NCNT_WL_STA_LAST, 1195 BTC_NCNT_FWINFO, 1196 BTC_NCNT_TIMER, 1197 BTC_NCNT_SWITCH_CHBW, 1198 BTC_NCNT_RESUME_DL_FW, 1199 BTC_NCNT_COUNTRYCODE, 1200 BTC_NCNT_NUM, 1201 }; 1202 1203 enum rtw89_btc_btinfo { 1204 BTC_BTINFO_L0 = 0, 1205 BTC_BTINFO_L1, 1206 BTC_BTINFO_L2, 1207 BTC_BTINFO_L3, 1208 BTC_BTINFO_H0, 1209 BTC_BTINFO_H1, 1210 BTC_BTINFO_H2, 1211 BTC_BTINFO_H3, 1212 BTC_BTINFO_MAX 1213 }; 1214 1215 enum rtw89_btc_dcnt { 1216 BTC_DCNT_RUN = 0x0, 1217 BTC_DCNT_CX_RUNINFO, 1218 BTC_DCNT_RPT, 1219 BTC_DCNT_RPT_HANG, 1220 BTC_DCNT_CYCLE, 1221 BTC_DCNT_CYCLE_HANG, 1222 BTC_DCNT_W1, 1223 BTC_DCNT_W1_HANG, 1224 BTC_DCNT_B1, 1225 BTC_DCNT_B1_HANG, 1226 BTC_DCNT_TDMA_NONSYNC, 1227 BTC_DCNT_SLOT_NONSYNC, 1228 BTC_DCNT_BTCNT_HANG, 1229 BTC_DCNT_BTTX_HANG, 1230 BTC_DCNT_WL_SLOT_DRIFT, 1231 BTC_DCNT_WL_STA_LAST, 1232 BTC_DCNT_BT_SLOT_DRIFT, 1233 BTC_DCNT_BT_SLOT_FLOOD, 1234 BTC_DCNT_FDDT_TRIG, 1235 BTC_DCNT_E2G, 1236 BTC_DCNT_E2G_HANG, 1237 BTC_DCNT_WL_FW_VER_MATCH, 1238 BTC_DCNT_NULL_TX_FAIL, 1239 BTC_DCNT_WL_STA_NTFY, 1240 BTC_DCNT_NUM, 1241 }; 1242 1243 enum rtw89_btc_wl_state_cnt { 1244 BTC_WCNT_SCANAP = 0x0, 1245 BTC_WCNT_DHCP, 1246 BTC_WCNT_EAPOL, 1247 BTC_WCNT_ARP, 1248 BTC_WCNT_SCBDUPDATE, 1249 BTC_WCNT_RFK_REQ, 1250 BTC_WCNT_RFK_GO, 1251 BTC_WCNT_RFK_REJECT, 1252 BTC_WCNT_RFK_TIMEOUT, 1253 BTC_WCNT_CH_UPDATE, 1254 BTC_WCNT_DBCC_ALL_2G, 1255 BTC_WCNT_DBCC_CHG, 1256 BTC_WCNT_RX_OK_LAST, 1257 BTC_WCNT_RX_OK_LAST2S, 1258 BTC_WCNT_RX_ERR_LAST, 1259 BTC_WCNT_RX_ERR_LAST2S, 1260 BTC_WCNT_RX_LAST, 1261 BTC_WCNT_NUM 1262 }; 1263 1264 enum rtw89_btc_bt_state_cnt { 1265 BTC_BCNT_RETRY = 0x0, 1266 BTC_BCNT_REINIT, 1267 BTC_BCNT_REENABLE, 1268 BTC_BCNT_SCBDREAD, 1269 BTC_BCNT_RELINK, 1270 BTC_BCNT_IGNOWL, 1271 BTC_BCNT_INQPAG, 1272 BTC_BCNT_INQ, 1273 BTC_BCNT_PAGE, 1274 BTC_BCNT_ROLESW, 1275 BTC_BCNT_AFH, 1276 BTC_BCNT_INFOUPDATE, 1277 BTC_BCNT_INFOSAME, 1278 BTC_BCNT_SCBDUPDATE, 1279 BTC_BCNT_HIPRI_TX, 1280 BTC_BCNT_HIPRI_RX, 1281 BTC_BCNT_LOPRI_TX, 1282 BTC_BCNT_LOPRI_RX, 1283 BTC_BCNT_POLUT, 1284 BTC_BCNT_POLUT_NOW, 1285 BTC_BCNT_POLUT_DIFF, 1286 BTC_BCNT_RATECHG, 1287 BTC_BCNT_NUM, 1288 }; 1289 1290 enum rtw89_btc_bt_profile { 1291 BTC_BT_NOPROFILE = 0, 1292 BTC_BT_HFP = BIT(0), 1293 BTC_BT_HID = BIT(1), 1294 BTC_BT_A2DP = BIT(2), 1295 BTC_BT_PAN = BIT(3), 1296 BTC_PROFILE_MAX = 4, 1297 }; 1298 1299 struct rtw89_btc_ant_info { 1300 u8 type; /* shared, dedicated */ 1301 u8 num; 1302 u8 isolation; 1303 1304 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1305 u8 diversity: 1; 1306 u8 btg_pos: 2; 1307 u8 stream_cnt: 4; 1308 }; 1309 1310 struct rtw89_btc_ant_info_v7 { 1311 u8 type; /* shared, dedicated(non-shared) */ 1312 u8 num; /* antenna count */ 1313 u8 isolation; 1314 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1315 1316 u8 diversity; /* only for wifi use 1-antenna */ 1317 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1318 u8 stream_cnt; /* spatial_stream count */ 1319 u8 rsvd; 1320 } __packed; 1321 1322 enum rtw89_tfc_dir { 1323 RTW89_TFC_UL, 1324 RTW89_TFC_DL, 1325 }; 1326 1327 struct rtw89_btc_wl_smap { 1328 u32 busy: 1; 1329 u32 scan: 1; 1330 u32 connecting: 1; 1331 u32 roaming: 1; 1332 u32 transacting: 1; 1333 u32 _4way: 1; 1334 u32 rf_off: 1; 1335 u32 lps: 2; 1336 u32 ips: 1; 1337 u32 init_ok: 1; 1338 u32 traffic_dir : 2; 1339 u32 rf_off_pre: 1; 1340 u32 lps_pre: 2; 1341 u32 lps_exiting: 1; 1342 u32 emlsr: 1; 1343 }; 1344 1345 enum rtw89_tfc_lv { 1346 RTW89_TFC_IDLE, 1347 RTW89_TFC_ULTRA_LOW, 1348 RTW89_TFC_LOW, 1349 RTW89_TFC_MID, 1350 RTW89_TFC_HIGH, 1351 }; 1352 1353 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1354 DECLARE_EWMA(tp, 10, 2); 1355 1356 struct rtw89_traffic_stats { 1357 /* units in bytes */ 1358 u64 tx_unicast; 1359 u64 rx_unicast; 1360 u32 tx_avg_len; 1361 u32 rx_avg_len; 1362 1363 /* count for packets */ 1364 u64 tx_cnt; 1365 u64 rx_cnt; 1366 1367 /* units in Mbps */ 1368 u32 tx_throughput; 1369 u32 rx_throughput; 1370 u32 tx_throughput_raw; 1371 u32 rx_throughput_raw; 1372 1373 u32 rx_tf_acc; 1374 u32 rx_tf_periodic; 1375 1376 enum rtw89_tfc_lv tx_tfc_lv; 1377 enum rtw89_tfc_lv rx_tfc_lv; 1378 struct ewma_tp tx_ewma_tp; 1379 struct ewma_tp rx_ewma_tp; 1380 1381 u16 tx_rate; 1382 u16 rx_rate; 1383 }; 1384 1385 struct rtw89_btc_chdef { 1386 u8 center_ch; 1387 u8 band; 1388 u8 chan; 1389 enum rtw89_sc_offset offset; 1390 enum rtw89_bandwidth bw; 1391 }; 1392 1393 struct rtw89_btc_statistic { 1394 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1395 struct rtw89_traffic_stats traffic; 1396 }; 1397 1398 #define BTC_WL_RSSI_THMAX 4 1399 1400 struct rtw89_btc_wl_link_info { 1401 struct rtw89_btc_chdef chdef; 1402 struct rtw89_btc_statistic stat; 1403 enum rtw89_tfc_dir dir; 1404 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1405 u8 mac_addr[ETH_ALEN]; 1406 u8 busy; 1407 u8 ch; 1408 u8 bw; 1409 u8 band; 1410 u8 role; 1411 u8 pid; 1412 u8 phy; 1413 u8 dtim_period; 1414 u8 mode; 1415 u8 tx_1ss_limit; 1416 1417 u8 mac_id; 1418 u8 tx_retry; 1419 1420 u32 bcn_period; 1421 u32 busy_t; 1422 u32 tx_time; 1423 u32 client_cnt; 1424 u32 rx_rate_drop_cnt; 1425 u32 noa_duration; 1426 1427 u32 active: 1; 1428 u32 noa: 1; 1429 u32 client_ps: 1; 1430 u32 connected: 2; 1431 }; 1432 1433 union rtw89_btc_wl_state_map { 1434 u32 val; 1435 struct rtw89_btc_wl_smap map; 1436 }; 1437 1438 struct rtw89_btc_bt_hfp_desc { 1439 u32 exist: 1; 1440 u32 type: 2; 1441 u32 rsvd: 29; 1442 }; 1443 1444 struct rtw89_btc_bt_hid_desc { 1445 u32 exist: 1; 1446 u32 slot_info: 2; 1447 u32 pair_cnt: 2; 1448 u32 type: 8; 1449 u32 rsvd: 19; 1450 }; 1451 1452 struct rtw89_btc_bt_a2dp_desc { 1453 u8 exist: 1; 1454 u8 exist_last: 1; 1455 u8 play_latency: 1; 1456 u8 type: 3; 1457 u8 active: 1; 1458 u8 sink: 1; 1459 u32 handle_update: 1; 1460 u32 devinfo_query: 1; 1461 u32 no_empty_streak_2s: 8; 1462 u32 no_empty_streak_max: 8; 1463 u32 rsvd: 6; 1464 1465 u8 bitpool; 1466 u16 vendor_id; 1467 u32 device_name; 1468 u32 flush_time; 1469 }; 1470 1471 struct rtw89_btc_bt_pan_desc { 1472 u32 exist: 1; 1473 u32 type: 1; 1474 u32 active: 1; 1475 u32 rsvd: 29; 1476 }; 1477 1478 struct rtw89_btc_bt_rfk_info { 1479 u32 run: 1; 1480 u32 req: 1; 1481 u32 timeout: 1; 1482 u32 rsvd: 29; 1483 }; 1484 1485 union rtw89_btc_bt_rfk_info_map { 1486 u32 val; 1487 struct rtw89_btc_bt_rfk_info map; 1488 }; 1489 1490 struct rtw89_btc_bt_ver_info { 1491 u32 fw_coex; /* match with which coex_ver */ 1492 u32 fw; 1493 }; 1494 1495 struct rtw89_btc_bool_sta_chg { 1496 u32 now: 1; 1497 u32 last: 1; 1498 u32 remain: 1; 1499 u32 srvd: 29; 1500 }; 1501 1502 struct rtw89_btc_u8_sta_chg { 1503 u8 now; 1504 u8 last; 1505 u8 remain; 1506 u8 rsvd; 1507 }; 1508 1509 struct rtw89_btc_wl_scan_info { 1510 u8 band[RTW89_PHY_MAX]; 1511 u8 phy_map; 1512 u8 rsvd; 1513 }; 1514 1515 struct rtw89_btc_wl_dbcc_info { 1516 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1517 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1518 u8 real_band[RTW89_PHY_MAX]; 1519 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1520 }; 1521 1522 struct rtw89_btc_wl_active_role { 1523 u8 connected: 1; 1524 u8 pid: 3; 1525 u8 phy: 1; 1526 u8 noa: 1; 1527 u8 band: 2; 1528 1529 u8 client_ps: 1; 1530 u8 bw: 7; 1531 1532 u8 role; 1533 u8 ch; 1534 1535 u16 tx_lvl; 1536 u16 rx_lvl; 1537 u16 tx_rate; 1538 u16 rx_rate; 1539 }; 1540 1541 struct rtw89_btc_wl_active_role_v1 { 1542 u8 connected: 1; 1543 u8 pid: 3; 1544 u8 phy: 1; 1545 u8 noa: 1; 1546 u8 band: 2; 1547 1548 u8 client_ps: 1; 1549 u8 bw: 7; 1550 1551 u8 role; 1552 u8 ch; 1553 1554 u16 tx_lvl; 1555 u16 rx_lvl; 1556 u16 tx_rate; 1557 u16 rx_rate; 1558 1559 u32 noa_duration; /* ms */ 1560 }; 1561 1562 struct rtw89_btc_wl_active_role_v2 { 1563 u8 connected: 1; 1564 u8 pid: 3; 1565 u8 phy: 1; 1566 u8 noa: 1; 1567 u8 band: 2; 1568 1569 u8 client_ps: 1; 1570 u8 bw: 7; 1571 1572 u8 role; 1573 u8 ch; 1574 1575 u32 noa_duration; /* ms */ 1576 }; 1577 1578 struct rtw89_btc_wl_role_info_bpos { 1579 u16 none: 1; 1580 u16 station: 1; 1581 u16 ap: 1; 1582 u16 vap: 1; 1583 u16 adhoc: 1; 1584 u16 adhoc_master: 1; 1585 u16 mesh: 1; 1586 u16 moniter: 1; 1587 u16 p2p_device: 1; 1588 u16 p2p_gc: 1; 1589 u16 p2p_go: 1; 1590 u16 nan: 1; 1591 }; 1592 1593 struct rtw89_btc_wl_scc_ctrl { 1594 u8 null_role1; 1595 u8 null_role2; 1596 u8 ebt_null; /* if tx null at EBT slot */ 1597 }; 1598 1599 union rtw89_btc_wl_role_info_map { 1600 u16 val; 1601 struct rtw89_btc_wl_role_info_bpos role; 1602 }; 1603 1604 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1605 u8 connect_cnt; 1606 u8 link_mode; 1607 union rtw89_btc_wl_role_info_map role_map; 1608 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1609 }; 1610 1611 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1612 u8 connect_cnt; 1613 u8 link_mode; 1614 union rtw89_btc_wl_role_info_map role_map; 1615 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1616 u32 mrole_type; /* btc_wl_mrole_type */ 1617 u32 mrole_noa_duration; /* ms */ 1618 1619 u32 dbcc_en: 1; 1620 u32 dbcc_chg: 1; 1621 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1622 u32 link_mode_chg: 1; 1623 u32 rsvd: 27; 1624 }; 1625 1626 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1627 u8 connect_cnt; 1628 u8 link_mode; 1629 union rtw89_btc_wl_role_info_map role_map; 1630 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1631 u32 mrole_type; /* btc_wl_mrole_type */ 1632 u32 mrole_noa_duration; /* ms */ 1633 1634 u32 dbcc_en: 1; 1635 u32 dbcc_chg: 1; 1636 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1637 u32 link_mode_chg: 1; 1638 u32 rsvd: 27; 1639 }; 1640 1641 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1642 u8 connected; 1643 u8 pid; 1644 u8 phy; 1645 u8 noa; 1646 1647 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1648 u8 active; /* 0:rlink is under doze */ 1649 u8 bw; /* enum channel_width */ 1650 u8 role; /*enum role_type */ 1651 1652 u8 ch; 1653 u8 noa_dur; /* ms */ 1654 u8 client_cnt; /* for Role = P2P-Go/AP */ 1655 u8 mode; /* wifi protocol */ 1656 } __packed; 1657 1658 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1659 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1660 u8 connect_cnt; 1661 u8 link_mode; 1662 u8 link_mode_chg; 1663 u8 p2p_2g; 1664 1665 u8 pta_req_band; 1666 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1667 u8 dbcc_chg; 1668 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1669 1670 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1671 1672 u32 role_map; 1673 u32 mrole_type; /* btc_wl_mrole_type */ 1674 u32 mrole_noa_duration; /* ms */ 1675 } __packed; 1676 1677 struct rtw89_btc_wl_ver_info { 1678 u32 fw_coex; /* match with which coex_ver */ 1679 u32 fw; 1680 u32 mac; 1681 u32 bb; 1682 u32 rf; 1683 }; 1684 1685 struct rtw89_btc_wl_afh_info { 1686 u8 en; 1687 u8 ch; 1688 u8 bw; 1689 u8 rsvd; 1690 } __packed; 1691 1692 struct rtw89_btc_wl_rfk_info { 1693 u32 state: 2; 1694 u32 path_map: 4; 1695 u32 phy_map: 2; 1696 u32 band: 2; 1697 u32 type: 8; 1698 u32 rsvd: 14; 1699 1700 u32 start_time; 1701 u32 proc_time; 1702 }; 1703 1704 struct rtw89_btc_bt_smap { 1705 u32 connect: 1; 1706 u32 ble_connect: 1; 1707 u32 acl_busy: 1; 1708 u32 sco_busy: 1; 1709 u32 mesh_busy: 1; 1710 u32 inq_pag: 1; 1711 }; 1712 1713 union rtw89_btc_bt_state_map { 1714 u32 val; 1715 struct rtw89_btc_bt_smap map; 1716 }; 1717 1718 #define BTC_BT_RSSI_THMAX 4 1719 #define BTC_BT_AFH_GROUP 12 1720 #define BTC_BT_AFH_LE_GROUP 5 1721 1722 struct rtw89_btc_bt_link_info { 1723 struct rtw89_btc_u8_sta_chg profile_cnt; 1724 struct rtw89_btc_bool_sta_chg multi_link; 1725 struct rtw89_btc_bool_sta_chg relink; 1726 struct rtw89_btc_bt_hfp_desc hfp_desc; 1727 struct rtw89_btc_bt_hid_desc hid_desc; 1728 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1729 struct rtw89_btc_bt_pan_desc pan_desc; 1730 union rtw89_btc_bt_state_map status; 1731 1732 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1733 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1734 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1735 u8 afh_map[BTC_BT_AFH_GROUP]; 1736 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1737 1738 u32 role_sw: 1; 1739 u32 slave_role: 1; 1740 u32 afh_update: 1; 1741 u32 cqddr: 1; 1742 u32 rssi: 8; 1743 u32 tx_3m: 1; 1744 u32 rsvd: 19; 1745 }; 1746 1747 struct rtw89_btc_3rdcx_info { 1748 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1749 u8 hw_coex; 1750 u16 rsvd; 1751 }; 1752 1753 struct rtw89_btc_dm_emap { 1754 u32 init: 1; 1755 u32 pta_owner: 1; 1756 u32 wl_rfk_timeout: 1; 1757 u32 bt_rfk_timeout: 1; 1758 u32 wl_fw_hang: 1; 1759 u32 cycle_hang: 1; 1760 u32 w1_hang: 1; 1761 u32 b1_hang: 1; 1762 u32 tdma_no_sync: 1; 1763 u32 slot_no_sync: 1; 1764 u32 wl_slot_drift: 1; 1765 u32 bt_slot_drift: 1; 1766 u32 role_num_mismatch: 1; 1767 u32 null1_tx_late: 1; 1768 u32 bt_afh_conflict: 1; 1769 u32 bt_leafh_conflict: 1; 1770 u32 bt_slot_flood: 1; 1771 u32 wl_e2g_hang: 1; 1772 u32 wl_ver_mismatch: 1; 1773 u32 bt_ver_mismatch: 1; 1774 u32 rfe_type0: 1; 1775 u32 h2c_buffer_over: 1; 1776 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1777 u32 wl_no_sta_ntfy: 1; 1778 1779 u32 h2c_bmap_mismatch: 1; 1780 u32 c2h_bmap_mismatch: 1; 1781 u32 h2c_struct_invalid: 1; 1782 u32 c2h_struct_invalid: 1; 1783 u32 h2c_c2h_buffer_mismatch: 1; 1784 }; 1785 1786 union rtw89_btc_dm_error_map { 1787 u32 val; 1788 struct rtw89_btc_dm_emap map; 1789 }; 1790 1791 struct rtw89_btc_rf_para { 1792 u32 tx_pwr_freerun; 1793 u32 rx_gain_freerun; 1794 u32 tx_pwr_perpkt; 1795 u32 rx_gain_perpkt; 1796 }; 1797 1798 struct rtw89_btc_wl_nhm { 1799 u8 instant_wl_nhm_dbm; 1800 u8 instant_wl_nhm_per_mhz; 1801 u16 valid_record_times; 1802 s8 record_pwr[16]; 1803 u8 record_ratio[16]; 1804 s8 pwr; /* dbm_per_MHz */ 1805 u8 ratio; 1806 u8 current_status; 1807 u8 refresh; 1808 bool start_flag; 1809 s8 pwr_max; 1810 s8 pwr_min; 1811 }; 1812 1813 struct rtw89_btc_wl_info { 1814 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1815 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1816 struct rtw89_btc_wl_rfk_info rfk_info; 1817 struct rtw89_btc_wl_ver_info ver_info; 1818 struct rtw89_btc_wl_afh_info afh_info; 1819 struct rtw89_btc_wl_role_info role_info; 1820 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1821 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1822 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1823 struct rtw89_btc_wl_scan_info scan_info; 1824 struct rtw89_btc_wl_dbcc_info dbcc_info; 1825 struct rtw89_btc_rf_para rf_para; 1826 struct rtw89_btc_wl_nhm nhm; 1827 union rtw89_btc_wl_state_map status; 1828 1829 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1830 u8 rssi_level; 1831 u8 cn_report; 1832 u8 coex_mode; 1833 u8 pta_req_mac; 1834 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */ 1835 1836 bool is_5g_hi_channel; 1837 bool pta_reg_mac_chg; 1838 bool bg_mode; 1839 bool scbd_change; 1840 bool fw_ver_mismatch; 1841 u32 scbd; 1842 }; 1843 1844 struct rtw89_btc_module { 1845 struct rtw89_btc_ant_info ant; 1846 u8 rfe_type; 1847 u8 cv; 1848 1849 u8 bt_solo: 1; 1850 u8 bt_pos: 1; 1851 u8 switch_type: 1; 1852 u8 wa_type: 3; 1853 1854 u8 kt_ver_adie; 1855 }; 1856 1857 struct rtw89_btc_module_v7 { 1858 u8 rfe_type; 1859 u8 kt_ver; 1860 u8 bt_solo; 1861 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1862 1863 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1864 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1865 u8 kt_ver_adie; 1866 u8 rsvd; 1867 1868 struct rtw89_btc_ant_info_v7 ant; 1869 } __packed; 1870 1871 union rtw89_btc_module_info { 1872 struct rtw89_btc_module md; 1873 struct rtw89_btc_module_v7 md_v7; 1874 }; 1875 1876 #define RTW89_BTC_DM_MAXSTEP 30 1877 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1878 1879 struct rtw89_btc_dm_step { 1880 u16 step[RTW89_BTC_DM_MAXSTEP]; 1881 u8 step_pos; 1882 bool step_ov; 1883 }; 1884 1885 struct rtw89_btc_init_info { 1886 struct rtw89_btc_module module; 1887 u8 wl_guard_ch; 1888 1889 u8 wl_only: 1; 1890 u8 wl_init_ok: 1; 1891 u8 dbcc_en: 1; 1892 u8 cx_other: 1; 1893 u8 bt_only: 1; 1894 1895 u16 rsvd; 1896 }; 1897 1898 struct rtw89_btc_init_info_v7 { 1899 u8 wl_guard_ch; 1900 u8 wl_only; 1901 u8 wl_init_ok; 1902 u8 rsvd3; 1903 1904 u8 cx_other; 1905 u8 bt_only; 1906 u8 pta_mode; 1907 u8 pta_direction; 1908 1909 struct rtw89_btc_module_v7 module; 1910 } __packed; 1911 1912 union rtw89_btc_init_info_u { 1913 struct rtw89_btc_init_info init; 1914 struct rtw89_btc_init_info_v7 init_v7; 1915 }; 1916 1917 struct rtw89_btc_wl_tx_limit_para { 1918 u16 enable; 1919 u32 tx_time; /* unit: us */ 1920 u16 tx_retry; 1921 }; 1922 1923 enum rtw89_btc_bt_scan_type { 1924 BTC_SCAN_INQ = 0, 1925 BTC_SCAN_PAGE, 1926 BTC_SCAN_BLE, 1927 BTC_SCAN_INIT, 1928 BTC_SCAN_TV, 1929 BTC_SCAN_ADV, 1930 BTC_SCAN_MAX1, 1931 }; 1932 1933 enum rtw89_btc_ble_scan_type { 1934 CXSCAN_BG = 0, 1935 CXSCAN_INIT, 1936 CXSCAN_LE, 1937 CXSCAN_MAX 1938 }; 1939 1940 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1941 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1942 1943 struct rtw89_btc_bt_scan_info_v1 { 1944 __le16 win; 1945 __le16 intvl; 1946 __le32 flags; 1947 } __packed; 1948 1949 struct rtw89_btc_bt_scan_info_v2 { 1950 __le16 win; 1951 __le16 intvl; 1952 } __packed; 1953 1954 struct rtw89_btc_fbtc_btscan_v1 { 1955 u8 fver; /* btc_ver::fcxbtscan */ 1956 u8 rsvd; 1957 __le16 rsvd2; 1958 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1959 } __packed; 1960 1961 struct rtw89_btc_fbtc_btscan_v2 { 1962 u8 fver; /* btc_ver::fcxbtscan */ 1963 u8 type; 1964 __le16 rsvd2; 1965 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1966 } __packed; 1967 1968 struct rtw89_btc_fbtc_btscan_v7 { 1969 u8 fver; /* btc_ver::fcxbtscan */ 1970 u8 type; 1971 u8 rsvd0; 1972 u8 rsvd1; 1973 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1974 } __packed; 1975 1976 union rtw89_btc_fbtc_btscan { 1977 struct rtw89_btc_fbtc_btscan_v1 v1; 1978 struct rtw89_btc_fbtc_btscan_v2 v2; 1979 struct rtw89_btc_fbtc_btscan_v7 v7; 1980 }; 1981 1982 struct rtw89_btc_bt_info { 1983 struct rtw89_btc_bt_link_info link_info; 1984 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1985 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1986 struct rtw89_btc_bt_ver_info ver_info; 1987 struct rtw89_btc_bool_sta_chg enable; 1988 struct rtw89_btc_bool_sta_chg inq_pag; 1989 struct rtw89_btc_rf_para rf_para; 1990 union rtw89_btc_bt_rfk_info_map rfk_info; 1991 1992 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1993 u8 rssi_level; 1994 1995 u32 scbd; 1996 u32 feature; 1997 1998 u32 mbx_avl: 1; 1999 u32 whql_test: 1; 2000 u32 igno_wl: 1; 2001 u32 reinit: 1; 2002 u32 ble_scan_en: 1; 2003 u32 btg_type: 1; 2004 u32 inq: 1; 2005 u32 pag: 1; 2006 u32 run_patch_code: 1; 2007 u32 hi_lna_rx: 1; 2008 u32 scan_rx_low_pri: 1; 2009 u32 scan_info_update: 1; 2010 u32 lna_constrain: 3; 2011 u32 rsvd: 17; 2012 }; 2013 2014 struct rtw89_btc_cx { 2015 struct rtw89_btc_wl_info wl; 2016 struct rtw89_btc_bt_info bt; 2017 struct rtw89_btc_3rdcx_info other; 2018 u32 state_map; 2019 u32 cnt_bt[BTC_BCNT_NUM]; 2020 u32 cnt_wl[BTC_WCNT_NUM]; 2021 }; 2022 2023 struct rtw89_btc_fbtc_tdma { 2024 u8 type; /* btc_ver::fcxtdma */ 2025 u8 rxflctrl; 2026 u8 txpause; 2027 u8 wtgle_n; 2028 u8 leak_n; 2029 u8 ext_ctrl; 2030 u8 rxflctrl_role; 2031 u8 option_ctrl; 2032 } __packed; 2033 2034 struct rtw89_btc_fbtc_tdma_v3 { 2035 u8 fver; /* btc_ver::fcxtdma */ 2036 u8 rsvd; 2037 __le16 rsvd1; 2038 struct rtw89_btc_fbtc_tdma tdma; 2039 } __packed; 2040 2041 union rtw89_btc_fbtc_tdma_le32 { 2042 struct rtw89_btc_fbtc_tdma v1; 2043 struct rtw89_btc_fbtc_tdma_v3 v3; 2044 }; 2045 2046 #define CXMREG_MAX 30 2047 #define CXMREG_MAX_V2 20 2048 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2049 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2050 2051 enum rtw89_btc_bt_sta_counter { 2052 BTC_BCNT_RFK_REQ = 0, 2053 BTC_BCNT_RFK_GO = 1, 2054 BTC_BCNT_RFK_REJECT = 2, 2055 BTC_BCNT_RFK_FAIL = 3, 2056 BTC_BCNT_RFK_TIMEOUT = 4, 2057 BTC_BCNT_HI_TX = 5, 2058 BTC_BCNT_HI_RX = 6, 2059 BTC_BCNT_LO_TX = 7, 2060 BTC_BCNT_LO_RX = 8, 2061 BTC_BCNT_POLLUTED = 9, 2062 BTC_BCNT_STA_MAX 2063 }; 2064 2065 enum rtw89_btc_bt_sta_counter_v105 { 2066 BTC_BCNT_RFK_REQ_V105 = 0, 2067 BTC_BCNT_HI_TX_V105 = 1, 2068 BTC_BCNT_HI_RX_V105 = 2, 2069 BTC_BCNT_LO_TX_V105 = 3, 2070 BTC_BCNT_LO_RX_V105 = 4, 2071 BTC_BCNT_POLLUTED_V105 = 5, 2072 BTC_BCNT_STA_MAX_V105 2073 }; 2074 2075 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2076 u16 fver; /* btc_ver::fcxbtcrpt */ 2077 u16 rpt_cnt; /* tmr counters */ 2078 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2079 u32 wl_fw_cx_offload; 2080 u32 wl_fw_ver; 2081 u32 rpt_enable; 2082 u32 rpt_para; /* ms */ 2083 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2084 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2085 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2086 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2087 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2088 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2089 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2090 u32 c2h_cnt; /* fw send c2h counter */ 2091 u32 h2c_cnt; /* fw recv h2c counter */ 2092 } __packed; 2093 2094 struct rtw89_btc_fbtc_rpt_ctrl_info { 2095 __le32 cnt; /* fw report counter */ 2096 __le32 en; /* report map */ 2097 __le32 para; /* not used */ 2098 2099 __le32 cnt_c2h; /* fw send c2h counter */ 2100 __le32 cnt_h2c; /* fw recv h2c counter */ 2101 __le32 len_c2h; /* The total length of the last C2H */ 2102 2103 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2104 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2105 } __packed; 2106 2107 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2108 __le32 cx_ver; /* match which driver's coex version */ 2109 __le32 fw_ver; 2110 __le32 en; /* report map */ 2111 2112 __le16 cnt; /* fw report counter */ 2113 __le16 cnt_c2h; /* fw send c2h counter */ 2114 __le16 cnt_h2c; /* fw recv h2c counter */ 2115 __le16 len_c2h; /* The total length of the last C2H */ 2116 2117 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2118 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2119 } __packed; 2120 2121 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2122 __le16 cnt; /* fw report counter */ 2123 __le16 cnt_c2h; /* fw send c2h counter */ 2124 __le16 cnt_h2c; /* fw recv h2c counter */ 2125 __le16 len_c2h; /* The total length of the last C2H */ 2126 2127 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2128 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2129 2130 __le32 cx_ver; /* match which driver's coex version */ 2131 __le32 fw_ver; 2132 __le32 en; /* report map */ 2133 } __packed; 2134 2135 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2136 __le32 cx_ver; /* match which driver's coex version */ 2137 __le32 cx_offload; 2138 __le32 fw_ver; 2139 } __packed; 2140 2141 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2142 __le32 cnt_empty; /* a2dp empty count */ 2143 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2144 __le32 cnt_tx; 2145 __le32 cnt_ack; 2146 __le32 cnt_nack; 2147 } __packed; 2148 2149 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2150 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2151 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2152 __le32 cnt_recv; /* fw recv mailbox counter */ 2153 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2154 } __packed; 2155 2156 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2157 u8 fver; 2158 u8 rsvd; 2159 __le16 rsvd1; 2160 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2161 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2162 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2163 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2164 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2165 } __packed; 2166 2167 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2168 u8 fver; 2169 u8 rsvd; 2170 __le16 rsvd1; 2171 2172 u8 gnt_val[RTW89_PHY_MAX][4]; 2173 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2174 2175 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2176 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2177 } __packed; 2178 2179 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2180 u8 fver; 2181 u8 rsvd; 2182 __le16 rsvd1; 2183 2184 u8 gnt_val[RTW89_PHY_MAX][4]; 2185 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2186 2187 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2188 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2189 } __packed; 2190 2191 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2192 u8 fver; 2193 u8 rsvd0; 2194 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2195 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2196 2197 u8 gnt_val[RTW89_PHY_MAX][4]; 2198 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2199 2200 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2201 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2202 } __packed; 2203 2204 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2205 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2206 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2207 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2208 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2209 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2210 }; 2211 2212 enum rtw89_fbtc_ext_ctrl_type { 2213 CXECTL_OFF = 0x0, /* tdma off */ 2214 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2215 CXECTL_EXT = 0x2, 2216 CXECTL_MAX 2217 }; 2218 2219 union rtw89_btc_fbtc_rxflct { 2220 u8 val; 2221 u8 type: 3; 2222 u8 tgln_n: 5; 2223 }; 2224 2225 enum rtw89_btc_cxst_state { 2226 CXST_OFF = 0x0, 2227 CXST_B2W = 0x1, 2228 CXST_W1 = 0x2, 2229 CXST_W2 = 0x3, 2230 CXST_W2B = 0x4, 2231 CXST_B1 = 0x5, 2232 CXST_B2 = 0x6, 2233 CXST_B3 = 0x7, 2234 CXST_B4 = 0x8, 2235 CXST_LK = 0x9, 2236 CXST_BLK = 0xa, 2237 CXST_E2G = 0xb, 2238 CXST_E5G = 0xc, 2239 CXST_EBT = 0xd, 2240 CXST_ENULL = 0xe, 2241 CXST_WLK = 0xf, 2242 CXST_W1FDD = 0x10, 2243 CXST_B1FDD = 0x11, 2244 CXST_MAX = 0x12, 2245 }; 2246 2247 enum rtw89_btc_cxevnt { 2248 CXEVNT_TDMA_ENTRY = 0x0, 2249 CXEVNT_WL_TMR, 2250 CXEVNT_B1_TMR, 2251 CXEVNT_B2_TMR, 2252 CXEVNT_B3_TMR, 2253 CXEVNT_B4_TMR, 2254 CXEVNT_W2B_TMR, 2255 CXEVNT_B2W_TMR, 2256 CXEVNT_BCN_EARLY, 2257 CXEVNT_A2DP_EMPTY, 2258 CXEVNT_LK_END, 2259 CXEVNT_RX_ISR, 2260 CXEVNT_RX_FC0, 2261 CXEVNT_RX_FC1, 2262 CXEVNT_BT_RELINK, 2263 CXEVNT_BT_RETRY, 2264 CXEVNT_E2G, 2265 CXEVNT_E5G, 2266 CXEVNT_EBT, 2267 CXEVNT_ENULL, 2268 CXEVNT_DRV_WLK, 2269 CXEVNT_BCN_OK, 2270 CXEVNT_BT_CHANGE, 2271 CXEVNT_EBT_EXTEND, 2272 CXEVNT_E2G_NULL1, 2273 CXEVNT_B1FDD_TMR, 2274 CXEVNT_MAX 2275 }; 2276 2277 enum { 2278 CXBCN_ALL = 0x0, 2279 CXBCN_ALL_OK, 2280 CXBCN_BT_SLOT, 2281 CXBCN_BT_OK, 2282 CXBCN_MAX 2283 }; 2284 2285 enum btc_slot_type { 2286 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2287 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2288 CXSTYPE_NUM, 2289 }; 2290 2291 enum { /* TIME */ 2292 CXT_BT = 0x0, 2293 CXT_WL = 0x1, 2294 CXT_MAX 2295 }; 2296 2297 enum { /* TIME-A2DP */ 2298 CXT_FLCTRL_OFF = 0x0, 2299 CXT_FLCTRL_ON = 0x1, 2300 CXT_FLCTRL_MAX 2301 }; 2302 2303 enum { /* STEP TYPE */ 2304 CXSTEP_NONE = 0x0, 2305 CXSTEP_EVNT = 0x1, 2306 CXSTEP_SLOT = 0x2, 2307 CXSTEP_MAX, 2308 }; 2309 2310 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2311 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2312 RPT_BT_AFH_SEQ_LE = 0x20 2313 }; 2314 2315 #define BTC_DBG_MAX1 32 2316 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2317 u8 fver; /* btc_ver::fcxgpiodbg */ 2318 u8 rsvd; 2319 __le16 rsvd2; 2320 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2321 __le32 pre_state; /* the debug signal is 1 or 0 */ 2322 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2323 } __packed; 2324 2325 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2326 u8 fver; 2327 u8 rsvd0; 2328 u8 rsvd1; 2329 u8 rsvd2; 2330 2331 u8 gpio_map[BTC_DBG_MAX1]; 2332 2333 __le32 en_map; 2334 __le32 pre_state; 2335 } __packed; 2336 2337 union rtw89_btc_fbtc_gpio_dbg { 2338 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2339 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2340 }; 2341 2342 struct rtw89_btc_fbtc_mreg_val_v1 { 2343 u8 fver; /* btc_ver::fcxmreg */ 2344 u8 reg_num; 2345 __le16 rsvd; 2346 __le32 mreg_val[CXMREG_MAX]; 2347 } __packed; 2348 2349 struct rtw89_btc_fbtc_mreg_val_v2 { 2350 u8 fver; /* btc_ver::fcxmreg */ 2351 u8 reg_num; 2352 __le16 rsvd; 2353 __le32 mreg_val[CXMREG_MAX_V2]; 2354 } __packed; 2355 2356 struct rtw89_btc_fbtc_mreg_val_v7 { 2357 u8 fver; 2358 u8 reg_num; 2359 u8 rsvd0; 2360 u8 rsvd1; 2361 __le32 mreg_val[CXMREG_MAX_V2]; 2362 } __packed; 2363 2364 union rtw89_btc_fbtc_mreg_val { 2365 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2366 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2367 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2368 }; 2369 2370 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2371 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2372 .offset = cpu_to_le32(__offset), } 2373 2374 struct rtw89_btc_fbtc_mreg { 2375 __le16 type; 2376 __le16 bytes; 2377 __le32 offset; 2378 } __packed; 2379 2380 struct rtw89_btc_fbtc_slot { 2381 __le16 dur; 2382 __le32 cxtbl; 2383 __le16 cxtype; 2384 } __packed; 2385 2386 struct rtw89_btc_fbtc_slots { 2387 u8 fver; /* btc_ver::fcxslots */ 2388 u8 tbl_num; 2389 __le16 rsvd; 2390 __le32 update_map; 2391 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2392 } __packed; 2393 2394 struct rtw89_btc_fbtc_slot_v7 { 2395 __le16 dur; /* slot duration */ 2396 __le16 cxtype; 2397 __le32 cxtbl; 2398 } __packed; 2399 2400 struct rtw89_btc_fbtc_slot_u16 { 2401 __le16 dur; /* slot duration */ 2402 __le16 cxtype; 2403 __le16 cxtbl_l16; /* coex table [15:0] */ 2404 __le16 cxtbl_h16; /* coex table [31:16] */ 2405 } __packed; 2406 2407 struct rtw89_btc_fbtc_1slot_v7 { 2408 u8 fver; 2409 u8 sid; /* slot id */ 2410 __le16 rsvd; 2411 struct rtw89_btc_fbtc_slot_v7 slot; 2412 } __packed; 2413 2414 struct rtw89_btc_fbtc_slots_v7 { 2415 u8 fver; 2416 u8 slot_cnt; 2417 u8 rsvd0; 2418 u8 rsvd1; 2419 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2420 __le32 update_map; 2421 } __packed; 2422 2423 union rtw89_btc_fbtc_slots_info { 2424 struct rtw89_btc_fbtc_slots v1; 2425 struct rtw89_btc_fbtc_slots_v7 v7; 2426 } __packed; 2427 2428 struct rtw89_btc_fbtc_step { 2429 u8 type; 2430 u8 val; 2431 __le16 difft; 2432 } __packed; 2433 2434 struct rtw89_btc_fbtc_steps_v2 { 2435 u8 fver; /* btc_ver::fcxstep */ 2436 u8 rsvd; 2437 __le16 cnt; 2438 __le16 pos_old; 2439 __le16 pos_new; 2440 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2441 } __packed; 2442 2443 struct rtw89_btc_fbtc_steps_v3 { 2444 u8 fver; 2445 u8 en; 2446 __le16 rsvd; 2447 __le32 cnt; 2448 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2449 } __packed; 2450 2451 union rtw89_btc_fbtc_steps_info { 2452 struct rtw89_btc_fbtc_steps_v2 v2; 2453 struct rtw89_btc_fbtc_steps_v3 v3; 2454 }; 2455 2456 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2457 u8 fver; /* btc_ver::fcxcysta */ 2458 u8 rsvd; 2459 __le16 cycles; /* total cycle number */ 2460 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2461 __le16 a2dpept; /* a2dp empty cnt */ 2462 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2463 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2464 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2465 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2466 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2467 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2468 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2469 __le16 tmax_a2dpept; /* max a2dp empty time */ 2470 __le16 tavg_lk; /* avg leak-slot time */ 2471 __le16 tmax_lk; /* max leak-slot time */ 2472 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2473 __le32 bcn_cnt[CXBCN_MAX]; 2474 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2475 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2476 __le32 skip_cnt; 2477 __le32 exception; 2478 __le32 except_cnt; 2479 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2480 } __packed; 2481 2482 struct rtw89_btc_fbtc_fdd_try_info { 2483 __le16 cycles[CXT_FLCTRL_MAX]; 2484 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2485 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2486 } __packed; 2487 2488 struct rtw89_btc_fbtc_cycle_time_info { 2489 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2490 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2491 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2492 } __packed; 2493 2494 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2495 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2496 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2497 } __packed; 2498 2499 struct rtw89_btc_fbtc_a2dp_trx_stat { 2500 u8 empty_cnt; 2501 u8 retry_cnt; 2502 u8 tx_rate; 2503 u8 tx_cnt; 2504 u8 ack_cnt; 2505 u8 nack_cnt; 2506 u8 rsvd1; 2507 u8 rsvd2; 2508 } __packed; 2509 2510 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2511 u8 empty_cnt; 2512 u8 retry_cnt; 2513 u8 tx_rate; 2514 u8 tx_cnt; 2515 u8 ack_cnt; 2516 u8 nack_cnt; 2517 u8 no_empty_cnt; 2518 u8 rsvd; 2519 } __packed; 2520 2521 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2522 __le16 cnt; /* a2dp empty cnt */ 2523 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2524 __le16 tavg; /* avg a2dp empty time */ 2525 __le16 tmax; /* max a2dp empty time */ 2526 } __packed; 2527 2528 struct rtw89_btc_fbtc_cycle_leak_info { 2529 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2530 __le16 tavg; /* avg leak-slot time */ 2531 __le16 tmax; /* max leak-slot time */ 2532 } __packed; 2533 2534 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2535 __le16 tavg; 2536 __le16 tamx; 2537 __le32 cnt_rximr; 2538 } __packed; 2539 2540 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2541 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2542 2543 struct rtw89_btc_fbtc_cycle_fddt_info { 2544 __le16 train_cycle; 2545 __le16 tp; 2546 2547 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2548 s8 bt_tx_power; /* decrease Tx power (dB) */ 2549 s8 bt_rx_gain; /* LNA constrain level */ 2550 u8 no_empty_cnt; 2551 2552 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2553 u8 cn; /* condition_num */ 2554 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2555 u8 train_result; /* refer to enum btc_fddt_check_map */ 2556 } __packed; 2557 2558 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2559 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2560 2561 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2562 __le16 train_cycle; 2563 __le16 tp; 2564 2565 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2566 s8 bt_tx_power; /* decrease Tx power (dB) */ 2567 s8 bt_rx_gain; /* LNA constrain level */ 2568 u8 no_empty_cnt; 2569 2570 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2571 u8 cn; /* condition_num */ 2572 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2573 u8 train_result; /* refer to enum btc_fddt_check_map */ 2574 } __packed; 2575 2576 struct rtw89_btc_fbtc_fddt_cell_status { 2577 s8 wl_tx_pwr; 2578 s8 bt_tx_pwr; 2579 s8 bt_rx_gain; 2580 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2581 } __packed; 2582 2583 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2584 u8 fver; 2585 u8 rsvd; 2586 __le16 cycles; /* total cycle number */ 2587 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2588 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2589 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2590 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2591 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2592 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2593 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2594 __le32 bcn_cnt[CXBCN_MAX]; 2595 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2596 __le32 skip_cnt; 2597 __le32 except_cnt; 2598 __le32 except_map; 2599 } __packed; 2600 2601 #define FDD_TRAIN_WL_DIRECTION 2 2602 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2603 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2604 2605 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2606 u8 fver; 2607 u8 rsvd; 2608 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2609 u8 except_cnt; 2610 2611 __le16 skip_cnt; 2612 __le16 cycles; /* total cycle number */ 2613 2614 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2615 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2616 __le16 bcn_cnt[CXBCN_MAX]; 2617 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2618 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2619 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2620 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2621 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2622 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2623 [FDD_TRAIN_WL_RSSI_LEVEL] 2624 [FDD_TRAIN_BT_RSSI_LEVEL]; 2625 __le32 except_map; 2626 } __packed; 2627 2628 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2629 u8 fver; 2630 u8 rsvd; 2631 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2632 u8 except_cnt; 2633 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2634 2635 __le16 skip_cnt; 2636 __le16 cycles; /* total cycle number */ 2637 2638 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2639 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2640 __le16 bcn_cnt[CXBCN_MAX]; 2641 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2642 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2643 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2644 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2645 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2646 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2647 [FDD_TRAIN_WL_RSSI_LEVEL] 2648 [FDD_TRAIN_BT_RSSI_LEVEL]; 2649 __le32 except_map; 2650 } __packed; 2651 2652 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2653 u8 fver; 2654 u8 rsvd; 2655 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2656 u8 except_cnt; 2657 2658 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2659 2660 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2661 2662 __le16 skip_cnt; 2663 __le16 cycles; /* total cycle number */ 2664 2665 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2666 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2667 __le16 bcn_cnt[CXBCN_MAX]; 2668 2669 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2670 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2671 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2672 2673 __le32 except_map; 2674 } __packed; 2675 2676 union rtw89_btc_fbtc_cysta_info { 2677 struct rtw89_btc_fbtc_cysta_v2 v2; 2678 struct rtw89_btc_fbtc_cysta_v3 v3; 2679 struct rtw89_btc_fbtc_cysta_v4 v4; 2680 struct rtw89_btc_fbtc_cysta_v5 v5; 2681 struct rtw89_btc_fbtc_cysta_v7 v7; 2682 }; 2683 2684 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2685 u8 fver; /* btc_ver::fcxnullsta */ 2686 u8 rsvd; 2687 __le16 rsvd2; 2688 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2689 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2690 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2691 } __packed; 2692 2693 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2694 u8 fver; /* btc_ver::fcxnullsta */ 2695 u8 rsvd; 2696 __le16 rsvd2; 2697 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2698 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2699 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2700 } __packed; 2701 2702 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2703 u8 fver; 2704 u8 rsvd0; 2705 u8 rsvd1; 2706 u8 rsvd2; 2707 2708 __le32 tmax[2]; 2709 __le32 tavg[2]; 2710 __le32 result[2][5]; 2711 } __packed; 2712 2713 union rtw89_btc_fbtc_cynullsta_info { 2714 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2715 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2716 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2717 }; 2718 2719 struct rtw89_btc_fbtc_btver_v1 { 2720 u8 fver; /* btc_ver::fcxbtver */ 2721 u8 rsvd; 2722 __le16 rsvd2; 2723 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2724 __le32 fw_ver; 2725 __le32 feature; 2726 } __packed; 2727 2728 struct rtw89_btc_fbtc_btver_v7 { 2729 u8 fver; 2730 u8 rsvd0; 2731 u8 rsvd1; 2732 u8 rsvd2; 2733 2734 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2735 __le32 fw_ver; 2736 __le32 feature; 2737 } __packed; 2738 2739 union rtw89_btc_fbtc_btver { 2740 struct rtw89_btc_fbtc_btver_v1 v1; 2741 struct rtw89_btc_fbtc_btver_v7 v7; 2742 } __packed; 2743 2744 struct rtw89_btc_fbtc_btafh { 2745 u8 fver; /* btc_ver::fcxbtafh */ 2746 u8 rsvd; 2747 __le16 rsvd2; 2748 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2749 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2750 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2751 } __packed; 2752 2753 struct rtw89_btc_fbtc_btafh_v2 { 2754 u8 fver; /* btc_ver::fcxbtafh */ 2755 u8 rsvd; 2756 u8 rsvd2; 2757 u8 map_type; 2758 u8 afh_l[4]; 2759 u8 afh_m[4]; 2760 u8 afh_h[4]; 2761 u8 afh_le_a[4]; 2762 u8 afh_le_b[4]; 2763 } __packed; 2764 2765 struct rtw89_btc_fbtc_btafh_v7 { 2766 u8 fver; 2767 u8 map_type; 2768 u8 rsvd0; 2769 u8 rsvd1; 2770 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2771 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2772 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2773 u8 afh_le_a[4]; 2774 u8 afh_le_b[4]; 2775 } __packed; 2776 2777 struct rtw89_btc_fbtc_btdevinfo { 2778 u8 fver; /* btc_ver::fcxbtdevinfo */ 2779 u8 rsvd; 2780 __le16 vendor_id; 2781 __le32 dev_name; /* only 24 bits valid */ 2782 __le32 flush_time; 2783 } __packed; 2784 2785 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2786 struct rtw89_btc_rf_trx_para { 2787 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2788 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2789 u8 bt_tx_power; /* decrease Tx power (dB) */ 2790 u8 bt_rx_gain; /* LNA constrain level */ 2791 }; 2792 2793 struct rtw89_btc_trx_info { 2794 u8 tx_lvl; 2795 u8 rx_lvl; 2796 u8 wl_rssi; 2797 u8 bt_rssi; 2798 2799 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2800 s8 rx_gain; /* rx gain table index (TBD.) */ 2801 s8 bt_tx_power; /* decrease Tx power (dB) */ 2802 s8 bt_rx_gain; /* LNA constrain level */ 2803 2804 u8 cn; /* condition_num */ 2805 s8 nhm; 2806 u8 bt_profile; 2807 u8 rsvd2; 2808 2809 u16 tx_rate; 2810 u16 rx_rate; 2811 2812 u32 tx_tp; 2813 u32 rx_tp; 2814 u32 rx_err_ratio; 2815 }; 2816 2817 union rtw89_btc_fbtc_slot_u { 2818 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2819 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2820 }; 2821 2822 struct rtw89_btc_dm { 2823 union rtw89_btc_fbtc_slot_u slot; 2824 union rtw89_btc_fbtc_slot_u slot_now; 2825 struct rtw89_btc_fbtc_tdma tdma; 2826 struct rtw89_btc_fbtc_tdma tdma_now; 2827 struct rtw89_mac_ax_coex_gnt gnt; 2828 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2829 struct rtw89_btc_rf_trx_para rf_trx_para; 2830 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2831 struct rtw89_btc_dm_step dm_step; 2832 struct rtw89_btc_wl_scc_ctrl wl_scc; 2833 struct rtw89_btc_trx_info trx_info; 2834 union rtw89_btc_dm_error_map error; 2835 u32 cnt_dm[BTC_DCNT_NUM]; 2836 u32 cnt_notify[BTC_NCNT_NUM]; 2837 2838 u32 update_slot_map; 2839 u32 set_ant_path; 2840 u32 e2g_slot_limit; 2841 u32 e2g_slot_nulltx_time; 2842 2843 u32 wl_only: 1; 2844 u32 wl_fw_cx_offload: 1; 2845 u32 freerun: 1; 2846 u32 fddt_train: 1; 2847 u32 wl_ps_ctrl: 2; 2848 u32 wl_mimo_ps: 1; 2849 u32 leak_ap: 1; 2850 u32 noisy_level: 3; 2851 u32 coex_info_map: 8; 2852 u32 bt_only: 1; 2853 u32 wl_btg_rx: 2; 2854 u32 trx_para_level: 8; 2855 u32 wl_stb_chg: 1; 2856 u32 pta_owner: 1; 2857 2858 u32 tdma_instant_excute: 1; 2859 u32 wl_btg_rx_rb: 2; 2860 2861 u16 slot_dur[CXST_MAX]; 2862 u16 bt_slot_flood; 2863 2864 u8 run_reason; 2865 u8 run_action; 2866 2867 u8 wl_pre_agc: 2; 2868 u8 wl_lna2: 1; 2869 u8 wl_pre_agc_rb: 2; 2870 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2871 u8 slot_req_more: 1; 2872 }; 2873 2874 struct rtw89_btc_ctrl { 2875 u32 manual: 1; 2876 u32 igno_bt: 1; 2877 u32 always_freerun: 1; 2878 u32 trace_step: 16; 2879 u32 rsvd: 12; 2880 }; 2881 2882 struct rtw89_btc_ctrl_v7 { 2883 u8 manual; 2884 u8 igno_bt; 2885 u8 always_freerun; 2886 u8 rsvd; 2887 } __packed; 2888 2889 union rtw89_btc_ctrl_list { 2890 struct rtw89_btc_ctrl ctrl; 2891 struct rtw89_btc_ctrl_v7 ctrl_v7; 2892 }; 2893 2894 struct rtw89_btc_dbg { 2895 /* cmd "rb" */ 2896 bool rb_done; 2897 u32 rb_val; 2898 }; 2899 2900 enum rtw89_btc_btf_fw_event { 2901 BTF_EVNT_RPT = 0, 2902 BTF_EVNT_BT_INFO = 1, 2903 BTF_EVNT_BT_SCBD = 2, 2904 BTF_EVNT_BT_REG = 3, 2905 BTF_EVNT_CX_RUNINFO = 4, 2906 BTF_EVNT_BT_PSD = 5, 2907 BTF_EVNT_BUF_OVERFLOW, 2908 BTF_EVNT_C2H_LOOPBACK, 2909 BTF_EVNT_MAX, 2910 }; 2911 2912 enum btf_fw_event_report { 2913 BTC_RPT_TYPE_CTRL = 0x0, 2914 BTC_RPT_TYPE_TDMA, 2915 BTC_RPT_TYPE_SLOT, 2916 BTC_RPT_TYPE_CYSTA, 2917 BTC_RPT_TYPE_STEP, 2918 BTC_RPT_TYPE_NULLSTA, 2919 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 2920 BTC_RPT_TYPE_MREG, 2921 BTC_RPT_TYPE_GPIO_DBG, 2922 BTC_RPT_TYPE_BT_VER, 2923 BTC_RPT_TYPE_BT_SCAN, 2924 BTC_RPT_TYPE_BT_AFH, 2925 BTC_RPT_TYPE_BT_DEVICE, 2926 BTC_RPT_TYPE_TEST, 2927 BTC_RPT_TYPE_MAX = 31, 2928 2929 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 2930 __BTC_RPT_TYPE_V0_MAX = 12, 2931 }; 2932 2933 enum rtw_btc_btf_reg_type { 2934 REG_MAC = 0x0, 2935 REG_BB = 0x1, 2936 REG_RF = 0x2, 2937 REG_BT_RF = 0x3, 2938 REG_BT_MODEM = 0x4, 2939 REG_BT_BLUEWIZE = 0x5, 2940 REG_BT_VENDOR = 0x6, 2941 REG_BT_LE = 0x7, 2942 REG_MAX_TYPE, 2943 }; 2944 2945 struct rtw89_btc_rpt_cmn_info { 2946 u32 rx_cnt; 2947 u32 rx_len; 2948 u32 req_len; /* expected rsp len */ 2949 u8 req_fver; /* expected rsp fver */ 2950 u8 rsp_fver; /* fver from fw */ 2951 u8 valid; 2952 } __packed; 2953 2954 union rtw89_btc_fbtc_btafh_info { 2955 struct rtw89_btc_fbtc_btafh v1; 2956 struct rtw89_btc_fbtc_btafh_v2 v2; 2957 }; 2958 2959 struct rtw89_btc_report_ctrl_state { 2960 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2961 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2962 }; 2963 2964 struct rtw89_btc_rpt_fbtc_tdma { 2965 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2966 union rtw89_btc_fbtc_tdma_le32 finfo; 2967 }; 2968 2969 struct rtw89_btc_rpt_fbtc_slots { 2970 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2971 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 2972 }; 2973 2974 struct rtw89_btc_rpt_fbtc_cysta { 2975 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2976 union rtw89_btc_fbtc_cysta_info finfo; 2977 }; 2978 2979 struct rtw89_btc_rpt_fbtc_step { 2980 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2981 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2982 }; 2983 2984 struct rtw89_btc_rpt_fbtc_nullsta { 2985 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2986 union rtw89_btc_fbtc_cynullsta_info finfo; 2987 }; 2988 2989 struct rtw89_btc_rpt_fbtc_mreg { 2990 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2991 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2992 }; 2993 2994 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2995 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2996 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2997 }; 2998 2999 struct rtw89_btc_rpt_fbtc_btver { 3000 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3001 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3002 }; 3003 3004 struct rtw89_btc_rpt_fbtc_btscan { 3005 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3006 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3007 }; 3008 3009 struct rtw89_btc_rpt_fbtc_btafh { 3010 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3011 union rtw89_btc_fbtc_btafh_info finfo; 3012 }; 3013 3014 struct rtw89_btc_rpt_fbtc_btdev { 3015 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3016 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3017 }; 3018 3019 enum rtw89_btc_btfre_type { 3020 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3021 BTFRE_UNDEF_TYPE, 3022 BTFRE_EXCEPTION, 3023 BTFRE_MAX, 3024 }; 3025 3026 struct rtw89_btc_btf_fwinfo { 3027 u32 cnt_c2h; 3028 u32 cnt_h2c; 3029 u32 cnt_h2c_fail; 3030 u32 event[BTF_EVNT_MAX]; 3031 3032 u32 err[BTFRE_MAX]; 3033 u32 len_mismch; 3034 u32 fver_mismch; 3035 u32 rpt_en_map; 3036 3037 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3038 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3039 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3040 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3041 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3042 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3043 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3044 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3045 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3046 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3047 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3048 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3049 }; 3050 3051 struct rtw89_btc_ver { 3052 enum rtw89_core_chip_id chip_id; 3053 u32 fw_ver_code; 3054 3055 u8 fcxbtcrpt; 3056 u8 fcxtdma; 3057 u8 fcxslots; 3058 u8 fcxcysta; 3059 u8 fcxstep; 3060 u8 fcxnullsta; 3061 u8 fcxmreg; 3062 u8 fcxgpiodbg; 3063 u8 fcxbtver; 3064 u8 fcxbtscan; 3065 u8 fcxbtafh; 3066 u8 fcxbtdevinfo; 3067 u8 fwlrole; 3068 u8 frptmap; 3069 u8 fcxctrl; 3070 u8 fcxinit; 3071 3072 u8 fwevntrptl; 3073 u8 drvinfo_type; 3074 u16 info_buf; 3075 u8 max_role_num; 3076 }; 3077 3078 #define RTW89_BTC_POLICY_MAXLEN 512 3079 3080 struct rtw89_btc { 3081 const struct rtw89_btc_ver *ver; 3082 3083 struct rtw89_btc_cx cx; 3084 struct rtw89_btc_dm dm; 3085 union rtw89_btc_ctrl_list ctrl; 3086 union rtw89_btc_module_info mdinfo; 3087 struct rtw89_btc_btf_fwinfo fwinfo; 3088 struct rtw89_btc_dbg dbg; 3089 3090 struct work_struct eapol_notify_work; 3091 struct work_struct arp_notify_work; 3092 struct work_struct dhcp_notify_work; 3093 struct work_struct icmp_notify_work; 3094 3095 u32 bt_req_len; 3096 3097 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3098 u8 ant_type; 3099 u8 btg_pos; 3100 u16 policy_len; 3101 u16 policy_type; 3102 u32 hubmsg_cnt; 3103 bool bt_req_en; 3104 bool update_policy_force; 3105 bool lps; 3106 bool manual_ctrl; 3107 }; 3108 3109 enum rtw89_btc_hmsg { 3110 RTW89_BTC_HMSG_TMR_EN = 0x0, 3111 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3112 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3113 RTW89_BTC_HMSG_FW_EV = 0x3, 3114 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3115 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3116 3117 NUM_OF_RTW89_BTC_HMSG, 3118 }; 3119 3120 enum rtw89_ra_mode { 3121 RTW89_RA_MODE_CCK = BIT(0), 3122 RTW89_RA_MODE_OFDM = BIT(1), 3123 RTW89_RA_MODE_HT = BIT(2), 3124 RTW89_RA_MODE_VHT = BIT(3), 3125 RTW89_RA_MODE_HE = BIT(4), 3126 RTW89_RA_MODE_EHT = BIT(5), 3127 }; 3128 3129 enum rtw89_ra_report_mode { 3130 RTW89_RA_RPT_MODE_LEGACY, 3131 RTW89_RA_RPT_MODE_HT, 3132 RTW89_RA_RPT_MODE_VHT, 3133 RTW89_RA_RPT_MODE_HE, 3134 RTW89_RA_RPT_MODE_EHT, 3135 }; 3136 3137 enum rtw89_dig_noisy_level { 3138 RTW89_DIG_NOISY_LEVEL0 = -1, 3139 RTW89_DIG_NOISY_LEVEL1 = 0, 3140 RTW89_DIG_NOISY_LEVEL2 = 1, 3141 RTW89_DIG_NOISY_LEVEL3 = 2, 3142 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3143 }; 3144 3145 enum rtw89_gi_ltf { 3146 RTW89_GILTF_LGI_4XHE32 = 0, 3147 RTW89_GILTF_SGI_4XHE08 = 1, 3148 RTW89_GILTF_2XHE16 = 2, 3149 RTW89_GILTF_2XHE08 = 3, 3150 RTW89_GILTF_1XHE16 = 4, 3151 RTW89_GILTF_1XHE08 = 5, 3152 RTW89_GILTF_MAX 3153 }; 3154 3155 enum rtw89_rx_frame_type { 3156 RTW89_RX_TYPE_MGNT = 0, 3157 RTW89_RX_TYPE_CTRL = 1, 3158 RTW89_RX_TYPE_DATA = 2, 3159 RTW89_RX_TYPE_RSVD = 3, 3160 }; 3161 3162 enum rtw89_efuse_block { 3163 RTW89_EFUSE_BLOCK_SYS = 0, 3164 RTW89_EFUSE_BLOCK_RF = 1, 3165 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3166 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3167 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3168 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3169 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3170 RTW89_EFUSE_BLOCK_ADIE = 7, 3171 3172 RTW89_EFUSE_BLOCK_NUM, 3173 RTW89_EFUSE_BLOCK_IGNORE, 3174 }; 3175 3176 struct rtw89_ra_info { 3177 u8 is_dis_ra:1; 3178 /* Bit0 : CCK 3179 * Bit1 : OFDM 3180 * Bit2 : HT 3181 * Bit3 : VHT 3182 * Bit4 : HE 3183 * Bit5 : EHT 3184 */ 3185 u8 mode_ctrl:6; 3186 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3187 u8 macid; 3188 u8 dcm_cap:1; 3189 u8 er_cap:1; 3190 u8 init_rate_lv:2; 3191 u8 upd_all:1; 3192 u8 en_sgi:1; 3193 u8 ldpc_cap:1; 3194 u8 stbc_cap:1; 3195 u8 ss_num:3; 3196 u8 giltf:3; 3197 u8 upd_bw_nss_mask:1; 3198 u8 upd_mask:1; 3199 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3200 /* BFee CSI */ 3201 u8 band_num; 3202 u8 ra_csi_rate_en:1; 3203 u8 fixed_csi_rate_en:1; 3204 u8 cr_tbl_sel:1; 3205 u8 fix_giltf_en:1; 3206 u8 fix_giltf:3; 3207 u8 rsvd2:1; 3208 u8 csi_mcs_ss_idx; 3209 u8 csi_mode:2; 3210 u8 csi_gi_ltf:3; 3211 u8 csi_bw:3; 3212 }; 3213 3214 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3215 #define RTW89_PPDU_MAC_INFO_SIZE 8 3216 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3217 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3218 3219 #define RTW89_MAX_RX_AGG_NUM 64 3220 #define RTW89_MAX_TX_AGG_NUM 128 3221 3222 struct rtw89_ampdu_params { 3223 u16 agg_num; 3224 bool amsdu; 3225 }; 3226 3227 struct rtw89_ra_report { 3228 struct rate_info txrate; 3229 u32 bit_rate; 3230 u16 hw_rate; 3231 bool might_fallback_legacy; 3232 }; 3233 3234 DECLARE_EWMA(rssi, 10, 16); 3235 DECLARE_EWMA(evm, 10, 16); 3236 DECLARE_EWMA(snr, 10, 16); 3237 3238 struct rtw89_ba_cam_entry { 3239 struct list_head list; 3240 u8 tid; 3241 }; 3242 3243 #define RTW89_MAX_ADDR_CAM_NUM 128 3244 #define RTW89_MAX_BSSID_CAM_NUM 20 3245 #define RTW89_MAX_SEC_CAM_NUM 128 3246 #define RTW89_MAX_BA_CAM_NUM 24 3247 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3248 3249 struct rtw89_addr_cam_entry { 3250 u8 addr_cam_idx; 3251 u8 offset; 3252 u8 len; 3253 u8 valid : 1; 3254 u8 addr_mask : 6; 3255 u8 wapi : 1; 3256 u8 mask_sel : 2; 3257 u8 bssid_cam_idx: 6; 3258 3259 u8 sec_ent_mode; 3260 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3261 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3262 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3263 }; 3264 3265 struct rtw89_bssid_cam_entry { 3266 u8 bssid[ETH_ALEN]; 3267 u8 phy_idx; 3268 u8 bssid_cam_idx; 3269 u8 offset; 3270 u8 len; 3271 u8 valid : 1; 3272 u8 num; 3273 }; 3274 3275 struct rtw89_sec_cam_entry { 3276 u8 sec_cam_idx; 3277 u8 offset; 3278 u8 len; 3279 u8 type : 4; 3280 u8 ext_key : 1; 3281 u8 spp_mode : 1; 3282 /* 256 bits */ 3283 u8 key[32]; 3284 }; 3285 3286 struct rtw89_sta { 3287 u8 mac_id; 3288 bool disassoc; 3289 bool er_cap; 3290 struct rtw89_dev *rtwdev; 3291 struct rtw89_vif *rtwvif; 3292 struct rtw89_ra_info ra; 3293 struct rtw89_ra_report ra_report; 3294 int max_agg_wait; 3295 u8 prev_rssi; 3296 struct ewma_rssi avg_rssi; 3297 struct ewma_rssi rssi[RF_PATH_MAX]; 3298 struct ewma_snr avg_snr; 3299 struct ewma_evm evm_min[RF_PATH_MAX]; 3300 struct ewma_evm evm_max[RF_PATH_MAX]; 3301 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 3302 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 3303 struct ieee80211_rx_status rx_status; 3304 u16 rx_hw_rate; 3305 __le32 htc_template; 3306 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3307 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3308 struct list_head ba_cam_list; 3309 struct sk_buff_head roc_queue; 3310 3311 bool use_cfg_mask; 3312 struct cfg80211_bitrate_mask mask; 3313 3314 bool cctl_tx_time; 3315 u32 ampdu_max_time:4; 3316 bool cctl_tx_retry_limit; 3317 u32 data_tx_cnt_lmt:6; 3318 }; 3319 3320 struct rtw89_efuse { 3321 bool valid; 3322 bool power_k_valid; 3323 u8 xtal_cap; 3324 u8 addr[ETH_ALEN]; 3325 u8 rfe_type; 3326 char country_code[2]; 3327 }; 3328 3329 struct rtw89_phy_rate_pattern { 3330 u64 ra_mask; 3331 u16 rate; 3332 u8 ra_mode; 3333 bool enable; 3334 }; 3335 3336 struct rtw89_tx_wait_info { 3337 struct rcu_head rcu_head; 3338 struct completion completion; 3339 bool tx_done; 3340 }; 3341 3342 struct rtw89_tx_skb_data { 3343 struct rtw89_tx_wait_info __rcu *wait; 3344 u8 hci_priv[]; 3345 }; 3346 3347 #define RTW89_ROC_IDLE_TIMEOUT 500 3348 #define RTW89_ROC_TX_TIMEOUT 30 3349 enum rtw89_roc_state { 3350 RTW89_ROC_IDLE, 3351 RTW89_ROC_NORMAL, 3352 RTW89_ROC_MGMT, 3353 }; 3354 3355 struct rtw89_roc { 3356 struct ieee80211_channel chan; 3357 struct delayed_work roc_work; 3358 enum ieee80211_roc_type type; 3359 enum rtw89_roc_state state; 3360 int duration; 3361 }; 3362 3363 #define RTW89_P2P_MAX_NOA_NUM 2 3364 3365 struct rtw89_p2p_ie_head { 3366 u8 eid; 3367 u8 ie_len; 3368 u8 oui[3]; 3369 u8 oui_type; 3370 } __packed; 3371 3372 struct rtw89_noa_attr_head { 3373 u8 attr_type; 3374 __le16 attr_len; 3375 u8 index; 3376 u8 oppps_ctwindow; 3377 } __packed; 3378 3379 struct rtw89_p2p_noa_ie { 3380 struct rtw89_p2p_ie_head p2p_head; 3381 struct rtw89_noa_attr_head noa_head; 3382 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3383 } __packed; 3384 3385 struct rtw89_p2p_noa_setter { 3386 struct rtw89_p2p_noa_ie ie; 3387 u8 noa_count; 3388 u8 noa_index; 3389 }; 3390 3391 struct rtw89_vif { 3392 struct list_head list; 3393 struct rtw89_dev *rtwdev; 3394 struct rtw89_roc roc; 3395 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3396 enum rtw89_sub_entity_idx sub_entity_idx; 3397 enum rtw89_reg_6ghz_power reg_6ghz_power; 3398 3399 u8 mac_id; 3400 u8 port; 3401 u8 mac_addr[ETH_ALEN]; 3402 u8 bssid[ETH_ALEN]; 3403 __be32 ip_addr; 3404 u8 phy_idx; 3405 u8 mac_idx; 3406 u8 net_type; 3407 u8 wifi_role; 3408 u8 self_role; 3409 u8 wmm; 3410 u8 bcn_hit_cond; 3411 u8 hit_rule; 3412 u8 last_noa_nr; 3413 u64 sync_bcn_tsf; 3414 bool offchan; 3415 bool trigger; 3416 bool lsig_txop; 3417 u8 tgt_ind; 3418 u8 frm_tgt_ind; 3419 bool wowlan_pattern; 3420 bool wowlan_uc; 3421 bool wowlan_magic; 3422 bool is_hesta; 3423 bool last_a_ctrl; 3424 bool dyn_tb_bedge_en; 3425 bool pre_pwr_diff_en; 3426 bool pwr_diff_en; 3427 u8 def_tri_idx; 3428 u32 tdls_peer; 3429 struct work_struct update_beacon_work; 3430 struct rtw89_addr_cam_entry addr_cam; 3431 struct rtw89_bssid_cam_entry bssid_cam; 3432 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3433 struct rtw89_traffic_stats stats; 3434 struct rtw89_phy_rate_pattern rate_pattern; 3435 struct cfg80211_scan_request *scan_req; 3436 struct ieee80211_scan_ies *scan_ies; 3437 struct list_head general_pkt_list; 3438 struct rtw89_p2p_noa_setter p2p_noa; 3439 }; 3440 3441 enum rtw89_lv1_rcvy_step { 3442 RTW89_LV1_RCVY_STEP_1, 3443 RTW89_LV1_RCVY_STEP_2, 3444 }; 3445 3446 struct rtw89_hci_ops { 3447 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3448 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3449 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3450 void (*reset)(struct rtw89_dev *rtwdev); 3451 int (*start)(struct rtw89_dev *rtwdev); 3452 void (*stop)(struct rtw89_dev *rtwdev); 3453 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3454 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3455 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3456 3457 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3458 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3459 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3460 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3461 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3462 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3463 3464 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3465 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3466 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3467 int (*deinit)(struct rtw89_dev *rtwdev); 3468 3469 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3470 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3471 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3472 int (*napi_poll)(struct napi_struct *napi, int budget); 3473 3474 /* Deal with locks inside recovery_start and recovery_complete callbacks 3475 * by hci instance, and handle things which need to consider under SER. 3476 * e.g. turn on/off interrupts except for the one for halt notification. 3477 */ 3478 void (*recovery_start)(struct rtw89_dev *rtwdev); 3479 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3480 3481 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3482 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3483 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3484 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3485 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3486 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3487 void (*disable_intr)(struct rtw89_dev *rtwdev); 3488 void (*enable_intr)(struct rtw89_dev *rtwdev); 3489 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3490 }; 3491 3492 struct rtw89_hci_info { 3493 const struct rtw89_hci_ops *ops; 3494 enum rtw89_hci_type type; 3495 u32 rpwm_addr; 3496 u32 cpwm_addr; 3497 bool paused; 3498 }; 3499 3500 struct rtw89_chip_ops { 3501 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3502 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3503 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3504 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3505 void (*bb_reset)(struct rtw89_dev *rtwdev, 3506 enum rtw89_phy_idx phy_idx); 3507 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3508 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3509 u32 addr, u32 mask); 3510 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3511 u32 addr, u32 mask, u32 data); 3512 void (*set_channel)(struct rtw89_dev *rtwdev, 3513 const struct rtw89_chan *chan, 3514 enum rtw89_mac_idx mac_idx, 3515 enum rtw89_phy_idx phy_idx); 3516 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3517 struct rtw89_channel_help_params *p, 3518 const struct rtw89_chan *chan, 3519 enum rtw89_mac_idx mac_idx, 3520 enum rtw89_phy_idx phy_idx); 3521 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3522 enum rtw89_efuse_block block); 3523 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3524 void (*fem_setup)(struct rtw89_dev *rtwdev); 3525 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3526 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3527 void (*rfk_init)(struct rtw89_dev *rtwdev); 3528 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3529 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3530 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3531 enum rtw89_phy_idx phy_idx); 3532 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3533 void (*rfk_track)(struct rtw89_dev *rtwdev); 3534 void (*power_trim)(struct rtw89_dev *rtwdev); 3535 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3536 const struct rtw89_chan *chan, 3537 enum rtw89_phy_idx phy_idx); 3538 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3539 enum rtw89_phy_idx phy_idx); 3540 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3541 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3542 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3543 enum rtw89_phy_idx phy_idx); 3544 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3545 struct rtw89_rx_phy_ppdu *phy_ppdu, 3546 struct ieee80211_rx_status *status); 3547 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3548 enum rtw89_phy_idx phy_idx); 3549 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3550 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3551 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3552 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3553 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3554 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3555 struct rtw89_rx_desc_info *desc_info, 3556 u8 *data, u32 data_offset); 3557 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3558 struct rtw89_tx_desc_info *desc_info, 3559 void *txdesc); 3560 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3561 struct rtw89_tx_desc_info *desc_info, 3562 void *txdesc); 3563 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3564 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3565 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3566 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3567 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3568 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3569 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3570 struct rtw89_vif *rtwvif, 3571 struct rtw89_sta *rtwsta); 3572 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3573 struct rtw89_vif *rtwvif, 3574 struct rtw89_sta *rtwsta); 3575 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3576 struct ieee80211_vif *vif, 3577 struct ieee80211_sta *sta); 3578 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3579 struct ieee80211_vif *vif, 3580 struct ieee80211_sta *sta); 3581 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3582 struct rtw89_vif *rtwvif, 3583 struct rtw89_sta *rtwsta); 3584 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3585 struct rtw89_vif *rtwvif); 3586 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3587 bool valid, struct ieee80211_ampdu_params *params); 3588 3589 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3590 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3591 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3592 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3593 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3594 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3595 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3596 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3597 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3598 }; 3599 3600 enum rtw89_dma_ch { 3601 RTW89_DMA_ACH0 = 0, 3602 RTW89_DMA_ACH1 = 1, 3603 RTW89_DMA_ACH2 = 2, 3604 RTW89_DMA_ACH3 = 3, 3605 RTW89_DMA_ACH4 = 4, 3606 RTW89_DMA_ACH5 = 5, 3607 RTW89_DMA_ACH6 = 6, 3608 RTW89_DMA_ACH7 = 7, 3609 RTW89_DMA_B0MG = 8, 3610 RTW89_DMA_B0HI = 9, 3611 RTW89_DMA_B1MG = 10, 3612 RTW89_DMA_B1HI = 11, 3613 RTW89_DMA_H2C = 12, 3614 RTW89_DMA_CH_NUM = 13 3615 }; 3616 3617 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3618 3619 enum rtw89_mlo_dbcc_mode { 3620 MLO_DBCC_NOT_SUPPORT = 1, 3621 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3622 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3623 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3624 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3625 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3626 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3627 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3628 DBCC_LEGACY = 0xffffffff, 3629 }; 3630 3631 enum rtw89_scan_be_operation { 3632 RTW89_SCAN_OP_STOP, 3633 RTW89_SCAN_OP_START, 3634 RTW89_SCAN_OP_SETPARM, 3635 RTW89_SCAN_OP_GETRPT, 3636 RTW89_SCAN_OP_NUM 3637 }; 3638 3639 enum rtw89_scan_be_mode { 3640 RTW89_SCAN_MODE_SA, 3641 RTW89_SCAN_MODE_MACC, 3642 RTW89_SCAN_MODE_NUM 3643 }; 3644 3645 enum rtw89_scan_be_opmode { 3646 RTW89_SCAN_OPMODE_NONE, 3647 RTW89_SCAN_OPMODE_TBTT, 3648 RTW89_SCAN_OPMODE_INTV, 3649 RTW89_SCAN_OPMODE_CNT, 3650 RTW89_SCAN_OPMODE_NUM, 3651 }; 3652 3653 struct rtw89_scan_option { 3654 bool enable; 3655 bool target_ch_mode; 3656 u8 num_macc_role; 3657 u8 num_opch; 3658 u8 repeat; 3659 u16 norm_pd; 3660 u16 slow_pd; 3661 u16 norm_cy; 3662 u8 opch_end; 3663 u64 prohib_chan; 3664 enum rtw89_phy_idx band; 3665 enum rtw89_scan_be_operation operation; 3666 enum rtw89_scan_be_mode scan_mode; 3667 enum rtw89_mlo_dbcc_mode mlo_mode; 3668 }; 3669 3670 enum rtw89_qta_mode { 3671 RTW89_QTA_SCC, 3672 RTW89_QTA_DBCC, 3673 RTW89_QTA_DLFW, 3674 RTW89_QTA_WOW, 3675 3676 /* keep last */ 3677 RTW89_QTA_INVALID, 3678 }; 3679 3680 struct rtw89_hfc_ch_cfg { 3681 u16 min; 3682 u16 max; 3683 #define grp_0 0 3684 #define grp_1 1 3685 #define grp_num 2 3686 u8 grp; 3687 }; 3688 3689 struct rtw89_hfc_ch_info { 3690 u16 aval; 3691 u16 used; 3692 }; 3693 3694 struct rtw89_hfc_pub_cfg { 3695 u16 grp0; 3696 u16 grp1; 3697 u16 pub_max; 3698 u16 wp_thrd; 3699 }; 3700 3701 struct rtw89_hfc_pub_info { 3702 u16 g0_used; 3703 u16 g1_used; 3704 u16 g0_aval; 3705 u16 g1_aval; 3706 u16 pub_aval; 3707 u16 wp_aval; 3708 }; 3709 3710 struct rtw89_hfc_prec_cfg { 3711 u16 ch011_prec; 3712 u16 h2c_prec; 3713 u16 wp_ch07_prec; 3714 u16 wp_ch811_prec; 3715 u8 ch011_full_cond; 3716 u8 h2c_full_cond; 3717 u8 wp_ch07_full_cond; 3718 u8 wp_ch811_full_cond; 3719 }; 3720 3721 struct rtw89_hfc_param { 3722 bool en; 3723 bool h2c_en; 3724 u8 mode; 3725 const struct rtw89_hfc_ch_cfg *ch_cfg; 3726 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3727 struct rtw89_hfc_pub_cfg pub_cfg; 3728 struct rtw89_hfc_pub_info pub_info; 3729 struct rtw89_hfc_prec_cfg prec_cfg; 3730 }; 3731 3732 struct rtw89_hfc_param_ini { 3733 const struct rtw89_hfc_ch_cfg *ch_cfg; 3734 const struct rtw89_hfc_pub_cfg *pub_cfg; 3735 const struct rtw89_hfc_prec_cfg *prec_cfg; 3736 u8 mode; 3737 }; 3738 3739 struct rtw89_dle_size { 3740 u16 pge_size; 3741 u16 lnk_pge_num; 3742 u16 unlnk_pge_num; 3743 /* for WiFi 7 chips below */ 3744 u32 srt_ofst; 3745 }; 3746 3747 struct rtw89_wde_quota { 3748 u16 hif; 3749 u16 wcpu; 3750 u16 pkt_in; 3751 u16 cpu_io; 3752 }; 3753 3754 struct rtw89_ple_quota { 3755 u16 cma0_tx; 3756 u16 cma1_tx; 3757 u16 c2h; 3758 u16 h2c; 3759 u16 wcpu; 3760 u16 mpdu_proc; 3761 u16 cma0_dma; 3762 u16 cma1_dma; 3763 u16 bb_rpt; 3764 u16 wd_rel; 3765 u16 cpu_io; 3766 u16 tx_rpt; 3767 /* for WiFi 7 chips below */ 3768 u16 h2d; 3769 }; 3770 3771 struct rtw89_rsvd_quota { 3772 u16 mpdu_info_tbl; 3773 u16 b0_csi; 3774 u16 b1_csi; 3775 u16 b0_lmr; 3776 u16 b1_lmr; 3777 u16 b0_ftm; 3778 u16 b1_ftm; 3779 u16 b0_smr; 3780 u16 b1_smr; 3781 u16 others; 3782 }; 3783 3784 struct rtw89_dle_rsvd_size { 3785 u32 srt_ofst; 3786 u32 size; 3787 }; 3788 3789 struct rtw89_dle_mem { 3790 enum rtw89_qta_mode mode; 3791 const struct rtw89_dle_size *wde_size; 3792 const struct rtw89_dle_size *ple_size; 3793 const struct rtw89_wde_quota *wde_min_qt; 3794 const struct rtw89_wde_quota *wde_max_qt; 3795 const struct rtw89_ple_quota *ple_min_qt; 3796 const struct rtw89_ple_quota *ple_max_qt; 3797 /* for WiFi 7 chips below */ 3798 const struct rtw89_rsvd_quota *rsvd_qt; 3799 const struct rtw89_dle_rsvd_size *rsvd0_size; 3800 const struct rtw89_dle_rsvd_size *rsvd1_size; 3801 }; 3802 3803 struct rtw89_reg_def { 3804 u32 addr; 3805 u32 mask; 3806 }; 3807 3808 struct rtw89_reg2_def { 3809 u32 addr; 3810 u32 data; 3811 }; 3812 3813 struct rtw89_reg3_def { 3814 u32 addr; 3815 u32 mask; 3816 u32 data; 3817 }; 3818 3819 struct rtw89_reg5_def { 3820 u8 flag; /* recognized by parsers */ 3821 u8 path; 3822 u32 addr; 3823 u32 mask; 3824 u32 data; 3825 }; 3826 3827 struct rtw89_reg_imr { 3828 u32 addr; 3829 u32 clr; 3830 u32 set; 3831 }; 3832 3833 struct rtw89_phy_table { 3834 const struct rtw89_reg2_def *regs; 3835 u32 n_regs; 3836 enum rtw89_rf_path rf_path; 3837 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3838 enum rtw89_rf_path rf_path, void *data); 3839 }; 3840 3841 struct rtw89_txpwr_table { 3842 const void *data; 3843 u32 size; 3844 void (*load)(struct rtw89_dev *rtwdev, 3845 const struct rtw89_txpwr_table *tbl); 3846 }; 3847 3848 struct rtw89_txpwr_rule_2ghz { 3849 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3850 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3851 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3852 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3853 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3854 }; 3855 3856 struct rtw89_txpwr_rule_5ghz { 3857 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3858 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3859 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3860 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3861 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3862 }; 3863 3864 struct rtw89_txpwr_rule_6ghz { 3865 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3866 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3867 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3868 [RTW89_6G_CH_NUM]; 3869 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3870 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3871 [RTW89_6G_CH_NUM]; 3872 }; 3873 3874 struct rtw89_tx_shape { 3875 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3876 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3877 }; 3878 3879 struct rtw89_rfe_parms { 3880 const struct rtw89_txpwr_table *byr_tbl; 3881 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3882 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3883 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3884 struct rtw89_tx_shape tx_shape; 3885 }; 3886 3887 struct rtw89_rfe_parms_conf { 3888 const struct rtw89_rfe_parms *rfe_parms; 3889 u8 rfe_type; 3890 }; 3891 3892 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3893 3894 struct rtw89_txpwr_conf { 3895 u8 rfe_type; 3896 u8 ent_sz; 3897 u32 num_ents; 3898 const void *data; 3899 }; 3900 3901 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3902 3903 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3904 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3905 memcpy(&(entry), cursor, \ 3906 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3907 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3908 (cursor) += (conf)->ent_sz, \ 3909 memcpy(&(entry), cursor, \ 3910 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3911 3912 struct rtw89_txpwr_byrate_data { 3913 struct rtw89_txpwr_conf conf; 3914 struct rtw89_txpwr_table tbl; 3915 }; 3916 3917 struct rtw89_txpwr_lmt_2ghz_data { 3918 struct rtw89_txpwr_conf conf; 3919 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3920 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3921 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3922 }; 3923 3924 struct rtw89_txpwr_lmt_5ghz_data { 3925 struct rtw89_txpwr_conf conf; 3926 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3927 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3928 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3929 }; 3930 3931 struct rtw89_txpwr_lmt_6ghz_data { 3932 struct rtw89_txpwr_conf conf; 3933 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3934 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3935 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3936 [RTW89_6G_CH_NUM]; 3937 }; 3938 3939 struct rtw89_txpwr_lmt_ru_2ghz_data { 3940 struct rtw89_txpwr_conf conf; 3941 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3942 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3943 }; 3944 3945 struct rtw89_txpwr_lmt_ru_5ghz_data { 3946 struct rtw89_txpwr_conf conf; 3947 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3948 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3949 }; 3950 3951 struct rtw89_txpwr_lmt_ru_6ghz_data { 3952 struct rtw89_txpwr_conf conf; 3953 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3954 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3955 [RTW89_6G_CH_NUM]; 3956 }; 3957 3958 struct rtw89_tx_shape_lmt_data { 3959 struct rtw89_txpwr_conf conf; 3960 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3961 }; 3962 3963 struct rtw89_tx_shape_lmt_ru_data { 3964 struct rtw89_txpwr_conf conf; 3965 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3966 }; 3967 3968 struct rtw89_rfe_data { 3969 struct rtw89_txpwr_byrate_data byrate; 3970 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3971 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3972 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3973 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3974 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3975 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3976 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3977 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3978 struct rtw89_rfe_parms rfe_parms; 3979 }; 3980 3981 struct rtw89_page_regs { 3982 u32 hci_fc_ctrl; 3983 u32 ch_page_ctrl; 3984 u32 ach_page_ctrl; 3985 u32 ach_page_info; 3986 u32 pub_page_info3; 3987 u32 pub_page_ctrl1; 3988 u32 pub_page_ctrl2; 3989 u32 pub_page_info1; 3990 u32 pub_page_info2; 3991 u32 wp_page_ctrl1; 3992 u32 wp_page_ctrl2; 3993 u32 wp_page_info1; 3994 }; 3995 3996 struct rtw89_imr_info { 3997 u32 wdrls_imr_set; 3998 u32 wsec_imr_reg; 3999 u32 wsec_imr_set; 4000 u32 mpdu_tx_imr_set; 4001 u32 mpdu_rx_imr_set; 4002 u32 sta_sch_imr_set; 4003 u32 txpktctl_imr_b0_reg; 4004 u32 txpktctl_imr_b0_clr; 4005 u32 txpktctl_imr_b0_set; 4006 u32 txpktctl_imr_b1_reg; 4007 u32 txpktctl_imr_b1_clr; 4008 u32 txpktctl_imr_b1_set; 4009 u32 wde_imr_clr; 4010 u32 wde_imr_set; 4011 u32 ple_imr_clr; 4012 u32 ple_imr_set; 4013 u32 host_disp_imr_clr; 4014 u32 host_disp_imr_set; 4015 u32 cpu_disp_imr_clr; 4016 u32 cpu_disp_imr_set; 4017 u32 other_disp_imr_clr; 4018 u32 other_disp_imr_set; 4019 u32 bbrpt_com_err_imr_reg; 4020 u32 bbrpt_chinfo_err_imr_reg; 4021 u32 bbrpt_err_imr_set; 4022 u32 bbrpt_dfs_err_imr_reg; 4023 u32 ptcl_imr_clr; 4024 u32 ptcl_imr_set; 4025 u32 cdma_imr_0_reg; 4026 u32 cdma_imr_0_clr; 4027 u32 cdma_imr_0_set; 4028 u32 cdma_imr_1_reg; 4029 u32 cdma_imr_1_clr; 4030 u32 cdma_imr_1_set; 4031 u32 phy_intf_imr_reg; 4032 u32 phy_intf_imr_clr; 4033 u32 phy_intf_imr_set; 4034 u32 rmac_imr_reg; 4035 u32 rmac_imr_clr; 4036 u32 rmac_imr_set; 4037 u32 tmac_imr_reg; 4038 u32 tmac_imr_clr; 4039 u32 tmac_imr_set; 4040 }; 4041 4042 struct rtw89_imr_table { 4043 const struct rtw89_reg_imr *regs; 4044 u32 n_regs; 4045 }; 4046 4047 struct rtw89_xtal_info { 4048 u32 xcap_reg; 4049 u32 sc_xo_mask; 4050 u32 sc_xi_mask; 4051 }; 4052 4053 struct rtw89_rrsr_cfgs { 4054 struct rtw89_reg3_def ref_rate; 4055 struct rtw89_reg3_def rsc; 4056 }; 4057 4058 struct rtw89_dig_regs { 4059 u32 seg0_pd_reg; 4060 u32 pd_lower_bound_mask; 4061 u32 pd_spatial_reuse_en; 4062 u32 bmode_pd_reg; 4063 u32 bmode_cca_rssi_limit_en; 4064 u32 bmode_pd_lower_bound_reg; 4065 u32 bmode_rssi_nocca_low_th_mask; 4066 struct rtw89_reg_def p0_lna_init; 4067 struct rtw89_reg_def p1_lna_init; 4068 struct rtw89_reg_def p0_tia_init; 4069 struct rtw89_reg_def p1_tia_init; 4070 struct rtw89_reg_def p0_rxb_init; 4071 struct rtw89_reg_def p1_rxb_init; 4072 struct rtw89_reg_def p0_p20_pagcugc_en; 4073 struct rtw89_reg_def p0_s20_pagcugc_en; 4074 struct rtw89_reg_def p1_p20_pagcugc_en; 4075 struct rtw89_reg_def p1_s20_pagcugc_en; 4076 }; 4077 4078 struct rtw89_edcca_regs { 4079 u32 edcca_level; 4080 u32 edcca_mask; 4081 u32 edcca_p_mask; 4082 u32 ppdu_level; 4083 u32 ppdu_mask; 4084 u32 rpt_a; 4085 u32 rpt_b; 4086 u32 rpt_sel; 4087 u32 rpt_sel_mask; 4088 u32 rpt_sel_be; 4089 u32 rpt_sel_be_mask; 4090 u32 tx_collision_t2r_st; 4091 u32 tx_collision_t2r_st_mask; 4092 }; 4093 4094 struct rtw89_phy_ul_tb_info { 4095 bool dyn_tb_tri_en; 4096 u8 def_if_bandedge; 4097 }; 4098 4099 struct rtw89_antdiv_stats { 4100 struct ewma_rssi cck_rssi_avg; 4101 struct ewma_rssi ofdm_rssi_avg; 4102 struct ewma_rssi non_legacy_rssi_avg; 4103 u16 pkt_cnt_cck; 4104 u16 pkt_cnt_ofdm; 4105 u16 pkt_cnt_non_legacy; 4106 u32 evm; 4107 }; 4108 4109 struct rtw89_antdiv_info { 4110 struct rtw89_antdiv_stats target_stats; 4111 struct rtw89_antdiv_stats main_stats; 4112 struct rtw89_antdiv_stats aux_stats; 4113 u8 training_count; 4114 u8 rssi_pre; 4115 bool get_stats; 4116 }; 4117 4118 enum rtw89_chanctx_state { 4119 RTW89_CHANCTX_STATE_MCC_START, 4120 RTW89_CHANCTX_STATE_MCC_STOP, 4121 }; 4122 4123 enum rtw89_chanctx_callbacks { 4124 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4125 RTW89_CHANCTX_CALLBACK_RFK, 4126 4127 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4128 }; 4129 4130 struct rtw89_chanctx_listener { 4131 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4132 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4133 }; 4134 4135 struct rtw89_chip_info { 4136 enum rtw89_core_chip_id chip_id; 4137 enum rtw89_chip_gen chip_gen; 4138 const struct rtw89_chip_ops *ops; 4139 const struct rtw89_mac_gen_def *mac_def; 4140 const struct rtw89_phy_gen_def *phy_def; 4141 const char *fw_basename; 4142 u8 fw_format_max; 4143 bool try_ce_fw; 4144 u8 bbmcu_nr; 4145 u32 needed_fw_elms; 4146 u32 fifo_size; 4147 bool small_fifo_size; 4148 u32 dle_scc_rsvd_size; 4149 u16 max_amsdu_limit; 4150 bool dis_2g_40m_ul_ofdma; 4151 u32 rsvd_ple_ofst; 4152 const struct rtw89_hfc_param_ini *hfc_param_ini; 4153 const struct rtw89_dle_mem *dle_mem; 4154 u8 wde_qempty_acq_grpnum; 4155 u8 wde_qempty_mgq_grpsel; 4156 u32 rf_base_addr[2]; 4157 u8 support_macid_num; 4158 u8 support_chanctx_num; 4159 u8 support_bands; 4160 u16 support_bandwidths; 4161 bool support_unii4; 4162 bool support_rnr; 4163 bool ul_tb_waveform_ctrl; 4164 bool ul_tb_pwr_diff; 4165 bool hw_sec_hdr; 4166 u8 rf_path_num; 4167 u8 tx_nss; 4168 u8 rx_nss; 4169 u8 acam_num; 4170 u8 bcam_num; 4171 u8 scam_num; 4172 u8 bacam_num; 4173 u8 bacam_dynamic_num; 4174 enum rtw89_bacam_ver bacam_ver; 4175 u8 ppdu_max_usr; 4176 4177 u8 sec_ctrl_efuse_size; 4178 u32 physical_efuse_size; 4179 u32 logical_efuse_size; 4180 u32 limit_efuse_size; 4181 u32 dav_phy_efuse_size; 4182 u32 dav_log_efuse_size; 4183 u32 phycap_addr; 4184 u32 phycap_size; 4185 const struct rtw89_efuse_block_cfg *efuse_blocks; 4186 4187 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4188 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4189 const struct rtw89_phy_table *bb_table; 4190 const struct rtw89_phy_table *bb_gain_table; 4191 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4192 const struct rtw89_phy_table *nctl_table; 4193 const struct rtw89_rfk_tbl *nctl_post_table; 4194 const struct rtw89_phy_dig_gain_table *dig_table; 4195 const struct rtw89_dig_regs *dig_regs; 4196 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4197 4198 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4199 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4200 const struct rtw89_rfe_parms *dflt_parms; 4201 const struct rtw89_chanctx_listener *chanctx_listener; 4202 4203 u8 txpwr_factor_rf; 4204 u8 txpwr_factor_mac; 4205 4206 u32 para_ver; 4207 u32 wlcx_desired; 4208 u8 btcx_desired; 4209 u8 scbd; 4210 u8 mailbox; 4211 4212 u8 afh_guard_ch; 4213 const u8 *wl_rssi_thres; 4214 const u8 *bt_rssi_thres; 4215 u8 rssi_tol; 4216 4217 u8 mon_reg_num; 4218 const struct rtw89_btc_fbtc_mreg *mon_reg; 4219 u8 rf_para_ulink_num; 4220 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4221 u8 rf_para_dlink_num; 4222 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4223 u8 ps_mode_supported; 4224 u8 low_power_hci_modes; 4225 4226 u32 h2c_cctl_func_id; 4227 u32 hci_func_en_addr; 4228 u32 h2c_desc_size; 4229 u32 txwd_body_size; 4230 u32 txwd_info_size; 4231 u32 h2c_ctrl_reg; 4232 const u32 *h2c_regs; 4233 struct rtw89_reg_def h2c_counter_reg; 4234 u32 c2h_ctrl_reg; 4235 const u32 *c2h_regs; 4236 struct rtw89_reg_def c2h_counter_reg; 4237 const struct rtw89_page_regs *page_regs; 4238 u32 wow_reason_reg; 4239 bool cfo_src_fd; 4240 bool cfo_hw_comp; 4241 const struct rtw89_reg_def *dcfo_comp; 4242 u8 dcfo_comp_sft; 4243 const struct rtw89_imr_info *imr_info; 4244 const struct rtw89_imr_table *imr_dmac_table; 4245 const struct rtw89_imr_table *imr_cmac_table; 4246 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4247 struct rtw89_reg_def bss_clr_vld; 4248 u32 bss_clr_map_reg; 4249 u32 dma_ch_mask; 4250 const struct rtw89_edcca_regs *edcca_regs; 4251 const struct wiphy_wowlan_support *wowlan_stub; 4252 const struct rtw89_xtal_info *xtal_info; 4253 }; 4254 4255 union rtw89_bus_info { 4256 const struct rtw89_pci_info *pci; 4257 }; 4258 4259 struct rtw89_driver_info { 4260 const struct rtw89_chip_info *chip; 4261 const struct dmi_system_id *quirks; 4262 union rtw89_bus_info bus; 4263 }; 4264 4265 enum rtw89_hcifc_mode { 4266 RTW89_HCIFC_POH = 0, 4267 RTW89_HCIFC_STF = 1, 4268 RTW89_HCIFC_SDIO = 2, 4269 4270 /* keep last */ 4271 RTW89_HCIFC_MODE_INVALID, 4272 }; 4273 4274 struct rtw89_dle_info { 4275 const struct rtw89_rsvd_quota *rsvd_qt; 4276 enum rtw89_qta_mode qta_mode; 4277 u16 ple_pg_size; 4278 u16 ple_free_pg; 4279 u16 c0_rx_qta; 4280 u16 c1_rx_qta; 4281 }; 4282 4283 enum rtw89_host_rpr_mode { 4284 RTW89_RPR_MODE_POH = 0, 4285 RTW89_RPR_MODE_STF 4286 }; 4287 4288 #define RTW89_COMPLETION_BUF_SIZE 40 4289 #define RTW89_WAIT_COND_IDLE UINT_MAX 4290 4291 struct rtw89_completion_data { 4292 bool err; 4293 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4294 }; 4295 4296 struct rtw89_wait_info { 4297 atomic_t cond; 4298 struct completion completion; 4299 struct rtw89_completion_data data; 4300 }; 4301 4302 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4303 4304 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4305 { 4306 init_completion(&wait->completion); 4307 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4308 } 4309 4310 struct rtw89_mac_info { 4311 struct rtw89_dle_info dle_info; 4312 struct rtw89_hfc_param hfc_param; 4313 enum rtw89_qta_mode qta_mode; 4314 u8 rpwm_seq_num; 4315 u8 cpwm_seq_num; 4316 4317 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4318 struct rtw89_wait_info fw_ofld_wait; 4319 }; 4320 4321 enum rtw89_fwdl_check_type { 4322 RTW89_FWDL_CHECK_FREERTOS_DONE, 4323 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4324 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4325 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4326 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4327 }; 4328 4329 enum rtw89_fw_type { 4330 RTW89_FW_NORMAL = 1, 4331 RTW89_FW_WOWLAN = 3, 4332 RTW89_FW_NORMAL_CE = 5, 4333 RTW89_FW_BBMCU0 = 64, 4334 RTW89_FW_BBMCU1 = 65, 4335 RTW89_FW_LOGFMT = 255, 4336 }; 4337 4338 enum rtw89_fw_feature { 4339 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4340 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4341 RTW89_FW_FEATURE_TX_WAKE, 4342 RTW89_FW_FEATURE_CRASH_TRIGGER, 4343 RTW89_FW_FEATURE_NO_PACKET_DROP, 4344 RTW89_FW_FEATURE_NO_DEEP_PS, 4345 RTW89_FW_FEATURE_NO_LPS_PG, 4346 RTW89_FW_FEATURE_BEACON_FILTER, 4347 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4348 }; 4349 4350 struct rtw89_fw_suit { 4351 enum rtw89_fw_type type; 4352 const u8 *data; 4353 u32 size; 4354 u8 major_ver; 4355 u8 minor_ver; 4356 u8 sub_ver; 4357 u8 sub_idex; 4358 u16 build_year; 4359 u16 build_mon; 4360 u16 build_date; 4361 u16 build_hour; 4362 u16 build_min; 4363 u8 cmd_ver; 4364 u8 hdr_ver; 4365 u32 commitid; 4366 }; 4367 4368 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4369 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4370 #define RTW89_FW_SUIT_VER_CODE(s) \ 4371 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4372 4373 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4374 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4375 (mfw_hdr)->ver.minor, \ 4376 (mfw_hdr)->ver.sub, \ 4377 (mfw_hdr)->ver.idx) 4378 4379 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4380 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4381 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4382 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4383 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4384 4385 struct rtw89_fw_req_info { 4386 const struct firmware *firmware; 4387 struct completion completion; 4388 }; 4389 4390 struct rtw89_fw_log { 4391 struct rtw89_fw_suit suit; 4392 bool enable; 4393 u32 last_fmt_id; 4394 u32 fmt_count; 4395 const __le32 *fmt_ids; 4396 const char *(*fmts)[]; 4397 }; 4398 4399 struct rtw89_fw_elm_info { 4400 struct rtw89_phy_table *bb_tbl; 4401 struct rtw89_phy_table *bb_gain; 4402 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4403 struct rtw89_phy_table *rf_nctl; 4404 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4405 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4406 }; 4407 4408 enum rtw89_fw_mss_dev_type { 4409 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4410 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4411 }; 4412 4413 struct rtw89_fw_secure { 4414 bool secure_boot; 4415 u32 sb_sel_mgn; 4416 u8 mss_dev_type; 4417 u8 mss_cust_idx; 4418 u8 mss_key_num; 4419 }; 4420 4421 struct rtw89_fw_info { 4422 struct rtw89_fw_req_info req; 4423 int fw_format; 4424 u8 h2c_seq; 4425 u8 rec_seq; 4426 u8 h2c_counter; 4427 u8 c2h_counter; 4428 struct rtw89_fw_suit normal; 4429 struct rtw89_fw_suit wowlan; 4430 struct rtw89_fw_suit bbmcu0; 4431 struct rtw89_fw_suit bbmcu1; 4432 struct rtw89_fw_log log; 4433 u32 feature_map; 4434 struct rtw89_fw_elm_info elm_info; 4435 struct rtw89_fw_secure sec; 4436 }; 4437 4438 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4439 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4440 4441 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4442 ((_fw)->feature_map |= BIT(_fw_feature)) 4443 4444 struct rtw89_cam_info { 4445 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4446 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4447 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4448 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4449 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4450 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4451 }; 4452 4453 enum rtw89_sar_sources { 4454 RTW89_SAR_SOURCE_NONE, 4455 RTW89_SAR_SOURCE_COMMON, 4456 4457 RTW89_SAR_SOURCE_NR, 4458 }; 4459 4460 enum rtw89_sar_subband { 4461 RTW89_SAR_2GHZ_SUBBAND, 4462 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4463 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4464 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4465 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4466 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4467 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4468 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4469 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4470 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4471 4472 RTW89_SAR_SUBBAND_NR, 4473 }; 4474 4475 struct rtw89_sar_cfg_common { 4476 bool set[RTW89_SAR_SUBBAND_NR]; 4477 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4478 }; 4479 4480 struct rtw89_sar_info { 4481 /* used to decide how to acces SAR cfg union */ 4482 enum rtw89_sar_sources src; 4483 4484 /* reserved for different knids of SAR cfg struct. 4485 * supposed that a single cfg struct cannot handle various SAR sources. 4486 */ 4487 union { 4488 struct rtw89_sar_cfg_common cfg_common; 4489 }; 4490 }; 4491 4492 enum rtw89_tas_state { 4493 RTW89_TAS_STATE_DPR_OFF, 4494 RTW89_TAS_STATE_DPR_ON, 4495 RTW89_TAS_STATE_DPR_FORBID, 4496 }; 4497 4498 #define RTW89_TAS_MAX_WINDOW 50 4499 struct rtw89_tas_info { 4500 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4501 s32 total_txpwr; 4502 u8 cur_idx; 4503 s8 dpr_gap; 4504 s8 delta; 4505 enum rtw89_tas_state state; 4506 bool enable; 4507 }; 4508 4509 struct rtw89_chanctx_cfg { 4510 enum rtw89_sub_entity_idx idx; 4511 int ref_count; 4512 }; 4513 4514 enum rtw89_chanctx_changes { 4515 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4516 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4517 RTW89_CHANCTX_P2P_PS_CHANGE, 4518 RTW89_CHANCTX_BT_SLOT_CHANGE, 4519 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4520 4521 NUM_OF_RTW89_CHANCTX_CHANGES, 4522 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4523 }; 4524 4525 enum rtw89_entity_mode { 4526 RTW89_ENTITY_MODE_SCC, 4527 RTW89_ENTITY_MODE_MCC_PREPARE, 4528 RTW89_ENTITY_MODE_MCC, 4529 4530 NUM_OF_RTW89_ENTITY_MODE, 4531 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4532 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4533 }; 4534 4535 struct rtw89_sub_entity { 4536 struct cfg80211_chan_def chandef; 4537 struct rtw89_chan chan; 4538 struct rtw89_chan_rcd rcd; 4539 4540 /* only assigned when running with chanctx_ops */ 4541 struct rtw89_chanctx_cfg *cfg; 4542 }; 4543 4544 struct rtw89_edcca_bak { 4545 u8 a; 4546 u8 p; 4547 u8 ppdu; 4548 u8 th_old; 4549 }; 4550 4551 enum rtw89_dm_type { 4552 RTW89_DM_DYNAMIC_EDCCA, 4553 }; 4554 4555 struct rtw89_hal { 4556 u32 rx_fltr; 4557 u8 cv; 4558 u8 acv; 4559 u32 antenna_tx; 4560 u32 antenna_rx; 4561 u8 tx_nss; 4562 u8 rx_nss; 4563 bool tx_path_diversity; 4564 bool ant_diversity; 4565 bool ant_diversity_fixed; 4566 bool support_cckpd; 4567 bool support_igi; 4568 atomic_t roc_entity_idx; 4569 4570 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4571 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4572 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4573 struct cfg80211_chan_def roc_chandef; 4574 4575 bool entity_active; 4576 bool entity_pause; 4577 enum rtw89_entity_mode entity_mode; 4578 4579 struct rtw89_edcca_bak edcca_bak; 4580 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4581 }; 4582 4583 #define RTW89_MAX_MAC_ID_NUM 128 4584 #define RTW89_MAX_PKT_OFLD_NUM 255 4585 4586 enum rtw89_flags { 4587 RTW89_FLAG_POWERON, 4588 RTW89_FLAG_DMAC_FUNC, 4589 RTW89_FLAG_CMAC0_FUNC, 4590 RTW89_FLAG_CMAC1_FUNC, 4591 RTW89_FLAG_FW_RDY, 4592 RTW89_FLAG_RUNNING, 4593 RTW89_FLAG_PROBE_DONE, 4594 RTW89_FLAG_BFEE_MON, 4595 RTW89_FLAG_BFEE_EN, 4596 RTW89_FLAG_BFEE_TIMER_KEEP, 4597 RTW89_FLAG_NAPI_RUNNING, 4598 RTW89_FLAG_LEISURE_PS, 4599 RTW89_FLAG_LOW_POWER_MODE, 4600 RTW89_FLAG_INACTIVE_PS, 4601 RTW89_FLAG_CRASH_SIMULATING, 4602 RTW89_FLAG_SER_HANDLING, 4603 RTW89_FLAG_WOWLAN, 4604 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4605 RTW89_FLAG_CHANGING_INTERFACE, 4606 4607 NUM_OF_RTW89_FLAGS, 4608 }; 4609 4610 enum rtw89_quirks { 4611 RTW89_QUIRK_PCI_BER, 4612 4613 NUM_OF_RTW89_QUIRKS, 4614 }; 4615 4616 enum rtw89_pkt_drop_sel { 4617 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4618 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4619 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4620 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4621 RTW89_PKT_DROP_SEL_MACID_ALL, 4622 RTW89_PKT_DROP_SEL_MG0_ONCE, 4623 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4624 RTW89_PKT_DROP_SEL_HIQ_PORT, 4625 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4626 RTW89_PKT_DROP_SEL_BAND, 4627 RTW89_PKT_DROP_SEL_BAND_ONCE, 4628 RTW89_PKT_DROP_SEL_REL_MACID, 4629 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4630 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4631 }; 4632 4633 struct rtw89_pkt_drop_params { 4634 enum rtw89_pkt_drop_sel sel; 4635 enum rtw89_mac_idx mac_band; 4636 u8 macid; 4637 u8 port; 4638 u8 mbssid; 4639 bool tf_trs; 4640 u32 macid_band_sel[4]; 4641 }; 4642 4643 struct rtw89_pkt_stat { 4644 u16 beacon_nr; 4645 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4646 }; 4647 4648 DECLARE_EWMA(thermal, 4, 4); 4649 4650 struct rtw89_phy_stat { 4651 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4652 struct rtw89_pkt_stat cur_pkt_stat; 4653 struct rtw89_pkt_stat last_pkt_stat; 4654 }; 4655 4656 enum rtw89_rfk_report_state { 4657 RTW89_RFK_STATE_START = 0x0, 4658 RTW89_RFK_STATE_OK = 0x1, 4659 RTW89_RFK_STATE_FAIL = 0x2, 4660 RTW89_RFK_STATE_TIMEOUT = 0x3, 4661 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4662 }; 4663 4664 struct rtw89_rfk_wait_info { 4665 struct completion completion; 4666 ktime_t start_time; 4667 enum rtw89_rfk_report_state state; 4668 u8 version; 4669 }; 4670 4671 #define RTW89_DACK_PATH_NR 2 4672 #define RTW89_DACK_IDX_NR 2 4673 #define RTW89_DACK_MSBK_NR 16 4674 struct rtw89_dack_info { 4675 bool dack_done; 4676 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4677 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4678 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4679 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4680 u32 dack_cnt; 4681 bool addck_timeout[RTW89_DACK_PATH_NR]; 4682 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4683 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4684 }; 4685 4686 #define RTW89_RFK_CHS_NR 3 4687 4688 struct rtw89_rfk_mcc_info { 4689 u8 ch[RTW89_RFK_CHS_NR]; 4690 u8 band[RTW89_RFK_CHS_NR]; 4691 u8 bw[RTW89_RFK_CHS_NR]; 4692 u8 table_idx; 4693 }; 4694 4695 #define RTW89_IQK_CHS_NR 2 4696 #define RTW89_IQK_PATH_NR 4 4697 4698 struct rtw89_lck_info { 4699 u8 thermal[RF_PATH_MAX]; 4700 }; 4701 4702 struct rtw89_rx_dck_info { 4703 u8 thermal[RF_PATH_MAX]; 4704 }; 4705 4706 struct rtw89_iqk_info { 4707 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4708 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4709 bool lok_fail[RTW89_IQK_PATH_NR]; 4710 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4711 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4712 u32 iqk_fail_cnt; 4713 bool is_iqk_init; 4714 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4715 u8 iqk_band[RTW89_IQK_PATH_NR]; 4716 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4717 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4718 u8 iqk_times; 4719 u8 version; 4720 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4721 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4722 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4723 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4724 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4725 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4726 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4727 bool is_nbiqk; 4728 bool iqk_fft_en; 4729 bool iqk_xym_en; 4730 bool iqk_sram_en; 4731 bool iqk_cfir_en; 4732 u32 syn1to2; 4733 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4734 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4735 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4736 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4737 }; 4738 4739 #define RTW89_DPK_RF_PATH 2 4740 #define RTW89_DPK_AVG_THERMAL_NUM 8 4741 #define RTW89_DPK_BKUP_NUM 2 4742 struct rtw89_dpk_bkup_para { 4743 enum rtw89_band band; 4744 enum rtw89_bandwidth bw; 4745 u8 ch; 4746 bool path_ok; 4747 u8 mdpd_en; 4748 u8 txagc_dpk; 4749 u8 ther_dpk; 4750 u8 gs; 4751 u16 pwsf; 4752 }; 4753 4754 struct rtw89_dpk_info { 4755 bool is_dpk_enable; 4756 bool is_dpk_reload_en; 4757 u8 dpk_gs[RTW89_PHY_MAX]; 4758 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4759 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4760 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4761 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4762 u8 cur_idx[RTW89_DPK_RF_PATH]; 4763 u8 cur_k_set; 4764 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4765 }; 4766 4767 struct rtw89_fem_info { 4768 bool elna_2g; 4769 bool elna_5g; 4770 bool epa_2g; 4771 bool epa_5g; 4772 bool epa_6g; 4773 }; 4774 4775 struct rtw89_phy_ch_info { 4776 u8 rssi_min; 4777 u16 rssi_min_macid; 4778 u8 pre_rssi_min; 4779 u8 rssi_max; 4780 u16 rssi_max_macid; 4781 u8 rxsc_160; 4782 u8 rxsc_80; 4783 u8 rxsc_40; 4784 u8 rxsc_20; 4785 u8 rxsc_l; 4786 u8 is_noisy; 4787 }; 4788 4789 struct rtw89_agc_gaincode_set { 4790 u8 lna_idx; 4791 u8 tia_idx; 4792 u8 rxb_idx; 4793 }; 4794 4795 #define IGI_RSSI_TH_NUM 5 4796 #define FA_TH_NUM 4 4797 #define LNA_GAIN_NUM 7 4798 #define TIA_GAIN_NUM 2 4799 struct rtw89_dig_info { 4800 struct rtw89_agc_gaincode_set cur_gaincode; 4801 bool force_gaincode_idx_en; 4802 struct rtw89_agc_gaincode_set force_gaincode; 4803 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4804 u16 fa_th[FA_TH_NUM]; 4805 u8 igi_rssi; 4806 u8 igi_fa_rssi; 4807 u8 fa_rssi_ofst; 4808 u8 dyn_igi_max; 4809 u8 dyn_igi_min; 4810 bool dyn_pd_th_en; 4811 u8 dyn_pd_th_max; 4812 u8 pd_low_th_ofst; 4813 u8 ib_pbk; 4814 s8 ib_pkpwr; 4815 s8 lna_gain_a[LNA_GAIN_NUM]; 4816 s8 lna_gain_g[LNA_GAIN_NUM]; 4817 s8 *lna_gain; 4818 s8 tia_gain_a[TIA_GAIN_NUM]; 4819 s8 tia_gain_g[TIA_GAIN_NUM]; 4820 s8 *tia_gain; 4821 bool is_linked_pre; 4822 bool bypass_dig; 4823 }; 4824 4825 enum rtw89_multi_cfo_mode { 4826 RTW89_PKT_BASED_AVG_MODE = 0, 4827 RTW89_ENTRY_BASED_AVG_MODE = 1, 4828 RTW89_TP_BASED_AVG_MODE = 2, 4829 }; 4830 4831 enum rtw89_phy_cfo_status { 4832 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4833 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4834 RTW89_PHY_DCFO_STATE_HOLD = 2, 4835 RTW89_PHY_DCFO_STATE_MAX 4836 }; 4837 4838 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4839 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4840 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4841 }; 4842 4843 struct rtw89_cfo_tracking_info { 4844 u16 cfo_timer_ms; 4845 bool cfo_trig_by_timer_en; 4846 enum rtw89_phy_cfo_status phy_cfo_status; 4847 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4848 u8 phy_cfo_trk_cnt; 4849 bool is_adjust; 4850 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4851 bool apply_compensation; 4852 u8 crystal_cap; 4853 u8 crystal_cap_default; 4854 u8 def_x_cap; 4855 s8 x_cap_ofst; 4856 u32 sta_cfo_tolerance; 4857 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4858 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4859 s32 cfo_avg_pre; 4860 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4861 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4862 s32 dcfo_avg; 4863 s32 dcfo_avg_pre; 4864 u32 packet_count; 4865 u32 packet_count_pre; 4866 s32 residual_cfo_acc; 4867 u8 phy_cfotrk_state; 4868 u8 phy_cfotrk_cnt; 4869 bool divergence_lock_en; 4870 u8 x_cap_lb; 4871 u8 x_cap_ub; 4872 u8 lock_cnt; 4873 }; 4874 4875 enum rtw89_tssi_mode { 4876 RTW89_TSSI_NORMAL = 0, 4877 RTW89_TSSI_SCAN = 1, 4878 }; 4879 4880 enum rtw89_tssi_alimk_band { 4881 TSSI_ALIMK_2G = 0, 4882 TSSI_ALIMK_5GL, 4883 TSSI_ALIMK_5GM, 4884 TSSI_ALIMK_5GH, 4885 TSSI_ALIMK_MAX 4886 }; 4887 4888 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4889 #define TSSI_TRIM_CH_GROUP_NUM 8 4890 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4891 4892 #define TSSI_CCK_CH_GROUP_NUM 6 4893 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4894 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4895 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4896 #define TSSI_MCS_CH_GROUP_NUM \ 4897 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4898 #define TSSI_MAX_CH_NUM 67 4899 #define TSSI_ALIMK_VALUE_NUM 8 4900 4901 struct rtw89_tssi_info { 4902 u8 thermal[RF_PATH_MAX]; 4903 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4904 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4905 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4906 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4907 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4908 s8 extra_ofst[RF_PATH_MAX]; 4909 bool tssi_tracking_check[RF_PATH_MAX]; 4910 u8 default_txagc_offset[RF_PATH_MAX]; 4911 u32 base_thermal[RF_PATH_MAX]; 4912 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4913 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4914 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4915 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4916 u32 tssi_alimk_time; 4917 }; 4918 4919 struct rtw89_power_trim_info { 4920 bool pg_thermal_trim; 4921 bool pg_pa_bias_trim; 4922 u8 thermal_trim[RF_PATH_MAX]; 4923 u8 pa_bias_trim[RF_PATH_MAX]; 4924 u8 pad_bias_trim[RF_PATH_MAX]; 4925 }; 4926 4927 struct rtw89_regd { 4928 char alpha2[3]; 4929 u8 txpwr_regd[RTW89_BAND_NUM]; 4930 }; 4931 4932 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4933 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 4934 #define RTW89_5GHZ_UNII4_START_INDEX 25 4935 4936 struct rtw89_regulatory_info { 4937 const struct rtw89_regd *regd; 4938 enum rtw89_reg_6ghz_power reg_6ghz_power; 4939 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 4940 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4941 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 4942 }; 4943 4944 enum rtw89_ifs_clm_application { 4945 RTW89_IFS_CLM_INIT = 0, 4946 RTW89_IFS_CLM_BACKGROUND = 1, 4947 RTW89_IFS_CLM_ACS = 2, 4948 RTW89_IFS_CLM_DIG = 3, 4949 RTW89_IFS_CLM_TDMA_DIG = 4, 4950 RTW89_IFS_CLM_DBG = 5, 4951 RTW89_IFS_CLM_DBG_MANUAL = 6 4952 }; 4953 4954 enum rtw89_env_racing_lv { 4955 RTW89_RAC_RELEASE = 0, 4956 RTW89_RAC_LV_1 = 1, 4957 RTW89_RAC_LV_2 = 2, 4958 RTW89_RAC_LV_3 = 3, 4959 RTW89_RAC_LV_4 = 4, 4960 RTW89_RAC_MAX_NUM = 5 4961 }; 4962 4963 struct rtw89_ccx_para_info { 4964 enum rtw89_env_racing_lv rac_lv; 4965 u16 mntr_time; 4966 u8 nhm_manual_th_ofst; 4967 u8 nhm_manual_th0; 4968 enum rtw89_ifs_clm_application ifs_clm_app; 4969 u32 ifs_clm_manual_th_times; 4970 u32 ifs_clm_manual_th0; 4971 u8 fahm_manual_th_ofst; 4972 u8 fahm_manual_th0; 4973 u8 fahm_numer_opt; 4974 u8 fahm_denom_opt; 4975 }; 4976 4977 enum rtw89_ccx_edcca_opt_sc_idx { 4978 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4979 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4980 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4981 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4982 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4983 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4984 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4985 RTW89_CCX_EDCCA_SEG1_S3 = 7 4986 }; 4987 4988 enum rtw89_ccx_edcca_opt_bw_idx { 4989 RTW89_CCX_EDCCA_BW20_0 = 0, 4990 RTW89_CCX_EDCCA_BW20_1 = 1, 4991 RTW89_CCX_EDCCA_BW20_2 = 2, 4992 RTW89_CCX_EDCCA_BW20_3 = 3, 4993 RTW89_CCX_EDCCA_BW20_4 = 4, 4994 RTW89_CCX_EDCCA_BW20_5 = 5, 4995 RTW89_CCX_EDCCA_BW20_6 = 6, 4996 RTW89_CCX_EDCCA_BW20_7 = 7 4997 }; 4998 4999 #define RTW89_NHM_TH_NUM 11 5000 #define RTW89_FAHM_TH_NUM 11 5001 #define RTW89_NHM_RPT_NUM 12 5002 #define RTW89_FAHM_RPT_NUM 12 5003 #define RTW89_IFS_CLM_NUM 4 5004 struct rtw89_env_monitor_info { 5005 u8 ccx_watchdog_result; 5006 bool ccx_ongoing; 5007 u8 ccx_rac_lv; 5008 bool ccx_manual_ctrl; 5009 u16 ifs_clm_mntr_time; 5010 enum rtw89_ifs_clm_application ifs_clm_app; 5011 u16 ccx_period; 5012 u8 ccx_unit_idx; 5013 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5014 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5015 u16 ifs_clm_tx; 5016 u16 ifs_clm_edcca_excl_cca; 5017 u16 ifs_clm_ofdmfa; 5018 u16 ifs_clm_ofdmcca_excl_fa; 5019 u16 ifs_clm_cckfa; 5020 u16 ifs_clm_cckcca_excl_fa; 5021 u16 ifs_clm_total_ifs; 5022 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5023 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5024 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5025 u8 ifs_clm_tx_ratio; 5026 u8 ifs_clm_edcca_excl_cca_ratio; 5027 u8 ifs_clm_cck_fa_ratio; 5028 u8 ifs_clm_ofdm_fa_ratio; 5029 u8 ifs_clm_cck_cca_excl_fa_ratio; 5030 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5031 u16 ifs_clm_cck_fa_permil; 5032 u16 ifs_clm_ofdm_fa_permil; 5033 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5034 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5035 }; 5036 5037 enum rtw89_ser_rcvy_step { 5038 RTW89_SER_DRV_STOP_TX, 5039 RTW89_SER_DRV_STOP_RX, 5040 RTW89_SER_DRV_STOP_RUN, 5041 RTW89_SER_HAL_STOP_DMA, 5042 RTW89_SER_SUPPRESS_LOG, 5043 RTW89_NUM_OF_SER_FLAGS 5044 }; 5045 5046 struct rtw89_ser { 5047 u8 state; 5048 u8 alarm_event; 5049 bool prehandle_l1; 5050 5051 struct work_struct ser_hdl_work; 5052 struct delayed_work ser_alarm_work; 5053 const struct state_ent *st_tbl; 5054 const struct event_ent *ev_tbl; 5055 struct list_head msg_q; 5056 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5057 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5058 }; 5059 5060 enum rtw89_mac_ax_ps_mode { 5061 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5062 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5063 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5064 RTW89_MAC_AX_PS_MODE_MAX = 3, 5065 }; 5066 5067 enum rtw89_last_rpwm_mode { 5068 RTW89_LAST_RPWM_PS = 0x0, 5069 RTW89_LAST_RPWM_ACTIVE = 0x6, 5070 }; 5071 5072 struct rtw89_lps_parm { 5073 u8 macid; 5074 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5075 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5076 }; 5077 5078 struct rtw89_ppdu_sts_info { 5079 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 5080 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 5081 }; 5082 5083 struct rtw89_early_h2c { 5084 struct list_head list; 5085 u8 *h2c; 5086 u16 h2c_len; 5087 }; 5088 5089 struct rtw89_hw_scan_info { 5090 struct ieee80211_vif *scanning_vif; 5091 struct list_head pkt_list[NUM_NL80211_BANDS]; 5092 struct rtw89_chan op_chan; 5093 bool abort; 5094 u32 last_chan_idx; 5095 }; 5096 5097 enum rtw89_phy_bb_gain_band { 5098 RTW89_BB_GAIN_BAND_2G = 0, 5099 RTW89_BB_GAIN_BAND_5G_L = 1, 5100 RTW89_BB_GAIN_BAND_5G_M = 2, 5101 RTW89_BB_GAIN_BAND_5G_H = 3, 5102 RTW89_BB_GAIN_BAND_6G_L = 4, 5103 RTW89_BB_GAIN_BAND_6G_M = 5, 5104 RTW89_BB_GAIN_BAND_6G_H = 6, 5105 RTW89_BB_GAIN_BAND_6G_UH = 7, 5106 5107 RTW89_BB_GAIN_BAND_NR, 5108 }; 5109 5110 enum rtw89_phy_gain_band_be { 5111 RTW89_BB_GAIN_BAND_2G_BE = 0, 5112 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5113 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5114 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5115 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5116 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5117 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5118 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5119 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5120 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5121 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5122 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5123 5124 RTW89_BB_GAIN_BAND_NR_BE, 5125 }; 5126 5127 enum rtw89_phy_bb_bw_be { 5128 RTW89_BB_BW_20_40 = 0, 5129 RTW89_BB_BW_80_160_320 = 1, 5130 5131 RTW89_BB_BW_NR_BE, 5132 }; 5133 5134 enum rtw89_bw20_sc { 5135 RTW89_BW20_SC_20M = 1, 5136 RTW89_BW20_SC_40M = 2, 5137 RTW89_BW20_SC_80M = 4, 5138 RTW89_BW20_SC_160M = 8, 5139 RTW89_BW20_SC_320M = 16, 5140 }; 5141 5142 enum rtw89_cmac_table_bw { 5143 RTW89_CMAC_BW_20M = 0, 5144 RTW89_CMAC_BW_40M = 1, 5145 RTW89_CMAC_BW_80M = 2, 5146 RTW89_CMAC_BW_160M = 3, 5147 RTW89_CMAC_BW_320M = 4, 5148 5149 RTW89_CMAC_BW_NR, 5150 }; 5151 5152 enum rtw89_phy_bb_rxsc_num { 5153 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5154 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5155 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5156 }; 5157 5158 struct rtw89_phy_bb_gain_info { 5159 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5160 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5161 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5162 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5163 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5164 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5165 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5166 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5167 [RTW89_BB_RXSC_NUM_40]; 5168 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5169 [RTW89_BB_RXSC_NUM_80]; 5170 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5171 [RTW89_BB_RXSC_NUM_160]; 5172 }; 5173 5174 struct rtw89_phy_bb_gain_info_be { 5175 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5176 [LNA_GAIN_NUM]; 5177 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5178 [TIA_GAIN_NUM]; 5179 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5180 [RF_PATH_MAX][LNA_GAIN_NUM]; 5181 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5182 [RF_PATH_MAX][LNA_GAIN_NUM]; 5183 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5184 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5185 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5186 [RTW89_BW20_SC_20M]; 5187 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5188 [RTW89_BW20_SC_40M]; 5189 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5190 [RTW89_BW20_SC_80M]; 5191 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5192 [RTW89_BW20_SC_160M]; 5193 }; 5194 5195 struct rtw89_phy_efuse_gain { 5196 bool offset_valid; 5197 bool comp_valid; 5198 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5199 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5200 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5201 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5202 }; 5203 5204 #define RTW89_MAX_PATTERN_NUM 18 5205 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5206 #define RTW89_MAX_PATTERN_SIZE 128 5207 5208 struct rtw89_wow_cam_info { 5209 bool r_w; 5210 u8 idx; 5211 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5212 u16 crc; 5213 bool negative_pattern_match; 5214 bool skip_mac_hdr; 5215 bool uc; 5216 bool mc; 5217 bool bc; 5218 bool valid; 5219 }; 5220 5221 struct rtw89_wow_key_info { 5222 u8 ptk_tx_iv[8]; 5223 u8 valid_check; 5224 u8 symbol_check_en; 5225 u8 gtk_keyidx; 5226 u8 rsvd[5]; 5227 u8 ptk_rx_iv[8]; 5228 u8 gtk_rx_iv[4][8]; 5229 } __packed; 5230 5231 struct rtw89_wow_gtk_info { 5232 u8 kck[32]; 5233 u8 kek[32]; 5234 u8 tk1[16]; 5235 u8 txmickey[8]; 5236 u8 rxmickey[8]; 5237 __le32 igtk_keyid; 5238 __le64 ipn; 5239 u8 igtk[2][32]; 5240 u8 psk[32]; 5241 } __packed; 5242 5243 struct rtw89_wow_aoac_report { 5244 u8 rpt_ver; 5245 u8 sec_type; 5246 u8 key_idx; 5247 u8 pattern_idx; 5248 u8 rekey_ok; 5249 u8 ptk_tx_iv[8]; 5250 u8 eapol_key_replay_count[8]; 5251 u8 gtk[32]; 5252 u8 ptk_rx_iv[8]; 5253 u8 gtk_rx_iv[4][8]; 5254 u64 igtk_key_id; 5255 u64 igtk_ipn; 5256 u8 igtk[32]; 5257 u8 csa_pri_ch; 5258 u8 csa_bw; 5259 u8 csa_ch_offset; 5260 u8 csa_chsw_failed; 5261 u8 csa_ch_band; 5262 }; 5263 5264 struct rtw89_wow_param { 5265 struct ieee80211_vif *wow_vif; 5266 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5267 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5268 struct rtw89_wow_key_info key_info; 5269 struct rtw89_wow_gtk_info gtk_info; 5270 struct rtw89_wow_aoac_report aoac_rpt; 5271 u8 pattern_cnt; 5272 u8 ptk_alg; 5273 u8 gtk_alg; 5274 u8 ptk_keyidx; 5275 u8 akm; 5276 }; 5277 5278 struct rtw89_mcc_limit { 5279 bool enable; 5280 u16 max_tob; /* TU; max time offset behind */ 5281 u16 max_toa; /* TU; max time offset ahead */ 5282 u16 max_dur; /* TU */ 5283 }; 5284 5285 struct rtw89_mcc_policy { 5286 u8 c2h_rpt; 5287 u8 tx_null_early; 5288 u8 dis_tx_null; 5289 u8 in_curr_ch; 5290 u8 dis_sw_retry; 5291 u8 sw_retry_count; 5292 }; 5293 5294 struct rtw89_mcc_role { 5295 struct rtw89_vif *rtwvif; 5296 struct rtw89_mcc_policy policy; 5297 struct rtw89_mcc_limit limit; 5298 5299 /* only valid when running with FW MRC mechanism */ 5300 u8 slot_idx; 5301 5302 /* byte-array in LE order for FW */ 5303 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5304 5305 u16 duration; /* TU */ 5306 u16 beacon_interval; /* TU */ 5307 bool is_2ghz; 5308 bool is_go; 5309 bool is_gc; 5310 }; 5311 5312 struct rtw89_mcc_bt_role { 5313 u16 duration; /* TU */ 5314 }; 5315 5316 struct rtw89_mcc_courtesy { 5317 bool enable; 5318 u8 slot_num; 5319 u8 macid_src; 5320 u8 macid_tgt; 5321 }; 5322 5323 enum rtw89_mcc_plan { 5324 RTW89_MCC_PLAN_TAIL_BT, 5325 RTW89_MCC_PLAN_MID_BT, 5326 RTW89_MCC_PLAN_NO_BT, 5327 5328 NUM_OF_RTW89_MCC_PLAN, 5329 }; 5330 5331 struct rtw89_mcc_pattern { 5332 s16 tob_ref; /* TU; time offset behind of reference role */ 5333 s16 toa_ref; /* TU; time offset ahead of reference role */ 5334 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5335 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5336 5337 enum rtw89_mcc_plan plan; 5338 struct rtw89_mcc_courtesy courtesy; 5339 }; 5340 5341 struct rtw89_mcc_sync { 5342 bool enable; 5343 u16 offset; /* TU */ 5344 u8 macid_src; 5345 u8 band_src; 5346 u8 port_src; 5347 u8 macid_tgt; 5348 u8 band_tgt; 5349 u8 port_tgt; 5350 }; 5351 5352 struct rtw89_mcc_config { 5353 struct rtw89_mcc_pattern pattern; 5354 struct rtw89_mcc_sync sync; 5355 u64 start_tsf; 5356 u16 mcc_interval; /* TU */ 5357 u16 beacon_offset; /* TU */ 5358 }; 5359 5360 enum rtw89_mcc_mode { 5361 RTW89_MCC_MODE_GO_STA, 5362 RTW89_MCC_MODE_GC_STA, 5363 }; 5364 5365 struct rtw89_mcc_info { 5366 struct rtw89_wait_info wait; 5367 5368 u8 group; 5369 enum rtw89_mcc_mode mode; 5370 struct rtw89_mcc_role role_ref; /* reference role */ 5371 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5372 struct rtw89_mcc_bt_role bt_role; 5373 struct rtw89_mcc_config config; 5374 }; 5375 5376 struct rtw89_dev { 5377 struct ieee80211_hw *hw; 5378 struct device *dev; 5379 const struct ieee80211_ops *ops; 5380 5381 bool dbcc_en; 5382 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5383 struct rtw89_hw_scan_info scan_info; 5384 const struct rtw89_chip_info *chip; 5385 const struct rtw89_pci_info *pci_info; 5386 const struct rtw89_rfe_parms *rfe_parms; 5387 struct rtw89_hal hal; 5388 struct rtw89_mcc_info mcc; 5389 struct rtw89_mac_info mac; 5390 struct rtw89_fw_info fw; 5391 struct rtw89_hci_info hci; 5392 struct rtw89_efuse efuse; 5393 struct rtw89_traffic_stats stats; 5394 struct rtw89_rfe_data *rfe_data; 5395 5396 /* ensures exclusive access from mac80211 callbacks */ 5397 struct mutex mutex; 5398 struct list_head rtwvifs_list; 5399 /* used to protect rf read write */ 5400 struct mutex rf_mutex; 5401 struct workqueue_struct *txq_wq; 5402 struct work_struct txq_work; 5403 struct delayed_work txq_reinvoke_work; 5404 /* used to protect ba_list and forbid_ba_list */ 5405 spinlock_t ba_lock; 5406 /* txqs to setup ba session */ 5407 struct list_head ba_list; 5408 /* txqs to forbid ba session */ 5409 struct list_head forbid_ba_list; 5410 struct work_struct ba_work; 5411 /* used to protect rpwm */ 5412 spinlock_t rpwm_lock; 5413 5414 struct rtw89_cam_info cam_info; 5415 5416 struct sk_buff_head c2h_queue; 5417 struct work_struct c2h_work; 5418 struct work_struct ips_work; 5419 struct work_struct load_firmware_work; 5420 struct work_struct cancel_6ghz_probe_work; 5421 5422 struct list_head early_h2c_list; 5423 5424 struct rtw89_ser ser; 5425 5426 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5427 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5428 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5429 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5430 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5431 5432 struct rtw89_phy_stat phystat; 5433 struct rtw89_rfk_wait_info rfk_wait; 5434 struct rtw89_dack_info dack; 5435 struct rtw89_iqk_info iqk; 5436 struct rtw89_dpk_info dpk; 5437 struct rtw89_rfk_mcc_info rfk_mcc; 5438 struct rtw89_lck_info lck; 5439 struct rtw89_rx_dck_info rx_dck; 5440 bool is_tssi_mode[RF_PATH_MAX]; 5441 bool is_bt_iqk_timeout; 5442 5443 struct rtw89_fem_info fem; 5444 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5445 struct rtw89_tssi_info tssi; 5446 struct rtw89_power_trim_info pwr_trim; 5447 5448 struct rtw89_cfo_tracking_info cfo_tracking; 5449 struct rtw89_env_monitor_info env_monitor; 5450 struct rtw89_dig_info dig; 5451 struct rtw89_phy_ch_info ch_info; 5452 union { 5453 struct rtw89_phy_bb_gain_info ax; 5454 struct rtw89_phy_bb_gain_info_be be; 5455 } bb_gain; 5456 struct rtw89_phy_efuse_gain efuse_gain; 5457 struct rtw89_phy_ul_tb_info ul_tb_info; 5458 struct rtw89_antdiv_info antdiv; 5459 5460 struct delayed_work track_work; 5461 struct delayed_work chanctx_work; 5462 struct delayed_work coex_act1_work; 5463 struct delayed_work coex_bt_devinfo_work; 5464 struct delayed_work coex_rfk_chk_work; 5465 struct delayed_work cfo_track_work; 5466 struct delayed_work forbid_ba_work; 5467 struct delayed_work roc_work; 5468 struct delayed_work antdiv_work; 5469 struct rtw89_ppdu_sts_info ppdu_sts; 5470 u8 total_sta_assoc; 5471 bool scanning; 5472 5473 struct rtw89_regulatory_info regulatory; 5474 struct rtw89_sar_info sar; 5475 struct rtw89_tas_info tas; 5476 5477 struct rtw89_btc btc; 5478 enum rtw89_ps_mode ps_mode; 5479 bool lps_enabled; 5480 5481 struct rtw89_wow_param wow; 5482 5483 /* napi structure */ 5484 struct net_device *netdev; 5485 struct napi_struct napi; 5486 int napi_budget_countdown; 5487 5488 /* HCI related data, keep last */ 5489 u8 priv[] __aligned(sizeof(void *)); 5490 }; 5491 5492 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5493 struct rtw89_core_tx_request *tx_req) 5494 { 5495 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5496 } 5497 5498 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5499 { 5500 rtwdev->hci.ops->reset(rtwdev); 5501 } 5502 5503 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5504 { 5505 return rtwdev->hci.ops->start(rtwdev); 5506 } 5507 5508 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5509 { 5510 rtwdev->hci.ops->stop(rtwdev); 5511 } 5512 5513 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5514 { 5515 return rtwdev->hci.ops->deinit(rtwdev); 5516 } 5517 5518 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5519 { 5520 rtwdev->hci.ops->pause(rtwdev, pause); 5521 } 5522 5523 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5524 { 5525 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5526 } 5527 5528 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5529 { 5530 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5531 } 5532 5533 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5534 { 5535 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5536 } 5537 5538 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5539 { 5540 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5541 } 5542 5543 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5544 { 5545 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5546 } 5547 5548 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5549 bool drop) 5550 { 5551 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5552 return; 5553 5554 if (rtwdev->hci.ops->flush_queues) 5555 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5556 } 5557 5558 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5559 { 5560 if (rtwdev->hci.ops->recovery_start) 5561 rtwdev->hci.ops->recovery_start(rtwdev); 5562 } 5563 5564 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5565 { 5566 if (rtwdev->hci.ops->recovery_complete) 5567 rtwdev->hci.ops->recovery_complete(rtwdev); 5568 } 5569 5570 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5571 { 5572 if (rtwdev->hci.ops->enable_intr) 5573 rtwdev->hci.ops->enable_intr(rtwdev); 5574 } 5575 5576 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5577 { 5578 if (rtwdev->hci.ops->disable_intr) 5579 rtwdev->hci.ops->disable_intr(rtwdev); 5580 } 5581 5582 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5583 { 5584 if (rtwdev->hci.ops->ctrl_txdma_ch) 5585 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5586 } 5587 5588 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5589 { 5590 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5591 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5592 } 5593 5594 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5595 { 5596 if (rtwdev->hci.ops->ctrl_trxhci) 5597 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5598 } 5599 5600 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5601 { 5602 int ret = 0; 5603 5604 if (rtwdev->hci.ops->poll_txdma_ch_idle) 5605 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 5606 return ret; 5607 } 5608 5609 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5610 { 5611 if (rtwdev->hci.ops->clr_idx_all) 5612 rtwdev->hci.ops->clr_idx_all(rtwdev); 5613 } 5614 5615 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 5616 { 5617 int ret = 0; 5618 5619 if (rtwdev->hci.ops->rst_bdram) 5620 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 5621 return ret; 5622 } 5623 5624 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 5625 { 5626 if (rtwdev->hci.ops->clear) 5627 rtwdev->hci.ops->clear(rtwdev, pdev); 5628 } 5629 5630 static inline 5631 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5632 { 5633 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5634 5635 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5636 } 5637 5638 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5639 { 5640 return rtwdev->hci.ops->read8(rtwdev, addr); 5641 } 5642 5643 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5644 { 5645 return rtwdev->hci.ops->read16(rtwdev, addr); 5646 } 5647 5648 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5649 { 5650 return rtwdev->hci.ops->read32(rtwdev, addr); 5651 } 5652 5653 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5654 { 5655 rtwdev->hci.ops->write8(rtwdev, addr, data); 5656 } 5657 5658 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5659 { 5660 rtwdev->hci.ops->write16(rtwdev, addr, data); 5661 } 5662 5663 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5664 { 5665 rtwdev->hci.ops->write32(rtwdev, addr, data); 5666 } 5667 5668 static inline void 5669 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5670 { 5671 u8 val; 5672 5673 val = rtw89_read8(rtwdev, addr); 5674 rtw89_write8(rtwdev, addr, val | bit); 5675 } 5676 5677 static inline void 5678 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5679 { 5680 u16 val; 5681 5682 val = rtw89_read16(rtwdev, addr); 5683 rtw89_write16(rtwdev, addr, val | bit); 5684 } 5685 5686 static inline void 5687 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5688 { 5689 u32 val; 5690 5691 val = rtw89_read32(rtwdev, addr); 5692 rtw89_write32(rtwdev, addr, val | bit); 5693 } 5694 5695 static inline void 5696 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5697 { 5698 u8 val; 5699 5700 val = rtw89_read8(rtwdev, addr); 5701 rtw89_write8(rtwdev, addr, val & ~bit); 5702 } 5703 5704 static inline void 5705 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5706 { 5707 u16 val; 5708 5709 val = rtw89_read16(rtwdev, addr); 5710 rtw89_write16(rtwdev, addr, val & ~bit); 5711 } 5712 5713 static inline void 5714 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5715 { 5716 u32 val; 5717 5718 val = rtw89_read32(rtwdev, addr); 5719 rtw89_write32(rtwdev, addr, val & ~bit); 5720 } 5721 5722 static inline u32 5723 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5724 { 5725 u32 shift = __ffs(mask); 5726 u32 orig; 5727 u32 ret; 5728 5729 orig = rtw89_read32(rtwdev, addr); 5730 ret = (orig & mask) >> shift; 5731 5732 return ret; 5733 } 5734 5735 static inline u16 5736 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5737 { 5738 u32 shift = __ffs(mask); 5739 u32 orig; 5740 u32 ret; 5741 5742 orig = rtw89_read16(rtwdev, addr); 5743 ret = (orig & mask) >> shift; 5744 5745 return ret; 5746 } 5747 5748 static inline u8 5749 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5750 { 5751 u32 shift = __ffs(mask); 5752 u32 orig; 5753 u32 ret; 5754 5755 orig = rtw89_read8(rtwdev, addr); 5756 ret = (orig & mask) >> shift; 5757 5758 return ret; 5759 } 5760 5761 static inline void 5762 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5763 { 5764 u32 shift = __ffs(mask); 5765 u32 orig; 5766 u32 set; 5767 5768 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5769 5770 orig = rtw89_read32(rtwdev, addr); 5771 set = (orig & ~mask) | ((data << shift) & mask); 5772 rtw89_write32(rtwdev, addr, set); 5773 } 5774 5775 static inline void 5776 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5777 { 5778 u32 shift; 5779 u16 orig, set; 5780 5781 mask &= 0xffff; 5782 shift = __ffs(mask); 5783 5784 orig = rtw89_read16(rtwdev, addr); 5785 set = (orig & ~mask) | ((data << shift) & mask); 5786 rtw89_write16(rtwdev, addr, set); 5787 } 5788 5789 static inline void 5790 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5791 { 5792 u32 shift; 5793 u8 orig, set; 5794 5795 mask &= 0xff; 5796 shift = __ffs(mask); 5797 5798 orig = rtw89_read8(rtwdev, addr); 5799 set = (orig & ~mask) | ((data << shift) & mask); 5800 rtw89_write8(rtwdev, addr, set); 5801 } 5802 5803 static inline u32 5804 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5805 u32 addr, u32 mask) 5806 { 5807 u32 val; 5808 5809 mutex_lock(&rtwdev->rf_mutex); 5810 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5811 mutex_unlock(&rtwdev->rf_mutex); 5812 5813 return val; 5814 } 5815 5816 static inline void 5817 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5818 u32 addr, u32 mask, u32 data) 5819 { 5820 mutex_lock(&rtwdev->rf_mutex); 5821 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5822 mutex_unlock(&rtwdev->rf_mutex); 5823 } 5824 5825 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5826 { 5827 void *p = rtwtxq; 5828 5829 return container_of(p, struct ieee80211_txq, drv_priv); 5830 } 5831 5832 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5833 struct ieee80211_txq *txq) 5834 { 5835 struct rtw89_txq *rtwtxq; 5836 5837 if (!txq) 5838 return; 5839 5840 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5841 INIT_LIST_HEAD(&rtwtxq->list); 5842 } 5843 5844 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5845 { 5846 void *p = rtwvif; 5847 5848 return container_of(p, struct ieee80211_vif, drv_priv); 5849 } 5850 5851 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5852 { 5853 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5854 } 5855 5856 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5857 { 5858 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5859 } 5860 5861 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5862 { 5863 void *p = rtwsta; 5864 5865 return container_of(p, struct ieee80211_sta, drv_priv); 5866 } 5867 5868 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5869 { 5870 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5871 } 5872 5873 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5874 { 5875 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5876 } 5877 5878 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5879 { 5880 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5881 return RATE_INFO_BW_160; 5882 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5883 return RATE_INFO_BW_80; 5884 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5885 return RATE_INFO_BW_40; 5886 else 5887 return RATE_INFO_BW_20; 5888 } 5889 5890 static inline 5891 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5892 { 5893 switch (hw_band) { 5894 default: 5895 case RTW89_BAND_2G: 5896 return NL80211_BAND_2GHZ; 5897 case RTW89_BAND_5G: 5898 return NL80211_BAND_5GHZ; 5899 case RTW89_BAND_6G: 5900 return NL80211_BAND_6GHZ; 5901 } 5902 } 5903 5904 static inline 5905 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5906 { 5907 switch (nl_band) { 5908 default: 5909 case NL80211_BAND_2GHZ: 5910 return RTW89_BAND_2G; 5911 case NL80211_BAND_5GHZ: 5912 return RTW89_BAND_5G; 5913 case NL80211_BAND_6GHZ: 5914 return RTW89_BAND_6G; 5915 } 5916 } 5917 5918 static inline 5919 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5920 { 5921 switch (width) { 5922 default: 5923 WARN(1, "Not support bandwidth %d\n", width); 5924 fallthrough; 5925 case NL80211_CHAN_WIDTH_20_NOHT: 5926 case NL80211_CHAN_WIDTH_20: 5927 return RTW89_CHANNEL_WIDTH_20; 5928 case NL80211_CHAN_WIDTH_40: 5929 return RTW89_CHANNEL_WIDTH_40; 5930 case NL80211_CHAN_WIDTH_80: 5931 return RTW89_CHANNEL_WIDTH_80; 5932 case NL80211_CHAN_WIDTH_160: 5933 return RTW89_CHANNEL_WIDTH_160; 5934 } 5935 } 5936 5937 static inline 5938 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5939 { 5940 switch (rua) { 5941 default: 5942 WARN(1, "Invalid RU allocation: %d\n", rua); 5943 fallthrough; 5944 case 0 ... 36: 5945 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5946 case 37 ... 52: 5947 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5948 case 53 ... 60: 5949 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5950 case 61 ... 64: 5951 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5952 case 65 ... 66: 5953 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5954 case 67: 5955 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5956 case 68: 5957 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5958 } 5959 } 5960 5961 static inline 5962 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5963 struct rtw89_sta *rtwsta) 5964 { 5965 if (rtwsta) { 5966 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5967 5968 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5969 return &rtwsta->addr_cam; 5970 } 5971 return &rtwvif->addr_cam; 5972 } 5973 5974 static inline 5975 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5976 struct rtw89_sta *rtwsta) 5977 { 5978 if (rtwsta) { 5979 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5980 5981 if (sta->tdls) 5982 return &rtwsta->bssid_cam; 5983 } 5984 return &rtwvif->bssid_cam; 5985 } 5986 5987 static inline 5988 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5989 struct rtw89_channel_help_params *p, 5990 const struct rtw89_chan *chan, 5991 enum rtw89_mac_idx mac_idx, 5992 enum rtw89_phy_idx phy_idx) 5993 { 5994 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5995 mac_idx, phy_idx); 5996 } 5997 5998 static inline 5999 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6000 struct rtw89_channel_help_params *p, 6001 const struct rtw89_chan *chan, 6002 enum rtw89_mac_idx mac_idx, 6003 enum rtw89_phy_idx phy_idx) 6004 { 6005 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6006 mac_idx, phy_idx); 6007 } 6008 6009 static inline 6010 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6011 enum rtw89_sub_entity_idx idx) 6012 { 6013 struct rtw89_hal *hal = &rtwdev->hal; 6014 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 6015 6016 if (roc_idx == idx) 6017 return &hal->roc_chandef; 6018 6019 return &hal->sub[idx].chandef; 6020 } 6021 6022 static inline 6023 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6024 enum rtw89_sub_entity_idx idx) 6025 { 6026 struct rtw89_hal *hal = &rtwdev->hal; 6027 6028 return &hal->sub[idx].chan; 6029 } 6030 6031 static inline 6032 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6033 enum rtw89_sub_entity_idx idx) 6034 { 6035 struct rtw89_hal *hal = &rtwdev->hal; 6036 6037 return &hal->sub[idx].rcd; 6038 } 6039 6040 static inline 6041 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6042 { 6043 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 6044 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 6045 6046 if (rtwvif) 6047 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 6048 else 6049 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 6050 } 6051 6052 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6053 { 6054 const struct rtw89_chip_info *chip = rtwdev->chip; 6055 6056 if (chip->ops->fem_setup) 6057 chip->ops->fem_setup(rtwdev); 6058 } 6059 6060 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6061 { 6062 const struct rtw89_chip_info *chip = rtwdev->chip; 6063 6064 if (chip->ops->rfe_gpio) 6065 chip->ops->rfe_gpio(rtwdev); 6066 } 6067 6068 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6069 { 6070 const struct rtw89_chip_info *chip = rtwdev->chip; 6071 6072 if (chip->ops->rfk_hw_init) 6073 chip->ops->rfk_hw_init(rtwdev); 6074 } 6075 6076 static inline 6077 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6078 { 6079 const struct rtw89_chip_info *chip = rtwdev->chip; 6080 6081 if (chip->ops->bb_preinit) 6082 chip->ops->bb_preinit(rtwdev, phy_idx); 6083 } 6084 6085 static inline 6086 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6087 { 6088 const struct rtw89_chip_info *chip = rtwdev->chip; 6089 6090 if (!chip->ops->bb_postinit) 6091 return; 6092 6093 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6094 6095 if (rtwdev->dbcc_en) 6096 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6097 } 6098 6099 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6100 { 6101 const struct rtw89_chip_info *chip = rtwdev->chip; 6102 6103 if (chip->ops->bb_sethw) 6104 chip->ops->bb_sethw(rtwdev); 6105 } 6106 6107 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6108 { 6109 const struct rtw89_chip_info *chip = rtwdev->chip; 6110 6111 if (chip->ops->rfk_init) 6112 chip->ops->rfk_init(rtwdev); 6113 } 6114 6115 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6116 { 6117 const struct rtw89_chip_info *chip = rtwdev->chip; 6118 6119 if (chip->ops->rfk_init_late) 6120 chip->ops->rfk_init_late(rtwdev); 6121 } 6122 6123 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 6124 { 6125 const struct rtw89_chip_info *chip = rtwdev->chip; 6126 6127 if (chip->ops->rfk_channel) 6128 chip->ops->rfk_channel(rtwdev); 6129 } 6130 6131 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6132 enum rtw89_phy_idx phy_idx) 6133 { 6134 const struct rtw89_chip_info *chip = rtwdev->chip; 6135 6136 if (chip->ops->rfk_band_changed) 6137 chip->ops->rfk_band_changed(rtwdev, phy_idx); 6138 } 6139 6140 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 6141 { 6142 const struct rtw89_chip_info *chip = rtwdev->chip; 6143 6144 if (chip->ops->rfk_scan) 6145 chip->ops->rfk_scan(rtwdev, start); 6146 } 6147 6148 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6149 { 6150 const struct rtw89_chip_info *chip = rtwdev->chip; 6151 6152 if (chip->ops->rfk_track) 6153 chip->ops->rfk_track(rtwdev); 6154 } 6155 6156 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6157 { 6158 const struct rtw89_chip_info *chip = rtwdev->chip; 6159 6160 if (chip->ops->set_txpwr_ctrl) 6161 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6162 } 6163 6164 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6165 { 6166 const struct rtw89_chip_info *chip = rtwdev->chip; 6167 6168 if (chip->ops->power_trim) 6169 chip->ops->power_trim(rtwdev); 6170 } 6171 6172 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6173 enum rtw89_phy_idx phy_idx) 6174 { 6175 const struct rtw89_chip_info *chip = rtwdev->chip; 6176 6177 if (chip->ops->init_txpwr_unit) 6178 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6179 } 6180 6181 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6182 enum rtw89_rf_path rf_path) 6183 { 6184 const struct rtw89_chip_info *chip = rtwdev->chip; 6185 6186 if (!chip->ops->get_thermal) 6187 return 0x10; 6188 6189 return chip->ops->get_thermal(rtwdev, rf_path); 6190 } 6191 6192 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6193 struct rtw89_rx_phy_ppdu *phy_ppdu, 6194 struct ieee80211_rx_status *status) 6195 { 6196 const struct rtw89_chip_info *chip = rtwdev->chip; 6197 6198 if (chip->ops->query_ppdu) 6199 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6200 } 6201 6202 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6203 enum rtw89_phy_idx phy_idx) 6204 { 6205 const struct rtw89_chip_info *chip = rtwdev->chip; 6206 6207 if (chip->ops->ctrl_nbtg_bt_tx) 6208 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6209 } 6210 6211 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6212 { 6213 const struct rtw89_chip_info *chip = rtwdev->chip; 6214 6215 if (chip->ops->cfg_txrx_path) 6216 chip->ops->cfg_txrx_path(rtwdev); 6217 } 6218 6219 static inline 6220 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 6221 struct ieee80211_vif *vif) 6222 { 6223 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6224 const struct rtw89_chip_info *chip = rtwdev->chip; 6225 6226 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 6227 return; 6228 6229 if (chip->ops->set_txpwr_ul_tb_offset) 6230 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 6231 } 6232 6233 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6234 const struct rtw89_txpwr_table *tbl) 6235 { 6236 tbl->load(rtwdev, tbl); 6237 } 6238 6239 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6240 { 6241 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6242 6243 return regd->txpwr_regd[band]; 6244 } 6245 6246 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6247 enum rtw89_phy_idx phy_idx) 6248 { 6249 const struct rtw89_chip_info *chip = rtwdev->chip; 6250 6251 if (chip->ops->ctrl_btg_bt_rx) 6252 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6253 } 6254 6255 static inline 6256 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6257 struct rtw89_rx_desc_info *desc_info, 6258 u8 *data, u32 data_offset) 6259 { 6260 const struct rtw89_chip_info *chip = rtwdev->chip; 6261 6262 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6263 } 6264 6265 static inline 6266 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6267 struct rtw89_tx_desc_info *desc_info, 6268 void *txdesc) 6269 { 6270 const struct rtw89_chip_info *chip = rtwdev->chip; 6271 6272 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6273 } 6274 6275 static inline 6276 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6277 struct rtw89_tx_desc_info *desc_info, 6278 void *txdesc) 6279 { 6280 const struct rtw89_chip_info *chip = rtwdev->chip; 6281 6282 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6283 } 6284 6285 static inline 6286 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6287 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6288 { 6289 const struct rtw89_chip_info *chip = rtwdev->chip; 6290 6291 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6292 } 6293 6294 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6295 { 6296 const struct rtw89_chip_info *chip = rtwdev->chip; 6297 6298 chip->ops->cfg_ctrl_path(rtwdev, wl); 6299 } 6300 6301 static inline 6302 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6303 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6304 { 6305 const struct rtw89_chip_info *chip = rtwdev->chip; 6306 6307 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6308 } 6309 6310 static inline 6311 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6312 { 6313 const struct rtw89_chip_info *chip = rtwdev->chip; 6314 6315 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6316 } 6317 6318 static inline 6319 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6320 struct rtw89_vif *rtwvif, 6321 struct rtw89_sta *rtwsta) 6322 { 6323 const struct rtw89_chip_info *chip = rtwdev->chip; 6324 6325 if (!chip->ops->h2c_dctl_sec_cam) 6326 return 0; 6327 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 6328 } 6329 6330 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6331 { 6332 __le16 fc = hdr->frame_control; 6333 6334 if (ieee80211_has_tods(fc)) 6335 return hdr->addr1; 6336 else if (ieee80211_has_fromds(fc)) 6337 return hdr->addr2; 6338 else 6339 return hdr->addr3; 6340 } 6341 6342 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 6343 { 6344 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6345 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6346 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 6347 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6348 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 6349 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6350 return true; 6351 return false; 6352 } 6353 6354 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6355 enum rtw89_fw_type type) 6356 { 6357 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6358 6359 switch (type) { 6360 case RTW89_FW_WOWLAN: 6361 return &fw_info->wowlan; 6362 case RTW89_FW_LOGFMT: 6363 return &fw_info->log.suit; 6364 case RTW89_FW_BBMCU0: 6365 return &fw_info->bbmcu0; 6366 case RTW89_FW_BBMCU1: 6367 return &fw_info->bbmcu1; 6368 default: 6369 break; 6370 } 6371 6372 return &fw_info->normal; 6373 } 6374 6375 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6376 unsigned int length) 6377 { 6378 struct sk_buff *skb; 6379 6380 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6381 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6382 if (!skb) 6383 return NULL; 6384 6385 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6386 return skb; 6387 } 6388 6389 return dev_alloc_skb(length); 6390 } 6391 6392 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6393 struct rtw89_tx_skb_data *skb_data, 6394 bool tx_done) 6395 { 6396 struct rtw89_tx_wait_info *wait; 6397 6398 rcu_read_lock(); 6399 6400 wait = rcu_dereference(skb_data->wait); 6401 if (!wait) 6402 goto out; 6403 6404 wait->tx_done = tx_done; 6405 complete(&wait->completion); 6406 6407 out: 6408 rcu_read_unlock(); 6409 } 6410 6411 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6412 { 6413 switch (rtwdev->mlo_dbcc_mode) { 6414 case MLO_1_PLUS_1_1RF: 6415 case MLO_1_PLUS_1_2RF: 6416 case DBCC_LEGACY: 6417 return true; 6418 default: 6419 return false; 6420 } 6421 } 6422 6423 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6424 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6425 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6426 struct sk_buff *skb, bool fwdl); 6427 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6428 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6429 int qsel, unsigned int timeout); 6430 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6431 struct rtw89_tx_desc_info *desc_info, 6432 void *txdesc); 6433 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6434 struct rtw89_tx_desc_info *desc_info, 6435 void *txdesc); 6436 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6437 struct rtw89_tx_desc_info *desc_info, 6438 void *txdesc); 6439 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6440 struct rtw89_tx_desc_info *desc_info, 6441 void *txdesc); 6442 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6443 struct rtw89_tx_desc_info *desc_info, 6444 void *txdesc); 6445 void rtw89_core_rx(struct rtw89_dev *rtwdev, 6446 struct rtw89_rx_desc_info *desc_info, 6447 struct sk_buff *skb); 6448 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 6449 struct rtw89_rx_desc_info *desc_info, 6450 u8 *data, u32 data_offset); 6451 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 6452 struct rtw89_rx_desc_info *desc_info, 6453 u8 *data, u32 data_offset); 6454 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 6455 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 6456 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 6457 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 6458 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 6459 struct ieee80211_vif *vif, 6460 struct ieee80211_sta *sta); 6461 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 6462 struct ieee80211_vif *vif, 6463 struct ieee80211_sta *sta); 6464 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 6465 struct ieee80211_vif *vif, 6466 struct ieee80211_sta *sta); 6467 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 6468 struct ieee80211_vif *vif, 6469 struct ieee80211_sta *sta); 6470 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 6471 struct ieee80211_vif *vif, 6472 struct ieee80211_sta *sta); 6473 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6474 struct ieee80211_sta *sta, 6475 struct cfg80211_tid_config *tid_config); 6476 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 6477 int rtw89_core_init(struct rtw89_dev *rtwdev); 6478 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 6479 int rtw89_core_register(struct rtw89_dev *rtwdev); 6480 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 6481 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6482 u32 bus_data_size, 6483 const struct rtw89_chip_info *chip); 6484 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 6485 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 6486 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 6487 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 6488 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 6489 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 6490 struct rtw89_chan *chan); 6491 int rtw89_set_channel(struct rtw89_dev *rtwdev); 6492 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6493 struct rtw89_chan *chan); 6494 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 6495 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 6496 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 6497 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 6498 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6499 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 6500 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6501 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 6502 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 6503 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 6504 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 6505 int rtw89_regd_init(struct rtw89_dev *rtwdev, 6506 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 6507 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 6508 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 6509 struct rtw89_traffic_stats *stats); 6510 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 6511 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6512 const struct rtw89_completion_data *data); 6513 int rtw89_core_start(struct rtw89_dev *rtwdev); 6514 void rtw89_core_stop(struct rtw89_dev *rtwdev); 6515 void rtw89_core_update_beacon_work(struct work_struct *work); 6516 void rtw89_roc_work(struct work_struct *work); 6517 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6518 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6519 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6520 const u8 *mac_addr, bool hw_scan); 6521 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6522 struct ieee80211_vif *vif, bool hw_scan); 6523 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 6524 struct rtw89_vif *rtwvif, bool active); 6525 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 6526 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 6527 6528 #endif 6529