1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 33 #define CFO_TRACK_MAX_USER 64 34 #define MAX_RSSI 110 35 #define RSSI_FACTOR 1 36 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 37 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 38 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64) 39 40 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 41 #define RTW89_HTC_VARIANT_HE 3 42 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 43 #define RTW89_HTC_VARIANT_HE_CID_OM 1 44 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 45 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 46 47 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 48 enum htc_om_channel_width { 49 HTC_OM_CHANNEL_WIDTH_20 = 0, 50 HTC_OM_CHANNEL_WIDTH_40 = 1, 51 HTC_OM_CHANNEL_WIDTH_80 = 2, 52 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 53 }; 54 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 55 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 56 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 57 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 58 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 59 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 60 61 #define RTW89_TF_PAD GENMASK(11, 0) 62 #define RTW89_TF_BASIC_USER_INFO_SZ 6 63 64 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 65 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 66 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 67 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 68 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 69 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 70 71 enum rtw89_subband { 72 RTW89_CH_2G = 0, 73 RTW89_CH_5G_BAND_1 = 1, 74 /* RTW89_CH_5G_BAND_2 = 2, unused */ 75 RTW89_CH_5G_BAND_3 = 3, 76 RTW89_CH_5G_BAND_4 = 4, 77 78 RTW89_CH_6G_BAND_IDX0, /* Low */ 79 RTW89_CH_6G_BAND_IDX1, /* Low */ 80 RTW89_CH_6G_BAND_IDX2, /* Mid */ 81 RTW89_CH_6G_BAND_IDX3, /* Mid */ 82 RTW89_CH_6G_BAND_IDX4, /* High */ 83 RTW89_CH_6G_BAND_IDX5, /* High */ 84 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 85 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 86 87 RTW89_SUBBAND_NR, 88 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 89 }; 90 91 enum rtw89_gain_offset { 92 RTW89_GAIN_OFFSET_2G_CCK, 93 RTW89_GAIN_OFFSET_2G_OFDM, 94 RTW89_GAIN_OFFSET_5G_LOW, 95 RTW89_GAIN_OFFSET_5G_MID, 96 RTW89_GAIN_OFFSET_5G_HIGH, 97 98 RTW89_GAIN_OFFSET_NR, 99 }; 100 101 enum rtw89_hci_type { 102 RTW89_HCI_TYPE_PCIE, 103 RTW89_HCI_TYPE_USB, 104 RTW89_HCI_TYPE_SDIO, 105 }; 106 107 enum rtw89_core_chip_id { 108 RTL8852A, 109 RTL8852B, 110 RTL8852C, 111 RTL8851B, 112 }; 113 114 enum rtw89_cv { 115 CHIP_CAV, 116 CHIP_CBV, 117 CHIP_CCV, 118 CHIP_CDV, 119 CHIP_CEV, 120 CHIP_CFV, 121 CHIP_CV_MAX, 122 CHIP_CV_INVALID = CHIP_CV_MAX, 123 }; 124 125 enum rtw89_bacam_ver { 126 RTW89_BACAM_V0, 127 RTW89_BACAM_V1, 128 129 RTW89_BACAM_V0_EXT = 99, 130 }; 131 132 enum rtw89_core_tx_type { 133 RTW89_CORE_TX_TYPE_DATA, 134 RTW89_CORE_TX_TYPE_MGMT, 135 RTW89_CORE_TX_TYPE_FWCMD, 136 }; 137 138 enum rtw89_core_rx_type { 139 RTW89_CORE_RX_TYPE_WIFI = 0, 140 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 141 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 142 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 143 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 144 RTW89_CORE_RX_TYPE_SS2FW = 5, 145 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 146 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 147 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 148 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 149 RTW89_CORE_RX_TYPE_C2H = 10, 150 RTW89_CORE_RX_TYPE_CSI = 11, 151 RTW89_CORE_RX_TYPE_CQI = 12, 152 RTW89_CORE_RX_TYPE_H2C = 13, 153 RTW89_CORE_RX_TYPE_FWDL = 14, 154 }; 155 156 enum rtw89_txq_flags { 157 RTW89_TXQ_F_AMPDU = 0, 158 RTW89_TXQ_F_BLOCK_BA = 1, 159 RTW89_TXQ_F_FORBID_BA = 2, 160 }; 161 162 enum rtw89_net_type { 163 RTW89_NET_TYPE_NO_LINK = 0, 164 RTW89_NET_TYPE_AD_HOC = 1, 165 RTW89_NET_TYPE_INFRA = 2, 166 RTW89_NET_TYPE_AP_MODE = 3, 167 }; 168 169 enum rtw89_wifi_role { 170 RTW89_WIFI_ROLE_NONE, 171 RTW89_WIFI_ROLE_STATION, 172 RTW89_WIFI_ROLE_AP, 173 RTW89_WIFI_ROLE_AP_VLAN, 174 RTW89_WIFI_ROLE_ADHOC, 175 RTW89_WIFI_ROLE_ADHOC_MASTER, 176 RTW89_WIFI_ROLE_MESH_POINT, 177 RTW89_WIFI_ROLE_MONITOR, 178 RTW89_WIFI_ROLE_P2P_DEVICE, 179 RTW89_WIFI_ROLE_P2P_CLIENT, 180 RTW89_WIFI_ROLE_P2P_GO, 181 RTW89_WIFI_ROLE_NAN, 182 RTW89_WIFI_ROLE_MLME_MAX 183 }; 184 185 enum rtw89_upd_mode { 186 RTW89_ROLE_CREATE, 187 RTW89_ROLE_REMOVE, 188 RTW89_ROLE_TYPE_CHANGE, 189 RTW89_ROLE_INFO_CHANGE, 190 RTW89_ROLE_CON_DISCONN, 191 RTW89_ROLE_BAND_SW, 192 RTW89_ROLE_FW_RESTORE, 193 }; 194 195 enum rtw89_self_role { 196 RTW89_SELF_ROLE_CLIENT, 197 RTW89_SELF_ROLE_AP, 198 RTW89_SELF_ROLE_AP_CLIENT 199 }; 200 201 enum rtw89_msk_sO_el { 202 RTW89_NO_MSK, 203 RTW89_SMA, 204 RTW89_TMA, 205 RTW89_BSSID 206 }; 207 208 enum rtw89_sch_tx_sel { 209 RTW89_SCH_TX_SEL_ALL, 210 RTW89_SCH_TX_SEL_HIQ, 211 RTW89_SCH_TX_SEL_MG0, 212 RTW89_SCH_TX_SEL_MACID, 213 }; 214 215 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 216 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 217 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 218 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 219 */ 220 enum rtw89_add_cam_sec_mode { 221 RTW89_ADDR_CAM_SEC_NONE = 0, 222 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 223 RTW89_ADDR_CAM_SEC_NORMAL = 2, 224 RTW89_ADDR_CAM_SEC_4GROUP = 3, 225 }; 226 227 enum rtw89_sec_key_type { 228 RTW89_SEC_KEY_TYPE_NONE = 0, 229 RTW89_SEC_KEY_TYPE_WEP40 = 1, 230 RTW89_SEC_KEY_TYPE_WEP104 = 2, 231 RTW89_SEC_KEY_TYPE_TKIP = 3, 232 RTW89_SEC_KEY_TYPE_WAPI = 4, 233 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 234 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 235 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 236 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 237 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 238 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 239 }; 240 241 enum rtw89_port { 242 RTW89_PORT_0 = 0, 243 RTW89_PORT_1 = 1, 244 RTW89_PORT_2 = 2, 245 RTW89_PORT_3 = 3, 246 RTW89_PORT_4 = 4, 247 RTW89_PORT_NUM 248 }; 249 250 enum rtw89_band { 251 RTW89_BAND_2G = 0, 252 RTW89_BAND_5G = 1, 253 RTW89_BAND_6G = 2, 254 RTW89_BAND_MAX, 255 }; 256 257 enum rtw89_hw_rate { 258 RTW89_HW_RATE_CCK1 = 0x0, 259 RTW89_HW_RATE_CCK2 = 0x1, 260 RTW89_HW_RATE_CCK5_5 = 0x2, 261 RTW89_HW_RATE_CCK11 = 0x3, 262 RTW89_HW_RATE_OFDM6 = 0x4, 263 RTW89_HW_RATE_OFDM9 = 0x5, 264 RTW89_HW_RATE_OFDM12 = 0x6, 265 RTW89_HW_RATE_OFDM18 = 0x7, 266 RTW89_HW_RATE_OFDM24 = 0x8, 267 RTW89_HW_RATE_OFDM36 = 0x9, 268 RTW89_HW_RATE_OFDM48 = 0xA, 269 RTW89_HW_RATE_OFDM54 = 0xB, 270 RTW89_HW_RATE_MCS0 = 0x80, 271 RTW89_HW_RATE_MCS1 = 0x81, 272 RTW89_HW_RATE_MCS2 = 0x82, 273 RTW89_HW_RATE_MCS3 = 0x83, 274 RTW89_HW_RATE_MCS4 = 0x84, 275 RTW89_HW_RATE_MCS5 = 0x85, 276 RTW89_HW_RATE_MCS6 = 0x86, 277 RTW89_HW_RATE_MCS7 = 0x87, 278 RTW89_HW_RATE_MCS8 = 0x88, 279 RTW89_HW_RATE_MCS9 = 0x89, 280 RTW89_HW_RATE_MCS10 = 0x8A, 281 RTW89_HW_RATE_MCS11 = 0x8B, 282 RTW89_HW_RATE_MCS12 = 0x8C, 283 RTW89_HW_RATE_MCS13 = 0x8D, 284 RTW89_HW_RATE_MCS14 = 0x8E, 285 RTW89_HW_RATE_MCS15 = 0x8F, 286 RTW89_HW_RATE_MCS16 = 0x90, 287 RTW89_HW_RATE_MCS17 = 0x91, 288 RTW89_HW_RATE_MCS18 = 0x92, 289 RTW89_HW_RATE_MCS19 = 0x93, 290 RTW89_HW_RATE_MCS20 = 0x94, 291 RTW89_HW_RATE_MCS21 = 0x95, 292 RTW89_HW_RATE_MCS22 = 0x96, 293 RTW89_HW_RATE_MCS23 = 0x97, 294 RTW89_HW_RATE_MCS24 = 0x98, 295 RTW89_HW_RATE_MCS25 = 0x99, 296 RTW89_HW_RATE_MCS26 = 0x9A, 297 RTW89_HW_RATE_MCS27 = 0x9B, 298 RTW89_HW_RATE_MCS28 = 0x9C, 299 RTW89_HW_RATE_MCS29 = 0x9D, 300 RTW89_HW_RATE_MCS30 = 0x9E, 301 RTW89_HW_RATE_MCS31 = 0x9F, 302 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 303 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 304 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 305 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 306 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 307 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 308 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 309 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 310 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 311 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 312 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 313 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 314 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 315 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 316 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 317 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 318 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 319 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 320 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 321 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 322 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 323 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 324 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 325 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 326 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 327 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 328 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 329 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 330 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 331 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 332 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 333 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 334 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 335 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 336 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 337 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 338 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 339 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 340 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 341 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 342 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 343 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 344 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 345 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 346 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 347 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 348 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 349 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 350 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 351 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 352 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 353 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 354 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 355 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 356 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 357 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 358 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 359 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 360 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 361 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 362 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 363 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 364 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 365 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 366 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 367 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 368 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 369 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 370 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 371 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 372 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 373 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 374 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 375 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 376 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 377 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 378 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 379 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 380 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 381 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 382 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 383 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 384 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 385 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 386 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 387 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 388 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 389 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 390 RTW89_HW_RATE_NR, 391 392 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 393 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 394 }; 395 396 /* 2G channels, 397 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 398 */ 399 #define RTW89_2G_CH_NUM 14 400 401 /* 5G channels, 402 * 36, 38, 40, 42, 44, 46, 48, 50, 403 * 52, 54, 56, 58, 60, 62, 64, 404 * 100, 102, 104, 106, 108, 110, 112, 114, 405 * 116, 118, 120, 122, 124, 126, 128, 130, 406 * 132, 134, 136, 138, 140, 142, 144, 407 * 149, 151, 153, 155, 157, 159, 161, 163, 408 * 165, 167, 169, 171, 173, 175, 177 409 */ 410 #define RTW89_5G_CH_NUM 53 411 412 /* 6G channels, 413 * 1, 3, 5, 7, 9, 11, 13, 15, 414 * 17, 19, 21, 23, 25, 27, 29, 33, 415 * 35, 37, 39, 41, 43, 45, 47, 49, 416 * 51, 53, 55, 57, 59, 61, 65, 67, 417 * 69, 71, 73, 75, 77, 79, 81, 83, 418 * 85, 87, 89, 91, 93, 97, 99, 101, 419 * 103, 105, 107, 109, 111, 113, 115, 117, 420 * 119, 121, 123, 125, 129, 131, 133, 135, 421 * 137, 139, 141, 143, 145, 147, 149, 151, 422 * 153, 155, 157, 161, 163, 165, 167, 169, 423 * 171, 173, 175, 177, 179, 181, 183, 185, 424 * 187, 189, 193, 195, 197, 199, 201, 203, 425 * 205, 207, 209, 211, 213, 215, 217, 219, 426 * 221, 225, 227, 229, 231, 233, 235, 237, 427 * 239, 241, 243, 245, 247, 249, 251, 253, 428 */ 429 #define RTW89_6G_CH_NUM 120 430 431 enum rtw89_rate_section { 432 RTW89_RS_CCK, 433 RTW89_RS_OFDM, 434 RTW89_RS_MCS, /* for HT/VHT/HE */ 435 RTW89_RS_HEDCM, 436 RTW89_RS_OFFSET, 437 RTW89_RS_MAX, 438 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 439 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 440 }; 441 442 enum rtw89_rate_max { 443 RTW89_RATE_CCK_MAX = 4, 444 RTW89_RATE_OFDM_MAX = 8, 445 RTW89_RATE_MCS_MAX = 12, 446 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 447 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 448 }; 449 450 enum rtw89_nss { 451 RTW89_NSS_1 = 0, 452 RTW89_NSS_2 = 1, 453 /* HE DCM only support 1ss and 2ss */ 454 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 455 RTW89_NSS_3 = 2, 456 RTW89_NSS_4 = 3, 457 RTW89_NSS_MAX, 458 }; 459 460 enum rtw89_ntx { 461 RTW89_1TX = 0, 462 RTW89_2TX = 1, 463 RTW89_NTX_NUM, 464 }; 465 466 enum rtw89_beamforming_type { 467 RTW89_NONBF = 0, 468 RTW89_BF = 1, 469 RTW89_BF_NUM, 470 }; 471 472 enum rtw89_regulation_type { 473 RTW89_WW = 0, 474 RTW89_ETSI = 1, 475 RTW89_FCC = 2, 476 RTW89_MKK = 3, 477 RTW89_NA = 4, 478 RTW89_IC = 5, 479 RTW89_KCC = 6, 480 RTW89_ACMA = 7, 481 RTW89_NCC = 8, 482 RTW89_MEXICO = 9, 483 RTW89_CHILE = 10, 484 RTW89_UKRAINE = 11, 485 RTW89_CN = 12, 486 RTW89_QATAR = 13, 487 RTW89_UK = 14, 488 RTW89_REGD_NUM, 489 }; 490 491 enum rtw89_reg_6ghz_power { 492 RTW89_REG_6GHZ_POWER_VLP = 0, 493 RTW89_REG_6GHZ_POWER_LPI = 1, 494 RTW89_REG_6GHZ_POWER_STD = 2, 495 496 NUM_OF_RTW89_REG_6GHZ_POWER, 497 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 498 }; 499 500 enum rtw89_fw_pkt_ofld_type { 501 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 502 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 503 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 504 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 505 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 506 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 507 RTW89_PKT_OFLD_TYPE_NDP = 6, 508 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 509 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 510 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 511 RTW89_PKT_OFLD_TYPE_NUM, 512 }; 513 514 struct rtw89_txpwr_byrate { 515 s8 cck[RTW89_RATE_CCK_MAX]; 516 s8 ofdm[RTW89_RATE_OFDM_MAX]; 517 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 518 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 519 s8 offset[RTW89_RATE_OFFSET_MAX]; 520 }; 521 522 enum rtw89_bandwidth_section_num { 523 RTW89_BW20_SEC_NUM = 8, 524 RTW89_BW40_SEC_NUM = 4, 525 RTW89_BW80_SEC_NUM = 2, 526 }; 527 528 #define RTW89_TXPWR_LMT_PAGE_SIZE 40 529 530 struct rtw89_txpwr_limit { 531 s8 cck_20m[RTW89_BF_NUM]; 532 s8 cck_40m[RTW89_BF_NUM]; 533 s8 ofdm[RTW89_BF_NUM]; 534 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 535 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 536 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 537 s8 mcs_160m[RTW89_BF_NUM]; 538 s8 mcs_40m_0p5[RTW89_BF_NUM]; 539 s8 mcs_40m_2p5[RTW89_BF_NUM]; 540 }; 541 542 #define RTW89_RU_SEC_NUM 8 543 544 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE 24 545 546 struct rtw89_txpwr_limit_ru { 547 s8 ru26[RTW89_RU_SEC_NUM]; 548 s8 ru52[RTW89_RU_SEC_NUM]; 549 s8 ru106[RTW89_RU_SEC_NUM]; 550 }; 551 552 struct rtw89_rate_desc { 553 enum rtw89_nss nss; 554 enum rtw89_rate_section rs; 555 u8 idx; 556 }; 557 558 #define PHY_STS_HDR_LEN 8 559 #define RF_PATH_MAX 4 560 #define RTW89_MAX_PPDU_CNT 8 561 struct rtw89_rx_phy_ppdu { 562 void *buf; 563 u32 len; 564 u8 rssi_avg; 565 u8 rssi[RF_PATH_MAX]; 566 u8 mac_id; 567 u8 chan_idx; 568 u8 ie; 569 u16 rate; 570 struct { 571 bool has; 572 u8 avg_snr; 573 u8 evm_max; 574 u8 evm_min; 575 } ofdm; 576 bool to_self; 577 bool valid; 578 }; 579 580 enum rtw89_mac_idx { 581 RTW89_MAC_0 = 0, 582 RTW89_MAC_1 = 1, 583 }; 584 585 enum rtw89_phy_idx { 586 RTW89_PHY_0 = 0, 587 RTW89_PHY_1 = 1, 588 RTW89_PHY_MAX 589 }; 590 591 enum rtw89_sub_entity_idx { 592 RTW89_SUB_ENTITY_0 = 0, 593 594 NUM_OF_RTW89_SUB_ENTITY, 595 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 596 }; 597 598 enum rtw89_rf_path { 599 RF_PATH_A = 0, 600 RF_PATH_B = 1, 601 RF_PATH_C = 2, 602 RF_PATH_D = 3, 603 RF_PATH_AB, 604 RF_PATH_AC, 605 RF_PATH_AD, 606 RF_PATH_BC, 607 RF_PATH_BD, 608 RF_PATH_CD, 609 RF_PATH_ABC, 610 RF_PATH_ABD, 611 RF_PATH_ACD, 612 RF_PATH_BCD, 613 RF_PATH_ABCD, 614 }; 615 616 enum rtw89_rf_path_bit { 617 RF_A = BIT(0), 618 RF_B = BIT(1), 619 RF_C = BIT(2), 620 RF_D = BIT(3), 621 622 RF_AB = (RF_A | RF_B), 623 RF_AC = (RF_A | RF_C), 624 RF_AD = (RF_A | RF_D), 625 RF_BC = (RF_B | RF_C), 626 RF_BD = (RF_B | RF_D), 627 RF_CD = (RF_C | RF_D), 628 629 RF_ABC = (RF_A | RF_B | RF_C), 630 RF_ABD = (RF_A | RF_B | RF_D), 631 RF_ACD = (RF_A | RF_C | RF_D), 632 RF_BCD = (RF_B | RF_C | RF_D), 633 634 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 635 }; 636 637 enum rtw89_bandwidth { 638 RTW89_CHANNEL_WIDTH_20 = 0, 639 RTW89_CHANNEL_WIDTH_40 = 1, 640 RTW89_CHANNEL_WIDTH_80 = 2, 641 RTW89_CHANNEL_WIDTH_160 = 3, 642 RTW89_CHANNEL_WIDTH_80_80 = 4, 643 RTW89_CHANNEL_WIDTH_5 = 5, 644 RTW89_CHANNEL_WIDTH_10 = 6, 645 }; 646 647 enum rtw89_ps_mode { 648 RTW89_PS_MODE_NONE = 0, 649 RTW89_PS_MODE_RFOFF = 1, 650 RTW89_PS_MODE_CLK_GATED = 2, 651 RTW89_PS_MODE_PWR_GATED = 3, 652 }; 653 654 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 655 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 656 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 657 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 658 659 enum rtw89_ru_bandwidth { 660 RTW89_RU26 = 0, 661 RTW89_RU52 = 1, 662 RTW89_RU106 = 2, 663 RTW89_RU_NUM, 664 }; 665 666 enum rtw89_sc_offset { 667 RTW89_SC_DONT_CARE = 0, 668 RTW89_SC_20_UPPER = 1, 669 RTW89_SC_20_LOWER = 2, 670 RTW89_SC_20_UPMOST = 3, 671 RTW89_SC_20_LOWEST = 4, 672 RTW89_SC_20_UP2X = 5, 673 RTW89_SC_20_LOW2X = 6, 674 RTW89_SC_20_UP3X = 7, 675 RTW89_SC_20_LOW3X = 8, 676 RTW89_SC_40_UPPER = 9, 677 RTW89_SC_40_LOWER = 10, 678 }; 679 680 enum rtw89_wow_flags { 681 RTW89_WOW_FLAG_EN_MAGIC_PKT, 682 RTW89_WOW_FLAG_EN_REKEY_PKT, 683 RTW89_WOW_FLAG_EN_DISCONNECT, 684 RTW89_WOW_FLAG_NUM, 685 }; 686 687 struct rtw89_chan { 688 u8 channel; 689 u8 primary_channel; 690 enum rtw89_band band_type; 691 enum rtw89_bandwidth band_width; 692 693 /* The follow-up are derived from the above. We must ensure that it 694 * is assigned correctly in rtw89_chan_create() if new one is added. 695 */ 696 u32 freq; 697 enum rtw89_subband subband_type; 698 enum rtw89_sc_offset pri_ch_idx; 699 }; 700 701 struct rtw89_chan_rcd { 702 u8 prev_primary_channel; 703 enum rtw89_band prev_band_type; 704 }; 705 706 struct rtw89_channel_help_params { 707 u32 tx_en; 708 }; 709 710 struct rtw89_port_reg { 711 u32 port_cfg; 712 u32 tbtt_prohib; 713 u32 bcn_area; 714 u32 bcn_early; 715 u32 tbtt_early; 716 u32 tbtt_agg; 717 u32 bcn_space; 718 u32 bcn_forcetx; 719 u32 bcn_err_cnt; 720 u32 bcn_err_flag; 721 u32 dtim_ctrl; 722 u32 tbtt_shift; 723 u32 bcn_cnt_tmr; 724 u32 tsftr_l; 725 u32 tsftr_h; 726 }; 727 728 struct rtw89_txwd_body { 729 __le32 dword0; 730 __le32 dword1; 731 __le32 dword2; 732 __le32 dword3; 733 __le32 dword4; 734 __le32 dword5; 735 } __packed; 736 737 struct rtw89_txwd_body_v1 { 738 __le32 dword0; 739 __le32 dword1; 740 __le32 dword2; 741 __le32 dword3; 742 __le32 dword4; 743 __le32 dword5; 744 __le32 dword6; 745 __le32 dword7; 746 } __packed; 747 748 struct rtw89_txwd_info { 749 __le32 dword0; 750 __le32 dword1; 751 __le32 dword2; 752 __le32 dword3; 753 __le32 dword4; 754 __le32 dword5; 755 } __packed; 756 757 struct rtw89_rx_desc_info { 758 u16 pkt_size; 759 u8 pkt_type; 760 u8 drv_info_size; 761 u8 shift; 762 u8 wl_hd_iv_len; 763 bool long_rxdesc; 764 bool bb_sel; 765 bool mac_info_valid; 766 u16 data_rate; 767 u8 gi_ltf; 768 u8 bw; 769 u32 free_run_cnt; 770 u8 user_id; 771 bool sr_en; 772 u8 ppdu_cnt; 773 u8 ppdu_type; 774 bool icv_err; 775 bool crc32_err; 776 bool hw_dec; 777 bool sw_dec; 778 bool addr1_match; 779 u8 frag; 780 u16 seq; 781 u8 frame_type; 782 u8 rx_pl_id; 783 bool addr_cam_valid; 784 u8 addr_cam_id; 785 u8 sec_cam_id; 786 u8 mac_id; 787 u16 offset; 788 u16 rxd_len; 789 bool ready; 790 }; 791 792 struct rtw89_rxdesc_short { 793 __le32 dword0; 794 __le32 dword1; 795 __le32 dword2; 796 __le32 dword3; 797 } __packed; 798 799 struct rtw89_rxdesc_long { 800 __le32 dword0; 801 __le32 dword1; 802 __le32 dword2; 803 __le32 dword3; 804 __le32 dword4; 805 __le32 dword5; 806 __le32 dword6; 807 __le32 dword7; 808 } __packed; 809 810 struct rtw89_tx_desc_info { 811 u16 pkt_size; 812 u8 wp_offset; 813 u8 mac_id; 814 u8 qsel; 815 u8 ch_dma; 816 u8 hdr_llc_len; 817 bool is_bmc; 818 bool en_wd_info; 819 bool wd_page; 820 bool use_rate; 821 bool dis_data_fb; 822 bool tid_indicate; 823 bool agg_en; 824 bool bk; 825 u8 ampdu_density; 826 u8 ampdu_num; 827 bool sec_en; 828 u8 addr_info_nr; 829 u8 sec_keyid; 830 u8 sec_type; 831 u8 sec_cam_idx; 832 u8 sec_seq[6]; 833 u16 data_rate; 834 u16 data_retry_lowest_rate; 835 bool fw_dl; 836 u16 seq; 837 bool a_ctrl_bsr; 838 u8 hw_ssn_sel; 839 #define RTW89_MGMT_HW_SSN_SEL 1 840 u8 hw_seq_mode; 841 #define RTW89_MGMT_HW_SEQ_MODE 1 842 bool hiq; 843 u8 port; 844 bool er_cap; 845 }; 846 847 struct rtw89_core_tx_request { 848 enum rtw89_core_tx_type tx_type; 849 850 struct sk_buff *skb; 851 struct ieee80211_vif *vif; 852 struct ieee80211_sta *sta; 853 struct rtw89_tx_desc_info desc_info; 854 }; 855 856 struct rtw89_txq { 857 struct list_head list; 858 unsigned long flags; 859 int wait_cnt; 860 }; 861 862 struct rtw89_mac_ax_gnt { 863 u8 gnt_bt_sw_en; 864 u8 gnt_bt; 865 u8 gnt_wl_sw_en; 866 u8 gnt_wl; 867 } __packed; 868 869 #define RTW89_MAC_AX_COEX_GNT_NR 2 870 struct rtw89_mac_ax_coex_gnt { 871 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 872 }; 873 874 enum rtw89_btc_ncnt { 875 BTC_NCNT_POWER_ON = 0x0, 876 BTC_NCNT_POWER_OFF, 877 BTC_NCNT_INIT_COEX, 878 BTC_NCNT_SCAN_START, 879 BTC_NCNT_SCAN_FINISH, 880 BTC_NCNT_SPECIAL_PACKET, 881 BTC_NCNT_SWITCH_BAND, 882 BTC_NCNT_RFK_TIMEOUT, 883 BTC_NCNT_SHOW_COEX_INFO, 884 BTC_NCNT_ROLE_INFO, 885 BTC_NCNT_CONTROL, 886 BTC_NCNT_RADIO_STATE, 887 BTC_NCNT_CUSTOMERIZE, 888 BTC_NCNT_WL_RFK, 889 BTC_NCNT_WL_STA, 890 BTC_NCNT_FWINFO, 891 BTC_NCNT_TIMER, 892 BTC_NCNT_NUM 893 }; 894 895 enum rtw89_btc_btinfo { 896 BTC_BTINFO_L0 = 0, 897 BTC_BTINFO_L1, 898 BTC_BTINFO_L2, 899 BTC_BTINFO_L3, 900 BTC_BTINFO_H0, 901 BTC_BTINFO_H1, 902 BTC_BTINFO_H2, 903 BTC_BTINFO_H3, 904 BTC_BTINFO_MAX 905 }; 906 907 enum rtw89_btc_dcnt { 908 BTC_DCNT_RUN = 0x0, 909 BTC_DCNT_CX_RUNINFO, 910 BTC_DCNT_RPT, 911 BTC_DCNT_RPT_HANG, 912 BTC_DCNT_CYCLE, 913 BTC_DCNT_CYCLE_HANG, 914 BTC_DCNT_W1, 915 BTC_DCNT_W1_HANG, 916 BTC_DCNT_B1, 917 BTC_DCNT_B1_HANG, 918 BTC_DCNT_TDMA_NONSYNC, 919 BTC_DCNT_SLOT_NONSYNC, 920 BTC_DCNT_BTCNT_HANG, 921 BTC_DCNT_WL_SLOT_DRIFT, 922 BTC_DCNT_WL_STA_LAST, 923 BTC_DCNT_BT_SLOT_DRIFT, 924 BTC_DCNT_BT_SLOT_FLOOD, 925 BTC_DCNT_FDDT_TRIG, 926 BTC_DCNT_E2G, 927 BTC_DCNT_E2G_HANG, 928 BTC_DCNT_NUM 929 }; 930 931 enum rtw89_btc_wl_state_cnt { 932 BTC_WCNT_SCANAP = 0x0, 933 BTC_WCNT_DHCP, 934 BTC_WCNT_EAPOL, 935 BTC_WCNT_ARP, 936 BTC_WCNT_SCBDUPDATE, 937 BTC_WCNT_RFK_REQ, 938 BTC_WCNT_RFK_GO, 939 BTC_WCNT_RFK_REJECT, 940 BTC_WCNT_RFK_TIMEOUT, 941 BTC_WCNT_CH_UPDATE, 942 BTC_WCNT_NUM 943 }; 944 945 enum rtw89_btc_bt_state_cnt { 946 BTC_BCNT_RETRY = 0x0, 947 BTC_BCNT_REINIT, 948 BTC_BCNT_REENABLE, 949 BTC_BCNT_SCBDREAD, 950 BTC_BCNT_RELINK, 951 BTC_BCNT_IGNOWL, 952 BTC_BCNT_INQPAG, 953 BTC_BCNT_INQ, 954 BTC_BCNT_PAGE, 955 BTC_BCNT_ROLESW, 956 BTC_BCNT_AFH, 957 BTC_BCNT_INFOUPDATE, 958 BTC_BCNT_INFOSAME, 959 BTC_BCNT_SCBDUPDATE, 960 BTC_BCNT_HIPRI_TX, 961 BTC_BCNT_HIPRI_RX, 962 BTC_BCNT_LOPRI_TX, 963 BTC_BCNT_LOPRI_RX, 964 BTC_BCNT_POLUT, 965 BTC_BCNT_RATECHG, 966 BTC_BCNT_NUM 967 }; 968 969 enum rtw89_btc_bt_profile { 970 BTC_BT_NOPROFILE = 0, 971 BTC_BT_HFP = BIT(0), 972 BTC_BT_HID = BIT(1), 973 BTC_BT_A2DP = BIT(2), 974 BTC_BT_PAN = BIT(3), 975 BTC_PROFILE_MAX = 4, 976 }; 977 978 struct rtw89_btc_ant_info { 979 u8 type; /* shared, dedicated */ 980 u8 num; 981 u8 isolation; 982 983 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 984 u8 diversity: 1; 985 u8 btg_pos: 2; 986 u8 stream_cnt: 4; 987 }; 988 989 enum rtw89_tfc_dir { 990 RTW89_TFC_UL, 991 RTW89_TFC_DL, 992 }; 993 994 struct rtw89_btc_wl_smap { 995 u32 busy: 1; 996 u32 scan: 1; 997 u32 connecting: 1; 998 u32 roaming: 1; 999 u32 _4way: 1; 1000 u32 rf_off: 1; 1001 u32 lps: 2; 1002 u32 ips: 1; 1003 u32 init_ok: 1; 1004 u32 traffic_dir : 2; 1005 u32 rf_off_pre: 1; 1006 u32 lps_pre: 2; 1007 }; 1008 1009 enum rtw89_tfc_lv { 1010 RTW89_TFC_IDLE, 1011 RTW89_TFC_ULTRA_LOW, 1012 RTW89_TFC_LOW, 1013 RTW89_TFC_MID, 1014 RTW89_TFC_HIGH, 1015 }; 1016 1017 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1018 DECLARE_EWMA(tp, 10, 2); 1019 1020 struct rtw89_traffic_stats { 1021 /* units in bytes */ 1022 u64 tx_unicast; 1023 u64 rx_unicast; 1024 u32 tx_avg_len; 1025 u32 rx_avg_len; 1026 1027 /* count for packets */ 1028 u64 tx_cnt; 1029 u64 rx_cnt; 1030 1031 /* units in Mbps */ 1032 u32 tx_throughput; 1033 u32 rx_throughput; 1034 u32 tx_throughput_raw; 1035 u32 rx_throughput_raw; 1036 1037 u32 rx_tf_acc; 1038 u32 rx_tf_periodic; 1039 1040 enum rtw89_tfc_lv tx_tfc_lv; 1041 enum rtw89_tfc_lv rx_tfc_lv; 1042 struct ewma_tp tx_ewma_tp; 1043 struct ewma_tp rx_ewma_tp; 1044 1045 u16 tx_rate; 1046 u16 rx_rate; 1047 }; 1048 1049 struct rtw89_btc_statistic { 1050 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1051 struct rtw89_traffic_stats traffic; 1052 }; 1053 1054 #define BTC_WL_RSSI_THMAX 4 1055 1056 struct rtw89_btc_wl_link_info { 1057 struct rtw89_btc_statistic stat; 1058 enum rtw89_tfc_dir dir; 1059 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1060 u8 mac_addr[ETH_ALEN]; 1061 u8 busy; 1062 u8 ch; 1063 u8 bw; 1064 u8 band; 1065 u8 role; 1066 u8 pid; 1067 u8 phy; 1068 u8 dtim_period; 1069 u8 mode; 1070 1071 u8 mac_id; 1072 u8 tx_retry; 1073 1074 u32 bcn_period; 1075 u32 busy_t; 1076 u32 tx_time; 1077 u32 client_cnt; 1078 u32 rx_rate_drop_cnt; 1079 1080 u32 active: 1; 1081 u32 noa: 1; 1082 u32 client_ps: 1; 1083 u32 connected: 2; 1084 }; 1085 1086 union rtw89_btc_wl_state_map { 1087 u32 val; 1088 struct rtw89_btc_wl_smap map; 1089 }; 1090 1091 struct rtw89_btc_bt_hfp_desc { 1092 u32 exist: 1; 1093 u32 type: 2; 1094 u32 rsvd: 29; 1095 }; 1096 1097 struct rtw89_btc_bt_hid_desc { 1098 u32 exist: 1; 1099 u32 slot_info: 2; 1100 u32 pair_cnt: 2; 1101 u32 type: 8; 1102 u32 rsvd: 19; 1103 }; 1104 1105 struct rtw89_btc_bt_a2dp_desc { 1106 u8 exist: 1; 1107 u8 exist_last: 1; 1108 u8 play_latency: 1; 1109 u8 type: 3; 1110 u8 active: 1; 1111 u8 sink: 1; 1112 1113 u8 bitpool; 1114 u16 vendor_id; 1115 u32 device_name; 1116 u32 flush_time; 1117 }; 1118 1119 struct rtw89_btc_bt_pan_desc { 1120 u32 exist: 1; 1121 u32 type: 1; 1122 u32 active: 1; 1123 u32 rsvd: 29; 1124 }; 1125 1126 struct rtw89_btc_bt_rfk_info { 1127 u32 run: 1; 1128 u32 req: 1; 1129 u32 timeout: 1; 1130 u32 rsvd: 29; 1131 }; 1132 1133 union rtw89_btc_bt_rfk_info_map { 1134 u32 val; 1135 struct rtw89_btc_bt_rfk_info map; 1136 }; 1137 1138 struct rtw89_btc_bt_ver_info { 1139 u32 fw_coex; /* match with which coex_ver */ 1140 u32 fw; 1141 }; 1142 1143 struct rtw89_btc_bool_sta_chg { 1144 u32 now: 1; 1145 u32 last: 1; 1146 u32 remain: 1; 1147 u32 srvd: 29; 1148 }; 1149 1150 struct rtw89_btc_u8_sta_chg { 1151 u8 now; 1152 u8 last; 1153 u8 remain; 1154 u8 rsvd; 1155 }; 1156 1157 struct rtw89_btc_wl_scan_info { 1158 u8 band[RTW89_PHY_MAX]; 1159 u8 phy_map; 1160 u8 rsvd; 1161 }; 1162 1163 struct rtw89_btc_wl_dbcc_info { 1164 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1165 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1166 u8 real_band[RTW89_PHY_MAX]; 1167 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1168 }; 1169 1170 struct rtw89_btc_wl_active_role { 1171 u8 connected: 1; 1172 u8 pid: 3; 1173 u8 phy: 1; 1174 u8 noa: 1; 1175 u8 band: 2; 1176 1177 u8 client_ps: 1; 1178 u8 bw: 7; 1179 1180 u8 role; 1181 u8 ch; 1182 1183 u16 tx_lvl; 1184 u16 rx_lvl; 1185 u16 tx_rate; 1186 u16 rx_rate; 1187 }; 1188 1189 struct rtw89_btc_wl_active_role_v1 { 1190 u8 connected: 1; 1191 u8 pid: 3; 1192 u8 phy: 1; 1193 u8 noa: 1; 1194 u8 band: 2; 1195 1196 u8 client_ps: 1; 1197 u8 bw: 7; 1198 1199 u8 role; 1200 u8 ch; 1201 1202 u16 tx_lvl; 1203 u16 rx_lvl; 1204 u16 tx_rate; 1205 u16 rx_rate; 1206 1207 u32 noa_duration; /* ms */ 1208 }; 1209 1210 struct rtw89_btc_wl_active_role_v2 { 1211 u8 connected: 1; 1212 u8 pid: 3; 1213 u8 phy: 1; 1214 u8 noa: 1; 1215 u8 band: 2; 1216 1217 u8 client_ps: 1; 1218 u8 bw: 7; 1219 1220 u8 role; 1221 u8 ch; 1222 1223 u32 noa_duration; /* ms */ 1224 }; 1225 1226 struct rtw89_btc_wl_role_info_bpos { 1227 u16 none: 1; 1228 u16 station: 1; 1229 u16 ap: 1; 1230 u16 vap: 1; 1231 u16 adhoc: 1; 1232 u16 adhoc_master: 1; 1233 u16 mesh: 1; 1234 u16 moniter: 1; 1235 u16 p2p_device: 1; 1236 u16 p2p_gc: 1; 1237 u16 p2p_go: 1; 1238 u16 nan: 1; 1239 }; 1240 1241 struct rtw89_btc_wl_scc_ctrl { 1242 u8 null_role1; 1243 u8 null_role2; 1244 u8 ebt_null; /* if tx null at EBT slot */ 1245 }; 1246 1247 union rtw89_btc_wl_role_info_map { 1248 u16 val; 1249 struct rtw89_btc_wl_role_info_bpos role; 1250 }; 1251 1252 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1253 u8 connect_cnt; 1254 u8 link_mode; 1255 union rtw89_btc_wl_role_info_map role_map; 1256 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1257 }; 1258 1259 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1260 u8 connect_cnt; 1261 u8 link_mode; 1262 union rtw89_btc_wl_role_info_map role_map; 1263 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1264 u32 mrole_type; /* btc_wl_mrole_type */ 1265 u32 mrole_noa_duration; /* ms */ 1266 1267 u32 dbcc_en: 1; 1268 u32 dbcc_chg: 1; 1269 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1270 u32 link_mode_chg: 1; 1271 u32 rsvd: 27; 1272 }; 1273 1274 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1275 u8 connect_cnt; 1276 u8 link_mode; 1277 union rtw89_btc_wl_role_info_map role_map; 1278 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1279 u32 mrole_type; /* btc_wl_mrole_type */ 1280 u32 mrole_noa_duration; /* ms */ 1281 1282 u32 dbcc_en: 1; 1283 u32 dbcc_chg: 1; 1284 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1285 u32 link_mode_chg: 1; 1286 u32 rsvd: 27; 1287 }; 1288 1289 struct rtw89_btc_wl_ver_info { 1290 u32 fw_coex; /* match with which coex_ver */ 1291 u32 fw; 1292 u32 mac; 1293 u32 bb; 1294 u32 rf; 1295 }; 1296 1297 struct rtw89_btc_wl_afh_info { 1298 u8 en; 1299 u8 ch; 1300 u8 bw; 1301 u8 rsvd; 1302 } __packed; 1303 1304 struct rtw89_btc_wl_rfk_info { 1305 u32 state: 2; 1306 u32 path_map: 4; 1307 u32 phy_map: 2; 1308 u32 band: 2; 1309 u32 type: 8; 1310 u32 rsvd: 14; 1311 }; 1312 1313 struct rtw89_btc_bt_smap { 1314 u32 connect: 1; 1315 u32 ble_connect: 1; 1316 u32 acl_busy: 1; 1317 u32 sco_busy: 1; 1318 u32 mesh_busy: 1; 1319 u32 inq_pag: 1; 1320 }; 1321 1322 union rtw89_btc_bt_state_map { 1323 u32 val; 1324 struct rtw89_btc_bt_smap map; 1325 }; 1326 1327 #define BTC_BT_RSSI_THMAX 4 1328 #define BTC_BT_AFH_GROUP 12 1329 #define BTC_BT_AFH_LE_GROUP 5 1330 1331 struct rtw89_btc_bt_link_info { 1332 struct rtw89_btc_u8_sta_chg profile_cnt; 1333 struct rtw89_btc_bool_sta_chg multi_link; 1334 struct rtw89_btc_bool_sta_chg relink; 1335 struct rtw89_btc_bt_hfp_desc hfp_desc; 1336 struct rtw89_btc_bt_hid_desc hid_desc; 1337 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1338 struct rtw89_btc_bt_pan_desc pan_desc; 1339 union rtw89_btc_bt_state_map status; 1340 1341 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1342 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1343 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1344 u8 afh_map[BTC_BT_AFH_GROUP]; 1345 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1346 1347 u32 role_sw: 1; 1348 u32 slave_role: 1; 1349 u32 afh_update: 1; 1350 u32 cqddr: 1; 1351 u32 rssi: 8; 1352 u32 tx_3m: 1; 1353 u32 rsvd: 19; 1354 }; 1355 1356 struct rtw89_btc_3rdcx_info { 1357 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1358 u8 hw_coex; 1359 u16 rsvd; 1360 }; 1361 1362 struct rtw89_btc_dm_emap { 1363 u32 init: 1; 1364 u32 pta_owner: 1; 1365 u32 wl_rfk_timeout: 1; 1366 u32 bt_rfk_timeout: 1; 1367 u32 wl_fw_hang: 1; 1368 u32 cycle_hang: 1; 1369 u32 w1_hang: 1; 1370 u32 b1_hang: 1; 1371 u32 tdma_no_sync: 1; 1372 u32 slot_no_sync: 1; 1373 u32 wl_slot_drift: 1; 1374 u32 bt_slot_drift: 1; 1375 u32 role_num_mismatch: 1; 1376 u32 null1_tx_late: 1; 1377 u32 bt_afh_conflict: 1; 1378 u32 bt_leafh_conflict: 1; 1379 u32 bt_slot_flood: 1; 1380 u32 wl_e2g_hang: 1; 1381 u32 wl_ver_mismatch: 1; 1382 u32 bt_ver_mismatch: 1; 1383 }; 1384 1385 union rtw89_btc_dm_error_map { 1386 u32 val; 1387 struct rtw89_btc_dm_emap map; 1388 }; 1389 1390 struct rtw89_btc_rf_para { 1391 u32 tx_pwr_freerun; 1392 u32 rx_gain_freerun; 1393 u32 tx_pwr_perpkt; 1394 u32 rx_gain_perpkt; 1395 }; 1396 1397 struct rtw89_btc_wl_nhm { 1398 u8 instant_wl_nhm_dbm; 1399 u8 instant_wl_nhm_per_mhz; 1400 u16 valid_record_times; 1401 s8 record_pwr[16]; 1402 u8 record_ratio[16]; 1403 s8 pwr; /* dbm_per_MHz */ 1404 u8 ratio; 1405 u8 current_status; 1406 u8 refresh; 1407 bool start_flag; 1408 u8 last_ccx_rpt_stamp; 1409 s8 pwr_max; 1410 s8 pwr_min; 1411 }; 1412 1413 struct rtw89_btc_wl_info { 1414 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1415 struct rtw89_btc_wl_rfk_info rfk_info; 1416 struct rtw89_btc_wl_ver_info ver_info; 1417 struct rtw89_btc_wl_afh_info afh_info; 1418 struct rtw89_btc_wl_role_info role_info; 1419 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1420 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1421 struct rtw89_btc_wl_scan_info scan_info; 1422 struct rtw89_btc_wl_dbcc_info dbcc_info; 1423 struct rtw89_btc_rf_para rf_para; 1424 struct rtw89_btc_wl_nhm nhm; 1425 union rtw89_btc_wl_state_map status; 1426 1427 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1428 u8 rssi_level; 1429 u8 cn_report; 1430 1431 bool scbd_change; 1432 u32 scbd; 1433 }; 1434 1435 struct rtw89_btc_module { 1436 struct rtw89_btc_ant_info ant; 1437 u8 rfe_type; 1438 u8 cv; 1439 1440 u8 bt_solo: 1; 1441 u8 bt_pos: 1; 1442 u8 switch_type: 1; 1443 u8 wa_type: 3; 1444 1445 u8 kt_ver_adie; 1446 }; 1447 1448 #define RTW89_BTC_DM_MAXSTEP 30 1449 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1450 1451 struct rtw89_btc_dm_step { 1452 u16 step[RTW89_BTC_DM_MAXSTEP]; 1453 u8 step_pos; 1454 bool step_ov; 1455 }; 1456 1457 struct rtw89_btc_init_info { 1458 struct rtw89_btc_module module; 1459 u8 wl_guard_ch; 1460 1461 u8 wl_only: 1; 1462 u8 wl_init_ok: 1; 1463 u8 dbcc_en: 1; 1464 u8 cx_other: 1; 1465 u8 bt_only: 1; 1466 1467 u16 rsvd; 1468 }; 1469 1470 struct rtw89_btc_wl_tx_limit_para { 1471 u16 enable; 1472 u32 tx_time; /* unit: us */ 1473 u16 tx_retry; 1474 }; 1475 1476 enum rtw89_btc_bt_scan_type { 1477 BTC_SCAN_INQ = 0, 1478 BTC_SCAN_PAGE, 1479 BTC_SCAN_BLE, 1480 BTC_SCAN_INIT, 1481 BTC_SCAN_TV, 1482 BTC_SCAN_ADV, 1483 BTC_SCAN_MAX1, 1484 }; 1485 1486 enum rtw89_btc_ble_scan_type { 1487 CXSCAN_BG = 0, 1488 CXSCAN_INIT, 1489 CXSCAN_LE, 1490 CXSCAN_MAX 1491 }; 1492 1493 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1494 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1495 1496 struct rtw89_btc_bt_scan_info_v1 { 1497 __le16 win; 1498 __le16 intvl; 1499 __le32 flags; 1500 } __packed; 1501 1502 struct rtw89_btc_bt_scan_info_v2 { 1503 __le16 win; 1504 __le16 intvl; 1505 } __packed; 1506 1507 struct rtw89_btc_fbtc_btscan_v1 { 1508 u8 fver; /* btc_ver::fcxbtscan */ 1509 u8 rsvd; 1510 __le16 rsvd2; 1511 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1512 } __packed; 1513 1514 struct rtw89_btc_fbtc_btscan_v2 { 1515 u8 fver; /* btc_ver::fcxbtscan */ 1516 u8 type; 1517 __le16 rsvd2; 1518 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1519 } __packed; 1520 1521 union rtw89_btc_fbtc_btscan { 1522 struct rtw89_btc_fbtc_btscan_v1 v1; 1523 struct rtw89_btc_fbtc_btscan_v2 v2; 1524 }; 1525 1526 struct rtw89_btc_bt_info { 1527 struct rtw89_btc_bt_link_info link_info; 1528 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1529 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1530 struct rtw89_btc_bt_ver_info ver_info; 1531 struct rtw89_btc_bool_sta_chg enable; 1532 struct rtw89_btc_bool_sta_chg inq_pag; 1533 struct rtw89_btc_rf_para rf_para; 1534 union rtw89_btc_bt_rfk_info_map rfk_info; 1535 1536 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1537 1538 u32 scbd; 1539 u32 feature; 1540 1541 u32 mbx_avl: 1; 1542 u32 whql_test: 1; 1543 u32 igno_wl: 1; 1544 u32 reinit: 1; 1545 u32 ble_scan_en: 1; 1546 u32 btg_type: 1; 1547 u32 inq: 1; 1548 u32 pag: 1; 1549 u32 run_patch_code: 1; 1550 u32 hi_lna_rx: 1; 1551 u32 scan_rx_low_pri: 1; 1552 u32 scan_info_update: 1; 1553 u32 rsvd: 20; 1554 }; 1555 1556 struct rtw89_btc_cx { 1557 struct rtw89_btc_wl_info wl; 1558 struct rtw89_btc_bt_info bt; 1559 struct rtw89_btc_3rdcx_info other; 1560 u32 state_map; 1561 u32 cnt_bt[BTC_BCNT_NUM]; 1562 u32 cnt_wl[BTC_WCNT_NUM]; 1563 }; 1564 1565 struct rtw89_btc_fbtc_tdma { 1566 u8 type; /* btc_ver::fcxtdma */ 1567 u8 rxflctrl; 1568 u8 txpause; 1569 u8 wtgle_n; 1570 u8 leak_n; 1571 u8 ext_ctrl; 1572 u8 rxflctrl_role; 1573 u8 option_ctrl; 1574 } __packed; 1575 1576 struct rtw89_btc_fbtc_tdma_v3 { 1577 u8 fver; /* btc_ver::fcxtdma */ 1578 u8 rsvd; 1579 __le16 rsvd1; 1580 struct rtw89_btc_fbtc_tdma tdma; 1581 } __packed; 1582 1583 union rtw89_btc_fbtc_tdma_le32 { 1584 struct rtw89_btc_fbtc_tdma v1; 1585 struct rtw89_btc_fbtc_tdma_v3 v3; 1586 }; 1587 1588 #define CXMREG_MAX 30 1589 #define CXMREG_MAX_V2 20 1590 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1591 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1592 1593 enum rtw89_btc_bt_sta_counter { 1594 BTC_BCNT_RFK_REQ = 0, 1595 BTC_BCNT_RFK_GO = 1, 1596 BTC_BCNT_RFK_REJECT = 2, 1597 BTC_BCNT_RFK_FAIL = 3, 1598 BTC_BCNT_RFK_TIMEOUT = 4, 1599 BTC_BCNT_HI_TX = 5, 1600 BTC_BCNT_HI_RX = 6, 1601 BTC_BCNT_LO_TX = 7, 1602 BTC_BCNT_LO_RX = 8, 1603 BTC_BCNT_POLLUTED = 9, 1604 BTC_BCNT_STA_MAX 1605 }; 1606 1607 enum rtw89_btc_bt_sta_counter_v105 { 1608 BTC_BCNT_RFK_REQ_V105 = 0, 1609 BTC_BCNT_HI_TX_V105 = 1, 1610 BTC_BCNT_HI_RX_V105 = 2, 1611 BTC_BCNT_LO_TX_V105 = 3, 1612 BTC_BCNT_LO_RX_V105 = 4, 1613 BTC_BCNT_POLLUTED_V105 = 5, 1614 BTC_BCNT_STA_MAX_V105 1615 }; 1616 1617 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1618 u16 fver; /* btc_ver::fcxbtcrpt */ 1619 u16 rpt_cnt; /* tmr counters */ 1620 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1621 u32 wl_fw_cx_offload; 1622 u32 wl_fw_ver; 1623 u32 rpt_enable; 1624 u32 rpt_para; /* ms */ 1625 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1626 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1627 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1628 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1629 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1630 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1631 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1632 u32 c2h_cnt; /* fw send c2h counter */ 1633 u32 h2c_cnt; /* fw recv h2c counter */ 1634 } __packed; 1635 1636 struct rtw89_btc_fbtc_rpt_ctrl_info { 1637 __le32 cnt; /* fw report counter */ 1638 __le32 en; /* report map */ 1639 __le32 para; /* not used */ 1640 1641 __le32 cnt_c2h; /* fw send c2h counter */ 1642 __le32 cnt_h2c; /* fw recv h2c counter */ 1643 __le32 len_c2h; /* The total length of the last C2H */ 1644 1645 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1646 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1647 } __packed; 1648 1649 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1650 __le32 cx_ver; /* match which driver's coex version */ 1651 __le32 fw_ver; 1652 __le32 en; /* report map */ 1653 1654 __le16 cnt; /* fw report counter */ 1655 __le16 cnt_c2h; /* fw send c2h counter */ 1656 __le16 cnt_h2c; /* fw recv h2c counter */ 1657 __le16 len_c2h; /* The total length of the last C2H */ 1658 1659 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1660 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1661 } __packed; 1662 1663 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1664 __le32 cx_ver; /* match which driver's coex version */ 1665 __le32 cx_offload; 1666 __le32 fw_ver; 1667 } __packed; 1668 1669 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1670 __le32 cnt_empty; /* a2dp empty count */ 1671 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1672 __le32 cnt_tx; 1673 __le32 cnt_ack; 1674 __le32 cnt_nack; 1675 } __packed; 1676 1677 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1678 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1679 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1680 __le32 cnt_recv; /* fw recv mailbox counter */ 1681 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1682 } __packed; 1683 1684 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1685 u8 fver; 1686 u8 rsvd; 1687 __le16 rsvd1; 1688 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1689 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1690 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1691 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1692 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1693 } __packed; 1694 1695 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1696 u8 fver; 1697 u8 rsvd; 1698 __le16 rsvd1; 1699 1700 u8 gnt_val[RTW89_PHY_MAX][4]; 1701 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1702 1703 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1704 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1705 } __packed; 1706 1707 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1708 u8 fver; 1709 u8 rsvd; 1710 __le16 rsvd1; 1711 1712 u8 gnt_val[RTW89_PHY_MAX][4]; 1713 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1714 1715 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1716 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1717 } __packed; 1718 1719 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1720 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 1721 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 1722 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 1723 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 1724 }; 1725 1726 enum rtw89_fbtc_ext_ctrl_type { 1727 CXECTL_OFF = 0x0, /* tdma off */ 1728 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1729 CXECTL_EXT = 0x2, 1730 CXECTL_MAX 1731 }; 1732 1733 union rtw89_btc_fbtc_rxflct { 1734 u8 val; 1735 u8 type: 3; 1736 u8 tgln_n: 5; 1737 }; 1738 1739 enum rtw89_btc_cxst_state { 1740 CXST_OFF = 0x0, 1741 CXST_B2W = 0x1, 1742 CXST_W1 = 0x2, 1743 CXST_W2 = 0x3, 1744 CXST_W2B = 0x4, 1745 CXST_B1 = 0x5, 1746 CXST_B2 = 0x6, 1747 CXST_B3 = 0x7, 1748 CXST_B4 = 0x8, 1749 CXST_LK = 0x9, 1750 CXST_BLK = 0xa, 1751 CXST_E2G = 0xb, 1752 CXST_E5G = 0xc, 1753 CXST_EBT = 0xd, 1754 CXST_ENULL = 0xe, 1755 CXST_WLK = 0xf, 1756 CXST_W1FDD = 0x10, 1757 CXST_B1FDD = 0x11, 1758 CXST_MAX = 0x12, 1759 }; 1760 1761 enum rtw89_btc_cxevnt { 1762 CXEVNT_TDMA_ENTRY = 0x0, 1763 CXEVNT_WL_TMR, 1764 CXEVNT_B1_TMR, 1765 CXEVNT_B2_TMR, 1766 CXEVNT_B3_TMR, 1767 CXEVNT_B4_TMR, 1768 CXEVNT_W2B_TMR, 1769 CXEVNT_B2W_TMR, 1770 CXEVNT_BCN_EARLY, 1771 CXEVNT_A2DP_EMPTY, 1772 CXEVNT_LK_END, 1773 CXEVNT_RX_ISR, 1774 CXEVNT_RX_FC0, 1775 CXEVNT_RX_FC1, 1776 CXEVNT_BT_RELINK, 1777 CXEVNT_BT_RETRY, 1778 CXEVNT_E2G, 1779 CXEVNT_E5G, 1780 CXEVNT_EBT, 1781 CXEVNT_ENULL, 1782 CXEVNT_DRV_WLK, 1783 CXEVNT_BCN_OK, 1784 CXEVNT_BT_CHANGE, 1785 CXEVNT_EBT_EXTEND, 1786 CXEVNT_E2G_NULL1, 1787 CXEVNT_B1FDD_TMR, 1788 CXEVNT_MAX 1789 }; 1790 1791 enum { 1792 CXBCN_ALL = 0x0, 1793 CXBCN_ALL_OK, 1794 CXBCN_BT_SLOT, 1795 CXBCN_BT_OK, 1796 CXBCN_MAX 1797 }; 1798 1799 enum btc_slot_type { 1800 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1801 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1802 CXSTYPE_NUM, 1803 }; 1804 1805 enum { /* TIME */ 1806 CXT_BT = 0x0, 1807 CXT_WL = 0x1, 1808 CXT_MAX 1809 }; 1810 1811 enum { /* TIME-A2DP */ 1812 CXT_FLCTRL_OFF = 0x0, 1813 CXT_FLCTRL_ON = 0x1, 1814 CXT_FLCTRL_MAX 1815 }; 1816 1817 enum { /* STEP TYPE */ 1818 CXSTEP_NONE = 0x0, 1819 CXSTEP_EVNT = 0x1, 1820 CXSTEP_SLOT = 0x2, 1821 CXSTEP_MAX, 1822 }; 1823 1824 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 1825 RPT_BT_AFH_SEQ_LEGACY = 0x10, 1826 RPT_BT_AFH_SEQ_LE = 0x20 1827 }; 1828 1829 #define BTC_DBG_MAX1 32 1830 struct rtw89_btc_fbtc_gpio_dbg { 1831 u8 fver; /* btc_ver::fcxgpiodbg */ 1832 u8 rsvd; 1833 u16 rsvd2; 1834 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1835 u32 pre_state; /* the debug signal is 1 or 0 */ 1836 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1837 } __packed; 1838 1839 struct rtw89_btc_fbtc_mreg_val_v1 { 1840 u8 fver; /* btc_ver::fcxmreg */ 1841 u8 reg_num; 1842 __le16 rsvd; 1843 __le32 mreg_val[CXMREG_MAX]; 1844 } __packed; 1845 1846 struct rtw89_btc_fbtc_mreg_val_v2 { 1847 u8 fver; /* btc_ver::fcxmreg */ 1848 u8 reg_num; 1849 __le16 rsvd; 1850 __le32 mreg_val[CXMREG_MAX_V2]; 1851 } __packed; 1852 1853 union rtw89_btc_fbtc_mreg_val { 1854 struct rtw89_btc_fbtc_mreg_val_v1 v1; 1855 struct rtw89_btc_fbtc_mreg_val_v2 v2; 1856 }; 1857 1858 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1859 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1860 .offset = cpu_to_le32(__offset), } 1861 1862 struct rtw89_btc_fbtc_mreg { 1863 __le16 type; 1864 __le16 bytes; 1865 __le32 offset; 1866 } __packed; 1867 1868 struct rtw89_btc_fbtc_slot { 1869 __le16 dur; 1870 __le32 cxtbl; 1871 __le16 cxtype; 1872 } __packed; 1873 1874 struct rtw89_btc_fbtc_slots { 1875 u8 fver; /* btc_ver::fcxslots */ 1876 u8 tbl_num; 1877 __le16 rsvd; 1878 __le32 update_map; 1879 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1880 } __packed; 1881 1882 struct rtw89_btc_fbtc_step { 1883 u8 type; 1884 u8 val; 1885 __le16 difft; 1886 } __packed; 1887 1888 struct rtw89_btc_fbtc_steps_v2 { 1889 u8 fver; /* btc_ver::fcxstep */ 1890 u8 rsvd; 1891 __le16 cnt; 1892 __le16 pos_old; 1893 __le16 pos_new; 1894 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1895 } __packed; 1896 1897 struct rtw89_btc_fbtc_steps_v3 { 1898 u8 fver; 1899 u8 en; 1900 __le16 rsvd; 1901 __le32 cnt; 1902 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1903 } __packed; 1904 1905 union rtw89_btc_fbtc_steps_info { 1906 struct rtw89_btc_fbtc_steps_v2 v2; 1907 struct rtw89_btc_fbtc_steps_v3 v3; 1908 }; 1909 1910 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 1911 u8 fver; /* btc_ver::fcxcysta */ 1912 u8 rsvd; 1913 __le16 cycles; /* total cycle number */ 1914 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1915 __le16 a2dpept; /* a2dp empty cnt */ 1916 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1917 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1918 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1919 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1920 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1921 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1922 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1923 __le16 tmax_a2dpept; /* max a2dp empty time */ 1924 __le16 tavg_lk; /* avg leak-slot time */ 1925 __le16 tmax_lk; /* max leak-slot time */ 1926 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1927 __le32 bcn_cnt[CXBCN_MAX]; 1928 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1929 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1930 __le32 skip_cnt; 1931 __le32 exception; 1932 __le32 except_cnt; 1933 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1934 } __packed; 1935 1936 struct rtw89_btc_fbtc_fdd_try_info { 1937 __le16 cycles[CXT_FLCTRL_MAX]; 1938 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 1939 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 1940 } __packed; 1941 1942 struct rtw89_btc_fbtc_cycle_time_info { 1943 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1944 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1945 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1946 } __packed; 1947 1948 struct rtw89_btc_fbtc_cycle_time_info_v5 { 1949 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 1950 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 1951 } __packed; 1952 1953 struct rtw89_btc_fbtc_a2dp_trx_stat { 1954 u8 empty_cnt; 1955 u8 retry_cnt; 1956 u8 tx_rate; 1957 u8 tx_cnt; 1958 u8 ack_cnt; 1959 u8 nack_cnt; 1960 u8 rsvd1; 1961 u8 rsvd2; 1962 } __packed; 1963 1964 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 1965 u8 empty_cnt; 1966 u8 retry_cnt; 1967 u8 tx_rate; 1968 u8 tx_cnt; 1969 u8 ack_cnt; 1970 u8 nack_cnt; 1971 u8 no_empty_cnt; 1972 u8 rsvd; 1973 } __packed; 1974 1975 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 1976 __le16 cnt; /* a2dp empty cnt */ 1977 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 1978 __le16 tavg; /* avg a2dp empty time */ 1979 __le16 tmax; /* max a2dp empty time */ 1980 } __packed; 1981 1982 struct rtw89_btc_fbtc_cycle_leak_info { 1983 __le32 cnt_rximr; /* the rximr occur at leak slot */ 1984 __le16 tavg; /* avg leak-slot time */ 1985 __le16 tmax; /* max leak-slot time */ 1986 } __packed; 1987 1988 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 1989 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 1990 1991 struct rtw89_btc_fbtc_cycle_fddt_info { 1992 __le16 train_cycle; 1993 __le16 tp; 1994 1995 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1996 s8 bt_tx_power; /* decrease Tx power (dB) */ 1997 s8 bt_rx_gain; /* LNA constrain level */ 1998 u8 no_empty_cnt; 1999 2000 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2001 u8 cn; /* condition_num */ 2002 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2003 u8 train_result; /* refer to enum btc_fddt_check_map */ 2004 } __packed; 2005 2006 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2007 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2008 2009 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2010 __le16 train_cycle; 2011 __le16 tp; 2012 2013 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2014 s8 bt_tx_power; /* decrease Tx power (dB) */ 2015 s8 bt_rx_gain; /* LNA constrain level */ 2016 u8 no_empty_cnt; 2017 2018 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2019 u8 cn; /* condition_num */ 2020 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2021 u8 train_result; /* refer to enum btc_fddt_check_map */ 2022 } __packed; 2023 2024 struct rtw89_btc_fbtc_fddt_cell_status { 2025 s8 wl_tx_pwr; 2026 s8 bt_tx_pwr; 2027 s8 bt_rx_gain; 2028 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2029 } __packed; 2030 2031 struct rtw89_btc_fbtc_fddt_cell_status_v5 { 2032 s8 wl_tx_pwr; 2033 s8 bt_tx_pwr; 2034 s8 bt_rx_gain; 2035 } __packed; 2036 2037 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2038 u8 fver; 2039 u8 rsvd; 2040 __le16 cycles; /* total cycle number */ 2041 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2042 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2043 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2044 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2045 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2046 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2047 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2048 __le32 bcn_cnt[CXBCN_MAX]; 2049 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2050 __le32 skip_cnt; 2051 __le32 except_cnt; 2052 __le32 except_map; 2053 } __packed; 2054 2055 #define FDD_TRAIN_WL_DIRECTION 2 2056 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2057 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2058 2059 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2060 u8 fver; 2061 u8 rsvd; 2062 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2063 u8 except_cnt; 2064 2065 __le16 skip_cnt; 2066 __le16 cycles; /* total cycle number */ 2067 2068 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2069 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2070 __le16 bcn_cnt[CXBCN_MAX]; 2071 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2072 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2073 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2074 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2075 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2076 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2077 [FDD_TRAIN_WL_RSSI_LEVEL] 2078 [FDD_TRAIN_BT_RSSI_LEVEL]; 2079 __le32 except_map; 2080 } __packed; 2081 2082 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2083 u8 fver; 2084 u8 rsvd; 2085 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2086 u8 except_cnt; 2087 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2088 2089 __le16 skip_cnt; 2090 __le16 cycles; /* total cycle number */ 2091 2092 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2093 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2094 __le16 bcn_cnt[CXBCN_MAX]; 2095 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2096 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2097 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2098 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2099 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2100 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] 2101 [FDD_TRAIN_WL_RSSI_LEVEL] 2102 [FDD_TRAIN_BT_RSSI_LEVEL]; 2103 __le32 except_map; 2104 } __packed; 2105 2106 union rtw89_btc_fbtc_cysta_info { 2107 struct rtw89_btc_fbtc_cysta_v2 v2; 2108 struct rtw89_btc_fbtc_cysta_v3 v3; 2109 struct rtw89_btc_fbtc_cysta_v4 v4; 2110 struct rtw89_btc_fbtc_cysta_v5 v5; 2111 }; 2112 2113 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2114 u8 fver; /* btc_ver::fcxnullsta */ 2115 u8 rsvd; 2116 __le16 rsvd2; 2117 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2118 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2119 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2120 } __packed; 2121 2122 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2123 u8 fver; /* btc_ver::fcxnullsta */ 2124 u8 rsvd; 2125 __le16 rsvd2; 2126 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2127 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2128 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2129 } __packed; 2130 2131 union rtw89_btc_fbtc_cynullsta_info { 2132 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2133 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2134 }; 2135 2136 struct rtw89_btc_fbtc_btver { 2137 u8 fver; /* btc_ver::fcxbtver */ 2138 u8 rsvd; 2139 __le16 rsvd2; 2140 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2141 __le32 fw_ver; 2142 __le32 feature; 2143 } __packed; 2144 2145 struct rtw89_btc_fbtc_btafh { 2146 u8 fver; /* btc_ver::fcxbtafh */ 2147 u8 rsvd; 2148 __le16 rsvd2; 2149 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2150 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2151 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2152 } __packed; 2153 2154 struct rtw89_btc_fbtc_btafh_v2 { 2155 u8 fver; /* btc_ver::fcxbtafh */ 2156 u8 rsvd; 2157 u8 rsvd2; 2158 u8 map_type; 2159 u8 afh_l[4]; 2160 u8 afh_m[4]; 2161 u8 afh_h[4]; 2162 u8 afh_le_a[4]; 2163 u8 afh_le_b[4]; 2164 } __packed; 2165 2166 struct rtw89_btc_fbtc_btdevinfo { 2167 u8 fver; /* btc_ver::fcxbtdevinfo */ 2168 u8 rsvd; 2169 __le16 vendor_id; 2170 __le32 dev_name; /* only 24 bits valid */ 2171 __le32 flush_time; 2172 } __packed; 2173 2174 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2175 struct rtw89_btc_rf_trx_para { 2176 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2177 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2178 u8 bt_tx_power; /* decrease Tx power (dB) */ 2179 u8 bt_rx_gain; /* LNA constrain level */ 2180 }; 2181 2182 struct rtw89_btc_trx_info { 2183 u8 tx_lvl; 2184 u8 rx_lvl; 2185 u8 wl_rssi; 2186 u8 bt_rssi; 2187 2188 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2189 s8 rx_gain; /* rx gain table index (TBD.) */ 2190 s8 bt_tx_power; /* decrease Tx power (dB) */ 2191 s8 bt_rx_gain; /* LNA constrain level */ 2192 2193 u8 cn; /* condition_num */ 2194 s8 nhm; 2195 u8 bt_profile; 2196 u8 rsvd2; 2197 2198 u16 tx_rate; 2199 u16 rx_rate; 2200 2201 u32 tx_tp; 2202 u32 rx_tp; 2203 u32 rx_err_ratio; 2204 }; 2205 2206 struct rtw89_btc_dm { 2207 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2208 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2209 struct rtw89_btc_fbtc_tdma tdma; 2210 struct rtw89_btc_fbtc_tdma tdma_now; 2211 struct rtw89_mac_ax_coex_gnt gnt; 2212 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2213 struct rtw89_btc_rf_trx_para rf_trx_para; 2214 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2215 struct rtw89_btc_dm_step dm_step; 2216 struct rtw89_btc_wl_scc_ctrl wl_scc; 2217 struct rtw89_btc_trx_info trx_info; 2218 union rtw89_btc_dm_error_map error; 2219 u32 cnt_dm[BTC_DCNT_NUM]; 2220 u32 cnt_notify[BTC_NCNT_NUM]; 2221 2222 u32 update_slot_map; 2223 u32 set_ant_path; 2224 2225 u32 wl_only: 1; 2226 u32 wl_fw_cx_offload: 1; 2227 u32 freerun: 1; 2228 u32 fddt_train: 1; 2229 u32 wl_ps_ctrl: 2; 2230 u32 wl_mimo_ps: 1; 2231 u32 leak_ap: 1; 2232 u32 noisy_level: 3; 2233 u32 coex_info_map: 8; 2234 u32 bt_only: 1; 2235 u32 wl_btg_rx: 1; 2236 u32 trx_para_level: 8; 2237 u32 wl_stb_chg: 1; 2238 u32 pta_owner: 1; 2239 u32 tdma_instant_excute: 1; 2240 2241 u16 slot_dur[CXST_MAX]; 2242 2243 u8 run_reason; 2244 u8 run_action; 2245 2246 u8 wl_lna2: 1; 2247 }; 2248 2249 struct rtw89_btc_ctrl { 2250 u32 manual: 1; 2251 u32 igno_bt: 1; 2252 u32 always_freerun: 1; 2253 u32 trace_step: 16; 2254 u32 rsvd: 12; 2255 }; 2256 2257 struct rtw89_btc_dbg { 2258 /* cmd "rb" */ 2259 bool rb_done; 2260 u32 rb_val; 2261 }; 2262 2263 enum rtw89_btc_btf_fw_event { 2264 BTF_EVNT_RPT = 0, 2265 BTF_EVNT_BT_INFO = 1, 2266 BTF_EVNT_BT_SCBD = 2, 2267 BTF_EVNT_BT_REG = 3, 2268 BTF_EVNT_CX_RUNINFO = 4, 2269 BTF_EVNT_BT_PSD = 5, 2270 BTF_EVNT_BUF_OVERFLOW, 2271 BTF_EVNT_C2H_LOOPBACK, 2272 BTF_EVNT_MAX, 2273 }; 2274 2275 enum btf_fw_event_report { 2276 BTC_RPT_TYPE_CTRL = 0x0, 2277 BTC_RPT_TYPE_TDMA, 2278 BTC_RPT_TYPE_SLOT, 2279 BTC_RPT_TYPE_CYSTA, 2280 BTC_RPT_TYPE_STEP, 2281 BTC_RPT_TYPE_NULLSTA, 2282 BTC_RPT_TYPE_MREG, 2283 BTC_RPT_TYPE_GPIO_DBG, 2284 BTC_RPT_TYPE_BT_VER, 2285 BTC_RPT_TYPE_BT_SCAN, 2286 BTC_RPT_TYPE_BT_AFH, 2287 BTC_RPT_TYPE_BT_DEVICE, 2288 BTC_RPT_TYPE_TEST, 2289 BTC_RPT_TYPE_MAX = 31 2290 }; 2291 2292 enum rtw_btc_btf_reg_type { 2293 REG_MAC = 0x0, 2294 REG_BB = 0x1, 2295 REG_RF = 0x2, 2296 REG_BT_RF = 0x3, 2297 REG_BT_MODEM = 0x4, 2298 REG_BT_BLUEWIZE = 0x5, 2299 REG_BT_VENDOR = 0x6, 2300 REG_BT_LE = 0x7, 2301 REG_MAX_TYPE, 2302 }; 2303 2304 struct rtw89_btc_rpt_cmn_info { 2305 u32 rx_cnt; 2306 u32 rx_len; 2307 u32 req_len; /* expected rsp len */ 2308 u8 req_fver; /* expected rsp fver */ 2309 u8 rsp_fver; /* fver from fw */ 2310 u8 valid; 2311 } __packed; 2312 2313 union rtw89_btc_fbtc_btafh_info { 2314 struct rtw89_btc_fbtc_btafh v1; 2315 struct rtw89_btc_fbtc_btafh_v2 v2; 2316 }; 2317 2318 struct rtw89_btc_report_ctrl_state { 2319 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2320 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2321 }; 2322 2323 struct rtw89_btc_rpt_fbtc_tdma { 2324 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2325 union rtw89_btc_fbtc_tdma_le32 finfo; 2326 }; 2327 2328 struct rtw89_btc_rpt_fbtc_slots { 2329 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2330 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2331 }; 2332 2333 struct rtw89_btc_rpt_fbtc_cysta { 2334 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2335 union rtw89_btc_fbtc_cysta_info finfo; 2336 }; 2337 2338 struct rtw89_btc_rpt_fbtc_step { 2339 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2340 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2341 }; 2342 2343 struct rtw89_btc_rpt_fbtc_nullsta { 2344 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2345 union rtw89_btc_fbtc_cynullsta_info finfo; 2346 }; 2347 2348 struct rtw89_btc_rpt_fbtc_mreg { 2349 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2350 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2351 }; 2352 2353 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2354 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2355 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2356 }; 2357 2358 struct rtw89_btc_rpt_fbtc_btver { 2359 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2360 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2361 }; 2362 2363 struct rtw89_btc_rpt_fbtc_btscan { 2364 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2365 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2366 }; 2367 2368 struct rtw89_btc_rpt_fbtc_btafh { 2369 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2370 union rtw89_btc_fbtc_btafh_info finfo; 2371 }; 2372 2373 struct rtw89_btc_rpt_fbtc_btdev { 2374 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2375 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2376 }; 2377 2378 enum rtw89_btc_btfre_type { 2379 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2380 BTFRE_UNDEF_TYPE, 2381 BTFRE_EXCEPTION, 2382 BTFRE_MAX, 2383 }; 2384 2385 struct rtw89_btc_btf_fwinfo { 2386 u32 cnt_c2h; 2387 u32 cnt_h2c; 2388 u32 cnt_h2c_fail; 2389 u32 event[BTF_EVNT_MAX]; 2390 2391 u32 err[BTFRE_MAX]; 2392 u32 len_mismch; 2393 u32 fver_mismch; 2394 u32 rpt_en_map; 2395 2396 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2397 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2398 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2399 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2400 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2401 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2402 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2403 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2404 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2405 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2406 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2407 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2408 }; 2409 2410 struct rtw89_btc_ver { 2411 enum rtw89_core_chip_id chip_id; 2412 u32 fw_ver_code; 2413 2414 u8 fcxbtcrpt; 2415 u8 fcxtdma; 2416 u8 fcxslots; 2417 u8 fcxcysta; 2418 u8 fcxstep; 2419 u8 fcxnullsta; 2420 u8 fcxmreg; 2421 u8 fcxgpiodbg; 2422 u8 fcxbtver; 2423 u8 fcxbtscan; 2424 u8 fcxbtafh; 2425 u8 fcxbtdevinfo; 2426 u8 fwlrole; 2427 u8 frptmap; 2428 u8 fcxctrl; 2429 2430 u16 info_buf; 2431 u8 max_role_num; 2432 }; 2433 2434 #define RTW89_BTC_POLICY_MAXLEN 512 2435 2436 struct rtw89_btc { 2437 const struct rtw89_btc_ver *ver; 2438 2439 struct rtw89_btc_cx cx; 2440 struct rtw89_btc_dm dm; 2441 struct rtw89_btc_ctrl ctrl; 2442 struct rtw89_btc_module mdinfo; 2443 struct rtw89_btc_btf_fwinfo fwinfo; 2444 struct rtw89_btc_dbg dbg; 2445 2446 struct work_struct eapol_notify_work; 2447 struct work_struct arp_notify_work; 2448 struct work_struct dhcp_notify_work; 2449 struct work_struct icmp_notify_work; 2450 2451 u32 bt_req_len; 2452 2453 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2454 u16 policy_len; 2455 u16 policy_type; 2456 bool bt_req_en; 2457 bool update_policy_force; 2458 bool lps; 2459 }; 2460 2461 enum rtw89_ra_mode { 2462 RTW89_RA_MODE_CCK = BIT(0), 2463 RTW89_RA_MODE_OFDM = BIT(1), 2464 RTW89_RA_MODE_HT = BIT(2), 2465 RTW89_RA_MODE_VHT = BIT(3), 2466 RTW89_RA_MODE_HE = BIT(4), 2467 }; 2468 2469 enum rtw89_ra_report_mode { 2470 RTW89_RA_RPT_MODE_LEGACY, 2471 RTW89_RA_RPT_MODE_HT, 2472 RTW89_RA_RPT_MODE_VHT, 2473 RTW89_RA_RPT_MODE_HE, 2474 }; 2475 2476 enum rtw89_dig_noisy_level { 2477 RTW89_DIG_NOISY_LEVEL0 = -1, 2478 RTW89_DIG_NOISY_LEVEL1 = 0, 2479 RTW89_DIG_NOISY_LEVEL2 = 1, 2480 RTW89_DIG_NOISY_LEVEL3 = 2, 2481 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2482 }; 2483 2484 enum rtw89_gi_ltf { 2485 RTW89_GILTF_LGI_4XHE32 = 0, 2486 RTW89_GILTF_SGI_4XHE08 = 1, 2487 RTW89_GILTF_2XHE16 = 2, 2488 RTW89_GILTF_2XHE08 = 3, 2489 RTW89_GILTF_1XHE16 = 4, 2490 RTW89_GILTF_1XHE08 = 5, 2491 RTW89_GILTF_MAX 2492 }; 2493 2494 enum rtw89_rx_frame_type { 2495 RTW89_RX_TYPE_MGNT = 0, 2496 RTW89_RX_TYPE_CTRL = 1, 2497 RTW89_RX_TYPE_DATA = 2, 2498 RTW89_RX_TYPE_RSVD = 3, 2499 }; 2500 2501 struct rtw89_ra_info { 2502 u8 is_dis_ra:1; 2503 /* Bit0 : CCK 2504 * Bit1 : OFDM 2505 * Bit2 : HT 2506 * Bit3 : VHT 2507 * Bit4 : HE 2508 */ 2509 u8 mode_ctrl:5; 2510 u8 bw_cap:2; 2511 u8 macid; 2512 u8 dcm_cap:1; 2513 u8 er_cap:1; 2514 u8 init_rate_lv:2; 2515 u8 upd_all:1; 2516 u8 en_sgi:1; 2517 u8 ldpc_cap:1; 2518 u8 stbc_cap:1; 2519 u8 ss_num:3; 2520 u8 giltf:3; 2521 u8 upd_bw_nss_mask:1; 2522 u8 upd_mask:1; 2523 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2524 /* BFee CSI */ 2525 u8 band_num; 2526 u8 ra_csi_rate_en:1; 2527 u8 fixed_csi_rate_en:1; 2528 u8 cr_tbl_sel:1; 2529 u8 fix_giltf_en:1; 2530 u8 fix_giltf:3; 2531 u8 rsvd2:1; 2532 u8 csi_mcs_ss_idx; 2533 u8 csi_mode:2; 2534 u8 csi_gi_ltf:3; 2535 u8 csi_bw:3; 2536 }; 2537 2538 #define RTW89_PPDU_MAX_USR 4 2539 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2540 #define RTW89_PPDU_MAC_INFO_SIZE 8 2541 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2542 2543 #define RTW89_MAX_RX_AGG_NUM 64 2544 #define RTW89_MAX_TX_AGG_NUM 128 2545 2546 struct rtw89_ampdu_params { 2547 u16 agg_num; 2548 bool amsdu; 2549 }; 2550 2551 struct rtw89_ra_report { 2552 struct rate_info txrate; 2553 u32 bit_rate; 2554 u16 hw_rate; 2555 bool might_fallback_legacy; 2556 }; 2557 2558 DECLARE_EWMA(rssi, 10, 16); 2559 DECLARE_EWMA(evm, 10, 16); 2560 DECLARE_EWMA(snr, 10, 16); 2561 2562 struct rtw89_ba_cam_entry { 2563 struct list_head list; 2564 u8 tid; 2565 }; 2566 2567 #define RTW89_MAX_ADDR_CAM_NUM 128 2568 #define RTW89_MAX_BSSID_CAM_NUM 20 2569 #define RTW89_MAX_SEC_CAM_NUM 128 2570 #define RTW89_MAX_BA_CAM_NUM 8 2571 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2572 2573 struct rtw89_addr_cam_entry { 2574 u8 addr_cam_idx; 2575 u8 offset; 2576 u8 len; 2577 u8 valid : 1; 2578 u8 addr_mask : 6; 2579 u8 wapi : 1; 2580 u8 mask_sel : 2; 2581 u8 bssid_cam_idx: 6; 2582 2583 u8 sec_ent_mode; 2584 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2585 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2586 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2587 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2588 }; 2589 2590 struct rtw89_bssid_cam_entry { 2591 u8 bssid[ETH_ALEN]; 2592 u8 phy_idx; 2593 u8 bssid_cam_idx; 2594 u8 offset; 2595 u8 len; 2596 u8 valid : 1; 2597 u8 num; 2598 }; 2599 2600 struct rtw89_sec_cam_entry { 2601 u8 sec_cam_idx; 2602 u8 offset; 2603 u8 len; 2604 u8 type : 4; 2605 u8 ext_key : 1; 2606 u8 spp_mode : 1; 2607 /* 256 bits */ 2608 u8 key[32]; 2609 }; 2610 2611 struct rtw89_sta { 2612 u8 mac_id; 2613 bool disassoc; 2614 bool er_cap; 2615 struct rtw89_dev *rtwdev; 2616 struct rtw89_vif *rtwvif; 2617 struct rtw89_ra_info ra; 2618 struct rtw89_ra_report ra_report; 2619 int max_agg_wait; 2620 u8 prev_rssi; 2621 struct ewma_rssi avg_rssi; 2622 struct ewma_rssi rssi[RF_PATH_MAX]; 2623 struct ewma_snr avg_snr; 2624 struct ewma_evm evm_min[RF_PATH_MAX]; 2625 struct ewma_evm evm_max[RF_PATH_MAX]; 2626 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2627 struct ieee80211_rx_status rx_status; 2628 u16 rx_hw_rate; 2629 __le32 htc_template; 2630 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2631 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2632 struct list_head ba_cam_list; 2633 struct sk_buff_head roc_queue; 2634 2635 bool use_cfg_mask; 2636 struct cfg80211_bitrate_mask mask; 2637 2638 bool cctl_tx_time; 2639 u32 ampdu_max_time:4; 2640 bool cctl_tx_retry_limit; 2641 u32 data_tx_cnt_lmt:6; 2642 }; 2643 2644 struct rtw89_efuse { 2645 bool valid; 2646 bool power_k_valid; 2647 u8 xtal_cap; 2648 u8 addr[ETH_ALEN]; 2649 u8 rfe_type; 2650 char country_code[2]; 2651 }; 2652 2653 struct rtw89_phy_rate_pattern { 2654 u64 ra_mask; 2655 u16 rate; 2656 u8 ra_mode; 2657 bool enable; 2658 }; 2659 2660 struct rtw89_tx_wait_info { 2661 struct rcu_head rcu_head; 2662 struct completion completion; 2663 bool tx_done; 2664 }; 2665 2666 struct rtw89_tx_skb_data { 2667 struct rtw89_tx_wait_info __rcu *wait; 2668 u8 hci_priv[]; 2669 }; 2670 2671 #define RTW89_ROC_IDLE_TIMEOUT 500 2672 #define RTW89_ROC_TX_TIMEOUT 30 2673 enum rtw89_roc_state { 2674 RTW89_ROC_IDLE, 2675 RTW89_ROC_NORMAL, 2676 RTW89_ROC_MGMT, 2677 }; 2678 2679 struct rtw89_roc { 2680 struct ieee80211_channel chan; 2681 struct delayed_work roc_work; 2682 enum ieee80211_roc_type type; 2683 enum rtw89_roc_state state; 2684 int duration; 2685 }; 2686 2687 #define RTW89_P2P_MAX_NOA_NUM 2 2688 2689 struct rtw89_vif { 2690 struct list_head list; 2691 struct rtw89_dev *rtwdev; 2692 struct rtw89_roc roc; 2693 enum rtw89_sub_entity_idx sub_entity_idx; 2694 enum rtw89_reg_6ghz_power reg_6ghz_power; 2695 2696 u8 mac_id; 2697 u8 port; 2698 u8 mac_addr[ETH_ALEN]; 2699 u8 bssid[ETH_ALEN]; 2700 u8 phy_idx; 2701 u8 mac_idx; 2702 u8 net_type; 2703 u8 wifi_role; 2704 u8 self_role; 2705 u8 wmm; 2706 u8 bcn_hit_cond; 2707 u8 hit_rule; 2708 u8 last_noa_nr; 2709 bool offchan; 2710 bool trigger; 2711 bool lsig_txop; 2712 u8 tgt_ind; 2713 u8 frm_tgt_ind; 2714 bool wowlan_pattern; 2715 bool wowlan_uc; 2716 bool wowlan_magic; 2717 bool is_hesta; 2718 bool last_a_ctrl; 2719 bool dyn_tb_bedge_en; 2720 u8 def_tri_idx; 2721 u32 tdls_peer; 2722 struct work_struct update_beacon_work; 2723 struct rtw89_addr_cam_entry addr_cam; 2724 struct rtw89_bssid_cam_entry bssid_cam; 2725 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 2726 struct rtw89_traffic_stats stats; 2727 struct rtw89_phy_rate_pattern rate_pattern; 2728 struct cfg80211_scan_request *scan_req; 2729 struct ieee80211_scan_ies *scan_ies; 2730 struct list_head general_pkt_list; 2731 }; 2732 2733 enum rtw89_lv1_rcvy_step { 2734 RTW89_LV1_RCVY_STEP_1, 2735 RTW89_LV1_RCVY_STEP_2, 2736 }; 2737 2738 struct rtw89_hci_ops { 2739 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2740 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2741 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2742 void (*reset)(struct rtw89_dev *rtwdev); 2743 int (*start)(struct rtw89_dev *rtwdev); 2744 void (*stop)(struct rtw89_dev *rtwdev); 2745 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 2746 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 2747 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2748 2749 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2750 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2751 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2752 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2753 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2754 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2755 2756 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2757 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2758 int (*deinit)(struct rtw89_dev *rtwdev); 2759 2760 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2761 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2762 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2763 int (*napi_poll)(struct napi_struct *napi, int budget); 2764 2765 /* Deal with locks inside recovery_start and recovery_complete callbacks 2766 * by hci instance, and handle things which need to consider under SER. 2767 * e.g. turn on/off interrupts except for the one for halt notification. 2768 */ 2769 void (*recovery_start)(struct rtw89_dev *rtwdev); 2770 void (*recovery_complete)(struct rtw89_dev *rtwdev); 2771 2772 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 2773 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 2774 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 2775 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 2776 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 2777 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 2778 void (*disable_intr)(struct rtw89_dev *rtwdev); 2779 void (*enable_intr)(struct rtw89_dev *rtwdev); 2780 int (*rst_bdram)(struct rtw89_dev *rtwdev); 2781 }; 2782 2783 struct rtw89_hci_info { 2784 const struct rtw89_hci_ops *ops; 2785 enum rtw89_hci_type type; 2786 u32 rpwm_addr; 2787 u32 cpwm_addr; 2788 bool paused; 2789 }; 2790 2791 struct rtw89_chip_ops { 2792 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 2793 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 2794 void (*bb_reset)(struct rtw89_dev *rtwdev, 2795 enum rtw89_phy_idx phy_idx); 2796 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2797 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2798 u32 addr, u32 mask); 2799 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2800 u32 addr, u32 mask, u32 data); 2801 void (*set_channel)(struct rtw89_dev *rtwdev, 2802 const struct rtw89_chan *chan, 2803 enum rtw89_mac_idx mac_idx, 2804 enum rtw89_phy_idx phy_idx); 2805 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2806 struct rtw89_channel_help_params *p, 2807 const struct rtw89_chan *chan, 2808 enum rtw89_mac_idx mac_idx, 2809 enum rtw89_phy_idx phy_idx); 2810 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2811 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2812 void (*fem_setup)(struct rtw89_dev *rtwdev); 2813 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 2814 void (*rfk_init)(struct rtw89_dev *rtwdev); 2815 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2816 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 2817 enum rtw89_phy_idx phy_idx); 2818 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2819 void (*rfk_track)(struct rtw89_dev *rtwdev); 2820 void (*power_trim)(struct rtw89_dev *rtwdev); 2821 void (*set_txpwr)(struct rtw89_dev *rtwdev, 2822 const struct rtw89_chan *chan, 2823 enum rtw89_phy_idx phy_idx); 2824 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 2825 enum rtw89_phy_idx phy_idx); 2826 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2827 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2828 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2829 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2830 struct rtw89_rx_phy_ppdu *phy_ppdu, 2831 struct ieee80211_rx_status *status); 2832 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2833 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 2834 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2835 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2836 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2837 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2838 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 2839 struct rtw89_rx_desc_info *desc_info, 2840 u8 *data, u32 data_offset); 2841 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 2842 struct rtw89_tx_desc_info *desc_info, 2843 void *txdesc); 2844 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 2845 struct rtw89_tx_desc_info *desc_info, 2846 void *txdesc); 2847 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2848 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2849 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2850 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2851 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2852 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2853 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 2854 struct rtw89_vif *rtwvif, 2855 struct rtw89_sta *rtwsta); 2856 2857 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2858 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2859 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2860 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2861 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2862 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2863 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2864 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 2865 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 2866 }; 2867 2868 enum rtw89_dma_ch { 2869 RTW89_DMA_ACH0 = 0, 2870 RTW89_DMA_ACH1 = 1, 2871 RTW89_DMA_ACH2 = 2, 2872 RTW89_DMA_ACH3 = 3, 2873 RTW89_DMA_ACH4 = 4, 2874 RTW89_DMA_ACH5 = 5, 2875 RTW89_DMA_ACH6 = 6, 2876 RTW89_DMA_ACH7 = 7, 2877 RTW89_DMA_B0MG = 8, 2878 RTW89_DMA_B0HI = 9, 2879 RTW89_DMA_B1MG = 10, 2880 RTW89_DMA_B1HI = 11, 2881 RTW89_DMA_H2C = 12, 2882 RTW89_DMA_CH_NUM = 13 2883 }; 2884 2885 enum rtw89_qta_mode { 2886 RTW89_QTA_SCC, 2887 RTW89_QTA_DLFW, 2888 RTW89_QTA_WOW, 2889 2890 /* keep last */ 2891 RTW89_QTA_INVALID, 2892 }; 2893 2894 struct rtw89_hfc_ch_cfg { 2895 u16 min; 2896 u16 max; 2897 #define grp_0 0 2898 #define grp_1 1 2899 #define grp_num 2 2900 u8 grp; 2901 }; 2902 2903 struct rtw89_hfc_ch_info { 2904 u16 aval; 2905 u16 used; 2906 }; 2907 2908 struct rtw89_hfc_pub_cfg { 2909 u16 grp0; 2910 u16 grp1; 2911 u16 pub_max; 2912 u16 wp_thrd; 2913 }; 2914 2915 struct rtw89_hfc_pub_info { 2916 u16 g0_used; 2917 u16 g1_used; 2918 u16 g0_aval; 2919 u16 g1_aval; 2920 u16 pub_aval; 2921 u16 wp_aval; 2922 }; 2923 2924 struct rtw89_hfc_prec_cfg { 2925 u16 ch011_prec; 2926 u16 h2c_prec; 2927 u16 wp_ch07_prec; 2928 u16 wp_ch811_prec; 2929 u8 ch011_full_cond; 2930 u8 h2c_full_cond; 2931 u8 wp_ch07_full_cond; 2932 u8 wp_ch811_full_cond; 2933 }; 2934 2935 struct rtw89_hfc_param { 2936 bool en; 2937 bool h2c_en; 2938 u8 mode; 2939 const struct rtw89_hfc_ch_cfg *ch_cfg; 2940 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2941 struct rtw89_hfc_pub_cfg pub_cfg; 2942 struct rtw89_hfc_pub_info pub_info; 2943 struct rtw89_hfc_prec_cfg prec_cfg; 2944 }; 2945 2946 struct rtw89_hfc_param_ini { 2947 const struct rtw89_hfc_ch_cfg *ch_cfg; 2948 const struct rtw89_hfc_pub_cfg *pub_cfg; 2949 const struct rtw89_hfc_prec_cfg *prec_cfg; 2950 u8 mode; 2951 }; 2952 2953 struct rtw89_dle_size { 2954 u16 pge_size; 2955 u16 lnk_pge_num; 2956 u16 unlnk_pge_num; 2957 }; 2958 2959 struct rtw89_wde_quota { 2960 u16 hif; 2961 u16 wcpu; 2962 u16 pkt_in; 2963 u16 cpu_io; 2964 }; 2965 2966 struct rtw89_ple_quota { 2967 u16 cma0_tx; 2968 u16 cma1_tx; 2969 u16 c2h; 2970 u16 h2c; 2971 u16 wcpu; 2972 u16 mpdu_proc; 2973 u16 cma0_dma; 2974 u16 cma1_dma; 2975 u16 bb_rpt; 2976 u16 wd_rel; 2977 u16 cpu_io; 2978 u16 tx_rpt; 2979 }; 2980 2981 struct rtw89_dle_mem { 2982 enum rtw89_qta_mode mode; 2983 const struct rtw89_dle_size *wde_size; 2984 const struct rtw89_dle_size *ple_size; 2985 const struct rtw89_wde_quota *wde_min_qt; 2986 const struct rtw89_wde_quota *wde_max_qt; 2987 const struct rtw89_ple_quota *ple_min_qt; 2988 const struct rtw89_ple_quota *ple_max_qt; 2989 }; 2990 2991 struct rtw89_reg_def { 2992 u32 addr; 2993 u32 mask; 2994 }; 2995 2996 struct rtw89_reg2_def { 2997 u32 addr; 2998 u32 data; 2999 }; 3000 3001 struct rtw89_reg3_def { 3002 u32 addr; 3003 u32 mask; 3004 u32 data; 3005 }; 3006 3007 struct rtw89_reg5_def { 3008 u8 flag; /* recognized by parsers */ 3009 u8 path; 3010 u32 addr; 3011 u32 mask; 3012 u32 data; 3013 }; 3014 3015 struct rtw89_phy_table { 3016 const struct rtw89_reg2_def *regs; 3017 u32 n_regs; 3018 enum rtw89_rf_path rf_path; 3019 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3020 enum rtw89_rf_path rf_path, void *data); 3021 }; 3022 3023 struct rtw89_txpwr_table { 3024 const void *data; 3025 u32 size; 3026 void (*load)(struct rtw89_dev *rtwdev, 3027 const struct rtw89_txpwr_table *tbl); 3028 }; 3029 3030 struct rtw89_txpwr_rule_2ghz { 3031 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3032 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3033 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3034 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3035 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3036 }; 3037 3038 struct rtw89_txpwr_rule_5ghz { 3039 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3040 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3041 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3042 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3043 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3044 }; 3045 3046 struct rtw89_txpwr_rule_6ghz { 3047 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3048 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3049 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3050 [RTW89_6G_CH_NUM]; 3051 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3052 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3053 [RTW89_6G_CH_NUM]; 3054 }; 3055 3056 struct rtw89_rfe_parms { 3057 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3058 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3059 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3060 }; 3061 3062 struct rtw89_rfe_parms_conf { 3063 const struct rtw89_rfe_parms *rfe_parms; 3064 u8 rfe_type; 3065 }; 3066 3067 struct rtw89_page_regs { 3068 u32 hci_fc_ctrl; 3069 u32 ch_page_ctrl; 3070 u32 ach_page_ctrl; 3071 u32 ach_page_info; 3072 u32 pub_page_info3; 3073 u32 pub_page_ctrl1; 3074 u32 pub_page_ctrl2; 3075 u32 pub_page_info1; 3076 u32 pub_page_info2; 3077 u32 wp_page_ctrl1; 3078 u32 wp_page_ctrl2; 3079 u32 wp_page_info1; 3080 }; 3081 3082 struct rtw89_imr_info { 3083 u32 wdrls_imr_set; 3084 u32 wsec_imr_reg; 3085 u32 wsec_imr_set; 3086 u32 mpdu_tx_imr_set; 3087 u32 mpdu_rx_imr_set; 3088 u32 sta_sch_imr_set; 3089 u32 txpktctl_imr_b0_reg; 3090 u32 txpktctl_imr_b0_clr; 3091 u32 txpktctl_imr_b0_set; 3092 u32 txpktctl_imr_b1_reg; 3093 u32 txpktctl_imr_b1_clr; 3094 u32 txpktctl_imr_b1_set; 3095 u32 wde_imr_clr; 3096 u32 wde_imr_set; 3097 u32 ple_imr_clr; 3098 u32 ple_imr_set; 3099 u32 host_disp_imr_clr; 3100 u32 host_disp_imr_set; 3101 u32 cpu_disp_imr_clr; 3102 u32 cpu_disp_imr_set; 3103 u32 other_disp_imr_clr; 3104 u32 other_disp_imr_set; 3105 u32 bbrpt_com_err_imr_reg; 3106 u32 bbrpt_chinfo_err_imr_reg; 3107 u32 bbrpt_err_imr_set; 3108 u32 bbrpt_dfs_err_imr_reg; 3109 u32 ptcl_imr_clr; 3110 u32 ptcl_imr_set; 3111 u32 cdma_imr_0_reg; 3112 u32 cdma_imr_0_clr; 3113 u32 cdma_imr_0_set; 3114 u32 cdma_imr_1_reg; 3115 u32 cdma_imr_1_clr; 3116 u32 cdma_imr_1_set; 3117 u32 phy_intf_imr_reg; 3118 u32 phy_intf_imr_clr; 3119 u32 phy_intf_imr_set; 3120 u32 rmac_imr_reg; 3121 u32 rmac_imr_clr; 3122 u32 rmac_imr_set; 3123 u32 tmac_imr_reg; 3124 u32 tmac_imr_clr; 3125 u32 tmac_imr_set; 3126 }; 3127 3128 struct rtw89_xtal_info { 3129 u32 xcap_reg; 3130 u32 sc_xo_mask; 3131 u32 sc_xi_mask; 3132 }; 3133 3134 struct rtw89_rrsr_cfgs { 3135 struct rtw89_reg3_def ref_rate; 3136 struct rtw89_reg3_def rsc; 3137 }; 3138 3139 struct rtw89_dig_regs { 3140 u32 seg0_pd_reg; 3141 u32 pd_lower_bound_mask; 3142 u32 pd_spatial_reuse_en; 3143 struct rtw89_reg_def p0_lna_init; 3144 struct rtw89_reg_def p1_lna_init; 3145 struct rtw89_reg_def p0_tia_init; 3146 struct rtw89_reg_def p1_tia_init; 3147 struct rtw89_reg_def p0_rxb_init; 3148 struct rtw89_reg_def p1_rxb_init; 3149 struct rtw89_reg_def p0_p20_pagcugc_en; 3150 struct rtw89_reg_def p0_s20_pagcugc_en; 3151 struct rtw89_reg_def p1_p20_pagcugc_en; 3152 struct rtw89_reg_def p1_s20_pagcugc_en; 3153 }; 3154 3155 struct rtw89_phy_ul_tb_info { 3156 bool dyn_tb_tri_en; 3157 u8 def_if_bandedge; 3158 }; 3159 3160 struct rtw89_antdiv_stats { 3161 struct ewma_rssi cck_rssi_avg; 3162 struct ewma_rssi ofdm_rssi_avg; 3163 struct ewma_rssi non_legacy_rssi_avg; 3164 u16 pkt_cnt_cck; 3165 u16 pkt_cnt_ofdm; 3166 u16 pkt_cnt_non_legacy; 3167 u32 evm; 3168 }; 3169 3170 struct rtw89_antdiv_info { 3171 struct rtw89_antdiv_stats target_stats; 3172 struct rtw89_antdiv_stats main_stats; 3173 struct rtw89_antdiv_stats aux_stats; 3174 u8 training_count; 3175 u8 rssi_pre; 3176 bool get_stats; 3177 }; 3178 3179 struct rtw89_chip_info { 3180 enum rtw89_core_chip_id chip_id; 3181 const struct rtw89_chip_ops *ops; 3182 const char *fw_basename; 3183 u8 fw_format_max; 3184 bool try_ce_fw; 3185 u32 fifo_size; 3186 bool small_fifo_size; 3187 u32 dle_scc_rsvd_size; 3188 u16 max_amsdu_limit; 3189 bool dis_2g_40m_ul_ofdma; 3190 u32 rsvd_ple_ofst; 3191 const struct rtw89_hfc_param_ini *hfc_param_ini; 3192 const struct rtw89_dle_mem *dle_mem; 3193 u8 wde_qempty_acq_num; 3194 u8 wde_qempty_mgq_sel; 3195 u32 rf_base_addr[2]; 3196 u8 support_chanctx_num; 3197 u8 support_bands; 3198 bool support_bw160; 3199 bool support_unii4; 3200 bool support_ul_tb_ctrl; 3201 bool hw_sec_hdr; 3202 u8 rf_path_num; 3203 u8 tx_nss; 3204 u8 rx_nss; 3205 u8 acam_num; 3206 u8 bcam_num; 3207 u8 scam_num; 3208 u8 bacam_num; 3209 u8 bacam_dynamic_num; 3210 enum rtw89_bacam_ver bacam_ver; 3211 3212 u8 sec_ctrl_efuse_size; 3213 u32 physical_efuse_size; 3214 u32 logical_efuse_size; 3215 u32 limit_efuse_size; 3216 u32 dav_phy_efuse_size; 3217 u32 dav_log_efuse_size; 3218 u32 phycap_addr; 3219 u32 phycap_size; 3220 3221 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3222 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3223 const struct rtw89_phy_table *bb_table; 3224 const struct rtw89_phy_table *bb_gain_table; 3225 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3226 const struct rtw89_phy_table *nctl_table; 3227 const struct rtw89_rfk_tbl *nctl_post_table; 3228 const struct rtw89_txpwr_table *byr_table; 3229 const struct rtw89_phy_dig_gain_table *dig_table; 3230 const struct rtw89_dig_regs *dig_regs; 3231 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3232 3233 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3234 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3235 const struct rtw89_rfe_parms *dflt_parms; 3236 3237 u8 txpwr_factor_rf; 3238 u8 txpwr_factor_mac; 3239 3240 u32 para_ver; 3241 u32 wlcx_desired; 3242 u8 btcx_desired; 3243 u8 scbd; 3244 u8 mailbox; 3245 3246 u8 afh_guard_ch; 3247 const u8 *wl_rssi_thres; 3248 const u8 *bt_rssi_thres; 3249 u8 rssi_tol; 3250 3251 u8 mon_reg_num; 3252 const struct rtw89_btc_fbtc_mreg *mon_reg; 3253 u8 rf_para_ulink_num; 3254 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3255 u8 rf_para_dlink_num; 3256 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3257 u8 ps_mode_supported; 3258 u8 low_power_hci_modes; 3259 3260 u32 h2c_cctl_func_id; 3261 u32 hci_func_en_addr; 3262 u32 h2c_desc_size; 3263 u32 txwd_body_size; 3264 u32 h2c_ctrl_reg; 3265 const u32 *h2c_regs; 3266 struct rtw89_reg_def h2c_counter_reg; 3267 u32 c2h_ctrl_reg; 3268 const u32 *c2h_regs; 3269 struct rtw89_reg_def c2h_counter_reg; 3270 const struct rtw89_page_regs *page_regs; 3271 bool cfo_src_fd; 3272 bool cfo_hw_comp; 3273 const struct rtw89_reg_def *dcfo_comp; 3274 u8 dcfo_comp_sft; 3275 const struct rtw89_imr_info *imr_info; 3276 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3277 u32 bss_clr_map_reg; 3278 u32 dma_ch_mask; 3279 u32 edcca_lvl_reg; 3280 const struct wiphy_wowlan_support *wowlan_stub; 3281 const struct rtw89_xtal_info *xtal_info; 3282 }; 3283 3284 union rtw89_bus_info { 3285 const struct rtw89_pci_info *pci; 3286 }; 3287 3288 struct rtw89_driver_info { 3289 const struct rtw89_chip_info *chip; 3290 union rtw89_bus_info bus; 3291 }; 3292 3293 enum rtw89_hcifc_mode { 3294 RTW89_HCIFC_POH = 0, 3295 RTW89_HCIFC_STF = 1, 3296 RTW89_HCIFC_SDIO = 2, 3297 3298 /* keep last */ 3299 RTW89_HCIFC_MODE_INVALID, 3300 }; 3301 3302 struct rtw89_dle_info { 3303 enum rtw89_qta_mode qta_mode; 3304 u16 wde_pg_size; 3305 u16 ple_pg_size; 3306 u16 c0_rx_qta; 3307 u16 c1_rx_qta; 3308 }; 3309 3310 enum rtw89_host_rpr_mode { 3311 RTW89_RPR_MODE_POH = 0, 3312 RTW89_RPR_MODE_STF 3313 }; 3314 3315 #define RTW89_COMPLETION_BUF_SIZE 24 3316 #define RTW89_WAIT_COND_IDLE UINT_MAX 3317 3318 struct rtw89_completion_data { 3319 bool err; 3320 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3321 }; 3322 3323 struct rtw89_wait_info { 3324 atomic_t cond; 3325 struct completion completion; 3326 struct rtw89_completion_data data; 3327 }; 3328 3329 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3330 3331 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3332 { 3333 init_completion(&wait->completion); 3334 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3335 } 3336 3337 struct rtw89_mac_info { 3338 struct rtw89_dle_info dle_info; 3339 struct rtw89_hfc_param hfc_param; 3340 enum rtw89_qta_mode qta_mode; 3341 u8 rpwm_seq_num; 3342 u8 cpwm_seq_num; 3343 3344 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 3345 struct rtw89_wait_info fw_ofld_wait; 3346 }; 3347 3348 enum rtw89_fw_type { 3349 RTW89_FW_NORMAL = 1, 3350 RTW89_FW_WOWLAN = 3, 3351 RTW89_FW_NORMAL_CE = 5, 3352 }; 3353 3354 enum rtw89_fw_feature { 3355 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3356 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3357 RTW89_FW_FEATURE_TX_WAKE, 3358 RTW89_FW_FEATURE_CRASH_TRIGGER, 3359 RTW89_FW_FEATURE_NO_PACKET_DROP, 3360 RTW89_FW_FEATURE_NO_DEEP_PS, 3361 RTW89_FW_FEATURE_NO_LPS_PG, 3362 RTW89_FW_FEATURE_BEACON_FILTER, 3363 }; 3364 3365 struct rtw89_fw_suit { 3366 const u8 *data; 3367 u32 size; 3368 u8 major_ver; 3369 u8 minor_ver; 3370 u8 sub_ver; 3371 u8 sub_idex; 3372 u16 build_year; 3373 u16 build_mon; 3374 u16 build_date; 3375 u16 build_hour; 3376 u16 build_min; 3377 u8 cmd_ver; 3378 }; 3379 3380 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3381 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3382 #define RTW89_FW_SUIT_VER_CODE(s) \ 3383 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3384 3385 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3386 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3387 (mfw_hdr)->ver.minor, \ 3388 (mfw_hdr)->ver.sub, \ 3389 (mfw_hdr)->ver.idx) 3390 3391 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3392 RTW89_FW_VER_CODE(GET_FW_HDR_MAJOR_VERSION(fw_hdr), \ 3393 GET_FW_HDR_MINOR_VERSION(fw_hdr), \ 3394 GET_FW_HDR_SUBVERSION(fw_hdr), \ 3395 GET_FW_HDR_SUBINDEX(fw_hdr)) 3396 3397 struct rtw89_fw_req_info { 3398 const struct firmware *firmware; 3399 struct completion completion; 3400 }; 3401 3402 struct rtw89_fw_info { 3403 struct rtw89_fw_req_info req; 3404 int fw_format; 3405 u8 h2c_seq; 3406 u8 rec_seq; 3407 u8 h2c_counter; 3408 u8 c2h_counter; 3409 struct rtw89_fw_suit normal; 3410 struct rtw89_fw_suit wowlan; 3411 bool fw_log_enable; 3412 u32 feature_map; 3413 }; 3414 3415 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3416 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3417 3418 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3419 ((_fw)->feature_map |= BIT(_fw_feature)) 3420 3421 struct rtw89_cam_info { 3422 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3423 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3424 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3425 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3426 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3427 }; 3428 3429 enum rtw89_sar_sources { 3430 RTW89_SAR_SOURCE_NONE, 3431 RTW89_SAR_SOURCE_COMMON, 3432 3433 RTW89_SAR_SOURCE_NR, 3434 }; 3435 3436 enum rtw89_sar_subband { 3437 RTW89_SAR_2GHZ_SUBBAND, 3438 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3439 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 3440 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 3441 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 3442 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 3443 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 3444 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 3445 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 3446 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 3447 3448 RTW89_SAR_SUBBAND_NR, 3449 }; 3450 3451 struct rtw89_sar_cfg_common { 3452 bool set[RTW89_SAR_SUBBAND_NR]; 3453 s32 cfg[RTW89_SAR_SUBBAND_NR]; 3454 }; 3455 3456 struct rtw89_sar_info { 3457 /* used to decide how to acces SAR cfg union */ 3458 enum rtw89_sar_sources src; 3459 3460 /* reserved for different knids of SAR cfg struct. 3461 * supposed that a single cfg struct cannot handle various SAR sources. 3462 */ 3463 union { 3464 struct rtw89_sar_cfg_common cfg_common; 3465 }; 3466 }; 3467 3468 struct rtw89_chanctx_cfg { 3469 enum rtw89_sub_entity_idx idx; 3470 }; 3471 3472 enum rtw89_entity_mode { 3473 RTW89_ENTITY_MODE_SCC, 3474 }; 3475 3476 struct rtw89_sub_entity { 3477 struct cfg80211_chan_def chandef; 3478 struct rtw89_chan chan; 3479 struct rtw89_chan_rcd rcd; 3480 struct rtw89_chanctx_cfg *cfg; 3481 }; 3482 3483 struct rtw89_hal { 3484 u32 rx_fltr; 3485 u8 cv; 3486 u8 acv; 3487 u32 sw_amsdu_max_size; 3488 u32 antenna_tx; 3489 u32 antenna_rx; 3490 u8 tx_nss; 3491 u8 rx_nss; 3492 bool tx_path_diversity; 3493 bool ant_diversity; 3494 bool ant_diversity_fixed; 3495 bool support_cckpd; 3496 bool support_igi; 3497 atomic_t roc_entity_idx; 3498 3499 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 3500 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 3501 struct cfg80211_chan_def roc_chandef; 3502 3503 bool entity_active; 3504 enum rtw89_entity_mode entity_mode; 3505 3506 u32 edcca_bak; 3507 }; 3508 3509 #define RTW89_MAX_MAC_ID_NUM 128 3510 #define RTW89_MAX_PKT_OFLD_NUM 255 3511 3512 enum rtw89_flags { 3513 RTW89_FLAG_POWERON, 3514 RTW89_FLAG_FW_RDY, 3515 RTW89_FLAG_RUNNING, 3516 RTW89_FLAG_BFEE_MON, 3517 RTW89_FLAG_BFEE_EN, 3518 RTW89_FLAG_BFEE_TIMER_KEEP, 3519 RTW89_FLAG_NAPI_RUNNING, 3520 RTW89_FLAG_LEISURE_PS, 3521 RTW89_FLAG_LOW_POWER_MODE, 3522 RTW89_FLAG_INACTIVE_PS, 3523 RTW89_FLAG_CRASH_SIMULATING, 3524 RTW89_FLAG_SER_HANDLING, 3525 RTW89_FLAG_WOWLAN, 3526 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 3527 RTW89_FLAG_CHANGING_INTERFACE, 3528 3529 NUM_OF_RTW89_FLAGS, 3530 }; 3531 3532 enum rtw89_pkt_drop_sel { 3533 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 3534 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 3535 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 3536 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 3537 RTW89_PKT_DROP_SEL_MACID_ALL, 3538 RTW89_PKT_DROP_SEL_MG0_ONCE, 3539 RTW89_PKT_DROP_SEL_HIQ_ONCE, 3540 RTW89_PKT_DROP_SEL_HIQ_PORT, 3541 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 3542 RTW89_PKT_DROP_SEL_BAND, 3543 RTW89_PKT_DROP_SEL_BAND_ONCE, 3544 RTW89_PKT_DROP_SEL_REL_MACID, 3545 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 3546 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 3547 }; 3548 3549 struct rtw89_pkt_drop_params { 3550 enum rtw89_pkt_drop_sel sel; 3551 enum rtw89_mac_idx mac_band; 3552 u8 macid; 3553 u8 port; 3554 u8 mbssid; 3555 bool tf_trs; 3556 u32 macid_band_sel[4]; 3557 }; 3558 3559 struct rtw89_pkt_stat { 3560 u16 beacon_nr; 3561 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 3562 }; 3563 3564 DECLARE_EWMA(thermal, 4, 4); 3565 3566 struct rtw89_phy_stat { 3567 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 3568 struct rtw89_pkt_stat cur_pkt_stat; 3569 struct rtw89_pkt_stat last_pkt_stat; 3570 }; 3571 3572 #define RTW89_DACK_PATH_NR 2 3573 #define RTW89_DACK_IDX_NR 2 3574 #define RTW89_DACK_MSBK_NR 16 3575 struct rtw89_dack_info { 3576 bool dack_done; 3577 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 3578 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3579 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3580 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 3581 u32 dack_cnt; 3582 bool addck_timeout[RTW89_DACK_PATH_NR]; 3583 bool dadck_timeout[RTW89_DACK_PATH_NR]; 3584 bool msbk_timeout[RTW89_DACK_PATH_NR]; 3585 }; 3586 3587 #define RTW89_IQK_CHS_NR 2 3588 #define RTW89_IQK_PATH_NR 4 3589 3590 struct rtw89_rfk_mcc_info { 3591 u8 ch[RTW89_IQK_CHS_NR]; 3592 u8 band[RTW89_IQK_CHS_NR]; 3593 u8 table_idx; 3594 }; 3595 3596 struct rtw89_lck_info { 3597 u8 thermal[RF_PATH_MAX]; 3598 }; 3599 3600 struct rtw89_rx_dck_info { 3601 u8 thermal[RF_PATH_MAX]; 3602 }; 3603 3604 struct rtw89_iqk_info { 3605 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3606 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3607 bool lok_fail[RTW89_IQK_PATH_NR]; 3608 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3609 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3610 u32 iqk_fail_cnt; 3611 bool is_iqk_init; 3612 u32 iqk_channel[RTW89_IQK_CHS_NR]; 3613 u8 iqk_band[RTW89_IQK_PATH_NR]; 3614 u8 iqk_ch[RTW89_IQK_PATH_NR]; 3615 u8 iqk_bw[RTW89_IQK_PATH_NR]; 3616 u8 kcount; 3617 u8 iqk_times; 3618 u8 version; 3619 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 3620 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 3621 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 3622 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 3623 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 3624 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 3625 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 3626 bool is_nbiqk; 3627 bool iqk_fft_en; 3628 bool iqk_xym_en; 3629 bool iqk_sram_en; 3630 bool iqk_cfir_en; 3631 u8 thermal[RTW89_IQK_PATH_NR]; 3632 bool thermal_rek_en; 3633 u32 syn1to2; 3634 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3635 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 3636 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3637 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 3638 }; 3639 3640 #define RTW89_DPK_RF_PATH 2 3641 #define RTW89_DPK_AVG_THERMAL_NUM 8 3642 #define RTW89_DPK_BKUP_NUM 2 3643 struct rtw89_dpk_bkup_para { 3644 enum rtw89_band band; 3645 enum rtw89_bandwidth bw; 3646 u8 ch; 3647 bool path_ok; 3648 u8 mdpd_en; 3649 u8 txagc_dpk; 3650 u8 ther_dpk; 3651 u8 gs; 3652 u16 pwsf; 3653 }; 3654 3655 struct rtw89_dpk_info { 3656 bool is_dpk_enable; 3657 bool is_dpk_reload_en; 3658 u8 dpk_gs[RTW89_PHY_MAX]; 3659 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3660 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3661 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3662 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3663 u8 cur_idx[RTW89_DPK_RF_PATH]; 3664 u8 cur_k_set; 3665 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 3666 }; 3667 3668 struct rtw89_fem_info { 3669 bool elna_2g; 3670 bool elna_5g; 3671 bool epa_2g; 3672 bool epa_5g; 3673 bool epa_6g; 3674 }; 3675 3676 struct rtw89_phy_ch_info { 3677 u8 rssi_min; 3678 u16 rssi_min_macid; 3679 u8 pre_rssi_min; 3680 u8 rssi_max; 3681 u16 rssi_max_macid; 3682 u8 rxsc_160; 3683 u8 rxsc_80; 3684 u8 rxsc_40; 3685 u8 rxsc_20; 3686 u8 rxsc_l; 3687 u8 is_noisy; 3688 }; 3689 3690 struct rtw89_agc_gaincode_set { 3691 u8 lna_idx; 3692 u8 tia_idx; 3693 u8 rxb_idx; 3694 }; 3695 3696 #define IGI_RSSI_TH_NUM 5 3697 #define FA_TH_NUM 4 3698 #define LNA_GAIN_NUM 7 3699 #define TIA_GAIN_NUM 2 3700 struct rtw89_dig_info { 3701 struct rtw89_agc_gaincode_set cur_gaincode; 3702 bool force_gaincode_idx_en; 3703 struct rtw89_agc_gaincode_set force_gaincode; 3704 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 3705 u16 fa_th[FA_TH_NUM]; 3706 u8 igi_rssi; 3707 u8 igi_fa_rssi; 3708 u8 fa_rssi_ofst; 3709 u8 dyn_igi_max; 3710 u8 dyn_igi_min; 3711 bool dyn_pd_th_en; 3712 u8 dyn_pd_th_max; 3713 u8 pd_low_th_ofst; 3714 u8 ib_pbk; 3715 s8 ib_pkpwr; 3716 s8 lna_gain_a[LNA_GAIN_NUM]; 3717 s8 lna_gain_g[LNA_GAIN_NUM]; 3718 s8 *lna_gain; 3719 s8 tia_gain_a[TIA_GAIN_NUM]; 3720 s8 tia_gain_g[TIA_GAIN_NUM]; 3721 s8 *tia_gain; 3722 bool is_linked_pre; 3723 bool bypass_dig; 3724 }; 3725 3726 enum rtw89_multi_cfo_mode { 3727 RTW89_PKT_BASED_AVG_MODE = 0, 3728 RTW89_ENTRY_BASED_AVG_MODE = 1, 3729 RTW89_TP_BASED_AVG_MODE = 2, 3730 }; 3731 3732 enum rtw89_phy_cfo_status { 3733 RTW89_PHY_DCFO_STATE_NORMAL = 0, 3734 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 3735 RTW89_PHY_DCFO_STATE_HOLD = 2, 3736 RTW89_PHY_DCFO_STATE_MAX 3737 }; 3738 3739 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 3740 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 3741 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 3742 }; 3743 3744 struct rtw89_cfo_tracking_info { 3745 u16 cfo_timer_ms; 3746 bool cfo_trig_by_timer_en; 3747 enum rtw89_phy_cfo_status phy_cfo_status; 3748 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 3749 u8 phy_cfo_trk_cnt; 3750 bool is_adjust; 3751 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 3752 bool apply_compensation; 3753 u8 crystal_cap; 3754 u8 crystal_cap_default; 3755 u8 def_x_cap; 3756 s8 x_cap_ofst; 3757 u32 sta_cfo_tolerance; 3758 s32 cfo_tail[CFO_TRACK_MAX_USER]; 3759 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 3760 s32 cfo_avg_pre; 3761 s32 cfo_avg[CFO_TRACK_MAX_USER]; 3762 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 3763 s32 dcfo_avg; 3764 s32 dcfo_avg_pre; 3765 u32 packet_count; 3766 u32 packet_count_pre; 3767 s32 residual_cfo_acc; 3768 u8 phy_cfotrk_state; 3769 u8 phy_cfotrk_cnt; 3770 bool divergence_lock_en; 3771 u8 x_cap_lb; 3772 u8 x_cap_ub; 3773 u8 lock_cnt; 3774 }; 3775 3776 enum rtw89_tssi_alimk_band { 3777 TSSI_ALIMK_2G = 0, 3778 TSSI_ALIMK_5GL, 3779 TSSI_ALIMK_5GM, 3780 TSSI_ALIMK_5GH, 3781 TSSI_ALIMK_MAX 3782 }; 3783 3784 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 3785 #define TSSI_TRIM_CH_GROUP_NUM 8 3786 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 3787 3788 #define TSSI_CCK_CH_GROUP_NUM 6 3789 #define TSSI_MCS_2G_CH_GROUP_NUM 5 3790 #define TSSI_MCS_5G_CH_GROUP_NUM 14 3791 #define TSSI_MCS_6G_CH_GROUP_NUM 32 3792 #define TSSI_MCS_CH_GROUP_NUM \ 3793 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 3794 #define TSSI_MAX_CH_NUM 67 3795 #define TSSI_ALIMK_VALUE_NUM 8 3796 3797 struct rtw89_tssi_info { 3798 u8 thermal[RF_PATH_MAX]; 3799 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 3800 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 3801 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 3802 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 3803 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 3804 s8 extra_ofst[RF_PATH_MAX]; 3805 bool tssi_tracking_check[RF_PATH_MAX]; 3806 u8 default_txagc_offset[RF_PATH_MAX]; 3807 u32 base_thermal[RF_PATH_MAX]; 3808 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 3809 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 3810 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 3811 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 3812 u32 tssi_alimk_time; 3813 }; 3814 3815 struct rtw89_power_trim_info { 3816 bool pg_thermal_trim; 3817 bool pg_pa_bias_trim; 3818 u8 thermal_trim[RF_PATH_MAX]; 3819 u8 pa_bias_trim[RF_PATH_MAX]; 3820 }; 3821 3822 struct rtw89_regd { 3823 char alpha2[3]; 3824 u8 txpwr_regd[RTW89_BAND_MAX]; 3825 }; 3826 3827 struct rtw89_regulatory_info { 3828 const struct rtw89_regd *regd; 3829 enum rtw89_reg_6ghz_power reg_6ghz_power; 3830 }; 3831 3832 enum rtw89_ifs_clm_application { 3833 RTW89_IFS_CLM_INIT = 0, 3834 RTW89_IFS_CLM_BACKGROUND = 1, 3835 RTW89_IFS_CLM_ACS = 2, 3836 RTW89_IFS_CLM_DIG = 3, 3837 RTW89_IFS_CLM_TDMA_DIG = 4, 3838 RTW89_IFS_CLM_DBG = 5, 3839 RTW89_IFS_CLM_DBG_MANUAL = 6 3840 }; 3841 3842 enum rtw89_env_racing_lv { 3843 RTW89_RAC_RELEASE = 0, 3844 RTW89_RAC_LV_1 = 1, 3845 RTW89_RAC_LV_2 = 2, 3846 RTW89_RAC_LV_3 = 3, 3847 RTW89_RAC_LV_4 = 4, 3848 RTW89_RAC_MAX_NUM = 5 3849 }; 3850 3851 struct rtw89_ccx_para_info { 3852 enum rtw89_env_racing_lv rac_lv; 3853 u16 mntr_time; 3854 u8 nhm_manual_th_ofst; 3855 u8 nhm_manual_th0; 3856 enum rtw89_ifs_clm_application ifs_clm_app; 3857 u32 ifs_clm_manual_th_times; 3858 u32 ifs_clm_manual_th0; 3859 u8 fahm_manual_th_ofst; 3860 u8 fahm_manual_th0; 3861 u8 fahm_numer_opt; 3862 u8 fahm_denom_opt; 3863 }; 3864 3865 enum rtw89_ccx_edcca_opt_sc_idx { 3866 RTW89_CCX_EDCCA_SEG0_P0 = 0, 3867 RTW89_CCX_EDCCA_SEG0_S1 = 1, 3868 RTW89_CCX_EDCCA_SEG0_S2 = 2, 3869 RTW89_CCX_EDCCA_SEG0_S3 = 3, 3870 RTW89_CCX_EDCCA_SEG1_P0 = 4, 3871 RTW89_CCX_EDCCA_SEG1_S1 = 5, 3872 RTW89_CCX_EDCCA_SEG1_S2 = 6, 3873 RTW89_CCX_EDCCA_SEG1_S3 = 7 3874 }; 3875 3876 enum rtw89_ccx_edcca_opt_bw_idx { 3877 RTW89_CCX_EDCCA_BW20_0 = 0, 3878 RTW89_CCX_EDCCA_BW20_1 = 1, 3879 RTW89_CCX_EDCCA_BW20_2 = 2, 3880 RTW89_CCX_EDCCA_BW20_3 = 3, 3881 RTW89_CCX_EDCCA_BW20_4 = 4, 3882 RTW89_CCX_EDCCA_BW20_5 = 5, 3883 RTW89_CCX_EDCCA_BW20_6 = 6, 3884 RTW89_CCX_EDCCA_BW20_7 = 7 3885 }; 3886 3887 #define RTW89_NHM_TH_NUM 11 3888 #define RTW89_FAHM_TH_NUM 11 3889 #define RTW89_NHM_RPT_NUM 12 3890 #define RTW89_FAHM_RPT_NUM 12 3891 #define RTW89_IFS_CLM_NUM 4 3892 struct rtw89_env_monitor_info { 3893 u32 ccx_trigger_time; 3894 u64 start_time; 3895 u8 ccx_rpt_stamp; 3896 u8 ccx_watchdog_result; 3897 bool ccx_ongoing; 3898 u8 ccx_rac_lv; 3899 bool ccx_manual_ctrl; 3900 u8 ccx_pre_rssi; 3901 u16 clm_mntr_time; 3902 u16 nhm_mntr_time; 3903 u16 ifs_clm_mntr_time; 3904 enum rtw89_ifs_clm_application ifs_clm_app; 3905 u16 fahm_mntr_time; 3906 u16 edcca_clm_mntr_time; 3907 u16 ccx_period; 3908 u8 ccx_unit_idx; 3909 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 3910 u8 nhm_th[RTW89_NHM_TH_NUM]; 3911 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 3912 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 3913 u8 fahm_numer_opt; 3914 u8 fahm_denom_opt; 3915 u8 fahm_th[RTW89_FAHM_TH_NUM]; 3916 u16 clm_result; 3917 u16 nhm_result[RTW89_NHM_RPT_NUM]; 3918 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 3919 u16 nhm_tx_cnt; 3920 u16 nhm_cca_cnt; 3921 u16 nhm_idle_cnt; 3922 u16 ifs_clm_tx; 3923 u16 ifs_clm_edcca_excl_cca; 3924 u16 ifs_clm_ofdmfa; 3925 u16 ifs_clm_ofdmcca_excl_fa; 3926 u16 ifs_clm_cckfa; 3927 u16 ifs_clm_cckcca_excl_fa; 3928 u16 ifs_clm_total_ifs; 3929 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 3930 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 3931 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 3932 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 3933 u16 fahm_denom_result; 3934 u16 edcca_clm_result; 3935 u8 clm_ratio; 3936 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 3937 u8 nhm_tx_ratio; 3938 u8 nhm_cca_ratio; 3939 u8 nhm_idle_ratio; 3940 u8 nhm_ratio; 3941 u16 nhm_result_sum; 3942 u8 nhm_pwr; 3943 u8 ifs_clm_tx_ratio; 3944 u8 ifs_clm_edcca_excl_cca_ratio; 3945 u8 ifs_clm_cck_fa_ratio; 3946 u8 ifs_clm_ofdm_fa_ratio; 3947 u8 ifs_clm_cck_cca_excl_fa_ratio; 3948 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 3949 u16 ifs_clm_cck_fa_permil; 3950 u16 ifs_clm_ofdm_fa_permil; 3951 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 3952 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 3953 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 3954 u16 fahm_result_sum; 3955 u8 fahm_ratio; 3956 u8 fahm_denom_ratio; 3957 u8 fahm_pwr; 3958 u8 edcca_clm_ratio; 3959 }; 3960 3961 enum rtw89_ser_rcvy_step { 3962 RTW89_SER_DRV_STOP_TX, 3963 RTW89_SER_DRV_STOP_RX, 3964 RTW89_SER_DRV_STOP_RUN, 3965 RTW89_SER_HAL_STOP_DMA, 3966 RTW89_SER_SUPPRESS_LOG, 3967 RTW89_NUM_OF_SER_FLAGS 3968 }; 3969 3970 struct rtw89_ser { 3971 u8 state; 3972 u8 alarm_event; 3973 bool prehandle_l1; 3974 3975 struct work_struct ser_hdl_work; 3976 struct delayed_work ser_alarm_work; 3977 const struct state_ent *st_tbl; 3978 const struct event_ent *ev_tbl; 3979 struct list_head msg_q; 3980 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 3981 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 3982 }; 3983 3984 enum rtw89_mac_ax_ps_mode { 3985 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 3986 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 3987 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 3988 RTW89_MAC_AX_PS_MODE_MAX = 3, 3989 }; 3990 3991 enum rtw89_last_rpwm_mode { 3992 RTW89_LAST_RPWM_PS = 0x0, 3993 RTW89_LAST_RPWM_ACTIVE = 0x6, 3994 }; 3995 3996 struct rtw89_lps_parm { 3997 u8 macid; 3998 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 3999 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4000 }; 4001 4002 struct rtw89_ppdu_sts_info { 4003 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4004 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4005 }; 4006 4007 struct rtw89_early_h2c { 4008 struct list_head list; 4009 u8 *h2c; 4010 u16 h2c_len; 4011 }; 4012 4013 struct rtw89_hw_scan_info { 4014 struct ieee80211_vif *scanning_vif; 4015 struct list_head pkt_list[NUM_NL80211_BANDS]; 4016 struct rtw89_chan op_chan; 4017 u32 last_chan_idx; 4018 }; 4019 4020 enum rtw89_phy_bb_gain_band { 4021 RTW89_BB_GAIN_BAND_2G = 0, 4022 RTW89_BB_GAIN_BAND_5G_L = 1, 4023 RTW89_BB_GAIN_BAND_5G_M = 2, 4024 RTW89_BB_GAIN_BAND_5G_H = 3, 4025 RTW89_BB_GAIN_BAND_6G_L = 4, 4026 RTW89_BB_GAIN_BAND_6G_M = 5, 4027 RTW89_BB_GAIN_BAND_6G_H = 6, 4028 RTW89_BB_GAIN_BAND_6G_UH = 7, 4029 4030 RTW89_BB_GAIN_BAND_NR, 4031 }; 4032 4033 enum rtw89_phy_bb_rxsc_num { 4034 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4035 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4036 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4037 }; 4038 4039 struct rtw89_phy_bb_gain_info { 4040 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4041 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4042 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4043 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4044 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4045 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4046 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4047 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4048 [RTW89_BB_RXSC_NUM_40]; 4049 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4050 [RTW89_BB_RXSC_NUM_80]; 4051 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4052 [RTW89_BB_RXSC_NUM_160]; 4053 }; 4054 4055 struct rtw89_phy_efuse_gain { 4056 bool offset_valid; 4057 bool comp_valid; 4058 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4059 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4060 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4061 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4062 }; 4063 4064 #define RTW89_MAX_PATTERN_NUM 18 4065 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4066 #define RTW89_MAX_PATTERN_SIZE 128 4067 4068 struct rtw89_wow_cam_info { 4069 bool r_w; 4070 u8 idx; 4071 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4072 u16 crc; 4073 bool negative_pattern_match; 4074 bool skip_mac_hdr; 4075 bool uc; 4076 bool mc; 4077 bool bc; 4078 bool valid; 4079 }; 4080 4081 struct rtw89_wow_param { 4082 struct ieee80211_vif *wow_vif; 4083 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4084 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4085 u8 pattern_cnt; 4086 }; 4087 4088 struct rtw89_mcc_info { 4089 struct rtw89_wait_info wait; 4090 }; 4091 4092 struct rtw89_dev { 4093 struct ieee80211_hw *hw; 4094 struct device *dev; 4095 const struct ieee80211_ops *ops; 4096 4097 bool dbcc_en; 4098 struct rtw89_hw_scan_info scan_info; 4099 const struct rtw89_chip_info *chip; 4100 const struct rtw89_pci_info *pci_info; 4101 const struct rtw89_rfe_parms *rfe_parms; 4102 struct rtw89_hal hal; 4103 struct rtw89_mcc_info mcc; 4104 struct rtw89_mac_info mac; 4105 struct rtw89_fw_info fw; 4106 struct rtw89_hci_info hci; 4107 struct rtw89_efuse efuse; 4108 struct rtw89_traffic_stats stats; 4109 4110 /* ensures exclusive access from mac80211 callbacks */ 4111 struct mutex mutex; 4112 struct list_head rtwvifs_list; 4113 /* used to protect rf read write */ 4114 struct mutex rf_mutex; 4115 struct workqueue_struct *txq_wq; 4116 struct work_struct txq_work; 4117 struct delayed_work txq_reinvoke_work; 4118 /* used to protect ba_list and forbid_ba_list */ 4119 spinlock_t ba_lock; 4120 /* txqs to setup ba session */ 4121 struct list_head ba_list; 4122 /* txqs to forbid ba session */ 4123 struct list_head forbid_ba_list; 4124 struct work_struct ba_work; 4125 /* used to protect rpwm */ 4126 spinlock_t rpwm_lock; 4127 4128 struct rtw89_cam_info cam_info; 4129 4130 struct sk_buff_head c2h_queue; 4131 struct work_struct c2h_work; 4132 struct work_struct ips_work; 4133 struct work_struct load_firmware_work; 4134 struct work_struct cancel_6ghz_probe_work; 4135 4136 struct list_head early_h2c_list; 4137 4138 struct rtw89_ser ser; 4139 4140 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4141 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 4142 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 4143 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 4144 4145 struct rtw89_phy_stat phystat; 4146 struct rtw89_dack_info dack; 4147 struct rtw89_iqk_info iqk; 4148 struct rtw89_dpk_info dpk; 4149 struct rtw89_rfk_mcc_info rfk_mcc; 4150 struct rtw89_lck_info lck; 4151 struct rtw89_rx_dck_info rx_dck; 4152 bool is_tssi_mode[RF_PATH_MAX]; 4153 bool is_bt_iqk_timeout; 4154 4155 struct rtw89_fem_info fem; 4156 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 4157 struct rtw89_tssi_info tssi; 4158 struct rtw89_power_trim_info pwr_trim; 4159 4160 struct rtw89_cfo_tracking_info cfo_tracking; 4161 struct rtw89_env_monitor_info env_monitor; 4162 struct rtw89_dig_info dig; 4163 struct rtw89_phy_ch_info ch_info; 4164 struct rtw89_phy_bb_gain_info bb_gain; 4165 struct rtw89_phy_efuse_gain efuse_gain; 4166 struct rtw89_phy_ul_tb_info ul_tb_info; 4167 struct rtw89_antdiv_info antdiv; 4168 4169 struct delayed_work track_work; 4170 struct delayed_work coex_act1_work; 4171 struct delayed_work coex_bt_devinfo_work; 4172 struct delayed_work coex_rfk_chk_work; 4173 struct delayed_work cfo_track_work; 4174 struct delayed_work forbid_ba_work; 4175 struct delayed_work roc_work; 4176 struct delayed_work antdiv_work; 4177 struct rtw89_ppdu_sts_info ppdu_sts; 4178 u8 total_sta_assoc; 4179 bool scanning; 4180 4181 struct rtw89_regulatory_info regulatory; 4182 struct rtw89_sar_info sar; 4183 4184 struct rtw89_btc btc; 4185 enum rtw89_ps_mode ps_mode; 4186 bool lps_enabled; 4187 4188 struct rtw89_wow_param wow; 4189 4190 /* napi structure */ 4191 struct net_device netdev; 4192 struct napi_struct napi; 4193 int napi_budget_countdown; 4194 4195 /* HCI related data, keep last */ 4196 u8 priv[] __aligned(sizeof(void *)); 4197 }; 4198 4199 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4200 struct rtw89_core_tx_request *tx_req) 4201 { 4202 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4203 } 4204 4205 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4206 { 4207 rtwdev->hci.ops->reset(rtwdev); 4208 } 4209 4210 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4211 { 4212 return rtwdev->hci.ops->start(rtwdev); 4213 } 4214 4215 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4216 { 4217 rtwdev->hci.ops->stop(rtwdev); 4218 } 4219 4220 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4221 { 4222 return rtwdev->hci.ops->deinit(rtwdev); 4223 } 4224 4225 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4226 { 4227 rtwdev->hci.ops->pause(rtwdev, pause); 4228 } 4229 4230 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4231 { 4232 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4233 } 4234 4235 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4236 { 4237 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4238 } 4239 4240 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4241 { 4242 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4243 } 4244 4245 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4246 { 4247 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4248 } 4249 4250 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4251 bool drop) 4252 { 4253 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4254 return; 4255 4256 if (rtwdev->hci.ops->flush_queues) 4257 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4258 } 4259 4260 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4261 { 4262 if (rtwdev->hci.ops->recovery_start) 4263 rtwdev->hci.ops->recovery_start(rtwdev); 4264 } 4265 4266 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4267 { 4268 if (rtwdev->hci.ops->recovery_complete) 4269 rtwdev->hci.ops->recovery_complete(rtwdev); 4270 } 4271 4272 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4273 { 4274 if (rtwdev->hci.ops->enable_intr) 4275 rtwdev->hci.ops->enable_intr(rtwdev); 4276 } 4277 4278 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4279 { 4280 if (rtwdev->hci.ops->disable_intr) 4281 rtwdev->hci.ops->disable_intr(rtwdev); 4282 } 4283 4284 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4285 { 4286 if (rtwdev->hci.ops->ctrl_txdma_ch) 4287 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4288 } 4289 4290 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4291 { 4292 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4293 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4294 } 4295 4296 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4297 { 4298 if (rtwdev->hci.ops->ctrl_trxhci) 4299 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4300 } 4301 4302 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4303 { 4304 int ret = 0; 4305 4306 if (rtwdev->hci.ops->poll_txdma_ch) 4307 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4308 return ret; 4309 } 4310 4311 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4312 { 4313 if (rtwdev->hci.ops->clr_idx_all) 4314 rtwdev->hci.ops->clr_idx_all(rtwdev); 4315 } 4316 4317 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4318 { 4319 int ret = 0; 4320 4321 if (rtwdev->hci.ops->rst_bdram) 4322 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4323 return ret; 4324 } 4325 4326 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4327 { 4328 if (rtwdev->hci.ops->clear) 4329 rtwdev->hci.ops->clear(rtwdev, pdev); 4330 } 4331 4332 static inline 4333 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 4334 { 4335 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 4336 4337 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 4338 } 4339 4340 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 4341 { 4342 return rtwdev->hci.ops->read8(rtwdev, addr); 4343 } 4344 4345 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 4346 { 4347 return rtwdev->hci.ops->read16(rtwdev, addr); 4348 } 4349 4350 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 4351 { 4352 return rtwdev->hci.ops->read32(rtwdev, addr); 4353 } 4354 4355 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 4356 { 4357 rtwdev->hci.ops->write8(rtwdev, addr, data); 4358 } 4359 4360 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 4361 { 4362 rtwdev->hci.ops->write16(rtwdev, addr, data); 4363 } 4364 4365 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 4366 { 4367 rtwdev->hci.ops->write32(rtwdev, addr, data); 4368 } 4369 4370 static inline void 4371 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4372 { 4373 u8 val; 4374 4375 val = rtw89_read8(rtwdev, addr); 4376 rtw89_write8(rtwdev, addr, val | bit); 4377 } 4378 4379 static inline void 4380 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4381 { 4382 u16 val; 4383 4384 val = rtw89_read16(rtwdev, addr); 4385 rtw89_write16(rtwdev, addr, val | bit); 4386 } 4387 4388 static inline void 4389 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4390 { 4391 u32 val; 4392 4393 val = rtw89_read32(rtwdev, addr); 4394 rtw89_write32(rtwdev, addr, val | bit); 4395 } 4396 4397 static inline void 4398 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4399 { 4400 u8 val; 4401 4402 val = rtw89_read8(rtwdev, addr); 4403 rtw89_write8(rtwdev, addr, val & ~bit); 4404 } 4405 4406 static inline void 4407 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4408 { 4409 u16 val; 4410 4411 val = rtw89_read16(rtwdev, addr); 4412 rtw89_write16(rtwdev, addr, val & ~bit); 4413 } 4414 4415 static inline void 4416 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4417 { 4418 u32 val; 4419 4420 val = rtw89_read32(rtwdev, addr); 4421 rtw89_write32(rtwdev, addr, val & ~bit); 4422 } 4423 4424 static inline u32 4425 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4426 { 4427 u32 shift = __ffs(mask); 4428 u32 orig; 4429 u32 ret; 4430 4431 orig = rtw89_read32(rtwdev, addr); 4432 ret = (orig & mask) >> shift; 4433 4434 return ret; 4435 } 4436 4437 static inline u16 4438 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4439 { 4440 u32 shift = __ffs(mask); 4441 u32 orig; 4442 u32 ret; 4443 4444 orig = rtw89_read16(rtwdev, addr); 4445 ret = (orig & mask) >> shift; 4446 4447 return ret; 4448 } 4449 4450 static inline u8 4451 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4452 { 4453 u32 shift = __ffs(mask); 4454 u32 orig; 4455 u32 ret; 4456 4457 orig = rtw89_read8(rtwdev, addr); 4458 ret = (orig & mask) >> shift; 4459 4460 return ret; 4461 } 4462 4463 static inline void 4464 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 4465 { 4466 u32 shift = __ffs(mask); 4467 u32 orig; 4468 u32 set; 4469 4470 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 4471 4472 orig = rtw89_read32(rtwdev, addr); 4473 set = (orig & ~mask) | ((data << shift) & mask); 4474 rtw89_write32(rtwdev, addr, set); 4475 } 4476 4477 static inline void 4478 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 4479 { 4480 u32 shift; 4481 u16 orig, set; 4482 4483 mask &= 0xffff; 4484 shift = __ffs(mask); 4485 4486 orig = rtw89_read16(rtwdev, addr); 4487 set = (orig & ~mask) | ((data << shift) & mask); 4488 rtw89_write16(rtwdev, addr, set); 4489 } 4490 4491 static inline void 4492 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 4493 { 4494 u32 shift; 4495 u8 orig, set; 4496 4497 mask &= 0xff; 4498 shift = __ffs(mask); 4499 4500 orig = rtw89_read8(rtwdev, addr); 4501 set = (orig & ~mask) | ((data << shift) & mask); 4502 rtw89_write8(rtwdev, addr, set); 4503 } 4504 4505 static inline u32 4506 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4507 u32 addr, u32 mask) 4508 { 4509 u32 val; 4510 4511 mutex_lock(&rtwdev->rf_mutex); 4512 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 4513 mutex_unlock(&rtwdev->rf_mutex); 4514 4515 return val; 4516 } 4517 4518 static inline void 4519 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4520 u32 addr, u32 mask, u32 data) 4521 { 4522 mutex_lock(&rtwdev->rf_mutex); 4523 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 4524 mutex_unlock(&rtwdev->rf_mutex); 4525 } 4526 4527 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 4528 { 4529 void *p = rtwtxq; 4530 4531 return container_of(p, struct ieee80211_txq, drv_priv); 4532 } 4533 4534 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 4535 struct ieee80211_txq *txq) 4536 { 4537 struct rtw89_txq *rtwtxq; 4538 4539 if (!txq) 4540 return; 4541 4542 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4543 INIT_LIST_HEAD(&rtwtxq->list); 4544 } 4545 4546 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 4547 { 4548 void *p = rtwvif; 4549 4550 return container_of(p, struct ieee80211_vif, drv_priv); 4551 } 4552 4553 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 4554 { 4555 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 4556 } 4557 4558 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 4559 { 4560 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4561 } 4562 4563 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 4564 { 4565 void *p = rtwsta; 4566 4567 return container_of(p, struct ieee80211_sta, drv_priv); 4568 } 4569 4570 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 4571 { 4572 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 4573 } 4574 4575 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 4576 { 4577 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 4578 } 4579 4580 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 4581 { 4582 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 4583 return RATE_INFO_BW_160; 4584 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 4585 return RATE_INFO_BW_80; 4586 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 4587 return RATE_INFO_BW_40; 4588 else 4589 return RATE_INFO_BW_20; 4590 } 4591 4592 static inline 4593 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 4594 { 4595 switch (hw_band) { 4596 default: 4597 case RTW89_BAND_2G: 4598 return NL80211_BAND_2GHZ; 4599 case RTW89_BAND_5G: 4600 return NL80211_BAND_5GHZ; 4601 case RTW89_BAND_6G: 4602 return NL80211_BAND_6GHZ; 4603 } 4604 } 4605 4606 static inline 4607 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 4608 { 4609 switch (nl_band) { 4610 default: 4611 case NL80211_BAND_2GHZ: 4612 return RTW89_BAND_2G; 4613 case NL80211_BAND_5GHZ: 4614 return RTW89_BAND_5G; 4615 case NL80211_BAND_6GHZ: 4616 return RTW89_BAND_6G; 4617 } 4618 } 4619 4620 static inline 4621 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 4622 { 4623 switch (width) { 4624 default: 4625 WARN(1, "Not support bandwidth %d\n", width); 4626 fallthrough; 4627 case NL80211_CHAN_WIDTH_20_NOHT: 4628 case NL80211_CHAN_WIDTH_20: 4629 return RTW89_CHANNEL_WIDTH_20; 4630 case NL80211_CHAN_WIDTH_40: 4631 return RTW89_CHANNEL_WIDTH_40; 4632 case NL80211_CHAN_WIDTH_80: 4633 return RTW89_CHANNEL_WIDTH_80; 4634 case NL80211_CHAN_WIDTH_160: 4635 return RTW89_CHANNEL_WIDTH_160; 4636 } 4637 } 4638 4639 static inline 4640 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 4641 struct rtw89_sta *rtwsta) 4642 { 4643 if (rtwsta) { 4644 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4645 4646 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 4647 return &rtwsta->addr_cam; 4648 } 4649 return &rtwvif->addr_cam; 4650 } 4651 4652 static inline 4653 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 4654 struct rtw89_sta *rtwsta) 4655 { 4656 if (rtwsta) { 4657 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 4658 4659 if (sta->tdls) 4660 return &rtwsta->bssid_cam; 4661 } 4662 return &rtwvif->bssid_cam; 4663 } 4664 4665 static inline 4666 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 4667 struct rtw89_channel_help_params *p, 4668 const struct rtw89_chan *chan, 4669 enum rtw89_mac_idx mac_idx, 4670 enum rtw89_phy_idx phy_idx) 4671 { 4672 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 4673 mac_idx, phy_idx); 4674 } 4675 4676 static inline 4677 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 4678 struct rtw89_channel_help_params *p, 4679 const struct rtw89_chan *chan, 4680 enum rtw89_mac_idx mac_idx, 4681 enum rtw89_phy_idx phy_idx) 4682 { 4683 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 4684 mac_idx, phy_idx); 4685 } 4686 4687 static inline 4688 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 4689 enum rtw89_sub_entity_idx idx) 4690 { 4691 struct rtw89_hal *hal = &rtwdev->hal; 4692 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 4693 4694 if (roc_idx == idx) 4695 return &hal->roc_chandef; 4696 4697 return &hal->sub[idx].chandef; 4698 } 4699 4700 static inline 4701 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 4702 enum rtw89_sub_entity_idx idx) 4703 { 4704 struct rtw89_hal *hal = &rtwdev->hal; 4705 4706 return &hal->sub[idx].chan; 4707 } 4708 4709 static inline 4710 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 4711 enum rtw89_sub_entity_idx idx) 4712 { 4713 struct rtw89_hal *hal = &rtwdev->hal; 4714 4715 return &hal->sub[idx].rcd; 4716 } 4717 4718 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 4719 { 4720 const struct rtw89_chip_info *chip = rtwdev->chip; 4721 4722 if (chip->ops->fem_setup) 4723 chip->ops->fem_setup(rtwdev); 4724 } 4725 4726 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 4727 { 4728 const struct rtw89_chip_info *chip = rtwdev->chip; 4729 4730 if (chip->ops->rfe_gpio) 4731 chip->ops->rfe_gpio(rtwdev); 4732 } 4733 4734 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 4735 { 4736 const struct rtw89_chip_info *chip = rtwdev->chip; 4737 4738 if (chip->ops->bb_sethw) 4739 chip->ops->bb_sethw(rtwdev); 4740 } 4741 4742 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 4743 { 4744 const struct rtw89_chip_info *chip = rtwdev->chip; 4745 4746 if (chip->ops->rfk_init) 4747 chip->ops->rfk_init(rtwdev); 4748 } 4749 4750 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 4751 { 4752 const struct rtw89_chip_info *chip = rtwdev->chip; 4753 4754 if (chip->ops->rfk_channel) 4755 chip->ops->rfk_channel(rtwdev); 4756 } 4757 4758 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 4759 enum rtw89_phy_idx phy_idx) 4760 { 4761 const struct rtw89_chip_info *chip = rtwdev->chip; 4762 4763 if (chip->ops->rfk_band_changed) 4764 chip->ops->rfk_band_changed(rtwdev, phy_idx); 4765 } 4766 4767 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 4768 { 4769 const struct rtw89_chip_info *chip = rtwdev->chip; 4770 4771 if (chip->ops->rfk_scan) 4772 chip->ops->rfk_scan(rtwdev, start); 4773 } 4774 4775 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 4776 { 4777 const struct rtw89_chip_info *chip = rtwdev->chip; 4778 4779 if (chip->ops->rfk_track) 4780 chip->ops->rfk_track(rtwdev); 4781 } 4782 4783 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 4784 { 4785 const struct rtw89_chip_info *chip = rtwdev->chip; 4786 4787 if (chip->ops->set_txpwr_ctrl) 4788 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 4789 } 4790 4791 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 4792 { 4793 const struct rtw89_chip_info *chip = rtwdev->chip; 4794 4795 if (chip->ops->power_trim) 4796 chip->ops->power_trim(rtwdev); 4797 } 4798 4799 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 4800 enum rtw89_phy_idx phy_idx) 4801 { 4802 const struct rtw89_chip_info *chip = rtwdev->chip; 4803 4804 if (chip->ops->init_txpwr_unit) 4805 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 4806 } 4807 4808 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 4809 enum rtw89_rf_path rf_path) 4810 { 4811 const struct rtw89_chip_info *chip = rtwdev->chip; 4812 4813 if (!chip->ops->get_thermal) 4814 return 0x10; 4815 4816 return chip->ops->get_thermal(rtwdev, rf_path); 4817 } 4818 4819 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 4820 struct rtw89_rx_phy_ppdu *phy_ppdu, 4821 struct ieee80211_rx_status *status) 4822 { 4823 const struct rtw89_chip_info *chip = rtwdev->chip; 4824 4825 if (chip->ops->query_ppdu) 4826 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 4827 } 4828 4829 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 4830 bool bt_en) 4831 { 4832 const struct rtw89_chip_info *chip = rtwdev->chip; 4833 4834 if (chip->ops->bb_ctrl_btc_preagc) 4835 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 4836 } 4837 4838 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 4839 { 4840 const struct rtw89_chip_info *chip = rtwdev->chip; 4841 4842 if (chip->ops->cfg_txrx_path) 4843 chip->ops->cfg_txrx_path(rtwdev); 4844 } 4845 4846 static inline 4847 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 4848 struct ieee80211_vif *vif) 4849 { 4850 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4851 const struct rtw89_chip_info *chip = rtwdev->chip; 4852 4853 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 4854 return; 4855 4856 if (chip->ops->set_txpwr_ul_tb_offset) 4857 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 4858 } 4859 4860 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 4861 const struct rtw89_txpwr_table *tbl) 4862 { 4863 tbl->load(rtwdev, tbl); 4864 } 4865 4866 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 4867 { 4868 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 4869 4870 return regd->txpwr_regd[band]; 4871 } 4872 4873 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 4874 { 4875 const struct rtw89_chip_info *chip = rtwdev->chip; 4876 4877 if (chip->ops->ctrl_btg) 4878 chip->ops->ctrl_btg(rtwdev, btg); 4879 } 4880 4881 static inline 4882 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 4883 struct rtw89_rx_desc_info *desc_info, 4884 u8 *data, u32 data_offset) 4885 { 4886 const struct rtw89_chip_info *chip = rtwdev->chip; 4887 4888 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 4889 } 4890 4891 static inline 4892 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 4893 struct rtw89_tx_desc_info *desc_info, 4894 void *txdesc) 4895 { 4896 const struct rtw89_chip_info *chip = rtwdev->chip; 4897 4898 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 4899 } 4900 4901 static inline 4902 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 4903 struct rtw89_tx_desc_info *desc_info, 4904 void *txdesc) 4905 { 4906 const struct rtw89_chip_info *chip = rtwdev->chip; 4907 4908 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 4909 } 4910 4911 static inline 4912 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 4913 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 4914 { 4915 const struct rtw89_chip_info *chip = rtwdev->chip; 4916 4917 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 4918 } 4919 4920 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 4921 { 4922 const struct rtw89_chip_info *chip = rtwdev->chip; 4923 4924 chip->ops->cfg_ctrl_path(rtwdev, wl); 4925 } 4926 4927 static inline 4928 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 4929 u32 *tx_en, enum rtw89_sch_tx_sel sel) 4930 { 4931 const struct rtw89_chip_info *chip = rtwdev->chip; 4932 4933 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 4934 } 4935 4936 static inline 4937 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 4938 { 4939 const struct rtw89_chip_info *chip = rtwdev->chip; 4940 4941 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 4942 } 4943 4944 static inline 4945 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 4946 struct rtw89_vif *rtwvif, 4947 struct rtw89_sta *rtwsta) 4948 { 4949 const struct rtw89_chip_info *chip = rtwdev->chip; 4950 4951 if (!chip->ops->h2c_dctl_sec_cam) 4952 return 0; 4953 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 4954 } 4955 4956 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 4957 { 4958 __le16 fc = hdr->frame_control; 4959 4960 if (ieee80211_has_tods(fc)) 4961 return hdr->addr1; 4962 else if (ieee80211_has_fromds(fc)) 4963 return hdr->addr2; 4964 else 4965 return hdr->addr3; 4966 } 4967 4968 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 4969 { 4970 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 4971 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 4972 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 4973 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 4974 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 4975 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 4976 return true; 4977 return false; 4978 } 4979 4980 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 4981 enum rtw89_fw_type type) 4982 { 4983 struct rtw89_fw_info *fw_info = &rtwdev->fw; 4984 4985 if (type == RTW89_FW_WOWLAN) 4986 return &fw_info->wowlan; 4987 return &fw_info->normal; 4988 } 4989 4990 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 4991 unsigned int length) 4992 { 4993 struct sk_buff *skb; 4994 4995 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 4996 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 4997 if (!skb) 4998 return NULL; 4999 5000 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 5001 return skb; 5002 } 5003 5004 return dev_alloc_skb(length); 5005 } 5006 5007 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 5008 struct rtw89_tx_skb_data *skb_data, 5009 bool tx_done) 5010 { 5011 struct rtw89_tx_wait_info *wait; 5012 5013 rcu_read_lock(); 5014 5015 wait = rcu_dereference(skb_data->wait); 5016 if (!wait) 5017 goto out; 5018 5019 wait->tx_done = tx_done; 5020 complete(&wait->completion); 5021 5022 out: 5023 rcu_read_unlock(); 5024 } 5025 5026 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5027 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 5028 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 5029 struct sk_buff *skb, bool fwdl); 5030 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 5031 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5032 int qsel, unsigned int timeout); 5033 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 5034 struct rtw89_tx_desc_info *desc_info, 5035 void *txdesc); 5036 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 5037 struct rtw89_tx_desc_info *desc_info, 5038 void *txdesc); 5039 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 5040 struct rtw89_tx_desc_info *desc_info, 5041 void *txdesc); 5042 void rtw89_core_rx(struct rtw89_dev *rtwdev, 5043 struct rtw89_rx_desc_info *desc_info, 5044 struct sk_buff *skb); 5045 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 5046 struct rtw89_rx_desc_info *desc_info, 5047 u8 *data, u32 data_offset); 5048 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 5049 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 5050 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 5051 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 5052 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 5053 struct ieee80211_vif *vif, 5054 struct ieee80211_sta *sta); 5055 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 5056 struct ieee80211_vif *vif, 5057 struct ieee80211_sta *sta); 5058 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 5059 struct ieee80211_vif *vif, 5060 struct ieee80211_sta *sta); 5061 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 5062 struct ieee80211_vif *vif, 5063 struct ieee80211_sta *sta); 5064 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 5065 struct ieee80211_vif *vif, 5066 struct ieee80211_sta *sta); 5067 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5068 struct ieee80211_sta *sta, 5069 struct cfg80211_tid_config *tid_config); 5070 int rtw89_core_init(struct rtw89_dev *rtwdev); 5071 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 5072 int rtw89_core_register(struct rtw89_dev *rtwdev); 5073 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 5074 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5075 u32 bus_data_size, 5076 const struct rtw89_chip_info *chip); 5077 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 5078 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 5079 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 5080 void rtw89_set_channel(struct rtw89_dev *rtwdev); 5081 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5082 struct rtw89_chan *chan); 5083 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 5084 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 5085 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 5086 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 5087 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5088 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 5089 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5090 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 5091 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 5092 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 5093 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 5094 int rtw89_regd_init(struct rtw89_dev *rtwdev, 5095 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 5096 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 5097 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 5098 struct rtw89_traffic_stats *stats); 5099 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 5100 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5101 const struct rtw89_completion_data *data); 5102 int rtw89_core_start(struct rtw89_dev *rtwdev); 5103 void rtw89_core_stop(struct rtw89_dev *rtwdev); 5104 void rtw89_core_update_beacon_work(struct work_struct *work); 5105 void rtw89_roc_work(struct work_struct *work); 5106 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5107 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5108 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5109 const u8 *mac_addr, bool hw_scan); 5110 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5111 struct ieee80211_vif *vif, bool hw_scan); 5112 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 5113 struct rtw89_vif *rtwvif, bool active); 5114 5115 #endif 5116