1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_usb_info; 19 struct rtw89_mac_gen_def; 20 struct rtw89_phy_gen_def; 21 struct rtw89_fw_blacklist; 22 struct rtw89_efuse_block_cfg; 23 struct rtw89_h2c_rf_tssi; 24 struct rtw89_fw_txpwr_track_cfg; 25 struct rtw89_phy_rfk_log_fmt; 26 struct rtw89_debugfs; 27 struct rtw89_regd_data; 28 29 extern const struct ieee80211_ops rtw89_ops; 30 31 #define MASKBYTE0 0xff 32 #define MASKBYTE1 0xff00 33 #define MASKBYTE2 0xff0000 34 #define MASKBYTE3 0xff000000 35 #define MASKBYTE4 0xff00000000ULL 36 #define MASKHWORD 0xffff0000 37 #define MASKLWORD 0x0000ffff 38 #define MASKDWORD 0xffffffff 39 #define RFREG_MASK 0xfffff 40 #define INV_RF_DATA 0xffffffff 41 #define BYPASS_CR_DATA 0xbabecafe 42 #define RTW89_R32_EA 0xEAEAEAEA 43 #define RTW89_R32_DEAD 0xDEADBEEF 44 45 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 46 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100) 47 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 48 #define RTW89_PS_HANG_MAX_CNT 3 49 #define CFO_TRACK_MAX_USER 64 50 #define MAX_RSSI 110 51 #define RSSI_FACTOR 1 52 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 53 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 54 #define DELTA_SWINGIDX_SIZE 30 55 56 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 57 #define RTW89_RADIOTAP_ROOM_EHT \ 58 (sizeof(struct ieee80211_radiotap_tlv) + \ 59 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 60 sizeof(struct ieee80211_radiotap_tlv) + \ 61 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 62 #define RTW89_RADIOTAP_ROOM \ 63 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 64 65 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 66 #define RTW89_HTC_VARIANT_HE 3 67 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 68 #define RTW89_HTC_VARIANT_HE_CID_OM 1 69 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 70 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 71 72 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 73 enum htc_om_channel_width { 74 HTC_OM_CHANNEL_WIDTH_20 = 0, 75 HTC_OM_CHANNEL_WIDTH_40 = 1, 76 HTC_OM_CHANNEL_WIDTH_80 = 2, 77 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 78 }; 79 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 80 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 81 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 82 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 83 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 84 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 85 86 #define RTW89_TF_PAD GENMASK(11, 0) 87 #define RTW89_TF_BASIC_USER_INFO_SZ 6 88 89 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 90 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 91 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 92 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 93 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 94 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 95 96 enum rtw89_subband { 97 RTW89_CH_2G = 0, 98 RTW89_CH_5G_BAND_1 = 1, 99 /* RTW89_CH_5G_BAND_2 = 2, unused */ 100 RTW89_CH_5G_BAND_3 = 3, 101 RTW89_CH_5G_BAND_4 = 4, 102 103 RTW89_CH_6G_BAND_IDX0, /* Low */ 104 RTW89_CH_6G_BAND_IDX1, /* Low */ 105 RTW89_CH_6G_BAND_IDX2, /* Mid */ 106 RTW89_CH_6G_BAND_IDX3, /* Mid */ 107 RTW89_CH_6G_BAND_IDX4, /* High */ 108 RTW89_CH_6G_BAND_IDX5, /* High */ 109 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 110 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 111 112 RTW89_SUBBAND_NR, 113 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 114 }; 115 116 enum rtw89_gain_offset { 117 RTW89_GAIN_OFFSET_2G_CCK, 118 RTW89_GAIN_OFFSET_2G_OFDM, 119 RTW89_GAIN_OFFSET_5G_LOW, 120 RTW89_GAIN_OFFSET_5G_MID, 121 RTW89_GAIN_OFFSET_5G_HIGH, 122 RTW89_GAIN_OFFSET_6G_L0, 123 RTW89_GAIN_OFFSET_6G_L1, 124 RTW89_GAIN_OFFSET_6G_M0, 125 RTW89_GAIN_OFFSET_6G_M1, 126 RTW89_GAIN_OFFSET_6G_H0, 127 RTW89_GAIN_OFFSET_6G_H1, 128 RTW89_GAIN_OFFSET_6G_UH0, 129 RTW89_GAIN_OFFSET_6G_UH1, 130 131 RTW89_GAIN_OFFSET_NR, 132 }; 133 134 enum rtw89_hci_type { 135 RTW89_HCI_TYPE_PCIE, 136 RTW89_HCI_TYPE_USB, 137 RTW89_HCI_TYPE_SDIO, 138 139 RTW89_HCI_TYPE_NUM, 140 }; 141 142 enum rtw89_hci_dle_type { 143 RTW89_HCI_DLE_TYPE_PCIE, 144 RTW89_HCI_DLE_TYPE_USB2, 145 RTW89_HCI_DLE_TYPE_USB3, 146 RTW89_HCI_DLE_TYPE_SDIO, 147 148 RTW89_HCI_DLE_TYPE_NUM, 149 }; 150 151 enum rtw89_core_chip_id { 152 RTL8852A, 153 RTL8852B, 154 RTL8852BT, 155 RTL8852C, 156 RTL8851B, 157 RTL8922A, 158 RTL8922D, 159 }; 160 161 enum rtw89_chip_gen { 162 RTW89_CHIP_AX, 163 RTW89_CHIP_BE, 164 165 RTW89_CHIP_GEN_NUM, 166 }; 167 168 enum rtw89_cv { 169 CHIP_CAV, 170 CHIP_CBV, 171 CHIP_CCV, 172 CHIP_CDV, 173 CHIP_CEV, 174 CHIP_CFV, 175 CHIP_CV_MAX, 176 CHIP_CV_INVALID = CHIP_CV_MAX, 177 }; 178 179 enum rtw89_bacam_ver { 180 RTW89_BACAM_V0, 181 RTW89_BACAM_V1, 182 183 RTW89_BACAM_V0_EXT = 99, 184 }; 185 186 enum rtw89_core_tx_type { 187 RTW89_CORE_TX_TYPE_DATA, 188 RTW89_CORE_TX_TYPE_MGMT, 189 RTW89_CORE_TX_TYPE_FWCMD, 190 }; 191 192 enum rtw89_core_rx_type { 193 RTW89_CORE_RX_TYPE_WIFI = 0, 194 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 195 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 196 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 197 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 198 RTW89_CORE_RX_TYPE_SS2FW = 5, 199 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 200 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 201 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 202 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 203 RTW89_CORE_RX_TYPE_C2H = 10, 204 RTW89_CORE_RX_TYPE_CSI = 11, 205 RTW89_CORE_RX_TYPE_CQI = 12, 206 RTW89_CORE_RX_TYPE_H2C = 13, 207 RTW89_CORE_RX_TYPE_FWDL = 14, 208 }; 209 210 enum rtw89_txq_flags { 211 RTW89_TXQ_F_AMPDU = 0, 212 RTW89_TXQ_F_BLOCK_BA = 1, 213 RTW89_TXQ_F_FORBID_BA = 2, 214 }; 215 216 enum rtw89_net_type { 217 RTW89_NET_TYPE_NO_LINK = 0, 218 RTW89_NET_TYPE_AD_HOC = 1, 219 RTW89_NET_TYPE_INFRA = 2, 220 RTW89_NET_TYPE_AP_MODE = 3, 221 }; 222 223 enum rtw89_wifi_role { 224 RTW89_WIFI_ROLE_NONE, 225 RTW89_WIFI_ROLE_STATION, 226 RTW89_WIFI_ROLE_AP, 227 RTW89_WIFI_ROLE_AP_VLAN, 228 RTW89_WIFI_ROLE_ADHOC, 229 RTW89_WIFI_ROLE_ADHOC_MASTER, 230 RTW89_WIFI_ROLE_MESH_POINT, 231 RTW89_WIFI_ROLE_MONITOR, 232 RTW89_WIFI_ROLE_P2P_DEVICE, 233 RTW89_WIFI_ROLE_P2P_CLIENT, 234 RTW89_WIFI_ROLE_P2P_GO, 235 RTW89_WIFI_ROLE_NAN, 236 RTW89_WIFI_ROLE_MLME_MAX 237 }; 238 239 enum rtw89_upd_mode { 240 RTW89_ROLE_CREATE, 241 RTW89_ROLE_REMOVE, 242 RTW89_ROLE_TYPE_CHANGE, 243 RTW89_ROLE_INFO_CHANGE, 244 RTW89_ROLE_CON_DISCONN, 245 RTW89_ROLE_BAND_SW, 246 RTW89_ROLE_FW_RESTORE, 247 }; 248 249 enum rtw89_self_role { 250 RTW89_SELF_ROLE_CLIENT, 251 RTW89_SELF_ROLE_AP, 252 RTW89_SELF_ROLE_AP_CLIENT 253 }; 254 255 enum rtw89_msk_sO_el { 256 RTW89_NO_MSK, 257 RTW89_SMA, 258 RTW89_TMA, 259 RTW89_BSSID 260 }; 261 262 enum rtw89_sch_tx_sel { 263 RTW89_SCH_TX_SEL_ALL, 264 RTW89_SCH_TX_SEL_HIQ, 265 RTW89_SCH_TX_SEL_MG0, 266 RTW89_SCH_TX_SEL_MACID, 267 }; 268 269 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 270 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 271 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 272 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 273 */ 274 enum rtw89_add_cam_sec_mode { 275 RTW89_ADDR_CAM_SEC_NONE = 0, 276 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 277 RTW89_ADDR_CAM_SEC_NORMAL = 2, 278 RTW89_ADDR_CAM_SEC_4GROUP = 3, 279 }; 280 281 enum rtw89_sec_key_type { 282 RTW89_SEC_KEY_TYPE_NONE = 0, 283 RTW89_SEC_KEY_TYPE_WEP40 = 1, 284 RTW89_SEC_KEY_TYPE_WEP104 = 2, 285 RTW89_SEC_KEY_TYPE_TKIP = 3, 286 RTW89_SEC_KEY_TYPE_WAPI = 4, 287 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 288 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 289 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 290 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 291 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 292 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 293 }; 294 295 enum rtw89_port { 296 RTW89_PORT_0 = 0, 297 RTW89_PORT_1 = 1, 298 RTW89_PORT_2 = 2, 299 RTW89_PORT_3 = 3, 300 RTW89_PORT_4 = 4, 301 RTW89_PORT_NUM 302 }; 303 304 enum rtw89_band { 305 RTW89_BAND_2G = 0, 306 RTW89_BAND_5G = 1, 307 RTW89_BAND_6G = 2, 308 RTW89_BAND_NUM, 309 }; 310 311 enum rtw89_hw_rate { 312 RTW89_HW_RATE_CCK1 = 0x0, 313 RTW89_HW_RATE_CCK2 = 0x1, 314 RTW89_HW_RATE_CCK5_5 = 0x2, 315 RTW89_HW_RATE_CCK11 = 0x3, 316 RTW89_HW_RATE_OFDM6 = 0x4, 317 RTW89_HW_RATE_OFDM9 = 0x5, 318 RTW89_HW_RATE_OFDM12 = 0x6, 319 RTW89_HW_RATE_OFDM18 = 0x7, 320 RTW89_HW_RATE_OFDM24 = 0x8, 321 RTW89_HW_RATE_OFDM36 = 0x9, 322 RTW89_HW_RATE_OFDM48 = 0xA, 323 RTW89_HW_RATE_OFDM54 = 0xB, 324 RTW89_HW_RATE_MCS0 = 0x80, 325 RTW89_HW_RATE_MCS1 = 0x81, 326 RTW89_HW_RATE_MCS2 = 0x82, 327 RTW89_HW_RATE_MCS3 = 0x83, 328 RTW89_HW_RATE_MCS4 = 0x84, 329 RTW89_HW_RATE_MCS5 = 0x85, 330 RTW89_HW_RATE_MCS6 = 0x86, 331 RTW89_HW_RATE_MCS7 = 0x87, 332 RTW89_HW_RATE_MCS8 = 0x88, 333 RTW89_HW_RATE_MCS9 = 0x89, 334 RTW89_HW_RATE_MCS10 = 0x8A, 335 RTW89_HW_RATE_MCS11 = 0x8B, 336 RTW89_HW_RATE_MCS12 = 0x8C, 337 RTW89_HW_RATE_MCS13 = 0x8D, 338 RTW89_HW_RATE_MCS14 = 0x8E, 339 RTW89_HW_RATE_MCS15 = 0x8F, 340 RTW89_HW_RATE_MCS16 = 0x90, 341 RTW89_HW_RATE_MCS17 = 0x91, 342 RTW89_HW_RATE_MCS18 = 0x92, 343 RTW89_HW_RATE_MCS19 = 0x93, 344 RTW89_HW_RATE_MCS20 = 0x94, 345 RTW89_HW_RATE_MCS21 = 0x95, 346 RTW89_HW_RATE_MCS22 = 0x96, 347 RTW89_HW_RATE_MCS23 = 0x97, 348 RTW89_HW_RATE_MCS24 = 0x98, 349 RTW89_HW_RATE_MCS25 = 0x99, 350 RTW89_HW_RATE_MCS26 = 0x9A, 351 RTW89_HW_RATE_MCS27 = 0x9B, 352 RTW89_HW_RATE_MCS28 = 0x9C, 353 RTW89_HW_RATE_MCS29 = 0x9D, 354 RTW89_HW_RATE_MCS30 = 0x9E, 355 RTW89_HW_RATE_MCS31 = 0x9F, 356 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 357 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 358 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 359 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 360 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 361 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 362 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 363 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 364 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 365 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 366 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 367 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 368 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 369 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 370 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 371 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 372 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 373 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 374 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 375 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 376 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 377 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 378 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 379 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 380 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 381 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 382 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 383 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 384 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 385 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 386 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 387 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 388 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 389 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 390 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 391 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 392 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 393 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 394 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 395 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 396 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 397 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 398 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 399 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 400 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 401 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 402 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 403 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 404 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 405 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 406 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 407 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 408 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 409 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 410 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 411 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 412 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 413 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 414 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 415 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 416 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 417 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 418 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 419 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 420 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 421 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 422 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 423 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 424 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 425 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 426 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 427 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 428 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 429 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 430 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 431 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 432 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 433 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 434 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 435 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 436 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 437 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 438 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 439 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 440 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 441 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 442 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 443 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 444 445 RTW89_HW_RATE_V1_MCS0 = 0x100, 446 RTW89_HW_RATE_V1_MCS1 = 0x101, 447 RTW89_HW_RATE_V1_MCS2 = 0x102, 448 RTW89_HW_RATE_V1_MCS3 = 0x103, 449 RTW89_HW_RATE_V1_MCS4 = 0x104, 450 RTW89_HW_RATE_V1_MCS5 = 0x105, 451 RTW89_HW_RATE_V1_MCS6 = 0x106, 452 RTW89_HW_RATE_V1_MCS7 = 0x107, 453 RTW89_HW_RATE_V1_MCS8 = 0x108, 454 RTW89_HW_RATE_V1_MCS9 = 0x109, 455 RTW89_HW_RATE_V1_MCS10 = 0x10A, 456 RTW89_HW_RATE_V1_MCS11 = 0x10B, 457 RTW89_HW_RATE_V1_MCS12 = 0x10C, 458 RTW89_HW_RATE_V1_MCS13 = 0x10D, 459 RTW89_HW_RATE_V1_MCS14 = 0x10E, 460 RTW89_HW_RATE_V1_MCS15 = 0x10F, 461 RTW89_HW_RATE_V1_MCS16 = 0x110, 462 RTW89_HW_RATE_V1_MCS17 = 0x111, 463 RTW89_HW_RATE_V1_MCS18 = 0x112, 464 RTW89_HW_RATE_V1_MCS19 = 0x113, 465 RTW89_HW_RATE_V1_MCS20 = 0x114, 466 RTW89_HW_RATE_V1_MCS21 = 0x115, 467 RTW89_HW_RATE_V1_MCS22 = 0x116, 468 RTW89_HW_RATE_V1_MCS23 = 0x117, 469 RTW89_HW_RATE_V1_MCS24 = 0x118, 470 RTW89_HW_RATE_V1_MCS25 = 0x119, 471 RTW89_HW_RATE_V1_MCS26 = 0x11A, 472 RTW89_HW_RATE_V1_MCS27 = 0x11B, 473 RTW89_HW_RATE_V1_MCS28 = 0x11C, 474 RTW89_HW_RATE_V1_MCS29 = 0x11D, 475 RTW89_HW_RATE_V1_MCS30 = 0x11E, 476 RTW89_HW_RATE_V1_MCS31 = 0x11F, 477 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 478 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 479 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 480 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 481 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 482 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 483 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 484 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 485 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 486 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 487 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 488 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 489 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 490 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 491 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 492 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 493 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 494 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 495 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 496 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 497 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 498 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 499 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 500 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 501 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 502 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 503 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 504 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 505 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 506 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 507 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 508 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 509 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 510 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 511 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 512 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 513 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 514 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 515 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 516 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 517 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 518 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 519 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 520 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 521 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 522 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 523 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 524 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 525 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 526 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 527 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 528 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 529 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 530 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 531 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 532 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 533 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 534 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 535 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 536 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 537 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 538 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 539 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 540 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 541 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 542 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 543 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 544 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 545 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 546 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 547 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 548 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 549 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 550 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 551 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 552 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 553 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 554 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 555 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 556 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 557 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 558 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 559 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 560 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 561 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 562 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 563 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 564 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 565 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 566 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 567 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 568 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 569 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 570 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 571 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 572 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 573 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 574 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 575 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 576 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 577 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 578 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 579 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 580 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 581 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 582 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 583 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 584 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 585 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 586 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 587 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 588 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 589 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 590 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 591 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 592 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 593 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 594 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 595 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 596 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 597 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 598 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 599 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 600 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 601 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 602 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 603 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 604 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 605 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 606 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 607 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 608 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 609 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 610 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 611 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 612 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 613 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 614 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 615 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 616 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 617 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 618 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 619 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 620 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 621 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 622 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 623 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 624 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 625 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 626 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 627 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 628 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 629 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 630 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 631 632 RTW89_HW_RATE_NR, 633 RTW89_HW_RATE_INVAL, 634 635 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 636 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 637 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 638 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 639 }; 640 641 /* 2G channels, 642 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 643 */ 644 #define RTW89_2G_CH_NUM 14 645 646 /* 5G channels, 647 * 36, 38, 40, 42, 44, 46, 48, 50, 648 * 52, 54, 56, 58, 60, 62, 64, 649 * 100, 102, 104, 106, 108, 110, 112, 114, 650 * 116, 118, 120, 122, 124, 126, 128, 130, 651 * 132, 134, 136, 138, 140, 142, 144, 652 * 149, 151, 153, 155, 157, 159, 161, 163, 653 * 165, 167, 169, 171, 173, 175, 177 654 */ 655 #define RTW89_5G_CH_NUM 53 656 657 /* 6G channels, 658 * 1, 3, 5, 7, 9, 11, 13, 15, 659 * 17, 19, 21, 23, 25, 27, 29, 33, 660 * 35, 37, 39, 41, 43, 45, 47, 49, 661 * 51, 53, 55, 57, 59, 61, 65, 67, 662 * 69, 71, 73, 75, 77, 79, 81, 83, 663 * 85, 87, 89, 91, 93, 97, 99, 101, 664 * 103, 105, 107, 109, 111, 113, 115, 117, 665 * 119, 121, 123, 125, 129, 131, 133, 135, 666 * 137, 139, 141, 143, 145, 147, 149, 151, 667 * 153, 155, 157, 161, 163, 165, 167, 169, 668 * 171, 173, 175, 177, 179, 181, 183, 185, 669 * 187, 189, 193, 195, 197, 199, 201, 203, 670 * 205, 207, 209, 211, 213, 215, 217, 219, 671 * 221, 225, 227, 229, 231, 233, 235, 237, 672 * 239, 241, 243, 245, 247, 249, 251, 253, 673 */ 674 #define RTW89_6G_CH_NUM 120 675 676 enum rtw89_rate_section { 677 RTW89_RS_CCK, 678 RTW89_RS_OFDM, 679 RTW89_RS_MCS, /* for HT/VHT/HE */ 680 RTW89_RS_HEDCM, 681 RTW89_RS_OFFSET, 682 RTW89_RS_NUM, 683 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 684 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 685 }; 686 687 enum rtw89_rate_offset_indexes { 688 RTW89_RATE_OFFSET_HE, 689 RTW89_RATE_OFFSET_VHT, 690 RTW89_RATE_OFFSET_HT, 691 RTW89_RATE_OFFSET_OFDM, 692 RTW89_RATE_OFFSET_CCK, 693 RTW89_RATE_OFFSET_DLRU_EHT, 694 RTW89_RATE_OFFSET_DLRU_HE, 695 RTW89_RATE_OFFSET_EHT, 696 __RTW89_RATE_OFFSET_NUM, 697 698 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 699 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 700 }; 701 702 enum rtw89_rate_num { 703 RTW89_RATE_CCK_NUM = 4, 704 RTW89_RATE_OFDM_NUM = 8, 705 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 706 707 RTW89_RATE_MCS_NUM_AX = 12, 708 RTW89_RATE_MCS_NUM_BE = 16, 709 __RTW89_RATE_MCS_NUM = 16, 710 }; 711 712 enum rtw89_nss { 713 RTW89_NSS_1 = 0, 714 RTW89_NSS_2 = 1, 715 /* HE DCM only support 1ss and 2ss */ 716 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 717 RTW89_NSS_3 = 2, 718 RTW89_NSS_4 = 3, 719 RTW89_NSS_NUM, 720 }; 721 722 enum rtw89_ntx { 723 RTW89_1TX = 0, 724 RTW89_2TX = 1, 725 RTW89_NTX_NUM, 726 }; 727 728 enum rtw89_beamforming_type { 729 RTW89_NONBF = 0, 730 RTW89_BF = 1, 731 RTW89_BF_NUM, 732 }; 733 734 enum rtw89_ofdma_type { 735 RTW89_NON_OFDMA = 0, 736 RTW89_OFDMA = 1, 737 RTW89_OFDMA_NUM, 738 }; 739 740 /* neither insert new in the middle, nor change any given definition */ 741 enum rtw89_regulation_type { 742 RTW89_WW = 0, 743 RTW89_ETSI = 1, 744 RTW89_FCC = 2, 745 RTW89_MKK = 3, 746 RTW89_NA = 4, 747 RTW89_IC = 5, 748 RTW89_KCC = 6, 749 RTW89_ACMA = 7, 750 RTW89_NCC = 8, 751 RTW89_MEXICO = 9, 752 RTW89_CHILE = 10, 753 RTW89_UKRAINE = 11, 754 RTW89_CN = 12, 755 RTW89_QATAR = 13, 756 RTW89_UK = 14, 757 RTW89_THAILAND = 15, 758 RTW89_REGD_NUM, 759 }; 760 761 enum rtw89_reg_6ghz_power { 762 RTW89_REG_6GHZ_POWER_VLP = 0, 763 RTW89_REG_6GHZ_POWER_LPI = 1, 764 RTW89_REG_6GHZ_POWER_STD = 2, 765 766 NUM_OF_RTW89_REG_6GHZ_POWER, 767 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 768 }; 769 770 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 771 772 /* calculate based on ieee80211 Transmit Power Envelope */ 773 struct rtw89_reg_6ghz_tpe { 774 bool valid; 775 s8 constraint; /* unit: dBm */ 776 }; 777 778 enum rtw89_fw_pkt_ofld_type { 779 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 780 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 781 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 782 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 783 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 784 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 785 RTW89_PKT_OFLD_TYPE_NDP = 6, 786 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 787 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 788 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 789 RTW89_PKT_OFLD_TYPE_NUM, 790 }; 791 792 struct rtw89_txpwr_byrate { 793 s8 cck[RTW89_RATE_CCK_NUM]; 794 s8 ofdm[RTW89_RATE_OFDM_NUM]; 795 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 796 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 797 s8 offset[__RTW89_RATE_OFFSET_NUM]; 798 s8 trap; 799 }; 800 801 struct rtw89_rate_desc { 802 enum rtw89_nss nss; 803 enum rtw89_rate_section rs; 804 enum rtw89_ofdma_type ofdma; 805 u8 idx; 806 }; 807 808 #define PHY_STS_HDR_LEN 8 809 #define RF_PATH_MAX 4 810 #define RTW89_MAX_PPDU_CNT 8 811 struct rtw89_rx_phy_ppdu { 812 void *buf; 813 u32 len; 814 u8 rssi_avg; 815 u8 rssi[RF_PATH_MAX]; 816 u8 mac_id; 817 u8 chan_idx; 818 u8 phy_idx; 819 u8 ie; 820 u16 rate; 821 u8 rpl_avg; 822 u8 rpl_path[RF_PATH_MAX]; 823 u8 rpl_fd[RF_PATH_MAX]; 824 u8 bw_idx; 825 u8 rx_path_en; 826 struct { 827 bool has; 828 u8 avg_snr; 829 u8 evm_max; 830 u8 evm_min; 831 } ofdm; 832 bool has_data; 833 bool has_bcn; 834 bool ldpc; 835 bool stbc; 836 bool to_self; 837 bool valid; 838 bool hdr_2_en; 839 }; 840 841 enum rtw89_mac_idx { 842 RTW89_MAC_0 = 0, 843 RTW89_MAC_1 = 1, 844 RTW89_MAC_NUM, 845 }; 846 847 enum rtw89_phy_idx { 848 RTW89_PHY_0 = 0, 849 RTW89_PHY_1 = 1, 850 RTW89_PHY_NUM, 851 }; 852 853 #define __RTW89_MLD_MAX_LINK_NUM 2 854 #define RTW89_MLD_NON_STA_LINK_NUM 1 855 856 enum rtw89_chanctx_idx { 857 RTW89_CHANCTX_0 = 0, 858 RTW89_CHANCTX_1 = 1, 859 860 NUM_OF_RTW89_CHANCTX, 861 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 862 }; 863 864 enum rtw89_rf_path { 865 RF_PATH_A = 0, 866 RF_PATH_B = 1, 867 RF_PATH_C = 2, 868 RF_PATH_D = 3, 869 RF_PATH_AB, 870 RF_PATH_AC, 871 RF_PATH_AD, 872 RF_PATH_BC, 873 RF_PATH_BD, 874 RF_PATH_CD, 875 RF_PATH_ABC, 876 RF_PATH_ABD, 877 RF_PATH_ACD, 878 RF_PATH_BCD, 879 RF_PATH_ABCD, 880 }; 881 882 enum rtw89_rf_path_bit { 883 RF_A = BIT(0), 884 RF_B = BIT(1), 885 RF_C = BIT(2), 886 RF_D = BIT(3), 887 888 RF_AB = (RF_A | RF_B), 889 RF_AC = (RF_A | RF_C), 890 RF_AD = (RF_A | RF_D), 891 RF_BC = (RF_B | RF_C), 892 RF_BD = (RF_B | RF_D), 893 RF_CD = (RF_C | RF_D), 894 895 RF_ABC = (RF_A | RF_B | RF_C), 896 RF_ABD = (RF_A | RF_B | RF_D), 897 RF_ACD = (RF_A | RF_C | RF_D), 898 RF_BCD = (RF_B | RF_C | RF_D), 899 900 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 901 }; 902 903 enum rtw89_bandwidth { 904 RTW89_CHANNEL_WIDTH_20 = 0, 905 RTW89_CHANNEL_WIDTH_40 = 1, 906 RTW89_CHANNEL_WIDTH_80 = 2, 907 RTW89_CHANNEL_WIDTH_160 = 3, 908 RTW89_CHANNEL_WIDTH_320 = 4, 909 910 /* keep index order above */ 911 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 912 913 RTW89_CHANNEL_WIDTH_80_80 = 5, 914 RTW89_CHANNEL_WIDTH_5 = 6, 915 RTW89_CHANNEL_WIDTH_10 = 7, 916 }; 917 918 enum rtw89_ps_mode { 919 RTW89_PS_MODE_NONE = 0, 920 RTW89_PS_MODE_RFOFF = 1, 921 RTW89_PS_MODE_CLK_GATED = 2, 922 RTW89_PS_MODE_PWR_GATED = 3, 923 }; 924 925 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 926 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 927 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 928 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 929 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 930 931 enum rtw89_pe_duration { 932 RTW89_PE_DURATION_0 = 0, 933 RTW89_PE_DURATION_8 = 1, 934 RTW89_PE_DURATION_16 = 2, 935 RTW89_PE_DURATION_16_20 = 3, 936 }; 937 938 enum rtw89_ru_bandwidth { 939 RTW89_RU26 = 0, 940 RTW89_RU52 = 1, 941 RTW89_RU106 = 2, 942 RTW89_RU52_26 = 3, 943 RTW89_RU106_26 = 4, 944 RTW89_RU_NUM, 945 }; 946 947 enum rtw89_sc_offset { 948 RTW89_SC_DONT_CARE = 0, 949 RTW89_SC_20_UPPER = 1, 950 RTW89_SC_20_LOWER = 2, 951 RTW89_SC_20_UPMOST = 3, 952 RTW89_SC_20_LOWEST = 4, 953 RTW89_SC_20_UP2X = 5, 954 RTW89_SC_20_LOW2X = 6, 955 RTW89_SC_20_UP3X = 7, 956 RTW89_SC_20_LOW3X = 8, 957 RTW89_SC_40_UPPER = 9, 958 RTW89_SC_40_LOWER = 10, 959 }; 960 961 /* only mgd features can be added to the enum */ 962 enum rtw89_wow_flags { 963 RTW89_WOW_FLAG_EN_MAGIC_PKT, 964 RTW89_WOW_FLAG_EN_REKEY_PKT, 965 RTW89_WOW_FLAG_EN_DISCONNECT, 966 RTW89_WOW_FLAG_EN_PATTERN, 967 RTW89_WOW_FLAG_NUM, 968 }; 969 970 struct rtw89_chan { 971 u8 channel; 972 u8 primary_channel; 973 enum rtw89_band band_type; 974 enum rtw89_bandwidth band_width; 975 976 /* The follow-up are derived from the above. We must ensure that it 977 * is assigned correctly in rtw89_chan_create() if new one is added. 978 */ 979 u32 freq; 980 enum rtw89_subband subband_type; 981 enum rtw89_sc_offset pri_ch_idx; 982 u8 pri_sb_idx; 983 }; 984 985 struct rtw89_chan_rcd { 986 u8 prev_primary_channel; 987 enum rtw89_band prev_band_type; 988 bool band_changed; 989 }; 990 991 struct rtw89_channel_help_params { 992 u32 tx_en; 993 }; 994 995 struct rtw89_port_reg { 996 u32 port_cfg; 997 u32 tbtt_prohib; 998 u32 bcn_area; 999 u32 bcn_early; 1000 u32 tbtt_early; 1001 u32 tbtt_agg; 1002 u32 bcn_space; 1003 u32 bcn_forcetx; 1004 u32 bcn_err_cnt; 1005 u32 bcn_err_flag; 1006 u32 dtim_ctrl; 1007 u32 tbtt_shift; 1008 u32 bcn_cnt_tmr; 1009 u32 tsftr_l; 1010 u32 tsftr_h; 1011 u32 md_tsft; 1012 u32 bss_color; 1013 u32 mbssid; 1014 u32 mbssid_drop; 1015 u32 tsf_sync; 1016 u32 ptcl_dbg; 1017 u32 ptcl_dbg_info; 1018 u32 bcn_drop_all; 1019 u32 bcn_psr_rpt; 1020 u32 hiq_win[RTW89_PORT_NUM]; 1021 }; 1022 1023 struct rtw89_txwd_body { 1024 __le32 dword0; 1025 __le32 dword1; 1026 __le32 dword2; 1027 __le32 dword3; 1028 __le32 dword4; 1029 __le32 dword5; 1030 } __packed; 1031 1032 struct rtw89_txwd_body_v1 { 1033 __le32 dword0; 1034 __le32 dword1; 1035 __le32 dword2; 1036 __le32 dword3; 1037 __le32 dword4; 1038 __le32 dword5; 1039 __le32 dword6; 1040 __le32 dword7; 1041 } __packed; 1042 1043 struct rtw89_txwd_body_v2 { 1044 __le32 dword0; 1045 __le32 dword1; 1046 __le32 dword2; 1047 __le32 dword3; 1048 __le32 dword4; 1049 __le32 dword5; 1050 __le32 dword6; 1051 __le32 dword7; 1052 } __packed; 1053 1054 struct rtw89_txwd_info { 1055 __le32 dword0; 1056 __le32 dword1; 1057 __le32 dword2; 1058 __le32 dword3; 1059 __le32 dword4; 1060 __le32 dword5; 1061 } __packed; 1062 1063 struct rtw89_txwd_info_v2 { 1064 __le32 dword0; 1065 __le32 dword1; 1066 __le32 dword2; 1067 __le32 dword3; 1068 __le32 dword4; 1069 __le32 dword5; 1070 __le32 dword6; 1071 __le32 dword7; 1072 } __packed; 1073 1074 struct rtw89_rx_desc_info { 1075 u16 pkt_size; 1076 u8 pkt_type; 1077 u8 drv_info_size; 1078 u8 phy_rpt_size; 1079 u8 hdr_cnv_size; 1080 u8 shift; 1081 u8 wl_hd_iv_len; 1082 bool long_rxdesc; 1083 bool bb_sel; 1084 bool mac_info_valid; 1085 u16 data_rate; 1086 u8 gi_ltf; 1087 u8 bw; 1088 u32 free_run_cnt; 1089 u8 user_id; 1090 bool sr_en; 1091 u8 ppdu_cnt; 1092 u8 ppdu_type; 1093 bool icv_err; 1094 bool crc32_err; 1095 bool hw_dec; 1096 bool sw_dec; 1097 bool addr1_match; 1098 u8 frag; 1099 u16 seq; 1100 u8 frame_type; 1101 u8 rx_pl_id; 1102 bool addr_cam_valid; 1103 u8 addr_cam_id; 1104 u8 sec_cam_id; 1105 u8 mac_id; 1106 u16 offset; 1107 u16 rxd_len; 1108 bool ready; 1109 u16 rssi; 1110 }; 1111 1112 struct rtw89_rxdesc_short { 1113 __le32 dword0; 1114 __le32 dword1; 1115 __le32 dword2; 1116 __le32 dword3; 1117 } __packed; 1118 1119 struct rtw89_rxdesc_short_v2 { 1120 __le32 dword0; 1121 __le32 dword1; 1122 __le32 dword2; 1123 __le32 dword3; 1124 __le32 dword4; 1125 __le32 dword5; 1126 } __packed; 1127 1128 struct rtw89_rxdesc_long { 1129 __le32 dword0; 1130 __le32 dword1; 1131 __le32 dword2; 1132 __le32 dword3; 1133 __le32 dword4; 1134 __le32 dword5; 1135 __le32 dword6; 1136 __le32 dword7; 1137 } __packed; 1138 1139 struct rtw89_rxdesc_long_v2 { 1140 __le32 dword0; 1141 __le32 dword1; 1142 __le32 dword2; 1143 __le32 dword3; 1144 __le32 dword4; 1145 __le32 dword5; 1146 __le32 dword6; 1147 __le32 dword7; 1148 __le32 dword8; 1149 __le32 dword9; 1150 } __packed; 1151 1152 struct rtw89_rxdesc_phy_rpt_v2 { 1153 __le32 dword0; 1154 __le32 dword1; 1155 } __packed; 1156 1157 struct rtw89_tx_desc_info { 1158 u16 pkt_size; 1159 u8 wp_offset; 1160 u8 mac_id; 1161 u8 qsel; 1162 u8 ch_dma; 1163 u8 hdr_llc_len; 1164 bool is_bmc; 1165 bool en_wd_info; 1166 bool wd_page; 1167 bool use_rate; 1168 bool dis_data_fb; 1169 bool tid_indicate; 1170 bool agg_en; 1171 bool bk; 1172 u8 ampdu_density; 1173 u8 ampdu_num; 1174 bool sec_en; 1175 bool report; 1176 bool tx_cnt_lmt_en; 1177 u8 sn: 4; 1178 u8 tx_cnt_lmt: 6; 1179 u8 addr_info_nr; 1180 u8 sec_keyid; 1181 u8 sec_type; 1182 u8 sec_cam_idx; 1183 u8 sec_seq[6]; 1184 u16 data_rate; 1185 u16 data_retry_lowest_rate; 1186 u8 data_bw; 1187 u8 gi_ltf; 1188 bool fw_dl; 1189 u16 seq; 1190 bool a_ctrl_bsr; 1191 u8 hw_ssn_sel; 1192 #define RTW89_MGMT_HW_SSN_SEL 1 1193 u8 hw_seq_mode; 1194 #define RTW89_MGMT_HW_SEQ_MODE 1 1195 bool hiq; 1196 u8 port; 1197 bool er_cap; 1198 bool stbc; 1199 bool ldpc; 1200 bool upd_wlan_hdr; 1201 bool mlo; 1202 bool sw_mld; 1203 }; 1204 1205 struct rtw89_core_tx_request { 1206 enum rtw89_core_tx_type tx_type; 1207 1208 struct sk_buff *skb; 1209 struct ieee80211_vif *vif; 1210 struct ieee80211_sta *sta; 1211 struct rtw89_vif_link *rtwvif_link; 1212 struct rtw89_sta_link *rtwsta_link; 1213 struct rtw89_tx_desc_info desc_info; 1214 }; 1215 1216 struct rtw89_txq { 1217 struct list_head list; 1218 unsigned long flags; 1219 int wait_cnt; 1220 }; 1221 1222 struct rtw89_mac_ax_gnt { 1223 u8 gnt_bt_sw_en; 1224 u8 gnt_bt; 1225 u8 gnt_wl_sw_en; 1226 u8 gnt_wl; 1227 } __packed; 1228 1229 struct rtw89_mac_ax_wl_act { 1230 u8 wlan_act_en; 1231 u8 wlan_act; 1232 } __packed; 1233 1234 #define RTW89_MAC_AX_COEX_GNT_NR 2 1235 struct rtw89_mac_ax_coex_gnt { 1236 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1237 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1238 }; 1239 1240 enum rtw89_btc_ncnt { 1241 BTC_NCNT_POWER_ON = 0x0, 1242 BTC_NCNT_POWER_OFF, 1243 BTC_NCNT_INIT_COEX, 1244 BTC_NCNT_SCAN_START, 1245 BTC_NCNT_SCAN_FINISH, 1246 BTC_NCNT_SPECIAL_PACKET, 1247 BTC_NCNT_SWITCH_BAND, 1248 BTC_NCNT_RFK_TIMEOUT, 1249 BTC_NCNT_SHOW_COEX_INFO, 1250 BTC_NCNT_ROLE_INFO, 1251 BTC_NCNT_CONTROL, 1252 BTC_NCNT_RADIO_STATE, 1253 BTC_NCNT_CUSTOMERIZE, 1254 BTC_NCNT_WL_RFK, 1255 BTC_NCNT_WL_STA, 1256 BTC_NCNT_WL_STA_LAST, 1257 BTC_NCNT_FWINFO, 1258 BTC_NCNT_TIMER, 1259 BTC_NCNT_SWITCH_CHBW, 1260 BTC_NCNT_RESUME_DL_FW, 1261 BTC_NCNT_COUNTRYCODE, 1262 BTC_NCNT_NUM, 1263 }; 1264 1265 enum rtw89_btc_btinfo { 1266 BTC_BTINFO_L0 = 0, 1267 BTC_BTINFO_L1, 1268 BTC_BTINFO_L2, 1269 BTC_BTINFO_L3, 1270 BTC_BTINFO_H0, 1271 BTC_BTINFO_H1, 1272 BTC_BTINFO_H2, 1273 BTC_BTINFO_H3, 1274 BTC_BTINFO_MAX 1275 }; 1276 1277 enum rtw89_btc_dcnt { 1278 BTC_DCNT_RUN = 0x0, 1279 BTC_DCNT_CX_RUNINFO, 1280 BTC_DCNT_RPT, 1281 BTC_DCNT_RPT_HANG, 1282 BTC_DCNT_CYCLE, 1283 BTC_DCNT_CYCLE_HANG, 1284 BTC_DCNT_W1, 1285 BTC_DCNT_W1_HANG, 1286 BTC_DCNT_B1, 1287 BTC_DCNT_B1_HANG, 1288 BTC_DCNT_TDMA_NONSYNC, 1289 BTC_DCNT_SLOT_NONSYNC, 1290 BTC_DCNT_BTCNT_HANG, 1291 BTC_DCNT_BTTX_HANG, 1292 BTC_DCNT_WL_SLOT_DRIFT, 1293 BTC_DCNT_WL_STA_LAST, 1294 BTC_DCNT_BT_SLOT_DRIFT, 1295 BTC_DCNT_BT_SLOT_FLOOD, 1296 BTC_DCNT_FDDT_TRIG, 1297 BTC_DCNT_E2G, 1298 BTC_DCNT_E2G_HANG, 1299 BTC_DCNT_WL_FW_VER_MATCH, 1300 BTC_DCNT_NULL_TX_FAIL, 1301 BTC_DCNT_WL_STA_NTFY, 1302 BTC_DCNT_NUM, 1303 }; 1304 1305 enum rtw89_btc_wl_state_cnt { 1306 BTC_WCNT_SCANAP = 0x0, 1307 BTC_WCNT_DHCP, 1308 BTC_WCNT_EAPOL, 1309 BTC_WCNT_ARP, 1310 BTC_WCNT_SCBDUPDATE, 1311 BTC_WCNT_RFK_REQ, 1312 BTC_WCNT_RFK_GO, 1313 BTC_WCNT_RFK_REJECT, 1314 BTC_WCNT_RFK_TIMEOUT, 1315 BTC_WCNT_CH_UPDATE, 1316 BTC_WCNT_DBCC_ALL_2G, 1317 BTC_WCNT_DBCC_CHG, 1318 BTC_WCNT_RX_OK_LAST, 1319 BTC_WCNT_RX_OK_LAST2S, 1320 BTC_WCNT_RX_ERR_LAST, 1321 BTC_WCNT_RX_ERR_LAST2S, 1322 BTC_WCNT_RX_LAST, 1323 BTC_WCNT_NUM 1324 }; 1325 1326 enum rtw89_btc_bt_state_cnt { 1327 BTC_BCNT_RETRY = 0x0, 1328 BTC_BCNT_REINIT, 1329 BTC_BCNT_REENABLE, 1330 BTC_BCNT_SCBDREAD, 1331 BTC_BCNT_RELINK, 1332 BTC_BCNT_IGNOWL, 1333 BTC_BCNT_INQPAG, 1334 BTC_BCNT_INQ, 1335 BTC_BCNT_PAGE, 1336 BTC_BCNT_ROLESW, 1337 BTC_BCNT_AFH, 1338 BTC_BCNT_INFOUPDATE, 1339 BTC_BCNT_INFOSAME, 1340 BTC_BCNT_SCBDUPDATE, 1341 BTC_BCNT_HIPRI_TX, 1342 BTC_BCNT_HIPRI_RX, 1343 BTC_BCNT_LOPRI_TX, 1344 BTC_BCNT_LOPRI_RX, 1345 BTC_BCNT_POLUT, 1346 BTC_BCNT_POLUT_NOW, 1347 BTC_BCNT_POLUT_DIFF, 1348 BTC_BCNT_RATECHG, 1349 BTC_BCNT_BTTXPWR_UPDATE, 1350 BTC_BCNT_NUM, 1351 }; 1352 1353 enum rtw89_btc_bt_profile { 1354 BTC_BT_NOPROFILE = 0, 1355 BTC_BT_HFP = BIT(0), 1356 BTC_BT_HID = BIT(1), 1357 BTC_BT_A2DP = BIT(2), 1358 BTC_BT_PAN = BIT(3), 1359 BTC_PROFILE_MAX = 4, 1360 }; 1361 1362 struct rtw89_btc_ant_info { 1363 u8 type; /* shared, dedicated */ 1364 u8 num; 1365 u8 isolation; 1366 1367 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1368 u8 diversity: 1; 1369 u8 btg_pos: 2; 1370 u8 stream_cnt: 4; 1371 }; 1372 1373 struct rtw89_btc_ant_info_v7 { 1374 u8 type; /* shared, dedicated(non-shared) */ 1375 u8 num; /* antenna count */ 1376 u8 isolation; 1377 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1378 1379 u8 diversity; /* only for wifi use 1-antenna */ 1380 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1381 u8 stream_cnt; /* spatial_stream count */ 1382 u8 rsvd; 1383 } __packed; 1384 1385 enum rtw89_tfc_dir { 1386 RTW89_TFC_UL, 1387 RTW89_TFC_DL, 1388 }; 1389 1390 struct rtw89_btc_wl_smap { 1391 u32 busy: 1; 1392 u32 scan: 1; 1393 u32 connecting: 1; 1394 u32 roaming: 1; 1395 u32 dbccing: 1; 1396 u32 _4way: 1; 1397 u32 rf_off: 1; 1398 u32 lps: 2; 1399 u32 ips: 1; 1400 u32 init_ok: 1; 1401 u32 traffic_dir : 2; 1402 u32 rf_off_pre: 1; 1403 u32 lps_pre: 2; 1404 u32 lps_exiting: 1; 1405 u32 emlsr: 1; 1406 }; 1407 1408 enum rtw89_tfc_interval { 1409 RTW89_TFC_INTERVAL_100MS, 1410 RTW89_TFC_INTERVAL_2SEC, 1411 }; 1412 1413 enum rtw89_tfc_lv { 1414 RTW89_TFC_IDLE, 1415 RTW89_TFC_ULTRA_LOW, 1416 RTW89_TFC_LOW, 1417 RTW89_TFC_MID, 1418 RTW89_TFC_HIGH, 1419 }; 1420 1421 DECLARE_EWMA(tp, 10, 2); 1422 1423 struct rtw89_traffic_stats { 1424 /* units in bytes */ 1425 u64 tx_unicast; 1426 u64 rx_unicast; 1427 u32 tx_avg_len; 1428 u32 rx_avg_len; 1429 1430 /* count for packets */ 1431 u64 tx_cnt; 1432 u64 rx_cnt; 1433 1434 /* units in Mbps */ 1435 u32 tx_throughput; 1436 u32 rx_throughput; 1437 u32 tx_throughput_raw; 1438 u32 rx_throughput_raw; 1439 1440 u32 rx_tf_acc; 1441 u32 rx_tf_periodic; 1442 1443 enum rtw89_tfc_lv tx_tfc_lv; 1444 enum rtw89_tfc_lv rx_tfc_lv; 1445 struct ewma_tp tx_ewma_tp; 1446 struct ewma_tp rx_ewma_tp; 1447 1448 u16 tx_rate; 1449 u16 rx_rate; 1450 }; 1451 1452 struct rtw89_btc_chdef { 1453 u8 center_ch; 1454 u8 band; 1455 u8 chan; 1456 enum rtw89_sc_offset offset; 1457 enum rtw89_bandwidth bw; 1458 }; 1459 1460 struct rtw89_btc_statistic { 1461 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1462 struct rtw89_traffic_stats traffic; 1463 }; 1464 1465 #define BTC_WL_RSSI_THMAX 4 1466 1467 struct rtw89_btc_wl_link_info { 1468 struct rtw89_btc_chdef chdef; 1469 struct rtw89_btc_statistic stat; 1470 enum rtw89_tfc_dir dir; 1471 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1472 u8 mac_addr[ETH_ALEN]; 1473 u8 busy; 1474 u8 ch; 1475 u8 bw; 1476 u8 band; 1477 u8 role; 1478 u8 pid; 1479 u8 phy; 1480 u8 dtim_period; 1481 u8 mode; 1482 u8 tx_1ss_limit; 1483 1484 u8 mac_id; 1485 u8 tx_retry; 1486 1487 u32 bcn_period; 1488 u32 busy_t; 1489 u32 tx_time; 1490 u32 client_cnt; 1491 u32 rx_rate_drop_cnt; 1492 u32 noa_duration; 1493 1494 u32 active: 1; 1495 u32 noa: 1; 1496 u32 client_ps: 1; 1497 u32 connected: 2; 1498 }; 1499 1500 union rtw89_btc_wl_state_map { 1501 u32 val; 1502 struct rtw89_btc_wl_smap map; 1503 }; 1504 1505 struct rtw89_btc_bt_hfp_desc { 1506 u32 exist: 1; 1507 u32 type: 2; 1508 u32 rsvd: 29; 1509 }; 1510 1511 struct rtw89_btc_bt_hid_desc { 1512 u32 exist: 1; 1513 u32 slot_info: 2; 1514 u32 pair_cnt: 2; 1515 u32 type: 8; 1516 u32 rsvd: 19; 1517 }; 1518 1519 struct rtw89_btc_bt_a2dp_desc { 1520 u8 exist: 1; 1521 u8 exist_last: 1; 1522 u8 play_latency: 1; 1523 u8 type: 3; 1524 u8 active: 1; 1525 u8 sink: 1; 1526 u32 handle_update: 1; 1527 u32 devinfo_query: 1; 1528 u32 no_empty_streak_2s: 8; 1529 u32 no_empty_streak_max: 8; 1530 u32 rsvd: 6; 1531 1532 u8 bitpool; 1533 u16 vendor_id; 1534 u32 device_name; 1535 u32 flush_time; 1536 }; 1537 1538 struct rtw89_btc_bt_pan_desc { 1539 u32 exist: 1; 1540 u32 type: 1; 1541 u32 active: 1; 1542 u32 rsvd: 29; 1543 }; 1544 1545 struct rtw89_btc_bt_rfk_info { 1546 u32 run: 1; 1547 u32 req: 1; 1548 u32 timeout: 1; 1549 u32 rsvd: 29; 1550 }; 1551 1552 union rtw89_btc_bt_rfk_info_map { 1553 u32 val; 1554 struct rtw89_btc_bt_rfk_info map; 1555 }; 1556 1557 struct rtw89_btc_bt_ver_info { 1558 u32 fw_coex; /* match with which coex_ver */ 1559 u32 fw; 1560 }; 1561 1562 struct rtw89_btc_bool_sta_chg { 1563 u32 now: 1; 1564 u32 last: 1; 1565 u32 remain: 1; 1566 u32 srvd: 29; 1567 }; 1568 1569 struct rtw89_btc_u8_sta_chg { 1570 u8 now; 1571 u8 last; 1572 u8 remain; 1573 u8 rsvd; 1574 }; 1575 1576 struct rtw89_btc_wl_scan_info { 1577 u8 band[RTW89_PHY_NUM]; 1578 u8 phy_map; 1579 u8 rsvd; 1580 }; 1581 1582 struct rtw89_btc_wl_dbcc_info { 1583 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1584 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1585 u8 real_band[RTW89_PHY_NUM]; 1586 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1587 }; 1588 1589 struct rtw89_btc_wl_mlo_info { 1590 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */ 1591 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */ 1592 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */ 1593 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */ 1594 1595 u8 wtype; /* enum phl_mr_wtype */ 1596 u8 mrcx_mode; 1597 u8 mrcx_act_hwb_map; 1598 u8 mrcx_bt_slot_rsp; 1599 1600 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */ 1601 u8 mlo_en; /* MLO enable */ 1602 u8 mlo_adie; /* a-die count */ 1603 u8 dual_hw_band_en; /* both 2 HW-band link exist */ 1604 1605 u32 link_status; /* enum mlo_dbcc_mode_type */ 1606 }; 1607 1608 struct rtw89_btc_wl_active_role { 1609 u8 connected: 1; 1610 u8 pid: 3; 1611 u8 phy: 1; 1612 u8 noa: 1; 1613 u8 band: 2; 1614 1615 u8 client_ps: 1; 1616 u8 bw: 7; 1617 1618 u8 role; 1619 u8 ch; 1620 1621 u16 tx_lvl; 1622 u16 rx_lvl; 1623 u16 tx_rate; 1624 u16 rx_rate; 1625 }; 1626 1627 struct rtw89_btc_wl_active_role_v1 { 1628 u8 connected: 1; 1629 u8 pid: 3; 1630 u8 phy: 1; 1631 u8 noa: 1; 1632 u8 band: 2; 1633 1634 u8 client_ps: 1; 1635 u8 bw: 7; 1636 1637 u8 role; 1638 u8 ch; 1639 1640 u16 tx_lvl; 1641 u16 rx_lvl; 1642 u16 tx_rate; 1643 u16 rx_rate; 1644 1645 u32 noa_duration; /* ms */ 1646 }; 1647 1648 struct rtw89_btc_wl_active_role_v2 { 1649 u8 connected: 1; 1650 u8 pid: 3; 1651 u8 phy: 1; 1652 u8 noa: 1; 1653 u8 band: 2; 1654 1655 u8 client_ps: 1; 1656 u8 bw: 7; 1657 1658 u8 role; 1659 u8 ch; 1660 1661 u32 noa_duration; /* ms */ 1662 }; 1663 1664 struct rtw89_btc_wl_active_role_v7 { 1665 u8 connected; 1666 u8 pid; 1667 u8 phy; 1668 u8 noa; 1669 1670 u8 band; 1671 u8 client_ps; 1672 u8 bw; 1673 u8 role; 1674 1675 u8 ch; 1676 u8 noa_dur; 1677 u8 client_cnt; 1678 u8 rsvd2; 1679 } __packed; 1680 1681 struct rtw89_btc_wl_role_info_bpos { 1682 u16 none: 1; 1683 u16 station: 1; 1684 u16 ap: 1; 1685 u16 vap: 1; 1686 u16 adhoc: 1; 1687 u16 adhoc_master: 1; 1688 u16 mesh: 1; 1689 u16 moniter: 1; 1690 u16 p2p_device: 1; 1691 u16 p2p_gc: 1; 1692 u16 p2p_go: 1; 1693 u16 nan: 1; 1694 }; 1695 1696 struct rtw89_btc_wl_scc_ctrl { 1697 u8 null_role1; 1698 u8 null_role2; 1699 u8 ebt_null; /* if tx null at EBT slot */ 1700 }; 1701 1702 union rtw89_btc_wl_role_info_map { 1703 u16 val; 1704 struct rtw89_btc_wl_role_info_bpos role; 1705 }; 1706 1707 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1708 u8 connect_cnt; 1709 u8 link_mode; 1710 union rtw89_btc_wl_role_info_map role_map; 1711 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1712 }; 1713 1714 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1715 u8 connect_cnt; 1716 u8 link_mode; 1717 union rtw89_btc_wl_role_info_map role_map; 1718 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1719 u32 mrole_type; /* btc_wl_mrole_type */ 1720 u32 mrole_noa_duration; /* ms */ 1721 1722 u32 dbcc_en: 1; 1723 u32 dbcc_chg: 1; 1724 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1725 u32 link_mode_chg: 1; 1726 u32 rsvd: 27; 1727 }; 1728 1729 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1730 u8 connect_cnt; 1731 u8 link_mode; 1732 union rtw89_btc_wl_role_info_map role_map; 1733 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1734 u32 mrole_type; /* btc_wl_mrole_type */ 1735 u32 mrole_noa_duration; /* ms */ 1736 1737 u32 dbcc_en: 1; 1738 u32 dbcc_chg: 1; 1739 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1740 u32 link_mode_chg: 1; 1741 u32 rsvd: 27; 1742 }; 1743 1744 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1745 u8 connected; 1746 u8 pid; 1747 u8 phy; 1748 u8 noa; 1749 1750 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1751 u8 active; /* 0:rlink is under doze */ 1752 u8 bw; /* enum channel_width */ 1753 u8 role; /*enum role_type */ 1754 1755 u8 ch; 1756 u8 noa_dur; /* ms */ 1757 u8 client_cnt; /* for Role = P2P-Go/AP */ 1758 u8 mode; /* wifi protocol */ 1759 } __packed; 1760 1761 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1762 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1763 u8 connect_cnt; 1764 u8 link_mode; 1765 u8 link_mode_chg; 1766 u8 p2p_2g; 1767 1768 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1769 1770 u32 role_map; 1771 u32 mrole_type; /* btc_wl_mrole_type */ 1772 u32 mrole_noa_duration; /* ms */ 1773 u32 dbcc_en; 1774 u32 dbcc_chg; 1775 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1776 } __packed; 1777 1778 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1779 u8 connect_cnt; 1780 u8 link_mode; 1781 u8 link_mode_chg; 1782 u8 p2p_2g; 1783 1784 u8 pta_req_band; 1785 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1786 u8 dbcc_chg; 1787 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1788 1789 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1790 1791 u32 role_map; 1792 u32 mrole_type; /* btc_wl_mrole_type */ 1793 u32 mrole_noa_duration; /* ms */ 1794 } __packed; 1795 1796 struct rtw89_btc_wl_ver_info { 1797 u32 fw_coex; /* match with which coex_ver */ 1798 u32 fw; 1799 u32 mac; 1800 u32 bb; 1801 u32 rf; 1802 }; 1803 1804 struct rtw89_btc_wl_afh_info { 1805 u8 en; 1806 u8 ch; 1807 u8 bw; 1808 u8 rsvd; 1809 } __packed; 1810 1811 struct rtw89_btc_wl_rfk_info { 1812 u32 state: 2; 1813 u32 path_map: 4; 1814 u32 phy_map: 2; 1815 u32 band: 2; 1816 u32 type: 8; 1817 u32 con_rfk: 1; 1818 u32 rsvd: 13; 1819 1820 u32 start_time; 1821 u32 proc_time; 1822 }; 1823 1824 struct rtw89_btc_bt_smap { 1825 u32 connect: 1; 1826 u32 ble_connect: 1; 1827 u32 acl_busy: 1; 1828 u32 sco_busy: 1; 1829 u32 mesh_busy: 1; 1830 u32 inq_pag: 1; 1831 }; 1832 1833 union rtw89_btc_bt_state_map { 1834 u32 val; 1835 struct rtw89_btc_bt_smap map; 1836 }; 1837 1838 #define BTC_BT_RSSI_THMAX 4 1839 #define BTC_BT_AFH_GROUP 12 1840 #define BTC_BT_AFH_LE_GROUP 5 1841 1842 struct rtw89_btc_bt_txpwr_desc { 1843 s8 br_dbm; 1844 s8 le_dbm; 1845 u8 br_gain_index; 1846 u8 le_gain_index; 1847 }; 1848 1849 struct rtw89_btc_bt_link_info { 1850 struct rtw89_btc_u8_sta_chg profile_cnt; 1851 struct rtw89_btc_bool_sta_chg multi_link; 1852 struct rtw89_btc_bool_sta_chg relink; 1853 struct rtw89_btc_bt_hfp_desc hfp_desc; 1854 struct rtw89_btc_bt_hid_desc hid_desc; 1855 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1856 struct rtw89_btc_bt_pan_desc pan_desc; 1857 union rtw89_btc_bt_state_map status; 1858 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc; 1859 1860 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1861 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1862 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1863 u8 afh_map[BTC_BT_AFH_GROUP]; 1864 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1865 1866 u32 role_sw: 1; 1867 u32 slave_role: 1; 1868 u32 afh_update: 1; 1869 u32 cqddr: 1; 1870 u32 rssi: 8; 1871 u32 tx_3m: 1; 1872 u32 rsvd: 19; 1873 }; 1874 1875 struct rtw89_btc_3rdcx_info { 1876 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1877 u8 hw_coex; 1878 u16 rsvd; 1879 }; 1880 1881 struct rtw89_btc_dm_emap { 1882 u32 init: 1; 1883 u32 pta_owner: 1; 1884 u32 wl_rfk_timeout: 1; 1885 u32 bt_rfk_timeout: 1; 1886 u32 wl_fw_hang: 1; 1887 u32 cycle_hang: 1; 1888 u32 w1_hang: 1; 1889 u32 b1_hang: 1; 1890 u32 tdma_no_sync: 1; 1891 u32 slot_no_sync: 1; 1892 u32 wl_slot_drift: 1; 1893 u32 bt_slot_drift: 1; 1894 u32 role_num_mismatch: 1; 1895 u32 null1_tx_late: 1; 1896 u32 bt_afh_conflict: 1; 1897 u32 bt_leafh_conflict: 1; 1898 u32 bt_slot_flood: 1; 1899 u32 wl_e2g_hang: 1; 1900 u32 wl_ver_mismatch: 1; 1901 u32 bt_ver_mismatch: 1; 1902 u32 rfe_type0: 1; 1903 u32 h2c_buffer_over: 1; 1904 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1905 u32 wl_no_sta_ntfy: 1; 1906 1907 u32 h2c_bmap_mismatch: 1; 1908 u32 c2h_bmap_mismatch: 1; 1909 u32 h2c_struct_invalid: 1; 1910 u32 c2h_struct_invalid: 1; 1911 u32 h2c_c2h_buffer_mismatch: 1; 1912 }; 1913 1914 union rtw89_btc_dm_error_map { 1915 u32 val; 1916 struct rtw89_btc_dm_emap map; 1917 }; 1918 1919 struct rtw89_btc_rf_para { 1920 u32 tx_pwr_freerun; 1921 u32 rx_gain_freerun; 1922 u32 tx_pwr_perpkt; 1923 u32 rx_gain_perpkt; 1924 }; 1925 1926 struct rtw89_btc_wl_nhm { 1927 u8 instant_wl_nhm_dbm; 1928 u8 instant_wl_nhm_per_mhz; 1929 u16 valid_record_times; 1930 s8 record_pwr[16]; 1931 u8 record_ratio[16]; 1932 s8 pwr; /* dbm_per_MHz */ 1933 u8 ratio; 1934 u8 current_status; 1935 u8 refresh; 1936 bool start_flag; 1937 s8 pwr_max; 1938 s8 pwr_min; 1939 }; 1940 1941 struct rtw89_btc_wl_info { 1942 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1943 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1944 struct rtw89_btc_wl_rfk_info rfk_info; 1945 struct rtw89_btc_wl_ver_info ver_info; 1946 struct rtw89_btc_wl_afh_info afh_info; 1947 struct rtw89_btc_wl_role_info role_info; 1948 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1949 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1950 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1951 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1952 struct rtw89_btc_wl_scan_info scan_info; 1953 struct rtw89_btc_wl_dbcc_info dbcc_info; 1954 struct rtw89_btc_wl_mlo_info mlo_info; 1955 struct rtw89_btc_rf_para rf_para; 1956 struct rtw89_btc_wl_nhm nhm; 1957 union rtw89_btc_wl_state_map status; 1958 1959 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1960 u8 rssi_level; 1961 u8 cn_report; 1962 u8 coex_mode; 1963 u8 pta_req_mac; 1964 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 1965 1966 bool is_5g_hi_channel; 1967 bool go_client_exist; 1968 bool noa_exist; 1969 bool pta_reg_mac_chg; 1970 bool bg_mode; 1971 bool he_mode; 1972 bool scbd_change; 1973 bool fw_ver_mismatch; 1974 bool client_cnt_inc_2g; 1975 bool link_mode_chg; 1976 bool dbcc_chg; 1977 u32 scbd; 1978 }; 1979 1980 struct rtw89_btc_module { 1981 struct rtw89_btc_ant_info ant; 1982 u8 rfe_type; 1983 u8 cv; 1984 1985 u8 bt_solo: 1; 1986 u8 bt_pos: 1; 1987 u8 switch_type: 1; 1988 u8 wa_type: 3; 1989 1990 u8 kt_ver_adie; 1991 }; 1992 1993 struct rtw89_btc_module_v7 { 1994 u8 rfe_type; 1995 u8 kt_ver; 1996 u8 bt_solo; 1997 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1998 1999 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 2000 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 2001 u8 kt_ver_adie; 2002 u8 rsvd; 2003 2004 struct rtw89_btc_ant_info_v7 ant; 2005 } __packed; 2006 2007 union rtw89_btc_module_info { 2008 struct rtw89_btc_module md; 2009 struct rtw89_btc_module_v7 md_v7; 2010 }; 2011 2012 #define RTW89_BTC_DM_MAXSTEP 30 2013 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 2014 2015 struct rtw89_btc_dm_step { 2016 u16 step[RTW89_BTC_DM_MAXSTEP]; 2017 u8 step_pos; 2018 bool step_ov; 2019 }; 2020 2021 struct rtw89_btc_init_info { 2022 struct rtw89_btc_module module; 2023 u8 wl_guard_ch; 2024 2025 u8 wl_only: 1; 2026 u8 wl_init_ok: 1; 2027 u8 dbcc_en: 1; 2028 u8 cx_other: 1; 2029 u8 bt_only: 1; 2030 2031 u16 rsvd; 2032 }; 2033 2034 struct rtw89_btc_init_info_v7 { 2035 u8 wl_guard_ch; 2036 u8 wl_only; 2037 u8 wl_init_ok; 2038 u8 rsvd3; 2039 2040 u8 cx_other; 2041 u8 bt_only; 2042 u8 pta_mode; 2043 u8 pta_direction; 2044 2045 struct rtw89_btc_module_v7 module; 2046 } __packed; 2047 2048 union rtw89_btc_init_info_u { 2049 struct rtw89_btc_init_info init; 2050 struct rtw89_btc_init_info_v7 init_v7; 2051 }; 2052 2053 struct rtw89_btc_wl_tx_limit_para { 2054 u16 enable; 2055 u32 tx_time; /* unit: us */ 2056 u16 tx_retry; 2057 }; 2058 2059 enum rtw89_btc_bt_scan_type { 2060 BTC_SCAN_INQ = 0, 2061 BTC_SCAN_PAGE, 2062 BTC_SCAN_BLE, 2063 BTC_SCAN_INIT, 2064 BTC_SCAN_TV, 2065 BTC_SCAN_ADV, 2066 BTC_SCAN_MAX1, 2067 }; 2068 2069 enum rtw89_btc_ble_scan_type { 2070 CXSCAN_BG = 0, 2071 CXSCAN_INIT, 2072 CXSCAN_LE, 2073 CXSCAN_MAX 2074 }; 2075 2076 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2077 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2078 2079 struct rtw89_btc_bt_scan_info_v1 { 2080 __le16 win; 2081 __le16 intvl; 2082 __le32 flags; 2083 } __packed; 2084 2085 struct rtw89_btc_bt_scan_info_v2 { 2086 __le16 win; 2087 __le16 intvl; 2088 } __packed; 2089 2090 struct rtw89_btc_fbtc_btscan_v1 { 2091 u8 fver; /* btc_ver::fcxbtscan */ 2092 u8 rsvd; 2093 __le16 rsvd2; 2094 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2095 } __packed; 2096 2097 struct rtw89_btc_fbtc_btscan_v2 { 2098 u8 fver; /* btc_ver::fcxbtscan */ 2099 u8 type; 2100 __le16 rsvd2; 2101 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2102 } __packed; 2103 2104 struct rtw89_btc_fbtc_btscan_v7 { 2105 u8 fver; /* btc_ver::fcxbtscan */ 2106 u8 type; 2107 u8 rsvd0; 2108 u8 rsvd1; 2109 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2110 } __packed; 2111 2112 union rtw89_btc_fbtc_btscan { 2113 struct rtw89_btc_fbtc_btscan_v1 v1; 2114 struct rtw89_btc_fbtc_btscan_v2 v2; 2115 struct rtw89_btc_fbtc_btscan_v7 v7; 2116 }; 2117 2118 struct rtw89_btc_bt_info { 2119 struct rtw89_btc_bt_link_info link_info; 2120 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2121 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2122 struct rtw89_btc_bt_ver_info ver_info; 2123 struct rtw89_btc_bool_sta_chg enable; 2124 struct rtw89_btc_bool_sta_chg inq_pag; 2125 struct rtw89_btc_rf_para rf_para; 2126 union rtw89_btc_bt_rfk_info_map rfk_info; 2127 2128 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2129 u8 txpwr_info[BTC_BTINFO_MAX]; 2130 u8 rssi_level; 2131 2132 u32 scbd; 2133 u32 feature; 2134 2135 u32 mbx_avl: 1; 2136 u32 whql_test: 1; 2137 u32 igno_wl: 1; 2138 u32 reinit: 1; 2139 u32 ble_scan_en: 1; 2140 u32 btg_type: 1; 2141 u32 inq: 1; 2142 u32 pag: 1; 2143 u32 run_patch_code: 1; 2144 u32 hi_lna_rx: 1; 2145 u32 scan_rx_low_pri: 1; 2146 u32 scan_info_update: 1; 2147 u32 lna_constrain: 3; 2148 u32 rsvd: 17; 2149 }; 2150 2151 struct rtw89_btc_cx { 2152 struct rtw89_btc_wl_info wl; 2153 struct rtw89_btc_bt_info bt; 2154 struct rtw89_btc_3rdcx_info other; 2155 u32 state_map; 2156 u32 cnt_bt[BTC_BCNT_NUM]; 2157 u32 cnt_wl[BTC_WCNT_NUM]; 2158 }; 2159 2160 struct rtw89_btc_fbtc_tdma { 2161 u8 type; /* btc_ver::fcxtdma */ 2162 u8 rxflctrl; 2163 u8 txpause; 2164 u8 wtgle_n; 2165 u8 leak_n; 2166 u8 ext_ctrl; 2167 u8 rxflctrl_role; 2168 u8 option_ctrl; 2169 } __packed; 2170 2171 struct rtw89_btc_fbtc_tdma_v3 { 2172 u8 fver; /* btc_ver::fcxtdma */ 2173 u8 rsvd; 2174 __le16 rsvd1; 2175 struct rtw89_btc_fbtc_tdma tdma; 2176 } __packed; 2177 2178 union rtw89_btc_fbtc_tdma_le32 { 2179 struct rtw89_btc_fbtc_tdma v1; 2180 struct rtw89_btc_fbtc_tdma_v3 v3; 2181 }; 2182 2183 #define CXMREG_MAX 30 2184 #define CXMREG_MAX_V2 20 2185 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2186 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2187 2188 enum rtw89_btc_bt_sta_counter { 2189 BTC_BCNT_RFK_REQ = 0, 2190 BTC_BCNT_RFK_GO = 1, 2191 BTC_BCNT_RFK_REJECT = 2, 2192 BTC_BCNT_RFK_FAIL = 3, 2193 BTC_BCNT_RFK_TIMEOUT = 4, 2194 BTC_BCNT_HI_TX = 5, 2195 BTC_BCNT_HI_RX = 6, 2196 BTC_BCNT_LO_TX = 7, 2197 BTC_BCNT_LO_RX = 8, 2198 BTC_BCNT_POLLUTED = 9, 2199 BTC_BCNT_STA_MAX 2200 }; 2201 2202 enum rtw89_btc_bt_sta_counter_v105 { 2203 BTC_BCNT_RFK_REQ_V105 = 0, 2204 BTC_BCNT_HI_TX_V105 = 1, 2205 BTC_BCNT_HI_RX_V105 = 2, 2206 BTC_BCNT_LO_TX_V105 = 3, 2207 BTC_BCNT_LO_RX_V105 = 4, 2208 BTC_BCNT_POLLUTED_V105 = 5, 2209 BTC_BCNT_STA_MAX_V105 2210 }; 2211 2212 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2213 u16 fver; /* btc_ver::fcxbtcrpt */ 2214 u16 rpt_cnt; /* tmr counters */ 2215 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2216 u32 wl_fw_cx_offload; 2217 u32 wl_fw_ver; 2218 u32 rpt_enable; 2219 u32 rpt_para; /* ms */ 2220 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2221 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2222 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2223 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2224 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2225 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2226 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2227 u32 c2h_cnt; /* fw send c2h counter */ 2228 u32 h2c_cnt; /* fw recv h2c counter */ 2229 } __packed; 2230 2231 struct rtw89_btc_fbtc_rpt_ctrl_info { 2232 __le32 cnt; /* fw report counter */ 2233 __le32 en; /* report map */ 2234 __le32 para; /* not used */ 2235 2236 __le32 cnt_c2h; /* fw send c2h counter */ 2237 __le32 cnt_h2c; /* fw recv h2c counter */ 2238 __le32 len_c2h; /* The total length of the last C2H */ 2239 2240 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2241 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2242 } __packed; 2243 2244 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2245 __le32 cx_ver; /* match which driver's coex version */ 2246 __le32 fw_ver; 2247 __le32 en; /* report map */ 2248 2249 __le16 cnt; /* fw report counter */ 2250 __le16 cnt_c2h; /* fw send c2h counter */ 2251 __le16 cnt_h2c; /* fw recv h2c counter */ 2252 __le16 len_c2h; /* The total length of the last C2H */ 2253 2254 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2255 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2256 } __packed; 2257 2258 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2259 __le16 cnt; /* fw report counter */ 2260 __le16 cnt_c2h; /* fw send c2h counter */ 2261 __le16 cnt_h2c; /* fw recv h2c counter */ 2262 __le16 len_c2h; /* The total length of the last C2H */ 2263 2264 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2265 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2266 2267 __le32 cx_ver; /* match which driver's coex version */ 2268 __le32 fw_ver; 2269 __le32 en; /* report map */ 2270 } __packed; 2271 2272 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2273 __le32 cx_ver; /* match which driver's coex version */ 2274 __le32 cx_offload; 2275 __le32 fw_ver; 2276 } __packed; 2277 2278 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2279 __le32 cnt_empty; /* a2dp empty count */ 2280 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2281 __le32 cnt_tx; 2282 __le32 cnt_ack; 2283 __le32 cnt_nack; 2284 } __packed; 2285 2286 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2287 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2288 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2289 __le32 cnt_recv; /* fw recv mailbox counter */ 2290 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2291 } __packed; 2292 2293 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2294 u8 fver; 2295 u8 rsvd; 2296 __le16 rsvd1; 2297 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2298 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2299 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2300 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2301 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2302 } __packed; 2303 2304 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2305 u8 fver; 2306 u8 rsvd; 2307 __le16 rsvd1; 2308 2309 u8 gnt_val[RTW89_PHY_NUM][4]; 2310 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2311 2312 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2313 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2314 } __packed; 2315 2316 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2317 u8 fver; 2318 u8 rsvd; 2319 __le16 rsvd1; 2320 2321 u8 gnt_val[RTW89_PHY_NUM][4]; 2322 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2323 2324 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2325 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2326 } __packed; 2327 2328 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2329 u8 fver; 2330 u8 rsvd0; 2331 u8 rsvd1; 2332 u8 rsvd2; 2333 2334 u8 gnt_val[RTW89_PHY_NUM][4]; 2335 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2336 2337 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2338 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2339 } __packed; 2340 2341 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2342 u8 fver; 2343 u8 rsvd0; 2344 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2345 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2346 2347 u8 gnt_val[RTW89_PHY_NUM][4]; 2348 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2349 2350 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2351 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2352 } __packed; 2353 2354 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2355 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2356 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2357 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2358 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2359 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2360 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2361 }; 2362 2363 enum rtw89_fbtc_ext_ctrl_type { 2364 CXECTL_OFF = 0x0, /* tdma off */ 2365 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2366 CXECTL_EXT = 0x2, 2367 CXECTL_MAX 2368 }; 2369 2370 union rtw89_btc_fbtc_rxflct { 2371 u8 val; 2372 u8 type: 3; 2373 u8 tgln_n: 5; 2374 }; 2375 2376 enum rtw89_btc_cxst_state { 2377 CXST_OFF = 0x0, 2378 CXST_B2W = 0x1, 2379 CXST_W1 = 0x2, 2380 CXST_W2 = 0x3, 2381 CXST_W2B = 0x4, 2382 CXST_B1 = 0x5, 2383 CXST_B2 = 0x6, 2384 CXST_B3 = 0x7, 2385 CXST_B4 = 0x8, 2386 CXST_LK = 0x9, 2387 CXST_BLK = 0xa, 2388 CXST_E2G = 0xb, 2389 CXST_E5G = 0xc, 2390 CXST_EBT = 0xd, 2391 CXST_ENULL = 0xe, 2392 CXST_WLK = 0xf, 2393 CXST_W1FDD = 0x10, 2394 CXST_B1FDD = 0x11, 2395 CXST_MAX = 0x12, 2396 }; 2397 2398 enum rtw89_btc_cxevnt { 2399 CXEVNT_TDMA_ENTRY = 0x0, 2400 CXEVNT_WL_TMR, 2401 CXEVNT_B1_TMR, 2402 CXEVNT_B2_TMR, 2403 CXEVNT_B3_TMR, 2404 CXEVNT_B4_TMR, 2405 CXEVNT_W2B_TMR, 2406 CXEVNT_B2W_TMR, 2407 CXEVNT_BCN_EARLY, 2408 CXEVNT_A2DP_EMPTY, 2409 CXEVNT_LK_END, 2410 CXEVNT_RX_ISR, 2411 CXEVNT_RX_FC0, 2412 CXEVNT_RX_FC1, 2413 CXEVNT_BT_RELINK, 2414 CXEVNT_BT_RETRY, 2415 CXEVNT_E2G, 2416 CXEVNT_E5G, 2417 CXEVNT_EBT, 2418 CXEVNT_ENULL, 2419 CXEVNT_DRV_WLK, 2420 CXEVNT_BCN_OK, 2421 CXEVNT_BT_CHANGE, 2422 CXEVNT_EBT_EXTEND, 2423 CXEVNT_E2G_NULL1, 2424 CXEVNT_B1FDD_TMR, 2425 CXEVNT_MAX 2426 }; 2427 2428 enum { 2429 CXBCN_ALL = 0x0, 2430 CXBCN_ALL_OK, 2431 CXBCN_BT_SLOT, 2432 CXBCN_BT_OK, 2433 CXBCN_MAX 2434 }; 2435 2436 enum btc_slot_type { 2437 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2438 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2439 CXSTYPE_NUM, 2440 }; 2441 2442 enum { /* TIME */ 2443 CXT_BT = 0x0, 2444 CXT_WL = 0x1, 2445 CXT_MAX 2446 }; 2447 2448 enum { /* TIME-A2DP */ 2449 CXT_FLCTRL_OFF = 0x0, 2450 CXT_FLCTRL_ON = 0x1, 2451 CXT_FLCTRL_MAX 2452 }; 2453 2454 enum { /* STEP TYPE */ 2455 CXSTEP_NONE = 0x0, 2456 CXSTEP_EVNT = 0x1, 2457 CXSTEP_SLOT = 0x2, 2458 CXSTEP_MAX, 2459 }; 2460 2461 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2462 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2463 RPT_BT_AFH_SEQ_LE = 0x20 2464 }; 2465 2466 #define BTC_DBG_MAX1 32 2467 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2468 u8 fver; /* btc_ver::fcxgpiodbg */ 2469 u8 rsvd; 2470 __le16 rsvd2; 2471 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2472 __le32 pre_state; /* the debug signal is 1 or 0 */ 2473 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2474 } __packed; 2475 2476 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2477 u8 fver; 2478 u8 rsvd0; 2479 u8 rsvd1; 2480 u8 rsvd2; 2481 2482 u8 gpio_map[BTC_DBG_MAX1]; 2483 2484 __le32 en_map; 2485 __le32 pre_state; 2486 } __packed; 2487 2488 union rtw89_btc_fbtc_gpio_dbg { 2489 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2490 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2491 }; 2492 2493 struct rtw89_btc_fbtc_mreg_val_v1 { 2494 u8 fver; /* btc_ver::fcxmreg */ 2495 u8 reg_num; 2496 __le16 rsvd; 2497 __le32 mreg_val[CXMREG_MAX]; 2498 } __packed; 2499 2500 struct rtw89_btc_fbtc_mreg_val_v2 { 2501 u8 fver; /* btc_ver::fcxmreg */ 2502 u8 reg_num; 2503 __le16 rsvd; 2504 __le32 mreg_val[CXMREG_MAX_V2]; 2505 } __packed; 2506 2507 struct rtw89_btc_fbtc_mreg_val_v7 { 2508 u8 fver; 2509 u8 reg_num; 2510 u8 rsvd0; 2511 u8 rsvd1; 2512 __le32 mreg_val[CXMREG_MAX_V2]; 2513 } __packed; 2514 2515 union rtw89_btc_fbtc_mreg_val { 2516 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2517 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2518 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2519 }; 2520 2521 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2522 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2523 .offset = cpu_to_le32(__offset), } 2524 2525 struct rtw89_btc_fbtc_mreg { 2526 __le16 type; 2527 __le16 bytes; 2528 __le32 offset; 2529 } __packed; 2530 2531 struct rtw89_btc_fbtc_slot { 2532 __le16 dur; 2533 __le32 cxtbl; 2534 __le16 cxtype; 2535 } __packed; 2536 2537 struct rtw89_btc_fbtc_slots { 2538 u8 fver; /* btc_ver::fcxslots */ 2539 u8 tbl_num; 2540 __le16 rsvd; 2541 __le32 update_map; 2542 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2543 } __packed; 2544 2545 struct rtw89_btc_fbtc_slot_v7 { 2546 __le16 dur; /* slot duration */ 2547 __le16 cxtype; 2548 __le32 cxtbl; 2549 } __packed; 2550 2551 struct rtw89_btc_fbtc_slot_u16 { 2552 __le16 dur; /* slot duration */ 2553 __le16 cxtype; 2554 __le16 cxtbl_l16; /* coex table [15:0] */ 2555 __le16 cxtbl_h16; /* coex table [31:16] */ 2556 } __packed; 2557 2558 struct rtw89_btc_fbtc_1slot_v7 { 2559 u8 fver; 2560 u8 sid; /* slot id */ 2561 __le16 rsvd; 2562 struct rtw89_btc_fbtc_slot_v7 slot; 2563 } __packed; 2564 2565 struct rtw89_btc_fbtc_slots_v7 { 2566 u8 fver; 2567 u8 slot_cnt; 2568 u8 rsvd0; 2569 u8 rsvd1; 2570 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2571 __le32 update_map; 2572 } __packed; 2573 2574 union rtw89_btc_fbtc_slots_info { 2575 struct rtw89_btc_fbtc_slots v1; 2576 struct rtw89_btc_fbtc_slots_v7 v7; 2577 } __packed; 2578 2579 struct rtw89_btc_fbtc_step { 2580 u8 type; 2581 u8 val; 2582 __le16 difft; 2583 } __packed; 2584 2585 struct rtw89_btc_fbtc_steps_v2 { 2586 u8 fver; /* btc_ver::fcxstep */ 2587 u8 rsvd; 2588 __le16 cnt; 2589 __le16 pos_old; 2590 __le16 pos_new; 2591 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2592 } __packed; 2593 2594 struct rtw89_btc_fbtc_steps_v3 { 2595 u8 fver; 2596 u8 en; 2597 __le16 rsvd; 2598 __le32 cnt; 2599 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2600 } __packed; 2601 2602 union rtw89_btc_fbtc_steps_info { 2603 struct rtw89_btc_fbtc_steps_v2 v2; 2604 struct rtw89_btc_fbtc_steps_v3 v3; 2605 }; 2606 2607 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2608 u8 fver; /* btc_ver::fcxcysta */ 2609 u8 rsvd; 2610 __le16 cycles; /* total cycle number */ 2611 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2612 __le16 a2dpept; /* a2dp empty cnt */ 2613 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2614 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2615 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2616 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2617 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2618 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2619 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2620 __le16 tmax_a2dpept; /* max a2dp empty time */ 2621 __le16 tavg_lk; /* avg leak-slot time */ 2622 __le16 tmax_lk; /* max leak-slot time */ 2623 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2624 __le32 bcn_cnt[CXBCN_MAX]; 2625 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2626 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2627 __le32 skip_cnt; 2628 __le32 exception; 2629 __le32 except_cnt; 2630 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2631 } __packed; 2632 2633 struct rtw89_btc_fbtc_fdd_try_info { 2634 __le16 cycles[CXT_FLCTRL_MAX]; 2635 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2636 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2637 } __packed; 2638 2639 struct rtw89_btc_fbtc_cycle_time_info { 2640 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2641 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2642 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2643 } __packed; 2644 2645 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2646 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2647 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2648 } __packed; 2649 2650 struct rtw89_btc_fbtc_a2dp_trx_stat { 2651 u8 empty_cnt; 2652 u8 retry_cnt; 2653 u8 tx_rate; 2654 u8 tx_cnt; 2655 u8 ack_cnt; 2656 u8 nack_cnt; 2657 u8 rsvd1; 2658 u8 rsvd2; 2659 } __packed; 2660 2661 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2662 u8 empty_cnt; 2663 u8 retry_cnt; 2664 u8 tx_rate; 2665 u8 tx_cnt; 2666 u8 ack_cnt; 2667 u8 nack_cnt; 2668 u8 no_empty_cnt; 2669 u8 rsvd; 2670 } __packed; 2671 2672 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2673 __le16 cnt; /* a2dp empty cnt */ 2674 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2675 __le16 tavg; /* avg a2dp empty time */ 2676 __le16 tmax; /* max a2dp empty time */ 2677 } __packed; 2678 2679 struct rtw89_btc_fbtc_cycle_leak_info { 2680 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2681 __le16 tavg; /* avg leak-slot time */ 2682 __le16 tmax; /* max leak-slot time */ 2683 } __packed; 2684 2685 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2686 __le16 tavg; 2687 __le16 tamx; 2688 __le32 cnt_rximr; 2689 } __packed; 2690 2691 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2692 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2693 2694 struct rtw89_btc_fbtc_cycle_fddt_info { 2695 __le16 train_cycle; 2696 __le16 tp; 2697 2698 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2699 s8 bt_tx_power; /* decrease Tx power (dB) */ 2700 s8 bt_rx_gain; /* LNA constrain level */ 2701 u8 no_empty_cnt; 2702 2703 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2704 u8 cn; /* condition_num */ 2705 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2706 u8 train_result; /* refer to enum btc_fddt_check_map */ 2707 } __packed; 2708 2709 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2710 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2711 2712 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2713 __le16 train_cycle; 2714 __le16 tp; 2715 2716 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2717 s8 bt_tx_power; /* decrease Tx power (dB) */ 2718 s8 bt_rx_gain; /* LNA constrain level */ 2719 u8 no_empty_cnt; 2720 2721 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2722 u8 cn; /* condition_num */ 2723 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2724 u8 train_result; /* refer to enum btc_fddt_check_map */ 2725 } __packed; 2726 2727 struct rtw89_btc_fbtc_fddt_cell_status { 2728 s8 wl_tx_pwr; 2729 s8 bt_tx_pwr; 2730 s8 bt_rx_gain; 2731 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2732 } __packed; 2733 2734 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2735 u8 fver; 2736 u8 rsvd; 2737 __le16 cycles; /* total cycle number */ 2738 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2739 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2740 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2741 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2742 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2743 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2744 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2745 __le32 bcn_cnt[CXBCN_MAX]; 2746 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2747 __le32 skip_cnt; 2748 __le32 except_cnt; 2749 __le32 except_map; 2750 } __packed; 2751 2752 #define FDD_TRAIN_WL_DIRECTION 2 2753 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2754 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2755 2756 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2757 u8 fver; 2758 u8 rsvd; 2759 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2760 u8 except_cnt; 2761 2762 __le16 skip_cnt; 2763 __le16 cycles; /* total cycle number */ 2764 2765 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2766 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2767 __le16 bcn_cnt[CXBCN_MAX]; 2768 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2769 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2770 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2771 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2772 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2773 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2774 [FDD_TRAIN_WL_RSSI_LEVEL] 2775 [FDD_TRAIN_BT_RSSI_LEVEL]; 2776 __le32 except_map; 2777 } __packed; 2778 2779 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2780 u8 fver; 2781 u8 rsvd; 2782 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2783 u8 except_cnt; 2784 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2785 2786 __le16 skip_cnt; 2787 __le16 cycles; /* total cycle number */ 2788 2789 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2790 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2791 __le16 bcn_cnt[CXBCN_MAX]; 2792 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2793 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2794 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2795 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2796 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2797 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2798 [FDD_TRAIN_WL_RSSI_LEVEL] 2799 [FDD_TRAIN_BT_RSSI_LEVEL]; 2800 __le32 except_map; 2801 } __packed; 2802 2803 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2804 u8 fver; 2805 u8 rsvd; 2806 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2807 u8 except_cnt; 2808 2809 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2810 2811 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2812 2813 __le16 skip_cnt; 2814 __le16 cycles; /* total cycle number */ 2815 2816 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2817 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2818 __le16 bcn_cnt[CXBCN_MAX]; 2819 2820 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2821 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2822 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2823 2824 __le32 except_map; 2825 } __packed; 2826 2827 union rtw89_btc_fbtc_cysta_info { 2828 struct rtw89_btc_fbtc_cysta_v2 v2; 2829 struct rtw89_btc_fbtc_cysta_v3 v3; 2830 struct rtw89_btc_fbtc_cysta_v4 v4; 2831 struct rtw89_btc_fbtc_cysta_v5 v5; 2832 struct rtw89_btc_fbtc_cysta_v7 v7; 2833 }; 2834 2835 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2836 u8 fver; /* btc_ver::fcxnullsta */ 2837 u8 rsvd; 2838 __le16 rsvd2; 2839 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2840 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2841 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2842 } __packed; 2843 2844 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2845 u8 fver; /* btc_ver::fcxnullsta */ 2846 u8 rsvd; 2847 __le16 rsvd2; 2848 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2849 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2850 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2851 } __packed; 2852 2853 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2854 u8 fver; 2855 u8 rsvd0; 2856 u8 rsvd1; 2857 u8 rsvd2; 2858 2859 __le32 tmax[2]; 2860 __le32 tavg[2]; 2861 __le32 result[2][5]; 2862 } __packed; 2863 2864 union rtw89_btc_fbtc_cynullsta_info { 2865 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2866 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2867 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2868 }; 2869 2870 struct rtw89_btc_fbtc_btver_v1 { 2871 u8 fver; /* btc_ver::fcxbtver */ 2872 u8 rsvd; 2873 __le16 rsvd2; 2874 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2875 __le32 fw_ver; 2876 __le32 feature; 2877 } __packed; 2878 2879 struct rtw89_btc_fbtc_btver_v7 { 2880 u8 fver; 2881 u8 rsvd0; 2882 u8 rsvd1; 2883 u8 rsvd2; 2884 2885 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2886 __le32 fw_ver; 2887 __le32 feature; 2888 } __packed; 2889 2890 union rtw89_btc_fbtc_btver { 2891 struct rtw89_btc_fbtc_btver_v1 v1; 2892 struct rtw89_btc_fbtc_btver_v7 v7; 2893 } __packed; 2894 2895 struct rtw89_btc_fbtc_btafh { 2896 u8 fver; /* btc_ver::fcxbtafh */ 2897 u8 rsvd; 2898 __le16 rsvd2; 2899 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2900 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2901 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2902 } __packed; 2903 2904 struct rtw89_btc_fbtc_btafh_v2 { 2905 u8 fver; /* btc_ver::fcxbtafh */ 2906 u8 rsvd; 2907 u8 rsvd2; 2908 u8 map_type; 2909 u8 afh_l[4]; 2910 u8 afh_m[4]; 2911 u8 afh_h[4]; 2912 u8 afh_le_a[4]; 2913 u8 afh_le_b[4]; 2914 } __packed; 2915 2916 struct rtw89_btc_fbtc_btafh_v7 { 2917 u8 fver; 2918 u8 map_type; 2919 u8 rsvd0; 2920 u8 rsvd1; 2921 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2922 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2923 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2924 u8 afh_le_a[4]; 2925 u8 afh_le_b[4]; 2926 } __packed; 2927 2928 struct rtw89_btc_fbtc_btdevinfo { 2929 u8 fver; /* btc_ver::fcxbtdevinfo */ 2930 u8 rsvd; 2931 __le16 vendor_id; 2932 __le32 dev_name; /* only 24 bits valid */ 2933 __le32 flush_time; 2934 } __packed; 2935 2936 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2937 struct rtw89_btc_rf_trx_para { 2938 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2939 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2940 u8 bt_tx_power; /* decrease Tx power (dB) */ 2941 u8 bt_rx_gain; /* LNA constrain level */ 2942 }; 2943 2944 struct rtw89_btc_trx_info { 2945 u8 tx_lvl; 2946 u8 rx_lvl; 2947 u8 wl_rssi; 2948 u8 bt_rssi; 2949 2950 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2951 s8 rx_gain; /* rx gain table index (TBD.) */ 2952 s8 bt_tx_power; /* decrease Tx power (dB) */ 2953 s8 bt_rx_gain; /* LNA constrain level */ 2954 2955 u8 cn; /* condition_num */ 2956 s8 nhm; 2957 u8 bt_profile; 2958 u8 rsvd2; 2959 2960 u16 tx_rate; 2961 u16 rx_rate; 2962 2963 u32 tx_tp; 2964 u32 rx_tp; 2965 u32 rx_err_ratio; 2966 }; 2967 2968 enum btc_rf_path { 2969 BTC_RF_S0 = 0, 2970 BTC_RF_S1 = 1, 2971 BTC_RF_NUM, 2972 }; 2973 2974 struct rtw89_btc_fbtc_outsrc_set_info { 2975 u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */ 2976 u8 btg_rx[BTC_RF_NUM]; 2977 u8 nbtg_tx[BTC_RF_NUM]; 2978 2979 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */ 2980 struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */ 2981 2982 u8 pta_req_hw_band; 2983 u8 rf_gbt_source; 2984 } __packed; 2985 2986 union rtw89_btc_fbtc_slot_u { 2987 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2988 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2989 }; 2990 2991 struct rtw89_btc_dm { 2992 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */ 2993 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */ 2994 union rtw89_btc_fbtc_slot_u slot; 2995 union rtw89_btc_fbtc_slot_u slot_now; 2996 struct rtw89_btc_fbtc_tdma tdma; 2997 struct rtw89_btc_fbtc_tdma tdma_now; 2998 struct rtw89_mac_ax_coex_gnt gnt; 2999 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 3000 struct rtw89_btc_rf_trx_para rf_trx_para; 3001 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 3002 struct rtw89_btc_dm_step dm_step; 3003 struct rtw89_btc_wl_scc_ctrl wl_scc; 3004 struct rtw89_btc_trx_info trx_info; 3005 union rtw89_btc_dm_error_map error; 3006 u32 cnt_dm[BTC_DCNT_NUM]; 3007 u32 cnt_notify[BTC_NCNT_NUM]; 3008 3009 u32 update_slot_map; 3010 u32 set_ant_path; 3011 u32 e2g_slot_limit; 3012 u32 e2g_slot_nulltx_time; 3013 3014 u32 wl_only: 1; 3015 u32 wl_fw_cx_offload: 1; 3016 u32 freerun: 1; 3017 u32 fddt_train: 1; 3018 u32 wl_ps_ctrl: 2; 3019 u32 wl_mimo_ps: 1; 3020 u32 leak_ap: 1; 3021 u32 noisy_level: 3; 3022 u32 coex_info_map: 8; 3023 u32 bt_only: 1; 3024 u32 wl_btg_rx: 2; 3025 u32 trx_para_level: 8; 3026 u32 wl_stb_chg: 1; 3027 u32 pta_owner: 1; 3028 3029 u32 tdma_instant_excute: 1; 3030 u32 wl_btg_rx_rb: 2; 3031 3032 u16 slot_dur[CXST_MAX]; 3033 u16 bt_slot_flood; 3034 3035 u8 run_reason; 3036 u8 run_action; 3037 3038 u8 wl_pre_agc: 2; 3039 u8 wl_lna2: 1; 3040 u8 freerun_chk: 1; 3041 u8 wl_pre_agc_rb: 2; 3042 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 3043 u8 slot_req_more: 1; 3044 }; 3045 3046 struct rtw89_btc_ctrl { 3047 u32 manual: 1; 3048 u32 igno_bt: 1; 3049 u32 always_freerun: 1; 3050 u32 trace_step: 16; 3051 u32 rsvd: 12; 3052 }; 3053 3054 struct rtw89_btc_ctrl_v7 { 3055 u8 manual; 3056 u8 igno_bt; 3057 u8 always_freerun; 3058 u8 rsvd; 3059 } __packed; 3060 3061 union rtw89_btc_ctrl_list { 3062 struct rtw89_btc_ctrl ctrl; 3063 struct rtw89_btc_ctrl_v7 ctrl_v7; 3064 }; 3065 3066 struct rtw89_btc_dbg { 3067 /* cmd "rb" */ 3068 bool rb_done; 3069 u32 rb_val; 3070 }; 3071 3072 enum rtw89_btc_btf_fw_event { 3073 BTF_EVNT_RPT = 0, 3074 BTF_EVNT_BT_INFO = 1, 3075 BTF_EVNT_BT_SCBD = 2, 3076 BTF_EVNT_BT_REG = 3, 3077 BTF_EVNT_CX_RUNINFO = 4, 3078 BTF_EVNT_BT_PSD = 5, 3079 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 3080 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 3081 BTF_EVNT_BUF_OVERFLOW, 3082 BTF_EVNT_C2H_LOOPBACK, 3083 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */ 3084 BTF_EVNT_MAX, 3085 }; 3086 3087 enum btf_fw_event_report { 3088 BTC_RPT_TYPE_CTRL = 0x0, 3089 BTC_RPT_TYPE_TDMA, 3090 BTC_RPT_TYPE_SLOT, 3091 BTC_RPT_TYPE_CYSTA, 3092 BTC_RPT_TYPE_STEP, 3093 BTC_RPT_TYPE_NULLSTA, 3094 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3095 BTC_RPT_TYPE_MREG, 3096 BTC_RPT_TYPE_GPIO_DBG, 3097 BTC_RPT_TYPE_BT_VER, 3098 BTC_RPT_TYPE_BT_SCAN, 3099 BTC_RPT_TYPE_BT_AFH, 3100 BTC_RPT_TYPE_BT_DEVICE, 3101 BTC_RPT_TYPE_TEST, 3102 BTC_RPT_TYPE_MAX = 31, 3103 3104 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3105 __BTC_RPT_TYPE_V0_MAX = 12, 3106 }; 3107 3108 enum rtw_btc_btf_reg_type { 3109 REG_MAC = 0x0, 3110 REG_BB = 0x1, 3111 REG_RF = 0x2, 3112 REG_BT_RF = 0x3, 3113 REG_BT_MODEM = 0x4, 3114 REG_BT_BLUEWIZE = 0x5, 3115 REG_BT_VENDOR = 0x6, 3116 REG_BT_LE = 0x7, 3117 REG_MAX_TYPE, 3118 }; 3119 3120 struct rtw89_btc_rpt_cmn_info { 3121 u32 rx_cnt; 3122 u32 rx_len; 3123 u32 req_len; /* expected rsp len */ 3124 u8 req_fver; /* expected rsp fver */ 3125 u8 rsp_fver; /* fver from fw */ 3126 u8 valid; 3127 } __packed; 3128 3129 union rtw89_btc_fbtc_btafh_info { 3130 struct rtw89_btc_fbtc_btafh v1; 3131 struct rtw89_btc_fbtc_btafh_v2 v2; 3132 struct rtw89_btc_fbtc_btafh_v7 v7; 3133 }; 3134 3135 struct rtw89_btc_report_ctrl_state { 3136 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3137 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3138 }; 3139 3140 struct rtw89_btc_rpt_fbtc_tdma { 3141 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3142 union rtw89_btc_fbtc_tdma_le32 finfo; 3143 }; 3144 3145 struct rtw89_btc_rpt_fbtc_slots { 3146 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3147 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3148 }; 3149 3150 struct rtw89_btc_rpt_fbtc_cysta { 3151 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3152 union rtw89_btc_fbtc_cysta_info finfo; 3153 }; 3154 3155 struct rtw89_btc_rpt_fbtc_step { 3156 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3157 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3158 }; 3159 3160 struct rtw89_btc_rpt_fbtc_nullsta { 3161 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3162 union rtw89_btc_fbtc_cynullsta_info finfo; 3163 }; 3164 3165 struct rtw89_btc_rpt_fbtc_mreg { 3166 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3167 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3168 }; 3169 3170 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3171 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3172 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3173 }; 3174 3175 struct rtw89_btc_rpt_fbtc_btver { 3176 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3177 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3178 }; 3179 3180 struct rtw89_btc_rpt_fbtc_btscan { 3181 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3182 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3183 }; 3184 3185 struct rtw89_btc_rpt_fbtc_btafh { 3186 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3187 union rtw89_btc_fbtc_btafh_info finfo; 3188 }; 3189 3190 struct rtw89_btc_rpt_fbtc_btdev { 3191 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3192 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3193 }; 3194 3195 enum rtw89_btc_btfre_type { 3196 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3197 BTFRE_UNDEF_TYPE, 3198 BTFRE_EXCEPTION, 3199 BTFRE_MAX, 3200 }; 3201 3202 struct rtw89_btc_ver { 3203 enum rtw89_core_chip_id chip_id; 3204 u32 fw_ver_code; 3205 3206 u8 fcxbtcrpt; 3207 u8 fcxtdma; 3208 u8 fcxslots; 3209 u8 fcxcysta; 3210 u8 fcxstep; 3211 u8 fcxnullsta; 3212 u8 fcxmreg; 3213 u8 fcxgpiodbg; 3214 u8 fcxbtver; 3215 u8 fcxbtscan; 3216 u8 fcxbtafh; 3217 u8 fcxbtdevinfo; 3218 u8 fwlrole; 3219 u8 frptmap; 3220 u8 fcxctrl; 3221 u8 fcxinit; 3222 3223 u8 fwevntrptl; 3224 u8 fwc2hfunc; 3225 u8 drvinfo_type; 3226 u16 info_buf; 3227 u8 max_role_num; 3228 u8 fcxosi; 3229 u8 fcxmlo; 3230 u8 bt_desired; 3231 }; 3232 3233 struct rtw89_btc_btf_fwinfo { 3234 u32 cnt_c2h; 3235 u32 cnt_h2c; 3236 u32 cnt_h2c_fail; 3237 u32 event[BTF_EVNT_MAX]; 3238 3239 u32 err[BTFRE_MAX]; 3240 u32 len_mismch; 3241 u32 fver_mismch; 3242 u32 rpt_en_map; 3243 3244 struct rtw89_btc_ver fw_subver; 3245 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3246 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3247 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3248 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3249 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3250 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3251 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3252 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3253 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3254 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3255 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3256 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3257 }; 3258 3259 #define RTW89_BTC_POLICY_MAXLEN 512 3260 3261 struct rtw89_btc { 3262 const struct rtw89_btc_ver *ver; 3263 3264 struct rtw89_btc_cx cx; 3265 struct rtw89_btc_dm dm; 3266 union rtw89_btc_ctrl_list ctrl; 3267 union rtw89_btc_module_info mdinfo; 3268 struct rtw89_btc_btf_fwinfo fwinfo; 3269 struct rtw89_btc_dbg dbg; 3270 3271 struct wiphy_work eapol_notify_work; 3272 struct wiphy_work arp_notify_work; 3273 struct wiphy_work dhcp_notify_work; 3274 struct wiphy_work icmp_notify_work; 3275 3276 u32 bt_req_len; 3277 3278 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3279 u8 ant_type; 3280 u8 btg_pos; 3281 u16 policy_len; 3282 u16 policy_type; 3283 u32 hubmsg_cnt; 3284 bool bt_req_en; 3285 bool update_policy_force; 3286 bool lps; 3287 bool manual_ctrl; 3288 }; 3289 3290 enum rtw89_btc_hmsg { 3291 RTW89_BTC_HMSG_TMR_EN = 0x0, 3292 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3293 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3294 RTW89_BTC_HMSG_FW_EV = 0x3, 3295 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3296 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3297 3298 NUM_OF_RTW89_BTC_HMSG, 3299 }; 3300 3301 enum rtw89_ra_mode { 3302 RTW89_RA_MODE_CCK = BIT(0), 3303 RTW89_RA_MODE_OFDM = BIT(1), 3304 RTW89_RA_MODE_HT = BIT(2), 3305 RTW89_RA_MODE_VHT = BIT(3), 3306 RTW89_RA_MODE_HE = BIT(4), 3307 RTW89_RA_MODE_EHT = BIT(5), 3308 }; 3309 3310 enum rtw89_ra_report_mode { 3311 RTW89_RA_RPT_MODE_LEGACY, 3312 RTW89_RA_RPT_MODE_HT, 3313 RTW89_RA_RPT_MODE_VHT, 3314 RTW89_RA_RPT_MODE_HE, 3315 RTW89_RA_RPT_MODE_EHT, 3316 }; 3317 3318 enum rtw89_dig_noisy_level { 3319 RTW89_DIG_NOISY_LEVEL0 = -1, 3320 RTW89_DIG_NOISY_LEVEL1 = 0, 3321 RTW89_DIG_NOISY_LEVEL2 = 1, 3322 RTW89_DIG_NOISY_LEVEL3 = 2, 3323 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3324 }; 3325 3326 enum rtw89_gi_ltf { 3327 RTW89_GILTF_LGI_4XHE32 = 0, 3328 RTW89_GILTF_SGI_4XHE08 = 1, 3329 RTW89_GILTF_2XHE16 = 2, 3330 RTW89_GILTF_2XHE08 = 3, 3331 RTW89_GILTF_1XHE16 = 4, 3332 RTW89_GILTF_1XHE08 = 5, 3333 RTW89_GILTF_MAX 3334 }; 3335 3336 enum rtw89_rx_frame_type { 3337 RTW89_RX_TYPE_MGNT = 0, 3338 RTW89_RX_TYPE_CTRL = 1, 3339 RTW89_RX_TYPE_DATA = 2, 3340 RTW89_RX_TYPE_RSVD = 3, 3341 }; 3342 3343 enum rtw89_efuse_block { 3344 RTW89_EFUSE_BLOCK_SYS = 0, 3345 RTW89_EFUSE_BLOCK_RF = 1, 3346 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3347 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3348 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3349 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3350 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3351 RTW89_EFUSE_BLOCK_ADIE = 7, 3352 3353 RTW89_EFUSE_BLOCK_NUM, 3354 RTW89_EFUSE_BLOCK_IGNORE, 3355 }; 3356 3357 struct rtw89_ra_info { 3358 u8 is_dis_ra:1; 3359 /* Bit0 : CCK 3360 * Bit1 : OFDM 3361 * Bit2 : HT 3362 * Bit3 : VHT 3363 * Bit4 : HE 3364 * Bit5 : EHT 3365 */ 3366 u8 mode_ctrl:6; 3367 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3368 u8 macid; 3369 u8 dcm_cap:1; 3370 u8 er_cap:1; 3371 u8 init_rate_lv:2; 3372 u8 upd_all:1; 3373 u8 en_sgi:1; 3374 u8 ldpc_cap:1; 3375 u8 stbc_cap:1; 3376 u8 ss_num:3; 3377 u8 giltf:3; 3378 u8 upd_bw_nss_mask:1; 3379 u8 upd_mask:1; 3380 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3381 /* BFee CSI */ 3382 u8 band_num; 3383 u8 ra_csi_rate_en:1; 3384 u8 fixed_csi_rate_en:1; 3385 u8 cr_tbl_sel:1; 3386 u8 fix_giltf_en:1; 3387 u8 fix_giltf:3; 3388 u8 partial_bw_er:1; 3389 u8 csi_mcs_ss_idx; 3390 u8 csi_mode:2; 3391 u8 csi_gi_ltf:3; 3392 u8 csi_bw:3; 3393 /* after v1 */ 3394 u8 is_noisy:1; 3395 u8 psra_en:1; 3396 u8 rsvd0:1; 3397 u8 macid_msb:2; 3398 u8 band:2; /* enum rtw89_band */ 3399 u8 is_new_dbgreg:1; 3400 }; 3401 3402 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3403 #define RTW89_PPDU_MAC_INFO_SIZE 8 3404 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3405 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3406 3407 #define RTW89_MAX_RX_AGG_NUM 64 3408 #define RTW89_MAX_TX_AGG_NUM 128 3409 3410 struct rtw89_ampdu_params { 3411 u16 agg_num; 3412 bool amsdu; 3413 }; 3414 3415 struct rtw89_ra_report { 3416 struct rate_info txrate; 3417 u32 bit_rate; 3418 u16 hw_rate; 3419 bool might_fallback_legacy; 3420 }; 3421 3422 DECLARE_EWMA(rssi, 10, 16); 3423 DECLARE_EWMA(evm, 10, 16); 3424 DECLARE_EWMA(snr, 10, 16); 3425 3426 struct rtw89_ba_cam_entry { 3427 struct list_head list; 3428 u8 tid; 3429 }; 3430 3431 #define RTW89_MAX_ADDR_CAM_NUM 128 3432 #define RTW89_MAX_BSSID_CAM_NUM 20 3433 #define RTW89_MAX_SEC_CAM_NUM 128 3434 #define RTW89_MAX_BA_CAM_NUM 24 3435 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3436 3437 struct rtw89_addr_cam_entry { 3438 u8 addr_cam_idx; 3439 u8 offset; 3440 u8 len; 3441 u8 valid : 1; 3442 u8 addr_mask : 6; 3443 u8 wapi : 1; 3444 u8 mask_sel : 2; 3445 u8 bssid_cam_idx: 6; 3446 3447 u8 sec_ent_mode; 3448 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3449 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3450 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3451 }; 3452 3453 struct rtw89_bssid_cam_entry { 3454 u8 bssid[ETH_ALEN]; 3455 u8 phy_idx; 3456 u8 bssid_cam_idx; 3457 u8 offset; 3458 u8 len; 3459 u8 valid : 1; 3460 u8 num; 3461 }; 3462 3463 struct rtw89_sec_cam_entry { 3464 u8 sec_cam_idx; 3465 u8 offset; 3466 u8 len; 3467 u8 type : 4; 3468 u8 ext_key : 1; 3469 u8 spp_mode : 1; 3470 /* 256 bits */ 3471 u8 key[32]; 3472 3473 struct ieee80211_key_conf *key_conf; 3474 }; 3475 3476 struct rtw89_sta_link { 3477 struct rtw89_sta *rtwsta; 3478 struct list_head dlink_schd; 3479 unsigned int link_id; 3480 3481 u8 mac_id; 3482 u8 tx_retry; 3483 bool er_cap; 3484 struct rtw89_vif_link *rtwvif_link; 3485 struct rtw89_ra_info ra; 3486 struct rtw89_ra_report ra_report; 3487 int max_agg_wait; 3488 u8 prev_rssi; 3489 struct ewma_rssi avg_rssi; 3490 struct ewma_rssi rssi[RF_PATH_MAX]; 3491 struct ewma_snr avg_snr; 3492 struct ewma_evm evm_1ss; 3493 struct ewma_evm evm_min[RF_PATH_MAX]; 3494 struct ewma_evm evm_max[RF_PATH_MAX]; 3495 struct ieee80211_rx_status rx_status; 3496 u16 rx_hw_rate; 3497 __le32 htc_template; 3498 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3499 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3500 struct list_head ba_cam_list; 3501 3502 bool use_cfg_mask; 3503 struct cfg80211_bitrate_mask mask; 3504 3505 bool cctl_tx_time; 3506 u32 ampdu_max_time:4; 3507 bool cctl_tx_retry_limit; 3508 u32 data_tx_cnt_lmt:6; 3509 }; 3510 3511 struct rtw89_efuse { 3512 bool valid; 3513 bool power_k_valid; 3514 u8 xtal_cap; 3515 u8 addr[ETH_ALEN]; 3516 u8 rfe_type; 3517 char country_code[2]; 3518 u8 adc_td; 3519 }; 3520 3521 struct rtw89_phy_rate_pattern { 3522 u64 ra_mask; 3523 u16 rate; 3524 u8 ra_mode; 3525 bool enable; 3526 }; 3527 3528 #define RTW89_TX_DONE 0x0 3529 #define RTW89_TX_RETRY_LIMIT 0x1 3530 #define RTW89_TX_LIFE_TIME 0x2 3531 #define RTW89_TX_MACID_DROP 0x3 3532 3533 #define RTW89_MAX_TX_RPTS 16 3534 #define RTW89_MAX_TX_RPTS_MASK (RTW89_MAX_TX_RPTS - 1) 3535 struct rtw89_tx_rpt { 3536 struct sk_buff *skbs[RTW89_MAX_TX_RPTS]; 3537 /* protect skbs array access/modification */ 3538 spinlock_t skb_lock; 3539 atomic_t sn; 3540 }; 3541 3542 #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500) 3543 struct rtw89_tx_wait_info { 3544 struct rcu_head rcu_head; 3545 struct list_head list; 3546 struct completion completion; 3547 struct sk_buff *skb; 3548 bool tx_done; 3549 }; 3550 3551 struct rtw89_tx_skb_data { 3552 struct rtw89_tx_wait_info __rcu *wait; 3553 u8 tx_rpt_sn; 3554 u8 tx_pkt_cnt_lmt; 3555 u8 hci_priv[]; 3556 }; 3557 3558 #define RTW89_SCAN_NULL_TIMEOUT 30 3559 3560 #define RTW89_ROC_IDLE_TIMEOUT 500 3561 #define RTW89_ROC_TX_TIMEOUT 30 3562 enum rtw89_roc_state { 3563 RTW89_ROC_IDLE, 3564 RTW89_ROC_NORMAL, 3565 RTW89_ROC_MGMT, 3566 }; 3567 3568 struct rtw89_roc { 3569 struct ieee80211_channel chan; 3570 struct wiphy_delayed_work roc_work; 3571 enum ieee80211_roc_type type; 3572 enum rtw89_roc_state state; 3573 int duration; 3574 unsigned int link_id; 3575 }; 3576 3577 #define RTW89_P2P_MAX_NOA_NUM 2 3578 3579 struct rtw89_p2p_ie_head { 3580 u8 eid; 3581 u8 ie_len; 3582 u8 oui[3]; 3583 u8 oui_type; 3584 } __packed; 3585 3586 struct rtw89_noa_attr_head { 3587 u8 attr_type; 3588 __le16 attr_len; 3589 u8 index; 3590 u8 oppps_ctwindow; 3591 } __packed; 3592 3593 struct rtw89_p2p_noa_ie { 3594 struct rtw89_p2p_ie_head p2p_head; 3595 struct rtw89_noa_attr_head noa_head; 3596 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3597 } __packed; 3598 3599 struct rtw89_p2p_noa_setter { 3600 struct rtw89_p2p_noa_ie ie; 3601 u8 noa_count; 3602 u8 noa_index; 3603 }; 3604 3605 struct rtw89_ps_noa_once_handler { 3606 bool in_duration; 3607 u64 tsf_begin; 3608 u64 tsf_end; 3609 struct wiphy_delayed_work set_work; 3610 struct wiphy_delayed_work clr_work; 3611 }; 3612 3613 struct rtw89_vif_link { 3614 struct rtw89_vif *rtwvif; 3615 struct list_head dlink_schd; 3616 unsigned int link_id; 3617 3618 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3619 enum rtw89_chanctx_idx chanctx_idx; 3620 enum rtw89_reg_6ghz_power reg_6ghz_power; 3621 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3622 3623 u8 mac_id; 3624 u8 port; 3625 u8 mac_addr[ETH_ALEN]; 3626 u8 bssid[ETH_ALEN]; 3627 u8 phy_idx; 3628 u8 mac_idx; 3629 u8 net_type; 3630 u8 wifi_role; 3631 u8 self_role; 3632 u8 wmm; 3633 u8 bcn_hit_cond; 3634 u8 bcn_bw_idx; 3635 u8 hit_rule; 3636 u8 last_noa_nr; 3637 u64 sync_bcn_tsf; 3638 u64 last_sync_bcn_tsf; 3639 bool rand_tsf_done; 3640 bool trigger; 3641 bool lsig_txop; 3642 u8 tgt_ind; 3643 u8 frm_tgt_ind; 3644 bool wowlan_pattern; 3645 bool wowlan_uc; 3646 bool wowlan_magic; 3647 bool is_hesta; 3648 bool last_a_ctrl; 3649 bool dyn_tb_bedge_en; 3650 bool pre_pwr_diff_en; 3651 bool pwr_diff_en; 3652 u8 def_tri_idx; 3653 struct wiphy_work update_beacon_work; 3654 struct wiphy_delayed_work csa_beacon_work; 3655 struct rtw89_addr_cam_entry addr_cam; 3656 struct rtw89_bssid_cam_entry bssid_cam; 3657 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3658 struct rtw89_phy_rate_pattern rate_pattern; 3659 struct list_head general_pkt_list; 3660 struct rtw89_p2p_noa_setter p2p_noa; 3661 struct rtw89_ps_noa_once_handler noa_once; 3662 struct wiphy_delayed_work mcc_gc_detect_beacon_work; 3663 u8 detect_bcn_count; 3664 }; 3665 3666 enum rtw89_lv1_rcvy_step { 3667 RTW89_LV1_RCVY_STEP_1, 3668 RTW89_LV1_RCVY_STEP_2, 3669 }; 3670 3671 struct rtw89_hci_ops { 3672 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3673 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3674 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3675 void (*reset)(struct rtw89_dev *rtwdev); 3676 int (*start)(struct rtw89_dev *rtwdev); 3677 void (*stop)(struct rtw89_dev *rtwdev); 3678 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3679 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3680 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3681 3682 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3683 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3684 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3685 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3686 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3687 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3688 3689 u32 (*read32_pci_cfg)(struct rtw89_dev *rtwdev, u32 addr); 3690 3691 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3692 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3693 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3694 int (*deinit)(struct rtw89_dev *rtwdev); 3695 3696 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3697 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3698 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3699 int (*napi_poll)(struct napi_struct *napi, int budget); 3700 3701 /* Deal with locks inside recovery_start and recovery_complete callbacks 3702 * by hci instance, and handle things which need to consider under SER. 3703 * e.g. turn on/off interrupts except for the one for halt notification. 3704 */ 3705 void (*recovery_start)(struct rtw89_dev *rtwdev); 3706 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3707 3708 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3709 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3710 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3711 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3712 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3713 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3714 void (*disable_intr)(struct rtw89_dev *rtwdev); 3715 void (*enable_intr)(struct rtw89_dev *rtwdev); 3716 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3717 }; 3718 3719 struct rtw89_hci_info { 3720 const struct rtw89_hci_ops *ops; 3721 enum rtw89_hci_type type; 3722 enum rtw89_hci_dle_type dle_type; 3723 u32 rpwm_addr; 3724 u32 cpwm_addr; 3725 bool paused; 3726 bool tx_rpt_enabled; 3727 }; 3728 3729 struct rtw89_chip_ops { 3730 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3731 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3732 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3733 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3734 void (*bb_reset)(struct rtw89_dev *rtwdev, 3735 enum rtw89_phy_idx phy_idx); 3736 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3737 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3738 u32 addr, u32 mask); 3739 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3740 u32 addr, u32 mask, u32 data); 3741 void (*set_channel)(struct rtw89_dev *rtwdev, 3742 const struct rtw89_chan *chan, 3743 enum rtw89_mac_idx mac_idx, 3744 enum rtw89_phy_idx phy_idx); 3745 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3746 struct rtw89_channel_help_params *p, 3747 const struct rtw89_chan *chan, 3748 enum rtw89_mac_idx mac_idx, 3749 enum rtw89_phy_idx phy_idx); 3750 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3751 enum rtw89_efuse_block block); 3752 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3753 void (*fem_setup)(struct rtw89_dev *rtwdev); 3754 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3755 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3756 void (*rfk_init)(struct rtw89_dev *rtwdev); 3757 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3758 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3759 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3760 enum rtw89_phy_idx phy_idx, 3761 const struct rtw89_chan *chan); 3762 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3763 bool start); 3764 void (*rfk_track)(struct rtw89_dev *rtwdev); 3765 void (*power_trim)(struct rtw89_dev *rtwdev); 3766 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3767 const struct rtw89_chan *chan, 3768 enum rtw89_phy_idx phy_idx); 3769 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3770 enum rtw89_phy_idx phy_idx); 3771 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3772 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3773 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev, 3774 const struct rtw89_chan *chan); 3775 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3776 enum rtw89_phy_idx phy_idx); 3777 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3778 struct rtw89_rx_phy_ppdu *phy_ppdu, 3779 struct ieee80211_rx_status *status); 3780 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3781 struct rtw89_rx_phy_ppdu *phy_ppdu); 3782 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3783 struct rtw89_rx_desc_info *desc_info, 3784 struct ieee80211_rx_status *rx_status); 3785 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3786 enum rtw89_phy_idx phy_idx); 3787 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3788 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3789 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3790 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3791 enum rtw89_phy_idx phy_idx); 3792 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3793 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3794 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3795 struct rtw89_rx_desc_info *desc_info, 3796 u8 *data, u32 data_offset); 3797 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3798 struct rtw89_tx_desc_info *desc_info, 3799 void *txdesc); 3800 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3801 struct rtw89_tx_desc_info *desc_info, 3802 void *txdesc); 3803 u8 (*get_ch_dma[RTW89_HCI_TYPE_NUM])(struct rtw89_dev *rtwdev, u8 qsel); 3804 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3805 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3806 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3807 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3808 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3809 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3810 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3811 struct rtw89_vif_link *rtwvif_link, 3812 struct rtw89_sta_link *rtwsta_link); 3813 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3814 struct rtw89_vif_link *rtwvif_link, 3815 struct rtw89_sta_link *rtwsta_link); 3816 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3817 struct rtw89_vif_link *rtwvif_link, 3818 struct rtw89_sta_link *rtwsta_link); 3819 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3820 struct rtw89_vif_link *rtwvif_link, 3821 struct rtw89_sta_link *rtwsta_link); 3822 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 3823 struct rtw89_sta_link *rtwsta_link); 3824 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev, 3825 struct rtw89_vif_link *rtwvif_link, 3826 u16 punctured); 3827 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3828 struct rtw89_vif_link *rtwvif_link, 3829 struct rtw89_sta_link *rtwsta_link); 3830 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3831 struct rtw89_vif_link *rtwvif_link); 3832 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3833 struct rtw89_vif_link *rtwvif_link, 3834 struct rtw89_sta_link *rtwsta_link, 3835 bool valid, struct ieee80211_ampdu_params *params); 3836 3837 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3838 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3839 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3840 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3841 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3842 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3843 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3844 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3845 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3846 }; 3847 3848 enum rtw89_dma_ch { 3849 RTW89_DMA_ACH0 = 0, 3850 RTW89_DMA_ACH1 = 1, 3851 RTW89_DMA_ACH2 = 2, 3852 RTW89_DMA_ACH3 = 3, 3853 RTW89_DMA_ACH4 = 4, 3854 RTW89_DMA_ACH5 = 5, 3855 RTW89_DMA_ACH6 = 6, 3856 RTW89_DMA_ACH7 = 7, 3857 RTW89_DMA_B0MG = 8, 3858 RTW89_DMA_B0HI = 9, 3859 RTW89_DMA_B1MG = 10, 3860 RTW89_DMA_B1HI = 11, 3861 RTW89_DMA_H2C = 12, 3862 RTW89_DMA_CH_NUM = 13 3863 }; 3864 3865 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3866 3867 enum rtw89_mlo_dbcc_mode { 3868 MLO_DBCC_NOT_SUPPORT = 1, 3869 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3870 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3871 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3872 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3873 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3874 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3875 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3876 DBCC_LEGACY = 0xffffffff, 3877 }; 3878 3879 enum rtw89_scan_be_operation { 3880 RTW89_SCAN_OP_STOP, 3881 RTW89_SCAN_OP_START, 3882 RTW89_SCAN_OP_SETPARM, 3883 RTW89_SCAN_OP_GETRPT, 3884 RTW89_SCAN_OP_NUM 3885 }; 3886 3887 enum rtw89_scan_be_mode { 3888 RTW89_SCAN_MODE_SA, 3889 RTW89_SCAN_MODE_MACC, 3890 RTW89_SCAN_MODE_NUM 3891 }; 3892 3893 enum rtw89_scan_be_opmode { 3894 RTW89_SCAN_OPMODE_NONE, 3895 RTW89_SCAN_OPMODE_TBTT, 3896 RTW89_SCAN_OPMODE_INTV, 3897 RTW89_SCAN_OPMODE_CNT, 3898 RTW89_SCAN_OPMODE_NUM, 3899 }; 3900 3901 struct rtw89_scan_option { 3902 bool enable; 3903 bool target_ch_mode; 3904 u8 num_macc_role; 3905 u8 num_opch; 3906 u8 repeat; 3907 u16 norm_pd; 3908 u16 slow_pd; 3909 u16 norm_cy; 3910 u8 opch_end; 3911 u16 delay; /* in unit of ms */ 3912 u64 prohib_chan; 3913 enum rtw89_phy_idx band; 3914 enum rtw89_scan_be_operation operation; 3915 enum rtw89_scan_be_mode scan_mode; 3916 enum rtw89_mlo_dbcc_mode mlo_mode; 3917 }; 3918 3919 enum rtw89_qta_mode { 3920 RTW89_QTA_SCC, 3921 RTW89_QTA_DBCC, 3922 RTW89_QTA_DLFW, 3923 RTW89_QTA_WOW, 3924 3925 /* keep last */ 3926 RTW89_QTA_INVALID, 3927 }; 3928 3929 struct rtw89_hfc_ch_cfg { 3930 u16 min; 3931 u16 max; 3932 #define grp_0 0 3933 #define grp_1 1 3934 #define grp_num 2 3935 u8 grp; 3936 }; 3937 3938 struct rtw89_hfc_ch_info { 3939 u16 aval; 3940 u16 used; 3941 }; 3942 3943 struct rtw89_hfc_pub_cfg { 3944 u16 grp0; 3945 u16 grp1; 3946 u16 pub_max; 3947 u16 wp_thrd; 3948 }; 3949 3950 struct rtw89_hfc_pub_info { 3951 u16 g0_used; 3952 u16 g1_used; 3953 u16 g0_aval; 3954 u16 g1_aval; 3955 u16 pub_aval; 3956 u16 wp_aval; 3957 }; 3958 3959 struct rtw89_hfc_prec_cfg { 3960 u16 ch011_prec; 3961 u16 h2c_prec; 3962 u16 wp_ch07_prec; 3963 u16 wp_ch811_prec; 3964 u8 ch011_full_cond; 3965 u8 h2c_full_cond; 3966 u8 wp_ch07_full_cond; 3967 u8 wp_ch811_full_cond; 3968 }; 3969 3970 struct rtw89_hfc_param { 3971 bool en; 3972 bool h2c_en; 3973 u8 mode; 3974 const struct rtw89_hfc_ch_cfg *ch_cfg; 3975 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3976 struct rtw89_hfc_pub_cfg pub_cfg; 3977 struct rtw89_hfc_pub_info pub_info; 3978 struct rtw89_hfc_prec_cfg prec_cfg; 3979 }; 3980 3981 struct rtw89_hfc_param_ini { 3982 const struct rtw89_hfc_ch_cfg *ch_cfg; 3983 const struct rtw89_hfc_pub_cfg *pub_cfg; 3984 const struct rtw89_hfc_prec_cfg *prec_cfg; 3985 u8 mode; 3986 }; 3987 3988 struct rtw89_dle_size { 3989 u16 pge_size; 3990 u16 lnk_pge_num; 3991 u16 unlnk_pge_num; 3992 /* for WiFi 7 chips below */ 3993 u32 srt_ofst; 3994 }; 3995 3996 struct rtw89_wde_quota { 3997 u16 hif; 3998 u16 wcpu; 3999 u16 pkt_in; 4000 u16 cpu_io; 4001 }; 4002 4003 struct rtw89_ple_quota { 4004 u16 cma0_tx; 4005 u16 cma1_tx; 4006 u16 c2h; 4007 u16 h2c; 4008 u16 wcpu; 4009 u16 mpdu_proc; 4010 u16 cma0_dma; 4011 u16 cma1_dma; 4012 u16 bb_rpt; 4013 u16 wd_rel; 4014 u16 cpu_io; 4015 u16 tx_rpt; 4016 /* for WiFi 7 chips below */ 4017 u16 h2d; 4018 }; 4019 4020 struct rtw89_rsvd_quota { 4021 u16 mpdu_info_tbl; 4022 u16 b0_csi; 4023 u16 b1_csi; 4024 u16 b0_lmr; 4025 u16 b1_lmr; 4026 u16 b0_ftm; 4027 u16 b1_ftm; 4028 u16 b0_smr; 4029 u16 b1_smr; 4030 u16 others; 4031 }; 4032 4033 struct rtw89_dle_rsvd_size { 4034 u32 srt_ofst; 4035 u32 size; 4036 }; 4037 4038 struct rtw89_dle_mem { 4039 enum rtw89_qta_mode mode; 4040 const struct rtw89_dle_size *wde_size; 4041 const struct rtw89_dle_size *ple_size; 4042 const struct rtw89_wde_quota *wde_min_qt; 4043 const struct rtw89_wde_quota *wde_max_qt; 4044 const struct rtw89_ple_quota *ple_min_qt; 4045 const struct rtw89_ple_quota *ple_max_qt; 4046 /* for WiFi 7 chips below */ 4047 const struct rtw89_rsvd_quota *rsvd_qt; 4048 const struct rtw89_dle_rsvd_size *rsvd0_size; 4049 const struct rtw89_dle_rsvd_size *rsvd1_size; 4050 }; 4051 4052 struct rtw89_reg_def { 4053 u32 addr; 4054 u32 mask; 4055 }; 4056 4057 struct rtw89_reg2_def { 4058 u32 addr; 4059 u32 data; 4060 }; 4061 4062 struct rtw89_reg3_def { 4063 u32 addr; 4064 u32 mask; 4065 u32 data; 4066 }; 4067 4068 struct rtw89_reg5_def { 4069 u8 flag; /* recognized by parsers */ 4070 u8 path; 4071 u32 addr; 4072 u32 mask; 4073 u32 data; 4074 }; 4075 4076 struct rtw89_reg_imr { 4077 u32 addr; 4078 u32 clr; 4079 u32 set; 4080 }; 4081 4082 struct rtw89_phy_table { 4083 const struct rtw89_reg2_def *regs; 4084 u32 n_regs; 4085 enum rtw89_rf_path rf_path; 4086 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 4087 enum rtw89_rf_path rf_path, void *data); 4088 }; 4089 4090 struct rtw89_txpwr_table { 4091 const void *data; 4092 u32 size; 4093 void (*load)(struct rtw89_dev *rtwdev, 4094 const struct rtw89_txpwr_table *tbl); 4095 }; 4096 4097 struct rtw89_txpwr_rule_2ghz { 4098 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4099 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4100 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4101 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4102 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4103 }; 4104 4105 struct rtw89_txpwr_rule_5ghz { 4106 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4107 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4108 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4109 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4110 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4111 }; 4112 4113 struct rtw89_txpwr_rule_6ghz { 4114 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4115 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4116 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4117 [RTW89_6G_CH_NUM]; 4118 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4119 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4120 [RTW89_6G_CH_NUM]; 4121 }; 4122 4123 struct rtw89_tx_shape { 4124 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4125 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4126 }; 4127 4128 struct rtw89_rfe_parms { 4129 const struct rtw89_txpwr_table *byr_tbl; 4130 struct rtw89_txpwr_rule_2ghz rule_2ghz; 4131 struct rtw89_txpwr_rule_5ghz rule_5ghz; 4132 struct rtw89_txpwr_rule_6ghz rule_6ghz; 4133 struct rtw89_txpwr_rule_2ghz rule_da_2ghz; 4134 struct rtw89_txpwr_rule_5ghz rule_da_5ghz; 4135 struct rtw89_txpwr_rule_6ghz rule_da_6ghz; 4136 struct rtw89_tx_shape tx_shape; 4137 bool has_da; 4138 }; 4139 4140 struct rtw89_rfe_parms_conf { 4141 const struct rtw89_rfe_parms *rfe_parms; 4142 u8 rfe_type; 4143 }; 4144 4145 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 4146 4147 struct rtw89_txpwr_conf { 4148 u8 rfe_type; 4149 u8 ent_sz; 4150 u32 num_ents; 4151 const void *data; 4152 }; 4153 4154 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4155 const struct rtw89_txpwr_conf *conf) 4156 { 4157 u8 valid_size = min(size, conf->ent_sz); 4158 4159 memcpy(entry, cursor, valid_size); 4160 return true; 4161 } 4162 4163 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4164 4165 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4166 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4167 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4168 (cursor) += (conf)->ent_sz) \ 4169 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4170 4171 struct rtw89_txpwr_byrate_data { 4172 struct rtw89_txpwr_conf conf; 4173 struct rtw89_txpwr_table tbl; 4174 }; 4175 4176 struct rtw89_txpwr_lmt_2ghz_data { 4177 struct rtw89_txpwr_conf conf; 4178 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4179 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4180 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4181 }; 4182 4183 struct rtw89_txpwr_lmt_5ghz_data { 4184 struct rtw89_txpwr_conf conf; 4185 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4186 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4187 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4188 }; 4189 4190 struct rtw89_txpwr_lmt_6ghz_data { 4191 struct rtw89_txpwr_conf conf; 4192 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4193 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4194 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4195 [RTW89_6G_CH_NUM]; 4196 }; 4197 4198 struct rtw89_txpwr_lmt_ru_2ghz_data { 4199 struct rtw89_txpwr_conf conf; 4200 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4201 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4202 }; 4203 4204 struct rtw89_txpwr_lmt_ru_5ghz_data { 4205 struct rtw89_txpwr_conf conf; 4206 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4207 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4208 }; 4209 4210 struct rtw89_txpwr_lmt_ru_6ghz_data { 4211 struct rtw89_txpwr_conf conf; 4212 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4213 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4214 [RTW89_6G_CH_NUM]; 4215 }; 4216 4217 struct rtw89_tx_shape_lmt_data { 4218 struct rtw89_txpwr_conf conf; 4219 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4220 }; 4221 4222 struct rtw89_tx_shape_lmt_ru_data { 4223 struct rtw89_txpwr_conf conf; 4224 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4225 }; 4226 4227 struct rtw89_rfe_data { 4228 struct rtw89_txpwr_byrate_data byrate; 4229 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4230 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4231 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4232 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz; 4233 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz; 4234 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz; 4235 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4236 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4237 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4238 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz; 4239 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz; 4240 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz; 4241 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4242 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4243 struct rtw89_rfe_parms rfe_parms; 4244 }; 4245 4246 struct rtw89_page_regs { 4247 u32 hci_fc_ctrl; 4248 u32 ch_page_ctrl; 4249 u32 ach_page_ctrl; 4250 u32 ach_page_info; 4251 u32 pub_page_info3; 4252 u32 pub_page_ctrl1; 4253 u32 pub_page_ctrl2; 4254 u32 pub_page_info1; 4255 u32 pub_page_info2; 4256 u32 wp_page_ctrl1; 4257 u32 wp_page_ctrl2; 4258 u32 wp_page_info1; 4259 }; 4260 4261 struct rtw89_imr_info { 4262 u32 wdrls_imr_set; 4263 u32 wsec_imr_reg; 4264 u32 wsec_imr_set; 4265 u32 mpdu_tx_imr_set; 4266 u32 mpdu_rx_imr_set; 4267 u32 sta_sch_imr_set; 4268 u32 txpktctl_imr_b0_reg; 4269 u32 txpktctl_imr_b0_clr; 4270 u32 txpktctl_imr_b0_set; 4271 u32 txpktctl_imr_b1_reg; 4272 u32 txpktctl_imr_b1_clr; 4273 u32 txpktctl_imr_b1_set; 4274 u32 wde_imr_clr; 4275 u32 wde_imr_set; 4276 u32 ple_imr_clr; 4277 u32 ple_imr_set; 4278 u32 host_disp_imr_clr; 4279 u32 host_disp_imr_set; 4280 u32 cpu_disp_imr_clr; 4281 u32 cpu_disp_imr_set; 4282 u32 other_disp_imr_clr; 4283 u32 other_disp_imr_set; 4284 u32 bbrpt_com_err_imr_reg; 4285 u32 bbrpt_chinfo_err_imr_reg; 4286 u32 bbrpt_err_imr_set; 4287 u32 bbrpt_dfs_err_imr_reg; 4288 u32 ptcl_imr_clr; 4289 u32 ptcl_imr_set; 4290 u32 cdma_imr_0_reg; 4291 u32 cdma_imr_0_clr; 4292 u32 cdma_imr_0_set; 4293 u32 cdma_imr_1_reg; 4294 u32 cdma_imr_1_clr; 4295 u32 cdma_imr_1_set; 4296 u32 phy_intf_imr_reg; 4297 u32 phy_intf_imr_clr; 4298 u32 phy_intf_imr_set; 4299 u32 rmac_imr_reg; 4300 u32 rmac_imr_clr; 4301 u32 rmac_imr_set; 4302 u32 tmac_imr_reg; 4303 u32 tmac_imr_clr; 4304 u32 tmac_imr_set; 4305 }; 4306 4307 struct rtw89_imr_table { 4308 const struct rtw89_reg_imr *regs; 4309 u32 n_regs; 4310 }; 4311 4312 struct rtw89_xtal_info { 4313 u32 xcap_reg; 4314 u32 sc_xo_mask; 4315 u32 sc_xi_mask; 4316 }; 4317 4318 struct rtw89_rrsr_cfgs { 4319 struct rtw89_reg3_def ref_rate; 4320 struct rtw89_reg3_def rsc; 4321 }; 4322 4323 struct rtw89_rfkill_regs { 4324 struct rtw89_reg3_def pinmux; 4325 struct rtw89_reg3_def mode; 4326 }; 4327 4328 struct rtw89_dig_regs { 4329 u32 seg0_pd_reg; 4330 u32 pd_lower_bound_mask; 4331 u32 pd_spatial_reuse_en; 4332 u32 bmode_pd_reg; 4333 u32 bmode_cca_rssi_limit_en; 4334 u32 bmode_pd_lower_bound_reg; 4335 u32 bmode_rssi_nocca_low_th_mask; 4336 struct rtw89_reg_def p0_lna_init; 4337 struct rtw89_reg_def p1_lna_init; 4338 struct rtw89_reg_def p0_tia_init; 4339 struct rtw89_reg_def p1_tia_init; 4340 struct rtw89_reg_def p0_rxb_init; 4341 struct rtw89_reg_def p1_rxb_init; 4342 struct rtw89_reg_def p0_p20_pagcugc_en; 4343 struct rtw89_reg_def p0_s20_pagcugc_en; 4344 struct rtw89_reg_def p1_p20_pagcugc_en; 4345 struct rtw89_reg_def p1_s20_pagcugc_en; 4346 }; 4347 4348 struct rtw89_edcca_regs { 4349 u32 edcca_level; 4350 u32 edcca_mask; 4351 u32 edcca_p_mask; 4352 u32 ppdu_level; 4353 u32 ppdu_mask; 4354 struct rtw89_edcca_p_regs { 4355 u32 rpt_a; 4356 u32 rpt_b; 4357 u32 rpt_sel; 4358 u32 rpt_sel_mask; 4359 } p[RTW89_PHY_NUM]; 4360 u32 rpt_sel_be; 4361 u32 rpt_sel_be_mask; 4362 u32 tx_collision_t2r_st; 4363 u32 tx_collision_t2r_st_mask; 4364 }; 4365 4366 struct rtw89_phy_ul_tb_info { 4367 bool dyn_tb_tri_en; 4368 u8 def_if_bandedge; 4369 }; 4370 4371 struct rtw89_antdiv_stats { 4372 struct ewma_rssi cck_rssi_avg; 4373 struct ewma_rssi ofdm_rssi_avg; 4374 struct ewma_rssi non_legacy_rssi_avg; 4375 u16 pkt_cnt_cck; 4376 u16 pkt_cnt_ofdm; 4377 u16 pkt_cnt_non_legacy; 4378 u32 evm; 4379 }; 4380 4381 struct rtw89_antdiv_info { 4382 struct rtw89_antdiv_stats target_stats; 4383 struct rtw89_antdiv_stats main_stats; 4384 struct rtw89_antdiv_stats aux_stats; 4385 u8 training_count; 4386 u8 rssi_pre; 4387 bool get_stats; 4388 }; 4389 4390 enum rtw89_chanctx_state { 4391 RTW89_CHANCTX_STATE_MCC_START, 4392 RTW89_CHANCTX_STATE_MCC_STOP, 4393 }; 4394 4395 enum rtw89_chanctx_callbacks { 4396 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4397 RTW89_CHANCTX_CALLBACK_RFK, 4398 RTW89_CHANCTX_CALLBACK_TAS, 4399 4400 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4401 }; 4402 4403 struct rtw89_chanctx_listener { 4404 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4405 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4406 }; 4407 4408 #define RTW89_NHM_TH_NUM 11 4409 #define RTW89_NHM_RPT_NUM 12 4410 4411 struct rtw89_chip_info { 4412 enum rtw89_core_chip_id chip_id; 4413 enum rtw89_chip_gen chip_gen; 4414 const struct rtw89_chip_ops *ops; 4415 const struct rtw89_mac_gen_def *mac_def; 4416 const struct rtw89_phy_gen_def *phy_def; 4417 const char *fw_basename; 4418 u8 fw_format_max; 4419 bool try_ce_fw; 4420 u8 bbmcu_nr; 4421 u32 needed_fw_elms; 4422 const struct rtw89_fw_blacklist *fw_blacklist; 4423 u32 fifo_size; 4424 bool small_fifo_size; 4425 u32 dle_scc_rsvd_size; 4426 u16 max_amsdu_limit; 4427 bool dis_2g_40m_ul_ofdma; 4428 u32 rsvd_ple_ofst; 4429 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM]; 4430 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM]; 4431 u8 wde_qempty_acq_grpnum; 4432 u8 wde_qempty_mgq_grpsel; 4433 u32 rf_base_addr[2]; 4434 u8 thermal_th[2]; 4435 u8 support_macid_num; 4436 u8 support_link_num; 4437 u8 support_chanctx_num; 4438 u8 support_bands; 4439 u16 support_bandwidths; 4440 bool support_unii4; 4441 bool support_rnr; 4442 bool support_ant_gain; 4443 bool support_tas; 4444 bool support_sar_by_ant; 4445 bool support_noise; 4446 bool ul_tb_waveform_ctrl; 4447 bool ul_tb_pwr_diff; 4448 bool rx_freq_frome_ie; 4449 bool hw_sec_hdr; 4450 bool hw_mgmt_tx_encrypt; 4451 bool hw_tkip_crypto; 4452 bool hw_mlo_bmc_crypto; 4453 u8 rf_path_num; 4454 u8 tx_nss; 4455 u8 rx_nss; 4456 u8 acam_num; 4457 u8 bcam_num; 4458 u8 scam_num; 4459 u8 bacam_num; 4460 u8 bacam_dynamic_num; 4461 enum rtw89_bacam_ver bacam_ver; 4462 u8 addrcam_ver; 4463 u8 ppdu_max_usr; 4464 4465 u8 sec_ctrl_efuse_size; 4466 u32 physical_efuse_size; 4467 u32 logical_efuse_size; 4468 u32 limit_efuse_size; 4469 u32 dav_phy_efuse_size; 4470 u32 dav_log_efuse_size; 4471 u32 phycap_addr; 4472 u32 phycap_size; 4473 const struct rtw89_efuse_block_cfg *efuse_blocks; 4474 4475 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4476 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4477 const struct rtw89_phy_table *bb_table; 4478 const struct rtw89_phy_table *bb_gain_table; 4479 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4480 const struct rtw89_phy_table *nctl_table; 4481 const struct rtw89_rfk_tbl *nctl_post_table; 4482 const struct rtw89_phy_dig_gain_table *dig_table; 4483 const struct rtw89_dig_regs *dig_regs; 4484 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4485 4486 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4487 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4488 const struct rtw89_rfe_parms *dflt_parms; 4489 const struct rtw89_chanctx_listener *chanctx_listener; 4490 4491 u8 txpwr_factor_bb; 4492 u8 txpwr_factor_rf; 4493 u8 txpwr_factor_mac; 4494 4495 u32 para_ver; 4496 u32 wlcx_desired; 4497 u8 scbd; 4498 u8 mailbox; 4499 4500 u8 afh_guard_ch; 4501 const u8 *wl_rssi_thres; 4502 const u8 *bt_rssi_thres; 4503 u8 rssi_tol; 4504 4505 u8 mon_reg_num; 4506 const struct rtw89_btc_fbtc_mreg *mon_reg; 4507 u8 rf_para_ulink_num; 4508 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4509 u8 rf_para_dlink_num; 4510 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4511 u8 ps_mode_supported; 4512 u8 low_power_hci_modes; 4513 4514 u32 h2c_cctl_func_id; 4515 u32 hci_func_en_addr; 4516 u32 h2c_desc_size; 4517 u32 txwd_body_size; 4518 u32 txwd_info_size; 4519 u32 h2c_ctrl_reg; 4520 const u32 *h2c_regs; 4521 struct rtw89_reg_def h2c_counter_reg; 4522 u32 c2h_ctrl_reg; 4523 const u32 *c2h_regs; 4524 struct rtw89_reg_def c2h_counter_reg; 4525 const struct rtw89_page_regs *page_regs; 4526 const u32 *wow_reason_reg; 4527 bool cfo_src_fd; 4528 bool cfo_hw_comp; 4529 const struct rtw89_reg_def *dcfo_comp; 4530 u8 dcfo_comp_sft; 4531 const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM]; 4532 const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM]; 4533 const struct rtw89_imr_info *imr_info; 4534 const struct rtw89_imr_table *imr_dmac_table; 4535 const struct rtw89_imr_table *imr_cmac_table; 4536 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4537 struct rtw89_reg_def bss_clr_vld; 4538 u32 bss_clr_map_reg; 4539 const struct rtw89_rfkill_regs *rfkill_init; 4540 struct rtw89_reg_def rfkill_get; 4541 u32 dma_ch_mask; 4542 const struct rtw89_edcca_regs *edcca_regs; 4543 const struct wiphy_wowlan_support *wowlan_stub; 4544 const struct rtw89_xtal_info *xtal_info; 4545 }; 4546 4547 struct rtw89_chip_variant { 4548 bool no_mcs_12_13: 1; 4549 u32 fw_min_ver_code; 4550 }; 4551 4552 union rtw89_bus_info { 4553 const struct rtw89_pci_info *pci; 4554 const struct rtw89_usb_info *usb; 4555 }; 4556 4557 struct rtw89_driver_info { 4558 const struct rtw89_chip_info *chip; 4559 const struct rtw89_chip_variant *variant; 4560 const struct dmi_system_id *quirks; 4561 union rtw89_bus_info bus; 4562 }; 4563 4564 enum rtw89_hcifc_mode { 4565 RTW89_HCIFC_POH = 0, 4566 RTW89_HCIFC_STF = 1, 4567 RTW89_HCIFC_SDIO = 2, 4568 4569 /* keep last */ 4570 RTW89_HCIFC_MODE_INVALID, 4571 }; 4572 4573 struct rtw89_dle_info { 4574 const struct rtw89_rsvd_quota *rsvd_qt; 4575 enum rtw89_qta_mode qta_mode; 4576 u16 ple_pg_size; 4577 u16 ple_free_pg; 4578 u16 c0_rx_qta; 4579 u16 c1_rx_qta; 4580 }; 4581 4582 enum rtw89_host_rpr_mode { 4583 RTW89_RPR_MODE_POH = 0, 4584 RTW89_RPR_MODE_STF 4585 }; 4586 4587 #define RTW89_COMPLETION_BUF_SIZE 40 4588 #define RTW89_WAIT_COND_IDLE UINT_MAX 4589 4590 struct rtw89_completion_data { 4591 bool err; 4592 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4593 }; 4594 4595 struct rtw89_wait_response { 4596 struct rcu_head rcu_head; 4597 struct completion completion; 4598 struct rtw89_completion_data data; 4599 }; 4600 4601 struct rtw89_wait_info { 4602 atomic_t cond; 4603 struct rtw89_completion_data data; 4604 struct rtw89_wait_response __rcu *resp; 4605 }; 4606 4607 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4608 4609 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4610 { 4611 rcu_assign_pointer(wait->resp, NULL); 4612 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4613 } 4614 4615 struct rtw89_mac_info { 4616 struct rtw89_dle_info dle_info; 4617 struct rtw89_hfc_param hfc_param; 4618 enum rtw89_qta_mode qta_mode; 4619 u8 rpwm_seq_num; 4620 u8 cpwm_seq_num; 4621 4622 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4623 struct rtw89_wait_info fw_ofld_wait; 4624 /* see RTW89_PS_WAIT_COND series for wait condition */ 4625 struct rtw89_wait_info ps_wait; 4626 }; 4627 4628 enum rtw89_fwdl_check_type { 4629 RTW89_FWDL_CHECK_FREERTOS_DONE, 4630 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4631 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4632 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4633 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4634 }; 4635 4636 enum rtw89_fw_type { 4637 RTW89_FW_NORMAL = 1, 4638 RTW89_FW_WOWLAN = 3, 4639 RTW89_FW_NORMAL_CE = 5, 4640 RTW89_FW_BBMCU0 = 64, 4641 RTW89_FW_BBMCU1 = 65, 4642 RTW89_FW_LOGFMT = 255, 4643 }; 4644 4645 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \ 4646 RTW89_FW_FEATURE_##_grp##_MIN, \ 4647 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \ 4648 _features \ 4649 __RTW89_FW_FEATURE_##_grp##_E, \ 4650 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1 4651 4652 enum rtw89_fw_feature { 4653 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4654 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4655 RTW89_FW_FEATURE_TX_WAKE, 4656 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER, 4657 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0, 4658 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1, 4659 ), 4660 RTW89_FW_FEATURE_NO_PACKET_DROP, 4661 RTW89_FW_FEATURE_NO_DEEP_PS, 4662 RTW89_FW_FEATURE_NO_LPS_PG, 4663 RTW89_FW_FEATURE_BEACON_FILTER, 4664 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4665 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4666 RTW89_FW_FEATURE_WOW_REASON_V1, 4667 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4668 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4669 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4670 RTW89_FW_FEATURE_RFK_IQK_V0, 4671 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4672 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4673 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4674 RTW89_FW_FEATURE_LPS_CH_INFO, 4675 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4676 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 4677 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1, 4678 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP, 4679 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0, 4680 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG, 4681 RTW89_FW_FEATURE_BEACON_TRACKING, 4682 RTW89_FW_FEATURE_ADDR_CAM_V0, 4683 }; 4684 4685 struct rtw89_fw_suit { 4686 enum rtw89_fw_type type; 4687 const u8 *data; 4688 u32 size; 4689 u8 major_ver; 4690 u8 minor_ver; 4691 u8 sub_ver; 4692 u8 sub_idex; 4693 u16 build_year; 4694 u16 build_mon; 4695 u16 build_date; 4696 u16 build_hour; 4697 u16 build_min; 4698 u8 cmd_ver; 4699 u8 hdr_ver; 4700 u32 commitid; 4701 }; 4702 4703 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4704 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4705 #define RTW89_FW_SUIT_VER_CODE(s) \ 4706 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4707 4708 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4709 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4710 (mfw_hdr)->ver.minor, \ 4711 (mfw_hdr)->ver.sub, \ 4712 (mfw_hdr)->ver.idx) 4713 4714 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4715 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4716 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4717 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4718 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4719 4720 struct rtw89_fw_req_info { 4721 const struct firmware *firmware; 4722 struct completion completion; 4723 }; 4724 4725 struct rtw89_fw_log { 4726 struct rtw89_fw_suit suit; 4727 bool enable; 4728 u32 last_fmt_id; 4729 u32 fmt_count; 4730 const __le32 *fmt_ids; 4731 const char *(*fmts)[]; 4732 }; 4733 4734 struct rtw89_fw_elm_info { 4735 struct rtw89_phy_table *bb_tbl; 4736 struct rtw89_phy_table *bb_gain; 4737 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4738 struct rtw89_phy_table *rf_nctl; 4739 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4740 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4741 const struct rtw89_regd_data *regd; 4742 const struct rtw89_fw_element_hdr *afe; 4743 const struct rtw89_fw_element_hdr *diag_mac; 4744 }; 4745 4746 enum rtw89_fw_mss_dev_type { 4747 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4748 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4749 }; 4750 4751 struct rtw89_fw_secure { 4752 bool secure_boot: 1; 4753 bool can_mss_v1: 1; 4754 bool can_mss_v0: 1; 4755 u32 sb_sel_mgn; 4756 u8 mss_dev_type; 4757 u8 mss_cust_idx; 4758 u8 mss_key_num; 4759 u8 mss_idx; /* v0 */ 4760 }; 4761 4762 struct rtw89_fw_info { 4763 struct rtw89_fw_req_info req; 4764 int fw_format; 4765 u8 h2c_seq; 4766 u8 rec_seq; 4767 u8 h2c_counter; 4768 u8 c2h_counter; 4769 struct rtw89_fw_suit normal; 4770 struct rtw89_fw_suit wowlan; 4771 struct rtw89_fw_suit bbmcu0; 4772 struct rtw89_fw_suit bbmcu1; 4773 struct rtw89_fw_log log; 4774 u32 feature_map; 4775 struct rtw89_fw_elm_info elm_info; 4776 struct rtw89_fw_secure sec; 4777 }; 4778 4779 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4780 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4781 4782 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \ 4783 (!!((_fw)->feature_map & GENMASK(RTW89_FW_FEATURE_ ## _grp ## _MAX, \ 4784 RTW89_FW_FEATURE_ ## _grp ## _MIN))) 4785 4786 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4787 ((_fw)->feature_map |= BIT(_fw_feature)) 4788 4789 struct rtw89_cam_info { 4790 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4791 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4792 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4793 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4794 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4795 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4796 }; 4797 4798 enum rtw89_sar_sources { 4799 RTW89_SAR_SOURCE_NONE, 4800 RTW89_SAR_SOURCE_COMMON, 4801 RTW89_SAR_SOURCE_ACPI, 4802 4803 RTW89_SAR_SOURCE_NR, 4804 }; 4805 4806 enum rtw89_sar_subband { 4807 RTW89_SAR_2GHZ_SUBBAND, 4808 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4809 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4810 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4811 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4812 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4813 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4814 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4815 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4816 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4817 4818 RTW89_SAR_SUBBAND_NR, 4819 }; 4820 4821 struct rtw89_sar_cfg_common { 4822 bool set[RTW89_SAR_SUBBAND_NR]; 4823 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4824 }; 4825 4826 enum rtw89_acpi_sar_subband { 4827 RTW89_ACPI_SAR_2GHZ_SUBBAND, 4828 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */ 4829 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */ 4830 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4831 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4832 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4833 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4834 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4835 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4836 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4837 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4838 4839 NUM_OF_RTW89_ACPI_SAR_SUBBAND, 4840 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1, 4841 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1, 4842 }; 4843 4844 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */ 4845 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX 4846 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN 4847 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6 4848 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1) 4849 4850 struct rtw89_sar_entry_from_acpi { 4851 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4852 }; 4853 4854 struct rtw89_sar_table_from_acpi { 4855 /* If this table is active, must fill all fields according to either 4856 * configuration in BIOS or some default values for SAR to work well. 4857 */ 4858 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM]; 4859 }; 4860 4861 struct rtw89_sar_indicator_from_acpi { 4862 bool enable_sync; 4863 unsigned int fields; 4864 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath); 4865 4866 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path. 4867 * Not design with pointers since addresses will be invalid after 4868 * sync content with local container instance. 4869 */ 4870 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4871 }; 4872 4873 struct rtw89_sar_cfg_acpi { 4874 u8 downgrade_2tx; 4875 unsigned int valid_num; 4876 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL]; 4877 struct rtw89_sar_indicator_from_acpi indicator; 4878 }; 4879 4880 struct rtw89_sar_info { 4881 /* used to decide how to access SAR cfg union */ 4882 enum rtw89_sar_sources src; 4883 4884 /* reserved for different knids of SAR cfg struct. 4885 * supposed that a single cfg struct cannot handle various SAR sources. 4886 */ 4887 union { 4888 struct rtw89_sar_cfg_common cfg_common; 4889 struct rtw89_sar_cfg_acpi cfg_acpi; 4890 }; 4891 }; 4892 4893 enum rtw89_ant_gain_subband { 4894 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4895 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4896 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4897 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4898 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4899 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4900 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4901 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4902 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4903 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4904 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4905 4906 RTW89_ANT_GAIN_SUBBAND_NR, 4907 }; 4908 4909 enum rtw89_ant_gain_domain_type { 4910 RTW89_ANT_GAIN_ETSI = 0, 4911 4912 RTW89_ANT_GAIN_DOMAIN_NUM, 4913 }; 4914 4915 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4916 struct rtw89_ant_gain_info { 4917 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4918 u32 regd_enabled; 4919 bool block_country; 4920 }; 4921 4922 struct rtw89_6ghz_span { 4923 enum rtw89_sar_subband sar_subband_low; 4924 enum rtw89_sar_subband sar_subband_high; 4925 enum rtw89_acpi_sar_subband acpi_sar_subband_low; 4926 enum rtw89_acpi_sar_subband acpi_sar_subband_high; 4927 enum rtw89_ant_gain_subband ant_gain_subband_low; 4928 enum rtw89_ant_gain_subband ant_gain_subband_high; 4929 }; 4930 4931 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4932 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high) 4933 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4934 4935 enum rtw89_tas_state { 4936 RTW89_TAS_STATE_DPR_OFF, 4937 RTW89_TAS_STATE_DPR_ON, 4938 RTW89_TAS_STATE_STATIC_SAR, 4939 }; 4940 4941 #define RTW89_TAS_TX_RATIO_WINDOW 6 4942 #define RTW89_TAS_TXPWR_WINDOW 180 4943 struct rtw89_tas_info { 4944 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 4945 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 4946 u8 enabled_countries; 4947 u8 txpwr_head_idx; 4948 u8 txpwr_tail_idx; 4949 u8 tx_ratio_idx; 4950 u16 total_tx_ratio; 4951 u64 total_txpwr; 4952 u64 instant_txpwr; 4953 u32 window_size; 4954 s8 dpr_on_threshold; 4955 s8 dpr_off_threshold; 4956 enum rtw89_tas_state backup_state; 4957 enum rtw89_tas_state state; 4958 bool keep_history; 4959 bool block_regd; 4960 bool enable; 4961 bool pause; 4962 }; 4963 4964 struct rtw89_chanctx_cfg { 4965 enum rtw89_chanctx_idx idx; 4966 int ref_count; 4967 }; 4968 4969 enum rtw89_chanctx_changes { 4970 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4971 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4972 RTW89_CHANCTX_P2P_PS_CHANGE, 4973 RTW89_CHANCTX_BT_SLOT_CHANGE, 4974 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4975 4976 NUM_OF_RTW89_CHANCTX_CHANGES, 4977 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4978 }; 4979 4980 enum rtw89_entity_mode { 4981 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4982 RTW89_ENTITY_MODE_MCC_PREPARE, 4983 RTW89_ENTITY_MODE_MCC, 4984 4985 NUM_OF_RTW89_ENTITY_MODE, 4986 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4987 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4988 }; 4989 4990 #define RTW89_MAX_INTERFACE_NUM 2 4991 4992 /* only valid when running with chanctx_ops */ 4993 struct rtw89_entity_mgnt { 4994 struct list_head active_list; 4995 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4996 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4997 [__RTW89_MLD_MAX_LINK_NUM]; 4998 }; 4999 5000 struct rtw89_chanctx { 5001 struct cfg80211_chan_def chandef; 5002 struct rtw89_chan chan; 5003 struct rtw89_chan_rcd rcd; 5004 5005 /* only assigned when running with chanctx_ops */ 5006 struct rtw89_chanctx_cfg *cfg; 5007 }; 5008 5009 struct rtw89_edcca_bak { 5010 u8 a; 5011 u8 p; 5012 u8 ppdu; 5013 u8 th_old; 5014 }; 5015 5016 enum rtw89_dm_type { 5017 RTW89_DM_DYNAMIC_EDCCA, 5018 RTW89_DM_THERMAL_PROTECT, 5019 RTW89_DM_TAS, 5020 RTW89_DM_MLO, 5021 }; 5022 5023 #define RTW89_THERMAL_PROT_LV_MAX 5 5024 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 5025 5026 struct rtw89_hal { 5027 u32 rx_fltr; 5028 u8 cv; 5029 u8 acv; 5030 u32 antenna_tx; 5031 u32 antenna_rx; 5032 u8 tx_nss; 5033 u8 rx_nss; 5034 bool tx_path_diversity; 5035 bool ant_diversity; 5036 bool ant_diversity_fixed; 5037 bool support_cckpd; 5038 bool support_igi; 5039 bool no_mcs_12_13; 5040 5041 atomic_t roc_chanctx_idx; 5042 u8 roc_link_index; 5043 5044 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 5045 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 5046 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 5047 struct cfg80211_chan_def roc_chandef; 5048 5049 bool entity_active[RTW89_PHY_NUM]; 5050 bool entity_pause; 5051 enum rtw89_entity_mode entity_mode; 5052 struct rtw89_entity_mgnt entity_mgnt; 5053 5054 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 5055 5056 u8 thermal_prot_th; 5057 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 5058 }; 5059 5060 #define RTW89_MAX_MAC_ID_NUM 128 5061 #define RTW89_MAX_PKT_OFLD_NUM 255 5062 5063 enum rtw89_flags { 5064 RTW89_FLAG_POWERON, 5065 RTW89_FLAG_DMAC_FUNC, 5066 RTW89_FLAG_CMAC0_FUNC, 5067 RTW89_FLAG_CMAC1_FUNC, 5068 RTW89_FLAG_FW_RDY, 5069 RTW89_FLAG_RUNNING, 5070 RTW89_FLAG_PROBE_DONE, 5071 RTW89_FLAG_BFEE_MON, 5072 RTW89_FLAG_BFEE_EN, 5073 RTW89_FLAG_BFEE_TIMER_KEEP, 5074 RTW89_FLAG_NAPI_RUNNING, 5075 RTW89_FLAG_LEISURE_PS, 5076 RTW89_FLAG_LOW_POWER_MODE, 5077 RTW89_FLAG_INACTIVE_PS, 5078 RTW89_FLAG_CRASH_SIMULATING, 5079 RTW89_FLAG_SER_HANDLING, 5080 RTW89_FLAG_WOWLAN, 5081 RTW89_FLAG_FORBIDDEN_TRACK_WORK, 5082 RTW89_FLAG_CHANGING_INTERFACE, 5083 RTW89_FLAG_HW_RFKILL_STATE, 5084 RTW89_FLAG_UNPLUGGED, 5085 5086 NUM_OF_RTW89_FLAGS, 5087 }; 5088 5089 enum rtw89_quirks { 5090 RTW89_QUIRK_PCI_BER, 5091 RTW89_QUIRK_THERMAL_PROT_120C, 5092 RTW89_QUIRK_THERMAL_PROT_110C, 5093 5094 NUM_OF_RTW89_QUIRKS, 5095 }; 5096 5097 enum rtw89_custid { 5098 RTW89_CUSTID_NONE, 5099 RTW89_CUSTID_ACER, 5100 RTW89_CUSTID_AMD, 5101 RTW89_CUSTID_ASUS, 5102 RTW89_CUSTID_DELL, 5103 RTW89_CUSTID_HP, 5104 RTW89_CUSTID_LENOVO, 5105 }; 5106 5107 enum rtw89_pkt_drop_sel { 5108 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5109 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5110 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5111 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5112 RTW89_PKT_DROP_SEL_MACID_ALL, 5113 RTW89_PKT_DROP_SEL_MG0_ONCE, 5114 RTW89_PKT_DROP_SEL_HIQ_ONCE, 5115 RTW89_PKT_DROP_SEL_HIQ_PORT, 5116 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 5117 RTW89_PKT_DROP_SEL_BAND, 5118 RTW89_PKT_DROP_SEL_BAND_ONCE, 5119 RTW89_PKT_DROP_SEL_REL_MACID, 5120 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 5121 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 5122 }; 5123 5124 struct rtw89_pkt_drop_params { 5125 enum rtw89_pkt_drop_sel sel; 5126 enum rtw89_mac_idx mac_band; 5127 u8 macid; 5128 u8 port; 5129 u8 mbssid; 5130 bool tf_trs; 5131 u32 macid_band_sel[4]; 5132 }; 5133 5134 struct rtw89_pkt_stat { 5135 u16 beacon_nr; 5136 u8 beacon_rate; 5137 u32 beacon_len; 5138 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 5139 }; 5140 5141 #define RTW89_BCN_TRACK_STAT_NR 32 5142 #define RTW89_BCN_TRACK_SCALE_FACTOR 10 5143 #define RTW89_BCN_TRACK_MAX_BIN_NUM 6 5144 #define RTW89_BCN_TRACK_BIN_WIDTH 5 5145 #define RTW89_BCN_TRACK_TARGET_BCN 80 5146 5147 struct rtw89_beacon_dist { 5148 u16 min; 5149 u16 max; 5150 u16 outlier_count; 5151 u16 lower_bound; 5152 u16 upper_bound; 5153 u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM]; 5154 }; 5155 5156 struct rtw89_beacon_stat { 5157 u8 num; 5158 u8 wp; 5159 u16 tbtt_tu_min; 5160 u16 tbtt_tu_max; 5161 u16 drift[RTW89_BCN_TRACK_STAT_NR]; 5162 u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR]; 5163 u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR]; 5164 struct rtw89_beacon_dist bcn_dist; 5165 }; 5166 5167 DECLARE_EWMA(thermal, 4, 4); 5168 5169 struct rtw89_phy_stat { 5170 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 5171 u8 last_thermal_max; 5172 struct ewma_rssi bcn_rssi; 5173 struct rtw89_pkt_stat cur_pkt_stat; 5174 struct rtw89_pkt_stat last_pkt_stat; 5175 struct rtw89_beacon_stat bcn_stat; 5176 }; 5177 5178 enum rtw89_rfk_report_state { 5179 RTW89_RFK_STATE_START = 0x0, 5180 RTW89_RFK_STATE_OK = 0x1, 5181 RTW89_RFK_STATE_FAIL = 0x2, 5182 RTW89_RFK_STATE_TIMEOUT = 0x3, 5183 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 5184 }; 5185 5186 struct rtw89_rfk_wait_info { 5187 struct completion completion; 5188 ktime_t start_time; 5189 enum rtw89_rfk_report_state state; 5190 u8 version; 5191 }; 5192 5193 #define RTW89_DACK_PATH_NR 2 5194 #define RTW89_DACK_IDX_NR 2 5195 #define RTW89_DACK_MSBK_NR 16 5196 struct rtw89_dack_info { 5197 bool dack_done; 5198 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 5199 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5200 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5201 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5202 u32 dack_cnt; 5203 bool addck_timeout[RTW89_DACK_PATH_NR]; 5204 bool dadck_timeout[RTW89_DACK_PATH_NR]; 5205 bool msbk_timeout[RTW89_DACK_PATH_NR]; 5206 }; 5207 5208 enum rtw89_rfk_chs_nrs { 5209 __RTW89_RFK_CHS_NR_V0 = 2, 5210 __RTW89_RFK_CHS_NR_V1 = 3, 5211 5212 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 5213 }; 5214 5215 struct rtw89_rfk_mcc_info_data { 5216 u8 ch[RTW89_RFK_CHS_NR]; 5217 u8 band[RTW89_RFK_CHS_NR]; 5218 u8 bw[RTW89_RFK_CHS_NR]; 5219 u8 table_idx; 5220 }; 5221 5222 struct rtw89_rfk_mcc_info { 5223 struct rtw89_rfk_mcc_info_data data[2]; 5224 }; 5225 5226 #define RTW89_IQK_CHS_NR 2 5227 #define RTW89_IQK_PATH_NR 4 5228 5229 struct rtw89_lck_info { 5230 u8 thermal[RF_PATH_MAX]; 5231 }; 5232 5233 struct rtw89_rx_dck_info { 5234 u8 thermal[RF_PATH_MAX]; 5235 }; 5236 5237 struct rtw89_iqk_info { 5238 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5239 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5240 bool lok_fail[RTW89_IQK_PATH_NR]; 5241 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5242 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5243 u32 iqk_fail_cnt; 5244 bool is_iqk_init; 5245 u32 iqk_channel[RTW89_IQK_CHS_NR]; 5246 u8 iqk_band[RTW89_IQK_PATH_NR]; 5247 u8 iqk_ch[RTW89_IQK_PATH_NR]; 5248 u8 iqk_bw[RTW89_IQK_PATH_NR]; 5249 u8 iqk_times; 5250 u8 version; 5251 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 5252 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 5253 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 5254 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 5255 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 5256 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 5257 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 5258 bool is_nbiqk; 5259 bool iqk_fft_en; 5260 bool iqk_xym_en; 5261 bool iqk_sram_en; 5262 bool iqk_cfir_en; 5263 u32 syn1to2; 5264 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5265 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 5266 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5267 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5268 }; 5269 5270 #define RTW89_DPK_RF_PATH 2 5271 #define RTW89_DPK_AVG_THERMAL_NUM 8 5272 #define RTW89_DPK_BKUP_NUM 2 5273 struct rtw89_dpk_bkup_para { 5274 enum rtw89_band band; 5275 enum rtw89_bandwidth bw; 5276 u8 ch; 5277 u8 path_ok; 5278 u8 mdpd_en; 5279 u8 txagc_dpk; 5280 u8 ther_dpk; 5281 u8 gs; 5282 u16 pwsf; 5283 }; 5284 5285 struct rtw89_dpk_info { 5286 bool is_dpk_enable; 5287 bool is_dpk_reload_en; 5288 u8 dpk_gs[RTW89_PHY_NUM]; 5289 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5290 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5291 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5292 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5293 u8 cur_idx[RTW89_DPK_RF_PATH]; 5294 u8 cur_k_set; 5295 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5296 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 5297 u32 dpk_order[RTW89_DPK_RF_PATH]; 5298 }; 5299 5300 struct rtw89_fem_info { 5301 bool elna_2g; 5302 bool elna_5g; 5303 bool epa_2g; 5304 bool epa_5g; 5305 bool epa_6g; 5306 }; 5307 5308 struct rtw89_phy_ch_info { 5309 u8 rssi_min; 5310 u16 rssi_min_macid; 5311 u8 pre_rssi_min; 5312 u8 rssi_max; 5313 u16 rssi_max_macid; 5314 u8 rxsc_160; 5315 u8 rxsc_80; 5316 u8 rxsc_40; 5317 u8 rxsc_20; 5318 u8 rxsc_l; 5319 u8 is_noisy; 5320 }; 5321 5322 struct rtw89_agc_gaincode_set { 5323 u8 lna_idx; 5324 u8 tia_idx; 5325 u8 rxb_idx; 5326 }; 5327 5328 #define IGI_RSSI_TH_NUM 5 5329 #define FA_TH_NUM 4 5330 #define TIA_LNA_OP1DB_NUM 8 5331 #define LNA_GAIN_NUM 7 5332 #define TIA_GAIN_NUM 2 5333 struct rtw89_dig_info { 5334 struct rtw89_agc_gaincode_set cur_gaincode; 5335 bool force_gaincode_idx_en; 5336 struct rtw89_agc_gaincode_set force_gaincode; 5337 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5338 u16 fa_th[FA_TH_NUM]; 5339 u8 igi_rssi; 5340 u8 igi_fa_rssi; 5341 u8 fa_rssi_ofst; 5342 u8 dyn_igi_max; 5343 u8 dyn_igi_min; 5344 bool dyn_pd_th_en; 5345 u8 dyn_pd_th_max; 5346 u8 pd_low_th_ofst; 5347 u8 ib_pbk; 5348 s8 ib_pkpwr; 5349 s8 lna_gain_a[LNA_GAIN_NUM]; 5350 s8 lna_gain_g[LNA_GAIN_NUM]; 5351 s8 *lna_gain; 5352 s8 tia_gain_a[TIA_GAIN_NUM]; 5353 s8 tia_gain_g[TIA_GAIN_NUM]; 5354 s8 *tia_gain; 5355 u32 bak_dig; 5356 bool is_linked_pre; 5357 bool bypass_dig; 5358 bool pause_dig; 5359 }; 5360 5361 enum rtw89_multi_cfo_mode { 5362 RTW89_PKT_BASED_AVG_MODE = 0, 5363 RTW89_ENTRY_BASED_AVG_MODE = 1, 5364 RTW89_TP_BASED_AVG_MODE = 2, 5365 }; 5366 5367 enum rtw89_phy_cfo_status { 5368 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5369 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5370 RTW89_PHY_DCFO_STATE_HOLD = 2, 5371 RTW89_PHY_DCFO_STATE_MAX 5372 }; 5373 5374 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5375 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5376 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5377 }; 5378 5379 struct rtw89_cfo_tracking_info { 5380 u16 cfo_timer_ms; 5381 bool cfo_trig_by_timer_en; 5382 enum rtw89_phy_cfo_status phy_cfo_status; 5383 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5384 u8 phy_cfo_trk_cnt; 5385 bool is_adjust; 5386 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5387 bool apply_compensation; 5388 u8 crystal_cap; 5389 u8 crystal_cap_default; 5390 u8 def_x_cap; 5391 s8 x_cap_ofst; 5392 u32 sta_cfo_tolerance; 5393 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5394 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5395 s32 cfo_avg_pre; 5396 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5397 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5398 s32 dcfo_avg; 5399 s32 dcfo_avg_pre; 5400 u32 packet_count; 5401 u32 packet_count_pre; 5402 s32 residual_cfo_acc; 5403 u8 phy_cfotrk_state; 5404 u8 phy_cfotrk_cnt; 5405 bool divergence_lock_en; 5406 u8 x_cap_lb; 5407 u8 x_cap_ub; 5408 u8 lock_cnt; 5409 }; 5410 5411 enum rtw89_tssi_mode { 5412 RTW89_TSSI_NORMAL = 0, 5413 RTW89_TSSI_SCAN = 1, 5414 }; 5415 5416 enum rtw89_tssi_alimk_band { 5417 TSSI_ALIMK_2G = 0, 5418 TSSI_ALIMK_5GL, 5419 TSSI_ALIMK_5GM, 5420 TSSI_ALIMK_5GH, 5421 TSSI_ALIMK_MAX 5422 }; 5423 5424 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5425 #define TSSI_TRIM_CH_GROUP_NUM 8 5426 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5427 5428 #define TSSI_CCK_CH_GROUP_NUM 6 5429 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5430 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5431 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5432 #define TSSI_MCS_CH_GROUP_NUM \ 5433 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5434 #define TSSI_MAX_CH_NUM 67 5435 #define TSSI_ALIMK_VALUE_NUM 8 5436 5437 struct rtw89_tssi_info { 5438 u8 thermal[RF_PATH_MAX]; 5439 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5440 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5441 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5442 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5443 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5444 s8 extra_ofst[RF_PATH_MAX]; 5445 bool tssi_tracking_check[RF_PATH_MAX]; 5446 u8 default_txagc_offset[RF_PATH_MAX]; 5447 u32 base_thermal[RF_PATH_MAX]; 5448 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5449 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5450 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5451 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5452 u64 tssi_alimk_time; 5453 }; 5454 5455 struct rtw89_power_trim_info { 5456 bool pg_thermal_trim; 5457 bool pg_pa_bias_trim; 5458 u8 thermal_trim[RF_PATH_MAX]; 5459 u8 pa_bias_trim[RF_PATH_MAX]; 5460 u8 pad_bias_trim[RF_PATH_MAX]; 5461 }; 5462 5463 enum rtw89_regd_func { 5464 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 5465 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 5466 5467 NUM_OF_RTW89_REGD_FUNC, 5468 }; 5469 5470 struct rtw89_regd { 5471 char alpha2[3]; 5472 u8 txpwr_regd[RTW89_BAND_NUM]; 5473 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 5474 }; 5475 5476 struct rtw89_regd_data { 5477 unsigned int nr; 5478 struct rtw89_regd map[] __counted_by(nr); 5479 }; 5480 5481 struct rtw89_regd_ctrl { 5482 unsigned int nr; 5483 const struct rtw89_regd *map; 5484 }; 5485 5486 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5487 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5488 #define RTW89_5GHZ_UNII4_START_INDEX 25 5489 5490 struct rtw89_regulatory_info { 5491 struct rtw89_regd_ctrl ctrl; 5492 const struct rtw89_regd *regd; 5493 bool programmed; 5494 5495 enum rtw89_reg_6ghz_power reg_6ghz_power; 5496 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5497 bool txpwr_uk_follow_etsi; 5498 5499 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5500 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5501 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5502 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM); 5503 }; 5504 5505 enum rtw89_ifs_clm_application { 5506 RTW89_IFS_CLM_INIT = 0, 5507 RTW89_IFS_CLM_BACKGROUND = 1, 5508 RTW89_IFS_CLM_ACS = 2, 5509 RTW89_IFS_CLM_DIG = 3, 5510 RTW89_IFS_CLM_TDMA_DIG = 4, 5511 RTW89_IFS_CLM_DBG = 5, 5512 RTW89_IFS_CLM_DBG_MANUAL = 6 5513 }; 5514 5515 enum rtw89_env_racing_lv { 5516 RTW89_RAC_RELEASE = 0, 5517 RTW89_RAC_LV_1 = 1, 5518 RTW89_RAC_LV_2 = 2, 5519 RTW89_RAC_LV_3 = 3, 5520 RTW89_RAC_LV_4 = 4, 5521 RTW89_RAC_MAX_NUM = 5 5522 }; 5523 5524 struct rtw89_ccx_para_info { 5525 enum rtw89_env_racing_lv rac_lv; 5526 u16 mntr_time; 5527 bool nhm_incld_cca; 5528 u8 nhm_manual_th_ofst; 5529 u8 nhm_manual_th0; 5530 enum rtw89_ifs_clm_application ifs_clm_app; 5531 u32 ifs_clm_manual_th_times; 5532 u32 ifs_clm_manual_th0; 5533 u8 fahm_manual_th_ofst; 5534 u8 fahm_manual_th0; 5535 u8 fahm_numer_opt; 5536 u8 fahm_denom_opt; 5537 }; 5538 5539 enum rtw89_ccx_edcca_opt_sc_idx { 5540 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5541 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5542 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5543 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5544 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5545 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5546 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5547 RTW89_CCX_EDCCA_SEG1_S3 = 7 5548 }; 5549 5550 enum rtw89_ccx_edcca_opt_bw_idx { 5551 RTW89_CCX_EDCCA_BW20_0 = 0, 5552 RTW89_CCX_EDCCA_BW20_1 = 1, 5553 RTW89_CCX_EDCCA_BW20_2 = 2, 5554 RTW89_CCX_EDCCA_BW20_3 = 3, 5555 RTW89_CCX_EDCCA_BW20_4 = 4, 5556 RTW89_CCX_EDCCA_BW20_5 = 5, 5557 RTW89_CCX_EDCCA_BW20_6 = 6, 5558 RTW89_CCX_EDCCA_BW20_7 = 7 5559 }; 5560 5561 struct rtw89_nhm_report { 5562 struct list_head list; 5563 struct ieee80211_channel *channel; 5564 u8 noise; 5565 }; 5566 5567 #define RTW89_FAHM_TH_NUM 11 5568 #define RTW89_FAHM_RPT_NUM 12 5569 #define RTW89_IFS_CLM_NUM 4 5570 struct rtw89_env_monitor_info { 5571 u8 ccx_watchdog_result; 5572 bool ccx_ongoing; 5573 u8 ccx_rac_lv; 5574 bool ccx_manual_ctrl; 5575 u16 ifs_clm_mntr_time; 5576 enum rtw89_ifs_clm_application ifs_clm_app; 5577 u16 ccx_period; 5578 u8 ccx_unit_idx; 5579 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5580 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5581 u16 ifs_clm_tx; 5582 u16 ifs_clm_edcca_excl_cca; 5583 u16 ifs_clm_ofdmfa; 5584 u16 ifs_clm_ofdmcca_excl_fa; 5585 u16 ifs_clm_cckfa; 5586 u16 ifs_clm_cckcca_excl_fa; 5587 u16 ifs_clm_total_ifs; 5588 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5589 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5590 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5591 u8 ifs_clm_tx_ratio; 5592 u8 ifs_clm_edcca_excl_cca_ratio; 5593 u8 ifs_clm_cck_fa_ratio; 5594 u8 ifs_clm_ofdm_fa_ratio; 5595 u8 ifs_clm_cck_cca_excl_fa_ratio; 5596 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5597 u16 ifs_clm_cck_fa_permil; 5598 u16 ifs_clm_ofdm_fa_permil; 5599 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5600 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5601 bool nhm_include_cca; 5602 u32 nhm_sum; 5603 u32 nhm_mntr_time; 5604 u16 nhm_result[RTW89_NHM_RPT_NUM]; 5605 u8 nhm_th[RTW89_NHM_RPT_NUM]; 5606 struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM]; 5607 struct list_head nhm_rpt_list; 5608 }; 5609 5610 enum rtw89_ser_rcvy_step { 5611 RTW89_SER_DRV_STOP_TX, 5612 RTW89_SER_DRV_STOP_RX, 5613 RTW89_SER_DRV_STOP_RUN, 5614 RTW89_SER_HAL_STOP_DMA, 5615 RTW89_SER_SUPPRESS_LOG, 5616 RTW89_NUM_OF_SER_FLAGS 5617 }; 5618 5619 struct rtw89_ser { 5620 u8 state; 5621 u8 alarm_event; 5622 bool prehandle_l1; 5623 5624 struct work_struct ser_hdl_work; 5625 struct delayed_work ser_alarm_work; 5626 const struct state_ent *st_tbl; 5627 const struct event_ent *ev_tbl; 5628 struct list_head msg_q; 5629 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5630 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5631 }; 5632 5633 enum rtw89_mac_ax_ps_mode { 5634 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5635 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5636 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5637 RTW89_MAC_AX_PS_MODE_MAX = 3, 5638 }; 5639 5640 enum rtw89_last_rpwm_mode { 5641 RTW89_LAST_RPWM_PS = 0x0, 5642 RTW89_LAST_RPWM_ACTIVE = 0x6, 5643 }; 5644 5645 struct rtw89_lps_parm { 5646 u8 macid; 5647 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5648 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5649 }; 5650 5651 struct rtw89_ppdu_sts_info { 5652 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 5653 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 5654 }; 5655 5656 struct rtw89_early_h2c { 5657 struct list_head list; 5658 u8 *h2c; 5659 u16 h2c_len; 5660 }; 5661 5662 struct rtw89_hw_scan_extra_op { 5663 bool set; 5664 u8 macid; 5665 u8 port; 5666 struct rtw89_chan chan; 5667 struct rtw89_vif_link *rtwvif_link; 5668 }; 5669 5670 struct rtw89_hw_scan_info { 5671 struct rtw89_vif_link *scanning_vif; 5672 struct list_head pkt_list[NUM_NL80211_BANDS]; 5673 struct list_head chan_list; 5674 struct rtw89_chan op_chan; 5675 struct rtw89_hw_scan_extra_op extra_op; 5676 bool connected; 5677 bool abort; 5678 u16 delay; /* in unit of ms */ 5679 u8 seq: 2; 5680 }; 5681 5682 enum rtw89_phy_bb_gain_band { 5683 RTW89_BB_GAIN_BAND_2G = 0, 5684 RTW89_BB_GAIN_BAND_5G_L = 1, 5685 RTW89_BB_GAIN_BAND_5G_M = 2, 5686 RTW89_BB_GAIN_BAND_5G_H = 3, 5687 RTW89_BB_GAIN_BAND_6G_L = 4, 5688 RTW89_BB_GAIN_BAND_6G_M = 5, 5689 RTW89_BB_GAIN_BAND_6G_H = 6, 5690 RTW89_BB_GAIN_BAND_6G_UH = 7, 5691 5692 RTW89_BB_GAIN_BAND_NR, 5693 }; 5694 5695 enum rtw89_phy_gain_band_be { 5696 RTW89_BB_GAIN_BAND_2G_BE = 0, 5697 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5698 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5699 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5700 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5701 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5702 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5703 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5704 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5705 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5706 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5707 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5708 5709 RTW89_BB_GAIN_BAND_NR_BE, 5710 }; 5711 5712 enum rtw89_phy_bb_bw_be { 5713 RTW89_BB_BW_20_40 = 0, 5714 RTW89_BB_BW_80_160_320 = 1, 5715 5716 RTW89_BB_BW_NR_BE, 5717 }; 5718 5719 enum rtw89_bw20_sc { 5720 RTW89_BW20_SC_20M = 1, 5721 RTW89_BW20_SC_40M = 2, 5722 RTW89_BW20_SC_80M = 4, 5723 RTW89_BW20_SC_160M = 8, 5724 RTW89_BW20_SC_320M = 16, 5725 }; 5726 5727 enum rtw89_cmac_table_bw { 5728 RTW89_CMAC_BW_20M = 0, 5729 RTW89_CMAC_BW_40M = 1, 5730 RTW89_CMAC_BW_80M = 2, 5731 RTW89_CMAC_BW_160M = 3, 5732 RTW89_CMAC_BW_320M = 4, 5733 5734 RTW89_CMAC_BW_NR, 5735 }; 5736 5737 enum rtw89_phy_bb_rxsc_num { 5738 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5739 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5740 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5741 }; 5742 5743 struct rtw89_phy_bb_gain_info { 5744 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5745 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5746 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5747 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5748 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5749 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5750 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5751 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5752 [RTW89_BB_RXSC_NUM_40]; 5753 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5754 [RTW89_BB_RXSC_NUM_80]; 5755 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5756 [RTW89_BB_RXSC_NUM_160]; 5757 }; 5758 5759 struct rtw89_phy_bb_gain_info_be { 5760 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5761 [LNA_GAIN_NUM]; 5762 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5763 [TIA_GAIN_NUM]; 5764 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5765 [RF_PATH_MAX][LNA_GAIN_NUM]; 5766 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5767 [RF_PATH_MAX][LNA_GAIN_NUM]; 5768 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5769 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5770 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5771 [RTW89_BW20_SC_20M]; 5772 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5773 [RTW89_BW20_SC_40M]; 5774 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5775 [RTW89_BW20_SC_80M]; 5776 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5777 [RTW89_BW20_SC_160M]; 5778 }; 5779 5780 struct rtw89_phy_efuse_gain { 5781 bool offset_valid; 5782 bool comp_valid; 5783 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5784 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5785 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5786 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5787 }; 5788 5789 #define RTW89_MAX_PATTERN_NUM 18 5790 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5791 #define RTW89_MAX_PATTERN_SIZE 128 5792 5793 struct rtw89_wow_cam_info { 5794 bool r_w; 5795 u8 idx; 5796 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5797 u16 crc; 5798 bool negative_pattern_match; 5799 bool skip_mac_hdr; 5800 bool uc; 5801 bool mc; 5802 bool bc; 5803 bool valid; 5804 }; 5805 5806 struct rtw89_wow_key_info { 5807 u8 ptk_tx_iv[8]; 5808 u8 valid_check; 5809 u8 symbol_check_en; 5810 u8 gtk_keyidx; 5811 u8 rsvd[5]; 5812 u8 ptk_rx_iv[8]; 5813 u8 gtk_rx_iv[4][8]; 5814 } __packed; 5815 5816 struct rtw89_wow_gtk_info { 5817 u8 kck[32]; 5818 u8 kek[32]; 5819 u8 tk1[16]; 5820 u8 rxmickey[8]; 5821 u8 txmickey[8]; 5822 __le32 igtk_keyid; 5823 __le64 ipn; 5824 u8 igtk[2][32]; 5825 u8 psk[32]; 5826 } __packed; 5827 5828 struct rtw89_wow_aoac_report { 5829 u8 rpt_ver; 5830 u8 sec_type; 5831 u8 key_idx; 5832 u8 pattern_idx; 5833 u8 rekey_ok; 5834 u8 ptk_tx_iv[8]; 5835 u8 eapol_key_replay_count[8]; 5836 u8 gtk[32]; 5837 u8 ptk_rx_iv[8]; 5838 u8 gtk_rx_iv[4][8]; 5839 u64 igtk_key_id; 5840 u64 igtk_ipn; 5841 u8 igtk[32]; 5842 u8 csa_pri_ch; 5843 u8 csa_bw; 5844 u8 csa_ch_offset; 5845 u8 csa_chsw_failed; 5846 u8 csa_ch_band; 5847 }; 5848 5849 struct rtw89_wow_param { 5850 struct rtw89_vif_link *rtwvif_link; 5851 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5852 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5853 struct rtw89_wow_key_info key_info; 5854 struct rtw89_wow_gtk_info gtk_info; 5855 struct rtw89_wow_aoac_report aoac_rpt; 5856 u8 pattern_cnt; 5857 u8 ptk_alg; 5858 u8 gtk_alg; 5859 u8 ptk_keyidx; 5860 u8 akm; 5861 5862 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5863 struct rtw89_wait_info wait; 5864 5865 bool pno_inited; 5866 struct list_head pno_pkt_list; 5867 struct cfg80211_sched_scan_request *nd_config; 5868 }; 5869 5870 struct rtw89_mcc_limit { 5871 bool enable; 5872 u16 max_tob; /* TU; max time offset behind */ 5873 u16 max_toa; /* TU; max time offset ahead */ 5874 u16 max_dur; /* TU */ 5875 }; 5876 5877 struct rtw89_mcc_policy { 5878 u8 c2h_rpt; 5879 u8 tx_null_early; 5880 u8 dis_tx_null; 5881 u8 in_curr_ch; 5882 u8 dis_sw_retry; 5883 u8 sw_retry_count; 5884 }; 5885 5886 struct rtw89_mcc_role { 5887 struct rtw89_vif_link *rtwvif_link; 5888 struct rtw89_mcc_policy policy; 5889 struct rtw89_mcc_limit limit; 5890 5891 const struct rtw89_mcc_courtesy_cfg *crtz; 5892 5893 /* only valid when running with FW MRC mechanism */ 5894 u8 slot_idx; 5895 5896 /* byte-array in LE order for FW */ 5897 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5898 u8 probe_count; 5899 5900 u16 duration; /* TU */ 5901 u16 beacon_interval; /* TU */ 5902 bool is_2ghz; 5903 bool is_go; 5904 bool is_gc; 5905 bool ignore_bcn; 5906 }; 5907 5908 struct rtw89_mcc_bt_role { 5909 u16 duration; /* TU */ 5910 }; 5911 5912 struct rtw89_mcc_courtesy_cfg { 5913 u8 slot_num; 5914 u8 macid_tgt; 5915 }; 5916 5917 struct rtw89_mcc_courtesy { 5918 struct rtw89_mcc_courtesy_cfg ref; 5919 struct rtw89_mcc_courtesy_cfg aux; 5920 }; 5921 5922 enum rtw89_mcc_plan { 5923 RTW89_MCC_PLAN_TAIL_BT, 5924 RTW89_MCC_PLAN_MID_BT, 5925 RTW89_MCC_PLAN_NO_BT, 5926 5927 NUM_OF_RTW89_MCC_PLAN, 5928 }; 5929 5930 struct rtw89_mcc_pattern { 5931 s16 tob_ref; /* TU; time offset behind of reference role */ 5932 s16 toa_ref; /* TU; time offset ahead of reference role */ 5933 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5934 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5935 5936 enum rtw89_mcc_plan plan; 5937 struct rtw89_mcc_courtesy courtesy; 5938 }; 5939 5940 struct rtw89_mcc_sync { 5941 bool enable; 5942 u16 offset; /* TU */ 5943 u8 macid_src; 5944 u8 band_src; 5945 u8 port_src; 5946 u8 macid_tgt; 5947 u8 band_tgt; 5948 u8 port_tgt; 5949 }; 5950 5951 struct rtw89_mcc_config { 5952 struct rtw89_mcc_pattern pattern; 5953 struct rtw89_mcc_sync sync; 5954 u64 start_tsf; 5955 u64 start_tsf_in_aux_domain; 5956 u64 prepare_delay; 5957 u16 mcc_interval; /* TU */ 5958 u16 beacon_offset; /* TU */ 5959 }; 5960 5961 enum rtw89_mcc_mode { 5962 RTW89_MCC_MODE_GO_STA, 5963 RTW89_MCC_MODE_GC_STA, 5964 }; 5965 5966 struct rtw89_mcc_info { 5967 struct rtw89_wait_info wait; 5968 5969 u8 group; 5970 enum rtw89_mcc_mode mode; 5971 struct rtw89_mcc_role role_ref; /* reference role */ 5972 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5973 struct rtw89_mcc_bt_role bt_role; 5974 struct rtw89_mcc_config config; 5975 }; 5976 5977 enum rtw89_mlo_mode { 5978 RTW89_MLO_MODE_MLSR = 0, 5979 RTW89_MLO_MODE_EMLSR = 1, 5980 5981 NUM_OF_RTW89_MLO_MODE, 5982 }; 5983 5984 struct rtw89_mlo_info { 5985 struct rtw89_wait_info wait; 5986 }; 5987 5988 struct rtw89_beacon_track_info { 5989 bool is_data_ready; 5990 u32 tbtt_offset; /* in unit of microsecond */ 5991 u16 bcn_timeout; /* in unit of millisecond */ 5992 5993 /* The following are constant and set at association. */ 5994 u8 dtim; 5995 u16 beacon_int; 5996 u16 low_bcn_th; 5997 u16 med_bcn_th; 5998 u16 high_bcn_th; 5999 u16 target_bcn_th; 6000 u16 outlier_low_bcn_th; 6001 u16 outlier_high_bcn_th; 6002 u32 close_bcn_intvl_th; 6003 u32 tbtt_diff_th; 6004 }; 6005 6006 struct rtw89_dev { 6007 struct ieee80211_hw *hw; 6008 struct device *dev; 6009 const struct ieee80211_ops *ops; 6010 6011 bool dbcc_en; 6012 bool support_mlo; 6013 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 6014 struct rtw89_hw_scan_info scan_info; 6015 const struct rtw89_chip_info *chip; 6016 const struct rtw89_chip_variant *variant; 6017 const struct rtw89_pci_info *pci_info; 6018 const struct rtw89_rfe_parms *rfe_parms; 6019 struct rtw89_hal hal; 6020 struct rtw89_beacon_track_info bcn_track; 6021 struct rtw89_mcc_info mcc; 6022 struct rtw89_mlo_info mlo; 6023 struct rtw89_mac_info mac; 6024 struct rtw89_fw_info fw; 6025 struct rtw89_hci_info hci; 6026 struct rtw89_efuse efuse; 6027 struct rtw89_traffic_stats stats; 6028 struct rtw89_rfe_data *rfe_data; 6029 enum rtw89_custid custid; 6030 6031 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 6032 refcount_t refcount_ap_info; 6033 6034 struct list_head rtwvifs_list; 6035 /* used to protect rf read write */ 6036 struct mutex rf_mutex; 6037 struct workqueue_struct *txq_wq; 6038 struct work_struct txq_work; 6039 struct delayed_work txq_reinvoke_work; 6040 /* used to protect ba_list and forbid_ba_list */ 6041 spinlock_t ba_lock; 6042 /* txqs to setup ba session */ 6043 struct list_head ba_list; 6044 /* txqs to forbid ba session */ 6045 struct list_head forbid_ba_list; 6046 struct work_struct ba_work; 6047 /* used to protect rpwm */ 6048 spinlock_t rpwm_lock; 6049 6050 struct list_head tx_waits; 6051 struct wiphy_delayed_work tx_wait_work; 6052 6053 struct rtw89_tx_rpt tx_rpt; 6054 6055 struct rtw89_cam_info cam_info; 6056 6057 struct sk_buff_head c2h_queue; 6058 struct wiphy_work c2h_work; 6059 struct wiphy_work ips_work; 6060 struct wiphy_work cancel_6ghz_probe_work; 6061 struct work_struct load_firmware_work; 6062 6063 struct list_head early_h2c_list; 6064 6065 struct rtw89_ser ser; 6066 6067 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 6068 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 6069 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 6070 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 6071 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 6072 6073 struct rtw89_phy_stat phystat; 6074 struct rtw89_rfk_wait_info rfk_wait; 6075 struct rtw89_dack_info dack; 6076 struct rtw89_iqk_info iqk; 6077 struct rtw89_dpk_info dpk; 6078 struct rtw89_rfk_mcc_info rfk_mcc; 6079 struct rtw89_lck_info lck; 6080 struct rtw89_rx_dck_info rx_dck; 6081 bool is_tssi_mode[RF_PATH_MAX]; 6082 bool is_bt_iqk_timeout; 6083 6084 struct rtw89_fem_info fem; 6085 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 6086 struct rtw89_tssi_info tssi; 6087 struct rtw89_power_trim_info pwr_trim; 6088 6089 struct rtw89_cfo_tracking_info cfo_tracking; 6090 union { 6091 struct rtw89_phy_bb_gain_info ax; 6092 struct rtw89_phy_bb_gain_info_be be; 6093 } bb_gain; 6094 struct rtw89_phy_efuse_gain efuse_gain; 6095 struct rtw89_phy_ul_tb_info ul_tb_info; 6096 struct rtw89_antdiv_info antdiv; 6097 6098 struct rtw89_bb_ctx { 6099 enum rtw89_phy_idx phy_idx; 6100 struct rtw89_env_monitor_info env_monitor; 6101 struct rtw89_dig_info dig; 6102 struct rtw89_phy_ch_info ch_info; 6103 struct rtw89_edcca_bak edcca_bak; 6104 } bbs[RTW89_PHY_NUM]; 6105 6106 struct wiphy_delayed_work track_work; 6107 struct wiphy_delayed_work track_ps_work; 6108 struct wiphy_delayed_work chanctx_work; 6109 struct wiphy_delayed_work coex_act1_work; 6110 struct wiphy_delayed_work coex_bt_devinfo_work; 6111 struct wiphy_delayed_work coex_rfk_chk_work; 6112 struct wiphy_delayed_work cfo_track_work; 6113 struct wiphy_delayed_work mcc_prepare_done_work; 6114 struct delayed_work forbid_ba_work; 6115 struct wiphy_delayed_work antdiv_work; 6116 struct rtw89_ppdu_sts_info ppdu_sts; 6117 u8 total_sta_assoc; 6118 bool scanning; 6119 6120 struct rtw89_regulatory_info regulatory; 6121 struct rtw89_sar_info sar; 6122 struct rtw89_tas_info tas; 6123 struct rtw89_ant_gain_info ant_gain; 6124 6125 struct rtw89_btc btc; 6126 enum rtw89_ps_mode ps_mode; 6127 bool lps_enabled; 6128 u8 ps_hang_cnt; 6129 6130 struct rtw89_wow_param wow; 6131 6132 /* napi structure */ 6133 struct net_device *netdev; 6134 struct napi_struct napi; 6135 int napi_budget_countdown; 6136 6137 struct rtw89_debugfs *debugfs; 6138 struct rtw89_vif *pure_monitor_mode_vif; 6139 6140 /* HCI related data, keep last */ 6141 u8 priv[] __aligned(sizeof(void *)); 6142 }; 6143 6144 struct rtw89_link_conf_container { 6145 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 6146 }; 6147 6148 struct rtw89_vif_ml_trans { 6149 u16 mediate_links; 6150 u16 links_to_del; 6151 u16 links_to_add; 6152 }; 6153 6154 #define RTW89_VIF_IDLE_LINK_ID 0 6155 6156 struct rtw89_vif { 6157 struct rtw89_dev *rtwdev; 6158 struct list_head list; 6159 struct list_head mgnt_entry; 6160 struct rtw89_link_conf_container __rcu *snap_link_confs; 6161 6162 u8 mac_addr[ETH_ALEN]; 6163 __be32 ip_addr; 6164 6165 struct rtw89_traffic_stats stats; 6166 struct rtw89_traffic_stats stats_ps; 6167 u32 tdls_peer; 6168 6169 struct ieee80211_scan_ies *scan_ies; 6170 struct cfg80211_scan_request *scan_req; 6171 6172 struct rtw89_roc roc; 6173 bool offchan; 6174 6175 enum rtw89_mlo_mode mlo_mode; 6176 struct rtw89_vif_ml_trans ml_trans; 6177 6178 struct list_head dlink_pool; 6179 u8 links_inst_valid_num; 6180 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6181 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6182 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 6183 }; 6184 6185 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 6186 const struct rtw89_vif *rtwvif, 6187 unsigned int link_id) 6188 { 6189 *rtwvif_link = rtwvif->links[link_id]; 6190 return !!*rtwvif_link; 6191 } 6192 6193 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 6194 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6195 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 6196 6197 enum rtw89_sta_flags { 6198 RTW89_REMOTE_STA_IN_PS, 6199 6200 NUM_OF_RTW89_STA_FLAGS, 6201 }; 6202 6203 struct rtw89_sta { 6204 struct rtw89_dev *rtwdev; 6205 struct rtw89_vif *rtwvif; 6206 6207 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 6208 6209 bool disassoc; 6210 6211 struct sk_buff_head roc_queue; 6212 6213 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 6214 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 6215 6216 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 6217 6218 struct list_head dlink_pool; 6219 u8 links_inst_valid_num; 6220 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6221 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6222 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 6223 }; 6224 6225 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 6226 const struct rtw89_sta *rtwsta, 6227 unsigned int link_id) 6228 { 6229 *rtwsta_link = rtwsta->links[link_id]; 6230 return !!*rtwsta_link; 6231 } 6232 6233 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 6234 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6235 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 6236 6237 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 6238 { 6239 /* const after init, so no need to check if active first */ 6240 return rtwvif->links_inst[0].mac_id; 6241 } 6242 6243 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 6244 { 6245 /* const after init, so no need to check if active first */ 6246 return rtwvif->links_inst[0].port; 6247 } 6248 6249 static inline struct rtw89_vif_link * 6250 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 6251 { 6252 if (index >= rtwvif->links_inst_valid_num || 6253 !test_bit(index, rtwvif->links_inst_map)) 6254 return NULL; 6255 return &rtwvif->links_inst[index]; 6256 } 6257 6258 static inline 6259 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 6260 { 6261 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6262 6263 return rtwvif_link - rtwvif->links_inst; 6264 } 6265 6266 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 6267 { 6268 /* const after init, so no need to check if active first */ 6269 return rtwsta->links_inst[0].mac_id; 6270 } 6271 6272 static inline struct rtw89_sta_link * 6273 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 6274 { 6275 if (index >= rtwsta->links_inst_valid_num || 6276 !test_bit(index, rtwsta->links_inst_map)) 6277 return NULL; 6278 return &rtwsta->links_inst[index]; 6279 } 6280 6281 static inline 6282 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 6283 { 6284 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6285 6286 return rtwsta_link - rtwsta->links_inst; 6287 } 6288 6289 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 6290 { 6291 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6292 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6293 6294 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6295 rtwsta_link); 6296 } 6297 6298 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 6299 { 6300 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6301 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6302 6303 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6304 NULL); 6305 synchronize_rcu(); 6306 } 6307 6308 static inline struct rtw89_sta_link * 6309 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 6310 { 6311 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 6312 } 6313 6314 #define rtw89_get_designated_link(links_holder) \ 6315 ({ \ 6316 typeof(links_holder) p = links_holder; \ 6317 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 6318 }) 6319 6320 static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait) 6321 { 6322 dev_kfree_skb_any(wait->skb); 6323 kfree_rcu(wait, rcu_head); 6324 } 6325 6326 static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev) 6327 { 6328 struct rtw89_tx_wait_info *wait, *tmp; 6329 6330 lockdep_assert_wiphy(rtwdev->hw->wiphy); 6331 6332 list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) { 6333 if (!completion_done(&wait->completion)) 6334 continue; 6335 list_del(&wait->list); 6336 rtw89_tx_wait_release(wait); 6337 } 6338 } 6339 6340 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 6341 struct rtw89_core_tx_request *tx_req) 6342 { 6343 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 6344 } 6345 6346 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 6347 { 6348 rtwdev->hci.ops->reset(rtwdev); 6349 /* hci.ops->reset must complete all pending TX wait SKBs */ 6350 rtw89_tx_wait_list_clear(rtwdev); 6351 } 6352 6353 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 6354 { 6355 return rtwdev->hci.ops->start(rtwdev); 6356 } 6357 6358 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 6359 { 6360 rtwdev->hci.ops->stop(rtwdev); 6361 } 6362 6363 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 6364 { 6365 return rtwdev->hci.ops->deinit(rtwdev); 6366 } 6367 6368 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 6369 { 6370 rtwdev->hci.ops->pause(rtwdev, pause); 6371 } 6372 6373 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 6374 { 6375 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 6376 } 6377 6378 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 6379 { 6380 rtwdev->hci.ops->recalc_int_mit(rtwdev); 6381 } 6382 6383 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 6384 { 6385 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 6386 } 6387 6388 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 6389 { 6390 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 6391 } 6392 6393 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 6394 { 6395 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 6396 } 6397 6398 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 6399 bool drop) 6400 { 6401 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6402 return; 6403 6404 if (rtwdev->hci.ops->flush_queues) 6405 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 6406 } 6407 6408 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 6409 { 6410 if (rtwdev->hci.ops->recovery_start) 6411 rtwdev->hci.ops->recovery_start(rtwdev); 6412 } 6413 6414 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 6415 { 6416 if (rtwdev->hci.ops->recovery_complete) 6417 rtwdev->hci.ops->recovery_complete(rtwdev); 6418 } 6419 6420 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 6421 { 6422 if (rtwdev->hci.ops->enable_intr) 6423 rtwdev->hci.ops->enable_intr(rtwdev); 6424 } 6425 6426 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 6427 { 6428 if (rtwdev->hci.ops->disable_intr) 6429 rtwdev->hci.ops->disable_intr(rtwdev); 6430 } 6431 6432 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 6433 { 6434 if (rtwdev->hci.ops->ctrl_txdma_ch) 6435 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 6436 } 6437 6438 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6439 { 6440 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6441 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6442 } 6443 6444 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6445 { 6446 if (rtwdev->hci.ops->ctrl_trxhci) 6447 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6448 } 6449 6450 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6451 { 6452 int ret = 0; 6453 6454 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6455 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6456 return ret; 6457 } 6458 6459 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6460 { 6461 if (rtwdev->hci.ops->clr_idx_all) 6462 rtwdev->hci.ops->clr_idx_all(rtwdev); 6463 } 6464 6465 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6466 { 6467 int ret = 0; 6468 6469 if (rtwdev->hci.ops->rst_bdram) 6470 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6471 return ret; 6472 } 6473 6474 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6475 { 6476 if (rtwdev->hci.ops->clear) 6477 rtwdev->hci.ops->clear(rtwdev, pdev); 6478 } 6479 6480 static inline 6481 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6482 { 6483 /* 6484 * This should be used by/after rtw89_hci_tx_write() and before doing 6485 * ieee80211_tx_info_clear_status(). 6486 */ 6487 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6488 6489 return (struct rtw89_tx_skb_data *)info->driver_data; 6490 } 6491 6492 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6493 { 6494 return rtwdev->hci.ops->read8(rtwdev, addr); 6495 } 6496 6497 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6498 { 6499 return rtwdev->hci.ops->read16(rtwdev, addr); 6500 } 6501 6502 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6503 { 6504 return rtwdev->hci.ops->read32(rtwdev, addr); 6505 } 6506 6507 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6508 { 6509 rtwdev->hci.ops->write8(rtwdev, addr, data); 6510 } 6511 6512 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6513 { 6514 rtwdev->hci.ops->write16(rtwdev, addr, data); 6515 } 6516 6517 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6518 { 6519 rtwdev->hci.ops->write32(rtwdev, addr, data); 6520 } 6521 6522 static inline void 6523 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6524 { 6525 u8 val; 6526 6527 val = rtw89_read8(rtwdev, addr); 6528 rtw89_write8(rtwdev, addr, val | bit); 6529 } 6530 6531 static inline void 6532 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6533 { 6534 u16 val; 6535 6536 val = rtw89_read16(rtwdev, addr); 6537 rtw89_write16(rtwdev, addr, val | bit); 6538 } 6539 6540 static inline void 6541 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6542 { 6543 u32 val; 6544 6545 val = rtw89_read32(rtwdev, addr); 6546 rtw89_write32(rtwdev, addr, val | bit); 6547 } 6548 6549 static inline void 6550 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6551 { 6552 u8 val; 6553 6554 val = rtw89_read8(rtwdev, addr); 6555 rtw89_write8(rtwdev, addr, val & ~bit); 6556 } 6557 6558 static inline void 6559 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6560 { 6561 u16 val; 6562 6563 val = rtw89_read16(rtwdev, addr); 6564 rtw89_write16(rtwdev, addr, val & ~bit); 6565 } 6566 6567 static inline void 6568 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6569 { 6570 u32 val; 6571 6572 val = rtw89_read32(rtwdev, addr); 6573 rtw89_write32(rtwdev, addr, val & ~bit); 6574 } 6575 6576 static inline u32 6577 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6578 { 6579 u32 shift = __ffs(mask); 6580 u32 orig; 6581 u32 ret; 6582 6583 orig = rtw89_read32(rtwdev, addr); 6584 ret = (orig & mask) >> shift; 6585 6586 return ret; 6587 } 6588 6589 static inline u16 6590 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6591 { 6592 u32 shift = __ffs(mask); 6593 u32 orig; 6594 u32 ret; 6595 6596 orig = rtw89_read16(rtwdev, addr); 6597 ret = (orig & mask) >> shift; 6598 6599 return ret; 6600 } 6601 6602 static inline u8 6603 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6604 { 6605 u32 shift = __ffs(mask); 6606 u32 orig; 6607 u32 ret; 6608 6609 orig = rtw89_read8(rtwdev, addr); 6610 ret = (orig & mask) >> shift; 6611 6612 return ret; 6613 } 6614 6615 static inline void 6616 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6617 { 6618 u32 shift = __ffs(mask); 6619 u32 orig; 6620 u32 set; 6621 6622 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6623 6624 orig = rtw89_read32(rtwdev, addr); 6625 set = (orig & ~mask) | ((data << shift) & mask); 6626 rtw89_write32(rtwdev, addr, set); 6627 } 6628 6629 static inline void 6630 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6631 { 6632 u32 shift; 6633 u16 orig, set; 6634 6635 mask &= 0xffff; 6636 shift = __ffs(mask); 6637 6638 orig = rtw89_read16(rtwdev, addr); 6639 set = (orig & ~mask) | ((data << shift) & mask); 6640 rtw89_write16(rtwdev, addr, set); 6641 } 6642 6643 static inline void 6644 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6645 { 6646 u32 shift; 6647 u8 orig, set; 6648 6649 mask &= 0xff; 6650 shift = __ffs(mask); 6651 6652 orig = rtw89_read8(rtwdev, addr); 6653 set = (orig & ~mask) | ((data << shift) & mask); 6654 rtw89_write8(rtwdev, addr, set); 6655 } 6656 6657 static inline u32 6658 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6659 u32 addr, u32 mask) 6660 { 6661 u32 val; 6662 6663 mutex_lock(&rtwdev->rf_mutex); 6664 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6665 mutex_unlock(&rtwdev->rf_mutex); 6666 6667 return val; 6668 } 6669 6670 static inline void 6671 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6672 u32 addr, u32 mask, u32 data) 6673 { 6674 mutex_lock(&rtwdev->rf_mutex); 6675 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6676 mutex_unlock(&rtwdev->rf_mutex); 6677 } 6678 6679 static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr) 6680 { 6681 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE || 6682 !rtwdev->hci.ops->read32_pci_cfg) 6683 return RTW89_R32_EA; 6684 6685 return rtwdev->hci.ops->read32_pci_cfg(rtwdev, addr); 6686 } 6687 6688 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6689 { 6690 void *p = rtwtxq; 6691 6692 return container_of(p, struct ieee80211_txq, drv_priv); 6693 } 6694 6695 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6696 struct ieee80211_txq *txq) 6697 { 6698 struct rtw89_txq *rtwtxq; 6699 6700 if (!txq) 6701 return; 6702 6703 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6704 INIT_LIST_HEAD(&rtwtxq->list); 6705 } 6706 6707 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6708 { 6709 void *p = rtwvif; 6710 6711 return container_of(p, struct ieee80211_vif, drv_priv); 6712 } 6713 6714 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6715 { 6716 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6717 } 6718 6719 static inline 6720 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6721 { 6722 return rtwvif_to_vif(rtwvif_link->rtwvif); 6723 } 6724 6725 static inline 6726 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6727 { 6728 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6729 } 6730 6731 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6732 { 6733 return (struct rtw89_vif *)vif->drv_priv; 6734 } 6735 6736 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6737 { 6738 return vif ? vif_to_rtwvif(vif) : NULL; 6739 } 6740 6741 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6742 { 6743 void *p = rtwsta; 6744 6745 return container_of(p, struct ieee80211_sta, drv_priv); 6746 } 6747 6748 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6749 { 6750 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6751 } 6752 6753 static inline 6754 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6755 { 6756 return rtwsta_to_sta(rtwsta_link->rtwsta); 6757 } 6758 6759 static inline 6760 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6761 { 6762 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6763 } 6764 6765 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6766 { 6767 return (struct rtw89_sta *)sta->drv_priv; 6768 } 6769 6770 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6771 { 6772 return sta ? sta_to_rtwsta(sta) : NULL; 6773 } 6774 6775 static inline struct ieee80211_bss_conf * 6776 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6777 { 6778 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6779 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6780 struct rtw89_link_conf_container *snap; 6781 struct ieee80211_bss_conf *bss_conf; 6782 6783 snap = rcu_dereference(rtwvif->snap_link_confs); 6784 if (snap) { 6785 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6786 goto out; 6787 } 6788 6789 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6790 6791 out: 6792 if (unlikely(!bss_conf)) { 6793 *nolink = true; 6794 return &vif->bss_conf; 6795 } 6796 6797 *nolink = false; 6798 return bss_conf; 6799 } 6800 6801 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6802 ({ \ 6803 typeof(rtwvif_link) p = rtwvif_link; \ 6804 struct ieee80211_bss_conf *bss_conf; \ 6805 bool nolink; \ 6806 \ 6807 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6808 if (unlikely(nolink) && (assert)) \ 6809 rtw89_err(p->rtwvif->rtwdev, \ 6810 "%s: cannot find exact bss_conf for link_id %u\n",\ 6811 __func__, p->link_id); \ 6812 bss_conf; \ 6813 }) 6814 6815 static inline struct ieee80211_link_sta * 6816 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6817 { 6818 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6819 struct ieee80211_link_sta *link_sta; 6820 6821 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6822 if (unlikely(!link_sta)) { 6823 *nolink = true; 6824 return &sta->deflink; 6825 } 6826 6827 *nolink = false; 6828 return link_sta; 6829 } 6830 6831 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6832 ({ \ 6833 typeof(rtwsta_link) p = rtwsta_link; \ 6834 struct ieee80211_link_sta *link_sta; \ 6835 bool nolink; \ 6836 \ 6837 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6838 if (unlikely(nolink) && (assert)) \ 6839 rtw89_err(p->rtwsta->rtwdev, \ 6840 "%s: cannot find exact link_sta for link_id %u\n",\ 6841 __func__, p->link_id); \ 6842 link_sta; \ 6843 }) 6844 6845 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6846 { 6847 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6848 return RATE_INFO_BW_160; 6849 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6850 return RATE_INFO_BW_80; 6851 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6852 return RATE_INFO_BW_40; 6853 else 6854 return RATE_INFO_BW_20; 6855 } 6856 6857 static inline 6858 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6859 { 6860 switch (hw_band) { 6861 default: 6862 case RTW89_BAND_2G: 6863 return NL80211_BAND_2GHZ; 6864 case RTW89_BAND_5G: 6865 return NL80211_BAND_5GHZ; 6866 case RTW89_BAND_6G: 6867 return NL80211_BAND_6GHZ; 6868 } 6869 } 6870 6871 static inline 6872 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6873 { 6874 switch (nl_band) { 6875 default: 6876 case NL80211_BAND_2GHZ: 6877 return RTW89_BAND_2G; 6878 case NL80211_BAND_5GHZ: 6879 return RTW89_BAND_5G; 6880 case NL80211_BAND_6GHZ: 6881 return RTW89_BAND_6G; 6882 } 6883 } 6884 6885 static inline 6886 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6887 { 6888 switch (width) { 6889 default: 6890 WARN(1, "Not support bandwidth %d\n", width); 6891 fallthrough; 6892 case NL80211_CHAN_WIDTH_20_NOHT: 6893 case NL80211_CHAN_WIDTH_20: 6894 return RTW89_CHANNEL_WIDTH_20; 6895 case NL80211_CHAN_WIDTH_40: 6896 return RTW89_CHANNEL_WIDTH_40; 6897 case NL80211_CHAN_WIDTH_80: 6898 return RTW89_CHANNEL_WIDTH_80; 6899 case NL80211_CHAN_WIDTH_160: 6900 return RTW89_CHANNEL_WIDTH_160; 6901 } 6902 } 6903 6904 static inline 6905 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6906 { 6907 switch (rua) { 6908 default: 6909 WARN(1, "Invalid RU allocation: %d\n", rua); 6910 fallthrough; 6911 case 0 ... 36: 6912 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6913 case 37 ... 52: 6914 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6915 case 53 ... 60: 6916 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6917 case 61 ... 64: 6918 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6919 case 65 ... 66: 6920 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6921 case 67: 6922 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6923 case 68: 6924 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6925 } 6926 } 6927 6928 static inline 6929 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6930 struct rtw89_sta_link *rtwsta_link) 6931 { 6932 if (rtwsta_link) { 6933 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6934 6935 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6936 return &rtwsta_link->addr_cam; 6937 } 6938 return &rtwvif_link->addr_cam; 6939 } 6940 6941 static inline 6942 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6943 struct rtw89_sta_link *rtwsta_link) 6944 { 6945 if (rtwsta_link) { 6946 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6947 6948 if (sta->tdls) 6949 return &rtwsta_link->bssid_cam; 6950 } 6951 return &rtwvif_link->bssid_cam; 6952 } 6953 6954 static inline 6955 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6956 struct rtw89_channel_help_params *p, 6957 const struct rtw89_chan *chan, 6958 enum rtw89_mac_idx mac_idx, 6959 enum rtw89_phy_idx phy_idx) 6960 { 6961 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6962 mac_idx, phy_idx); 6963 } 6964 6965 static inline 6966 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6967 struct rtw89_channel_help_params *p, 6968 const struct rtw89_chan *chan, 6969 enum rtw89_mac_idx mac_idx, 6970 enum rtw89_phy_idx phy_idx) 6971 { 6972 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6973 mac_idx, phy_idx); 6974 } 6975 6976 static inline 6977 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6978 enum rtw89_chanctx_idx idx) 6979 { 6980 struct rtw89_hal *hal = &rtwdev->hal; 6981 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6982 6983 if (roc_idx == idx) 6984 return &hal->roc_chandef; 6985 6986 return &hal->chanctx[idx].chandef; 6987 } 6988 6989 static inline 6990 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6991 enum rtw89_chanctx_idx idx) 6992 { 6993 struct rtw89_hal *hal = &rtwdev->hal; 6994 6995 return &hal->chanctx[idx].chan; 6996 } 6997 6998 static inline 6999 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 7000 enum rtw89_chanctx_idx idx) 7001 { 7002 struct rtw89_hal *hal = &rtwdev->hal; 7003 7004 return &hal->chanctx[idx].rcd; 7005 } 7006 7007 static inline 7008 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 7009 { 7010 const struct rtw89_chanctx *chanctx = 7011 container_of_const(chan, struct rtw89_chanctx, chan); 7012 7013 return &chanctx->rcd; 7014 } 7015 7016 static inline 7017 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 7018 { 7019 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 7020 7021 if (rtwvif_link) 7022 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 7023 else 7024 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 7025 } 7026 7027 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 7028 { 7029 const struct rtw89_chip_info *chip = rtwdev->chip; 7030 7031 if (chip->ops->fem_setup) 7032 chip->ops->fem_setup(rtwdev); 7033 } 7034 7035 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 7036 { 7037 const struct rtw89_chip_info *chip = rtwdev->chip; 7038 7039 if (chip->ops->rfe_gpio) 7040 chip->ops->rfe_gpio(rtwdev); 7041 } 7042 7043 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 7044 { 7045 const struct rtw89_chip_info *chip = rtwdev->chip; 7046 7047 if (chip->ops->rfk_hw_init) 7048 chip->ops->rfk_hw_init(rtwdev); 7049 } 7050 7051 static inline 7052 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev) 7053 { 7054 const struct rtw89_chip_info *chip = rtwdev->chip; 7055 7056 if (!chip->ops->bb_preinit) 7057 return; 7058 7059 chip->ops->bb_preinit(rtwdev, RTW89_PHY_0); 7060 7061 if (rtwdev->dbcc_en) 7062 chip->ops->bb_preinit(rtwdev, RTW89_PHY_1); 7063 } 7064 7065 static inline 7066 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 7067 { 7068 const struct rtw89_chip_info *chip = rtwdev->chip; 7069 7070 if (!chip->ops->bb_postinit) 7071 return; 7072 7073 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 7074 7075 if (rtwdev->dbcc_en) 7076 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 7077 } 7078 7079 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 7080 { 7081 const struct rtw89_chip_info *chip = rtwdev->chip; 7082 7083 if (chip->ops->bb_sethw) 7084 chip->ops->bb_sethw(rtwdev); 7085 } 7086 7087 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 7088 { 7089 const struct rtw89_chip_info *chip = rtwdev->chip; 7090 7091 if (chip->ops->rfk_init) 7092 chip->ops->rfk_init(rtwdev); 7093 } 7094 7095 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 7096 { 7097 const struct rtw89_chip_info *chip = rtwdev->chip; 7098 7099 if (chip->ops->rfk_init_late) 7100 chip->ops->rfk_init_late(rtwdev); 7101 } 7102 7103 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 7104 struct rtw89_vif_link *rtwvif_link) 7105 { 7106 const struct rtw89_chip_info *chip = rtwdev->chip; 7107 7108 if (chip->ops->rfk_channel) 7109 chip->ops->rfk_channel(rtwdev, rtwvif_link); 7110 } 7111 7112 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 7113 enum rtw89_phy_idx phy_idx, 7114 const struct rtw89_chan *chan) 7115 { 7116 const struct rtw89_chip_info *chip = rtwdev->chip; 7117 7118 if (chip->ops->rfk_band_changed) 7119 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 7120 } 7121 7122 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 7123 struct rtw89_vif_link *rtwvif_link, bool start) 7124 { 7125 const struct rtw89_chip_info *chip = rtwdev->chip; 7126 7127 if (chip->ops->rfk_scan) 7128 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 7129 } 7130 7131 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 7132 { 7133 const struct rtw89_chip_info *chip = rtwdev->chip; 7134 7135 if (chip->ops->rfk_track) 7136 chip->ops->rfk_track(rtwdev); 7137 } 7138 7139 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 7140 { 7141 const struct rtw89_chip_info *chip = rtwdev->chip; 7142 7143 if (!chip->ops->set_txpwr_ctrl) 7144 return; 7145 7146 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 7147 if (rtwdev->dbcc_en) 7148 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 7149 } 7150 7151 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 7152 { 7153 const struct rtw89_chip_info *chip = rtwdev->chip; 7154 7155 if (chip->ops->power_trim) 7156 chip->ops->power_trim(rtwdev); 7157 } 7158 7159 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 7160 enum rtw89_phy_idx phy_idx) 7161 { 7162 const struct rtw89_chip_info *chip = rtwdev->chip; 7163 7164 if (chip->ops->init_txpwr_unit) 7165 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 7166 } 7167 7168 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 7169 { 7170 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 7171 if (rtwdev->dbcc_en) 7172 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 7173 } 7174 7175 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 7176 enum rtw89_rf_path rf_path) 7177 { 7178 const struct rtw89_chip_info *chip = rtwdev->chip; 7179 7180 if (!chip->ops->get_thermal) 7181 return 0x10; 7182 7183 return chip->ops->get_thermal(rtwdev, rf_path); 7184 } 7185 7186 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev, 7187 const struct rtw89_chan *chan) 7188 { 7189 const struct rtw89_chip_info *chip = rtwdev->chip; 7190 7191 if (!chip->ops->chan_to_rf18_val) 7192 return 0; 7193 7194 return chip->ops->chan_to_rf18_val(rtwdev, chan); 7195 } 7196 7197 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 7198 struct rtw89_rx_phy_ppdu *phy_ppdu, 7199 struct ieee80211_rx_status *status) 7200 { 7201 const struct rtw89_chip_info *chip = rtwdev->chip; 7202 7203 if (chip->ops->query_ppdu) 7204 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 7205 } 7206 7207 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 7208 struct rtw89_rx_phy_ppdu *phy_ppdu) 7209 { 7210 const struct rtw89_chip_info *chip = rtwdev->chip; 7211 7212 if (chip->ops->convert_rpl_to_rssi) 7213 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 7214 } 7215 7216 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 7217 struct rtw89_rx_desc_info *desc_info, 7218 struct ieee80211_rx_status *rx_status) 7219 { 7220 const struct rtw89_chip_info *chip = rtwdev->chip; 7221 7222 if (chip->ops->phy_rpt_to_rssi) 7223 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 7224 } 7225 7226 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 7227 enum rtw89_phy_idx phy_idx) 7228 { 7229 const struct rtw89_chip_info *chip = rtwdev->chip; 7230 7231 if (chip->ops->ctrl_nbtg_bt_tx) 7232 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 7233 } 7234 7235 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 7236 { 7237 const struct rtw89_chip_info *chip = rtwdev->chip; 7238 7239 if (chip->ops->cfg_txrx_path) 7240 chip->ops->cfg_txrx_path(rtwdev); 7241 } 7242 7243 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 7244 enum rtw89_phy_idx phy_idx) 7245 { 7246 const struct rtw89_chip_info *chip = rtwdev->chip; 7247 7248 if (chip->ops->digital_pwr_comp) 7249 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 7250 } 7251 7252 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 7253 const struct rtw89_txpwr_table *tbl) 7254 { 7255 tbl->load(rtwdev, tbl); 7256 } 7257 7258 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 7259 { 7260 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 7261 const struct rtw89_regd *regd = regulatory->regd; 7262 u8 txpwr_regd = regd->txpwr_regd[band]; 7263 7264 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK) 7265 return RTW89_ETSI; 7266 7267 return txpwr_regd; 7268 } 7269 7270 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 7271 enum rtw89_phy_idx phy_idx) 7272 { 7273 const struct rtw89_chip_info *chip = rtwdev->chip; 7274 7275 if (chip->ops->ctrl_btg_bt_rx) 7276 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 7277 } 7278 7279 static inline 7280 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 7281 struct rtw89_rx_desc_info *desc_info, 7282 u8 *data, u32 data_offset) 7283 { 7284 const struct rtw89_chip_info *chip = rtwdev->chip; 7285 7286 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 7287 } 7288 7289 static inline 7290 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 7291 struct rtw89_tx_desc_info *desc_info, 7292 void *txdesc) 7293 { 7294 const struct rtw89_chip_info *chip = rtwdev->chip; 7295 7296 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 7297 } 7298 7299 static inline 7300 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 7301 struct rtw89_tx_desc_info *desc_info, 7302 void *txdesc) 7303 { 7304 const struct rtw89_chip_info *chip = rtwdev->chip; 7305 7306 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 7307 } 7308 7309 static inline 7310 u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 7311 { 7312 const struct rtw89_chip_info *chip = rtwdev->chip; 7313 7314 return chip->ops->get_ch_dma[rtwdev->hci.type](rtwdev, qsel); 7315 } 7316 7317 static inline 7318 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 7319 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 7320 { 7321 const struct rtw89_chip_info *chip = rtwdev->chip; 7322 7323 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 7324 } 7325 7326 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 7327 { 7328 const struct rtw89_chip_info *chip = rtwdev->chip; 7329 7330 chip->ops->cfg_ctrl_path(rtwdev, wl); 7331 } 7332 7333 static inline 7334 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 7335 u32 *tx_en, enum rtw89_sch_tx_sel sel) 7336 { 7337 const struct rtw89_chip_info *chip = rtwdev->chip; 7338 7339 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 7340 } 7341 7342 static inline 7343 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 7344 { 7345 const struct rtw89_chip_info *chip = rtwdev->chip; 7346 7347 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 7348 } 7349 7350 static inline 7351 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 7352 struct rtw89_vif_link *rtwvif_link, 7353 struct rtw89_sta_link *rtwsta_link) 7354 { 7355 const struct rtw89_chip_info *chip = rtwdev->chip; 7356 7357 if (!chip->ops->h2c_dctl_sec_cam) 7358 return 0; 7359 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 7360 } 7361 7362 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 7363 { 7364 __le16 fc = hdr->frame_control; 7365 7366 if (ieee80211_has_tods(fc)) 7367 return hdr->addr1; 7368 else if (ieee80211_has_fromds(fc)) 7369 return hdr->addr2; 7370 else 7371 return hdr->addr3; 7372 } 7373 7374 static inline 7375 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 7376 { 7377 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 7378 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 7379 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 7380 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 7381 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 7382 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 7383 return true; 7384 return false; 7385 } 7386 7387 static inline 7388 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 7389 { 7390 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 7391 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 7392 return true; 7393 7394 return false; 7395 } 7396 7397 static inline 7398 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 7399 { 7400 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 7401 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 7402 return true; 7403 7404 return false; 7405 } 7406 7407 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 7408 enum rtw89_fw_type type) 7409 { 7410 struct rtw89_fw_info *fw_info = &rtwdev->fw; 7411 7412 switch (type) { 7413 case RTW89_FW_WOWLAN: 7414 return &fw_info->wowlan; 7415 case RTW89_FW_LOGFMT: 7416 return &fw_info->log.suit; 7417 case RTW89_FW_BBMCU0: 7418 return &fw_info->bbmcu0; 7419 case RTW89_FW_BBMCU1: 7420 return &fw_info->bbmcu1; 7421 default: 7422 break; 7423 } 7424 7425 return &fw_info->normal; 7426 } 7427 7428 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 7429 unsigned int length) 7430 { 7431 struct sk_buff *skb; 7432 7433 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 7434 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 7435 if (!skb) 7436 return NULL; 7437 7438 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 7439 return skb; 7440 } 7441 7442 return dev_alloc_skb(length); 7443 } 7444 7445 static inline bool rtw89_core_is_tx_wait(struct rtw89_dev *rtwdev, 7446 struct rtw89_tx_skb_data *skb_data) 7447 { 7448 return rcu_access_pointer(skb_data->wait); 7449 } 7450 7451 static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7452 struct rtw89_tx_skb_data *skb_data, 7453 u8 tx_status) 7454 { 7455 struct rtw89_tx_wait_info *wait; 7456 7457 guard(rcu)(); 7458 7459 wait = rcu_dereference(skb_data->wait); 7460 if (!wait) 7461 return false; 7462 7463 wait->tx_done = tx_status == RTW89_TX_DONE; 7464 /* Don't access skb anymore after completion */ 7465 complete_all(&wait->completion); 7466 return true; 7467 } 7468 7469 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 7470 { 7471 switch (rtwdev->mlo_dbcc_mode) { 7472 case MLO_1_PLUS_1_1RF: 7473 case MLO_1_PLUS_1_2RF: 7474 case DBCC_LEGACY: 7475 return true; 7476 default: 7477 return false; 7478 } 7479 } 7480 7481 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 7482 { 7483 if (!rtwdev->dbcc_en) 7484 return BIT(RTW89_PHY_0); 7485 7486 switch (rtwdev->mlo_dbcc_mode) { 7487 case MLO_0_PLUS_2_1RF: 7488 case MLO_0_PLUS_2_2RF: 7489 return BIT(RTW89_PHY_1); 7490 case MLO_1_PLUS_1_1RF: 7491 case MLO_1_PLUS_1_2RF: 7492 case MLO_2_PLUS_2_2RF: 7493 case DBCC_LEGACY: 7494 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 7495 case MLO_2_PLUS_0_1RF: 7496 case MLO_2_PLUS_0_2RF: 7497 default: 7498 return BIT(RTW89_PHY_0); 7499 } 7500 } 7501 7502 #define rtw89_for_each_active_bb(rtwdev, bb) \ 7503 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 7504 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 7505 if (__active_bb_bitmap & BIT(__phy_idx) && \ 7506 (bb = &rtwdev->bbs[__phy_idx])) 7507 7508 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 7509 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 7510 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 7511 if ((bb = &rtwdev->bbs[__phy_idx])) 7512 7513 static inline 7514 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 7515 enum rtw89_phy_idx phy_idx) 7516 { 7517 if (phy_idx >= RTW89_PHY_NUM) 7518 return &rtwdev->bbs[RTW89_PHY_0]; 7519 7520 return &rtwdev->bbs[phy_idx]; 7521 } 7522 7523 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7524 { 7525 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7526 7527 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7528 return true; 7529 7530 return false; 7531 } 7532 7533 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval) 7534 { 7535 switch (interval) { 7536 default: 7537 case RTW89_TFC_INTERVAL_2SEC: 7538 return bytes >> 18; /* bytes/2s --> Mbps */; 7539 case RTW89_TFC_INTERVAL_100MS: 7540 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */ 7541 } 7542 } 7543 7544 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7545 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7546 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7547 struct sk_buff *skb, bool fwdl); 7548 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7549 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7550 struct rtw89_tx_wait_info *wait, int qsel, 7551 unsigned int timeout); 7552 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7553 struct rtw89_tx_desc_info *desc_info, 7554 void *txdesc); 7555 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7556 struct rtw89_tx_desc_info *desc_info, 7557 void *txdesc); 7558 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7559 struct rtw89_tx_desc_info *desc_info, 7560 void *txdesc); 7561 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7562 struct rtw89_tx_desc_info *desc_info, 7563 void *txdesc); 7564 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7565 struct rtw89_tx_desc_info *desc_info, 7566 void *txdesc); 7567 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel); 7568 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel); 7569 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel); 7570 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7571 struct rtw89_rx_desc_info *desc_info, 7572 struct sk_buff *skb); 7573 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7574 struct rtw89_rx_desc_info *desc_info, 7575 u8 *data, u32 data_offset); 7576 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7577 struct rtw89_rx_desc_info *desc_info, 7578 u8 *data, u32 data_offset); 7579 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7580 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7581 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7582 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7583 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7584 struct rtw89_vif_link *rtwvif_link, 7585 struct rtw89_sta_link *rtwsta_link); 7586 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7587 struct rtw89_vif_link *rtwvif_link, 7588 struct rtw89_sta_link *rtwsta_link); 7589 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7590 struct rtw89_vif_link *rtwvif_link, 7591 struct rtw89_sta_link *rtwsta_link); 7592 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7593 struct rtw89_vif_link *rtwvif_link, 7594 struct rtw89_sta_link *rtwsta_link); 7595 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7596 struct rtw89_vif_link *rtwvif_link, 7597 struct rtw89_sta_link *rtwsta_link); 7598 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7599 struct ieee80211_sta *sta, 7600 struct cfg80211_tid_config *tid_config); 7601 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7602 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7603 int rtw89_core_init(struct rtw89_dev *rtwdev); 7604 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7605 int rtw89_core_register(struct rtw89_dev *rtwdev); 7606 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7607 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7608 u32 bus_data_size, 7609 const struct rtw89_chip_info *chip, 7610 const struct rtw89_chip_variant *variant); 7611 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7612 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7613 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7614 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7615 u8 mac_id, u8 port); 7616 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7617 struct rtw89_sta *rtwsta, u8 mac_id); 7618 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7619 unsigned int link_id); 7620 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7621 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7622 unsigned int link_id); 7623 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7624 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7625 const struct rtw89_6ghz_span * 7626 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7627 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7628 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7629 struct rtw89_chan *chan); 7630 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7631 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7632 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7633 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7634 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7635 struct rtw89_sta_link *rtwsta_link, u8 tid, 7636 u8 *cam_idx); 7637 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7638 struct rtw89_sta_link *rtwsta_link, u8 tid, 7639 u8 *cam_idx); 7640 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7641 struct ieee80211_sta *sta); 7642 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7643 struct ieee80211_sta *sta); 7644 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7645 struct ieee80211_sta *sta); 7646 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7647 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7648 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7649 struct rtw89_vif_link *rtwvif_link); 7650 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate); 7651 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7652 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7653 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 7654 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7655 struct rtw89_traffic_stats *stats); 7656 struct rtw89_wait_response * 7657 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 7658 __acquires(rtw89_wait); 7659 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 7660 struct rtw89_wait_response *prep, int err) 7661 __releases(rtw89_wait); 7662 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7663 const struct rtw89_completion_data *data); 7664 int rtw89_core_start(struct rtw89_dev *rtwdev); 7665 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7666 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7667 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7668 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7669 bool qos, bool ps, int timeout); 7670 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 7671 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7672 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7673 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7674 const u8 *mac_addr, bool hw_scan); 7675 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7676 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7677 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7678 bool active); 7679 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7680 struct rtw89_vif_link *rtwvif_link, 7681 struct ieee80211_bss_conf *bss_conf); 7682 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7683 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7684 unsigned int link_id); 7685 7686 #endif 7687