1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 struct rtw89_mac_gen_def; 18 struct rtw89_phy_gen_def; 19 struct rtw89_efuse_block_cfg; 20 struct rtw89_fw_txpwr_track_cfg; 21 struct rtw89_phy_rfk_log_fmt; 22 23 extern const struct ieee80211_ops rtw89_ops; 24 25 #define MASKBYTE0 0xff 26 #define MASKBYTE1 0xff00 27 #define MASKBYTE2 0xff0000 28 #define MASKBYTE3 0xff000000 29 #define MASKBYTE4 0xff00000000ULL 30 #define MASKHWORD 0xffff0000 31 #define MASKLWORD 0x0000ffff 32 #define MASKDWORD 0xffffffff 33 #define RFREG_MASK 0xfffff 34 #define INV_RF_DATA 0xffffffff 35 36 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 37 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 38 #define CFO_TRACK_MAX_USER 64 39 #define MAX_RSSI 110 40 #define RSSI_FACTOR 1 41 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 42 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 43 #define DELTA_SWINGIDX_SIZE 30 44 45 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 46 #define RTW89_RADIOTAP_ROOM_EHT \ 47 (sizeof(struct ieee80211_radiotap_tlv) + \ 48 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 49 sizeof(struct ieee80211_radiotap_tlv) + \ 50 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 51 #define RTW89_RADIOTAP_ROOM \ 52 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 53 54 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 55 #define RTW89_HTC_VARIANT_HE 3 56 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 57 #define RTW89_HTC_VARIANT_HE_CID_OM 1 58 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 59 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 60 61 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 62 enum htc_om_channel_width { 63 HTC_OM_CHANNEL_WIDTH_20 = 0, 64 HTC_OM_CHANNEL_WIDTH_40 = 1, 65 HTC_OM_CHANNEL_WIDTH_80 = 2, 66 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 67 }; 68 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 69 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 70 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 71 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 72 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 73 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 74 75 #define RTW89_TF_PAD GENMASK(11, 0) 76 #define RTW89_TF_BASIC_USER_INFO_SZ 6 77 78 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 79 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 80 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 81 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 82 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 83 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 84 85 enum rtw89_subband { 86 RTW89_CH_2G = 0, 87 RTW89_CH_5G_BAND_1 = 1, 88 /* RTW89_CH_5G_BAND_2 = 2, unused */ 89 RTW89_CH_5G_BAND_3 = 3, 90 RTW89_CH_5G_BAND_4 = 4, 91 92 RTW89_CH_6G_BAND_IDX0, /* Low */ 93 RTW89_CH_6G_BAND_IDX1, /* Low */ 94 RTW89_CH_6G_BAND_IDX2, /* Mid */ 95 RTW89_CH_6G_BAND_IDX3, /* Mid */ 96 RTW89_CH_6G_BAND_IDX4, /* High */ 97 RTW89_CH_6G_BAND_IDX5, /* High */ 98 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 99 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 100 101 RTW89_SUBBAND_NR, 102 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 103 }; 104 105 enum rtw89_gain_offset { 106 RTW89_GAIN_OFFSET_2G_CCK, 107 RTW89_GAIN_OFFSET_2G_OFDM, 108 RTW89_GAIN_OFFSET_5G_LOW, 109 RTW89_GAIN_OFFSET_5G_MID, 110 RTW89_GAIN_OFFSET_5G_HIGH, 111 RTW89_GAIN_OFFSET_6G_L0, 112 RTW89_GAIN_OFFSET_6G_L1, 113 RTW89_GAIN_OFFSET_6G_M0, 114 RTW89_GAIN_OFFSET_6G_M1, 115 RTW89_GAIN_OFFSET_6G_H0, 116 RTW89_GAIN_OFFSET_6G_H1, 117 RTW89_GAIN_OFFSET_6G_UH0, 118 RTW89_GAIN_OFFSET_6G_UH1, 119 120 RTW89_GAIN_OFFSET_NR, 121 }; 122 123 enum rtw89_hci_type { 124 RTW89_HCI_TYPE_PCIE, 125 RTW89_HCI_TYPE_USB, 126 RTW89_HCI_TYPE_SDIO, 127 }; 128 129 enum rtw89_core_chip_id { 130 RTL8852A, 131 RTL8852B, 132 RTL8852C, 133 RTL8851B, 134 RTL8922A, 135 }; 136 137 enum rtw89_chip_gen { 138 RTW89_CHIP_AX, 139 RTW89_CHIP_BE, 140 141 RTW89_CHIP_GEN_NUM, 142 }; 143 144 enum rtw89_cv { 145 CHIP_CAV, 146 CHIP_CBV, 147 CHIP_CCV, 148 CHIP_CDV, 149 CHIP_CEV, 150 CHIP_CFV, 151 CHIP_CV_MAX, 152 CHIP_CV_INVALID = CHIP_CV_MAX, 153 }; 154 155 enum rtw89_bacam_ver { 156 RTW89_BACAM_V0, 157 RTW89_BACAM_V1, 158 159 RTW89_BACAM_V0_EXT = 99, 160 }; 161 162 enum rtw89_core_tx_type { 163 RTW89_CORE_TX_TYPE_DATA, 164 RTW89_CORE_TX_TYPE_MGMT, 165 RTW89_CORE_TX_TYPE_FWCMD, 166 }; 167 168 enum rtw89_core_rx_type { 169 RTW89_CORE_RX_TYPE_WIFI = 0, 170 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 171 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 172 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 173 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 174 RTW89_CORE_RX_TYPE_SS2FW = 5, 175 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 176 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 177 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 178 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 179 RTW89_CORE_RX_TYPE_C2H = 10, 180 RTW89_CORE_RX_TYPE_CSI = 11, 181 RTW89_CORE_RX_TYPE_CQI = 12, 182 RTW89_CORE_RX_TYPE_H2C = 13, 183 RTW89_CORE_RX_TYPE_FWDL = 14, 184 }; 185 186 enum rtw89_txq_flags { 187 RTW89_TXQ_F_AMPDU = 0, 188 RTW89_TXQ_F_BLOCK_BA = 1, 189 RTW89_TXQ_F_FORBID_BA = 2, 190 }; 191 192 enum rtw89_net_type { 193 RTW89_NET_TYPE_NO_LINK = 0, 194 RTW89_NET_TYPE_AD_HOC = 1, 195 RTW89_NET_TYPE_INFRA = 2, 196 RTW89_NET_TYPE_AP_MODE = 3, 197 }; 198 199 enum rtw89_wifi_role { 200 RTW89_WIFI_ROLE_NONE, 201 RTW89_WIFI_ROLE_STATION, 202 RTW89_WIFI_ROLE_AP, 203 RTW89_WIFI_ROLE_AP_VLAN, 204 RTW89_WIFI_ROLE_ADHOC, 205 RTW89_WIFI_ROLE_ADHOC_MASTER, 206 RTW89_WIFI_ROLE_MESH_POINT, 207 RTW89_WIFI_ROLE_MONITOR, 208 RTW89_WIFI_ROLE_P2P_DEVICE, 209 RTW89_WIFI_ROLE_P2P_CLIENT, 210 RTW89_WIFI_ROLE_P2P_GO, 211 RTW89_WIFI_ROLE_NAN, 212 RTW89_WIFI_ROLE_MLME_MAX 213 }; 214 215 enum rtw89_upd_mode { 216 RTW89_ROLE_CREATE, 217 RTW89_ROLE_REMOVE, 218 RTW89_ROLE_TYPE_CHANGE, 219 RTW89_ROLE_INFO_CHANGE, 220 RTW89_ROLE_CON_DISCONN, 221 RTW89_ROLE_BAND_SW, 222 RTW89_ROLE_FW_RESTORE, 223 }; 224 225 enum rtw89_self_role { 226 RTW89_SELF_ROLE_CLIENT, 227 RTW89_SELF_ROLE_AP, 228 RTW89_SELF_ROLE_AP_CLIENT 229 }; 230 231 enum rtw89_msk_sO_el { 232 RTW89_NO_MSK, 233 RTW89_SMA, 234 RTW89_TMA, 235 RTW89_BSSID 236 }; 237 238 enum rtw89_sch_tx_sel { 239 RTW89_SCH_TX_SEL_ALL, 240 RTW89_SCH_TX_SEL_HIQ, 241 RTW89_SCH_TX_SEL_MG0, 242 RTW89_SCH_TX_SEL_MACID, 243 }; 244 245 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 246 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 247 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 248 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 249 */ 250 enum rtw89_add_cam_sec_mode { 251 RTW89_ADDR_CAM_SEC_NONE = 0, 252 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 253 RTW89_ADDR_CAM_SEC_NORMAL = 2, 254 RTW89_ADDR_CAM_SEC_4GROUP = 3, 255 }; 256 257 enum rtw89_sec_key_type { 258 RTW89_SEC_KEY_TYPE_NONE = 0, 259 RTW89_SEC_KEY_TYPE_WEP40 = 1, 260 RTW89_SEC_KEY_TYPE_WEP104 = 2, 261 RTW89_SEC_KEY_TYPE_TKIP = 3, 262 RTW89_SEC_KEY_TYPE_WAPI = 4, 263 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 264 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 265 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 266 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 267 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 268 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 269 }; 270 271 enum rtw89_port { 272 RTW89_PORT_0 = 0, 273 RTW89_PORT_1 = 1, 274 RTW89_PORT_2 = 2, 275 RTW89_PORT_3 = 3, 276 RTW89_PORT_4 = 4, 277 RTW89_PORT_NUM 278 }; 279 280 enum rtw89_band { 281 RTW89_BAND_2G = 0, 282 RTW89_BAND_5G = 1, 283 RTW89_BAND_6G = 2, 284 RTW89_BAND_NUM, 285 }; 286 287 enum rtw89_hw_rate { 288 RTW89_HW_RATE_CCK1 = 0x0, 289 RTW89_HW_RATE_CCK2 = 0x1, 290 RTW89_HW_RATE_CCK5_5 = 0x2, 291 RTW89_HW_RATE_CCK11 = 0x3, 292 RTW89_HW_RATE_OFDM6 = 0x4, 293 RTW89_HW_RATE_OFDM9 = 0x5, 294 RTW89_HW_RATE_OFDM12 = 0x6, 295 RTW89_HW_RATE_OFDM18 = 0x7, 296 RTW89_HW_RATE_OFDM24 = 0x8, 297 RTW89_HW_RATE_OFDM36 = 0x9, 298 RTW89_HW_RATE_OFDM48 = 0xA, 299 RTW89_HW_RATE_OFDM54 = 0xB, 300 RTW89_HW_RATE_MCS0 = 0x80, 301 RTW89_HW_RATE_MCS1 = 0x81, 302 RTW89_HW_RATE_MCS2 = 0x82, 303 RTW89_HW_RATE_MCS3 = 0x83, 304 RTW89_HW_RATE_MCS4 = 0x84, 305 RTW89_HW_RATE_MCS5 = 0x85, 306 RTW89_HW_RATE_MCS6 = 0x86, 307 RTW89_HW_RATE_MCS7 = 0x87, 308 RTW89_HW_RATE_MCS8 = 0x88, 309 RTW89_HW_RATE_MCS9 = 0x89, 310 RTW89_HW_RATE_MCS10 = 0x8A, 311 RTW89_HW_RATE_MCS11 = 0x8B, 312 RTW89_HW_RATE_MCS12 = 0x8C, 313 RTW89_HW_RATE_MCS13 = 0x8D, 314 RTW89_HW_RATE_MCS14 = 0x8E, 315 RTW89_HW_RATE_MCS15 = 0x8F, 316 RTW89_HW_RATE_MCS16 = 0x90, 317 RTW89_HW_RATE_MCS17 = 0x91, 318 RTW89_HW_RATE_MCS18 = 0x92, 319 RTW89_HW_RATE_MCS19 = 0x93, 320 RTW89_HW_RATE_MCS20 = 0x94, 321 RTW89_HW_RATE_MCS21 = 0x95, 322 RTW89_HW_RATE_MCS22 = 0x96, 323 RTW89_HW_RATE_MCS23 = 0x97, 324 RTW89_HW_RATE_MCS24 = 0x98, 325 RTW89_HW_RATE_MCS25 = 0x99, 326 RTW89_HW_RATE_MCS26 = 0x9A, 327 RTW89_HW_RATE_MCS27 = 0x9B, 328 RTW89_HW_RATE_MCS28 = 0x9C, 329 RTW89_HW_RATE_MCS29 = 0x9D, 330 RTW89_HW_RATE_MCS30 = 0x9E, 331 RTW89_HW_RATE_MCS31 = 0x9F, 332 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 333 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 334 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 335 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 336 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 337 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 338 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 339 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 340 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 341 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 342 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 343 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 344 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 345 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 346 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 347 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 348 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 349 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 350 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 351 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 352 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 353 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 354 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 355 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 356 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 357 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 358 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 359 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 360 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 361 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 362 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 363 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 364 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 365 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 366 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 367 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 368 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 369 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 370 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 371 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 372 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 373 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 374 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 375 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 376 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 377 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 378 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 379 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 380 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 381 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 382 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 383 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 384 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 385 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 386 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 387 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 388 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 389 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 390 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 391 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 392 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 393 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 394 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 395 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 396 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 397 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 398 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 399 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 400 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 401 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 402 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 403 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 404 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 405 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 406 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 407 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 408 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 409 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 410 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 411 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 412 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 413 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 414 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 415 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 416 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 417 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 418 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 419 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 420 421 RTW89_HW_RATE_V1_MCS0 = 0x100, 422 RTW89_HW_RATE_V1_MCS1 = 0x101, 423 RTW89_HW_RATE_V1_MCS2 = 0x102, 424 RTW89_HW_RATE_V1_MCS3 = 0x103, 425 RTW89_HW_RATE_V1_MCS4 = 0x104, 426 RTW89_HW_RATE_V1_MCS5 = 0x105, 427 RTW89_HW_RATE_V1_MCS6 = 0x106, 428 RTW89_HW_RATE_V1_MCS7 = 0x107, 429 RTW89_HW_RATE_V1_MCS8 = 0x108, 430 RTW89_HW_RATE_V1_MCS9 = 0x109, 431 RTW89_HW_RATE_V1_MCS10 = 0x10A, 432 RTW89_HW_RATE_V1_MCS11 = 0x10B, 433 RTW89_HW_RATE_V1_MCS12 = 0x10C, 434 RTW89_HW_RATE_V1_MCS13 = 0x10D, 435 RTW89_HW_RATE_V1_MCS14 = 0x10E, 436 RTW89_HW_RATE_V1_MCS15 = 0x10F, 437 RTW89_HW_RATE_V1_MCS16 = 0x110, 438 RTW89_HW_RATE_V1_MCS17 = 0x111, 439 RTW89_HW_RATE_V1_MCS18 = 0x112, 440 RTW89_HW_RATE_V1_MCS19 = 0x113, 441 RTW89_HW_RATE_V1_MCS20 = 0x114, 442 RTW89_HW_RATE_V1_MCS21 = 0x115, 443 RTW89_HW_RATE_V1_MCS22 = 0x116, 444 RTW89_HW_RATE_V1_MCS23 = 0x117, 445 RTW89_HW_RATE_V1_MCS24 = 0x118, 446 RTW89_HW_RATE_V1_MCS25 = 0x119, 447 RTW89_HW_RATE_V1_MCS26 = 0x11A, 448 RTW89_HW_RATE_V1_MCS27 = 0x11B, 449 RTW89_HW_RATE_V1_MCS28 = 0x11C, 450 RTW89_HW_RATE_V1_MCS29 = 0x11D, 451 RTW89_HW_RATE_V1_MCS30 = 0x11E, 452 RTW89_HW_RATE_V1_MCS31 = 0x11F, 453 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 454 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 455 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 456 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 465 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 466 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 467 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 468 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 477 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 478 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 479 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 480 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 489 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 490 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 491 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 492 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 501 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 502 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 503 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 504 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 513 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 514 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 515 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 516 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 525 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 526 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 527 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 528 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 537 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 538 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 539 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 540 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 549 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 550 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 551 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 552 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 565 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 566 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 567 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 568 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 579 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 580 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 581 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 582 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 593 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 594 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 595 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 596 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 607 608 RTW89_HW_RATE_NR, 609 RTW89_HW_RATE_INVAL, 610 611 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 612 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 613 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 614 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 615 }; 616 617 /* 2G channels, 618 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 619 */ 620 #define RTW89_2G_CH_NUM 14 621 622 /* 5G channels, 623 * 36, 38, 40, 42, 44, 46, 48, 50, 624 * 52, 54, 56, 58, 60, 62, 64, 625 * 100, 102, 104, 106, 108, 110, 112, 114, 626 * 116, 118, 120, 122, 124, 126, 128, 130, 627 * 132, 134, 136, 138, 140, 142, 144, 628 * 149, 151, 153, 155, 157, 159, 161, 163, 629 * 165, 167, 169, 171, 173, 175, 177 630 */ 631 #define RTW89_5G_CH_NUM 53 632 633 /* 6G channels, 634 * 1, 3, 5, 7, 9, 11, 13, 15, 635 * 17, 19, 21, 23, 25, 27, 29, 33, 636 * 35, 37, 39, 41, 43, 45, 47, 49, 637 * 51, 53, 55, 57, 59, 61, 65, 67, 638 * 69, 71, 73, 75, 77, 79, 81, 83, 639 * 85, 87, 89, 91, 93, 97, 99, 101, 640 * 103, 105, 107, 109, 111, 113, 115, 117, 641 * 119, 121, 123, 125, 129, 131, 133, 135, 642 * 137, 139, 141, 143, 145, 147, 149, 151, 643 * 153, 155, 157, 161, 163, 165, 167, 169, 644 * 171, 173, 175, 177, 179, 181, 183, 185, 645 * 187, 189, 193, 195, 197, 199, 201, 203, 646 * 205, 207, 209, 211, 213, 215, 217, 219, 647 * 221, 225, 227, 229, 231, 233, 235, 237, 648 * 239, 241, 243, 245, 247, 249, 251, 253, 649 */ 650 #define RTW89_6G_CH_NUM 120 651 652 enum rtw89_rate_section { 653 RTW89_RS_CCK, 654 RTW89_RS_OFDM, 655 RTW89_RS_MCS, /* for HT/VHT/HE */ 656 RTW89_RS_HEDCM, 657 RTW89_RS_OFFSET, 658 RTW89_RS_NUM, 659 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 660 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 661 }; 662 663 enum rtw89_rate_offset_indexes { 664 RTW89_RATE_OFFSET_HE, 665 RTW89_RATE_OFFSET_VHT, 666 RTW89_RATE_OFFSET_HT, 667 RTW89_RATE_OFFSET_OFDM, 668 RTW89_RATE_OFFSET_CCK, 669 RTW89_RATE_OFFSET_DLRU_EHT, 670 RTW89_RATE_OFFSET_DLRU_HE, 671 RTW89_RATE_OFFSET_EHT, 672 __RTW89_RATE_OFFSET_NUM, 673 674 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 675 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 676 }; 677 678 enum rtw89_rate_num { 679 RTW89_RATE_CCK_NUM = 4, 680 RTW89_RATE_OFDM_NUM = 8, 681 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 682 683 RTW89_RATE_MCS_NUM_AX = 12, 684 RTW89_RATE_MCS_NUM_BE = 16, 685 __RTW89_RATE_MCS_NUM = 16, 686 }; 687 688 enum rtw89_nss { 689 RTW89_NSS_1 = 0, 690 RTW89_NSS_2 = 1, 691 /* HE DCM only support 1ss and 2ss */ 692 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 693 RTW89_NSS_3 = 2, 694 RTW89_NSS_4 = 3, 695 RTW89_NSS_NUM, 696 }; 697 698 enum rtw89_ntx { 699 RTW89_1TX = 0, 700 RTW89_2TX = 1, 701 RTW89_NTX_NUM, 702 }; 703 704 enum rtw89_beamforming_type { 705 RTW89_NONBF = 0, 706 RTW89_BF = 1, 707 RTW89_BF_NUM, 708 }; 709 710 enum rtw89_ofdma_type { 711 RTW89_NON_OFDMA = 0, 712 RTW89_OFDMA = 1, 713 RTW89_OFDMA_NUM, 714 }; 715 716 enum rtw89_regulation_type { 717 RTW89_WW = 0, 718 RTW89_ETSI = 1, 719 RTW89_FCC = 2, 720 RTW89_MKK = 3, 721 RTW89_NA = 4, 722 RTW89_IC = 5, 723 RTW89_KCC = 6, 724 RTW89_ACMA = 7, 725 RTW89_NCC = 8, 726 RTW89_MEXICO = 9, 727 RTW89_CHILE = 10, 728 RTW89_UKRAINE = 11, 729 RTW89_CN = 12, 730 RTW89_QATAR = 13, 731 RTW89_UK = 14, 732 RTW89_THAILAND = 15, 733 RTW89_REGD_NUM, 734 }; 735 736 enum rtw89_reg_6ghz_power { 737 RTW89_REG_6GHZ_POWER_VLP = 0, 738 RTW89_REG_6GHZ_POWER_LPI = 1, 739 RTW89_REG_6GHZ_POWER_STD = 2, 740 741 NUM_OF_RTW89_REG_6GHZ_POWER, 742 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 743 }; 744 745 enum rtw89_fw_pkt_ofld_type { 746 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 747 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 748 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 749 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 750 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 751 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 752 RTW89_PKT_OFLD_TYPE_NDP = 6, 753 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 754 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 755 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 756 RTW89_PKT_OFLD_TYPE_NUM, 757 }; 758 759 struct rtw89_txpwr_byrate { 760 s8 cck[RTW89_RATE_CCK_NUM]; 761 s8 ofdm[RTW89_RATE_OFDM_NUM]; 762 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 763 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 764 s8 offset[__RTW89_RATE_OFFSET_NUM]; 765 s8 trap; 766 }; 767 768 struct rtw89_rate_desc { 769 enum rtw89_nss nss; 770 enum rtw89_rate_section rs; 771 enum rtw89_ofdma_type ofdma; 772 u8 idx; 773 }; 774 775 #define PHY_STS_HDR_LEN 8 776 #define RF_PATH_MAX 4 777 #define RTW89_MAX_PPDU_CNT 8 778 struct rtw89_rx_phy_ppdu { 779 void *buf; 780 u32 len; 781 u8 rssi_avg; 782 u8 rssi[RF_PATH_MAX]; 783 u8 mac_id; 784 u8 chan_idx; 785 u8 ie; 786 u16 rate; 787 struct { 788 bool has; 789 u8 avg_snr; 790 u8 evm_max; 791 u8 evm_min; 792 } ofdm; 793 bool to_self; 794 bool valid; 795 }; 796 797 enum rtw89_mac_idx { 798 RTW89_MAC_0 = 0, 799 RTW89_MAC_1 = 1, 800 }; 801 802 enum rtw89_phy_idx { 803 RTW89_PHY_0 = 0, 804 RTW89_PHY_1 = 1, 805 RTW89_PHY_MAX 806 }; 807 808 enum rtw89_sub_entity_idx { 809 RTW89_SUB_ENTITY_0 = 0, 810 RTW89_SUB_ENTITY_1 = 1, 811 812 NUM_OF_RTW89_SUB_ENTITY, 813 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 814 }; 815 816 enum rtw89_rf_path { 817 RF_PATH_A = 0, 818 RF_PATH_B = 1, 819 RF_PATH_C = 2, 820 RF_PATH_D = 3, 821 RF_PATH_AB, 822 RF_PATH_AC, 823 RF_PATH_AD, 824 RF_PATH_BC, 825 RF_PATH_BD, 826 RF_PATH_CD, 827 RF_PATH_ABC, 828 RF_PATH_ABD, 829 RF_PATH_ACD, 830 RF_PATH_BCD, 831 RF_PATH_ABCD, 832 }; 833 834 enum rtw89_rf_path_bit { 835 RF_A = BIT(0), 836 RF_B = BIT(1), 837 RF_C = BIT(2), 838 RF_D = BIT(3), 839 840 RF_AB = (RF_A | RF_B), 841 RF_AC = (RF_A | RF_C), 842 RF_AD = (RF_A | RF_D), 843 RF_BC = (RF_B | RF_C), 844 RF_BD = (RF_B | RF_D), 845 RF_CD = (RF_C | RF_D), 846 847 RF_ABC = (RF_A | RF_B | RF_C), 848 RF_ABD = (RF_A | RF_B | RF_D), 849 RF_ACD = (RF_A | RF_C | RF_D), 850 RF_BCD = (RF_B | RF_C | RF_D), 851 852 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 853 }; 854 855 enum rtw89_bandwidth { 856 RTW89_CHANNEL_WIDTH_20 = 0, 857 RTW89_CHANNEL_WIDTH_40 = 1, 858 RTW89_CHANNEL_WIDTH_80 = 2, 859 RTW89_CHANNEL_WIDTH_160 = 3, 860 RTW89_CHANNEL_WIDTH_320 = 4, 861 862 /* keep index order above */ 863 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 864 865 RTW89_CHANNEL_WIDTH_80_80 = 5, 866 RTW89_CHANNEL_WIDTH_5 = 6, 867 RTW89_CHANNEL_WIDTH_10 = 7, 868 }; 869 870 enum rtw89_ps_mode { 871 RTW89_PS_MODE_NONE = 0, 872 RTW89_PS_MODE_RFOFF = 1, 873 RTW89_PS_MODE_CLK_GATED = 2, 874 RTW89_PS_MODE_PWR_GATED = 3, 875 }; 876 877 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 878 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 879 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 880 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 881 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 882 883 enum rtw89_ru_bandwidth { 884 RTW89_RU26 = 0, 885 RTW89_RU52 = 1, 886 RTW89_RU106 = 2, 887 RTW89_RU52_26 = 3, 888 RTW89_RU106_26 = 4, 889 RTW89_RU_NUM, 890 }; 891 892 enum rtw89_sc_offset { 893 RTW89_SC_DONT_CARE = 0, 894 RTW89_SC_20_UPPER = 1, 895 RTW89_SC_20_LOWER = 2, 896 RTW89_SC_20_UPMOST = 3, 897 RTW89_SC_20_LOWEST = 4, 898 RTW89_SC_20_UP2X = 5, 899 RTW89_SC_20_LOW2X = 6, 900 RTW89_SC_20_UP3X = 7, 901 RTW89_SC_20_LOW3X = 8, 902 RTW89_SC_40_UPPER = 9, 903 RTW89_SC_40_LOWER = 10, 904 }; 905 906 enum rtw89_wow_flags { 907 RTW89_WOW_FLAG_EN_MAGIC_PKT, 908 RTW89_WOW_FLAG_EN_REKEY_PKT, 909 RTW89_WOW_FLAG_EN_DISCONNECT, 910 RTW89_WOW_FLAG_NUM, 911 }; 912 913 struct rtw89_chan { 914 u8 channel; 915 u8 primary_channel; 916 enum rtw89_band band_type; 917 enum rtw89_bandwidth band_width; 918 919 /* The follow-up are derived from the above. We must ensure that it 920 * is assigned correctly in rtw89_chan_create() if new one is added. 921 */ 922 u32 freq; 923 enum rtw89_subband subband_type; 924 enum rtw89_sc_offset pri_ch_idx; 925 u8 pri_sb_idx; 926 }; 927 928 struct rtw89_chan_rcd { 929 u8 prev_primary_channel; 930 enum rtw89_band prev_band_type; 931 bool band_changed; 932 }; 933 934 struct rtw89_channel_help_params { 935 u32 tx_en; 936 }; 937 938 struct rtw89_port_reg { 939 u32 port_cfg; 940 u32 tbtt_prohib; 941 u32 bcn_area; 942 u32 bcn_early; 943 u32 tbtt_early; 944 u32 tbtt_agg; 945 u32 bcn_space; 946 u32 bcn_forcetx; 947 u32 bcn_err_cnt; 948 u32 bcn_err_flag; 949 u32 dtim_ctrl; 950 u32 tbtt_shift; 951 u32 bcn_cnt_tmr; 952 u32 tsftr_l; 953 u32 tsftr_h; 954 u32 md_tsft; 955 u32 bss_color; 956 u32 mbssid; 957 u32 mbssid_drop; 958 u32 tsf_sync; 959 u32 hiq_win[RTW89_PORT_NUM]; 960 }; 961 962 struct rtw89_txwd_body { 963 __le32 dword0; 964 __le32 dword1; 965 __le32 dword2; 966 __le32 dword3; 967 __le32 dword4; 968 __le32 dword5; 969 } __packed; 970 971 struct rtw89_txwd_body_v1 { 972 __le32 dword0; 973 __le32 dword1; 974 __le32 dword2; 975 __le32 dword3; 976 __le32 dword4; 977 __le32 dword5; 978 __le32 dword6; 979 __le32 dword7; 980 } __packed; 981 982 struct rtw89_txwd_body_v2 { 983 __le32 dword0; 984 __le32 dword1; 985 __le32 dword2; 986 __le32 dword3; 987 __le32 dword4; 988 __le32 dword5; 989 __le32 dword6; 990 __le32 dword7; 991 } __packed; 992 993 struct rtw89_txwd_info { 994 __le32 dword0; 995 __le32 dword1; 996 __le32 dword2; 997 __le32 dword3; 998 __le32 dword4; 999 __le32 dword5; 1000 } __packed; 1001 1002 struct rtw89_txwd_info_v2 { 1003 __le32 dword0; 1004 __le32 dword1; 1005 __le32 dword2; 1006 __le32 dword3; 1007 __le32 dword4; 1008 __le32 dword5; 1009 __le32 dword6; 1010 __le32 dword7; 1011 } __packed; 1012 1013 struct rtw89_rx_desc_info { 1014 u16 pkt_size; 1015 u8 pkt_type; 1016 u8 drv_info_size; 1017 u8 phy_rpt_size; 1018 u8 hdr_cnv_size; 1019 u8 shift; 1020 u8 wl_hd_iv_len; 1021 bool long_rxdesc; 1022 bool bb_sel; 1023 bool mac_info_valid; 1024 u16 data_rate; 1025 u8 gi_ltf; 1026 u8 bw; 1027 u32 free_run_cnt; 1028 u8 user_id; 1029 bool sr_en; 1030 u8 ppdu_cnt; 1031 u8 ppdu_type; 1032 bool icv_err; 1033 bool crc32_err; 1034 bool hw_dec; 1035 bool sw_dec; 1036 bool addr1_match; 1037 u8 frag; 1038 u16 seq; 1039 u8 frame_type; 1040 u8 rx_pl_id; 1041 bool addr_cam_valid; 1042 u8 addr_cam_id; 1043 u8 sec_cam_id; 1044 u8 mac_id; 1045 u16 offset; 1046 u16 rxd_len; 1047 bool ready; 1048 }; 1049 1050 struct rtw89_rxdesc_short { 1051 __le32 dword0; 1052 __le32 dword1; 1053 __le32 dword2; 1054 __le32 dword3; 1055 } __packed; 1056 1057 struct rtw89_rxdesc_short_v2 { 1058 __le32 dword0; 1059 __le32 dword1; 1060 __le32 dword2; 1061 __le32 dword3; 1062 __le32 dword4; 1063 __le32 dword5; 1064 } __packed; 1065 1066 struct rtw89_rxdesc_long { 1067 __le32 dword0; 1068 __le32 dword1; 1069 __le32 dword2; 1070 __le32 dword3; 1071 __le32 dword4; 1072 __le32 dword5; 1073 __le32 dword6; 1074 __le32 dword7; 1075 } __packed; 1076 1077 struct rtw89_rxdesc_long_v2 { 1078 __le32 dword0; 1079 __le32 dword1; 1080 __le32 dword2; 1081 __le32 dword3; 1082 __le32 dword4; 1083 __le32 dword5; 1084 __le32 dword6; 1085 __le32 dword7; 1086 __le32 dword8; 1087 __le32 dword9; 1088 } __packed; 1089 1090 struct rtw89_tx_desc_info { 1091 u16 pkt_size; 1092 u8 wp_offset; 1093 u8 mac_id; 1094 u8 qsel; 1095 u8 ch_dma; 1096 u8 hdr_llc_len; 1097 bool is_bmc; 1098 bool en_wd_info; 1099 bool wd_page; 1100 bool use_rate; 1101 bool dis_data_fb; 1102 bool tid_indicate; 1103 bool agg_en; 1104 bool bk; 1105 u8 ampdu_density; 1106 u8 ampdu_num; 1107 bool sec_en; 1108 u8 addr_info_nr; 1109 u8 sec_keyid; 1110 u8 sec_type; 1111 u8 sec_cam_idx; 1112 u8 sec_seq[6]; 1113 u16 data_rate; 1114 u16 data_retry_lowest_rate; 1115 bool fw_dl; 1116 u16 seq; 1117 bool a_ctrl_bsr; 1118 u8 hw_ssn_sel; 1119 #define RTW89_MGMT_HW_SSN_SEL 1 1120 u8 hw_seq_mode; 1121 #define RTW89_MGMT_HW_SEQ_MODE 1 1122 bool hiq; 1123 u8 port; 1124 bool er_cap; 1125 }; 1126 1127 struct rtw89_core_tx_request { 1128 enum rtw89_core_tx_type tx_type; 1129 1130 struct sk_buff *skb; 1131 struct ieee80211_vif *vif; 1132 struct ieee80211_sta *sta; 1133 struct rtw89_tx_desc_info desc_info; 1134 }; 1135 1136 struct rtw89_txq { 1137 struct list_head list; 1138 unsigned long flags; 1139 int wait_cnt; 1140 }; 1141 1142 struct rtw89_mac_ax_gnt { 1143 u8 gnt_bt_sw_en; 1144 u8 gnt_bt; 1145 u8 gnt_wl_sw_en; 1146 u8 gnt_wl; 1147 } __packed; 1148 1149 #define RTW89_MAC_AX_COEX_GNT_NR 2 1150 struct rtw89_mac_ax_coex_gnt { 1151 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1152 }; 1153 1154 enum rtw89_btc_ncnt { 1155 BTC_NCNT_POWER_ON = 0x0, 1156 BTC_NCNT_POWER_OFF, 1157 BTC_NCNT_INIT_COEX, 1158 BTC_NCNT_SCAN_START, 1159 BTC_NCNT_SCAN_FINISH, 1160 BTC_NCNT_SPECIAL_PACKET, 1161 BTC_NCNT_SWITCH_BAND, 1162 BTC_NCNT_RFK_TIMEOUT, 1163 BTC_NCNT_SHOW_COEX_INFO, 1164 BTC_NCNT_ROLE_INFO, 1165 BTC_NCNT_CONTROL, 1166 BTC_NCNT_RADIO_STATE, 1167 BTC_NCNT_CUSTOMERIZE, 1168 BTC_NCNT_WL_RFK, 1169 BTC_NCNT_WL_STA, 1170 BTC_NCNT_FWINFO, 1171 BTC_NCNT_TIMER, 1172 BTC_NCNT_NUM 1173 }; 1174 1175 enum rtw89_btc_btinfo { 1176 BTC_BTINFO_L0 = 0, 1177 BTC_BTINFO_L1, 1178 BTC_BTINFO_L2, 1179 BTC_BTINFO_L3, 1180 BTC_BTINFO_H0, 1181 BTC_BTINFO_H1, 1182 BTC_BTINFO_H2, 1183 BTC_BTINFO_H3, 1184 BTC_BTINFO_MAX 1185 }; 1186 1187 enum rtw89_btc_dcnt { 1188 BTC_DCNT_RUN = 0x0, 1189 BTC_DCNT_CX_RUNINFO, 1190 BTC_DCNT_RPT, 1191 BTC_DCNT_RPT_HANG, 1192 BTC_DCNT_CYCLE, 1193 BTC_DCNT_CYCLE_HANG, 1194 BTC_DCNT_W1, 1195 BTC_DCNT_W1_HANG, 1196 BTC_DCNT_B1, 1197 BTC_DCNT_B1_HANG, 1198 BTC_DCNT_TDMA_NONSYNC, 1199 BTC_DCNT_SLOT_NONSYNC, 1200 BTC_DCNT_BTCNT_HANG, 1201 BTC_DCNT_WL_SLOT_DRIFT, 1202 BTC_DCNT_WL_STA_LAST, 1203 BTC_DCNT_BT_SLOT_DRIFT, 1204 BTC_DCNT_BT_SLOT_FLOOD, 1205 BTC_DCNT_FDDT_TRIG, 1206 BTC_DCNT_E2G, 1207 BTC_DCNT_E2G_HANG, 1208 BTC_DCNT_NUM 1209 }; 1210 1211 enum rtw89_btc_wl_state_cnt { 1212 BTC_WCNT_SCANAP = 0x0, 1213 BTC_WCNT_DHCP, 1214 BTC_WCNT_EAPOL, 1215 BTC_WCNT_ARP, 1216 BTC_WCNT_SCBDUPDATE, 1217 BTC_WCNT_RFK_REQ, 1218 BTC_WCNT_RFK_GO, 1219 BTC_WCNT_RFK_REJECT, 1220 BTC_WCNT_RFK_TIMEOUT, 1221 BTC_WCNT_CH_UPDATE, 1222 BTC_WCNT_NUM 1223 }; 1224 1225 enum rtw89_btc_bt_state_cnt { 1226 BTC_BCNT_RETRY = 0x0, 1227 BTC_BCNT_REINIT, 1228 BTC_BCNT_REENABLE, 1229 BTC_BCNT_SCBDREAD, 1230 BTC_BCNT_RELINK, 1231 BTC_BCNT_IGNOWL, 1232 BTC_BCNT_INQPAG, 1233 BTC_BCNT_INQ, 1234 BTC_BCNT_PAGE, 1235 BTC_BCNT_ROLESW, 1236 BTC_BCNT_AFH, 1237 BTC_BCNT_INFOUPDATE, 1238 BTC_BCNT_INFOSAME, 1239 BTC_BCNT_SCBDUPDATE, 1240 BTC_BCNT_HIPRI_TX, 1241 BTC_BCNT_HIPRI_RX, 1242 BTC_BCNT_LOPRI_TX, 1243 BTC_BCNT_LOPRI_RX, 1244 BTC_BCNT_POLUT, 1245 BTC_BCNT_RATECHG, 1246 BTC_BCNT_NUM 1247 }; 1248 1249 enum rtw89_btc_bt_profile { 1250 BTC_BT_NOPROFILE = 0, 1251 BTC_BT_HFP = BIT(0), 1252 BTC_BT_HID = BIT(1), 1253 BTC_BT_A2DP = BIT(2), 1254 BTC_BT_PAN = BIT(3), 1255 BTC_PROFILE_MAX = 4, 1256 }; 1257 1258 struct rtw89_btc_ant_info { 1259 u8 type; /* shared, dedicated */ 1260 u8 num; 1261 u8 isolation; 1262 1263 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1264 u8 diversity: 1; 1265 u8 btg_pos: 2; 1266 u8 stream_cnt: 4; 1267 }; 1268 1269 enum rtw89_tfc_dir { 1270 RTW89_TFC_UL, 1271 RTW89_TFC_DL, 1272 }; 1273 1274 struct rtw89_btc_wl_smap { 1275 u32 busy: 1; 1276 u32 scan: 1; 1277 u32 connecting: 1; 1278 u32 roaming: 1; 1279 u32 _4way: 1; 1280 u32 rf_off: 1; 1281 u32 lps: 2; 1282 u32 ips: 1; 1283 u32 init_ok: 1; 1284 u32 traffic_dir : 2; 1285 u32 rf_off_pre: 1; 1286 u32 lps_pre: 2; 1287 }; 1288 1289 enum rtw89_tfc_lv { 1290 RTW89_TFC_IDLE, 1291 RTW89_TFC_ULTRA_LOW, 1292 RTW89_TFC_LOW, 1293 RTW89_TFC_MID, 1294 RTW89_TFC_HIGH, 1295 }; 1296 1297 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1298 DECLARE_EWMA(tp, 10, 2); 1299 1300 struct rtw89_traffic_stats { 1301 /* units in bytes */ 1302 u64 tx_unicast; 1303 u64 rx_unicast; 1304 u32 tx_avg_len; 1305 u32 rx_avg_len; 1306 1307 /* count for packets */ 1308 u64 tx_cnt; 1309 u64 rx_cnt; 1310 1311 /* units in Mbps */ 1312 u32 tx_throughput; 1313 u32 rx_throughput; 1314 u32 tx_throughput_raw; 1315 u32 rx_throughput_raw; 1316 1317 u32 rx_tf_acc; 1318 u32 rx_tf_periodic; 1319 1320 enum rtw89_tfc_lv tx_tfc_lv; 1321 enum rtw89_tfc_lv rx_tfc_lv; 1322 struct ewma_tp tx_ewma_tp; 1323 struct ewma_tp rx_ewma_tp; 1324 1325 u16 tx_rate; 1326 u16 rx_rate; 1327 }; 1328 1329 struct rtw89_btc_statistic { 1330 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1331 struct rtw89_traffic_stats traffic; 1332 }; 1333 1334 #define BTC_WL_RSSI_THMAX 4 1335 1336 struct rtw89_btc_wl_link_info { 1337 struct rtw89_btc_statistic stat; 1338 enum rtw89_tfc_dir dir; 1339 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1340 u8 mac_addr[ETH_ALEN]; 1341 u8 busy; 1342 u8 ch; 1343 u8 bw; 1344 u8 band; 1345 u8 role; 1346 u8 pid; 1347 u8 phy; 1348 u8 dtim_period; 1349 u8 mode; 1350 1351 u8 mac_id; 1352 u8 tx_retry; 1353 1354 u32 bcn_period; 1355 u32 busy_t; 1356 u32 tx_time; 1357 u32 client_cnt; 1358 u32 rx_rate_drop_cnt; 1359 1360 u32 active: 1; 1361 u32 noa: 1; 1362 u32 client_ps: 1; 1363 u32 connected: 2; 1364 }; 1365 1366 union rtw89_btc_wl_state_map { 1367 u32 val; 1368 struct rtw89_btc_wl_smap map; 1369 }; 1370 1371 struct rtw89_btc_bt_hfp_desc { 1372 u32 exist: 1; 1373 u32 type: 2; 1374 u32 rsvd: 29; 1375 }; 1376 1377 struct rtw89_btc_bt_hid_desc { 1378 u32 exist: 1; 1379 u32 slot_info: 2; 1380 u32 pair_cnt: 2; 1381 u32 type: 8; 1382 u32 rsvd: 19; 1383 }; 1384 1385 struct rtw89_btc_bt_a2dp_desc { 1386 u8 exist: 1; 1387 u8 exist_last: 1; 1388 u8 play_latency: 1; 1389 u8 type: 3; 1390 u8 active: 1; 1391 u8 sink: 1; 1392 1393 u8 bitpool; 1394 u16 vendor_id; 1395 u32 device_name; 1396 u32 flush_time; 1397 }; 1398 1399 struct rtw89_btc_bt_pan_desc { 1400 u32 exist: 1; 1401 u32 type: 1; 1402 u32 active: 1; 1403 u32 rsvd: 29; 1404 }; 1405 1406 struct rtw89_btc_bt_rfk_info { 1407 u32 run: 1; 1408 u32 req: 1; 1409 u32 timeout: 1; 1410 u32 rsvd: 29; 1411 }; 1412 1413 union rtw89_btc_bt_rfk_info_map { 1414 u32 val; 1415 struct rtw89_btc_bt_rfk_info map; 1416 }; 1417 1418 struct rtw89_btc_bt_ver_info { 1419 u32 fw_coex; /* match with which coex_ver */ 1420 u32 fw; 1421 }; 1422 1423 struct rtw89_btc_bool_sta_chg { 1424 u32 now: 1; 1425 u32 last: 1; 1426 u32 remain: 1; 1427 u32 srvd: 29; 1428 }; 1429 1430 struct rtw89_btc_u8_sta_chg { 1431 u8 now; 1432 u8 last; 1433 u8 remain; 1434 u8 rsvd; 1435 }; 1436 1437 struct rtw89_btc_wl_scan_info { 1438 u8 band[RTW89_PHY_MAX]; 1439 u8 phy_map; 1440 u8 rsvd; 1441 }; 1442 1443 struct rtw89_btc_wl_dbcc_info { 1444 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1445 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1446 u8 real_band[RTW89_PHY_MAX]; 1447 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1448 }; 1449 1450 struct rtw89_btc_wl_active_role { 1451 u8 connected: 1; 1452 u8 pid: 3; 1453 u8 phy: 1; 1454 u8 noa: 1; 1455 u8 band: 2; 1456 1457 u8 client_ps: 1; 1458 u8 bw: 7; 1459 1460 u8 role; 1461 u8 ch; 1462 1463 u16 tx_lvl; 1464 u16 rx_lvl; 1465 u16 tx_rate; 1466 u16 rx_rate; 1467 }; 1468 1469 struct rtw89_btc_wl_active_role_v1 { 1470 u8 connected: 1; 1471 u8 pid: 3; 1472 u8 phy: 1; 1473 u8 noa: 1; 1474 u8 band: 2; 1475 1476 u8 client_ps: 1; 1477 u8 bw: 7; 1478 1479 u8 role; 1480 u8 ch; 1481 1482 u16 tx_lvl; 1483 u16 rx_lvl; 1484 u16 tx_rate; 1485 u16 rx_rate; 1486 1487 u32 noa_duration; /* ms */ 1488 }; 1489 1490 struct rtw89_btc_wl_active_role_v2 { 1491 u8 connected: 1; 1492 u8 pid: 3; 1493 u8 phy: 1; 1494 u8 noa: 1; 1495 u8 band: 2; 1496 1497 u8 client_ps: 1; 1498 u8 bw: 7; 1499 1500 u8 role; 1501 u8 ch; 1502 1503 u32 noa_duration; /* ms */ 1504 }; 1505 1506 struct rtw89_btc_wl_role_info_bpos { 1507 u16 none: 1; 1508 u16 station: 1; 1509 u16 ap: 1; 1510 u16 vap: 1; 1511 u16 adhoc: 1; 1512 u16 adhoc_master: 1; 1513 u16 mesh: 1; 1514 u16 moniter: 1; 1515 u16 p2p_device: 1; 1516 u16 p2p_gc: 1; 1517 u16 p2p_go: 1; 1518 u16 nan: 1; 1519 }; 1520 1521 struct rtw89_btc_wl_scc_ctrl { 1522 u8 null_role1; 1523 u8 null_role2; 1524 u8 ebt_null; /* if tx null at EBT slot */ 1525 }; 1526 1527 union rtw89_btc_wl_role_info_map { 1528 u16 val; 1529 struct rtw89_btc_wl_role_info_bpos role; 1530 }; 1531 1532 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1533 u8 connect_cnt; 1534 u8 link_mode; 1535 union rtw89_btc_wl_role_info_map role_map; 1536 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1537 }; 1538 1539 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1540 u8 connect_cnt; 1541 u8 link_mode; 1542 union rtw89_btc_wl_role_info_map role_map; 1543 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1544 u32 mrole_type; /* btc_wl_mrole_type */ 1545 u32 mrole_noa_duration; /* ms */ 1546 1547 u32 dbcc_en: 1; 1548 u32 dbcc_chg: 1; 1549 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1550 u32 link_mode_chg: 1; 1551 u32 rsvd: 27; 1552 }; 1553 1554 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1555 u8 connect_cnt; 1556 u8 link_mode; 1557 union rtw89_btc_wl_role_info_map role_map; 1558 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1559 u32 mrole_type; /* btc_wl_mrole_type */ 1560 u32 mrole_noa_duration; /* ms */ 1561 1562 u32 dbcc_en: 1; 1563 u32 dbcc_chg: 1; 1564 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1565 u32 link_mode_chg: 1; 1566 u32 rsvd: 27; 1567 }; 1568 1569 struct rtw89_btc_wl_ver_info { 1570 u32 fw_coex; /* match with which coex_ver */ 1571 u32 fw; 1572 u32 mac; 1573 u32 bb; 1574 u32 rf; 1575 }; 1576 1577 struct rtw89_btc_wl_afh_info { 1578 u8 en; 1579 u8 ch; 1580 u8 bw; 1581 u8 rsvd; 1582 } __packed; 1583 1584 struct rtw89_btc_wl_rfk_info { 1585 u32 state: 2; 1586 u32 path_map: 4; 1587 u32 phy_map: 2; 1588 u32 band: 2; 1589 u32 type: 8; 1590 u32 rsvd: 14; 1591 }; 1592 1593 struct rtw89_btc_bt_smap { 1594 u32 connect: 1; 1595 u32 ble_connect: 1; 1596 u32 acl_busy: 1; 1597 u32 sco_busy: 1; 1598 u32 mesh_busy: 1; 1599 u32 inq_pag: 1; 1600 }; 1601 1602 union rtw89_btc_bt_state_map { 1603 u32 val; 1604 struct rtw89_btc_bt_smap map; 1605 }; 1606 1607 #define BTC_BT_RSSI_THMAX 4 1608 #define BTC_BT_AFH_GROUP 12 1609 #define BTC_BT_AFH_LE_GROUP 5 1610 1611 struct rtw89_btc_bt_link_info { 1612 struct rtw89_btc_u8_sta_chg profile_cnt; 1613 struct rtw89_btc_bool_sta_chg multi_link; 1614 struct rtw89_btc_bool_sta_chg relink; 1615 struct rtw89_btc_bt_hfp_desc hfp_desc; 1616 struct rtw89_btc_bt_hid_desc hid_desc; 1617 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1618 struct rtw89_btc_bt_pan_desc pan_desc; 1619 union rtw89_btc_bt_state_map status; 1620 1621 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1622 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1623 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1624 u8 afh_map[BTC_BT_AFH_GROUP]; 1625 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1626 1627 u32 role_sw: 1; 1628 u32 slave_role: 1; 1629 u32 afh_update: 1; 1630 u32 cqddr: 1; 1631 u32 rssi: 8; 1632 u32 tx_3m: 1; 1633 u32 rsvd: 19; 1634 }; 1635 1636 struct rtw89_btc_3rdcx_info { 1637 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1638 u8 hw_coex; 1639 u16 rsvd; 1640 }; 1641 1642 struct rtw89_btc_dm_emap { 1643 u32 init: 1; 1644 u32 pta_owner: 1; 1645 u32 wl_rfk_timeout: 1; 1646 u32 bt_rfk_timeout: 1; 1647 u32 wl_fw_hang: 1; 1648 u32 cycle_hang: 1; 1649 u32 w1_hang: 1; 1650 u32 b1_hang: 1; 1651 u32 tdma_no_sync: 1; 1652 u32 slot_no_sync: 1; 1653 u32 wl_slot_drift: 1; 1654 u32 bt_slot_drift: 1; 1655 u32 role_num_mismatch: 1; 1656 u32 null1_tx_late: 1; 1657 u32 bt_afh_conflict: 1; 1658 u32 bt_leafh_conflict: 1; 1659 u32 bt_slot_flood: 1; 1660 u32 wl_e2g_hang: 1; 1661 u32 wl_ver_mismatch: 1; 1662 u32 bt_ver_mismatch: 1; 1663 }; 1664 1665 union rtw89_btc_dm_error_map { 1666 u32 val; 1667 struct rtw89_btc_dm_emap map; 1668 }; 1669 1670 struct rtw89_btc_rf_para { 1671 u32 tx_pwr_freerun; 1672 u32 rx_gain_freerun; 1673 u32 tx_pwr_perpkt; 1674 u32 rx_gain_perpkt; 1675 }; 1676 1677 struct rtw89_btc_wl_nhm { 1678 u8 instant_wl_nhm_dbm; 1679 u8 instant_wl_nhm_per_mhz; 1680 u16 valid_record_times; 1681 s8 record_pwr[16]; 1682 u8 record_ratio[16]; 1683 s8 pwr; /* dbm_per_MHz */ 1684 u8 ratio; 1685 u8 current_status; 1686 u8 refresh; 1687 bool start_flag; 1688 s8 pwr_max; 1689 s8 pwr_min; 1690 }; 1691 1692 struct rtw89_btc_wl_info { 1693 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1694 struct rtw89_btc_wl_rfk_info rfk_info; 1695 struct rtw89_btc_wl_ver_info ver_info; 1696 struct rtw89_btc_wl_afh_info afh_info; 1697 struct rtw89_btc_wl_role_info role_info; 1698 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1699 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1700 struct rtw89_btc_wl_scan_info scan_info; 1701 struct rtw89_btc_wl_dbcc_info dbcc_info; 1702 struct rtw89_btc_rf_para rf_para; 1703 struct rtw89_btc_wl_nhm nhm; 1704 union rtw89_btc_wl_state_map status; 1705 1706 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1707 u8 rssi_level; 1708 u8 cn_report; 1709 1710 bool scbd_change; 1711 u32 scbd; 1712 }; 1713 1714 struct rtw89_btc_module { 1715 struct rtw89_btc_ant_info ant; 1716 u8 rfe_type; 1717 u8 cv; 1718 1719 u8 bt_solo: 1; 1720 u8 bt_pos: 1; 1721 u8 switch_type: 1; 1722 u8 wa_type: 3; 1723 1724 u8 kt_ver_adie; 1725 }; 1726 1727 #define RTW89_BTC_DM_MAXSTEP 30 1728 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1729 1730 struct rtw89_btc_dm_step { 1731 u16 step[RTW89_BTC_DM_MAXSTEP]; 1732 u8 step_pos; 1733 bool step_ov; 1734 }; 1735 1736 struct rtw89_btc_init_info { 1737 struct rtw89_btc_module module; 1738 u8 wl_guard_ch; 1739 1740 u8 wl_only: 1; 1741 u8 wl_init_ok: 1; 1742 u8 dbcc_en: 1; 1743 u8 cx_other: 1; 1744 u8 bt_only: 1; 1745 1746 u16 rsvd; 1747 }; 1748 1749 struct rtw89_btc_wl_tx_limit_para { 1750 u16 enable; 1751 u32 tx_time; /* unit: us */ 1752 u16 tx_retry; 1753 }; 1754 1755 enum rtw89_btc_bt_scan_type { 1756 BTC_SCAN_INQ = 0, 1757 BTC_SCAN_PAGE, 1758 BTC_SCAN_BLE, 1759 BTC_SCAN_INIT, 1760 BTC_SCAN_TV, 1761 BTC_SCAN_ADV, 1762 BTC_SCAN_MAX1, 1763 }; 1764 1765 enum rtw89_btc_ble_scan_type { 1766 CXSCAN_BG = 0, 1767 CXSCAN_INIT, 1768 CXSCAN_LE, 1769 CXSCAN_MAX 1770 }; 1771 1772 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1773 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1774 1775 struct rtw89_btc_bt_scan_info_v1 { 1776 __le16 win; 1777 __le16 intvl; 1778 __le32 flags; 1779 } __packed; 1780 1781 struct rtw89_btc_bt_scan_info_v2 { 1782 __le16 win; 1783 __le16 intvl; 1784 } __packed; 1785 1786 struct rtw89_btc_fbtc_btscan_v1 { 1787 u8 fver; /* btc_ver::fcxbtscan */ 1788 u8 rsvd; 1789 __le16 rsvd2; 1790 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1791 } __packed; 1792 1793 struct rtw89_btc_fbtc_btscan_v2 { 1794 u8 fver; /* btc_ver::fcxbtscan */ 1795 u8 type; 1796 __le16 rsvd2; 1797 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1798 } __packed; 1799 1800 union rtw89_btc_fbtc_btscan { 1801 struct rtw89_btc_fbtc_btscan_v1 v1; 1802 struct rtw89_btc_fbtc_btscan_v2 v2; 1803 }; 1804 1805 struct rtw89_btc_bt_info { 1806 struct rtw89_btc_bt_link_info link_info; 1807 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1808 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1809 struct rtw89_btc_bt_ver_info ver_info; 1810 struct rtw89_btc_bool_sta_chg enable; 1811 struct rtw89_btc_bool_sta_chg inq_pag; 1812 struct rtw89_btc_rf_para rf_para; 1813 union rtw89_btc_bt_rfk_info_map rfk_info; 1814 1815 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1816 1817 u32 scbd; 1818 u32 feature; 1819 1820 u32 mbx_avl: 1; 1821 u32 whql_test: 1; 1822 u32 igno_wl: 1; 1823 u32 reinit: 1; 1824 u32 ble_scan_en: 1; 1825 u32 btg_type: 1; 1826 u32 inq: 1; 1827 u32 pag: 1; 1828 u32 run_patch_code: 1; 1829 u32 hi_lna_rx: 1; 1830 u32 scan_rx_low_pri: 1; 1831 u32 scan_info_update: 1; 1832 u32 rsvd: 20; 1833 }; 1834 1835 struct rtw89_btc_cx { 1836 struct rtw89_btc_wl_info wl; 1837 struct rtw89_btc_bt_info bt; 1838 struct rtw89_btc_3rdcx_info other; 1839 u32 state_map; 1840 u32 cnt_bt[BTC_BCNT_NUM]; 1841 u32 cnt_wl[BTC_WCNT_NUM]; 1842 }; 1843 1844 struct rtw89_btc_fbtc_tdma { 1845 u8 type; /* btc_ver::fcxtdma */ 1846 u8 rxflctrl; 1847 u8 txpause; 1848 u8 wtgle_n; 1849 u8 leak_n; 1850 u8 ext_ctrl; 1851 u8 rxflctrl_role; 1852 u8 option_ctrl; 1853 } __packed; 1854 1855 struct rtw89_btc_fbtc_tdma_v3 { 1856 u8 fver; /* btc_ver::fcxtdma */ 1857 u8 rsvd; 1858 __le16 rsvd1; 1859 struct rtw89_btc_fbtc_tdma tdma; 1860 } __packed; 1861 1862 union rtw89_btc_fbtc_tdma_le32 { 1863 struct rtw89_btc_fbtc_tdma v1; 1864 struct rtw89_btc_fbtc_tdma_v3 v3; 1865 }; 1866 1867 #define CXMREG_MAX 30 1868 #define CXMREG_MAX_V2 20 1869 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1870 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1871 1872 enum rtw89_btc_bt_sta_counter { 1873 BTC_BCNT_RFK_REQ = 0, 1874 BTC_BCNT_RFK_GO = 1, 1875 BTC_BCNT_RFK_REJECT = 2, 1876 BTC_BCNT_RFK_FAIL = 3, 1877 BTC_BCNT_RFK_TIMEOUT = 4, 1878 BTC_BCNT_HI_TX = 5, 1879 BTC_BCNT_HI_RX = 6, 1880 BTC_BCNT_LO_TX = 7, 1881 BTC_BCNT_LO_RX = 8, 1882 BTC_BCNT_POLLUTED = 9, 1883 BTC_BCNT_STA_MAX 1884 }; 1885 1886 enum rtw89_btc_bt_sta_counter_v105 { 1887 BTC_BCNT_RFK_REQ_V105 = 0, 1888 BTC_BCNT_HI_TX_V105 = 1, 1889 BTC_BCNT_HI_RX_V105 = 2, 1890 BTC_BCNT_LO_TX_V105 = 3, 1891 BTC_BCNT_LO_RX_V105 = 4, 1892 BTC_BCNT_POLLUTED_V105 = 5, 1893 BTC_BCNT_STA_MAX_V105 1894 }; 1895 1896 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1897 u16 fver; /* btc_ver::fcxbtcrpt */ 1898 u16 rpt_cnt; /* tmr counters */ 1899 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1900 u32 wl_fw_cx_offload; 1901 u32 wl_fw_ver; 1902 u32 rpt_enable; 1903 u32 rpt_para; /* ms */ 1904 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1905 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1906 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1907 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1908 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1909 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1910 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1911 u32 c2h_cnt; /* fw send c2h counter */ 1912 u32 h2c_cnt; /* fw recv h2c counter */ 1913 } __packed; 1914 1915 struct rtw89_btc_fbtc_rpt_ctrl_info { 1916 __le32 cnt; /* fw report counter */ 1917 __le32 en; /* report map */ 1918 __le32 para; /* not used */ 1919 1920 __le32 cnt_c2h; /* fw send c2h counter */ 1921 __le32 cnt_h2c; /* fw recv h2c counter */ 1922 __le32 len_c2h; /* The total length of the last C2H */ 1923 1924 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1925 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1926 } __packed; 1927 1928 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1929 __le32 cx_ver; /* match which driver's coex version */ 1930 __le32 fw_ver; 1931 __le32 en; /* report map */ 1932 1933 __le16 cnt; /* fw report counter */ 1934 __le16 cnt_c2h; /* fw send c2h counter */ 1935 __le16 cnt_h2c; /* fw recv h2c counter */ 1936 __le16 len_c2h; /* The total length of the last C2H */ 1937 1938 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1939 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1940 } __packed; 1941 1942 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1943 __le32 cx_ver; /* match which driver's coex version */ 1944 __le32 cx_offload; 1945 __le32 fw_ver; 1946 } __packed; 1947 1948 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1949 __le32 cnt_empty; /* a2dp empty count */ 1950 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1951 __le32 cnt_tx; 1952 __le32 cnt_ack; 1953 __le32 cnt_nack; 1954 } __packed; 1955 1956 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1957 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1958 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1959 __le32 cnt_recv; /* fw recv mailbox counter */ 1960 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1961 } __packed; 1962 1963 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1964 u8 fver; 1965 u8 rsvd; 1966 __le16 rsvd1; 1967 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1968 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1969 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1970 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1971 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1972 } __packed; 1973 1974 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1975 u8 fver; 1976 u8 rsvd; 1977 __le16 rsvd1; 1978 1979 u8 gnt_val[RTW89_PHY_MAX][4]; 1980 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1981 1982 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1983 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1984 } __packed; 1985 1986 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1987 u8 fver; 1988 u8 rsvd; 1989 __le16 rsvd1; 1990 1991 u8 gnt_val[RTW89_PHY_MAX][4]; 1992 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1993 1994 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1995 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1996 } __packed; 1997 1998 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1999 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2000 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2001 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2002 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2003 }; 2004 2005 enum rtw89_fbtc_ext_ctrl_type { 2006 CXECTL_OFF = 0x0, /* tdma off */ 2007 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2008 CXECTL_EXT = 0x2, 2009 CXECTL_MAX 2010 }; 2011 2012 union rtw89_btc_fbtc_rxflct { 2013 u8 val; 2014 u8 type: 3; 2015 u8 tgln_n: 5; 2016 }; 2017 2018 enum rtw89_btc_cxst_state { 2019 CXST_OFF = 0x0, 2020 CXST_B2W = 0x1, 2021 CXST_W1 = 0x2, 2022 CXST_W2 = 0x3, 2023 CXST_W2B = 0x4, 2024 CXST_B1 = 0x5, 2025 CXST_B2 = 0x6, 2026 CXST_B3 = 0x7, 2027 CXST_B4 = 0x8, 2028 CXST_LK = 0x9, 2029 CXST_BLK = 0xa, 2030 CXST_E2G = 0xb, 2031 CXST_E5G = 0xc, 2032 CXST_EBT = 0xd, 2033 CXST_ENULL = 0xe, 2034 CXST_WLK = 0xf, 2035 CXST_W1FDD = 0x10, 2036 CXST_B1FDD = 0x11, 2037 CXST_MAX = 0x12, 2038 }; 2039 2040 enum rtw89_btc_cxevnt { 2041 CXEVNT_TDMA_ENTRY = 0x0, 2042 CXEVNT_WL_TMR, 2043 CXEVNT_B1_TMR, 2044 CXEVNT_B2_TMR, 2045 CXEVNT_B3_TMR, 2046 CXEVNT_B4_TMR, 2047 CXEVNT_W2B_TMR, 2048 CXEVNT_B2W_TMR, 2049 CXEVNT_BCN_EARLY, 2050 CXEVNT_A2DP_EMPTY, 2051 CXEVNT_LK_END, 2052 CXEVNT_RX_ISR, 2053 CXEVNT_RX_FC0, 2054 CXEVNT_RX_FC1, 2055 CXEVNT_BT_RELINK, 2056 CXEVNT_BT_RETRY, 2057 CXEVNT_E2G, 2058 CXEVNT_E5G, 2059 CXEVNT_EBT, 2060 CXEVNT_ENULL, 2061 CXEVNT_DRV_WLK, 2062 CXEVNT_BCN_OK, 2063 CXEVNT_BT_CHANGE, 2064 CXEVNT_EBT_EXTEND, 2065 CXEVNT_E2G_NULL1, 2066 CXEVNT_B1FDD_TMR, 2067 CXEVNT_MAX 2068 }; 2069 2070 enum { 2071 CXBCN_ALL = 0x0, 2072 CXBCN_ALL_OK, 2073 CXBCN_BT_SLOT, 2074 CXBCN_BT_OK, 2075 CXBCN_MAX 2076 }; 2077 2078 enum btc_slot_type { 2079 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2080 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2081 CXSTYPE_NUM, 2082 }; 2083 2084 enum { /* TIME */ 2085 CXT_BT = 0x0, 2086 CXT_WL = 0x1, 2087 CXT_MAX 2088 }; 2089 2090 enum { /* TIME-A2DP */ 2091 CXT_FLCTRL_OFF = 0x0, 2092 CXT_FLCTRL_ON = 0x1, 2093 CXT_FLCTRL_MAX 2094 }; 2095 2096 enum { /* STEP TYPE */ 2097 CXSTEP_NONE = 0x0, 2098 CXSTEP_EVNT = 0x1, 2099 CXSTEP_SLOT = 0x2, 2100 CXSTEP_MAX, 2101 }; 2102 2103 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2104 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2105 RPT_BT_AFH_SEQ_LE = 0x20 2106 }; 2107 2108 #define BTC_DBG_MAX1 32 2109 struct rtw89_btc_fbtc_gpio_dbg { 2110 u8 fver; /* btc_ver::fcxgpiodbg */ 2111 u8 rsvd; 2112 u16 rsvd2; 2113 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2114 u32 pre_state; /* the debug signal is 1 or 0 */ 2115 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2116 } __packed; 2117 2118 struct rtw89_btc_fbtc_mreg_val_v1 { 2119 u8 fver; /* btc_ver::fcxmreg */ 2120 u8 reg_num; 2121 __le16 rsvd; 2122 __le32 mreg_val[CXMREG_MAX]; 2123 } __packed; 2124 2125 struct rtw89_btc_fbtc_mreg_val_v2 { 2126 u8 fver; /* btc_ver::fcxmreg */ 2127 u8 reg_num; 2128 __le16 rsvd; 2129 __le32 mreg_val[CXMREG_MAX_V2]; 2130 } __packed; 2131 2132 union rtw89_btc_fbtc_mreg_val { 2133 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2134 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2135 }; 2136 2137 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2138 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2139 .offset = cpu_to_le32(__offset), } 2140 2141 struct rtw89_btc_fbtc_mreg { 2142 __le16 type; 2143 __le16 bytes; 2144 __le32 offset; 2145 } __packed; 2146 2147 struct rtw89_btc_fbtc_slot { 2148 __le16 dur; 2149 __le32 cxtbl; 2150 __le16 cxtype; 2151 } __packed; 2152 2153 struct rtw89_btc_fbtc_slots { 2154 u8 fver; /* btc_ver::fcxslots */ 2155 u8 tbl_num; 2156 __le16 rsvd; 2157 __le32 update_map; 2158 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2159 } __packed; 2160 2161 struct rtw89_btc_fbtc_step { 2162 u8 type; 2163 u8 val; 2164 __le16 difft; 2165 } __packed; 2166 2167 struct rtw89_btc_fbtc_steps_v2 { 2168 u8 fver; /* btc_ver::fcxstep */ 2169 u8 rsvd; 2170 __le16 cnt; 2171 __le16 pos_old; 2172 __le16 pos_new; 2173 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2174 } __packed; 2175 2176 struct rtw89_btc_fbtc_steps_v3 { 2177 u8 fver; 2178 u8 en; 2179 __le16 rsvd; 2180 __le32 cnt; 2181 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2182 } __packed; 2183 2184 union rtw89_btc_fbtc_steps_info { 2185 struct rtw89_btc_fbtc_steps_v2 v2; 2186 struct rtw89_btc_fbtc_steps_v3 v3; 2187 }; 2188 2189 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2190 u8 fver; /* btc_ver::fcxcysta */ 2191 u8 rsvd; 2192 __le16 cycles; /* total cycle number */ 2193 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2194 __le16 a2dpept; /* a2dp empty cnt */ 2195 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2196 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2197 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2198 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2199 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2200 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2201 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2202 __le16 tmax_a2dpept; /* max a2dp empty time */ 2203 __le16 tavg_lk; /* avg leak-slot time */ 2204 __le16 tmax_lk; /* max leak-slot time */ 2205 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2206 __le32 bcn_cnt[CXBCN_MAX]; 2207 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2208 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2209 __le32 skip_cnt; 2210 __le32 exception; 2211 __le32 except_cnt; 2212 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2213 } __packed; 2214 2215 struct rtw89_btc_fbtc_fdd_try_info { 2216 __le16 cycles[CXT_FLCTRL_MAX]; 2217 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2218 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2219 } __packed; 2220 2221 struct rtw89_btc_fbtc_cycle_time_info { 2222 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2223 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2224 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2225 } __packed; 2226 2227 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2228 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2229 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2230 } __packed; 2231 2232 struct rtw89_btc_fbtc_a2dp_trx_stat { 2233 u8 empty_cnt; 2234 u8 retry_cnt; 2235 u8 tx_rate; 2236 u8 tx_cnt; 2237 u8 ack_cnt; 2238 u8 nack_cnt; 2239 u8 rsvd1; 2240 u8 rsvd2; 2241 } __packed; 2242 2243 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2244 u8 empty_cnt; 2245 u8 retry_cnt; 2246 u8 tx_rate; 2247 u8 tx_cnt; 2248 u8 ack_cnt; 2249 u8 nack_cnt; 2250 u8 no_empty_cnt; 2251 u8 rsvd; 2252 } __packed; 2253 2254 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2255 __le16 cnt; /* a2dp empty cnt */ 2256 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2257 __le16 tavg; /* avg a2dp empty time */ 2258 __le16 tmax; /* max a2dp empty time */ 2259 } __packed; 2260 2261 struct rtw89_btc_fbtc_cycle_leak_info { 2262 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2263 __le16 tavg; /* avg leak-slot time */ 2264 __le16 tmax; /* max leak-slot time */ 2265 } __packed; 2266 2267 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2268 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2269 2270 struct rtw89_btc_fbtc_cycle_fddt_info { 2271 __le16 train_cycle; 2272 __le16 tp; 2273 2274 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2275 s8 bt_tx_power; /* decrease Tx power (dB) */ 2276 s8 bt_rx_gain; /* LNA constrain level */ 2277 u8 no_empty_cnt; 2278 2279 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2280 u8 cn; /* condition_num */ 2281 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2282 u8 train_result; /* refer to enum btc_fddt_check_map */ 2283 } __packed; 2284 2285 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2286 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2287 2288 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2289 __le16 train_cycle; 2290 __le16 tp; 2291 2292 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2293 s8 bt_tx_power; /* decrease Tx power (dB) */ 2294 s8 bt_rx_gain; /* LNA constrain level */ 2295 u8 no_empty_cnt; 2296 2297 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2298 u8 cn; /* condition_num */ 2299 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2300 u8 train_result; /* refer to enum btc_fddt_check_map */ 2301 } __packed; 2302 2303 struct rtw89_btc_fbtc_fddt_cell_status { 2304 s8 wl_tx_pwr; 2305 s8 bt_tx_pwr; 2306 s8 bt_rx_gain; 2307 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2308 } __packed; 2309 2310 struct rtw89_btc_fbtc_fddt_cell_status_v5 { 2311 s8 wl_tx_pwr; 2312 s8 bt_tx_pwr; 2313 s8 bt_rx_gain; 2314 } __packed; 2315 2316 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2317 u8 fver; 2318 u8 rsvd; 2319 __le16 cycles; /* total cycle number */ 2320 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2321 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2322 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2323 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2324 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2325 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2326 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2327 __le32 bcn_cnt[CXBCN_MAX]; 2328 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2329 __le32 skip_cnt; 2330 __le32 except_cnt; 2331 __le32 except_map; 2332 } __packed; 2333 2334 #define FDD_TRAIN_WL_DIRECTION 2 2335 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2336 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2337 2338 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2339 u8 fver; 2340 u8 rsvd; 2341 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2342 u8 except_cnt; 2343 2344 __le16 skip_cnt; 2345 __le16 cycles; /* total cycle number */ 2346 2347 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2348 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2349 __le16 bcn_cnt[CXBCN_MAX]; 2350 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2351 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2352 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2353 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2354 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2355 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2356 [FDD_TRAIN_WL_RSSI_LEVEL] 2357 [FDD_TRAIN_BT_RSSI_LEVEL]; 2358 __le32 except_map; 2359 } __packed; 2360 2361 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2362 u8 fver; 2363 u8 rsvd; 2364 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2365 u8 except_cnt; 2366 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2367 2368 __le16 skip_cnt; 2369 __le16 cycles; /* total cycle number */ 2370 2371 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2372 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2373 __le16 bcn_cnt[CXBCN_MAX]; 2374 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2375 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2376 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2377 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2378 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2379 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] 2380 [FDD_TRAIN_WL_RSSI_LEVEL] 2381 [FDD_TRAIN_BT_RSSI_LEVEL]; 2382 __le32 except_map; 2383 } __packed; 2384 2385 union rtw89_btc_fbtc_cysta_info { 2386 struct rtw89_btc_fbtc_cysta_v2 v2; 2387 struct rtw89_btc_fbtc_cysta_v3 v3; 2388 struct rtw89_btc_fbtc_cysta_v4 v4; 2389 struct rtw89_btc_fbtc_cysta_v5 v5; 2390 }; 2391 2392 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2393 u8 fver; /* btc_ver::fcxnullsta */ 2394 u8 rsvd; 2395 __le16 rsvd2; 2396 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2397 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2398 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2399 } __packed; 2400 2401 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2402 u8 fver; /* btc_ver::fcxnullsta */ 2403 u8 rsvd; 2404 __le16 rsvd2; 2405 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2406 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2407 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2408 } __packed; 2409 2410 union rtw89_btc_fbtc_cynullsta_info { 2411 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2412 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2413 }; 2414 2415 struct rtw89_btc_fbtc_btver { 2416 u8 fver; /* btc_ver::fcxbtver */ 2417 u8 rsvd; 2418 __le16 rsvd2; 2419 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2420 __le32 fw_ver; 2421 __le32 feature; 2422 } __packed; 2423 2424 struct rtw89_btc_fbtc_btafh { 2425 u8 fver; /* btc_ver::fcxbtafh */ 2426 u8 rsvd; 2427 __le16 rsvd2; 2428 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2429 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2430 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2431 } __packed; 2432 2433 struct rtw89_btc_fbtc_btafh_v2 { 2434 u8 fver; /* btc_ver::fcxbtafh */ 2435 u8 rsvd; 2436 u8 rsvd2; 2437 u8 map_type; 2438 u8 afh_l[4]; 2439 u8 afh_m[4]; 2440 u8 afh_h[4]; 2441 u8 afh_le_a[4]; 2442 u8 afh_le_b[4]; 2443 } __packed; 2444 2445 struct rtw89_btc_fbtc_btdevinfo { 2446 u8 fver; /* btc_ver::fcxbtdevinfo */ 2447 u8 rsvd; 2448 __le16 vendor_id; 2449 __le32 dev_name; /* only 24 bits valid */ 2450 __le32 flush_time; 2451 } __packed; 2452 2453 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2454 struct rtw89_btc_rf_trx_para { 2455 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2456 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2457 u8 bt_tx_power; /* decrease Tx power (dB) */ 2458 u8 bt_rx_gain; /* LNA constrain level */ 2459 }; 2460 2461 struct rtw89_btc_trx_info { 2462 u8 tx_lvl; 2463 u8 rx_lvl; 2464 u8 wl_rssi; 2465 u8 bt_rssi; 2466 2467 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2468 s8 rx_gain; /* rx gain table index (TBD.) */ 2469 s8 bt_tx_power; /* decrease Tx power (dB) */ 2470 s8 bt_rx_gain; /* LNA constrain level */ 2471 2472 u8 cn; /* condition_num */ 2473 s8 nhm; 2474 u8 bt_profile; 2475 u8 rsvd2; 2476 2477 u16 tx_rate; 2478 u16 rx_rate; 2479 2480 u32 tx_tp; 2481 u32 rx_tp; 2482 u32 rx_err_ratio; 2483 }; 2484 2485 struct rtw89_btc_dm { 2486 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2487 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2488 struct rtw89_btc_fbtc_tdma tdma; 2489 struct rtw89_btc_fbtc_tdma tdma_now; 2490 struct rtw89_mac_ax_coex_gnt gnt; 2491 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2492 struct rtw89_btc_rf_trx_para rf_trx_para; 2493 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2494 struct rtw89_btc_dm_step dm_step; 2495 struct rtw89_btc_wl_scc_ctrl wl_scc; 2496 struct rtw89_btc_trx_info trx_info; 2497 union rtw89_btc_dm_error_map error; 2498 u32 cnt_dm[BTC_DCNT_NUM]; 2499 u32 cnt_notify[BTC_NCNT_NUM]; 2500 2501 u32 update_slot_map; 2502 u32 set_ant_path; 2503 2504 u32 wl_only: 1; 2505 u32 wl_fw_cx_offload: 1; 2506 u32 freerun: 1; 2507 u32 fddt_train: 1; 2508 u32 wl_ps_ctrl: 2; 2509 u32 wl_mimo_ps: 1; 2510 u32 leak_ap: 1; 2511 u32 noisy_level: 3; 2512 u32 coex_info_map: 8; 2513 u32 bt_only: 1; 2514 u32 wl_btg_rx: 1; 2515 u32 trx_para_level: 8; 2516 u32 wl_stb_chg: 1; 2517 u32 pta_owner: 1; 2518 u32 tdma_instant_excute: 1; 2519 2520 u16 slot_dur[CXST_MAX]; 2521 2522 u8 run_reason; 2523 u8 run_action; 2524 2525 u8 wl_lna2: 1; 2526 }; 2527 2528 struct rtw89_btc_ctrl { 2529 u32 manual: 1; 2530 u32 igno_bt: 1; 2531 u32 always_freerun: 1; 2532 u32 trace_step: 16; 2533 u32 rsvd: 12; 2534 }; 2535 2536 struct rtw89_btc_dbg { 2537 /* cmd "rb" */ 2538 bool rb_done; 2539 u32 rb_val; 2540 }; 2541 2542 enum rtw89_btc_btf_fw_event { 2543 BTF_EVNT_RPT = 0, 2544 BTF_EVNT_BT_INFO = 1, 2545 BTF_EVNT_BT_SCBD = 2, 2546 BTF_EVNT_BT_REG = 3, 2547 BTF_EVNT_CX_RUNINFO = 4, 2548 BTF_EVNT_BT_PSD = 5, 2549 BTF_EVNT_BUF_OVERFLOW, 2550 BTF_EVNT_C2H_LOOPBACK, 2551 BTF_EVNT_MAX, 2552 }; 2553 2554 enum btf_fw_event_report { 2555 BTC_RPT_TYPE_CTRL = 0x0, 2556 BTC_RPT_TYPE_TDMA, 2557 BTC_RPT_TYPE_SLOT, 2558 BTC_RPT_TYPE_CYSTA, 2559 BTC_RPT_TYPE_STEP, 2560 BTC_RPT_TYPE_NULLSTA, 2561 BTC_RPT_TYPE_MREG, 2562 BTC_RPT_TYPE_GPIO_DBG, 2563 BTC_RPT_TYPE_BT_VER, 2564 BTC_RPT_TYPE_BT_SCAN, 2565 BTC_RPT_TYPE_BT_AFH, 2566 BTC_RPT_TYPE_BT_DEVICE, 2567 BTC_RPT_TYPE_TEST, 2568 BTC_RPT_TYPE_MAX = 31 2569 }; 2570 2571 enum rtw_btc_btf_reg_type { 2572 REG_MAC = 0x0, 2573 REG_BB = 0x1, 2574 REG_RF = 0x2, 2575 REG_BT_RF = 0x3, 2576 REG_BT_MODEM = 0x4, 2577 REG_BT_BLUEWIZE = 0x5, 2578 REG_BT_VENDOR = 0x6, 2579 REG_BT_LE = 0x7, 2580 REG_MAX_TYPE, 2581 }; 2582 2583 struct rtw89_btc_rpt_cmn_info { 2584 u32 rx_cnt; 2585 u32 rx_len; 2586 u32 req_len; /* expected rsp len */ 2587 u8 req_fver; /* expected rsp fver */ 2588 u8 rsp_fver; /* fver from fw */ 2589 u8 valid; 2590 } __packed; 2591 2592 union rtw89_btc_fbtc_btafh_info { 2593 struct rtw89_btc_fbtc_btafh v1; 2594 struct rtw89_btc_fbtc_btafh_v2 v2; 2595 }; 2596 2597 struct rtw89_btc_report_ctrl_state { 2598 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2599 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2600 }; 2601 2602 struct rtw89_btc_rpt_fbtc_tdma { 2603 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2604 union rtw89_btc_fbtc_tdma_le32 finfo; 2605 }; 2606 2607 struct rtw89_btc_rpt_fbtc_slots { 2608 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2609 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2610 }; 2611 2612 struct rtw89_btc_rpt_fbtc_cysta { 2613 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2614 union rtw89_btc_fbtc_cysta_info finfo; 2615 }; 2616 2617 struct rtw89_btc_rpt_fbtc_step { 2618 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2619 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2620 }; 2621 2622 struct rtw89_btc_rpt_fbtc_nullsta { 2623 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2624 union rtw89_btc_fbtc_cynullsta_info finfo; 2625 }; 2626 2627 struct rtw89_btc_rpt_fbtc_mreg { 2628 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2629 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2630 }; 2631 2632 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2633 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2634 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2635 }; 2636 2637 struct rtw89_btc_rpt_fbtc_btver { 2638 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2639 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2640 }; 2641 2642 struct rtw89_btc_rpt_fbtc_btscan { 2643 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2644 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2645 }; 2646 2647 struct rtw89_btc_rpt_fbtc_btafh { 2648 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2649 union rtw89_btc_fbtc_btafh_info finfo; 2650 }; 2651 2652 struct rtw89_btc_rpt_fbtc_btdev { 2653 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2654 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2655 }; 2656 2657 enum rtw89_btc_btfre_type { 2658 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2659 BTFRE_UNDEF_TYPE, 2660 BTFRE_EXCEPTION, 2661 BTFRE_MAX, 2662 }; 2663 2664 struct rtw89_btc_btf_fwinfo { 2665 u32 cnt_c2h; 2666 u32 cnt_h2c; 2667 u32 cnt_h2c_fail; 2668 u32 event[BTF_EVNT_MAX]; 2669 2670 u32 err[BTFRE_MAX]; 2671 u32 len_mismch; 2672 u32 fver_mismch; 2673 u32 rpt_en_map; 2674 2675 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2676 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2677 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2678 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2679 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2680 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2681 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2682 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2683 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2684 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2685 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2686 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2687 }; 2688 2689 struct rtw89_btc_ver { 2690 enum rtw89_core_chip_id chip_id; 2691 u32 fw_ver_code; 2692 2693 u8 fcxbtcrpt; 2694 u8 fcxtdma; 2695 u8 fcxslots; 2696 u8 fcxcysta; 2697 u8 fcxstep; 2698 u8 fcxnullsta; 2699 u8 fcxmreg; 2700 u8 fcxgpiodbg; 2701 u8 fcxbtver; 2702 u8 fcxbtscan; 2703 u8 fcxbtafh; 2704 u8 fcxbtdevinfo; 2705 u8 fwlrole; 2706 u8 frptmap; 2707 u8 fcxctrl; 2708 2709 u16 info_buf; 2710 u8 max_role_num; 2711 }; 2712 2713 #define RTW89_BTC_POLICY_MAXLEN 512 2714 2715 struct rtw89_btc { 2716 const struct rtw89_btc_ver *ver; 2717 2718 struct rtw89_btc_cx cx; 2719 struct rtw89_btc_dm dm; 2720 struct rtw89_btc_ctrl ctrl; 2721 struct rtw89_btc_module mdinfo; 2722 struct rtw89_btc_btf_fwinfo fwinfo; 2723 struct rtw89_btc_dbg dbg; 2724 2725 struct work_struct eapol_notify_work; 2726 struct work_struct arp_notify_work; 2727 struct work_struct dhcp_notify_work; 2728 struct work_struct icmp_notify_work; 2729 2730 u32 bt_req_len; 2731 2732 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2733 u16 policy_len; 2734 u16 policy_type; 2735 bool bt_req_en; 2736 bool update_policy_force; 2737 bool lps; 2738 }; 2739 2740 enum rtw89_btc_hmsg { 2741 RTW89_BTC_HMSG_TMR_EN = 0x0, 2742 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 2743 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 2744 RTW89_BTC_HMSG_FW_EV = 0x3, 2745 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 2746 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 2747 2748 NUM_OF_RTW89_BTC_HMSG, 2749 }; 2750 2751 enum rtw89_ra_mode { 2752 RTW89_RA_MODE_CCK = BIT(0), 2753 RTW89_RA_MODE_OFDM = BIT(1), 2754 RTW89_RA_MODE_HT = BIT(2), 2755 RTW89_RA_MODE_VHT = BIT(3), 2756 RTW89_RA_MODE_HE = BIT(4), 2757 RTW89_RA_MODE_EHT = BIT(5), 2758 }; 2759 2760 enum rtw89_ra_report_mode { 2761 RTW89_RA_RPT_MODE_LEGACY, 2762 RTW89_RA_RPT_MODE_HT, 2763 RTW89_RA_RPT_MODE_VHT, 2764 RTW89_RA_RPT_MODE_HE, 2765 RTW89_RA_RPT_MODE_EHT, 2766 }; 2767 2768 enum rtw89_dig_noisy_level { 2769 RTW89_DIG_NOISY_LEVEL0 = -1, 2770 RTW89_DIG_NOISY_LEVEL1 = 0, 2771 RTW89_DIG_NOISY_LEVEL2 = 1, 2772 RTW89_DIG_NOISY_LEVEL3 = 2, 2773 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2774 }; 2775 2776 enum rtw89_gi_ltf { 2777 RTW89_GILTF_LGI_4XHE32 = 0, 2778 RTW89_GILTF_SGI_4XHE08 = 1, 2779 RTW89_GILTF_2XHE16 = 2, 2780 RTW89_GILTF_2XHE08 = 3, 2781 RTW89_GILTF_1XHE16 = 4, 2782 RTW89_GILTF_1XHE08 = 5, 2783 RTW89_GILTF_MAX 2784 }; 2785 2786 enum rtw89_rx_frame_type { 2787 RTW89_RX_TYPE_MGNT = 0, 2788 RTW89_RX_TYPE_CTRL = 1, 2789 RTW89_RX_TYPE_DATA = 2, 2790 RTW89_RX_TYPE_RSVD = 3, 2791 }; 2792 2793 enum rtw89_efuse_block { 2794 RTW89_EFUSE_BLOCK_SYS = 0, 2795 RTW89_EFUSE_BLOCK_RF = 1, 2796 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 2797 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 2798 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 2799 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 2800 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 2801 RTW89_EFUSE_BLOCK_ADIE = 7, 2802 2803 RTW89_EFUSE_BLOCK_NUM, 2804 RTW89_EFUSE_BLOCK_IGNORE, 2805 }; 2806 2807 struct rtw89_ra_info { 2808 u8 is_dis_ra:1; 2809 /* Bit0 : CCK 2810 * Bit1 : OFDM 2811 * Bit2 : HT 2812 * Bit3 : VHT 2813 * Bit4 : HE 2814 * Bit5 : EHT 2815 */ 2816 u8 mode_ctrl:6; 2817 u8 bw_cap:3; /* enum rtw89_bandwidth */ 2818 u8 macid; 2819 u8 dcm_cap:1; 2820 u8 er_cap:1; 2821 u8 init_rate_lv:2; 2822 u8 upd_all:1; 2823 u8 en_sgi:1; 2824 u8 ldpc_cap:1; 2825 u8 stbc_cap:1; 2826 u8 ss_num:3; 2827 u8 giltf:3; 2828 u8 upd_bw_nss_mask:1; 2829 u8 upd_mask:1; 2830 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2831 /* BFee CSI */ 2832 u8 band_num; 2833 u8 ra_csi_rate_en:1; 2834 u8 fixed_csi_rate_en:1; 2835 u8 cr_tbl_sel:1; 2836 u8 fix_giltf_en:1; 2837 u8 fix_giltf:3; 2838 u8 rsvd2:1; 2839 u8 csi_mcs_ss_idx; 2840 u8 csi_mode:2; 2841 u8 csi_gi_ltf:3; 2842 u8 csi_bw:3; 2843 }; 2844 2845 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2846 #define RTW89_PPDU_MAC_INFO_SIZE 8 2847 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2848 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 2849 2850 #define RTW89_MAX_RX_AGG_NUM 64 2851 #define RTW89_MAX_TX_AGG_NUM 128 2852 2853 struct rtw89_ampdu_params { 2854 u16 agg_num; 2855 bool amsdu; 2856 }; 2857 2858 struct rtw89_ra_report { 2859 struct rate_info txrate; 2860 u32 bit_rate; 2861 u16 hw_rate; 2862 bool might_fallback_legacy; 2863 }; 2864 2865 DECLARE_EWMA(rssi, 10, 16); 2866 DECLARE_EWMA(evm, 10, 16); 2867 DECLARE_EWMA(snr, 10, 16); 2868 2869 struct rtw89_ba_cam_entry { 2870 struct list_head list; 2871 u8 tid; 2872 }; 2873 2874 #define RTW89_MAX_ADDR_CAM_NUM 128 2875 #define RTW89_MAX_BSSID_CAM_NUM 20 2876 #define RTW89_MAX_SEC_CAM_NUM 128 2877 #define RTW89_MAX_BA_CAM_NUM 8 2878 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2879 2880 struct rtw89_addr_cam_entry { 2881 u8 addr_cam_idx; 2882 u8 offset; 2883 u8 len; 2884 u8 valid : 1; 2885 u8 addr_mask : 6; 2886 u8 wapi : 1; 2887 u8 mask_sel : 2; 2888 u8 bssid_cam_idx: 6; 2889 2890 u8 sec_ent_mode; 2891 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2892 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2893 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2894 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2895 }; 2896 2897 struct rtw89_bssid_cam_entry { 2898 u8 bssid[ETH_ALEN]; 2899 u8 phy_idx; 2900 u8 bssid_cam_idx; 2901 u8 offset; 2902 u8 len; 2903 u8 valid : 1; 2904 u8 num; 2905 }; 2906 2907 struct rtw89_sec_cam_entry { 2908 u8 sec_cam_idx; 2909 u8 offset; 2910 u8 len; 2911 u8 type : 4; 2912 u8 ext_key : 1; 2913 u8 spp_mode : 1; 2914 /* 256 bits */ 2915 u8 key[32]; 2916 }; 2917 2918 struct rtw89_sta { 2919 u8 mac_id; 2920 bool disassoc; 2921 bool er_cap; 2922 struct rtw89_dev *rtwdev; 2923 struct rtw89_vif *rtwvif; 2924 struct rtw89_ra_info ra; 2925 struct rtw89_ra_report ra_report; 2926 int max_agg_wait; 2927 u8 prev_rssi; 2928 struct ewma_rssi avg_rssi; 2929 struct ewma_rssi rssi[RF_PATH_MAX]; 2930 struct ewma_snr avg_snr; 2931 struct ewma_evm evm_min[RF_PATH_MAX]; 2932 struct ewma_evm evm_max[RF_PATH_MAX]; 2933 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2934 struct ieee80211_rx_status rx_status; 2935 u16 rx_hw_rate; 2936 __le32 htc_template; 2937 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2938 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2939 struct list_head ba_cam_list; 2940 struct sk_buff_head roc_queue; 2941 2942 bool use_cfg_mask; 2943 struct cfg80211_bitrate_mask mask; 2944 2945 bool cctl_tx_time; 2946 u32 ampdu_max_time:4; 2947 bool cctl_tx_retry_limit; 2948 u32 data_tx_cnt_lmt:6; 2949 }; 2950 2951 struct rtw89_efuse { 2952 bool valid; 2953 bool power_k_valid; 2954 u8 xtal_cap; 2955 u8 addr[ETH_ALEN]; 2956 u8 rfe_type; 2957 char country_code[2]; 2958 }; 2959 2960 struct rtw89_phy_rate_pattern { 2961 u64 ra_mask; 2962 u16 rate; 2963 u8 ra_mode; 2964 bool enable; 2965 }; 2966 2967 struct rtw89_tx_wait_info { 2968 struct rcu_head rcu_head; 2969 struct completion completion; 2970 bool tx_done; 2971 }; 2972 2973 struct rtw89_tx_skb_data { 2974 struct rtw89_tx_wait_info __rcu *wait; 2975 u8 hci_priv[]; 2976 }; 2977 2978 #define RTW89_ROC_IDLE_TIMEOUT 500 2979 #define RTW89_ROC_TX_TIMEOUT 30 2980 enum rtw89_roc_state { 2981 RTW89_ROC_IDLE, 2982 RTW89_ROC_NORMAL, 2983 RTW89_ROC_MGMT, 2984 }; 2985 2986 struct rtw89_roc { 2987 struct ieee80211_channel chan; 2988 struct delayed_work roc_work; 2989 enum ieee80211_roc_type type; 2990 enum rtw89_roc_state state; 2991 int duration; 2992 }; 2993 2994 #define RTW89_P2P_MAX_NOA_NUM 2 2995 2996 struct rtw89_p2p_ie_head { 2997 u8 eid; 2998 u8 ie_len; 2999 u8 oui[3]; 3000 u8 oui_type; 3001 } __packed; 3002 3003 struct rtw89_noa_attr_head { 3004 u8 attr_type; 3005 __le16 attr_len; 3006 u8 index; 3007 u8 oppps_ctwindow; 3008 } __packed; 3009 3010 struct rtw89_p2p_noa_ie { 3011 struct rtw89_p2p_ie_head p2p_head; 3012 struct rtw89_noa_attr_head noa_head; 3013 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3014 } __packed; 3015 3016 struct rtw89_p2p_noa_setter { 3017 struct rtw89_p2p_noa_ie ie; 3018 u8 noa_count; 3019 u8 noa_index; 3020 }; 3021 3022 struct rtw89_vif { 3023 struct list_head list; 3024 struct rtw89_dev *rtwdev; 3025 struct rtw89_roc roc; 3026 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3027 enum rtw89_sub_entity_idx sub_entity_idx; 3028 enum rtw89_reg_6ghz_power reg_6ghz_power; 3029 3030 u8 mac_id; 3031 u8 port; 3032 u8 mac_addr[ETH_ALEN]; 3033 u8 bssid[ETH_ALEN]; 3034 u8 phy_idx; 3035 u8 mac_idx; 3036 u8 net_type; 3037 u8 wifi_role; 3038 u8 self_role; 3039 u8 wmm; 3040 u8 bcn_hit_cond; 3041 u8 hit_rule; 3042 u8 last_noa_nr; 3043 bool offchan; 3044 bool trigger; 3045 bool lsig_txop; 3046 u8 tgt_ind; 3047 u8 frm_tgt_ind; 3048 bool wowlan_pattern; 3049 bool wowlan_uc; 3050 bool wowlan_magic; 3051 bool is_hesta; 3052 bool last_a_ctrl; 3053 bool dyn_tb_bedge_en; 3054 bool pre_pwr_diff_en; 3055 bool pwr_diff_en; 3056 u8 def_tri_idx; 3057 u32 tdls_peer; 3058 struct work_struct update_beacon_work; 3059 struct rtw89_addr_cam_entry addr_cam; 3060 struct rtw89_bssid_cam_entry bssid_cam; 3061 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3062 struct rtw89_traffic_stats stats; 3063 struct rtw89_phy_rate_pattern rate_pattern; 3064 struct cfg80211_scan_request *scan_req; 3065 struct ieee80211_scan_ies *scan_ies; 3066 struct list_head general_pkt_list; 3067 struct rtw89_p2p_noa_setter p2p_noa; 3068 }; 3069 3070 enum rtw89_lv1_rcvy_step { 3071 RTW89_LV1_RCVY_STEP_1, 3072 RTW89_LV1_RCVY_STEP_2, 3073 }; 3074 3075 struct rtw89_hci_ops { 3076 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3077 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3078 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3079 void (*reset)(struct rtw89_dev *rtwdev); 3080 int (*start)(struct rtw89_dev *rtwdev); 3081 void (*stop)(struct rtw89_dev *rtwdev); 3082 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3083 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3084 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3085 3086 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3087 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3088 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3089 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3090 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3091 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3092 3093 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3094 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3095 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3096 int (*deinit)(struct rtw89_dev *rtwdev); 3097 3098 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3099 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3100 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3101 int (*napi_poll)(struct napi_struct *napi, int budget); 3102 3103 /* Deal with locks inside recovery_start and recovery_complete callbacks 3104 * by hci instance, and handle things which need to consider under SER. 3105 * e.g. turn on/off interrupts except for the one for halt notification. 3106 */ 3107 void (*recovery_start)(struct rtw89_dev *rtwdev); 3108 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3109 3110 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3111 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3112 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3113 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 3114 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3115 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3116 void (*disable_intr)(struct rtw89_dev *rtwdev); 3117 void (*enable_intr)(struct rtw89_dev *rtwdev); 3118 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3119 }; 3120 3121 struct rtw89_hci_info { 3122 const struct rtw89_hci_ops *ops; 3123 enum rtw89_hci_type type; 3124 u32 rpwm_addr; 3125 u32 cpwm_addr; 3126 bool paused; 3127 }; 3128 3129 struct rtw89_chip_ops { 3130 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3131 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3132 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3133 void (*bb_reset)(struct rtw89_dev *rtwdev, 3134 enum rtw89_phy_idx phy_idx); 3135 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3136 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3137 u32 addr, u32 mask); 3138 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3139 u32 addr, u32 mask, u32 data); 3140 void (*set_channel)(struct rtw89_dev *rtwdev, 3141 const struct rtw89_chan *chan, 3142 enum rtw89_mac_idx mac_idx, 3143 enum rtw89_phy_idx phy_idx); 3144 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3145 struct rtw89_channel_help_params *p, 3146 const struct rtw89_chan *chan, 3147 enum rtw89_mac_idx mac_idx, 3148 enum rtw89_phy_idx phy_idx); 3149 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3150 enum rtw89_efuse_block block); 3151 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3152 void (*fem_setup)(struct rtw89_dev *rtwdev); 3153 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3154 void (*rfk_init)(struct rtw89_dev *rtwdev); 3155 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3156 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3157 enum rtw89_phy_idx phy_idx); 3158 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3159 void (*rfk_track)(struct rtw89_dev *rtwdev); 3160 void (*power_trim)(struct rtw89_dev *rtwdev); 3161 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3162 const struct rtw89_chan *chan, 3163 enum rtw89_phy_idx phy_idx); 3164 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3165 enum rtw89_phy_idx phy_idx); 3166 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3167 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3168 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3169 enum rtw89_phy_idx phy_idx); 3170 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3171 struct rtw89_rx_phy_ppdu *phy_ppdu, 3172 struct ieee80211_rx_status *status); 3173 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3174 enum rtw89_phy_idx phy_idx); 3175 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3176 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3177 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3178 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3179 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3180 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3181 struct rtw89_rx_desc_info *desc_info, 3182 u8 *data, u32 data_offset); 3183 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3184 struct rtw89_tx_desc_info *desc_info, 3185 void *txdesc); 3186 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3187 struct rtw89_tx_desc_info *desc_info, 3188 void *txdesc); 3189 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3190 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3191 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3192 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3193 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3194 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3195 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3196 struct rtw89_vif *rtwvif, 3197 struct rtw89_sta *rtwsta); 3198 3199 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3200 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3201 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3202 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3203 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3204 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3205 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3206 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3207 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3208 }; 3209 3210 enum rtw89_dma_ch { 3211 RTW89_DMA_ACH0 = 0, 3212 RTW89_DMA_ACH1 = 1, 3213 RTW89_DMA_ACH2 = 2, 3214 RTW89_DMA_ACH3 = 3, 3215 RTW89_DMA_ACH4 = 4, 3216 RTW89_DMA_ACH5 = 5, 3217 RTW89_DMA_ACH6 = 6, 3218 RTW89_DMA_ACH7 = 7, 3219 RTW89_DMA_B0MG = 8, 3220 RTW89_DMA_B0HI = 9, 3221 RTW89_DMA_B1MG = 10, 3222 RTW89_DMA_B1HI = 11, 3223 RTW89_DMA_H2C = 12, 3224 RTW89_DMA_CH_NUM = 13 3225 }; 3226 3227 enum rtw89_qta_mode { 3228 RTW89_QTA_SCC, 3229 RTW89_QTA_DLFW, 3230 RTW89_QTA_WOW, 3231 3232 /* keep last */ 3233 RTW89_QTA_INVALID, 3234 }; 3235 3236 struct rtw89_hfc_ch_cfg { 3237 u16 min; 3238 u16 max; 3239 #define grp_0 0 3240 #define grp_1 1 3241 #define grp_num 2 3242 u8 grp; 3243 }; 3244 3245 struct rtw89_hfc_ch_info { 3246 u16 aval; 3247 u16 used; 3248 }; 3249 3250 struct rtw89_hfc_pub_cfg { 3251 u16 grp0; 3252 u16 grp1; 3253 u16 pub_max; 3254 u16 wp_thrd; 3255 }; 3256 3257 struct rtw89_hfc_pub_info { 3258 u16 g0_used; 3259 u16 g1_used; 3260 u16 g0_aval; 3261 u16 g1_aval; 3262 u16 pub_aval; 3263 u16 wp_aval; 3264 }; 3265 3266 struct rtw89_hfc_prec_cfg { 3267 u16 ch011_prec; 3268 u16 h2c_prec; 3269 u16 wp_ch07_prec; 3270 u16 wp_ch811_prec; 3271 u8 ch011_full_cond; 3272 u8 h2c_full_cond; 3273 u8 wp_ch07_full_cond; 3274 u8 wp_ch811_full_cond; 3275 }; 3276 3277 struct rtw89_hfc_param { 3278 bool en; 3279 bool h2c_en; 3280 u8 mode; 3281 const struct rtw89_hfc_ch_cfg *ch_cfg; 3282 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3283 struct rtw89_hfc_pub_cfg pub_cfg; 3284 struct rtw89_hfc_pub_info pub_info; 3285 struct rtw89_hfc_prec_cfg prec_cfg; 3286 }; 3287 3288 struct rtw89_hfc_param_ini { 3289 const struct rtw89_hfc_ch_cfg *ch_cfg; 3290 const struct rtw89_hfc_pub_cfg *pub_cfg; 3291 const struct rtw89_hfc_prec_cfg *prec_cfg; 3292 u8 mode; 3293 }; 3294 3295 struct rtw89_dle_size { 3296 u16 pge_size; 3297 u16 lnk_pge_num; 3298 u16 unlnk_pge_num; 3299 /* for WiFi 7 chips below */ 3300 u32 srt_ofst; 3301 }; 3302 3303 struct rtw89_wde_quota { 3304 u16 hif; 3305 u16 wcpu; 3306 u16 pkt_in; 3307 u16 cpu_io; 3308 }; 3309 3310 struct rtw89_ple_quota { 3311 u16 cma0_tx; 3312 u16 cma1_tx; 3313 u16 c2h; 3314 u16 h2c; 3315 u16 wcpu; 3316 u16 mpdu_proc; 3317 u16 cma0_dma; 3318 u16 cma1_dma; 3319 u16 bb_rpt; 3320 u16 wd_rel; 3321 u16 cpu_io; 3322 u16 tx_rpt; 3323 /* for WiFi 7 chips below */ 3324 u16 h2d; 3325 }; 3326 3327 struct rtw89_rsvd_quota { 3328 u16 mpdu_info_tbl; 3329 u16 b0_csi; 3330 u16 b1_csi; 3331 u16 b0_lmr; 3332 u16 b1_lmr; 3333 u16 b0_ftm; 3334 u16 b1_ftm; 3335 u16 b0_smr; 3336 u16 b1_smr; 3337 u16 others; 3338 }; 3339 3340 struct rtw89_dle_rsvd_size { 3341 u32 srt_ofst; 3342 u32 size; 3343 }; 3344 3345 struct rtw89_dle_mem { 3346 enum rtw89_qta_mode mode; 3347 const struct rtw89_dle_size *wde_size; 3348 const struct rtw89_dle_size *ple_size; 3349 const struct rtw89_wde_quota *wde_min_qt; 3350 const struct rtw89_wde_quota *wde_max_qt; 3351 const struct rtw89_ple_quota *ple_min_qt; 3352 const struct rtw89_ple_quota *ple_max_qt; 3353 /* for WiFi 7 chips below */ 3354 const struct rtw89_rsvd_quota *rsvd_qt; 3355 const struct rtw89_dle_rsvd_size *rsvd0_size; 3356 const struct rtw89_dle_rsvd_size *rsvd1_size; 3357 }; 3358 3359 struct rtw89_reg_def { 3360 u32 addr; 3361 u32 mask; 3362 }; 3363 3364 struct rtw89_reg2_def { 3365 u32 addr; 3366 u32 data; 3367 }; 3368 3369 struct rtw89_reg3_def { 3370 u32 addr; 3371 u32 mask; 3372 u32 data; 3373 }; 3374 3375 struct rtw89_reg5_def { 3376 u8 flag; /* recognized by parsers */ 3377 u8 path; 3378 u32 addr; 3379 u32 mask; 3380 u32 data; 3381 }; 3382 3383 struct rtw89_reg_imr { 3384 u32 addr; 3385 u32 clr; 3386 u32 set; 3387 }; 3388 3389 struct rtw89_phy_table { 3390 const struct rtw89_reg2_def *regs; 3391 u32 n_regs; 3392 enum rtw89_rf_path rf_path; 3393 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3394 enum rtw89_rf_path rf_path, void *data); 3395 }; 3396 3397 struct rtw89_txpwr_table { 3398 const void *data; 3399 u32 size; 3400 void (*load)(struct rtw89_dev *rtwdev, 3401 const struct rtw89_txpwr_table *tbl); 3402 }; 3403 3404 struct rtw89_txpwr_rule_2ghz { 3405 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3406 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3407 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3408 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3409 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3410 }; 3411 3412 struct rtw89_txpwr_rule_5ghz { 3413 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3414 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3415 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3416 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3417 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3418 }; 3419 3420 struct rtw89_txpwr_rule_6ghz { 3421 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3422 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3423 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3424 [RTW89_6G_CH_NUM]; 3425 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3426 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3427 [RTW89_6G_CH_NUM]; 3428 }; 3429 3430 struct rtw89_tx_shape { 3431 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3432 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3433 }; 3434 3435 struct rtw89_rfe_parms { 3436 const struct rtw89_txpwr_table *byr_tbl; 3437 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3438 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3439 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3440 struct rtw89_tx_shape tx_shape; 3441 }; 3442 3443 struct rtw89_rfe_parms_conf { 3444 const struct rtw89_rfe_parms *rfe_parms; 3445 u8 rfe_type; 3446 }; 3447 3448 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3449 3450 struct rtw89_txpwr_conf { 3451 u8 rfe_type; 3452 u8 ent_sz; 3453 u32 num_ents; 3454 const void *data; 3455 }; 3456 3457 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3458 3459 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3460 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3461 memcpy(&(entry), cursor, \ 3462 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3463 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3464 (cursor) += (conf)->ent_sz, \ 3465 memcpy(&(entry), cursor, \ 3466 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3467 3468 struct rtw89_txpwr_byrate_data { 3469 struct rtw89_txpwr_conf conf; 3470 struct rtw89_txpwr_table tbl; 3471 }; 3472 3473 struct rtw89_txpwr_lmt_2ghz_data { 3474 struct rtw89_txpwr_conf conf; 3475 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3476 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3477 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3478 }; 3479 3480 struct rtw89_txpwr_lmt_5ghz_data { 3481 struct rtw89_txpwr_conf conf; 3482 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3483 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3484 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3485 }; 3486 3487 struct rtw89_txpwr_lmt_6ghz_data { 3488 struct rtw89_txpwr_conf conf; 3489 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3490 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3491 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3492 [RTW89_6G_CH_NUM]; 3493 }; 3494 3495 struct rtw89_txpwr_lmt_ru_2ghz_data { 3496 struct rtw89_txpwr_conf conf; 3497 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3498 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3499 }; 3500 3501 struct rtw89_txpwr_lmt_ru_5ghz_data { 3502 struct rtw89_txpwr_conf conf; 3503 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3504 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3505 }; 3506 3507 struct rtw89_txpwr_lmt_ru_6ghz_data { 3508 struct rtw89_txpwr_conf conf; 3509 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3510 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3511 [RTW89_6G_CH_NUM]; 3512 }; 3513 3514 struct rtw89_tx_shape_lmt_data { 3515 struct rtw89_txpwr_conf conf; 3516 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3517 }; 3518 3519 struct rtw89_tx_shape_lmt_ru_data { 3520 struct rtw89_txpwr_conf conf; 3521 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3522 }; 3523 3524 struct rtw89_rfe_data { 3525 struct rtw89_txpwr_byrate_data byrate; 3526 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3527 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3528 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3529 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3530 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3531 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3532 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3533 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3534 struct rtw89_rfe_parms rfe_parms; 3535 }; 3536 3537 struct rtw89_page_regs { 3538 u32 hci_fc_ctrl; 3539 u32 ch_page_ctrl; 3540 u32 ach_page_ctrl; 3541 u32 ach_page_info; 3542 u32 pub_page_info3; 3543 u32 pub_page_ctrl1; 3544 u32 pub_page_ctrl2; 3545 u32 pub_page_info1; 3546 u32 pub_page_info2; 3547 u32 wp_page_ctrl1; 3548 u32 wp_page_ctrl2; 3549 u32 wp_page_info1; 3550 }; 3551 3552 struct rtw89_imr_info { 3553 u32 wdrls_imr_set; 3554 u32 wsec_imr_reg; 3555 u32 wsec_imr_set; 3556 u32 mpdu_tx_imr_set; 3557 u32 mpdu_rx_imr_set; 3558 u32 sta_sch_imr_set; 3559 u32 txpktctl_imr_b0_reg; 3560 u32 txpktctl_imr_b0_clr; 3561 u32 txpktctl_imr_b0_set; 3562 u32 txpktctl_imr_b1_reg; 3563 u32 txpktctl_imr_b1_clr; 3564 u32 txpktctl_imr_b1_set; 3565 u32 wde_imr_clr; 3566 u32 wde_imr_set; 3567 u32 ple_imr_clr; 3568 u32 ple_imr_set; 3569 u32 host_disp_imr_clr; 3570 u32 host_disp_imr_set; 3571 u32 cpu_disp_imr_clr; 3572 u32 cpu_disp_imr_set; 3573 u32 other_disp_imr_clr; 3574 u32 other_disp_imr_set; 3575 u32 bbrpt_com_err_imr_reg; 3576 u32 bbrpt_chinfo_err_imr_reg; 3577 u32 bbrpt_err_imr_set; 3578 u32 bbrpt_dfs_err_imr_reg; 3579 u32 ptcl_imr_clr; 3580 u32 ptcl_imr_set; 3581 u32 cdma_imr_0_reg; 3582 u32 cdma_imr_0_clr; 3583 u32 cdma_imr_0_set; 3584 u32 cdma_imr_1_reg; 3585 u32 cdma_imr_1_clr; 3586 u32 cdma_imr_1_set; 3587 u32 phy_intf_imr_reg; 3588 u32 phy_intf_imr_clr; 3589 u32 phy_intf_imr_set; 3590 u32 rmac_imr_reg; 3591 u32 rmac_imr_clr; 3592 u32 rmac_imr_set; 3593 u32 tmac_imr_reg; 3594 u32 tmac_imr_clr; 3595 u32 tmac_imr_set; 3596 }; 3597 3598 struct rtw89_imr_table { 3599 const struct rtw89_reg_imr *regs; 3600 u32 n_regs; 3601 }; 3602 3603 struct rtw89_xtal_info { 3604 u32 xcap_reg; 3605 u32 sc_xo_mask; 3606 u32 sc_xi_mask; 3607 }; 3608 3609 struct rtw89_rrsr_cfgs { 3610 struct rtw89_reg3_def ref_rate; 3611 struct rtw89_reg3_def rsc; 3612 }; 3613 3614 struct rtw89_dig_regs { 3615 u32 seg0_pd_reg; 3616 u32 pd_lower_bound_mask; 3617 u32 pd_spatial_reuse_en; 3618 u32 bmode_pd_reg; 3619 u32 bmode_cca_rssi_limit_en; 3620 u32 bmode_pd_lower_bound_reg; 3621 u32 bmode_rssi_nocca_low_th_mask; 3622 struct rtw89_reg_def p0_lna_init; 3623 struct rtw89_reg_def p1_lna_init; 3624 struct rtw89_reg_def p0_tia_init; 3625 struct rtw89_reg_def p1_tia_init; 3626 struct rtw89_reg_def p0_rxb_init; 3627 struct rtw89_reg_def p1_rxb_init; 3628 struct rtw89_reg_def p0_p20_pagcugc_en; 3629 struct rtw89_reg_def p0_s20_pagcugc_en; 3630 struct rtw89_reg_def p1_p20_pagcugc_en; 3631 struct rtw89_reg_def p1_s20_pagcugc_en; 3632 }; 3633 3634 struct rtw89_edcca_regs { 3635 u32 edcca_level; 3636 u32 edcca_mask; 3637 u32 edcca_p_mask; 3638 u32 ppdu_level; 3639 u32 ppdu_mask; 3640 u32 rpt_a; 3641 u32 rpt_b; 3642 u32 rpt_sel; 3643 u32 rpt_sel_mask; 3644 u32 rpt_sel_be; 3645 u32 rpt_sel_be_mask; 3646 u32 tx_collision_t2r_st; 3647 u32 tx_collision_t2r_st_mask; 3648 }; 3649 3650 struct rtw89_phy_ul_tb_info { 3651 bool dyn_tb_tri_en; 3652 u8 def_if_bandedge; 3653 }; 3654 3655 struct rtw89_antdiv_stats { 3656 struct ewma_rssi cck_rssi_avg; 3657 struct ewma_rssi ofdm_rssi_avg; 3658 struct ewma_rssi non_legacy_rssi_avg; 3659 u16 pkt_cnt_cck; 3660 u16 pkt_cnt_ofdm; 3661 u16 pkt_cnt_non_legacy; 3662 u32 evm; 3663 }; 3664 3665 struct rtw89_antdiv_info { 3666 struct rtw89_antdiv_stats target_stats; 3667 struct rtw89_antdiv_stats main_stats; 3668 struct rtw89_antdiv_stats aux_stats; 3669 u8 training_count; 3670 u8 rssi_pre; 3671 bool get_stats; 3672 }; 3673 3674 enum rtw89_chanctx_state { 3675 RTW89_CHANCTX_STATE_MCC_START, 3676 RTW89_CHANCTX_STATE_MCC_STOP, 3677 }; 3678 3679 enum rtw89_chanctx_callbacks { 3680 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 3681 RTW89_CHANCTX_CALLBACK_RFK, 3682 3683 NUM_OF_RTW89_CHANCTX_CALLBACKS, 3684 }; 3685 3686 struct rtw89_chanctx_listener { 3687 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 3688 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 3689 }; 3690 3691 struct rtw89_chip_info { 3692 enum rtw89_core_chip_id chip_id; 3693 enum rtw89_chip_gen chip_gen; 3694 const struct rtw89_chip_ops *ops; 3695 const struct rtw89_mac_gen_def *mac_def; 3696 const struct rtw89_phy_gen_def *phy_def; 3697 const char *fw_basename; 3698 u8 fw_format_max; 3699 bool try_ce_fw; 3700 u8 bbmcu_nr; 3701 u32 needed_fw_elms; 3702 u32 fifo_size; 3703 bool small_fifo_size; 3704 u32 dle_scc_rsvd_size; 3705 u16 max_amsdu_limit; 3706 bool dis_2g_40m_ul_ofdma; 3707 u32 rsvd_ple_ofst; 3708 const struct rtw89_hfc_param_ini *hfc_param_ini; 3709 const struct rtw89_dle_mem *dle_mem; 3710 u8 wde_qempty_acq_grpnum; 3711 u8 wde_qempty_mgq_grpsel; 3712 u32 rf_base_addr[2]; 3713 u8 support_chanctx_num; 3714 u8 support_bands; 3715 bool support_bw160; 3716 bool support_unii4; 3717 bool ul_tb_waveform_ctrl; 3718 bool ul_tb_pwr_diff; 3719 bool hw_sec_hdr; 3720 u8 rf_path_num; 3721 u8 tx_nss; 3722 u8 rx_nss; 3723 u8 acam_num; 3724 u8 bcam_num; 3725 u8 scam_num; 3726 u8 bacam_num; 3727 u8 bacam_dynamic_num; 3728 enum rtw89_bacam_ver bacam_ver; 3729 u8 ppdu_max_usr; 3730 3731 u8 sec_ctrl_efuse_size; 3732 u32 physical_efuse_size; 3733 u32 logical_efuse_size; 3734 u32 limit_efuse_size; 3735 u32 dav_phy_efuse_size; 3736 u32 dav_log_efuse_size; 3737 u32 phycap_addr; 3738 u32 phycap_size; 3739 const struct rtw89_efuse_block_cfg *efuse_blocks; 3740 3741 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3742 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3743 const struct rtw89_phy_table *bb_table; 3744 const struct rtw89_phy_table *bb_gain_table; 3745 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3746 const struct rtw89_phy_table *nctl_table; 3747 const struct rtw89_rfk_tbl *nctl_post_table; 3748 const struct rtw89_phy_dig_gain_table *dig_table; 3749 const struct rtw89_dig_regs *dig_regs; 3750 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3751 3752 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3753 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3754 const struct rtw89_rfe_parms *dflt_parms; 3755 const struct rtw89_chanctx_listener *chanctx_listener; 3756 3757 u8 txpwr_factor_rf; 3758 u8 txpwr_factor_mac; 3759 3760 u32 para_ver; 3761 u32 wlcx_desired; 3762 u8 btcx_desired; 3763 u8 scbd; 3764 u8 mailbox; 3765 3766 u8 afh_guard_ch; 3767 const u8 *wl_rssi_thres; 3768 const u8 *bt_rssi_thres; 3769 u8 rssi_tol; 3770 3771 u8 mon_reg_num; 3772 const struct rtw89_btc_fbtc_mreg *mon_reg; 3773 u8 rf_para_ulink_num; 3774 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3775 u8 rf_para_dlink_num; 3776 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3777 u8 ps_mode_supported; 3778 u8 low_power_hci_modes; 3779 3780 u32 h2c_cctl_func_id; 3781 u32 hci_func_en_addr; 3782 u32 h2c_desc_size; 3783 u32 txwd_body_size; 3784 u32 txwd_info_size; 3785 u32 h2c_ctrl_reg; 3786 const u32 *h2c_regs; 3787 struct rtw89_reg_def h2c_counter_reg; 3788 u32 c2h_ctrl_reg; 3789 const u32 *c2h_regs; 3790 struct rtw89_reg_def c2h_counter_reg; 3791 const struct rtw89_page_regs *page_regs; 3792 bool cfo_src_fd; 3793 bool cfo_hw_comp; 3794 const struct rtw89_reg_def *dcfo_comp; 3795 u8 dcfo_comp_sft; 3796 const struct rtw89_imr_info *imr_info; 3797 const struct rtw89_imr_table *imr_dmac_table; 3798 const struct rtw89_imr_table *imr_cmac_table; 3799 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3800 struct rtw89_reg_def bss_clr_vld; 3801 u32 bss_clr_map_reg; 3802 u32 dma_ch_mask; 3803 const struct rtw89_edcca_regs *edcca_regs; 3804 const struct wiphy_wowlan_support *wowlan_stub; 3805 const struct rtw89_xtal_info *xtal_info; 3806 }; 3807 3808 union rtw89_bus_info { 3809 const struct rtw89_pci_info *pci; 3810 }; 3811 3812 struct rtw89_driver_info { 3813 const struct rtw89_chip_info *chip; 3814 union rtw89_bus_info bus; 3815 }; 3816 3817 enum rtw89_hcifc_mode { 3818 RTW89_HCIFC_POH = 0, 3819 RTW89_HCIFC_STF = 1, 3820 RTW89_HCIFC_SDIO = 2, 3821 3822 /* keep last */ 3823 RTW89_HCIFC_MODE_INVALID, 3824 }; 3825 3826 struct rtw89_dle_info { 3827 const struct rtw89_rsvd_quota *rsvd_qt; 3828 enum rtw89_qta_mode qta_mode; 3829 u16 ple_pg_size; 3830 u16 ple_free_pg; 3831 u16 c0_rx_qta; 3832 u16 c1_rx_qta; 3833 }; 3834 3835 enum rtw89_host_rpr_mode { 3836 RTW89_RPR_MODE_POH = 0, 3837 RTW89_RPR_MODE_STF 3838 }; 3839 3840 #define RTW89_COMPLETION_BUF_SIZE 24 3841 #define RTW89_WAIT_COND_IDLE UINT_MAX 3842 3843 struct rtw89_completion_data { 3844 bool err; 3845 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3846 }; 3847 3848 struct rtw89_wait_info { 3849 atomic_t cond; 3850 struct completion completion; 3851 struct rtw89_completion_data data; 3852 }; 3853 3854 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3855 3856 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3857 { 3858 init_completion(&wait->completion); 3859 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3860 } 3861 3862 struct rtw89_mac_info { 3863 struct rtw89_dle_info dle_info; 3864 struct rtw89_hfc_param hfc_param; 3865 enum rtw89_qta_mode qta_mode; 3866 u8 rpwm_seq_num; 3867 u8 cpwm_seq_num; 3868 3869 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 3870 struct rtw89_wait_info fw_ofld_wait; 3871 }; 3872 3873 enum rtw89_fwdl_check_type { 3874 RTW89_FWDL_CHECK_FREERTOS_DONE, 3875 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 3876 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 3877 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 3878 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 3879 }; 3880 3881 enum rtw89_fw_type { 3882 RTW89_FW_NORMAL = 1, 3883 RTW89_FW_WOWLAN = 3, 3884 RTW89_FW_NORMAL_CE = 5, 3885 RTW89_FW_BBMCU0 = 64, 3886 RTW89_FW_BBMCU1 = 65, 3887 RTW89_FW_LOGFMT = 255, 3888 }; 3889 3890 enum rtw89_fw_feature { 3891 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3892 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3893 RTW89_FW_FEATURE_TX_WAKE, 3894 RTW89_FW_FEATURE_CRASH_TRIGGER, 3895 RTW89_FW_FEATURE_NO_PACKET_DROP, 3896 RTW89_FW_FEATURE_NO_DEEP_PS, 3897 RTW89_FW_FEATURE_NO_LPS_PG, 3898 RTW89_FW_FEATURE_BEACON_FILTER, 3899 }; 3900 3901 struct rtw89_fw_suit { 3902 enum rtw89_fw_type type; 3903 const u8 *data; 3904 u32 size; 3905 u8 major_ver; 3906 u8 minor_ver; 3907 u8 sub_ver; 3908 u8 sub_idex; 3909 u16 build_year; 3910 u16 build_mon; 3911 u16 build_date; 3912 u16 build_hour; 3913 u16 build_min; 3914 u8 cmd_ver; 3915 u8 hdr_ver; 3916 u32 commitid; 3917 }; 3918 3919 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3920 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3921 #define RTW89_FW_SUIT_VER_CODE(s) \ 3922 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3923 3924 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3925 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3926 (mfw_hdr)->ver.minor, \ 3927 (mfw_hdr)->ver.sub, \ 3928 (mfw_hdr)->ver.idx) 3929 3930 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3931 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 3932 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 3933 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 3934 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 3935 3936 struct rtw89_fw_req_info { 3937 const struct firmware *firmware; 3938 struct completion completion; 3939 }; 3940 3941 struct rtw89_fw_log { 3942 struct rtw89_fw_suit suit; 3943 bool enable; 3944 u32 last_fmt_id; 3945 u32 fmt_count; 3946 const __le32 *fmt_ids; 3947 const char *(*fmts)[]; 3948 }; 3949 3950 struct rtw89_fw_elm_info { 3951 struct rtw89_phy_table *bb_tbl; 3952 struct rtw89_phy_table *bb_gain; 3953 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 3954 struct rtw89_phy_table *rf_nctl; 3955 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 3956 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 3957 }; 3958 3959 struct rtw89_fw_info { 3960 struct rtw89_fw_req_info req; 3961 int fw_format; 3962 u8 h2c_seq; 3963 u8 rec_seq; 3964 u8 h2c_counter; 3965 u8 c2h_counter; 3966 struct rtw89_fw_suit normal; 3967 struct rtw89_fw_suit wowlan; 3968 struct rtw89_fw_suit bbmcu0; 3969 struct rtw89_fw_suit bbmcu1; 3970 struct rtw89_fw_log log; 3971 u32 feature_map; 3972 struct rtw89_fw_elm_info elm_info; 3973 }; 3974 3975 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3976 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3977 3978 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3979 ((_fw)->feature_map |= BIT(_fw_feature)) 3980 3981 struct rtw89_cam_info { 3982 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3983 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3984 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3985 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3986 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3987 }; 3988 3989 enum rtw89_sar_sources { 3990 RTW89_SAR_SOURCE_NONE, 3991 RTW89_SAR_SOURCE_COMMON, 3992 3993 RTW89_SAR_SOURCE_NR, 3994 }; 3995 3996 enum rtw89_sar_subband { 3997 RTW89_SAR_2GHZ_SUBBAND, 3998 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3999 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4000 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4001 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4002 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4003 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4004 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4005 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4006 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4007 4008 RTW89_SAR_SUBBAND_NR, 4009 }; 4010 4011 struct rtw89_sar_cfg_common { 4012 bool set[RTW89_SAR_SUBBAND_NR]; 4013 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4014 }; 4015 4016 struct rtw89_sar_info { 4017 /* used to decide how to acces SAR cfg union */ 4018 enum rtw89_sar_sources src; 4019 4020 /* reserved for different knids of SAR cfg struct. 4021 * supposed that a single cfg struct cannot handle various SAR sources. 4022 */ 4023 union { 4024 struct rtw89_sar_cfg_common cfg_common; 4025 }; 4026 }; 4027 4028 enum rtw89_tas_state { 4029 RTW89_TAS_STATE_DPR_OFF, 4030 RTW89_TAS_STATE_DPR_ON, 4031 RTW89_TAS_STATE_DPR_FORBID, 4032 }; 4033 4034 #define RTW89_TAS_MAX_WINDOW 50 4035 struct rtw89_tas_info { 4036 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4037 s32 total_txpwr; 4038 u8 cur_idx; 4039 s8 dpr_gap; 4040 s8 delta; 4041 enum rtw89_tas_state state; 4042 bool enable; 4043 }; 4044 4045 struct rtw89_chanctx_cfg { 4046 enum rtw89_sub_entity_idx idx; 4047 }; 4048 4049 enum rtw89_chanctx_changes { 4050 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4051 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4052 RTW89_CHANCTX_P2P_PS_CHANGE, 4053 RTW89_CHANCTX_BT_SLOT_CHANGE, 4054 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4055 4056 NUM_OF_RTW89_CHANCTX_CHANGES, 4057 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4058 }; 4059 4060 enum rtw89_entity_mode { 4061 RTW89_ENTITY_MODE_SCC, 4062 RTW89_ENTITY_MODE_MCC_PREPARE, 4063 RTW89_ENTITY_MODE_MCC, 4064 4065 NUM_OF_RTW89_ENTITY_MODE, 4066 RTW89_ENTITY_MODE_INVALID = NUM_OF_RTW89_ENTITY_MODE, 4067 }; 4068 4069 struct rtw89_sub_entity { 4070 struct cfg80211_chan_def chandef; 4071 struct rtw89_chan chan; 4072 struct rtw89_chan_rcd rcd; 4073 struct rtw89_chanctx_cfg *cfg; 4074 }; 4075 4076 struct rtw89_edcca_bak { 4077 u8 a; 4078 u8 p; 4079 u8 ppdu; 4080 u8 th_old; 4081 }; 4082 4083 enum rtw89_dm_type { 4084 RTW89_DM_DYNAMIC_EDCCA, 4085 }; 4086 4087 struct rtw89_hal { 4088 u32 rx_fltr; 4089 u8 cv; 4090 u8 acv; 4091 u32 antenna_tx; 4092 u32 antenna_rx; 4093 u8 tx_nss; 4094 u8 rx_nss; 4095 bool tx_path_diversity; 4096 bool ant_diversity; 4097 bool ant_diversity_fixed; 4098 bool support_cckpd; 4099 bool support_igi; 4100 atomic_t roc_entity_idx; 4101 4102 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4103 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4104 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4105 struct cfg80211_chan_def roc_chandef; 4106 4107 bool entity_active; 4108 bool entity_pause; 4109 enum rtw89_entity_mode entity_mode; 4110 4111 struct rtw89_edcca_bak edcca_bak; 4112 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4113 }; 4114 4115 #define RTW89_MAX_MAC_ID_NUM 128 4116 #define RTW89_MAX_PKT_OFLD_NUM 255 4117 4118 enum rtw89_flags { 4119 RTW89_FLAG_POWERON, 4120 RTW89_FLAG_DMAC_FUNC, 4121 RTW89_FLAG_CMAC0_FUNC, 4122 RTW89_FLAG_CMAC1_FUNC, 4123 RTW89_FLAG_FW_RDY, 4124 RTW89_FLAG_RUNNING, 4125 RTW89_FLAG_BFEE_MON, 4126 RTW89_FLAG_BFEE_EN, 4127 RTW89_FLAG_BFEE_TIMER_KEEP, 4128 RTW89_FLAG_NAPI_RUNNING, 4129 RTW89_FLAG_LEISURE_PS, 4130 RTW89_FLAG_LOW_POWER_MODE, 4131 RTW89_FLAG_INACTIVE_PS, 4132 RTW89_FLAG_CRASH_SIMULATING, 4133 RTW89_FLAG_SER_HANDLING, 4134 RTW89_FLAG_WOWLAN, 4135 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4136 RTW89_FLAG_CHANGING_INTERFACE, 4137 4138 NUM_OF_RTW89_FLAGS, 4139 }; 4140 4141 enum rtw89_pkt_drop_sel { 4142 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4143 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4144 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4145 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4146 RTW89_PKT_DROP_SEL_MACID_ALL, 4147 RTW89_PKT_DROP_SEL_MG0_ONCE, 4148 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4149 RTW89_PKT_DROP_SEL_HIQ_PORT, 4150 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4151 RTW89_PKT_DROP_SEL_BAND, 4152 RTW89_PKT_DROP_SEL_BAND_ONCE, 4153 RTW89_PKT_DROP_SEL_REL_MACID, 4154 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4155 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4156 }; 4157 4158 struct rtw89_pkt_drop_params { 4159 enum rtw89_pkt_drop_sel sel; 4160 enum rtw89_mac_idx mac_band; 4161 u8 macid; 4162 u8 port; 4163 u8 mbssid; 4164 bool tf_trs; 4165 u32 macid_band_sel[4]; 4166 }; 4167 4168 struct rtw89_pkt_stat { 4169 u16 beacon_nr; 4170 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4171 }; 4172 4173 DECLARE_EWMA(thermal, 4, 4); 4174 4175 struct rtw89_phy_stat { 4176 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4177 struct rtw89_pkt_stat cur_pkt_stat; 4178 struct rtw89_pkt_stat last_pkt_stat; 4179 }; 4180 4181 #define RTW89_DACK_PATH_NR 2 4182 #define RTW89_DACK_IDX_NR 2 4183 #define RTW89_DACK_MSBK_NR 16 4184 struct rtw89_dack_info { 4185 bool dack_done; 4186 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4187 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4188 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4189 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4190 u32 dack_cnt; 4191 bool addck_timeout[RTW89_DACK_PATH_NR]; 4192 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4193 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4194 }; 4195 4196 #define RTW89_IQK_CHS_NR 2 4197 #define RTW89_IQK_PATH_NR 4 4198 4199 struct rtw89_rfk_mcc_info { 4200 u8 ch[RTW89_IQK_CHS_NR]; 4201 u8 band[RTW89_IQK_CHS_NR]; 4202 u8 table_idx; 4203 }; 4204 4205 struct rtw89_lck_info { 4206 u8 thermal[RF_PATH_MAX]; 4207 }; 4208 4209 struct rtw89_rx_dck_info { 4210 u8 thermal[RF_PATH_MAX]; 4211 }; 4212 4213 struct rtw89_iqk_info { 4214 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4215 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4216 bool lok_fail[RTW89_IQK_PATH_NR]; 4217 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4218 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4219 u32 iqk_fail_cnt; 4220 bool is_iqk_init; 4221 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4222 u8 iqk_band[RTW89_IQK_PATH_NR]; 4223 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4224 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4225 u8 iqk_times; 4226 u8 version; 4227 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4228 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4229 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4230 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4231 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4232 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4233 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4234 bool is_nbiqk; 4235 bool iqk_fft_en; 4236 bool iqk_xym_en; 4237 bool iqk_sram_en; 4238 bool iqk_cfir_en; 4239 u32 syn1to2; 4240 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4241 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4242 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4243 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4244 }; 4245 4246 #define RTW89_DPK_RF_PATH 2 4247 #define RTW89_DPK_AVG_THERMAL_NUM 8 4248 #define RTW89_DPK_BKUP_NUM 2 4249 struct rtw89_dpk_bkup_para { 4250 enum rtw89_band band; 4251 enum rtw89_bandwidth bw; 4252 u8 ch; 4253 bool path_ok; 4254 u8 mdpd_en; 4255 u8 txagc_dpk; 4256 u8 ther_dpk; 4257 u8 gs; 4258 u16 pwsf; 4259 }; 4260 4261 struct rtw89_dpk_info { 4262 bool is_dpk_enable; 4263 bool is_dpk_reload_en; 4264 u8 dpk_gs[RTW89_PHY_MAX]; 4265 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4266 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4267 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4268 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4269 u8 cur_idx[RTW89_DPK_RF_PATH]; 4270 u8 cur_k_set; 4271 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4272 }; 4273 4274 struct rtw89_fem_info { 4275 bool elna_2g; 4276 bool elna_5g; 4277 bool epa_2g; 4278 bool epa_5g; 4279 bool epa_6g; 4280 }; 4281 4282 struct rtw89_phy_ch_info { 4283 u8 rssi_min; 4284 u16 rssi_min_macid; 4285 u8 pre_rssi_min; 4286 u8 rssi_max; 4287 u16 rssi_max_macid; 4288 u8 rxsc_160; 4289 u8 rxsc_80; 4290 u8 rxsc_40; 4291 u8 rxsc_20; 4292 u8 rxsc_l; 4293 u8 is_noisy; 4294 }; 4295 4296 struct rtw89_agc_gaincode_set { 4297 u8 lna_idx; 4298 u8 tia_idx; 4299 u8 rxb_idx; 4300 }; 4301 4302 #define IGI_RSSI_TH_NUM 5 4303 #define FA_TH_NUM 4 4304 #define LNA_GAIN_NUM 7 4305 #define TIA_GAIN_NUM 2 4306 struct rtw89_dig_info { 4307 struct rtw89_agc_gaincode_set cur_gaincode; 4308 bool force_gaincode_idx_en; 4309 struct rtw89_agc_gaincode_set force_gaincode; 4310 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4311 u16 fa_th[FA_TH_NUM]; 4312 u8 igi_rssi; 4313 u8 igi_fa_rssi; 4314 u8 fa_rssi_ofst; 4315 u8 dyn_igi_max; 4316 u8 dyn_igi_min; 4317 bool dyn_pd_th_en; 4318 u8 dyn_pd_th_max; 4319 u8 pd_low_th_ofst; 4320 u8 ib_pbk; 4321 s8 ib_pkpwr; 4322 s8 lna_gain_a[LNA_GAIN_NUM]; 4323 s8 lna_gain_g[LNA_GAIN_NUM]; 4324 s8 *lna_gain; 4325 s8 tia_gain_a[TIA_GAIN_NUM]; 4326 s8 tia_gain_g[TIA_GAIN_NUM]; 4327 s8 *tia_gain; 4328 bool is_linked_pre; 4329 bool bypass_dig; 4330 }; 4331 4332 enum rtw89_multi_cfo_mode { 4333 RTW89_PKT_BASED_AVG_MODE = 0, 4334 RTW89_ENTRY_BASED_AVG_MODE = 1, 4335 RTW89_TP_BASED_AVG_MODE = 2, 4336 }; 4337 4338 enum rtw89_phy_cfo_status { 4339 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4340 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4341 RTW89_PHY_DCFO_STATE_HOLD = 2, 4342 RTW89_PHY_DCFO_STATE_MAX 4343 }; 4344 4345 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4346 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4347 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4348 }; 4349 4350 struct rtw89_cfo_tracking_info { 4351 u16 cfo_timer_ms; 4352 bool cfo_trig_by_timer_en; 4353 enum rtw89_phy_cfo_status phy_cfo_status; 4354 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4355 u8 phy_cfo_trk_cnt; 4356 bool is_adjust; 4357 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4358 bool apply_compensation; 4359 u8 crystal_cap; 4360 u8 crystal_cap_default; 4361 u8 def_x_cap; 4362 s8 x_cap_ofst; 4363 u32 sta_cfo_tolerance; 4364 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4365 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4366 s32 cfo_avg_pre; 4367 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4368 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4369 s32 dcfo_avg; 4370 s32 dcfo_avg_pre; 4371 u32 packet_count; 4372 u32 packet_count_pre; 4373 s32 residual_cfo_acc; 4374 u8 phy_cfotrk_state; 4375 u8 phy_cfotrk_cnt; 4376 bool divergence_lock_en; 4377 u8 x_cap_lb; 4378 u8 x_cap_ub; 4379 u8 lock_cnt; 4380 }; 4381 4382 enum rtw89_tssi_alimk_band { 4383 TSSI_ALIMK_2G = 0, 4384 TSSI_ALIMK_5GL, 4385 TSSI_ALIMK_5GM, 4386 TSSI_ALIMK_5GH, 4387 TSSI_ALIMK_MAX 4388 }; 4389 4390 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4391 #define TSSI_TRIM_CH_GROUP_NUM 8 4392 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4393 4394 #define TSSI_CCK_CH_GROUP_NUM 6 4395 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4396 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4397 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4398 #define TSSI_MCS_CH_GROUP_NUM \ 4399 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4400 #define TSSI_MAX_CH_NUM 67 4401 #define TSSI_ALIMK_VALUE_NUM 8 4402 4403 struct rtw89_tssi_info { 4404 u8 thermal[RF_PATH_MAX]; 4405 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4406 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4407 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4408 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4409 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4410 s8 extra_ofst[RF_PATH_MAX]; 4411 bool tssi_tracking_check[RF_PATH_MAX]; 4412 u8 default_txagc_offset[RF_PATH_MAX]; 4413 u32 base_thermal[RF_PATH_MAX]; 4414 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4415 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4416 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4417 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4418 u32 tssi_alimk_time; 4419 }; 4420 4421 struct rtw89_power_trim_info { 4422 bool pg_thermal_trim; 4423 bool pg_pa_bias_trim; 4424 u8 thermal_trim[RF_PATH_MAX]; 4425 u8 pa_bias_trim[RF_PATH_MAX]; 4426 u8 pad_bias_trim[RF_PATH_MAX]; 4427 }; 4428 4429 struct rtw89_regd { 4430 char alpha2[3]; 4431 u8 txpwr_regd[RTW89_BAND_NUM]; 4432 }; 4433 4434 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4435 4436 struct rtw89_regulatory_info { 4437 const struct rtw89_regd *regd; 4438 enum rtw89_reg_6ghz_power reg_6ghz_power; 4439 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4440 }; 4441 4442 enum rtw89_ifs_clm_application { 4443 RTW89_IFS_CLM_INIT = 0, 4444 RTW89_IFS_CLM_BACKGROUND = 1, 4445 RTW89_IFS_CLM_ACS = 2, 4446 RTW89_IFS_CLM_DIG = 3, 4447 RTW89_IFS_CLM_TDMA_DIG = 4, 4448 RTW89_IFS_CLM_DBG = 5, 4449 RTW89_IFS_CLM_DBG_MANUAL = 6 4450 }; 4451 4452 enum rtw89_env_racing_lv { 4453 RTW89_RAC_RELEASE = 0, 4454 RTW89_RAC_LV_1 = 1, 4455 RTW89_RAC_LV_2 = 2, 4456 RTW89_RAC_LV_3 = 3, 4457 RTW89_RAC_LV_4 = 4, 4458 RTW89_RAC_MAX_NUM = 5 4459 }; 4460 4461 struct rtw89_ccx_para_info { 4462 enum rtw89_env_racing_lv rac_lv; 4463 u16 mntr_time; 4464 u8 nhm_manual_th_ofst; 4465 u8 nhm_manual_th0; 4466 enum rtw89_ifs_clm_application ifs_clm_app; 4467 u32 ifs_clm_manual_th_times; 4468 u32 ifs_clm_manual_th0; 4469 u8 fahm_manual_th_ofst; 4470 u8 fahm_manual_th0; 4471 u8 fahm_numer_opt; 4472 u8 fahm_denom_opt; 4473 }; 4474 4475 enum rtw89_ccx_edcca_opt_sc_idx { 4476 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4477 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4478 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4479 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4480 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4481 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4482 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4483 RTW89_CCX_EDCCA_SEG1_S3 = 7 4484 }; 4485 4486 enum rtw89_ccx_edcca_opt_bw_idx { 4487 RTW89_CCX_EDCCA_BW20_0 = 0, 4488 RTW89_CCX_EDCCA_BW20_1 = 1, 4489 RTW89_CCX_EDCCA_BW20_2 = 2, 4490 RTW89_CCX_EDCCA_BW20_3 = 3, 4491 RTW89_CCX_EDCCA_BW20_4 = 4, 4492 RTW89_CCX_EDCCA_BW20_5 = 5, 4493 RTW89_CCX_EDCCA_BW20_6 = 6, 4494 RTW89_CCX_EDCCA_BW20_7 = 7 4495 }; 4496 4497 #define RTW89_NHM_TH_NUM 11 4498 #define RTW89_FAHM_TH_NUM 11 4499 #define RTW89_NHM_RPT_NUM 12 4500 #define RTW89_FAHM_RPT_NUM 12 4501 #define RTW89_IFS_CLM_NUM 4 4502 struct rtw89_env_monitor_info { 4503 u8 ccx_watchdog_result; 4504 bool ccx_ongoing; 4505 u8 ccx_rac_lv; 4506 bool ccx_manual_ctrl; 4507 u16 ifs_clm_mntr_time; 4508 enum rtw89_ifs_clm_application ifs_clm_app; 4509 u16 ccx_period; 4510 u8 ccx_unit_idx; 4511 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4512 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4513 u16 ifs_clm_tx; 4514 u16 ifs_clm_edcca_excl_cca; 4515 u16 ifs_clm_ofdmfa; 4516 u16 ifs_clm_ofdmcca_excl_fa; 4517 u16 ifs_clm_cckfa; 4518 u16 ifs_clm_cckcca_excl_fa; 4519 u16 ifs_clm_total_ifs; 4520 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4521 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4522 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4523 u8 ifs_clm_tx_ratio; 4524 u8 ifs_clm_edcca_excl_cca_ratio; 4525 u8 ifs_clm_cck_fa_ratio; 4526 u8 ifs_clm_ofdm_fa_ratio; 4527 u8 ifs_clm_cck_cca_excl_fa_ratio; 4528 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4529 u16 ifs_clm_cck_fa_permil; 4530 u16 ifs_clm_ofdm_fa_permil; 4531 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4532 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4533 }; 4534 4535 enum rtw89_ser_rcvy_step { 4536 RTW89_SER_DRV_STOP_TX, 4537 RTW89_SER_DRV_STOP_RX, 4538 RTW89_SER_DRV_STOP_RUN, 4539 RTW89_SER_HAL_STOP_DMA, 4540 RTW89_SER_SUPPRESS_LOG, 4541 RTW89_NUM_OF_SER_FLAGS 4542 }; 4543 4544 struct rtw89_ser { 4545 u8 state; 4546 u8 alarm_event; 4547 bool prehandle_l1; 4548 4549 struct work_struct ser_hdl_work; 4550 struct delayed_work ser_alarm_work; 4551 const struct state_ent *st_tbl; 4552 const struct event_ent *ev_tbl; 4553 struct list_head msg_q; 4554 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4555 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4556 }; 4557 4558 enum rtw89_mac_ax_ps_mode { 4559 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4560 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4561 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4562 RTW89_MAC_AX_PS_MODE_MAX = 3, 4563 }; 4564 4565 enum rtw89_last_rpwm_mode { 4566 RTW89_LAST_RPWM_PS = 0x0, 4567 RTW89_LAST_RPWM_ACTIVE = 0x6, 4568 }; 4569 4570 struct rtw89_lps_parm { 4571 u8 macid; 4572 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4573 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4574 }; 4575 4576 struct rtw89_ppdu_sts_info { 4577 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4578 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4579 }; 4580 4581 struct rtw89_early_h2c { 4582 struct list_head list; 4583 u8 *h2c; 4584 u16 h2c_len; 4585 }; 4586 4587 struct rtw89_hw_scan_info { 4588 struct ieee80211_vif *scanning_vif; 4589 struct list_head pkt_list[NUM_NL80211_BANDS]; 4590 struct rtw89_chan op_chan; 4591 u32 last_chan_idx; 4592 }; 4593 4594 enum rtw89_phy_bb_gain_band { 4595 RTW89_BB_GAIN_BAND_2G = 0, 4596 RTW89_BB_GAIN_BAND_5G_L = 1, 4597 RTW89_BB_GAIN_BAND_5G_M = 2, 4598 RTW89_BB_GAIN_BAND_5G_H = 3, 4599 RTW89_BB_GAIN_BAND_6G_L = 4, 4600 RTW89_BB_GAIN_BAND_6G_M = 5, 4601 RTW89_BB_GAIN_BAND_6G_H = 6, 4602 RTW89_BB_GAIN_BAND_6G_UH = 7, 4603 4604 RTW89_BB_GAIN_BAND_NR, 4605 }; 4606 4607 enum rtw89_phy_bb_rxsc_num { 4608 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4609 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4610 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4611 }; 4612 4613 struct rtw89_phy_bb_gain_info { 4614 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4615 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4616 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4617 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4618 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4619 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4620 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4621 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4622 [RTW89_BB_RXSC_NUM_40]; 4623 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4624 [RTW89_BB_RXSC_NUM_80]; 4625 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4626 [RTW89_BB_RXSC_NUM_160]; 4627 }; 4628 4629 struct rtw89_phy_efuse_gain { 4630 bool offset_valid; 4631 bool comp_valid; 4632 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4633 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4634 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4635 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4636 }; 4637 4638 #define RTW89_MAX_PATTERN_NUM 18 4639 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4640 #define RTW89_MAX_PATTERN_SIZE 128 4641 4642 struct rtw89_wow_cam_info { 4643 bool r_w; 4644 u8 idx; 4645 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4646 u16 crc; 4647 bool negative_pattern_match; 4648 bool skip_mac_hdr; 4649 bool uc; 4650 bool mc; 4651 bool bc; 4652 bool valid; 4653 }; 4654 4655 struct rtw89_wow_param { 4656 struct ieee80211_vif *wow_vif; 4657 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4658 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4659 u8 pattern_cnt; 4660 }; 4661 4662 struct rtw89_mcc_limit { 4663 bool enable; 4664 u16 max_tob; /* TU; max time offset behind */ 4665 u16 max_toa; /* TU; max time offset ahead */ 4666 u16 max_dur; /* TU */ 4667 }; 4668 4669 struct rtw89_mcc_policy { 4670 u8 c2h_rpt; 4671 u8 tx_null_early; 4672 u8 dis_tx_null; 4673 u8 in_curr_ch; 4674 u8 dis_sw_retry; 4675 u8 sw_retry_count; 4676 }; 4677 4678 struct rtw89_mcc_role { 4679 struct rtw89_vif *rtwvif; 4680 struct rtw89_mcc_policy policy; 4681 struct rtw89_mcc_limit limit; 4682 4683 /* byte-array in LE order for FW */ 4684 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 4685 4686 u16 duration; /* TU */ 4687 u16 beacon_interval; /* TU */ 4688 bool is_2ghz; 4689 bool is_go; 4690 bool is_gc; 4691 }; 4692 4693 struct rtw89_mcc_bt_role { 4694 u16 duration; /* TU */ 4695 }; 4696 4697 struct rtw89_mcc_courtesy { 4698 bool enable; 4699 u8 slot_num; 4700 u8 macid_src; 4701 u8 macid_tgt; 4702 }; 4703 4704 enum rtw89_mcc_plan { 4705 RTW89_MCC_PLAN_TAIL_BT, 4706 RTW89_MCC_PLAN_MID_BT, 4707 RTW89_MCC_PLAN_NO_BT, 4708 4709 NUM_OF_RTW89_MCC_PLAN, 4710 }; 4711 4712 struct rtw89_mcc_pattern { 4713 s16 tob_ref; /* TU; time offset behind of reference role */ 4714 s16 toa_ref; /* TU; time offset ahead of reference role */ 4715 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 4716 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 4717 4718 enum rtw89_mcc_plan plan; 4719 struct rtw89_mcc_courtesy courtesy; 4720 }; 4721 4722 struct rtw89_mcc_sync { 4723 bool enable; 4724 u16 offset; /* TU */ 4725 u8 macid_src; 4726 u8 macid_tgt; 4727 }; 4728 4729 struct rtw89_mcc_config { 4730 struct rtw89_mcc_pattern pattern; 4731 struct rtw89_mcc_sync sync; 4732 u64 start_tsf; 4733 u16 mcc_interval; /* TU */ 4734 u16 beacon_offset; /* TU */ 4735 }; 4736 4737 enum rtw89_mcc_mode { 4738 RTW89_MCC_MODE_GO_STA, 4739 RTW89_MCC_MODE_GC_STA, 4740 }; 4741 4742 struct rtw89_mcc_info { 4743 struct rtw89_wait_info wait; 4744 4745 u8 group; 4746 enum rtw89_mcc_mode mode; 4747 struct rtw89_mcc_role role_ref; /* reference role */ 4748 struct rtw89_mcc_role role_aux; /* auxiliary role */ 4749 struct rtw89_mcc_bt_role bt_role; 4750 struct rtw89_mcc_config config; 4751 }; 4752 4753 struct rtw89_dev { 4754 struct ieee80211_hw *hw; 4755 struct device *dev; 4756 const struct ieee80211_ops *ops; 4757 4758 bool dbcc_en; 4759 struct rtw89_hw_scan_info scan_info; 4760 const struct rtw89_chip_info *chip; 4761 const struct rtw89_pci_info *pci_info; 4762 const struct rtw89_rfe_parms *rfe_parms; 4763 struct rtw89_hal hal; 4764 struct rtw89_mcc_info mcc; 4765 struct rtw89_mac_info mac; 4766 struct rtw89_fw_info fw; 4767 struct rtw89_hci_info hci; 4768 struct rtw89_efuse efuse; 4769 struct rtw89_traffic_stats stats; 4770 struct rtw89_rfe_data *rfe_data; 4771 4772 /* ensures exclusive access from mac80211 callbacks */ 4773 struct mutex mutex; 4774 struct list_head rtwvifs_list; 4775 /* used to protect rf read write */ 4776 struct mutex rf_mutex; 4777 struct workqueue_struct *txq_wq; 4778 struct work_struct txq_work; 4779 struct delayed_work txq_reinvoke_work; 4780 /* used to protect ba_list and forbid_ba_list */ 4781 spinlock_t ba_lock; 4782 /* txqs to setup ba session */ 4783 struct list_head ba_list; 4784 /* txqs to forbid ba session */ 4785 struct list_head forbid_ba_list; 4786 struct work_struct ba_work; 4787 /* used to protect rpwm */ 4788 spinlock_t rpwm_lock; 4789 4790 struct rtw89_cam_info cam_info; 4791 4792 struct sk_buff_head c2h_queue; 4793 struct work_struct c2h_work; 4794 struct work_struct ips_work; 4795 struct work_struct load_firmware_work; 4796 struct work_struct cancel_6ghz_probe_work; 4797 4798 struct list_head early_h2c_list; 4799 4800 struct rtw89_ser ser; 4801 4802 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4803 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 4804 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 4805 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 4806 4807 struct rtw89_phy_stat phystat; 4808 struct rtw89_dack_info dack; 4809 struct rtw89_iqk_info iqk; 4810 struct rtw89_dpk_info dpk; 4811 struct rtw89_rfk_mcc_info rfk_mcc; 4812 struct rtw89_lck_info lck; 4813 struct rtw89_rx_dck_info rx_dck; 4814 bool is_tssi_mode[RF_PATH_MAX]; 4815 bool is_bt_iqk_timeout; 4816 4817 struct rtw89_fem_info fem; 4818 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 4819 struct rtw89_tssi_info tssi; 4820 struct rtw89_power_trim_info pwr_trim; 4821 4822 struct rtw89_cfo_tracking_info cfo_tracking; 4823 struct rtw89_env_monitor_info env_monitor; 4824 struct rtw89_dig_info dig; 4825 struct rtw89_phy_ch_info ch_info; 4826 struct rtw89_phy_bb_gain_info bb_gain; 4827 struct rtw89_phy_efuse_gain efuse_gain; 4828 struct rtw89_phy_ul_tb_info ul_tb_info; 4829 struct rtw89_antdiv_info antdiv; 4830 4831 struct delayed_work track_work; 4832 struct delayed_work chanctx_work; 4833 struct delayed_work coex_act1_work; 4834 struct delayed_work coex_bt_devinfo_work; 4835 struct delayed_work coex_rfk_chk_work; 4836 struct delayed_work cfo_track_work; 4837 struct delayed_work forbid_ba_work; 4838 struct delayed_work roc_work; 4839 struct delayed_work antdiv_work; 4840 struct rtw89_ppdu_sts_info ppdu_sts; 4841 u8 total_sta_assoc; 4842 bool scanning; 4843 4844 struct rtw89_regulatory_info regulatory; 4845 struct rtw89_sar_info sar; 4846 struct rtw89_tas_info tas; 4847 4848 struct rtw89_btc btc; 4849 enum rtw89_ps_mode ps_mode; 4850 bool lps_enabled; 4851 4852 struct rtw89_wow_param wow; 4853 4854 /* napi structure */ 4855 struct net_device netdev; 4856 struct napi_struct napi; 4857 int napi_budget_countdown; 4858 4859 /* HCI related data, keep last */ 4860 u8 priv[] __aligned(sizeof(void *)); 4861 }; 4862 4863 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4864 struct rtw89_core_tx_request *tx_req) 4865 { 4866 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4867 } 4868 4869 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4870 { 4871 rtwdev->hci.ops->reset(rtwdev); 4872 } 4873 4874 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4875 { 4876 return rtwdev->hci.ops->start(rtwdev); 4877 } 4878 4879 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4880 { 4881 rtwdev->hci.ops->stop(rtwdev); 4882 } 4883 4884 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4885 { 4886 return rtwdev->hci.ops->deinit(rtwdev); 4887 } 4888 4889 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4890 { 4891 rtwdev->hci.ops->pause(rtwdev, pause); 4892 } 4893 4894 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4895 { 4896 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4897 } 4898 4899 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4900 { 4901 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4902 } 4903 4904 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4905 { 4906 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4907 } 4908 4909 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4910 { 4911 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4912 } 4913 4914 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 4915 { 4916 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 4917 } 4918 4919 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4920 bool drop) 4921 { 4922 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4923 return; 4924 4925 if (rtwdev->hci.ops->flush_queues) 4926 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4927 } 4928 4929 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4930 { 4931 if (rtwdev->hci.ops->recovery_start) 4932 rtwdev->hci.ops->recovery_start(rtwdev); 4933 } 4934 4935 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4936 { 4937 if (rtwdev->hci.ops->recovery_complete) 4938 rtwdev->hci.ops->recovery_complete(rtwdev); 4939 } 4940 4941 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4942 { 4943 if (rtwdev->hci.ops->enable_intr) 4944 rtwdev->hci.ops->enable_intr(rtwdev); 4945 } 4946 4947 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4948 { 4949 if (rtwdev->hci.ops->disable_intr) 4950 rtwdev->hci.ops->disable_intr(rtwdev); 4951 } 4952 4953 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4954 { 4955 if (rtwdev->hci.ops->ctrl_txdma_ch) 4956 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4957 } 4958 4959 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4960 { 4961 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4962 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4963 } 4964 4965 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4966 { 4967 if (rtwdev->hci.ops->ctrl_trxhci) 4968 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4969 } 4970 4971 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4972 { 4973 int ret = 0; 4974 4975 if (rtwdev->hci.ops->poll_txdma_ch) 4976 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4977 return ret; 4978 } 4979 4980 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4981 { 4982 if (rtwdev->hci.ops->clr_idx_all) 4983 rtwdev->hci.ops->clr_idx_all(rtwdev); 4984 } 4985 4986 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4987 { 4988 int ret = 0; 4989 4990 if (rtwdev->hci.ops->rst_bdram) 4991 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4992 return ret; 4993 } 4994 4995 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4996 { 4997 if (rtwdev->hci.ops->clear) 4998 rtwdev->hci.ops->clear(rtwdev, pdev); 4999 } 5000 5001 static inline 5002 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5003 { 5004 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5005 5006 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5007 } 5008 5009 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5010 { 5011 return rtwdev->hci.ops->read8(rtwdev, addr); 5012 } 5013 5014 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5015 { 5016 return rtwdev->hci.ops->read16(rtwdev, addr); 5017 } 5018 5019 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5020 { 5021 return rtwdev->hci.ops->read32(rtwdev, addr); 5022 } 5023 5024 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5025 { 5026 rtwdev->hci.ops->write8(rtwdev, addr, data); 5027 } 5028 5029 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5030 { 5031 rtwdev->hci.ops->write16(rtwdev, addr, data); 5032 } 5033 5034 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5035 { 5036 rtwdev->hci.ops->write32(rtwdev, addr, data); 5037 } 5038 5039 static inline void 5040 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5041 { 5042 u8 val; 5043 5044 val = rtw89_read8(rtwdev, addr); 5045 rtw89_write8(rtwdev, addr, val | bit); 5046 } 5047 5048 static inline void 5049 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5050 { 5051 u16 val; 5052 5053 val = rtw89_read16(rtwdev, addr); 5054 rtw89_write16(rtwdev, addr, val | bit); 5055 } 5056 5057 static inline void 5058 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5059 { 5060 u32 val; 5061 5062 val = rtw89_read32(rtwdev, addr); 5063 rtw89_write32(rtwdev, addr, val | bit); 5064 } 5065 5066 static inline void 5067 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5068 { 5069 u8 val; 5070 5071 val = rtw89_read8(rtwdev, addr); 5072 rtw89_write8(rtwdev, addr, val & ~bit); 5073 } 5074 5075 static inline void 5076 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5077 { 5078 u16 val; 5079 5080 val = rtw89_read16(rtwdev, addr); 5081 rtw89_write16(rtwdev, addr, val & ~bit); 5082 } 5083 5084 static inline void 5085 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5086 { 5087 u32 val; 5088 5089 val = rtw89_read32(rtwdev, addr); 5090 rtw89_write32(rtwdev, addr, val & ~bit); 5091 } 5092 5093 static inline u32 5094 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5095 { 5096 u32 shift = __ffs(mask); 5097 u32 orig; 5098 u32 ret; 5099 5100 orig = rtw89_read32(rtwdev, addr); 5101 ret = (orig & mask) >> shift; 5102 5103 return ret; 5104 } 5105 5106 static inline u16 5107 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5108 { 5109 u32 shift = __ffs(mask); 5110 u32 orig; 5111 u32 ret; 5112 5113 orig = rtw89_read16(rtwdev, addr); 5114 ret = (orig & mask) >> shift; 5115 5116 return ret; 5117 } 5118 5119 static inline u8 5120 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5121 { 5122 u32 shift = __ffs(mask); 5123 u32 orig; 5124 u32 ret; 5125 5126 orig = rtw89_read8(rtwdev, addr); 5127 ret = (orig & mask) >> shift; 5128 5129 return ret; 5130 } 5131 5132 static inline void 5133 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5134 { 5135 u32 shift = __ffs(mask); 5136 u32 orig; 5137 u32 set; 5138 5139 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5140 5141 orig = rtw89_read32(rtwdev, addr); 5142 set = (orig & ~mask) | ((data << shift) & mask); 5143 rtw89_write32(rtwdev, addr, set); 5144 } 5145 5146 static inline void 5147 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5148 { 5149 u32 shift; 5150 u16 orig, set; 5151 5152 mask &= 0xffff; 5153 shift = __ffs(mask); 5154 5155 orig = rtw89_read16(rtwdev, addr); 5156 set = (orig & ~mask) | ((data << shift) & mask); 5157 rtw89_write16(rtwdev, addr, set); 5158 } 5159 5160 static inline void 5161 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5162 { 5163 u32 shift; 5164 u8 orig, set; 5165 5166 mask &= 0xff; 5167 shift = __ffs(mask); 5168 5169 orig = rtw89_read8(rtwdev, addr); 5170 set = (orig & ~mask) | ((data << shift) & mask); 5171 rtw89_write8(rtwdev, addr, set); 5172 } 5173 5174 static inline u32 5175 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5176 u32 addr, u32 mask) 5177 { 5178 u32 val; 5179 5180 mutex_lock(&rtwdev->rf_mutex); 5181 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5182 mutex_unlock(&rtwdev->rf_mutex); 5183 5184 return val; 5185 } 5186 5187 static inline void 5188 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5189 u32 addr, u32 mask, u32 data) 5190 { 5191 mutex_lock(&rtwdev->rf_mutex); 5192 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5193 mutex_unlock(&rtwdev->rf_mutex); 5194 } 5195 5196 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5197 { 5198 void *p = rtwtxq; 5199 5200 return container_of(p, struct ieee80211_txq, drv_priv); 5201 } 5202 5203 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5204 struct ieee80211_txq *txq) 5205 { 5206 struct rtw89_txq *rtwtxq; 5207 5208 if (!txq) 5209 return; 5210 5211 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5212 INIT_LIST_HEAD(&rtwtxq->list); 5213 } 5214 5215 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5216 { 5217 void *p = rtwvif; 5218 5219 return container_of(p, struct ieee80211_vif, drv_priv); 5220 } 5221 5222 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5223 { 5224 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5225 } 5226 5227 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5228 { 5229 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5230 } 5231 5232 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5233 { 5234 void *p = rtwsta; 5235 5236 return container_of(p, struct ieee80211_sta, drv_priv); 5237 } 5238 5239 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5240 { 5241 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5242 } 5243 5244 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5245 { 5246 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5247 } 5248 5249 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5250 { 5251 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5252 return RATE_INFO_BW_160; 5253 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5254 return RATE_INFO_BW_80; 5255 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5256 return RATE_INFO_BW_40; 5257 else 5258 return RATE_INFO_BW_20; 5259 } 5260 5261 static inline 5262 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5263 { 5264 switch (hw_band) { 5265 default: 5266 case RTW89_BAND_2G: 5267 return NL80211_BAND_2GHZ; 5268 case RTW89_BAND_5G: 5269 return NL80211_BAND_5GHZ; 5270 case RTW89_BAND_6G: 5271 return NL80211_BAND_6GHZ; 5272 } 5273 } 5274 5275 static inline 5276 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5277 { 5278 switch (nl_band) { 5279 default: 5280 case NL80211_BAND_2GHZ: 5281 return RTW89_BAND_2G; 5282 case NL80211_BAND_5GHZ: 5283 return RTW89_BAND_5G; 5284 case NL80211_BAND_6GHZ: 5285 return RTW89_BAND_6G; 5286 } 5287 } 5288 5289 static inline 5290 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5291 { 5292 switch (width) { 5293 default: 5294 WARN(1, "Not support bandwidth %d\n", width); 5295 fallthrough; 5296 case NL80211_CHAN_WIDTH_20_NOHT: 5297 case NL80211_CHAN_WIDTH_20: 5298 return RTW89_CHANNEL_WIDTH_20; 5299 case NL80211_CHAN_WIDTH_40: 5300 return RTW89_CHANNEL_WIDTH_40; 5301 case NL80211_CHAN_WIDTH_80: 5302 return RTW89_CHANNEL_WIDTH_80; 5303 case NL80211_CHAN_WIDTH_160: 5304 return RTW89_CHANNEL_WIDTH_160; 5305 } 5306 } 5307 5308 static inline 5309 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5310 { 5311 switch (rua) { 5312 default: 5313 WARN(1, "Invalid RU allocation: %d\n", rua); 5314 fallthrough; 5315 case 0 ... 36: 5316 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5317 case 37 ... 52: 5318 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5319 case 53 ... 60: 5320 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5321 case 61 ... 64: 5322 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5323 case 65 ... 66: 5324 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5325 case 67: 5326 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5327 case 68: 5328 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5329 } 5330 } 5331 5332 static inline 5333 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5334 struct rtw89_sta *rtwsta) 5335 { 5336 if (rtwsta) { 5337 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5338 5339 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5340 return &rtwsta->addr_cam; 5341 } 5342 return &rtwvif->addr_cam; 5343 } 5344 5345 static inline 5346 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5347 struct rtw89_sta *rtwsta) 5348 { 5349 if (rtwsta) { 5350 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5351 5352 if (sta->tdls) 5353 return &rtwsta->bssid_cam; 5354 } 5355 return &rtwvif->bssid_cam; 5356 } 5357 5358 static inline 5359 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5360 struct rtw89_channel_help_params *p, 5361 const struct rtw89_chan *chan, 5362 enum rtw89_mac_idx mac_idx, 5363 enum rtw89_phy_idx phy_idx) 5364 { 5365 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5366 mac_idx, phy_idx); 5367 } 5368 5369 static inline 5370 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 5371 struct rtw89_channel_help_params *p, 5372 const struct rtw89_chan *chan, 5373 enum rtw89_mac_idx mac_idx, 5374 enum rtw89_phy_idx phy_idx) 5375 { 5376 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 5377 mac_idx, phy_idx); 5378 } 5379 5380 static inline 5381 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 5382 enum rtw89_sub_entity_idx idx) 5383 { 5384 struct rtw89_hal *hal = &rtwdev->hal; 5385 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 5386 5387 if (roc_idx == idx) 5388 return &hal->roc_chandef; 5389 5390 return &hal->sub[idx].chandef; 5391 } 5392 5393 static inline 5394 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 5395 enum rtw89_sub_entity_idx idx) 5396 { 5397 struct rtw89_hal *hal = &rtwdev->hal; 5398 5399 return &hal->sub[idx].chan; 5400 } 5401 5402 static inline 5403 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 5404 enum rtw89_sub_entity_idx idx) 5405 { 5406 struct rtw89_hal *hal = &rtwdev->hal; 5407 5408 return &hal->sub[idx].rcd; 5409 } 5410 5411 static inline 5412 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 5413 { 5414 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 5415 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 5416 5417 if (rtwvif) 5418 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 5419 else 5420 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5421 } 5422 5423 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 5424 { 5425 const struct rtw89_chip_info *chip = rtwdev->chip; 5426 5427 if (chip->ops->fem_setup) 5428 chip->ops->fem_setup(rtwdev); 5429 } 5430 5431 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 5432 { 5433 const struct rtw89_chip_info *chip = rtwdev->chip; 5434 5435 if (chip->ops->rfe_gpio) 5436 chip->ops->rfe_gpio(rtwdev); 5437 } 5438 5439 static inline 5440 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5441 { 5442 const struct rtw89_chip_info *chip = rtwdev->chip; 5443 5444 if (chip->ops->bb_preinit) 5445 chip->ops->bb_preinit(rtwdev, phy_idx); 5446 } 5447 5448 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 5449 { 5450 const struct rtw89_chip_info *chip = rtwdev->chip; 5451 5452 if (chip->ops->bb_sethw) 5453 chip->ops->bb_sethw(rtwdev); 5454 } 5455 5456 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 5457 { 5458 const struct rtw89_chip_info *chip = rtwdev->chip; 5459 5460 if (chip->ops->rfk_init) 5461 chip->ops->rfk_init(rtwdev); 5462 } 5463 5464 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 5465 { 5466 const struct rtw89_chip_info *chip = rtwdev->chip; 5467 5468 if (chip->ops->rfk_channel) 5469 chip->ops->rfk_channel(rtwdev); 5470 } 5471 5472 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 5473 enum rtw89_phy_idx phy_idx) 5474 { 5475 const struct rtw89_chip_info *chip = rtwdev->chip; 5476 5477 if (chip->ops->rfk_band_changed) 5478 chip->ops->rfk_band_changed(rtwdev, phy_idx); 5479 } 5480 5481 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 5482 { 5483 const struct rtw89_chip_info *chip = rtwdev->chip; 5484 5485 if (chip->ops->rfk_scan) 5486 chip->ops->rfk_scan(rtwdev, start); 5487 } 5488 5489 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 5490 { 5491 const struct rtw89_chip_info *chip = rtwdev->chip; 5492 5493 if (chip->ops->rfk_track) 5494 chip->ops->rfk_track(rtwdev); 5495 } 5496 5497 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 5498 { 5499 const struct rtw89_chip_info *chip = rtwdev->chip; 5500 5501 if (chip->ops->set_txpwr_ctrl) 5502 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 5503 } 5504 5505 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 5506 { 5507 const struct rtw89_chip_info *chip = rtwdev->chip; 5508 5509 if (chip->ops->power_trim) 5510 chip->ops->power_trim(rtwdev); 5511 } 5512 5513 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 5514 enum rtw89_phy_idx phy_idx) 5515 { 5516 const struct rtw89_chip_info *chip = rtwdev->chip; 5517 5518 if (chip->ops->init_txpwr_unit) 5519 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 5520 } 5521 5522 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 5523 enum rtw89_rf_path rf_path) 5524 { 5525 const struct rtw89_chip_info *chip = rtwdev->chip; 5526 5527 if (!chip->ops->get_thermal) 5528 return 0x10; 5529 5530 return chip->ops->get_thermal(rtwdev, rf_path); 5531 } 5532 5533 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 5534 struct rtw89_rx_phy_ppdu *phy_ppdu, 5535 struct ieee80211_rx_status *status) 5536 { 5537 const struct rtw89_chip_info *chip = rtwdev->chip; 5538 5539 if (chip->ops->query_ppdu) 5540 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 5541 } 5542 5543 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 5544 enum rtw89_phy_idx phy_idx) 5545 { 5546 const struct rtw89_chip_info *chip = rtwdev->chip; 5547 5548 if (chip->ops->ctrl_nbtg_bt_tx) 5549 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 5550 } 5551 5552 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 5553 { 5554 const struct rtw89_chip_info *chip = rtwdev->chip; 5555 5556 if (chip->ops->cfg_txrx_path) 5557 chip->ops->cfg_txrx_path(rtwdev); 5558 } 5559 5560 static inline 5561 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5562 struct ieee80211_vif *vif) 5563 { 5564 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5565 const struct rtw89_chip_info *chip = rtwdev->chip; 5566 5567 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5568 return; 5569 5570 if (chip->ops->set_txpwr_ul_tb_offset) 5571 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5572 } 5573 5574 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 5575 const struct rtw89_txpwr_table *tbl) 5576 { 5577 tbl->load(rtwdev, tbl); 5578 } 5579 5580 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 5581 { 5582 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 5583 5584 return regd->txpwr_regd[band]; 5585 } 5586 5587 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 5588 enum rtw89_phy_idx phy_idx) 5589 { 5590 const struct rtw89_chip_info *chip = rtwdev->chip; 5591 5592 if (chip->ops->ctrl_btg_bt_rx) 5593 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 5594 } 5595 5596 static inline 5597 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 5598 struct rtw89_rx_desc_info *desc_info, 5599 u8 *data, u32 data_offset) 5600 { 5601 const struct rtw89_chip_info *chip = rtwdev->chip; 5602 5603 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 5604 } 5605 5606 static inline 5607 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 5608 struct rtw89_tx_desc_info *desc_info, 5609 void *txdesc) 5610 { 5611 const struct rtw89_chip_info *chip = rtwdev->chip; 5612 5613 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 5614 } 5615 5616 static inline 5617 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 5618 struct rtw89_tx_desc_info *desc_info, 5619 void *txdesc) 5620 { 5621 const struct rtw89_chip_info *chip = rtwdev->chip; 5622 5623 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 5624 } 5625 5626 static inline 5627 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5628 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5629 { 5630 const struct rtw89_chip_info *chip = rtwdev->chip; 5631 5632 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 5633 } 5634 5635 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5636 { 5637 const struct rtw89_chip_info *chip = rtwdev->chip; 5638 5639 chip->ops->cfg_ctrl_path(rtwdev, wl); 5640 } 5641 5642 static inline 5643 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 5644 u32 *tx_en, enum rtw89_sch_tx_sel sel) 5645 { 5646 const struct rtw89_chip_info *chip = rtwdev->chip; 5647 5648 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 5649 } 5650 5651 static inline 5652 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 5653 { 5654 const struct rtw89_chip_info *chip = rtwdev->chip; 5655 5656 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 5657 } 5658 5659 static inline 5660 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 5661 struct rtw89_vif *rtwvif, 5662 struct rtw89_sta *rtwsta) 5663 { 5664 const struct rtw89_chip_info *chip = rtwdev->chip; 5665 5666 if (!chip->ops->h2c_dctl_sec_cam) 5667 return 0; 5668 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 5669 } 5670 5671 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 5672 { 5673 __le16 fc = hdr->frame_control; 5674 5675 if (ieee80211_has_tods(fc)) 5676 return hdr->addr1; 5677 else if (ieee80211_has_fromds(fc)) 5678 return hdr->addr2; 5679 else 5680 return hdr->addr3; 5681 } 5682 5683 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 5684 { 5685 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5686 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 5687 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 5688 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5689 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 5690 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 5691 return true; 5692 return false; 5693 } 5694 5695 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 5696 enum rtw89_fw_type type) 5697 { 5698 struct rtw89_fw_info *fw_info = &rtwdev->fw; 5699 5700 switch (type) { 5701 case RTW89_FW_WOWLAN: 5702 return &fw_info->wowlan; 5703 case RTW89_FW_LOGFMT: 5704 return &fw_info->log.suit; 5705 case RTW89_FW_BBMCU0: 5706 return &fw_info->bbmcu0; 5707 case RTW89_FW_BBMCU1: 5708 return &fw_info->bbmcu1; 5709 default: 5710 break; 5711 } 5712 5713 return &fw_info->normal; 5714 } 5715 5716 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 5717 unsigned int length) 5718 { 5719 struct sk_buff *skb; 5720 5721 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 5722 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 5723 if (!skb) 5724 return NULL; 5725 5726 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 5727 return skb; 5728 } 5729 5730 return dev_alloc_skb(length); 5731 } 5732 5733 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 5734 struct rtw89_tx_skb_data *skb_data, 5735 bool tx_done) 5736 { 5737 struct rtw89_tx_wait_info *wait; 5738 5739 rcu_read_lock(); 5740 5741 wait = rcu_dereference(skb_data->wait); 5742 if (!wait) 5743 goto out; 5744 5745 wait->tx_done = tx_done; 5746 complete(&wait->completion); 5747 5748 out: 5749 rcu_read_unlock(); 5750 } 5751 5752 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5753 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 5754 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 5755 struct sk_buff *skb, bool fwdl); 5756 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 5757 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5758 int qsel, unsigned int timeout); 5759 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 5760 struct rtw89_tx_desc_info *desc_info, 5761 void *txdesc); 5762 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 5763 struct rtw89_tx_desc_info *desc_info, 5764 void *txdesc); 5765 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 5766 struct rtw89_tx_desc_info *desc_info, 5767 void *txdesc); 5768 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 5769 struct rtw89_tx_desc_info *desc_info, 5770 void *txdesc); 5771 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 5772 struct rtw89_tx_desc_info *desc_info, 5773 void *txdesc); 5774 void rtw89_core_rx(struct rtw89_dev *rtwdev, 5775 struct rtw89_rx_desc_info *desc_info, 5776 struct sk_buff *skb); 5777 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 5778 struct rtw89_rx_desc_info *desc_info, 5779 u8 *data, u32 data_offset); 5780 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 5781 struct rtw89_rx_desc_info *desc_info, 5782 u8 *data, u32 data_offset); 5783 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 5784 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 5785 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 5786 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 5787 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 5788 struct ieee80211_vif *vif, 5789 struct ieee80211_sta *sta); 5790 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 5791 struct ieee80211_vif *vif, 5792 struct ieee80211_sta *sta); 5793 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 5794 struct ieee80211_vif *vif, 5795 struct ieee80211_sta *sta); 5796 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 5797 struct ieee80211_vif *vif, 5798 struct ieee80211_sta *sta); 5799 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 5800 struct ieee80211_vif *vif, 5801 struct ieee80211_sta *sta); 5802 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5803 struct ieee80211_sta *sta, 5804 struct cfg80211_tid_config *tid_config); 5805 int rtw89_core_init(struct rtw89_dev *rtwdev); 5806 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 5807 int rtw89_core_register(struct rtw89_dev *rtwdev); 5808 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 5809 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5810 u32 bus_data_size, 5811 const struct rtw89_chip_info *chip); 5812 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 5813 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 5814 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 5815 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 5816 struct rtw89_chan *chan); 5817 void rtw89_set_channel(struct rtw89_dev *rtwdev); 5818 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5819 struct rtw89_chan *chan); 5820 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 5821 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 5822 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 5823 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 5824 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5825 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 5826 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5827 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 5828 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 5829 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 5830 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 5831 int rtw89_regd_init(struct rtw89_dev *rtwdev, 5832 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 5833 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 5834 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 5835 struct rtw89_traffic_stats *stats); 5836 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 5837 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5838 const struct rtw89_completion_data *data); 5839 int rtw89_core_start(struct rtw89_dev *rtwdev); 5840 void rtw89_core_stop(struct rtw89_dev *rtwdev); 5841 void rtw89_core_update_beacon_work(struct work_struct *work); 5842 void rtw89_roc_work(struct work_struct *work); 5843 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5844 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5845 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5846 const u8 *mac_addr, bool hw_scan); 5847 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5848 struct ieee80211_vif *vif, bool hw_scan); 5849 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 5850 struct rtw89_vif *rtwvif, bool active); 5851 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 5852 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 5853 5854 #endif 5855