1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_fw_blacklist; 21 struct rtw89_efuse_block_cfg; 22 struct rtw89_h2c_rf_tssi; 23 struct rtw89_fw_txpwr_track_cfg; 24 struct rtw89_phy_rfk_log_fmt; 25 struct rtw89_debugfs; 26 struct rtw89_regd_data; 27 28 extern const struct ieee80211_ops rtw89_ops; 29 30 #define MASKBYTE0 0xff 31 #define MASKBYTE1 0xff00 32 #define MASKBYTE2 0xff0000 33 #define MASKBYTE3 0xff000000 34 #define MASKBYTE4 0xff00000000ULL 35 #define MASKHWORD 0xffff0000 36 #define MASKLWORD 0x0000ffff 37 #define MASKDWORD 0xffffffff 38 #define RFREG_MASK 0xfffff 39 #define INV_RF_DATA 0xffffffff 40 #define BYPASS_CR_DATA 0xbabecafe 41 42 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 43 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100) 44 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 45 #define CFO_TRACK_MAX_USER 64 46 #define MAX_RSSI 110 47 #define RSSI_FACTOR 1 48 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 49 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 50 #define DELTA_SWINGIDX_SIZE 30 51 52 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 53 #define RTW89_RADIOTAP_ROOM_EHT \ 54 (sizeof(struct ieee80211_radiotap_tlv) + \ 55 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 56 sizeof(struct ieee80211_radiotap_tlv) + \ 57 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 58 #define RTW89_RADIOTAP_ROOM \ 59 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 60 61 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 62 #define RTW89_HTC_VARIANT_HE 3 63 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 64 #define RTW89_HTC_VARIANT_HE_CID_OM 1 65 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 66 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 67 68 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 69 enum htc_om_channel_width { 70 HTC_OM_CHANNEL_WIDTH_20 = 0, 71 HTC_OM_CHANNEL_WIDTH_40 = 1, 72 HTC_OM_CHANNEL_WIDTH_80 = 2, 73 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 74 }; 75 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 76 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 77 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 78 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 79 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 80 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 81 82 #define RTW89_TF_PAD GENMASK(11, 0) 83 #define RTW89_TF_BASIC_USER_INFO_SZ 6 84 85 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 86 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 87 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 88 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 89 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 90 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 91 92 enum rtw89_subband { 93 RTW89_CH_2G = 0, 94 RTW89_CH_5G_BAND_1 = 1, 95 /* RTW89_CH_5G_BAND_2 = 2, unused */ 96 RTW89_CH_5G_BAND_3 = 3, 97 RTW89_CH_5G_BAND_4 = 4, 98 99 RTW89_CH_6G_BAND_IDX0, /* Low */ 100 RTW89_CH_6G_BAND_IDX1, /* Low */ 101 RTW89_CH_6G_BAND_IDX2, /* Mid */ 102 RTW89_CH_6G_BAND_IDX3, /* Mid */ 103 RTW89_CH_6G_BAND_IDX4, /* High */ 104 RTW89_CH_6G_BAND_IDX5, /* High */ 105 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 106 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 107 108 RTW89_SUBBAND_NR, 109 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 110 }; 111 112 enum rtw89_gain_offset { 113 RTW89_GAIN_OFFSET_2G_CCK, 114 RTW89_GAIN_OFFSET_2G_OFDM, 115 RTW89_GAIN_OFFSET_5G_LOW, 116 RTW89_GAIN_OFFSET_5G_MID, 117 RTW89_GAIN_OFFSET_5G_HIGH, 118 RTW89_GAIN_OFFSET_6G_L0, 119 RTW89_GAIN_OFFSET_6G_L1, 120 RTW89_GAIN_OFFSET_6G_M0, 121 RTW89_GAIN_OFFSET_6G_M1, 122 RTW89_GAIN_OFFSET_6G_H0, 123 RTW89_GAIN_OFFSET_6G_H1, 124 RTW89_GAIN_OFFSET_6G_UH0, 125 RTW89_GAIN_OFFSET_6G_UH1, 126 127 RTW89_GAIN_OFFSET_NR, 128 }; 129 130 enum rtw89_hci_type { 131 RTW89_HCI_TYPE_PCIE, 132 RTW89_HCI_TYPE_USB, 133 RTW89_HCI_TYPE_SDIO, 134 135 RTW89_HCI_TYPE_NUM, 136 }; 137 138 enum rtw89_hci_dle_type { 139 RTW89_HCI_DLE_TYPE_PCIE, 140 RTW89_HCI_DLE_TYPE_USB2, 141 RTW89_HCI_DLE_TYPE_USB3, 142 RTW89_HCI_DLE_TYPE_SDIO, 143 144 RTW89_HCI_DLE_TYPE_NUM, 145 }; 146 147 enum rtw89_core_chip_id { 148 RTL8852A, 149 RTL8852B, 150 RTL8852BT, 151 RTL8852C, 152 RTL8851B, 153 RTL8922A, 154 }; 155 156 enum rtw89_chip_gen { 157 RTW89_CHIP_AX, 158 RTW89_CHIP_BE, 159 160 RTW89_CHIP_GEN_NUM, 161 }; 162 163 enum rtw89_cv { 164 CHIP_CAV, 165 CHIP_CBV, 166 CHIP_CCV, 167 CHIP_CDV, 168 CHIP_CEV, 169 CHIP_CFV, 170 CHIP_CV_MAX, 171 CHIP_CV_INVALID = CHIP_CV_MAX, 172 }; 173 174 enum rtw89_bacam_ver { 175 RTW89_BACAM_V0, 176 RTW89_BACAM_V1, 177 178 RTW89_BACAM_V0_EXT = 99, 179 }; 180 181 enum rtw89_core_tx_type { 182 RTW89_CORE_TX_TYPE_DATA, 183 RTW89_CORE_TX_TYPE_MGMT, 184 RTW89_CORE_TX_TYPE_FWCMD, 185 }; 186 187 enum rtw89_core_rx_type { 188 RTW89_CORE_RX_TYPE_WIFI = 0, 189 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 190 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 191 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 192 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 193 RTW89_CORE_RX_TYPE_SS2FW = 5, 194 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 195 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 196 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 197 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 198 RTW89_CORE_RX_TYPE_C2H = 10, 199 RTW89_CORE_RX_TYPE_CSI = 11, 200 RTW89_CORE_RX_TYPE_CQI = 12, 201 RTW89_CORE_RX_TYPE_H2C = 13, 202 RTW89_CORE_RX_TYPE_FWDL = 14, 203 }; 204 205 enum rtw89_txq_flags { 206 RTW89_TXQ_F_AMPDU = 0, 207 RTW89_TXQ_F_BLOCK_BA = 1, 208 RTW89_TXQ_F_FORBID_BA = 2, 209 }; 210 211 enum rtw89_net_type { 212 RTW89_NET_TYPE_NO_LINK = 0, 213 RTW89_NET_TYPE_AD_HOC = 1, 214 RTW89_NET_TYPE_INFRA = 2, 215 RTW89_NET_TYPE_AP_MODE = 3, 216 }; 217 218 enum rtw89_wifi_role { 219 RTW89_WIFI_ROLE_NONE, 220 RTW89_WIFI_ROLE_STATION, 221 RTW89_WIFI_ROLE_AP, 222 RTW89_WIFI_ROLE_AP_VLAN, 223 RTW89_WIFI_ROLE_ADHOC, 224 RTW89_WIFI_ROLE_ADHOC_MASTER, 225 RTW89_WIFI_ROLE_MESH_POINT, 226 RTW89_WIFI_ROLE_MONITOR, 227 RTW89_WIFI_ROLE_P2P_DEVICE, 228 RTW89_WIFI_ROLE_P2P_CLIENT, 229 RTW89_WIFI_ROLE_P2P_GO, 230 RTW89_WIFI_ROLE_NAN, 231 RTW89_WIFI_ROLE_MLME_MAX 232 }; 233 234 enum rtw89_upd_mode { 235 RTW89_ROLE_CREATE, 236 RTW89_ROLE_REMOVE, 237 RTW89_ROLE_TYPE_CHANGE, 238 RTW89_ROLE_INFO_CHANGE, 239 RTW89_ROLE_CON_DISCONN, 240 RTW89_ROLE_BAND_SW, 241 RTW89_ROLE_FW_RESTORE, 242 }; 243 244 enum rtw89_self_role { 245 RTW89_SELF_ROLE_CLIENT, 246 RTW89_SELF_ROLE_AP, 247 RTW89_SELF_ROLE_AP_CLIENT 248 }; 249 250 enum rtw89_msk_sO_el { 251 RTW89_NO_MSK, 252 RTW89_SMA, 253 RTW89_TMA, 254 RTW89_BSSID 255 }; 256 257 enum rtw89_sch_tx_sel { 258 RTW89_SCH_TX_SEL_ALL, 259 RTW89_SCH_TX_SEL_HIQ, 260 RTW89_SCH_TX_SEL_MG0, 261 RTW89_SCH_TX_SEL_MACID, 262 }; 263 264 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 265 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 266 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 267 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 268 */ 269 enum rtw89_add_cam_sec_mode { 270 RTW89_ADDR_CAM_SEC_NONE = 0, 271 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 272 RTW89_ADDR_CAM_SEC_NORMAL = 2, 273 RTW89_ADDR_CAM_SEC_4GROUP = 3, 274 }; 275 276 enum rtw89_sec_key_type { 277 RTW89_SEC_KEY_TYPE_NONE = 0, 278 RTW89_SEC_KEY_TYPE_WEP40 = 1, 279 RTW89_SEC_KEY_TYPE_WEP104 = 2, 280 RTW89_SEC_KEY_TYPE_TKIP = 3, 281 RTW89_SEC_KEY_TYPE_WAPI = 4, 282 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 283 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 284 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 285 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 286 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 287 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 288 }; 289 290 enum rtw89_port { 291 RTW89_PORT_0 = 0, 292 RTW89_PORT_1 = 1, 293 RTW89_PORT_2 = 2, 294 RTW89_PORT_3 = 3, 295 RTW89_PORT_4 = 4, 296 RTW89_PORT_NUM 297 }; 298 299 enum rtw89_band { 300 RTW89_BAND_2G = 0, 301 RTW89_BAND_5G = 1, 302 RTW89_BAND_6G = 2, 303 RTW89_BAND_NUM, 304 }; 305 306 enum rtw89_hw_rate { 307 RTW89_HW_RATE_CCK1 = 0x0, 308 RTW89_HW_RATE_CCK2 = 0x1, 309 RTW89_HW_RATE_CCK5_5 = 0x2, 310 RTW89_HW_RATE_CCK11 = 0x3, 311 RTW89_HW_RATE_OFDM6 = 0x4, 312 RTW89_HW_RATE_OFDM9 = 0x5, 313 RTW89_HW_RATE_OFDM12 = 0x6, 314 RTW89_HW_RATE_OFDM18 = 0x7, 315 RTW89_HW_RATE_OFDM24 = 0x8, 316 RTW89_HW_RATE_OFDM36 = 0x9, 317 RTW89_HW_RATE_OFDM48 = 0xA, 318 RTW89_HW_RATE_OFDM54 = 0xB, 319 RTW89_HW_RATE_MCS0 = 0x80, 320 RTW89_HW_RATE_MCS1 = 0x81, 321 RTW89_HW_RATE_MCS2 = 0x82, 322 RTW89_HW_RATE_MCS3 = 0x83, 323 RTW89_HW_RATE_MCS4 = 0x84, 324 RTW89_HW_RATE_MCS5 = 0x85, 325 RTW89_HW_RATE_MCS6 = 0x86, 326 RTW89_HW_RATE_MCS7 = 0x87, 327 RTW89_HW_RATE_MCS8 = 0x88, 328 RTW89_HW_RATE_MCS9 = 0x89, 329 RTW89_HW_RATE_MCS10 = 0x8A, 330 RTW89_HW_RATE_MCS11 = 0x8B, 331 RTW89_HW_RATE_MCS12 = 0x8C, 332 RTW89_HW_RATE_MCS13 = 0x8D, 333 RTW89_HW_RATE_MCS14 = 0x8E, 334 RTW89_HW_RATE_MCS15 = 0x8F, 335 RTW89_HW_RATE_MCS16 = 0x90, 336 RTW89_HW_RATE_MCS17 = 0x91, 337 RTW89_HW_RATE_MCS18 = 0x92, 338 RTW89_HW_RATE_MCS19 = 0x93, 339 RTW89_HW_RATE_MCS20 = 0x94, 340 RTW89_HW_RATE_MCS21 = 0x95, 341 RTW89_HW_RATE_MCS22 = 0x96, 342 RTW89_HW_RATE_MCS23 = 0x97, 343 RTW89_HW_RATE_MCS24 = 0x98, 344 RTW89_HW_RATE_MCS25 = 0x99, 345 RTW89_HW_RATE_MCS26 = 0x9A, 346 RTW89_HW_RATE_MCS27 = 0x9B, 347 RTW89_HW_RATE_MCS28 = 0x9C, 348 RTW89_HW_RATE_MCS29 = 0x9D, 349 RTW89_HW_RATE_MCS30 = 0x9E, 350 RTW89_HW_RATE_MCS31 = 0x9F, 351 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 352 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 353 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 354 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 355 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 356 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 357 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 358 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 359 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 360 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 361 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 362 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 363 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 364 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 365 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 366 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 367 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 368 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 369 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 370 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 371 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 372 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 373 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 374 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 375 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 376 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 377 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 378 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 379 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 380 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 381 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 382 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 383 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 384 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 385 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 386 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 387 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 388 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 389 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 390 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 391 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 392 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 393 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 394 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 395 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 396 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 397 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 398 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 399 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 400 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 401 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 402 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 403 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 404 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 405 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 406 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 407 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 408 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 409 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 410 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 411 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 412 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 413 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 414 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 415 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 416 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 417 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 418 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 419 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 420 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 421 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 422 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 423 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 424 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 425 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 426 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 427 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 428 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 429 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 430 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 431 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 432 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 433 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 434 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 435 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 436 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 437 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 438 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 439 440 RTW89_HW_RATE_V1_MCS0 = 0x100, 441 RTW89_HW_RATE_V1_MCS1 = 0x101, 442 RTW89_HW_RATE_V1_MCS2 = 0x102, 443 RTW89_HW_RATE_V1_MCS3 = 0x103, 444 RTW89_HW_RATE_V1_MCS4 = 0x104, 445 RTW89_HW_RATE_V1_MCS5 = 0x105, 446 RTW89_HW_RATE_V1_MCS6 = 0x106, 447 RTW89_HW_RATE_V1_MCS7 = 0x107, 448 RTW89_HW_RATE_V1_MCS8 = 0x108, 449 RTW89_HW_RATE_V1_MCS9 = 0x109, 450 RTW89_HW_RATE_V1_MCS10 = 0x10A, 451 RTW89_HW_RATE_V1_MCS11 = 0x10B, 452 RTW89_HW_RATE_V1_MCS12 = 0x10C, 453 RTW89_HW_RATE_V1_MCS13 = 0x10D, 454 RTW89_HW_RATE_V1_MCS14 = 0x10E, 455 RTW89_HW_RATE_V1_MCS15 = 0x10F, 456 RTW89_HW_RATE_V1_MCS16 = 0x110, 457 RTW89_HW_RATE_V1_MCS17 = 0x111, 458 RTW89_HW_RATE_V1_MCS18 = 0x112, 459 RTW89_HW_RATE_V1_MCS19 = 0x113, 460 RTW89_HW_RATE_V1_MCS20 = 0x114, 461 RTW89_HW_RATE_V1_MCS21 = 0x115, 462 RTW89_HW_RATE_V1_MCS22 = 0x116, 463 RTW89_HW_RATE_V1_MCS23 = 0x117, 464 RTW89_HW_RATE_V1_MCS24 = 0x118, 465 RTW89_HW_RATE_V1_MCS25 = 0x119, 466 RTW89_HW_RATE_V1_MCS26 = 0x11A, 467 RTW89_HW_RATE_V1_MCS27 = 0x11B, 468 RTW89_HW_RATE_V1_MCS28 = 0x11C, 469 RTW89_HW_RATE_V1_MCS29 = 0x11D, 470 RTW89_HW_RATE_V1_MCS30 = 0x11E, 471 RTW89_HW_RATE_V1_MCS31 = 0x11F, 472 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 473 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 474 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 475 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 476 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 477 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 478 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 479 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 480 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 481 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 482 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 483 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 484 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 485 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 486 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 487 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 488 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 489 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 490 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 491 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 492 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 493 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 494 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 495 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 496 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 497 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 498 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 499 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 500 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 501 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 502 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 503 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 504 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 505 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 506 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 507 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 508 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 509 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 510 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 511 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 512 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 513 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 514 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 515 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 516 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 517 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 518 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 519 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 520 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 521 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 522 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 523 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 524 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 525 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 526 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 527 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 528 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 529 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 530 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 531 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 532 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 533 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 534 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 535 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 536 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 537 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 538 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 539 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 540 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 541 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 542 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 543 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 544 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 545 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 546 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 547 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 548 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 549 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 550 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 551 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 552 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 553 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 554 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 555 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 556 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 557 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 558 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 559 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 560 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 561 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 562 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 563 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 564 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 565 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 566 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 567 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 570 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 571 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 572 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 573 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 574 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 575 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 576 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 577 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 578 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 579 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 580 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 581 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 582 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 583 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 584 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 585 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 586 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 587 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 588 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 589 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 590 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 591 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 592 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 593 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 594 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 595 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 596 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 597 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 598 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 599 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 600 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 601 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 602 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 603 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 604 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 605 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 606 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 607 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 608 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 609 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 610 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 611 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 612 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 613 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 614 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 615 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 616 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 617 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 618 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 619 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 620 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 621 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 622 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 623 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 624 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 625 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 626 627 RTW89_HW_RATE_NR, 628 RTW89_HW_RATE_INVAL, 629 630 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 631 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 632 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 633 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 634 }; 635 636 /* 2G channels, 637 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 638 */ 639 #define RTW89_2G_CH_NUM 14 640 641 /* 5G channels, 642 * 36, 38, 40, 42, 44, 46, 48, 50, 643 * 52, 54, 56, 58, 60, 62, 64, 644 * 100, 102, 104, 106, 108, 110, 112, 114, 645 * 116, 118, 120, 122, 124, 126, 128, 130, 646 * 132, 134, 136, 138, 140, 142, 144, 647 * 149, 151, 153, 155, 157, 159, 161, 163, 648 * 165, 167, 169, 171, 173, 175, 177 649 */ 650 #define RTW89_5G_CH_NUM 53 651 652 /* 6G channels, 653 * 1, 3, 5, 7, 9, 11, 13, 15, 654 * 17, 19, 21, 23, 25, 27, 29, 33, 655 * 35, 37, 39, 41, 43, 45, 47, 49, 656 * 51, 53, 55, 57, 59, 61, 65, 67, 657 * 69, 71, 73, 75, 77, 79, 81, 83, 658 * 85, 87, 89, 91, 93, 97, 99, 101, 659 * 103, 105, 107, 109, 111, 113, 115, 117, 660 * 119, 121, 123, 125, 129, 131, 133, 135, 661 * 137, 139, 141, 143, 145, 147, 149, 151, 662 * 153, 155, 157, 161, 163, 165, 167, 169, 663 * 171, 173, 175, 177, 179, 181, 183, 185, 664 * 187, 189, 193, 195, 197, 199, 201, 203, 665 * 205, 207, 209, 211, 213, 215, 217, 219, 666 * 221, 225, 227, 229, 231, 233, 235, 237, 667 * 239, 241, 243, 245, 247, 249, 251, 253, 668 */ 669 #define RTW89_6G_CH_NUM 120 670 671 enum rtw89_rate_section { 672 RTW89_RS_CCK, 673 RTW89_RS_OFDM, 674 RTW89_RS_MCS, /* for HT/VHT/HE */ 675 RTW89_RS_HEDCM, 676 RTW89_RS_OFFSET, 677 RTW89_RS_NUM, 678 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 679 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 680 }; 681 682 enum rtw89_rate_offset_indexes { 683 RTW89_RATE_OFFSET_HE, 684 RTW89_RATE_OFFSET_VHT, 685 RTW89_RATE_OFFSET_HT, 686 RTW89_RATE_OFFSET_OFDM, 687 RTW89_RATE_OFFSET_CCK, 688 RTW89_RATE_OFFSET_DLRU_EHT, 689 RTW89_RATE_OFFSET_DLRU_HE, 690 RTW89_RATE_OFFSET_EHT, 691 __RTW89_RATE_OFFSET_NUM, 692 693 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 694 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 695 }; 696 697 enum rtw89_rate_num { 698 RTW89_RATE_CCK_NUM = 4, 699 RTW89_RATE_OFDM_NUM = 8, 700 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 701 702 RTW89_RATE_MCS_NUM_AX = 12, 703 RTW89_RATE_MCS_NUM_BE = 16, 704 __RTW89_RATE_MCS_NUM = 16, 705 }; 706 707 enum rtw89_nss { 708 RTW89_NSS_1 = 0, 709 RTW89_NSS_2 = 1, 710 /* HE DCM only support 1ss and 2ss */ 711 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 712 RTW89_NSS_3 = 2, 713 RTW89_NSS_4 = 3, 714 RTW89_NSS_NUM, 715 }; 716 717 enum rtw89_ntx { 718 RTW89_1TX = 0, 719 RTW89_2TX = 1, 720 RTW89_NTX_NUM, 721 }; 722 723 enum rtw89_beamforming_type { 724 RTW89_NONBF = 0, 725 RTW89_BF = 1, 726 RTW89_BF_NUM, 727 }; 728 729 enum rtw89_ofdma_type { 730 RTW89_NON_OFDMA = 0, 731 RTW89_OFDMA = 1, 732 RTW89_OFDMA_NUM, 733 }; 734 735 /* neither insert new in the middle, nor change any given definition */ 736 enum rtw89_regulation_type { 737 RTW89_WW = 0, 738 RTW89_ETSI = 1, 739 RTW89_FCC = 2, 740 RTW89_MKK = 3, 741 RTW89_NA = 4, 742 RTW89_IC = 5, 743 RTW89_KCC = 6, 744 RTW89_ACMA = 7, 745 RTW89_NCC = 8, 746 RTW89_MEXICO = 9, 747 RTW89_CHILE = 10, 748 RTW89_UKRAINE = 11, 749 RTW89_CN = 12, 750 RTW89_QATAR = 13, 751 RTW89_UK = 14, 752 RTW89_THAILAND = 15, 753 RTW89_REGD_NUM, 754 }; 755 756 enum rtw89_reg_6ghz_power { 757 RTW89_REG_6GHZ_POWER_VLP = 0, 758 RTW89_REG_6GHZ_POWER_LPI = 1, 759 RTW89_REG_6GHZ_POWER_STD = 2, 760 761 NUM_OF_RTW89_REG_6GHZ_POWER, 762 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 763 }; 764 765 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 766 767 /* calculate based on ieee80211 Transmit Power Envelope */ 768 struct rtw89_reg_6ghz_tpe { 769 bool valid; 770 s8 constraint; /* unit: dBm */ 771 }; 772 773 enum rtw89_fw_pkt_ofld_type { 774 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 775 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 776 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 777 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 778 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 779 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 780 RTW89_PKT_OFLD_TYPE_NDP = 6, 781 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 782 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 783 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 784 RTW89_PKT_OFLD_TYPE_NUM, 785 }; 786 787 struct rtw89_txpwr_byrate { 788 s8 cck[RTW89_RATE_CCK_NUM]; 789 s8 ofdm[RTW89_RATE_OFDM_NUM]; 790 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 791 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 792 s8 offset[__RTW89_RATE_OFFSET_NUM]; 793 s8 trap; 794 }; 795 796 struct rtw89_rate_desc { 797 enum rtw89_nss nss; 798 enum rtw89_rate_section rs; 799 enum rtw89_ofdma_type ofdma; 800 u8 idx; 801 }; 802 803 #define PHY_STS_HDR_LEN 8 804 #define RF_PATH_MAX 4 805 #define RTW89_MAX_PPDU_CNT 8 806 struct rtw89_rx_phy_ppdu { 807 void *buf; 808 u32 len; 809 u8 rssi_avg; 810 u8 rssi[RF_PATH_MAX]; 811 u8 mac_id; 812 u8 chan_idx; 813 u8 phy_idx; 814 u8 ie; 815 u16 rate; 816 u8 rpl_avg; 817 u8 rpl_path[RF_PATH_MAX]; 818 u8 rpl_fd[RF_PATH_MAX]; 819 u8 bw_idx; 820 u8 rx_path_en; 821 struct { 822 bool has; 823 u8 avg_snr; 824 u8 evm_max; 825 u8 evm_min; 826 } ofdm; 827 bool has_data; 828 bool has_bcn; 829 bool ldpc; 830 bool stbc; 831 bool to_self; 832 bool valid; 833 bool hdr_2_en; 834 }; 835 836 enum rtw89_mac_idx { 837 RTW89_MAC_0 = 0, 838 RTW89_MAC_1 = 1, 839 RTW89_MAC_NUM, 840 }; 841 842 enum rtw89_phy_idx { 843 RTW89_PHY_0 = 0, 844 RTW89_PHY_1 = 1, 845 RTW89_PHY_NUM, 846 }; 847 848 #define __RTW89_MLD_MAX_LINK_NUM 2 849 #define RTW89_MLD_NON_STA_LINK_NUM 1 850 851 enum rtw89_chanctx_idx { 852 RTW89_CHANCTX_0 = 0, 853 RTW89_CHANCTX_1 = 1, 854 855 NUM_OF_RTW89_CHANCTX, 856 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 857 }; 858 859 enum rtw89_rf_path { 860 RF_PATH_A = 0, 861 RF_PATH_B = 1, 862 RF_PATH_C = 2, 863 RF_PATH_D = 3, 864 RF_PATH_AB, 865 RF_PATH_AC, 866 RF_PATH_AD, 867 RF_PATH_BC, 868 RF_PATH_BD, 869 RF_PATH_CD, 870 RF_PATH_ABC, 871 RF_PATH_ABD, 872 RF_PATH_ACD, 873 RF_PATH_BCD, 874 RF_PATH_ABCD, 875 }; 876 877 enum rtw89_rf_path_bit { 878 RF_A = BIT(0), 879 RF_B = BIT(1), 880 RF_C = BIT(2), 881 RF_D = BIT(3), 882 883 RF_AB = (RF_A | RF_B), 884 RF_AC = (RF_A | RF_C), 885 RF_AD = (RF_A | RF_D), 886 RF_BC = (RF_B | RF_C), 887 RF_BD = (RF_B | RF_D), 888 RF_CD = (RF_C | RF_D), 889 890 RF_ABC = (RF_A | RF_B | RF_C), 891 RF_ABD = (RF_A | RF_B | RF_D), 892 RF_ACD = (RF_A | RF_C | RF_D), 893 RF_BCD = (RF_B | RF_C | RF_D), 894 895 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 896 }; 897 898 enum rtw89_bandwidth { 899 RTW89_CHANNEL_WIDTH_20 = 0, 900 RTW89_CHANNEL_WIDTH_40 = 1, 901 RTW89_CHANNEL_WIDTH_80 = 2, 902 RTW89_CHANNEL_WIDTH_160 = 3, 903 RTW89_CHANNEL_WIDTH_320 = 4, 904 905 /* keep index order above */ 906 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 907 908 RTW89_CHANNEL_WIDTH_80_80 = 5, 909 RTW89_CHANNEL_WIDTH_5 = 6, 910 RTW89_CHANNEL_WIDTH_10 = 7, 911 }; 912 913 enum rtw89_ps_mode { 914 RTW89_PS_MODE_NONE = 0, 915 RTW89_PS_MODE_RFOFF = 1, 916 RTW89_PS_MODE_CLK_GATED = 2, 917 RTW89_PS_MODE_PWR_GATED = 3, 918 }; 919 920 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 921 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 922 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 923 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 924 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 925 926 enum rtw89_pe_duration { 927 RTW89_PE_DURATION_0 = 0, 928 RTW89_PE_DURATION_8 = 1, 929 RTW89_PE_DURATION_16 = 2, 930 RTW89_PE_DURATION_16_20 = 3, 931 }; 932 933 enum rtw89_ru_bandwidth { 934 RTW89_RU26 = 0, 935 RTW89_RU52 = 1, 936 RTW89_RU106 = 2, 937 RTW89_RU52_26 = 3, 938 RTW89_RU106_26 = 4, 939 RTW89_RU_NUM, 940 }; 941 942 enum rtw89_sc_offset { 943 RTW89_SC_DONT_CARE = 0, 944 RTW89_SC_20_UPPER = 1, 945 RTW89_SC_20_LOWER = 2, 946 RTW89_SC_20_UPMOST = 3, 947 RTW89_SC_20_LOWEST = 4, 948 RTW89_SC_20_UP2X = 5, 949 RTW89_SC_20_LOW2X = 6, 950 RTW89_SC_20_UP3X = 7, 951 RTW89_SC_20_LOW3X = 8, 952 RTW89_SC_40_UPPER = 9, 953 RTW89_SC_40_LOWER = 10, 954 }; 955 956 /* only mgd features can be added to the enum */ 957 enum rtw89_wow_flags { 958 RTW89_WOW_FLAG_EN_MAGIC_PKT, 959 RTW89_WOW_FLAG_EN_REKEY_PKT, 960 RTW89_WOW_FLAG_EN_DISCONNECT, 961 RTW89_WOW_FLAG_EN_PATTERN, 962 RTW89_WOW_FLAG_NUM, 963 }; 964 965 struct rtw89_chan { 966 u8 channel; 967 u8 primary_channel; 968 enum rtw89_band band_type; 969 enum rtw89_bandwidth band_width; 970 971 /* The follow-up are derived from the above. We must ensure that it 972 * is assigned correctly in rtw89_chan_create() if new one is added. 973 */ 974 u32 freq; 975 enum rtw89_subband subband_type; 976 enum rtw89_sc_offset pri_ch_idx; 977 u8 pri_sb_idx; 978 }; 979 980 struct rtw89_chan_rcd { 981 u8 prev_primary_channel; 982 enum rtw89_band prev_band_type; 983 bool band_changed; 984 }; 985 986 struct rtw89_channel_help_params { 987 u32 tx_en; 988 }; 989 990 struct rtw89_port_reg { 991 u32 port_cfg; 992 u32 tbtt_prohib; 993 u32 bcn_area; 994 u32 bcn_early; 995 u32 tbtt_early; 996 u32 tbtt_agg; 997 u32 bcn_space; 998 u32 bcn_forcetx; 999 u32 bcn_err_cnt; 1000 u32 bcn_err_flag; 1001 u32 dtim_ctrl; 1002 u32 tbtt_shift; 1003 u32 bcn_cnt_tmr; 1004 u32 tsftr_l; 1005 u32 tsftr_h; 1006 u32 md_tsft; 1007 u32 bss_color; 1008 u32 mbssid; 1009 u32 mbssid_drop; 1010 u32 tsf_sync; 1011 u32 ptcl_dbg; 1012 u32 ptcl_dbg_info; 1013 u32 bcn_drop_all; 1014 u32 bcn_psr_rpt; 1015 u32 hiq_win[RTW89_PORT_NUM]; 1016 }; 1017 1018 struct rtw89_txwd_body { 1019 __le32 dword0; 1020 __le32 dword1; 1021 __le32 dword2; 1022 __le32 dword3; 1023 __le32 dword4; 1024 __le32 dword5; 1025 } __packed; 1026 1027 struct rtw89_txwd_body_v1 { 1028 __le32 dword0; 1029 __le32 dword1; 1030 __le32 dword2; 1031 __le32 dword3; 1032 __le32 dword4; 1033 __le32 dword5; 1034 __le32 dword6; 1035 __le32 dword7; 1036 } __packed; 1037 1038 struct rtw89_txwd_body_v2 { 1039 __le32 dword0; 1040 __le32 dword1; 1041 __le32 dword2; 1042 __le32 dword3; 1043 __le32 dword4; 1044 __le32 dword5; 1045 __le32 dword6; 1046 __le32 dword7; 1047 } __packed; 1048 1049 struct rtw89_txwd_info { 1050 __le32 dword0; 1051 __le32 dword1; 1052 __le32 dword2; 1053 __le32 dword3; 1054 __le32 dword4; 1055 __le32 dword5; 1056 } __packed; 1057 1058 struct rtw89_txwd_info_v2 { 1059 __le32 dword0; 1060 __le32 dword1; 1061 __le32 dword2; 1062 __le32 dword3; 1063 __le32 dword4; 1064 __le32 dword5; 1065 __le32 dword6; 1066 __le32 dword7; 1067 } __packed; 1068 1069 struct rtw89_rx_desc_info { 1070 u16 pkt_size; 1071 u8 pkt_type; 1072 u8 drv_info_size; 1073 u8 phy_rpt_size; 1074 u8 hdr_cnv_size; 1075 u8 shift; 1076 u8 wl_hd_iv_len; 1077 bool long_rxdesc; 1078 bool bb_sel; 1079 bool mac_info_valid; 1080 u16 data_rate; 1081 u8 gi_ltf; 1082 u8 bw; 1083 u32 free_run_cnt; 1084 u8 user_id; 1085 bool sr_en; 1086 u8 ppdu_cnt; 1087 u8 ppdu_type; 1088 bool icv_err; 1089 bool crc32_err; 1090 bool hw_dec; 1091 bool sw_dec; 1092 bool addr1_match; 1093 u8 frag; 1094 u16 seq; 1095 u8 frame_type; 1096 u8 rx_pl_id; 1097 bool addr_cam_valid; 1098 u8 addr_cam_id; 1099 u8 sec_cam_id; 1100 u8 mac_id; 1101 u16 offset; 1102 u16 rxd_len; 1103 bool ready; 1104 u16 rssi; 1105 }; 1106 1107 struct rtw89_rxdesc_short { 1108 __le32 dword0; 1109 __le32 dword1; 1110 __le32 dword2; 1111 __le32 dword3; 1112 } __packed; 1113 1114 struct rtw89_rxdesc_short_v2 { 1115 __le32 dword0; 1116 __le32 dword1; 1117 __le32 dword2; 1118 __le32 dword3; 1119 __le32 dword4; 1120 __le32 dword5; 1121 } __packed; 1122 1123 struct rtw89_rxdesc_long { 1124 __le32 dword0; 1125 __le32 dword1; 1126 __le32 dword2; 1127 __le32 dword3; 1128 __le32 dword4; 1129 __le32 dword5; 1130 __le32 dword6; 1131 __le32 dword7; 1132 } __packed; 1133 1134 struct rtw89_rxdesc_long_v2 { 1135 __le32 dword0; 1136 __le32 dword1; 1137 __le32 dword2; 1138 __le32 dword3; 1139 __le32 dword4; 1140 __le32 dword5; 1141 __le32 dword6; 1142 __le32 dword7; 1143 __le32 dword8; 1144 __le32 dword9; 1145 } __packed; 1146 1147 struct rtw89_rxdesc_phy_rpt_v2 { 1148 __le32 dword0; 1149 __le32 dword1; 1150 } __packed; 1151 1152 struct rtw89_tx_desc_info { 1153 u16 pkt_size; 1154 u8 wp_offset; 1155 u8 mac_id; 1156 u8 qsel; 1157 u8 ch_dma; 1158 u8 hdr_llc_len; 1159 bool is_bmc; 1160 bool en_wd_info; 1161 bool wd_page; 1162 bool use_rate; 1163 bool dis_data_fb; 1164 bool tid_indicate; 1165 bool agg_en; 1166 bool bk; 1167 u8 ampdu_density; 1168 u8 ampdu_num; 1169 bool sec_en; 1170 u8 addr_info_nr; 1171 u8 sec_keyid; 1172 u8 sec_type; 1173 u8 sec_cam_idx; 1174 u8 sec_seq[6]; 1175 u16 data_rate; 1176 u16 data_retry_lowest_rate; 1177 bool fw_dl; 1178 u16 seq; 1179 bool a_ctrl_bsr; 1180 u8 hw_ssn_sel; 1181 #define RTW89_MGMT_HW_SSN_SEL 1 1182 u8 hw_seq_mode; 1183 #define RTW89_MGMT_HW_SEQ_MODE 1 1184 bool hiq; 1185 u8 port; 1186 bool er_cap; 1187 bool stbc; 1188 bool ldpc; 1189 bool upd_wlan_hdr; 1190 bool mlo; 1191 bool sw_mld; 1192 }; 1193 1194 struct rtw89_core_tx_request { 1195 enum rtw89_core_tx_type tx_type; 1196 1197 struct sk_buff *skb; 1198 struct ieee80211_vif *vif; 1199 struct ieee80211_sta *sta; 1200 struct rtw89_vif_link *rtwvif_link; 1201 struct rtw89_sta_link *rtwsta_link; 1202 struct rtw89_tx_desc_info desc_info; 1203 }; 1204 1205 struct rtw89_txq { 1206 struct list_head list; 1207 unsigned long flags; 1208 int wait_cnt; 1209 }; 1210 1211 struct rtw89_mac_ax_gnt { 1212 u8 gnt_bt_sw_en; 1213 u8 gnt_bt; 1214 u8 gnt_wl_sw_en; 1215 u8 gnt_wl; 1216 } __packed; 1217 1218 struct rtw89_mac_ax_wl_act { 1219 u8 wlan_act_en; 1220 u8 wlan_act; 1221 } __packed; 1222 1223 #define RTW89_MAC_AX_COEX_GNT_NR 2 1224 struct rtw89_mac_ax_coex_gnt { 1225 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1226 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1227 }; 1228 1229 enum rtw89_btc_ncnt { 1230 BTC_NCNT_POWER_ON = 0x0, 1231 BTC_NCNT_POWER_OFF, 1232 BTC_NCNT_INIT_COEX, 1233 BTC_NCNT_SCAN_START, 1234 BTC_NCNT_SCAN_FINISH, 1235 BTC_NCNT_SPECIAL_PACKET, 1236 BTC_NCNT_SWITCH_BAND, 1237 BTC_NCNT_RFK_TIMEOUT, 1238 BTC_NCNT_SHOW_COEX_INFO, 1239 BTC_NCNT_ROLE_INFO, 1240 BTC_NCNT_CONTROL, 1241 BTC_NCNT_RADIO_STATE, 1242 BTC_NCNT_CUSTOMERIZE, 1243 BTC_NCNT_WL_RFK, 1244 BTC_NCNT_WL_STA, 1245 BTC_NCNT_WL_STA_LAST, 1246 BTC_NCNT_FWINFO, 1247 BTC_NCNT_TIMER, 1248 BTC_NCNT_SWITCH_CHBW, 1249 BTC_NCNT_RESUME_DL_FW, 1250 BTC_NCNT_COUNTRYCODE, 1251 BTC_NCNT_NUM, 1252 }; 1253 1254 enum rtw89_btc_btinfo { 1255 BTC_BTINFO_L0 = 0, 1256 BTC_BTINFO_L1, 1257 BTC_BTINFO_L2, 1258 BTC_BTINFO_L3, 1259 BTC_BTINFO_H0, 1260 BTC_BTINFO_H1, 1261 BTC_BTINFO_H2, 1262 BTC_BTINFO_H3, 1263 BTC_BTINFO_MAX 1264 }; 1265 1266 enum rtw89_btc_dcnt { 1267 BTC_DCNT_RUN = 0x0, 1268 BTC_DCNT_CX_RUNINFO, 1269 BTC_DCNT_RPT, 1270 BTC_DCNT_RPT_HANG, 1271 BTC_DCNT_CYCLE, 1272 BTC_DCNT_CYCLE_HANG, 1273 BTC_DCNT_W1, 1274 BTC_DCNT_W1_HANG, 1275 BTC_DCNT_B1, 1276 BTC_DCNT_B1_HANG, 1277 BTC_DCNT_TDMA_NONSYNC, 1278 BTC_DCNT_SLOT_NONSYNC, 1279 BTC_DCNT_BTCNT_HANG, 1280 BTC_DCNT_BTTX_HANG, 1281 BTC_DCNT_WL_SLOT_DRIFT, 1282 BTC_DCNT_WL_STA_LAST, 1283 BTC_DCNT_BT_SLOT_DRIFT, 1284 BTC_DCNT_BT_SLOT_FLOOD, 1285 BTC_DCNT_FDDT_TRIG, 1286 BTC_DCNT_E2G, 1287 BTC_DCNT_E2G_HANG, 1288 BTC_DCNT_WL_FW_VER_MATCH, 1289 BTC_DCNT_NULL_TX_FAIL, 1290 BTC_DCNT_WL_STA_NTFY, 1291 BTC_DCNT_NUM, 1292 }; 1293 1294 enum rtw89_btc_wl_state_cnt { 1295 BTC_WCNT_SCANAP = 0x0, 1296 BTC_WCNT_DHCP, 1297 BTC_WCNT_EAPOL, 1298 BTC_WCNT_ARP, 1299 BTC_WCNT_SCBDUPDATE, 1300 BTC_WCNT_RFK_REQ, 1301 BTC_WCNT_RFK_GO, 1302 BTC_WCNT_RFK_REJECT, 1303 BTC_WCNT_RFK_TIMEOUT, 1304 BTC_WCNT_CH_UPDATE, 1305 BTC_WCNT_DBCC_ALL_2G, 1306 BTC_WCNT_DBCC_CHG, 1307 BTC_WCNT_RX_OK_LAST, 1308 BTC_WCNT_RX_OK_LAST2S, 1309 BTC_WCNT_RX_ERR_LAST, 1310 BTC_WCNT_RX_ERR_LAST2S, 1311 BTC_WCNT_RX_LAST, 1312 BTC_WCNT_NUM 1313 }; 1314 1315 enum rtw89_btc_bt_state_cnt { 1316 BTC_BCNT_RETRY = 0x0, 1317 BTC_BCNT_REINIT, 1318 BTC_BCNT_REENABLE, 1319 BTC_BCNT_SCBDREAD, 1320 BTC_BCNT_RELINK, 1321 BTC_BCNT_IGNOWL, 1322 BTC_BCNT_INQPAG, 1323 BTC_BCNT_INQ, 1324 BTC_BCNT_PAGE, 1325 BTC_BCNT_ROLESW, 1326 BTC_BCNT_AFH, 1327 BTC_BCNT_INFOUPDATE, 1328 BTC_BCNT_INFOSAME, 1329 BTC_BCNT_SCBDUPDATE, 1330 BTC_BCNT_HIPRI_TX, 1331 BTC_BCNT_HIPRI_RX, 1332 BTC_BCNT_LOPRI_TX, 1333 BTC_BCNT_LOPRI_RX, 1334 BTC_BCNT_POLUT, 1335 BTC_BCNT_POLUT_NOW, 1336 BTC_BCNT_POLUT_DIFF, 1337 BTC_BCNT_RATECHG, 1338 BTC_BCNT_BTTXPWR_UPDATE, 1339 BTC_BCNT_NUM, 1340 }; 1341 1342 enum rtw89_btc_bt_profile { 1343 BTC_BT_NOPROFILE = 0, 1344 BTC_BT_HFP = BIT(0), 1345 BTC_BT_HID = BIT(1), 1346 BTC_BT_A2DP = BIT(2), 1347 BTC_BT_PAN = BIT(3), 1348 BTC_PROFILE_MAX = 4, 1349 }; 1350 1351 struct rtw89_btc_ant_info { 1352 u8 type; /* shared, dedicated */ 1353 u8 num; 1354 u8 isolation; 1355 1356 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1357 u8 diversity: 1; 1358 u8 btg_pos: 2; 1359 u8 stream_cnt: 4; 1360 }; 1361 1362 struct rtw89_btc_ant_info_v7 { 1363 u8 type; /* shared, dedicated(non-shared) */ 1364 u8 num; /* antenna count */ 1365 u8 isolation; 1366 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1367 1368 u8 diversity; /* only for wifi use 1-antenna */ 1369 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1370 u8 stream_cnt; /* spatial_stream count */ 1371 u8 rsvd; 1372 } __packed; 1373 1374 enum rtw89_tfc_dir { 1375 RTW89_TFC_UL, 1376 RTW89_TFC_DL, 1377 }; 1378 1379 struct rtw89_btc_wl_smap { 1380 u32 busy: 1; 1381 u32 scan: 1; 1382 u32 connecting: 1; 1383 u32 roaming: 1; 1384 u32 dbccing: 1; 1385 u32 _4way: 1; 1386 u32 rf_off: 1; 1387 u32 lps: 2; 1388 u32 ips: 1; 1389 u32 init_ok: 1; 1390 u32 traffic_dir : 2; 1391 u32 rf_off_pre: 1; 1392 u32 lps_pre: 2; 1393 u32 lps_exiting: 1; 1394 u32 emlsr: 1; 1395 }; 1396 1397 enum rtw89_tfc_interval { 1398 RTW89_TFC_INTERVAL_100MS, 1399 RTW89_TFC_INTERVAL_2SEC, 1400 }; 1401 1402 enum rtw89_tfc_lv { 1403 RTW89_TFC_IDLE, 1404 RTW89_TFC_ULTRA_LOW, 1405 RTW89_TFC_LOW, 1406 RTW89_TFC_MID, 1407 RTW89_TFC_HIGH, 1408 }; 1409 1410 DECLARE_EWMA(tp, 10, 2); 1411 1412 struct rtw89_traffic_stats { 1413 /* units in bytes */ 1414 u64 tx_unicast; 1415 u64 rx_unicast; 1416 u32 tx_avg_len; 1417 u32 rx_avg_len; 1418 1419 /* count for packets */ 1420 u64 tx_cnt; 1421 u64 rx_cnt; 1422 1423 /* units in Mbps */ 1424 u32 tx_throughput; 1425 u32 rx_throughput; 1426 u32 tx_throughput_raw; 1427 u32 rx_throughput_raw; 1428 1429 u32 rx_tf_acc; 1430 u32 rx_tf_periodic; 1431 1432 enum rtw89_tfc_lv tx_tfc_lv; 1433 enum rtw89_tfc_lv rx_tfc_lv; 1434 struct ewma_tp tx_ewma_tp; 1435 struct ewma_tp rx_ewma_tp; 1436 1437 u16 tx_rate; 1438 u16 rx_rate; 1439 }; 1440 1441 struct rtw89_btc_chdef { 1442 u8 center_ch; 1443 u8 band; 1444 u8 chan; 1445 enum rtw89_sc_offset offset; 1446 enum rtw89_bandwidth bw; 1447 }; 1448 1449 struct rtw89_btc_statistic { 1450 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1451 struct rtw89_traffic_stats traffic; 1452 }; 1453 1454 #define BTC_WL_RSSI_THMAX 4 1455 1456 struct rtw89_btc_wl_link_info { 1457 struct rtw89_btc_chdef chdef; 1458 struct rtw89_btc_statistic stat; 1459 enum rtw89_tfc_dir dir; 1460 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1461 u8 mac_addr[ETH_ALEN]; 1462 u8 busy; 1463 u8 ch; 1464 u8 bw; 1465 u8 band; 1466 u8 role; 1467 u8 pid; 1468 u8 phy; 1469 u8 dtim_period; 1470 u8 mode; 1471 u8 tx_1ss_limit; 1472 1473 u8 mac_id; 1474 u8 tx_retry; 1475 1476 u32 bcn_period; 1477 u32 busy_t; 1478 u32 tx_time; 1479 u32 client_cnt; 1480 u32 rx_rate_drop_cnt; 1481 u32 noa_duration; 1482 1483 u32 active: 1; 1484 u32 noa: 1; 1485 u32 client_ps: 1; 1486 u32 connected: 2; 1487 }; 1488 1489 union rtw89_btc_wl_state_map { 1490 u32 val; 1491 struct rtw89_btc_wl_smap map; 1492 }; 1493 1494 struct rtw89_btc_bt_hfp_desc { 1495 u32 exist: 1; 1496 u32 type: 2; 1497 u32 rsvd: 29; 1498 }; 1499 1500 struct rtw89_btc_bt_hid_desc { 1501 u32 exist: 1; 1502 u32 slot_info: 2; 1503 u32 pair_cnt: 2; 1504 u32 type: 8; 1505 u32 rsvd: 19; 1506 }; 1507 1508 struct rtw89_btc_bt_a2dp_desc { 1509 u8 exist: 1; 1510 u8 exist_last: 1; 1511 u8 play_latency: 1; 1512 u8 type: 3; 1513 u8 active: 1; 1514 u8 sink: 1; 1515 u32 handle_update: 1; 1516 u32 devinfo_query: 1; 1517 u32 no_empty_streak_2s: 8; 1518 u32 no_empty_streak_max: 8; 1519 u32 rsvd: 6; 1520 1521 u8 bitpool; 1522 u16 vendor_id; 1523 u32 device_name; 1524 u32 flush_time; 1525 }; 1526 1527 struct rtw89_btc_bt_pan_desc { 1528 u32 exist: 1; 1529 u32 type: 1; 1530 u32 active: 1; 1531 u32 rsvd: 29; 1532 }; 1533 1534 struct rtw89_btc_bt_rfk_info { 1535 u32 run: 1; 1536 u32 req: 1; 1537 u32 timeout: 1; 1538 u32 rsvd: 29; 1539 }; 1540 1541 union rtw89_btc_bt_rfk_info_map { 1542 u32 val; 1543 struct rtw89_btc_bt_rfk_info map; 1544 }; 1545 1546 struct rtw89_btc_bt_ver_info { 1547 u32 fw_coex; /* match with which coex_ver */ 1548 u32 fw; 1549 }; 1550 1551 struct rtw89_btc_bool_sta_chg { 1552 u32 now: 1; 1553 u32 last: 1; 1554 u32 remain: 1; 1555 u32 srvd: 29; 1556 }; 1557 1558 struct rtw89_btc_u8_sta_chg { 1559 u8 now; 1560 u8 last; 1561 u8 remain; 1562 u8 rsvd; 1563 }; 1564 1565 struct rtw89_btc_wl_scan_info { 1566 u8 band[RTW89_PHY_NUM]; 1567 u8 phy_map; 1568 u8 rsvd; 1569 }; 1570 1571 struct rtw89_btc_wl_dbcc_info { 1572 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1573 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1574 u8 real_band[RTW89_PHY_NUM]; 1575 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1576 }; 1577 1578 struct rtw89_btc_wl_mlo_info { 1579 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */ 1580 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */ 1581 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */ 1582 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */ 1583 1584 u8 wtype; /* enum phl_mr_wtype */ 1585 u8 mrcx_mode; 1586 u8 mrcx_act_hwb_map; 1587 u8 mrcx_bt_slot_rsp; 1588 1589 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */ 1590 u8 mlo_en; /* MLO enable */ 1591 u8 mlo_adie; /* a-die count */ 1592 u8 dual_hw_band_en; /* both 2 HW-band link exist */ 1593 1594 u32 link_status; /* enum mlo_dbcc_mode_type */ 1595 }; 1596 1597 struct rtw89_btc_wl_active_role { 1598 u8 connected: 1; 1599 u8 pid: 3; 1600 u8 phy: 1; 1601 u8 noa: 1; 1602 u8 band: 2; 1603 1604 u8 client_ps: 1; 1605 u8 bw: 7; 1606 1607 u8 role; 1608 u8 ch; 1609 1610 u16 tx_lvl; 1611 u16 rx_lvl; 1612 u16 tx_rate; 1613 u16 rx_rate; 1614 }; 1615 1616 struct rtw89_btc_wl_active_role_v1 { 1617 u8 connected: 1; 1618 u8 pid: 3; 1619 u8 phy: 1; 1620 u8 noa: 1; 1621 u8 band: 2; 1622 1623 u8 client_ps: 1; 1624 u8 bw: 7; 1625 1626 u8 role; 1627 u8 ch; 1628 1629 u16 tx_lvl; 1630 u16 rx_lvl; 1631 u16 tx_rate; 1632 u16 rx_rate; 1633 1634 u32 noa_duration; /* ms */ 1635 }; 1636 1637 struct rtw89_btc_wl_active_role_v2 { 1638 u8 connected: 1; 1639 u8 pid: 3; 1640 u8 phy: 1; 1641 u8 noa: 1; 1642 u8 band: 2; 1643 1644 u8 client_ps: 1; 1645 u8 bw: 7; 1646 1647 u8 role; 1648 u8 ch; 1649 1650 u32 noa_duration; /* ms */ 1651 }; 1652 1653 struct rtw89_btc_wl_active_role_v7 { 1654 u8 connected; 1655 u8 pid; 1656 u8 phy; 1657 u8 noa; 1658 1659 u8 band; 1660 u8 client_ps; 1661 u8 bw; 1662 u8 role; 1663 1664 u8 ch; 1665 u8 noa_dur; 1666 u8 client_cnt; 1667 u8 rsvd2; 1668 } __packed; 1669 1670 struct rtw89_btc_wl_role_info_bpos { 1671 u16 none: 1; 1672 u16 station: 1; 1673 u16 ap: 1; 1674 u16 vap: 1; 1675 u16 adhoc: 1; 1676 u16 adhoc_master: 1; 1677 u16 mesh: 1; 1678 u16 moniter: 1; 1679 u16 p2p_device: 1; 1680 u16 p2p_gc: 1; 1681 u16 p2p_go: 1; 1682 u16 nan: 1; 1683 }; 1684 1685 struct rtw89_btc_wl_scc_ctrl { 1686 u8 null_role1; 1687 u8 null_role2; 1688 u8 ebt_null; /* if tx null at EBT slot */ 1689 }; 1690 1691 union rtw89_btc_wl_role_info_map { 1692 u16 val; 1693 struct rtw89_btc_wl_role_info_bpos role; 1694 }; 1695 1696 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1697 u8 connect_cnt; 1698 u8 link_mode; 1699 union rtw89_btc_wl_role_info_map role_map; 1700 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1701 }; 1702 1703 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1704 u8 connect_cnt; 1705 u8 link_mode; 1706 union rtw89_btc_wl_role_info_map role_map; 1707 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1708 u32 mrole_type; /* btc_wl_mrole_type */ 1709 u32 mrole_noa_duration; /* ms */ 1710 1711 u32 dbcc_en: 1; 1712 u32 dbcc_chg: 1; 1713 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1714 u32 link_mode_chg: 1; 1715 u32 rsvd: 27; 1716 }; 1717 1718 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1719 u8 connect_cnt; 1720 u8 link_mode; 1721 union rtw89_btc_wl_role_info_map role_map; 1722 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1723 u32 mrole_type; /* btc_wl_mrole_type */ 1724 u32 mrole_noa_duration; /* ms */ 1725 1726 u32 dbcc_en: 1; 1727 u32 dbcc_chg: 1; 1728 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1729 u32 link_mode_chg: 1; 1730 u32 rsvd: 27; 1731 }; 1732 1733 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1734 u8 connected; 1735 u8 pid; 1736 u8 phy; 1737 u8 noa; 1738 1739 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1740 u8 active; /* 0:rlink is under doze */ 1741 u8 bw; /* enum channel_width */ 1742 u8 role; /*enum role_type */ 1743 1744 u8 ch; 1745 u8 noa_dur; /* ms */ 1746 u8 client_cnt; /* for Role = P2P-Go/AP */ 1747 u8 mode; /* wifi protocol */ 1748 } __packed; 1749 1750 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1751 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1752 u8 connect_cnt; 1753 u8 link_mode; 1754 u8 link_mode_chg; 1755 u8 p2p_2g; 1756 1757 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1758 1759 u32 role_map; 1760 u32 mrole_type; /* btc_wl_mrole_type */ 1761 u32 mrole_noa_duration; /* ms */ 1762 u32 dbcc_en; 1763 u32 dbcc_chg; 1764 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1765 } __packed; 1766 1767 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1768 u8 connect_cnt; 1769 u8 link_mode; 1770 u8 link_mode_chg; 1771 u8 p2p_2g; 1772 1773 u8 pta_req_band; 1774 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1775 u8 dbcc_chg; 1776 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1777 1778 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1779 1780 u32 role_map; 1781 u32 mrole_type; /* btc_wl_mrole_type */ 1782 u32 mrole_noa_duration; /* ms */ 1783 } __packed; 1784 1785 struct rtw89_btc_wl_ver_info { 1786 u32 fw_coex; /* match with which coex_ver */ 1787 u32 fw; 1788 u32 mac; 1789 u32 bb; 1790 u32 rf; 1791 }; 1792 1793 struct rtw89_btc_wl_afh_info { 1794 u8 en; 1795 u8 ch; 1796 u8 bw; 1797 u8 rsvd; 1798 } __packed; 1799 1800 struct rtw89_btc_wl_rfk_info { 1801 u32 state: 2; 1802 u32 path_map: 4; 1803 u32 phy_map: 2; 1804 u32 band: 2; 1805 u32 type: 8; 1806 u32 con_rfk: 1; 1807 u32 rsvd: 13; 1808 1809 u32 start_time; 1810 u32 proc_time; 1811 }; 1812 1813 struct rtw89_btc_bt_smap { 1814 u32 connect: 1; 1815 u32 ble_connect: 1; 1816 u32 acl_busy: 1; 1817 u32 sco_busy: 1; 1818 u32 mesh_busy: 1; 1819 u32 inq_pag: 1; 1820 }; 1821 1822 union rtw89_btc_bt_state_map { 1823 u32 val; 1824 struct rtw89_btc_bt_smap map; 1825 }; 1826 1827 #define BTC_BT_RSSI_THMAX 4 1828 #define BTC_BT_AFH_GROUP 12 1829 #define BTC_BT_AFH_LE_GROUP 5 1830 1831 struct rtw89_btc_bt_txpwr_desc { 1832 s8 br_dbm; 1833 s8 le_dbm; 1834 u8 br_gain_index; 1835 u8 le_gain_index; 1836 }; 1837 1838 struct rtw89_btc_bt_link_info { 1839 struct rtw89_btc_u8_sta_chg profile_cnt; 1840 struct rtw89_btc_bool_sta_chg multi_link; 1841 struct rtw89_btc_bool_sta_chg relink; 1842 struct rtw89_btc_bt_hfp_desc hfp_desc; 1843 struct rtw89_btc_bt_hid_desc hid_desc; 1844 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1845 struct rtw89_btc_bt_pan_desc pan_desc; 1846 union rtw89_btc_bt_state_map status; 1847 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc; 1848 1849 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1850 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1851 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1852 u8 afh_map[BTC_BT_AFH_GROUP]; 1853 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1854 1855 u32 role_sw: 1; 1856 u32 slave_role: 1; 1857 u32 afh_update: 1; 1858 u32 cqddr: 1; 1859 u32 rssi: 8; 1860 u32 tx_3m: 1; 1861 u32 rsvd: 19; 1862 }; 1863 1864 struct rtw89_btc_3rdcx_info { 1865 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1866 u8 hw_coex; 1867 u16 rsvd; 1868 }; 1869 1870 struct rtw89_btc_dm_emap { 1871 u32 init: 1; 1872 u32 pta_owner: 1; 1873 u32 wl_rfk_timeout: 1; 1874 u32 bt_rfk_timeout: 1; 1875 u32 wl_fw_hang: 1; 1876 u32 cycle_hang: 1; 1877 u32 w1_hang: 1; 1878 u32 b1_hang: 1; 1879 u32 tdma_no_sync: 1; 1880 u32 slot_no_sync: 1; 1881 u32 wl_slot_drift: 1; 1882 u32 bt_slot_drift: 1; 1883 u32 role_num_mismatch: 1; 1884 u32 null1_tx_late: 1; 1885 u32 bt_afh_conflict: 1; 1886 u32 bt_leafh_conflict: 1; 1887 u32 bt_slot_flood: 1; 1888 u32 wl_e2g_hang: 1; 1889 u32 wl_ver_mismatch: 1; 1890 u32 bt_ver_mismatch: 1; 1891 u32 rfe_type0: 1; 1892 u32 h2c_buffer_over: 1; 1893 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1894 u32 wl_no_sta_ntfy: 1; 1895 1896 u32 h2c_bmap_mismatch: 1; 1897 u32 c2h_bmap_mismatch: 1; 1898 u32 h2c_struct_invalid: 1; 1899 u32 c2h_struct_invalid: 1; 1900 u32 h2c_c2h_buffer_mismatch: 1; 1901 }; 1902 1903 union rtw89_btc_dm_error_map { 1904 u32 val; 1905 struct rtw89_btc_dm_emap map; 1906 }; 1907 1908 struct rtw89_btc_rf_para { 1909 u32 tx_pwr_freerun; 1910 u32 rx_gain_freerun; 1911 u32 tx_pwr_perpkt; 1912 u32 rx_gain_perpkt; 1913 }; 1914 1915 struct rtw89_btc_wl_nhm { 1916 u8 instant_wl_nhm_dbm; 1917 u8 instant_wl_nhm_per_mhz; 1918 u16 valid_record_times; 1919 s8 record_pwr[16]; 1920 u8 record_ratio[16]; 1921 s8 pwr; /* dbm_per_MHz */ 1922 u8 ratio; 1923 u8 current_status; 1924 u8 refresh; 1925 bool start_flag; 1926 s8 pwr_max; 1927 s8 pwr_min; 1928 }; 1929 1930 struct rtw89_btc_wl_info { 1931 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1932 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1933 struct rtw89_btc_wl_rfk_info rfk_info; 1934 struct rtw89_btc_wl_ver_info ver_info; 1935 struct rtw89_btc_wl_afh_info afh_info; 1936 struct rtw89_btc_wl_role_info role_info; 1937 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1938 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1939 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1940 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1941 struct rtw89_btc_wl_scan_info scan_info; 1942 struct rtw89_btc_wl_dbcc_info dbcc_info; 1943 struct rtw89_btc_wl_mlo_info mlo_info; 1944 struct rtw89_btc_rf_para rf_para; 1945 struct rtw89_btc_wl_nhm nhm; 1946 union rtw89_btc_wl_state_map status; 1947 1948 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1949 u8 rssi_level; 1950 u8 cn_report; 1951 u8 coex_mode; 1952 u8 pta_req_mac; 1953 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 1954 1955 bool is_5g_hi_channel; 1956 bool go_client_exist; 1957 bool noa_exist; 1958 bool pta_reg_mac_chg; 1959 bool bg_mode; 1960 bool he_mode; 1961 bool scbd_change; 1962 bool fw_ver_mismatch; 1963 bool client_cnt_inc_2g; 1964 bool link_mode_chg; 1965 bool dbcc_chg; 1966 u32 scbd; 1967 }; 1968 1969 struct rtw89_btc_module { 1970 struct rtw89_btc_ant_info ant; 1971 u8 rfe_type; 1972 u8 cv; 1973 1974 u8 bt_solo: 1; 1975 u8 bt_pos: 1; 1976 u8 switch_type: 1; 1977 u8 wa_type: 3; 1978 1979 u8 kt_ver_adie; 1980 }; 1981 1982 struct rtw89_btc_module_v7 { 1983 u8 rfe_type; 1984 u8 kt_ver; 1985 u8 bt_solo; 1986 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1987 1988 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1989 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1990 u8 kt_ver_adie; 1991 u8 rsvd; 1992 1993 struct rtw89_btc_ant_info_v7 ant; 1994 } __packed; 1995 1996 union rtw89_btc_module_info { 1997 struct rtw89_btc_module md; 1998 struct rtw89_btc_module_v7 md_v7; 1999 }; 2000 2001 #define RTW89_BTC_DM_MAXSTEP 30 2002 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 2003 2004 struct rtw89_btc_dm_step { 2005 u16 step[RTW89_BTC_DM_MAXSTEP]; 2006 u8 step_pos; 2007 bool step_ov; 2008 }; 2009 2010 struct rtw89_btc_init_info { 2011 struct rtw89_btc_module module; 2012 u8 wl_guard_ch; 2013 2014 u8 wl_only: 1; 2015 u8 wl_init_ok: 1; 2016 u8 dbcc_en: 1; 2017 u8 cx_other: 1; 2018 u8 bt_only: 1; 2019 2020 u16 rsvd; 2021 }; 2022 2023 struct rtw89_btc_init_info_v7 { 2024 u8 wl_guard_ch; 2025 u8 wl_only; 2026 u8 wl_init_ok; 2027 u8 rsvd3; 2028 2029 u8 cx_other; 2030 u8 bt_only; 2031 u8 pta_mode; 2032 u8 pta_direction; 2033 2034 struct rtw89_btc_module_v7 module; 2035 } __packed; 2036 2037 union rtw89_btc_init_info_u { 2038 struct rtw89_btc_init_info init; 2039 struct rtw89_btc_init_info_v7 init_v7; 2040 }; 2041 2042 struct rtw89_btc_wl_tx_limit_para { 2043 u16 enable; 2044 u32 tx_time; /* unit: us */ 2045 u16 tx_retry; 2046 }; 2047 2048 enum rtw89_btc_bt_scan_type { 2049 BTC_SCAN_INQ = 0, 2050 BTC_SCAN_PAGE, 2051 BTC_SCAN_BLE, 2052 BTC_SCAN_INIT, 2053 BTC_SCAN_TV, 2054 BTC_SCAN_ADV, 2055 BTC_SCAN_MAX1, 2056 }; 2057 2058 enum rtw89_btc_ble_scan_type { 2059 CXSCAN_BG = 0, 2060 CXSCAN_INIT, 2061 CXSCAN_LE, 2062 CXSCAN_MAX 2063 }; 2064 2065 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2066 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2067 2068 struct rtw89_btc_bt_scan_info_v1 { 2069 __le16 win; 2070 __le16 intvl; 2071 __le32 flags; 2072 } __packed; 2073 2074 struct rtw89_btc_bt_scan_info_v2 { 2075 __le16 win; 2076 __le16 intvl; 2077 } __packed; 2078 2079 struct rtw89_btc_fbtc_btscan_v1 { 2080 u8 fver; /* btc_ver::fcxbtscan */ 2081 u8 rsvd; 2082 __le16 rsvd2; 2083 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2084 } __packed; 2085 2086 struct rtw89_btc_fbtc_btscan_v2 { 2087 u8 fver; /* btc_ver::fcxbtscan */ 2088 u8 type; 2089 __le16 rsvd2; 2090 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2091 } __packed; 2092 2093 struct rtw89_btc_fbtc_btscan_v7 { 2094 u8 fver; /* btc_ver::fcxbtscan */ 2095 u8 type; 2096 u8 rsvd0; 2097 u8 rsvd1; 2098 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2099 } __packed; 2100 2101 union rtw89_btc_fbtc_btscan { 2102 struct rtw89_btc_fbtc_btscan_v1 v1; 2103 struct rtw89_btc_fbtc_btscan_v2 v2; 2104 struct rtw89_btc_fbtc_btscan_v7 v7; 2105 }; 2106 2107 struct rtw89_btc_bt_info { 2108 struct rtw89_btc_bt_link_info link_info; 2109 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2110 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2111 struct rtw89_btc_bt_ver_info ver_info; 2112 struct rtw89_btc_bool_sta_chg enable; 2113 struct rtw89_btc_bool_sta_chg inq_pag; 2114 struct rtw89_btc_rf_para rf_para; 2115 union rtw89_btc_bt_rfk_info_map rfk_info; 2116 2117 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2118 u8 txpwr_info[BTC_BTINFO_MAX]; 2119 u8 rssi_level; 2120 2121 u32 scbd; 2122 u32 feature; 2123 2124 u32 mbx_avl: 1; 2125 u32 whql_test: 1; 2126 u32 igno_wl: 1; 2127 u32 reinit: 1; 2128 u32 ble_scan_en: 1; 2129 u32 btg_type: 1; 2130 u32 inq: 1; 2131 u32 pag: 1; 2132 u32 run_patch_code: 1; 2133 u32 hi_lna_rx: 1; 2134 u32 scan_rx_low_pri: 1; 2135 u32 scan_info_update: 1; 2136 u32 lna_constrain: 3; 2137 u32 rsvd: 17; 2138 }; 2139 2140 struct rtw89_btc_cx { 2141 struct rtw89_btc_wl_info wl; 2142 struct rtw89_btc_bt_info bt; 2143 struct rtw89_btc_3rdcx_info other; 2144 u32 state_map; 2145 u32 cnt_bt[BTC_BCNT_NUM]; 2146 u32 cnt_wl[BTC_WCNT_NUM]; 2147 }; 2148 2149 struct rtw89_btc_fbtc_tdma { 2150 u8 type; /* btc_ver::fcxtdma */ 2151 u8 rxflctrl; 2152 u8 txpause; 2153 u8 wtgle_n; 2154 u8 leak_n; 2155 u8 ext_ctrl; 2156 u8 rxflctrl_role; 2157 u8 option_ctrl; 2158 } __packed; 2159 2160 struct rtw89_btc_fbtc_tdma_v3 { 2161 u8 fver; /* btc_ver::fcxtdma */ 2162 u8 rsvd; 2163 __le16 rsvd1; 2164 struct rtw89_btc_fbtc_tdma tdma; 2165 } __packed; 2166 2167 union rtw89_btc_fbtc_tdma_le32 { 2168 struct rtw89_btc_fbtc_tdma v1; 2169 struct rtw89_btc_fbtc_tdma_v3 v3; 2170 }; 2171 2172 #define CXMREG_MAX 30 2173 #define CXMREG_MAX_V2 20 2174 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2175 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2176 2177 enum rtw89_btc_bt_sta_counter { 2178 BTC_BCNT_RFK_REQ = 0, 2179 BTC_BCNT_RFK_GO = 1, 2180 BTC_BCNT_RFK_REJECT = 2, 2181 BTC_BCNT_RFK_FAIL = 3, 2182 BTC_BCNT_RFK_TIMEOUT = 4, 2183 BTC_BCNT_HI_TX = 5, 2184 BTC_BCNT_HI_RX = 6, 2185 BTC_BCNT_LO_TX = 7, 2186 BTC_BCNT_LO_RX = 8, 2187 BTC_BCNT_POLLUTED = 9, 2188 BTC_BCNT_STA_MAX 2189 }; 2190 2191 enum rtw89_btc_bt_sta_counter_v105 { 2192 BTC_BCNT_RFK_REQ_V105 = 0, 2193 BTC_BCNT_HI_TX_V105 = 1, 2194 BTC_BCNT_HI_RX_V105 = 2, 2195 BTC_BCNT_LO_TX_V105 = 3, 2196 BTC_BCNT_LO_RX_V105 = 4, 2197 BTC_BCNT_POLLUTED_V105 = 5, 2198 BTC_BCNT_STA_MAX_V105 2199 }; 2200 2201 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2202 u16 fver; /* btc_ver::fcxbtcrpt */ 2203 u16 rpt_cnt; /* tmr counters */ 2204 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2205 u32 wl_fw_cx_offload; 2206 u32 wl_fw_ver; 2207 u32 rpt_enable; 2208 u32 rpt_para; /* ms */ 2209 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2210 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2211 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2212 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2213 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2214 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2215 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2216 u32 c2h_cnt; /* fw send c2h counter */ 2217 u32 h2c_cnt; /* fw recv h2c counter */ 2218 } __packed; 2219 2220 struct rtw89_btc_fbtc_rpt_ctrl_info { 2221 __le32 cnt; /* fw report counter */ 2222 __le32 en; /* report map */ 2223 __le32 para; /* not used */ 2224 2225 __le32 cnt_c2h; /* fw send c2h counter */ 2226 __le32 cnt_h2c; /* fw recv h2c counter */ 2227 __le32 len_c2h; /* The total length of the last C2H */ 2228 2229 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2230 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2231 } __packed; 2232 2233 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2234 __le32 cx_ver; /* match which driver's coex version */ 2235 __le32 fw_ver; 2236 __le32 en; /* report map */ 2237 2238 __le16 cnt; /* fw report counter */ 2239 __le16 cnt_c2h; /* fw send c2h counter */ 2240 __le16 cnt_h2c; /* fw recv h2c counter */ 2241 __le16 len_c2h; /* The total length of the last C2H */ 2242 2243 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2244 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2245 } __packed; 2246 2247 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2248 __le16 cnt; /* fw report counter */ 2249 __le16 cnt_c2h; /* fw send c2h counter */ 2250 __le16 cnt_h2c; /* fw recv h2c counter */ 2251 __le16 len_c2h; /* The total length of the last C2H */ 2252 2253 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2254 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2255 2256 __le32 cx_ver; /* match which driver's coex version */ 2257 __le32 fw_ver; 2258 __le32 en; /* report map */ 2259 } __packed; 2260 2261 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2262 __le32 cx_ver; /* match which driver's coex version */ 2263 __le32 cx_offload; 2264 __le32 fw_ver; 2265 } __packed; 2266 2267 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2268 __le32 cnt_empty; /* a2dp empty count */ 2269 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2270 __le32 cnt_tx; 2271 __le32 cnt_ack; 2272 __le32 cnt_nack; 2273 } __packed; 2274 2275 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2276 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2277 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2278 __le32 cnt_recv; /* fw recv mailbox counter */ 2279 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2280 } __packed; 2281 2282 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2283 u8 fver; 2284 u8 rsvd; 2285 __le16 rsvd1; 2286 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2287 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2288 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2289 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2290 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2291 } __packed; 2292 2293 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2294 u8 fver; 2295 u8 rsvd; 2296 __le16 rsvd1; 2297 2298 u8 gnt_val[RTW89_PHY_NUM][4]; 2299 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2300 2301 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2302 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2303 } __packed; 2304 2305 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2306 u8 fver; 2307 u8 rsvd; 2308 __le16 rsvd1; 2309 2310 u8 gnt_val[RTW89_PHY_NUM][4]; 2311 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2312 2313 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2314 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2315 } __packed; 2316 2317 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2318 u8 fver; 2319 u8 rsvd0; 2320 u8 rsvd1; 2321 u8 rsvd2; 2322 2323 u8 gnt_val[RTW89_PHY_NUM][4]; 2324 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2325 2326 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2327 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2328 } __packed; 2329 2330 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2331 u8 fver; 2332 u8 rsvd0; 2333 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2334 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2335 2336 u8 gnt_val[RTW89_PHY_NUM][4]; 2337 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2338 2339 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2340 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2341 } __packed; 2342 2343 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2344 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2345 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2346 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2347 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2348 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2349 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2350 }; 2351 2352 enum rtw89_fbtc_ext_ctrl_type { 2353 CXECTL_OFF = 0x0, /* tdma off */ 2354 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2355 CXECTL_EXT = 0x2, 2356 CXECTL_MAX 2357 }; 2358 2359 union rtw89_btc_fbtc_rxflct { 2360 u8 val; 2361 u8 type: 3; 2362 u8 tgln_n: 5; 2363 }; 2364 2365 enum rtw89_btc_cxst_state { 2366 CXST_OFF = 0x0, 2367 CXST_B2W = 0x1, 2368 CXST_W1 = 0x2, 2369 CXST_W2 = 0x3, 2370 CXST_W2B = 0x4, 2371 CXST_B1 = 0x5, 2372 CXST_B2 = 0x6, 2373 CXST_B3 = 0x7, 2374 CXST_B4 = 0x8, 2375 CXST_LK = 0x9, 2376 CXST_BLK = 0xa, 2377 CXST_E2G = 0xb, 2378 CXST_E5G = 0xc, 2379 CXST_EBT = 0xd, 2380 CXST_ENULL = 0xe, 2381 CXST_WLK = 0xf, 2382 CXST_W1FDD = 0x10, 2383 CXST_B1FDD = 0x11, 2384 CXST_MAX = 0x12, 2385 }; 2386 2387 enum rtw89_btc_cxevnt { 2388 CXEVNT_TDMA_ENTRY = 0x0, 2389 CXEVNT_WL_TMR, 2390 CXEVNT_B1_TMR, 2391 CXEVNT_B2_TMR, 2392 CXEVNT_B3_TMR, 2393 CXEVNT_B4_TMR, 2394 CXEVNT_W2B_TMR, 2395 CXEVNT_B2W_TMR, 2396 CXEVNT_BCN_EARLY, 2397 CXEVNT_A2DP_EMPTY, 2398 CXEVNT_LK_END, 2399 CXEVNT_RX_ISR, 2400 CXEVNT_RX_FC0, 2401 CXEVNT_RX_FC1, 2402 CXEVNT_BT_RELINK, 2403 CXEVNT_BT_RETRY, 2404 CXEVNT_E2G, 2405 CXEVNT_E5G, 2406 CXEVNT_EBT, 2407 CXEVNT_ENULL, 2408 CXEVNT_DRV_WLK, 2409 CXEVNT_BCN_OK, 2410 CXEVNT_BT_CHANGE, 2411 CXEVNT_EBT_EXTEND, 2412 CXEVNT_E2G_NULL1, 2413 CXEVNT_B1FDD_TMR, 2414 CXEVNT_MAX 2415 }; 2416 2417 enum { 2418 CXBCN_ALL = 0x0, 2419 CXBCN_ALL_OK, 2420 CXBCN_BT_SLOT, 2421 CXBCN_BT_OK, 2422 CXBCN_MAX 2423 }; 2424 2425 enum btc_slot_type { 2426 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2427 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2428 CXSTYPE_NUM, 2429 }; 2430 2431 enum { /* TIME */ 2432 CXT_BT = 0x0, 2433 CXT_WL = 0x1, 2434 CXT_MAX 2435 }; 2436 2437 enum { /* TIME-A2DP */ 2438 CXT_FLCTRL_OFF = 0x0, 2439 CXT_FLCTRL_ON = 0x1, 2440 CXT_FLCTRL_MAX 2441 }; 2442 2443 enum { /* STEP TYPE */ 2444 CXSTEP_NONE = 0x0, 2445 CXSTEP_EVNT = 0x1, 2446 CXSTEP_SLOT = 0x2, 2447 CXSTEP_MAX, 2448 }; 2449 2450 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2451 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2452 RPT_BT_AFH_SEQ_LE = 0x20 2453 }; 2454 2455 #define BTC_DBG_MAX1 32 2456 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2457 u8 fver; /* btc_ver::fcxgpiodbg */ 2458 u8 rsvd; 2459 __le16 rsvd2; 2460 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2461 __le32 pre_state; /* the debug signal is 1 or 0 */ 2462 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2463 } __packed; 2464 2465 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2466 u8 fver; 2467 u8 rsvd0; 2468 u8 rsvd1; 2469 u8 rsvd2; 2470 2471 u8 gpio_map[BTC_DBG_MAX1]; 2472 2473 __le32 en_map; 2474 __le32 pre_state; 2475 } __packed; 2476 2477 union rtw89_btc_fbtc_gpio_dbg { 2478 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2479 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2480 }; 2481 2482 struct rtw89_btc_fbtc_mreg_val_v1 { 2483 u8 fver; /* btc_ver::fcxmreg */ 2484 u8 reg_num; 2485 __le16 rsvd; 2486 __le32 mreg_val[CXMREG_MAX]; 2487 } __packed; 2488 2489 struct rtw89_btc_fbtc_mreg_val_v2 { 2490 u8 fver; /* btc_ver::fcxmreg */ 2491 u8 reg_num; 2492 __le16 rsvd; 2493 __le32 mreg_val[CXMREG_MAX_V2]; 2494 } __packed; 2495 2496 struct rtw89_btc_fbtc_mreg_val_v7 { 2497 u8 fver; 2498 u8 reg_num; 2499 u8 rsvd0; 2500 u8 rsvd1; 2501 __le32 mreg_val[CXMREG_MAX_V2]; 2502 } __packed; 2503 2504 union rtw89_btc_fbtc_mreg_val { 2505 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2506 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2507 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2508 }; 2509 2510 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2511 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2512 .offset = cpu_to_le32(__offset), } 2513 2514 struct rtw89_btc_fbtc_mreg { 2515 __le16 type; 2516 __le16 bytes; 2517 __le32 offset; 2518 } __packed; 2519 2520 struct rtw89_btc_fbtc_slot { 2521 __le16 dur; 2522 __le32 cxtbl; 2523 __le16 cxtype; 2524 } __packed; 2525 2526 struct rtw89_btc_fbtc_slots { 2527 u8 fver; /* btc_ver::fcxslots */ 2528 u8 tbl_num; 2529 __le16 rsvd; 2530 __le32 update_map; 2531 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2532 } __packed; 2533 2534 struct rtw89_btc_fbtc_slot_v7 { 2535 __le16 dur; /* slot duration */ 2536 __le16 cxtype; 2537 __le32 cxtbl; 2538 } __packed; 2539 2540 struct rtw89_btc_fbtc_slot_u16 { 2541 __le16 dur; /* slot duration */ 2542 __le16 cxtype; 2543 __le16 cxtbl_l16; /* coex table [15:0] */ 2544 __le16 cxtbl_h16; /* coex table [31:16] */ 2545 } __packed; 2546 2547 struct rtw89_btc_fbtc_1slot_v7 { 2548 u8 fver; 2549 u8 sid; /* slot id */ 2550 __le16 rsvd; 2551 struct rtw89_btc_fbtc_slot_v7 slot; 2552 } __packed; 2553 2554 struct rtw89_btc_fbtc_slots_v7 { 2555 u8 fver; 2556 u8 slot_cnt; 2557 u8 rsvd0; 2558 u8 rsvd1; 2559 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2560 __le32 update_map; 2561 } __packed; 2562 2563 union rtw89_btc_fbtc_slots_info { 2564 struct rtw89_btc_fbtc_slots v1; 2565 struct rtw89_btc_fbtc_slots_v7 v7; 2566 } __packed; 2567 2568 struct rtw89_btc_fbtc_step { 2569 u8 type; 2570 u8 val; 2571 __le16 difft; 2572 } __packed; 2573 2574 struct rtw89_btc_fbtc_steps_v2 { 2575 u8 fver; /* btc_ver::fcxstep */ 2576 u8 rsvd; 2577 __le16 cnt; 2578 __le16 pos_old; 2579 __le16 pos_new; 2580 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2581 } __packed; 2582 2583 struct rtw89_btc_fbtc_steps_v3 { 2584 u8 fver; 2585 u8 en; 2586 __le16 rsvd; 2587 __le32 cnt; 2588 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2589 } __packed; 2590 2591 union rtw89_btc_fbtc_steps_info { 2592 struct rtw89_btc_fbtc_steps_v2 v2; 2593 struct rtw89_btc_fbtc_steps_v3 v3; 2594 }; 2595 2596 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2597 u8 fver; /* btc_ver::fcxcysta */ 2598 u8 rsvd; 2599 __le16 cycles; /* total cycle number */ 2600 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2601 __le16 a2dpept; /* a2dp empty cnt */ 2602 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2603 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2604 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2605 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2606 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2607 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2608 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2609 __le16 tmax_a2dpept; /* max a2dp empty time */ 2610 __le16 tavg_lk; /* avg leak-slot time */ 2611 __le16 tmax_lk; /* max leak-slot time */ 2612 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2613 __le32 bcn_cnt[CXBCN_MAX]; 2614 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2615 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2616 __le32 skip_cnt; 2617 __le32 exception; 2618 __le32 except_cnt; 2619 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2620 } __packed; 2621 2622 struct rtw89_btc_fbtc_fdd_try_info { 2623 __le16 cycles[CXT_FLCTRL_MAX]; 2624 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2625 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2626 } __packed; 2627 2628 struct rtw89_btc_fbtc_cycle_time_info { 2629 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2630 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2631 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2632 } __packed; 2633 2634 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2635 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2636 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2637 } __packed; 2638 2639 struct rtw89_btc_fbtc_a2dp_trx_stat { 2640 u8 empty_cnt; 2641 u8 retry_cnt; 2642 u8 tx_rate; 2643 u8 tx_cnt; 2644 u8 ack_cnt; 2645 u8 nack_cnt; 2646 u8 rsvd1; 2647 u8 rsvd2; 2648 } __packed; 2649 2650 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2651 u8 empty_cnt; 2652 u8 retry_cnt; 2653 u8 tx_rate; 2654 u8 tx_cnt; 2655 u8 ack_cnt; 2656 u8 nack_cnt; 2657 u8 no_empty_cnt; 2658 u8 rsvd; 2659 } __packed; 2660 2661 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2662 __le16 cnt; /* a2dp empty cnt */ 2663 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2664 __le16 tavg; /* avg a2dp empty time */ 2665 __le16 tmax; /* max a2dp empty time */ 2666 } __packed; 2667 2668 struct rtw89_btc_fbtc_cycle_leak_info { 2669 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2670 __le16 tavg; /* avg leak-slot time */ 2671 __le16 tmax; /* max leak-slot time */ 2672 } __packed; 2673 2674 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2675 __le16 tavg; 2676 __le16 tamx; 2677 __le32 cnt_rximr; 2678 } __packed; 2679 2680 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2681 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2682 2683 struct rtw89_btc_fbtc_cycle_fddt_info { 2684 __le16 train_cycle; 2685 __le16 tp; 2686 2687 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2688 s8 bt_tx_power; /* decrease Tx power (dB) */ 2689 s8 bt_rx_gain; /* LNA constrain level */ 2690 u8 no_empty_cnt; 2691 2692 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2693 u8 cn; /* condition_num */ 2694 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2695 u8 train_result; /* refer to enum btc_fddt_check_map */ 2696 } __packed; 2697 2698 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2699 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2700 2701 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2702 __le16 train_cycle; 2703 __le16 tp; 2704 2705 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2706 s8 bt_tx_power; /* decrease Tx power (dB) */ 2707 s8 bt_rx_gain; /* LNA constrain level */ 2708 u8 no_empty_cnt; 2709 2710 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2711 u8 cn; /* condition_num */ 2712 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2713 u8 train_result; /* refer to enum btc_fddt_check_map */ 2714 } __packed; 2715 2716 struct rtw89_btc_fbtc_fddt_cell_status { 2717 s8 wl_tx_pwr; 2718 s8 bt_tx_pwr; 2719 s8 bt_rx_gain; 2720 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2721 } __packed; 2722 2723 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2724 u8 fver; 2725 u8 rsvd; 2726 __le16 cycles; /* total cycle number */ 2727 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2728 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2729 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2730 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2731 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2732 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2733 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2734 __le32 bcn_cnt[CXBCN_MAX]; 2735 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2736 __le32 skip_cnt; 2737 __le32 except_cnt; 2738 __le32 except_map; 2739 } __packed; 2740 2741 #define FDD_TRAIN_WL_DIRECTION 2 2742 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2743 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2744 2745 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2746 u8 fver; 2747 u8 rsvd; 2748 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2749 u8 except_cnt; 2750 2751 __le16 skip_cnt; 2752 __le16 cycles; /* total cycle number */ 2753 2754 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2755 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2756 __le16 bcn_cnt[CXBCN_MAX]; 2757 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2758 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2759 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2760 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2761 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2762 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2763 [FDD_TRAIN_WL_RSSI_LEVEL] 2764 [FDD_TRAIN_BT_RSSI_LEVEL]; 2765 __le32 except_map; 2766 } __packed; 2767 2768 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2769 u8 fver; 2770 u8 rsvd; 2771 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2772 u8 except_cnt; 2773 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2774 2775 __le16 skip_cnt; 2776 __le16 cycles; /* total cycle number */ 2777 2778 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2779 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2780 __le16 bcn_cnt[CXBCN_MAX]; 2781 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2782 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2783 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2784 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2785 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2786 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2787 [FDD_TRAIN_WL_RSSI_LEVEL] 2788 [FDD_TRAIN_BT_RSSI_LEVEL]; 2789 __le32 except_map; 2790 } __packed; 2791 2792 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2793 u8 fver; 2794 u8 rsvd; 2795 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2796 u8 except_cnt; 2797 2798 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2799 2800 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2801 2802 __le16 skip_cnt; 2803 __le16 cycles; /* total cycle number */ 2804 2805 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2806 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2807 __le16 bcn_cnt[CXBCN_MAX]; 2808 2809 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2810 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2811 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2812 2813 __le32 except_map; 2814 } __packed; 2815 2816 union rtw89_btc_fbtc_cysta_info { 2817 struct rtw89_btc_fbtc_cysta_v2 v2; 2818 struct rtw89_btc_fbtc_cysta_v3 v3; 2819 struct rtw89_btc_fbtc_cysta_v4 v4; 2820 struct rtw89_btc_fbtc_cysta_v5 v5; 2821 struct rtw89_btc_fbtc_cysta_v7 v7; 2822 }; 2823 2824 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2825 u8 fver; /* btc_ver::fcxnullsta */ 2826 u8 rsvd; 2827 __le16 rsvd2; 2828 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2829 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2830 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2831 } __packed; 2832 2833 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2834 u8 fver; /* btc_ver::fcxnullsta */ 2835 u8 rsvd; 2836 __le16 rsvd2; 2837 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2838 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2839 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2840 } __packed; 2841 2842 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2843 u8 fver; 2844 u8 rsvd0; 2845 u8 rsvd1; 2846 u8 rsvd2; 2847 2848 __le32 tmax[2]; 2849 __le32 tavg[2]; 2850 __le32 result[2][5]; 2851 } __packed; 2852 2853 union rtw89_btc_fbtc_cynullsta_info { 2854 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2855 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2856 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2857 }; 2858 2859 struct rtw89_btc_fbtc_btver_v1 { 2860 u8 fver; /* btc_ver::fcxbtver */ 2861 u8 rsvd; 2862 __le16 rsvd2; 2863 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2864 __le32 fw_ver; 2865 __le32 feature; 2866 } __packed; 2867 2868 struct rtw89_btc_fbtc_btver_v7 { 2869 u8 fver; 2870 u8 rsvd0; 2871 u8 rsvd1; 2872 u8 rsvd2; 2873 2874 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2875 __le32 fw_ver; 2876 __le32 feature; 2877 } __packed; 2878 2879 union rtw89_btc_fbtc_btver { 2880 struct rtw89_btc_fbtc_btver_v1 v1; 2881 struct rtw89_btc_fbtc_btver_v7 v7; 2882 } __packed; 2883 2884 struct rtw89_btc_fbtc_btafh { 2885 u8 fver; /* btc_ver::fcxbtafh */ 2886 u8 rsvd; 2887 __le16 rsvd2; 2888 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2889 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2890 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2891 } __packed; 2892 2893 struct rtw89_btc_fbtc_btafh_v2 { 2894 u8 fver; /* btc_ver::fcxbtafh */ 2895 u8 rsvd; 2896 u8 rsvd2; 2897 u8 map_type; 2898 u8 afh_l[4]; 2899 u8 afh_m[4]; 2900 u8 afh_h[4]; 2901 u8 afh_le_a[4]; 2902 u8 afh_le_b[4]; 2903 } __packed; 2904 2905 struct rtw89_btc_fbtc_btafh_v7 { 2906 u8 fver; 2907 u8 map_type; 2908 u8 rsvd0; 2909 u8 rsvd1; 2910 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2911 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2912 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2913 u8 afh_le_a[4]; 2914 u8 afh_le_b[4]; 2915 } __packed; 2916 2917 struct rtw89_btc_fbtc_btdevinfo { 2918 u8 fver; /* btc_ver::fcxbtdevinfo */ 2919 u8 rsvd; 2920 __le16 vendor_id; 2921 __le32 dev_name; /* only 24 bits valid */ 2922 __le32 flush_time; 2923 } __packed; 2924 2925 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2926 struct rtw89_btc_rf_trx_para { 2927 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2928 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2929 u8 bt_tx_power; /* decrease Tx power (dB) */ 2930 u8 bt_rx_gain; /* LNA constrain level */ 2931 }; 2932 2933 struct rtw89_btc_trx_info { 2934 u8 tx_lvl; 2935 u8 rx_lvl; 2936 u8 wl_rssi; 2937 u8 bt_rssi; 2938 2939 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2940 s8 rx_gain; /* rx gain table index (TBD.) */ 2941 s8 bt_tx_power; /* decrease Tx power (dB) */ 2942 s8 bt_rx_gain; /* LNA constrain level */ 2943 2944 u8 cn; /* condition_num */ 2945 s8 nhm; 2946 u8 bt_profile; 2947 u8 rsvd2; 2948 2949 u16 tx_rate; 2950 u16 rx_rate; 2951 2952 u32 tx_tp; 2953 u32 rx_tp; 2954 u32 rx_err_ratio; 2955 }; 2956 2957 enum btc_rf_path { 2958 BTC_RF_S0 = 0, 2959 BTC_RF_S1 = 1, 2960 BTC_RF_NUM, 2961 }; 2962 2963 struct rtw89_btc_fbtc_outsrc_set_info { 2964 u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */ 2965 u8 btg_rx[BTC_RF_NUM]; 2966 u8 nbtg_tx[BTC_RF_NUM]; 2967 2968 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */ 2969 struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */ 2970 2971 u8 pta_req_hw_band; 2972 u8 rf_gbt_source; 2973 } __packed; 2974 2975 union rtw89_btc_fbtc_slot_u { 2976 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2977 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2978 }; 2979 2980 struct rtw89_btc_dm { 2981 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */ 2982 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */ 2983 union rtw89_btc_fbtc_slot_u slot; 2984 union rtw89_btc_fbtc_slot_u slot_now; 2985 struct rtw89_btc_fbtc_tdma tdma; 2986 struct rtw89_btc_fbtc_tdma tdma_now; 2987 struct rtw89_mac_ax_coex_gnt gnt; 2988 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2989 struct rtw89_btc_rf_trx_para rf_trx_para; 2990 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2991 struct rtw89_btc_dm_step dm_step; 2992 struct rtw89_btc_wl_scc_ctrl wl_scc; 2993 struct rtw89_btc_trx_info trx_info; 2994 union rtw89_btc_dm_error_map error; 2995 u32 cnt_dm[BTC_DCNT_NUM]; 2996 u32 cnt_notify[BTC_NCNT_NUM]; 2997 2998 u32 update_slot_map; 2999 u32 set_ant_path; 3000 u32 e2g_slot_limit; 3001 u32 e2g_slot_nulltx_time; 3002 3003 u32 wl_only: 1; 3004 u32 wl_fw_cx_offload: 1; 3005 u32 freerun: 1; 3006 u32 fddt_train: 1; 3007 u32 wl_ps_ctrl: 2; 3008 u32 wl_mimo_ps: 1; 3009 u32 leak_ap: 1; 3010 u32 noisy_level: 3; 3011 u32 coex_info_map: 8; 3012 u32 bt_only: 1; 3013 u32 wl_btg_rx: 2; 3014 u32 trx_para_level: 8; 3015 u32 wl_stb_chg: 1; 3016 u32 pta_owner: 1; 3017 3018 u32 tdma_instant_excute: 1; 3019 u32 wl_btg_rx_rb: 2; 3020 3021 u16 slot_dur[CXST_MAX]; 3022 u16 bt_slot_flood; 3023 3024 u8 run_reason; 3025 u8 run_action; 3026 3027 u8 wl_pre_agc: 2; 3028 u8 wl_lna2: 1; 3029 u8 freerun_chk: 1; 3030 u8 wl_pre_agc_rb: 2; 3031 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 3032 u8 slot_req_more: 1; 3033 }; 3034 3035 struct rtw89_btc_ctrl { 3036 u32 manual: 1; 3037 u32 igno_bt: 1; 3038 u32 always_freerun: 1; 3039 u32 trace_step: 16; 3040 u32 rsvd: 12; 3041 }; 3042 3043 struct rtw89_btc_ctrl_v7 { 3044 u8 manual; 3045 u8 igno_bt; 3046 u8 always_freerun; 3047 u8 rsvd; 3048 } __packed; 3049 3050 union rtw89_btc_ctrl_list { 3051 struct rtw89_btc_ctrl ctrl; 3052 struct rtw89_btc_ctrl_v7 ctrl_v7; 3053 }; 3054 3055 struct rtw89_btc_dbg { 3056 /* cmd "rb" */ 3057 bool rb_done; 3058 u32 rb_val; 3059 }; 3060 3061 enum rtw89_btc_btf_fw_event { 3062 BTF_EVNT_RPT = 0, 3063 BTF_EVNT_BT_INFO = 1, 3064 BTF_EVNT_BT_SCBD = 2, 3065 BTF_EVNT_BT_REG = 3, 3066 BTF_EVNT_CX_RUNINFO = 4, 3067 BTF_EVNT_BT_PSD = 5, 3068 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 3069 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 3070 BTF_EVNT_BUF_OVERFLOW, 3071 BTF_EVNT_C2H_LOOPBACK, 3072 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */ 3073 BTF_EVNT_MAX, 3074 }; 3075 3076 enum btf_fw_event_report { 3077 BTC_RPT_TYPE_CTRL = 0x0, 3078 BTC_RPT_TYPE_TDMA, 3079 BTC_RPT_TYPE_SLOT, 3080 BTC_RPT_TYPE_CYSTA, 3081 BTC_RPT_TYPE_STEP, 3082 BTC_RPT_TYPE_NULLSTA, 3083 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3084 BTC_RPT_TYPE_MREG, 3085 BTC_RPT_TYPE_GPIO_DBG, 3086 BTC_RPT_TYPE_BT_VER, 3087 BTC_RPT_TYPE_BT_SCAN, 3088 BTC_RPT_TYPE_BT_AFH, 3089 BTC_RPT_TYPE_BT_DEVICE, 3090 BTC_RPT_TYPE_TEST, 3091 BTC_RPT_TYPE_MAX = 31, 3092 3093 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3094 __BTC_RPT_TYPE_V0_MAX = 12, 3095 }; 3096 3097 enum rtw_btc_btf_reg_type { 3098 REG_MAC = 0x0, 3099 REG_BB = 0x1, 3100 REG_RF = 0x2, 3101 REG_BT_RF = 0x3, 3102 REG_BT_MODEM = 0x4, 3103 REG_BT_BLUEWIZE = 0x5, 3104 REG_BT_VENDOR = 0x6, 3105 REG_BT_LE = 0x7, 3106 REG_MAX_TYPE, 3107 }; 3108 3109 struct rtw89_btc_rpt_cmn_info { 3110 u32 rx_cnt; 3111 u32 rx_len; 3112 u32 req_len; /* expected rsp len */ 3113 u8 req_fver; /* expected rsp fver */ 3114 u8 rsp_fver; /* fver from fw */ 3115 u8 valid; 3116 } __packed; 3117 3118 union rtw89_btc_fbtc_btafh_info { 3119 struct rtw89_btc_fbtc_btafh v1; 3120 struct rtw89_btc_fbtc_btafh_v2 v2; 3121 struct rtw89_btc_fbtc_btafh_v7 v7; 3122 }; 3123 3124 struct rtw89_btc_report_ctrl_state { 3125 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3126 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3127 }; 3128 3129 struct rtw89_btc_rpt_fbtc_tdma { 3130 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3131 union rtw89_btc_fbtc_tdma_le32 finfo; 3132 }; 3133 3134 struct rtw89_btc_rpt_fbtc_slots { 3135 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3136 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3137 }; 3138 3139 struct rtw89_btc_rpt_fbtc_cysta { 3140 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3141 union rtw89_btc_fbtc_cysta_info finfo; 3142 }; 3143 3144 struct rtw89_btc_rpt_fbtc_step { 3145 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3146 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3147 }; 3148 3149 struct rtw89_btc_rpt_fbtc_nullsta { 3150 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3151 union rtw89_btc_fbtc_cynullsta_info finfo; 3152 }; 3153 3154 struct rtw89_btc_rpt_fbtc_mreg { 3155 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3156 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3157 }; 3158 3159 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3160 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3161 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3162 }; 3163 3164 struct rtw89_btc_rpt_fbtc_btver { 3165 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3166 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3167 }; 3168 3169 struct rtw89_btc_rpt_fbtc_btscan { 3170 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3171 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3172 }; 3173 3174 struct rtw89_btc_rpt_fbtc_btafh { 3175 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3176 union rtw89_btc_fbtc_btafh_info finfo; 3177 }; 3178 3179 struct rtw89_btc_rpt_fbtc_btdev { 3180 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3181 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3182 }; 3183 3184 enum rtw89_btc_btfre_type { 3185 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3186 BTFRE_UNDEF_TYPE, 3187 BTFRE_EXCEPTION, 3188 BTFRE_MAX, 3189 }; 3190 3191 struct rtw89_btc_ver { 3192 enum rtw89_core_chip_id chip_id; 3193 u32 fw_ver_code; 3194 3195 u8 fcxbtcrpt; 3196 u8 fcxtdma; 3197 u8 fcxslots; 3198 u8 fcxcysta; 3199 u8 fcxstep; 3200 u8 fcxnullsta; 3201 u8 fcxmreg; 3202 u8 fcxgpiodbg; 3203 u8 fcxbtver; 3204 u8 fcxbtscan; 3205 u8 fcxbtafh; 3206 u8 fcxbtdevinfo; 3207 u8 fwlrole; 3208 u8 frptmap; 3209 u8 fcxctrl; 3210 u8 fcxinit; 3211 3212 u8 fwevntrptl; 3213 u8 fwc2hfunc; 3214 u8 drvinfo_type; 3215 u16 info_buf; 3216 u8 max_role_num; 3217 u8 fcxosi; 3218 u8 fcxmlo; 3219 u8 bt_desired; 3220 }; 3221 3222 struct rtw89_btc_btf_fwinfo { 3223 u32 cnt_c2h; 3224 u32 cnt_h2c; 3225 u32 cnt_h2c_fail; 3226 u32 event[BTF_EVNT_MAX]; 3227 3228 u32 err[BTFRE_MAX]; 3229 u32 len_mismch; 3230 u32 fver_mismch; 3231 u32 rpt_en_map; 3232 3233 struct rtw89_btc_ver fw_subver; 3234 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3235 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3236 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3237 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3238 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3239 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3240 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3241 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3242 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3243 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3244 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3245 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3246 }; 3247 3248 #define RTW89_BTC_POLICY_MAXLEN 512 3249 3250 struct rtw89_btc { 3251 const struct rtw89_btc_ver *ver; 3252 3253 struct rtw89_btc_cx cx; 3254 struct rtw89_btc_dm dm; 3255 union rtw89_btc_ctrl_list ctrl; 3256 union rtw89_btc_module_info mdinfo; 3257 struct rtw89_btc_btf_fwinfo fwinfo; 3258 struct rtw89_btc_dbg dbg; 3259 3260 struct wiphy_work eapol_notify_work; 3261 struct wiphy_work arp_notify_work; 3262 struct wiphy_work dhcp_notify_work; 3263 struct wiphy_work icmp_notify_work; 3264 3265 u32 bt_req_len; 3266 3267 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3268 u8 ant_type; 3269 u8 btg_pos; 3270 u16 policy_len; 3271 u16 policy_type; 3272 u32 hubmsg_cnt; 3273 bool bt_req_en; 3274 bool update_policy_force; 3275 bool lps; 3276 bool manual_ctrl; 3277 }; 3278 3279 enum rtw89_btc_hmsg { 3280 RTW89_BTC_HMSG_TMR_EN = 0x0, 3281 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3282 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3283 RTW89_BTC_HMSG_FW_EV = 0x3, 3284 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3285 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3286 3287 NUM_OF_RTW89_BTC_HMSG, 3288 }; 3289 3290 enum rtw89_ra_mode { 3291 RTW89_RA_MODE_CCK = BIT(0), 3292 RTW89_RA_MODE_OFDM = BIT(1), 3293 RTW89_RA_MODE_HT = BIT(2), 3294 RTW89_RA_MODE_VHT = BIT(3), 3295 RTW89_RA_MODE_HE = BIT(4), 3296 RTW89_RA_MODE_EHT = BIT(5), 3297 }; 3298 3299 enum rtw89_ra_report_mode { 3300 RTW89_RA_RPT_MODE_LEGACY, 3301 RTW89_RA_RPT_MODE_HT, 3302 RTW89_RA_RPT_MODE_VHT, 3303 RTW89_RA_RPT_MODE_HE, 3304 RTW89_RA_RPT_MODE_EHT, 3305 }; 3306 3307 enum rtw89_dig_noisy_level { 3308 RTW89_DIG_NOISY_LEVEL0 = -1, 3309 RTW89_DIG_NOISY_LEVEL1 = 0, 3310 RTW89_DIG_NOISY_LEVEL2 = 1, 3311 RTW89_DIG_NOISY_LEVEL3 = 2, 3312 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3313 }; 3314 3315 enum rtw89_gi_ltf { 3316 RTW89_GILTF_LGI_4XHE32 = 0, 3317 RTW89_GILTF_SGI_4XHE08 = 1, 3318 RTW89_GILTF_2XHE16 = 2, 3319 RTW89_GILTF_2XHE08 = 3, 3320 RTW89_GILTF_1XHE16 = 4, 3321 RTW89_GILTF_1XHE08 = 5, 3322 RTW89_GILTF_MAX 3323 }; 3324 3325 enum rtw89_rx_frame_type { 3326 RTW89_RX_TYPE_MGNT = 0, 3327 RTW89_RX_TYPE_CTRL = 1, 3328 RTW89_RX_TYPE_DATA = 2, 3329 RTW89_RX_TYPE_RSVD = 3, 3330 }; 3331 3332 enum rtw89_efuse_block { 3333 RTW89_EFUSE_BLOCK_SYS = 0, 3334 RTW89_EFUSE_BLOCK_RF = 1, 3335 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3336 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3337 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3338 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3339 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3340 RTW89_EFUSE_BLOCK_ADIE = 7, 3341 3342 RTW89_EFUSE_BLOCK_NUM, 3343 RTW89_EFUSE_BLOCK_IGNORE, 3344 }; 3345 3346 struct rtw89_ra_info { 3347 u8 is_dis_ra:1; 3348 /* Bit0 : CCK 3349 * Bit1 : OFDM 3350 * Bit2 : HT 3351 * Bit3 : VHT 3352 * Bit4 : HE 3353 * Bit5 : EHT 3354 */ 3355 u8 mode_ctrl:6; 3356 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3357 u8 macid; 3358 u8 dcm_cap:1; 3359 u8 er_cap:1; 3360 u8 init_rate_lv:2; 3361 u8 upd_all:1; 3362 u8 en_sgi:1; 3363 u8 ldpc_cap:1; 3364 u8 stbc_cap:1; 3365 u8 ss_num:3; 3366 u8 giltf:3; 3367 u8 upd_bw_nss_mask:1; 3368 u8 upd_mask:1; 3369 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3370 /* BFee CSI */ 3371 u8 band_num; 3372 u8 ra_csi_rate_en:1; 3373 u8 fixed_csi_rate_en:1; 3374 u8 cr_tbl_sel:1; 3375 u8 fix_giltf_en:1; 3376 u8 fix_giltf:3; 3377 u8 rsvd2:1; 3378 u8 csi_mcs_ss_idx; 3379 u8 csi_mode:2; 3380 u8 csi_gi_ltf:3; 3381 u8 csi_bw:3; 3382 }; 3383 3384 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3385 #define RTW89_PPDU_MAC_INFO_SIZE 8 3386 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3387 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3388 3389 #define RTW89_MAX_RX_AGG_NUM 64 3390 #define RTW89_MAX_TX_AGG_NUM 128 3391 3392 struct rtw89_ampdu_params { 3393 u16 agg_num; 3394 bool amsdu; 3395 }; 3396 3397 struct rtw89_ra_report { 3398 struct rate_info txrate; 3399 u32 bit_rate; 3400 u16 hw_rate; 3401 bool might_fallback_legacy; 3402 }; 3403 3404 DECLARE_EWMA(rssi, 10, 16); 3405 DECLARE_EWMA(evm, 10, 16); 3406 DECLARE_EWMA(snr, 10, 16); 3407 3408 struct rtw89_ba_cam_entry { 3409 struct list_head list; 3410 u8 tid; 3411 }; 3412 3413 #define RTW89_MAX_ADDR_CAM_NUM 128 3414 #define RTW89_MAX_BSSID_CAM_NUM 20 3415 #define RTW89_MAX_SEC_CAM_NUM 128 3416 #define RTW89_MAX_BA_CAM_NUM 24 3417 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3418 3419 struct rtw89_addr_cam_entry { 3420 u8 addr_cam_idx; 3421 u8 offset; 3422 u8 len; 3423 u8 valid : 1; 3424 u8 addr_mask : 6; 3425 u8 wapi : 1; 3426 u8 mask_sel : 2; 3427 u8 bssid_cam_idx: 6; 3428 3429 u8 sec_ent_mode; 3430 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3431 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3432 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3433 }; 3434 3435 struct rtw89_bssid_cam_entry { 3436 u8 bssid[ETH_ALEN]; 3437 u8 phy_idx; 3438 u8 bssid_cam_idx; 3439 u8 offset; 3440 u8 len; 3441 u8 valid : 1; 3442 u8 num; 3443 }; 3444 3445 struct rtw89_sec_cam_entry { 3446 u8 sec_cam_idx; 3447 u8 offset; 3448 u8 len; 3449 u8 type : 4; 3450 u8 ext_key : 1; 3451 u8 spp_mode : 1; 3452 /* 256 bits */ 3453 u8 key[32]; 3454 3455 struct ieee80211_key_conf *key_conf; 3456 }; 3457 3458 struct rtw89_sta_link { 3459 struct rtw89_sta *rtwsta; 3460 struct list_head dlink_schd; 3461 unsigned int link_id; 3462 3463 u8 mac_id; 3464 u8 tx_retry; 3465 bool er_cap; 3466 struct rtw89_vif_link *rtwvif_link; 3467 struct rtw89_ra_info ra; 3468 struct rtw89_ra_report ra_report; 3469 int max_agg_wait; 3470 u8 prev_rssi; 3471 struct ewma_rssi avg_rssi; 3472 struct ewma_rssi rssi[RF_PATH_MAX]; 3473 struct ewma_snr avg_snr; 3474 struct ewma_evm evm_1ss; 3475 struct ewma_evm evm_min[RF_PATH_MAX]; 3476 struct ewma_evm evm_max[RF_PATH_MAX]; 3477 struct ieee80211_rx_status rx_status; 3478 u16 rx_hw_rate; 3479 __le32 htc_template; 3480 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3481 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3482 struct list_head ba_cam_list; 3483 3484 bool use_cfg_mask; 3485 struct cfg80211_bitrate_mask mask; 3486 3487 bool cctl_tx_time; 3488 u32 ampdu_max_time:4; 3489 bool cctl_tx_retry_limit; 3490 u32 data_tx_cnt_lmt:6; 3491 }; 3492 3493 struct rtw89_efuse { 3494 bool valid; 3495 bool power_k_valid; 3496 u8 xtal_cap; 3497 u8 addr[ETH_ALEN]; 3498 u8 rfe_type; 3499 char country_code[2]; 3500 u8 adc_td; 3501 }; 3502 3503 struct rtw89_phy_rate_pattern { 3504 u64 ra_mask; 3505 u16 rate; 3506 u8 ra_mode; 3507 bool enable; 3508 }; 3509 3510 #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500) 3511 struct rtw89_tx_wait_info { 3512 struct rcu_head rcu_head; 3513 struct list_head list; 3514 struct completion completion; 3515 struct sk_buff *skb; 3516 bool tx_done; 3517 }; 3518 3519 struct rtw89_tx_skb_data { 3520 struct rtw89_tx_wait_info __rcu *wait; 3521 u8 hci_priv[]; 3522 }; 3523 3524 #define RTW89_SCAN_NULL_TIMEOUT 30 3525 3526 #define RTW89_ROC_IDLE_TIMEOUT 500 3527 #define RTW89_ROC_TX_TIMEOUT 30 3528 enum rtw89_roc_state { 3529 RTW89_ROC_IDLE, 3530 RTW89_ROC_NORMAL, 3531 RTW89_ROC_MGMT, 3532 }; 3533 3534 struct rtw89_roc { 3535 struct ieee80211_channel chan; 3536 struct wiphy_delayed_work roc_work; 3537 enum ieee80211_roc_type type; 3538 enum rtw89_roc_state state; 3539 int duration; 3540 unsigned int link_id; 3541 }; 3542 3543 #define RTW89_P2P_MAX_NOA_NUM 2 3544 3545 struct rtw89_p2p_ie_head { 3546 u8 eid; 3547 u8 ie_len; 3548 u8 oui[3]; 3549 u8 oui_type; 3550 } __packed; 3551 3552 struct rtw89_noa_attr_head { 3553 u8 attr_type; 3554 __le16 attr_len; 3555 u8 index; 3556 u8 oppps_ctwindow; 3557 } __packed; 3558 3559 struct rtw89_p2p_noa_ie { 3560 struct rtw89_p2p_ie_head p2p_head; 3561 struct rtw89_noa_attr_head noa_head; 3562 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3563 } __packed; 3564 3565 struct rtw89_p2p_noa_setter { 3566 struct rtw89_p2p_noa_ie ie; 3567 u8 noa_count; 3568 u8 noa_index; 3569 }; 3570 3571 struct rtw89_ps_noa_once_handler { 3572 bool in_duration; 3573 u64 tsf_begin; 3574 u64 tsf_end; 3575 struct wiphy_delayed_work set_work; 3576 struct wiphy_delayed_work clr_work; 3577 }; 3578 3579 struct rtw89_vif_link { 3580 struct rtw89_vif *rtwvif; 3581 struct list_head dlink_schd; 3582 unsigned int link_id; 3583 3584 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3585 enum rtw89_chanctx_idx chanctx_idx; 3586 enum rtw89_reg_6ghz_power reg_6ghz_power; 3587 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3588 3589 u8 mac_id; 3590 u8 port; 3591 u8 mac_addr[ETH_ALEN]; 3592 u8 bssid[ETH_ALEN]; 3593 u8 phy_idx; 3594 u8 mac_idx; 3595 u8 net_type; 3596 u8 wifi_role; 3597 u8 self_role; 3598 u8 wmm; 3599 u8 bcn_hit_cond; 3600 u8 bcn_bw_idx; 3601 u8 hit_rule; 3602 u8 last_noa_nr; 3603 u64 sync_bcn_tsf; 3604 u64 last_sync_bcn_tsf; 3605 bool rand_tsf_done; 3606 bool trigger; 3607 bool lsig_txop; 3608 u8 tgt_ind; 3609 u8 frm_tgt_ind; 3610 bool wowlan_pattern; 3611 bool wowlan_uc; 3612 bool wowlan_magic; 3613 bool is_hesta; 3614 bool last_a_ctrl; 3615 bool dyn_tb_bedge_en; 3616 bool pre_pwr_diff_en; 3617 bool pwr_diff_en; 3618 u8 def_tri_idx; 3619 struct wiphy_work update_beacon_work; 3620 struct wiphy_delayed_work csa_beacon_work; 3621 struct rtw89_addr_cam_entry addr_cam; 3622 struct rtw89_bssid_cam_entry bssid_cam; 3623 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3624 struct rtw89_phy_rate_pattern rate_pattern; 3625 struct list_head general_pkt_list; 3626 struct rtw89_p2p_noa_setter p2p_noa; 3627 struct rtw89_ps_noa_once_handler noa_once; 3628 struct wiphy_delayed_work mcc_gc_detect_beacon_work; 3629 u8 detect_bcn_count; 3630 }; 3631 3632 enum rtw89_lv1_rcvy_step { 3633 RTW89_LV1_RCVY_STEP_1, 3634 RTW89_LV1_RCVY_STEP_2, 3635 }; 3636 3637 struct rtw89_hci_ops { 3638 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3639 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3640 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3641 void (*reset)(struct rtw89_dev *rtwdev); 3642 int (*start)(struct rtw89_dev *rtwdev); 3643 void (*stop)(struct rtw89_dev *rtwdev); 3644 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3645 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3646 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3647 3648 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3649 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3650 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3651 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3652 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3653 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3654 3655 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3656 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3657 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3658 int (*deinit)(struct rtw89_dev *rtwdev); 3659 3660 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3661 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3662 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3663 int (*napi_poll)(struct napi_struct *napi, int budget); 3664 3665 /* Deal with locks inside recovery_start and recovery_complete callbacks 3666 * by hci instance, and handle things which need to consider under SER. 3667 * e.g. turn on/off interrupts except for the one for halt notification. 3668 */ 3669 void (*recovery_start)(struct rtw89_dev *rtwdev); 3670 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3671 3672 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3673 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3674 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3675 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3676 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3677 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3678 void (*disable_intr)(struct rtw89_dev *rtwdev); 3679 void (*enable_intr)(struct rtw89_dev *rtwdev); 3680 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3681 }; 3682 3683 struct rtw89_hci_info { 3684 const struct rtw89_hci_ops *ops; 3685 enum rtw89_hci_type type; 3686 enum rtw89_hci_dle_type dle_type; 3687 u32 rpwm_addr; 3688 u32 cpwm_addr; 3689 bool paused; 3690 }; 3691 3692 struct rtw89_chip_ops { 3693 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3694 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3695 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3696 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3697 void (*bb_reset)(struct rtw89_dev *rtwdev, 3698 enum rtw89_phy_idx phy_idx); 3699 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3700 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3701 u32 addr, u32 mask); 3702 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3703 u32 addr, u32 mask, u32 data); 3704 void (*set_channel)(struct rtw89_dev *rtwdev, 3705 const struct rtw89_chan *chan, 3706 enum rtw89_mac_idx mac_idx, 3707 enum rtw89_phy_idx phy_idx); 3708 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3709 struct rtw89_channel_help_params *p, 3710 const struct rtw89_chan *chan, 3711 enum rtw89_mac_idx mac_idx, 3712 enum rtw89_phy_idx phy_idx); 3713 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3714 enum rtw89_efuse_block block); 3715 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3716 void (*fem_setup)(struct rtw89_dev *rtwdev); 3717 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3718 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3719 void (*rfk_init)(struct rtw89_dev *rtwdev); 3720 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3721 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3722 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3723 enum rtw89_phy_idx phy_idx, 3724 const struct rtw89_chan *chan); 3725 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3726 bool start); 3727 void (*rfk_track)(struct rtw89_dev *rtwdev); 3728 void (*power_trim)(struct rtw89_dev *rtwdev); 3729 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3730 const struct rtw89_chan *chan, 3731 enum rtw89_phy_idx phy_idx); 3732 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3733 enum rtw89_phy_idx phy_idx); 3734 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3735 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3736 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev, 3737 const struct rtw89_chan *chan); 3738 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3739 enum rtw89_phy_idx phy_idx); 3740 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3741 struct rtw89_rx_phy_ppdu *phy_ppdu, 3742 struct ieee80211_rx_status *status); 3743 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3744 struct rtw89_rx_phy_ppdu *phy_ppdu); 3745 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3746 struct rtw89_rx_desc_info *desc_info, 3747 struct ieee80211_rx_status *rx_status); 3748 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3749 enum rtw89_phy_idx phy_idx); 3750 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3751 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3752 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3753 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3754 enum rtw89_phy_idx phy_idx); 3755 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3756 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3757 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3758 struct rtw89_rx_desc_info *desc_info, 3759 u8 *data, u32 data_offset); 3760 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3761 struct rtw89_tx_desc_info *desc_info, 3762 void *txdesc); 3763 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3764 struct rtw89_tx_desc_info *desc_info, 3765 void *txdesc); 3766 u8 (*get_ch_dma)(struct rtw89_dev *rtwdev, u8 qsel); 3767 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3768 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3769 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3770 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3771 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3772 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3773 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3774 struct rtw89_vif_link *rtwvif_link, 3775 struct rtw89_sta_link *rtwsta_link); 3776 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3777 struct rtw89_vif_link *rtwvif_link, 3778 struct rtw89_sta_link *rtwsta_link); 3779 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3780 struct rtw89_vif_link *rtwvif_link, 3781 struct rtw89_sta_link *rtwsta_link); 3782 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3783 struct rtw89_vif_link *rtwvif_link, 3784 struct rtw89_sta_link *rtwsta_link); 3785 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 3786 struct rtw89_sta_link *rtwsta_link); 3787 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev, 3788 struct rtw89_vif_link *rtwvif_link, 3789 u16 punctured); 3790 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3791 struct rtw89_vif_link *rtwvif_link, 3792 struct rtw89_sta_link *rtwsta_link); 3793 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3794 struct rtw89_vif_link *rtwvif_link); 3795 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3796 struct rtw89_vif_link *rtwvif_link, 3797 struct rtw89_sta_link *rtwsta_link, 3798 bool valid, struct ieee80211_ampdu_params *params); 3799 3800 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3801 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3802 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3803 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3804 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3805 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3806 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3807 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3808 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3809 }; 3810 3811 enum rtw89_dma_ch { 3812 RTW89_DMA_ACH0 = 0, 3813 RTW89_DMA_ACH1 = 1, 3814 RTW89_DMA_ACH2 = 2, 3815 RTW89_DMA_ACH3 = 3, 3816 RTW89_DMA_ACH4 = 4, 3817 RTW89_DMA_ACH5 = 5, 3818 RTW89_DMA_ACH6 = 6, 3819 RTW89_DMA_ACH7 = 7, 3820 RTW89_DMA_B0MG = 8, 3821 RTW89_DMA_B0HI = 9, 3822 RTW89_DMA_B1MG = 10, 3823 RTW89_DMA_B1HI = 11, 3824 RTW89_DMA_H2C = 12, 3825 RTW89_DMA_CH_NUM = 13 3826 }; 3827 3828 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3829 3830 enum rtw89_mlo_dbcc_mode { 3831 MLO_DBCC_NOT_SUPPORT = 1, 3832 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3833 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3834 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3835 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3836 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3837 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3838 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3839 DBCC_LEGACY = 0xffffffff, 3840 }; 3841 3842 enum rtw89_scan_be_operation { 3843 RTW89_SCAN_OP_STOP, 3844 RTW89_SCAN_OP_START, 3845 RTW89_SCAN_OP_SETPARM, 3846 RTW89_SCAN_OP_GETRPT, 3847 RTW89_SCAN_OP_NUM 3848 }; 3849 3850 enum rtw89_scan_be_mode { 3851 RTW89_SCAN_MODE_SA, 3852 RTW89_SCAN_MODE_MACC, 3853 RTW89_SCAN_MODE_NUM 3854 }; 3855 3856 enum rtw89_scan_be_opmode { 3857 RTW89_SCAN_OPMODE_NONE, 3858 RTW89_SCAN_OPMODE_TBTT, 3859 RTW89_SCAN_OPMODE_INTV, 3860 RTW89_SCAN_OPMODE_CNT, 3861 RTW89_SCAN_OPMODE_NUM, 3862 }; 3863 3864 struct rtw89_scan_option { 3865 bool enable; 3866 bool target_ch_mode; 3867 u8 num_macc_role; 3868 u8 num_opch; 3869 u8 repeat; 3870 u16 norm_pd; 3871 u16 slow_pd; 3872 u16 norm_cy; 3873 u8 opch_end; 3874 u16 delay; /* in unit of ms */ 3875 u64 prohib_chan; 3876 enum rtw89_phy_idx band; 3877 enum rtw89_scan_be_operation operation; 3878 enum rtw89_scan_be_mode scan_mode; 3879 enum rtw89_mlo_dbcc_mode mlo_mode; 3880 }; 3881 3882 enum rtw89_qta_mode { 3883 RTW89_QTA_SCC, 3884 RTW89_QTA_DBCC, 3885 RTW89_QTA_DLFW, 3886 RTW89_QTA_WOW, 3887 3888 /* keep last */ 3889 RTW89_QTA_INVALID, 3890 }; 3891 3892 struct rtw89_hfc_ch_cfg { 3893 u16 min; 3894 u16 max; 3895 #define grp_0 0 3896 #define grp_1 1 3897 #define grp_num 2 3898 u8 grp; 3899 }; 3900 3901 struct rtw89_hfc_ch_info { 3902 u16 aval; 3903 u16 used; 3904 }; 3905 3906 struct rtw89_hfc_pub_cfg { 3907 u16 grp0; 3908 u16 grp1; 3909 u16 pub_max; 3910 u16 wp_thrd; 3911 }; 3912 3913 struct rtw89_hfc_pub_info { 3914 u16 g0_used; 3915 u16 g1_used; 3916 u16 g0_aval; 3917 u16 g1_aval; 3918 u16 pub_aval; 3919 u16 wp_aval; 3920 }; 3921 3922 struct rtw89_hfc_prec_cfg { 3923 u16 ch011_prec; 3924 u16 h2c_prec; 3925 u16 wp_ch07_prec; 3926 u16 wp_ch811_prec; 3927 u8 ch011_full_cond; 3928 u8 h2c_full_cond; 3929 u8 wp_ch07_full_cond; 3930 u8 wp_ch811_full_cond; 3931 }; 3932 3933 struct rtw89_hfc_param { 3934 bool en; 3935 bool h2c_en; 3936 u8 mode; 3937 const struct rtw89_hfc_ch_cfg *ch_cfg; 3938 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3939 struct rtw89_hfc_pub_cfg pub_cfg; 3940 struct rtw89_hfc_pub_info pub_info; 3941 struct rtw89_hfc_prec_cfg prec_cfg; 3942 }; 3943 3944 struct rtw89_hfc_param_ini { 3945 const struct rtw89_hfc_ch_cfg *ch_cfg; 3946 const struct rtw89_hfc_pub_cfg *pub_cfg; 3947 const struct rtw89_hfc_prec_cfg *prec_cfg; 3948 u8 mode; 3949 }; 3950 3951 struct rtw89_dle_size { 3952 u16 pge_size; 3953 u16 lnk_pge_num; 3954 u16 unlnk_pge_num; 3955 /* for WiFi 7 chips below */ 3956 u32 srt_ofst; 3957 }; 3958 3959 struct rtw89_wde_quota { 3960 u16 hif; 3961 u16 wcpu; 3962 u16 pkt_in; 3963 u16 cpu_io; 3964 }; 3965 3966 struct rtw89_ple_quota { 3967 u16 cma0_tx; 3968 u16 cma1_tx; 3969 u16 c2h; 3970 u16 h2c; 3971 u16 wcpu; 3972 u16 mpdu_proc; 3973 u16 cma0_dma; 3974 u16 cma1_dma; 3975 u16 bb_rpt; 3976 u16 wd_rel; 3977 u16 cpu_io; 3978 u16 tx_rpt; 3979 /* for WiFi 7 chips below */ 3980 u16 h2d; 3981 }; 3982 3983 struct rtw89_rsvd_quota { 3984 u16 mpdu_info_tbl; 3985 u16 b0_csi; 3986 u16 b1_csi; 3987 u16 b0_lmr; 3988 u16 b1_lmr; 3989 u16 b0_ftm; 3990 u16 b1_ftm; 3991 u16 b0_smr; 3992 u16 b1_smr; 3993 u16 others; 3994 }; 3995 3996 struct rtw89_dle_rsvd_size { 3997 u32 srt_ofst; 3998 u32 size; 3999 }; 4000 4001 struct rtw89_dle_mem { 4002 enum rtw89_qta_mode mode; 4003 const struct rtw89_dle_size *wde_size; 4004 const struct rtw89_dle_size *ple_size; 4005 const struct rtw89_wde_quota *wde_min_qt; 4006 const struct rtw89_wde_quota *wde_max_qt; 4007 const struct rtw89_ple_quota *ple_min_qt; 4008 const struct rtw89_ple_quota *ple_max_qt; 4009 /* for WiFi 7 chips below */ 4010 const struct rtw89_rsvd_quota *rsvd_qt; 4011 const struct rtw89_dle_rsvd_size *rsvd0_size; 4012 const struct rtw89_dle_rsvd_size *rsvd1_size; 4013 }; 4014 4015 struct rtw89_reg_def { 4016 u32 addr; 4017 u32 mask; 4018 }; 4019 4020 struct rtw89_reg2_def { 4021 u32 addr; 4022 u32 data; 4023 }; 4024 4025 struct rtw89_reg3_def { 4026 u32 addr; 4027 u32 mask; 4028 u32 data; 4029 }; 4030 4031 struct rtw89_reg5_def { 4032 u8 flag; /* recognized by parsers */ 4033 u8 path; 4034 u32 addr; 4035 u32 mask; 4036 u32 data; 4037 }; 4038 4039 struct rtw89_reg_imr { 4040 u32 addr; 4041 u32 clr; 4042 u32 set; 4043 }; 4044 4045 struct rtw89_phy_table { 4046 const struct rtw89_reg2_def *regs; 4047 u32 n_regs; 4048 enum rtw89_rf_path rf_path; 4049 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 4050 enum rtw89_rf_path rf_path, void *data); 4051 }; 4052 4053 struct rtw89_txpwr_table { 4054 const void *data; 4055 u32 size; 4056 void (*load)(struct rtw89_dev *rtwdev, 4057 const struct rtw89_txpwr_table *tbl); 4058 }; 4059 4060 struct rtw89_txpwr_rule_2ghz { 4061 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4062 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4063 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4064 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4065 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4066 }; 4067 4068 struct rtw89_txpwr_rule_5ghz { 4069 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4070 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4071 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4072 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4073 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4074 }; 4075 4076 struct rtw89_txpwr_rule_6ghz { 4077 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4078 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4079 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4080 [RTW89_6G_CH_NUM]; 4081 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4082 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4083 [RTW89_6G_CH_NUM]; 4084 }; 4085 4086 struct rtw89_tx_shape { 4087 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4088 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4089 }; 4090 4091 struct rtw89_rfe_parms { 4092 const struct rtw89_txpwr_table *byr_tbl; 4093 struct rtw89_txpwr_rule_2ghz rule_2ghz; 4094 struct rtw89_txpwr_rule_5ghz rule_5ghz; 4095 struct rtw89_txpwr_rule_6ghz rule_6ghz; 4096 struct rtw89_txpwr_rule_2ghz rule_da_2ghz; 4097 struct rtw89_txpwr_rule_5ghz rule_da_5ghz; 4098 struct rtw89_txpwr_rule_6ghz rule_da_6ghz; 4099 struct rtw89_tx_shape tx_shape; 4100 bool has_da; 4101 }; 4102 4103 struct rtw89_rfe_parms_conf { 4104 const struct rtw89_rfe_parms *rfe_parms; 4105 u8 rfe_type; 4106 }; 4107 4108 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 4109 4110 struct rtw89_txpwr_conf { 4111 u8 rfe_type; 4112 u8 ent_sz; 4113 u32 num_ents; 4114 const void *data; 4115 }; 4116 4117 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4118 const struct rtw89_txpwr_conf *conf) 4119 { 4120 u8 valid_size = min(size, conf->ent_sz); 4121 4122 memcpy(entry, cursor, valid_size); 4123 return true; 4124 } 4125 4126 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4127 4128 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4129 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4130 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4131 (cursor) += (conf)->ent_sz) \ 4132 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4133 4134 struct rtw89_txpwr_byrate_data { 4135 struct rtw89_txpwr_conf conf; 4136 struct rtw89_txpwr_table tbl; 4137 }; 4138 4139 struct rtw89_txpwr_lmt_2ghz_data { 4140 struct rtw89_txpwr_conf conf; 4141 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4142 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4143 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4144 }; 4145 4146 struct rtw89_txpwr_lmt_5ghz_data { 4147 struct rtw89_txpwr_conf conf; 4148 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4149 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4150 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4151 }; 4152 4153 struct rtw89_txpwr_lmt_6ghz_data { 4154 struct rtw89_txpwr_conf conf; 4155 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4156 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4157 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4158 [RTW89_6G_CH_NUM]; 4159 }; 4160 4161 struct rtw89_txpwr_lmt_ru_2ghz_data { 4162 struct rtw89_txpwr_conf conf; 4163 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4164 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4165 }; 4166 4167 struct rtw89_txpwr_lmt_ru_5ghz_data { 4168 struct rtw89_txpwr_conf conf; 4169 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4170 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4171 }; 4172 4173 struct rtw89_txpwr_lmt_ru_6ghz_data { 4174 struct rtw89_txpwr_conf conf; 4175 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4176 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4177 [RTW89_6G_CH_NUM]; 4178 }; 4179 4180 struct rtw89_tx_shape_lmt_data { 4181 struct rtw89_txpwr_conf conf; 4182 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4183 }; 4184 4185 struct rtw89_tx_shape_lmt_ru_data { 4186 struct rtw89_txpwr_conf conf; 4187 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4188 }; 4189 4190 struct rtw89_rfe_data { 4191 struct rtw89_txpwr_byrate_data byrate; 4192 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4193 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4194 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4195 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz; 4196 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz; 4197 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz; 4198 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4199 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4200 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4201 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz; 4202 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz; 4203 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz; 4204 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4205 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4206 struct rtw89_rfe_parms rfe_parms; 4207 }; 4208 4209 struct rtw89_page_regs { 4210 u32 hci_fc_ctrl; 4211 u32 ch_page_ctrl; 4212 u32 ach_page_ctrl; 4213 u32 ach_page_info; 4214 u32 pub_page_info3; 4215 u32 pub_page_ctrl1; 4216 u32 pub_page_ctrl2; 4217 u32 pub_page_info1; 4218 u32 pub_page_info2; 4219 u32 wp_page_ctrl1; 4220 u32 wp_page_ctrl2; 4221 u32 wp_page_info1; 4222 }; 4223 4224 struct rtw89_imr_info { 4225 u32 wdrls_imr_set; 4226 u32 wsec_imr_reg; 4227 u32 wsec_imr_set; 4228 u32 mpdu_tx_imr_set; 4229 u32 mpdu_rx_imr_set; 4230 u32 sta_sch_imr_set; 4231 u32 txpktctl_imr_b0_reg; 4232 u32 txpktctl_imr_b0_clr; 4233 u32 txpktctl_imr_b0_set; 4234 u32 txpktctl_imr_b1_reg; 4235 u32 txpktctl_imr_b1_clr; 4236 u32 txpktctl_imr_b1_set; 4237 u32 wde_imr_clr; 4238 u32 wde_imr_set; 4239 u32 ple_imr_clr; 4240 u32 ple_imr_set; 4241 u32 host_disp_imr_clr; 4242 u32 host_disp_imr_set; 4243 u32 cpu_disp_imr_clr; 4244 u32 cpu_disp_imr_set; 4245 u32 other_disp_imr_clr; 4246 u32 other_disp_imr_set; 4247 u32 bbrpt_com_err_imr_reg; 4248 u32 bbrpt_chinfo_err_imr_reg; 4249 u32 bbrpt_err_imr_set; 4250 u32 bbrpt_dfs_err_imr_reg; 4251 u32 ptcl_imr_clr; 4252 u32 ptcl_imr_set; 4253 u32 cdma_imr_0_reg; 4254 u32 cdma_imr_0_clr; 4255 u32 cdma_imr_0_set; 4256 u32 cdma_imr_1_reg; 4257 u32 cdma_imr_1_clr; 4258 u32 cdma_imr_1_set; 4259 u32 phy_intf_imr_reg; 4260 u32 phy_intf_imr_clr; 4261 u32 phy_intf_imr_set; 4262 u32 rmac_imr_reg; 4263 u32 rmac_imr_clr; 4264 u32 rmac_imr_set; 4265 u32 tmac_imr_reg; 4266 u32 tmac_imr_clr; 4267 u32 tmac_imr_set; 4268 }; 4269 4270 struct rtw89_imr_table { 4271 const struct rtw89_reg_imr *regs; 4272 u32 n_regs; 4273 }; 4274 4275 struct rtw89_xtal_info { 4276 u32 xcap_reg; 4277 u32 sc_xo_mask; 4278 u32 sc_xi_mask; 4279 }; 4280 4281 struct rtw89_rrsr_cfgs { 4282 struct rtw89_reg3_def ref_rate; 4283 struct rtw89_reg3_def rsc; 4284 }; 4285 4286 struct rtw89_rfkill_regs { 4287 struct rtw89_reg3_def pinmux; 4288 struct rtw89_reg3_def mode; 4289 }; 4290 4291 struct rtw89_dig_regs { 4292 u32 seg0_pd_reg; 4293 u32 pd_lower_bound_mask; 4294 u32 pd_spatial_reuse_en; 4295 u32 bmode_pd_reg; 4296 u32 bmode_cca_rssi_limit_en; 4297 u32 bmode_pd_lower_bound_reg; 4298 u32 bmode_rssi_nocca_low_th_mask; 4299 struct rtw89_reg_def p0_lna_init; 4300 struct rtw89_reg_def p1_lna_init; 4301 struct rtw89_reg_def p0_tia_init; 4302 struct rtw89_reg_def p1_tia_init; 4303 struct rtw89_reg_def p0_rxb_init; 4304 struct rtw89_reg_def p1_rxb_init; 4305 struct rtw89_reg_def p0_p20_pagcugc_en; 4306 struct rtw89_reg_def p0_s20_pagcugc_en; 4307 struct rtw89_reg_def p1_p20_pagcugc_en; 4308 struct rtw89_reg_def p1_s20_pagcugc_en; 4309 }; 4310 4311 struct rtw89_edcca_regs { 4312 u32 edcca_level; 4313 u32 edcca_mask; 4314 u32 edcca_p_mask; 4315 u32 ppdu_level; 4316 u32 ppdu_mask; 4317 struct rtw89_edcca_p_regs { 4318 u32 rpt_a; 4319 u32 rpt_b; 4320 u32 rpt_sel; 4321 u32 rpt_sel_mask; 4322 } p[RTW89_PHY_NUM]; 4323 u32 rpt_sel_be; 4324 u32 rpt_sel_be_mask; 4325 u32 tx_collision_t2r_st; 4326 u32 tx_collision_t2r_st_mask; 4327 }; 4328 4329 struct rtw89_phy_ul_tb_info { 4330 bool dyn_tb_tri_en; 4331 u8 def_if_bandedge; 4332 }; 4333 4334 struct rtw89_antdiv_stats { 4335 struct ewma_rssi cck_rssi_avg; 4336 struct ewma_rssi ofdm_rssi_avg; 4337 struct ewma_rssi non_legacy_rssi_avg; 4338 u16 pkt_cnt_cck; 4339 u16 pkt_cnt_ofdm; 4340 u16 pkt_cnt_non_legacy; 4341 u32 evm; 4342 }; 4343 4344 struct rtw89_antdiv_info { 4345 struct rtw89_antdiv_stats target_stats; 4346 struct rtw89_antdiv_stats main_stats; 4347 struct rtw89_antdiv_stats aux_stats; 4348 u8 training_count; 4349 u8 rssi_pre; 4350 bool get_stats; 4351 }; 4352 4353 enum rtw89_chanctx_state { 4354 RTW89_CHANCTX_STATE_MCC_START, 4355 RTW89_CHANCTX_STATE_MCC_STOP, 4356 }; 4357 4358 enum rtw89_chanctx_callbacks { 4359 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4360 RTW89_CHANCTX_CALLBACK_RFK, 4361 RTW89_CHANCTX_CALLBACK_TAS, 4362 4363 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4364 }; 4365 4366 struct rtw89_chanctx_listener { 4367 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4368 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4369 }; 4370 4371 #define RTW89_NHM_TH_NUM 11 4372 #define RTW89_NHM_RPT_NUM 12 4373 4374 struct rtw89_chip_info { 4375 enum rtw89_core_chip_id chip_id; 4376 enum rtw89_chip_gen chip_gen; 4377 const struct rtw89_chip_ops *ops; 4378 const struct rtw89_mac_gen_def *mac_def; 4379 const struct rtw89_phy_gen_def *phy_def; 4380 const char *fw_basename; 4381 u8 fw_format_max; 4382 bool try_ce_fw; 4383 u8 bbmcu_nr; 4384 u32 needed_fw_elms; 4385 const struct rtw89_fw_blacklist *fw_blacklist; 4386 u32 fifo_size; 4387 bool small_fifo_size; 4388 u32 dle_scc_rsvd_size; 4389 u16 max_amsdu_limit; 4390 bool dis_2g_40m_ul_ofdma; 4391 u32 rsvd_ple_ofst; 4392 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM]; 4393 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM]; 4394 u8 wde_qempty_acq_grpnum; 4395 u8 wde_qempty_mgq_grpsel; 4396 u32 rf_base_addr[2]; 4397 u8 thermal_th[2]; 4398 u8 support_macid_num; 4399 u8 support_link_num; 4400 u8 support_chanctx_num; 4401 u8 support_bands; 4402 u16 support_bandwidths; 4403 bool support_unii4; 4404 bool support_rnr; 4405 bool support_ant_gain; 4406 bool support_tas; 4407 bool support_sar_by_ant; 4408 bool support_noise; 4409 bool ul_tb_waveform_ctrl; 4410 bool ul_tb_pwr_diff; 4411 bool rx_freq_frome_ie; 4412 bool hw_sec_hdr; 4413 bool hw_mgmt_tx_encrypt; 4414 bool hw_tkip_crypto; 4415 bool hw_mlo_bmc_crypto; 4416 u8 rf_path_num; 4417 u8 tx_nss; 4418 u8 rx_nss; 4419 u8 acam_num; 4420 u8 bcam_num; 4421 u8 scam_num; 4422 u8 bacam_num; 4423 u8 bacam_dynamic_num; 4424 enum rtw89_bacam_ver bacam_ver; 4425 u8 ppdu_max_usr; 4426 4427 u8 sec_ctrl_efuse_size; 4428 u32 physical_efuse_size; 4429 u32 logical_efuse_size; 4430 u32 limit_efuse_size; 4431 u32 dav_phy_efuse_size; 4432 u32 dav_log_efuse_size; 4433 u32 phycap_addr; 4434 u32 phycap_size; 4435 const struct rtw89_efuse_block_cfg *efuse_blocks; 4436 4437 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4438 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4439 const struct rtw89_phy_table *bb_table; 4440 const struct rtw89_phy_table *bb_gain_table; 4441 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4442 const struct rtw89_phy_table *nctl_table; 4443 const struct rtw89_rfk_tbl *nctl_post_table; 4444 const struct rtw89_phy_dig_gain_table *dig_table; 4445 const struct rtw89_dig_regs *dig_regs; 4446 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4447 4448 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4449 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4450 const struct rtw89_rfe_parms *dflt_parms; 4451 const struct rtw89_chanctx_listener *chanctx_listener; 4452 4453 u8 txpwr_factor_bb; 4454 u8 txpwr_factor_rf; 4455 u8 txpwr_factor_mac; 4456 4457 u32 para_ver; 4458 u32 wlcx_desired; 4459 u8 scbd; 4460 u8 mailbox; 4461 4462 u8 afh_guard_ch; 4463 const u8 *wl_rssi_thres; 4464 const u8 *bt_rssi_thres; 4465 u8 rssi_tol; 4466 4467 u8 mon_reg_num; 4468 const struct rtw89_btc_fbtc_mreg *mon_reg; 4469 u8 rf_para_ulink_num; 4470 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4471 u8 rf_para_dlink_num; 4472 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4473 u8 ps_mode_supported; 4474 u8 low_power_hci_modes; 4475 4476 u32 h2c_cctl_func_id; 4477 u32 hci_func_en_addr; 4478 u32 h2c_desc_size; 4479 u32 txwd_body_size; 4480 u32 txwd_info_size; 4481 u32 h2c_ctrl_reg; 4482 const u32 *h2c_regs; 4483 struct rtw89_reg_def h2c_counter_reg; 4484 u32 c2h_ctrl_reg; 4485 const u32 *c2h_regs; 4486 struct rtw89_reg_def c2h_counter_reg; 4487 const struct rtw89_page_regs *page_regs; 4488 const u32 *wow_reason_reg; 4489 bool cfo_src_fd; 4490 bool cfo_hw_comp; 4491 const struct rtw89_reg_def *dcfo_comp; 4492 u8 dcfo_comp_sft; 4493 const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM]; 4494 const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM]; 4495 const struct rtw89_imr_info *imr_info; 4496 const struct rtw89_imr_table *imr_dmac_table; 4497 const struct rtw89_imr_table *imr_cmac_table; 4498 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4499 struct rtw89_reg_def bss_clr_vld; 4500 u32 bss_clr_map_reg; 4501 const struct rtw89_rfkill_regs *rfkill_init; 4502 struct rtw89_reg_def rfkill_get; 4503 u32 dma_ch_mask; 4504 const struct rtw89_edcca_regs *edcca_regs; 4505 const struct wiphy_wowlan_support *wowlan_stub; 4506 const struct rtw89_xtal_info *xtal_info; 4507 }; 4508 4509 struct rtw89_chip_variant { 4510 bool no_mcs_12_13: 1; 4511 u32 fw_min_ver_code; 4512 }; 4513 4514 union rtw89_bus_info { 4515 const struct rtw89_pci_info *pci; 4516 }; 4517 4518 struct rtw89_driver_info { 4519 const struct rtw89_chip_info *chip; 4520 const struct rtw89_chip_variant *variant; 4521 const struct dmi_system_id *quirks; 4522 union rtw89_bus_info bus; 4523 }; 4524 4525 enum rtw89_hcifc_mode { 4526 RTW89_HCIFC_POH = 0, 4527 RTW89_HCIFC_STF = 1, 4528 RTW89_HCIFC_SDIO = 2, 4529 4530 /* keep last */ 4531 RTW89_HCIFC_MODE_INVALID, 4532 }; 4533 4534 struct rtw89_dle_info { 4535 const struct rtw89_rsvd_quota *rsvd_qt; 4536 enum rtw89_qta_mode qta_mode; 4537 u16 ple_pg_size; 4538 u16 ple_free_pg; 4539 u16 c0_rx_qta; 4540 u16 c1_rx_qta; 4541 }; 4542 4543 enum rtw89_host_rpr_mode { 4544 RTW89_RPR_MODE_POH = 0, 4545 RTW89_RPR_MODE_STF 4546 }; 4547 4548 #define RTW89_COMPLETION_BUF_SIZE 40 4549 #define RTW89_WAIT_COND_IDLE UINT_MAX 4550 4551 struct rtw89_completion_data { 4552 bool err; 4553 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4554 }; 4555 4556 struct rtw89_wait_response { 4557 struct rcu_head rcu_head; 4558 struct completion completion; 4559 struct rtw89_completion_data data; 4560 }; 4561 4562 struct rtw89_wait_info { 4563 atomic_t cond; 4564 struct rtw89_completion_data data; 4565 struct rtw89_wait_response __rcu *resp; 4566 }; 4567 4568 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4569 4570 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4571 { 4572 rcu_assign_pointer(wait->resp, NULL); 4573 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4574 } 4575 4576 struct rtw89_mac_info { 4577 struct rtw89_dle_info dle_info; 4578 struct rtw89_hfc_param hfc_param; 4579 enum rtw89_qta_mode qta_mode; 4580 u8 rpwm_seq_num; 4581 u8 cpwm_seq_num; 4582 4583 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4584 struct rtw89_wait_info fw_ofld_wait; 4585 /* see RTW89_PS_WAIT_COND series for wait condition */ 4586 struct rtw89_wait_info ps_wait; 4587 }; 4588 4589 enum rtw89_fwdl_check_type { 4590 RTW89_FWDL_CHECK_FREERTOS_DONE, 4591 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4592 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4593 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4594 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4595 }; 4596 4597 enum rtw89_fw_type { 4598 RTW89_FW_NORMAL = 1, 4599 RTW89_FW_WOWLAN = 3, 4600 RTW89_FW_NORMAL_CE = 5, 4601 RTW89_FW_BBMCU0 = 64, 4602 RTW89_FW_BBMCU1 = 65, 4603 RTW89_FW_LOGFMT = 255, 4604 }; 4605 4606 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \ 4607 RTW89_FW_FEATURE_##_grp##_MIN, \ 4608 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \ 4609 _features \ 4610 __RTW89_FW_FEATURE_##_grp##_E, \ 4611 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1 4612 4613 enum rtw89_fw_feature { 4614 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4615 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4616 RTW89_FW_FEATURE_TX_WAKE, 4617 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER, 4618 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0, 4619 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1, 4620 ), 4621 RTW89_FW_FEATURE_NO_PACKET_DROP, 4622 RTW89_FW_FEATURE_NO_DEEP_PS, 4623 RTW89_FW_FEATURE_NO_LPS_PG, 4624 RTW89_FW_FEATURE_BEACON_FILTER, 4625 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4626 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4627 RTW89_FW_FEATURE_WOW_REASON_V1, 4628 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4629 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4630 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4631 RTW89_FW_FEATURE_RFK_IQK_V0, 4632 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4633 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4634 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4635 RTW89_FW_FEATURE_LPS_CH_INFO, 4636 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4637 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 4638 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1, 4639 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP, 4640 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0, 4641 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG, 4642 RTW89_FW_FEATURE_BEACON_TRACKING, 4643 }; 4644 4645 struct rtw89_fw_suit { 4646 enum rtw89_fw_type type; 4647 const u8 *data; 4648 u32 size; 4649 u8 major_ver; 4650 u8 minor_ver; 4651 u8 sub_ver; 4652 u8 sub_idex; 4653 u16 build_year; 4654 u16 build_mon; 4655 u16 build_date; 4656 u16 build_hour; 4657 u16 build_min; 4658 u8 cmd_ver; 4659 u8 hdr_ver; 4660 u32 commitid; 4661 }; 4662 4663 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4664 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4665 #define RTW89_FW_SUIT_VER_CODE(s) \ 4666 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4667 4668 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4669 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4670 (mfw_hdr)->ver.minor, \ 4671 (mfw_hdr)->ver.sub, \ 4672 (mfw_hdr)->ver.idx) 4673 4674 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4675 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4676 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4677 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4678 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4679 4680 struct rtw89_fw_req_info { 4681 const struct firmware *firmware; 4682 struct completion completion; 4683 }; 4684 4685 struct rtw89_fw_log { 4686 struct rtw89_fw_suit suit; 4687 bool enable; 4688 u32 last_fmt_id; 4689 u32 fmt_count; 4690 const __le32 *fmt_ids; 4691 const char *(*fmts)[]; 4692 }; 4693 4694 struct rtw89_fw_elm_info { 4695 struct rtw89_phy_table *bb_tbl; 4696 struct rtw89_phy_table *bb_gain; 4697 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4698 struct rtw89_phy_table *rf_nctl; 4699 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4700 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4701 const struct rtw89_regd_data *regd; 4702 const struct rtw89_fw_element_hdr *afe; 4703 }; 4704 4705 enum rtw89_fw_mss_dev_type { 4706 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4707 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4708 }; 4709 4710 struct rtw89_fw_secure { 4711 bool secure_boot: 1; 4712 bool can_mss_v1: 1; 4713 bool can_mss_v0: 1; 4714 u32 sb_sel_mgn; 4715 u8 mss_dev_type; 4716 u8 mss_cust_idx; 4717 u8 mss_key_num; 4718 u8 mss_idx; /* v0 */ 4719 }; 4720 4721 struct rtw89_fw_info { 4722 struct rtw89_fw_req_info req; 4723 int fw_format; 4724 u8 h2c_seq; 4725 u8 rec_seq; 4726 u8 h2c_counter; 4727 u8 c2h_counter; 4728 struct rtw89_fw_suit normal; 4729 struct rtw89_fw_suit wowlan; 4730 struct rtw89_fw_suit bbmcu0; 4731 struct rtw89_fw_suit bbmcu1; 4732 struct rtw89_fw_log log; 4733 u32 feature_map; 4734 struct rtw89_fw_elm_info elm_info; 4735 struct rtw89_fw_secure sec; 4736 }; 4737 4738 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4739 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4740 4741 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \ 4742 (!!((_fw)->feature_map & GENMASK(RTW89_FW_FEATURE_ ## _grp ## _MAX, \ 4743 RTW89_FW_FEATURE_ ## _grp ## _MIN))) 4744 4745 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4746 ((_fw)->feature_map |= BIT(_fw_feature)) 4747 4748 struct rtw89_cam_info { 4749 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4750 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4751 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4752 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4753 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4754 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4755 }; 4756 4757 enum rtw89_sar_sources { 4758 RTW89_SAR_SOURCE_NONE, 4759 RTW89_SAR_SOURCE_COMMON, 4760 RTW89_SAR_SOURCE_ACPI, 4761 4762 RTW89_SAR_SOURCE_NR, 4763 }; 4764 4765 enum rtw89_sar_subband { 4766 RTW89_SAR_2GHZ_SUBBAND, 4767 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4768 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4769 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4770 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4771 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4772 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4773 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4774 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4775 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4776 4777 RTW89_SAR_SUBBAND_NR, 4778 }; 4779 4780 struct rtw89_sar_cfg_common { 4781 bool set[RTW89_SAR_SUBBAND_NR]; 4782 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4783 }; 4784 4785 enum rtw89_acpi_sar_subband { 4786 RTW89_ACPI_SAR_2GHZ_SUBBAND, 4787 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */ 4788 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */ 4789 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4790 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4791 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4792 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4793 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4794 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4795 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4796 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4797 4798 NUM_OF_RTW89_ACPI_SAR_SUBBAND, 4799 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1, 4800 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1, 4801 }; 4802 4803 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */ 4804 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX 4805 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN 4806 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6 4807 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1) 4808 4809 struct rtw89_sar_entry_from_acpi { 4810 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4811 }; 4812 4813 struct rtw89_sar_table_from_acpi { 4814 /* If this table is active, must fill all fields according to either 4815 * configuration in BIOS or some default values for SAR to work well. 4816 */ 4817 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM]; 4818 }; 4819 4820 struct rtw89_sar_indicator_from_acpi { 4821 bool enable_sync; 4822 unsigned int fields; 4823 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath); 4824 4825 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path. 4826 * Not design with pointers since addresses will be invalid after 4827 * sync content with local container instance. 4828 */ 4829 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4830 }; 4831 4832 struct rtw89_sar_cfg_acpi { 4833 u8 downgrade_2tx; 4834 unsigned int valid_num; 4835 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL]; 4836 struct rtw89_sar_indicator_from_acpi indicator; 4837 }; 4838 4839 struct rtw89_sar_info { 4840 /* used to decide how to access SAR cfg union */ 4841 enum rtw89_sar_sources src; 4842 4843 /* reserved for different knids of SAR cfg struct. 4844 * supposed that a single cfg struct cannot handle various SAR sources. 4845 */ 4846 union { 4847 struct rtw89_sar_cfg_common cfg_common; 4848 struct rtw89_sar_cfg_acpi cfg_acpi; 4849 }; 4850 }; 4851 4852 enum rtw89_ant_gain_subband { 4853 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4854 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4855 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4856 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4857 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4858 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4859 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4860 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4861 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4862 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4863 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4864 4865 RTW89_ANT_GAIN_SUBBAND_NR, 4866 }; 4867 4868 enum rtw89_ant_gain_domain_type { 4869 RTW89_ANT_GAIN_ETSI = 0, 4870 4871 RTW89_ANT_GAIN_DOMAIN_NUM, 4872 }; 4873 4874 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4875 struct rtw89_ant_gain_info { 4876 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4877 u32 regd_enabled; 4878 bool block_country; 4879 }; 4880 4881 struct rtw89_6ghz_span { 4882 enum rtw89_sar_subband sar_subband_low; 4883 enum rtw89_sar_subband sar_subband_high; 4884 enum rtw89_acpi_sar_subband acpi_sar_subband_low; 4885 enum rtw89_acpi_sar_subband acpi_sar_subband_high; 4886 enum rtw89_ant_gain_subband ant_gain_subband_low; 4887 enum rtw89_ant_gain_subband ant_gain_subband_high; 4888 }; 4889 4890 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4891 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high) 4892 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4893 4894 enum rtw89_tas_state { 4895 RTW89_TAS_STATE_DPR_OFF, 4896 RTW89_TAS_STATE_DPR_ON, 4897 RTW89_TAS_STATE_STATIC_SAR, 4898 }; 4899 4900 #define RTW89_TAS_TX_RATIO_WINDOW 6 4901 #define RTW89_TAS_TXPWR_WINDOW 180 4902 struct rtw89_tas_info { 4903 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 4904 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 4905 u8 enabled_countries; 4906 u8 txpwr_head_idx; 4907 u8 txpwr_tail_idx; 4908 u8 tx_ratio_idx; 4909 u16 total_tx_ratio; 4910 u64 total_txpwr; 4911 u64 instant_txpwr; 4912 u32 window_size; 4913 s8 dpr_on_threshold; 4914 s8 dpr_off_threshold; 4915 enum rtw89_tas_state backup_state; 4916 enum rtw89_tas_state state; 4917 bool keep_history; 4918 bool block_regd; 4919 bool enable; 4920 bool pause; 4921 }; 4922 4923 struct rtw89_chanctx_cfg { 4924 enum rtw89_chanctx_idx idx; 4925 int ref_count; 4926 }; 4927 4928 enum rtw89_chanctx_changes { 4929 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4930 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4931 RTW89_CHANCTX_P2P_PS_CHANGE, 4932 RTW89_CHANCTX_BT_SLOT_CHANGE, 4933 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4934 4935 NUM_OF_RTW89_CHANCTX_CHANGES, 4936 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4937 }; 4938 4939 enum rtw89_entity_mode { 4940 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4941 RTW89_ENTITY_MODE_MCC_PREPARE, 4942 RTW89_ENTITY_MODE_MCC, 4943 4944 NUM_OF_RTW89_ENTITY_MODE, 4945 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4946 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4947 }; 4948 4949 #define RTW89_MAX_INTERFACE_NUM 2 4950 4951 /* only valid when running with chanctx_ops */ 4952 struct rtw89_entity_mgnt { 4953 struct list_head active_list; 4954 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4955 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4956 [__RTW89_MLD_MAX_LINK_NUM]; 4957 }; 4958 4959 struct rtw89_chanctx { 4960 struct cfg80211_chan_def chandef; 4961 struct rtw89_chan chan; 4962 struct rtw89_chan_rcd rcd; 4963 4964 /* only assigned when running with chanctx_ops */ 4965 struct rtw89_chanctx_cfg *cfg; 4966 }; 4967 4968 struct rtw89_edcca_bak { 4969 u8 a; 4970 u8 p; 4971 u8 ppdu; 4972 u8 th_old; 4973 }; 4974 4975 enum rtw89_dm_type { 4976 RTW89_DM_DYNAMIC_EDCCA, 4977 RTW89_DM_THERMAL_PROTECT, 4978 RTW89_DM_TAS, 4979 RTW89_DM_MLO, 4980 }; 4981 4982 #define RTW89_THERMAL_PROT_LV_MAX 5 4983 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 4984 4985 struct rtw89_hal { 4986 u32 rx_fltr; 4987 u8 cv; 4988 u8 acv; 4989 u32 antenna_tx; 4990 u32 antenna_rx; 4991 u8 tx_nss; 4992 u8 rx_nss; 4993 bool tx_path_diversity; 4994 bool ant_diversity; 4995 bool ant_diversity_fixed; 4996 bool support_cckpd; 4997 bool support_igi; 4998 bool no_mcs_12_13; 4999 5000 atomic_t roc_chanctx_idx; 5001 u8 roc_link_index; 5002 5003 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 5004 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 5005 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 5006 struct cfg80211_chan_def roc_chandef; 5007 5008 bool entity_active[RTW89_PHY_NUM]; 5009 bool entity_pause; 5010 enum rtw89_entity_mode entity_mode; 5011 struct rtw89_entity_mgnt entity_mgnt; 5012 5013 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 5014 5015 u8 thermal_prot_th; 5016 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 5017 }; 5018 5019 #define RTW89_MAX_MAC_ID_NUM 128 5020 #define RTW89_MAX_PKT_OFLD_NUM 255 5021 5022 enum rtw89_flags { 5023 RTW89_FLAG_POWERON, 5024 RTW89_FLAG_DMAC_FUNC, 5025 RTW89_FLAG_CMAC0_FUNC, 5026 RTW89_FLAG_CMAC1_FUNC, 5027 RTW89_FLAG_FW_RDY, 5028 RTW89_FLAG_RUNNING, 5029 RTW89_FLAG_PROBE_DONE, 5030 RTW89_FLAG_BFEE_MON, 5031 RTW89_FLAG_BFEE_EN, 5032 RTW89_FLAG_BFEE_TIMER_KEEP, 5033 RTW89_FLAG_NAPI_RUNNING, 5034 RTW89_FLAG_LEISURE_PS, 5035 RTW89_FLAG_LOW_POWER_MODE, 5036 RTW89_FLAG_INACTIVE_PS, 5037 RTW89_FLAG_CRASH_SIMULATING, 5038 RTW89_FLAG_SER_HANDLING, 5039 RTW89_FLAG_WOWLAN, 5040 RTW89_FLAG_FORBIDDEN_TRACK_WORK, 5041 RTW89_FLAG_CHANGING_INTERFACE, 5042 RTW89_FLAG_HW_RFKILL_STATE, 5043 RTW89_FLAG_UNPLUGGED, 5044 5045 NUM_OF_RTW89_FLAGS, 5046 }; 5047 5048 enum rtw89_quirks { 5049 RTW89_QUIRK_PCI_BER, 5050 RTW89_QUIRK_THERMAL_PROT_120C, 5051 RTW89_QUIRK_THERMAL_PROT_110C, 5052 5053 NUM_OF_RTW89_QUIRKS, 5054 }; 5055 5056 enum rtw89_custid { 5057 RTW89_CUSTID_NONE, 5058 RTW89_CUSTID_ACER, 5059 RTW89_CUSTID_AMD, 5060 RTW89_CUSTID_ASUS, 5061 RTW89_CUSTID_DELL, 5062 RTW89_CUSTID_HP, 5063 RTW89_CUSTID_LENOVO, 5064 }; 5065 5066 enum rtw89_pkt_drop_sel { 5067 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5068 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5069 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5070 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5071 RTW89_PKT_DROP_SEL_MACID_ALL, 5072 RTW89_PKT_DROP_SEL_MG0_ONCE, 5073 RTW89_PKT_DROP_SEL_HIQ_ONCE, 5074 RTW89_PKT_DROP_SEL_HIQ_PORT, 5075 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 5076 RTW89_PKT_DROP_SEL_BAND, 5077 RTW89_PKT_DROP_SEL_BAND_ONCE, 5078 RTW89_PKT_DROP_SEL_REL_MACID, 5079 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 5080 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 5081 }; 5082 5083 struct rtw89_pkt_drop_params { 5084 enum rtw89_pkt_drop_sel sel; 5085 enum rtw89_mac_idx mac_band; 5086 u8 macid; 5087 u8 port; 5088 u8 mbssid; 5089 bool tf_trs; 5090 u32 macid_band_sel[4]; 5091 }; 5092 5093 struct rtw89_pkt_stat { 5094 u16 beacon_nr; 5095 u8 beacon_rate; 5096 u32 beacon_len; 5097 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 5098 }; 5099 5100 #define RTW89_BCN_TRACK_STAT_NR 32 5101 #define RTW89_BCN_TRACK_SCALE_FACTOR 10 5102 #define RTW89_BCN_TRACK_MAX_BIN_NUM 6 5103 #define RTW89_BCN_TRACK_BIN_WIDTH 5 5104 #define RTW89_BCN_TRACK_TARGET_BCN 80 5105 5106 struct rtw89_beacon_dist { 5107 u16 min; 5108 u16 max; 5109 u16 outlier_count; 5110 u16 lower_bound; 5111 u16 upper_bound; 5112 u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM]; 5113 }; 5114 5115 struct rtw89_beacon_stat { 5116 u8 num; 5117 u8 wp; 5118 u16 tbtt_tu_min; 5119 u16 tbtt_tu_max; 5120 u16 drift[RTW89_BCN_TRACK_STAT_NR]; 5121 u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR]; 5122 u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR]; 5123 struct rtw89_beacon_dist bcn_dist; 5124 }; 5125 5126 DECLARE_EWMA(thermal, 4, 4); 5127 5128 struct rtw89_phy_stat { 5129 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 5130 u8 last_thermal_max; 5131 struct ewma_rssi bcn_rssi; 5132 struct rtw89_pkt_stat cur_pkt_stat; 5133 struct rtw89_pkt_stat last_pkt_stat; 5134 struct rtw89_beacon_stat bcn_stat; 5135 }; 5136 5137 enum rtw89_rfk_report_state { 5138 RTW89_RFK_STATE_START = 0x0, 5139 RTW89_RFK_STATE_OK = 0x1, 5140 RTW89_RFK_STATE_FAIL = 0x2, 5141 RTW89_RFK_STATE_TIMEOUT = 0x3, 5142 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 5143 }; 5144 5145 struct rtw89_rfk_wait_info { 5146 struct completion completion; 5147 ktime_t start_time; 5148 enum rtw89_rfk_report_state state; 5149 u8 version; 5150 }; 5151 5152 #define RTW89_DACK_PATH_NR 2 5153 #define RTW89_DACK_IDX_NR 2 5154 #define RTW89_DACK_MSBK_NR 16 5155 struct rtw89_dack_info { 5156 bool dack_done; 5157 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 5158 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5159 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5160 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5161 u32 dack_cnt; 5162 bool addck_timeout[RTW89_DACK_PATH_NR]; 5163 bool dadck_timeout[RTW89_DACK_PATH_NR]; 5164 bool msbk_timeout[RTW89_DACK_PATH_NR]; 5165 }; 5166 5167 enum rtw89_rfk_chs_nrs { 5168 __RTW89_RFK_CHS_NR_V0 = 2, 5169 __RTW89_RFK_CHS_NR_V1 = 3, 5170 5171 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 5172 }; 5173 5174 struct rtw89_rfk_mcc_info_data { 5175 u8 ch[RTW89_RFK_CHS_NR]; 5176 u8 band[RTW89_RFK_CHS_NR]; 5177 u8 bw[RTW89_RFK_CHS_NR]; 5178 u8 table_idx; 5179 }; 5180 5181 struct rtw89_rfk_mcc_info { 5182 struct rtw89_rfk_mcc_info_data data[2]; 5183 }; 5184 5185 #define RTW89_IQK_CHS_NR 2 5186 #define RTW89_IQK_PATH_NR 4 5187 5188 struct rtw89_lck_info { 5189 u8 thermal[RF_PATH_MAX]; 5190 }; 5191 5192 struct rtw89_rx_dck_info { 5193 u8 thermal[RF_PATH_MAX]; 5194 }; 5195 5196 struct rtw89_iqk_info { 5197 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5198 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5199 bool lok_fail[RTW89_IQK_PATH_NR]; 5200 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5201 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5202 u32 iqk_fail_cnt; 5203 bool is_iqk_init; 5204 u32 iqk_channel[RTW89_IQK_CHS_NR]; 5205 u8 iqk_band[RTW89_IQK_PATH_NR]; 5206 u8 iqk_ch[RTW89_IQK_PATH_NR]; 5207 u8 iqk_bw[RTW89_IQK_PATH_NR]; 5208 u8 iqk_times; 5209 u8 version; 5210 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 5211 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 5212 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 5213 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 5214 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 5215 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 5216 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 5217 bool is_nbiqk; 5218 bool iqk_fft_en; 5219 bool iqk_xym_en; 5220 bool iqk_sram_en; 5221 bool iqk_cfir_en; 5222 u32 syn1to2; 5223 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5224 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 5225 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5226 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5227 }; 5228 5229 #define RTW89_DPK_RF_PATH 2 5230 #define RTW89_DPK_AVG_THERMAL_NUM 8 5231 #define RTW89_DPK_BKUP_NUM 2 5232 struct rtw89_dpk_bkup_para { 5233 enum rtw89_band band; 5234 enum rtw89_bandwidth bw; 5235 u8 ch; 5236 u8 path_ok; 5237 u8 mdpd_en; 5238 u8 txagc_dpk; 5239 u8 ther_dpk; 5240 u8 gs; 5241 u16 pwsf; 5242 }; 5243 5244 struct rtw89_dpk_info { 5245 bool is_dpk_enable; 5246 bool is_dpk_reload_en; 5247 u8 dpk_gs[RTW89_PHY_NUM]; 5248 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5249 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5250 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5251 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5252 u8 cur_idx[RTW89_DPK_RF_PATH]; 5253 u8 cur_k_set; 5254 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5255 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 5256 u32 dpk_order[RTW89_DPK_RF_PATH]; 5257 }; 5258 5259 struct rtw89_fem_info { 5260 bool elna_2g; 5261 bool elna_5g; 5262 bool epa_2g; 5263 bool epa_5g; 5264 bool epa_6g; 5265 }; 5266 5267 struct rtw89_phy_ch_info { 5268 u8 rssi_min; 5269 u16 rssi_min_macid; 5270 u8 pre_rssi_min; 5271 u8 rssi_max; 5272 u16 rssi_max_macid; 5273 u8 rxsc_160; 5274 u8 rxsc_80; 5275 u8 rxsc_40; 5276 u8 rxsc_20; 5277 u8 rxsc_l; 5278 u8 is_noisy; 5279 }; 5280 5281 struct rtw89_agc_gaincode_set { 5282 u8 lna_idx; 5283 u8 tia_idx; 5284 u8 rxb_idx; 5285 }; 5286 5287 #define IGI_RSSI_TH_NUM 5 5288 #define FA_TH_NUM 4 5289 #define TIA_LNA_OP1DB_NUM 8 5290 #define LNA_GAIN_NUM 7 5291 #define TIA_GAIN_NUM 2 5292 struct rtw89_dig_info { 5293 struct rtw89_agc_gaincode_set cur_gaincode; 5294 bool force_gaincode_idx_en; 5295 struct rtw89_agc_gaincode_set force_gaincode; 5296 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5297 u16 fa_th[FA_TH_NUM]; 5298 u8 igi_rssi; 5299 u8 igi_fa_rssi; 5300 u8 fa_rssi_ofst; 5301 u8 dyn_igi_max; 5302 u8 dyn_igi_min; 5303 bool dyn_pd_th_en; 5304 u8 dyn_pd_th_max; 5305 u8 pd_low_th_ofst; 5306 u8 ib_pbk; 5307 s8 ib_pkpwr; 5308 s8 lna_gain_a[LNA_GAIN_NUM]; 5309 s8 lna_gain_g[LNA_GAIN_NUM]; 5310 s8 *lna_gain; 5311 s8 tia_gain_a[TIA_GAIN_NUM]; 5312 s8 tia_gain_g[TIA_GAIN_NUM]; 5313 s8 *tia_gain; 5314 u32 bak_dig; 5315 bool is_linked_pre; 5316 bool bypass_dig; 5317 bool pause_dig; 5318 }; 5319 5320 enum rtw89_multi_cfo_mode { 5321 RTW89_PKT_BASED_AVG_MODE = 0, 5322 RTW89_ENTRY_BASED_AVG_MODE = 1, 5323 RTW89_TP_BASED_AVG_MODE = 2, 5324 }; 5325 5326 enum rtw89_phy_cfo_status { 5327 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5328 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5329 RTW89_PHY_DCFO_STATE_HOLD = 2, 5330 RTW89_PHY_DCFO_STATE_MAX 5331 }; 5332 5333 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5334 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5335 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5336 }; 5337 5338 struct rtw89_cfo_tracking_info { 5339 u16 cfo_timer_ms; 5340 bool cfo_trig_by_timer_en; 5341 enum rtw89_phy_cfo_status phy_cfo_status; 5342 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5343 u8 phy_cfo_trk_cnt; 5344 bool is_adjust; 5345 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5346 bool apply_compensation; 5347 u8 crystal_cap; 5348 u8 crystal_cap_default; 5349 u8 def_x_cap; 5350 s8 x_cap_ofst; 5351 u32 sta_cfo_tolerance; 5352 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5353 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5354 s32 cfo_avg_pre; 5355 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5356 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5357 s32 dcfo_avg; 5358 s32 dcfo_avg_pre; 5359 u32 packet_count; 5360 u32 packet_count_pre; 5361 s32 residual_cfo_acc; 5362 u8 phy_cfotrk_state; 5363 u8 phy_cfotrk_cnt; 5364 bool divergence_lock_en; 5365 u8 x_cap_lb; 5366 u8 x_cap_ub; 5367 u8 lock_cnt; 5368 }; 5369 5370 enum rtw89_tssi_mode { 5371 RTW89_TSSI_NORMAL = 0, 5372 RTW89_TSSI_SCAN = 1, 5373 }; 5374 5375 enum rtw89_tssi_alimk_band { 5376 TSSI_ALIMK_2G = 0, 5377 TSSI_ALIMK_5GL, 5378 TSSI_ALIMK_5GM, 5379 TSSI_ALIMK_5GH, 5380 TSSI_ALIMK_MAX 5381 }; 5382 5383 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5384 #define TSSI_TRIM_CH_GROUP_NUM 8 5385 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5386 5387 #define TSSI_CCK_CH_GROUP_NUM 6 5388 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5389 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5390 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5391 #define TSSI_MCS_CH_GROUP_NUM \ 5392 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5393 #define TSSI_MAX_CH_NUM 67 5394 #define TSSI_ALIMK_VALUE_NUM 8 5395 5396 struct rtw89_tssi_info { 5397 u8 thermal[RF_PATH_MAX]; 5398 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5399 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5400 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5401 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5402 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5403 s8 extra_ofst[RF_PATH_MAX]; 5404 bool tssi_tracking_check[RF_PATH_MAX]; 5405 u8 default_txagc_offset[RF_PATH_MAX]; 5406 u32 base_thermal[RF_PATH_MAX]; 5407 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5408 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5409 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5410 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5411 u64 tssi_alimk_time; 5412 }; 5413 5414 struct rtw89_power_trim_info { 5415 bool pg_thermal_trim; 5416 bool pg_pa_bias_trim; 5417 u8 thermal_trim[RF_PATH_MAX]; 5418 u8 pa_bias_trim[RF_PATH_MAX]; 5419 u8 pad_bias_trim[RF_PATH_MAX]; 5420 }; 5421 5422 enum rtw89_regd_func { 5423 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 5424 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 5425 5426 NUM_OF_RTW89_REGD_FUNC, 5427 }; 5428 5429 struct rtw89_regd { 5430 char alpha2[3]; 5431 u8 txpwr_regd[RTW89_BAND_NUM]; 5432 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 5433 }; 5434 5435 struct rtw89_regd_data { 5436 unsigned int nr; 5437 struct rtw89_regd map[] __counted_by(nr); 5438 }; 5439 5440 struct rtw89_regd_ctrl { 5441 unsigned int nr; 5442 const struct rtw89_regd *map; 5443 }; 5444 5445 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5446 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5447 #define RTW89_5GHZ_UNII4_START_INDEX 25 5448 5449 struct rtw89_regulatory_info { 5450 struct rtw89_regd_ctrl ctrl; 5451 const struct rtw89_regd *regd; 5452 enum rtw89_reg_6ghz_power reg_6ghz_power; 5453 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5454 bool txpwr_uk_follow_etsi; 5455 5456 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5457 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5458 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5459 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM); 5460 }; 5461 5462 enum rtw89_ifs_clm_application { 5463 RTW89_IFS_CLM_INIT = 0, 5464 RTW89_IFS_CLM_BACKGROUND = 1, 5465 RTW89_IFS_CLM_ACS = 2, 5466 RTW89_IFS_CLM_DIG = 3, 5467 RTW89_IFS_CLM_TDMA_DIG = 4, 5468 RTW89_IFS_CLM_DBG = 5, 5469 RTW89_IFS_CLM_DBG_MANUAL = 6 5470 }; 5471 5472 enum rtw89_env_racing_lv { 5473 RTW89_RAC_RELEASE = 0, 5474 RTW89_RAC_LV_1 = 1, 5475 RTW89_RAC_LV_2 = 2, 5476 RTW89_RAC_LV_3 = 3, 5477 RTW89_RAC_LV_4 = 4, 5478 RTW89_RAC_MAX_NUM = 5 5479 }; 5480 5481 struct rtw89_ccx_para_info { 5482 enum rtw89_env_racing_lv rac_lv; 5483 u16 mntr_time; 5484 bool nhm_incld_cca; 5485 u8 nhm_manual_th_ofst; 5486 u8 nhm_manual_th0; 5487 enum rtw89_ifs_clm_application ifs_clm_app; 5488 u32 ifs_clm_manual_th_times; 5489 u32 ifs_clm_manual_th0; 5490 u8 fahm_manual_th_ofst; 5491 u8 fahm_manual_th0; 5492 u8 fahm_numer_opt; 5493 u8 fahm_denom_opt; 5494 }; 5495 5496 enum rtw89_ccx_edcca_opt_sc_idx { 5497 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5498 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5499 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5500 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5501 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5502 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5503 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5504 RTW89_CCX_EDCCA_SEG1_S3 = 7 5505 }; 5506 5507 enum rtw89_ccx_edcca_opt_bw_idx { 5508 RTW89_CCX_EDCCA_BW20_0 = 0, 5509 RTW89_CCX_EDCCA_BW20_1 = 1, 5510 RTW89_CCX_EDCCA_BW20_2 = 2, 5511 RTW89_CCX_EDCCA_BW20_3 = 3, 5512 RTW89_CCX_EDCCA_BW20_4 = 4, 5513 RTW89_CCX_EDCCA_BW20_5 = 5, 5514 RTW89_CCX_EDCCA_BW20_6 = 6, 5515 RTW89_CCX_EDCCA_BW20_7 = 7 5516 }; 5517 5518 struct rtw89_nhm_report { 5519 struct list_head list; 5520 struct ieee80211_channel *channel; 5521 u8 noise; 5522 }; 5523 5524 #define RTW89_FAHM_TH_NUM 11 5525 #define RTW89_FAHM_RPT_NUM 12 5526 #define RTW89_IFS_CLM_NUM 4 5527 struct rtw89_env_monitor_info { 5528 u8 ccx_watchdog_result; 5529 bool ccx_ongoing; 5530 u8 ccx_rac_lv; 5531 bool ccx_manual_ctrl; 5532 u16 ifs_clm_mntr_time; 5533 enum rtw89_ifs_clm_application ifs_clm_app; 5534 u16 ccx_period; 5535 u8 ccx_unit_idx; 5536 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5537 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5538 u16 ifs_clm_tx; 5539 u16 ifs_clm_edcca_excl_cca; 5540 u16 ifs_clm_ofdmfa; 5541 u16 ifs_clm_ofdmcca_excl_fa; 5542 u16 ifs_clm_cckfa; 5543 u16 ifs_clm_cckcca_excl_fa; 5544 u16 ifs_clm_total_ifs; 5545 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5546 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5547 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5548 u8 ifs_clm_tx_ratio; 5549 u8 ifs_clm_edcca_excl_cca_ratio; 5550 u8 ifs_clm_cck_fa_ratio; 5551 u8 ifs_clm_ofdm_fa_ratio; 5552 u8 ifs_clm_cck_cca_excl_fa_ratio; 5553 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5554 u16 ifs_clm_cck_fa_permil; 5555 u16 ifs_clm_ofdm_fa_permil; 5556 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5557 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5558 bool nhm_include_cca; 5559 u32 nhm_sum; 5560 u32 nhm_mntr_time; 5561 u16 nhm_result[RTW89_NHM_RPT_NUM]; 5562 u8 nhm_th[RTW89_NHM_RPT_NUM]; 5563 struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM]; 5564 struct list_head nhm_rpt_list; 5565 }; 5566 5567 enum rtw89_ser_rcvy_step { 5568 RTW89_SER_DRV_STOP_TX, 5569 RTW89_SER_DRV_STOP_RX, 5570 RTW89_SER_DRV_STOP_RUN, 5571 RTW89_SER_HAL_STOP_DMA, 5572 RTW89_SER_SUPPRESS_LOG, 5573 RTW89_NUM_OF_SER_FLAGS 5574 }; 5575 5576 struct rtw89_ser { 5577 u8 state; 5578 u8 alarm_event; 5579 bool prehandle_l1; 5580 5581 struct work_struct ser_hdl_work; 5582 struct delayed_work ser_alarm_work; 5583 const struct state_ent *st_tbl; 5584 const struct event_ent *ev_tbl; 5585 struct list_head msg_q; 5586 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5587 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5588 }; 5589 5590 enum rtw89_mac_ax_ps_mode { 5591 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5592 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5593 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5594 RTW89_MAC_AX_PS_MODE_MAX = 3, 5595 }; 5596 5597 enum rtw89_last_rpwm_mode { 5598 RTW89_LAST_RPWM_PS = 0x0, 5599 RTW89_LAST_RPWM_ACTIVE = 0x6, 5600 }; 5601 5602 struct rtw89_lps_parm { 5603 u8 macid; 5604 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5605 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5606 }; 5607 5608 struct rtw89_ppdu_sts_info { 5609 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 5610 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 5611 }; 5612 5613 struct rtw89_early_h2c { 5614 struct list_head list; 5615 u8 *h2c; 5616 u16 h2c_len; 5617 }; 5618 5619 struct rtw89_hw_scan_extra_op { 5620 bool set; 5621 u8 macid; 5622 u8 port; 5623 struct rtw89_chan chan; 5624 struct rtw89_vif_link *rtwvif_link; 5625 }; 5626 5627 struct rtw89_hw_scan_info { 5628 struct rtw89_vif_link *scanning_vif; 5629 struct list_head pkt_list[NUM_NL80211_BANDS]; 5630 struct list_head chan_list; 5631 struct rtw89_chan op_chan; 5632 struct rtw89_hw_scan_extra_op extra_op; 5633 bool connected; 5634 bool abort; 5635 u16 delay; /* in unit of ms */ 5636 u8 seq: 2; 5637 }; 5638 5639 enum rtw89_phy_bb_gain_band { 5640 RTW89_BB_GAIN_BAND_2G = 0, 5641 RTW89_BB_GAIN_BAND_5G_L = 1, 5642 RTW89_BB_GAIN_BAND_5G_M = 2, 5643 RTW89_BB_GAIN_BAND_5G_H = 3, 5644 RTW89_BB_GAIN_BAND_6G_L = 4, 5645 RTW89_BB_GAIN_BAND_6G_M = 5, 5646 RTW89_BB_GAIN_BAND_6G_H = 6, 5647 RTW89_BB_GAIN_BAND_6G_UH = 7, 5648 5649 RTW89_BB_GAIN_BAND_NR, 5650 }; 5651 5652 enum rtw89_phy_gain_band_be { 5653 RTW89_BB_GAIN_BAND_2G_BE = 0, 5654 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5655 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5656 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5657 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5658 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5659 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5660 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5661 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5662 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5663 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5664 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5665 5666 RTW89_BB_GAIN_BAND_NR_BE, 5667 }; 5668 5669 enum rtw89_phy_bb_bw_be { 5670 RTW89_BB_BW_20_40 = 0, 5671 RTW89_BB_BW_80_160_320 = 1, 5672 5673 RTW89_BB_BW_NR_BE, 5674 }; 5675 5676 enum rtw89_bw20_sc { 5677 RTW89_BW20_SC_20M = 1, 5678 RTW89_BW20_SC_40M = 2, 5679 RTW89_BW20_SC_80M = 4, 5680 RTW89_BW20_SC_160M = 8, 5681 RTW89_BW20_SC_320M = 16, 5682 }; 5683 5684 enum rtw89_cmac_table_bw { 5685 RTW89_CMAC_BW_20M = 0, 5686 RTW89_CMAC_BW_40M = 1, 5687 RTW89_CMAC_BW_80M = 2, 5688 RTW89_CMAC_BW_160M = 3, 5689 RTW89_CMAC_BW_320M = 4, 5690 5691 RTW89_CMAC_BW_NR, 5692 }; 5693 5694 enum rtw89_phy_bb_rxsc_num { 5695 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5696 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5697 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5698 }; 5699 5700 struct rtw89_phy_bb_gain_info { 5701 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5702 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5703 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5704 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5705 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5706 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5707 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5708 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5709 [RTW89_BB_RXSC_NUM_40]; 5710 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5711 [RTW89_BB_RXSC_NUM_80]; 5712 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5713 [RTW89_BB_RXSC_NUM_160]; 5714 }; 5715 5716 struct rtw89_phy_bb_gain_info_be { 5717 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5718 [LNA_GAIN_NUM]; 5719 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5720 [TIA_GAIN_NUM]; 5721 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5722 [RF_PATH_MAX][LNA_GAIN_NUM]; 5723 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5724 [RF_PATH_MAX][LNA_GAIN_NUM]; 5725 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5726 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5727 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5728 [RTW89_BW20_SC_20M]; 5729 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5730 [RTW89_BW20_SC_40M]; 5731 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5732 [RTW89_BW20_SC_80M]; 5733 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5734 [RTW89_BW20_SC_160M]; 5735 }; 5736 5737 struct rtw89_phy_efuse_gain { 5738 bool offset_valid; 5739 bool comp_valid; 5740 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5741 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5742 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5743 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5744 }; 5745 5746 #define RTW89_MAX_PATTERN_NUM 18 5747 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5748 #define RTW89_MAX_PATTERN_SIZE 128 5749 5750 struct rtw89_wow_cam_info { 5751 bool r_w; 5752 u8 idx; 5753 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5754 u16 crc; 5755 bool negative_pattern_match; 5756 bool skip_mac_hdr; 5757 bool uc; 5758 bool mc; 5759 bool bc; 5760 bool valid; 5761 }; 5762 5763 struct rtw89_wow_key_info { 5764 u8 ptk_tx_iv[8]; 5765 u8 valid_check; 5766 u8 symbol_check_en; 5767 u8 gtk_keyidx; 5768 u8 rsvd[5]; 5769 u8 ptk_rx_iv[8]; 5770 u8 gtk_rx_iv[4][8]; 5771 } __packed; 5772 5773 struct rtw89_wow_gtk_info { 5774 u8 kck[32]; 5775 u8 kek[32]; 5776 u8 tk1[16]; 5777 u8 rxmickey[8]; 5778 u8 txmickey[8]; 5779 __le32 igtk_keyid; 5780 __le64 ipn; 5781 u8 igtk[2][32]; 5782 u8 psk[32]; 5783 } __packed; 5784 5785 struct rtw89_wow_aoac_report { 5786 u8 rpt_ver; 5787 u8 sec_type; 5788 u8 key_idx; 5789 u8 pattern_idx; 5790 u8 rekey_ok; 5791 u8 ptk_tx_iv[8]; 5792 u8 eapol_key_replay_count[8]; 5793 u8 gtk[32]; 5794 u8 ptk_rx_iv[8]; 5795 u8 gtk_rx_iv[4][8]; 5796 u64 igtk_key_id; 5797 u64 igtk_ipn; 5798 u8 igtk[32]; 5799 u8 csa_pri_ch; 5800 u8 csa_bw; 5801 u8 csa_ch_offset; 5802 u8 csa_chsw_failed; 5803 u8 csa_ch_band; 5804 }; 5805 5806 struct rtw89_wow_param { 5807 struct rtw89_vif_link *rtwvif_link; 5808 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5809 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5810 struct rtw89_wow_key_info key_info; 5811 struct rtw89_wow_gtk_info gtk_info; 5812 struct rtw89_wow_aoac_report aoac_rpt; 5813 u8 pattern_cnt; 5814 u8 ptk_alg; 5815 u8 gtk_alg; 5816 u8 ptk_keyidx; 5817 u8 akm; 5818 5819 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5820 struct rtw89_wait_info wait; 5821 5822 bool pno_inited; 5823 struct list_head pno_pkt_list; 5824 struct cfg80211_sched_scan_request *nd_config; 5825 }; 5826 5827 struct rtw89_mcc_limit { 5828 bool enable; 5829 u16 max_tob; /* TU; max time offset behind */ 5830 u16 max_toa; /* TU; max time offset ahead */ 5831 u16 max_dur; /* TU */ 5832 }; 5833 5834 struct rtw89_mcc_policy { 5835 u8 c2h_rpt; 5836 u8 tx_null_early; 5837 u8 dis_tx_null; 5838 u8 in_curr_ch; 5839 u8 dis_sw_retry; 5840 u8 sw_retry_count; 5841 }; 5842 5843 struct rtw89_mcc_role { 5844 struct rtw89_vif_link *rtwvif_link; 5845 struct rtw89_mcc_policy policy; 5846 struct rtw89_mcc_limit limit; 5847 5848 const struct rtw89_mcc_courtesy_cfg *crtz; 5849 5850 /* only valid when running with FW MRC mechanism */ 5851 u8 slot_idx; 5852 5853 /* byte-array in LE order for FW */ 5854 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5855 u8 probe_count; 5856 5857 u16 duration; /* TU */ 5858 u16 beacon_interval; /* TU */ 5859 bool is_2ghz; 5860 bool is_go; 5861 bool is_gc; 5862 bool ignore_bcn; 5863 }; 5864 5865 struct rtw89_mcc_bt_role { 5866 u16 duration; /* TU */ 5867 }; 5868 5869 struct rtw89_mcc_courtesy_cfg { 5870 u8 slot_num; 5871 u8 macid_tgt; 5872 }; 5873 5874 struct rtw89_mcc_courtesy { 5875 struct rtw89_mcc_courtesy_cfg ref; 5876 struct rtw89_mcc_courtesy_cfg aux; 5877 }; 5878 5879 enum rtw89_mcc_plan { 5880 RTW89_MCC_PLAN_TAIL_BT, 5881 RTW89_MCC_PLAN_MID_BT, 5882 RTW89_MCC_PLAN_NO_BT, 5883 5884 NUM_OF_RTW89_MCC_PLAN, 5885 }; 5886 5887 struct rtw89_mcc_pattern { 5888 s16 tob_ref; /* TU; time offset behind of reference role */ 5889 s16 toa_ref; /* TU; time offset ahead of reference role */ 5890 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5891 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5892 5893 enum rtw89_mcc_plan plan; 5894 struct rtw89_mcc_courtesy courtesy; 5895 }; 5896 5897 struct rtw89_mcc_sync { 5898 bool enable; 5899 u16 offset; /* TU */ 5900 u8 macid_src; 5901 u8 band_src; 5902 u8 port_src; 5903 u8 macid_tgt; 5904 u8 band_tgt; 5905 u8 port_tgt; 5906 }; 5907 5908 struct rtw89_mcc_config { 5909 struct rtw89_mcc_pattern pattern; 5910 struct rtw89_mcc_sync sync; 5911 u64 start_tsf; 5912 u64 start_tsf_in_aux_domain; 5913 u64 prepare_delay; 5914 u16 mcc_interval; /* TU */ 5915 u16 beacon_offset; /* TU */ 5916 }; 5917 5918 enum rtw89_mcc_mode { 5919 RTW89_MCC_MODE_GO_STA, 5920 RTW89_MCC_MODE_GC_STA, 5921 }; 5922 5923 struct rtw89_mcc_info { 5924 struct rtw89_wait_info wait; 5925 5926 u8 group; 5927 enum rtw89_mcc_mode mode; 5928 struct rtw89_mcc_role role_ref; /* reference role */ 5929 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5930 struct rtw89_mcc_bt_role bt_role; 5931 struct rtw89_mcc_config config; 5932 }; 5933 5934 enum rtw89_mlo_mode { 5935 RTW89_MLO_MODE_MLSR = 0, 5936 5937 NUM_OF_RTW89_MLO_MODE, 5938 }; 5939 5940 struct rtw89_mlo_info { 5941 struct rtw89_wait_info wait; 5942 }; 5943 5944 struct rtw89_beacon_track_info { 5945 bool is_data_ready; 5946 u32 tbtt_offset; /* in unit of microsecond */ 5947 u16 bcn_timeout; /* in unit of millisecond */ 5948 5949 /* The following are constant and set at association. */ 5950 u8 dtim; 5951 u16 beacon_int; 5952 u16 low_bcn_th; 5953 u16 med_bcn_th; 5954 u16 high_bcn_th; 5955 u16 target_bcn_th; 5956 u16 outlier_low_bcn_th; 5957 u16 outlier_high_bcn_th; 5958 u32 close_bcn_intvl_th; 5959 u32 tbtt_diff_th; 5960 }; 5961 5962 struct rtw89_dev { 5963 struct ieee80211_hw *hw; 5964 struct device *dev; 5965 const struct ieee80211_ops *ops; 5966 5967 bool dbcc_en; 5968 bool support_mlo; 5969 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5970 struct rtw89_hw_scan_info scan_info; 5971 const struct rtw89_chip_info *chip; 5972 const struct rtw89_chip_variant *variant; 5973 const struct rtw89_pci_info *pci_info; 5974 const struct rtw89_rfe_parms *rfe_parms; 5975 struct rtw89_hal hal; 5976 struct rtw89_beacon_track_info bcn_track; 5977 struct rtw89_mcc_info mcc; 5978 struct rtw89_mlo_info mlo; 5979 struct rtw89_mac_info mac; 5980 struct rtw89_fw_info fw; 5981 struct rtw89_hci_info hci; 5982 struct rtw89_efuse efuse; 5983 struct rtw89_traffic_stats stats; 5984 struct rtw89_rfe_data *rfe_data; 5985 enum rtw89_custid custid; 5986 5987 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 5988 refcount_t refcount_ap_info; 5989 5990 struct list_head rtwvifs_list; 5991 /* used to protect rf read write */ 5992 struct mutex rf_mutex; 5993 struct workqueue_struct *txq_wq; 5994 struct work_struct txq_work; 5995 struct delayed_work txq_reinvoke_work; 5996 /* used to protect ba_list and forbid_ba_list */ 5997 spinlock_t ba_lock; 5998 /* txqs to setup ba session */ 5999 struct list_head ba_list; 6000 /* txqs to forbid ba session */ 6001 struct list_head forbid_ba_list; 6002 struct work_struct ba_work; 6003 /* used to protect rpwm */ 6004 spinlock_t rpwm_lock; 6005 6006 struct list_head tx_waits; 6007 struct wiphy_delayed_work tx_wait_work; 6008 6009 struct rtw89_cam_info cam_info; 6010 6011 struct sk_buff_head c2h_queue; 6012 struct wiphy_work c2h_work; 6013 struct wiphy_work ips_work; 6014 struct wiphy_work cancel_6ghz_probe_work; 6015 struct work_struct load_firmware_work; 6016 6017 struct list_head early_h2c_list; 6018 6019 struct rtw89_ser ser; 6020 6021 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 6022 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 6023 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 6024 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 6025 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 6026 6027 struct rtw89_phy_stat phystat; 6028 struct rtw89_rfk_wait_info rfk_wait; 6029 struct rtw89_dack_info dack; 6030 struct rtw89_iqk_info iqk; 6031 struct rtw89_dpk_info dpk; 6032 struct rtw89_rfk_mcc_info rfk_mcc; 6033 struct rtw89_lck_info lck; 6034 struct rtw89_rx_dck_info rx_dck; 6035 bool is_tssi_mode[RF_PATH_MAX]; 6036 bool is_bt_iqk_timeout; 6037 6038 struct rtw89_fem_info fem; 6039 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 6040 struct rtw89_tssi_info tssi; 6041 struct rtw89_power_trim_info pwr_trim; 6042 6043 struct rtw89_cfo_tracking_info cfo_tracking; 6044 union { 6045 struct rtw89_phy_bb_gain_info ax; 6046 struct rtw89_phy_bb_gain_info_be be; 6047 } bb_gain; 6048 struct rtw89_phy_efuse_gain efuse_gain; 6049 struct rtw89_phy_ul_tb_info ul_tb_info; 6050 struct rtw89_antdiv_info antdiv; 6051 6052 struct rtw89_bb_ctx { 6053 enum rtw89_phy_idx phy_idx; 6054 struct rtw89_env_monitor_info env_monitor; 6055 struct rtw89_dig_info dig; 6056 struct rtw89_phy_ch_info ch_info; 6057 struct rtw89_edcca_bak edcca_bak; 6058 } bbs[RTW89_PHY_NUM]; 6059 6060 struct wiphy_delayed_work track_work; 6061 struct wiphy_delayed_work track_ps_work; 6062 struct wiphy_delayed_work chanctx_work; 6063 struct wiphy_delayed_work coex_act1_work; 6064 struct wiphy_delayed_work coex_bt_devinfo_work; 6065 struct wiphy_delayed_work coex_rfk_chk_work; 6066 struct wiphy_delayed_work cfo_track_work; 6067 struct wiphy_delayed_work mcc_prepare_done_work; 6068 struct delayed_work forbid_ba_work; 6069 struct wiphy_delayed_work antdiv_work; 6070 struct rtw89_ppdu_sts_info ppdu_sts; 6071 u8 total_sta_assoc; 6072 bool scanning; 6073 6074 struct rtw89_regulatory_info regulatory; 6075 struct rtw89_sar_info sar; 6076 struct rtw89_tas_info tas; 6077 struct rtw89_ant_gain_info ant_gain; 6078 6079 struct rtw89_btc btc; 6080 enum rtw89_ps_mode ps_mode; 6081 bool lps_enabled; 6082 6083 struct rtw89_wow_param wow; 6084 6085 /* napi structure */ 6086 struct net_device *netdev; 6087 struct napi_struct napi; 6088 int napi_budget_countdown; 6089 6090 struct rtw89_debugfs *debugfs; 6091 6092 /* HCI related data, keep last */ 6093 u8 priv[] __aligned(sizeof(void *)); 6094 }; 6095 6096 struct rtw89_link_conf_container { 6097 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 6098 }; 6099 6100 #define RTW89_VIF_IDLE_LINK_ID 0 6101 6102 struct rtw89_vif { 6103 struct rtw89_dev *rtwdev; 6104 struct list_head list; 6105 struct list_head mgnt_entry; 6106 struct rtw89_link_conf_container __rcu *snap_link_confs; 6107 6108 u8 mac_addr[ETH_ALEN]; 6109 __be32 ip_addr; 6110 6111 struct rtw89_traffic_stats stats; 6112 struct rtw89_traffic_stats stats_ps; 6113 u32 tdls_peer; 6114 6115 struct ieee80211_scan_ies *scan_ies; 6116 struct cfg80211_scan_request *scan_req; 6117 6118 struct rtw89_roc roc; 6119 bool offchan; 6120 6121 enum rtw89_mlo_mode mlo_mode; 6122 6123 struct list_head dlink_pool; 6124 u8 links_inst_valid_num; 6125 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6126 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6127 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 6128 }; 6129 6130 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 6131 const struct rtw89_vif *rtwvif, 6132 unsigned int link_id) 6133 { 6134 *rtwvif_link = rtwvif->links[link_id]; 6135 return !!*rtwvif_link; 6136 } 6137 6138 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 6139 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6140 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 6141 6142 enum rtw89_sta_flags { 6143 RTW89_REMOTE_STA_IN_PS, 6144 6145 NUM_OF_RTW89_STA_FLAGS, 6146 }; 6147 6148 struct rtw89_sta { 6149 struct rtw89_dev *rtwdev; 6150 struct rtw89_vif *rtwvif; 6151 6152 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 6153 6154 bool disassoc; 6155 6156 struct sk_buff_head roc_queue; 6157 6158 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 6159 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 6160 6161 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 6162 6163 struct list_head dlink_pool; 6164 u8 links_inst_valid_num; 6165 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6166 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6167 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 6168 }; 6169 6170 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 6171 const struct rtw89_sta *rtwsta, 6172 unsigned int link_id) 6173 { 6174 *rtwsta_link = rtwsta->links[link_id]; 6175 return !!*rtwsta_link; 6176 } 6177 6178 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 6179 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6180 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 6181 6182 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 6183 { 6184 /* const after init, so no need to check if active first */ 6185 return rtwvif->links_inst[0].mac_id; 6186 } 6187 6188 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 6189 { 6190 /* const after init, so no need to check if active first */ 6191 return rtwvif->links_inst[0].port; 6192 } 6193 6194 static inline struct rtw89_vif_link * 6195 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 6196 { 6197 if (index >= rtwvif->links_inst_valid_num || 6198 !test_bit(index, rtwvif->links_inst_map)) 6199 return NULL; 6200 return &rtwvif->links_inst[index]; 6201 } 6202 6203 static inline 6204 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 6205 { 6206 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6207 6208 return rtwvif_link - rtwvif->links_inst; 6209 } 6210 6211 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 6212 { 6213 /* const after init, so no need to check if active first */ 6214 return rtwsta->links_inst[0].mac_id; 6215 } 6216 6217 static inline struct rtw89_sta_link * 6218 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 6219 { 6220 if (index >= rtwsta->links_inst_valid_num || 6221 !test_bit(index, rtwsta->links_inst_map)) 6222 return NULL; 6223 return &rtwsta->links_inst[index]; 6224 } 6225 6226 static inline 6227 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 6228 { 6229 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6230 6231 return rtwsta_link - rtwsta->links_inst; 6232 } 6233 6234 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 6235 { 6236 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6237 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6238 6239 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6240 rtwsta_link); 6241 } 6242 6243 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 6244 { 6245 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6246 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6247 6248 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6249 NULL); 6250 synchronize_rcu(); 6251 } 6252 6253 static inline struct rtw89_sta_link * 6254 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 6255 { 6256 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 6257 } 6258 6259 #define rtw89_get_designated_link(links_holder) \ 6260 ({ \ 6261 typeof(links_holder) p = links_holder; \ 6262 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 6263 }) 6264 6265 static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait) 6266 { 6267 dev_kfree_skb_any(wait->skb); 6268 kfree_rcu(wait, rcu_head); 6269 } 6270 6271 static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev) 6272 { 6273 struct rtw89_tx_wait_info *wait, *tmp; 6274 6275 lockdep_assert_wiphy(rtwdev->hw->wiphy); 6276 6277 list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) { 6278 if (!completion_done(&wait->completion)) 6279 continue; 6280 list_del(&wait->list); 6281 rtw89_tx_wait_release(wait); 6282 } 6283 } 6284 6285 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 6286 struct rtw89_core_tx_request *tx_req) 6287 { 6288 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 6289 } 6290 6291 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 6292 { 6293 rtwdev->hci.ops->reset(rtwdev); 6294 rtw89_tx_wait_list_clear(rtwdev); 6295 } 6296 6297 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 6298 { 6299 return rtwdev->hci.ops->start(rtwdev); 6300 } 6301 6302 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 6303 { 6304 rtwdev->hci.ops->stop(rtwdev); 6305 } 6306 6307 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 6308 { 6309 return rtwdev->hci.ops->deinit(rtwdev); 6310 } 6311 6312 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 6313 { 6314 rtwdev->hci.ops->pause(rtwdev, pause); 6315 } 6316 6317 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 6318 { 6319 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 6320 } 6321 6322 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 6323 { 6324 rtwdev->hci.ops->recalc_int_mit(rtwdev); 6325 } 6326 6327 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 6328 { 6329 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 6330 } 6331 6332 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 6333 { 6334 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 6335 } 6336 6337 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 6338 { 6339 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 6340 } 6341 6342 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 6343 bool drop) 6344 { 6345 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6346 return; 6347 6348 if (rtwdev->hci.ops->flush_queues) 6349 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 6350 } 6351 6352 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 6353 { 6354 if (rtwdev->hci.ops->recovery_start) 6355 rtwdev->hci.ops->recovery_start(rtwdev); 6356 } 6357 6358 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 6359 { 6360 if (rtwdev->hci.ops->recovery_complete) 6361 rtwdev->hci.ops->recovery_complete(rtwdev); 6362 } 6363 6364 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 6365 { 6366 if (rtwdev->hci.ops->enable_intr) 6367 rtwdev->hci.ops->enable_intr(rtwdev); 6368 } 6369 6370 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 6371 { 6372 if (rtwdev->hci.ops->disable_intr) 6373 rtwdev->hci.ops->disable_intr(rtwdev); 6374 } 6375 6376 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 6377 { 6378 if (rtwdev->hci.ops->ctrl_txdma_ch) 6379 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 6380 } 6381 6382 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6383 { 6384 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6385 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6386 } 6387 6388 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6389 { 6390 if (rtwdev->hci.ops->ctrl_trxhci) 6391 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6392 } 6393 6394 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6395 { 6396 int ret = 0; 6397 6398 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6399 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6400 return ret; 6401 } 6402 6403 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6404 { 6405 if (rtwdev->hci.ops->clr_idx_all) 6406 rtwdev->hci.ops->clr_idx_all(rtwdev); 6407 } 6408 6409 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6410 { 6411 int ret = 0; 6412 6413 if (rtwdev->hci.ops->rst_bdram) 6414 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6415 return ret; 6416 } 6417 6418 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6419 { 6420 if (rtwdev->hci.ops->clear) 6421 rtwdev->hci.ops->clear(rtwdev, pdev); 6422 } 6423 6424 static inline 6425 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6426 { 6427 /* 6428 * This should be used by/after rtw89_hci_tx_write() and before doing 6429 * ieee80211_tx_info_clear_status(). 6430 */ 6431 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6432 6433 return (struct rtw89_tx_skb_data *)info->driver_data; 6434 } 6435 6436 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6437 { 6438 return rtwdev->hci.ops->read8(rtwdev, addr); 6439 } 6440 6441 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6442 { 6443 return rtwdev->hci.ops->read16(rtwdev, addr); 6444 } 6445 6446 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6447 { 6448 return rtwdev->hci.ops->read32(rtwdev, addr); 6449 } 6450 6451 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6452 { 6453 rtwdev->hci.ops->write8(rtwdev, addr, data); 6454 } 6455 6456 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6457 { 6458 rtwdev->hci.ops->write16(rtwdev, addr, data); 6459 } 6460 6461 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6462 { 6463 rtwdev->hci.ops->write32(rtwdev, addr, data); 6464 } 6465 6466 static inline void 6467 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6468 { 6469 u8 val; 6470 6471 val = rtw89_read8(rtwdev, addr); 6472 rtw89_write8(rtwdev, addr, val | bit); 6473 } 6474 6475 static inline void 6476 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6477 { 6478 u16 val; 6479 6480 val = rtw89_read16(rtwdev, addr); 6481 rtw89_write16(rtwdev, addr, val | bit); 6482 } 6483 6484 static inline void 6485 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6486 { 6487 u32 val; 6488 6489 val = rtw89_read32(rtwdev, addr); 6490 rtw89_write32(rtwdev, addr, val | bit); 6491 } 6492 6493 static inline void 6494 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6495 { 6496 u8 val; 6497 6498 val = rtw89_read8(rtwdev, addr); 6499 rtw89_write8(rtwdev, addr, val & ~bit); 6500 } 6501 6502 static inline void 6503 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6504 { 6505 u16 val; 6506 6507 val = rtw89_read16(rtwdev, addr); 6508 rtw89_write16(rtwdev, addr, val & ~bit); 6509 } 6510 6511 static inline void 6512 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6513 { 6514 u32 val; 6515 6516 val = rtw89_read32(rtwdev, addr); 6517 rtw89_write32(rtwdev, addr, val & ~bit); 6518 } 6519 6520 static inline u32 6521 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6522 { 6523 u32 shift = __ffs(mask); 6524 u32 orig; 6525 u32 ret; 6526 6527 orig = rtw89_read32(rtwdev, addr); 6528 ret = (orig & mask) >> shift; 6529 6530 return ret; 6531 } 6532 6533 static inline u16 6534 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6535 { 6536 u32 shift = __ffs(mask); 6537 u32 orig; 6538 u32 ret; 6539 6540 orig = rtw89_read16(rtwdev, addr); 6541 ret = (orig & mask) >> shift; 6542 6543 return ret; 6544 } 6545 6546 static inline u8 6547 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6548 { 6549 u32 shift = __ffs(mask); 6550 u32 orig; 6551 u32 ret; 6552 6553 orig = rtw89_read8(rtwdev, addr); 6554 ret = (orig & mask) >> shift; 6555 6556 return ret; 6557 } 6558 6559 static inline void 6560 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6561 { 6562 u32 shift = __ffs(mask); 6563 u32 orig; 6564 u32 set; 6565 6566 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6567 6568 orig = rtw89_read32(rtwdev, addr); 6569 set = (orig & ~mask) | ((data << shift) & mask); 6570 rtw89_write32(rtwdev, addr, set); 6571 } 6572 6573 static inline void 6574 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6575 { 6576 u32 shift; 6577 u16 orig, set; 6578 6579 mask &= 0xffff; 6580 shift = __ffs(mask); 6581 6582 orig = rtw89_read16(rtwdev, addr); 6583 set = (orig & ~mask) | ((data << shift) & mask); 6584 rtw89_write16(rtwdev, addr, set); 6585 } 6586 6587 static inline void 6588 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6589 { 6590 u32 shift; 6591 u8 orig, set; 6592 6593 mask &= 0xff; 6594 shift = __ffs(mask); 6595 6596 orig = rtw89_read8(rtwdev, addr); 6597 set = (orig & ~mask) | ((data << shift) & mask); 6598 rtw89_write8(rtwdev, addr, set); 6599 } 6600 6601 static inline u32 6602 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6603 u32 addr, u32 mask) 6604 { 6605 u32 val; 6606 6607 mutex_lock(&rtwdev->rf_mutex); 6608 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6609 mutex_unlock(&rtwdev->rf_mutex); 6610 6611 return val; 6612 } 6613 6614 static inline void 6615 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6616 u32 addr, u32 mask, u32 data) 6617 { 6618 mutex_lock(&rtwdev->rf_mutex); 6619 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6620 mutex_unlock(&rtwdev->rf_mutex); 6621 } 6622 6623 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6624 { 6625 void *p = rtwtxq; 6626 6627 return container_of(p, struct ieee80211_txq, drv_priv); 6628 } 6629 6630 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6631 struct ieee80211_txq *txq) 6632 { 6633 struct rtw89_txq *rtwtxq; 6634 6635 if (!txq) 6636 return; 6637 6638 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6639 INIT_LIST_HEAD(&rtwtxq->list); 6640 } 6641 6642 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6643 { 6644 void *p = rtwvif; 6645 6646 return container_of(p, struct ieee80211_vif, drv_priv); 6647 } 6648 6649 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6650 { 6651 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6652 } 6653 6654 static inline 6655 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6656 { 6657 return rtwvif_to_vif(rtwvif_link->rtwvif); 6658 } 6659 6660 static inline 6661 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6662 { 6663 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6664 } 6665 6666 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6667 { 6668 return (struct rtw89_vif *)vif->drv_priv; 6669 } 6670 6671 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6672 { 6673 return vif ? vif_to_rtwvif(vif) : NULL; 6674 } 6675 6676 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6677 { 6678 void *p = rtwsta; 6679 6680 return container_of(p, struct ieee80211_sta, drv_priv); 6681 } 6682 6683 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6684 { 6685 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6686 } 6687 6688 static inline 6689 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6690 { 6691 return rtwsta_to_sta(rtwsta_link->rtwsta); 6692 } 6693 6694 static inline 6695 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6696 { 6697 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6698 } 6699 6700 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6701 { 6702 return (struct rtw89_sta *)sta->drv_priv; 6703 } 6704 6705 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6706 { 6707 return sta ? sta_to_rtwsta(sta) : NULL; 6708 } 6709 6710 static inline struct ieee80211_bss_conf * 6711 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6712 { 6713 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6714 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6715 struct rtw89_link_conf_container *snap; 6716 struct ieee80211_bss_conf *bss_conf; 6717 6718 snap = rcu_dereference(rtwvif->snap_link_confs); 6719 if (snap) { 6720 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6721 goto out; 6722 } 6723 6724 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6725 6726 out: 6727 if (unlikely(!bss_conf)) { 6728 *nolink = true; 6729 return &vif->bss_conf; 6730 } 6731 6732 *nolink = false; 6733 return bss_conf; 6734 } 6735 6736 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6737 ({ \ 6738 typeof(rtwvif_link) p = rtwvif_link; \ 6739 struct ieee80211_bss_conf *bss_conf; \ 6740 bool nolink; \ 6741 \ 6742 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6743 if (unlikely(nolink) && (assert)) \ 6744 rtw89_err(p->rtwvif->rtwdev, \ 6745 "%s: cannot find exact bss_conf for link_id %u\n",\ 6746 __func__, p->link_id); \ 6747 bss_conf; \ 6748 }) 6749 6750 static inline struct ieee80211_link_sta * 6751 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6752 { 6753 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6754 struct ieee80211_link_sta *link_sta; 6755 6756 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6757 if (unlikely(!link_sta)) { 6758 *nolink = true; 6759 return &sta->deflink; 6760 } 6761 6762 *nolink = false; 6763 return link_sta; 6764 } 6765 6766 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6767 ({ \ 6768 typeof(rtwsta_link) p = rtwsta_link; \ 6769 struct ieee80211_link_sta *link_sta; \ 6770 bool nolink; \ 6771 \ 6772 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6773 if (unlikely(nolink) && (assert)) \ 6774 rtw89_err(p->rtwsta->rtwdev, \ 6775 "%s: cannot find exact link_sta for link_id %u\n",\ 6776 __func__, p->link_id); \ 6777 link_sta; \ 6778 }) 6779 6780 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6781 { 6782 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6783 return RATE_INFO_BW_160; 6784 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6785 return RATE_INFO_BW_80; 6786 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6787 return RATE_INFO_BW_40; 6788 else 6789 return RATE_INFO_BW_20; 6790 } 6791 6792 static inline 6793 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6794 { 6795 switch (hw_band) { 6796 default: 6797 case RTW89_BAND_2G: 6798 return NL80211_BAND_2GHZ; 6799 case RTW89_BAND_5G: 6800 return NL80211_BAND_5GHZ; 6801 case RTW89_BAND_6G: 6802 return NL80211_BAND_6GHZ; 6803 } 6804 } 6805 6806 static inline 6807 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6808 { 6809 switch (nl_band) { 6810 default: 6811 case NL80211_BAND_2GHZ: 6812 return RTW89_BAND_2G; 6813 case NL80211_BAND_5GHZ: 6814 return RTW89_BAND_5G; 6815 case NL80211_BAND_6GHZ: 6816 return RTW89_BAND_6G; 6817 } 6818 } 6819 6820 static inline 6821 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6822 { 6823 switch (width) { 6824 default: 6825 WARN(1, "Not support bandwidth %d\n", width); 6826 fallthrough; 6827 case NL80211_CHAN_WIDTH_20_NOHT: 6828 case NL80211_CHAN_WIDTH_20: 6829 return RTW89_CHANNEL_WIDTH_20; 6830 case NL80211_CHAN_WIDTH_40: 6831 return RTW89_CHANNEL_WIDTH_40; 6832 case NL80211_CHAN_WIDTH_80: 6833 return RTW89_CHANNEL_WIDTH_80; 6834 case NL80211_CHAN_WIDTH_160: 6835 return RTW89_CHANNEL_WIDTH_160; 6836 } 6837 } 6838 6839 static inline 6840 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6841 { 6842 switch (rua) { 6843 default: 6844 WARN(1, "Invalid RU allocation: %d\n", rua); 6845 fallthrough; 6846 case 0 ... 36: 6847 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6848 case 37 ... 52: 6849 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6850 case 53 ... 60: 6851 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6852 case 61 ... 64: 6853 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6854 case 65 ... 66: 6855 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6856 case 67: 6857 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6858 case 68: 6859 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6860 } 6861 } 6862 6863 static inline 6864 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6865 struct rtw89_sta_link *rtwsta_link) 6866 { 6867 if (rtwsta_link) { 6868 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6869 6870 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6871 return &rtwsta_link->addr_cam; 6872 } 6873 return &rtwvif_link->addr_cam; 6874 } 6875 6876 static inline 6877 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6878 struct rtw89_sta_link *rtwsta_link) 6879 { 6880 if (rtwsta_link) { 6881 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6882 6883 if (sta->tdls) 6884 return &rtwsta_link->bssid_cam; 6885 } 6886 return &rtwvif_link->bssid_cam; 6887 } 6888 6889 static inline 6890 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6891 struct rtw89_channel_help_params *p, 6892 const struct rtw89_chan *chan, 6893 enum rtw89_mac_idx mac_idx, 6894 enum rtw89_phy_idx phy_idx) 6895 { 6896 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6897 mac_idx, phy_idx); 6898 } 6899 6900 static inline 6901 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6902 struct rtw89_channel_help_params *p, 6903 const struct rtw89_chan *chan, 6904 enum rtw89_mac_idx mac_idx, 6905 enum rtw89_phy_idx phy_idx) 6906 { 6907 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6908 mac_idx, phy_idx); 6909 } 6910 6911 static inline 6912 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6913 enum rtw89_chanctx_idx idx) 6914 { 6915 struct rtw89_hal *hal = &rtwdev->hal; 6916 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6917 6918 if (roc_idx == idx) 6919 return &hal->roc_chandef; 6920 6921 return &hal->chanctx[idx].chandef; 6922 } 6923 6924 static inline 6925 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6926 enum rtw89_chanctx_idx idx) 6927 { 6928 struct rtw89_hal *hal = &rtwdev->hal; 6929 6930 return &hal->chanctx[idx].chan; 6931 } 6932 6933 static inline 6934 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6935 enum rtw89_chanctx_idx idx) 6936 { 6937 struct rtw89_hal *hal = &rtwdev->hal; 6938 6939 return &hal->chanctx[idx].rcd; 6940 } 6941 6942 static inline 6943 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6944 { 6945 const struct rtw89_chanctx *chanctx = 6946 container_of_const(chan, struct rtw89_chanctx, chan); 6947 6948 return &chanctx->rcd; 6949 } 6950 6951 static inline 6952 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6953 { 6954 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6955 6956 if (rtwvif_link) 6957 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6958 else 6959 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6960 } 6961 6962 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6963 { 6964 const struct rtw89_chip_info *chip = rtwdev->chip; 6965 6966 if (chip->ops->fem_setup) 6967 chip->ops->fem_setup(rtwdev); 6968 } 6969 6970 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6971 { 6972 const struct rtw89_chip_info *chip = rtwdev->chip; 6973 6974 if (chip->ops->rfe_gpio) 6975 chip->ops->rfe_gpio(rtwdev); 6976 } 6977 6978 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6979 { 6980 const struct rtw89_chip_info *chip = rtwdev->chip; 6981 6982 if (chip->ops->rfk_hw_init) 6983 chip->ops->rfk_hw_init(rtwdev); 6984 } 6985 6986 static inline 6987 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6988 { 6989 const struct rtw89_chip_info *chip = rtwdev->chip; 6990 6991 if (chip->ops->bb_preinit) 6992 chip->ops->bb_preinit(rtwdev, phy_idx); 6993 } 6994 6995 static inline 6996 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6997 { 6998 const struct rtw89_chip_info *chip = rtwdev->chip; 6999 7000 if (!chip->ops->bb_postinit) 7001 return; 7002 7003 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 7004 7005 if (rtwdev->dbcc_en) 7006 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 7007 } 7008 7009 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 7010 { 7011 const struct rtw89_chip_info *chip = rtwdev->chip; 7012 7013 if (chip->ops->bb_sethw) 7014 chip->ops->bb_sethw(rtwdev); 7015 } 7016 7017 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 7018 { 7019 const struct rtw89_chip_info *chip = rtwdev->chip; 7020 7021 if (chip->ops->rfk_init) 7022 chip->ops->rfk_init(rtwdev); 7023 } 7024 7025 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 7026 { 7027 const struct rtw89_chip_info *chip = rtwdev->chip; 7028 7029 if (chip->ops->rfk_init_late) 7030 chip->ops->rfk_init_late(rtwdev); 7031 } 7032 7033 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 7034 struct rtw89_vif_link *rtwvif_link) 7035 { 7036 const struct rtw89_chip_info *chip = rtwdev->chip; 7037 7038 if (chip->ops->rfk_channel) 7039 chip->ops->rfk_channel(rtwdev, rtwvif_link); 7040 } 7041 7042 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 7043 enum rtw89_phy_idx phy_idx, 7044 const struct rtw89_chan *chan) 7045 { 7046 const struct rtw89_chip_info *chip = rtwdev->chip; 7047 7048 if (chip->ops->rfk_band_changed) 7049 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 7050 } 7051 7052 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 7053 struct rtw89_vif_link *rtwvif_link, bool start) 7054 { 7055 const struct rtw89_chip_info *chip = rtwdev->chip; 7056 7057 if (chip->ops->rfk_scan) 7058 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 7059 } 7060 7061 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 7062 { 7063 const struct rtw89_chip_info *chip = rtwdev->chip; 7064 7065 if (chip->ops->rfk_track) 7066 chip->ops->rfk_track(rtwdev); 7067 } 7068 7069 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 7070 { 7071 const struct rtw89_chip_info *chip = rtwdev->chip; 7072 7073 if (!chip->ops->set_txpwr_ctrl) 7074 return; 7075 7076 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 7077 if (rtwdev->dbcc_en) 7078 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 7079 } 7080 7081 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 7082 { 7083 const struct rtw89_chip_info *chip = rtwdev->chip; 7084 7085 if (chip->ops->power_trim) 7086 chip->ops->power_trim(rtwdev); 7087 } 7088 7089 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 7090 enum rtw89_phy_idx phy_idx) 7091 { 7092 const struct rtw89_chip_info *chip = rtwdev->chip; 7093 7094 if (chip->ops->init_txpwr_unit) 7095 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 7096 } 7097 7098 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 7099 { 7100 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 7101 if (rtwdev->dbcc_en) 7102 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 7103 } 7104 7105 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 7106 enum rtw89_rf_path rf_path) 7107 { 7108 const struct rtw89_chip_info *chip = rtwdev->chip; 7109 7110 if (!chip->ops->get_thermal) 7111 return 0x10; 7112 7113 return chip->ops->get_thermal(rtwdev, rf_path); 7114 } 7115 7116 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev, 7117 const struct rtw89_chan *chan) 7118 { 7119 const struct rtw89_chip_info *chip = rtwdev->chip; 7120 7121 if (!chip->ops->chan_to_rf18_val) 7122 return 0; 7123 7124 return chip->ops->chan_to_rf18_val(rtwdev, chan); 7125 } 7126 7127 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 7128 struct rtw89_rx_phy_ppdu *phy_ppdu, 7129 struct ieee80211_rx_status *status) 7130 { 7131 const struct rtw89_chip_info *chip = rtwdev->chip; 7132 7133 if (chip->ops->query_ppdu) 7134 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 7135 } 7136 7137 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 7138 struct rtw89_rx_phy_ppdu *phy_ppdu) 7139 { 7140 const struct rtw89_chip_info *chip = rtwdev->chip; 7141 7142 if (chip->ops->convert_rpl_to_rssi) 7143 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 7144 } 7145 7146 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 7147 struct rtw89_rx_desc_info *desc_info, 7148 struct ieee80211_rx_status *rx_status) 7149 { 7150 const struct rtw89_chip_info *chip = rtwdev->chip; 7151 7152 if (chip->ops->phy_rpt_to_rssi) 7153 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 7154 } 7155 7156 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 7157 enum rtw89_phy_idx phy_idx) 7158 { 7159 const struct rtw89_chip_info *chip = rtwdev->chip; 7160 7161 if (chip->ops->ctrl_nbtg_bt_tx) 7162 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 7163 } 7164 7165 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 7166 { 7167 const struct rtw89_chip_info *chip = rtwdev->chip; 7168 7169 if (chip->ops->cfg_txrx_path) 7170 chip->ops->cfg_txrx_path(rtwdev); 7171 } 7172 7173 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 7174 enum rtw89_phy_idx phy_idx) 7175 { 7176 const struct rtw89_chip_info *chip = rtwdev->chip; 7177 7178 if (chip->ops->digital_pwr_comp) 7179 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 7180 } 7181 7182 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 7183 const struct rtw89_txpwr_table *tbl) 7184 { 7185 tbl->load(rtwdev, tbl); 7186 } 7187 7188 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 7189 { 7190 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 7191 const struct rtw89_regd *regd = regulatory->regd; 7192 u8 txpwr_regd = regd->txpwr_regd[band]; 7193 7194 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK) 7195 return RTW89_ETSI; 7196 7197 return txpwr_regd; 7198 } 7199 7200 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 7201 enum rtw89_phy_idx phy_idx) 7202 { 7203 const struct rtw89_chip_info *chip = rtwdev->chip; 7204 7205 if (chip->ops->ctrl_btg_bt_rx) 7206 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 7207 } 7208 7209 static inline 7210 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 7211 struct rtw89_rx_desc_info *desc_info, 7212 u8 *data, u32 data_offset) 7213 { 7214 const struct rtw89_chip_info *chip = rtwdev->chip; 7215 7216 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 7217 } 7218 7219 static inline 7220 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 7221 struct rtw89_tx_desc_info *desc_info, 7222 void *txdesc) 7223 { 7224 const struct rtw89_chip_info *chip = rtwdev->chip; 7225 7226 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 7227 } 7228 7229 static inline 7230 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 7231 struct rtw89_tx_desc_info *desc_info, 7232 void *txdesc) 7233 { 7234 const struct rtw89_chip_info *chip = rtwdev->chip; 7235 7236 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 7237 } 7238 7239 static inline 7240 u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 7241 { 7242 const struct rtw89_chip_info *chip = rtwdev->chip; 7243 7244 return chip->ops->get_ch_dma(rtwdev, qsel); 7245 } 7246 7247 static inline 7248 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 7249 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 7250 { 7251 const struct rtw89_chip_info *chip = rtwdev->chip; 7252 7253 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 7254 } 7255 7256 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 7257 { 7258 const struct rtw89_chip_info *chip = rtwdev->chip; 7259 7260 chip->ops->cfg_ctrl_path(rtwdev, wl); 7261 } 7262 7263 static inline 7264 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 7265 u32 *tx_en, enum rtw89_sch_tx_sel sel) 7266 { 7267 const struct rtw89_chip_info *chip = rtwdev->chip; 7268 7269 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 7270 } 7271 7272 static inline 7273 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 7274 { 7275 const struct rtw89_chip_info *chip = rtwdev->chip; 7276 7277 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 7278 } 7279 7280 static inline 7281 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 7282 struct rtw89_vif_link *rtwvif_link, 7283 struct rtw89_sta_link *rtwsta_link) 7284 { 7285 const struct rtw89_chip_info *chip = rtwdev->chip; 7286 7287 if (!chip->ops->h2c_dctl_sec_cam) 7288 return 0; 7289 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 7290 } 7291 7292 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 7293 { 7294 __le16 fc = hdr->frame_control; 7295 7296 if (ieee80211_has_tods(fc)) 7297 return hdr->addr1; 7298 else if (ieee80211_has_fromds(fc)) 7299 return hdr->addr2; 7300 else 7301 return hdr->addr3; 7302 } 7303 7304 static inline 7305 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 7306 { 7307 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 7308 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 7309 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 7310 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 7311 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 7312 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 7313 return true; 7314 return false; 7315 } 7316 7317 static inline 7318 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 7319 { 7320 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 7321 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 7322 return true; 7323 7324 return false; 7325 } 7326 7327 static inline 7328 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 7329 { 7330 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 7331 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 7332 return true; 7333 7334 return false; 7335 } 7336 7337 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 7338 enum rtw89_fw_type type) 7339 { 7340 struct rtw89_fw_info *fw_info = &rtwdev->fw; 7341 7342 switch (type) { 7343 case RTW89_FW_WOWLAN: 7344 return &fw_info->wowlan; 7345 case RTW89_FW_LOGFMT: 7346 return &fw_info->log.suit; 7347 case RTW89_FW_BBMCU0: 7348 return &fw_info->bbmcu0; 7349 case RTW89_FW_BBMCU1: 7350 return &fw_info->bbmcu1; 7351 default: 7352 break; 7353 } 7354 7355 return &fw_info->normal; 7356 } 7357 7358 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 7359 unsigned int length) 7360 { 7361 struct sk_buff *skb; 7362 7363 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 7364 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 7365 if (!skb) 7366 return NULL; 7367 7368 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 7369 return skb; 7370 } 7371 7372 return dev_alloc_skb(length); 7373 } 7374 7375 static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7376 struct rtw89_tx_skb_data *skb_data, 7377 bool tx_done) 7378 { 7379 struct rtw89_tx_wait_info *wait; 7380 bool ret = false; 7381 7382 rcu_read_lock(); 7383 7384 wait = rcu_dereference(skb_data->wait); 7385 if (!wait) 7386 goto out; 7387 7388 ret = true; 7389 wait->tx_done = tx_done; 7390 /* Don't access skb anymore after completion */ 7391 complete_all(&wait->completion); 7392 7393 out: 7394 rcu_read_unlock(); 7395 return ret; 7396 } 7397 7398 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 7399 { 7400 switch (rtwdev->mlo_dbcc_mode) { 7401 case MLO_1_PLUS_1_1RF: 7402 case MLO_1_PLUS_1_2RF: 7403 case DBCC_LEGACY: 7404 return true; 7405 default: 7406 return false; 7407 } 7408 } 7409 7410 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 7411 { 7412 if (!rtwdev->dbcc_en) 7413 return BIT(RTW89_PHY_0); 7414 7415 switch (rtwdev->mlo_dbcc_mode) { 7416 case MLO_0_PLUS_2_1RF: 7417 case MLO_0_PLUS_2_2RF: 7418 return BIT(RTW89_PHY_1); 7419 case MLO_1_PLUS_1_1RF: 7420 case MLO_1_PLUS_1_2RF: 7421 case MLO_2_PLUS_2_2RF: 7422 case DBCC_LEGACY: 7423 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 7424 case MLO_2_PLUS_0_1RF: 7425 case MLO_2_PLUS_0_2RF: 7426 default: 7427 return BIT(RTW89_PHY_0); 7428 } 7429 } 7430 7431 #define rtw89_for_each_active_bb(rtwdev, bb) \ 7432 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 7433 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 7434 if (__active_bb_bitmap & BIT(__phy_idx) && \ 7435 (bb = &rtwdev->bbs[__phy_idx])) 7436 7437 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 7438 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 7439 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 7440 if ((bb = &rtwdev->bbs[__phy_idx])) 7441 7442 static inline 7443 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 7444 enum rtw89_phy_idx phy_idx) 7445 { 7446 if (phy_idx >= RTW89_PHY_NUM) 7447 return &rtwdev->bbs[RTW89_PHY_0]; 7448 7449 return &rtwdev->bbs[phy_idx]; 7450 } 7451 7452 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7453 { 7454 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7455 7456 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7457 return true; 7458 7459 return false; 7460 } 7461 7462 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval) 7463 { 7464 switch (interval) { 7465 default: 7466 case RTW89_TFC_INTERVAL_2SEC: 7467 return bytes >> 18; /* bytes/2s --> Mbps */; 7468 case RTW89_TFC_INTERVAL_100MS: 7469 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */ 7470 } 7471 } 7472 7473 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7474 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7475 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7476 struct sk_buff *skb, bool fwdl); 7477 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7478 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7479 struct rtw89_tx_wait_info *wait, int qsel, 7480 unsigned int timeout); 7481 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7482 struct rtw89_tx_desc_info *desc_info, 7483 void *txdesc); 7484 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7485 struct rtw89_tx_desc_info *desc_info, 7486 void *txdesc); 7487 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7488 struct rtw89_tx_desc_info *desc_info, 7489 void *txdesc); 7490 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7491 struct rtw89_tx_desc_info *desc_info, 7492 void *txdesc); 7493 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7494 struct rtw89_tx_desc_info *desc_info, 7495 void *txdesc); 7496 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel); 7497 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel); 7498 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7499 struct rtw89_rx_desc_info *desc_info, 7500 struct sk_buff *skb); 7501 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7502 struct rtw89_rx_desc_info *desc_info, 7503 u8 *data, u32 data_offset); 7504 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7505 struct rtw89_rx_desc_info *desc_info, 7506 u8 *data, u32 data_offset); 7507 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7508 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7509 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7510 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7511 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7512 struct rtw89_vif_link *rtwvif_link, 7513 struct rtw89_sta_link *rtwsta_link); 7514 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7515 struct rtw89_vif_link *rtwvif_link, 7516 struct rtw89_sta_link *rtwsta_link); 7517 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7518 struct rtw89_vif_link *rtwvif_link, 7519 struct rtw89_sta_link *rtwsta_link); 7520 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7521 struct rtw89_vif_link *rtwvif_link, 7522 struct rtw89_sta_link *rtwsta_link); 7523 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7524 struct rtw89_vif_link *rtwvif_link, 7525 struct rtw89_sta_link *rtwsta_link); 7526 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7527 struct ieee80211_sta *sta, 7528 struct cfg80211_tid_config *tid_config); 7529 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7530 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7531 int rtw89_core_init(struct rtw89_dev *rtwdev); 7532 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7533 int rtw89_core_register(struct rtw89_dev *rtwdev); 7534 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7535 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7536 u32 bus_data_size, 7537 const struct rtw89_chip_info *chip, 7538 const struct rtw89_chip_variant *variant); 7539 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7540 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7541 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7542 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7543 u8 mac_id, u8 port); 7544 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7545 struct rtw89_sta *rtwsta, u8 mac_id); 7546 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7547 unsigned int link_id); 7548 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7549 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7550 unsigned int link_id); 7551 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7552 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7553 const struct rtw89_6ghz_span * 7554 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7555 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7556 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7557 struct rtw89_chan *chan); 7558 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7559 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7560 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7561 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7562 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7563 struct rtw89_sta_link *rtwsta_link, u8 tid, 7564 u8 *cam_idx); 7565 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7566 struct rtw89_sta_link *rtwsta_link, u8 tid, 7567 u8 *cam_idx); 7568 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7569 struct ieee80211_sta *sta); 7570 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7571 struct ieee80211_sta *sta); 7572 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7573 struct ieee80211_sta *sta); 7574 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7575 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7576 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7577 struct rtw89_vif_link *rtwvif_link); 7578 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate); 7579 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7580 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7581 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 7582 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7583 struct rtw89_traffic_stats *stats); 7584 struct rtw89_wait_response * 7585 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 7586 __acquires(rtw89_wait); 7587 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 7588 struct rtw89_wait_response *prep, int err) 7589 __releases(rtw89_wait); 7590 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7591 const struct rtw89_completion_data *data); 7592 int rtw89_core_start(struct rtw89_dev *rtwdev); 7593 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7594 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7595 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7596 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7597 bool qos, bool ps, int timeout); 7598 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 7599 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7600 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7601 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7602 const u8 *mac_addr, bool hw_scan); 7603 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7604 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7605 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7606 bool active); 7607 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7608 struct rtw89_vif_link *rtwvif_link, 7609 struct ieee80211_bss_conf *bss_conf); 7610 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7611 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7612 unsigned int link_id); 7613 7614 #endif 7615