1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_efuse_block_cfg; 21 struct rtw89_h2c_rf_tssi; 22 struct rtw89_fw_txpwr_track_cfg; 23 struct rtw89_phy_rfk_log_fmt; 24 25 extern const struct ieee80211_ops rtw89_ops; 26 27 #define MASKBYTE0 0xff 28 #define MASKBYTE1 0xff00 29 #define MASKBYTE2 0xff0000 30 #define MASKBYTE3 0xff000000 31 #define MASKBYTE4 0xff00000000ULL 32 #define MASKHWORD 0xffff0000 33 #define MASKLWORD 0x0000ffff 34 #define MASKDWORD 0xffffffff 35 #define RFREG_MASK 0xfffff 36 #define INV_RF_DATA 0xffffffff 37 #define BYPASS_CR_DATA 0xbabecafe 38 39 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 40 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 41 #define CFO_TRACK_MAX_USER 64 42 #define MAX_RSSI 110 43 #define RSSI_FACTOR 1 44 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 45 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 46 #define DELTA_SWINGIDX_SIZE 30 47 48 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 49 #define RTW89_RADIOTAP_ROOM_EHT \ 50 (sizeof(struct ieee80211_radiotap_tlv) + \ 51 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 52 sizeof(struct ieee80211_radiotap_tlv) + \ 53 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 54 #define RTW89_RADIOTAP_ROOM \ 55 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 56 57 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 58 #define RTW89_HTC_VARIANT_HE 3 59 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 60 #define RTW89_HTC_VARIANT_HE_CID_OM 1 61 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 62 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 63 64 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 65 enum htc_om_channel_width { 66 HTC_OM_CHANNEL_WIDTH_20 = 0, 67 HTC_OM_CHANNEL_WIDTH_40 = 1, 68 HTC_OM_CHANNEL_WIDTH_80 = 2, 69 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 70 }; 71 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 72 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 73 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 74 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 75 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 76 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 77 78 #define RTW89_TF_PAD GENMASK(11, 0) 79 #define RTW89_TF_BASIC_USER_INFO_SZ 6 80 81 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 82 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 83 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 84 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 85 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 86 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 87 88 enum rtw89_subband { 89 RTW89_CH_2G = 0, 90 RTW89_CH_5G_BAND_1 = 1, 91 /* RTW89_CH_5G_BAND_2 = 2, unused */ 92 RTW89_CH_5G_BAND_3 = 3, 93 RTW89_CH_5G_BAND_4 = 4, 94 95 RTW89_CH_6G_BAND_IDX0, /* Low */ 96 RTW89_CH_6G_BAND_IDX1, /* Low */ 97 RTW89_CH_6G_BAND_IDX2, /* Mid */ 98 RTW89_CH_6G_BAND_IDX3, /* Mid */ 99 RTW89_CH_6G_BAND_IDX4, /* High */ 100 RTW89_CH_6G_BAND_IDX5, /* High */ 101 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 102 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 103 104 RTW89_SUBBAND_NR, 105 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 106 }; 107 108 enum rtw89_gain_offset { 109 RTW89_GAIN_OFFSET_2G_CCK, 110 RTW89_GAIN_OFFSET_2G_OFDM, 111 RTW89_GAIN_OFFSET_5G_LOW, 112 RTW89_GAIN_OFFSET_5G_MID, 113 RTW89_GAIN_OFFSET_5G_HIGH, 114 RTW89_GAIN_OFFSET_6G_L0, 115 RTW89_GAIN_OFFSET_6G_L1, 116 RTW89_GAIN_OFFSET_6G_M0, 117 RTW89_GAIN_OFFSET_6G_M1, 118 RTW89_GAIN_OFFSET_6G_H0, 119 RTW89_GAIN_OFFSET_6G_H1, 120 RTW89_GAIN_OFFSET_6G_UH0, 121 RTW89_GAIN_OFFSET_6G_UH1, 122 123 RTW89_GAIN_OFFSET_NR, 124 }; 125 126 enum rtw89_hci_type { 127 RTW89_HCI_TYPE_PCIE, 128 RTW89_HCI_TYPE_USB, 129 RTW89_HCI_TYPE_SDIO, 130 }; 131 132 enum rtw89_core_chip_id { 133 RTL8852A, 134 RTL8852B, 135 RTL8852BT, 136 RTL8852C, 137 RTL8851B, 138 RTL8922A, 139 }; 140 141 enum rtw89_chip_gen { 142 RTW89_CHIP_AX, 143 RTW89_CHIP_BE, 144 145 RTW89_CHIP_GEN_NUM, 146 }; 147 148 enum rtw89_cv { 149 CHIP_CAV, 150 CHIP_CBV, 151 CHIP_CCV, 152 CHIP_CDV, 153 CHIP_CEV, 154 CHIP_CFV, 155 CHIP_CV_MAX, 156 CHIP_CV_INVALID = CHIP_CV_MAX, 157 }; 158 159 enum rtw89_bacam_ver { 160 RTW89_BACAM_V0, 161 RTW89_BACAM_V1, 162 163 RTW89_BACAM_V0_EXT = 99, 164 }; 165 166 enum rtw89_core_tx_type { 167 RTW89_CORE_TX_TYPE_DATA, 168 RTW89_CORE_TX_TYPE_MGMT, 169 RTW89_CORE_TX_TYPE_FWCMD, 170 }; 171 172 enum rtw89_core_rx_type { 173 RTW89_CORE_RX_TYPE_WIFI = 0, 174 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 175 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 176 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 177 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 178 RTW89_CORE_RX_TYPE_SS2FW = 5, 179 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 180 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 181 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 182 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 183 RTW89_CORE_RX_TYPE_C2H = 10, 184 RTW89_CORE_RX_TYPE_CSI = 11, 185 RTW89_CORE_RX_TYPE_CQI = 12, 186 RTW89_CORE_RX_TYPE_H2C = 13, 187 RTW89_CORE_RX_TYPE_FWDL = 14, 188 }; 189 190 enum rtw89_txq_flags { 191 RTW89_TXQ_F_AMPDU = 0, 192 RTW89_TXQ_F_BLOCK_BA = 1, 193 RTW89_TXQ_F_FORBID_BA = 2, 194 }; 195 196 enum rtw89_net_type { 197 RTW89_NET_TYPE_NO_LINK = 0, 198 RTW89_NET_TYPE_AD_HOC = 1, 199 RTW89_NET_TYPE_INFRA = 2, 200 RTW89_NET_TYPE_AP_MODE = 3, 201 }; 202 203 enum rtw89_wifi_role { 204 RTW89_WIFI_ROLE_NONE, 205 RTW89_WIFI_ROLE_STATION, 206 RTW89_WIFI_ROLE_AP, 207 RTW89_WIFI_ROLE_AP_VLAN, 208 RTW89_WIFI_ROLE_ADHOC, 209 RTW89_WIFI_ROLE_ADHOC_MASTER, 210 RTW89_WIFI_ROLE_MESH_POINT, 211 RTW89_WIFI_ROLE_MONITOR, 212 RTW89_WIFI_ROLE_P2P_DEVICE, 213 RTW89_WIFI_ROLE_P2P_CLIENT, 214 RTW89_WIFI_ROLE_P2P_GO, 215 RTW89_WIFI_ROLE_NAN, 216 RTW89_WIFI_ROLE_MLME_MAX 217 }; 218 219 enum rtw89_upd_mode { 220 RTW89_ROLE_CREATE, 221 RTW89_ROLE_REMOVE, 222 RTW89_ROLE_TYPE_CHANGE, 223 RTW89_ROLE_INFO_CHANGE, 224 RTW89_ROLE_CON_DISCONN, 225 RTW89_ROLE_BAND_SW, 226 RTW89_ROLE_FW_RESTORE, 227 }; 228 229 enum rtw89_self_role { 230 RTW89_SELF_ROLE_CLIENT, 231 RTW89_SELF_ROLE_AP, 232 RTW89_SELF_ROLE_AP_CLIENT 233 }; 234 235 enum rtw89_msk_sO_el { 236 RTW89_NO_MSK, 237 RTW89_SMA, 238 RTW89_TMA, 239 RTW89_BSSID 240 }; 241 242 enum rtw89_sch_tx_sel { 243 RTW89_SCH_TX_SEL_ALL, 244 RTW89_SCH_TX_SEL_HIQ, 245 RTW89_SCH_TX_SEL_MG0, 246 RTW89_SCH_TX_SEL_MACID, 247 }; 248 249 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 250 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 251 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 252 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 253 */ 254 enum rtw89_add_cam_sec_mode { 255 RTW89_ADDR_CAM_SEC_NONE = 0, 256 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 257 RTW89_ADDR_CAM_SEC_NORMAL = 2, 258 RTW89_ADDR_CAM_SEC_4GROUP = 3, 259 }; 260 261 enum rtw89_sec_key_type { 262 RTW89_SEC_KEY_TYPE_NONE = 0, 263 RTW89_SEC_KEY_TYPE_WEP40 = 1, 264 RTW89_SEC_KEY_TYPE_WEP104 = 2, 265 RTW89_SEC_KEY_TYPE_TKIP = 3, 266 RTW89_SEC_KEY_TYPE_WAPI = 4, 267 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 268 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 269 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 270 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 271 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 272 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 273 }; 274 275 enum rtw89_port { 276 RTW89_PORT_0 = 0, 277 RTW89_PORT_1 = 1, 278 RTW89_PORT_2 = 2, 279 RTW89_PORT_3 = 3, 280 RTW89_PORT_4 = 4, 281 RTW89_PORT_NUM 282 }; 283 284 enum rtw89_band { 285 RTW89_BAND_2G = 0, 286 RTW89_BAND_5G = 1, 287 RTW89_BAND_6G = 2, 288 RTW89_BAND_NUM, 289 }; 290 291 enum rtw89_hw_rate { 292 RTW89_HW_RATE_CCK1 = 0x0, 293 RTW89_HW_RATE_CCK2 = 0x1, 294 RTW89_HW_RATE_CCK5_5 = 0x2, 295 RTW89_HW_RATE_CCK11 = 0x3, 296 RTW89_HW_RATE_OFDM6 = 0x4, 297 RTW89_HW_RATE_OFDM9 = 0x5, 298 RTW89_HW_RATE_OFDM12 = 0x6, 299 RTW89_HW_RATE_OFDM18 = 0x7, 300 RTW89_HW_RATE_OFDM24 = 0x8, 301 RTW89_HW_RATE_OFDM36 = 0x9, 302 RTW89_HW_RATE_OFDM48 = 0xA, 303 RTW89_HW_RATE_OFDM54 = 0xB, 304 RTW89_HW_RATE_MCS0 = 0x80, 305 RTW89_HW_RATE_MCS1 = 0x81, 306 RTW89_HW_RATE_MCS2 = 0x82, 307 RTW89_HW_RATE_MCS3 = 0x83, 308 RTW89_HW_RATE_MCS4 = 0x84, 309 RTW89_HW_RATE_MCS5 = 0x85, 310 RTW89_HW_RATE_MCS6 = 0x86, 311 RTW89_HW_RATE_MCS7 = 0x87, 312 RTW89_HW_RATE_MCS8 = 0x88, 313 RTW89_HW_RATE_MCS9 = 0x89, 314 RTW89_HW_RATE_MCS10 = 0x8A, 315 RTW89_HW_RATE_MCS11 = 0x8B, 316 RTW89_HW_RATE_MCS12 = 0x8C, 317 RTW89_HW_RATE_MCS13 = 0x8D, 318 RTW89_HW_RATE_MCS14 = 0x8E, 319 RTW89_HW_RATE_MCS15 = 0x8F, 320 RTW89_HW_RATE_MCS16 = 0x90, 321 RTW89_HW_RATE_MCS17 = 0x91, 322 RTW89_HW_RATE_MCS18 = 0x92, 323 RTW89_HW_RATE_MCS19 = 0x93, 324 RTW89_HW_RATE_MCS20 = 0x94, 325 RTW89_HW_RATE_MCS21 = 0x95, 326 RTW89_HW_RATE_MCS22 = 0x96, 327 RTW89_HW_RATE_MCS23 = 0x97, 328 RTW89_HW_RATE_MCS24 = 0x98, 329 RTW89_HW_RATE_MCS25 = 0x99, 330 RTW89_HW_RATE_MCS26 = 0x9A, 331 RTW89_HW_RATE_MCS27 = 0x9B, 332 RTW89_HW_RATE_MCS28 = 0x9C, 333 RTW89_HW_RATE_MCS29 = 0x9D, 334 RTW89_HW_RATE_MCS30 = 0x9E, 335 RTW89_HW_RATE_MCS31 = 0x9F, 336 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 337 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 338 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 339 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 340 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 341 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 342 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 343 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 344 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 345 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 346 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 347 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 348 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 349 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 350 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 351 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 352 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 353 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 354 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 355 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 356 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 357 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 358 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 359 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 360 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 361 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 362 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 363 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 364 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 365 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 366 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 367 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 368 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 369 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 370 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 371 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 372 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 373 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 374 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 375 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 376 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 377 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 378 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 379 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 380 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 381 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 382 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 383 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 384 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 385 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 386 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 387 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 388 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 389 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 390 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 391 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 392 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 393 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 394 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 395 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 396 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 397 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 398 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 399 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 400 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 401 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 402 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 403 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 404 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 405 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 406 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 407 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 408 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 409 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 410 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 411 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 412 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 413 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 414 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 415 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 416 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 417 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 418 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 419 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 420 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 421 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 422 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 423 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 424 425 RTW89_HW_RATE_V1_MCS0 = 0x100, 426 RTW89_HW_RATE_V1_MCS1 = 0x101, 427 RTW89_HW_RATE_V1_MCS2 = 0x102, 428 RTW89_HW_RATE_V1_MCS3 = 0x103, 429 RTW89_HW_RATE_V1_MCS4 = 0x104, 430 RTW89_HW_RATE_V1_MCS5 = 0x105, 431 RTW89_HW_RATE_V1_MCS6 = 0x106, 432 RTW89_HW_RATE_V1_MCS7 = 0x107, 433 RTW89_HW_RATE_V1_MCS8 = 0x108, 434 RTW89_HW_RATE_V1_MCS9 = 0x109, 435 RTW89_HW_RATE_V1_MCS10 = 0x10A, 436 RTW89_HW_RATE_V1_MCS11 = 0x10B, 437 RTW89_HW_RATE_V1_MCS12 = 0x10C, 438 RTW89_HW_RATE_V1_MCS13 = 0x10D, 439 RTW89_HW_RATE_V1_MCS14 = 0x10E, 440 RTW89_HW_RATE_V1_MCS15 = 0x10F, 441 RTW89_HW_RATE_V1_MCS16 = 0x110, 442 RTW89_HW_RATE_V1_MCS17 = 0x111, 443 RTW89_HW_RATE_V1_MCS18 = 0x112, 444 RTW89_HW_RATE_V1_MCS19 = 0x113, 445 RTW89_HW_RATE_V1_MCS20 = 0x114, 446 RTW89_HW_RATE_V1_MCS21 = 0x115, 447 RTW89_HW_RATE_V1_MCS22 = 0x116, 448 RTW89_HW_RATE_V1_MCS23 = 0x117, 449 RTW89_HW_RATE_V1_MCS24 = 0x118, 450 RTW89_HW_RATE_V1_MCS25 = 0x119, 451 RTW89_HW_RATE_V1_MCS26 = 0x11A, 452 RTW89_HW_RATE_V1_MCS27 = 0x11B, 453 RTW89_HW_RATE_V1_MCS28 = 0x11C, 454 RTW89_HW_RATE_V1_MCS29 = 0x11D, 455 RTW89_HW_RATE_V1_MCS30 = 0x11E, 456 RTW89_HW_RATE_V1_MCS31 = 0x11F, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 611 612 RTW89_HW_RATE_NR, 613 RTW89_HW_RATE_INVAL, 614 615 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 616 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 617 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 618 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 619 }; 620 621 /* 2G channels, 622 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 623 */ 624 #define RTW89_2G_CH_NUM 14 625 626 /* 5G channels, 627 * 36, 38, 40, 42, 44, 46, 48, 50, 628 * 52, 54, 56, 58, 60, 62, 64, 629 * 100, 102, 104, 106, 108, 110, 112, 114, 630 * 116, 118, 120, 122, 124, 126, 128, 130, 631 * 132, 134, 136, 138, 140, 142, 144, 632 * 149, 151, 153, 155, 157, 159, 161, 163, 633 * 165, 167, 169, 171, 173, 175, 177 634 */ 635 #define RTW89_5G_CH_NUM 53 636 637 /* 6G channels, 638 * 1, 3, 5, 7, 9, 11, 13, 15, 639 * 17, 19, 21, 23, 25, 27, 29, 33, 640 * 35, 37, 39, 41, 43, 45, 47, 49, 641 * 51, 53, 55, 57, 59, 61, 65, 67, 642 * 69, 71, 73, 75, 77, 79, 81, 83, 643 * 85, 87, 89, 91, 93, 97, 99, 101, 644 * 103, 105, 107, 109, 111, 113, 115, 117, 645 * 119, 121, 123, 125, 129, 131, 133, 135, 646 * 137, 139, 141, 143, 145, 147, 149, 151, 647 * 153, 155, 157, 161, 163, 165, 167, 169, 648 * 171, 173, 175, 177, 179, 181, 183, 185, 649 * 187, 189, 193, 195, 197, 199, 201, 203, 650 * 205, 207, 209, 211, 213, 215, 217, 219, 651 * 221, 225, 227, 229, 231, 233, 235, 237, 652 * 239, 241, 243, 245, 247, 249, 251, 253, 653 */ 654 #define RTW89_6G_CH_NUM 120 655 656 enum rtw89_rate_section { 657 RTW89_RS_CCK, 658 RTW89_RS_OFDM, 659 RTW89_RS_MCS, /* for HT/VHT/HE */ 660 RTW89_RS_HEDCM, 661 RTW89_RS_OFFSET, 662 RTW89_RS_NUM, 663 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 664 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 665 }; 666 667 enum rtw89_rate_offset_indexes { 668 RTW89_RATE_OFFSET_HE, 669 RTW89_RATE_OFFSET_VHT, 670 RTW89_RATE_OFFSET_HT, 671 RTW89_RATE_OFFSET_OFDM, 672 RTW89_RATE_OFFSET_CCK, 673 RTW89_RATE_OFFSET_DLRU_EHT, 674 RTW89_RATE_OFFSET_DLRU_HE, 675 RTW89_RATE_OFFSET_EHT, 676 __RTW89_RATE_OFFSET_NUM, 677 678 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 679 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 680 }; 681 682 enum rtw89_rate_num { 683 RTW89_RATE_CCK_NUM = 4, 684 RTW89_RATE_OFDM_NUM = 8, 685 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 686 687 RTW89_RATE_MCS_NUM_AX = 12, 688 RTW89_RATE_MCS_NUM_BE = 16, 689 __RTW89_RATE_MCS_NUM = 16, 690 }; 691 692 enum rtw89_nss { 693 RTW89_NSS_1 = 0, 694 RTW89_NSS_2 = 1, 695 /* HE DCM only support 1ss and 2ss */ 696 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 697 RTW89_NSS_3 = 2, 698 RTW89_NSS_4 = 3, 699 RTW89_NSS_NUM, 700 }; 701 702 enum rtw89_ntx { 703 RTW89_1TX = 0, 704 RTW89_2TX = 1, 705 RTW89_NTX_NUM, 706 }; 707 708 enum rtw89_beamforming_type { 709 RTW89_NONBF = 0, 710 RTW89_BF = 1, 711 RTW89_BF_NUM, 712 }; 713 714 enum rtw89_ofdma_type { 715 RTW89_NON_OFDMA = 0, 716 RTW89_OFDMA = 1, 717 RTW89_OFDMA_NUM, 718 }; 719 720 enum rtw89_regulation_type { 721 RTW89_WW = 0, 722 RTW89_ETSI = 1, 723 RTW89_FCC = 2, 724 RTW89_MKK = 3, 725 RTW89_NA = 4, 726 RTW89_IC = 5, 727 RTW89_KCC = 6, 728 RTW89_ACMA = 7, 729 RTW89_NCC = 8, 730 RTW89_MEXICO = 9, 731 RTW89_CHILE = 10, 732 RTW89_UKRAINE = 11, 733 RTW89_CN = 12, 734 RTW89_QATAR = 13, 735 RTW89_UK = 14, 736 RTW89_THAILAND = 15, 737 RTW89_REGD_NUM, 738 }; 739 740 enum rtw89_reg_6ghz_power { 741 RTW89_REG_6GHZ_POWER_VLP = 0, 742 RTW89_REG_6GHZ_POWER_LPI = 1, 743 RTW89_REG_6GHZ_POWER_STD = 2, 744 745 NUM_OF_RTW89_REG_6GHZ_POWER, 746 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 747 }; 748 749 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 750 751 /* calculate based on ieee80211 Transmit Power Envelope */ 752 struct rtw89_reg_6ghz_tpe { 753 bool valid; 754 s8 constraint; /* unit: dBm */ 755 }; 756 757 enum rtw89_fw_pkt_ofld_type { 758 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 759 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 760 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 761 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 762 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 763 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 764 RTW89_PKT_OFLD_TYPE_NDP = 6, 765 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 766 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 767 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 768 RTW89_PKT_OFLD_TYPE_NUM, 769 }; 770 771 struct rtw89_txpwr_byrate { 772 s8 cck[RTW89_RATE_CCK_NUM]; 773 s8 ofdm[RTW89_RATE_OFDM_NUM]; 774 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 775 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 776 s8 offset[__RTW89_RATE_OFFSET_NUM]; 777 s8 trap; 778 }; 779 780 struct rtw89_rate_desc { 781 enum rtw89_nss nss; 782 enum rtw89_rate_section rs; 783 enum rtw89_ofdma_type ofdma; 784 u8 idx; 785 }; 786 787 #define PHY_STS_HDR_LEN 8 788 #define RF_PATH_MAX 4 789 #define RTW89_MAX_PPDU_CNT 8 790 struct rtw89_rx_phy_ppdu { 791 void *buf; 792 u32 len; 793 u8 rssi_avg; 794 u8 rssi[RF_PATH_MAX]; 795 u8 mac_id; 796 u8 chan_idx; 797 u8 ie; 798 u16 rate; 799 struct { 800 bool has; 801 u8 avg_snr; 802 u8 evm_max; 803 u8 evm_min; 804 } ofdm; 805 bool has_data; 806 bool has_bcn; 807 bool ldpc; 808 bool stbc; 809 bool to_self; 810 bool valid; 811 }; 812 813 enum rtw89_mac_idx { 814 RTW89_MAC_0 = 0, 815 RTW89_MAC_1 = 1, 816 RTW89_MAC_NUM, 817 }; 818 819 enum rtw89_phy_idx { 820 RTW89_PHY_0 = 0, 821 RTW89_PHY_1 = 1, 822 RTW89_PHY_MAX 823 }; 824 825 enum rtw89_chanctx_idx { 826 RTW89_CHANCTX_0 = 0, 827 RTW89_CHANCTX_1 = 1, 828 829 NUM_OF_RTW89_CHANCTX, 830 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 831 }; 832 833 enum rtw89_rf_path { 834 RF_PATH_A = 0, 835 RF_PATH_B = 1, 836 RF_PATH_C = 2, 837 RF_PATH_D = 3, 838 RF_PATH_AB, 839 RF_PATH_AC, 840 RF_PATH_AD, 841 RF_PATH_BC, 842 RF_PATH_BD, 843 RF_PATH_CD, 844 RF_PATH_ABC, 845 RF_PATH_ABD, 846 RF_PATH_ACD, 847 RF_PATH_BCD, 848 RF_PATH_ABCD, 849 }; 850 851 enum rtw89_rf_path_bit { 852 RF_A = BIT(0), 853 RF_B = BIT(1), 854 RF_C = BIT(2), 855 RF_D = BIT(3), 856 857 RF_AB = (RF_A | RF_B), 858 RF_AC = (RF_A | RF_C), 859 RF_AD = (RF_A | RF_D), 860 RF_BC = (RF_B | RF_C), 861 RF_BD = (RF_B | RF_D), 862 RF_CD = (RF_C | RF_D), 863 864 RF_ABC = (RF_A | RF_B | RF_C), 865 RF_ABD = (RF_A | RF_B | RF_D), 866 RF_ACD = (RF_A | RF_C | RF_D), 867 RF_BCD = (RF_B | RF_C | RF_D), 868 869 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 870 }; 871 872 enum rtw89_bandwidth { 873 RTW89_CHANNEL_WIDTH_20 = 0, 874 RTW89_CHANNEL_WIDTH_40 = 1, 875 RTW89_CHANNEL_WIDTH_80 = 2, 876 RTW89_CHANNEL_WIDTH_160 = 3, 877 RTW89_CHANNEL_WIDTH_320 = 4, 878 879 /* keep index order above */ 880 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 881 882 RTW89_CHANNEL_WIDTH_80_80 = 5, 883 RTW89_CHANNEL_WIDTH_5 = 6, 884 RTW89_CHANNEL_WIDTH_10 = 7, 885 }; 886 887 enum rtw89_ps_mode { 888 RTW89_PS_MODE_NONE = 0, 889 RTW89_PS_MODE_RFOFF = 1, 890 RTW89_PS_MODE_CLK_GATED = 2, 891 RTW89_PS_MODE_PWR_GATED = 3, 892 }; 893 894 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 895 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 896 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 897 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 898 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 899 900 enum rtw89_pe_duration { 901 RTW89_PE_DURATION_0 = 0, 902 RTW89_PE_DURATION_8 = 1, 903 RTW89_PE_DURATION_16 = 2, 904 RTW89_PE_DURATION_16_20 = 3, 905 }; 906 907 enum rtw89_ru_bandwidth { 908 RTW89_RU26 = 0, 909 RTW89_RU52 = 1, 910 RTW89_RU106 = 2, 911 RTW89_RU52_26 = 3, 912 RTW89_RU106_26 = 4, 913 RTW89_RU_NUM, 914 }; 915 916 enum rtw89_sc_offset { 917 RTW89_SC_DONT_CARE = 0, 918 RTW89_SC_20_UPPER = 1, 919 RTW89_SC_20_LOWER = 2, 920 RTW89_SC_20_UPMOST = 3, 921 RTW89_SC_20_LOWEST = 4, 922 RTW89_SC_20_UP2X = 5, 923 RTW89_SC_20_LOW2X = 6, 924 RTW89_SC_20_UP3X = 7, 925 RTW89_SC_20_LOW3X = 8, 926 RTW89_SC_40_UPPER = 9, 927 RTW89_SC_40_LOWER = 10, 928 }; 929 930 /* only mgd features can be added to the enum */ 931 enum rtw89_wow_flags { 932 RTW89_WOW_FLAG_EN_MAGIC_PKT, 933 RTW89_WOW_FLAG_EN_REKEY_PKT, 934 RTW89_WOW_FLAG_EN_DISCONNECT, 935 RTW89_WOW_FLAG_EN_PATTERN, 936 RTW89_WOW_FLAG_NUM, 937 }; 938 939 struct rtw89_chan { 940 u8 channel; 941 u8 primary_channel; 942 enum rtw89_band band_type; 943 enum rtw89_bandwidth band_width; 944 945 /* The follow-up are derived from the above. We must ensure that it 946 * is assigned correctly in rtw89_chan_create() if new one is added. 947 */ 948 u32 freq; 949 enum rtw89_subband subband_type; 950 enum rtw89_sc_offset pri_ch_idx; 951 u8 pri_sb_idx; 952 }; 953 954 struct rtw89_chan_rcd { 955 u8 prev_primary_channel; 956 enum rtw89_band prev_band_type; 957 bool band_changed; 958 }; 959 960 struct rtw89_channel_help_params { 961 u32 tx_en; 962 }; 963 964 struct rtw89_port_reg { 965 u32 port_cfg; 966 u32 tbtt_prohib; 967 u32 bcn_area; 968 u32 bcn_early; 969 u32 tbtt_early; 970 u32 tbtt_agg; 971 u32 bcn_space; 972 u32 bcn_forcetx; 973 u32 bcn_err_cnt; 974 u32 bcn_err_flag; 975 u32 dtim_ctrl; 976 u32 tbtt_shift; 977 u32 bcn_cnt_tmr; 978 u32 tsftr_l; 979 u32 tsftr_h; 980 u32 md_tsft; 981 u32 bss_color; 982 u32 mbssid; 983 u32 mbssid_drop; 984 u32 tsf_sync; 985 u32 ptcl_dbg; 986 u32 ptcl_dbg_info; 987 u32 bcn_drop_all; 988 u32 hiq_win[RTW89_PORT_NUM]; 989 }; 990 991 struct rtw89_txwd_body { 992 __le32 dword0; 993 __le32 dword1; 994 __le32 dword2; 995 __le32 dword3; 996 __le32 dword4; 997 __le32 dword5; 998 } __packed; 999 1000 struct rtw89_txwd_body_v1 { 1001 __le32 dword0; 1002 __le32 dword1; 1003 __le32 dword2; 1004 __le32 dword3; 1005 __le32 dword4; 1006 __le32 dword5; 1007 __le32 dword6; 1008 __le32 dword7; 1009 } __packed; 1010 1011 struct rtw89_txwd_body_v2 { 1012 __le32 dword0; 1013 __le32 dword1; 1014 __le32 dword2; 1015 __le32 dword3; 1016 __le32 dword4; 1017 __le32 dword5; 1018 __le32 dword6; 1019 __le32 dword7; 1020 } __packed; 1021 1022 struct rtw89_txwd_info { 1023 __le32 dword0; 1024 __le32 dword1; 1025 __le32 dword2; 1026 __le32 dword3; 1027 __le32 dword4; 1028 __le32 dword5; 1029 } __packed; 1030 1031 struct rtw89_txwd_info_v2 { 1032 __le32 dword0; 1033 __le32 dword1; 1034 __le32 dword2; 1035 __le32 dword3; 1036 __le32 dword4; 1037 __le32 dword5; 1038 __le32 dword6; 1039 __le32 dword7; 1040 } __packed; 1041 1042 struct rtw89_rx_desc_info { 1043 u16 pkt_size; 1044 u8 pkt_type; 1045 u8 drv_info_size; 1046 u8 phy_rpt_size; 1047 u8 hdr_cnv_size; 1048 u8 shift; 1049 u8 wl_hd_iv_len; 1050 bool long_rxdesc; 1051 bool bb_sel; 1052 bool mac_info_valid; 1053 u16 data_rate; 1054 u8 gi_ltf; 1055 u8 bw; 1056 u32 free_run_cnt; 1057 u8 user_id; 1058 bool sr_en; 1059 u8 ppdu_cnt; 1060 u8 ppdu_type; 1061 bool icv_err; 1062 bool crc32_err; 1063 bool hw_dec; 1064 bool sw_dec; 1065 bool addr1_match; 1066 u8 frag; 1067 u16 seq; 1068 u8 frame_type; 1069 u8 rx_pl_id; 1070 bool addr_cam_valid; 1071 u8 addr_cam_id; 1072 u8 sec_cam_id; 1073 u8 mac_id; 1074 u16 offset; 1075 u16 rxd_len; 1076 bool ready; 1077 }; 1078 1079 struct rtw89_rxdesc_short { 1080 __le32 dword0; 1081 __le32 dword1; 1082 __le32 dword2; 1083 __le32 dword3; 1084 } __packed; 1085 1086 struct rtw89_rxdesc_short_v2 { 1087 __le32 dword0; 1088 __le32 dword1; 1089 __le32 dword2; 1090 __le32 dword3; 1091 __le32 dword4; 1092 __le32 dword5; 1093 } __packed; 1094 1095 struct rtw89_rxdesc_long { 1096 __le32 dword0; 1097 __le32 dword1; 1098 __le32 dword2; 1099 __le32 dword3; 1100 __le32 dword4; 1101 __le32 dword5; 1102 __le32 dword6; 1103 __le32 dword7; 1104 } __packed; 1105 1106 struct rtw89_rxdesc_long_v2 { 1107 __le32 dword0; 1108 __le32 dword1; 1109 __le32 dword2; 1110 __le32 dword3; 1111 __le32 dword4; 1112 __le32 dword5; 1113 __le32 dword6; 1114 __le32 dword7; 1115 __le32 dword8; 1116 __le32 dword9; 1117 } __packed; 1118 1119 struct rtw89_tx_desc_info { 1120 u16 pkt_size; 1121 u8 wp_offset; 1122 u8 mac_id; 1123 u8 qsel; 1124 u8 ch_dma; 1125 u8 hdr_llc_len; 1126 bool is_bmc; 1127 bool en_wd_info; 1128 bool wd_page; 1129 bool use_rate; 1130 bool dis_data_fb; 1131 bool tid_indicate; 1132 bool agg_en; 1133 bool bk; 1134 u8 ampdu_density; 1135 u8 ampdu_num; 1136 bool sec_en; 1137 u8 addr_info_nr; 1138 u8 sec_keyid; 1139 u8 sec_type; 1140 u8 sec_cam_idx; 1141 u8 sec_seq[6]; 1142 u16 data_rate; 1143 u16 data_retry_lowest_rate; 1144 bool fw_dl; 1145 u16 seq; 1146 bool a_ctrl_bsr; 1147 u8 hw_ssn_sel; 1148 #define RTW89_MGMT_HW_SSN_SEL 1 1149 u8 hw_seq_mode; 1150 #define RTW89_MGMT_HW_SEQ_MODE 1 1151 bool hiq; 1152 u8 port; 1153 bool er_cap; 1154 bool stbc; 1155 bool ldpc; 1156 }; 1157 1158 struct rtw89_core_tx_request { 1159 enum rtw89_core_tx_type tx_type; 1160 1161 struct sk_buff *skb; 1162 struct ieee80211_vif *vif; 1163 struct ieee80211_sta *sta; 1164 struct rtw89_tx_desc_info desc_info; 1165 }; 1166 1167 struct rtw89_txq { 1168 struct list_head list; 1169 unsigned long flags; 1170 int wait_cnt; 1171 }; 1172 1173 struct rtw89_mac_ax_gnt { 1174 u8 gnt_bt_sw_en; 1175 u8 gnt_bt; 1176 u8 gnt_wl_sw_en; 1177 u8 gnt_wl; 1178 } __packed; 1179 1180 struct rtw89_mac_ax_wl_act { 1181 u8 wlan_act_en; 1182 u8 wlan_act; 1183 }; 1184 1185 #define RTW89_MAC_AX_COEX_GNT_NR 2 1186 struct rtw89_mac_ax_coex_gnt { 1187 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1188 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1189 }; 1190 1191 enum rtw89_btc_ncnt { 1192 BTC_NCNT_POWER_ON = 0x0, 1193 BTC_NCNT_POWER_OFF, 1194 BTC_NCNT_INIT_COEX, 1195 BTC_NCNT_SCAN_START, 1196 BTC_NCNT_SCAN_FINISH, 1197 BTC_NCNT_SPECIAL_PACKET, 1198 BTC_NCNT_SWITCH_BAND, 1199 BTC_NCNT_RFK_TIMEOUT, 1200 BTC_NCNT_SHOW_COEX_INFO, 1201 BTC_NCNT_ROLE_INFO, 1202 BTC_NCNT_CONTROL, 1203 BTC_NCNT_RADIO_STATE, 1204 BTC_NCNT_CUSTOMERIZE, 1205 BTC_NCNT_WL_RFK, 1206 BTC_NCNT_WL_STA, 1207 BTC_NCNT_WL_STA_LAST, 1208 BTC_NCNT_FWINFO, 1209 BTC_NCNT_TIMER, 1210 BTC_NCNT_SWITCH_CHBW, 1211 BTC_NCNT_RESUME_DL_FW, 1212 BTC_NCNT_COUNTRYCODE, 1213 BTC_NCNT_NUM, 1214 }; 1215 1216 enum rtw89_btc_btinfo { 1217 BTC_BTINFO_L0 = 0, 1218 BTC_BTINFO_L1, 1219 BTC_BTINFO_L2, 1220 BTC_BTINFO_L3, 1221 BTC_BTINFO_H0, 1222 BTC_BTINFO_H1, 1223 BTC_BTINFO_H2, 1224 BTC_BTINFO_H3, 1225 BTC_BTINFO_MAX 1226 }; 1227 1228 enum rtw89_btc_dcnt { 1229 BTC_DCNT_RUN = 0x0, 1230 BTC_DCNT_CX_RUNINFO, 1231 BTC_DCNT_RPT, 1232 BTC_DCNT_RPT_HANG, 1233 BTC_DCNT_CYCLE, 1234 BTC_DCNT_CYCLE_HANG, 1235 BTC_DCNT_W1, 1236 BTC_DCNT_W1_HANG, 1237 BTC_DCNT_B1, 1238 BTC_DCNT_B1_HANG, 1239 BTC_DCNT_TDMA_NONSYNC, 1240 BTC_DCNT_SLOT_NONSYNC, 1241 BTC_DCNT_BTCNT_HANG, 1242 BTC_DCNT_BTTX_HANG, 1243 BTC_DCNT_WL_SLOT_DRIFT, 1244 BTC_DCNT_WL_STA_LAST, 1245 BTC_DCNT_BT_SLOT_DRIFT, 1246 BTC_DCNT_BT_SLOT_FLOOD, 1247 BTC_DCNT_FDDT_TRIG, 1248 BTC_DCNT_E2G, 1249 BTC_DCNT_E2G_HANG, 1250 BTC_DCNT_WL_FW_VER_MATCH, 1251 BTC_DCNT_NULL_TX_FAIL, 1252 BTC_DCNT_WL_STA_NTFY, 1253 BTC_DCNT_NUM, 1254 }; 1255 1256 enum rtw89_btc_wl_state_cnt { 1257 BTC_WCNT_SCANAP = 0x0, 1258 BTC_WCNT_DHCP, 1259 BTC_WCNT_EAPOL, 1260 BTC_WCNT_ARP, 1261 BTC_WCNT_SCBDUPDATE, 1262 BTC_WCNT_RFK_REQ, 1263 BTC_WCNT_RFK_GO, 1264 BTC_WCNT_RFK_REJECT, 1265 BTC_WCNT_RFK_TIMEOUT, 1266 BTC_WCNT_CH_UPDATE, 1267 BTC_WCNT_DBCC_ALL_2G, 1268 BTC_WCNT_DBCC_CHG, 1269 BTC_WCNT_RX_OK_LAST, 1270 BTC_WCNT_RX_OK_LAST2S, 1271 BTC_WCNT_RX_ERR_LAST, 1272 BTC_WCNT_RX_ERR_LAST2S, 1273 BTC_WCNT_RX_LAST, 1274 BTC_WCNT_NUM 1275 }; 1276 1277 enum rtw89_btc_bt_state_cnt { 1278 BTC_BCNT_RETRY = 0x0, 1279 BTC_BCNT_REINIT, 1280 BTC_BCNT_REENABLE, 1281 BTC_BCNT_SCBDREAD, 1282 BTC_BCNT_RELINK, 1283 BTC_BCNT_IGNOWL, 1284 BTC_BCNT_INQPAG, 1285 BTC_BCNT_INQ, 1286 BTC_BCNT_PAGE, 1287 BTC_BCNT_ROLESW, 1288 BTC_BCNT_AFH, 1289 BTC_BCNT_INFOUPDATE, 1290 BTC_BCNT_INFOSAME, 1291 BTC_BCNT_SCBDUPDATE, 1292 BTC_BCNT_HIPRI_TX, 1293 BTC_BCNT_HIPRI_RX, 1294 BTC_BCNT_LOPRI_TX, 1295 BTC_BCNT_LOPRI_RX, 1296 BTC_BCNT_POLUT, 1297 BTC_BCNT_POLUT_NOW, 1298 BTC_BCNT_POLUT_DIFF, 1299 BTC_BCNT_RATECHG, 1300 BTC_BCNT_NUM, 1301 }; 1302 1303 enum rtw89_btc_bt_profile { 1304 BTC_BT_NOPROFILE = 0, 1305 BTC_BT_HFP = BIT(0), 1306 BTC_BT_HID = BIT(1), 1307 BTC_BT_A2DP = BIT(2), 1308 BTC_BT_PAN = BIT(3), 1309 BTC_PROFILE_MAX = 4, 1310 }; 1311 1312 struct rtw89_btc_ant_info { 1313 u8 type; /* shared, dedicated */ 1314 u8 num; 1315 u8 isolation; 1316 1317 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1318 u8 diversity: 1; 1319 u8 btg_pos: 2; 1320 u8 stream_cnt: 4; 1321 }; 1322 1323 struct rtw89_btc_ant_info_v7 { 1324 u8 type; /* shared, dedicated(non-shared) */ 1325 u8 num; /* antenna count */ 1326 u8 isolation; 1327 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1328 1329 u8 diversity; /* only for wifi use 1-antenna */ 1330 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1331 u8 stream_cnt; /* spatial_stream count */ 1332 u8 rsvd; 1333 } __packed; 1334 1335 enum rtw89_tfc_dir { 1336 RTW89_TFC_UL, 1337 RTW89_TFC_DL, 1338 }; 1339 1340 struct rtw89_btc_wl_smap { 1341 u32 busy: 1; 1342 u32 scan: 1; 1343 u32 connecting: 1; 1344 u32 roaming: 1; 1345 u32 dbccing: 1; 1346 u32 transacting: 1; 1347 u32 _4way: 1; 1348 u32 rf_off: 1; 1349 u32 lps: 2; 1350 u32 ips: 1; 1351 u32 init_ok: 1; 1352 u32 traffic_dir : 2; 1353 u32 rf_off_pre: 1; 1354 u32 lps_pre: 2; 1355 u32 lps_exiting: 1; 1356 u32 emlsr: 1; 1357 }; 1358 1359 enum rtw89_tfc_lv { 1360 RTW89_TFC_IDLE, 1361 RTW89_TFC_ULTRA_LOW, 1362 RTW89_TFC_LOW, 1363 RTW89_TFC_MID, 1364 RTW89_TFC_HIGH, 1365 }; 1366 1367 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1368 DECLARE_EWMA(tp, 10, 2); 1369 1370 struct rtw89_traffic_stats { 1371 /* units in bytes */ 1372 u64 tx_unicast; 1373 u64 rx_unicast; 1374 u32 tx_avg_len; 1375 u32 rx_avg_len; 1376 1377 /* count for packets */ 1378 u64 tx_cnt; 1379 u64 rx_cnt; 1380 1381 /* units in Mbps */ 1382 u32 tx_throughput; 1383 u32 rx_throughput; 1384 u32 tx_throughput_raw; 1385 u32 rx_throughput_raw; 1386 1387 u32 rx_tf_acc; 1388 u32 rx_tf_periodic; 1389 1390 enum rtw89_tfc_lv tx_tfc_lv; 1391 enum rtw89_tfc_lv rx_tfc_lv; 1392 struct ewma_tp tx_ewma_tp; 1393 struct ewma_tp rx_ewma_tp; 1394 1395 u16 tx_rate; 1396 u16 rx_rate; 1397 }; 1398 1399 struct rtw89_btc_chdef { 1400 u8 center_ch; 1401 u8 band; 1402 u8 chan; 1403 enum rtw89_sc_offset offset; 1404 enum rtw89_bandwidth bw; 1405 }; 1406 1407 struct rtw89_btc_statistic { 1408 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1409 struct rtw89_traffic_stats traffic; 1410 }; 1411 1412 #define BTC_WL_RSSI_THMAX 4 1413 1414 struct rtw89_btc_wl_link_info { 1415 struct rtw89_btc_chdef chdef; 1416 struct rtw89_btc_statistic stat; 1417 enum rtw89_tfc_dir dir; 1418 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1419 u8 mac_addr[ETH_ALEN]; 1420 u8 busy; 1421 u8 ch; 1422 u8 bw; 1423 u8 band; 1424 u8 role; 1425 u8 pid; 1426 u8 phy; 1427 u8 dtim_period; 1428 u8 mode; 1429 u8 tx_1ss_limit; 1430 1431 u8 mac_id; 1432 u8 tx_retry; 1433 1434 u32 bcn_period; 1435 u32 busy_t; 1436 u32 tx_time; 1437 u32 client_cnt; 1438 u32 rx_rate_drop_cnt; 1439 u32 noa_duration; 1440 1441 u32 active: 1; 1442 u32 noa: 1; 1443 u32 client_ps: 1; 1444 u32 connected: 2; 1445 }; 1446 1447 union rtw89_btc_wl_state_map { 1448 u32 val; 1449 struct rtw89_btc_wl_smap map; 1450 }; 1451 1452 struct rtw89_btc_bt_hfp_desc { 1453 u32 exist: 1; 1454 u32 type: 2; 1455 u32 rsvd: 29; 1456 }; 1457 1458 struct rtw89_btc_bt_hid_desc { 1459 u32 exist: 1; 1460 u32 slot_info: 2; 1461 u32 pair_cnt: 2; 1462 u32 type: 8; 1463 u32 rsvd: 19; 1464 }; 1465 1466 struct rtw89_btc_bt_a2dp_desc { 1467 u8 exist: 1; 1468 u8 exist_last: 1; 1469 u8 play_latency: 1; 1470 u8 type: 3; 1471 u8 active: 1; 1472 u8 sink: 1; 1473 u32 handle_update: 1; 1474 u32 devinfo_query: 1; 1475 u32 no_empty_streak_2s: 8; 1476 u32 no_empty_streak_max: 8; 1477 u32 rsvd: 6; 1478 1479 u8 bitpool; 1480 u16 vendor_id; 1481 u32 device_name; 1482 u32 flush_time; 1483 }; 1484 1485 struct rtw89_btc_bt_pan_desc { 1486 u32 exist: 1; 1487 u32 type: 1; 1488 u32 active: 1; 1489 u32 rsvd: 29; 1490 }; 1491 1492 struct rtw89_btc_bt_rfk_info { 1493 u32 run: 1; 1494 u32 req: 1; 1495 u32 timeout: 1; 1496 u32 rsvd: 29; 1497 }; 1498 1499 union rtw89_btc_bt_rfk_info_map { 1500 u32 val; 1501 struct rtw89_btc_bt_rfk_info map; 1502 }; 1503 1504 struct rtw89_btc_bt_ver_info { 1505 u32 fw_coex; /* match with which coex_ver */ 1506 u32 fw; 1507 }; 1508 1509 struct rtw89_btc_bool_sta_chg { 1510 u32 now: 1; 1511 u32 last: 1; 1512 u32 remain: 1; 1513 u32 srvd: 29; 1514 }; 1515 1516 struct rtw89_btc_u8_sta_chg { 1517 u8 now; 1518 u8 last; 1519 u8 remain; 1520 u8 rsvd; 1521 }; 1522 1523 struct rtw89_btc_wl_scan_info { 1524 u8 band[RTW89_PHY_MAX]; 1525 u8 phy_map; 1526 u8 rsvd; 1527 }; 1528 1529 struct rtw89_btc_wl_dbcc_info { 1530 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1531 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1532 u8 real_band[RTW89_PHY_MAX]; 1533 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1534 }; 1535 1536 struct rtw89_btc_wl_active_role { 1537 u8 connected: 1; 1538 u8 pid: 3; 1539 u8 phy: 1; 1540 u8 noa: 1; 1541 u8 band: 2; 1542 1543 u8 client_ps: 1; 1544 u8 bw: 7; 1545 1546 u8 role; 1547 u8 ch; 1548 1549 u16 tx_lvl; 1550 u16 rx_lvl; 1551 u16 tx_rate; 1552 u16 rx_rate; 1553 }; 1554 1555 struct rtw89_btc_wl_active_role_v1 { 1556 u8 connected: 1; 1557 u8 pid: 3; 1558 u8 phy: 1; 1559 u8 noa: 1; 1560 u8 band: 2; 1561 1562 u8 client_ps: 1; 1563 u8 bw: 7; 1564 1565 u8 role; 1566 u8 ch; 1567 1568 u16 tx_lvl; 1569 u16 rx_lvl; 1570 u16 tx_rate; 1571 u16 rx_rate; 1572 1573 u32 noa_duration; /* ms */ 1574 }; 1575 1576 struct rtw89_btc_wl_active_role_v2 { 1577 u8 connected: 1; 1578 u8 pid: 3; 1579 u8 phy: 1; 1580 u8 noa: 1; 1581 u8 band: 2; 1582 1583 u8 client_ps: 1; 1584 u8 bw: 7; 1585 1586 u8 role; 1587 u8 ch; 1588 1589 u32 noa_duration; /* ms */ 1590 }; 1591 1592 struct rtw89_btc_wl_role_info_bpos { 1593 u16 none: 1; 1594 u16 station: 1; 1595 u16 ap: 1; 1596 u16 vap: 1; 1597 u16 adhoc: 1; 1598 u16 adhoc_master: 1; 1599 u16 mesh: 1; 1600 u16 moniter: 1; 1601 u16 p2p_device: 1; 1602 u16 p2p_gc: 1; 1603 u16 p2p_go: 1; 1604 u16 nan: 1; 1605 }; 1606 1607 struct rtw89_btc_wl_scc_ctrl { 1608 u8 null_role1; 1609 u8 null_role2; 1610 u8 ebt_null; /* if tx null at EBT slot */ 1611 }; 1612 1613 union rtw89_btc_wl_role_info_map { 1614 u16 val; 1615 struct rtw89_btc_wl_role_info_bpos role; 1616 }; 1617 1618 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1619 u8 connect_cnt; 1620 u8 link_mode; 1621 union rtw89_btc_wl_role_info_map role_map; 1622 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1623 }; 1624 1625 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1626 u8 connect_cnt; 1627 u8 link_mode; 1628 union rtw89_btc_wl_role_info_map role_map; 1629 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1630 u32 mrole_type; /* btc_wl_mrole_type */ 1631 u32 mrole_noa_duration; /* ms */ 1632 1633 u32 dbcc_en: 1; 1634 u32 dbcc_chg: 1; 1635 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1636 u32 link_mode_chg: 1; 1637 u32 rsvd: 27; 1638 }; 1639 1640 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1641 u8 connect_cnt; 1642 u8 link_mode; 1643 union rtw89_btc_wl_role_info_map role_map; 1644 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1645 u32 mrole_type; /* btc_wl_mrole_type */ 1646 u32 mrole_noa_duration; /* ms */ 1647 1648 u32 dbcc_en: 1; 1649 u32 dbcc_chg: 1; 1650 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1651 u32 link_mode_chg: 1; 1652 u32 rsvd: 27; 1653 }; 1654 1655 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1656 u8 connected; 1657 u8 pid; 1658 u8 phy; 1659 u8 noa; 1660 1661 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1662 u8 active; /* 0:rlink is under doze */ 1663 u8 bw; /* enum channel_width */ 1664 u8 role; /*enum role_type */ 1665 1666 u8 ch; 1667 u8 noa_dur; /* ms */ 1668 u8 client_cnt; /* for Role = P2P-Go/AP */ 1669 u8 mode; /* wifi protocol */ 1670 } __packed; 1671 1672 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1673 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1674 u8 connect_cnt; 1675 u8 link_mode; 1676 u8 link_mode_chg; 1677 u8 p2p_2g; 1678 1679 u8 pta_req_band; 1680 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1681 u8 dbcc_chg; 1682 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1683 1684 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1685 1686 u32 role_map; 1687 u32 mrole_type; /* btc_wl_mrole_type */ 1688 u32 mrole_noa_duration; /* ms */ 1689 } __packed; 1690 1691 struct rtw89_btc_wl_ver_info { 1692 u32 fw_coex; /* match with which coex_ver */ 1693 u32 fw; 1694 u32 mac; 1695 u32 bb; 1696 u32 rf; 1697 }; 1698 1699 struct rtw89_btc_wl_afh_info { 1700 u8 en; 1701 u8 ch; 1702 u8 bw; 1703 u8 rsvd; 1704 } __packed; 1705 1706 struct rtw89_btc_wl_rfk_info { 1707 u32 state: 2; 1708 u32 path_map: 4; 1709 u32 phy_map: 2; 1710 u32 band: 2; 1711 u32 type: 8; 1712 u32 rsvd: 14; 1713 1714 u32 start_time; 1715 u32 proc_time; 1716 }; 1717 1718 struct rtw89_btc_bt_smap { 1719 u32 connect: 1; 1720 u32 ble_connect: 1; 1721 u32 acl_busy: 1; 1722 u32 sco_busy: 1; 1723 u32 mesh_busy: 1; 1724 u32 inq_pag: 1; 1725 }; 1726 1727 union rtw89_btc_bt_state_map { 1728 u32 val; 1729 struct rtw89_btc_bt_smap map; 1730 }; 1731 1732 #define BTC_BT_RSSI_THMAX 4 1733 #define BTC_BT_AFH_GROUP 12 1734 #define BTC_BT_AFH_LE_GROUP 5 1735 1736 struct rtw89_btc_bt_link_info { 1737 struct rtw89_btc_u8_sta_chg profile_cnt; 1738 struct rtw89_btc_bool_sta_chg multi_link; 1739 struct rtw89_btc_bool_sta_chg relink; 1740 struct rtw89_btc_bt_hfp_desc hfp_desc; 1741 struct rtw89_btc_bt_hid_desc hid_desc; 1742 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1743 struct rtw89_btc_bt_pan_desc pan_desc; 1744 union rtw89_btc_bt_state_map status; 1745 1746 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1747 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1748 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1749 u8 afh_map[BTC_BT_AFH_GROUP]; 1750 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1751 1752 u32 role_sw: 1; 1753 u32 slave_role: 1; 1754 u32 afh_update: 1; 1755 u32 cqddr: 1; 1756 u32 rssi: 8; 1757 u32 tx_3m: 1; 1758 u32 rsvd: 19; 1759 }; 1760 1761 struct rtw89_btc_3rdcx_info { 1762 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1763 u8 hw_coex; 1764 u16 rsvd; 1765 }; 1766 1767 struct rtw89_btc_dm_emap { 1768 u32 init: 1; 1769 u32 pta_owner: 1; 1770 u32 wl_rfk_timeout: 1; 1771 u32 bt_rfk_timeout: 1; 1772 u32 wl_fw_hang: 1; 1773 u32 cycle_hang: 1; 1774 u32 w1_hang: 1; 1775 u32 b1_hang: 1; 1776 u32 tdma_no_sync: 1; 1777 u32 slot_no_sync: 1; 1778 u32 wl_slot_drift: 1; 1779 u32 bt_slot_drift: 1; 1780 u32 role_num_mismatch: 1; 1781 u32 null1_tx_late: 1; 1782 u32 bt_afh_conflict: 1; 1783 u32 bt_leafh_conflict: 1; 1784 u32 bt_slot_flood: 1; 1785 u32 wl_e2g_hang: 1; 1786 u32 wl_ver_mismatch: 1; 1787 u32 bt_ver_mismatch: 1; 1788 u32 rfe_type0: 1; 1789 u32 h2c_buffer_over: 1; 1790 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1791 u32 wl_no_sta_ntfy: 1; 1792 1793 u32 h2c_bmap_mismatch: 1; 1794 u32 c2h_bmap_mismatch: 1; 1795 u32 h2c_struct_invalid: 1; 1796 u32 c2h_struct_invalid: 1; 1797 u32 h2c_c2h_buffer_mismatch: 1; 1798 }; 1799 1800 union rtw89_btc_dm_error_map { 1801 u32 val; 1802 struct rtw89_btc_dm_emap map; 1803 }; 1804 1805 struct rtw89_btc_rf_para { 1806 u32 tx_pwr_freerun; 1807 u32 rx_gain_freerun; 1808 u32 tx_pwr_perpkt; 1809 u32 rx_gain_perpkt; 1810 }; 1811 1812 struct rtw89_btc_wl_nhm { 1813 u8 instant_wl_nhm_dbm; 1814 u8 instant_wl_nhm_per_mhz; 1815 u16 valid_record_times; 1816 s8 record_pwr[16]; 1817 u8 record_ratio[16]; 1818 s8 pwr; /* dbm_per_MHz */ 1819 u8 ratio; 1820 u8 current_status; 1821 u8 refresh; 1822 bool start_flag; 1823 s8 pwr_max; 1824 s8 pwr_min; 1825 }; 1826 1827 struct rtw89_btc_wl_info { 1828 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1829 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1830 struct rtw89_btc_wl_rfk_info rfk_info; 1831 struct rtw89_btc_wl_ver_info ver_info; 1832 struct rtw89_btc_wl_afh_info afh_info; 1833 struct rtw89_btc_wl_role_info role_info; 1834 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1835 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1836 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1837 struct rtw89_btc_wl_scan_info scan_info; 1838 struct rtw89_btc_wl_dbcc_info dbcc_info; 1839 struct rtw89_btc_rf_para rf_para; 1840 struct rtw89_btc_wl_nhm nhm; 1841 union rtw89_btc_wl_state_map status; 1842 1843 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1844 u8 rssi_level; 1845 u8 cn_report; 1846 u8 coex_mode; 1847 u8 pta_req_mac; 1848 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */ 1849 1850 bool is_5g_hi_channel; 1851 bool pta_reg_mac_chg; 1852 bool bg_mode; 1853 bool scbd_change; 1854 bool fw_ver_mismatch; 1855 u32 scbd; 1856 }; 1857 1858 struct rtw89_btc_module { 1859 struct rtw89_btc_ant_info ant; 1860 u8 rfe_type; 1861 u8 cv; 1862 1863 u8 bt_solo: 1; 1864 u8 bt_pos: 1; 1865 u8 switch_type: 1; 1866 u8 wa_type: 3; 1867 1868 u8 kt_ver_adie; 1869 }; 1870 1871 struct rtw89_btc_module_v7 { 1872 u8 rfe_type; 1873 u8 kt_ver; 1874 u8 bt_solo; 1875 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1876 1877 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1878 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1879 u8 kt_ver_adie; 1880 u8 rsvd; 1881 1882 struct rtw89_btc_ant_info_v7 ant; 1883 } __packed; 1884 1885 union rtw89_btc_module_info { 1886 struct rtw89_btc_module md; 1887 struct rtw89_btc_module_v7 md_v7; 1888 }; 1889 1890 #define RTW89_BTC_DM_MAXSTEP 30 1891 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1892 1893 struct rtw89_btc_dm_step { 1894 u16 step[RTW89_BTC_DM_MAXSTEP]; 1895 u8 step_pos; 1896 bool step_ov; 1897 }; 1898 1899 struct rtw89_btc_init_info { 1900 struct rtw89_btc_module module; 1901 u8 wl_guard_ch; 1902 1903 u8 wl_only: 1; 1904 u8 wl_init_ok: 1; 1905 u8 dbcc_en: 1; 1906 u8 cx_other: 1; 1907 u8 bt_only: 1; 1908 1909 u16 rsvd; 1910 }; 1911 1912 struct rtw89_btc_init_info_v7 { 1913 u8 wl_guard_ch; 1914 u8 wl_only; 1915 u8 wl_init_ok; 1916 u8 rsvd3; 1917 1918 u8 cx_other; 1919 u8 bt_only; 1920 u8 pta_mode; 1921 u8 pta_direction; 1922 1923 struct rtw89_btc_module_v7 module; 1924 } __packed; 1925 1926 union rtw89_btc_init_info_u { 1927 struct rtw89_btc_init_info init; 1928 struct rtw89_btc_init_info_v7 init_v7; 1929 }; 1930 1931 struct rtw89_btc_wl_tx_limit_para { 1932 u16 enable; 1933 u32 tx_time; /* unit: us */ 1934 u16 tx_retry; 1935 }; 1936 1937 enum rtw89_btc_bt_scan_type { 1938 BTC_SCAN_INQ = 0, 1939 BTC_SCAN_PAGE, 1940 BTC_SCAN_BLE, 1941 BTC_SCAN_INIT, 1942 BTC_SCAN_TV, 1943 BTC_SCAN_ADV, 1944 BTC_SCAN_MAX1, 1945 }; 1946 1947 enum rtw89_btc_ble_scan_type { 1948 CXSCAN_BG = 0, 1949 CXSCAN_INIT, 1950 CXSCAN_LE, 1951 CXSCAN_MAX 1952 }; 1953 1954 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1955 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1956 1957 struct rtw89_btc_bt_scan_info_v1 { 1958 __le16 win; 1959 __le16 intvl; 1960 __le32 flags; 1961 } __packed; 1962 1963 struct rtw89_btc_bt_scan_info_v2 { 1964 __le16 win; 1965 __le16 intvl; 1966 } __packed; 1967 1968 struct rtw89_btc_fbtc_btscan_v1 { 1969 u8 fver; /* btc_ver::fcxbtscan */ 1970 u8 rsvd; 1971 __le16 rsvd2; 1972 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1973 } __packed; 1974 1975 struct rtw89_btc_fbtc_btscan_v2 { 1976 u8 fver; /* btc_ver::fcxbtscan */ 1977 u8 type; 1978 __le16 rsvd2; 1979 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1980 } __packed; 1981 1982 struct rtw89_btc_fbtc_btscan_v7 { 1983 u8 fver; /* btc_ver::fcxbtscan */ 1984 u8 type; 1985 u8 rsvd0; 1986 u8 rsvd1; 1987 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1988 } __packed; 1989 1990 union rtw89_btc_fbtc_btscan { 1991 struct rtw89_btc_fbtc_btscan_v1 v1; 1992 struct rtw89_btc_fbtc_btscan_v2 v2; 1993 struct rtw89_btc_fbtc_btscan_v7 v7; 1994 }; 1995 1996 struct rtw89_btc_bt_info { 1997 struct rtw89_btc_bt_link_info link_info; 1998 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1999 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2000 struct rtw89_btc_bt_ver_info ver_info; 2001 struct rtw89_btc_bool_sta_chg enable; 2002 struct rtw89_btc_bool_sta_chg inq_pag; 2003 struct rtw89_btc_rf_para rf_para; 2004 union rtw89_btc_bt_rfk_info_map rfk_info; 2005 2006 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2007 u8 rssi_level; 2008 2009 u32 scbd; 2010 u32 feature; 2011 2012 u32 mbx_avl: 1; 2013 u32 whql_test: 1; 2014 u32 igno_wl: 1; 2015 u32 reinit: 1; 2016 u32 ble_scan_en: 1; 2017 u32 btg_type: 1; 2018 u32 inq: 1; 2019 u32 pag: 1; 2020 u32 run_patch_code: 1; 2021 u32 hi_lna_rx: 1; 2022 u32 scan_rx_low_pri: 1; 2023 u32 scan_info_update: 1; 2024 u32 lna_constrain: 3; 2025 u32 rsvd: 17; 2026 }; 2027 2028 struct rtw89_btc_cx { 2029 struct rtw89_btc_wl_info wl; 2030 struct rtw89_btc_bt_info bt; 2031 struct rtw89_btc_3rdcx_info other; 2032 u32 state_map; 2033 u32 cnt_bt[BTC_BCNT_NUM]; 2034 u32 cnt_wl[BTC_WCNT_NUM]; 2035 }; 2036 2037 struct rtw89_btc_fbtc_tdma { 2038 u8 type; /* btc_ver::fcxtdma */ 2039 u8 rxflctrl; 2040 u8 txpause; 2041 u8 wtgle_n; 2042 u8 leak_n; 2043 u8 ext_ctrl; 2044 u8 rxflctrl_role; 2045 u8 option_ctrl; 2046 } __packed; 2047 2048 struct rtw89_btc_fbtc_tdma_v3 { 2049 u8 fver; /* btc_ver::fcxtdma */ 2050 u8 rsvd; 2051 __le16 rsvd1; 2052 struct rtw89_btc_fbtc_tdma tdma; 2053 } __packed; 2054 2055 union rtw89_btc_fbtc_tdma_le32 { 2056 struct rtw89_btc_fbtc_tdma v1; 2057 struct rtw89_btc_fbtc_tdma_v3 v3; 2058 }; 2059 2060 #define CXMREG_MAX 30 2061 #define CXMREG_MAX_V2 20 2062 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2063 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2064 2065 enum rtw89_btc_bt_sta_counter { 2066 BTC_BCNT_RFK_REQ = 0, 2067 BTC_BCNT_RFK_GO = 1, 2068 BTC_BCNT_RFK_REJECT = 2, 2069 BTC_BCNT_RFK_FAIL = 3, 2070 BTC_BCNT_RFK_TIMEOUT = 4, 2071 BTC_BCNT_HI_TX = 5, 2072 BTC_BCNT_HI_RX = 6, 2073 BTC_BCNT_LO_TX = 7, 2074 BTC_BCNT_LO_RX = 8, 2075 BTC_BCNT_POLLUTED = 9, 2076 BTC_BCNT_STA_MAX 2077 }; 2078 2079 enum rtw89_btc_bt_sta_counter_v105 { 2080 BTC_BCNT_RFK_REQ_V105 = 0, 2081 BTC_BCNT_HI_TX_V105 = 1, 2082 BTC_BCNT_HI_RX_V105 = 2, 2083 BTC_BCNT_LO_TX_V105 = 3, 2084 BTC_BCNT_LO_RX_V105 = 4, 2085 BTC_BCNT_POLLUTED_V105 = 5, 2086 BTC_BCNT_STA_MAX_V105 2087 }; 2088 2089 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2090 u16 fver; /* btc_ver::fcxbtcrpt */ 2091 u16 rpt_cnt; /* tmr counters */ 2092 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2093 u32 wl_fw_cx_offload; 2094 u32 wl_fw_ver; 2095 u32 rpt_enable; 2096 u32 rpt_para; /* ms */ 2097 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2098 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2099 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2100 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2101 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2102 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2103 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2104 u32 c2h_cnt; /* fw send c2h counter */ 2105 u32 h2c_cnt; /* fw recv h2c counter */ 2106 } __packed; 2107 2108 struct rtw89_btc_fbtc_rpt_ctrl_info { 2109 __le32 cnt; /* fw report counter */ 2110 __le32 en; /* report map */ 2111 __le32 para; /* not used */ 2112 2113 __le32 cnt_c2h; /* fw send c2h counter */ 2114 __le32 cnt_h2c; /* fw recv h2c counter */ 2115 __le32 len_c2h; /* The total length of the last C2H */ 2116 2117 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2118 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2119 } __packed; 2120 2121 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2122 __le32 cx_ver; /* match which driver's coex version */ 2123 __le32 fw_ver; 2124 __le32 en; /* report map */ 2125 2126 __le16 cnt; /* fw report counter */ 2127 __le16 cnt_c2h; /* fw send c2h counter */ 2128 __le16 cnt_h2c; /* fw recv h2c counter */ 2129 __le16 len_c2h; /* The total length of the last C2H */ 2130 2131 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2132 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2133 } __packed; 2134 2135 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2136 __le16 cnt; /* fw report counter */ 2137 __le16 cnt_c2h; /* fw send c2h counter */ 2138 __le16 cnt_h2c; /* fw recv h2c counter */ 2139 __le16 len_c2h; /* The total length of the last C2H */ 2140 2141 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2142 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2143 2144 __le32 cx_ver; /* match which driver's coex version */ 2145 __le32 fw_ver; 2146 __le32 en; /* report map */ 2147 } __packed; 2148 2149 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2150 __le32 cx_ver; /* match which driver's coex version */ 2151 __le32 cx_offload; 2152 __le32 fw_ver; 2153 } __packed; 2154 2155 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2156 __le32 cnt_empty; /* a2dp empty count */ 2157 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2158 __le32 cnt_tx; 2159 __le32 cnt_ack; 2160 __le32 cnt_nack; 2161 } __packed; 2162 2163 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2164 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2165 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2166 __le32 cnt_recv; /* fw recv mailbox counter */ 2167 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2168 } __packed; 2169 2170 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2171 u8 fver; 2172 u8 rsvd; 2173 __le16 rsvd1; 2174 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2175 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2176 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2177 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2178 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2179 } __packed; 2180 2181 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2182 u8 fver; 2183 u8 rsvd; 2184 __le16 rsvd1; 2185 2186 u8 gnt_val[RTW89_PHY_MAX][4]; 2187 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2188 2189 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2190 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2191 } __packed; 2192 2193 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2194 u8 fver; 2195 u8 rsvd; 2196 __le16 rsvd1; 2197 2198 u8 gnt_val[RTW89_PHY_MAX][4]; 2199 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2200 2201 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2202 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2203 } __packed; 2204 2205 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2206 u8 fver; 2207 u8 rsvd0; 2208 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2209 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2210 2211 u8 gnt_val[RTW89_PHY_MAX][4]; 2212 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2213 2214 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2215 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2216 } __packed; 2217 2218 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2219 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2220 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2221 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2222 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2223 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2224 }; 2225 2226 enum rtw89_fbtc_ext_ctrl_type { 2227 CXECTL_OFF = 0x0, /* tdma off */ 2228 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2229 CXECTL_EXT = 0x2, 2230 CXECTL_MAX 2231 }; 2232 2233 union rtw89_btc_fbtc_rxflct { 2234 u8 val; 2235 u8 type: 3; 2236 u8 tgln_n: 5; 2237 }; 2238 2239 enum rtw89_btc_cxst_state { 2240 CXST_OFF = 0x0, 2241 CXST_B2W = 0x1, 2242 CXST_W1 = 0x2, 2243 CXST_W2 = 0x3, 2244 CXST_W2B = 0x4, 2245 CXST_B1 = 0x5, 2246 CXST_B2 = 0x6, 2247 CXST_B3 = 0x7, 2248 CXST_B4 = 0x8, 2249 CXST_LK = 0x9, 2250 CXST_BLK = 0xa, 2251 CXST_E2G = 0xb, 2252 CXST_E5G = 0xc, 2253 CXST_EBT = 0xd, 2254 CXST_ENULL = 0xe, 2255 CXST_WLK = 0xf, 2256 CXST_W1FDD = 0x10, 2257 CXST_B1FDD = 0x11, 2258 CXST_MAX = 0x12, 2259 }; 2260 2261 enum rtw89_btc_cxevnt { 2262 CXEVNT_TDMA_ENTRY = 0x0, 2263 CXEVNT_WL_TMR, 2264 CXEVNT_B1_TMR, 2265 CXEVNT_B2_TMR, 2266 CXEVNT_B3_TMR, 2267 CXEVNT_B4_TMR, 2268 CXEVNT_W2B_TMR, 2269 CXEVNT_B2W_TMR, 2270 CXEVNT_BCN_EARLY, 2271 CXEVNT_A2DP_EMPTY, 2272 CXEVNT_LK_END, 2273 CXEVNT_RX_ISR, 2274 CXEVNT_RX_FC0, 2275 CXEVNT_RX_FC1, 2276 CXEVNT_BT_RELINK, 2277 CXEVNT_BT_RETRY, 2278 CXEVNT_E2G, 2279 CXEVNT_E5G, 2280 CXEVNT_EBT, 2281 CXEVNT_ENULL, 2282 CXEVNT_DRV_WLK, 2283 CXEVNT_BCN_OK, 2284 CXEVNT_BT_CHANGE, 2285 CXEVNT_EBT_EXTEND, 2286 CXEVNT_E2G_NULL1, 2287 CXEVNT_B1FDD_TMR, 2288 CXEVNT_MAX 2289 }; 2290 2291 enum { 2292 CXBCN_ALL = 0x0, 2293 CXBCN_ALL_OK, 2294 CXBCN_BT_SLOT, 2295 CXBCN_BT_OK, 2296 CXBCN_MAX 2297 }; 2298 2299 enum btc_slot_type { 2300 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2301 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2302 CXSTYPE_NUM, 2303 }; 2304 2305 enum { /* TIME */ 2306 CXT_BT = 0x0, 2307 CXT_WL = 0x1, 2308 CXT_MAX 2309 }; 2310 2311 enum { /* TIME-A2DP */ 2312 CXT_FLCTRL_OFF = 0x0, 2313 CXT_FLCTRL_ON = 0x1, 2314 CXT_FLCTRL_MAX 2315 }; 2316 2317 enum { /* STEP TYPE */ 2318 CXSTEP_NONE = 0x0, 2319 CXSTEP_EVNT = 0x1, 2320 CXSTEP_SLOT = 0x2, 2321 CXSTEP_MAX, 2322 }; 2323 2324 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2325 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2326 RPT_BT_AFH_SEQ_LE = 0x20 2327 }; 2328 2329 #define BTC_DBG_MAX1 32 2330 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2331 u8 fver; /* btc_ver::fcxgpiodbg */ 2332 u8 rsvd; 2333 __le16 rsvd2; 2334 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2335 __le32 pre_state; /* the debug signal is 1 or 0 */ 2336 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2337 } __packed; 2338 2339 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2340 u8 fver; 2341 u8 rsvd0; 2342 u8 rsvd1; 2343 u8 rsvd2; 2344 2345 u8 gpio_map[BTC_DBG_MAX1]; 2346 2347 __le32 en_map; 2348 __le32 pre_state; 2349 } __packed; 2350 2351 union rtw89_btc_fbtc_gpio_dbg { 2352 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2353 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2354 }; 2355 2356 struct rtw89_btc_fbtc_mreg_val_v1 { 2357 u8 fver; /* btc_ver::fcxmreg */ 2358 u8 reg_num; 2359 __le16 rsvd; 2360 __le32 mreg_val[CXMREG_MAX]; 2361 } __packed; 2362 2363 struct rtw89_btc_fbtc_mreg_val_v2 { 2364 u8 fver; /* btc_ver::fcxmreg */ 2365 u8 reg_num; 2366 __le16 rsvd; 2367 __le32 mreg_val[CXMREG_MAX_V2]; 2368 } __packed; 2369 2370 struct rtw89_btc_fbtc_mreg_val_v7 { 2371 u8 fver; 2372 u8 reg_num; 2373 u8 rsvd0; 2374 u8 rsvd1; 2375 __le32 mreg_val[CXMREG_MAX_V2]; 2376 } __packed; 2377 2378 union rtw89_btc_fbtc_mreg_val { 2379 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2380 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2381 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2382 }; 2383 2384 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2385 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2386 .offset = cpu_to_le32(__offset), } 2387 2388 struct rtw89_btc_fbtc_mreg { 2389 __le16 type; 2390 __le16 bytes; 2391 __le32 offset; 2392 } __packed; 2393 2394 struct rtw89_btc_fbtc_slot { 2395 __le16 dur; 2396 __le32 cxtbl; 2397 __le16 cxtype; 2398 } __packed; 2399 2400 struct rtw89_btc_fbtc_slots { 2401 u8 fver; /* btc_ver::fcxslots */ 2402 u8 tbl_num; 2403 __le16 rsvd; 2404 __le32 update_map; 2405 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2406 } __packed; 2407 2408 struct rtw89_btc_fbtc_slot_v7 { 2409 __le16 dur; /* slot duration */ 2410 __le16 cxtype; 2411 __le32 cxtbl; 2412 } __packed; 2413 2414 struct rtw89_btc_fbtc_slot_u16 { 2415 __le16 dur; /* slot duration */ 2416 __le16 cxtype; 2417 __le16 cxtbl_l16; /* coex table [15:0] */ 2418 __le16 cxtbl_h16; /* coex table [31:16] */ 2419 } __packed; 2420 2421 struct rtw89_btc_fbtc_1slot_v7 { 2422 u8 fver; 2423 u8 sid; /* slot id */ 2424 __le16 rsvd; 2425 struct rtw89_btc_fbtc_slot_v7 slot; 2426 } __packed; 2427 2428 struct rtw89_btc_fbtc_slots_v7 { 2429 u8 fver; 2430 u8 slot_cnt; 2431 u8 rsvd0; 2432 u8 rsvd1; 2433 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2434 __le32 update_map; 2435 } __packed; 2436 2437 union rtw89_btc_fbtc_slots_info { 2438 struct rtw89_btc_fbtc_slots v1; 2439 struct rtw89_btc_fbtc_slots_v7 v7; 2440 } __packed; 2441 2442 struct rtw89_btc_fbtc_step { 2443 u8 type; 2444 u8 val; 2445 __le16 difft; 2446 } __packed; 2447 2448 struct rtw89_btc_fbtc_steps_v2 { 2449 u8 fver; /* btc_ver::fcxstep */ 2450 u8 rsvd; 2451 __le16 cnt; 2452 __le16 pos_old; 2453 __le16 pos_new; 2454 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2455 } __packed; 2456 2457 struct rtw89_btc_fbtc_steps_v3 { 2458 u8 fver; 2459 u8 en; 2460 __le16 rsvd; 2461 __le32 cnt; 2462 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2463 } __packed; 2464 2465 union rtw89_btc_fbtc_steps_info { 2466 struct rtw89_btc_fbtc_steps_v2 v2; 2467 struct rtw89_btc_fbtc_steps_v3 v3; 2468 }; 2469 2470 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2471 u8 fver; /* btc_ver::fcxcysta */ 2472 u8 rsvd; 2473 __le16 cycles; /* total cycle number */ 2474 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2475 __le16 a2dpept; /* a2dp empty cnt */ 2476 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2477 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2478 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2479 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2480 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2481 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2482 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2483 __le16 tmax_a2dpept; /* max a2dp empty time */ 2484 __le16 tavg_lk; /* avg leak-slot time */ 2485 __le16 tmax_lk; /* max leak-slot time */ 2486 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2487 __le32 bcn_cnt[CXBCN_MAX]; 2488 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2489 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2490 __le32 skip_cnt; 2491 __le32 exception; 2492 __le32 except_cnt; 2493 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2494 } __packed; 2495 2496 struct rtw89_btc_fbtc_fdd_try_info { 2497 __le16 cycles[CXT_FLCTRL_MAX]; 2498 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2499 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2500 } __packed; 2501 2502 struct rtw89_btc_fbtc_cycle_time_info { 2503 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2504 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2505 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2506 } __packed; 2507 2508 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2509 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2510 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2511 } __packed; 2512 2513 struct rtw89_btc_fbtc_a2dp_trx_stat { 2514 u8 empty_cnt; 2515 u8 retry_cnt; 2516 u8 tx_rate; 2517 u8 tx_cnt; 2518 u8 ack_cnt; 2519 u8 nack_cnt; 2520 u8 rsvd1; 2521 u8 rsvd2; 2522 } __packed; 2523 2524 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2525 u8 empty_cnt; 2526 u8 retry_cnt; 2527 u8 tx_rate; 2528 u8 tx_cnt; 2529 u8 ack_cnt; 2530 u8 nack_cnt; 2531 u8 no_empty_cnt; 2532 u8 rsvd; 2533 } __packed; 2534 2535 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2536 __le16 cnt; /* a2dp empty cnt */ 2537 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2538 __le16 tavg; /* avg a2dp empty time */ 2539 __le16 tmax; /* max a2dp empty time */ 2540 } __packed; 2541 2542 struct rtw89_btc_fbtc_cycle_leak_info { 2543 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2544 __le16 tavg; /* avg leak-slot time */ 2545 __le16 tmax; /* max leak-slot time */ 2546 } __packed; 2547 2548 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2549 __le16 tavg; 2550 __le16 tamx; 2551 __le32 cnt_rximr; 2552 } __packed; 2553 2554 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2555 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2556 2557 struct rtw89_btc_fbtc_cycle_fddt_info { 2558 __le16 train_cycle; 2559 __le16 tp; 2560 2561 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2562 s8 bt_tx_power; /* decrease Tx power (dB) */ 2563 s8 bt_rx_gain; /* LNA constrain level */ 2564 u8 no_empty_cnt; 2565 2566 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2567 u8 cn; /* condition_num */ 2568 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2569 u8 train_result; /* refer to enum btc_fddt_check_map */ 2570 } __packed; 2571 2572 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2573 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2574 2575 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2576 __le16 train_cycle; 2577 __le16 tp; 2578 2579 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2580 s8 bt_tx_power; /* decrease Tx power (dB) */ 2581 s8 bt_rx_gain; /* LNA constrain level */ 2582 u8 no_empty_cnt; 2583 2584 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2585 u8 cn; /* condition_num */ 2586 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2587 u8 train_result; /* refer to enum btc_fddt_check_map */ 2588 } __packed; 2589 2590 struct rtw89_btc_fbtc_fddt_cell_status { 2591 s8 wl_tx_pwr; 2592 s8 bt_tx_pwr; 2593 s8 bt_rx_gain; 2594 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2595 } __packed; 2596 2597 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2598 u8 fver; 2599 u8 rsvd; 2600 __le16 cycles; /* total cycle number */ 2601 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2602 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2603 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2604 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2605 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2606 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2607 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2608 __le32 bcn_cnt[CXBCN_MAX]; 2609 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2610 __le32 skip_cnt; 2611 __le32 except_cnt; 2612 __le32 except_map; 2613 } __packed; 2614 2615 #define FDD_TRAIN_WL_DIRECTION 2 2616 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2617 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2618 2619 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2620 u8 fver; 2621 u8 rsvd; 2622 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2623 u8 except_cnt; 2624 2625 __le16 skip_cnt; 2626 __le16 cycles; /* total cycle number */ 2627 2628 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2629 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2630 __le16 bcn_cnt[CXBCN_MAX]; 2631 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2632 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2633 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2634 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2635 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2636 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2637 [FDD_TRAIN_WL_RSSI_LEVEL] 2638 [FDD_TRAIN_BT_RSSI_LEVEL]; 2639 __le32 except_map; 2640 } __packed; 2641 2642 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2643 u8 fver; 2644 u8 rsvd; 2645 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2646 u8 except_cnt; 2647 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2648 2649 __le16 skip_cnt; 2650 __le16 cycles; /* total cycle number */ 2651 2652 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2653 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2654 __le16 bcn_cnt[CXBCN_MAX]; 2655 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2656 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2657 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2658 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2659 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2660 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2661 [FDD_TRAIN_WL_RSSI_LEVEL] 2662 [FDD_TRAIN_BT_RSSI_LEVEL]; 2663 __le32 except_map; 2664 } __packed; 2665 2666 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2667 u8 fver; 2668 u8 rsvd; 2669 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2670 u8 except_cnt; 2671 2672 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2673 2674 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2675 2676 __le16 skip_cnt; 2677 __le16 cycles; /* total cycle number */ 2678 2679 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2680 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2681 __le16 bcn_cnt[CXBCN_MAX]; 2682 2683 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2684 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2685 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2686 2687 __le32 except_map; 2688 } __packed; 2689 2690 union rtw89_btc_fbtc_cysta_info { 2691 struct rtw89_btc_fbtc_cysta_v2 v2; 2692 struct rtw89_btc_fbtc_cysta_v3 v3; 2693 struct rtw89_btc_fbtc_cysta_v4 v4; 2694 struct rtw89_btc_fbtc_cysta_v5 v5; 2695 struct rtw89_btc_fbtc_cysta_v7 v7; 2696 }; 2697 2698 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2699 u8 fver; /* btc_ver::fcxnullsta */ 2700 u8 rsvd; 2701 __le16 rsvd2; 2702 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2703 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2704 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2705 } __packed; 2706 2707 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2708 u8 fver; /* btc_ver::fcxnullsta */ 2709 u8 rsvd; 2710 __le16 rsvd2; 2711 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2712 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2713 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2714 } __packed; 2715 2716 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2717 u8 fver; 2718 u8 rsvd0; 2719 u8 rsvd1; 2720 u8 rsvd2; 2721 2722 __le32 tmax[2]; 2723 __le32 tavg[2]; 2724 __le32 result[2][5]; 2725 } __packed; 2726 2727 union rtw89_btc_fbtc_cynullsta_info { 2728 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2729 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2730 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2731 }; 2732 2733 struct rtw89_btc_fbtc_btver_v1 { 2734 u8 fver; /* btc_ver::fcxbtver */ 2735 u8 rsvd; 2736 __le16 rsvd2; 2737 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2738 __le32 fw_ver; 2739 __le32 feature; 2740 } __packed; 2741 2742 struct rtw89_btc_fbtc_btver_v7 { 2743 u8 fver; 2744 u8 rsvd0; 2745 u8 rsvd1; 2746 u8 rsvd2; 2747 2748 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2749 __le32 fw_ver; 2750 __le32 feature; 2751 } __packed; 2752 2753 union rtw89_btc_fbtc_btver { 2754 struct rtw89_btc_fbtc_btver_v1 v1; 2755 struct rtw89_btc_fbtc_btver_v7 v7; 2756 } __packed; 2757 2758 struct rtw89_btc_fbtc_btafh { 2759 u8 fver; /* btc_ver::fcxbtafh */ 2760 u8 rsvd; 2761 __le16 rsvd2; 2762 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2763 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2764 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2765 } __packed; 2766 2767 struct rtw89_btc_fbtc_btafh_v2 { 2768 u8 fver; /* btc_ver::fcxbtafh */ 2769 u8 rsvd; 2770 u8 rsvd2; 2771 u8 map_type; 2772 u8 afh_l[4]; 2773 u8 afh_m[4]; 2774 u8 afh_h[4]; 2775 u8 afh_le_a[4]; 2776 u8 afh_le_b[4]; 2777 } __packed; 2778 2779 struct rtw89_btc_fbtc_btafh_v7 { 2780 u8 fver; 2781 u8 map_type; 2782 u8 rsvd0; 2783 u8 rsvd1; 2784 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2785 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2786 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2787 u8 afh_le_a[4]; 2788 u8 afh_le_b[4]; 2789 } __packed; 2790 2791 struct rtw89_btc_fbtc_btdevinfo { 2792 u8 fver; /* btc_ver::fcxbtdevinfo */ 2793 u8 rsvd; 2794 __le16 vendor_id; 2795 __le32 dev_name; /* only 24 bits valid */ 2796 __le32 flush_time; 2797 } __packed; 2798 2799 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2800 struct rtw89_btc_rf_trx_para { 2801 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2802 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2803 u8 bt_tx_power; /* decrease Tx power (dB) */ 2804 u8 bt_rx_gain; /* LNA constrain level */ 2805 }; 2806 2807 struct rtw89_btc_trx_info { 2808 u8 tx_lvl; 2809 u8 rx_lvl; 2810 u8 wl_rssi; 2811 u8 bt_rssi; 2812 2813 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2814 s8 rx_gain; /* rx gain table index (TBD.) */ 2815 s8 bt_tx_power; /* decrease Tx power (dB) */ 2816 s8 bt_rx_gain; /* LNA constrain level */ 2817 2818 u8 cn; /* condition_num */ 2819 s8 nhm; 2820 u8 bt_profile; 2821 u8 rsvd2; 2822 2823 u16 tx_rate; 2824 u16 rx_rate; 2825 2826 u32 tx_tp; 2827 u32 rx_tp; 2828 u32 rx_err_ratio; 2829 }; 2830 2831 union rtw89_btc_fbtc_slot_u { 2832 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2833 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2834 }; 2835 2836 struct rtw89_btc_dm { 2837 union rtw89_btc_fbtc_slot_u slot; 2838 union rtw89_btc_fbtc_slot_u slot_now; 2839 struct rtw89_btc_fbtc_tdma tdma; 2840 struct rtw89_btc_fbtc_tdma tdma_now; 2841 struct rtw89_mac_ax_coex_gnt gnt; 2842 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2843 struct rtw89_btc_rf_trx_para rf_trx_para; 2844 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2845 struct rtw89_btc_dm_step dm_step; 2846 struct rtw89_btc_wl_scc_ctrl wl_scc; 2847 struct rtw89_btc_trx_info trx_info; 2848 union rtw89_btc_dm_error_map error; 2849 u32 cnt_dm[BTC_DCNT_NUM]; 2850 u32 cnt_notify[BTC_NCNT_NUM]; 2851 2852 u32 update_slot_map; 2853 u32 set_ant_path; 2854 u32 e2g_slot_limit; 2855 u32 e2g_slot_nulltx_time; 2856 2857 u32 wl_only: 1; 2858 u32 wl_fw_cx_offload: 1; 2859 u32 freerun: 1; 2860 u32 fddt_train: 1; 2861 u32 wl_ps_ctrl: 2; 2862 u32 wl_mimo_ps: 1; 2863 u32 leak_ap: 1; 2864 u32 noisy_level: 3; 2865 u32 coex_info_map: 8; 2866 u32 bt_only: 1; 2867 u32 wl_btg_rx: 2; 2868 u32 trx_para_level: 8; 2869 u32 wl_stb_chg: 1; 2870 u32 pta_owner: 1; 2871 2872 u32 tdma_instant_excute: 1; 2873 u32 wl_btg_rx_rb: 2; 2874 2875 u16 slot_dur[CXST_MAX]; 2876 u16 bt_slot_flood; 2877 2878 u8 run_reason; 2879 u8 run_action; 2880 2881 u8 wl_pre_agc: 2; 2882 u8 wl_lna2: 1; 2883 u8 wl_pre_agc_rb: 2; 2884 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2885 u8 slot_req_more: 1; 2886 }; 2887 2888 struct rtw89_btc_ctrl { 2889 u32 manual: 1; 2890 u32 igno_bt: 1; 2891 u32 always_freerun: 1; 2892 u32 trace_step: 16; 2893 u32 rsvd: 12; 2894 }; 2895 2896 struct rtw89_btc_ctrl_v7 { 2897 u8 manual; 2898 u8 igno_bt; 2899 u8 always_freerun; 2900 u8 rsvd; 2901 } __packed; 2902 2903 union rtw89_btc_ctrl_list { 2904 struct rtw89_btc_ctrl ctrl; 2905 struct rtw89_btc_ctrl_v7 ctrl_v7; 2906 }; 2907 2908 struct rtw89_btc_dbg { 2909 /* cmd "rb" */ 2910 bool rb_done; 2911 u32 rb_val; 2912 }; 2913 2914 enum rtw89_btc_btf_fw_event { 2915 BTF_EVNT_RPT = 0, 2916 BTF_EVNT_BT_INFO = 1, 2917 BTF_EVNT_BT_SCBD = 2, 2918 BTF_EVNT_BT_REG = 3, 2919 BTF_EVNT_CX_RUNINFO = 4, 2920 BTF_EVNT_BT_PSD = 5, 2921 BTF_EVNT_BUF_OVERFLOW, 2922 BTF_EVNT_C2H_LOOPBACK, 2923 BTF_EVNT_MAX, 2924 }; 2925 2926 enum btf_fw_event_report { 2927 BTC_RPT_TYPE_CTRL = 0x0, 2928 BTC_RPT_TYPE_TDMA, 2929 BTC_RPT_TYPE_SLOT, 2930 BTC_RPT_TYPE_CYSTA, 2931 BTC_RPT_TYPE_STEP, 2932 BTC_RPT_TYPE_NULLSTA, 2933 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 2934 BTC_RPT_TYPE_MREG, 2935 BTC_RPT_TYPE_GPIO_DBG, 2936 BTC_RPT_TYPE_BT_VER, 2937 BTC_RPT_TYPE_BT_SCAN, 2938 BTC_RPT_TYPE_BT_AFH, 2939 BTC_RPT_TYPE_BT_DEVICE, 2940 BTC_RPT_TYPE_TEST, 2941 BTC_RPT_TYPE_MAX = 31, 2942 2943 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 2944 __BTC_RPT_TYPE_V0_MAX = 12, 2945 }; 2946 2947 enum rtw_btc_btf_reg_type { 2948 REG_MAC = 0x0, 2949 REG_BB = 0x1, 2950 REG_RF = 0x2, 2951 REG_BT_RF = 0x3, 2952 REG_BT_MODEM = 0x4, 2953 REG_BT_BLUEWIZE = 0x5, 2954 REG_BT_VENDOR = 0x6, 2955 REG_BT_LE = 0x7, 2956 REG_MAX_TYPE, 2957 }; 2958 2959 struct rtw89_btc_rpt_cmn_info { 2960 u32 rx_cnt; 2961 u32 rx_len; 2962 u32 req_len; /* expected rsp len */ 2963 u8 req_fver; /* expected rsp fver */ 2964 u8 rsp_fver; /* fver from fw */ 2965 u8 valid; 2966 } __packed; 2967 2968 union rtw89_btc_fbtc_btafh_info { 2969 struct rtw89_btc_fbtc_btafh v1; 2970 struct rtw89_btc_fbtc_btafh_v2 v2; 2971 }; 2972 2973 struct rtw89_btc_report_ctrl_state { 2974 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2975 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2976 }; 2977 2978 struct rtw89_btc_rpt_fbtc_tdma { 2979 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2980 union rtw89_btc_fbtc_tdma_le32 finfo; 2981 }; 2982 2983 struct rtw89_btc_rpt_fbtc_slots { 2984 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2985 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 2986 }; 2987 2988 struct rtw89_btc_rpt_fbtc_cysta { 2989 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2990 union rtw89_btc_fbtc_cysta_info finfo; 2991 }; 2992 2993 struct rtw89_btc_rpt_fbtc_step { 2994 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2995 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2996 }; 2997 2998 struct rtw89_btc_rpt_fbtc_nullsta { 2999 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3000 union rtw89_btc_fbtc_cynullsta_info finfo; 3001 }; 3002 3003 struct rtw89_btc_rpt_fbtc_mreg { 3004 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3005 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3006 }; 3007 3008 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3009 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3010 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3011 }; 3012 3013 struct rtw89_btc_rpt_fbtc_btver { 3014 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3015 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3016 }; 3017 3018 struct rtw89_btc_rpt_fbtc_btscan { 3019 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3020 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3021 }; 3022 3023 struct rtw89_btc_rpt_fbtc_btafh { 3024 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3025 union rtw89_btc_fbtc_btafh_info finfo; 3026 }; 3027 3028 struct rtw89_btc_rpt_fbtc_btdev { 3029 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3030 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3031 }; 3032 3033 enum rtw89_btc_btfre_type { 3034 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3035 BTFRE_UNDEF_TYPE, 3036 BTFRE_EXCEPTION, 3037 BTFRE_MAX, 3038 }; 3039 3040 struct rtw89_btc_btf_fwinfo { 3041 u32 cnt_c2h; 3042 u32 cnt_h2c; 3043 u32 cnt_h2c_fail; 3044 u32 event[BTF_EVNT_MAX]; 3045 3046 u32 err[BTFRE_MAX]; 3047 u32 len_mismch; 3048 u32 fver_mismch; 3049 u32 rpt_en_map; 3050 3051 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3052 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3053 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3054 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3055 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3056 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3057 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3058 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3059 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3060 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3061 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3062 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3063 }; 3064 3065 struct rtw89_btc_ver { 3066 enum rtw89_core_chip_id chip_id; 3067 u32 fw_ver_code; 3068 3069 u8 fcxbtcrpt; 3070 u8 fcxtdma; 3071 u8 fcxslots; 3072 u8 fcxcysta; 3073 u8 fcxstep; 3074 u8 fcxnullsta; 3075 u8 fcxmreg; 3076 u8 fcxgpiodbg; 3077 u8 fcxbtver; 3078 u8 fcxbtscan; 3079 u8 fcxbtafh; 3080 u8 fcxbtdevinfo; 3081 u8 fwlrole; 3082 u8 frptmap; 3083 u8 fcxctrl; 3084 u8 fcxinit; 3085 3086 u8 fwevntrptl; 3087 u8 drvinfo_type; 3088 u16 info_buf; 3089 u8 max_role_num; 3090 }; 3091 3092 #define RTW89_BTC_POLICY_MAXLEN 512 3093 3094 struct rtw89_btc { 3095 const struct rtw89_btc_ver *ver; 3096 3097 struct rtw89_btc_cx cx; 3098 struct rtw89_btc_dm dm; 3099 union rtw89_btc_ctrl_list ctrl; 3100 union rtw89_btc_module_info mdinfo; 3101 struct rtw89_btc_btf_fwinfo fwinfo; 3102 struct rtw89_btc_dbg dbg; 3103 3104 struct work_struct eapol_notify_work; 3105 struct work_struct arp_notify_work; 3106 struct work_struct dhcp_notify_work; 3107 struct work_struct icmp_notify_work; 3108 3109 u32 bt_req_len; 3110 3111 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3112 u8 ant_type; 3113 u8 btg_pos; 3114 u16 policy_len; 3115 u16 policy_type; 3116 u32 hubmsg_cnt; 3117 bool bt_req_en; 3118 bool update_policy_force; 3119 bool lps; 3120 bool manual_ctrl; 3121 }; 3122 3123 enum rtw89_btc_hmsg { 3124 RTW89_BTC_HMSG_TMR_EN = 0x0, 3125 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3126 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3127 RTW89_BTC_HMSG_FW_EV = 0x3, 3128 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3129 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3130 3131 NUM_OF_RTW89_BTC_HMSG, 3132 }; 3133 3134 enum rtw89_ra_mode { 3135 RTW89_RA_MODE_CCK = BIT(0), 3136 RTW89_RA_MODE_OFDM = BIT(1), 3137 RTW89_RA_MODE_HT = BIT(2), 3138 RTW89_RA_MODE_VHT = BIT(3), 3139 RTW89_RA_MODE_HE = BIT(4), 3140 RTW89_RA_MODE_EHT = BIT(5), 3141 }; 3142 3143 enum rtw89_ra_report_mode { 3144 RTW89_RA_RPT_MODE_LEGACY, 3145 RTW89_RA_RPT_MODE_HT, 3146 RTW89_RA_RPT_MODE_VHT, 3147 RTW89_RA_RPT_MODE_HE, 3148 RTW89_RA_RPT_MODE_EHT, 3149 }; 3150 3151 enum rtw89_dig_noisy_level { 3152 RTW89_DIG_NOISY_LEVEL0 = -1, 3153 RTW89_DIG_NOISY_LEVEL1 = 0, 3154 RTW89_DIG_NOISY_LEVEL2 = 1, 3155 RTW89_DIG_NOISY_LEVEL3 = 2, 3156 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3157 }; 3158 3159 enum rtw89_gi_ltf { 3160 RTW89_GILTF_LGI_4XHE32 = 0, 3161 RTW89_GILTF_SGI_4XHE08 = 1, 3162 RTW89_GILTF_2XHE16 = 2, 3163 RTW89_GILTF_2XHE08 = 3, 3164 RTW89_GILTF_1XHE16 = 4, 3165 RTW89_GILTF_1XHE08 = 5, 3166 RTW89_GILTF_MAX 3167 }; 3168 3169 enum rtw89_rx_frame_type { 3170 RTW89_RX_TYPE_MGNT = 0, 3171 RTW89_RX_TYPE_CTRL = 1, 3172 RTW89_RX_TYPE_DATA = 2, 3173 RTW89_RX_TYPE_RSVD = 3, 3174 }; 3175 3176 enum rtw89_efuse_block { 3177 RTW89_EFUSE_BLOCK_SYS = 0, 3178 RTW89_EFUSE_BLOCK_RF = 1, 3179 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3180 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3181 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3182 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3183 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3184 RTW89_EFUSE_BLOCK_ADIE = 7, 3185 3186 RTW89_EFUSE_BLOCK_NUM, 3187 RTW89_EFUSE_BLOCK_IGNORE, 3188 }; 3189 3190 struct rtw89_ra_info { 3191 u8 is_dis_ra:1; 3192 /* Bit0 : CCK 3193 * Bit1 : OFDM 3194 * Bit2 : HT 3195 * Bit3 : VHT 3196 * Bit4 : HE 3197 * Bit5 : EHT 3198 */ 3199 u8 mode_ctrl:6; 3200 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3201 u8 macid; 3202 u8 dcm_cap:1; 3203 u8 er_cap:1; 3204 u8 init_rate_lv:2; 3205 u8 upd_all:1; 3206 u8 en_sgi:1; 3207 u8 ldpc_cap:1; 3208 u8 stbc_cap:1; 3209 u8 ss_num:3; 3210 u8 giltf:3; 3211 u8 upd_bw_nss_mask:1; 3212 u8 upd_mask:1; 3213 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3214 /* BFee CSI */ 3215 u8 band_num; 3216 u8 ra_csi_rate_en:1; 3217 u8 fixed_csi_rate_en:1; 3218 u8 cr_tbl_sel:1; 3219 u8 fix_giltf_en:1; 3220 u8 fix_giltf:3; 3221 u8 rsvd2:1; 3222 u8 csi_mcs_ss_idx; 3223 u8 csi_mode:2; 3224 u8 csi_gi_ltf:3; 3225 u8 csi_bw:3; 3226 }; 3227 3228 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3229 #define RTW89_PPDU_MAC_INFO_SIZE 8 3230 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3231 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3232 3233 #define RTW89_MAX_RX_AGG_NUM 64 3234 #define RTW89_MAX_TX_AGG_NUM 128 3235 3236 struct rtw89_ampdu_params { 3237 u16 agg_num; 3238 bool amsdu; 3239 }; 3240 3241 struct rtw89_ra_report { 3242 struct rate_info txrate; 3243 u32 bit_rate; 3244 u16 hw_rate; 3245 bool might_fallback_legacy; 3246 }; 3247 3248 DECLARE_EWMA(rssi, 10, 16); 3249 DECLARE_EWMA(evm, 10, 16); 3250 DECLARE_EWMA(snr, 10, 16); 3251 3252 struct rtw89_ba_cam_entry { 3253 struct list_head list; 3254 u8 tid; 3255 }; 3256 3257 #define RTW89_MAX_ADDR_CAM_NUM 128 3258 #define RTW89_MAX_BSSID_CAM_NUM 20 3259 #define RTW89_MAX_SEC_CAM_NUM 128 3260 #define RTW89_MAX_BA_CAM_NUM 24 3261 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3262 3263 struct rtw89_addr_cam_entry { 3264 u8 addr_cam_idx; 3265 u8 offset; 3266 u8 len; 3267 u8 valid : 1; 3268 u8 addr_mask : 6; 3269 u8 wapi : 1; 3270 u8 mask_sel : 2; 3271 u8 bssid_cam_idx: 6; 3272 3273 u8 sec_ent_mode; 3274 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3275 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3276 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3277 }; 3278 3279 struct rtw89_bssid_cam_entry { 3280 u8 bssid[ETH_ALEN]; 3281 u8 phy_idx; 3282 u8 bssid_cam_idx; 3283 u8 offset; 3284 u8 len; 3285 u8 valid : 1; 3286 u8 num; 3287 }; 3288 3289 struct rtw89_sec_cam_entry { 3290 u8 sec_cam_idx; 3291 u8 offset; 3292 u8 len; 3293 u8 type : 4; 3294 u8 ext_key : 1; 3295 u8 spp_mode : 1; 3296 /* 256 bits */ 3297 u8 key[32]; 3298 }; 3299 3300 struct rtw89_sta { 3301 u8 mac_id; 3302 bool disassoc; 3303 bool er_cap; 3304 struct rtw89_dev *rtwdev; 3305 struct rtw89_vif *rtwvif; 3306 struct rtw89_ra_info ra; 3307 struct rtw89_ra_report ra_report; 3308 int max_agg_wait; 3309 u8 prev_rssi; 3310 struct ewma_rssi avg_rssi; 3311 struct ewma_rssi rssi[RF_PATH_MAX]; 3312 struct ewma_snr avg_snr; 3313 struct ewma_evm evm_1ss; 3314 struct ewma_evm evm_min[RF_PATH_MAX]; 3315 struct ewma_evm evm_max[RF_PATH_MAX]; 3316 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 3317 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 3318 struct ieee80211_rx_status rx_status; 3319 u16 rx_hw_rate; 3320 __le32 htc_template; 3321 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3322 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3323 struct list_head ba_cam_list; 3324 struct sk_buff_head roc_queue; 3325 3326 bool use_cfg_mask; 3327 struct cfg80211_bitrate_mask mask; 3328 3329 bool cctl_tx_time; 3330 u32 ampdu_max_time:4; 3331 bool cctl_tx_retry_limit; 3332 u32 data_tx_cnt_lmt:6; 3333 }; 3334 3335 struct rtw89_efuse { 3336 bool valid; 3337 bool power_k_valid; 3338 u8 xtal_cap; 3339 u8 addr[ETH_ALEN]; 3340 u8 rfe_type; 3341 char country_code[2]; 3342 }; 3343 3344 struct rtw89_phy_rate_pattern { 3345 u64 ra_mask; 3346 u16 rate; 3347 u8 ra_mode; 3348 bool enable; 3349 }; 3350 3351 struct rtw89_tx_wait_info { 3352 struct rcu_head rcu_head; 3353 struct completion completion; 3354 bool tx_done; 3355 }; 3356 3357 struct rtw89_tx_skb_data { 3358 struct rtw89_tx_wait_info __rcu *wait; 3359 u8 hci_priv[]; 3360 }; 3361 3362 #define RTW89_ROC_IDLE_TIMEOUT 500 3363 #define RTW89_ROC_TX_TIMEOUT 30 3364 enum rtw89_roc_state { 3365 RTW89_ROC_IDLE, 3366 RTW89_ROC_NORMAL, 3367 RTW89_ROC_MGMT, 3368 }; 3369 3370 struct rtw89_roc { 3371 struct ieee80211_channel chan; 3372 struct delayed_work roc_work; 3373 enum ieee80211_roc_type type; 3374 enum rtw89_roc_state state; 3375 int duration; 3376 }; 3377 3378 #define RTW89_P2P_MAX_NOA_NUM 2 3379 3380 struct rtw89_p2p_ie_head { 3381 u8 eid; 3382 u8 ie_len; 3383 u8 oui[3]; 3384 u8 oui_type; 3385 } __packed; 3386 3387 struct rtw89_noa_attr_head { 3388 u8 attr_type; 3389 __le16 attr_len; 3390 u8 index; 3391 u8 oppps_ctwindow; 3392 } __packed; 3393 3394 struct rtw89_p2p_noa_ie { 3395 struct rtw89_p2p_ie_head p2p_head; 3396 struct rtw89_noa_attr_head noa_head; 3397 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3398 } __packed; 3399 3400 struct rtw89_p2p_noa_setter { 3401 struct rtw89_p2p_noa_ie ie; 3402 u8 noa_count; 3403 u8 noa_index; 3404 }; 3405 3406 struct rtw89_vif { 3407 struct list_head list; 3408 struct rtw89_dev *rtwdev; 3409 struct rtw89_roc roc; 3410 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3411 enum rtw89_chanctx_idx chanctx_idx; 3412 enum rtw89_reg_6ghz_power reg_6ghz_power; 3413 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3414 3415 u8 mac_id; 3416 u8 port; 3417 u8 mac_addr[ETH_ALEN]; 3418 u8 bssid[ETH_ALEN]; 3419 __be32 ip_addr; 3420 u8 phy_idx; 3421 u8 mac_idx; 3422 u8 net_type; 3423 u8 wifi_role; 3424 u8 self_role; 3425 u8 wmm; 3426 u8 bcn_hit_cond; 3427 u8 hit_rule; 3428 u8 last_noa_nr; 3429 u64 sync_bcn_tsf; 3430 bool offchan; 3431 bool trigger; 3432 bool lsig_txop; 3433 u8 tgt_ind; 3434 u8 frm_tgt_ind; 3435 bool wowlan_pattern; 3436 bool wowlan_uc; 3437 bool wowlan_magic; 3438 bool is_hesta; 3439 bool last_a_ctrl; 3440 bool dyn_tb_bedge_en; 3441 bool pre_pwr_diff_en; 3442 bool pwr_diff_en; 3443 u8 def_tri_idx; 3444 u32 tdls_peer; 3445 struct work_struct update_beacon_work; 3446 struct rtw89_addr_cam_entry addr_cam; 3447 struct rtw89_bssid_cam_entry bssid_cam; 3448 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3449 struct rtw89_traffic_stats stats; 3450 struct rtw89_phy_rate_pattern rate_pattern; 3451 struct cfg80211_scan_request *scan_req; 3452 struct ieee80211_scan_ies *scan_ies; 3453 struct list_head general_pkt_list; 3454 struct rtw89_p2p_noa_setter p2p_noa; 3455 }; 3456 3457 enum rtw89_lv1_rcvy_step { 3458 RTW89_LV1_RCVY_STEP_1, 3459 RTW89_LV1_RCVY_STEP_2, 3460 }; 3461 3462 struct rtw89_hci_ops { 3463 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3464 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3465 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3466 void (*reset)(struct rtw89_dev *rtwdev); 3467 int (*start)(struct rtw89_dev *rtwdev); 3468 void (*stop)(struct rtw89_dev *rtwdev); 3469 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3470 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3471 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3472 3473 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3474 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3475 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3476 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3477 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3478 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3479 3480 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3481 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3482 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3483 int (*deinit)(struct rtw89_dev *rtwdev); 3484 3485 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3486 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3487 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3488 int (*napi_poll)(struct napi_struct *napi, int budget); 3489 3490 /* Deal with locks inside recovery_start and recovery_complete callbacks 3491 * by hci instance, and handle things which need to consider under SER. 3492 * e.g. turn on/off interrupts except for the one for halt notification. 3493 */ 3494 void (*recovery_start)(struct rtw89_dev *rtwdev); 3495 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3496 3497 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3498 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3499 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3500 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3501 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3502 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3503 void (*disable_intr)(struct rtw89_dev *rtwdev); 3504 void (*enable_intr)(struct rtw89_dev *rtwdev); 3505 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3506 }; 3507 3508 struct rtw89_hci_info { 3509 const struct rtw89_hci_ops *ops; 3510 enum rtw89_hci_type type; 3511 u32 rpwm_addr; 3512 u32 cpwm_addr; 3513 bool paused; 3514 }; 3515 3516 struct rtw89_chip_ops { 3517 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3518 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3519 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3520 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3521 void (*bb_reset)(struct rtw89_dev *rtwdev, 3522 enum rtw89_phy_idx phy_idx); 3523 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3524 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3525 u32 addr, u32 mask); 3526 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3527 u32 addr, u32 mask, u32 data); 3528 void (*set_channel)(struct rtw89_dev *rtwdev, 3529 const struct rtw89_chan *chan, 3530 enum rtw89_mac_idx mac_idx, 3531 enum rtw89_phy_idx phy_idx); 3532 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3533 struct rtw89_channel_help_params *p, 3534 const struct rtw89_chan *chan, 3535 enum rtw89_mac_idx mac_idx, 3536 enum rtw89_phy_idx phy_idx); 3537 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3538 enum rtw89_efuse_block block); 3539 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3540 void (*fem_setup)(struct rtw89_dev *rtwdev); 3541 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3542 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3543 void (*rfk_init)(struct rtw89_dev *rtwdev); 3544 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3545 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 3546 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3547 enum rtw89_phy_idx phy_idx); 3548 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3549 bool start); 3550 void (*rfk_track)(struct rtw89_dev *rtwdev); 3551 void (*power_trim)(struct rtw89_dev *rtwdev); 3552 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3553 const struct rtw89_chan *chan, 3554 enum rtw89_phy_idx phy_idx); 3555 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3556 enum rtw89_phy_idx phy_idx); 3557 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3558 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3559 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3560 enum rtw89_phy_idx phy_idx); 3561 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3562 struct rtw89_rx_phy_ppdu *phy_ppdu, 3563 struct ieee80211_rx_status *status); 3564 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3565 enum rtw89_phy_idx phy_idx); 3566 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3567 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3568 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3569 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3570 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3571 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3572 struct rtw89_rx_desc_info *desc_info, 3573 u8 *data, u32 data_offset); 3574 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3575 struct rtw89_tx_desc_info *desc_info, 3576 void *txdesc); 3577 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3578 struct rtw89_tx_desc_info *desc_info, 3579 void *txdesc); 3580 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3581 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3582 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3583 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3584 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3585 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3586 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3587 struct rtw89_vif *rtwvif, 3588 struct rtw89_sta *rtwsta); 3589 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3590 struct rtw89_vif *rtwvif, 3591 struct rtw89_sta *rtwsta); 3592 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3593 struct ieee80211_vif *vif, 3594 struct ieee80211_sta *sta); 3595 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3596 struct ieee80211_vif *vif, 3597 struct ieee80211_sta *sta); 3598 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3599 struct rtw89_vif *rtwvif, 3600 struct rtw89_sta *rtwsta); 3601 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3602 struct rtw89_vif *rtwvif); 3603 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3604 bool valid, struct ieee80211_ampdu_params *params); 3605 3606 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3607 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3608 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3609 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3610 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3611 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3612 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3613 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3614 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3615 }; 3616 3617 enum rtw89_dma_ch { 3618 RTW89_DMA_ACH0 = 0, 3619 RTW89_DMA_ACH1 = 1, 3620 RTW89_DMA_ACH2 = 2, 3621 RTW89_DMA_ACH3 = 3, 3622 RTW89_DMA_ACH4 = 4, 3623 RTW89_DMA_ACH5 = 5, 3624 RTW89_DMA_ACH6 = 6, 3625 RTW89_DMA_ACH7 = 7, 3626 RTW89_DMA_B0MG = 8, 3627 RTW89_DMA_B0HI = 9, 3628 RTW89_DMA_B1MG = 10, 3629 RTW89_DMA_B1HI = 11, 3630 RTW89_DMA_H2C = 12, 3631 RTW89_DMA_CH_NUM = 13 3632 }; 3633 3634 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3635 3636 enum rtw89_mlo_dbcc_mode { 3637 MLO_DBCC_NOT_SUPPORT = 1, 3638 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3639 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3640 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3641 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3642 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3643 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3644 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3645 DBCC_LEGACY = 0xffffffff, 3646 }; 3647 3648 enum rtw89_scan_be_operation { 3649 RTW89_SCAN_OP_STOP, 3650 RTW89_SCAN_OP_START, 3651 RTW89_SCAN_OP_SETPARM, 3652 RTW89_SCAN_OP_GETRPT, 3653 RTW89_SCAN_OP_NUM 3654 }; 3655 3656 enum rtw89_scan_be_mode { 3657 RTW89_SCAN_MODE_SA, 3658 RTW89_SCAN_MODE_MACC, 3659 RTW89_SCAN_MODE_NUM 3660 }; 3661 3662 enum rtw89_scan_be_opmode { 3663 RTW89_SCAN_OPMODE_NONE, 3664 RTW89_SCAN_OPMODE_TBTT, 3665 RTW89_SCAN_OPMODE_INTV, 3666 RTW89_SCAN_OPMODE_CNT, 3667 RTW89_SCAN_OPMODE_NUM, 3668 }; 3669 3670 struct rtw89_scan_option { 3671 bool enable; 3672 bool target_ch_mode; 3673 u8 num_macc_role; 3674 u8 num_opch; 3675 u8 repeat; 3676 u16 norm_pd; 3677 u16 slow_pd; 3678 u16 norm_cy; 3679 u8 opch_end; 3680 u16 delay; 3681 u64 prohib_chan; 3682 enum rtw89_phy_idx band; 3683 enum rtw89_scan_be_operation operation; 3684 enum rtw89_scan_be_mode scan_mode; 3685 enum rtw89_mlo_dbcc_mode mlo_mode; 3686 }; 3687 3688 enum rtw89_qta_mode { 3689 RTW89_QTA_SCC, 3690 RTW89_QTA_DBCC, 3691 RTW89_QTA_DLFW, 3692 RTW89_QTA_WOW, 3693 3694 /* keep last */ 3695 RTW89_QTA_INVALID, 3696 }; 3697 3698 struct rtw89_hfc_ch_cfg { 3699 u16 min; 3700 u16 max; 3701 #define grp_0 0 3702 #define grp_1 1 3703 #define grp_num 2 3704 u8 grp; 3705 }; 3706 3707 struct rtw89_hfc_ch_info { 3708 u16 aval; 3709 u16 used; 3710 }; 3711 3712 struct rtw89_hfc_pub_cfg { 3713 u16 grp0; 3714 u16 grp1; 3715 u16 pub_max; 3716 u16 wp_thrd; 3717 }; 3718 3719 struct rtw89_hfc_pub_info { 3720 u16 g0_used; 3721 u16 g1_used; 3722 u16 g0_aval; 3723 u16 g1_aval; 3724 u16 pub_aval; 3725 u16 wp_aval; 3726 }; 3727 3728 struct rtw89_hfc_prec_cfg { 3729 u16 ch011_prec; 3730 u16 h2c_prec; 3731 u16 wp_ch07_prec; 3732 u16 wp_ch811_prec; 3733 u8 ch011_full_cond; 3734 u8 h2c_full_cond; 3735 u8 wp_ch07_full_cond; 3736 u8 wp_ch811_full_cond; 3737 }; 3738 3739 struct rtw89_hfc_param { 3740 bool en; 3741 bool h2c_en; 3742 u8 mode; 3743 const struct rtw89_hfc_ch_cfg *ch_cfg; 3744 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3745 struct rtw89_hfc_pub_cfg pub_cfg; 3746 struct rtw89_hfc_pub_info pub_info; 3747 struct rtw89_hfc_prec_cfg prec_cfg; 3748 }; 3749 3750 struct rtw89_hfc_param_ini { 3751 const struct rtw89_hfc_ch_cfg *ch_cfg; 3752 const struct rtw89_hfc_pub_cfg *pub_cfg; 3753 const struct rtw89_hfc_prec_cfg *prec_cfg; 3754 u8 mode; 3755 }; 3756 3757 struct rtw89_dle_size { 3758 u16 pge_size; 3759 u16 lnk_pge_num; 3760 u16 unlnk_pge_num; 3761 /* for WiFi 7 chips below */ 3762 u32 srt_ofst; 3763 }; 3764 3765 struct rtw89_wde_quota { 3766 u16 hif; 3767 u16 wcpu; 3768 u16 pkt_in; 3769 u16 cpu_io; 3770 }; 3771 3772 struct rtw89_ple_quota { 3773 u16 cma0_tx; 3774 u16 cma1_tx; 3775 u16 c2h; 3776 u16 h2c; 3777 u16 wcpu; 3778 u16 mpdu_proc; 3779 u16 cma0_dma; 3780 u16 cma1_dma; 3781 u16 bb_rpt; 3782 u16 wd_rel; 3783 u16 cpu_io; 3784 u16 tx_rpt; 3785 /* for WiFi 7 chips below */ 3786 u16 h2d; 3787 }; 3788 3789 struct rtw89_rsvd_quota { 3790 u16 mpdu_info_tbl; 3791 u16 b0_csi; 3792 u16 b1_csi; 3793 u16 b0_lmr; 3794 u16 b1_lmr; 3795 u16 b0_ftm; 3796 u16 b1_ftm; 3797 u16 b0_smr; 3798 u16 b1_smr; 3799 u16 others; 3800 }; 3801 3802 struct rtw89_dle_rsvd_size { 3803 u32 srt_ofst; 3804 u32 size; 3805 }; 3806 3807 struct rtw89_dle_mem { 3808 enum rtw89_qta_mode mode; 3809 const struct rtw89_dle_size *wde_size; 3810 const struct rtw89_dle_size *ple_size; 3811 const struct rtw89_wde_quota *wde_min_qt; 3812 const struct rtw89_wde_quota *wde_max_qt; 3813 const struct rtw89_ple_quota *ple_min_qt; 3814 const struct rtw89_ple_quota *ple_max_qt; 3815 /* for WiFi 7 chips below */ 3816 const struct rtw89_rsvd_quota *rsvd_qt; 3817 const struct rtw89_dle_rsvd_size *rsvd0_size; 3818 const struct rtw89_dle_rsvd_size *rsvd1_size; 3819 }; 3820 3821 struct rtw89_reg_def { 3822 u32 addr; 3823 u32 mask; 3824 }; 3825 3826 struct rtw89_reg2_def { 3827 u32 addr; 3828 u32 data; 3829 }; 3830 3831 struct rtw89_reg3_def { 3832 u32 addr; 3833 u32 mask; 3834 u32 data; 3835 }; 3836 3837 struct rtw89_reg5_def { 3838 u8 flag; /* recognized by parsers */ 3839 u8 path; 3840 u32 addr; 3841 u32 mask; 3842 u32 data; 3843 }; 3844 3845 struct rtw89_reg_imr { 3846 u32 addr; 3847 u32 clr; 3848 u32 set; 3849 }; 3850 3851 struct rtw89_phy_table { 3852 const struct rtw89_reg2_def *regs; 3853 u32 n_regs; 3854 enum rtw89_rf_path rf_path; 3855 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3856 enum rtw89_rf_path rf_path, void *data); 3857 }; 3858 3859 struct rtw89_txpwr_table { 3860 const void *data; 3861 u32 size; 3862 void (*load)(struct rtw89_dev *rtwdev, 3863 const struct rtw89_txpwr_table *tbl); 3864 }; 3865 3866 struct rtw89_txpwr_rule_2ghz { 3867 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3868 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3869 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3870 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3871 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3872 }; 3873 3874 struct rtw89_txpwr_rule_5ghz { 3875 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3876 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3877 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3878 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3879 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3880 }; 3881 3882 struct rtw89_txpwr_rule_6ghz { 3883 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3884 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3885 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3886 [RTW89_6G_CH_NUM]; 3887 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3888 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3889 [RTW89_6G_CH_NUM]; 3890 }; 3891 3892 struct rtw89_tx_shape { 3893 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3894 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3895 }; 3896 3897 struct rtw89_rfe_parms { 3898 const struct rtw89_txpwr_table *byr_tbl; 3899 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3900 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3901 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3902 struct rtw89_tx_shape tx_shape; 3903 }; 3904 3905 struct rtw89_rfe_parms_conf { 3906 const struct rtw89_rfe_parms *rfe_parms; 3907 u8 rfe_type; 3908 }; 3909 3910 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3911 3912 struct rtw89_txpwr_conf { 3913 u8 rfe_type; 3914 u8 ent_sz; 3915 u32 num_ents; 3916 const void *data; 3917 }; 3918 3919 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3920 3921 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3922 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3923 memcpy(&(entry), cursor, \ 3924 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3925 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3926 (cursor) += (conf)->ent_sz, \ 3927 memcpy(&(entry), cursor, \ 3928 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3929 3930 struct rtw89_txpwr_byrate_data { 3931 struct rtw89_txpwr_conf conf; 3932 struct rtw89_txpwr_table tbl; 3933 }; 3934 3935 struct rtw89_txpwr_lmt_2ghz_data { 3936 struct rtw89_txpwr_conf conf; 3937 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3938 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3939 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3940 }; 3941 3942 struct rtw89_txpwr_lmt_5ghz_data { 3943 struct rtw89_txpwr_conf conf; 3944 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3945 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3946 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3947 }; 3948 3949 struct rtw89_txpwr_lmt_6ghz_data { 3950 struct rtw89_txpwr_conf conf; 3951 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3952 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3953 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3954 [RTW89_6G_CH_NUM]; 3955 }; 3956 3957 struct rtw89_txpwr_lmt_ru_2ghz_data { 3958 struct rtw89_txpwr_conf conf; 3959 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3960 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3961 }; 3962 3963 struct rtw89_txpwr_lmt_ru_5ghz_data { 3964 struct rtw89_txpwr_conf conf; 3965 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3966 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3967 }; 3968 3969 struct rtw89_txpwr_lmt_ru_6ghz_data { 3970 struct rtw89_txpwr_conf conf; 3971 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3972 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3973 [RTW89_6G_CH_NUM]; 3974 }; 3975 3976 struct rtw89_tx_shape_lmt_data { 3977 struct rtw89_txpwr_conf conf; 3978 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3979 }; 3980 3981 struct rtw89_tx_shape_lmt_ru_data { 3982 struct rtw89_txpwr_conf conf; 3983 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3984 }; 3985 3986 struct rtw89_rfe_data { 3987 struct rtw89_txpwr_byrate_data byrate; 3988 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3989 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3990 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3991 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3992 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3993 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3994 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3995 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3996 struct rtw89_rfe_parms rfe_parms; 3997 }; 3998 3999 struct rtw89_page_regs { 4000 u32 hci_fc_ctrl; 4001 u32 ch_page_ctrl; 4002 u32 ach_page_ctrl; 4003 u32 ach_page_info; 4004 u32 pub_page_info3; 4005 u32 pub_page_ctrl1; 4006 u32 pub_page_ctrl2; 4007 u32 pub_page_info1; 4008 u32 pub_page_info2; 4009 u32 wp_page_ctrl1; 4010 u32 wp_page_ctrl2; 4011 u32 wp_page_info1; 4012 }; 4013 4014 struct rtw89_imr_info { 4015 u32 wdrls_imr_set; 4016 u32 wsec_imr_reg; 4017 u32 wsec_imr_set; 4018 u32 mpdu_tx_imr_set; 4019 u32 mpdu_rx_imr_set; 4020 u32 sta_sch_imr_set; 4021 u32 txpktctl_imr_b0_reg; 4022 u32 txpktctl_imr_b0_clr; 4023 u32 txpktctl_imr_b0_set; 4024 u32 txpktctl_imr_b1_reg; 4025 u32 txpktctl_imr_b1_clr; 4026 u32 txpktctl_imr_b1_set; 4027 u32 wde_imr_clr; 4028 u32 wde_imr_set; 4029 u32 ple_imr_clr; 4030 u32 ple_imr_set; 4031 u32 host_disp_imr_clr; 4032 u32 host_disp_imr_set; 4033 u32 cpu_disp_imr_clr; 4034 u32 cpu_disp_imr_set; 4035 u32 other_disp_imr_clr; 4036 u32 other_disp_imr_set; 4037 u32 bbrpt_com_err_imr_reg; 4038 u32 bbrpt_chinfo_err_imr_reg; 4039 u32 bbrpt_err_imr_set; 4040 u32 bbrpt_dfs_err_imr_reg; 4041 u32 ptcl_imr_clr; 4042 u32 ptcl_imr_set; 4043 u32 cdma_imr_0_reg; 4044 u32 cdma_imr_0_clr; 4045 u32 cdma_imr_0_set; 4046 u32 cdma_imr_1_reg; 4047 u32 cdma_imr_1_clr; 4048 u32 cdma_imr_1_set; 4049 u32 phy_intf_imr_reg; 4050 u32 phy_intf_imr_clr; 4051 u32 phy_intf_imr_set; 4052 u32 rmac_imr_reg; 4053 u32 rmac_imr_clr; 4054 u32 rmac_imr_set; 4055 u32 tmac_imr_reg; 4056 u32 tmac_imr_clr; 4057 u32 tmac_imr_set; 4058 }; 4059 4060 struct rtw89_imr_table { 4061 const struct rtw89_reg_imr *regs; 4062 u32 n_regs; 4063 }; 4064 4065 struct rtw89_xtal_info { 4066 u32 xcap_reg; 4067 u32 sc_xo_mask; 4068 u32 sc_xi_mask; 4069 }; 4070 4071 struct rtw89_rrsr_cfgs { 4072 struct rtw89_reg3_def ref_rate; 4073 struct rtw89_reg3_def rsc; 4074 }; 4075 4076 struct rtw89_rfkill_regs { 4077 struct rtw89_reg3_def pinmux; 4078 struct rtw89_reg3_def mode; 4079 }; 4080 4081 struct rtw89_dig_regs { 4082 u32 seg0_pd_reg; 4083 u32 pd_lower_bound_mask; 4084 u32 pd_spatial_reuse_en; 4085 u32 bmode_pd_reg; 4086 u32 bmode_cca_rssi_limit_en; 4087 u32 bmode_pd_lower_bound_reg; 4088 u32 bmode_rssi_nocca_low_th_mask; 4089 struct rtw89_reg_def p0_lna_init; 4090 struct rtw89_reg_def p1_lna_init; 4091 struct rtw89_reg_def p0_tia_init; 4092 struct rtw89_reg_def p1_tia_init; 4093 struct rtw89_reg_def p0_rxb_init; 4094 struct rtw89_reg_def p1_rxb_init; 4095 struct rtw89_reg_def p0_p20_pagcugc_en; 4096 struct rtw89_reg_def p0_s20_pagcugc_en; 4097 struct rtw89_reg_def p1_p20_pagcugc_en; 4098 struct rtw89_reg_def p1_s20_pagcugc_en; 4099 }; 4100 4101 struct rtw89_edcca_regs { 4102 u32 edcca_level; 4103 u32 edcca_mask; 4104 u32 edcca_p_mask; 4105 u32 ppdu_level; 4106 u32 ppdu_mask; 4107 u32 rpt_a; 4108 u32 rpt_b; 4109 u32 rpt_sel; 4110 u32 rpt_sel_mask; 4111 u32 rpt_sel_be; 4112 u32 rpt_sel_be_mask; 4113 u32 tx_collision_t2r_st; 4114 u32 tx_collision_t2r_st_mask; 4115 }; 4116 4117 struct rtw89_phy_ul_tb_info { 4118 bool dyn_tb_tri_en; 4119 u8 def_if_bandedge; 4120 }; 4121 4122 struct rtw89_antdiv_stats { 4123 struct ewma_rssi cck_rssi_avg; 4124 struct ewma_rssi ofdm_rssi_avg; 4125 struct ewma_rssi non_legacy_rssi_avg; 4126 u16 pkt_cnt_cck; 4127 u16 pkt_cnt_ofdm; 4128 u16 pkt_cnt_non_legacy; 4129 u32 evm; 4130 }; 4131 4132 struct rtw89_antdiv_info { 4133 struct rtw89_antdiv_stats target_stats; 4134 struct rtw89_antdiv_stats main_stats; 4135 struct rtw89_antdiv_stats aux_stats; 4136 u8 training_count; 4137 u8 rssi_pre; 4138 bool get_stats; 4139 }; 4140 4141 enum rtw89_chanctx_state { 4142 RTW89_CHANCTX_STATE_MCC_START, 4143 RTW89_CHANCTX_STATE_MCC_STOP, 4144 }; 4145 4146 enum rtw89_chanctx_callbacks { 4147 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4148 RTW89_CHANCTX_CALLBACK_RFK, 4149 4150 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4151 }; 4152 4153 struct rtw89_chanctx_listener { 4154 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4155 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4156 }; 4157 4158 struct rtw89_chip_info { 4159 enum rtw89_core_chip_id chip_id; 4160 enum rtw89_chip_gen chip_gen; 4161 const struct rtw89_chip_ops *ops; 4162 const struct rtw89_mac_gen_def *mac_def; 4163 const struct rtw89_phy_gen_def *phy_def; 4164 const char *fw_basename; 4165 u8 fw_format_max; 4166 bool try_ce_fw; 4167 u8 bbmcu_nr; 4168 u32 needed_fw_elms; 4169 u32 fifo_size; 4170 bool small_fifo_size; 4171 u32 dle_scc_rsvd_size; 4172 u16 max_amsdu_limit; 4173 bool dis_2g_40m_ul_ofdma; 4174 u32 rsvd_ple_ofst; 4175 const struct rtw89_hfc_param_ini *hfc_param_ini; 4176 const struct rtw89_dle_mem *dle_mem; 4177 u8 wde_qempty_acq_grpnum; 4178 u8 wde_qempty_mgq_grpsel; 4179 u32 rf_base_addr[2]; 4180 u8 support_macid_num; 4181 u8 support_chanctx_num; 4182 u8 support_bands; 4183 u16 support_bandwidths; 4184 bool support_unii4; 4185 bool support_rnr; 4186 bool ul_tb_waveform_ctrl; 4187 bool ul_tb_pwr_diff; 4188 bool hw_sec_hdr; 4189 bool hw_mgmt_tx_encrypt; 4190 u8 rf_path_num; 4191 u8 tx_nss; 4192 u8 rx_nss; 4193 u8 acam_num; 4194 u8 bcam_num; 4195 u8 scam_num; 4196 u8 bacam_num; 4197 u8 bacam_dynamic_num; 4198 enum rtw89_bacam_ver bacam_ver; 4199 u8 ppdu_max_usr; 4200 4201 u8 sec_ctrl_efuse_size; 4202 u32 physical_efuse_size; 4203 u32 logical_efuse_size; 4204 u32 limit_efuse_size; 4205 u32 dav_phy_efuse_size; 4206 u32 dav_log_efuse_size; 4207 u32 phycap_addr; 4208 u32 phycap_size; 4209 const struct rtw89_efuse_block_cfg *efuse_blocks; 4210 4211 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4212 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4213 const struct rtw89_phy_table *bb_table; 4214 const struct rtw89_phy_table *bb_gain_table; 4215 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4216 const struct rtw89_phy_table *nctl_table; 4217 const struct rtw89_rfk_tbl *nctl_post_table; 4218 const struct rtw89_phy_dig_gain_table *dig_table; 4219 const struct rtw89_dig_regs *dig_regs; 4220 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4221 4222 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4223 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4224 const struct rtw89_rfe_parms *dflt_parms; 4225 const struct rtw89_chanctx_listener *chanctx_listener; 4226 4227 u8 txpwr_factor_rf; 4228 u8 txpwr_factor_mac; 4229 4230 u32 para_ver; 4231 u32 wlcx_desired; 4232 u8 btcx_desired; 4233 u8 scbd; 4234 u8 mailbox; 4235 4236 u8 afh_guard_ch; 4237 const u8 *wl_rssi_thres; 4238 const u8 *bt_rssi_thres; 4239 u8 rssi_tol; 4240 4241 u8 mon_reg_num; 4242 const struct rtw89_btc_fbtc_mreg *mon_reg; 4243 u8 rf_para_ulink_num; 4244 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4245 u8 rf_para_dlink_num; 4246 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4247 u8 ps_mode_supported; 4248 u8 low_power_hci_modes; 4249 4250 u32 h2c_cctl_func_id; 4251 u32 hci_func_en_addr; 4252 u32 h2c_desc_size; 4253 u32 txwd_body_size; 4254 u32 txwd_info_size; 4255 u32 h2c_ctrl_reg; 4256 const u32 *h2c_regs; 4257 struct rtw89_reg_def h2c_counter_reg; 4258 u32 c2h_ctrl_reg; 4259 const u32 *c2h_regs; 4260 struct rtw89_reg_def c2h_counter_reg; 4261 const struct rtw89_page_regs *page_regs; 4262 const u32 *wow_reason_reg; 4263 bool cfo_src_fd; 4264 bool cfo_hw_comp; 4265 const struct rtw89_reg_def *dcfo_comp; 4266 u8 dcfo_comp_sft; 4267 const struct rtw89_imr_info *imr_info; 4268 const struct rtw89_imr_table *imr_dmac_table; 4269 const struct rtw89_imr_table *imr_cmac_table; 4270 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4271 struct rtw89_reg_def bss_clr_vld; 4272 u32 bss_clr_map_reg; 4273 const struct rtw89_rfkill_regs *rfkill_init; 4274 struct rtw89_reg_def rfkill_get; 4275 u32 dma_ch_mask; 4276 const struct rtw89_edcca_regs *edcca_regs; 4277 const struct wiphy_wowlan_support *wowlan_stub; 4278 const struct rtw89_xtal_info *xtal_info; 4279 }; 4280 4281 union rtw89_bus_info { 4282 const struct rtw89_pci_info *pci; 4283 }; 4284 4285 struct rtw89_driver_info { 4286 const struct rtw89_chip_info *chip; 4287 const struct dmi_system_id *quirks; 4288 union rtw89_bus_info bus; 4289 }; 4290 4291 enum rtw89_hcifc_mode { 4292 RTW89_HCIFC_POH = 0, 4293 RTW89_HCIFC_STF = 1, 4294 RTW89_HCIFC_SDIO = 2, 4295 4296 /* keep last */ 4297 RTW89_HCIFC_MODE_INVALID, 4298 }; 4299 4300 struct rtw89_dle_info { 4301 const struct rtw89_rsvd_quota *rsvd_qt; 4302 enum rtw89_qta_mode qta_mode; 4303 u16 ple_pg_size; 4304 u16 ple_free_pg; 4305 u16 c0_rx_qta; 4306 u16 c1_rx_qta; 4307 }; 4308 4309 enum rtw89_host_rpr_mode { 4310 RTW89_RPR_MODE_POH = 0, 4311 RTW89_RPR_MODE_STF 4312 }; 4313 4314 #define RTW89_COMPLETION_BUF_SIZE 40 4315 #define RTW89_WAIT_COND_IDLE UINT_MAX 4316 4317 struct rtw89_completion_data { 4318 bool err; 4319 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4320 }; 4321 4322 struct rtw89_wait_info { 4323 atomic_t cond; 4324 struct completion completion; 4325 struct rtw89_completion_data data; 4326 }; 4327 4328 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4329 4330 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4331 { 4332 init_completion(&wait->completion); 4333 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4334 } 4335 4336 struct rtw89_mac_info { 4337 struct rtw89_dle_info dle_info; 4338 struct rtw89_hfc_param hfc_param; 4339 enum rtw89_qta_mode qta_mode; 4340 u8 rpwm_seq_num; 4341 u8 cpwm_seq_num; 4342 4343 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4344 struct rtw89_wait_info fw_ofld_wait; 4345 }; 4346 4347 enum rtw89_fwdl_check_type { 4348 RTW89_FWDL_CHECK_FREERTOS_DONE, 4349 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4350 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4351 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4352 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4353 }; 4354 4355 enum rtw89_fw_type { 4356 RTW89_FW_NORMAL = 1, 4357 RTW89_FW_WOWLAN = 3, 4358 RTW89_FW_NORMAL_CE = 5, 4359 RTW89_FW_BBMCU0 = 64, 4360 RTW89_FW_BBMCU1 = 65, 4361 RTW89_FW_LOGFMT = 255, 4362 }; 4363 4364 enum rtw89_fw_feature { 4365 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4366 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4367 RTW89_FW_FEATURE_TX_WAKE, 4368 RTW89_FW_FEATURE_CRASH_TRIGGER, 4369 RTW89_FW_FEATURE_NO_PACKET_DROP, 4370 RTW89_FW_FEATURE_NO_DEEP_PS, 4371 RTW89_FW_FEATURE_NO_LPS_PG, 4372 RTW89_FW_FEATURE_BEACON_FILTER, 4373 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4374 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4375 RTW89_FW_FEATURE_WOW_REASON_V1, 4376 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4377 }; 4378 4379 struct rtw89_fw_suit { 4380 enum rtw89_fw_type type; 4381 const u8 *data; 4382 u32 size; 4383 u8 major_ver; 4384 u8 minor_ver; 4385 u8 sub_ver; 4386 u8 sub_idex; 4387 u16 build_year; 4388 u16 build_mon; 4389 u16 build_date; 4390 u16 build_hour; 4391 u16 build_min; 4392 u8 cmd_ver; 4393 u8 hdr_ver; 4394 u32 commitid; 4395 }; 4396 4397 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4398 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4399 #define RTW89_FW_SUIT_VER_CODE(s) \ 4400 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4401 4402 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4403 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4404 (mfw_hdr)->ver.minor, \ 4405 (mfw_hdr)->ver.sub, \ 4406 (mfw_hdr)->ver.idx) 4407 4408 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4409 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4410 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4411 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4412 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4413 4414 struct rtw89_fw_req_info { 4415 const struct firmware *firmware; 4416 struct completion completion; 4417 }; 4418 4419 struct rtw89_fw_log { 4420 struct rtw89_fw_suit suit; 4421 bool enable; 4422 u32 last_fmt_id; 4423 u32 fmt_count; 4424 const __le32 *fmt_ids; 4425 const char *(*fmts)[]; 4426 }; 4427 4428 struct rtw89_fw_elm_info { 4429 struct rtw89_phy_table *bb_tbl; 4430 struct rtw89_phy_table *bb_gain; 4431 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4432 struct rtw89_phy_table *rf_nctl; 4433 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4434 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4435 }; 4436 4437 enum rtw89_fw_mss_dev_type { 4438 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4439 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4440 }; 4441 4442 struct rtw89_fw_secure { 4443 bool secure_boot; 4444 u32 sb_sel_mgn; 4445 u8 mss_dev_type; 4446 u8 mss_cust_idx; 4447 u8 mss_key_num; 4448 }; 4449 4450 struct rtw89_fw_info { 4451 struct rtw89_fw_req_info req; 4452 int fw_format; 4453 u8 h2c_seq; 4454 u8 rec_seq; 4455 u8 h2c_counter; 4456 u8 c2h_counter; 4457 struct rtw89_fw_suit normal; 4458 struct rtw89_fw_suit wowlan; 4459 struct rtw89_fw_suit bbmcu0; 4460 struct rtw89_fw_suit bbmcu1; 4461 struct rtw89_fw_log log; 4462 u32 feature_map; 4463 struct rtw89_fw_elm_info elm_info; 4464 struct rtw89_fw_secure sec; 4465 }; 4466 4467 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4468 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4469 4470 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4471 ((_fw)->feature_map |= BIT(_fw_feature)) 4472 4473 struct rtw89_cam_info { 4474 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4475 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4476 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4477 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4478 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4479 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4480 }; 4481 4482 enum rtw89_sar_sources { 4483 RTW89_SAR_SOURCE_NONE, 4484 RTW89_SAR_SOURCE_COMMON, 4485 4486 RTW89_SAR_SOURCE_NR, 4487 }; 4488 4489 enum rtw89_sar_subband { 4490 RTW89_SAR_2GHZ_SUBBAND, 4491 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4492 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4493 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4494 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4495 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4496 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4497 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4498 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4499 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4500 4501 RTW89_SAR_SUBBAND_NR, 4502 }; 4503 4504 struct rtw89_sar_cfg_common { 4505 bool set[RTW89_SAR_SUBBAND_NR]; 4506 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4507 }; 4508 4509 struct rtw89_sar_info { 4510 /* used to decide how to acces SAR cfg union */ 4511 enum rtw89_sar_sources src; 4512 4513 /* reserved for different knids of SAR cfg struct. 4514 * supposed that a single cfg struct cannot handle various SAR sources. 4515 */ 4516 union { 4517 struct rtw89_sar_cfg_common cfg_common; 4518 }; 4519 }; 4520 4521 enum rtw89_tas_state { 4522 RTW89_TAS_STATE_DPR_OFF, 4523 RTW89_TAS_STATE_DPR_ON, 4524 RTW89_TAS_STATE_DPR_FORBID, 4525 }; 4526 4527 #define RTW89_TAS_MAX_WINDOW 50 4528 struct rtw89_tas_info { 4529 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4530 s32 total_txpwr; 4531 u8 cur_idx; 4532 s8 dpr_gap; 4533 s8 delta; 4534 enum rtw89_tas_state state; 4535 bool enable; 4536 }; 4537 4538 struct rtw89_chanctx_cfg { 4539 enum rtw89_chanctx_idx idx; 4540 int ref_count; 4541 }; 4542 4543 enum rtw89_chanctx_changes { 4544 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4545 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4546 RTW89_CHANCTX_P2P_PS_CHANGE, 4547 RTW89_CHANCTX_BT_SLOT_CHANGE, 4548 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4549 4550 NUM_OF_RTW89_CHANCTX_CHANGES, 4551 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4552 }; 4553 4554 enum rtw89_entity_mode { 4555 RTW89_ENTITY_MODE_SCC, 4556 RTW89_ENTITY_MODE_MCC_PREPARE, 4557 RTW89_ENTITY_MODE_MCC, 4558 4559 NUM_OF_RTW89_ENTITY_MODE, 4560 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4561 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4562 }; 4563 4564 struct rtw89_chanctx { 4565 struct cfg80211_chan_def chandef; 4566 struct rtw89_chan chan; 4567 struct rtw89_chan_rcd rcd; 4568 4569 /* only assigned when running with chanctx_ops */ 4570 struct rtw89_chanctx_cfg *cfg; 4571 }; 4572 4573 struct rtw89_edcca_bak { 4574 u8 a; 4575 u8 p; 4576 u8 ppdu; 4577 u8 th_old; 4578 }; 4579 4580 enum rtw89_dm_type { 4581 RTW89_DM_DYNAMIC_EDCCA, 4582 }; 4583 4584 struct rtw89_hal { 4585 u32 rx_fltr; 4586 u8 cv; 4587 u8 acv; 4588 u32 antenna_tx; 4589 u32 antenna_rx; 4590 u8 tx_nss; 4591 u8 rx_nss; 4592 bool tx_path_diversity; 4593 bool ant_diversity; 4594 bool ant_diversity_fixed; 4595 bool support_cckpd; 4596 bool support_igi; 4597 atomic_t roc_entity_idx; 4598 4599 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4600 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4601 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4602 struct cfg80211_chan_def roc_chandef; 4603 4604 bool entity_active; 4605 bool entity_pause; 4606 enum rtw89_entity_mode entity_mode; 4607 4608 struct rtw89_edcca_bak edcca_bak; 4609 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4610 }; 4611 4612 #define RTW89_MAX_MAC_ID_NUM 128 4613 #define RTW89_MAX_PKT_OFLD_NUM 255 4614 4615 enum rtw89_flags { 4616 RTW89_FLAG_POWERON, 4617 RTW89_FLAG_DMAC_FUNC, 4618 RTW89_FLAG_CMAC0_FUNC, 4619 RTW89_FLAG_CMAC1_FUNC, 4620 RTW89_FLAG_FW_RDY, 4621 RTW89_FLAG_RUNNING, 4622 RTW89_FLAG_PROBE_DONE, 4623 RTW89_FLAG_BFEE_MON, 4624 RTW89_FLAG_BFEE_EN, 4625 RTW89_FLAG_BFEE_TIMER_KEEP, 4626 RTW89_FLAG_NAPI_RUNNING, 4627 RTW89_FLAG_LEISURE_PS, 4628 RTW89_FLAG_LOW_POWER_MODE, 4629 RTW89_FLAG_INACTIVE_PS, 4630 RTW89_FLAG_CRASH_SIMULATING, 4631 RTW89_FLAG_SER_HANDLING, 4632 RTW89_FLAG_WOWLAN, 4633 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4634 RTW89_FLAG_CHANGING_INTERFACE, 4635 RTW89_FLAG_HW_RFKILL_STATE, 4636 4637 NUM_OF_RTW89_FLAGS, 4638 }; 4639 4640 enum rtw89_quirks { 4641 RTW89_QUIRK_PCI_BER, 4642 4643 NUM_OF_RTW89_QUIRKS, 4644 }; 4645 4646 enum rtw89_pkt_drop_sel { 4647 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4648 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4649 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4650 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4651 RTW89_PKT_DROP_SEL_MACID_ALL, 4652 RTW89_PKT_DROP_SEL_MG0_ONCE, 4653 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4654 RTW89_PKT_DROP_SEL_HIQ_PORT, 4655 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4656 RTW89_PKT_DROP_SEL_BAND, 4657 RTW89_PKT_DROP_SEL_BAND_ONCE, 4658 RTW89_PKT_DROP_SEL_REL_MACID, 4659 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4660 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4661 }; 4662 4663 struct rtw89_pkt_drop_params { 4664 enum rtw89_pkt_drop_sel sel; 4665 enum rtw89_mac_idx mac_band; 4666 u8 macid; 4667 u8 port; 4668 u8 mbssid; 4669 bool tf_trs; 4670 u32 macid_band_sel[4]; 4671 }; 4672 4673 struct rtw89_pkt_stat { 4674 u16 beacon_nr; 4675 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4676 }; 4677 4678 DECLARE_EWMA(thermal, 4, 4); 4679 4680 struct rtw89_phy_stat { 4681 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4682 struct rtw89_pkt_stat cur_pkt_stat; 4683 struct rtw89_pkt_stat last_pkt_stat; 4684 }; 4685 4686 enum rtw89_rfk_report_state { 4687 RTW89_RFK_STATE_START = 0x0, 4688 RTW89_RFK_STATE_OK = 0x1, 4689 RTW89_RFK_STATE_FAIL = 0x2, 4690 RTW89_RFK_STATE_TIMEOUT = 0x3, 4691 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4692 }; 4693 4694 struct rtw89_rfk_wait_info { 4695 struct completion completion; 4696 ktime_t start_time; 4697 enum rtw89_rfk_report_state state; 4698 u8 version; 4699 }; 4700 4701 #define RTW89_DACK_PATH_NR 2 4702 #define RTW89_DACK_IDX_NR 2 4703 #define RTW89_DACK_MSBK_NR 16 4704 struct rtw89_dack_info { 4705 bool dack_done; 4706 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4707 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4708 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4709 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4710 u32 dack_cnt; 4711 bool addck_timeout[RTW89_DACK_PATH_NR]; 4712 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4713 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4714 }; 4715 4716 enum rtw89_rfk_chs_nrs { 4717 __RTW89_RFK_CHS_NR_V0 = 2, 4718 __RTW89_RFK_CHS_NR_V1 = 3, 4719 4720 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 4721 }; 4722 4723 struct rtw89_rfk_mcc_info { 4724 u8 ch[RTW89_RFK_CHS_NR]; 4725 u8 band[RTW89_RFK_CHS_NR]; 4726 u8 bw[RTW89_RFK_CHS_NR]; 4727 u8 table_idx; 4728 }; 4729 4730 #define RTW89_IQK_CHS_NR 2 4731 #define RTW89_IQK_PATH_NR 4 4732 4733 struct rtw89_lck_info { 4734 u8 thermal[RF_PATH_MAX]; 4735 }; 4736 4737 struct rtw89_rx_dck_info { 4738 u8 thermal[RF_PATH_MAX]; 4739 }; 4740 4741 struct rtw89_iqk_info { 4742 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4743 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4744 bool lok_fail[RTW89_IQK_PATH_NR]; 4745 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4746 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4747 u32 iqk_fail_cnt; 4748 bool is_iqk_init; 4749 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4750 u8 iqk_band[RTW89_IQK_PATH_NR]; 4751 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4752 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4753 u8 iqk_times; 4754 u8 version; 4755 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4756 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4757 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4758 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4759 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4760 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4761 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4762 bool is_nbiqk; 4763 bool iqk_fft_en; 4764 bool iqk_xym_en; 4765 bool iqk_sram_en; 4766 bool iqk_cfir_en; 4767 u32 syn1to2; 4768 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4769 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4770 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4771 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4772 }; 4773 4774 #define RTW89_DPK_RF_PATH 2 4775 #define RTW89_DPK_AVG_THERMAL_NUM 8 4776 #define RTW89_DPK_BKUP_NUM 2 4777 struct rtw89_dpk_bkup_para { 4778 enum rtw89_band band; 4779 enum rtw89_bandwidth bw; 4780 u8 ch; 4781 bool path_ok; 4782 u8 mdpd_en; 4783 u8 txagc_dpk; 4784 u8 ther_dpk; 4785 u8 gs; 4786 u16 pwsf; 4787 }; 4788 4789 struct rtw89_dpk_info { 4790 bool is_dpk_enable; 4791 bool is_dpk_reload_en; 4792 u8 dpk_gs[RTW89_PHY_MAX]; 4793 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4794 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4795 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4796 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4797 u8 cur_idx[RTW89_DPK_RF_PATH]; 4798 u8 cur_k_set; 4799 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4800 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 4801 u32 dpk_order[RTW89_DPK_RF_PATH]; 4802 }; 4803 4804 struct rtw89_fem_info { 4805 bool elna_2g; 4806 bool elna_5g; 4807 bool epa_2g; 4808 bool epa_5g; 4809 bool epa_6g; 4810 }; 4811 4812 struct rtw89_phy_ch_info { 4813 u8 rssi_min; 4814 u16 rssi_min_macid; 4815 u8 pre_rssi_min; 4816 u8 rssi_max; 4817 u16 rssi_max_macid; 4818 u8 rxsc_160; 4819 u8 rxsc_80; 4820 u8 rxsc_40; 4821 u8 rxsc_20; 4822 u8 rxsc_l; 4823 u8 is_noisy; 4824 }; 4825 4826 struct rtw89_agc_gaincode_set { 4827 u8 lna_idx; 4828 u8 tia_idx; 4829 u8 rxb_idx; 4830 }; 4831 4832 #define IGI_RSSI_TH_NUM 5 4833 #define FA_TH_NUM 4 4834 #define LNA_GAIN_NUM 7 4835 #define TIA_GAIN_NUM 2 4836 struct rtw89_dig_info { 4837 struct rtw89_agc_gaincode_set cur_gaincode; 4838 bool force_gaincode_idx_en; 4839 struct rtw89_agc_gaincode_set force_gaincode; 4840 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4841 u16 fa_th[FA_TH_NUM]; 4842 u8 igi_rssi; 4843 u8 igi_fa_rssi; 4844 u8 fa_rssi_ofst; 4845 u8 dyn_igi_max; 4846 u8 dyn_igi_min; 4847 bool dyn_pd_th_en; 4848 u8 dyn_pd_th_max; 4849 u8 pd_low_th_ofst; 4850 u8 ib_pbk; 4851 s8 ib_pkpwr; 4852 s8 lna_gain_a[LNA_GAIN_NUM]; 4853 s8 lna_gain_g[LNA_GAIN_NUM]; 4854 s8 *lna_gain; 4855 s8 tia_gain_a[TIA_GAIN_NUM]; 4856 s8 tia_gain_g[TIA_GAIN_NUM]; 4857 s8 *tia_gain; 4858 bool is_linked_pre; 4859 bool bypass_dig; 4860 }; 4861 4862 enum rtw89_multi_cfo_mode { 4863 RTW89_PKT_BASED_AVG_MODE = 0, 4864 RTW89_ENTRY_BASED_AVG_MODE = 1, 4865 RTW89_TP_BASED_AVG_MODE = 2, 4866 }; 4867 4868 enum rtw89_phy_cfo_status { 4869 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4870 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4871 RTW89_PHY_DCFO_STATE_HOLD = 2, 4872 RTW89_PHY_DCFO_STATE_MAX 4873 }; 4874 4875 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4876 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4877 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4878 }; 4879 4880 struct rtw89_cfo_tracking_info { 4881 u16 cfo_timer_ms; 4882 bool cfo_trig_by_timer_en; 4883 enum rtw89_phy_cfo_status phy_cfo_status; 4884 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4885 u8 phy_cfo_trk_cnt; 4886 bool is_adjust; 4887 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4888 bool apply_compensation; 4889 u8 crystal_cap; 4890 u8 crystal_cap_default; 4891 u8 def_x_cap; 4892 s8 x_cap_ofst; 4893 u32 sta_cfo_tolerance; 4894 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4895 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4896 s32 cfo_avg_pre; 4897 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4898 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4899 s32 dcfo_avg; 4900 s32 dcfo_avg_pre; 4901 u32 packet_count; 4902 u32 packet_count_pre; 4903 s32 residual_cfo_acc; 4904 u8 phy_cfotrk_state; 4905 u8 phy_cfotrk_cnt; 4906 bool divergence_lock_en; 4907 u8 x_cap_lb; 4908 u8 x_cap_ub; 4909 u8 lock_cnt; 4910 }; 4911 4912 enum rtw89_tssi_mode { 4913 RTW89_TSSI_NORMAL = 0, 4914 RTW89_TSSI_SCAN = 1, 4915 }; 4916 4917 enum rtw89_tssi_alimk_band { 4918 TSSI_ALIMK_2G = 0, 4919 TSSI_ALIMK_5GL, 4920 TSSI_ALIMK_5GM, 4921 TSSI_ALIMK_5GH, 4922 TSSI_ALIMK_MAX 4923 }; 4924 4925 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4926 #define TSSI_TRIM_CH_GROUP_NUM 8 4927 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4928 4929 #define TSSI_CCK_CH_GROUP_NUM 6 4930 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4931 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4932 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4933 #define TSSI_MCS_CH_GROUP_NUM \ 4934 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4935 #define TSSI_MAX_CH_NUM 67 4936 #define TSSI_ALIMK_VALUE_NUM 8 4937 4938 struct rtw89_tssi_info { 4939 u8 thermal[RF_PATH_MAX]; 4940 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4941 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4942 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4943 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4944 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4945 s8 extra_ofst[RF_PATH_MAX]; 4946 bool tssi_tracking_check[RF_PATH_MAX]; 4947 u8 default_txagc_offset[RF_PATH_MAX]; 4948 u32 base_thermal[RF_PATH_MAX]; 4949 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4950 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4951 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4952 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4953 u32 tssi_alimk_time; 4954 }; 4955 4956 struct rtw89_power_trim_info { 4957 bool pg_thermal_trim; 4958 bool pg_pa_bias_trim; 4959 u8 thermal_trim[RF_PATH_MAX]; 4960 u8 pa_bias_trim[RF_PATH_MAX]; 4961 u8 pad_bias_trim[RF_PATH_MAX]; 4962 }; 4963 4964 struct rtw89_regd { 4965 char alpha2[3]; 4966 u8 txpwr_regd[RTW89_BAND_NUM]; 4967 }; 4968 4969 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4970 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 4971 #define RTW89_5GHZ_UNII4_START_INDEX 25 4972 4973 struct rtw89_regulatory_info { 4974 const struct rtw89_regd *regd; 4975 enum rtw89_reg_6ghz_power reg_6ghz_power; 4976 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 4977 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 4978 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4979 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 4980 }; 4981 4982 enum rtw89_ifs_clm_application { 4983 RTW89_IFS_CLM_INIT = 0, 4984 RTW89_IFS_CLM_BACKGROUND = 1, 4985 RTW89_IFS_CLM_ACS = 2, 4986 RTW89_IFS_CLM_DIG = 3, 4987 RTW89_IFS_CLM_TDMA_DIG = 4, 4988 RTW89_IFS_CLM_DBG = 5, 4989 RTW89_IFS_CLM_DBG_MANUAL = 6 4990 }; 4991 4992 enum rtw89_env_racing_lv { 4993 RTW89_RAC_RELEASE = 0, 4994 RTW89_RAC_LV_1 = 1, 4995 RTW89_RAC_LV_2 = 2, 4996 RTW89_RAC_LV_3 = 3, 4997 RTW89_RAC_LV_4 = 4, 4998 RTW89_RAC_MAX_NUM = 5 4999 }; 5000 5001 struct rtw89_ccx_para_info { 5002 enum rtw89_env_racing_lv rac_lv; 5003 u16 mntr_time; 5004 u8 nhm_manual_th_ofst; 5005 u8 nhm_manual_th0; 5006 enum rtw89_ifs_clm_application ifs_clm_app; 5007 u32 ifs_clm_manual_th_times; 5008 u32 ifs_clm_manual_th0; 5009 u8 fahm_manual_th_ofst; 5010 u8 fahm_manual_th0; 5011 u8 fahm_numer_opt; 5012 u8 fahm_denom_opt; 5013 }; 5014 5015 enum rtw89_ccx_edcca_opt_sc_idx { 5016 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5017 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5018 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5019 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5020 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5021 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5022 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5023 RTW89_CCX_EDCCA_SEG1_S3 = 7 5024 }; 5025 5026 enum rtw89_ccx_edcca_opt_bw_idx { 5027 RTW89_CCX_EDCCA_BW20_0 = 0, 5028 RTW89_CCX_EDCCA_BW20_1 = 1, 5029 RTW89_CCX_EDCCA_BW20_2 = 2, 5030 RTW89_CCX_EDCCA_BW20_3 = 3, 5031 RTW89_CCX_EDCCA_BW20_4 = 4, 5032 RTW89_CCX_EDCCA_BW20_5 = 5, 5033 RTW89_CCX_EDCCA_BW20_6 = 6, 5034 RTW89_CCX_EDCCA_BW20_7 = 7 5035 }; 5036 5037 #define RTW89_NHM_TH_NUM 11 5038 #define RTW89_FAHM_TH_NUM 11 5039 #define RTW89_NHM_RPT_NUM 12 5040 #define RTW89_FAHM_RPT_NUM 12 5041 #define RTW89_IFS_CLM_NUM 4 5042 struct rtw89_env_monitor_info { 5043 u8 ccx_watchdog_result; 5044 bool ccx_ongoing; 5045 u8 ccx_rac_lv; 5046 bool ccx_manual_ctrl; 5047 u16 ifs_clm_mntr_time; 5048 enum rtw89_ifs_clm_application ifs_clm_app; 5049 u16 ccx_period; 5050 u8 ccx_unit_idx; 5051 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5052 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5053 u16 ifs_clm_tx; 5054 u16 ifs_clm_edcca_excl_cca; 5055 u16 ifs_clm_ofdmfa; 5056 u16 ifs_clm_ofdmcca_excl_fa; 5057 u16 ifs_clm_cckfa; 5058 u16 ifs_clm_cckcca_excl_fa; 5059 u16 ifs_clm_total_ifs; 5060 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5061 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5062 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5063 u8 ifs_clm_tx_ratio; 5064 u8 ifs_clm_edcca_excl_cca_ratio; 5065 u8 ifs_clm_cck_fa_ratio; 5066 u8 ifs_clm_ofdm_fa_ratio; 5067 u8 ifs_clm_cck_cca_excl_fa_ratio; 5068 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5069 u16 ifs_clm_cck_fa_permil; 5070 u16 ifs_clm_ofdm_fa_permil; 5071 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5072 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5073 }; 5074 5075 enum rtw89_ser_rcvy_step { 5076 RTW89_SER_DRV_STOP_TX, 5077 RTW89_SER_DRV_STOP_RX, 5078 RTW89_SER_DRV_STOP_RUN, 5079 RTW89_SER_HAL_STOP_DMA, 5080 RTW89_SER_SUPPRESS_LOG, 5081 RTW89_NUM_OF_SER_FLAGS 5082 }; 5083 5084 struct rtw89_ser { 5085 u8 state; 5086 u8 alarm_event; 5087 bool prehandle_l1; 5088 5089 struct work_struct ser_hdl_work; 5090 struct delayed_work ser_alarm_work; 5091 const struct state_ent *st_tbl; 5092 const struct event_ent *ev_tbl; 5093 struct list_head msg_q; 5094 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5095 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5096 }; 5097 5098 enum rtw89_mac_ax_ps_mode { 5099 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5100 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5101 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5102 RTW89_MAC_AX_PS_MODE_MAX = 3, 5103 }; 5104 5105 enum rtw89_last_rpwm_mode { 5106 RTW89_LAST_RPWM_PS = 0x0, 5107 RTW89_LAST_RPWM_ACTIVE = 0x6, 5108 }; 5109 5110 struct rtw89_lps_parm { 5111 u8 macid; 5112 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5113 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5114 }; 5115 5116 struct rtw89_ppdu_sts_info { 5117 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 5118 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 5119 }; 5120 5121 struct rtw89_early_h2c { 5122 struct list_head list; 5123 u8 *h2c; 5124 u16 h2c_len; 5125 }; 5126 5127 struct rtw89_hw_scan_info { 5128 struct ieee80211_vif *scanning_vif; 5129 struct list_head pkt_list[NUM_NL80211_BANDS]; 5130 struct rtw89_chan op_chan; 5131 bool abort; 5132 u32 last_chan_idx; 5133 }; 5134 5135 enum rtw89_phy_bb_gain_band { 5136 RTW89_BB_GAIN_BAND_2G = 0, 5137 RTW89_BB_GAIN_BAND_5G_L = 1, 5138 RTW89_BB_GAIN_BAND_5G_M = 2, 5139 RTW89_BB_GAIN_BAND_5G_H = 3, 5140 RTW89_BB_GAIN_BAND_6G_L = 4, 5141 RTW89_BB_GAIN_BAND_6G_M = 5, 5142 RTW89_BB_GAIN_BAND_6G_H = 6, 5143 RTW89_BB_GAIN_BAND_6G_UH = 7, 5144 5145 RTW89_BB_GAIN_BAND_NR, 5146 }; 5147 5148 enum rtw89_phy_gain_band_be { 5149 RTW89_BB_GAIN_BAND_2G_BE = 0, 5150 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5151 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5152 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5153 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5154 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5155 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5156 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5157 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5158 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5159 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5160 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5161 5162 RTW89_BB_GAIN_BAND_NR_BE, 5163 }; 5164 5165 enum rtw89_phy_bb_bw_be { 5166 RTW89_BB_BW_20_40 = 0, 5167 RTW89_BB_BW_80_160_320 = 1, 5168 5169 RTW89_BB_BW_NR_BE, 5170 }; 5171 5172 enum rtw89_bw20_sc { 5173 RTW89_BW20_SC_20M = 1, 5174 RTW89_BW20_SC_40M = 2, 5175 RTW89_BW20_SC_80M = 4, 5176 RTW89_BW20_SC_160M = 8, 5177 RTW89_BW20_SC_320M = 16, 5178 }; 5179 5180 enum rtw89_cmac_table_bw { 5181 RTW89_CMAC_BW_20M = 0, 5182 RTW89_CMAC_BW_40M = 1, 5183 RTW89_CMAC_BW_80M = 2, 5184 RTW89_CMAC_BW_160M = 3, 5185 RTW89_CMAC_BW_320M = 4, 5186 5187 RTW89_CMAC_BW_NR, 5188 }; 5189 5190 enum rtw89_phy_bb_rxsc_num { 5191 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5192 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5193 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5194 }; 5195 5196 struct rtw89_phy_bb_gain_info { 5197 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5198 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5199 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5200 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5201 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5202 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5203 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5204 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5205 [RTW89_BB_RXSC_NUM_40]; 5206 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5207 [RTW89_BB_RXSC_NUM_80]; 5208 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5209 [RTW89_BB_RXSC_NUM_160]; 5210 }; 5211 5212 struct rtw89_phy_bb_gain_info_be { 5213 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5214 [LNA_GAIN_NUM]; 5215 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5216 [TIA_GAIN_NUM]; 5217 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5218 [RF_PATH_MAX][LNA_GAIN_NUM]; 5219 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5220 [RF_PATH_MAX][LNA_GAIN_NUM]; 5221 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5222 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5223 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5224 [RTW89_BW20_SC_20M]; 5225 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5226 [RTW89_BW20_SC_40M]; 5227 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5228 [RTW89_BW20_SC_80M]; 5229 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5230 [RTW89_BW20_SC_160M]; 5231 }; 5232 5233 struct rtw89_phy_efuse_gain { 5234 bool offset_valid; 5235 bool comp_valid; 5236 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5237 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5238 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5239 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5240 }; 5241 5242 #define RTW89_MAX_PATTERN_NUM 18 5243 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5244 #define RTW89_MAX_PATTERN_SIZE 128 5245 5246 struct rtw89_wow_cam_info { 5247 bool r_w; 5248 u8 idx; 5249 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5250 u16 crc; 5251 bool negative_pattern_match; 5252 bool skip_mac_hdr; 5253 bool uc; 5254 bool mc; 5255 bool bc; 5256 bool valid; 5257 }; 5258 5259 struct rtw89_wow_key_info { 5260 u8 ptk_tx_iv[8]; 5261 u8 valid_check; 5262 u8 symbol_check_en; 5263 u8 gtk_keyidx; 5264 u8 rsvd[5]; 5265 u8 ptk_rx_iv[8]; 5266 u8 gtk_rx_iv[4][8]; 5267 } __packed; 5268 5269 struct rtw89_wow_gtk_info { 5270 u8 kck[32]; 5271 u8 kek[32]; 5272 u8 tk1[16]; 5273 u8 txmickey[8]; 5274 u8 rxmickey[8]; 5275 __le32 igtk_keyid; 5276 __le64 ipn; 5277 u8 igtk[2][32]; 5278 u8 psk[32]; 5279 } __packed; 5280 5281 struct rtw89_wow_aoac_report { 5282 u8 rpt_ver; 5283 u8 sec_type; 5284 u8 key_idx; 5285 u8 pattern_idx; 5286 u8 rekey_ok; 5287 u8 ptk_tx_iv[8]; 5288 u8 eapol_key_replay_count[8]; 5289 u8 gtk[32]; 5290 u8 ptk_rx_iv[8]; 5291 u8 gtk_rx_iv[4][8]; 5292 u64 igtk_key_id; 5293 u64 igtk_ipn; 5294 u8 igtk[32]; 5295 u8 csa_pri_ch; 5296 u8 csa_bw; 5297 u8 csa_ch_offset; 5298 u8 csa_chsw_failed; 5299 u8 csa_ch_band; 5300 }; 5301 5302 struct rtw89_wow_param { 5303 struct ieee80211_vif *wow_vif; 5304 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5305 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5306 struct rtw89_wow_key_info key_info; 5307 struct rtw89_wow_gtk_info gtk_info; 5308 struct rtw89_wow_aoac_report aoac_rpt; 5309 u8 pattern_cnt; 5310 u8 ptk_alg; 5311 u8 gtk_alg; 5312 u8 ptk_keyidx; 5313 u8 akm; 5314 5315 bool pno_inited; 5316 struct list_head pno_pkt_list; 5317 struct cfg80211_sched_scan_request *nd_config; 5318 }; 5319 5320 struct rtw89_mcc_limit { 5321 bool enable; 5322 u16 max_tob; /* TU; max time offset behind */ 5323 u16 max_toa; /* TU; max time offset ahead */ 5324 u16 max_dur; /* TU */ 5325 }; 5326 5327 struct rtw89_mcc_policy { 5328 u8 c2h_rpt; 5329 u8 tx_null_early; 5330 u8 dis_tx_null; 5331 u8 in_curr_ch; 5332 u8 dis_sw_retry; 5333 u8 sw_retry_count; 5334 }; 5335 5336 struct rtw89_mcc_role { 5337 struct rtw89_vif *rtwvif; 5338 struct rtw89_mcc_policy policy; 5339 struct rtw89_mcc_limit limit; 5340 5341 /* only valid when running with FW MRC mechanism */ 5342 u8 slot_idx; 5343 5344 /* byte-array in LE order for FW */ 5345 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5346 5347 u16 duration; /* TU */ 5348 u16 beacon_interval; /* TU */ 5349 bool is_2ghz; 5350 bool is_go; 5351 bool is_gc; 5352 }; 5353 5354 struct rtw89_mcc_bt_role { 5355 u16 duration; /* TU */ 5356 }; 5357 5358 struct rtw89_mcc_courtesy { 5359 bool enable; 5360 u8 slot_num; 5361 u8 macid_src; 5362 u8 macid_tgt; 5363 }; 5364 5365 enum rtw89_mcc_plan { 5366 RTW89_MCC_PLAN_TAIL_BT, 5367 RTW89_MCC_PLAN_MID_BT, 5368 RTW89_MCC_PLAN_NO_BT, 5369 5370 NUM_OF_RTW89_MCC_PLAN, 5371 }; 5372 5373 struct rtw89_mcc_pattern { 5374 s16 tob_ref; /* TU; time offset behind of reference role */ 5375 s16 toa_ref; /* TU; time offset ahead of reference role */ 5376 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5377 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5378 5379 enum rtw89_mcc_plan plan; 5380 struct rtw89_mcc_courtesy courtesy; 5381 }; 5382 5383 struct rtw89_mcc_sync { 5384 bool enable; 5385 u16 offset; /* TU */ 5386 u8 macid_src; 5387 u8 band_src; 5388 u8 port_src; 5389 u8 macid_tgt; 5390 u8 band_tgt; 5391 u8 port_tgt; 5392 }; 5393 5394 struct rtw89_mcc_config { 5395 struct rtw89_mcc_pattern pattern; 5396 struct rtw89_mcc_sync sync; 5397 u64 start_tsf; 5398 u16 mcc_interval; /* TU */ 5399 u16 beacon_offset; /* TU */ 5400 }; 5401 5402 enum rtw89_mcc_mode { 5403 RTW89_MCC_MODE_GO_STA, 5404 RTW89_MCC_MODE_GC_STA, 5405 }; 5406 5407 struct rtw89_mcc_info { 5408 struct rtw89_wait_info wait; 5409 5410 u8 group; 5411 enum rtw89_mcc_mode mode; 5412 struct rtw89_mcc_role role_ref; /* reference role */ 5413 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5414 struct rtw89_mcc_bt_role bt_role; 5415 struct rtw89_mcc_config config; 5416 }; 5417 5418 struct rtw89_dev { 5419 struct ieee80211_hw *hw; 5420 struct device *dev; 5421 const struct ieee80211_ops *ops; 5422 5423 bool dbcc_en; 5424 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5425 struct rtw89_hw_scan_info scan_info; 5426 const struct rtw89_chip_info *chip; 5427 const struct rtw89_pci_info *pci_info; 5428 const struct rtw89_rfe_parms *rfe_parms; 5429 struct rtw89_hal hal; 5430 struct rtw89_mcc_info mcc; 5431 struct rtw89_mac_info mac; 5432 struct rtw89_fw_info fw; 5433 struct rtw89_hci_info hci; 5434 struct rtw89_efuse efuse; 5435 struct rtw89_traffic_stats stats; 5436 struct rtw89_rfe_data *rfe_data; 5437 5438 /* ensures exclusive access from mac80211 callbacks */ 5439 struct mutex mutex; 5440 struct list_head rtwvifs_list; 5441 /* used to protect rf read write */ 5442 struct mutex rf_mutex; 5443 struct workqueue_struct *txq_wq; 5444 struct work_struct txq_work; 5445 struct delayed_work txq_reinvoke_work; 5446 /* used to protect ba_list and forbid_ba_list */ 5447 spinlock_t ba_lock; 5448 /* txqs to setup ba session */ 5449 struct list_head ba_list; 5450 /* txqs to forbid ba session */ 5451 struct list_head forbid_ba_list; 5452 struct work_struct ba_work; 5453 /* used to protect rpwm */ 5454 spinlock_t rpwm_lock; 5455 5456 struct rtw89_cam_info cam_info; 5457 5458 struct sk_buff_head c2h_queue; 5459 struct work_struct c2h_work; 5460 struct work_struct ips_work; 5461 struct work_struct load_firmware_work; 5462 struct work_struct cancel_6ghz_probe_work; 5463 5464 struct list_head early_h2c_list; 5465 5466 struct rtw89_ser ser; 5467 5468 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5469 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5470 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5471 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5472 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5473 5474 struct rtw89_phy_stat phystat; 5475 struct rtw89_rfk_wait_info rfk_wait; 5476 struct rtw89_dack_info dack; 5477 struct rtw89_iqk_info iqk; 5478 struct rtw89_dpk_info dpk; 5479 struct rtw89_rfk_mcc_info rfk_mcc; 5480 struct rtw89_lck_info lck; 5481 struct rtw89_rx_dck_info rx_dck; 5482 bool is_tssi_mode[RF_PATH_MAX]; 5483 bool is_bt_iqk_timeout; 5484 5485 struct rtw89_fem_info fem; 5486 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5487 struct rtw89_tssi_info tssi; 5488 struct rtw89_power_trim_info pwr_trim; 5489 5490 struct rtw89_cfo_tracking_info cfo_tracking; 5491 struct rtw89_env_monitor_info env_monitor; 5492 struct rtw89_dig_info dig; 5493 struct rtw89_phy_ch_info ch_info; 5494 union { 5495 struct rtw89_phy_bb_gain_info ax; 5496 struct rtw89_phy_bb_gain_info_be be; 5497 } bb_gain; 5498 struct rtw89_phy_efuse_gain efuse_gain; 5499 struct rtw89_phy_ul_tb_info ul_tb_info; 5500 struct rtw89_antdiv_info antdiv; 5501 5502 struct delayed_work track_work; 5503 struct delayed_work chanctx_work; 5504 struct delayed_work coex_act1_work; 5505 struct delayed_work coex_bt_devinfo_work; 5506 struct delayed_work coex_rfk_chk_work; 5507 struct delayed_work cfo_track_work; 5508 struct delayed_work forbid_ba_work; 5509 struct delayed_work roc_work; 5510 struct delayed_work antdiv_work; 5511 struct rtw89_ppdu_sts_info ppdu_sts; 5512 u8 total_sta_assoc; 5513 bool scanning; 5514 5515 struct rtw89_regulatory_info regulatory; 5516 struct rtw89_sar_info sar; 5517 struct rtw89_tas_info tas; 5518 5519 struct rtw89_btc btc; 5520 enum rtw89_ps_mode ps_mode; 5521 bool lps_enabled; 5522 5523 struct rtw89_wow_param wow; 5524 5525 /* napi structure */ 5526 struct net_device *netdev; 5527 struct napi_struct napi; 5528 int napi_budget_countdown; 5529 5530 /* HCI related data, keep last */ 5531 u8 priv[] __aligned(sizeof(void *)); 5532 }; 5533 5534 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5535 struct rtw89_core_tx_request *tx_req) 5536 { 5537 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5538 } 5539 5540 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5541 { 5542 rtwdev->hci.ops->reset(rtwdev); 5543 } 5544 5545 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5546 { 5547 return rtwdev->hci.ops->start(rtwdev); 5548 } 5549 5550 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5551 { 5552 rtwdev->hci.ops->stop(rtwdev); 5553 } 5554 5555 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5556 { 5557 return rtwdev->hci.ops->deinit(rtwdev); 5558 } 5559 5560 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5561 { 5562 rtwdev->hci.ops->pause(rtwdev, pause); 5563 } 5564 5565 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5566 { 5567 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5568 } 5569 5570 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5571 { 5572 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5573 } 5574 5575 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5576 { 5577 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5578 } 5579 5580 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5581 { 5582 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5583 } 5584 5585 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5586 { 5587 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5588 } 5589 5590 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5591 bool drop) 5592 { 5593 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5594 return; 5595 5596 if (rtwdev->hci.ops->flush_queues) 5597 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5598 } 5599 5600 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5601 { 5602 if (rtwdev->hci.ops->recovery_start) 5603 rtwdev->hci.ops->recovery_start(rtwdev); 5604 } 5605 5606 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5607 { 5608 if (rtwdev->hci.ops->recovery_complete) 5609 rtwdev->hci.ops->recovery_complete(rtwdev); 5610 } 5611 5612 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5613 { 5614 if (rtwdev->hci.ops->enable_intr) 5615 rtwdev->hci.ops->enable_intr(rtwdev); 5616 } 5617 5618 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5619 { 5620 if (rtwdev->hci.ops->disable_intr) 5621 rtwdev->hci.ops->disable_intr(rtwdev); 5622 } 5623 5624 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5625 { 5626 if (rtwdev->hci.ops->ctrl_txdma_ch) 5627 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5628 } 5629 5630 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5631 { 5632 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5633 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5634 } 5635 5636 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5637 { 5638 if (rtwdev->hci.ops->ctrl_trxhci) 5639 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5640 } 5641 5642 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5643 { 5644 int ret = 0; 5645 5646 if (rtwdev->hci.ops->poll_txdma_ch_idle) 5647 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 5648 return ret; 5649 } 5650 5651 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5652 { 5653 if (rtwdev->hci.ops->clr_idx_all) 5654 rtwdev->hci.ops->clr_idx_all(rtwdev); 5655 } 5656 5657 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 5658 { 5659 int ret = 0; 5660 5661 if (rtwdev->hci.ops->rst_bdram) 5662 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 5663 return ret; 5664 } 5665 5666 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 5667 { 5668 if (rtwdev->hci.ops->clear) 5669 rtwdev->hci.ops->clear(rtwdev, pdev); 5670 } 5671 5672 static inline 5673 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5674 { 5675 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5676 5677 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5678 } 5679 5680 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5681 { 5682 return rtwdev->hci.ops->read8(rtwdev, addr); 5683 } 5684 5685 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5686 { 5687 return rtwdev->hci.ops->read16(rtwdev, addr); 5688 } 5689 5690 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5691 { 5692 return rtwdev->hci.ops->read32(rtwdev, addr); 5693 } 5694 5695 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5696 { 5697 rtwdev->hci.ops->write8(rtwdev, addr, data); 5698 } 5699 5700 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5701 { 5702 rtwdev->hci.ops->write16(rtwdev, addr, data); 5703 } 5704 5705 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5706 { 5707 rtwdev->hci.ops->write32(rtwdev, addr, data); 5708 } 5709 5710 static inline void 5711 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5712 { 5713 u8 val; 5714 5715 val = rtw89_read8(rtwdev, addr); 5716 rtw89_write8(rtwdev, addr, val | bit); 5717 } 5718 5719 static inline void 5720 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5721 { 5722 u16 val; 5723 5724 val = rtw89_read16(rtwdev, addr); 5725 rtw89_write16(rtwdev, addr, val | bit); 5726 } 5727 5728 static inline void 5729 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5730 { 5731 u32 val; 5732 5733 val = rtw89_read32(rtwdev, addr); 5734 rtw89_write32(rtwdev, addr, val | bit); 5735 } 5736 5737 static inline void 5738 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5739 { 5740 u8 val; 5741 5742 val = rtw89_read8(rtwdev, addr); 5743 rtw89_write8(rtwdev, addr, val & ~bit); 5744 } 5745 5746 static inline void 5747 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5748 { 5749 u16 val; 5750 5751 val = rtw89_read16(rtwdev, addr); 5752 rtw89_write16(rtwdev, addr, val & ~bit); 5753 } 5754 5755 static inline void 5756 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5757 { 5758 u32 val; 5759 5760 val = rtw89_read32(rtwdev, addr); 5761 rtw89_write32(rtwdev, addr, val & ~bit); 5762 } 5763 5764 static inline u32 5765 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5766 { 5767 u32 shift = __ffs(mask); 5768 u32 orig; 5769 u32 ret; 5770 5771 orig = rtw89_read32(rtwdev, addr); 5772 ret = (orig & mask) >> shift; 5773 5774 return ret; 5775 } 5776 5777 static inline u16 5778 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5779 { 5780 u32 shift = __ffs(mask); 5781 u32 orig; 5782 u32 ret; 5783 5784 orig = rtw89_read16(rtwdev, addr); 5785 ret = (orig & mask) >> shift; 5786 5787 return ret; 5788 } 5789 5790 static inline u8 5791 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5792 { 5793 u32 shift = __ffs(mask); 5794 u32 orig; 5795 u32 ret; 5796 5797 orig = rtw89_read8(rtwdev, addr); 5798 ret = (orig & mask) >> shift; 5799 5800 return ret; 5801 } 5802 5803 static inline void 5804 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5805 { 5806 u32 shift = __ffs(mask); 5807 u32 orig; 5808 u32 set; 5809 5810 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5811 5812 orig = rtw89_read32(rtwdev, addr); 5813 set = (orig & ~mask) | ((data << shift) & mask); 5814 rtw89_write32(rtwdev, addr, set); 5815 } 5816 5817 static inline void 5818 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5819 { 5820 u32 shift; 5821 u16 orig, set; 5822 5823 mask &= 0xffff; 5824 shift = __ffs(mask); 5825 5826 orig = rtw89_read16(rtwdev, addr); 5827 set = (orig & ~mask) | ((data << shift) & mask); 5828 rtw89_write16(rtwdev, addr, set); 5829 } 5830 5831 static inline void 5832 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5833 { 5834 u32 shift; 5835 u8 orig, set; 5836 5837 mask &= 0xff; 5838 shift = __ffs(mask); 5839 5840 orig = rtw89_read8(rtwdev, addr); 5841 set = (orig & ~mask) | ((data << shift) & mask); 5842 rtw89_write8(rtwdev, addr, set); 5843 } 5844 5845 static inline u32 5846 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5847 u32 addr, u32 mask) 5848 { 5849 u32 val; 5850 5851 mutex_lock(&rtwdev->rf_mutex); 5852 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5853 mutex_unlock(&rtwdev->rf_mutex); 5854 5855 return val; 5856 } 5857 5858 static inline void 5859 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5860 u32 addr, u32 mask, u32 data) 5861 { 5862 mutex_lock(&rtwdev->rf_mutex); 5863 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5864 mutex_unlock(&rtwdev->rf_mutex); 5865 } 5866 5867 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5868 { 5869 void *p = rtwtxq; 5870 5871 return container_of(p, struct ieee80211_txq, drv_priv); 5872 } 5873 5874 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5875 struct ieee80211_txq *txq) 5876 { 5877 struct rtw89_txq *rtwtxq; 5878 5879 if (!txq) 5880 return; 5881 5882 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5883 INIT_LIST_HEAD(&rtwtxq->list); 5884 } 5885 5886 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5887 { 5888 void *p = rtwvif; 5889 5890 return container_of(p, struct ieee80211_vif, drv_priv); 5891 } 5892 5893 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5894 { 5895 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5896 } 5897 5898 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5899 { 5900 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5901 } 5902 5903 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5904 { 5905 void *p = rtwsta; 5906 5907 return container_of(p, struct ieee80211_sta, drv_priv); 5908 } 5909 5910 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5911 { 5912 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5913 } 5914 5915 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5916 { 5917 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5918 } 5919 5920 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5921 { 5922 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5923 return RATE_INFO_BW_160; 5924 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5925 return RATE_INFO_BW_80; 5926 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5927 return RATE_INFO_BW_40; 5928 else 5929 return RATE_INFO_BW_20; 5930 } 5931 5932 static inline 5933 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5934 { 5935 switch (hw_band) { 5936 default: 5937 case RTW89_BAND_2G: 5938 return NL80211_BAND_2GHZ; 5939 case RTW89_BAND_5G: 5940 return NL80211_BAND_5GHZ; 5941 case RTW89_BAND_6G: 5942 return NL80211_BAND_6GHZ; 5943 } 5944 } 5945 5946 static inline 5947 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5948 { 5949 switch (nl_band) { 5950 default: 5951 case NL80211_BAND_2GHZ: 5952 return RTW89_BAND_2G; 5953 case NL80211_BAND_5GHZ: 5954 return RTW89_BAND_5G; 5955 case NL80211_BAND_6GHZ: 5956 return RTW89_BAND_6G; 5957 } 5958 } 5959 5960 static inline 5961 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5962 { 5963 switch (width) { 5964 default: 5965 WARN(1, "Not support bandwidth %d\n", width); 5966 fallthrough; 5967 case NL80211_CHAN_WIDTH_20_NOHT: 5968 case NL80211_CHAN_WIDTH_20: 5969 return RTW89_CHANNEL_WIDTH_20; 5970 case NL80211_CHAN_WIDTH_40: 5971 return RTW89_CHANNEL_WIDTH_40; 5972 case NL80211_CHAN_WIDTH_80: 5973 return RTW89_CHANNEL_WIDTH_80; 5974 case NL80211_CHAN_WIDTH_160: 5975 return RTW89_CHANNEL_WIDTH_160; 5976 } 5977 } 5978 5979 static inline 5980 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5981 { 5982 switch (rua) { 5983 default: 5984 WARN(1, "Invalid RU allocation: %d\n", rua); 5985 fallthrough; 5986 case 0 ... 36: 5987 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5988 case 37 ... 52: 5989 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5990 case 53 ... 60: 5991 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5992 case 61 ... 64: 5993 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5994 case 65 ... 66: 5995 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5996 case 67: 5997 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5998 case 68: 5999 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6000 } 6001 } 6002 6003 static inline 6004 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 6005 struct rtw89_sta *rtwsta) 6006 { 6007 if (rtwsta) { 6008 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 6009 6010 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6011 return &rtwsta->addr_cam; 6012 } 6013 return &rtwvif->addr_cam; 6014 } 6015 6016 static inline 6017 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 6018 struct rtw89_sta *rtwsta) 6019 { 6020 if (rtwsta) { 6021 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 6022 6023 if (sta->tdls) 6024 return &rtwsta->bssid_cam; 6025 } 6026 return &rtwvif->bssid_cam; 6027 } 6028 6029 static inline 6030 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6031 struct rtw89_channel_help_params *p, 6032 const struct rtw89_chan *chan, 6033 enum rtw89_mac_idx mac_idx, 6034 enum rtw89_phy_idx phy_idx) 6035 { 6036 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6037 mac_idx, phy_idx); 6038 } 6039 6040 static inline 6041 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6042 struct rtw89_channel_help_params *p, 6043 const struct rtw89_chan *chan, 6044 enum rtw89_mac_idx mac_idx, 6045 enum rtw89_phy_idx phy_idx) 6046 { 6047 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6048 mac_idx, phy_idx); 6049 } 6050 6051 static inline 6052 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6053 enum rtw89_chanctx_idx idx) 6054 { 6055 struct rtw89_hal *hal = &rtwdev->hal; 6056 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_entity_idx); 6057 6058 if (roc_idx == idx) 6059 return &hal->roc_chandef; 6060 6061 return &hal->chanctx[idx].chandef; 6062 } 6063 6064 static inline 6065 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6066 enum rtw89_chanctx_idx idx) 6067 { 6068 struct rtw89_hal *hal = &rtwdev->hal; 6069 6070 return &hal->chanctx[idx].chan; 6071 } 6072 6073 static inline 6074 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6075 enum rtw89_chanctx_idx idx) 6076 { 6077 struct rtw89_hal *hal = &rtwdev->hal; 6078 6079 return &hal->chanctx[idx].rcd; 6080 } 6081 6082 static inline 6083 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6084 { 6085 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 6086 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 6087 6088 if (rtwvif) 6089 return rtw89_chan_get(rtwdev, rtwvif->chanctx_idx); 6090 else 6091 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6092 } 6093 6094 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6095 { 6096 const struct rtw89_chip_info *chip = rtwdev->chip; 6097 6098 if (chip->ops->fem_setup) 6099 chip->ops->fem_setup(rtwdev); 6100 } 6101 6102 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6103 { 6104 const struct rtw89_chip_info *chip = rtwdev->chip; 6105 6106 if (chip->ops->rfe_gpio) 6107 chip->ops->rfe_gpio(rtwdev); 6108 } 6109 6110 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6111 { 6112 const struct rtw89_chip_info *chip = rtwdev->chip; 6113 6114 if (chip->ops->rfk_hw_init) 6115 chip->ops->rfk_hw_init(rtwdev); 6116 } 6117 6118 static inline 6119 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6120 { 6121 const struct rtw89_chip_info *chip = rtwdev->chip; 6122 6123 if (chip->ops->bb_preinit) 6124 chip->ops->bb_preinit(rtwdev, phy_idx); 6125 } 6126 6127 static inline 6128 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6129 { 6130 const struct rtw89_chip_info *chip = rtwdev->chip; 6131 6132 if (!chip->ops->bb_postinit) 6133 return; 6134 6135 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6136 6137 if (rtwdev->dbcc_en) 6138 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6139 } 6140 6141 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6142 { 6143 const struct rtw89_chip_info *chip = rtwdev->chip; 6144 6145 if (chip->ops->bb_sethw) 6146 chip->ops->bb_sethw(rtwdev); 6147 } 6148 6149 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6150 { 6151 const struct rtw89_chip_info *chip = rtwdev->chip; 6152 6153 if (chip->ops->rfk_init) 6154 chip->ops->rfk_init(rtwdev); 6155 } 6156 6157 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6158 { 6159 const struct rtw89_chip_info *chip = rtwdev->chip; 6160 6161 if (chip->ops->rfk_init_late) 6162 chip->ops->rfk_init_late(rtwdev); 6163 } 6164 6165 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6166 struct rtw89_vif *rtwvif) 6167 { 6168 const struct rtw89_chip_info *chip = rtwdev->chip; 6169 6170 if (chip->ops->rfk_channel) 6171 chip->ops->rfk_channel(rtwdev, rtwvif); 6172 } 6173 6174 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6175 enum rtw89_phy_idx phy_idx) 6176 { 6177 const struct rtw89_chip_info *chip = rtwdev->chip; 6178 6179 if (chip->ops->rfk_band_changed) 6180 chip->ops->rfk_band_changed(rtwdev, phy_idx); 6181 } 6182 6183 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6184 struct rtw89_vif *rtwvif, bool start) 6185 { 6186 const struct rtw89_chip_info *chip = rtwdev->chip; 6187 6188 if (chip->ops->rfk_scan) 6189 chip->ops->rfk_scan(rtwdev, rtwvif, start); 6190 } 6191 6192 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6193 { 6194 const struct rtw89_chip_info *chip = rtwdev->chip; 6195 6196 if (chip->ops->rfk_track) 6197 chip->ops->rfk_track(rtwdev); 6198 } 6199 6200 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6201 { 6202 const struct rtw89_chip_info *chip = rtwdev->chip; 6203 6204 if (chip->ops->set_txpwr_ctrl) 6205 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6206 } 6207 6208 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6209 { 6210 const struct rtw89_chip_info *chip = rtwdev->chip; 6211 6212 if (chip->ops->power_trim) 6213 chip->ops->power_trim(rtwdev); 6214 } 6215 6216 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6217 enum rtw89_phy_idx phy_idx) 6218 { 6219 const struct rtw89_chip_info *chip = rtwdev->chip; 6220 6221 if (chip->ops->init_txpwr_unit) 6222 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6223 } 6224 6225 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6226 enum rtw89_rf_path rf_path) 6227 { 6228 const struct rtw89_chip_info *chip = rtwdev->chip; 6229 6230 if (!chip->ops->get_thermal) 6231 return 0x10; 6232 6233 return chip->ops->get_thermal(rtwdev, rf_path); 6234 } 6235 6236 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6237 struct rtw89_rx_phy_ppdu *phy_ppdu, 6238 struct ieee80211_rx_status *status) 6239 { 6240 const struct rtw89_chip_info *chip = rtwdev->chip; 6241 6242 if (chip->ops->query_ppdu) 6243 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6244 } 6245 6246 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6247 enum rtw89_phy_idx phy_idx) 6248 { 6249 const struct rtw89_chip_info *chip = rtwdev->chip; 6250 6251 if (chip->ops->ctrl_nbtg_bt_tx) 6252 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6253 } 6254 6255 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6256 { 6257 const struct rtw89_chip_info *chip = rtwdev->chip; 6258 6259 if (chip->ops->cfg_txrx_path) 6260 chip->ops->cfg_txrx_path(rtwdev); 6261 } 6262 6263 static inline 6264 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 6265 struct ieee80211_vif *vif) 6266 { 6267 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6268 const struct rtw89_chip_info *chip = rtwdev->chip; 6269 6270 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 6271 return; 6272 6273 if (chip->ops->set_txpwr_ul_tb_offset) 6274 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 6275 } 6276 6277 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6278 const struct rtw89_txpwr_table *tbl) 6279 { 6280 tbl->load(rtwdev, tbl); 6281 } 6282 6283 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6284 { 6285 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6286 6287 return regd->txpwr_regd[band]; 6288 } 6289 6290 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6291 enum rtw89_phy_idx phy_idx) 6292 { 6293 const struct rtw89_chip_info *chip = rtwdev->chip; 6294 6295 if (chip->ops->ctrl_btg_bt_rx) 6296 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6297 } 6298 6299 static inline 6300 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6301 struct rtw89_rx_desc_info *desc_info, 6302 u8 *data, u32 data_offset) 6303 { 6304 const struct rtw89_chip_info *chip = rtwdev->chip; 6305 6306 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6307 } 6308 6309 static inline 6310 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6311 struct rtw89_tx_desc_info *desc_info, 6312 void *txdesc) 6313 { 6314 const struct rtw89_chip_info *chip = rtwdev->chip; 6315 6316 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6317 } 6318 6319 static inline 6320 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6321 struct rtw89_tx_desc_info *desc_info, 6322 void *txdesc) 6323 { 6324 const struct rtw89_chip_info *chip = rtwdev->chip; 6325 6326 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6327 } 6328 6329 static inline 6330 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6331 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6332 { 6333 const struct rtw89_chip_info *chip = rtwdev->chip; 6334 6335 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6336 } 6337 6338 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6339 { 6340 const struct rtw89_chip_info *chip = rtwdev->chip; 6341 6342 chip->ops->cfg_ctrl_path(rtwdev, wl); 6343 } 6344 6345 static inline 6346 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6347 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6348 { 6349 const struct rtw89_chip_info *chip = rtwdev->chip; 6350 6351 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6352 } 6353 6354 static inline 6355 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6356 { 6357 const struct rtw89_chip_info *chip = rtwdev->chip; 6358 6359 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6360 } 6361 6362 static inline 6363 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6364 struct rtw89_vif *rtwvif, 6365 struct rtw89_sta *rtwsta) 6366 { 6367 const struct rtw89_chip_info *chip = rtwdev->chip; 6368 6369 if (!chip->ops->h2c_dctl_sec_cam) 6370 return 0; 6371 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 6372 } 6373 6374 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6375 { 6376 __le16 fc = hdr->frame_control; 6377 6378 if (ieee80211_has_tods(fc)) 6379 return hdr->addr1; 6380 else if (ieee80211_has_fromds(fc)) 6381 return hdr->addr2; 6382 else 6383 return hdr->addr3; 6384 } 6385 6386 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 6387 { 6388 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6389 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6390 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 6391 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6392 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 6393 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6394 return true; 6395 return false; 6396 } 6397 6398 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6399 enum rtw89_fw_type type) 6400 { 6401 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6402 6403 switch (type) { 6404 case RTW89_FW_WOWLAN: 6405 return &fw_info->wowlan; 6406 case RTW89_FW_LOGFMT: 6407 return &fw_info->log.suit; 6408 case RTW89_FW_BBMCU0: 6409 return &fw_info->bbmcu0; 6410 case RTW89_FW_BBMCU1: 6411 return &fw_info->bbmcu1; 6412 default: 6413 break; 6414 } 6415 6416 return &fw_info->normal; 6417 } 6418 6419 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6420 unsigned int length) 6421 { 6422 struct sk_buff *skb; 6423 6424 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6425 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6426 if (!skb) 6427 return NULL; 6428 6429 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6430 return skb; 6431 } 6432 6433 return dev_alloc_skb(length); 6434 } 6435 6436 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6437 struct rtw89_tx_skb_data *skb_data, 6438 bool tx_done) 6439 { 6440 struct rtw89_tx_wait_info *wait; 6441 6442 rcu_read_lock(); 6443 6444 wait = rcu_dereference(skb_data->wait); 6445 if (!wait) 6446 goto out; 6447 6448 wait->tx_done = tx_done; 6449 complete(&wait->completion); 6450 6451 out: 6452 rcu_read_unlock(); 6453 } 6454 6455 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6456 { 6457 switch (rtwdev->mlo_dbcc_mode) { 6458 case MLO_1_PLUS_1_1RF: 6459 case MLO_1_PLUS_1_2RF: 6460 case DBCC_LEGACY: 6461 return true; 6462 default: 6463 return false; 6464 } 6465 } 6466 6467 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 6468 { 6469 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6470 6471 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 6472 return true; 6473 6474 return false; 6475 } 6476 6477 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6478 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6479 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6480 struct sk_buff *skb, bool fwdl); 6481 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6482 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6483 int qsel, unsigned int timeout); 6484 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6485 struct rtw89_tx_desc_info *desc_info, 6486 void *txdesc); 6487 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6488 struct rtw89_tx_desc_info *desc_info, 6489 void *txdesc); 6490 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6491 struct rtw89_tx_desc_info *desc_info, 6492 void *txdesc); 6493 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6494 struct rtw89_tx_desc_info *desc_info, 6495 void *txdesc); 6496 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6497 struct rtw89_tx_desc_info *desc_info, 6498 void *txdesc); 6499 void rtw89_core_rx(struct rtw89_dev *rtwdev, 6500 struct rtw89_rx_desc_info *desc_info, 6501 struct sk_buff *skb); 6502 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 6503 struct rtw89_rx_desc_info *desc_info, 6504 u8 *data, u32 data_offset); 6505 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 6506 struct rtw89_rx_desc_info *desc_info, 6507 u8 *data, u32 data_offset); 6508 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 6509 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 6510 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 6511 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 6512 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 6513 struct ieee80211_vif *vif, 6514 struct ieee80211_sta *sta); 6515 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 6516 struct ieee80211_vif *vif, 6517 struct ieee80211_sta *sta); 6518 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 6519 struct ieee80211_vif *vif, 6520 struct ieee80211_sta *sta); 6521 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 6522 struct ieee80211_vif *vif, 6523 struct ieee80211_sta *sta); 6524 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 6525 struct ieee80211_vif *vif, 6526 struct ieee80211_sta *sta); 6527 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6528 struct ieee80211_sta *sta, 6529 struct cfg80211_tid_config *tid_config); 6530 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 6531 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 6532 int rtw89_core_init(struct rtw89_dev *rtwdev); 6533 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 6534 int rtw89_core_register(struct rtw89_dev *rtwdev); 6535 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 6536 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6537 u32 bus_data_size, 6538 const struct rtw89_chip_info *chip); 6539 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 6540 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 6541 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 6542 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 6543 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 6544 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 6545 struct rtw89_chan *chan); 6546 int rtw89_set_channel(struct rtw89_dev *rtwdev); 6547 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6548 struct rtw89_chan *chan); 6549 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 6550 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 6551 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 6552 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 6553 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6554 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 6555 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6556 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 6557 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 6558 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 6559 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 6560 int rtw89_regd_init(struct rtw89_dev *rtwdev, 6561 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 6562 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 6563 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 6564 struct rtw89_traffic_stats *stats); 6565 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 6566 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6567 const struct rtw89_completion_data *data); 6568 int rtw89_core_start(struct rtw89_dev *rtwdev); 6569 void rtw89_core_stop(struct rtw89_dev *rtwdev); 6570 void rtw89_core_update_beacon_work(struct work_struct *work); 6571 void rtw89_roc_work(struct work_struct *work); 6572 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6573 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6574 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6575 const u8 *mac_addr, bool hw_scan); 6576 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6577 struct ieee80211_vif *vif, bool hw_scan); 6578 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6579 bool active); 6580 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 6581 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 6582 6583 #endif 6584