1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 struct rtw89_mac_gen_def; 18 struct rtw89_phy_gen_def; 19 20 extern const struct ieee80211_ops rtw89_ops; 21 22 #define MASKBYTE0 0xff 23 #define MASKBYTE1 0xff00 24 #define MASKBYTE2 0xff0000 25 #define MASKBYTE3 0xff000000 26 #define MASKBYTE4 0xff00000000ULL 27 #define MASKHWORD 0xffff0000 28 #define MASKLWORD 0x0000ffff 29 #define MASKDWORD 0xffffffff 30 #define RFREG_MASK 0xfffff 31 #define INV_RF_DATA 0xffffffff 32 33 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 34 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 35 #define CFO_TRACK_MAX_USER 64 36 #define MAX_RSSI 110 37 #define RSSI_FACTOR 1 38 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 39 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 40 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 41 #define RTW89_RADIOTAP_ROOM_EHT \ 42 (sizeof(struct ieee80211_radiotap_tlv) + \ 43 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 44 sizeof(struct ieee80211_radiotap_tlv) + \ 45 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 46 #define RTW89_RADIOTAP_ROOM \ 47 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 48 49 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 50 #define RTW89_HTC_VARIANT_HE 3 51 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 52 #define RTW89_HTC_VARIANT_HE_CID_OM 1 53 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 54 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 55 56 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 57 enum htc_om_channel_width { 58 HTC_OM_CHANNEL_WIDTH_20 = 0, 59 HTC_OM_CHANNEL_WIDTH_40 = 1, 60 HTC_OM_CHANNEL_WIDTH_80 = 2, 61 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 62 }; 63 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 64 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 65 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 66 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 67 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 68 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 69 70 #define RTW89_TF_PAD GENMASK(11, 0) 71 #define RTW89_TF_BASIC_USER_INFO_SZ 6 72 73 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 74 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 75 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 76 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 77 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 78 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 79 80 enum rtw89_subband { 81 RTW89_CH_2G = 0, 82 RTW89_CH_5G_BAND_1 = 1, 83 /* RTW89_CH_5G_BAND_2 = 2, unused */ 84 RTW89_CH_5G_BAND_3 = 3, 85 RTW89_CH_5G_BAND_4 = 4, 86 87 RTW89_CH_6G_BAND_IDX0, /* Low */ 88 RTW89_CH_6G_BAND_IDX1, /* Low */ 89 RTW89_CH_6G_BAND_IDX2, /* Mid */ 90 RTW89_CH_6G_BAND_IDX3, /* Mid */ 91 RTW89_CH_6G_BAND_IDX4, /* High */ 92 RTW89_CH_6G_BAND_IDX5, /* High */ 93 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 94 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 95 96 RTW89_SUBBAND_NR, 97 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 98 }; 99 100 enum rtw89_gain_offset { 101 RTW89_GAIN_OFFSET_2G_CCK, 102 RTW89_GAIN_OFFSET_2G_OFDM, 103 RTW89_GAIN_OFFSET_5G_LOW, 104 RTW89_GAIN_OFFSET_5G_MID, 105 RTW89_GAIN_OFFSET_5G_HIGH, 106 107 RTW89_GAIN_OFFSET_NR, 108 }; 109 110 enum rtw89_hci_type { 111 RTW89_HCI_TYPE_PCIE, 112 RTW89_HCI_TYPE_USB, 113 RTW89_HCI_TYPE_SDIO, 114 }; 115 116 enum rtw89_core_chip_id { 117 RTL8852A, 118 RTL8852B, 119 RTL8852C, 120 RTL8851B, 121 RTL8922A, 122 }; 123 124 enum rtw89_chip_gen { 125 RTW89_CHIP_AX, 126 RTW89_CHIP_BE, 127 128 RTW89_CHIP_GEN_NUM, 129 }; 130 131 enum rtw89_cv { 132 CHIP_CAV, 133 CHIP_CBV, 134 CHIP_CCV, 135 CHIP_CDV, 136 CHIP_CEV, 137 CHIP_CFV, 138 CHIP_CV_MAX, 139 CHIP_CV_INVALID = CHIP_CV_MAX, 140 }; 141 142 enum rtw89_bacam_ver { 143 RTW89_BACAM_V0, 144 RTW89_BACAM_V1, 145 146 RTW89_BACAM_V0_EXT = 99, 147 }; 148 149 enum rtw89_core_tx_type { 150 RTW89_CORE_TX_TYPE_DATA, 151 RTW89_CORE_TX_TYPE_MGMT, 152 RTW89_CORE_TX_TYPE_FWCMD, 153 }; 154 155 enum rtw89_core_rx_type { 156 RTW89_CORE_RX_TYPE_WIFI = 0, 157 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 158 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 159 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 160 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 161 RTW89_CORE_RX_TYPE_SS2FW = 5, 162 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 163 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 164 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 165 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 166 RTW89_CORE_RX_TYPE_C2H = 10, 167 RTW89_CORE_RX_TYPE_CSI = 11, 168 RTW89_CORE_RX_TYPE_CQI = 12, 169 RTW89_CORE_RX_TYPE_H2C = 13, 170 RTW89_CORE_RX_TYPE_FWDL = 14, 171 }; 172 173 enum rtw89_txq_flags { 174 RTW89_TXQ_F_AMPDU = 0, 175 RTW89_TXQ_F_BLOCK_BA = 1, 176 RTW89_TXQ_F_FORBID_BA = 2, 177 }; 178 179 enum rtw89_net_type { 180 RTW89_NET_TYPE_NO_LINK = 0, 181 RTW89_NET_TYPE_AD_HOC = 1, 182 RTW89_NET_TYPE_INFRA = 2, 183 RTW89_NET_TYPE_AP_MODE = 3, 184 }; 185 186 enum rtw89_wifi_role { 187 RTW89_WIFI_ROLE_NONE, 188 RTW89_WIFI_ROLE_STATION, 189 RTW89_WIFI_ROLE_AP, 190 RTW89_WIFI_ROLE_AP_VLAN, 191 RTW89_WIFI_ROLE_ADHOC, 192 RTW89_WIFI_ROLE_ADHOC_MASTER, 193 RTW89_WIFI_ROLE_MESH_POINT, 194 RTW89_WIFI_ROLE_MONITOR, 195 RTW89_WIFI_ROLE_P2P_DEVICE, 196 RTW89_WIFI_ROLE_P2P_CLIENT, 197 RTW89_WIFI_ROLE_P2P_GO, 198 RTW89_WIFI_ROLE_NAN, 199 RTW89_WIFI_ROLE_MLME_MAX 200 }; 201 202 enum rtw89_upd_mode { 203 RTW89_ROLE_CREATE, 204 RTW89_ROLE_REMOVE, 205 RTW89_ROLE_TYPE_CHANGE, 206 RTW89_ROLE_INFO_CHANGE, 207 RTW89_ROLE_CON_DISCONN, 208 RTW89_ROLE_BAND_SW, 209 RTW89_ROLE_FW_RESTORE, 210 }; 211 212 enum rtw89_self_role { 213 RTW89_SELF_ROLE_CLIENT, 214 RTW89_SELF_ROLE_AP, 215 RTW89_SELF_ROLE_AP_CLIENT 216 }; 217 218 enum rtw89_msk_sO_el { 219 RTW89_NO_MSK, 220 RTW89_SMA, 221 RTW89_TMA, 222 RTW89_BSSID 223 }; 224 225 enum rtw89_sch_tx_sel { 226 RTW89_SCH_TX_SEL_ALL, 227 RTW89_SCH_TX_SEL_HIQ, 228 RTW89_SCH_TX_SEL_MG0, 229 RTW89_SCH_TX_SEL_MACID, 230 }; 231 232 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 233 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 234 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 235 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 236 */ 237 enum rtw89_add_cam_sec_mode { 238 RTW89_ADDR_CAM_SEC_NONE = 0, 239 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 240 RTW89_ADDR_CAM_SEC_NORMAL = 2, 241 RTW89_ADDR_CAM_SEC_4GROUP = 3, 242 }; 243 244 enum rtw89_sec_key_type { 245 RTW89_SEC_KEY_TYPE_NONE = 0, 246 RTW89_SEC_KEY_TYPE_WEP40 = 1, 247 RTW89_SEC_KEY_TYPE_WEP104 = 2, 248 RTW89_SEC_KEY_TYPE_TKIP = 3, 249 RTW89_SEC_KEY_TYPE_WAPI = 4, 250 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 251 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 252 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 253 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 254 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 255 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 256 }; 257 258 enum rtw89_port { 259 RTW89_PORT_0 = 0, 260 RTW89_PORT_1 = 1, 261 RTW89_PORT_2 = 2, 262 RTW89_PORT_3 = 3, 263 RTW89_PORT_4 = 4, 264 RTW89_PORT_NUM 265 }; 266 267 enum rtw89_band { 268 RTW89_BAND_2G = 0, 269 RTW89_BAND_5G = 1, 270 RTW89_BAND_6G = 2, 271 RTW89_BAND_NUM, 272 }; 273 274 enum rtw89_hw_rate { 275 RTW89_HW_RATE_CCK1 = 0x0, 276 RTW89_HW_RATE_CCK2 = 0x1, 277 RTW89_HW_RATE_CCK5_5 = 0x2, 278 RTW89_HW_RATE_CCK11 = 0x3, 279 RTW89_HW_RATE_OFDM6 = 0x4, 280 RTW89_HW_RATE_OFDM9 = 0x5, 281 RTW89_HW_RATE_OFDM12 = 0x6, 282 RTW89_HW_RATE_OFDM18 = 0x7, 283 RTW89_HW_RATE_OFDM24 = 0x8, 284 RTW89_HW_RATE_OFDM36 = 0x9, 285 RTW89_HW_RATE_OFDM48 = 0xA, 286 RTW89_HW_RATE_OFDM54 = 0xB, 287 RTW89_HW_RATE_MCS0 = 0x80, 288 RTW89_HW_RATE_MCS1 = 0x81, 289 RTW89_HW_RATE_MCS2 = 0x82, 290 RTW89_HW_RATE_MCS3 = 0x83, 291 RTW89_HW_RATE_MCS4 = 0x84, 292 RTW89_HW_RATE_MCS5 = 0x85, 293 RTW89_HW_RATE_MCS6 = 0x86, 294 RTW89_HW_RATE_MCS7 = 0x87, 295 RTW89_HW_RATE_MCS8 = 0x88, 296 RTW89_HW_RATE_MCS9 = 0x89, 297 RTW89_HW_RATE_MCS10 = 0x8A, 298 RTW89_HW_RATE_MCS11 = 0x8B, 299 RTW89_HW_RATE_MCS12 = 0x8C, 300 RTW89_HW_RATE_MCS13 = 0x8D, 301 RTW89_HW_RATE_MCS14 = 0x8E, 302 RTW89_HW_RATE_MCS15 = 0x8F, 303 RTW89_HW_RATE_MCS16 = 0x90, 304 RTW89_HW_RATE_MCS17 = 0x91, 305 RTW89_HW_RATE_MCS18 = 0x92, 306 RTW89_HW_RATE_MCS19 = 0x93, 307 RTW89_HW_RATE_MCS20 = 0x94, 308 RTW89_HW_RATE_MCS21 = 0x95, 309 RTW89_HW_RATE_MCS22 = 0x96, 310 RTW89_HW_RATE_MCS23 = 0x97, 311 RTW89_HW_RATE_MCS24 = 0x98, 312 RTW89_HW_RATE_MCS25 = 0x99, 313 RTW89_HW_RATE_MCS26 = 0x9A, 314 RTW89_HW_RATE_MCS27 = 0x9B, 315 RTW89_HW_RATE_MCS28 = 0x9C, 316 RTW89_HW_RATE_MCS29 = 0x9D, 317 RTW89_HW_RATE_MCS30 = 0x9E, 318 RTW89_HW_RATE_MCS31 = 0x9F, 319 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 320 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 321 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 322 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 323 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 324 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 325 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 326 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 327 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 328 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 329 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 330 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 331 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 332 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 333 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 334 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 335 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 336 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 337 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 338 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 339 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 340 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 341 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 342 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 343 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 344 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 345 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 346 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 347 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 348 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 349 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 350 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 351 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 352 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 353 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 354 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 355 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 356 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 357 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 358 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 359 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 360 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 361 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 362 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 363 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 364 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 365 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 366 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 367 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 368 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 369 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 370 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 371 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 372 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 373 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 374 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 375 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 376 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 377 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 378 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 379 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 380 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 381 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 382 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 383 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 384 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 385 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 386 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 387 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 388 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 389 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 390 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 391 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 392 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 393 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 394 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 395 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 396 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 397 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 398 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 399 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 400 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 401 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 402 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 403 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 404 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 405 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 406 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 407 408 RTW89_HW_RATE_V1_MCS0 = 0x100, 409 RTW89_HW_RATE_V1_MCS1 = 0x101, 410 RTW89_HW_RATE_V1_MCS2 = 0x102, 411 RTW89_HW_RATE_V1_MCS3 = 0x103, 412 RTW89_HW_RATE_V1_MCS4 = 0x104, 413 RTW89_HW_RATE_V1_MCS5 = 0x105, 414 RTW89_HW_RATE_V1_MCS6 = 0x106, 415 RTW89_HW_RATE_V1_MCS7 = 0x107, 416 RTW89_HW_RATE_V1_MCS8 = 0x108, 417 RTW89_HW_RATE_V1_MCS9 = 0x109, 418 RTW89_HW_RATE_V1_MCS10 = 0x10A, 419 RTW89_HW_RATE_V1_MCS11 = 0x10B, 420 RTW89_HW_RATE_V1_MCS12 = 0x10C, 421 RTW89_HW_RATE_V1_MCS13 = 0x10D, 422 RTW89_HW_RATE_V1_MCS14 = 0x10E, 423 RTW89_HW_RATE_V1_MCS15 = 0x10F, 424 RTW89_HW_RATE_V1_MCS16 = 0x110, 425 RTW89_HW_RATE_V1_MCS17 = 0x111, 426 RTW89_HW_RATE_V1_MCS18 = 0x112, 427 RTW89_HW_RATE_V1_MCS19 = 0x113, 428 RTW89_HW_RATE_V1_MCS20 = 0x114, 429 RTW89_HW_RATE_V1_MCS21 = 0x115, 430 RTW89_HW_RATE_V1_MCS22 = 0x116, 431 RTW89_HW_RATE_V1_MCS23 = 0x117, 432 RTW89_HW_RATE_V1_MCS24 = 0x118, 433 RTW89_HW_RATE_V1_MCS25 = 0x119, 434 RTW89_HW_RATE_V1_MCS26 = 0x11A, 435 RTW89_HW_RATE_V1_MCS27 = 0x11B, 436 RTW89_HW_RATE_V1_MCS28 = 0x11C, 437 RTW89_HW_RATE_V1_MCS29 = 0x11D, 438 RTW89_HW_RATE_V1_MCS30 = 0x11E, 439 RTW89_HW_RATE_V1_MCS31 = 0x11F, 440 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 441 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 442 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 443 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 444 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 445 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 446 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 447 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 448 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 449 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 450 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 451 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 452 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 453 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 454 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 455 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 456 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 457 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 458 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 459 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 460 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 461 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 462 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 463 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 464 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 465 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 466 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 467 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 468 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 469 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 470 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 471 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 472 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 473 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 474 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 475 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 476 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 477 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 478 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 479 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 480 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 481 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 482 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 483 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 484 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 485 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 486 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 487 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 488 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 489 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 490 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 491 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 492 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 493 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 494 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 495 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 496 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 497 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 498 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 499 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 500 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 501 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 502 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 503 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 504 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 505 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 506 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 507 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 508 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 509 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 510 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 511 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 512 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 513 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 514 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 515 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 516 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 517 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 518 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 519 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 520 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 521 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 522 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 523 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 524 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 525 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 526 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 527 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 528 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 529 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 530 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 531 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 532 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 533 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 534 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 535 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 536 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 537 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 538 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 539 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 540 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 541 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 542 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 543 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 544 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 545 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 546 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 547 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 548 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 549 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 550 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 551 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 552 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 553 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 554 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 555 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 556 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 557 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 558 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 559 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 560 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 561 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 562 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 563 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 564 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 565 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 566 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 567 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 568 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 569 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 570 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 571 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 572 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 573 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 574 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 575 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 576 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 577 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 578 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 579 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 580 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 581 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 582 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 583 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 584 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 585 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 586 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 587 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 588 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 589 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 590 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 591 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 592 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 593 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 594 595 RTW89_HW_RATE_NR, 596 RTW89_HW_RATE_INVAL, 597 598 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 599 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 600 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 601 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 602 }; 603 604 /* 2G channels, 605 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 606 */ 607 #define RTW89_2G_CH_NUM 14 608 609 /* 5G channels, 610 * 36, 38, 40, 42, 44, 46, 48, 50, 611 * 52, 54, 56, 58, 60, 62, 64, 612 * 100, 102, 104, 106, 108, 110, 112, 114, 613 * 116, 118, 120, 122, 124, 126, 128, 130, 614 * 132, 134, 136, 138, 140, 142, 144, 615 * 149, 151, 153, 155, 157, 159, 161, 163, 616 * 165, 167, 169, 171, 173, 175, 177 617 */ 618 #define RTW89_5G_CH_NUM 53 619 620 /* 6G channels, 621 * 1, 3, 5, 7, 9, 11, 13, 15, 622 * 17, 19, 21, 23, 25, 27, 29, 33, 623 * 35, 37, 39, 41, 43, 45, 47, 49, 624 * 51, 53, 55, 57, 59, 61, 65, 67, 625 * 69, 71, 73, 75, 77, 79, 81, 83, 626 * 85, 87, 89, 91, 93, 97, 99, 101, 627 * 103, 105, 107, 109, 111, 113, 115, 117, 628 * 119, 121, 123, 125, 129, 131, 133, 135, 629 * 137, 139, 141, 143, 145, 147, 149, 151, 630 * 153, 155, 157, 161, 163, 165, 167, 169, 631 * 171, 173, 175, 177, 179, 181, 183, 185, 632 * 187, 189, 193, 195, 197, 199, 201, 203, 633 * 205, 207, 209, 211, 213, 215, 217, 219, 634 * 221, 225, 227, 229, 231, 233, 235, 237, 635 * 239, 241, 243, 245, 247, 249, 251, 253, 636 */ 637 #define RTW89_6G_CH_NUM 120 638 639 enum rtw89_rate_section { 640 RTW89_RS_CCK, 641 RTW89_RS_OFDM, 642 RTW89_RS_MCS, /* for HT/VHT/HE */ 643 RTW89_RS_HEDCM, 644 RTW89_RS_OFFSET, 645 RTW89_RS_NUM, 646 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 647 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 648 }; 649 650 enum rtw89_rate_offset_indexes { 651 RTW89_RATE_OFFSET_HE, 652 RTW89_RATE_OFFSET_VHT, 653 RTW89_RATE_OFFSET_HT, 654 RTW89_RATE_OFFSET_OFDM, 655 RTW89_RATE_OFFSET_CCK, 656 RTW89_RATE_OFFSET_DLRU_EHT, 657 RTW89_RATE_OFFSET_DLRU_HE, 658 RTW89_RATE_OFFSET_EHT, 659 __RTW89_RATE_OFFSET_NUM, 660 661 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 662 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 663 }; 664 665 enum rtw89_rate_num { 666 RTW89_RATE_CCK_NUM = 4, 667 RTW89_RATE_OFDM_NUM = 8, 668 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 669 670 RTW89_RATE_MCS_NUM_AX = 12, 671 RTW89_RATE_MCS_NUM_BE = 16, 672 __RTW89_RATE_MCS_NUM = 16, 673 }; 674 675 enum rtw89_nss { 676 RTW89_NSS_1 = 0, 677 RTW89_NSS_2 = 1, 678 /* HE DCM only support 1ss and 2ss */ 679 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 680 RTW89_NSS_3 = 2, 681 RTW89_NSS_4 = 3, 682 RTW89_NSS_NUM, 683 }; 684 685 enum rtw89_ntx { 686 RTW89_1TX = 0, 687 RTW89_2TX = 1, 688 RTW89_NTX_NUM, 689 }; 690 691 enum rtw89_beamforming_type { 692 RTW89_NONBF = 0, 693 RTW89_BF = 1, 694 RTW89_BF_NUM, 695 }; 696 697 enum rtw89_ofdma_type { 698 RTW89_NON_OFDMA = 0, 699 RTW89_OFDMA = 1, 700 RTW89_OFDMA_NUM, 701 }; 702 703 enum rtw89_regulation_type { 704 RTW89_WW = 0, 705 RTW89_ETSI = 1, 706 RTW89_FCC = 2, 707 RTW89_MKK = 3, 708 RTW89_NA = 4, 709 RTW89_IC = 5, 710 RTW89_KCC = 6, 711 RTW89_ACMA = 7, 712 RTW89_NCC = 8, 713 RTW89_MEXICO = 9, 714 RTW89_CHILE = 10, 715 RTW89_UKRAINE = 11, 716 RTW89_CN = 12, 717 RTW89_QATAR = 13, 718 RTW89_UK = 14, 719 RTW89_THAILAND = 15, 720 RTW89_REGD_NUM, 721 }; 722 723 enum rtw89_reg_6ghz_power { 724 RTW89_REG_6GHZ_POWER_VLP = 0, 725 RTW89_REG_6GHZ_POWER_LPI = 1, 726 RTW89_REG_6GHZ_POWER_STD = 2, 727 728 NUM_OF_RTW89_REG_6GHZ_POWER, 729 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 730 }; 731 732 enum rtw89_fw_pkt_ofld_type { 733 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 734 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 735 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 736 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 737 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 738 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 739 RTW89_PKT_OFLD_TYPE_NDP = 6, 740 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 741 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 742 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 743 RTW89_PKT_OFLD_TYPE_NUM, 744 }; 745 746 struct rtw89_txpwr_byrate { 747 s8 cck[RTW89_RATE_CCK_NUM]; 748 s8 ofdm[RTW89_RATE_OFDM_NUM]; 749 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 750 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 751 s8 offset[__RTW89_RATE_OFFSET_NUM]; 752 s8 trap; 753 }; 754 755 struct rtw89_rate_desc { 756 enum rtw89_nss nss; 757 enum rtw89_rate_section rs; 758 enum rtw89_ofdma_type ofdma; 759 u8 idx; 760 }; 761 762 #define PHY_STS_HDR_LEN 8 763 #define RF_PATH_MAX 4 764 #define RTW89_MAX_PPDU_CNT 8 765 struct rtw89_rx_phy_ppdu { 766 void *buf; 767 u32 len; 768 u8 rssi_avg; 769 u8 rssi[RF_PATH_MAX]; 770 u8 mac_id; 771 u8 chan_idx; 772 u8 ie; 773 u16 rate; 774 struct { 775 bool has; 776 u8 avg_snr; 777 u8 evm_max; 778 u8 evm_min; 779 } ofdm; 780 bool to_self; 781 bool valid; 782 }; 783 784 enum rtw89_mac_idx { 785 RTW89_MAC_0 = 0, 786 RTW89_MAC_1 = 1, 787 }; 788 789 enum rtw89_phy_idx { 790 RTW89_PHY_0 = 0, 791 RTW89_PHY_1 = 1, 792 RTW89_PHY_MAX 793 }; 794 795 enum rtw89_sub_entity_idx { 796 RTW89_SUB_ENTITY_0 = 0, 797 RTW89_SUB_ENTITY_1 = 1, 798 799 NUM_OF_RTW89_SUB_ENTITY, 800 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 801 }; 802 803 enum rtw89_rf_path { 804 RF_PATH_A = 0, 805 RF_PATH_B = 1, 806 RF_PATH_C = 2, 807 RF_PATH_D = 3, 808 RF_PATH_AB, 809 RF_PATH_AC, 810 RF_PATH_AD, 811 RF_PATH_BC, 812 RF_PATH_BD, 813 RF_PATH_CD, 814 RF_PATH_ABC, 815 RF_PATH_ABD, 816 RF_PATH_ACD, 817 RF_PATH_BCD, 818 RF_PATH_ABCD, 819 }; 820 821 enum rtw89_rf_path_bit { 822 RF_A = BIT(0), 823 RF_B = BIT(1), 824 RF_C = BIT(2), 825 RF_D = BIT(3), 826 827 RF_AB = (RF_A | RF_B), 828 RF_AC = (RF_A | RF_C), 829 RF_AD = (RF_A | RF_D), 830 RF_BC = (RF_B | RF_C), 831 RF_BD = (RF_B | RF_D), 832 RF_CD = (RF_C | RF_D), 833 834 RF_ABC = (RF_A | RF_B | RF_C), 835 RF_ABD = (RF_A | RF_B | RF_D), 836 RF_ACD = (RF_A | RF_C | RF_D), 837 RF_BCD = (RF_B | RF_C | RF_D), 838 839 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 840 }; 841 842 enum rtw89_bandwidth { 843 RTW89_CHANNEL_WIDTH_20 = 0, 844 RTW89_CHANNEL_WIDTH_40 = 1, 845 RTW89_CHANNEL_WIDTH_80 = 2, 846 RTW89_CHANNEL_WIDTH_160 = 3, 847 RTW89_CHANNEL_WIDTH_320 = 4, 848 849 /* keep index order above */ 850 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 851 852 RTW89_CHANNEL_WIDTH_80_80 = 5, 853 RTW89_CHANNEL_WIDTH_5 = 6, 854 RTW89_CHANNEL_WIDTH_10 = 7, 855 }; 856 857 enum rtw89_ps_mode { 858 RTW89_PS_MODE_NONE = 0, 859 RTW89_PS_MODE_RFOFF = 1, 860 RTW89_PS_MODE_CLK_GATED = 2, 861 RTW89_PS_MODE_PWR_GATED = 3, 862 }; 863 864 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 865 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 866 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 867 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 868 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 869 870 enum rtw89_ru_bandwidth { 871 RTW89_RU26 = 0, 872 RTW89_RU52 = 1, 873 RTW89_RU106 = 2, 874 RTW89_RU52_26 = 3, 875 RTW89_RU106_26 = 4, 876 RTW89_RU_NUM, 877 }; 878 879 enum rtw89_sc_offset { 880 RTW89_SC_DONT_CARE = 0, 881 RTW89_SC_20_UPPER = 1, 882 RTW89_SC_20_LOWER = 2, 883 RTW89_SC_20_UPMOST = 3, 884 RTW89_SC_20_LOWEST = 4, 885 RTW89_SC_20_UP2X = 5, 886 RTW89_SC_20_LOW2X = 6, 887 RTW89_SC_20_UP3X = 7, 888 RTW89_SC_20_LOW3X = 8, 889 RTW89_SC_40_UPPER = 9, 890 RTW89_SC_40_LOWER = 10, 891 }; 892 893 enum rtw89_wow_flags { 894 RTW89_WOW_FLAG_EN_MAGIC_PKT, 895 RTW89_WOW_FLAG_EN_REKEY_PKT, 896 RTW89_WOW_FLAG_EN_DISCONNECT, 897 RTW89_WOW_FLAG_NUM, 898 }; 899 900 struct rtw89_chan { 901 u8 channel; 902 u8 primary_channel; 903 enum rtw89_band band_type; 904 enum rtw89_bandwidth band_width; 905 906 /* The follow-up are derived from the above. We must ensure that it 907 * is assigned correctly in rtw89_chan_create() if new one is added. 908 */ 909 u32 freq; 910 enum rtw89_subband subband_type; 911 enum rtw89_sc_offset pri_ch_idx; 912 u8 pri_sb_idx; 913 }; 914 915 struct rtw89_chan_rcd { 916 u8 prev_primary_channel; 917 enum rtw89_band prev_band_type; 918 bool band_changed; 919 }; 920 921 struct rtw89_channel_help_params { 922 u32 tx_en; 923 }; 924 925 struct rtw89_port_reg { 926 u32 port_cfg; 927 u32 tbtt_prohib; 928 u32 bcn_area; 929 u32 bcn_early; 930 u32 tbtt_early; 931 u32 tbtt_agg; 932 u32 bcn_space; 933 u32 bcn_forcetx; 934 u32 bcn_err_cnt; 935 u32 bcn_err_flag; 936 u32 dtim_ctrl; 937 u32 tbtt_shift; 938 u32 bcn_cnt_tmr; 939 u32 tsftr_l; 940 u32 tsftr_h; 941 u32 md_tsft; 942 u32 bss_color; 943 u32 mbssid; 944 u32 mbssid_drop; 945 u32 tsf_sync; 946 u32 hiq_win[RTW89_PORT_NUM]; 947 }; 948 949 struct rtw89_txwd_body { 950 __le32 dword0; 951 __le32 dword1; 952 __le32 dword2; 953 __le32 dword3; 954 __le32 dword4; 955 __le32 dword5; 956 } __packed; 957 958 struct rtw89_txwd_body_v1 { 959 __le32 dword0; 960 __le32 dword1; 961 __le32 dword2; 962 __le32 dword3; 963 __le32 dword4; 964 __le32 dword5; 965 __le32 dword6; 966 __le32 dword7; 967 } __packed; 968 969 struct rtw89_txwd_body_v2 { 970 __le32 dword0; 971 __le32 dword1; 972 __le32 dword2; 973 __le32 dword3; 974 __le32 dword4; 975 __le32 dword5; 976 __le32 dword6; 977 __le32 dword7; 978 } __packed; 979 980 struct rtw89_txwd_info { 981 __le32 dword0; 982 __le32 dword1; 983 __le32 dword2; 984 __le32 dword3; 985 __le32 dword4; 986 __le32 dword5; 987 } __packed; 988 989 struct rtw89_txwd_info_v2 { 990 __le32 dword0; 991 __le32 dword1; 992 __le32 dword2; 993 __le32 dword3; 994 __le32 dword4; 995 __le32 dword5; 996 __le32 dword6; 997 __le32 dword7; 998 } __packed; 999 1000 struct rtw89_rx_desc_info { 1001 u16 pkt_size; 1002 u8 pkt_type; 1003 u8 drv_info_size; 1004 u8 phy_rpt_size; 1005 u8 hdr_cnv_size; 1006 u8 shift; 1007 u8 wl_hd_iv_len; 1008 bool long_rxdesc; 1009 bool bb_sel; 1010 bool mac_info_valid; 1011 u16 data_rate; 1012 u8 gi_ltf; 1013 u8 bw; 1014 u32 free_run_cnt; 1015 u8 user_id; 1016 bool sr_en; 1017 u8 ppdu_cnt; 1018 u8 ppdu_type; 1019 bool icv_err; 1020 bool crc32_err; 1021 bool hw_dec; 1022 bool sw_dec; 1023 bool addr1_match; 1024 u8 frag; 1025 u16 seq; 1026 u8 frame_type; 1027 u8 rx_pl_id; 1028 bool addr_cam_valid; 1029 u8 addr_cam_id; 1030 u8 sec_cam_id; 1031 u8 mac_id; 1032 u16 offset; 1033 u16 rxd_len; 1034 bool ready; 1035 }; 1036 1037 struct rtw89_rxdesc_short { 1038 __le32 dword0; 1039 __le32 dword1; 1040 __le32 dword2; 1041 __le32 dword3; 1042 } __packed; 1043 1044 struct rtw89_rxdesc_short_v2 { 1045 __le32 dword0; 1046 __le32 dword1; 1047 __le32 dword2; 1048 __le32 dword3; 1049 __le32 dword4; 1050 __le32 dword5; 1051 } __packed; 1052 1053 struct rtw89_rxdesc_long { 1054 __le32 dword0; 1055 __le32 dword1; 1056 __le32 dword2; 1057 __le32 dword3; 1058 __le32 dword4; 1059 __le32 dword5; 1060 __le32 dword6; 1061 __le32 dword7; 1062 } __packed; 1063 1064 struct rtw89_rxdesc_long_v2 { 1065 __le32 dword0; 1066 __le32 dword1; 1067 __le32 dword2; 1068 __le32 dword3; 1069 __le32 dword4; 1070 __le32 dword5; 1071 __le32 dword6; 1072 __le32 dword7; 1073 __le32 dword8; 1074 __le32 dword9; 1075 } __packed; 1076 1077 struct rtw89_tx_desc_info { 1078 u16 pkt_size; 1079 u8 wp_offset; 1080 u8 mac_id; 1081 u8 qsel; 1082 u8 ch_dma; 1083 u8 hdr_llc_len; 1084 bool is_bmc; 1085 bool en_wd_info; 1086 bool wd_page; 1087 bool use_rate; 1088 bool dis_data_fb; 1089 bool tid_indicate; 1090 bool agg_en; 1091 bool bk; 1092 u8 ampdu_density; 1093 u8 ampdu_num; 1094 bool sec_en; 1095 u8 addr_info_nr; 1096 u8 sec_keyid; 1097 u8 sec_type; 1098 u8 sec_cam_idx; 1099 u8 sec_seq[6]; 1100 u16 data_rate; 1101 u16 data_retry_lowest_rate; 1102 bool fw_dl; 1103 u16 seq; 1104 bool a_ctrl_bsr; 1105 u8 hw_ssn_sel; 1106 #define RTW89_MGMT_HW_SSN_SEL 1 1107 u8 hw_seq_mode; 1108 #define RTW89_MGMT_HW_SEQ_MODE 1 1109 bool hiq; 1110 u8 port; 1111 bool er_cap; 1112 }; 1113 1114 struct rtw89_core_tx_request { 1115 enum rtw89_core_tx_type tx_type; 1116 1117 struct sk_buff *skb; 1118 struct ieee80211_vif *vif; 1119 struct ieee80211_sta *sta; 1120 struct rtw89_tx_desc_info desc_info; 1121 }; 1122 1123 struct rtw89_txq { 1124 struct list_head list; 1125 unsigned long flags; 1126 int wait_cnt; 1127 }; 1128 1129 struct rtw89_mac_ax_gnt { 1130 u8 gnt_bt_sw_en; 1131 u8 gnt_bt; 1132 u8 gnt_wl_sw_en; 1133 u8 gnt_wl; 1134 } __packed; 1135 1136 #define RTW89_MAC_AX_COEX_GNT_NR 2 1137 struct rtw89_mac_ax_coex_gnt { 1138 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1139 }; 1140 1141 enum rtw89_btc_ncnt { 1142 BTC_NCNT_POWER_ON = 0x0, 1143 BTC_NCNT_POWER_OFF, 1144 BTC_NCNT_INIT_COEX, 1145 BTC_NCNT_SCAN_START, 1146 BTC_NCNT_SCAN_FINISH, 1147 BTC_NCNT_SPECIAL_PACKET, 1148 BTC_NCNT_SWITCH_BAND, 1149 BTC_NCNT_RFK_TIMEOUT, 1150 BTC_NCNT_SHOW_COEX_INFO, 1151 BTC_NCNT_ROLE_INFO, 1152 BTC_NCNT_CONTROL, 1153 BTC_NCNT_RADIO_STATE, 1154 BTC_NCNT_CUSTOMERIZE, 1155 BTC_NCNT_WL_RFK, 1156 BTC_NCNT_WL_STA, 1157 BTC_NCNT_FWINFO, 1158 BTC_NCNT_TIMER, 1159 BTC_NCNT_NUM 1160 }; 1161 1162 enum rtw89_btc_btinfo { 1163 BTC_BTINFO_L0 = 0, 1164 BTC_BTINFO_L1, 1165 BTC_BTINFO_L2, 1166 BTC_BTINFO_L3, 1167 BTC_BTINFO_H0, 1168 BTC_BTINFO_H1, 1169 BTC_BTINFO_H2, 1170 BTC_BTINFO_H3, 1171 BTC_BTINFO_MAX 1172 }; 1173 1174 enum rtw89_btc_dcnt { 1175 BTC_DCNT_RUN = 0x0, 1176 BTC_DCNT_CX_RUNINFO, 1177 BTC_DCNT_RPT, 1178 BTC_DCNT_RPT_HANG, 1179 BTC_DCNT_CYCLE, 1180 BTC_DCNT_CYCLE_HANG, 1181 BTC_DCNT_W1, 1182 BTC_DCNT_W1_HANG, 1183 BTC_DCNT_B1, 1184 BTC_DCNT_B1_HANG, 1185 BTC_DCNT_TDMA_NONSYNC, 1186 BTC_DCNT_SLOT_NONSYNC, 1187 BTC_DCNT_BTCNT_HANG, 1188 BTC_DCNT_WL_SLOT_DRIFT, 1189 BTC_DCNT_WL_STA_LAST, 1190 BTC_DCNT_BT_SLOT_DRIFT, 1191 BTC_DCNT_BT_SLOT_FLOOD, 1192 BTC_DCNT_FDDT_TRIG, 1193 BTC_DCNT_E2G, 1194 BTC_DCNT_E2G_HANG, 1195 BTC_DCNT_NUM 1196 }; 1197 1198 enum rtw89_btc_wl_state_cnt { 1199 BTC_WCNT_SCANAP = 0x0, 1200 BTC_WCNT_DHCP, 1201 BTC_WCNT_EAPOL, 1202 BTC_WCNT_ARP, 1203 BTC_WCNT_SCBDUPDATE, 1204 BTC_WCNT_RFK_REQ, 1205 BTC_WCNT_RFK_GO, 1206 BTC_WCNT_RFK_REJECT, 1207 BTC_WCNT_RFK_TIMEOUT, 1208 BTC_WCNT_CH_UPDATE, 1209 BTC_WCNT_NUM 1210 }; 1211 1212 enum rtw89_btc_bt_state_cnt { 1213 BTC_BCNT_RETRY = 0x0, 1214 BTC_BCNT_REINIT, 1215 BTC_BCNT_REENABLE, 1216 BTC_BCNT_SCBDREAD, 1217 BTC_BCNT_RELINK, 1218 BTC_BCNT_IGNOWL, 1219 BTC_BCNT_INQPAG, 1220 BTC_BCNT_INQ, 1221 BTC_BCNT_PAGE, 1222 BTC_BCNT_ROLESW, 1223 BTC_BCNT_AFH, 1224 BTC_BCNT_INFOUPDATE, 1225 BTC_BCNT_INFOSAME, 1226 BTC_BCNT_SCBDUPDATE, 1227 BTC_BCNT_HIPRI_TX, 1228 BTC_BCNT_HIPRI_RX, 1229 BTC_BCNT_LOPRI_TX, 1230 BTC_BCNT_LOPRI_RX, 1231 BTC_BCNT_POLUT, 1232 BTC_BCNT_RATECHG, 1233 BTC_BCNT_NUM 1234 }; 1235 1236 enum rtw89_btc_bt_profile { 1237 BTC_BT_NOPROFILE = 0, 1238 BTC_BT_HFP = BIT(0), 1239 BTC_BT_HID = BIT(1), 1240 BTC_BT_A2DP = BIT(2), 1241 BTC_BT_PAN = BIT(3), 1242 BTC_PROFILE_MAX = 4, 1243 }; 1244 1245 struct rtw89_btc_ant_info { 1246 u8 type; /* shared, dedicated */ 1247 u8 num; 1248 u8 isolation; 1249 1250 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1251 u8 diversity: 1; 1252 u8 btg_pos: 2; 1253 u8 stream_cnt: 4; 1254 }; 1255 1256 enum rtw89_tfc_dir { 1257 RTW89_TFC_UL, 1258 RTW89_TFC_DL, 1259 }; 1260 1261 struct rtw89_btc_wl_smap { 1262 u32 busy: 1; 1263 u32 scan: 1; 1264 u32 connecting: 1; 1265 u32 roaming: 1; 1266 u32 _4way: 1; 1267 u32 rf_off: 1; 1268 u32 lps: 2; 1269 u32 ips: 1; 1270 u32 init_ok: 1; 1271 u32 traffic_dir : 2; 1272 u32 rf_off_pre: 1; 1273 u32 lps_pre: 2; 1274 }; 1275 1276 enum rtw89_tfc_lv { 1277 RTW89_TFC_IDLE, 1278 RTW89_TFC_ULTRA_LOW, 1279 RTW89_TFC_LOW, 1280 RTW89_TFC_MID, 1281 RTW89_TFC_HIGH, 1282 }; 1283 1284 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1285 DECLARE_EWMA(tp, 10, 2); 1286 1287 struct rtw89_traffic_stats { 1288 /* units in bytes */ 1289 u64 tx_unicast; 1290 u64 rx_unicast; 1291 u32 tx_avg_len; 1292 u32 rx_avg_len; 1293 1294 /* count for packets */ 1295 u64 tx_cnt; 1296 u64 rx_cnt; 1297 1298 /* units in Mbps */ 1299 u32 tx_throughput; 1300 u32 rx_throughput; 1301 u32 tx_throughput_raw; 1302 u32 rx_throughput_raw; 1303 1304 u32 rx_tf_acc; 1305 u32 rx_tf_periodic; 1306 1307 enum rtw89_tfc_lv tx_tfc_lv; 1308 enum rtw89_tfc_lv rx_tfc_lv; 1309 struct ewma_tp tx_ewma_tp; 1310 struct ewma_tp rx_ewma_tp; 1311 1312 u16 tx_rate; 1313 u16 rx_rate; 1314 }; 1315 1316 struct rtw89_btc_statistic { 1317 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1318 struct rtw89_traffic_stats traffic; 1319 }; 1320 1321 #define BTC_WL_RSSI_THMAX 4 1322 1323 struct rtw89_btc_wl_link_info { 1324 struct rtw89_btc_statistic stat; 1325 enum rtw89_tfc_dir dir; 1326 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1327 u8 mac_addr[ETH_ALEN]; 1328 u8 busy; 1329 u8 ch; 1330 u8 bw; 1331 u8 band; 1332 u8 role; 1333 u8 pid; 1334 u8 phy; 1335 u8 dtim_period; 1336 u8 mode; 1337 1338 u8 mac_id; 1339 u8 tx_retry; 1340 1341 u32 bcn_period; 1342 u32 busy_t; 1343 u32 tx_time; 1344 u32 client_cnt; 1345 u32 rx_rate_drop_cnt; 1346 1347 u32 active: 1; 1348 u32 noa: 1; 1349 u32 client_ps: 1; 1350 u32 connected: 2; 1351 }; 1352 1353 union rtw89_btc_wl_state_map { 1354 u32 val; 1355 struct rtw89_btc_wl_smap map; 1356 }; 1357 1358 struct rtw89_btc_bt_hfp_desc { 1359 u32 exist: 1; 1360 u32 type: 2; 1361 u32 rsvd: 29; 1362 }; 1363 1364 struct rtw89_btc_bt_hid_desc { 1365 u32 exist: 1; 1366 u32 slot_info: 2; 1367 u32 pair_cnt: 2; 1368 u32 type: 8; 1369 u32 rsvd: 19; 1370 }; 1371 1372 struct rtw89_btc_bt_a2dp_desc { 1373 u8 exist: 1; 1374 u8 exist_last: 1; 1375 u8 play_latency: 1; 1376 u8 type: 3; 1377 u8 active: 1; 1378 u8 sink: 1; 1379 1380 u8 bitpool; 1381 u16 vendor_id; 1382 u32 device_name; 1383 u32 flush_time; 1384 }; 1385 1386 struct rtw89_btc_bt_pan_desc { 1387 u32 exist: 1; 1388 u32 type: 1; 1389 u32 active: 1; 1390 u32 rsvd: 29; 1391 }; 1392 1393 struct rtw89_btc_bt_rfk_info { 1394 u32 run: 1; 1395 u32 req: 1; 1396 u32 timeout: 1; 1397 u32 rsvd: 29; 1398 }; 1399 1400 union rtw89_btc_bt_rfk_info_map { 1401 u32 val; 1402 struct rtw89_btc_bt_rfk_info map; 1403 }; 1404 1405 struct rtw89_btc_bt_ver_info { 1406 u32 fw_coex; /* match with which coex_ver */ 1407 u32 fw; 1408 }; 1409 1410 struct rtw89_btc_bool_sta_chg { 1411 u32 now: 1; 1412 u32 last: 1; 1413 u32 remain: 1; 1414 u32 srvd: 29; 1415 }; 1416 1417 struct rtw89_btc_u8_sta_chg { 1418 u8 now; 1419 u8 last; 1420 u8 remain; 1421 u8 rsvd; 1422 }; 1423 1424 struct rtw89_btc_wl_scan_info { 1425 u8 band[RTW89_PHY_MAX]; 1426 u8 phy_map; 1427 u8 rsvd; 1428 }; 1429 1430 struct rtw89_btc_wl_dbcc_info { 1431 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1432 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1433 u8 real_band[RTW89_PHY_MAX]; 1434 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1435 }; 1436 1437 struct rtw89_btc_wl_active_role { 1438 u8 connected: 1; 1439 u8 pid: 3; 1440 u8 phy: 1; 1441 u8 noa: 1; 1442 u8 band: 2; 1443 1444 u8 client_ps: 1; 1445 u8 bw: 7; 1446 1447 u8 role; 1448 u8 ch; 1449 1450 u16 tx_lvl; 1451 u16 rx_lvl; 1452 u16 tx_rate; 1453 u16 rx_rate; 1454 }; 1455 1456 struct rtw89_btc_wl_active_role_v1 { 1457 u8 connected: 1; 1458 u8 pid: 3; 1459 u8 phy: 1; 1460 u8 noa: 1; 1461 u8 band: 2; 1462 1463 u8 client_ps: 1; 1464 u8 bw: 7; 1465 1466 u8 role; 1467 u8 ch; 1468 1469 u16 tx_lvl; 1470 u16 rx_lvl; 1471 u16 tx_rate; 1472 u16 rx_rate; 1473 1474 u32 noa_duration; /* ms */ 1475 }; 1476 1477 struct rtw89_btc_wl_active_role_v2 { 1478 u8 connected: 1; 1479 u8 pid: 3; 1480 u8 phy: 1; 1481 u8 noa: 1; 1482 u8 band: 2; 1483 1484 u8 client_ps: 1; 1485 u8 bw: 7; 1486 1487 u8 role; 1488 u8 ch; 1489 1490 u32 noa_duration; /* ms */ 1491 }; 1492 1493 struct rtw89_btc_wl_role_info_bpos { 1494 u16 none: 1; 1495 u16 station: 1; 1496 u16 ap: 1; 1497 u16 vap: 1; 1498 u16 adhoc: 1; 1499 u16 adhoc_master: 1; 1500 u16 mesh: 1; 1501 u16 moniter: 1; 1502 u16 p2p_device: 1; 1503 u16 p2p_gc: 1; 1504 u16 p2p_go: 1; 1505 u16 nan: 1; 1506 }; 1507 1508 struct rtw89_btc_wl_scc_ctrl { 1509 u8 null_role1; 1510 u8 null_role2; 1511 u8 ebt_null; /* if tx null at EBT slot */ 1512 }; 1513 1514 union rtw89_btc_wl_role_info_map { 1515 u16 val; 1516 struct rtw89_btc_wl_role_info_bpos role; 1517 }; 1518 1519 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1520 u8 connect_cnt; 1521 u8 link_mode; 1522 union rtw89_btc_wl_role_info_map role_map; 1523 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1524 }; 1525 1526 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1527 u8 connect_cnt; 1528 u8 link_mode; 1529 union rtw89_btc_wl_role_info_map role_map; 1530 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1531 u32 mrole_type; /* btc_wl_mrole_type */ 1532 u32 mrole_noa_duration; /* ms */ 1533 1534 u32 dbcc_en: 1; 1535 u32 dbcc_chg: 1; 1536 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1537 u32 link_mode_chg: 1; 1538 u32 rsvd: 27; 1539 }; 1540 1541 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1542 u8 connect_cnt; 1543 u8 link_mode; 1544 union rtw89_btc_wl_role_info_map role_map; 1545 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1546 u32 mrole_type; /* btc_wl_mrole_type */ 1547 u32 mrole_noa_duration; /* ms */ 1548 1549 u32 dbcc_en: 1; 1550 u32 dbcc_chg: 1; 1551 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1552 u32 link_mode_chg: 1; 1553 u32 rsvd: 27; 1554 }; 1555 1556 struct rtw89_btc_wl_ver_info { 1557 u32 fw_coex; /* match with which coex_ver */ 1558 u32 fw; 1559 u32 mac; 1560 u32 bb; 1561 u32 rf; 1562 }; 1563 1564 struct rtw89_btc_wl_afh_info { 1565 u8 en; 1566 u8 ch; 1567 u8 bw; 1568 u8 rsvd; 1569 } __packed; 1570 1571 struct rtw89_btc_wl_rfk_info { 1572 u32 state: 2; 1573 u32 path_map: 4; 1574 u32 phy_map: 2; 1575 u32 band: 2; 1576 u32 type: 8; 1577 u32 rsvd: 14; 1578 }; 1579 1580 struct rtw89_btc_bt_smap { 1581 u32 connect: 1; 1582 u32 ble_connect: 1; 1583 u32 acl_busy: 1; 1584 u32 sco_busy: 1; 1585 u32 mesh_busy: 1; 1586 u32 inq_pag: 1; 1587 }; 1588 1589 union rtw89_btc_bt_state_map { 1590 u32 val; 1591 struct rtw89_btc_bt_smap map; 1592 }; 1593 1594 #define BTC_BT_RSSI_THMAX 4 1595 #define BTC_BT_AFH_GROUP 12 1596 #define BTC_BT_AFH_LE_GROUP 5 1597 1598 struct rtw89_btc_bt_link_info { 1599 struct rtw89_btc_u8_sta_chg profile_cnt; 1600 struct rtw89_btc_bool_sta_chg multi_link; 1601 struct rtw89_btc_bool_sta_chg relink; 1602 struct rtw89_btc_bt_hfp_desc hfp_desc; 1603 struct rtw89_btc_bt_hid_desc hid_desc; 1604 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1605 struct rtw89_btc_bt_pan_desc pan_desc; 1606 union rtw89_btc_bt_state_map status; 1607 1608 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1609 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1610 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1611 u8 afh_map[BTC_BT_AFH_GROUP]; 1612 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1613 1614 u32 role_sw: 1; 1615 u32 slave_role: 1; 1616 u32 afh_update: 1; 1617 u32 cqddr: 1; 1618 u32 rssi: 8; 1619 u32 tx_3m: 1; 1620 u32 rsvd: 19; 1621 }; 1622 1623 struct rtw89_btc_3rdcx_info { 1624 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1625 u8 hw_coex; 1626 u16 rsvd; 1627 }; 1628 1629 struct rtw89_btc_dm_emap { 1630 u32 init: 1; 1631 u32 pta_owner: 1; 1632 u32 wl_rfk_timeout: 1; 1633 u32 bt_rfk_timeout: 1; 1634 u32 wl_fw_hang: 1; 1635 u32 cycle_hang: 1; 1636 u32 w1_hang: 1; 1637 u32 b1_hang: 1; 1638 u32 tdma_no_sync: 1; 1639 u32 slot_no_sync: 1; 1640 u32 wl_slot_drift: 1; 1641 u32 bt_slot_drift: 1; 1642 u32 role_num_mismatch: 1; 1643 u32 null1_tx_late: 1; 1644 u32 bt_afh_conflict: 1; 1645 u32 bt_leafh_conflict: 1; 1646 u32 bt_slot_flood: 1; 1647 u32 wl_e2g_hang: 1; 1648 u32 wl_ver_mismatch: 1; 1649 u32 bt_ver_mismatch: 1; 1650 }; 1651 1652 union rtw89_btc_dm_error_map { 1653 u32 val; 1654 struct rtw89_btc_dm_emap map; 1655 }; 1656 1657 struct rtw89_btc_rf_para { 1658 u32 tx_pwr_freerun; 1659 u32 rx_gain_freerun; 1660 u32 tx_pwr_perpkt; 1661 u32 rx_gain_perpkt; 1662 }; 1663 1664 struct rtw89_btc_wl_nhm { 1665 u8 instant_wl_nhm_dbm; 1666 u8 instant_wl_nhm_per_mhz; 1667 u16 valid_record_times; 1668 s8 record_pwr[16]; 1669 u8 record_ratio[16]; 1670 s8 pwr; /* dbm_per_MHz */ 1671 u8 ratio; 1672 u8 current_status; 1673 u8 refresh; 1674 bool start_flag; 1675 s8 pwr_max; 1676 s8 pwr_min; 1677 }; 1678 1679 struct rtw89_btc_wl_info { 1680 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1681 struct rtw89_btc_wl_rfk_info rfk_info; 1682 struct rtw89_btc_wl_ver_info ver_info; 1683 struct rtw89_btc_wl_afh_info afh_info; 1684 struct rtw89_btc_wl_role_info role_info; 1685 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1686 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1687 struct rtw89_btc_wl_scan_info scan_info; 1688 struct rtw89_btc_wl_dbcc_info dbcc_info; 1689 struct rtw89_btc_rf_para rf_para; 1690 struct rtw89_btc_wl_nhm nhm; 1691 union rtw89_btc_wl_state_map status; 1692 1693 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1694 u8 rssi_level; 1695 u8 cn_report; 1696 1697 bool scbd_change; 1698 u32 scbd; 1699 }; 1700 1701 struct rtw89_btc_module { 1702 struct rtw89_btc_ant_info ant; 1703 u8 rfe_type; 1704 u8 cv; 1705 1706 u8 bt_solo: 1; 1707 u8 bt_pos: 1; 1708 u8 switch_type: 1; 1709 u8 wa_type: 3; 1710 1711 u8 kt_ver_adie; 1712 }; 1713 1714 #define RTW89_BTC_DM_MAXSTEP 30 1715 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1716 1717 struct rtw89_btc_dm_step { 1718 u16 step[RTW89_BTC_DM_MAXSTEP]; 1719 u8 step_pos; 1720 bool step_ov; 1721 }; 1722 1723 struct rtw89_btc_init_info { 1724 struct rtw89_btc_module module; 1725 u8 wl_guard_ch; 1726 1727 u8 wl_only: 1; 1728 u8 wl_init_ok: 1; 1729 u8 dbcc_en: 1; 1730 u8 cx_other: 1; 1731 u8 bt_only: 1; 1732 1733 u16 rsvd; 1734 }; 1735 1736 struct rtw89_btc_wl_tx_limit_para { 1737 u16 enable; 1738 u32 tx_time; /* unit: us */ 1739 u16 tx_retry; 1740 }; 1741 1742 enum rtw89_btc_bt_scan_type { 1743 BTC_SCAN_INQ = 0, 1744 BTC_SCAN_PAGE, 1745 BTC_SCAN_BLE, 1746 BTC_SCAN_INIT, 1747 BTC_SCAN_TV, 1748 BTC_SCAN_ADV, 1749 BTC_SCAN_MAX1, 1750 }; 1751 1752 enum rtw89_btc_ble_scan_type { 1753 CXSCAN_BG = 0, 1754 CXSCAN_INIT, 1755 CXSCAN_LE, 1756 CXSCAN_MAX 1757 }; 1758 1759 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1760 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1761 1762 struct rtw89_btc_bt_scan_info_v1 { 1763 __le16 win; 1764 __le16 intvl; 1765 __le32 flags; 1766 } __packed; 1767 1768 struct rtw89_btc_bt_scan_info_v2 { 1769 __le16 win; 1770 __le16 intvl; 1771 } __packed; 1772 1773 struct rtw89_btc_fbtc_btscan_v1 { 1774 u8 fver; /* btc_ver::fcxbtscan */ 1775 u8 rsvd; 1776 __le16 rsvd2; 1777 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1778 } __packed; 1779 1780 struct rtw89_btc_fbtc_btscan_v2 { 1781 u8 fver; /* btc_ver::fcxbtscan */ 1782 u8 type; 1783 __le16 rsvd2; 1784 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1785 } __packed; 1786 1787 union rtw89_btc_fbtc_btscan { 1788 struct rtw89_btc_fbtc_btscan_v1 v1; 1789 struct rtw89_btc_fbtc_btscan_v2 v2; 1790 }; 1791 1792 struct rtw89_btc_bt_info { 1793 struct rtw89_btc_bt_link_info link_info; 1794 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1795 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1796 struct rtw89_btc_bt_ver_info ver_info; 1797 struct rtw89_btc_bool_sta_chg enable; 1798 struct rtw89_btc_bool_sta_chg inq_pag; 1799 struct rtw89_btc_rf_para rf_para; 1800 union rtw89_btc_bt_rfk_info_map rfk_info; 1801 1802 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1803 1804 u32 scbd; 1805 u32 feature; 1806 1807 u32 mbx_avl: 1; 1808 u32 whql_test: 1; 1809 u32 igno_wl: 1; 1810 u32 reinit: 1; 1811 u32 ble_scan_en: 1; 1812 u32 btg_type: 1; 1813 u32 inq: 1; 1814 u32 pag: 1; 1815 u32 run_patch_code: 1; 1816 u32 hi_lna_rx: 1; 1817 u32 scan_rx_low_pri: 1; 1818 u32 scan_info_update: 1; 1819 u32 rsvd: 20; 1820 }; 1821 1822 struct rtw89_btc_cx { 1823 struct rtw89_btc_wl_info wl; 1824 struct rtw89_btc_bt_info bt; 1825 struct rtw89_btc_3rdcx_info other; 1826 u32 state_map; 1827 u32 cnt_bt[BTC_BCNT_NUM]; 1828 u32 cnt_wl[BTC_WCNT_NUM]; 1829 }; 1830 1831 struct rtw89_btc_fbtc_tdma { 1832 u8 type; /* btc_ver::fcxtdma */ 1833 u8 rxflctrl; 1834 u8 txpause; 1835 u8 wtgle_n; 1836 u8 leak_n; 1837 u8 ext_ctrl; 1838 u8 rxflctrl_role; 1839 u8 option_ctrl; 1840 } __packed; 1841 1842 struct rtw89_btc_fbtc_tdma_v3 { 1843 u8 fver; /* btc_ver::fcxtdma */ 1844 u8 rsvd; 1845 __le16 rsvd1; 1846 struct rtw89_btc_fbtc_tdma tdma; 1847 } __packed; 1848 1849 union rtw89_btc_fbtc_tdma_le32 { 1850 struct rtw89_btc_fbtc_tdma v1; 1851 struct rtw89_btc_fbtc_tdma_v3 v3; 1852 }; 1853 1854 #define CXMREG_MAX 30 1855 #define CXMREG_MAX_V2 20 1856 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1857 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1858 1859 enum rtw89_btc_bt_sta_counter { 1860 BTC_BCNT_RFK_REQ = 0, 1861 BTC_BCNT_RFK_GO = 1, 1862 BTC_BCNT_RFK_REJECT = 2, 1863 BTC_BCNT_RFK_FAIL = 3, 1864 BTC_BCNT_RFK_TIMEOUT = 4, 1865 BTC_BCNT_HI_TX = 5, 1866 BTC_BCNT_HI_RX = 6, 1867 BTC_BCNT_LO_TX = 7, 1868 BTC_BCNT_LO_RX = 8, 1869 BTC_BCNT_POLLUTED = 9, 1870 BTC_BCNT_STA_MAX 1871 }; 1872 1873 enum rtw89_btc_bt_sta_counter_v105 { 1874 BTC_BCNT_RFK_REQ_V105 = 0, 1875 BTC_BCNT_HI_TX_V105 = 1, 1876 BTC_BCNT_HI_RX_V105 = 2, 1877 BTC_BCNT_LO_TX_V105 = 3, 1878 BTC_BCNT_LO_RX_V105 = 4, 1879 BTC_BCNT_POLLUTED_V105 = 5, 1880 BTC_BCNT_STA_MAX_V105 1881 }; 1882 1883 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1884 u16 fver; /* btc_ver::fcxbtcrpt */ 1885 u16 rpt_cnt; /* tmr counters */ 1886 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1887 u32 wl_fw_cx_offload; 1888 u32 wl_fw_ver; 1889 u32 rpt_enable; 1890 u32 rpt_para; /* ms */ 1891 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1892 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1893 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1894 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1895 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1896 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1897 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1898 u32 c2h_cnt; /* fw send c2h counter */ 1899 u32 h2c_cnt; /* fw recv h2c counter */ 1900 } __packed; 1901 1902 struct rtw89_btc_fbtc_rpt_ctrl_info { 1903 __le32 cnt; /* fw report counter */ 1904 __le32 en; /* report map */ 1905 __le32 para; /* not used */ 1906 1907 __le32 cnt_c2h; /* fw send c2h counter */ 1908 __le32 cnt_h2c; /* fw recv h2c counter */ 1909 __le32 len_c2h; /* The total length of the last C2H */ 1910 1911 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1912 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1913 } __packed; 1914 1915 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1916 __le32 cx_ver; /* match which driver's coex version */ 1917 __le32 fw_ver; 1918 __le32 en; /* report map */ 1919 1920 __le16 cnt; /* fw report counter */ 1921 __le16 cnt_c2h; /* fw send c2h counter */ 1922 __le16 cnt_h2c; /* fw recv h2c counter */ 1923 __le16 len_c2h; /* The total length of the last C2H */ 1924 1925 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1926 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1927 } __packed; 1928 1929 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1930 __le32 cx_ver; /* match which driver's coex version */ 1931 __le32 cx_offload; 1932 __le32 fw_ver; 1933 } __packed; 1934 1935 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1936 __le32 cnt_empty; /* a2dp empty count */ 1937 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1938 __le32 cnt_tx; 1939 __le32 cnt_ack; 1940 __le32 cnt_nack; 1941 } __packed; 1942 1943 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1944 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1945 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1946 __le32 cnt_recv; /* fw recv mailbox counter */ 1947 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1948 } __packed; 1949 1950 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1951 u8 fver; 1952 u8 rsvd; 1953 __le16 rsvd1; 1954 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1955 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1956 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1957 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1958 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1959 } __packed; 1960 1961 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1962 u8 fver; 1963 u8 rsvd; 1964 __le16 rsvd1; 1965 1966 u8 gnt_val[RTW89_PHY_MAX][4]; 1967 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1968 1969 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1970 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1971 } __packed; 1972 1973 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1974 u8 fver; 1975 u8 rsvd; 1976 __le16 rsvd1; 1977 1978 u8 gnt_val[RTW89_PHY_MAX][4]; 1979 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1980 1981 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1982 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1983 } __packed; 1984 1985 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1986 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 1987 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 1988 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 1989 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 1990 }; 1991 1992 enum rtw89_fbtc_ext_ctrl_type { 1993 CXECTL_OFF = 0x0, /* tdma off */ 1994 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1995 CXECTL_EXT = 0x2, 1996 CXECTL_MAX 1997 }; 1998 1999 union rtw89_btc_fbtc_rxflct { 2000 u8 val; 2001 u8 type: 3; 2002 u8 tgln_n: 5; 2003 }; 2004 2005 enum rtw89_btc_cxst_state { 2006 CXST_OFF = 0x0, 2007 CXST_B2W = 0x1, 2008 CXST_W1 = 0x2, 2009 CXST_W2 = 0x3, 2010 CXST_W2B = 0x4, 2011 CXST_B1 = 0x5, 2012 CXST_B2 = 0x6, 2013 CXST_B3 = 0x7, 2014 CXST_B4 = 0x8, 2015 CXST_LK = 0x9, 2016 CXST_BLK = 0xa, 2017 CXST_E2G = 0xb, 2018 CXST_E5G = 0xc, 2019 CXST_EBT = 0xd, 2020 CXST_ENULL = 0xe, 2021 CXST_WLK = 0xf, 2022 CXST_W1FDD = 0x10, 2023 CXST_B1FDD = 0x11, 2024 CXST_MAX = 0x12, 2025 }; 2026 2027 enum rtw89_btc_cxevnt { 2028 CXEVNT_TDMA_ENTRY = 0x0, 2029 CXEVNT_WL_TMR, 2030 CXEVNT_B1_TMR, 2031 CXEVNT_B2_TMR, 2032 CXEVNT_B3_TMR, 2033 CXEVNT_B4_TMR, 2034 CXEVNT_W2B_TMR, 2035 CXEVNT_B2W_TMR, 2036 CXEVNT_BCN_EARLY, 2037 CXEVNT_A2DP_EMPTY, 2038 CXEVNT_LK_END, 2039 CXEVNT_RX_ISR, 2040 CXEVNT_RX_FC0, 2041 CXEVNT_RX_FC1, 2042 CXEVNT_BT_RELINK, 2043 CXEVNT_BT_RETRY, 2044 CXEVNT_E2G, 2045 CXEVNT_E5G, 2046 CXEVNT_EBT, 2047 CXEVNT_ENULL, 2048 CXEVNT_DRV_WLK, 2049 CXEVNT_BCN_OK, 2050 CXEVNT_BT_CHANGE, 2051 CXEVNT_EBT_EXTEND, 2052 CXEVNT_E2G_NULL1, 2053 CXEVNT_B1FDD_TMR, 2054 CXEVNT_MAX 2055 }; 2056 2057 enum { 2058 CXBCN_ALL = 0x0, 2059 CXBCN_ALL_OK, 2060 CXBCN_BT_SLOT, 2061 CXBCN_BT_OK, 2062 CXBCN_MAX 2063 }; 2064 2065 enum btc_slot_type { 2066 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2067 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2068 CXSTYPE_NUM, 2069 }; 2070 2071 enum { /* TIME */ 2072 CXT_BT = 0x0, 2073 CXT_WL = 0x1, 2074 CXT_MAX 2075 }; 2076 2077 enum { /* TIME-A2DP */ 2078 CXT_FLCTRL_OFF = 0x0, 2079 CXT_FLCTRL_ON = 0x1, 2080 CXT_FLCTRL_MAX 2081 }; 2082 2083 enum { /* STEP TYPE */ 2084 CXSTEP_NONE = 0x0, 2085 CXSTEP_EVNT = 0x1, 2086 CXSTEP_SLOT = 0x2, 2087 CXSTEP_MAX, 2088 }; 2089 2090 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2091 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2092 RPT_BT_AFH_SEQ_LE = 0x20 2093 }; 2094 2095 #define BTC_DBG_MAX1 32 2096 struct rtw89_btc_fbtc_gpio_dbg { 2097 u8 fver; /* btc_ver::fcxgpiodbg */ 2098 u8 rsvd; 2099 u16 rsvd2; 2100 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2101 u32 pre_state; /* the debug signal is 1 or 0 */ 2102 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2103 } __packed; 2104 2105 struct rtw89_btc_fbtc_mreg_val_v1 { 2106 u8 fver; /* btc_ver::fcxmreg */ 2107 u8 reg_num; 2108 __le16 rsvd; 2109 __le32 mreg_val[CXMREG_MAX]; 2110 } __packed; 2111 2112 struct rtw89_btc_fbtc_mreg_val_v2 { 2113 u8 fver; /* btc_ver::fcxmreg */ 2114 u8 reg_num; 2115 __le16 rsvd; 2116 __le32 mreg_val[CXMREG_MAX_V2]; 2117 } __packed; 2118 2119 union rtw89_btc_fbtc_mreg_val { 2120 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2121 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2122 }; 2123 2124 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2125 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2126 .offset = cpu_to_le32(__offset), } 2127 2128 struct rtw89_btc_fbtc_mreg { 2129 __le16 type; 2130 __le16 bytes; 2131 __le32 offset; 2132 } __packed; 2133 2134 struct rtw89_btc_fbtc_slot { 2135 __le16 dur; 2136 __le32 cxtbl; 2137 __le16 cxtype; 2138 } __packed; 2139 2140 struct rtw89_btc_fbtc_slots { 2141 u8 fver; /* btc_ver::fcxslots */ 2142 u8 tbl_num; 2143 __le16 rsvd; 2144 __le32 update_map; 2145 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2146 } __packed; 2147 2148 struct rtw89_btc_fbtc_step { 2149 u8 type; 2150 u8 val; 2151 __le16 difft; 2152 } __packed; 2153 2154 struct rtw89_btc_fbtc_steps_v2 { 2155 u8 fver; /* btc_ver::fcxstep */ 2156 u8 rsvd; 2157 __le16 cnt; 2158 __le16 pos_old; 2159 __le16 pos_new; 2160 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2161 } __packed; 2162 2163 struct rtw89_btc_fbtc_steps_v3 { 2164 u8 fver; 2165 u8 en; 2166 __le16 rsvd; 2167 __le32 cnt; 2168 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2169 } __packed; 2170 2171 union rtw89_btc_fbtc_steps_info { 2172 struct rtw89_btc_fbtc_steps_v2 v2; 2173 struct rtw89_btc_fbtc_steps_v3 v3; 2174 }; 2175 2176 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2177 u8 fver; /* btc_ver::fcxcysta */ 2178 u8 rsvd; 2179 __le16 cycles; /* total cycle number */ 2180 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2181 __le16 a2dpept; /* a2dp empty cnt */ 2182 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2183 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2184 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2185 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2186 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2187 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2188 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2189 __le16 tmax_a2dpept; /* max a2dp empty time */ 2190 __le16 tavg_lk; /* avg leak-slot time */ 2191 __le16 tmax_lk; /* max leak-slot time */ 2192 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2193 __le32 bcn_cnt[CXBCN_MAX]; 2194 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2195 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2196 __le32 skip_cnt; 2197 __le32 exception; 2198 __le32 except_cnt; 2199 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2200 } __packed; 2201 2202 struct rtw89_btc_fbtc_fdd_try_info { 2203 __le16 cycles[CXT_FLCTRL_MAX]; 2204 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2205 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2206 } __packed; 2207 2208 struct rtw89_btc_fbtc_cycle_time_info { 2209 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2210 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2211 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2212 } __packed; 2213 2214 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2215 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2216 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2217 } __packed; 2218 2219 struct rtw89_btc_fbtc_a2dp_trx_stat { 2220 u8 empty_cnt; 2221 u8 retry_cnt; 2222 u8 tx_rate; 2223 u8 tx_cnt; 2224 u8 ack_cnt; 2225 u8 nack_cnt; 2226 u8 rsvd1; 2227 u8 rsvd2; 2228 } __packed; 2229 2230 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2231 u8 empty_cnt; 2232 u8 retry_cnt; 2233 u8 tx_rate; 2234 u8 tx_cnt; 2235 u8 ack_cnt; 2236 u8 nack_cnt; 2237 u8 no_empty_cnt; 2238 u8 rsvd; 2239 } __packed; 2240 2241 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2242 __le16 cnt; /* a2dp empty cnt */ 2243 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2244 __le16 tavg; /* avg a2dp empty time */ 2245 __le16 tmax; /* max a2dp empty time */ 2246 } __packed; 2247 2248 struct rtw89_btc_fbtc_cycle_leak_info { 2249 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2250 __le16 tavg; /* avg leak-slot time */ 2251 __le16 tmax; /* max leak-slot time */ 2252 } __packed; 2253 2254 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2255 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2256 2257 struct rtw89_btc_fbtc_cycle_fddt_info { 2258 __le16 train_cycle; 2259 __le16 tp; 2260 2261 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2262 s8 bt_tx_power; /* decrease Tx power (dB) */ 2263 s8 bt_rx_gain; /* LNA constrain level */ 2264 u8 no_empty_cnt; 2265 2266 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2267 u8 cn; /* condition_num */ 2268 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2269 u8 train_result; /* refer to enum btc_fddt_check_map */ 2270 } __packed; 2271 2272 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2273 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2274 2275 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2276 __le16 train_cycle; 2277 __le16 tp; 2278 2279 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2280 s8 bt_tx_power; /* decrease Tx power (dB) */ 2281 s8 bt_rx_gain; /* LNA constrain level */ 2282 u8 no_empty_cnt; 2283 2284 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2285 u8 cn; /* condition_num */ 2286 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2287 u8 train_result; /* refer to enum btc_fddt_check_map */ 2288 } __packed; 2289 2290 struct rtw89_btc_fbtc_fddt_cell_status { 2291 s8 wl_tx_pwr; 2292 s8 bt_tx_pwr; 2293 s8 bt_rx_gain; 2294 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2295 } __packed; 2296 2297 struct rtw89_btc_fbtc_fddt_cell_status_v5 { 2298 s8 wl_tx_pwr; 2299 s8 bt_tx_pwr; 2300 s8 bt_rx_gain; 2301 } __packed; 2302 2303 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2304 u8 fver; 2305 u8 rsvd; 2306 __le16 cycles; /* total cycle number */ 2307 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2308 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2309 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2310 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2311 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2312 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2313 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2314 __le32 bcn_cnt[CXBCN_MAX]; 2315 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2316 __le32 skip_cnt; 2317 __le32 except_cnt; 2318 __le32 except_map; 2319 } __packed; 2320 2321 #define FDD_TRAIN_WL_DIRECTION 2 2322 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2323 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2324 2325 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2326 u8 fver; 2327 u8 rsvd; 2328 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2329 u8 except_cnt; 2330 2331 __le16 skip_cnt; 2332 __le16 cycles; /* total cycle number */ 2333 2334 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2335 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2336 __le16 bcn_cnt[CXBCN_MAX]; 2337 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2338 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2339 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2340 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2341 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2342 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2343 [FDD_TRAIN_WL_RSSI_LEVEL] 2344 [FDD_TRAIN_BT_RSSI_LEVEL]; 2345 __le32 except_map; 2346 } __packed; 2347 2348 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2349 u8 fver; 2350 u8 rsvd; 2351 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2352 u8 except_cnt; 2353 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2354 2355 __le16 skip_cnt; 2356 __le16 cycles; /* total cycle number */ 2357 2358 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2359 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2360 __le16 bcn_cnt[CXBCN_MAX]; 2361 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2362 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2363 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2364 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2365 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2366 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] 2367 [FDD_TRAIN_WL_RSSI_LEVEL] 2368 [FDD_TRAIN_BT_RSSI_LEVEL]; 2369 __le32 except_map; 2370 } __packed; 2371 2372 union rtw89_btc_fbtc_cysta_info { 2373 struct rtw89_btc_fbtc_cysta_v2 v2; 2374 struct rtw89_btc_fbtc_cysta_v3 v3; 2375 struct rtw89_btc_fbtc_cysta_v4 v4; 2376 struct rtw89_btc_fbtc_cysta_v5 v5; 2377 }; 2378 2379 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2380 u8 fver; /* btc_ver::fcxnullsta */ 2381 u8 rsvd; 2382 __le16 rsvd2; 2383 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2384 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2385 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2386 } __packed; 2387 2388 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2389 u8 fver; /* btc_ver::fcxnullsta */ 2390 u8 rsvd; 2391 __le16 rsvd2; 2392 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2393 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2394 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2395 } __packed; 2396 2397 union rtw89_btc_fbtc_cynullsta_info { 2398 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2399 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2400 }; 2401 2402 struct rtw89_btc_fbtc_btver { 2403 u8 fver; /* btc_ver::fcxbtver */ 2404 u8 rsvd; 2405 __le16 rsvd2; 2406 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2407 __le32 fw_ver; 2408 __le32 feature; 2409 } __packed; 2410 2411 struct rtw89_btc_fbtc_btafh { 2412 u8 fver; /* btc_ver::fcxbtafh */ 2413 u8 rsvd; 2414 __le16 rsvd2; 2415 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2416 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2417 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2418 } __packed; 2419 2420 struct rtw89_btc_fbtc_btafh_v2 { 2421 u8 fver; /* btc_ver::fcxbtafh */ 2422 u8 rsvd; 2423 u8 rsvd2; 2424 u8 map_type; 2425 u8 afh_l[4]; 2426 u8 afh_m[4]; 2427 u8 afh_h[4]; 2428 u8 afh_le_a[4]; 2429 u8 afh_le_b[4]; 2430 } __packed; 2431 2432 struct rtw89_btc_fbtc_btdevinfo { 2433 u8 fver; /* btc_ver::fcxbtdevinfo */ 2434 u8 rsvd; 2435 __le16 vendor_id; 2436 __le32 dev_name; /* only 24 bits valid */ 2437 __le32 flush_time; 2438 } __packed; 2439 2440 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2441 struct rtw89_btc_rf_trx_para { 2442 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2443 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2444 u8 bt_tx_power; /* decrease Tx power (dB) */ 2445 u8 bt_rx_gain; /* LNA constrain level */ 2446 }; 2447 2448 struct rtw89_btc_trx_info { 2449 u8 tx_lvl; 2450 u8 rx_lvl; 2451 u8 wl_rssi; 2452 u8 bt_rssi; 2453 2454 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2455 s8 rx_gain; /* rx gain table index (TBD.) */ 2456 s8 bt_tx_power; /* decrease Tx power (dB) */ 2457 s8 bt_rx_gain; /* LNA constrain level */ 2458 2459 u8 cn; /* condition_num */ 2460 s8 nhm; 2461 u8 bt_profile; 2462 u8 rsvd2; 2463 2464 u16 tx_rate; 2465 u16 rx_rate; 2466 2467 u32 tx_tp; 2468 u32 rx_tp; 2469 u32 rx_err_ratio; 2470 }; 2471 2472 struct rtw89_btc_dm { 2473 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2474 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2475 struct rtw89_btc_fbtc_tdma tdma; 2476 struct rtw89_btc_fbtc_tdma tdma_now; 2477 struct rtw89_mac_ax_coex_gnt gnt; 2478 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2479 struct rtw89_btc_rf_trx_para rf_trx_para; 2480 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2481 struct rtw89_btc_dm_step dm_step; 2482 struct rtw89_btc_wl_scc_ctrl wl_scc; 2483 struct rtw89_btc_trx_info trx_info; 2484 union rtw89_btc_dm_error_map error; 2485 u32 cnt_dm[BTC_DCNT_NUM]; 2486 u32 cnt_notify[BTC_NCNT_NUM]; 2487 2488 u32 update_slot_map; 2489 u32 set_ant_path; 2490 2491 u32 wl_only: 1; 2492 u32 wl_fw_cx_offload: 1; 2493 u32 freerun: 1; 2494 u32 fddt_train: 1; 2495 u32 wl_ps_ctrl: 2; 2496 u32 wl_mimo_ps: 1; 2497 u32 leak_ap: 1; 2498 u32 noisy_level: 3; 2499 u32 coex_info_map: 8; 2500 u32 bt_only: 1; 2501 u32 wl_btg_rx: 1; 2502 u32 trx_para_level: 8; 2503 u32 wl_stb_chg: 1; 2504 u32 pta_owner: 1; 2505 u32 tdma_instant_excute: 1; 2506 2507 u16 slot_dur[CXST_MAX]; 2508 2509 u8 run_reason; 2510 u8 run_action; 2511 2512 u8 wl_lna2: 1; 2513 }; 2514 2515 struct rtw89_btc_ctrl { 2516 u32 manual: 1; 2517 u32 igno_bt: 1; 2518 u32 always_freerun: 1; 2519 u32 trace_step: 16; 2520 u32 rsvd: 12; 2521 }; 2522 2523 struct rtw89_btc_dbg { 2524 /* cmd "rb" */ 2525 bool rb_done; 2526 u32 rb_val; 2527 }; 2528 2529 enum rtw89_btc_btf_fw_event { 2530 BTF_EVNT_RPT = 0, 2531 BTF_EVNT_BT_INFO = 1, 2532 BTF_EVNT_BT_SCBD = 2, 2533 BTF_EVNT_BT_REG = 3, 2534 BTF_EVNT_CX_RUNINFO = 4, 2535 BTF_EVNT_BT_PSD = 5, 2536 BTF_EVNT_BUF_OVERFLOW, 2537 BTF_EVNT_C2H_LOOPBACK, 2538 BTF_EVNT_MAX, 2539 }; 2540 2541 enum btf_fw_event_report { 2542 BTC_RPT_TYPE_CTRL = 0x0, 2543 BTC_RPT_TYPE_TDMA, 2544 BTC_RPT_TYPE_SLOT, 2545 BTC_RPT_TYPE_CYSTA, 2546 BTC_RPT_TYPE_STEP, 2547 BTC_RPT_TYPE_NULLSTA, 2548 BTC_RPT_TYPE_MREG, 2549 BTC_RPT_TYPE_GPIO_DBG, 2550 BTC_RPT_TYPE_BT_VER, 2551 BTC_RPT_TYPE_BT_SCAN, 2552 BTC_RPT_TYPE_BT_AFH, 2553 BTC_RPT_TYPE_BT_DEVICE, 2554 BTC_RPT_TYPE_TEST, 2555 BTC_RPT_TYPE_MAX = 31 2556 }; 2557 2558 enum rtw_btc_btf_reg_type { 2559 REG_MAC = 0x0, 2560 REG_BB = 0x1, 2561 REG_RF = 0x2, 2562 REG_BT_RF = 0x3, 2563 REG_BT_MODEM = 0x4, 2564 REG_BT_BLUEWIZE = 0x5, 2565 REG_BT_VENDOR = 0x6, 2566 REG_BT_LE = 0x7, 2567 REG_MAX_TYPE, 2568 }; 2569 2570 struct rtw89_btc_rpt_cmn_info { 2571 u32 rx_cnt; 2572 u32 rx_len; 2573 u32 req_len; /* expected rsp len */ 2574 u8 req_fver; /* expected rsp fver */ 2575 u8 rsp_fver; /* fver from fw */ 2576 u8 valid; 2577 } __packed; 2578 2579 union rtw89_btc_fbtc_btafh_info { 2580 struct rtw89_btc_fbtc_btafh v1; 2581 struct rtw89_btc_fbtc_btafh_v2 v2; 2582 }; 2583 2584 struct rtw89_btc_report_ctrl_state { 2585 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2586 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2587 }; 2588 2589 struct rtw89_btc_rpt_fbtc_tdma { 2590 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2591 union rtw89_btc_fbtc_tdma_le32 finfo; 2592 }; 2593 2594 struct rtw89_btc_rpt_fbtc_slots { 2595 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2596 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2597 }; 2598 2599 struct rtw89_btc_rpt_fbtc_cysta { 2600 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2601 union rtw89_btc_fbtc_cysta_info finfo; 2602 }; 2603 2604 struct rtw89_btc_rpt_fbtc_step { 2605 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2606 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2607 }; 2608 2609 struct rtw89_btc_rpt_fbtc_nullsta { 2610 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2611 union rtw89_btc_fbtc_cynullsta_info finfo; 2612 }; 2613 2614 struct rtw89_btc_rpt_fbtc_mreg { 2615 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2616 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2617 }; 2618 2619 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2620 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2621 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2622 }; 2623 2624 struct rtw89_btc_rpt_fbtc_btver { 2625 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2626 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2627 }; 2628 2629 struct rtw89_btc_rpt_fbtc_btscan { 2630 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2631 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2632 }; 2633 2634 struct rtw89_btc_rpt_fbtc_btafh { 2635 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2636 union rtw89_btc_fbtc_btafh_info finfo; 2637 }; 2638 2639 struct rtw89_btc_rpt_fbtc_btdev { 2640 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2641 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2642 }; 2643 2644 enum rtw89_btc_btfre_type { 2645 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2646 BTFRE_UNDEF_TYPE, 2647 BTFRE_EXCEPTION, 2648 BTFRE_MAX, 2649 }; 2650 2651 struct rtw89_btc_btf_fwinfo { 2652 u32 cnt_c2h; 2653 u32 cnt_h2c; 2654 u32 cnt_h2c_fail; 2655 u32 event[BTF_EVNT_MAX]; 2656 2657 u32 err[BTFRE_MAX]; 2658 u32 len_mismch; 2659 u32 fver_mismch; 2660 u32 rpt_en_map; 2661 2662 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2663 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2664 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2665 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2666 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2667 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2668 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2669 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2670 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2671 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2672 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2673 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2674 }; 2675 2676 struct rtw89_btc_ver { 2677 enum rtw89_core_chip_id chip_id; 2678 u32 fw_ver_code; 2679 2680 u8 fcxbtcrpt; 2681 u8 fcxtdma; 2682 u8 fcxslots; 2683 u8 fcxcysta; 2684 u8 fcxstep; 2685 u8 fcxnullsta; 2686 u8 fcxmreg; 2687 u8 fcxgpiodbg; 2688 u8 fcxbtver; 2689 u8 fcxbtscan; 2690 u8 fcxbtafh; 2691 u8 fcxbtdevinfo; 2692 u8 fwlrole; 2693 u8 frptmap; 2694 u8 fcxctrl; 2695 2696 u16 info_buf; 2697 u8 max_role_num; 2698 }; 2699 2700 #define RTW89_BTC_POLICY_MAXLEN 512 2701 2702 struct rtw89_btc { 2703 const struct rtw89_btc_ver *ver; 2704 2705 struct rtw89_btc_cx cx; 2706 struct rtw89_btc_dm dm; 2707 struct rtw89_btc_ctrl ctrl; 2708 struct rtw89_btc_module mdinfo; 2709 struct rtw89_btc_btf_fwinfo fwinfo; 2710 struct rtw89_btc_dbg dbg; 2711 2712 struct work_struct eapol_notify_work; 2713 struct work_struct arp_notify_work; 2714 struct work_struct dhcp_notify_work; 2715 struct work_struct icmp_notify_work; 2716 2717 u32 bt_req_len; 2718 2719 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2720 u16 policy_len; 2721 u16 policy_type; 2722 bool bt_req_en; 2723 bool update_policy_force; 2724 bool lps; 2725 }; 2726 2727 enum rtw89_btc_hmsg { 2728 RTW89_BTC_HMSG_TMR_EN = 0x0, 2729 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 2730 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 2731 RTW89_BTC_HMSG_FW_EV = 0x3, 2732 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 2733 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 2734 2735 NUM_OF_RTW89_BTC_HMSG, 2736 }; 2737 2738 enum rtw89_ra_mode { 2739 RTW89_RA_MODE_CCK = BIT(0), 2740 RTW89_RA_MODE_OFDM = BIT(1), 2741 RTW89_RA_MODE_HT = BIT(2), 2742 RTW89_RA_MODE_VHT = BIT(3), 2743 RTW89_RA_MODE_HE = BIT(4), 2744 RTW89_RA_MODE_EHT = BIT(5), 2745 }; 2746 2747 enum rtw89_ra_report_mode { 2748 RTW89_RA_RPT_MODE_LEGACY, 2749 RTW89_RA_RPT_MODE_HT, 2750 RTW89_RA_RPT_MODE_VHT, 2751 RTW89_RA_RPT_MODE_HE, 2752 RTW89_RA_RPT_MODE_EHT, 2753 }; 2754 2755 enum rtw89_dig_noisy_level { 2756 RTW89_DIG_NOISY_LEVEL0 = -1, 2757 RTW89_DIG_NOISY_LEVEL1 = 0, 2758 RTW89_DIG_NOISY_LEVEL2 = 1, 2759 RTW89_DIG_NOISY_LEVEL3 = 2, 2760 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2761 }; 2762 2763 enum rtw89_gi_ltf { 2764 RTW89_GILTF_LGI_4XHE32 = 0, 2765 RTW89_GILTF_SGI_4XHE08 = 1, 2766 RTW89_GILTF_2XHE16 = 2, 2767 RTW89_GILTF_2XHE08 = 3, 2768 RTW89_GILTF_1XHE16 = 4, 2769 RTW89_GILTF_1XHE08 = 5, 2770 RTW89_GILTF_MAX 2771 }; 2772 2773 enum rtw89_rx_frame_type { 2774 RTW89_RX_TYPE_MGNT = 0, 2775 RTW89_RX_TYPE_CTRL = 1, 2776 RTW89_RX_TYPE_DATA = 2, 2777 RTW89_RX_TYPE_RSVD = 3, 2778 }; 2779 2780 struct rtw89_ra_info { 2781 u8 is_dis_ra:1; 2782 /* Bit0 : CCK 2783 * Bit1 : OFDM 2784 * Bit2 : HT 2785 * Bit3 : VHT 2786 * Bit4 : HE 2787 * Bit5 : EHT 2788 */ 2789 u8 mode_ctrl:6; 2790 u8 bw_cap:3; /* enum rtw89_bandwidth */ 2791 u8 macid; 2792 u8 dcm_cap:1; 2793 u8 er_cap:1; 2794 u8 init_rate_lv:2; 2795 u8 upd_all:1; 2796 u8 en_sgi:1; 2797 u8 ldpc_cap:1; 2798 u8 stbc_cap:1; 2799 u8 ss_num:3; 2800 u8 giltf:3; 2801 u8 upd_bw_nss_mask:1; 2802 u8 upd_mask:1; 2803 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2804 /* BFee CSI */ 2805 u8 band_num; 2806 u8 ra_csi_rate_en:1; 2807 u8 fixed_csi_rate_en:1; 2808 u8 cr_tbl_sel:1; 2809 u8 fix_giltf_en:1; 2810 u8 fix_giltf:3; 2811 u8 rsvd2:1; 2812 u8 csi_mcs_ss_idx; 2813 u8 csi_mode:2; 2814 u8 csi_gi_ltf:3; 2815 u8 csi_bw:3; 2816 }; 2817 2818 #define RTW89_PPDU_MAX_USR 4 2819 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2820 #define RTW89_PPDU_MAC_INFO_SIZE 8 2821 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2822 2823 #define RTW89_MAX_RX_AGG_NUM 64 2824 #define RTW89_MAX_TX_AGG_NUM 128 2825 2826 struct rtw89_ampdu_params { 2827 u16 agg_num; 2828 bool amsdu; 2829 }; 2830 2831 struct rtw89_ra_report { 2832 struct rate_info txrate; 2833 u32 bit_rate; 2834 u16 hw_rate; 2835 bool might_fallback_legacy; 2836 }; 2837 2838 DECLARE_EWMA(rssi, 10, 16); 2839 DECLARE_EWMA(evm, 10, 16); 2840 DECLARE_EWMA(snr, 10, 16); 2841 2842 struct rtw89_ba_cam_entry { 2843 struct list_head list; 2844 u8 tid; 2845 }; 2846 2847 #define RTW89_MAX_ADDR_CAM_NUM 128 2848 #define RTW89_MAX_BSSID_CAM_NUM 20 2849 #define RTW89_MAX_SEC_CAM_NUM 128 2850 #define RTW89_MAX_BA_CAM_NUM 8 2851 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2852 2853 struct rtw89_addr_cam_entry { 2854 u8 addr_cam_idx; 2855 u8 offset; 2856 u8 len; 2857 u8 valid : 1; 2858 u8 addr_mask : 6; 2859 u8 wapi : 1; 2860 u8 mask_sel : 2; 2861 u8 bssid_cam_idx: 6; 2862 2863 u8 sec_ent_mode; 2864 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2865 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2866 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2867 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2868 }; 2869 2870 struct rtw89_bssid_cam_entry { 2871 u8 bssid[ETH_ALEN]; 2872 u8 phy_idx; 2873 u8 bssid_cam_idx; 2874 u8 offset; 2875 u8 len; 2876 u8 valid : 1; 2877 u8 num; 2878 }; 2879 2880 struct rtw89_sec_cam_entry { 2881 u8 sec_cam_idx; 2882 u8 offset; 2883 u8 len; 2884 u8 type : 4; 2885 u8 ext_key : 1; 2886 u8 spp_mode : 1; 2887 /* 256 bits */ 2888 u8 key[32]; 2889 }; 2890 2891 struct rtw89_sta { 2892 u8 mac_id; 2893 bool disassoc; 2894 bool er_cap; 2895 struct rtw89_dev *rtwdev; 2896 struct rtw89_vif *rtwvif; 2897 struct rtw89_ra_info ra; 2898 struct rtw89_ra_report ra_report; 2899 int max_agg_wait; 2900 u8 prev_rssi; 2901 struct ewma_rssi avg_rssi; 2902 struct ewma_rssi rssi[RF_PATH_MAX]; 2903 struct ewma_snr avg_snr; 2904 struct ewma_evm evm_min[RF_PATH_MAX]; 2905 struct ewma_evm evm_max[RF_PATH_MAX]; 2906 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2907 struct ieee80211_rx_status rx_status; 2908 u16 rx_hw_rate; 2909 __le32 htc_template; 2910 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2911 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2912 struct list_head ba_cam_list; 2913 struct sk_buff_head roc_queue; 2914 2915 bool use_cfg_mask; 2916 struct cfg80211_bitrate_mask mask; 2917 2918 bool cctl_tx_time; 2919 u32 ampdu_max_time:4; 2920 bool cctl_tx_retry_limit; 2921 u32 data_tx_cnt_lmt:6; 2922 }; 2923 2924 struct rtw89_efuse { 2925 bool valid; 2926 bool power_k_valid; 2927 u8 xtal_cap; 2928 u8 addr[ETH_ALEN]; 2929 u8 rfe_type; 2930 char country_code[2]; 2931 }; 2932 2933 struct rtw89_phy_rate_pattern { 2934 u64 ra_mask; 2935 u16 rate; 2936 u8 ra_mode; 2937 bool enable; 2938 }; 2939 2940 struct rtw89_tx_wait_info { 2941 struct rcu_head rcu_head; 2942 struct completion completion; 2943 bool tx_done; 2944 }; 2945 2946 struct rtw89_tx_skb_data { 2947 struct rtw89_tx_wait_info __rcu *wait; 2948 u8 hci_priv[]; 2949 }; 2950 2951 #define RTW89_ROC_IDLE_TIMEOUT 500 2952 #define RTW89_ROC_TX_TIMEOUT 30 2953 enum rtw89_roc_state { 2954 RTW89_ROC_IDLE, 2955 RTW89_ROC_NORMAL, 2956 RTW89_ROC_MGMT, 2957 }; 2958 2959 struct rtw89_roc { 2960 struct ieee80211_channel chan; 2961 struct delayed_work roc_work; 2962 enum ieee80211_roc_type type; 2963 enum rtw89_roc_state state; 2964 int duration; 2965 }; 2966 2967 #define RTW89_P2P_MAX_NOA_NUM 2 2968 2969 struct rtw89_p2p_ie_head { 2970 u8 eid; 2971 u8 ie_len; 2972 u8 oui[3]; 2973 u8 oui_type; 2974 } __packed; 2975 2976 struct rtw89_noa_attr_head { 2977 u8 attr_type; 2978 __le16 attr_len; 2979 u8 index; 2980 u8 oppps_ctwindow; 2981 } __packed; 2982 2983 struct rtw89_p2p_noa_ie { 2984 struct rtw89_p2p_ie_head p2p_head; 2985 struct rtw89_noa_attr_head noa_head; 2986 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 2987 } __packed; 2988 2989 struct rtw89_p2p_noa_setter { 2990 struct rtw89_p2p_noa_ie ie; 2991 u8 noa_count; 2992 u8 noa_index; 2993 }; 2994 2995 struct rtw89_vif { 2996 struct list_head list; 2997 struct rtw89_dev *rtwdev; 2998 struct rtw89_roc roc; 2999 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3000 enum rtw89_sub_entity_idx sub_entity_idx; 3001 enum rtw89_reg_6ghz_power reg_6ghz_power; 3002 3003 u8 mac_id; 3004 u8 port; 3005 u8 mac_addr[ETH_ALEN]; 3006 u8 bssid[ETH_ALEN]; 3007 u8 phy_idx; 3008 u8 mac_idx; 3009 u8 net_type; 3010 u8 wifi_role; 3011 u8 self_role; 3012 u8 wmm; 3013 u8 bcn_hit_cond; 3014 u8 hit_rule; 3015 u8 last_noa_nr; 3016 bool offchan; 3017 bool trigger; 3018 bool lsig_txop; 3019 u8 tgt_ind; 3020 u8 frm_tgt_ind; 3021 bool wowlan_pattern; 3022 bool wowlan_uc; 3023 bool wowlan_magic; 3024 bool is_hesta; 3025 bool last_a_ctrl; 3026 bool dyn_tb_bedge_en; 3027 bool pre_pwr_diff_en; 3028 bool pwr_diff_en; 3029 u8 def_tri_idx; 3030 u32 tdls_peer; 3031 struct work_struct update_beacon_work; 3032 struct rtw89_addr_cam_entry addr_cam; 3033 struct rtw89_bssid_cam_entry bssid_cam; 3034 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3035 struct rtw89_traffic_stats stats; 3036 struct rtw89_phy_rate_pattern rate_pattern; 3037 struct cfg80211_scan_request *scan_req; 3038 struct ieee80211_scan_ies *scan_ies; 3039 struct list_head general_pkt_list; 3040 struct rtw89_p2p_noa_setter p2p_noa; 3041 }; 3042 3043 enum rtw89_lv1_rcvy_step { 3044 RTW89_LV1_RCVY_STEP_1, 3045 RTW89_LV1_RCVY_STEP_2, 3046 }; 3047 3048 struct rtw89_hci_ops { 3049 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3050 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3051 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3052 void (*reset)(struct rtw89_dev *rtwdev); 3053 int (*start)(struct rtw89_dev *rtwdev); 3054 void (*stop)(struct rtw89_dev *rtwdev); 3055 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3056 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3057 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3058 3059 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3060 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3061 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3062 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3063 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3064 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3065 3066 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3067 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3068 int (*deinit)(struct rtw89_dev *rtwdev); 3069 3070 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3071 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3072 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3073 int (*napi_poll)(struct napi_struct *napi, int budget); 3074 3075 /* Deal with locks inside recovery_start and recovery_complete callbacks 3076 * by hci instance, and handle things which need to consider under SER. 3077 * e.g. turn on/off interrupts except for the one for halt notification. 3078 */ 3079 void (*recovery_start)(struct rtw89_dev *rtwdev); 3080 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3081 3082 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3083 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3084 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3085 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 3086 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3087 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3088 void (*disable_intr)(struct rtw89_dev *rtwdev); 3089 void (*enable_intr)(struct rtw89_dev *rtwdev); 3090 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3091 }; 3092 3093 struct rtw89_hci_info { 3094 const struct rtw89_hci_ops *ops; 3095 enum rtw89_hci_type type; 3096 u32 rpwm_addr; 3097 u32 cpwm_addr; 3098 bool paused; 3099 }; 3100 3101 struct rtw89_chip_ops { 3102 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3103 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3104 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3105 void (*bb_reset)(struct rtw89_dev *rtwdev, 3106 enum rtw89_phy_idx phy_idx); 3107 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3108 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3109 u32 addr, u32 mask); 3110 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3111 u32 addr, u32 mask, u32 data); 3112 void (*set_channel)(struct rtw89_dev *rtwdev, 3113 const struct rtw89_chan *chan, 3114 enum rtw89_mac_idx mac_idx, 3115 enum rtw89_phy_idx phy_idx); 3116 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3117 struct rtw89_channel_help_params *p, 3118 const struct rtw89_chan *chan, 3119 enum rtw89_mac_idx mac_idx, 3120 enum rtw89_phy_idx phy_idx); 3121 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 3122 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3123 void (*fem_setup)(struct rtw89_dev *rtwdev); 3124 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3125 void (*rfk_init)(struct rtw89_dev *rtwdev); 3126 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3127 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3128 enum rtw89_phy_idx phy_idx); 3129 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3130 void (*rfk_track)(struct rtw89_dev *rtwdev); 3131 void (*power_trim)(struct rtw89_dev *rtwdev); 3132 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3133 const struct rtw89_chan *chan, 3134 enum rtw89_phy_idx phy_idx); 3135 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3136 enum rtw89_phy_idx phy_idx); 3137 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3138 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3139 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3140 enum rtw89_phy_idx phy_idx); 3141 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3142 struct rtw89_rx_phy_ppdu *phy_ppdu, 3143 struct ieee80211_rx_status *status); 3144 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3145 enum rtw89_phy_idx phy_idx); 3146 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3147 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3148 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3149 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3150 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3151 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3152 struct rtw89_rx_desc_info *desc_info, 3153 u8 *data, u32 data_offset); 3154 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3155 struct rtw89_tx_desc_info *desc_info, 3156 void *txdesc); 3157 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3158 struct rtw89_tx_desc_info *desc_info, 3159 void *txdesc); 3160 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3161 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3162 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3163 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3164 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3165 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3166 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3167 struct rtw89_vif *rtwvif, 3168 struct rtw89_sta *rtwsta); 3169 3170 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3171 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3172 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3173 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3174 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3175 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3176 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3177 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3178 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3179 }; 3180 3181 enum rtw89_dma_ch { 3182 RTW89_DMA_ACH0 = 0, 3183 RTW89_DMA_ACH1 = 1, 3184 RTW89_DMA_ACH2 = 2, 3185 RTW89_DMA_ACH3 = 3, 3186 RTW89_DMA_ACH4 = 4, 3187 RTW89_DMA_ACH5 = 5, 3188 RTW89_DMA_ACH6 = 6, 3189 RTW89_DMA_ACH7 = 7, 3190 RTW89_DMA_B0MG = 8, 3191 RTW89_DMA_B0HI = 9, 3192 RTW89_DMA_B1MG = 10, 3193 RTW89_DMA_B1HI = 11, 3194 RTW89_DMA_H2C = 12, 3195 RTW89_DMA_CH_NUM = 13 3196 }; 3197 3198 enum rtw89_qta_mode { 3199 RTW89_QTA_SCC, 3200 RTW89_QTA_DLFW, 3201 RTW89_QTA_WOW, 3202 3203 /* keep last */ 3204 RTW89_QTA_INVALID, 3205 }; 3206 3207 struct rtw89_hfc_ch_cfg { 3208 u16 min; 3209 u16 max; 3210 #define grp_0 0 3211 #define grp_1 1 3212 #define grp_num 2 3213 u8 grp; 3214 }; 3215 3216 struct rtw89_hfc_ch_info { 3217 u16 aval; 3218 u16 used; 3219 }; 3220 3221 struct rtw89_hfc_pub_cfg { 3222 u16 grp0; 3223 u16 grp1; 3224 u16 pub_max; 3225 u16 wp_thrd; 3226 }; 3227 3228 struct rtw89_hfc_pub_info { 3229 u16 g0_used; 3230 u16 g1_used; 3231 u16 g0_aval; 3232 u16 g1_aval; 3233 u16 pub_aval; 3234 u16 wp_aval; 3235 }; 3236 3237 struct rtw89_hfc_prec_cfg { 3238 u16 ch011_prec; 3239 u16 h2c_prec; 3240 u16 wp_ch07_prec; 3241 u16 wp_ch811_prec; 3242 u8 ch011_full_cond; 3243 u8 h2c_full_cond; 3244 u8 wp_ch07_full_cond; 3245 u8 wp_ch811_full_cond; 3246 }; 3247 3248 struct rtw89_hfc_param { 3249 bool en; 3250 bool h2c_en; 3251 u8 mode; 3252 const struct rtw89_hfc_ch_cfg *ch_cfg; 3253 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3254 struct rtw89_hfc_pub_cfg pub_cfg; 3255 struct rtw89_hfc_pub_info pub_info; 3256 struct rtw89_hfc_prec_cfg prec_cfg; 3257 }; 3258 3259 struct rtw89_hfc_param_ini { 3260 const struct rtw89_hfc_ch_cfg *ch_cfg; 3261 const struct rtw89_hfc_pub_cfg *pub_cfg; 3262 const struct rtw89_hfc_prec_cfg *prec_cfg; 3263 u8 mode; 3264 }; 3265 3266 struct rtw89_dle_size { 3267 u16 pge_size; 3268 u16 lnk_pge_num; 3269 u16 unlnk_pge_num; 3270 }; 3271 3272 struct rtw89_wde_quota { 3273 u16 hif; 3274 u16 wcpu; 3275 u16 pkt_in; 3276 u16 cpu_io; 3277 }; 3278 3279 struct rtw89_ple_quota { 3280 u16 cma0_tx; 3281 u16 cma1_tx; 3282 u16 c2h; 3283 u16 h2c; 3284 u16 wcpu; 3285 u16 mpdu_proc; 3286 u16 cma0_dma; 3287 u16 cma1_dma; 3288 u16 bb_rpt; 3289 u16 wd_rel; 3290 u16 cpu_io; 3291 u16 tx_rpt; 3292 }; 3293 3294 struct rtw89_dle_mem { 3295 enum rtw89_qta_mode mode; 3296 const struct rtw89_dle_size *wde_size; 3297 const struct rtw89_dle_size *ple_size; 3298 const struct rtw89_wde_quota *wde_min_qt; 3299 const struct rtw89_wde_quota *wde_max_qt; 3300 const struct rtw89_ple_quota *ple_min_qt; 3301 const struct rtw89_ple_quota *ple_max_qt; 3302 }; 3303 3304 struct rtw89_reg_def { 3305 u32 addr; 3306 u32 mask; 3307 }; 3308 3309 struct rtw89_reg2_def { 3310 u32 addr; 3311 u32 data; 3312 }; 3313 3314 struct rtw89_reg3_def { 3315 u32 addr; 3316 u32 mask; 3317 u32 data; 3318 }; 3319 3320 struct rtw89_reg5_def { 3321 u8 flag; /* recognized by parsers */ 3322 u8 path; 3323 u32 addr; 3324 u32 mask; 3325 u32 data; 3326 }; 3327 3328 struct rtw89_phy_table { 3329 const struct rtw89_reg2_def *regs; 3330 u32 n_regs; 3331 enum rtw89_rf_path rf_path; 3332 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3333 enum rtw89_rf_path rf_path, void *data); 3334 }; 3335 3336 struct rtw89_txpwr_table { 3337 const void *data; 3338 u32 size; 3339 void (*load)(struct rtw89_dev *rtwdev, 3340 const struct rtw89_txpwr_table *tbl); 3341 }; 3342 3343 struct rtw89_txpwr_rule_2ghz { 3344 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3345 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3346 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3347 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3348 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3349 }; 3350 3351 struct rtw89_txpwr_rule_5ghz { 3352 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3353 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3354 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3355 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3356 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3357 }; 3358 3359 struct rtw89_txpwr_rule_6ghz { 3360 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3361 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3362 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3363 [RTW89_6G_CH_NUM]; 3364 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3365 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3366 [RTW89_6G_CH_NUM]; 3367 }; 3368 3369 struct rtw89_tx_shape { 3370 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3371 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3372 }; 3373 3374 struct rtw89_rfe_parms { 3375 const struct rtw89_txpwr_table *byr_tbl; 3376 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3377 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3378 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3379 struct rtw89_tx_shape tx_shape; 3380 }; 3381 3382 struct rtw89_rfe_parms_conf { 3383 const struct rtw89_rfe_parms *rfe_parms; 3384 u8 rfe_type; 3385 }; 3386 3387 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3388 3389 struct rtw89_txpwr_conf { 3390 u8 rfe_type; 3391 u8 ent_sz; 3392 u32 num_ents; 3393 const void *data; 3394 }; 3395 3396 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3397 3398 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3399 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3400 memcpy(&(entry), cursor, \ 3401 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3402 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3403 (cursor) += (conf)->ent_sz, \ 3404 memcpy(&(entry), cursor, \ 3405 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3406 3407 struct rtw89_txpwr_byrate_data { 3408 struct rtw89_txpwr_conf conf; 3409 struct rtw89_txpwr_table tbl; 3410 }; 3411 3412 struct rtw89_txpwr_lmt_2ghz_data { 3413 struct rtw89_txpwr_conf conf; 3414 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3415 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3416 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3417 }; 3418 3419 struct rtw89_txpwr_lmt_5ghz_data { 3420 struct rtw89_txpwr_conf conf; 3421 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3422 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3423 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3424 }; 3425 3426 struct rtw89_txpwr_lmt_6ghz_data { 3427 struct rtw89_txpwr_conf conf; 3428 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3429 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3430 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3431 [RTW89_6G_CH_NUM]; 3432 }; 3433 3434 struct rtw89_txpwr_lmt_ru_2ghz_data { 3435 struct rtw89_txpwr_conf conf; 3436 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3437 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3438 }; 3439 3440 struct rtw89_txpwr_lmt_ru_5ghz_data { 3441 struct rtw89_txpwr_conf conf; 3442 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3443 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3444 }; 3445 3446 struct rtw89_txpwr_lmt_ru_6ghz_data { 3447 struct rtw89_txpwr_conf conf; 3448 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3449 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3450 [RTW89_6G_CH_NUM]; 3451 }; 3452 3453 struct rtw89_tx_shape_lmt_data { 3454 struct rtw89_txpwr_conf conf; 3455 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3456 }; 3457 3458 struct rtw89_tx_shape_lmt_ru_data { 3459 struct rtw89_txpwr_conf conf; 3460 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3461 }; 3462 3463 struct rtw89_rfe_data { 3464 struct rtw89_txpwr_byrate_data byrate; 3465 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3466 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3467 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3468 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3469 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3470 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3471 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3472 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3473 struct rtw89_rfe_parms rfe_parms; 3474 }; 3475 3476 struct rtw89_page_regs { 3477 u32 hci_fc_ctrl; 3478 u32 ch_page_ctrl; 3479 u32 ach_page_ctrl; 3480 u32 ach_page_info; 3481 u32 pub_page_info3; 3482 u32 pub_page_ctrl1; 3483 u32 pub_page_ctrl2; 3484 u32 pub_page_info1; 3485 u32 pub_page_info2; 3486 u32 wp_page_ctrl1; 3487 u32 wp_page_ctrl2; 3488 u32 wp_page_info1; 3489 }; 3490 3491 struct rtw89_imr_info { 3492 u32 wdrls_imr_set; 3493 u32 wsec_imr_reg; 3494 u32 wsec_imr_set; 3495 u32 mpdu_tx_imr_set; 3496 u32 mpdu_rx_imr_set; 3497 u32 sta_sch_imr_set; 3498 u32 txpktctl_imr_b0_reg; 3499 u32 txpktctl_imr_b0_clr; 3500 u32 txpktctl_imr_b0_set; 3501 u32 txpktctl_imr_b1_reg; 3502 u32 txpktctl_imr_b1_clr; 3503 u32 txpktctl_imr_b1_set; 3504 u32 wde_imr_clr; 3505 u32 wde_imr_set; 3506 u32 ple_imr_clr; 3507 u32 ple_imr_set; 3508 u32 host_disp_imr_clr; 3509 u32 host_disp_imr_set; 3510 u32 cpu_disp_imr_clr; 3511 u32 cpu_disp_imr_set; 3512 u32 other_disp_imr_clr; 3513 u32 other_disp_imr_set; 3514 u32 bbrpt_com_err_imr_reg; 3515 u32 bbrpt_chinfo_err_imr_reg; 3516 u32 bbrpt_err_imr_set; 3517 u32 bbrpt_dfs_err_imr_reg; 3518 u32 ptcl_imr_clr; 3519 u32 ptcl_imr_set; 3520 u32 cdma_imr_0_reg; 3521 u32 cdma_imr_0_clr; 3522 u32 cdma_imr_0_set; 3523 u32 cdma_imr_1_reg; 3524 u32 cdma_imr_1_clr; 3525 u32 cdma_imr_1_set; 3526 u32 phy_intf_imr_reg; 3527 u32 phy_intf_imr_clr; 3528 u32 phy_intf_imr_set; 3529 u32 rmac_imr_reg; 3530 u32 rmac_imr_clr; 3531 u32 rmac_imr_set; 3532 u32 tmac_imr_reg; 3533 u32 tmac_imr_clr; 3534 u32 tmac_imr_set; 3535 }; 3536 3537 struct rtw89_xtal_info { 3538 u32 xcap_reg; 3539 u32 sc_xo_mask; 3540 u32 sc_xi_mask; 3541 }; 3542 3543 struct rtw89_rrsr_cfgs { 3544 struct rtw89_reg3_def ref_rate; 3545 struct rtw89_reg3_def rsc; 3546 }; 3547 3548 struct rtw89_dig_regs { 3549 u32 seg0_pd_reg; 3550 u32 pd_lower_bound_mask; 3551 u32 pd_spatial_reuse_en; 3552 u32 bmode_pd_reg; 3553 u32 bmode_cca_rssi_limit_en; 3554 u32 bmode_pd_lower_bound_reg; 3555 u32 bmode_rssi_nocca_low_th_mask; 3556 struct rtw89_reg_def p0_lna_init; 3557 struct rtw89_reg_def p1_lna_init; 3558 struct rtw89_reg_def p0_tia_init; 3559 struct rtw89_reg_def p1_tia_init; 3560 struct rtw89_reg_def p0_rxb_init; 3561 struct rtw89_reg_def p1_rxb_init; 3562 struct rtw89_reg_def p0_p20_pagcugc_en; 3563 struct rtw89_reg_def p0_s20_pagcugc_en; 3564 struct rtw89_reg_def p1_p20_pagcugc_en; 3565 struct rtw89_reg_def p1_s20_pagcugc_en; 3566 }; 3567 3568 struct rtw89_phy_ul_tb_info { 3569 bool dyn_tb_tri_en; 3570 u8 def_if_bandedge; 3571 }; 3572 3573 struct rtw89_antdiv_stats { 3574 struct ewma_rssi cck_rssi_avg; 3575 struct ewma_rssi ofdm_rssi_avg; 3576 struct ewma_rssi non_legacy_rssi_avg; 3577 u16 pkt_cnt_cck; 3578 u16 pkt_cnt_ofdm; 3579 u16 pkt_cnt_non_legacy; 3580 u32 evm; 3581 }; 3582 3583 struct rtw89_antdiv_info { 3584 struct rtw89_antdiv_stats target_stats; 3585 struct rtw89_antdiv_stats main_stats; 3586 struct rtw89_antdiv_stats aux_stats; 3587 u8 training_count; 3588 u8 rssi_pre; 3589 bool get_stats; 3590 }; 3591 3592 enum rtw89_chanctx_state { 3593 RTW89_CHANCTX_STATE_MCC_START, 3594 RTW89_CHANCTX_STATE_MCC_STOP, 3595 }; 3596 3597 enum rtw89_chanctx_callbacks { 3598 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 3599 RTW89_CHANCTX_CALLBACK_RFK, 3600 3601 NUM_OF_RTW89_CHANCTX_CALLBACKS, 3602 }; 3603 3604 struct rtw89_chanctx_listener { 3605 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 3606 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 3607 }; 3608 3609 struct rtw89_chip_info { 3610 enum rtw89_core_chip_id chip_id; 3611 enum rtw89_chip_gen chip_gen; 3612 const struct rtw89_chip_ops *ops; 3613 const struct rtw89_mac_gen_def *mac_def; 3614 const struct rtw89_phy_gen_def *phy_def; 3615 const char *fw_basename; 3616 u8 fw_format_max; 3617 bool try_ce_fw; 3618 u8 bbmcu_nr; 3619 u32 needed_fw_elms; 3620 u32 fifo_size; 3621 bool small_fifo_size; 3622 u32 dle_scc_rsvd_size; 3623 u16 max_amsdu_limit; 3624 bool dis_2g_40m_ul_ofdma; 3625 u32 rsvd_ple_ofst; 3626 const struct rtw89_hfc_param_ini *hfc_param_ini; 3627 const struct rtw89_dle_mem *dle_mem; 3628 u8 wde_qempty_acq_num; 3629 u8 wde_qempty_mgq_sel; 3630 u32 rf_base_addr[2]; 3631 u8 support_chanctx_num; 3632 u8 support_bands; 3633 bool support_bw160; 3634 bool support_unii4; 3635 bool ul_tb_waveform_ctrl; 3636 bool ul_tb_pwr_diff; 3637 bool hw_sec_hdr; 3638 u8 rf_path_num; 3639 u8 tx_nss; 3640 u8 rx_nss; 3641 u8 acam_num; 3642 u8 bcam_num; 3643 u8 scam_num; 3644 u8 bacam_num; 3645 u8 bacam_dynamic_num; 3646 enum rtw89_bacam_ver bacam_ver; 3647 3648 u8 sec_ctrl_efuse_size; 3649 u32 physical_efuse_size; 3650 u32 logical_efuse_size; 3651 u32 limit_efuse_size; 3652 u32 dav_phy_efuse_size; 3653 u32 dav_log_efuse_size; 3654 u32 phycap_addr; 3655 u32 phycap_size; 3656 3657 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3658 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3659 const struct rtw89_phy_table *bb_table; 3660 const struct rtw89_phy_table *bb_gain_table; 3661 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3662 const struct rtw89_phy_table *nctl_table; 3663 const struct rtw89_rfk_tbl *nctl_post_table; 3664 const struct rtw89_phy_dig_gain_table *dig_table; 3665 const struct rtw89_dig_regs *dig_regs; 3666 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3667 3668 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3669 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3670 const struct rtw89_rfe_parms *dflt_parms; 3671 const struct rtw89_chanctx_listener *chanctx_listener; 3672 3673 u8 txpwr_factor_rf; 3674 u8 txpwr_factor_mac; 3675 3676 u32 para_ver; 3677 u32 wlcx_desired; 3678 u8 btcx_desired; 3679 u8 scbd; 3680 u8 mailbox; 3681 3682 u8 afh_guard_ch; 3683 const u8 *wl_rssi_thres; 3684 const u8 *bt_rssi_thres; 3685 u8 rssi_tol; 3686 3687 u8 mon_reg_num; 3688 const struct rtw89_btc_fbtc_mreg *mon_reg; 3689 u8 rf_para_ulink_num; 3690 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3691 u8 rf_para_dlink_num; 3692 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3693 u8 ps_mode_supported; 3694 u8 low_power_hci_modes; 3695 3696 u32 h2c_cctl_func_id; 3697 u32 hci_func_en_addr; 3698 u32 h2c_desc_size; 3699 u32 txwd_body_size; 3700 u32 txwd_info_size; 3701 u32 h2c_ctrl_reg; 3702 const u32 *h2c_regs; 3703 struct rtw89_reg_def h2c_counter_reg; 3704 u32 c2h_ctrl_reg; 3705 const u32 *c2h_regs; 3706 struct rtw89_reg_def c2h_counter_reg; 3707 const struct rtw89_page_regs *page_regs; 3708 bool cfo_src_fd; 3709 bool cfo_hw_comp; 3710 const struct rtw89_reg_def *dcfo_comp; 3711 u8 dcfo_comp_sft; 3712 const struct rtw89_imr_info *imr_info; 3713 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3714 struct rtw89_reg_def bss_clr_vld; 3715 u32 bss_clr_map_reg; 3716 u32 dma_ch_mask; 3717 u32 edcca_lvl_reg; 3718 const struct wiphy_wowlan_support *wowlan_stub; 3719 const struct rtw89_xtal_info *xtal_info; 3720 }; 3721 3722 union rtw89_bus_info { 3723 const struct rtw89_pci_info *pci; 3724 }; 3725 3726 struct rtw89_driver_info { 3727 const struct rtw89_chip_info *chip; 3728 union rtw89_bus_info bus; 3729 }; 3730 3731 enum rtw89_hcifc_mode { 3732 RTW89_HCIFC_POH = 0, 3733 RTW89_HCIFC_STF = 1, 3734 RTW89_HCIFC_SDIO = 2, 3735 3736 /* keep last */ 3737 RTW89_HCIFC_MODE_INVALID, 3738 }; 3739 3740 struct rtw89_dle_info { 3741 enum rtw89_qta_mode qta_mode; 3742 u16 ple_pg_size; 3743 u16 c0_rx_qta; 3744 u16 c1_rx_qta; 3745 }; 3746 3747 enum rtw89_host_rpr_mode { 3748 RTW89_RPR_MODE_POH = 0, 3749 RTW89_RPR_MODE_STF 3750 }; 3751 3752 #define RTW89_COMPLETION_BUF_SIZE 24 3753 #define RTW89_WAIT_COND_IDLE UINT_MAX 3754 3755 struct rtw89_completion_data { 3756 bool err; 3757 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3758 }; 3759 3760 struct rtw89_wait_info { 3761 atomic_t cond; 3762 struct completion completion; 3763 struct rtw89_completion_data data; 3764 }; 3765 3766 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3767 3768 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3769 { 3770 init_completion(&wait->completion); 3771 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3772 } 3773 3774 struct rtw89_mac_info { 3775 struct rtw89_dle_info dle_info; 3776 struct rtw89_hfc_param hfc_param; 3777 enum rtw89_qta_mode qta_mode; 3778 u8 rpwm_seq_num; 3779 u8 cpwm_seq_num; 3780 3781 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 3782 struct rtw89_wait_info fw_ofld_wait; 3783 }; 3784 3785 enum rtw89_fwdl_check_type { 3786 RTW89_FWDL_CHECK_FREERTOS_DONE, 3787 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 3788 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 3789 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 3790 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 3791 }; 3792 3793 enum rtw89_fw_type { 3794 RTW89_FW_NORMAL = 1, 3795 RTW89_FW_WOWLAN = 3, 3796 RTW89_FW_NORMAL_CE = 5, 3797 RTW89_FW_BBMCU0 = 64, 3798 RTW89_FW_BBMCU1 = 65, 3799 RTW89_FW_LOGFMT = 255, 3800 }; 3801 3802 enum rtw89_fw_feature { 3803 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3804 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3805 RTW89_FW_FEATURE_TX_WAKE, 3806 RTW89_FW_FEATURE_CRASH_TRIGGER, 3807 RTW89_FW_FEATURE_NO_PACKET_DROP, 3808 RTW89_FW_FEATURE_NO_DEEP_PS, 3809 RTW89_FW_FEATURE_NO_LPS_PG, 3810 RTW89_FW_FEATURE_BEACON_FILTER, 3811 }; 3812 3813 struct rtw89_fw_suit { 3814 enum rtw89_fw_type type; 3815 const u8 *data; 3816 u32 size; 3817 u8 major_ver; 3818 u8 minor_ver; 3819 u8 sub_ver; 3820 u8 sub_idex; 3821 u16 build_year; 3822 u16 build_mon; 3823 u16 build_date; 3824 u16 build_hour; 3825 u16 build_min; 3826 u8 cmd_ver; 3827 u8 hdr_ver; 3828 u32 commitid; 3829 }; 3830 3831 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3832 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3833 #define RTW89_FW_SUIT_VER_CODE(s) \ 3834 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3835 3836 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3837 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3838 (mfw_hdr)->ver.minor, \ 3839 (mfw_hdr)->ver.sub, \ 3840 (mfw_hdr)->ver.idx) 3841 3842 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3843 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 3844 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 3845 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 3846 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 3847 3848 struct rtw89_fw_req_info { 3849 const struct firmware *firmware; 3850 struct completion completion; 3851 }; 3852 3853 struct rtw89_fw_log { 3854 struct rtw89_fw_suit suit; 3855 bool enable; 3856 u32 last_fmt_id; 3857 u32 fmt_count; 3858 const __le32 *fmt_ids; 3859 const char *(*fmts)[]; 3860 }; 3861 3862 struct rtw89_fw_elm_info { 3863 struct rtw89_phy_table *bb_tbl; 3864 struct rtw89_phy_table *bb_gain; 3865 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 3866 struct rtw89_phy_table *rf_nctl; 3867 }; 3868 3869 struct rtw89_fw_info { 3870 struct rtw89_fw_req_info req; 3871 int fw_format; 3872 u8 h2c_seq; 3873 u8 rec_seq; 3874 u8 h2c_counter; 3875 u8 c2h_counter; 3876 struct rtw89_fw_suit normal; 3877 struct rtw89_fw_suit wowlan; 3878 struct rtw89_fw_suit bbmcu0; 3879 struct rtw89_fw_suit bbmcu1; 3880 struct rtw89_fw_log log; 3881 u32 feature_map; 3882 struct rtw89_fw_elm_info elm_info; 3883 }; 3884 3885 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3886 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3887 3888 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3889 ((_fw)->feature_map |= BIT(_fw_feature)) 3890 3891 struct rtw89_cam_info { 3892 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3893 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3894 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3895 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3896 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3897 }; 3898 3899 enum rtw89_sar_sources { 3900 RTW89_SAR_SOURCE_NONE, 3901 RTW89_SAR_SOURCE_COMMON, 3902 3903 RTW89_SAR_SOURCE_NR, 3904 }; 3905 3906 enum rtw89_sar_subband { 3907 RTW89_SAR_2GHZ_SUBBAND, 3908 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3909 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 3910 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 3911 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 3912 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 3913 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 3914 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 3915 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 3916 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 3917 3918 RTW89_SAR_SUBBAND_NR, 3919 }; 3920 3921 struct rtw89_sar_cfg_common { 3922 bool set[RTW89_SAR_SUBBAND_NR]; 3923 s32 cfg[RTW89_SAR_SUBBAND_NR]; 3924 }; 3925 3926 struct rtw89_sar_info { 3927 /* used to decide how to acces SAR cfg union */ 3928 enum rtw89_sar_sources src; 3929 3930 /* reserved for different knids of SAR cfg struct. 3931 * supposed that a single cfg struct cannot handle various SAR sources. 3932 */ 3933 union { 3934 struct rtw89_sar_cfg_common cfg_common; 3935 }; 3936 }; 3937 3938 enum rtw89_tas_state { 3939 RTW89_TAS_STATE_DPR_OFF, 3940 RTW89_TAS_STATE_DPR_ON, 3941 RTW89_TAS_STATE_DPR_FORBID, 3942 }; 3943 3944 #define RTW89_TAS_MAX_WINDOW 50 3945 struct rtw89_tas_info { 3946 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 3947 s32 total_txpwr; 3948 u8 cur_idx; 3949 s8 dpr_gap; 3950 s8 delta; 3951 enum rtw89_tas_state state; 3952 bool enable; 3953 }; 3954 3955 struct rtw89_chanctx_cfg { 3956 enum rtw89_sub_entity_idx idx; 3957 }; 3958 3959 enum rtw89_chanctx_changes { 3960 RTW89_CHANCTX_REMOTE_STA_CHANGE, 3961 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 3962 RTW89_CHANCTX_P2P_PS_CHANGE, 3963 RTW89_CHANCTX_BT_SLOT_CHANGE, 3964 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 3965 3966 NUM_OF_RTW89_CHANCTX_CHANGES, 3967 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 3968 }; 3969 3970 enum rtw89_entity_mode { 3971 RTW89_ENTITY_MODE_SCC, 3972 RTW89_ENTITY_MODE_MCC_PREPARE, 3973 RTW89_ENTITY_MODE_MCC, 3974 3975 NUM_OF_RTW89_ENTITY_MODE, 3976 RTW89_ENTITY_MODE_INVALID = NUM_OF_RTW89_ENTITY_MODE, 3977 }; 3978 3979 struct rtw89_sub_entity { 3980 struct cfg80211_chan_def chandef; 3981 struct rtw89_chan chan; 3982 struct rtw89_chan_rcd rcd; 3983 struct rtw89_chanctx_cfg *cfg; 3984 }; 3985 3986 struct rtw89_hal { 3987 u32 rx_fltr; 3988 u8 cv; 3989 u8 acv; 3990 u32 antenna_tx; 3991 u32 antenna_rx; 3992 u8 tx_nss; 3993 u8 rx_nss; 3994 bool tx_path_diversity; 3995 bool ant_diversity; 3996 bool ant_diversity_fixed; 3997 bool support_cckpd; 3998 bool support_igi; 3999 atomic_t roc_entity_idx; 4000 4001 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4002 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4003 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4004 struct cfg80211_chan_def roc_chandef; 4005 4006 bool entity_active; 4007 bool entity_pause; 4008 enum rtw89_entity_mode entity_mode; 4009 4010 u32 edcca_bak; 4011 }; 4012 4013 #define RTW89_MAX_MAC_ID_NUM 128 4014 #define RTW89_MAX_PKT_OFLD_NUM 255 4015 4016 enum rtw89_flags { 4017 RTW89_FLAG_POWERON, 4018 RTW89_FLAG_FW_RDY, 4019 RTW89_FLAG_RUNNING, 4020 RTW89_FLAG_BFEE_MON, 4021 RTW89_FLAG_BFEE_EN, 4022 RTW89_FLAG_BFEE_TIMER_KEEP, 4023 RTW89_FLAG_NAPI_RUNNING, 4024 RTW89_FLAG_LEISURE_PS, 4025 RTW89_FLAG_LOW_POWER_MODE, 4026 RTW89_FLAG_INACTIVE_PS, 4027 RTW89_FLAG_CRASH_SIMULATING, 4028 RTW89_FLAG_SER_HANDLING, 4029 RTW89_FLAG_WOWLAN, 4030 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4031 RTW89_FLAG_CHANGING_INTERFACE, 4032 4033 NUM_OF_RTW89_FLAGS, 4034 }; 4035 4036 enum rtw89_pkt_drop_sel { 4037 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4038 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4039 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4040 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4041 RTW89_PKT_DROP_SEL_MACID_ALL, 4042 RTW89_PKT_DROP_SEL_MG0_ONCE, 4043 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4044 RTW89_PKT_DROP_SEL_HIQ_PORT, 4045 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4046 RTW89_PKT_DROP_SEL_BAND, 4047 RTW89_PKT_DROP_SEL_BAND_ONCE, 4048 RTW89_PKT_DROP_SEL_REL_MACID, 4049 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4050 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4051 }; 4052 4053 struct rtw89_pkt_drop_params { 4054 enum rtw89_pkt_drop_sel sel; 4055 enum rtw89_mac_idx mac_band; 4056 u8 macid; 4057 u8 port; 4058 u8 mbssid; 4059 bool tf_trs; 4060 u32 macid_band_sel[4]; 4061 }; 4062 4063 struct rtw89_pkt_stat { 4064 u16 beacon_nr; 4065 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4066 }; 4067 4068 DECLARE_EWMA(thermal, 4, 4); 4069 4070 struct rtw89_phy_stat { 4071 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4072 struct rtw89_pkt_stat cur_pkt_stat; 4073 struct rtw89_pkt_stat last_pkt_stat; 4074 }; 4075 4076 #define RTW89_DACK_PATH_NR 2 4077 #define RTW89_DACK_IDX_NR 2 4078 #define RTW89_DACK_MSBK_NR 16 4079 struct rtw89_dack_info { 4080 bool dack_done; 4081 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4082 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4083 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4084 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4085 u32 dack_cnt; 4086 bool addck_timeout[RTW89_DACK_PATH_NR]; 4087 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4088 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4089 }; 4090 4091 #define RTW89_IQK_CHS_NR 2 4092 #define RTW89_IQK_PATH_NR 4 4093 4094 struct rtw89_rfk_mcc_info { 4095 u8 ch[RTW89_IQK_CHS_NR]; 4096 u8 band[RTW89_IQK_CHS_NR]; 4097 u8 table_idx; 4098 }; 4099 4100 struct rtw89_lck_info { 4101 u8 thermal[RF_PATH_MAX]; 4102 }; 4103 4104 struct rtw89_rx_dck_info { 4105 u8 thermal[RF_PATH_MAX]; 4106 }; 4107 4108 struct rtw89_iqk_info { 4109 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4110 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4111 bool lok_fail[RTW89_IQK_PATH_NR]; 4112 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4113 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4114 u32 iqk_fail_cnt; 4115 bool is_iqk_init; 4116 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4117 u8 iqk_band[RTW89_IQK_PATH_NR]; 4118 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4119 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4120 u8 iqk_times; 4121 u8 version; 4122 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4123 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4124 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4125 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4126 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4127 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4128 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4129 bool is_nbiqk; 4130 bool iqk_fft_en; 4131 bool iqk_xym_en; 4132 bool iqk_sram_en; 4133 bool iqk_cfir_en; 4134 u32 syn1to2; 4135 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4136 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4137 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4138 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4139 }; 4140 4141 #define RTW89_DPK_RF_PATH 2 4142 #define RTW89_DPK_AVG_THERMAL_NUM 8 4143 #define RTW89_DPK_BKUP_NUM 2 4144 struct rtw89_dpk_bkup_para { 4145 enum rtw89_band band; 4146 enum rtw89_bandwidth bw; 4147 u8 ch; 4148 bool path_ok; 4149 u8 mdpd_en; 4150 u8 txagc_dpk; 4151 u8 ther_dpk; 4152 u8 gs; 4153 u16 pwsf; 4154 }; 4155 4156 struct rtw89_dpk_info { 4157 bool is_dpk_enable; 4158 bool is_dpk_reload_en; 4159 u8 dpk_gs[RTW89_PHY_MAX]; 4160 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4161 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4162 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4163 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4164 u8 cur_idx[RTW89_DPK_RF_PATH]; 4165 u8 cur_k_set; 4166 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4167 }; 4168 4169 struct rtw89_fem_info { 4170 bool elna_2g; 4171 bool elna_5g; 4172 bool epa_2g; 4173 bool epa_5g; 4174 bool epa_6g; 4175 }; 4176 4177 struct rtw89_phy_ch_info { 4178 u8 rssi_min; 4179 u16 rssi_min_macid; 4180 u8 pre_rssi_min; 4181 u8 rssi_max; 4182 u16 rssi_max_macid; 4183 u8 rxsc_160; 4184 u8 rxsc_80; 4185 u8 rxsc_40; 4186 u8 rxsc_20; 4187 u8 rxsc_l; 4188 u8 is_noisy; 4189 }; 4190 4191 struct rtw89_agc_gaincode_set { 4192 u8 lna_idx; 4193 u8 tia_idx; 4194 u8 rxb_idx; 4195 }; 4196 4197 #define IGI_RSSI_TH_NUM 5 4198 #define FA_TH_NUM 4 4199 #define LNA_GAIN_NUM 7 4200 #define TIA_GAIN_NUM 2 4201 struct rtw89_dig_info { 4202 struct rtw89_agc_gaincode_set cur_gaincode; 4203 bool force_gaincode_idx_en; 4204 struct rtw89_agc_gaincode_set force_gaincode; 4205 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4206 u16 fa_th[FA_TH_NUM]; 4207 u8 igi_rssi; 4208 u8 igi_fa_rssi; 4209 u8 fa_rssi_ofst; 4210 u8 dyn_igi_max; 4211 u8 dyn_igi_min; 4212 bool dyn_pd_th_en; 4213 u8 dyn_pd_th_max; 4214 u8 pd_low_th_ofst; 4215 u8 ib_pbk; 4216 s8 ib_pkpwr; 4217 s8 lna_gain_a[LNA_GAIN_NUM]; 4218 s8 lna_gain_g[LNA_GAIN_NUM]; 4219 s8 *lna_gain; 4220 s8 tia_gain_a[TIA_GAIN_NUM]; 4221 s8 tia_gain_g[TIA_GAIN_NUM]; 4222 s8 *tia_gain; 4223 bool is_linked_pre; 4224 bool bypass_dig; 4225 }; 4226 4227 enum rtw89_multi_cfo_mode { 4228 RTW89_PKT_BASED_AVG_MODE = 0, 4229 RTW89_ENTRY_BASED_AVG_MODE = 1, 4230 RTW89_TP_BASED_AVG_MODE = 2, 4231 }; 4232 4233 enum rtw89_phy_cfo_status { 4234 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4235 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4236 RTW89_PHY_DCFO_STATE_HOLD = 2, 4237 RTW89_PHY_DCFO_STATE_MAX 4238 }; 4239 4240 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4241 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4242 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4243 }; 4244 4245 struct rtw89_cfo_tracking_info { 4246 u16 cfo_timer_ms; 4247 bool cfo_trig_by_timer_en; 4248 enum rtw89_phy_cfo_status phy_cfo_status; 4249 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4250 u8 phy_cfo_trk_cnt; 4251 bool is_adjust; 4252 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4253 bool apply_compensation; 4254 u8 crystal_cap; 4255 u8 crystal_cap_default; 4256 u8 def_x_cap; 4257 s8 x_cap_ofst; 4258 u32 sta_cfo_tolerance; 4259 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4260 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4261 s32 cfo_avg_pre; 4262 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4263 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4264 s32 dcfo_avg; 4265 s32 dcfo_avg_pre; 4266 u32 packet_count; 4267 u32 packet_count_pre; 4268 s32 residual_cfo_acc; 4269 u8 phy_cfotrk_state; 4270 u8 phy_cfotrk_cnt; 4271 bool divergence_lock_en; 4272 u8 x_cap_lb; 4273 u8 x_cap_ub; 4274 u8 lock_cnt; 4275 }; 4276 4277 enum rtw89_tssi_alimk_band { 4278 TSSI_ALIMK_2G = 0, 4279 TSSI_ALIMK_5GL, 4280 TSSI_ALIMK_5GM, 4281 TSSI_ALIMK_5GH, 4282 TSSI_ALIMK_MAX 4283 }; 4284 4285 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4286 #define TSSI_TRIM_CH_GROUP_NUM 8 4287 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4288 4289 #define TSSI_CCK_CH_GROUP_NUM 6 4290 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4291 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4292 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4293 #define TSSI_MCS_CH_GROUP_NUM \ 4294 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4295 #define TSSI_MAX_CH_NUM 67 4296 #define TSSI_ALIMK_VALUE_NUM 8 4297 4298 struct rtw89_tssi_info { 4299 u8 thermal[RF_PATH_MAX]; 4300 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4301 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4302 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4303 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4304 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4305 s8 extra_ofst[RF_PATH_MAX]; 4306 bool tssi_tracking_check[RF_PATH_MAX]; 4307 u8 default_txagc_offset[RF_PATH_MAX]; 4308 u32 base_thermal[RF_PATH_MAX]; 4309 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4310 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4311 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4312 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4313 u32 tssi_alimk_time; 4314 }; 4315 4316 struct rtw89_power_trim_info { 4317 bool pg_thermal_trim; 4318 bool pg_pa_bias_trim; 4319 u8 thermal_trim[RF_PATH_MAX]; 4320 u8 pa_bias_trim[RF_PATH_MAX]; 4321 }; 4322 4323 struct rtw89_regd { 4324 char alpha2[3]; 4325 u8 txpwr_regd[RTW89_BAND_NUM]; 4326 }; 4327 4328 struct rtw89_regulatory_info { 4329 const struct rtw89_regd *regd; 4330 enum rtw89_reg_6ghz_power reg_6ghz_power; 4331 }; 4332 4333 enum rtw89_ifs_clm_application { 4334 RTW89_IFS_CLM_INIT = 0, 4335 RTW89_IFS_CLM_BACKGROUND = 1, 4336 RTW89_IFS_CLM_ACS = 2, 4337 RTW89_IFS_CLM_DIG = 3, 4338 RTW89_IFS_CLM_TDMA_DIG = 4, 4339 RTW89_IFS_CLM_DBG = 5, 4340 RTW89_IFS_CLM_DBG_MANUAL = 6 4341 }; 4342 4343 enum rtw89_env_racing_lv { 4344 RTW89_RAC_RELEASE = 0, 4345 RTW89_RAC_LV_1 = 1, 4346 RTW89_RAC_LV_2 = 2, 4347 RTW89_RAC_LV_3 = 3, 4348 RTW89_RAC_LV_4 = 4, 4349 RTW89_RAC_MAX_NUM = 5 4350 }; 4351 4352 struct rtw89_ccx_para_info { 4353 enum rtw89_env_racing_lv rac_lv; 4354 u16 mntr_time; 4355 u8 nhm_manual_th_ofst; 4356 u8 nhm_manual_th0; 4357 enum rtw89_ifs_clm_application ifs_clm_app; 4358 u32 ifs_clm_manual_th_times; 4359 u32 ifs_clm_manual_th0; 4360 u8 fahm_manual_th_ofst; 4361 u8 fahm_manual_th0; 4362 u8 fahm_numer_opt; 4363 u8 fahm_denom_opt; 4364 }; 4365 4366 enum rtw89_ccx_edcca_opt_sc_idx { 4367 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4368 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4369 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4370 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4371 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4372 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4373 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4374 RTW89_CCX_EDCCA_SEG1_S3 = 7 4375 }; 4376 4377 enum rtw89_ccx_edcca_opt_bw_idx { 4378 RTW89_CCX_EDCCA_BW20_0 = 0, 4379 RTW89_CCX_EDCCA_BW20_1 = 1, 4380 RTW89_CCX_EDCCA_BW20_2 = 2, 4381 RTW89_CCX_EDCCA_BW20_3 = 3, 4382 RTW89_CCX_EDCCA_BW20_4 = 4, 4383 RTW89_CCX_EDCCA_BW20_5 = 5, 4384 RTW89_CCX_EDCCA_BW20_6 = 6, 4385 RTW89_CCX_EDCCA_BW20_7 = 7 4386 }; 4387 4388 #define RTW89_NHM_TH_NUM 11 4389 #define RTW89_FAHM_TH_NUM 11 4390 #define RTW89_NHM_RPT_NUM 12 4391 #define RTW89_FAHM_RPT_NUM 12 4392 #define RTW89_IFS_CLM_NUM 4 4393 struct rtw89_env_monitor_info { 4394 u8 ccx_watchdog_result; 4395 bool ccx_ongoing; 4396 u8 ccx_rac_lv; 4397 bool ccx_manual_ctrl; 4398 u16 ifs_clm_mntr_time; 4399 enum rtw89_ifs_clm_application ifs_clm_app; 4400 u16 ccx_period; 4401 u8 ccx_unit_idx; 4402 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4403 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4404 u16 ifs_clm_tx; 4405 u16 ifs_clm_edcca_excl_cca; 4406 u16 ifs_clm_ofdmfa; 4407 u16 ifs_clm_ofdmcca_excl_fa; 4408 u16 ifs_clm_cckfa; 4409 u16 ifs_clm_cckcca_excl_fa; 4410 u16 ifs_clm_total_ifs; 4411 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4412 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4413 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4414 u8 ifs_clm_tx_ratio; 4415 u8 ifs_clm_edcca_excl_cca_ratio; 4416 u8 ifs_clm_cck_fa_ratio; 4417 u8 ifs_clm_ofdm_fa_ratio; 4418 u8 ifs_clm_cck_cca_excl_fa_ratio; 4419 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4420 u16 ifs_clm_cck_fa_permil; 4421 u16 ifs_clm_ofdm_fa_permil; 4422 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4423 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4424 }; 4425 4426 enum rtw89_ser_rcvy_step { 4427 RTW89_SER_DRV_STOP_TX, 4428 RTW89_SER_DRV_STOP_RX, 4429 RTW89_SER_DRV_STOP_RUN, 4430 RTW89_SER_HAL_STOP_DMA, 4431 RTW89_SER_SUPPRESS_LOG, 4432 RTW89_NUM_OF_SER_FLAGS 4433 }; 4434 4435 struct rtw89_ser { 4436 u8 state; 4437 u8 alarm_event; 4438 bool prehandle_l1; 4439 4440 struct work_struct ser_hdl_work; 4441 struct delayed_work ser_alarm_work; 4442 const struct state_ent *st_tbl; 4443 const struct event_ent *ev_tbl; 4444 struct list_head msg_q; 4445 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4446 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4447 }; 4448 4449 enum rtw89_mac_ax_ps_mode { 4450 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4451 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4452 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4453 RTW89_MAC_AX_PS_MODE_MAX = 3, 4454 }; 4455 4456 enum rtw89_last_rpwm_mode { 4457 RTW89_LAST_RPWM_PS = 0x0, 4458 RTW89_LAST_RPWM_ACTIVE = 0x6, 4459 }; 4460 4461 struct rtw89_lps_parm { 4462 u8 macid; 4463 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4464 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4465 }; 4466 4467 struct rtw89_ppdu_sts_info { 4468 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4469 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4470 }; 4471 4472 struct rtw89_early_h2c { 4473 struct list_head list; 4474 u8 *h2c; 4475 u16 h2c_len; 4476 }; 4477 4478 struct rtw89_hw_scan_info { 4479 struct ieee80211_vif *scanning_vif; 4480 struct list_head pkt_list[NUM_NL80211_BANDS]; 4481 struct rtw89_chan op_chan; 4482 u32 last_chan_idx; 4483 }; 4484 4485 enum rtw89_phy_bb_gain_band { 4486 RTW89_BB_GAIN_BAND_2G = 0, 4487 RTW89_BB_GAIN_BAND_5G_L = 1, 4488 RTW89_BB_GAIN_BAND_5G_M = 2, 4489 RTW89_BB_GAIN_BAND_5G_H = 3, 4490 RTW89_BB_GAIN_BAND_6G_L = 4, 4491 RTW89_BB_GAIN_BAND_6G_M = 5, 4492 RTW89_BB_GAIN_BAND_6G_H = 6, 4493 RTW89_BB_GAIN_BAND_6G_UH = 7, 4494 4495 RTW89_BB_GAIN_BAND_NR, 4496 }; 4497 4498 enum rtw89_phy_bb_rxsc_num { 4499 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4500 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4501 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4502 }; 4503 4504 struct rtw89_phy_bb_gain_info { 4505 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4506 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4507 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4508 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4509 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4510 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4511 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4512 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4513 [RTW89_BB_RXSC_NUM_40]; 4514 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4515 [RTW89_BB_RXSC_NUM_80]; 4516 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4517 [RTW89_BB_RXSC_NUM_160]; 4518 }; 4519 4520 struct rtw89_phy_efuse_gain { 4521 bool offset_valid; 4522 bool comp_valid; 4523 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4524 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4525 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4526 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4527 }; 4528 4529 #define RTW89_MAX_PATTERN_NUM 18 4530 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4531 #define RTW89_MAX_PATTERN_SIZE 128 4532 4533 struct rtw89_wow_cam_info { 4534 bool r_w; 4535 u8 idx; 4536 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4537 u16 crc; 4538 bool negative_pattern_match; 4539 bool skip_mac_hdr; 4540 bool uc; 4541 bool mc; 4542 bool bc; 4543 bool valid; 4544 }; 4545 4546 struct rtw89_wow_param { 4547 struct ieee80211_vif *wow_vif; 4548 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4549 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4550 u8 pattern_cnt; 4551 }; 4552 4553 struct rtw89_mcc_limit { 4554 bool enable; 4555 u16 max_tob; /* TU; max time offset behind */ 4556 u16 max_toa; /* TU; max time offset ahead */ 4557 u16 max_dur; /* TU */ 4558 }; 4559 4560 struct rtw89_mcc_policy { 4561 u8 c2h_rpt; 4562 u8 tx_null_early; 4563 u8 dis_tx_null; 4564 u8 in_curr_ch; 4565 u8 dis_sw_retry; 4566 u8 sw_retry_count; 4567 }; 4568 4569 struct rtw89_mcc_role { 4570 struct rtw89_vif *rtwvif; 4571 struct rtw89_mcc_policy policy; 4572 struct rtw89_mcc_limit limit; 4573 4574 /* byte-array in LE order for FW */ 4575 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 4576 4577 u16 duration; /* TU */ 4578 u16 beacon_interval; /* TU */ 4579 bool is_2ghz; 4580 bool is_go; 4581 bool is_gc; 4582 }; 4583 4584 struct rtw89_mcc_bt_role { 4585 u16 duration; /* TU */ 4586 }; 4587 4588 struct rtw89_mcc_courtesy { 4589 bool enable; 4590 u8 slot_num; 4591 u8 macid_src; 4592 u8 macid_tgt; 4593 }; 4594 4595 enum rtw89_mcc_plan { 4596 RTW89_MCC_PLAN_TAIL_BT, 4597 RTW89_MCC_PLAN_MID_BT, 4598 RTW89_MCC_PLAN_NO_BT, 4599 4600 NUM_OF_RTW89_MCC_PLAN, 4601 }; 4602 4603 struct rtw89_mcc_pattern { 4604 s16 tob_ref; /* TU; time offset behind of reference role */ 4605 s16 toa_ref; /* TU; time offset ahead of reference role */ 4606 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 4607 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 4608 4609 enum rtw89_mcc_plan plan; 4610 struct rtw89_mcc_courtesy courtesy; 4611 }; 4612 4613 struct rtw89_mcc_sync { 4614 bool enable; 4615 u16 offset; /* TU */ 4616 u8 macid_src; 4617 u8 macid_tgt; 4618 }; 4619 4620 struct rtw89_mcc_config { 4621 struct rtw89_mcc_pattern pattern; 4622 struct rtw89_mcc_sync sync; 4623 u64 start_tsf; 4624 u16 mcc_interval; /* TU */ 4625 u16 beacon_offset; /* TU */ 4626 }; 4627 4628 enum rtw89_mcc_mode { 4629 RTW89_MCC_MODE_GO_STA, 4630 RTW89_MCC_MODE_GC_STA, 4631 }; 4632 4633 struct rtw89_mcc_info { 4634 struct rtw89_wait_info wait; 4635 4636 u8 group; 4637 enum rtw89_mcc_mode mode; 4638 struct rtw89_mcc_role role_ref; /* reference role */ 4639 struct rtw89_mcc_role role_aux; /* auxiliary role */ 4640 struct rtw89_mcc_bt_role bt_role; 4641 struct rtw89_mcc_config config; 4642 }; 4643 4644 struct rtw89_dev { 4645 struct ieee80211_hw *hw; 4646 struct device *dev; 4647 const struct ieee80211_ops *ops; 4648 4649 bool dbcc_en; 4650 struct rtw89_hw_scan_info scan_info; 4651 const struct rtw89_chip_info *chip; 4652 const struct rtw89_pci_info *pci_info; 4653 const struct rtw89_rfe_parms *rfe_parms; 4654 struct rtw89_hal hal; 4655 struct rtw89_mcc_info mcc; 4656 struct rtw89_mac_info mac; 4657 struct rtw89_fw_info fw; 4658 struct rtw89_hci_info hci; 4659 struct rtw89_efuse efuse; 4660 struct rtw89_traffic_stats stats; 4661 struct rtw89_rfe_data *rfe_data; 4662 4663 /* ensures exclusive access from mac80211 callbacks */ 4664 struct mutex mutex; 4665 struct list_head rtwvifs_list; 4666 /* used to protect rf read write */ 4667 struct mutex rf_mutex; 4668 struct workqueue_struct *txq_wq; 4669 struct work_struct txq_work; 4670 struct delayed_work txq_reinvoke_work; 4671 /* used to protect ba_list and forbid_ba_list */ 4672 spinlock_t ba_lock; 4673 /* txqs to setup ba session */ 4674 struct list_head ba_list; 4675 /* txqs to forbid ba session */ 4676 struct list_head forbid_ba_list; 4677 struct work_struct ba_work; 4678 /* used to protect rpwm */ 4679 spinlock_t rpwm_lock; 4680 4681 struct rtw89_cam_info cam_info; 4682 4683 struct sk_buff_head c2h_queue; 4684 struct work_struct c2h_work; 4685 struct work_struct ips_work; 4686 struct work_struct load_firmware_work; 4687 struct work_struct cancel_6ghz_probe_work; 4688 4689 struct list_head early_h2c_list; 4690 4691 struct rtw89_ser ser; 4692 4693 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4694 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 4695 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 4696 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 4697 4698 struct rtw89_phy_stat phystat; 4699 struct rtw89_dack_info dack; 4700 struct rtw89_iqk_info iqk; 4701 struct rtw89_dpk_info dpk; 4702 struct rtw89_rfk_mcc_info rfk_mcc; 4703 struct rtw89_lck_info lck; 4704 struct rtw89_rx_dck_info rx_dck; 4705 bool is_tssi_mode[RF_PATH_MAX]; 4706 bool is_bt_iqk_timeout; 4707 4708 struct rtw89_fem_info fem; 4709 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 4710 struct rtw89_tssi_info tssi; 4711 struct rtw89_power_trim_info pwr_trim; 4712 4713 struct rtw89_cfo_tracking_info cfo_tracking; 4714 struct rtw89_env_monitor_info env_monitor; 4715 struct rtw89_dig_info dig; 4716 struct rtw89_phy_ch_info ch_info; 4717 struct rtw89_phy_bb_gain_info bb_gain; 4718 struct rtw89_phy_efuse_gain efuse_gain; 4719 struct rtw89_phy_ul_tb_info ul_tb_info; 4720 struct rtw89_antdiv_info antdiv; 4721 4722 struct delayed_work track_work; 4723 struct delayed_work chanctx_work; 4724 struct delayed_work coex_act1_work; 4725 struct delayed_work coex_bt_devinfo_work; 4726 struct delayed_work coex_rfk_chk_work; 4727 struct delayed_work cfo_track_work; 4728 struct delayed_work forbid_ba_work; 4729 struct delayed_work roc_work; 4730 struct delayed_work antdiv_work; 4731 struct rtw89_ppdu_sts_info ppdu_sts; 4732 u8 total_sta_assoc; 4733 bool scanning; 4734 4735 struct rtw89_regulatory_info regulatory; 4736 struct rtw89_sar_info sar; 4737 struct rtw89_tas_info tas; 4738 4739 struct rtw89_btc btc; 4740 enum rtw89_ps_mode ps_mode; 4741 bool lps_enabled; 4742 4743 struct rtw89_wow_param wow; 4744 4745 /* napi structure */ 4746 struct net_device netdev; 4747 struct napi_struct napi; 4748 int napi_budget_countdown; 4749 4750 /* HCI related data, keep last */ 4751 u8 priv[] __aligned(sizeof(void *)); 4752 }; 4753 4754 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4755 struct rtw89_core_tx_request *tx_req) 4756 { 4757 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4758 } 4759 4760 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4761 { 4762 rtwdev->hci.ops->reset(rtwdev); 4763 } 4764 4765 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4766 { 4767 return rtwdev->hci.ops->start(rtwdev); 4768 } 4769 4770 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4771 { 4772 rtwdev->hci.ops->stop(rtwdev); 4773 } 4774 4775 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4776 { 4777 return rtwdev->hci.ops->deinit(rtwdev); 4778 } 4779 4780 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4781 { 4782 rtwdev->hci.ops->pause(rtwdev, pause); 4783 } 4784 4785 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4786 { 4787 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4788 } 4789 4790 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4791 { 4792 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4793 } 4794 4795 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4796 { 4797 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4798 } 4799 4800 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4801 { 4802 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4803 } 4804 4805 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4806 bool drop) 4807 { 4808 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4809 return; 4810 4811 if (rtwdev->hci.ops->flush_queues) 4812 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4813 } 4814 4815 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4816 { 4817 if (rtwdev->hci.ops->recovery_start) 4818 rtwdev->hci.ops->recovery_start(rtwdev); 4819 } 4820 4821 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4822 { 4823 if (rtwdev->hci.ops->recovery_complete) 4824 rtwdev->hci.ops->recovery_complete(rtwdev); 4825 } 4826 4827 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4828 { 4829 if (rtwdev->hci.ops->enable_intr) 4830 rtwdev->hci.ops->enable_intr(rtwdev); 4831 } 4832 4833 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4834 { 4835 if (rtwdev->hci.ops->disable_intr) 4836 rtwdev->hci.ops->disable_intr(rtwdev); 4837 } 4838 4839 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4840 { 4841 if (rtwdev->hci.ops->ctrl_txdma_ch) 4842 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4843 } 4844 4845 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4846 { 4847 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4848 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4849 } 4850 4851 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4852 { 4853 if (rtwdev->hci.ops->ctrl_trxhci) 4854 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4855 } 4856 4857 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4858 { 4859 int ret = 0; 4860 4861 if (rtwdev->hci.ops->poll_txdma_ch) 4862 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4863 return ret; 4864 } 4865 4866 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4867 { 4868 if (rtwdev->hci.ops->clr_idx_all) 4869 rtwdev->hci.ops->clr_idx_all(rtwdev); 4870 } 4871 4872 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4873 { 4874 int ret = 0; 4875 4876 if (rtwdev->hci.ops->rst_bdram) 4877 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4878 return ret; 4879 } 4880 4881 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4882 { 4883 if (rtwdev->hci.ops->clear) 4884 rtwdev->hci.ops->clear(rtwdev, pdev); 4885 } 4886 4887 static inline 4888 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 4889 { 4890 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 4891 4892 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 4893 } 4894 4895 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 4896 { 4897 return rtwdev->hci.ops->read8(rtwdev, addr); 4898 } 4899 4900 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 4901 { 4902 return rtwdev->hci.ops->read16(rtwdev, addr); 4903 } 4904 4905 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 4906 { 4907 return rtwdev->hci.ops->read32(rtwdev, addr); 4908 } 4909 4910 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 4911 { 4912 rtwdev->hci.ops->write8(rtwdev, addr, data); 4913 } 4914 4915 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 4916 { 4917 rtwdev->hci.ops->write16(rtwdev, addr, data); 4918 } 4919 4920 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 4921 { 4922 rtwdev->hci.ops->write32(rtwdev, addr, data); 4923 } 4924 4925 static inline void 4926 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4927 { 4928 u8 val; 4929 4930 val = rtw89_read8(rtwdev, addr); 4931 rtw89_write8(rtwdev, addr, val | bit); 4932 } 4933 4934 static inline void 4935 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4936 { 4937 u16 val; 4938 4939 val = rtw89_read16(rtwdev, addr); 4940 rtw89_write16(rtwdev, addr, val | bit); 4941 } 4942 4943 static inline void 4944 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4945 { 4946 u32 val; 4947 4948 val = rtw89_read32(rtwdev, addr); 4949 rtw89_write32(rtwdev, addr, val | bit); 4950 } 4951 4952 static inline void 4953 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4954 { 4955 u8 val; 4956 4957 val = rtw89_read8(rtwdev, addr); 4958 rtw89_write8(rtwdev, addr, val & ~bit); 4959 } 4960 4961 static inline void 4962 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4963 { 4964 u16 val; 4965 4966 val = rtw89_read16(rtwdev, addr); 4967 rtw89_write16(rtwdev, addr, val & ~bit); 4968 } 4969 4970 static inline void 4971 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4972 { 4973 u32 val; 4974 4975 val = rtw89_read32(rtwdev, addr); 4976 rtw89_write32(rtwdev, addr, val & ~bit); 4977 } 4978 4979 static inline u32 4980 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4981 { 4982 u32 shift = __ffs(mask); 4983 u32 orig; 4984 u32 ret; 4985 4986 orig = rtw89_read32(rtwdev, addr); 4987 ret = (orig & mask) >> shift; 4988 4989 return ret; 4990 } 4991 4992 static inline u16 4993 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4994 { 4995 u32 shift = __ffs(mask); 4996 u32 orig; 4997 u32 ret; 4998 4999 orig = rtw89_read16(rtwdev, addr); 5000 ret = (orig & mask) >> shift; 5001 5002 return ret; 5003 } 5004 5005 static inline u8 5006 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5007 { 5008 u32 shift = __ffs(mask); 5009 u32 orig; 5010 u32 ret; 5011 5012 orig = rtw89_read8(rtwdev, addr); 5013 ret = (orig & mask) >> shift; 5014 5015 return ret; 5016 } 5017 5018 static inline void 5019 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5020 { 5021 u32 shift = __ffs(mask); 5022 u32 orig; 5023 u32 set; 5024 5025 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5026 5027 orig = rtw89_read32(rtwdev, addr); 5028 set = (orig & ~mask) | ((data << shift) & mask); 5029 rtw89_write32(rtwdev, addr, set); 5030 } 5031 5032 static inline void 5033 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5034 { 5035 u32 shift; 5036 u16 orig, set; 5037 5038 mask &= 0xffff; 5039 shift = __ffs(mask); 5040 5041 orig = rtw89_read16(rtwdev, addr); 5042 set = (orig & ~mask) | ((data << shift) & mask); 5043 rtw89_write16(rtwdev, addr, set); 5044 } 5045 5046 static inline void 5047 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5048 { 5049 u32 shift; 5050 u8 orig, set; 5051 5052 mask &= 0xff; 5053 shift = __ffs(mask); 5054 5055 orig = rtw89_read8(rtwdev, addr); 5056 set = (orig & ~mask) | ((data << shift) & mask); 5057 rtw89_write8(rtwdev, addr, set); 5058 } 5059 5060 static inline u32 5061 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5062 u32 addr, u32 mask) 5063 { 5064 u32 val; 5065 5066 mutex_lock(&rtwdev->rf_mutex); 5067 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5068 mutex_unlock(&rtwdev->rf_mutex); 5069 5070 return val; 5071 } 5072 5073 static inline void 5074 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5075 u32 addr, u32 mask, u32 data) 5076 { 5077 mutex_lock(&rtwdev->rf_mutex); 5078 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5079 mutex_unlock(&rtwdev->rf_mutex); 5080 } 5081 5082 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5083 { 5084 void *p = rtwtxq; 5085 5086 return container_of(p, struct ieee80211_txq, drv_priv); 5087 } 5088 5089 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5090 struct ieee80211_txq *txq) 5091 { 5092 struct rtw89_txq *rtwtxq; 5093 5094 if (!txq) 5095 return; 5096 5097 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5098 INIT_LIST_HEAD(&rtwtxq->list); 5099 } 5100 5101 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5102 { 5103 void *p = rtwvif; 5104 5105 return container_of(p, struct ieee80211_vif, drv_priv); 5106 } 5107 5108 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5109 { 5110 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5111 } 5112 5113 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5114 { 5115 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5116 } 5117 5118 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5119 { 5120 void *p = rtwsta; 5121 5122 return container_of(p, struct ieee80211_sta, drv_priv); 5123 } 5124 5125 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5126 { 5127 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5128 } 5129 5130 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5131 { 5132 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5133 } 5134 5135 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5136 { 5137 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5138 return RATE_INFO_BW_160; 5139 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5140 return RATE_INFO_BW_80; 5141 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5142 return RATE_INFO_BW_40; 5143 else 5144 return RATE_INFO_BW_20; 5145 } 5146 5147 static inline 5148 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5149 { 5150 switch (hw_band) { 5151 default: 5152 case RTW89_BAND_2G: 5153 return NL80211_BAND_2GHZ; 5154 case RTW89_BAND_5G: 5155 return NL80211_BAND_5GHZ; 5156 case RTW89_BAND_6G: 5157 return NL80211_BAND_6GHZ; 5158 } 5159 } 5160 5161 static inline 5162 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5163 { 5164 switch (nl_band) { 5165 default: 5166 case NL80211_BAND_2GHZ: 5167 return RTW89_BAND_2G; 5168 case NL80211_BAND_5GHZ: 5169 return RTW89_BAND_5G; 5170 case NL80211_BAND_6GHZ: 5171 return RTW89_BAND_6G; 5172 } 5173 } 5174 5175 static inline 5176 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5177 { 5178 switch (width) { 5179 default: 5180 WARN(1, "Not support bandwidth %d\n", width); 5181 fallthrough; 5182 case NL80211_CHAN_WIDTH_20_NOHT: 5183 case NL80211_CHAN_WIDTH_20: 5184 return RTW89_CHANNEL_WIDTH_20; 5185 case NL80211_CHAN_WIDTH_40: 5186 return RTW89_CHANNEL_WIDTH_40; 5187 case NL80211_CHAN_WIDTH_80: 5188 return RTW89_CHANNEL_WIDTH_80; 5189 case NL80211_CHAN_WIDTH_160: 5190 return RTW89_CHANNEL_WIDTH_160; 5191 } 5192 } 5193 5194 static inline 5195 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5196 { 5197 switch (rua) { 5198 default: 5199 WARN(1, "Invalid RU allocation: %d\n", rua); 5200 fallthrough; 5201 case 0 ... 36: 5202 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5203 case 37 ... 52: 5204 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5205 case 53 ... 60: 5206 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5207 case 61 ... 64: 5208 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5209 case 65 ... 66: 5210 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5211 case 67: 5212 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5213 case 68: 5214 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5215 } 5216 } 5217 5218 static inline 5219 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5220 struct rtw89_sta *rtwsta) 5221 { 5222 if (rtwsta) { 5223 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5224 5225 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5226 return &rtwsta->addr_cam; 5227 } 5228 return &rtwvif->addr_cam; 5229 } 5230 5231 static inline 5232 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5233 struct rtw89_sta *rtwsta) 5234 { 5235 if (rtwsta) { 5236 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5237 5238 if (sta->tdls) 5239 return &rtwsta->bssid_cam; 5240 } 5241 return &rtwvif->bssid_cam; 5242 } 5243 5244 static inline 5245 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5246 struct rtw89_channel_help_params *p, 5247 const struct rtw89_chan *chan, 5248 enum rtw89_mac_idx mac_idx, 5249 enum rtw89_phy_idx phy_idx) 5250 { 5251 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5252 mac_idx, phy_idx); 5253 } 5254 5255 static inline 5256 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 5257 struct rtw89_channel_help_params *p, 5258 const struct rtw89_chan *chan, 5259 enum rtw89_mac_idx mac_idx, 5260 enum rtw89_phy_idx phy_idx) 5261 { 5262 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 5263 mac_idx, phy_idx); 5264 } 5265 5266 static inline 5267 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 5268 enum rtw89_sub_entity_idx idx) 5269 { 5270 struct rtw89_hal *hal = &rtwdev->hal; 5271 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 5272 5273 if (roc_idx == idx) 5274 return &hal->roc_chandef; 5275 5276 return &hal->sub[idx].chandef; 5277 } 5278 5279 static inline 5280 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 5281 enum rtw89_sub_entity_idx idx) 5282 { 5283 struct rtw89_hal *hal = &rtwdev->hal; 5284 5285 return &hal->sub[idx].chan; 5286 } 5287 5288 static inline 5289 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 5290 enum rtw89_sub_entity_idx idx) 5291 { 5292 struct rtw89_hal *hal = &rtwdev->hal; 5293 5294 return &hal->sub[idx].rcd; 5295 } 5296 5297 static inline 5298 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 5299 { 5300 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 5301 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 5302 5303 if (rtwvif) 5304 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 5305 else 5306 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5307 } 5308 5309 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 5310 { 5311 const struct rtw89_chip_info *chip = rtwdev->chip; 5312 5313 if (chip->ops->fem_setup) 5314 chip->ops->fem_setup(rtwdev); 5315 } 5316 5317 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 5318 { 5319 const struct rtw89_chip_info *chip = rtwdev->chip; 5320 5321 if (chip->ops->rfe_gpio) 5322 chip->ops->rfe_gpio(rtwdev); 5323 } 5324 5325 static inline 5326 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5327 { 5328 const struct rtw89_chip_info *chip = rtwdev->chip; 5329 5330 if (chip->ops->bb_preinit) 5331 chip->ops->bb_preinit(rtwdev, phy_idx); 5332 } 5333 5334 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 5335 { 5336 const struct rtw89_chip_info *chip = rtwdev->chip; 5337 5338 if (chip->ops->bb_sethw) 5339 chip->ops->bb_sethw(rtwdev); 5340 } 5341 5342 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 5343 { 5344 const struct rtw89_chip_info *chip = rtwdev->chip; 5345 5346 if (chip->ops->rfk_init) 5347 chip->ops->rfk_init(rtwdev); 5348 } 5349 5350 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 5351 { 5352 const struct rtw89_chip_info *chip = rtwdev->chip; 5353 5354 if (chip->ops->rfk_channel) 5355 chip->ops->rfk_channel(rtwdev); 5356 } 5357 5358 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 5359 enum rtw89_phy_idx phy_idx) 5360 { 5361 const struct rtw89_chip_info *chip = rtwdev->chip; 5362 5363 if (chip->ops->rfk_band_changed) 5364 chip->ops->rfk_band_changed(rtwdev, phy_idx); 5365 } 5366 5367 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 5368 { 5369 const struct rtw89_chip_info *chip = rtwdev->chip; 5370 5371 if (chip->ops->rfk_scan) 5372 chip->ops->rfk_scan(rtwdev, start); 5373 } 5374 5375 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 5376 { 5377 const struct rtw89_chip_info *chip = rtwdev->chip; 5378 5379 if (chip->ops->rfk_track) 5380 chip->ops->rfk_track(rtwdev); 5381 } 5382 5383 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 5384 { 5385 const struct rtw89_chip_info *chip = rtwdev->chip; 5386 5387 if (chip->ops->set_txpwr_ctrl) 5388 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 5389 } 5390 5391 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 5392 { 5393 const struct rtw89_chip_info *chip = rtwdev->chip; 5394 5395 if (chip->ops->power_trim) 5396 chip->ops->power_trim(rtwdev); 5397 } 5398 5399 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 5400 enum rtw89_phy_idx phy_idx) 5401 { 5402 const struct rtw89_chip_info *chip = rtwdev->chip; 5403 5404 if (chip->ops->init_txpwr_unit) 5405 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 5406 } 5407 5408 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 5409 enum rtw89_rf_path rf_path) 5410 { 5411 const struct rtw89_chip_info *chip = rtwdev->chip; 5412 5413 if (!chip->ops->get_thermal) 5414 return 0x10; 5415 5416 return chip->ops->get_thermal(rtwdev, rf_path); 5417 } 5418 5419 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 5420 struct rtw89_rx_phy_ppdu *phy_ppdu, 5421 struct ieee80211_rx_status *status) 5422 { 5423 const struct rtw89_chip_info *chip = rtwdev->chip; 5424 5425 if (chip->ops->query_ppdu) 5426 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 5427 } 5428 5429 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 5430 enum rtw89_phy_idx phy_idx) 5431 { 5432 const struct rtw89_chip_info *chip = rtwdev->chip; 5433 5434 if (chip->ops->ctrl_nbtg_bt_tx) 5435 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 5436 } 5437 5438 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 5439 { 5440 const struct rtw89_chip_info *chip = rtwdev->chip; 5441 5442 if (chip->ops->cfg_txrx_path) 5443 chip->ops->cfg_txrx_path(rtwdev); 5444 } 5445 5446 static inline 5447 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5448 struct ieee80211_vif *vif) 5449 { 5450 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5451 const struct rtw89_chip_info *chip = rtwdev->chip; 5452 5453 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5454 return; 5455 5456 if (chip->ops->set_txpwr_ul_tb_offset) 5457 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5458 } 5459 5460 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 5461 const struct rtw89_txpwr_table *tbl) 5462 { 5463 tbl->load(rtwdev, tbl); 5464 } 5465 5466 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 5467 { 5468 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 5469 5470 return regd->txpwr_regd[band]; 5471 } 5472 5473 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 5474 enum rtw89_phy_idx phy_idx) 5475 { 5476 const struct rtw89_chip_info *chip = rtwdev->chip; 5477 5478 if (chip->ops->ctrl_btg_bt_rx) 5479 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 5480 } 5481 5482 static inline 5483 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 5484 struct rtw89_rx_desc_info *desc_info, 5485 u8 *data, u32 data_offset) 5486 { 5487 const struct rtw89_chip_info *chip = rtwdev->chip; 5488 5489 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 5490 } 5491 5492 static inline 5493 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 5494 struct rtw89_tx_desc_info *desc_info, 5495 void *txdesc) 5496 { 5497 const struct rtw89_chip_info *chip = rtwdev->chip; 5498 5499 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 5500 } 5501 5502 static inline 5503 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 5504 struct rtw89_tx_desc_info *desc_info, 5505 void *txdesc) 5506 { 5507 const struct rtw89_chip_info *chip = rtwdev->chip; 5508 5509 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 5510 } 5511 5512 static inline 5513 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5514 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5515 { 5516 const struct rtw89_chip_info *chip = rtwdev->chip; 5517 5518 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 5519 } 5520 5521 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5522 { 5523 const struct rtw89_chip_info *chip = rtwdev->chip; 5524 5525 chip->ops->cfg_ctrl_path(rtwdev, wl); 5526 } 5527 5528 static inline 5529 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 5530 u32 *tx_en, enum rtw89_sch_tx_sel sel) 5531 { 5532 const struct rtw89_chip_info *chip = rtwdev->chip; 5533 5534 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 5535 } 5536 5537 static inline 5538 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 5539 { 5540 const struct rtw89_chip_info *chip = rtwdev->chip; 5541 5542 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 5543 } 5544 5545 static inline 5546 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 5547 struct rtw89_vif *rtwvif, 5548 struct rtw89_sta *rtwsta) 5549 { 5550 const struct rtw89_chip_info *chip = rtwdev->chip; 5551 5552 if (!chip->ops->h2c_dctl_sec_cam) 5553 return 0; 5554 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 5555 } 5556 5557 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 5558 { 5559 __le16 fc = hdr->frame_control; 5560 5561 if (ieee80211_has_tods(fc)) 5562 return hdr->addr1; 5563 else if (ieee80211_has_fromds(fc)) 5564 return hdr->addr2; 5565 else 5566 return hdr->addr3; 5567 } 5568 5569 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 5570 { 5571 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5572 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 5573 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 5574 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5575 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 5576 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 5577 return true; 5578 return false; 5579 } 5580 5581 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 5582 enum rtw89_fw_type type) 5583 { 5584 struct rtw89_fw_info *fw_info = &rtwdev->fw; 5585 5586 switch (type) { 5587 case RTW89_FW_WOWLAN: 5588 return &fw_info->wowlan; 5589 case RTW89_FW_LOGFMT: 5590 return &fw_info->log.suit; 5591 case RTW89_FW_BBMCU0: 5592 return &fw_info->bbmcu0; 5593 case RTW89_FW_BBMCU1: 5594 return &fw_info->bbmcu1; 5595 default: 5596 break; 5597 } 5598 5599 return &fw_info->normal; 5600 } 5601 5602 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 5603 unsigned int length) 5604 { 5605 struct sk_buff *skb; 5606 5607 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 5608 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 5609 if (!skb) 5610 return NULL; 5611 5612 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 5613 return skb; 5614 } 5615 5616 return dev_alloc_skb(length); 5617 } 5618 5619 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 5620 struct rtw89_tx_skb_data *skb_data, 5621 bool tx_done) 5622 { 5623 struct rtw89_tx_wait_info *wait; 5624 5625 rcu_read_lock(); 5626 5627 wait = rcu_dereference(skb_data->wait); 5628 if (!wait) 5629 goto out; 5630 5631 wait->tx_done = tx_done; 5632 complete(&wait->completion); 5633 5634 out: 5635 rcu_read_unlock(); 5636 } 5637 5638 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5639 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 5640 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 5641 struct sk_buff *skb, bool fwdl); 5642 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 5643 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5644 int qsel, unsigned int timeout); 5645 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 5646 struct rtw89_tx_desc_info *desc_info, 5647 void *txdesc); 5648 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 5649 struct rtw89_tx_desc_info *desc_info, 5650 void *txdesc); 5651 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 5652 struct rtw89_tx_desc_info *desc_info, 5653 void *txdesc); 5654 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 5655 struct rtw89_tx_desc_info *desc_info, 5656 void *txdesc); 5657 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 5658 struct rtw89_tx_desc_info *desc_info, 5659 void *txdesc); 5660 void rtw89_core_rx(struct rtw89_dev *rtwdev, 5661 struct rtw89_rx_desc_info *desc_info, 5662 struct sk_buff *skb); 5663 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 5664 struct rtw89_rx_desc_info *desc_info, 5665 u8 *data, u32 data_offset); 5666 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 5667 struct rtw89_rx_desc_info *desc_info, 5668 u8 *data, u32 data_offset); 5669 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 5670 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 5671 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 5672 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 5673 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 5674 struct ieee80211_vif *vif, 5675 struct ieee80211_sta *sta); 5676 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 5677 struct ieee80211_vif *vif, 5678 struct ieee80211_sta *sta); 5679 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 5680 struct ieee80211_vif *vif, 5681 struct ieee80211_sta *sta); 5682 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 5683 struct ieee80211_vif *vif, 5684 struct ieee80211_sta *sta); 5685 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 5686 struct ieee80211_vif *vif, 5687 struct ieee80211_sta *sta); 5688 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5689 struct ieee80211_sta *sta, 5690 struct cfg80211_tid_config *tid_config); 5691 int rtw89_core_init(struct rtw89_dev *rtwdev); 5692 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 5693 int rtw89_core_register(struct rtw89_dev *rtwdev); 5694 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 5695 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5696 u32 bus_data_size, 5697 const struct rtw89_chip_info *chip); 5698 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 5699 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 5700 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 5701 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 5702 struct rtw89_chan *chan); 5703 void rtw89_set_channel(struct rtw89_dev *rtwdev); 5704 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5705 struct rtw89_chan *chan); 5706 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 5707 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 5708 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 5709 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 5710 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5711 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 5712 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5713 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 5714 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 5715 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 5716 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 5717 int rtw89_regd_init(struct rtw89_dev *rtwdev, 5718 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 5719 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 5720 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 5721 struct rtw89_traffic_stats *stats); 5722 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 5723 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5724 const struct rtw89_completion_data *data); 5725 int rtw89_core_start(struct rtw89_dev *rtwdev); 5726 void rtw89_core_stop(struct rtw89_dev *rtwdev); 5727 void rtw89_core_update_beacon_work(struct work_struct *work); 5728 void rtw89_roc_work(struct work_struct *work); 5729 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5730 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5731 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5732 const u8 *mac_addr, bool hw_scan); 5733 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5734 struct ieee80211_vif *vif, bool hw_scan); 5735 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 5736 struct rtw89_vif *rtwvif, bool active); 5737 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 5738 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 5739 5740 #endif 5741