xref: /linux/drivers/net/wireless/realtek/rtw89/core.h (revision a4eb44a6435d6d8f9e642407a4a06f65eb90ca04) 
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7 
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/firmware.h>
11 #include <linux/iopoll.h>
12 #include <linux/workqueue.h>
13 #include <net/mac80211.h>
14 
15 struct rtw89_dev;
16 
17 extern const struct ieee80211_ops rtw89_ops;
18 extern const struct rtw89_chip_info rtw8852a_chip_info;
19 
20 #define MASKBYTE0 0xff
21 #define MASKBYTE1 0xff00
22 #define MASKBYTE2 0xff0000
23 #define MASKBYTE3 0xff000000
24 #define MASKBYTE4 0xff00000000ULL
25 #define MASKHWORD 0xffff0000
26 #define MASKLWORD 0x0000ffff
27 #define MASKDWORD 0xffffffff
28 #define RFREG_MASK 0xfffff
29 #define INV_RF_DATA 0xffffffff
30 
31 #define RTW89_TRACK_WORK_PERIOD	round_jiffies_relative(HZ * 2)
32 #define CFO_TRACK_MAX_USER 64
33 #define MAX_RSSI 110
34 #define RSSI_FACTOR 1
35 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
36 #define RTW89_MAX_HW_PORT_NUM 5
37 
38 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
39 #define RTW89_HTC_VARIANT_HE 3
40 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
41 #define RTW89_HTC_VARIANT_HE_CID_OM 1
42 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
43 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
44 
45 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
46 enum htc_om_channel_width {
47 	HTC_OM_CHANNEL_WIDTH_20 = 0,
48 	HTC_OM_CHANNEL_WIDTH_40 = 1,
49 	HTC_OM_CHANNEL_WIDTH_80 = 2,
50 	HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
51 };
52 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
53 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
54 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
55 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
56 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
57 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
58 
59 enum rtw89_subband {
60 	RTW89_CH_2G = 0,
61 	RTW89_CH_5G_BAND_1 = 1,
62 	/* RTW89_CH_5G_BAND_2 = 2, unused */
63 	RTW89_CH_5G_BAND_3 = 3,
64 	RTW89_CH_5G_BAND_4 = 4,
65 
66 	RTW89_SUBBAND_NR,
67 };
68 
69 enum rtw89_hci_type {
70 	RTW89_HCI_TYPE_PCIE,
71 	RTW89_HCI_TYPE_USB,
72 	RTW89_HCI_TYPE_SDIO,
73 };
74 
75 enum rtw89_core_chip_id {
76 	RTL8852A,
77 	RTL8852B,
78 	RTL8852C,
79 };
80 
81 enum rtw89_cv {
82 	CHIP_CAV,
83 	CHIP_CBV,
84 	CHIP_CCV,
85 	CHIP_CDV,
86 	CHIP_CEV,
87 	CHIP_CFV,
88 	CHIP_CV_MAX,
89 	CHIP_CV_INVALID = CHIP_CV_MAX,
90 };
91 
92 enum rtw89_core_tx_type {
93 	RTW89_CORE_TX_TYPE_DATA,
94 	RTW89_CORE_TX_TYPE_MGMT,
95 	RTW89_CORE_TX_TYPE_FWCMD,
96 };
97 
98 enum rtw89_core_rx_type {
99 	RTW89_CORE_RX_TYPE_WIFI		= 0,
100 	RTW89_CORE_RX_TYPE_PPDU_STAT	= 1,
101 	RTW89_CORE_RX_TYPE_CHAN_INFO	= 2,
102 	RTW89_CORE_RX_TYPE_BB_SCOPE	= 3,
103 	RTW89_CORE_RX_TYPE_F2P_TXCMD	= 4,
104 	RTW89_CORE_RX_TYPE_SS2FW	= 5,
105 	RTW89_CORE_RX_TYPE_TX_REPORT	= 6,
106 	RTW89_CORE_RX_TYPE_TX_REL_HOST	= 7,
107 	RTW89_CORE_RX_TYPE_DFS_REPORT	= 8,
108 	RTW89_CORE_RX_TYPE_TX_REL_CPU	= 9,
109 	RTW89_CORE_RX_TYPE_C2H		= 10,
110 	RTW89_CORE_RX_TYPE_CSI		= 11,
111 	RTW89_CORE_RX_TYPE_CQI		= 12,
112 };
113 
114 enum rtw89_txq_flags {
115 	RTW89_TXQ_F_AMPDU		= 0,
116 	RTW89_TXQ_F_BLOCK_BA		= 1,
117 };
118 
119 enum rtw89_net_type {
120 	RTW89_NET_TYPE_NO_LINK		= 0,
121 	RTW89_NET_TYPE_AD_HOC		= 1,
122 	RTW89_NET_TYPE_INFRA		= 2,
123 	RTW89_NET_TYPE_AP_MODE		= 3,
124 };
125 
126 enum rtw89_wifi_role {
127 	RTW89_WIFI_ROLE_NONE,
128 	RTW89_WIFI_ROLE_STATION,
129 	RTW89_WIFI_ROLE_AP,
130 	RTW89_WIFI_ROLE_AP_VLAN,
131 	RTW89_WIFI_ROLE_ADHOC,
132 	RTW89_WIFI_ROLE_ADHOC_MASTER,
133 	RTW89_WIFI_ROLE_MESH_POINT,
134 	RTW89_WIFI_ROLE_MONITOR,
135 	RTW89_WIFI_ROLE_P2P_DEVICE,
136 	RTW89_WIFI_ROLE_P2P_CLIENT,
137 	RTW89_WIFI_ROLE_P2P_GO,
138 	RTW89_WIFI_ROLE_NAN,
139 	RTW89_WIFI_ROLE_MLME_MAX
140 };
141 
142 enum rtw89_upd_mode {
143 	RTW89_VIF_CREATE,
144 	RTW89_VIF_REMOVE,
145 	RTW89_VIF_TYPE_CHANGE,
146 	RTW89_VIF_INFO_CHANGE,
147 	RTW89_VIF_CON_DISCONN
148 };
149 
150 enum rtw89_self_role {
151 	RTW89_SELF_ROLE_CLIENT,
152 	RTW89_SELF_ROLE_AP,
153 	RTW89_SELF_ROLE_AP_CLIENT
154 };
155 
156 enum rtw89_msk_sO_el {
157 	RTW89_NO_MSK,
158 	RTW89_SMA,
159 	RTW89_TMA,
160 	RTW89_BSSID
161 };
162 
163 enum rtw89_sch_tx_sel {
164 	RTW89_SCH_TX_SEL_ALL,
165 	RTW89_SCH_TX_SEL_HIQ,
166 	RTW89_SCH_TX_SEL_MG0,
167 	RTW89_SCH_TX_SEL_MACID,
168 };
169 
170 /* RTW89_ADDR_CAM_SEC_NONE	: not enabled
171  * RTW89_ADDR_CAM_SEC_ALL_UNI	: 0 - 6 unicast
172  * RTW89_ADDR_CAM_SEC_NORMAL	: 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
173  * RTW89_ADDR_CAM_SEC_4GROUP	: 0 - 1 unicast, 2 - 5 group, 6 BIP
174  */
175 enum rtw89_add_cam_sec_mode {
176 	RTW89_ADDR_CAM_SEC_NONE		= 0,
177 	RTW89_ADDR_CAM_SEC_ALL_UNI	= 1,
178 	RTW89_ADDR_CAM_SEC_NORMAL	= 2,
179 	RTW89_ADDR_CAM_SEC_4GROUP	= 3,
180 };
181 
182 enum rtw89_sec_key_type {
183 	RTW89_SEC_KEY_TYPE_NONE		= 0,
184 	RTW89_SEC_KEY_TYPE_WEP40	= 1,
185 	RTW89_SEC_KEY_TYPE_WEP104	= 2,
186 	RTW89_SEC_KEY_TYPE_TKIP		= 3,
187 	RTW89_SEC_KEY_TYPE_WAPI		= 4,
188 	RTW89_SEC_KEY_TYPE_GCMSMS4	= 5,
189 	RTW89_SEC_KEY_TYPE_CCMP128	= 6,
190 	RTW89_SEC_KEY_TYPE_CCMP256	= 7,
191 	RTW89_SEC_KEY_TYPE_GCMP128	= 8,
192 	RTW89_SEC_KEY_TYPE_GCMP256	= 9,
193 	RTW89_SEC_KEY_TYPE_BIP_CCMP128	= 10,
194 };
195 
196 enum rtw89_port {
197 	RTW89_PORT_0 = 0,
198 	RTW89_PORT_1 = 1,
199 	RTW89_PORT_2 = 2,
200 	RTW89_PORT_3 = 3,
201 	RTW89_PORT_4 = 4,
202 	RTW89_PORT_NUM
203 };
204 
205 enum rtw89_band {
206 	RTW89_BAND_2G = 0,
207 	RTW89_BAND_5G = 1,
208 	RTW89_BAND_MAX,
209 };
210 
211 enum rtw89_hw_rate {
212 	RTW89_HW_RATE_CCK1	= 0x0,
213 	RTW89_HW_RATE_CCK2	= 0x1,
214 	RTW89_HW_RATE_CCK5_5	= 0x2,
215 	RTW89_HW_RATE_CCK11	= 0x3,
216 	RTW89_HW_RATE_OFDM6	= 0x4,
217 	RTW89_HW_RATE_OFDM9	= 0x5,
218 	RTW89_HW_RATE_OFDM12	= 0x6,
219 	RTW89_HW_RATE_OFDM18	= 0x7,
220 	RTW89_HW_RATE_OFDM24	= 0x8,
221 	RTW89_HW_RATE_OFDM36	= 0x9,
222 	RTW89_HW_RATE_OFDM48	= 0xA,
223 	RTW89_HW_RATE_OFDM54	= 0xB,
224 	RTW89_HW_RATE_MCS0	= 0x80,
225 	RTW89_HW_RATE_MCS1	= 0x81,
226 	RTW89_HW_RATE_MCS2	= 0x82,
227 	RTW89_HW_RATE_MCS3	= 0x83,
228 	RTW89_HW_RATE_MCS4	= 0x84,
229 	RTW89_HW_RATE_MCS5	= 0x85,
230 	RTW89_HW_RATE_MCS6	= 0x86,
231 	RTW89_HW_RATE_MCS7	= 0x87,
232 	RTW89_HW_RATE_MCS8	= 0x88,
233 	RTW89_HW_RATE_MCS9	= 0x89,
234 	RTW89_HW_RATE_MCS10	= 0x8A,
235 	RTW89_HW_RATE_MCS11	= 0x8B,
236 	RTW89_HW_RATE_MCS12	= 0x8C,
237 	RTW89_HW_RATE_MCS13	= 0x8D,
238 	RTW89_HW_RATE_MCS14	= 0x8E,
239 	RTW89_HW_RATE_MCS15	= 0x8F,
240 	RTW89_HW_RATE_MCS16	= 0x90,
241 	RTW89_HW_RATE_MCS17	= 0x91,
242 	RTW89_HW_RATE_MCS18	= 0x92,
243 	RTW89_HW_RATE_MCS19	= 0x93,
244 	RTW89_HW_RATE_MCS20	= 0x94,
245 	RTW89_HW_RATE_MCS21	= 0x95,
246 	RTW89_HW_RATE_MCS22	= 0x96,
247 	RTW89_HW_RATE_MCS23	= 0x97,
248 	RTW89_HW_RATE_MCS24	= 0x98,
249 	RTW89_HW_RATE_MCS25	= 0x99,
250 	RTW89_HW_RATE_MCS26	= 0x9A,
251 	RTW89_HW_RATE_MCS27	= 0x9B,
252 	RTW89_HW_RATE_MCS28	= 0x9C,
253 	RTW89_HW_RATE_MCS29	= 0x9D,
254 	RTW89_HW_RATE_MCS30	= 0x9E,
255 	RTW89_HW_RATE_MCS31	= 0x9F,
256 	RTW89_HW_RATE_VHT_NSS1_MCS0	= 0x100,
257 	RTW89_HW_RATE_VHT_NSS1_MCS1	= 0x101,
258 	RTW89_HW_RATE_VHT_NSS1_MCS2	= 0x102,
259 	RTW89_HW_RATE_VHT_NSS1_MCS3	= 0x103,
260 	RTW89_HW_RATE_VHT_NSS1_MCS4	= 0x104,
261 	RTW89_HW_RATE_VHT_NSS1_MCS5	= 0x105,
262 	RTW89_HW_RATE_VHT_NSS1_MCS6	= 0x106,
263 	RTW89_HW_RATE_VHT_NSS1_MCS7	= 0x107,
264 	RTW89_HW_RATE_VHT_NSS1_MCS8	= 0x108,
265 	RTW89_HW_RATE_VHT_NSS1_MCS9	= 0x109,
266 	RTW89_HW_RATE_VHT_NSS2_MCS0	= 0x110,
267 	RTW89_HW_RATE_VHT_NSS2_MCS1	= 0x111,
268 	RTW89_HW_RATE_VHT_NSS2_MCS2	= 0x112,
269 	RTW89_HW_RATE_VHT_NSS2_MCS3	= 0x113,
270 	RTW89_HW_RATE_VHT_NSS2_MCS4	= 0x114,
271 	RTW89_HW_RATE_VHT_NSS2_MCS5	= 0x115,
272 	RTW89_HW_RATE_VHT_NSS2_MCS6	= 0x116,
273 	RTW89_HW_RATE_VHT_NSS2_MCS7	= 0x117,
274 	RTW89_HW_RATE_VHT_NSS2_MCS8	= 0x118,
275 	RTW89_HW_RATE_VHT_NSS2_MCS9	= 0x119,
276 	RTW89_HW_RATE_VHT_NSS3_MCS0	= 0x120,
277 	RTW89_HW_RATE_VHT_NSS3_MCS1	= 0x121,
278 	RTW89_HW_RATE_VHT_NSS3_MCS2	= 0x122,
279 	RTW89_HW_RATE_VHT_NSS3_MCS3	= 0x123,
280 	RTW89_HW_RATE_VHT_NSS3_MCS4	= 0x124,
281 	RTW89_HW_RATE_VHT_NSS3_MCS5	= 0x125,
282 	RTW89_HW_RATE_VHT_NSS3_MCS6	= 0x126,
283 	RTW89_HW_RATE_VHT_NSS3_MCS7	= 0x127,
284 	RTW89_HW_RATE_VHT_NSS3_MCS8	= 0x128,
285 	RTW89_HW_RATE_VHT_NSS3_MCS9	= 0x129,
286 	RTW89_HW_RATE_VHT_NSS4_MCS0	= 0x130,
287 	RTW89_HW_RATE_VHT_NSS4_MCS1	= 0x131,
288 	RTW89_HW_RATE_VHT_NSS4_MCS2	= 0x132,
289 	RTW89_HW_RATE_VHT_NSS4_MCS3	= 0x133,
290 	RTW89_HW_RATE_VHT_NSS4_MCS4	= 0x134,
291 	RTW89_HW_RATE_VHT_NSS4_MCS5	= 0x135,
292 	RTW89_HW_RATE_VHT_NSS4_MCS6	= 0x136,
293 	RTW89_HW_RATE_VHT_NSS4_MCS7	= 0x137,
294 	RTW89_HW_RATE_VHT_NSS4_MCS8	= 0x138,
295 	RTW89_HW_RATE_VHT_NSS4_MCS9	= 0x139,
296 	RTW89_HW_RATE_HE_NSS1_MCS0	= 0x180,
297 	RTW89_HW_RATE_HE_NSS1_MCS1	= 0x181,
298 	RTW89_HW_RATE_HE_NSS1_MCS2	= 0x182,
299 	RTW89_HW_RATE_HE_NSS1_MCS3	= 0x183,
300 	RTW89_HW_RATE_HE_NSS1_MCS4	= 0x184,
301 	RTW89_HW_RATE_HE_NSS1_MCS5	= 0x185,
302 	RTW89_HW_RATE_HE_NSS1_MCS6	= 0x186,
303 	RTW89_HW_RATE_HE_NSS1_MCS7	= 0x187,
304 	RTW89_HW_RATE_HE_NSS1_MCS8	= 0x188,
305 	RTW89_HW_RATE_HE_NSS1_MCS9	= 0x189,
306 	RTW89_HW_RATE_HE_NSS1_MCS10	= 0x18A,
307 	RTW89_HW_RATE_HE_NSS1_MCS11	= 0x18B,
308 	RTW89_HW_RATE_HE_NSS2_MCS0	= 0x190,
309 	RTW89_HW_RATE_HE_NSS2_MCS1	= 0x191,
310 	RTW89_HW_RATE_HE_NSS2_MCS2	= 0x192,
311 	RTW89_HW_RATE_HE_NSS2_MCS3	= 0x193,
312 	RTW89_HW_RATE_HE_NSS2_MCS4	= 0x194,
313 	RTW89_HW_RATE_HE_NSS2_MCS5	= 0x195,
314 	RTW89_HW_RATE_HE_NSS2_MCS6	= 0x196,
315 	RTW89_HW_RATE_HE_NSS2_MCS7	= 0x197,
316 	RTW89_HW_RATE_HE_NSS2_MCS8	= 0x198,
317 	RTW89_HW_RATE_HE_NSS2_MCS9	= 0x199,
318 	RTW89_HW_RATE_HE_NSS2_MCS10	= 0x19A,
319 	RTW89_HW_RATE_HE_NSS2_MCS11	= 0x19B,
320 	RTW89_HW_RATE_HE_NSS3_MCS0	= 0x1A0,
321 	RTW89_HW_RATE_HE_NSS3_MCS1	= 0x1A1,
322 	RTW89_HW_RATE_HE_NSS3_MCS2	= 0x1A2,
323 	RTW89_HW_RATE_HE_NSS3_MCS3	= 0x1A3,
324 	RTW89_HW_RATE_HE_NSS3_MCS4	= 0x1A4,
325 	RTW89_HW_RATE_HE_NSS3_MCS5	= 0x1A5,
326 	RTW89_HW_RATE_HE_NSS3_MCS6	= 0x1A6,
327 	RTW89_HW_RATE_HE_NSS3_MCS7	= 0x1A7,
328 	RTW89_HW_RATE_HE_NSS3_MCS8	= 0x1A8,
329 	RTW89_HW_RATE_HE_NSS3_MCS9	= 0x1A9,
330 	RTW89_HW_RATE_HE_NSS3_MCS10	= 0x1AA,
331 	RTW89_HW_RATE_HE_NSS3_MCS11	= 0x1AB,
332 	RTW89_HW_RATE_HE_NSS4_MCS0	= 0x1B0,
333 	RTW89_HW_RATE_HE_NSS4_MCS1	= 0x1B1,
334 	RTW89_HW_RATE_HE_NSS4_MCS2	= 0x1B2,
335 	RTW89_HW_RATE_HE_NSS4_MCS3	= 0x1B3,
336 	RTW89_HW_RATE_HE_NSS4_MCS4	= 0x1B4,
337 	RTW89_HW_RATE_HE_NSS4_MCS5	= 0x1B5,
338 	RTW89_HW_RATE_HE_NSS4_MCS6	= 0x1B6,
339 	RTW89_HW_RATE_HE_NSS4_MCS7	= 0x1B7,
340 	RTW89_HW_RATE_HE_NSS4_MCS8	= 0x1B8,
341 	RTW89_HW_RATE_HE_NSS4_MCS9	= 0x1B9,
342 	RTW89_HW_RATE_HE_NSS4_MCS10	= 0x1BA,
343 	RTW89_HW_RATE_HE_NSS4_MCS11	= 0x1BB,
344 	RTW89_HW_RATE_NR,
345 
346 	RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
347 	RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
348 };
349 
350 /* 2G channels,
351  * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
352  */
353 #define RTW89_2G_CH_NUM 14
354 
355 /* 5G channels,
356  * 36, 38, 40, 42, 44, 46, 48, 50,
357  * 52, 54, 56, 58, 60, 62, 64,
358  * 100, 102, 104, 106, 108, 110, 112, 114,
359  * 116, 118, 120, 122, 124, 126, 128, 130,
360  * 132, 134, 136, 138, 140, 142, 144,
361  * 149, 151, 153, 155, 157, 159, 161, 163,
362  * 165, 167, 169, 171, 173, 175, 177
363  */
364 #define RTW89_5G_CH_NUM 53
365 
366 enum rtw89_rate_section {
367 	RTW89_RS_CCK,
368 	RTW89_RS_OFDM,
369 	RTW89_RS_MCS, /* for HT/VHT/HE */
370 	RTW89_RS_HEDCM,
371 	RTW89_RS_OFFSET,
372 	RTW89_RS_MAX,
373 	RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
374 };
375 
376 enum rtw89_rate_max {
377 	RTW89_RATE_CCK_MAX	= 4,
378 	RTW89_RATE_OFDM_MAX	= 8,
379 	RTW89_RATE_MCS_MAX	= 12,
380 	RTW89_RATE_HEDCM_MAX	= 4, /* for HEDCM MCS0/1/3/4 */
381 	RTW89_RATE_OFFSET_MAX	= 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
382 };
383 
384 enum rtw89_nss {
385 	RTW89_NSS_1		= 0,
386 	RTW89_NSS_2		= 1,
387 	/* HE DCM only support 1ss and 2ss */
388 	RTW89_NSS_HEDCM_MAX	= RTW89_NSS_2 + 1,
389 	RTW89_NSS_3		= 2,
390 	RTW89_NSS_4		= 3,
391 	RTW89_NSS_MAX,
392 };
393 
394 enum rtw89_ntx {
395 	RTW89_1TX	= 0,
396 	RTW89_2TX	= 1,
397 	RTW89_NTX_NUM,
398 };
399 
400 enum rtw89_beamforming_type {
401 	RTW89_NONBF	= 0,
402 	RTW89_BF	= 1,
403 	RTW89_BF_NUM,
404 };
405 
406 enum rtw89_regulation_type {
407 	RTW89_WW	= 0,
408 	RTW89_ETSI	= 1,
409 	RTW89_FCC	= 2,
410 	RTW89_MKK	= 3,
411 	RTW89_NA	= 4,
412 	RTW89_IC	= 5,
413 	RTW89_KCC	= 6,
414 	RTW89_ACMA	= 7,
415 	RTW89_NCC	= 8,
416 	RTW89_MEXICO	= 9,
417 	RTW89_CHILE	= 10,
418 	RTW89_UKRAINE	= 11,
419 	RTW89_CN	= 12,
420 	RTW89_QATAR	= 13,
421 	RTW89_REGD_NUM,
422 };
423 
424 extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX];
425 extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX];
426 
427 struct rtw89_txpwr_byrate {
428 	s8 cck[RTW89_RATE_CCK_MAX];
429 	s8 ofdm[RTW89_RATE_OFDM_MAX];
430 	s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX];
431 	s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX];
432 	s8 offset[RTW89_RATE_OFFSET_MAX];
433 };
434 
435 enum rtw89_bandwidth_section_num {
436 	RTW89_BW20_SEC_NUM = 8,
437 	RTW89_BW40_SEC_NUM = 4,
438 	RTW89_BW80_SEC_NUM = 2,
439 };
440 
441 struct rtw89_txpwr_limit {
442 	s8 cck_20m[RTW89_BF_NUM];
443 	s8 cck_40m[RTW89_BF_NUM];
444 	s8 ofdm[RTW89_BF_NUM];
445 	s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
446 	s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
447 	s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
448 	s8 mcs_160m[RTW89_BF_NUM];
449 	s8 mcs_40m_0p5[RTW89_BF_NUM];
450 	s8 mcs_40m_2p5[RTW89_BF_NUM];
451 };
452 
453 #define RTW89_RU_SEC_NUM 8
454 
455 struct rtw89_txpwr_limit_ru {
456 	s8 ru26[RTW89_RU_SEC_NUM];
457 	s8 ru52[RTW89_RU_SEC_NUM];
458 	s8 ru106[RTW89_RU_SEC_NUM];
459 };
460 
461 struct rtw89_rate_desc {
462 	enum rtw89_nss nss;
463 	enum rtw89_rate_section rs;
464 	u8 idx;
465 };
466 
467 #define PHY_STS_HDR_LEN 8
468 #define RF_PATH_MAX 4
469 #define RTW89_MAX_PPDU_CNT 8
470 struct rtw89_rx_phy_ppdu {
471 	u8 *buf;
472 	u32 len;
473 	u8 rssi_avg;
474 	s8 rssi[RF_PATH_MAX];
475 	u8 mac_id;
476 	u8 chan_idx;
477 	u8 ie;
478 	u16 rate;
479 	bool to_self;
480 	bool valid;
481 };
482 
483 enum rtw89_mac_idx {
484 	RTW89_MAC_0 = 0,
485 	RTW89_MAC_1 = 1,
486 };
487 
488 enum rtw89_phy_idx {
489 	RTW89_PHY_0 = 0,
490 	RTW89_PHY_1 = 1,
491 	RTW89_PHY_MAX
492 };
493 
494 enum rtw89_rf_path {
495 	RF_PATH_A = 0,
496 	RF_PATH_B = 1,
497 	RF_PATH_C = 2,
498 	RF_PATH_D = 3,
499 	RF_PATH_AB,
500 	RF_PATH_AC,
501 	RF_PATH_AD,
502 	RF_PATH_BC,
503 	RF_PATH_BD,
504 	RF_PATH_CD,
505 	RF_PATH_ABC,
506 	RF_PATH_ABD,
507 	RF_PATH_ACD,
508 	RF_PATH_BCD,
509 	RF_PATH_ABCD,
510 };
511 
512 enum rtw89_rf_path_bit {
513 	RF_A	= BIT(0),
514 	RF_B	= BIT(1),
515 	RF_C	= BIT(2),
516 	RF_D	= BIT(3),
517 
518 	RF_AB	= (RF_A | RF_B),
519 	RF_AC	= (RF_A | RF_C),
520 	RF_AD	= (RF_A | RF_D),
521 	RF_BC	= (RF_B | RF_C),
522 	RF_BD	= (RF_B | RF_D),
523 	RF_CD	= (RF_C | RF_D),
524 
525 	RF_ABC	= (RF_A | RF_B | RF_C),
526 	RF_ABD	= (RF_A | RF_B | RF_D),
527 	RF_ACD	= (RF_A | RF_C | RF_D),
528 	RF_BCD	= (RF_B | RF_C | RF_D),
529 
530 	RF_ABCD	= (RF_A | RF_B | RF_C | RF_D),
531 };
532 
533 enum rtw89_bandwidth {
534 	RTW89_CHANNEL_WIDTH_20	= 0,
535 	RTW89_CHANNEL_WIDTH_40	= 1,
536 	RTW89_CHANNEL_WIDTH_80	= 2,
537 	RTW89_CHANNEL_WIDTH_160	= 3,
538 	RTW89_CHANNEL_WIDTH_80_80	= 4,
539 	RTW89_CHANNEL_WIDTH_5	= 5,
540 	RTW89_CHANNEL_WIDTH_10	= 6,
541 };
542 
543 enum rtw89_ps_mode {
544 	RTW89_PS_MODE_NONE	= 0,
545 	RTW89_PS_MODE_RFOFF	= 1,
546 	RTW89_PS_MODE_CLK_GATED	= 2,
547 	RTW89_PS_MODE_PWR_GATED	= 3,
548 };
549 
550 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
551 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1)
552 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1)
553 
554 enum rtw89_ru_bandwidth {
555 	RTW89_RU26 = 0,
556 	RTW89_RU52 = 1,
557 	RTW89_RU106 = 2,
558 	RTW89_RU_NUM,
559 };
560 
561 enum rtw89_sc_offset {
562 	RTW89_SC_DONT_CARE	= 0,
563 	RTW89_SC_20_UPPER	= 1,
564 	RTW89_SC_20_LOWER	= 2,
565 	RTW89_SC_20_UPMOST	= 3,
566 	RTW89_SC_20_LOWEST	= 4,
567 	RTW89_SC_40_UPPER	= 9,
568 	RTW89_SC_40_LOWER	= 10,
569 };
570 
571 struct rtw89_channel_params {
572 	u8 center_chan;
573 	u8 primary_chan;
574 	u8 bandwidth;
575 	u8 pri_ch_idx;
576 };
577 
578 struct rtw89_channel_help_params {
579 	u16 tx_en;
580 };
581 
582 struct rtw89_port_reg {
583 	u32 port_cfg;
584 	u32 tbtt_prohib;
585 	u32 bcn_area;
586 	u32 bcn_early;
587 	u32 tbtt_early;
588 	u32 tbtt_agg;
589 	u32 bcn_space;
590 	u32 bcn_forcetx;
591 	u32 bcn_err_cnt;
592 	u32 bcn_err_flag;
593 	u32 dtim_ctrl;
594 	u32 tbtt_shift;
595 	u32 bcn_cnt_tmr;
596 	u32 tsftr_l;
597 	u32 tsftr_h;
598 };
599 
600 struct rtw89_txwd_body {
601 	__le32 dword0;
602 	__le32 dword1;
603 	__le32 dword2;
604 	__le32 dword3;
605 	__le32 dword4;
606 	__le32 dword5;
607 } __packed;
608 
609 struct rtw89_txwd_info {
610 	__le32 dword0;
611 	__le32 dword1;
612 	__le32 dword2;
613 	__le32 dword3;
614 	__le32 dword4;
615 	__le32 dword5;
616 } __packed;
617 
618 struct rtw89_rx_desc_info {
619 	u16 pkt_size;
620 	u8 pkt_type;
621 	u8 drv_info_size;
622 	u8 shift;
623 	u8 wl_hd_iv_len;
624 	bool long_rxdesc;
625 	bool bb_sel;
626 	bool mac_info_valid;
627 	u16 data_rate;
628 	u8 gi_ltf;
629 	u8 bw;
630 	u32 free_run_cnt;
631 	u8 user_id;
632 	bool sr_en;
633 	u8 ppdu_cnt;
634 	u8 ppdu_type;
635 	bool icv_err;
636 	bool crc32_err;
637 	bool hw_dec;
638 	bool sw_dec;
639 	bool addr1_match;
640 	u8 frag;
641 	u16 seq;
642 	u8 frame_type;
643 	u8 rx_pl_id;
644 	bool addr_cam_valid;
645 	u8 addr_cam_id;
646 	u8 sec_cam_id;
647 	u8 mac_id;
648 	u16 offset;
649 	bool ready;
650 };
651 
652 struct rtw89_rxdesc_short {
653 	__le32 dword0;
654 	__le32 dword1;
655 	__le32 dword2;
656 	__le32 dword3;
657 } __packed;
658 
659 struct rtw89_rxdesc_long {
660 	__le32 dword0;
661 	__le32 dword1;
662 	__le32 dword2;
663 	__le32 dword3;
664 	__le32 dword4;
665 	__le32 dword5;
666 	__le32 dword6;
667 	__le32 dword7;
668 } __packed;
669 
670 struct rtw89_tx_desc_info {
671 	u16 pkt_size;
672 	u8 wp_offset;
673 	u8 qsel;
674 	u8 ch_dma;
675 	u8 hdr_llc_len;
676 	bool is_bmc;
677 	bool en_wd_info;
678 	bool wd_page;
679 	bool use_rate;
680 	bool dis_data_fb;
681 	bool tid_indicate;
682 	bool agg_en;
683 	bool bk;
684 	u8 ampdu_density;
685 	u8 ampdu_num;
686 	bool sec_en;
687 	u8 sec_type;
688 	u8 sec_cam_idx;
689 	u16 data_rate;
690 	u16 data_retry_lowest_rate;
691 	bool fw_dl;
692 	u16 seq;
693 	bool a_ctrl_bsr;
694 };
695 
696 struct rtw89_core_tx_request {
697 	enum rtw89_core_tx_type tx_type;
698 
699 	struct sk_buff *skb;
700 	struct ieee80211_vif *vif;
701 	struct ieee80211_sta *sta;
702 	struct rtw89_tx_desc_info desc_info;
703 };
704 
705 struct rtw89_txq {
706 	struct list_head list;
707 	unsigned long flags;
708 	int wait_cnt;
709 };
710 
711 struct rtw89_mac_ax_gnt {
712 	u8 gnt_bt_sw_en;
713 	u8 gnt_bt;
714 	u8 gnt_wl_sw_en;
715 	u8 gnt_wl;
716 };
717 
718 #define RTW89_MAC_AX_COEX_GNT_NR 2
719 struct rtw89_mac_ax_coex_gnt {
720 	struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
721 };
722 
723 enum rtw89_btc_ncnt {
724 	BTC_NCNT_POWER_ON = 0x0,
725 	BTC_NCNT_POWER_OFF,
726 	BTC_NCNT_INIT_COEX,
727 	BTC_NCNT_SCAN_START,
728 	BTC_NCNT_SCAN_FINISH,
729 	BTC_NCNT_SPECIAL_PACKET,
730 	BTC_NCNT_SWITCH_BAND,
731 	BTC_NCNT_RFK_TIMEOUT,
732 	BTC_NCNT_SHOW_COEX_INFO,
733 	BTC_NCNT_ROLE_INFO,
734 	BTC_NCNT_CONTROL,
735 	BTC_NCNT_RADIO_STATE,
736 	BTC_NCNT_CUSTOMERIZE,
737 	BTC_NCNT_WL_RFK,
738 	BTC_NCNT_WL_STA,
739 	BTC_NCNT_FWINFO,
740 	BTC_NCNT_TIMER,
741 	BTC_NCNT_NUM
742 };
743 
744 enum rtw89_btc_btinfo {
745 	BTC_BTINFO_L0 = 0,
746 	BTC_BTINFO_L1,
747 	BTC_BTINFO_L2,
748 	BTC_BTINFO_L3,
749 	BTC_BTINFO_H0,
750 	BTC_BTINFO_H1,
751 	BTC_BTINFO_H2,
752 	BTC_BTINFO_H3,
753 	BTC_BTINFO_MAX
754 };
755 
756 enum rtw89_btc_dcnt {
757 	BTC_DCNT_RUN = 0x0,
758 	BTC_DCNT_CX_RUNINFO,
759 	BTC_DCNT_RPT,
760 	BTC_DCNT_RPT_FREEZE,
761 	BTC_DCNT_CYCLE,
762 	BTC_DCNT_CYCLE_FREEZE,
763 	BTC_DCNT_W1,
764 	BTC_DCNT_W1_FREEZE,
765 	BTC_DCNT_B1,
766 	BTC_DCNT_B1_FREEZE,
767 	BTC_DCNT_TDMA_NONSYNC,
768 	BTC_DCNT_SLOT_NONSYNC,
769 	BTC_DCNT_BTCNT_FREEZE,
770 	BTC_DCNT_WL_SLOT_DRIFT,
771 	BTC_DCNT_WL_STA_LAST,
772 	BTC_DCNT_NUM,
773 };
774 
775 enum rtw89_btc_wl_state_cnt {
776 	BTC_WCNT_SCANAP = 0x0,
777 	BTC_WCNT_DHCP,
778 	BTC_WCNT_EAPOL,
779 	BTC_WCNT_ARP,
780 	BTC_WCNT_SCBDUPDATE,
781 	BTC_WCNT_RFK_REQ,
782 	BTC_WCNT_RFK_GO,
783 	BTC_WCNT_RFK_REJECT,
784 	BTC_WCNT_RFK_TIMEOUT,
785 	BTC_WCNT_CH_UPDATE,
786 	BTC_WCNT_NUM
787 };
788 
789 enum rtw89_btc_bt_state_cnt {
790 	BTC_BCNT_RETRY = 0x0,
791 	BTC_BCNT_REINIT,
792 	BTC_BCNT_REENABLE,
793 	BTC_BCNT_SCBDREAD,
794 	BTC_BCNT_RELINK,
795 	BTC_BCNT_IGNOWL,
796 	BTC_BCNT_INQPAG,
797 	BTC_BCNT_INQ,
798 	BTC_BCNT_PAGE,
799 	BTC_BCNT_ROLESW,
800 	BTC_BCNT_AFH,
801 	BTC_BCNT_INFOUPDATE,
802 	BTC_BCNT_INFOSAME,
803 	BTC_BCNT_SCBDUPDATE,
804 	BTC_BCNT_HIPRI_TX,
805 	BTC_BCNT_HIPRI_RX,
806 	BTC_BCNT_LOPRI_TX,
807 	BTC_BCNT_LOPRI_RX,
808 	BTC_BCNT_POLUT,
809 	BTC_BCNT_RATECHG,
810 	BTC_BCNT_NUM
811 };
812 
813 enum rtw89_btc_bt_profile {
814 	BTC_BT_NOPROFILE = 0,
815 	BTC_BT_HFP = BIT(0),
816 	BTC_BT_HID = BIT(1),
817 	BTC_BT_A2DP = BIT(2),
818 	BTC_BT_PAN = BIT(3),
819 	BTC_PROFILE_MAX = 4,
820 };
821 
822 struct rtw89_btc_ant_info {
823 	u8 type;  /* shared, dedicated */
824 	u8 num;
825 	u8 isolation;
826 
827 	u8 single_pos: 1;/* Single antenna at S0 or S1 */
828 	u8 diversity: 1;
829 };
830 
831 enum rtw89_tfc_dir {
832 	RTW89_TFC_UL,
833 	RTW89_TFC_DL,
834 };
835 
836 struct rtw89_btc_wl_smap {
837 	u32 busy: 1;
838 	u32 scan: 1;
839 	u32 connecting: 1;
840 	u32 roaming: 1;
841 	u32 _4way: 1;
842 	u32 rf_off: 1;
843 	u32 lps: 1;
844 	u32 ips: 1;
845 	u32 init_ok: 1;
846 	u32 traffic_dir : 2;
847 	u32 rf_off_pre: 1;
848 	u32 lps_pre: 1;
849 };
850 
851 enum rtw89_tfc_lv {
852 	RTW89_TFC_IDLE,
853 	RTW89_TFC_ULTRA_LOW,
854 	RTW89_TFC_LOW,
855 	RTW89_TFC_MID,
856 	RTW89_TFC_HIGH,
857 };
858 
859 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
860 DECLARE_EWMA(tp, 10, 2);
861 
862 struct rtw89_traffic_stats {
863 	/* units in bytes */
864 	u64 tx_unicast;
865 	u64 rx_unicast;
866 	u32 tx_avg_len;
867 	u32 rx_avg_len;
868 
869 	/* count for packets */
870 	u64 tx_cnt;
871 	u64 rx_cnt;
872 
873 	/* units in Mbps */
874 	u32 tx_throughput;
875 	u32 rx_throughput;
876 	u32 tx_throughput_raw;
877 	u32 rx_throughput_raw;
878 	enum rtw89_tfc_lv tx_tfc_lv;
879 	enum rtw89_tfc_lv rx_tfc_lv;
880 	struct ewma_tp tx_ewma_tp;
881 	struct ewma_tp rx_ewma_tp;
882 
883 	u16 tx_rate;
884 	u16 rx_rate;
885 };
886 
887 struct rtw89_btc_statistic {
888 	u8 rssi; /* 0%~110% (dBm = rssi -110) */
889 	struct rtw89_traffic_stats traffic;
890 };
891 
892 #define BTC_WL_RSSI_THMAX 4
893 
894 struct rtw89_btc_wl_link_info {
895 	struct rtw89_btc_statistic stat;
896 	enum rtw89_tfc_dir dir;
897 	u8 rssi_state[BTC_WL_RSSI_THMAX];
898 	u8 mac_addr[ETH_ALEN];
899 	u8 busy;
900 	u8 ch;
901 	u8 bw;
902 	u8 band;
903 	u8 role;
904 	u8 pid;
905 	u8 phy;
906 	u8 dtim_period;
907 	u8 mode;
908 
909 	u8 mac_id;
910 	u8 tx_retry;
911 
912 	u32 bcn_period;
913 	u32 busy_t;
914 	u32 tx_time;
915 	u32 client_cnt;
916 	u32 rx_rate_drop_cnt;
917 
918 	u32 active: 1;
919 	u32 noa: 1;
920 	u32 client_ps: 1;
921 	u32 connected: 2;
922 };
923 
924 union rtw89_btc_wl_state_map {
925 	u32 val;
926 	struct rtw89_btc_wl_smap map;
927 };
928 
929 struct rtw89_btc_bt_hfp_desc {
930 	u32 exist: 1;
931 	u32 type: 2;
932 	u32 rsvd: 29;
933 };
934 
935 struct rtw89_btc_bt_hid_desc {
936 	u32 exist: 1;
937 	u32 slot_info: 2;
938 	u32 pair_cnt: 2;
939 	u32 type: 8;
940 	u32 rsvd: 19;
941 };
942 
943 struct rtw89_btc_bt_a2dp_desc {
944 	u8 exist: 1;
945 	u8 exist_last: 1;
946 	u8 play_latency: 1;
947 	u8 type: 3;
948 	u8 active: 1;
949 	u8 sink: 1;
950 
951 	u8 bitpool;
952 	u16 vendor_id;
953 	u32 device_name;
954 	u32 flush_time;
955 };
956 
957 struct rtw89_btc_bt_pan_desc {
958 	u32 exist: 1;
959 	u32 type: 1;
960 	u32 active: 1;
961 	u32 rsvd: 29;
962 };
963 
964 struct rtw89_btc_bt_rfk_info {
965 	u32 run: 1;
966 	u32 req: 1;
967 	u32 timeout: 1;
968 	u32 rsvd: 29;
969 };
970 
971 union rtw89_btc_bt_rfk_info_map {
972 	u32 val;
973 	struct rtw89_btc_bt_rfk_info map;
974 };
975 
976 struct rtw89_btc_bt_ver_info {
977 	u32 fw_coex; /* match with which coex_ver */
978 	u32 fw;
979 };
980 
981 struct rtw89_btc_bool_sta_chg {
982 	u32 now: 1;
983 	u32 last: 1;
984 	u32 remain: 1;
985 	u32 srvd: 29;
986 };
987 
988 struct rtw89_btc_u8_sta_chg {
989 	u8 now;
990 	u8 last;
991 	u8 remain;
992 	u8 rsvd;
993 };
994 
995 struct rtw89_btc_wl_scan_info {
996 	u8 band[RTW89_PHY_MAX];
997 	u8 phy_map;
998 	u8 rsvd;
999 };
1000 
1001 struct rtw89_btc_wl_dbcc_info {
1002 	u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1003 	u8 scan_band[RTW89_PHY_MAX]; /* scan band in  each phy */
1004 	u8 real_band[RTW89_PHY_MAX];
1005 	u8 role[RTW89_PHY_MAX]; /* role in each phy */
1006 };
1007 
1008 struct rtw89_btc_wl_active_role {
1009 	u8 connected: 1;
1010 	u8 pid: 3;
1011 	u8 phy: 1;
1012 	u8 noa: 1;
1013 	u8 band: 2;
1014 
1015 	u8 client_ps: 1;
1016 	u8 bw: 7;
1017 
1018 	u8 role;
1019 	u8 ch;
1020 
1021 	u16 tx_lvl;
1022 	u16 rx_lvl;
1023 	u16 tx_rate;
1024 	u16 rx_rate;
1025 };
1026 
1027 struct rtw89_btc_wl_role_info_bpos {
1028 	u16 none: 1;
1029 	u16 station: 1;
1030 	u16 ap: 1;
1031 	u16 vap: 1;
1032 	u16 adhoc: 1;
1033 	u16 adhoc_master: 1;
1034 	u16 mesh: 1;
1035 	u16 moniter: 1;
1036 	u16 p2p_device: 1;
1037 	u16 p2p_gc: 1;
1038 	u16 p2p_go: 1;
1039 	u16 nan: 1;
1040 };
1041 
1042 union rtw89_btc_wl_role_info_map {
1043 	u16 val;
1044 	struct rtw89_btc_wl_role_info_bpos role;
1045 };
1046 
1047 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1048 	u8 connect_cnt;
1049 	u8 link_mode;
1050 	union rtw89_btc_wl_role_info_map role_map;
1051 	struct rtw89_btc_wl_active_role active_role[RTW89_MAX_HW_PORT_NUM];
1052 };
1053 
1054 struct rtw89_btc_wl_ver_info {
1055 	u32 fw_coex; /* match with which coex_ver */
1056 	u32 fw;
1057 	u32 mac;
1058 	u32 bb;
1059 	u32 rf;
1060 };
1061 
1062 struct rtw89_btc_wl_afh_info {
1063 	u8 en;
1064 	u8 ch;
1065 	u8 bw;
1066 	u8 rsvd;
1067 } __packed;
1068 
1069 struct rtw89_btc_wl_rfk_info {
1070 	u32 state: 2;
1071 	u32 path_map: 4;
1072 	u32 phy_map: 2;
1073 	u32 band: 2;
1074 	u32 type: 8;
1075 	u32 rsvd: 14;
1076 };
1077 
1078 struct rtw89_btc_bt_smap {
1079 	u32 connect: 1;
1080 	u32 ble_connect: 1;
1081 	u32 acl_busy: 1;
1082 	u32 sco_busy: 1;
1083 	u32 mesh_busy: 1;
1084 	u32 inq_pag: 1;
1085 };
1086 
1087 union rtw89_btc_bt_state_map {
1088 	u32 val;
1089 	struct rtw89_btc_bt_smap map;
1090 };
1091 
1092 #define BTC_BT_RSSI_THMAX 4
1093 #define BTC_BT_AFH_GROUP 12
1094 
1095 struct rtw89_btc_bt_link_info {
1096 	struct rtw89_btc_u8_sta_chg profile_cnt;
1097 	struct rtw89_btc_bool_sta_chg multi_link;
1098 	struct rtw89_btc_bool_sta_chg relink;
1099 	struct rtw89_btc_bt_hfp_desc hfp_desc;
1100 	struct rtw89_btc_bt_hid_desc hid_desc;
1101 	struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1102 	struct rtw89_btc_bt_pan_desc pan_desc;
1103 	union rtw89_btc_bt_state_map status;
1104 
1105 	u8 sut_pwr_level[BTC_PROFILE_MAX];
1106 	u8 golden_rx_shift[BTC_PROFILE_MAX];
1107 	u8 rssi_state[BTC_BT_RSSI_THMAX];
1108 	u8 afh_map[BTC_BT_AFH_GROUP];
1109 
1110 	u32 role_sw: 1;
1111 	u32 slave_role: 1;
1112 	u32 afh_update: 1;
1113 	u32 cqddr: 1;
1114 	u32 rssi: 8;
1115 	u32 tx_3m: 1;
1116 	u32 rsvd: 19;
1117 };
1118 
1119 struct rtw89_btc_3rdcx_info {
1120 	u8 type;   /* 0: none, 1:zigbee, 2:LTE  */
1121 	u8 hw_coex;
1122 	u16 rsvd;
1123 };
1124 
1125 struct rtw89_btc_dm_emap {
1126 	u32 init: 1;
1127 	u32 pta_owner: 1;
1128 	u32 wl_rfk_timeout: 1;
1129 	u32 bt_rfk_timeout: 1;
1130 
1131 	u32 wl_fw_hang: 1;
1132 	u32 offload_mismatch: 1;
1133 	u32 cycle_hang: 1;
1134 	u32 w1_hang: 1;
1135 
1136 	u32 b1_hang: 1;
1137 	u32 tdma_no_sync: 1;
1138 	u32 wl_slot_drift: 1;
1139 };
1140 
1141 union rtw89_btc_dm_error_map {
1142 	u32 val;
1143 	struct rtw89_btc_dm_emap map;
1144 };
1145 
1146 struct rtw89_btc_rf_para {
1147 	u32 tx_pwr_freerun;
1148 	u32 rx_gain_freerun;
1149 	u32 tx_pwr_perpkt;
1150 	u32 rx_gain_perpkt;
1151 };
1152 
1153 struct rtw89_btc_wl_info {
1154 	struct rtw89_btc_wl_link_info link_info[RTW89_MAX_HW_PORT_NUM];
1155 	struct rtw89_btc_wl_rfk_info rfk_info;
1156 	struct rtw89_btc_wl_ver_info  ver_info;
1157 	struct rtw89_btc_wl_afh_info afh_info;
1158 	struct rtw89_btc_wl_role_info role_info;
1159 	struct rtw89_btc_wl_scan_info scan_info;
1160 	struct rtw89_btc_wl_dbcc_info dbcc_info;
1161 	struct rtw89_btc_rf_para rf_para;
1162 	union rtw89_btc_wl_state_map status;
1163 
1164 	u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1165 	u8 rssi_level;
1166 
1167 	u32 scbd;
1168 };
1169 
1170 struct rtw89_btc_module {
1171 	struct rtw89_btc_ant_info ant;
1172 	u8 rfe_type;
1173 	u8 cv;
1174 
1175 	u8 bt_solo: 1;
1176 	u8 bt_pos: 1;
1177 	u8 switch_type: 1;
1178 
1179 	u8 rsvd;
1180 };
1181 
1182 #define RTW89_BTC_DM_MAXSTEP 30
1183 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1184 
1185 struct rtw89_btc_dm_step {
1186 	u16 step[RTW89_BTC_DM_MAXSTEP];
1187 	u8 step_pos;
1188 	bool step_ov;
1189 };
1190 
1191 struct rtw89_btc_init_info {
1192 	struct rtw89_btc_module module;
1193 	u8 wl_guard_ch;
1194 
1195 	u8 wl_only: 1;
1196 	u8 wl_init_ok: 1;
1197 	u8 dbcc_en: 1;
1198 	u8 cx_other: 1;
1199 	u8 bt_only: 1;
1200 
1201 	u16 rsvd;
1202 };
1203 
1204 struct rtw89_btc_wl_tx_limit_para {
1205 	u16 enable;
1206 	u32 tx_time;	/* unit: us */
1207 	u16 tx_retry;
1208 };
1209 
1210 struct rtw89_btc_bt_scan_info {
1211 	u16 win;
1212 	u16 intvl;
1213 	u32 enable: 1;
1214 	u32 interlace: 1;
1215 	u32 rsvd: 30;
1216 };
1217 
1218 enum rtw89_btc_bt_scan_type {
1219 	BTC_SCAN_INQ	= 0,
1220 	BTC_SCAN_PAGE,
1221 	BTC_SCAN_BLE,
1222 	BTC_SCAN_INIT,
1223 	BTC_SCAN_TV,
1224 	BTC_SCAN_ADV,
1225 	BTC_SCAN_MAX1,
1226 };
1227 
1228 struct rtw89_btc_bt_info {
1229 	struct rtw89_btc_bt_link_info link_info;
1230 	struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1];
1231 	struct rtw89_btc_bt_ver_info ver_info;
1232 	struct rtw89_btc_bool_sta_chg enable;
1233 	struct rtw89_btc_bool_sta_chg inq_pag;
1234 	struct rtw89_btc_rf_para rf_para;
1235 	union rtw89_btc_bt_rfk_info_map rfk_info;
1236 
1237 	u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1238 
1239 	u32 scbd;
1240 	u32 feature;
1241 
1242 	u32 mbx_avl: 1;
1243 	u32 whql_test: 1;
1244 	u32 igno_wl: 1;
1245 	u32 reinit: 1;
1246 	u32 ble_scan_en: 1;
1247 	u32 btg_type: 1;
1248 	u32 inq: 1;
1249 	u32 pag: 1;
1250 	u32 run_patch_code: 1;
1251 	u32 hi_lna_rx: 1;
1252 	u32 rsvd: 22;
1253 };
1254 
1255 struct rtw89_btc_cx {
1256 	struct rtw89_btc_wl_info wl;
1257 	struct rtw89_btc_bt_info bt;
1258 	struct rtw89_btc_3rdcx_info other;
1259 	u32 state_map;
1260 	u32 cnt_bt[BTC_BCNT_NUM];
1261 	u32 cnt_wl[BTC_WCNT_NUM];
1262 };
1263 
1264 struct rtw89_btc_fbtc_tdma {
1265 	u8 type;
1266 	u8 rxflctrl;
1267 	u8 txpause;
1268 	u8 wtgle_n;
1269 	u8 leak_n;
1270 	u8 ext_ctrl;
1271 	u8 rsvd0;
1272 	u8 rsvd1;
1273 } __packed;
1274 
1275 #define CXMREG_MAX 30
1276 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1277 #define BTCRPT_VER 1
1278 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1279 
1280 enum rtw89_btc_bt_rfk_counter {
1281 	BTC_BCNT_RFK_REQ = 0,
1282 	BTC_BCNT_RFK_GO = 1,
1283 	BTC_BCNT_RFK_REJECT = 2,
1284 	BTC_BCNT_RFK_FAIL = 3,
1285 	BTC_BCNT_RFK_TIMEOUT = 4,
1286 	BTC_BCNT_RFK_MAX
1287 };
1288 
1289 struct rtw89_btc_fbtc_rpt_ctrl {
1290 	u16 fver;
1291 	u16 rpt_cnt; /* tmr counters */
1292 	u32 wl_fw_coex_ver; /* match which driver's coex version */
1293 	u32 wl_fw_cx_offload;
1294 	u32 wl_fw_ver;
1295 	u32 rpt_enable;
1296 	u32 rpt_para; /* ms */
1297 	u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1298 	u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1299 	u32 mb_recv_cnt; /* fw recv mailbox counter */
1300 	u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1301 	u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1302 	u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1303 	u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX];
1304 	u32 c2h_cnt; /* fw send c2h counter  */
1305 	u32 h2c_cnt; /* fw recv h2c counter */
1306 } __packed;
1307 
1308 enum rtw89_fbtc_ext_ctrl_type {
1309 	CXECTL_OFF = 0x0, /* tdma off */
1310 	CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
1311 	CXECTL_EXT = 0x2,
1312 	CXECTL_MAX
1313 };
1314 
1315 union rtw89_btc_fbtc_rxflct {
1316 	u8 val;
1317 	u8 type: 3;
1318 	u8 tgln_n: 5;
1319 };
1320 
1321 enum rtw89_btc_cxst_state {
1322 	CXST_OFF = 0x0,
1323 	CXST_B2W = 0x1,
1324 	CXST_W1 = 0x2,
1325 	CXST_W2 = 0x3,
1326 	CXST_W2B = 0x4,
1327 	CXST_B1 = 0x5,
1328 	CXST_B2 = 0x6,
1329 	CXST_B3 = 0x7,
1330 	CXST_B4 = 0x8,
1331 	CXST_LK = 0x9,
1332 	CXST_BLK = 0xa,
1333 	CXST_E2G = 0xb,
1334 	CXST_E5G = 0xc,
1335 	CXST_EBT = 0xd,
1336 	CXST_ENULL = 0xe,
1337 	CXST_WLK = 0xf,
1338 	CXST_W1FDD = 0x10,
1339 	CXST_B1FDD = 0x11,
1340 	CXST_MAX = 0x12,
1341 };
1342 
1343 enum {
1344 	CXBCN_ALL = 0x0,
1345 	CXBCN_ALL_OK,
1346 	CXBCN_BT_SLOT,
1347 	CXBCN_BT_OK,
1348 	CXBCN_MAX
1349 };
1350 
1351 enum btc_slot_type {
1352 	SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
1353 	SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
1354 	CXSTYPE_NUM,
1355 };
1356 
1357 enum { /* TIME */
1358 	CXT_BT = 0x0,
1359 	CXT_WL = 0x1,
1360 	CXT_MAX
1361 };
1362 
1363 enum { /* TIME-A2DP */
1364 	CXT_FLCTRL_OFF = 0x0,
1365 	CXT_FLCTRL_ON = 0x1,
1366 	CXT_FLCTRL_MAX
1367 };
1368 
1369 enum { /* STEP TYPE */
1370 	CXSTEP_NONE = 0x0,
1371 	CXSTEP_EVNT = 0x1,
1372 	CXSTEP_SLOT = 0x2,
1373 	CXSTEP_MAX,
1374 };
1375 
1376 #define FCXGPIODBG_VER 1
1377 #define BTC_DBG_MAX1  32
1378 struct rtw89_btc_fbtc_gpio_dbg {
1379 	u8 fver;
1380 	u8 rsvd;
1381 	u16 rsvd2;
1382 	u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
1383 	u32 pre_state; /* the debug signal is 1 or 0  */
1384 	u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
1385 } __packed;
1386 
1387 #define FCXMREG_VER 1
1388 struct rtw89_btc_fbtc_mreg_val {
1389 	u8 fver;
1390 	u8 reg_num;
1391 	__le16 rsvd;
1392 	__le32 mreg_val[CXMREG_MAX];
1393 } __packed;
1394 
1395 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
1396 	{ .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
1397 	  .offset = cpu_to_le32(__offset), }
1398 
1399 struct rtw89_btc_fbtc_mreg {
1400 	__le16 type;
1401 	__le16 bytes;
1402 	__le32 offset;
1403 } __packed;
1404 
1405 struct rtw89_btc_fbtc_slot {
1406 	__le16 dur;
1407 	__le32 cxtbl;
1408 	__le16 cxtype;
1409 } __packed;
1410 
1411 #define FCXSLOTS_VER 1
1412 struct rtw89_btc_fbtc_slots {
1413 	u8 fver;
1414 	u8 tbl_num;
1415 	__le16 rsvd;
1416 	__le32 update_map;
1417 	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1418 } __packed;
1419 
1420 #define FCXSTEP_VER 2
1421 struct rtw89_btc_fbtc_step {
1422 	u8 type;
1423 	u8 val;
1424 	__le16 difft;
1425 } __packed;
1426 
1427 struct rtw89_btc_fbtc_steps {
1428 	u8 fver;
1429 	u8 rsvd;
1430 	__le16 cnt;
1431 	__le16 pos_old;
1432 	__le16 pos_new;
1433 	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
1434 } __packed;
1435 
1436 #define FCXCYSTA_VER 2
1437 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */
1438 	u8 fver;
1439 	u8 rsvd;
1440 	__le16 cycles; /* total cycle number */
1441 	__le16 cycles_a2dp[CXT_FLCTRL_MAX];
1442 	__le16 a2dpept; /* a2dp empty cnt */
1443 	__le16 a2dpeptto; /* a2dp empty timeout cnt*/
1444 	__le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
1445 	__le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
1446 	__le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
1447 	__le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
1448 	__le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
1449 	__le16 tavg_a2dpept; /* avg a2dp empty time */
1450 	__le16 tmax_a2dpept; /* max a2dp empty time */
1451 	__le16 tavg_lk; /* avg leak-slot time */
1452 	__le16 tmax_lk; /* max leak-slot time */
1453 	__le32 slot_cnt[CXST_MAX]; /* slot count */
1454 	__le32 bcn_cnt[CXBCN_MAX];
1455 	__le32 leakrx_cnt; /* the rximr occur at leak slot  */
1456 	__le32 collision_cnt; /* counter for event/timer occur at same time */
1457 	__le32 skip_cnt;
1458 	__le32 exception;
1459 	__le32 except_cnt;
1460 	__le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
1461 } __packed;
1462 
1463 #define FCXNULLSTA_VER 1
1464 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */
1465 	u8 fver;
1466 	u8 rsvd;
1467 	__le16 rsvd2;
1468 	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
1469 	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
1470 	__le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
1471 } __packed;
1472 
1473 #define FCX_BTVER_VER 1
1474 struct rtw89_btc_fbtc_btver {
1475 	u8 fver;
1476 	u8 rsvd;
1477 	__le16 rsvd2;
1478 	__le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
1479 	__le32 fw_ver;
1480 	__le32 feature;
1481 } __packed;
1482 
1483 #define FCX_BTSCAN_VER 1
1484 struct rtw89_btc_fbtc_btscan {
1485 	u8 fver;
1486 	u8 rsvd;
1487 	__le16 rsvd2;
1488 	u8 scan[6];
1489 } __packed;
1490 
1491 #define FCX_BTAFH_VER 1
1492 struct rtw89_btc_fbtc_btafh {
1493 	u8 fver;
1494 	u8 rsvd;
1495 	__le16 rsvd2;
1496 	u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
1497 	u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
1498 	u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
1499 } __packed;
1500 
1501 #define FCX_BTDEVINFO_VER 1
1502 struct rtw89_btc_fbtc_btdevinfo {
1503 	u8 fver;
1504 	u8 rsvd;
1505 	__le16 vendor_id;
1506 	__le32 dev_name; /* only 24 bits valid */
1507 	__le32 flush_time;
1508 } __packed;
1509 
1510 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
1511 struct rtw89_btc_rf_trx_para {
1512 	u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
1513 	u32 wl_rx_gain;  /* rx gain table index (TBD.) */
1514 	u8 bt_tx_power; /* decrease Tx power (dB) */
1515 	u8 bt_rx_gain;  /* LNA constrain level */
1516 };
1517 
1518 struct rtw89_btc_dm {
1519 	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1520 	struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
1521 	struct rtw89_btc_fbtc_tdma tdma;
1522 	struct rtw89_btc_fbtc_tdma tdma_now;
1523 	struct rtw89_mac_ax_coex_gnt gnt;
1524 	struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
1525 	struct rtw89_btc_rf_trx_para rf_trx_para;
1526 	struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
1527 	struct rtw89_btc_dm_step dm_step;
1528 	union rtw89_btc_dm_error_map error;
1529 	u32 cnt_dm[BTC_DCNT_NUM];
1530 	u32 cnt_notify[BTC_NCNT_NUM];
1531 
1532 	u32 update_slot_map;
1533 	u32 set_ant_path;
1534 
1535 	u32 wl_only: 1;
1536 	u32 wl_fw_cx_offload: 1;
1537 	u32 freerun: 1;
1538 	u32 wl_ps_ctrl: 2;
1539 	u32 wl_mimo_ps: 1;
1540 	u32 leak_ap: 1;
1541 	u32 noisy_level: 3;
1542 	u32 coex_info_map: 8;
1543 	u32 bt_only: 1;
1544 	u32 wl_btg_rx: 1;
1545 	u32 trx_para_level: 8;
1546 	u32 wl_stb_chg: 1;
1547 	u32 rsvd: 3;
1548 
1549 	u16 slot_dur[CXST_MAX];
1550 
1551 	u8 run_reason;
1552 	u8 run_action;
1553 };
1554 
1555 struct rtw89_btc_ctrl {
1556 	u32 manual: 1;
1557 	u32 igno_bt: 1;
1558 	u32 always_freerun: 1;
1559 	u32 trace_step: 16;
1560 	u32 rsvd: 12;
1561 };
1562 
1563 struct rtw89_btc_dbg {
1564 	/* cmd "rb" */
1565 	bool rb_done;
1566 	u32 rb_val;
1567 };
1568 
1569 #define FCXTDMA_VER 1
1570 
1571 enum rtw89_btc_btf_fw_event {
1572 	BTF_EVNT_RPT = 0,
1573 	BTF_EVNT_BT_INFO = 1,
1574 	BTF_EVNT_BT_SCBD = 2,
1575 	BTF_EVNT_BT_REG = 3,
1576 	BTF_EVNT_CX_RUNINFO = 4,
1577 	BTF_EVNT_BT_PSD = 5,
1578 	BTF_EVNT_BUF_OVERFLOW,
1579 	BTF_EVNT_C2H_LOOPBACK,
1580 	BTF_EVNT_MAX,
1581 };
1582 
1583 enum btf_fw_event_report {
1584 	BTC_RPT_TYPE_CTRL = 0x0,
1585 	BTC_RPT_TYPE_TDMA,
1586 	BTC_RPT_TYPE_SLOT,
1587 	BTC_RPT_TYPE_CYSTA,
1588 	BTC_RPT_TYPE_STEP,
1589 	BTC_RPT_TYPE_NULLSTA,
1590 	BTC_RPT_TYPE_MREG,
1591 	BTC_RPT_TYPE_GPIO_DBG,
1592 	BTC_RPT_TYPE_BT_VER,
1593 	BTC_RPT_TYPE_BT_SCAN,
1594 	BTC_RPT_TYPE_BT_AFH,
1595 	BTC_RPT_TYPE_BT_DEVICE,
1596 	BTC_RPT_TYPE_TEST,
1597 	BTC_RPT_TYPE_MAX = 31
1598 };
1599 
1600 enum rtw_btc_btf_reg_type {
1601 	REG_MAC = 0x0,
1602 	REG_BB = 0x1,
1603 	REG_RF = 0x2,
1604 	REG_BT_RF = 0x3,
1605 	REG_BT_MODEM = 0x4,
1606 	REG_BT_BLUEWIZE = 0x5,
1607 	REG_BT_VENDOR = 0x6,
1608 	REG_BT_LE = 0x7,
1609 	REG_MAX_TYPE,
1610 };
1611 
1612 struct rtw89_btc_rpt_cmn_info {
1613 	u32 rx_cnt;
1614 	u32 rx_len;
1615 	u32 req_len; /* expected rsp len */
1616 	u8 req_fver; /* expected rsp fver */
1617 	u8 rsp_fver; /* fver from fw */
1618 	u8 valid;
1619 } __packed;
1620 
1621 struct rtw89_btc_report_ctrl_state {
1622 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1623 	struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */
1624 };
1625 
1626 struct rtw89_btc_rpt_fbtc_tdma {
1627 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1628 	struct rtw89_btc_fbtc_tdma finfo; /* info from fw */
1629 };
1630 
1631 struct rtw89_btc_rpt_fbtc_slots {
1632 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1633 	struct rtw89_btc_fbtc_slots finfo; /* info from fw */
1634 };
1635 
1636 struct rtw89_btc_rpt_fbtc_cysta {
1637 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1638 	struct rtw89_btc_fbtc_cysta finfo; /* info from fw */
1639 };
1640 
1641 struct rtw89_btc_rpt_fbtc_step {
1642 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1643 	struct rtw89_btc_fbtc_steps finfo; /* info from fw */
1644 };
1645 
1646 struct rtw89_btc_rpt_fbtc_nullsta {
1647 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1648 	struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */
1649 };
1650 
1651 struct rtw89_btc_rpt_fbtc_mreg {
1652 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1653 	struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
1654 };
1655 
1656 struct rtw89_btc_rpt_fbtc_gpio_dbg {
1657 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1658 	struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
1659 };
1660 
1661 struct rtw89_btc_rpt_fbtc_btver {
1662 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1663 	struct rtw89_btc_fbtc_btver finfo; /* info from fw */
1664 };
1665 
1666 struct rtw89_btc_rpt_fbtc_btscan {
1667 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1668 	struct rtw89_btc_fbtc_btscan finfo; /* info from fw */
1669 };
1670 
1671 struct rtw89_btc_rpt_fbtc_btafh {
1672 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1673 	struct rtw89_btc_fbtc_btafh finfo; /* info from fw */
1674 };
1675 
1676 struct rtw89_btc_rpt_fbtc_btdev {
1677 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1678 	struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
1679 };
1680 
1681 enum rtw89_btc_btfre_type {
1682 	BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
1683 	BTFRE_UNDEF_TYPE,
1684 	BTFRE_EXCEPTION,
1685 	BTFRE_MAX,
1686 };
1687 
1688 struct rtw89_btc_btf_fwinfo {
1689 	u32 cnt_c2h;
1690 	u32 cnt_h2c;
1691 	u32 cnt_h2c_fail;
1692 	u32 event[BTF_EVNT_MAX];
1693 
1694 	u32 err[BTFRE_MAX];
1695 	u32 len_mismch;
1696 	u32 fver_mismch;
1697 	u32 rpt_en_map;
1698 
1699 	struct rtw89_btc_report_ctrl_state rpt_ctrl;
1700 	struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
1701 	struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
1702 	struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
1703 	struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
1704 	struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
1705 	struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
1706 	struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
1707 	struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
1708 	struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
1709 	struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
1710 	struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
1711 };
1712 
1713 #define RTW89_BTC_POLICY_MAXLEN 512
1714 
1715 struct rtw89_btc {
1716 	struct rtw89_btc_cx cx;
1717 	struct rtw89_btc_dm dm;
1718 	struct rtw89_btc_ctrl ctrl;
1719 	struct rtw89_btc_module mdinfo;
1720 	struct rtw89_btc_btf_fwinfo fwinfo;
1721 	struct rtw89_btc_dbg dbg;
1722 
1723 	struct work_struct eapol_notify_work;
1724 	struct work_struct arp_notify_work;
1725 	struct work_struct dhcp_notify_work;
1726 	struct work_struct icmp_notify_work;
1727 
1728 	u32 bt_req_len;
1729 
1730 	u8 policy[RTW89_BTC_POLICY_MAXLEN];
1731 	u16 policy_len;
1732 	u16 policy_type;
1733 	bool bt_req_en;
1734 	bool update_policy_force;
1735 	bool lps;
1736 };
1737 
1738 enum rtw89_ra_mode {
1739 	RTW89_RA_MODE_CCK = BIT(0),
1740 	RTW89_RA_MODE_OFDM = BIT(1),
1741 	RTW89_RA_MODE_HT = BIT(2),
1742 	RTW89_RA_MODE_VHT = BIT(3),
1743 	RTW89_RA_MODE_HE = BIT(4),
1744 };
1745 
1746 enum rtw89_ra_report_mode {
1747 	RTW89_RA_RPT_MODE_LEGACY,
1748 	RTW89_RA_RPT_MODE_HT,
1749 	RTW89_RA_RPT_MODE_VHT,
1750 	RTW89_RA_RPT_MODE_HE,
1751 };
1752 
1753 enum rtw89_dig_noisy_level {
1754 	RTW89_DIG_NOISY_LEVEL0 = -1,
1755 	RTW89_DIG_NOISY_LEVEL1 = 0,
1756 	RTW89_DIG_NOISY_LEVEL2 = 1,
1757 	RTW89_DIG_NOISY_LEVEL3 = 2,
1758 	RTW89_DIG_NOISY_LEVEL_MAX = 3,
1759 };
1760 
1761 enum rtw89_gi_ltf {
1762 	RTW89_GILTF_LGI_4XHE32 = 0,
1763 	RTW89_GILTF_SGI_4XHE08 = 1,
1764 	RTW89_GILTF_2XHE16 = 2,
1765 	RTW89_GILTF_2XHE08 = 3,
1766 	RTW89_GILTF_1XHE16 = 4,
1767 	RTW89_GILTF_1XHE08 = 5,
1768 	RTW89_GILTF_MAX
1769 };
1770 
1771 enum rtw89_rx_frame_type {
1772 	RTW89_RX_TYPE_MGNT = 0,
1773 	RTW89_RX_TYPE_CTRL = 1,
1774 	RTW89_RX_TYPE_DATA = 2,
1775 	RTW89_RX_TYPE_RSVD = 3,
1776 };
1777 
1778 struct rtw89_ra_info {
1779 	u8 is_dis_ra:1;
1780 	/* Bit0 : CCK
1781 	 * Bit1 : OFDM
1782 	 * Bit2 : HT
1783 	 * Bit3 : VHT
1784 	 * Bit4 : HE
1785 	 */
1786 	u8 mode_ctrl:5;
1787 	u8 bw_cap:2;
1788 	u8 macid;
1789 	u8 dcm_cap:1;
1790 	u8 er_cap:1;
1791 	u8 init_rate_lv:2;
1792 	u8 upd_all:1;
1793 	u8 en_sgi:1;
1794 	u8 ldpc_cap:1;
1795 	u8 stbc_cap:1;
1796 	u8 ss_num:3;
1797 	u8 giltf:3;
1798 	u8 upd_bw_nss_mask:1;
1799 	u8 upd_mask:1;
1800 	u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
1801 	/* BFee CSI */
1802 	u8 band_num;
1803 	u8 ra_csi_rate_en:1;
1804 	u8 fixed_csi_rate_en:1;
1805 	u8 cr_tbl_sel:1;
1806 	u8 rsvd2:5;
1807 	u8 csi_mcs_ss_idx;
1808 	u8 csi_mode:2;
1809 	u8 csi_gi_ltf:3;
1810 	u8 csi_bw:3;
1811 };
1812 
1813 #define RTW89_PPDU_MAX_USR 4
1814 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
1815 #define RTW89_PPDU_MAC_INFO_SIZE 8
1816 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
1817 
1818 #define RTW89_MAX_RX_AGG_NUM 64
1819 #define RTW89_MAX_TX_AGG_NUM 128
1820 
1821 struct rtw89_ampdu_params {
1822 	u16 agg_num;
1823 	bool amsdu;
1824 };
1825 
1826 struct rtw89_ra_report {
1827 	struct rate_info txrate;
1828 	u32 bit_rate;
1829 	u16 hw_rate;
1830 };
1831 
1832 DECLARE_EWMA(rssi, 10, 16);
1833 
1834 struct rtw89_sta {
1835 	u8 mac_id;
1836 	bool disassoc;
1837 	struct rtw89_vif *rtwvif;
1838 	struct rtw89_ra_info ra;
1839 	struct rtw89_ra_report ra_report;
1840 	int max_agg_wait;
1841 	u8 prev_rssi;
1842 	struct ewma_rssi avg_rssi;
1843 	struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
1844 	struct ieee80211_rx_status rx_status;
1845 	u16 rx_hw_rate;
1846 	__le32 htc_template;
1847 
1848 	bool use_cfg_mask;
1849 	struct cfg80211_bitrate_mask mask;
1850 
1851 	bool cctl_tx_time;
1852 	u32 ampdu_max_time:4;
1853 	bool cctl_tx_retry_limit;
1854 	u32 data_tx_cnt_lmt:6;
1855 };
1856 
1857 #define RTW89_MAX_ADDR_CAM_NUM		128
1858 #define RTW89_MAX_BSSID_CAM_NUM		20
1859 #define RTW89_MAX_SEC_CAM_NUM		128
1860 #define RTW89_SEC_CAM_IN_ADDR_CAM	7
1861 
1862 struct rtw89_addr_cam_entry {
1863 	u8 addr_cam_idx;
1864 	u8 offset;
1865 	u8 len;
1866 	u8 valid	: 1;
1867 	u8 addr_mask	: 6;
1868 	u8 wapi		: 1;
1869 	u8 mask_sel	: 2;
1870 	u8 bssid_cam_idx: 6;
1871 	u8 sma[ETH_ALEN];
1872 
1873 	u8 sec_ent_mode;
1874 	DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
1875 	u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
1876 	u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
1877 	struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
1878 };
1879 
1880 struct rtw89_bssid_cam_entry {
1881 	u8 bssid[ETH_ALEN];
1882 	u8 phy_idx;
1883 	u8 bssid_cam_idx;
1884 	u8 offset;
1885 	u8 len;
1886 	u8 valid : 1;
1887 	u8 num;
1888 };
1889 
1890 struct rtw89_sec_cam_entry {
1891 	u8 sec_cam_idx;
1892 	u8 offset;
1893 	u8 len;
1894 	u8 type : 4;
1895 	u8 ext_key : 1;
1896 	u8 spp_mode : 1;
1897 	/* 256 bits */
1898 	u8 key[32];
1899 };
1900 
1901 struct rtw89_efuse {
1902 	bool valid;
1903 	u8 xtal_cap;
1904 	u8 addr[ETH_ALEN];
1905 	u8 rfe_type;
1906 	char country_code[2];
1907 };
1908 
1909 struct rtw89_phy_rate_pattern {
1910 	u64 ra_mask;
1911 	u16 rate;
1912 	u8 ra_mode;
1913 	bool enable;
1914 };
1915 
1916 struct rtw89_vif {
1917 	struct list_head list;
1918 	u8 mac_id;
1919 	u8 port;
1920 	u8 mac_addr[ETH_ALEN];
1921 	u8 bssid[ETH_ALEN];
1922 	u8 phy_idx;
1923 	u8 mac_idx;
1924 	u8 net_type;
1925 	u8 wifi_role;
1926 	u8 self_role;
1927 	u8 wmm;
1928 	u8 bcn_hit_cond;
1929 	u8 hit_rule;
1930 	bool trigger;
1931 	bool lsig_txop;
1932 	u8 tgt_ind;
1933 	u8 frm_tgt_ind;
1934 	bool wowlan_pattern;
1935 	bool wowlan_uc;
1936 	bool wowlan_magic;
1937 	bool is_hesta;
1938 	bool last_a_ctrl;
1939 	struct rtw89_addr_cam_entry addr_cam;
1940 	struct rtw89_bssid_cam_entry bssid_cam;
1941 	struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
1942 	struct rtw89_traffic_stats stats;
1943 	struct rtw89_phy_rate_pattern rate_pattern;
1944 };
1945 
1946 enum rtw89_lv1_rcvy_step {
1947 	RTW89_LV1_RCVY_STEP_1,
1948 	RTW89_LV1_RCVY_STEP_2,
1949 };
1950 
1951 struct rtw89_hci_ops {
1952 	int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
1953 	void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
1954 	void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1955 	void (*reset)(struct rtw89_dev *rtwdev);
1956 	int (*start)(struct rtw89_dev *rtwdev);
1957 	void (*stop)(struct rtw89_dev *rtwdev);
1958 	void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
1959 
1960 	u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
1961 	u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
1962 	u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
1963 	void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
1964 	void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
1965 	void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
1966 
1967 	int (*mac_pre_init)(struct rtw89_dev *rtwdev);
1968 	int (*mac_post_init)(struct rtw89_dev *rtwdev);
1969 	int (*deinit)(struct rtw89_dev *rtwdev);
1970 
1971 	u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
1972 	int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
1973 	void (*dump_err_status)(struct rtw89_dev *rtwdev);
1974 	int (*napi_poll)(struct napi_struct *napi, int budget);
1975 };
1976 
1977 struct rtw89_hci_info {
1978 	const struct rtw89_hci_ops *ops;
1979 	enum rtw89_hci_type type;
1980 	u32 rpwm_addr;
1981 	u32 cpwm_addr;
1982 };
1983 
1984 struct rtw89_chip_ops {
1985 	void (*bb_reset)(struct rtw89_dev *rtwdev,
1986 			 enum rtw89_phy_idx phy_idx);
1987 	void (*bb_sethw)(struct rtw89_dev *rtwdev);
1988 	u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1989 		       u32 addr, u32 mask);
1990 	bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1991 			 u32 addr, u32 mask, u32 data);
1992 	void (*set_channel)(struct rtw89_dev *rtwdev,
1993 			    struct rtw89_channel_params *param);
1994 	void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
1995 				 struct rtw89_channel_help_params *p);
1996 	int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
1997 	int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
1998 	void (*fem_setup)(struct rtw89_dev *rtwdev);
1999 	void (*rfk_init)(struct rtw89_dev *rtwdev);
2000 	void (*rfk_channel)(struct rtw89_dev *rtwdev);
2001 	void (*rfk_band_changed)(struct rtw89_dev *rtwdev);
2002 	void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
2003 	void (*rfk_track)(struct rtw89_dev *rtwdev);
2004 	void (*power_trim)(struct rtw89_dev *rtwdev);
2005 	void (*set_txpwr)(struct rtw89_dev *rtwdev);
2006 	void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev);
2007 	int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
2008 	u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
2009 	void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);
2010 	void (*query_ppdu)(struct rtw89_dev *rtwdev,
2011 			   struct rtw89_rx_phy_ppdu *phy_ppdu,
2012 			   struct ieee80211_rx_status *status);
2013 	void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);
2014 	void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
2015 				       s16 pw_ofst, enum rtw89_mac_idx mac_idx);
2016 
2017 	void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
2018 	void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
2019 	void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
2020 	void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
2021 	s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
2022 	void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev);
2023 	void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
2024 	void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
2025 };
2026 
2027 enum rtw89_dma_ch {
2028 	RTW89_DMA_ACH0 = 0,
2029 	RTW89_DMA_ACH1 = 1,
2030 	RTW89_DMA_ACH2 = 2,
2031 	RTW89_DMA_ACH3 = 3,
2032 	RTW89_DMA_ACH4 = 4,
2033 	RTW89_DMA_ACH5 = 5,
2034 	RTW89_DMA_ACH6 = 6,
2035 	RTW89_DMA_ACH7 = 7,
2036 	RTW89_DMA_B0MG = 8,
2037 	RTW89_DMA_B0HI = 9,
2038 	RTW89_DMA_B1MG = 10,
2039 	RTW89_DMA_B1HI = 11,
2040 	RTW89_DMA_H2C = 12,
2041 	RTW89_DMA_CH_NUM = 13
2042 };
2043 
2044 enum rtw89_qta_mode {
2045 	RTW89_QTA_SCC,
2046 	RTW89_QTA_DLFW,
2047 
2048 	/* keep last */
2049 	RTW89_QTA_INVALID,
2050 };
2051 
2052 struct rtw89_hfc_ch_cfg {
2053 	u16 min;
2054 	u16 max;
2055 #define grp_0 0
2056 #define grp_1 1
2057 #define grp_num 2
2058 	u8 grp;
2059 };
2060 
2061 struct rtw89_hfc_ch_info {
2062 	u16 aval;
2063 	u16 used;
2064 };
2065 
2066 struct rtw89_hfc_pub_cfg {
2067 	u16 grp0;
2068 	u16 grp1;
2069 	u16 pub_max;
2070 	u16 wp_thrd;
2071 };
2072 
2073 struct rtw89_hfc_pub_info {
2074 	u16 g0_used;
2075 	u16 g1_used;
2076 	u16 g0_aval;
2077 	u16 g1_aval;
2078 	u16 pub_aval;
2079 	u16 wp_aval;
2080 };
2081 
2082 struct rtw89_hfc_prec_cfg {
2083 	u16 ch011_prec;
2084 	u16 h2c_prec;
2085 	u16 wp_ch07_prec;
2086 	u16 wp_ch811_prec;
2087 	u8 ch011_full_cond;
2088 	u8 h2c_full_cond;
2089 	u8 wp_ch07_full_cond;
2090 	u8 wp_ch811_full_cond;
2091 };
2092 
2093 struct rtw89_hfc_param {
2094 	bool en;
2095 	bool h2c_en;
2096 	u8 mode;
2097 	const struct rtw89_hfc_ch_cfg *ch_cfg;
2098 	struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
2099 	struct rtw89_hfc_pub_cfg pub_cfg;
2100 	struct rtw89_hfc_pub_info pub_info;
2101 	struct rtw89_hfc_prec_cfg prec_cfg;
2102 };
2103 
2104 struct rtw89_hfc_param_ini {
2105 	const struct rtw89_hfc_ch_cfg *ch_cfg;
2106 	const struct rtw89_hfc_pub_cfg *pub_cfg;
2107 	const struct rtw89_hfc_prec_cfg *prec_cfg;
2108 	u8 mode;
2109 };
2110 
2111 struct rtw89_dle_size {
2112 	u16 pge_size;
2113 	u16 lnk_pge_num;
2114 	u16 unlnk_pge_num;
2115 };
2116 
2117 struct rtw89_wde_quota {
2118 	u16 hif;
2119 	u16 wcpu;
2120 	u16 pkt_in;
2121 	u16 cpu_io;
2122 };
2123 
2124 struct rtw89_ple_quota {
2125 	u16 cma0_tx;
2126 	u16 cma1_tx;
2127 	u16 c2h;
2128 	u16 h2c;
2129 	u16 wcpu;
2130 	u16 mpdu_proc;
2131 	u16 cma0_dma;
2132 	u16 cma1_dma;
2133 	u16 bb_rpt;
2134 	u16 wd_rel;
2135 	u16 cpu_io;
2136 };
2137 
2138 struct rtw89_dle_mem {
2139 	enum rtw89_qta_mode mode;
2140 	const struct rtw89_dle_size *wde_size;
2141 	const struct rtw89_dle_size *ple_size;
2142 	const struct rtw89_wde_quota *wde_min_qt;
2143 	const struct rtw89_wde_quota *wde_max_qt;
2144 	const struct rtw89_ple_quota *ple_min_qt;
2145 	const struct rtw89_ple_quota *ple_max_qt;
2146 };
2147 
2148 struct rtw89_reg_def {
2149 	u32 addr;
2150 	u32 mask;
2151 };
2152 
2153 struct rtw89_reg2_def {
2154 	u32 addr;
2155 	u32 data;
2156 };
2157 
2158 struct rtw89_reg3_def {
2159 	u32 addr;
2160 	u32 mask;
2161 	u32 data;
2162 };
2163 
2164 struct rtw89_reg5_def {
2165 	u8 flag; /* recognized by parsers */
2166 	u8 path;
2167 	u32 addr;
2168 	u32 mask;
2169 	u32 data;
2170 };
2171 
2172 struct rtw89_phy_table {
2173 	const struct rtw89_reg2_def *regs;
2174 	u32 n_regs;
2175 	enum rtw89_rf_path rf_path;
2176 };
2177 
2178 struct rtw89_txpwr_table {
2179 	const void *data;
2180 	u32 size;
2181 	void (*load)(struct rtw89_dev *rtwdev,
2182 		     const struct rtw89_txpwr_table *tbl);
2183 };
2184 
2185 struct rtw89_chip_info {
2186 	enum rtw89_core_chip_id chip_id;
2187 	const struct rtw89_chip_ops *ops;
2188 	const char *fw_name;
2189 	u32 fifo_size;
2190 	u16 max_amsdu_limit;
2191 	bool dis_2g_40m_ul_ofdma;
2192 	const struct rtw89_hfc_param_ini *hfc_param_ini;
2193 	const struct rtw89_dle_mem *dle_mem;
2194 	u32 rf_base_addr[2];
2195 	u8 rf_path_num;
2196 	u8 tx_nss;
2197 	u8 rx_nss;
2198 	u8 acam_num;
2199 	u8 bcam_num;
2200 	u8 scam_num;
2201 
2202 	u8 sec_ctrl_efuse_size;
2203 	u32 physical_efuse_size;
2204 	u32 logical_efuse_size;
2205 	u32 limit_efuse_size;
2206 	u32 phycap_addr;
2207 	u32 phycap_size;
2208 
2209 	const struct rtw89_pwr_cfg * const *pwr_on_seq;
2210 	const struct rtw89_pwr_cfg * const *pwr_off_seq;
2211 	const struct rtw89_phy_table *bb_table;
2212 	const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
2213 	const struct rtw89_phy_table *nctl_table;
2214 	const struct rtw89_txpwr_table *byr_table;
2215 	const struct rtw89_phy_dig_gain_table *dig_table;
2216 	const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
2217 				[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2218 				[RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2219 	const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
2220 				[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2221 				[RTW89_REGD_NUM][RTW89_5G_CH_NUM];
2222 	const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2223 				   [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2224 	const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2225 				   [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
2226 
2227 	u8 txpwr_factor_rf;
2228 	u8 txpwr_factor_mac;
2229 
2230 	u32 para_ver;
2231 	u32 wlcx_desired;
2232 	u8 btcx_desired;
2233 	u8 scbd;
2234 	u8 mailbox;
2235 
2236 	u8 afh_guard_ch;
2237 	const u8 *wl_rssi_thres;
2238 	const u8 *bt_rssi_thres;
2239 	u8 rssi_tol;
2240 
2241 	u8 mon_reg_num;
2242 	const struct rtw89_btc_fbtc_mreg *mon_reg;
2243 	u8 rf_para_ulink_num;
2244 	const struct rtw89_btc_rf_trx_para *rf_para_ulink;
2245 	u8 rf_para_dlink_num;
2246 	const struct rtw89_btc_rf_trx_para *rf_para_dlink;
2247 	u8 ps_mode_supported;
2248 };
2249 
2250 enum rtw89_hcifc_mode {
2251 	RTW89_HCIFC_POH = 0,
2252 	RTW89_HCIFC_STF = 1,
2253 	RTW89_HCIFC_SDIO = 2,
2254 
2255 	/* keep last */
2256 	RTW89_HCIFC_MODE_INVALID,
2257 };
2258 
2259 struct rtw89_dle_info {
2260 	enum rtw89_qta_mode qta_mode;
2261 	u16 wde_pg_size;
2262 	u16 ple_pg_size;
2263 	u16 c0_rx_qta;
2264 	u16 c1_rx_qta;
2265 };
2266 
2267 enum rtw89_host_rpr_mode {
2268 	RTW89_RPR_MODE_POH = 0,
2269 	RTW89_RPR_MODE_STF
2270 };
2271 
2272 struct rtw89_mac_info {
2273 	struct rtw89_dle_info dle_info;
2274 	struct rtw89_hfc_param hfc_param;
2275 	enum rtw89_qta_mode qta_mode;
2276 	u8 rpwm_seq_num;
2277 	u8 cpwm_seq_num;
2278 };
2279 
2280 enum rtw89_fw_type {
2281 	RTW89_FW_NORMAL = 1,
2282 	RTW89_FW_WOWLAN = 3,
2283 };
2284 
2285 struct rtw89_fw_suit {
2286 	const u8 *data;
2287 	u32 size;
2288 	u8 major_ver;
2289 	u8 minor_ver;
2290 	u8 sub_ver;
2291 	u8 sub_idex;
2292 	u16 build_year;
2293 	u16 build_mon;
2294 	u16 build_date;
2295 	u16 build_hour;
2296 	u16 build_min;
2297 	u8 cmd_ver;
2298 };
2299 
2300 #define RTW89_FW_VER_CODE(major, minor, sub, idx)	\
2301 	(((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
2302 #define RTW89_FW_SUIT_VER_CODE(s)	\
2303 	RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
2304 
2305 struct rtw89_fw_info {
2306 	const struct firmware *firmware;
2307 	struct rtw89_dev *rtwdev;
2308 	struct completion completion;
2309 	u8 h2c_seq;
2310 	u8 rec_seq;
2311 	struct rtw89_fw_suit normal;
2312 	struct rtw89_fw_suit wowlan;
2313 	bool fw_log_enable;
2314 	bool old_ht_ra_format;
2315 };
2316 
2317 struct rtw89_cam_info {
2318 	DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
2319 	DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
2320 	DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
2321 };
2322 
2323 enum rtw89_sar_sources {
2324 	RTW89_SAR_SOURCE_NONE,
2325 	RTW89_SAR_SOURCE_COMMON,
2326 
2327 	RTW89_SAR_SOURCE_NR,
2328 };
2329 
2330 struct rtw89_sar_cfg_common {
2331 	bool set[RTW89_SUBBAND_NR];
2332 	s32 cfg[RTW89_SUBBAND_NR];
2333 };
2334 
2335 struct rtw89_sar_info {
2336 	/* used to decide how to acces SAR cfg union */
2337 	enum rtw89_sar_sources src;
2338 
2339 	/* reserved for different knids of SAR cfg struct.
2340 	 * supposed that a single cfg struct cannot handle various SAR sources.
2341 	 */
2342 	union {
2343 		struct rtw89_sar_cfg_common cfg_common;
2344 	};
2345 };
2346 
2347 struct rtw89_hal {
2348 	u32 rx_fltr;
2349 	u8 cv;
2350 	u8 current_channel;
2351 	u8 prev_primary_channel;
2352 	u8 current_primary_channel;
2353 	enum rtw89_subband current_subband;
2354 	u8 current_band_width;
2355 	u8 current_band_type;
2356 	u32 sw_amsdu_max_size;
2357 	u32 antenna_tx;
2358 	u32 antenna_rx;
2359 	u8 tx_nss;
2360 	u8 rx_nss;
2361 };
2362 
2363 #define RTW89_MAX_MAC_ID_NUM 128
2364 
2365 enum rtw89_flags {
2366 	RTW89_FLAG_POWERON,
2367 	RTW89_FLAG_FW_RDY,
2368 	RTW89_FLAG_RUNNING,
2369 	RTW89_FLAG_BFEE_MON,
2370 	RTW89_FLAG_BFEE_EN,
2371 	RTW89_FLAG_NAPI_RUNNING,
2372 	RTW89_FLAG_LEISURE_PS,
2373 	RTW89_FLAG_LOW_POWER_MODE,
2374 	RTW89_FLAG_INACTIVE_PS,
2375 
2376 	NUM_OF_RTW89_FLAGS,
2377 };
2378 
2379 struct rtw89_pkt_stat {
2380 	u16 beacon_nr;
2381 	u32 rx_rate_cnt[RTW89_HW_RATE_NR];
2382 };
2383 
2384 DECLARE_EWMA(thermal, 4, 4);
2385 
2386 struct rtw89_phy_stat {
2387 	struct ewma_thermal avg_thermal[RF_PATH_MAX];
2388 	struct rtw89_pkt_stat cur_pkt_stat;
2389 	struct rtw89_pkt_stat last_pkt_stat;
2390 };
2391 
2392 #define RTW89_DACK_PATH_NR 2
2393 #define RTW89_DACK_IDX_NR 2
2394 #define RTW89_DACK_MSBK_NR 16
2395 struct rtw89_dack_info {
2396 	bool dack_done;
2397 	u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
2398 	u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2399 	u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2400 	u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2401 	u32 dack_cnt;
2402 	bool addck_timeout[RTW89_DACK_PATH_NR];
2403 	bool dadck_timeout[RTW89_DACK_PATH_NR];
2404 	bool msbk_timeout[RTW89_DACK_PATH_NR];
2405 };
2406 
2407 #define RTW89_IQK_CHS_NR 2
2408 #define RTW89_IQK_PATH_NR 4
2409 struct rtw89_iqk_info {
2410 	bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2411 	bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2412 	bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2413 	bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2414 	u32 iqk_fail_cnt;
2415 	bool is_iqk_init;
2416 	u32 iqk_channel[RTW89_IQK_CHS_NR];
2417 	u8 iqk_band[RTW89_IQK_PATH_NR];
2418 	u8 iqk_ch[RTW89_IQK_PATH_NR];
2419 	u8 iqk_bw[RTW89_IQK_PATH_NR];
2420 	u8 kcount;
2421 	u8 iqk_times;
2422 	u8 version;
2423 	u32 nb_txcfir[RTW89_IQK_PATH_NR];
2424 	u32 nb_rxcfir[RTW89_IQK_PATH_NR];
2425 	u32 bp_txkresult[RTW89_IQK_PATH_NR];
2426 	u32 bp_rxkresult[RTW89_IQK_PATH_NR];
2427 	u32 bp_iqkenable[RTW89_IQK_PATH_NR];
2428 	bool is_wb_txiqk[RTW89_IQK_PATH_NR];
2429 	bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
2430 	bool is_nbiqk;
2431 	bool iqk_fft_en;
2432 	bool iqk_xym_en;
2433 	bool iqk_sram_en;
2434 	bool iqk_cfir_en;
2435 	u8 thermal[RTW89_IQK_PATH_NR];
2436 	bool thermal_rek_en;
2437 	u32 syn1to2;
2438 	u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2439 	u8 iqk_table_idx[RTW89_IQK_PATH_NR];
2440 };
2441 
2442 #define RTW89_DPK_RF_PATH 2
2443 #define RTW89_DPK_AVG_THERMAL_NUM 8
2444 #define RTW89_DPK_BKUP_NUM 2
2445 struct rtw89_dpk_bkup_para {
2446 	enum rtw89_band band;
2447 	enum rtw89_bandwidth bw;
2448 	u8 ch;
2449 	bool path_ok;
2450 	u8 txagc_dpk;
2451 	u8 ther_dpk;
2452 	u8 gs;
2453 	u16 pwsf;
2454 };
2455 
2456 struct rtw89_dpk_info {
2457 	bool is_dpk_enable;
2458 	bool is_dpk_reload_en;
2459 	u16 dc_i[RTW89_DPK_RF_PATH];
2460 	u16 dc_q[RTW89_DPK_RF_PATH];
2461 	u8 corr_val[RTW89_DPK_RF_PATH];
2462 	u8 corr_idx[RTW89_DPK_RF_PATH];
2463 	u8 cur_idx[RTW89_DPK_RF_PATH];
2464 	struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2465 };
2466 
2467 struct rtw89_fem_info {
2468 	bool elna_2g;
2469 	bool elna_5g;
2470 	bool epa_2g;
2471 	bool epa_5g;
2472 };
2473 
2474 struct rtw89_phy_ch_info {
2475 	u8 rssi_min;
2476 	u16 rssi_min_macid;
2477 	u8 pre_rssi_min;
2478 	u8 rssi_max;
2479 	u16 rssi_max_macid;
2480 	u8 rxsc_160;
2481 	u8 rxsc_80;
2482 	u8 rxsc_40;
2483 	u8 rxsc_20;
2484 	u8 rxsc_l;
2485 	u8 is_noisy;
2486 };
2487 
2488 struct rtw89_agc_gaincode_set {
2489 	u8 lna_idx;
2490 	u8 tia_idx;
2491 	u8 rxb_idx;
2492 };
2493 
2494 #define IGI_RSSI_TH_NUM 5
2495 #define FA_TH_NUM 4
2496 #define LNA_GAIN_NUM 7
2497 #define TIA_GAIN_NUM 2
2498 struct rtw89_dig_info {
2499 	struct rtw89_agc_gaincode_set cur_gaincode;
2500 	bool force_gaincode_idx_en;
2501 	struct rtw89_agc_gaincode_set force_gaincode;
2502 	u8 igi_rssi_th[IGI_RSSI_TH_NUM];
2503 	u16 fa_th[FA_TH_NUM];
2504 	u8 igi_rssi;
2505 	u8 igi_fa_rssi;
2506 	u8 fa_rssi_ofst;
2507 	u8 dyn_igi_max;
2508 	u8 dyn_igi_min;
2509 	bool dyn_pd_th_en;
2510 	u8 dyn_pd_th_max;
2511 	u8 pd_low_th_ofst;
2512 	u8 ib_pbk;
2513 	s8 ib_pkpwr;
2514 	s8 lna_gain_a[LNA_GAIN_NUM];
2515 	s8 lna_gain_g[LNA_GAIN_NUM];
2516 	s8 *lna_gain;
2517 	s8 tia_gain_a[TIA_GAIN_NUM];
2518 	s8 tia_gain_g[TIA_GAIN_NUM];
2519 	s8 *tia_gain;
2520 	bool is_linked_pre;
2521 	bool bypass_dig;
2522 };
2523 
2524 enum rtw89_multi_cfo_mode {
2525 	RTW89_PKT_BASED_AVG_MODE = 0,
2526 	RTW89_ENTRY_BASED_AVG_MODE = 1,
2527 	RTW89_TP_BASED_AVG_MODE = 2,
2528 };
2529 
2530 enum rtw89_phy_cfo_status {
2531 	RTW89_PHY_DCFO_STATE_NORMAL = 0,
2532 	RTW89_PHY_DCFO_STATE_ENHANCE = 1,
2533 	RTW89_PHY_DCFO_STATE_MAX
2534 };
2535 
2536 struct rtw89_cfo_tracking_info {
2537 	u16 cfo_timer_ms;
2538 	bool cfo_trig_by_timer_en;
2539 	enum rtw89_phy_cfo_status phy_cfo_status;
2540 	u8 phy_cfo_trk_cnt;
2541 	bool is_adjust;
2542 	enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
2543 	bool apply_compensation;
2544 	u8 crystal_cap;
2545 	u8 crystal_cap_default;
2546 	u8 def_x_cap;
2547 	s8 x_cap_ofst;
2548 	u32 sta_cfo_tolerance;
2549 	s32 cfo_tail[CFO_TRACK_MAX_USER];
2550 	u16 cfo_cnt[CFO_TRACK_MAX_USER];
2551 	s32 cfo_avg_pre;
2552 	s32 cfo_avg[CFO_TRACK_MAX_USER];
2553 	s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
2554 	u32 packet_count;
2555 	u32 packet_count_pre;
2556 	s32 residual_cfo_acc;
2557 	u8 phy_cfotrk_state;
2558 	u8 phy_cfotrk_cnt;
2559 };
2560 
2561 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
2562 #define TSSI_TRIM_CH_GROUP_NUM 8
2563 
2564 #define TSSI_CCK_CH_GROUP_NUM 6
2565 #define TSSI_MCS_2G_CH_GROUP_NUM 5
2566 #define TSSI_MCS_5G_CH_GROUP_NUM 14
2567 #define TSSI_MCS_CH_GROUP_NUM \
2568 	(TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
2569 
2570 struct rtw89_tssi_info {
2571 	u8 thermal[RF_PATH_MAX];
2572 	s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
2573 	s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
2574 	s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
2575 	s8 extra_ofst[RF_PATH_MAX];
2576 	bool tssi_tracking_check[RF_PATH_MAX];
2577 	u8 default_txagc_offset[RF_PATH_MAX];
2578 	u32 base_thermal[RF_PATH_MAX];
2579 };
2580 
2581 struct rtw89_power_trim_info {
2582 	bool pg_thermal_trim;
2583 	bool pg_pa_bias_trim;
2584 	u8 thermal_trim[RF_PATH_MAX];
2585 	u8 pa_bias_trim[RF_PATH_MAX];
2586 };
2587 
2588 struct rtw89_regulatory {
2589 	char alpha2[3];
2590 	u8 txpwr_regd[RTW89_BAND_MAX];
2591 };
2592 
2593 enum rtw89_ifs_clm_application {
2594 	RTW89_IFS_CLM_INIT = 0,
2595 	RTW89_IFS_CLM_BACKGROUND = 1,
2596 	RTW89_IFS_CLM_ACS = 2,
2597 	RTW89_IFS_CLM_DIG = 3,
2598 	RTW89_IFS_CLM_TDMA_DIG = 4,
2599 	RTW89_IFS_CLM_DBG = 5,
2600 	RTW89_IFS_CLM_DBG_MANUAL = 6
2601 };
2602 
2603 enum rtw89_env_racing_lv {
2604 	RTW89_RAC_RELEASE = 0,
2605 	RTW89_RAC_LV_1 = 1,
2606 	RTW89_RAC_LV_2 = 2,
2607 	RTW89_RAC_LV_3 = 3,
2608 	RTW89_RAC_LV_4 = 4,
2609 	RTW89_RAC_MAX_NUM = 5
2610 };
2611 
2612 struct rtw89_ccx_para_info {
2613 	enum rtw89_env_racing_lv rac_lv;
2614 	u16 mntr_time;
2615 	u8 nhm_manual_th_ofst;
2616 	u8 nhm_manual_th0;
2617 	enum rtw89_ifs_clm_application ifs_clm_app;
2618 	u32 ifs_clm_manual_th_times;
2619 	u32 ifs_clm_manual_th0;
2620 	u8 fahm_manual_th_ofst;
2621 	u8 fahm_manual_th0;
2622 	u8 fahm_numer_opt;
2623 	u8 fahm_denom_opt;
2624 };
2625 
2626 enum rtw89_ccx_edcca_opt_sc_idx {
2627 	RTW89_CCX_EDCCA_SEG0_P0 = 0,
2628 	RTW89_CCX_EDCCA_SEG0_S1 = 1,
2629 	RTW89_CCX_EDCCA_SEG0_S2 = 2,
2630 	RTW89_CCX_EDCCA_SEG0_S3 = 3,
2631 	RTW89_CCX_EDCCA_SEG1_P0 = 4,
2632 	RTW89_CCX_EDCCA_SEG1_S1 = 5,
2633 	RTW89_CCX_EDCCA_SEG1_S2 = 6,
2634 	RTW89_CCX_EDCCA_SEG1_S3 = 7
2635 };
2636 
2637 enum rtw89_ccx_edcca_opt_bw_idx {
2638 	RTW89_CCX_EDCCA_BW20_0 = 0,
2639 	RTW89_CCX_EDCCA_BW20_1 = 1,
2640 	RTW89_CCX_EDCCA_BW20_2 = 2,
2641 	RTW89_CCX_EDCCA_BW20_3 = 3,
2642 	RTW89_CCX_EDCCA_BW20_4 = 4,
2643 	RTW89_CCX_EDCCA_BW20_5 = 5,
2644 	RTW89_CCX_EDCCA_BW20_6 = 6,
2645 	RTW89_CCX_EDCCA_BW20_7 = 7
2646 };
2647 
2648 #define RTW89_NHM_TH_NUM 11
2649 #define RTW89_FAHM_TH_NUM 11
2650 #define RTW89_NHM_RPT_NUM 12
2651 #define RTW89_FAHM_RPT_NUM 12
2652 #define RTW89_IFS_CLM_NUM 4
2653 struct rtw89_env_monitor_info {
2654 	u32 ccx_trigger_time;
2655 	u64 start_time;
2656 	u8 ccx_rpt_stamp;
2657 	u8 ccx_watchdog_result;
2658 	bool ccx_ongoing;
2659 	u8 ccx_rac_lv;
2660 	bool ccx_manual_ctrl;
2661 	u8 ccx_pre_rssi;
2662 	u16 clm_mntr_time;
2663 	u16 nhm_mntr_time;
2664 	u16 ifs_clm_mntr_time;
2665 	enum rtw89_ifs_clm_application ifs_clm_app;
2666 	u16 fahm_mntr_time;
2667 	u16 edcca_clm_mntr_time;
2668 	u16 ccx_period;
2669 	u8 ccx_unit_idx;
2670 	enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx;
2671 	u8 nhm_th[RTW89_NHM_TH_NUM];
2672 	u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
2673 	u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
2674 	u8 fahm_numer_opt;
2675 	u8 fahm_denom_opt;
2676 	u8 fahm_th[RTW89_FAHM_TH_NUM];
2677 	u16 clm_result;
2678 	u16 nhm_result[RTW89_NHM_RPT_NUM];
2679 	u8 nhm_wgt[RTW89_NHM_RPT_NUM];
2680 	u16 nhm_tx_cnt;
2681 	u16 nhm_cca_cnt;
2682 	u16 nhm_idle_cnt;
2683 	u16 ifs_clm_tx;
2684 	u16 ifs_clm_edcca_excl_cca;
2685 	u16 ifs_clm_ofdmfa;
2686 	u16 ifs_clm_ofdmcca_excl_fa;
2687 	u16 ifs_clm_cckfa;
2688 	u16 ifs_clm_cckcca_excl_fa;
2689 	u16 ifs_clm_total_ifs;
2690 	u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
2691 	u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
2692 	u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
2693 	u16 fahm_result[RTW89_FAHM_RPT_NUM];
2694 	u16 fahm_denom_result;
2695 	u16 edcca_clm_result;
2696 	u8 clm_ratio;
2697 	u8 nhm_rpt[RTW89_NHM_RPT_NUM];
2698 	u8 nhm_tx_ratio;
2699 	u8 nhm_cca_ratio;
2700 	u8 nhm_idle_ratio;
2701 	u8 nhm_ratio;
2702 	u16 nhm_result_sum;
2703 	u8 nhm_pwr;
2704 	u8 ifs_clm_tx_ratio;
2705 	u8 ifs_clm_edcca_excl_cca_ratio;
2706 	u8 ifs_clm_cck_fa_ratio;
2707 	u8 ifs_clm_ofdm_fa_ratio;
2708 	u8 ifs_clm_cck_cca_excl_fa_ratio;
2709 	u8 ifs_clm_ofdm_cca_excl_fa_ratio;
2710 	u16 ifs_clm_cck_fa_permil;
2711 	u16 ifs_clm_ofdm_fa_permil;
2712 	u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
2713 	u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
2714 	u8 fahm_rpt[RTW89_FAHM_RPT_NUM];
2715 	u16 fahm_result_sum;
2716 	u8 fahm_ratio;
2717 	u8 fahm_denom_ratio;
2718 	u8 fahm_pwr;
2719 	u8 edcca_clm_ratio;
2720 };
2721 
2722 enum rtw89_ser_rcvy_step {
2723 	RTW89_SER_DRV_STOP_TX,
2724 	RTW89_SER_DRV_STOP_RX,
2725 	RTW89_SER_DRV_STOP_RUN,
2726 	RTW89_SER_HAL_STOP_DMA,
2727 	RTW89_NUM_OF_SER_FLAGS
2728 };
2729 
2730 struct rtw89_ser {
2731 	u8 state;
2732 	u8 alarm_event;
2733 
2734 	struct work_struct ser_hdl_work;
2735 	struct delayed_work ser_alarm_work;
2736 	struct state_ent *st_tbl;
2737 	struct event_ent *ev_tbl;
2738 	struct list_head msg_q;
2739 	spinlock_t msg_q_lock; /* lock when read/write ser msg */
2740 	DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
2741 };
2742 
2743 enum rtw89_mac_ax_ps_mode {
2744 	RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
2745 	RTW89_MAC_AX_PS_MODE_LEGACY = 1,
2746 	RTW89_MAC_AX_PS_MODE_WMMPS  = 2,
2747 	RTW89_MAC_AX_PS_MODE_MAX    = 3,
2748 };
2749 
2750 enum rtw89_last_rpwm_mode {
2751 	RTW89_LAST_RPWM_PS        = 0x0,
2752 	RTW89_LAST_RPWM_ACTIVE    = 0x6,
2753 };
2754 
2755 struct rtw89_lps_parm {
2756 	u8 macid;
2757 	u8 psmode; /* enum rtw89_mac_ax_ps_mode */
2758 	u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
2759 };
2760 
2761 struct rtw89_ppdu_sts_info {
2762 	struct sk_buff_head rx_queue[RTW89_PHY_MAX];
2763 	u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
2764 };
2765 
2766 struct rtw89_early_h2c {
2767 	struct list_head list;
2768 	u8 *h2c;
2769 	u16 h2c_len;
2770 };
2771 
2772 struct rtw89_dev {
2773 	struct ieee80211_hw *hw;
2774 	struct device *dev;
2775 
2776 	bool dbcc_en;
2777 	const struct rtw89_chip_info *chip;
2778 	struct rtw89_hal hal;
2779 	struct rtw89_mac_info mac;
2780 	struct rtw89_fw_info fw;
2781 	struct rtw89_hci_info hci;
2782 	struct rtw89_efuse efuse;
2783 	struct rtw89_traffic_stats stats;
2784 
2785 	/* ensures exclusive access from mac80211 callbacks */
2786 	struct mutex mutex;
2787 	struct list_head rtwvifs_list;
2788 	/* used to protect rf read write */
2789 	struct mutex rf_mutex;
2790 	struct workqueue_struct *txq_wq;
2791 	struct work_struct txq_work;
2792 	struct delayed_work txq_reinvoke_work;
2793 	/* used to protect ba_list */
2794 	spinlock_t ba_lock;
2795 	/* txqs to setup ba session */
2796 	struct list_head ba_list;
2797 	struct work_struct ba_work;
2798 
2799 	struct rtw89_cam_info cam_info;
2800 
2801 	struct sk_buff_head c2h_queue;
2802 	struct work_struct c2h_work;
2803 
2804 	struct list_head early_h2c_list;
2805 
2806 	struct rtw89_ser ser;
2807 
2808 	DECLARE_BITMAP(hw_port, RTW89_MAX_HW_PORT_NUM);
2809 	DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
2810 	DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
2811 
2812 	struct rtw89_phy_stat phystat;
2813 	struct rtw89_dack_info dack;
2814 	struct rtw89_iqk_info iqk;
2815 	struct rtw89_dpk_info dpk;
2816 	bool is_tssi_mode[RF_PATH_MAX];
2817 	bool is_bt_iqk_timeout;
2818 
2819 	struct rtw89_fem_info fem;
2820 	struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX];
2821 	struct rtw89_tssi_info tssi;
2822 	struct rtw89_power_trim_info pwr_trim;
2823 
2824 	struct rtw89_cfo_tracking_info cfo_tracking;
2825 	struct rtw89_env_monitor_info env_monitor;
2826 	struct rtw89_dig_info dig;
2827 	struct rtw89_phy_ch_info ch_info;
2828 	struct delayed_work track_work;
2829 	struct delayed_work coex_act1_work;
2830 	struct delayed_work coex_bt_devinfo_work;
2831 	struct delayed_work coex_rfk_chk_work;
2832 	struct delayed_work cfo_track_work;
2833 	struct rtw89_ppdu_sts_info ppdu_sts;
2834 	u8 total_sta_assoc;
2835 	bool scanning;
2836 
2837 	const struct rtw89_regulatory *regd;
2838 	struct rtw89_sar_info sar;
2839 
2840 	struct rtw89_btc btc;
2841 	enum rtw89_ps_mode ps_mode;
2842 	bool lps_enabled;
2843 
2844 	/* napi structure */
2845 	struct net_device netdev;
2846 	struct napi_struct napi;
2847 	int napi_budget_countdown;
2848 
2849 	/* HCI related data, keep last */
2850 	u8 priv[0] __aligned(sizeof(void *));
2851 };
2852 
2853 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
2854 				     struct rtw89_core_tx_request *tx_req)
2855 {
2856 	return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
2857 }
2858 
2859 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
2860 {
2861 	rtwdev->hci.ops->reset(rtwdev);
2862 }
2863 
2864 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
2865 {
2866 	return rtwdev->hci.ops->start(rtwdev);
2867 }
2868 
2869 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
2870 {
2871 	rtwdev->hci.ops->stop(rtwdev);
2872 }
2873 
2874 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
2875 {
2876 	return rtwdev->hci.ops->deinit(rtwdev);
2877 }
2878 
2879 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
2880 {
2881 	rtwdev->hci.ops->recalc_int_mit(rtwdev);
2882 }
2883 
2884 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
2885 {
2886 	return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
2887 }
2888 
2889 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
2890 {
2891 	return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
2892 }
2893 
2894 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
2895 					  bool drop)
2896 {
2897 	if (rtwdev->hci.ops->flush_queues)
2898 		return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
2899 }
2900 
2901 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
2902 {
2903 	return rtwdev->hci.ops->read8(rtwdev, addr);
2904 }
2905 
2906 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
2907 {
2908 	return rtwdev->hci.ops->read16(rtwdev, addr);
2909 }
2910 
2911 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
2912 {
2913 	return rtwdev->hci.ops->read32(rtwdev, addr);
2914 }
2915 
2916 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
2917 {
2918 	rtwdev->hci.ops->write8(rtwdev, addr, data);
2919 }
2920 
2921 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
2922 {
2923 	rtwdev->hci.ops->write16(rtwdev, addr, data);
2924 }
2925 
2926 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
2927 {
2928 	rtwdev->hci.ops->write32(rtwdev, addr, data);
2929 }
2930 
2931 static inline void
2932 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
2933 {
2934 	u8 val;
2935 
2936 	val = rtw89_read8(rtwdev, addr);
2937 	rtw89_write8(rtwdev, addr, val | bit);
2938 }
2939 
2940 static inline void
2941 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
2942 {
2943 	u16 val;
2944 
2945 	val = rtw89_read16(rtwdev, addr);
2946 	rtw89_write16(rtwdev, addr, val | bit);
2947 }
2948 
2949 static inline void
2950 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
2951 {
2952 	u32 val;
2953 
2954 	val = rtw89_read32(rtwdev, addr);
2955 	rtw89_write32(rtwdev, addr, val | bit);
2956 }
2957 
2958 static inline void
2959 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
2960 {
2961 	u8 val;
2962 
2963 	val = rtw89_read8(rtwdev, addr);
2964 	rtw89_write8(rtwdev, addr, val & ~bit);
2965 }
2966 
2967 static inline void
2968 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
2969 {
2970 	u16 val;
2971 
2972 	val = rtw89_read16(rtwdev, addr);
2973 	rtw89_write16(rtwdev, addr, val & ~bit);
2974 }
2975 
2976 static inline void
2977 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
2978 {
2979 	u32 val;
2980 
2981 	val = rtw89_read32(rtwdev, addr);
2982 	rtw89_write32(rtwdev, addr, val & ~bit);
2983 }
2984 
2985 static inline u32
2986 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
2987 {
2988 	u32 shift = __ffs(mask);
2989 	u32 orig;
2990 	u32 ret;
2991 
2992 	orig = rtw89_read32(rtwdev, addr);
2993 	ret = (orig & mask) >> shift;
2994 
2995 	return ret;
2996 }
2997 
2998 static inline u16
2999 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3000 {
3001 	u32 shift = __ffs(mask);
3002 	u32 orig;
3003 	u32 ret;
3004 
3005 	orig = rtw89_read16(rtwdev, addr);
3006 	ret = (orig & mask) >> shift;
3007 
3008 	return ret;
3009 }
3010 
3011 static inline u8
3012 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3013 {
3014 	u32 shift = __ffs(mask);
3015 	u32 orig;
3016 	u32 ret;
3017 
3018 	orig = rtw89_read8(rtwdev, addr);
3019 	ret = (orig & mask) >> shift;
3020 
3021 	return ret;
3022 }
3023 
3024 static inline void
3025 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
3026 {
3027 	u32 shift = __ffs(mask);
3028 	u32 orig;
3029 	u32 set;
3030 
3031 	WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
3032 
3033 	orig = rtw89_read32(rtwdev, addr);
3034 	set = (orig & ~mask) | ((data << shift) & mask);
3035 	rtw89_write32(rtwdev, addr, set);
3036 }
3037 
3038 static inline void
3039 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
3040 {
3041 	u32 shift;
3042 	u16 orig, set;
3043 
3044 	mask &= 0xffff;
3045 	shift = __ffs(mask);
3046 
3047 	orig = rtw89_read16(rtwdev, addr);
3048 	set = (orig & ~mask) | ((data << shift) & mask);
3049 	rtw89_write16(rtwdev, addr, set);
3050 }
3051 
3052 static inline void
3053 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
3054 {
3055 	u32 shift;
3056 	u8 orig, set;
3057 
3058 	mask &= 0xff;
3059 	shift = __ffs(mask);
3060 
3061 	orig = rtw89_read8(rtwdev, addr);
3062 	set = (orig & ~mask) | ((data << shift) & mask);
3063 	rtw89_write8(rtwdev, addr, set);
3064 }
3065 
3066 static inline u32
3067 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3068 	      u32 addr, u32 mask)
3069 {
3070 	u32 val;
3071 
3072 	mutex_lock(&rtwdev->rf_mutex);
3073 	val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
3074 	mutex_unlock(&rtwdev->rf_mutex);
3075 
3076 	return val;
3077 }
3078 
3079 static inline void
3080 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3081 	       u32 addr, u32 mask, u32 data)
3082 {
3083 	mutex_lock(&rtwdev->rf_mutex);
3084 	rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
3085 	mutex_unlock(&rtwdev->rf_mutex);
3086 }
3087 
3088 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
3089 {
3090 	void *p = rtwtxq;
3091 
3092 	return container_of(p, struct ieee80211_txq, drv_priv);
3093 }
3094 
3095 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
3096 				       struct ieee80211_txq *txq)
3097 {
3098 	struct rtw89_txq *rtwtxq;
3099 
3100 	if (!txq)
3101 		return;
3102 
3103 	rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3104 	INIT_LIST_HEAD(&rtwtxq->list);
3105 }
3106 
3107 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
3108 {
3109 	void *p = rtwvif;
3110 
3111 	return container_of(p, struct ieee80211_vif, drv_priv);
3112 }
3113 
3114 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
3115 {
3116 	void *p = rtwsta;
3117 
3118 	return container_of(p, struct ieee80211_sta, drv_priv);
3119 }
3120 
3121 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
3122 {
3123 	return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
3124 }
3125 
3126 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
3127 {
3128 	return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
3129 }
3130 
3131 static inline
3132 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
3133 				    struct rtw89_channel_help_params *p)
3134 {
3135 	rtwdev->chip->ops->set_channel_help(rtwdev, true, p);
3136 }
3137 
3138 static inline
3139 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
3140 				 struct rtw89_channel_help_params *p)
3141 {
3142 	rtwdev->chip->ops->set_channel_help(rtwdev, false, p);
3143 }
3144 
3145 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
3146 {
3147 	const struct rtw89_chip_info *chip = rtwdev->chip;
3148 
3149 	if (chip->ops->fem_setup)
3150 		chip->ops->fem_setup(rtwdev);
3151 }
3152 
3153 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
3154 {
3155 	const struct rtw89_chip_info *chip = rtwdev->chip;
3156 
3157 	if (chip->ops->bb_sethw)
3158 		chip->ops->bb_sethw(rtwdev);
3159 }
3160 
3161 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
3162 {
3163 	const struct rtw89_chip_info *chip = rtwdev->chip;
3164 
3165 	if (chip->ops->rfk_init)
3166 		chip->ops->rfk_init(rtwdev);
3167 }
3168 
3169 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
3170 {
3171 	const struct rtw89_chip_info *chip = rtwdev->chip;
3172 
3173 	if (chip->ops->rfk_channel)
3174 		chip->ops->rfk_channel(rtwdev);
3175 }
3176 
3177 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev)
3178 {
3179 	const struct rtw89_chip_info *chip = rtwdev->chip;
3180 
3181 	if (chip->ops->rfk_band_changed)
3182 		chip->ops->rfk_band_changed(rtwdev);
3183 }
3184 
3185 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
3186 {
3187 	const struct rtw89_chip_info *chip = rtwdev->chip;
3188 
3189 	if (chip->ops->rfk_scan)
3190 		chip->ops->rfk_scan(rtwdev, start);
3191 }
3192 
3193 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
3194 {
3195 	const struct rtw89_chip_info *chip = rtwdev->chip;
3196 
3197 	if (chip->ops->rfk_track)
3198 		chip->ops->rfk_track(rtwdev);
3199 }
3200 
3201 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
3202 {
3203 	const struct rtw89_chip_info *chip = rtwdev->chip;
3204 
3205 	if (chip->ops->set_txpwr_ctrl)
3206 		chip->ops->set_txpwr_ctrl(rtwdev);
3207 }
3208 
3209 static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev)
3210 {
3211 	const struct rtw89_chip_info *chip = rtwdev->chip;
3212 	u8 ch = rtwdev->hal.current_channel;
3213 
3214 	if (!ch)
3215 		return;
3216 
3217 	if (chip->ops->set_txpwr)
3218 		chip->ops->set_txpwr(rtwdev);
3219 }
3220 
3221 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
3222 {
3223 	const struct rtw89_chip_info *chip = rtwdev->chip;
3224 
3225 	if (chip->ops->power_trim)
3226 		chip->ops->power_trim(rtwdev);
3227 }
3228 
3229 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
3230 					      enum rtw89_phy_idx phy_idx)
3231 {
3232 	const struct rtw89_chip_info *chip = rtwdev->chip;
3233 
3234 	if (chip->ops->init_txpwr_unit)
3235 		chip->ops->init_txpwr_unit(rtwdev, phy_idx);
3236 }
3237 
3238 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
3239 					enum rtw89_rf_path rf_path)
3240 {
3241 	const struct rtw89_chip_info *chip = rtwdev->chip;
3242 
3243 	if (!chip->ops->get_thermal)
3244 		return 0x10;
3245 
3246 	return chip->ops->get_thermal(rtwdev, rf_path);
3247 }
3248 
3249 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
3250 					 struct rtw89_rx_phy_ppdu *phy_ppdu,
3251 					 struct ieee80211_rx_status *status)
3252 {
3253 	const struct rtw89_chip_info *chip = rtwdev->chip;
3254 
3255 	if (chip->ops->query_ppdu)
3256 		chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
3257 }
3258 
3259 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,
3260 						 bool bt_en)
3261 {
3262 	const struct rtw89_chip_info *chip = rtwdev->chip;
3263 
3264 	if (chip->ops->bb_ctrl_btc_preagc)
3265 		chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en);
3266 }
3267 
3268 static inline
3269 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
3270 				       struct ieee80211_vif *vif)
3271 {
3272 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3273 	const struct rtw89_chip_info *chip = rtwdev->chip;
3274 
3275 	if (!vif->bss_conf.he_support || !vif->bss_conf.assoc)
3276 		return;
3277 
3278 	if (chip->ops->set_txpwr_ul_tb_offset)
3279 		chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
3280 }
3281 
3282 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
3283 					  const struct rtw89_txpwr_table *tbl)
3284 {
3285 	tbl->load(rtwdev, tbl);
3286 }
3287 
3288 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
3289 {
3290 	return rtwdev->regd->txpwr_regd[band];
3291 }
3292 
3293 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
3294 {
3295 	const struct rtw89_chip_info *chip = rtwdev->chip;
3296 
3297 	if (chip->ops->ctrl_btg)
3298 		chip->ops->ctrl_btg(rtwdev, btg);
3299 }
3300 
3301 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
3302 {
3303 	__le16 fc = hdr->frame_control;
3304 
3305 	if (ieee80211_has_tods(fc))
3306 		return hdr->addr1;
3307 	else if (ieee80211_has_fromds(fc))
3308 		return hdr->addr2;
3309 	else
3310 		return hdr->addr3;
3311 }
3312 
3313 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
3314 {
3315 	if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
3316 	    (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
3317 	    (sta->he_cap.he_cap_elem.phy_cap_info[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
3318 	    (sta->he_cap.he_cap_elem.phy_cap_info[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
3319 		return true;
3320 	return false;
3321 }
3322 
3323 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
3324 						      enum rtw89_fw_type type)
3325 {
3326 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
3327 
3328 	if (type == RTW89_FW_WOWLAN)
3329 		return &fw_info->wowlan;
3330 	return &fw_info->normal;
3331 }
3332 
3333 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3334 			struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
3335 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
3336 		 struct sk_buff *skb, bool fwdl);
3337 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
3338 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
3339 			    struct rtw89_tx_desc_info *desc_info,
3340 			    void *txdesc);
3341 void rtw89_core_rx(struct rtw89_dev *rtwdev,
3342 		   struct rtw89_rx_desc_info *desc_info,
3343 		   struct sk_buff *skb);
3344 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
3345 			     struct rtw89_rx_desc_info *desc_info,
3346 			     u8 *data, u32 data_offset);
3347 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
3348 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
3349 void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
3350 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
3351 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
3352 		       struct ieee80211_vif *vif,
3353 		       struct ieee80211_sta *sta);
3354 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
3355 			 struct ieee80211_vif *vif,
3356 			 struct ieee80211_sta *sta);
3357 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
3358 			    struct ieee80211_vif *vif,
3359 			    struct ieee80211_sta *sta);
3360 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
3361 			      struct ieee80211_vif *vif,
3362 			      struct ieee80211_sta *sta);
3363 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
3364 			  struct ieee80211_vif *vif,
3365 			  struct ieee80211_sta *sta);
3366 int rtw89_core_init(struct rtw89_dev *rtwdev);
3367 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
3368 int rtw89_core_register(struct rtw89_dev *rtwdev);
3369 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
3370 void rtw89_set_channel(struct rtw89_dev *rtwdev);
3371 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
3372 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
3373 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
3374 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
3375 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
3376 u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate);
3377 int rtw89_regd_init(struct rtw89_dev *rtwdev,
3378 		    void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
3379 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
3380 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
3381 			      struct rtw89_traffic_stats *stats);
3382 int rtw89_core_start(struct rtw89_dev *rtwdev);
3383 void rtw89_core_stop(struct rtw89_dev *rtwdev);
3384 
3385 #endif
3386