1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 struct rtw89_mac_gen_def; 18 struct rtw89_phy_gen_def; 19 struct rtw89_efuse_block_cfg; 20 struct rtw89_h2c_rf_tssi; 21 struct rtw89_fw_txpwr_track_cfg; 22 struct rtw89_phy_rfk_log_fmt; 23 24 extern const struct ieee80211_ops rtw89_ops; 25 26 #define MASKBYTE0 0xff 27 #define MASKBYTE1 0xff00 28 #define MASKBYTE2 0xff0000 29 #define MASKBYTE3 0xff000000 30 #define MASKBYTE4 0xff00000000ULL 31 #define MASKHWORD 0xffff0000 32 #define MASKLWORD 0x0000ffff 33 #define MASKDWORD 0xffffffff 34 #define RFREG_MASK 0xfffff 35 #define INV_RF_DATA 0xffffffff 36 #define BYPASS_CR_DATA 0xbabecafe 37 38 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 39 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 40 #define CFO_TRACK_MAX_USER 64 41 #define MAX_RSSI 110 42 #define RSSI_FACTOR 1 43 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 44 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 45 #define DELTA_SWINGIDX_SIZE 30 46 47 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 48 #define RTW89_RADIOTAP_ROOM_EHT \ 49 (sizeof(struct ieee80211_radiotap_tlv) + \ 50 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 51 sizeof(struct ieee80211_radiotap_tlv) + \ 52 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 53 #define RTW89_RADIOTAP_ROOM \ 54 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 55 56 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 57 #define RTW89_HTC_VARIANT_HE 3 58 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 59 #define RTW89_HTC_VARIANT_HE_CID_OM 1 60 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 61 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 62 63 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 64 enum htc_om_channel_width { 65 HTC_OM_CHANNEL_WIDTH_20 = 0, 66 HTC_OM_CHANNEL_WIDTH_40 = 1, 67 HTC_OM_CHANNEL_WIDTH_80 = 2, 68 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 69 }; 70 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 71 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 72 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 73 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 74 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 75 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 76 77 #define RTW89_TF_PAD GENMASK(11, 0) 78 #define RTW89_TF_BASIC_USER_INFO_SZ 6 79 80 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 81 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 82 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 83 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 84 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 86 87 enum rtw89_subband { 88 RTW89_CH_2G = 0, 89 RTW89_CH_5G_BAND_1 = 1, 90 /* RTW89_CH_5G_BAND_2 = 2, unused */ 91 RTW89_CH_5G_BAND_3 = 3, 92 RTW89_CH_5G_BAND_4 = 4, 93 94 RTW89_CH_6G_BAND_IDX0, /* Low */ 95 RTW89_CH_6G_BAND_IDX1, /* Low */ 96 RTW89_CH_6G_BAND_IDX2, /* Mid */ 97 RTW89_CH_6G_BAND_IDX3, /* Mid */ 98 RTW89_CH_6G_BAND_IDX4, /* High */ 99 RTW89_CH_6G_BAND_IDX5, /* High */ 100 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 101 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 102 103 RTW89_SUBBAND_NR, 104 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 105 }; 106 107 enum rtw89_gain_offset { 108 RTW89_GAIN_OFFSET_2G_CCK, 109 RTW89_GAIN_OFFSET_2G_OFDM, 110 RTW89_GAIN_OFFSET_5G_LOW, 111 RTW89_GAIN_OFFSET_5G_MID, 112 RTW89_GAIN_OFFSET_5G_HIGH, 113 RTW89_GAIN_OFFSET_6G_L0, 114 RTW89_GAIN_OFFSET_6G_L1, 115 RTW89_GAIN_OFFSET_6G_M0, 116 RTW89_GAIN_OFFSET_6G_M1, 117 RTW89_GAIN_OFFSET_6G_H0, 118 RTW89_GAIN_OFFSET_6G_H1, 119 RTW89_GAIN_OFFSET_6G_UH0, 120 RTW89_GAIN_OFFSET_6G_UH1, 121 122 RTW89_GAIN_OFFSET_NR, 123 }; 124 125 enum rtw89_hci_type { 126 RTW89_HCI_TYPE_PCIE, 127 RTW89_HCI_TYPE_USB, 128 RTW89_HCI_TYPE_SDIO, 129 }; 130 131 enum rtw89_core_chip_id { 132 RTL8852A, 133 RTL8852B, 134 RTL8852C, 135 RTL8851B, 136 RTL8922A, 137 }; 138 139 enum rtw89_chip_gen { 140 RTW89_CHIP_AX, 141 RTW89_CHIP_BE, 142 143 RTW89_CHIP_GEN_NUM, 144 }; 145 146 enum rtw89_cv { 147 CHIP_CAV, 148 CHIP_CBV, 149 CHIP_CCV, 150 CHIP_CDV, 151 CHIP_CEV, 152 CHIP_CFV, 153 CHIP_CV_MAX, 154 CHIP_CV_INVALID = CHIP_CV_MAX, 155 }; 156 157 enum rtw89_bacam_ver { 158 RTW89_BACAM_V0, 159 RTW89_BACAM_V1, 160 161 RTW89_BACAM_V0_EXT = 99, 162 }; 163 164 enum rtw89_core_tx_type { 165 RTW89_CORE_TX_TYPE_DATA, 166 RTW89_CORE_TX_TYPE_MGMT, 167 RTW89_CORE_TX_TYPE_FWCMD, 168 }; 169 170 enum rtw89_core_rx_type { 171 RTW89_CORE_RX_TYPE_WIFI = 0, 172 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 173 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 174 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 175 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 176 RTW89_CORE_RX_TYPE_SS2FW = 5, 177 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 178 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 179 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 180 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 181 RTW89_CORE_RX_TYPE_C2H = 10, 182 RTW89_CORE_RX_TYPE_CSI = 11, 183 RTW89_CORE_RX_TYPE_CQI = 12, 184 RTW89_CORE_RX_TYPE_H2C = 13, 185 RTW89_CORE_RX_TYPE_FWDL = 14, 186 }; 187 188 enum rtw89_txq_flags { 189 RTW89_TXQ_F_AMPDU = 0, 190 RTW89_TXQ_F_BLOCK_BA = 1, 191 RTW89_TXQ_F_FORBID_BA = 2, 192 }; 193 194 enum rtw89_net_type { 195 RTW89_NET_TYPE_NO_LINK = 0, 196 RTW89_NET_TYPE_AD_HOC = 1, 197 RTW89_NET_TYPE_INFRA = 2, 198 RTW89_NET_TYPE_AP_MODE = 3, 199 }; 200 201 enum rtw89_wifi_role { 202 RTW89_WIFI_ROLE_NONE, 203 RTW89_WIFI_ROLE_STATION, 204 RTW89_WIFI_ROLE_AP, 205 RTW89_WIFI_ROLE_AP_VLAN, 206 RTW89_WIFI_ROLE_ADHOC, 207 RTW89_WIFI_ROLE_ADHOC_MASTER, 208 RTW89_WIFI_ROLE_MESH_POINT, 209 RTW89_WIFI_ROLE_MONITOR, 210 RTW89_WIFI_ROLE_P2P_DEVICE, 211 RTW89_WIFI_ROLE_P2P_CLIENT, 212 RTW89_WIFI_ROLE_P2P_GO, 213 RTW89_WIFI_ROLE_NAN, 214 RTW89_WIFI_ROLE_MLME_MAX 215 }; 216 217 enum rtw89_upd_mode { 218 RTW89_ROLE_CREATE, 219 RTW89_ROLE_REMOVE, 220 RTW89_ROLE_TYPE_CHANGE, 221 RTW89_ROLE_INFO_CHANGE, 222 RTW89_ROLE_CON_DISCONN, 223 RTW89_ROLE_BAND_SW, 224 RTW89_ROLE_FW_RESTORE, 225 }; 226 227 enum rtw89_self_role { 228 RTW89_SELF_ROLE_CLIENT, 229 RTW89_SELF_ROLE_AP, 230 RTW89_SELF_ROLE_AP_CLIENT 231 }; 232 233 enum rtw89_msk_sO_el { 234 RTW89_NO_MSK, 235 RTW89_SMA, 236 RTW89_TMA, 237 RTW89_BSSID 238 }; 239 240 enum rtw89_sch_tx_sel { 241 RTW89_SCH_TX_SEL_ALL, 242 RTW89_SCH_TX_SEL_HIQ, 243 RTW89_SCH_TX_SEL_MG0, 244 RTW89_SCH_TX_SEL_MACID, 245 }; 246 247 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 248 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 249 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 250 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 251 */ 252 enum rtw89_add_cam_sec_mode { 253 RTW89_ADDR_CAM_SEC_NONE = 0, 254 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 255 RTW89_ADDR_CAM_SEC_NORMAL = 2, 256 RTW89_ADDR_CAM_SEC_4GROUP = 3, 257 }; 258 259 enum rtw89_sec_key_type { 260 RTW89_SEC_KEY_TYPE_NONE = 0, 261 RTW89_SEC_KEY_TYPE_WEP40 = 1, 262 RTW89_SEC_KEY_TYPE_WEP104 = 2, 263 RTW89_SEC_KEY_TYPE_TKIP = 3, 264 RTW89_SEC_KEY_TYPE_WAPI = 4, 265 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 266 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 267 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 268 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 269 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 270 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 271 }; 272 273 enum rtw89_port { 274 RTW89_PORT_0 = 0, 275 RTW89_PORT_1 = 1, 276 RTW89_PORT_2 = 2, 277 RTW89_PORT_3 = 3, 278 RTW89_PORT_4 = 4, 279 RTW89_PORT_NUM 280 }; 281 282 enum rtw89_band { 283 RTW89_BAND_2G = 0, 284 RTW89_BAND_5G = 1, 285 RTW89_BAND_6G = 2, 286 RTW89_BAND_NUM, 287 }; 288 289 enum rtw89_hw_rate { 290 RTW89_HW_RATE_CCK1 = 0x0, 291 RTW89_HW_RATE_CCK2 = 0x1, 292 RTW89_HW_RATE_CCK5_5 = 0x2, 293 RTW89_HW_RATE_CCK11 = 0x3, 294 RTW89_HW_RATE_OFDM6 = 0x4, 295 RTW89_HW_RATE_OFDM9 = 0x5, 296 RTW89_HW_RATE_OFDM12 = 0x6, 297 RTW89_HW_RATE_OFDM18 = 0x7, 298 RTW89_HW_RATE_OFDM24 = 0x8, 299 RTW89_HW_RATE_OFDM36 = 0x9, 300 RTW89_HW_RATE_OFDM48 = 0xA, 301 RTW89_HW_RATE_OFDM54 = 0xB, 302 RTW89_HW_RATE_MCS0 = 0x80, 303 RTW89_HW_RATE_MCS1 = 0x81, 304 RTW89_HW_RATE_MCS2 = 0x82, 305 RTW89_HW_RATE_MCS3 = 0x83, 306 RTW89_HW_RATE_MCS4 = 0x84, 307 RTW89_HW_RATE_MCS5 = 0x85, 308 RTW89_HW_RATE_MCS6 = 0x86, 309 RTW89_HW_RATE_MCS7 = 0x87, 310 RTW89_HW_RATE_MCS8 = 0x88, 311 RTW89_HW_RATE_MCS9 = 0x89, 312 RTW89_HW_RATE_MCS10 = 0x8A, 313 RTW89_HW_RATE_MCS11 = 0x8B, 314 RTW89_HW_RATE_MCS12 = 0x8C, 315 RTW89_HW_RATE_MCS13 = 0x8D, 316 RTW89_HW_RATE_MCS14 = 0x8E, 317 RTW89_HW_RATE_MCS15 = 0x8F, 318 RTW89_HW_RATE_MCS16 = 0x90, 319 RTW89_HW_RATE_MCS17 = 0x91, 320 RTW89_HW_RATE_MCS18 = 0x92, 321 RTW89_HW_RATE_MCS19 = 0x93, 322 RTW89_HW_RATE_MCS20 = 0x94, 323 RTW89_HW_RATE_MCS21 = 0x95, 324 RTW89_HW_RATE_MCS22 = 0x96, 325 RTW89_HW_RATE_MCS23 = 0x97, 326 RTW89_HW_RATE_MCS24 = 0x98, 327 RTW89_HW_RATE_MCS25 = 0x99, 328 RTW89_HW_RATE_MCS26 = 0x9A, 329 RTW89_HW_RATE_MCS27 = 0x9B, 330 RTW89_HW_RATE_MCS28 = 0x9C, 331 RTW89_HW_RATE_MCS29 = 0x9D, 332 RTW89_HW_RATE_MCS30 = 0x9E, 333 RTW89_HW_RATE_MCS31 = 0x9F, 334 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 335 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 336 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 337 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 338 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 339 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 340 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 341 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 342 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 343 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 344 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 345 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 346 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 347 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 348 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 349 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 350 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 351 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 352 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 353 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 354 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 355 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 356 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 357 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 358 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 359 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 360 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 361 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 362 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 363 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 364 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 365 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 366 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 367 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 368 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 369 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 370 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 371 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 372 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 373 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 374 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 375 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 376 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 377 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 378 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 379 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 380 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 381 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 382 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 383 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 384 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 385 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 386 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 387 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 388 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 389 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 390 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 391 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 392 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 393 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 394 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 395 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 396 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 397 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 398 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 399 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 400 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 401 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 402 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 403 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 404 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 405 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 406 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 407 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 408 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 409 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 410 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 411 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 412 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 413 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 414 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 415 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 416 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 417 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 418 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 419 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 420 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 421 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 422 423 RTW89_HW_RATE_V1_MCS0 = 0x100, 424 RTW89_HW_RATE_V1_MCS1 = 0x101, 425 RTW89_HW_RATE_V1_MCS2 = 0x102, 426 RTW89_HW_RATE_V1_MCS3 = 0x103, 427 RTW89_HW_RATE_V1_MCS4 = 0x104, 428 RTW89_HW_RATE_V1_MCS5 = 0x105, 429 RTW89_HW_RATE_V1_MCS6 = 0x106, 430 RTW89_HW_RATE_V1_MCS7 = 0x107, 431 RTW89_HW_RATE_V1_MCS8 = 0x108, 432 RTW89_HW_RATE_V1_MCS9 = 0x109, 433 RTW89_HW_RATE_V1_MCS10 = 0x10A, 434 RTW89_HW_RATE_V1_MCS11 = 0x10B, 435 RTW89_HW_RATE_V1_MCS12 = 0x10C, 436 RTW89_HW_RATE_V1_MCS13 = 0x10D, 437 RTW89_HW_RATE_V1_MCS14 = 0x10E, 438 RTW89_HW_RATE_V1_MCS15 = 0x10F, 439 RTW89_HW_RATE_V1_MCS16 = 0x110, 440 RTW89_HW_RATE_V1_MCS17 = 0x111, 441 RTW89_HW_RATE_V1_MCS18 = 0x112, 442 RTW89_HW_RATE_V1_MCS19 = 0x113, 443 RTW89_HW_RATE_V1_MCS20 = 0x114, 444 RTW89_HW_RATE_V1_MCS21 = 0x115, 445 RTW89_HW_RATE_V1_MCS22 = 0x116, 446 RTW89_HW_RATE_V1_MCS23 = 0x117, 447 RTW89_HW_RATE_V1_MCS24 = 0x118, 448 RTW89_HW_RATE_V1_MCS25 = 0x119, 449 RTW89_HW_RATE_V1_MCS26 = 0x11A, 450 RTW89_HW_RATE_V1_MCS27 = 0x11B, 451 RTW89_HW_RATE_V1_MCS28 = 0x11C, 452 RTW89_HW_RATE_V1_MCS29 = 0x11D, 453 RTW89_HW_RATE_V1_MCS30 = 0x11E, 454 RTW89_HW_RATE_V1_MCS31 = 0x11F, 455 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 456 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 467 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 468 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 479 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 480 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 491 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 492 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 503 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 504 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 515 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 516 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 527 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 528 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 539 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 540 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 551 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 552 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 567 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 568 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 581 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 582 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 595 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 596 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 609 610 RTW89_HW_RATE_NR, 611 RTW89_HW_RATE_INVAL, 612 613 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 614 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 615 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 616 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 617 }; 618 619 /* 2G channels, 620 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 621 */ 622 #define RTW89_2G_CH_NUM 14 623 624 /* 5G channels, 625 * 36, 38, 40, 42, 44, 46, 48, 50, 626 * 52, 54, 56, 58, 60, 62, 64, 627 * 100, 102, 104, 106, 108, 110, 112, 114, 628 * 116, 118, 120, 122, 124, 126, 128, 130, 629 * 132, 134, 136, 138, 140, 142, 144, 630 * 149, 151, 153, 155, 157, 159, 161, 163, 631 * 165, 167, 169, 171, 173, 175, 177 632 */ 633 #define RTW89_5G_CH_NUM 53 634 635 /* 6G channels, 636 * 1, 3, 5, 7, 9, 11, 13, 15, 637 * 17, 19, 21, 23, 25, 27, 29, 33, 638 * 35, 37, 39, 41, 43, 45, 47, 49, 639 * 51, 53, 55, 57, 59, 61, 65, 67, 640 * 69, 71, 73, 75, 77, 79, 81, 83, 641 * 85, 87, 89, 91, 93, 97, 99, 101, 642 * 103, 105, 107, 109, 111, 113, 115, 117, 643 * 119, 121, 123, 125, 129, 131, 133, 135, 644 * 137, 139, 141, 143, 145, 147, 149, 151, 645 * 153, 155, 157, 161, 163, 165, 167, 169, 646 * 171, 173, 175, 177, 179, 181, 183, 185, 647 * 187, 189, 193, 195, 197, 199, 201, 203, 648 * 205, 207, 209, 211, 213, 215, 217, 219, 649 * 221, 225, 227, 229, 231, 233, 235, 237, 650 * 239, 241, 243, 245, 247, 249, 251, 253, 651 */ 652 #define RTW89_6G_CH_NUM 120 653 654 enum rtw89_rate_section { 655 RTW89_RS_CCK, 656 RTW89_RS_OFDM, 657 RTW89_RS_MCS, /* for HT/VHT/HE */ 658 RTW89_RS_HEDCM, 659 RTW89_RS_OFFSET, 660 RTW89_RS_NUM, 661 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 662 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 663 }; 664 665 enum rtw89_rate_offset_indexes { 666 RTW89_RATE_OFFSET_HE, 667 RTW89_RATE_OFFSET_VHT, 668 RTW89_RATE_OFFSET_HT, 669 RTW89_RATE_OFFSET_OFDM, 670 RTW89_RATE_OFFSET_CCK, 671 RTW89_RATE_OFFSET_DLRU_EHT, 672 RTW89_RATE_OFFSET_DLRU_HE, 673 RTW89_RATE_OFFSET_EHT, 674 __RTW89_RATE_OFFSET_NUM, 675 676 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 677 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 678 }; 679 680 enum rtw89_rate_num { 681 RTW89_RATE_CCK_NUM = 4, 682 RTW89_RATE_OFDM_NUM = 8, 683 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 684 685 RTW89_RATE_MCS_NUM_AX = 12, 686 RTW89_RATE_MCS_NUM_BE = 16, 687 __RTW89_RATE_MCS_NUM = 16, 688 }; 689 690 enum rtw89_nss { 691 RTW89_NSS_1 = 0, 692 RTW89_NSS_2 = 1, 693 /* HE DCM only support 1ss and 2ss */ 694 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 695 RTW89_NSS_3 = 2, 696 RTW89_NSS_4 = 3, 697 RTW89_NSS_NUM, 698 }; 699 700 enum rtw89_ntx { 701 RTW89_1TX = 0, 702 RTW89_2TX = 1, 703 RTW89_NTX_NUM, 704 }; 705 706 enum rtw89_beamforming_type { 707 RTW89_NONBF = 0, 708 RTW89_BF = 1, 709 RTW89_BF_NUM, 710 }; 711 712 enum rtw89_ofdma_type { 713 RTW89_NON_OFDMA = 0, 714 RTW89_OFDMA = 1, 715 RTW89_OFDMA_NUM, 716 }; 717 718 enum rtw89_regulation_type { 719 RTW89_WW = 0, 720 RTW89_ETSI = 1, 721 RTW89_FCC = 2, 722 RTW89_MKK = 3, 723 RTW89_NA = 4, 724 RTW89_IC = 5, 725 RTW89_KCC = 6, 726 RTW89_ACMA = 7, 727 RTW89_NCC = 8, 728 RTW89_MEXICO = 9, 729 RTW89_CHILE = 10, 730 RTW89_UKRAINE = 11, 731 RTW89_CN = 12, 732 RTW89_QATAR = 13, 733 RTW89_UK = 14, 734 RTW89_THAILAND = 15, 735 RTW89_REGD_NUM, 736 }; 737 738 enum rtw89_reg_6ghz_power { 739 RTW89_REG_6GHZ_POWER_VLP = 0, 740 RTW89_REG_6GHZ_POWER_LPI = 1, 741 RTW89_REG_6GHZ_POWER_STD = 2, 742 743 NUM_OF_RTW89_REG_6GHZ_POWER, 744 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 745 }; 746 747 enum rtw89_fw_pkt_ofld_type { 748 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 749 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 750 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 751 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 752 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 753 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 754 RTW89_PKT_OFLD_TYPE_NDP = 6, 755 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 756 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 757 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 758 RTW89_PKT_OFLD_TYPE_NUM, 759 }; 760 761 struct rtw89_txpwr_byrate { 762 s8 cck[RTW89_RATE_CCK_NUM]; 763 s8 ofdm[RTW89_RATE_OFDM_NUM]; 764 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 765 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 766 s8 offset[__RTW89_RATE_OFFSET_NUM]; 767 s8 trap; 768 }; 769 770 struct rtw89_rate_desc { 771 enum rtw89_nss nss; 772 enum rtw89_rate_section rs; 773 enum rtw89_ofdma_type ofdma; 774 u8 idx; 775 }; 776 777 #define PHY_STS_HDR_LEN 8 778 #define RF_PATH_MAX 4 779 #define RTW89_MAX_PPDU_CNT 8 780 struct rtw89_rx_phy_ppdu { 781 void *buf; 782 u32 len; 783 u8 rssi_avg; 784 u8 rssi[RF_PATH_MAX]; 785 u8 mac_id; 786 u8 chan_idx; 787 u8 ie; 788 u16 rate; 789 struct { 790 bool has; 791 u8 avg_snr; 792 u8 evm_max; 793 u8 evm_min; 794 } ofdm; 795 bool to_self; 796 bool valid; 797 }; 798 799 enum rtw89_mac_idx { 800 RTW89_MAC_0 = 0, 801 RTW89_MAC_1 = 1, 802 RTW89_MAC_NUM, 803 }; 804 805 enum rtw89_phy_idx { 806 RTW89_PHY_0 = 0, 807 RTW89_PHY_1 = 1, 808 RTW89_PHY_MAX 809 }; 810 811 enum rtw89_sub_entity_idx { 812 RTW89_SUB_ENTITY_0 = 0, 813 RTW89_SUB_ENTITY_1 = 1, 814 815 NUM_OF_RTW89_SUB_ENTITY, 816 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 817 }; 818 819 enum rtw89_rf_path { 820 RF_PATH_A = 0, 821 RF_PATH_B = 1, 822 RF_PATH_C = 2, 823 RF_PATH_D = 3, 824 RF_PATH_AB, 825 RF_PATH_AC, 826 RF_PATH_AD, 827 RF_PATH_BC, 828 RF_PATH_BD, 829 RF_PATH_CD, 830 RF_PATH_ABC, 831 RF_PATH_ABD, 832 RF_PATH_ACD, 833 RF_PATH_BCD, 834 RF_PATH_ABCD, 835 }; 836 837 enum rtw89_rf_path_bit { 838 RF_A = BIT(0), 839 RF_B = BIT(1), 840 RF_C = BIT(2), 841 RF_D = BIT(3), 842 843 RF_AB = (RF_A | RF_B), 844 RF_AC = (RF_A | RF_C), 845 RF_AD = (RF_A | RF_D), 846 RF_BC = (RF_B | RF_C), 847 RF_BD = (RF_B | RF_D), 848 RF_CD = (RF_C | RF_D), 849 850 RF_ABC = (RF_A | RF_B | RF_C), 851 RF_ABD = (RF_A | RF_B | RF_D), 852 RF_ACD = (RF_A | RF_C | RF_D), 853 RF_BCD = (RF_B | RF_C | RF_D), 854 855 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 856 }; 857 858 enum rtw89_bandwidth { 859 RTW89_CHANNEL_WIDTH_20 = 0, 860 RTW89_CHANNEL_WIDTH_40 = 1, 861 RTW89_CHANNEL_WIDTH_80 = 2, 862 RTW89_CHANNEL_WIDTH_160 = 3, 863 RTW89_CHANNEL_WIDTH_320 = 4, 864 865 /* keep index order above */ 866 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 867 868 RTW89_CHANNEL_WIDTH_80_80 = 5, 869 RTW89_CHANNEL_WIDTH_5 = 6, 870 RTW89_CHANNEL_WIDTH_10 = 7, 871 }; 872 873 enum rtw89_ps_mode { 874 RTW89_PS_MODE_NONE = 0, 875 RTW89_PS_MODE_RFOFF = 1, 876 RTW89_PS_MODE_CLK_GATED = 2, 877 RTW89_PS_MODE_PWR_GATED = 3, 878 }; 879 880 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 881 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 882 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 883 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 884 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 885 886 enum rtw89_ru_bandwidth { 887 RTW89_RU26 = 0, 888 RTW89_RU52 = 1, 889 RTW89_RU106 = 2, 890 RTW89_RU52_26 = 3, 891 RTW89_RU106_26 = 4, 892 RTW89_RU_NUM, 893 }; 894 895 enum rtw89_sc_offset { 896 RTW89_SC_DONT_CARE = 0, 897 RTW89_SC_20_UPPER = 1, 898 RTW89_SC_20_LOWER = 2, 899 RTW89_SC_20_UPMOST = 3, 900 RTW89_SC_20_LOWEST = 4, 901 RTW89_SC_20_UP2X = 5, 902 RTW89_SC_20_LOW2X = 6, 903 RTW89_SC_20_UP3X = 7, 904 RTW89_SC_20_LOW3X = 8, 905 RTW89_SC_40_UPPER = 9, 906 RTW89_SC_40_LOWER = 10, 907 }; 908 909 enum rtw89_wow_flags { 910 RTW89_WOW_FLAG_EN_MAGIC_PKT, 911 RTW89_WOW_FLAG_EN_REKEY_PKT, 912 RTW89_WOW_FLAG_EN_DISCONNECT, 913 RTW89_WOW_FLAG_NUM, 914 }; 915 916 struct rtw89_chan { 917 u8 channel; 918 u8 primary_channel; 919 enum rtw89_band band_type; 920 enum rtw89_bandwidth band_width; 921 922 /* The follow-up are derived from the above. We must ensure that it 923 * is assigned correctly in rtw89_chan_create() if new one is added. 924 */ 925 u32 freq; 926 enum rtw89_subband subband_type; 927 enum rtw89_sc_offset pri_ch_idx; 928 u8 pri_sb_idx; 929 }; 930 931 struct rtw89_chan_rcd { 932 u8 prev_primary_channel; 933 enum rtw89_band prev_band_type; 934 bool band_changed; 935 }; 936 937 struct rtw89_channel_help_params { 938 u32 tx_en; 939 }; 940 941 struct rtw89_port_reg { 942 u32 port_cfg; 943 u32 tbtt_prohib; 944 u32 bcn_area; 945 u32 bcn_early; 946 u32 tbtt_early; 947 u32 tbtt_agg; 948 u32 bcn_space; 949 u32 bcn_forcetx; 950 u32 bcn_err_cnt; 951 u32 bcn_err_flag; 952 u32 dtim_ctrl; 953 u32 tbtt_shift; 954 u32 bcn_cnt_tmr; 955 u32 tsftr_l; 956 u32 tsftr_h; 957 u32 md_tsft; 958 u32 bss_color; 959 u32 mbssid; 960 u32 mbssid_drop; 961 u32 tsf_sync; 962 u32 ptcl_dbg; 963 u32 ptcl_dbg_info; 964 u32 bcn_drop_all; 965 u32 hiq_win[RTW89_PORT_NUM]; 966 }; 967 968 struct rtw89_txwd_body { 969 __le32 dword0; 970 __le32 dword1; 971 __le32 dword2; 972 __le32 dword3; 973 __le32 dword4; 974 __le32 dword5; 975 } __packed; 976 977 struct rtw89_txwd_body_v1 { 978 __le32 dword0; 979 __le32 dword1; 980 __le32 dword2; 981 __le32 dword3; 982 __le32 dword4; 983 __le32 dword5; 984 __le32 dword6; 985 __le32 dword7; 986 } __packed; 987 988 struct rtw89_txwd_body_v2 { 989 __le32 dword0; 990 __le32 dword1; 991 __le32 dword2; 992 __le32 dword3; 993 __le32 dword4; 994 __le32 dword5; 995 __le32 dword6; 996 __le32 dword7; 997 } __packed; 998 999 struct rtw89_txwd_info { 1000 __le32 dword0; 1001 __le32 dword1; 1002 __le32 dword2; 1003 __le32 dword3; 1004 __le32 dword4; 1005 __le32 dword5; 1006 } __packed; 1007 1008 struct rtw89_txwd_info_v2 { 1009 __le32 dword0; 1010 __le32 dword1; 1011 __le32 dword2; 1012 __le32 dword3; 1013 __le32 dword4; 1014 __le32 dword5; 1015 __le32 dword6; 1016 __le32 dword7; 1017 } __packed; 1018 1019 struct rtw89_rx_desc_info { 1020 u16 pkt_size; 1021 u8 pkt_type; 1022 u8 drv_info_size; 1023 u8 phy_rpt_size; 1024 u8 hdr_cnv_size; 1025 u8 shift; 1026 u8 wl_hd_iv_len; 1027 bool long_rxdesc; 1028 bool bb_sel; 1029 bool mac_info_valid; 1030 u16 data_rate; 1031 u8 gi_ltf; 1032 u8 bw; 1033 u32 free_run_cnt; 1034 u8 user_id; 1035 bool sr_en; 1036 u8 ppdu_cnt; 1037 u8 ppdu_type; 1038 bool icv_err; 1039 bool crc32_err; 1040 bool hw_dec; 1041 bool sw_dec; 1042 bool addr1_match; 1043 u8 frag; 1044 u16 seq; 1045 u8 frame_type; 1046 u8 rx_pl_id; 1047 bool addr_cam_valid; 1048 u8 addr_cam_id; 1049 u8 sec_cam_id; 1050 u8 mac_id; 1051 u16 offset; 1052 u16 rxd_len; 1053 bool ready; 1054 }; 1055 1056 struct rtw89_rxdesc_short { 1057 __le32 dword0; 1058 __le32 dword1; 1059 __le32 dword2; 1060 __le32 dword3; 1061 } __packed; 1062 1063 struct rtw89_rxdesc_short_v2 { 1064 __le32 dword0; 1065 __le32 dword1; 1066 __le32 dword2; 1067 __le32 dword3; 1068 __le32 dword4; 1069 __le32 dword5; 1070 } __packed; 1071 1072 struct rtw89_rxdesc_long { 1073 __le32 dword0; 1074 __le32 dword1; 1075 __le32 dword2; 1076 __le32 dword3; 1077 __le32 dword4; 1078 __le32 dword5; 1079 __le32 dword6; 1080 __le32 dword7; 1081 } __packed; 1082 1083 struct rtw89_rxdesc_long_v2 { 1084 __le32 dword0; 1085 __le32 dword1; 1086 __le32 dword2; 1087 __le32 dword3; 1088 __le32 dword4; 1089 __le32 dword5; 1090 __le32 dword6; 1091 __le32 dword7; 1092 __le32 dword8; 1093 __le32 dword9; 1094 } __packed; 1095 1096 struct rtw89_tx_desc_info { 1097 u16 pkt_size; 1098 u8 wp_offset; 1099 u8 mac_id; 1100 u8 qsel; 1101 u8 ch_dma; 1102 u8 hdr_llc_len; 1103 bool is_bmc; 1104 bool en_wd_info; 1105 bool wd_page; 1106 bool use_rate; 1107 bool dis_data_fb; 1108 bool tid_indicate; 1109 bool agg_en; 1110 bool bk; 1111 u8 ampdu_density; 1112 u8 ampdu_num; 1113 bool sec_en; 1114 u8 addr_info_nr; 1115 u8 sec_keyid; 1116 u8 sec_type; 1117 u8 sec_cam_idx; 1118 u8 sec_seq[6]; 1119 u16 data_rate; 1120 u16 data_retry_lowest_rate; 1121 bool fw_dl; 1122 u16 seq; 1123 bool a_ctrl_bsr; 1124 u8 hw_ssn_sel; 1125 #define RTW89_MGMT_HW_SSN_SEL 1 1126 u8 hw_seq_mode; 1127 #define RTW89_MGMT_HW_SEQ_MODE 1 1128 bool hiq; 1129 u8 port; 1130 bool er_cap; 1131 }; 1132 1133 struct rtw89_core_tx_request { 1134 enum rtw89_core_tx_type tx_type; 1135 1136 struct sk_buff *skb; 1137 struct ieee80211_vif *vif; 1138 struct ieee80211_sta *sta; 1139 struct rtw89_tx_desc_info desc_info; 1140 }; 1141 1142 struct rtw89_txq { 1143 struct list_head list; 1144 unsigned long flags; 1145 int wait_cnt; 1146 }; 1147 1148 struct rtw89_mac_ax_gnt { 1149 u8 gnt_bt_sw_en; 1150 u8 gnt_bt; 1151 u8 gnt_wl_sw_en; 1152 u8 gnt_wl; 1153 } __packed; 1154 1155 struct rtw89_mac_ax_wl_act { 1156 u8 wlan_act_en; 1157 u8 wlan_act; 1158 }; 1159 1160 #define RTW89_MAC_AX_COEX_GNT_NR 2 1161 struct rtw89_mac_ax_coex_gnt { 1162 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1163 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1164 }; 1165 1166 enum rtw89_btc_ncnt { 1167 BTC_NCNT_POWER_ON = 0x0, 1168 BTC_NCNT_POWER_OFF, 1169 BTC_NCNT_INIT_COEX, 1170 BTC_NCNT_SCAN_START, 1171 BTC_NCNT_SCAN_FINISH, 1172 BTC_NCNT_SPECIAL_PACKET, 1173 BTC_NCNT_SWITCH_BAND, 1174 BTC_NCNT_RFK_TIMEOUT, 1175 BTC_NCNT_SHOW_COEX_INFO, 1176 BTC_NCNT_ROLE_INFO, 1177 BTC_NCNT_CONTROL, 1178 BTC_NCNT_RADIO_STATE, 1179 BTC_NCNT_CUSTOMERIZE, 1180 BTC_NCNT_WL_RFK, 1181 BTC_NCNT_WL_STA, 1182 BTC_NCNT_FWINFO, 1183 BTC_NCNT_TIMER, 1184 BTC_NCNT_NUM 1185 }; 1186 1187 enum rtw89_btc_btinfo { 1188 BTC_BTINFO_L0 = 0, 1189 BTC_BTINFO_L1, 1190 BTC_BTINFO_L2, 1191 BTC_BTINFO_L3, 1192 BTC_BTINFO_H0, 1193 BTC_BTINFO_H1, 1194 BTC_BTINFO_H2, 1195 BTC_BTINFO_H3, 1196 BTC_BTINFO_MAX 1197 }; 1198 1199 enum rtw89_btc_dcnt { 1200 BTC_DCNT_RUN = 0x0, 1201 BTC_DCNT_CX_RUNINFO, 1202 BTC_DCNT_RPT, 1203 BTC_DCNT_RPT_HANG, 1204 BTC_DCNT_CYCLE, 1205 BTC_DCNT_CYCLE_HANG, 1206 BTC_DCNT_W1, 1207 BTC_DCNT_W1_HANG, 1208 BTC_DCNT_B1, 1209 BTC_DCNT_B1_HANG, 1210 BTC_DCNT_TDMA_NONSYNC, 1211 BTC_DCNT_SLOT_NONSYNC, 1212 BTC_DCNT_BTCNT_HANG, 1213 BTC_DCNT_WL_SLOT_DRIFT, 1214 BTC_DCNT_WL_STA_LAST, 1215 BTC_DCNT_BT_SLOT_DRIFT, 1216 BTC_DCNT_BT_SLOT_FLOOD, 1217 BTC_DCNT_FDDT_TRIG, 1218 BTC_DCNT_E2G, 1219 BTC_DCNT_E2G_HANG, 1220 BTC_DCNT_NUM 1221 }; 1222 1223 enum rtw89_btc_wl_state_cnt { 1224 BTC_WCNT_SCANAP = 0x0, 1225 BTC_WCNT_DHCP, 1226 BTC_WCNT_EAPOL, 1227 BTC_WCNT_ARP, 1228 BTC_WCNT_SCBDUPDATE, 1229 BTC_WCNT_RFK_REQ, 1230 BTC_WCNT_RFK_GO, 1231 BTC_WCNT_RFK_REJECT, 1232 BTC_WCNT_RFK_TIMEOUT, 1233 BTC_WCNT_CH_UPDATE, 1234 BTC_WCNT_DBCC_ALL_2G, 1235 BTC_WCNT_DBCC_CHG, 1236 BTC_WCNT_RX_OK_LAST, 1237 BTC_WCNT_RX_OK_LAST2S, 1238 BTC_WCNT_RX_ERR_LAST, 1239 BTC_WCNT_RX_ERR_LAST2S, 1240 BTC_WCNT_RX_LAST, 1241 BTC_WCNT_NUM 1242 }; 1243 1244 enum rtw89_btc_bt_state_cnt { 1245 BTC_BCNT_RETRY = 0x0, 1246 BTC_BCNT_REINIT, 1247 BTC_BCNT_REENABLE, 1248 BTC_BCNT_SCBDREAD, 1249 BTC_BCNT_RELINK, 1250 BTC_BCNT_IGNOWL, 1251 BTC_BCNT_INQPAG, 1252 BTC_BCNT_INQ, 1253 BTC_BCNT_PAGE, 1254 BTC_BCNT_ROLESW, 1255 BTC_BCNT_AFH, 1256 BTC_BCNT_INFOUPDATE, 1257 BTC_BCNT_INFOSAME, 1258 BTC_BCNT_SCBDUPDATE, 1259 BTC_BCNT_HIPRI_TX, 1260 BTC_BCNT_HIPRI_RX, 1261 BTC_BCNT_LOPRI_TX, 1262 BTC_BCNT_LOPRI_RX, 1263 BTC_BCNT_POLUT, 1264 BTC_BCNT_RATECHG, 1265 BTC_BCNT_NUM 1266 }; 1267 1268 enum rtw89_btc_bt_profile { 1269 BTC_BT_NOPROFILE = 0, 1270 BTC_BT_HFP = BIT(0), 1271 BTC_BT_HID = BIT(1), 1272 BTC_BT_A2DP = BIT(2), 1273 BTC_BT_PAN = BIT(3), 1274 BTC_PROFILE_MAX = 4, 1275 }; 1276 1277 struct rtw89_btc_ant_info { 1278 u8 type; /* shared, dedicated */ 1279 u8 num; 1280 u8 isolation; 1281 1282 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1283 u8 diversity: 1; 1284 u8 btg_pos: 2; 1285 u8 stream_cnt: 4; 1286 }; 1287 1288 struct rtw89_btc_ant_info_v7 { 1289 u8 type; /* shared, dedicated(non-shared) */ 1290 u8 num; /* antenna count */ 1291 u8 isolation; 1292 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1293 1294 u8 diversity; /* only for wifi use 1-antenna */ 1295 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1296 u8 stream_cnt; /* spatial_stream count */ 1297 u8 rsvd; 1298 } __packed; 1299 1300 enum rtw89_tfc_dir { 1301 RTW89_TFC_UL, 1302 RTW89_TFC_DL, 1303 }; 1304 1305 struct rtw89_btc_wl_smap { 1306 u32 busy: 1; 1307 u32 scan: 1; 1308 u32 connecting: 1; 1309 u32 roaming: 1; 1310 u32 _4way: 1; 1311 u32 rf_off: 1; 1312 u32 lps: 2; 1313 u32 ips: 1; 1314 u32 init_ok: 1; 1315 u32 traffic_dir : 2; 1316 u32 rf_off_pre: 1; 1317 u32 lps_pre: 2; 1318 }; 1319 1320 enum rtw89_tfc_lv { 1321 RTW89_TFC_IDLE, 1322 RTW89_TFC_ULTRA_LOW, 1323 RTW89_TFC_LOW, 1324 RTW89_TFC_MID, 1325 RTW89_TFC_HIGH, 1326 }; 1327 1328 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1329 DECLARE_EWMA(tp, 10, 2); 1330 1331 struct rtw89_traffic_stats { 1332 /* units in bytes */ 1333 u64 tx_unicast; 1334 u64 rx_unicast; 1335 u32 tx_avg_len; 1336 u32 rx_avg_len; 1337 1338 /* count for packets */ 1339 u64 tx_cnt; 1340 u64 rx_cnt; 1341 1342 /* units in Mbps */ 1343 u32 tx_throughput; 1344 u32 rx_throughput; 1345 u32 tx_throughput_raw; 1346 u32 rx_throughput_raw; 1347 1348 u32 rx_tf_acc; 1349 u32 rx_tf_periodic; 1350 1351 enum rtw89_tfc_lv tx_tfc_lv; 1352 enum rtw89_tfc_lv rx_tfc_lv; 1353 struct ewma_tp tx_ewma_tp; 1354 struct ewma_tp rx_ewma_tp; 1355 1356 u16 tx_rate; 1357 u16 rx_rate; 1358 }; 1359 1360 struct rtw89_btc_chdef { 1361 u8 center_ch; 1362 u8 band; 1363 u8 chan; 1364 enum rtw89_sc_offset offset; 1365 enum rtw89_bandwidth bw; 1366 }; 1367 1368 struct rtw89_btc_statistic { 1369 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1370 struct rtw89_traffic_stats traffic; 1371 }; 1372 1373 #define BTC_WL_RSSI_THMAX 4 1374 1375 struct rtw89_btc_wl_link_info { 1376 struct rtw89_btc_chdef chdef; 1377 struct rtw89_btc_statistic stat; 1378 enum rtw89_tfc_dir dir; 1379 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1380 u8 mac_addr[ETH_ALEN]; 1381 u8 busy; 1382 u8 ch; 1383 u8 bw; 1384 u8 band; 1385 u8 role; 1386 u8 pid; 1387 u8 phy; 1388 u8 dtim_period; 1389 u8 mode; 1390 u8 tx_1ss_limit; 1391 1392 u8 mac_id; 1393 u8 tx_retry; 1394 1395 u32 bcn_period; 1396 u32 busy_t; 1397 u32 tx_time; 1398 u32 client_cnt; 1399 u32 rx_rate_drop_cnt; 1400 u32 noa_duration; 1401 1402 u32 active: 1; 1403 u32 noa: 1; 1404 u32 client_ps: 1; 1405 u32 connected: 2; 1406 }; 1407 1408 union rtw89_btc_wl_state_map { 1409 u32 val; 1410 struct rtw89_btc_wl_smap map; 1411 }; 1412 1413 struct rtw89_btc_bt_hfp_desc { 1414 u32 exist: 1; 1415 u32 type: 2; 1416 u32 rsvd: 29; 1417 }; 1418 1419 struct rtw89_btc_bt_hid_desc { 1420 u32 exist: 1; 1421 u32 slot_info: 2; 1422 u32 pair_cnt: 2; 1423 u32 type: 8; 1424 u32 rsvd: 19; 1425 }; 1426 1427 struct rtw89_btc_bt_a2dp_desc { 1428 u8 exist: 1; 1429 u8 exist_last: 1; 1430 u8 play_latency: 1; 1431 u8 type: 3; 1432 u8 active: 1; 1433 u8 sink: 1; 1434 1435 u8 bitpool; 1436 u16 vendor_id; 1437 u32 device_name; 1438 u32 flush_time; 1439 }; 1440 1441 struct rtw89_btc_bt_pan_desc { 1442 u32 exist: 1; 1443 u32 type: 1; 1444 u32 active: 1; 1445 u32 rsvd: 29; 1446 }; 1447 1448 struct rtw89_btc_bt_rfk_info { 1449 u32 run: 1; 1450 u32 req: 1; 1451 u32 timeout: 1; 1452 u32 rsvd: 29; 1453 }; 1454 1455 union rtw89_btc_bt_rfk_info_map { 1456 u32 val; 1457 struct rtw89_btc_bt_rfk_info map; 1458 }; 1459 1460 struct rtw89_btc_bt_ver_info { 1461 u32 fw_coex; /* match with which coex_ver */ 1462 u32 fw; 1463 }; 1464 1465 struct rtw89_btc_bool_sta_chg { 1466 u32 now: 1; 1467 u32 last: 1; 1468 u32 remain: 1; 1469 u32 srvd: 29; 1470 }; 1471 1472 struct rtw89_btc_u8_sta_chg { 1473 u8 now; 1474 u8 last; 1475 u8 remain; 1476 u8 rsvd; 1477 }; 1478 1479 struct rtw89_btc_wl_scan_info { 1480 u8 band[RTW89_PHY_MAX]; 1481 u8 phy_map; 1482 u8 rsvd; 1483 }; 1484 1485 struct rtw89_btc_wl_dbcc_info { 1486 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1487 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1488 u8 real_band[RTW89_PHY_MAX]; 1489 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1490 }; 1491 1492 struct rtw89_btc_wl_active_role { 1493 u8 connected: 1; 1494 u8 pid: 3; 1495 u8 phy: 1; 1496 u8 noa: 1; 1497 u8 band: 2; 1498 1499 u8 client_ps: 1; 1500 u8 bw: 7; 1501 1502 u8 role; 1503 u8 ch; 1504 1505 u16 tx_lvl; 1506 u16 rx_lvl; 1507 u16 tx_rate; 1508 u16 rx_rate; 1509 }; 1510 1511 struct rtw89_btc_wl_active_role_v1 { 1512 u8 connected: 1; 1513 u8 pid: 3; 1514 u8 phy: 1; 1515 u8 noa: 1; 1516 u8 band: 2; 1517 1518 u8 client_ps: 1; 1519 u8 bw: 7; 1520 1521 u8 role; 1522 u8 ch; 1523 1524 u16 tx_lvl; 1525 u16 rx_lvl; 1526 u16 tx_rate; 1527 u16 rx_rate; 1528 1529 u32 noa_duration; /* ms */ 1530 }; 1531 1532 struct rtw89_btc_wl_active_role_v2 { 1533 u8 connected: 1; 1534 u8 pid: 3; 1535 u8 phy: 1; 1536 u8 noa: 1; 1537 u8 band: 2; 1538 1539 u8 client_ps: 1; 1540 u8 bw: 7; 1541 1542 u8 role; 1543 u8 ch; 1544 1545 u32 noa_duration; /* ms */ 1546 }; 1547 1548 struct rtw89_btc_wl_role_info_bpos { 1549 u16 none: 1; 1550 u16 station: 1; 1551 u16 ap: 1; 1552 u16 vap: 1; 1553 u16 adhoc: 1; 1554 u16 adhoc_master: 1; 1555 u16 mesh: 1; 1556 u16 moniter: 1; 1557 u16 p2p_device: 1; 1558 u16 p2p_gc: 1; 1559 u16 p2p_go: 1; 1560 u16 nan: 1; 1561 }; 1562 1563 struct rtw89_btc_wl_scc_ctrl { 1564 u8 null_role1; 1565 u8 null_role2; 1566 u8 ebt_null; /* if tx null at EBT slot */ 1567 }; 1568 1569 union rtw89_btc_wl_role_info_map { 1570 u16 val; 1571 struct rtw89_btc_wl_role_info_bpos role; 1572 }; 1573 1574 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1575 u8 connect_cnt; 1576 u8 link_mode; 1577 union rtw89_btc_wl_role_info_map role_map; 1578 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1579 }; 1580 1581 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1582 u8 connect_cnt; 1583 u8 link_mode; 1584 union rtw89_btc_wl_role_info_map role_map; 1585 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1586 u32 mrole_type; /* btc_wl_mrole_type */ 1587 u32 mrole_noa_duration; /* ms */ 1588 1589 u32 dbcc_en: 1; 1590 u32 dbcc_chg: 1; 1591 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1592 u32 link_mode_chg: 1; 1593 u32 rsvd: 27; 1594 }; 1595 1596 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1597 u8 connect_cnt; 1598 u8 link_mode; 1599 union rtw89_btc_wl_role_info_map role_map; 1600 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1601 u32 mrole_type; /* btc_wl_mrole_type */ 1602 u32 mrole_noa_duration; /* ms */ 1603 1604 u32 dbcc_en: 1; 1605 u32 dbcc_chg: 1; 1606 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1607 u32 link_mode_chg: 1; 1608 u32 rsvd: 27; 1609 }; 1610 1611 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1612 u8 connected; 1613 u8 pid; 1614 u8 phy; 1615 u8 noa; 1616 1617 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1618 u8 active; /* 0:rlink is under doze */ 1619 u8 bw; /* enum channel_width */ 1620 u8 role; /*enum role_type */ 1621 1622 u8 ch; 1623 u8 noa_dur; /* ms */ 1624 u8 client_cnt; /* for Role = P2P-Go/AP */ 1625 u8 mode; /* wifi protocol */ 1626 } __packed; 1627 1628 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1629 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1630 u8 connect_cnt; 1631 u8 link_mode; 1632 u8 link_mode_chg; 1633 u8 p2p_2g; 1634 1635 u8 pta_req_band; 1636 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1637 u8 dbcc_chg; 1638 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1639 1640 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1641 1642 u32 role_map; 1643 u32 mrole_type; /* btc_wl_mrole_type */ 1644 u32 mrole_noa_duration; /* ms */ 1645 } __packed; 1646 1647 struct rtw89_btc_wl_ver_info { 1648 u32 fw_coex; /* match with which coex_ver */ 1649 u32 fw; 1650 u32 mac; 1651 u32 bb; 1652 u32 rf; 1653 }; 1654 1655 struct rtw89_btc_wl_afh_info { 1656 u8 en; 1657 u8 ch; 1658 u8 bw; 1659 u8 rsvd; 1660 } __packed; 1661 1662 struct rtw89_btc_wl_rfk_info { 1663 u32 state: 2; 1664 u32 path_map: 4; 1665 u32 phy_map: 2; 1666 u32 band: 2; 1667 u32 type: 8; 1668 u32 rsvd: 14; 1669 }; 1670 1671 struct rtw89_btc_bt_smap { 1672 u32 connect: 1; 1673 u32 ble_connect: 1; 1674 u32 acl_busy: 1; 1675 u32 sco_busy: 1; 1676 u32 mesh_busy: 1; 1677 u32 inq_pag: 1; 1678 }; 1679 1680 union rtw89_btc_bt_state_map { 1681 u32 val; 1682 struct rtw89_btc_bt_smap map; 1683 }; 1684 1685 #define BTC_BT_RSSI_THMAX 4 1686 #define BTC_BT_AFH_GROUP 12 1687 #define BTC_BT_AFH_LE_GROUP 5 1688 1689 struct rtw89_btc_bt_link_info { 1690 struct rtw89_btc_u8_sta_chg profile_cnt; 1691 struct rtw89_btc_bool_sta_chg multi_link; 1692 struct rtw89_btc_bool_sta_chg relink; 1693 struct rtw89_btc_bt_hfp_desc hfp_desc; 1694 struct rtw89_btc_bt_hid_desc hid_desc; 1695 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1696 struct rtw89_btc_bt_pan_desc pan_desc; 1697 union rtw89_btc_bt_state_map status; 1698 1699 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1700 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1701 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1702 u8 afh_map[BTC_BT_AFH_GROUP]; 1703 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1704 1705 u32 role_sw: 1; 1706 u32 slave_role: 1; 1707 u32 afh_update: 1; 1708 u32 cqddr: 1; 1709 u32 rssi: 8; 1710 u32 tx_3m: 1; 1711 u32 rsvd: 19; 1712 }; 1713 1714 struct rtw89_btc_3rdcx_info { 1715 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1716 u8 hw_coex; 1717 u16 rsvd; 1718 }; 1719 1720 struct rtw89_btc_dm_emap { 1721 u32 init: 1; 1722 u32 pta_owner: 1; 1723 u32 wl_rfk_timeout: 1; 1724 u32 bt_rfk_timeout: 1; 1725 u32 wl_fw_hang: 1; 1726 u32 cycle_hang: 1; 1727 u32 w1_hang: 1; 1728 u32 b1_hang: 1; 1729 u32 tdma_no_sync: 1; 1730 u32 slot_no_sync: 1; 1731 u32 wl_slot_drift: 1; 1732 u32 bt_slot_drift: 1; 1733 u32 role_num_mismatch: 1; 1734 u32 null1_tx_late: 1; 1735 u32 bt_afh_conflict: 1; 1736 u32 bt_leafh_conflict: 1; 1737 u32 bt_slot_flood: 1; 1738 u32 wl_e2g_hang: 1; 1739 u32 wl_ver_mismatch: 1; 1740 u32 bt_ver_mismatch: 1; 1741 u32 rfe_type0: 1; 1742 u32 h2c_buffer_over: 1; 1743 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1744 u32 wl_no_sta_ntfy: 1; 1745 1746 u32 h2c_bmap_mismatch: 1; 1747 u32 c2h_bmap_mismatch: 1; 1748 u32 h2c_struct_invalid: 1; 1749 u32 c2h_struct_invalid: 1; 1750 u32 h2c_c2h_buffer_mismatch: 1; 1751 }; 1752 1753 union rtw89_btc_dm_error_map { 1754 u32 val; 1755 struct rtw89_btc_dm_emap map; 1756 }; 1757 1758 struct rtw89_btc_rf_para { 1759 u32 tx_pwr_freerun; 1760 u32 rx_gain_freerun; 1761 u32 tx_pwr_perpkt; 1762 u32 rx_gain_perpkt; 1763 }; 1764 1765 struct rtw89_btc_wl_nhm { 1766 u8 instant_wl_nhm_dbm; 1767 u8 instant_wl_nhm_per_mhz; 1768 u16 valid_record_times; 1769 s8 record_pwr[16]; 1770 u8 record_ratio[16]; 1771 s8 pwr; /* dbm_per_MHz */ 1772 u8 ratio; 1773 u8 current_status; 1774 u8 refresh; 1775 bool start_flag; 1776 s8 pwr_max; 1777 s8 pwr_min; 1778 }; 1779 1780 struct rtw89_btc_wl_info { 1781 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1782 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1783 struct rtw89_btc_wl_rfk_info rfk_info; 1784 struct rtw89_btc_wl_ver_info ver_info; 1785 struct rtw89_btc_wl_afh_info afh_info; 1786 struct rtw89_btc_wl_role_info role_info; 1787 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1788 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1789 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1790 struct rtw89_btc_wl_scan_info scan_info; 1791 struct rtw89_btc_wl_dbcc_info dbcc_info; 1792 struct rtw89_btc_rf_para rf_para; 1793 struct rtw89_btc_wl_nhm nhm; 1794 union rtw89_btc_wl_state_map status; 1795 1796 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1797 u8 rssi_level; 1798 u8 cn_report; 1799 u8 coex_mode; 1800 u8 pta_req_mac; 1801 1802 bool is_5g_hi_channel; 1803 bool pta_reg_mac_chg; 1804 bool bg_mode; 1805 bool scbd_change; 1806 u32 scbd; 1807 }; 1808 1809 struct rtw89_btc_module { 1810 struct rtw89_btc_ant_info ant; 1811 u8 rfe_type; 1812 u8 cv; 1813 1814 u8 bt_solo: 1; 1815 u8 bt_pos: 1; 1816 u8 switch_type: 1; 1817 u8 wa_type: 3; 1818 1819 u8 kt_ver_adie; 1820 }; 1821 1822 struct rtw89_btc_module_v7 { 1823 u8 rfe_type; 1824 u8 kt_ver; 1825 u8 bt_solo; 1826 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1827 1828 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1829 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1830 u8 kt_ver_adie; 1831 u8 rsvd; 1832 1833 struct rtw89_btc_ant_info_v7 ant; 1834 } __packed; 1835 1836 union rtw89_btc_module_info { 1837 struct rtw89_btc_module md; 1838 struct rtw89_btc_module_v7 md_v7; 1839 }; 1840 1841 #define RTW89_BTC_DM_MAXSTEP 30 1842 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1843 1844 struct rtw89_btc_dm_step { 1845 u16 step[RTW89_BTC_DM_MAXSTEP]; 1846 u8 step_pos; 1847 bool step_ov; 1848 }; 1849 1850 struct rtw89_btc_init_info { 1851 struct rtw89_btc_module module; 1852 u8 wl_guard_ch; 1853 1854 u8 wl_only: 1; 1855 u8 wl_init_ok: 1; 1856 u8 dbcc_en: 1; 1857 u8 cx_other: 1; 1858 u8 bt_only: 1; 1859 1860 u16 rsvd; 1861 }; 1862 1863 struct rtw89_btc_init_info_v7 { 1864 u8 wl_guard_ch; 1865 u8 wl_only; 1866 u8 wl_init_ok; 1867 u8 rsvd3; 1868 1869 u8 cx_other; 1870 u8 bt_only; 1871 u8 pta_mode; 1872 u8 pta_direction; 1873 1874 struct rtw89_btc_module_v7 module; 1875 } __packed; 1876 1877 union rtw89_btc_init_info_u { 1878 struct rtw89_btc_init_info init; 1879 struct rtw89_btc_init_info_v7 init_v7; 1880 }; 1881 1882 struct rtw89_btc_wl_tx_limit_para { 1883 u16 enable; 1884 u32 tx_time; /* unit: us */ 1885 u16 tx_retry; 1886 }; 1887 1888 enum rtw89_btc_bt_scan_type { 1889 BTC_SCAN_INQ = 0, 1890 BTC_SCAN_PAGE, 1891 BTC_SCAN_BLE, 1892 BTC_SCAN_INIT, 1893 BTC_SCAN_TV, 1894 BTC_SCAN_ADV, 1895 BTC_SCAN_MAX1, 1896 }; 1897 1898 enum rtw89_btc_ble_scan_type { 1899 CXSCAN_BG = 0, 1900 CXSCAN_INIT, 1901 CXSCAN_LE, 1902 CXSCAN_MAX 1903 }; 1904 1905 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1906 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1907 1908 struct rtw89_btc_bt_scan_info_v1 { 1909 __le16 win; 1910 __le16 intvl; 1911 __le32 flags; 1912 } __packed; 1913 1914 struct rtw89_btc_bt_scan_info_v2 { 1915 __le16 win; 1916 __le16 intvl; 1917 } __packed; 1918 1919 struct rtw89_btc_fbtc_btscan_v1 { 1920 u8 fver; /* btc_ver::fcxbtscan */ 1921 u8 rsvd; 1922 __le16 rsvd2; 1923 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1924 } __packed; 1925 1926 struct rtw89_btc_fbtc_btscan_v2 { 1927 u8 fver; /* btc_ver::fcxbtscan */ 1928 u8 type; 1929 __le16 rsvd2; 1930 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1931 } __packed; 1932 1933 union rtw89_btc_fbtc_btscan { 1934 struct rtw89_btc_fbtc_btscan_v1 v1; 1935 struct rtw89_btc_fbtc_btscan_v2 v2; 1936 }; 1937 1938 struct rtw89_btc_bt_info { 1939 struct rtw89_btc_bt_link_info link_info; 1940 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1941 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1942 struct rtw89_btc_bt_ver_info ver_info; 1943 struct rtw89_btc_bool_sta_chg enable; 1944 struct rtw89_btc_bool_sta_chg inq_pag; 1945 struct rtw89_btc_rf_para rf_para; 1946 union rtw89_btc_bt_rfk_info_map rfk_info; 1947 1948 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1949 u8 rssi_level; 1950 1951 u32 scbd; 1952 u32 feature; 1953 1954 u32 mbx_avl: 1; 1955 u32 whql_test: 1; 1956 u32 igno_wl: 1; 1957 u32 reinit: 1; 1958 u32 ble_scan_en: 1; 1959 u32 btg_type: 1; 1960 u32 inq: 1; 1961 u32 pag: 1; 1962 u32 run_patch_code: 1; 1963 u32 hi_lna_rx: 1; 1964 u32 scan_rx_low_pri: 1; 1965 u32 scan_info_update: 1; 1966 u32 lna_constrain: 3; 1967 u32 rsvd: 17; 1968 }; 1969 1970 struct rtw89_btc_cx { 1971 struct rtw89_btc_wl_info wl; 1972 struct rtw89_btc_bt_info bt; 1973 struct rtw89_btc_3rdcx_info other; 1974 u32 state_map; 1975 u32 cnt_bt[BTC_BCNT_NUM]; 1976 u32 cnt_wl[BTC_WCNT_NUM]; 1977 }; 1978 1979 struct rtw89_btc_fbtc_tdma { 1980 u8 type; /* btc_ver::fcxtdma */ 1981 u8 rxflctrl; 1982 u8 txpause; 1983 u8 wtgle_n; 1984 u8 leak_n; 1985 u8 ext_ctrl; 1986 u8 rxflctrl_role; 1987 u8 option_ctrl; 1988 } __packed; 1989 1990 struct rtw89_btc_fbtc_tdma_v3 { 1991 u8 fver; /* btc_ver::fcxtdma */ 1992 u8 rsvd; 1993 __le16 rsvd1; 1994 struct rtw89_btc_fbtc_tdma tdma; 1995 } __packed; 1996 1997 union rtw89_btc_fbtc_tdma_le32 { 1998 struct rtw89_btc_fbtc_tdma v1; 1999 struct rtw89_btc_fbtc_tdma_v3 v3; 2000 }; 2001 2002 #define CXMREG_MAX 30 2003 #define CXMREG_MAX_V2 20 2004 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2005 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2006 2007 enum rtw89_btc_bt_sta_counter { 2008 BTC_BCNT_RFK_REQ = 0, 2009 BTC_BCNT_RFK_GO = 1, 2010 BTC_BCNT_RFK_REJECT = 2, 2011 BTC_BCNT_RFK_FAIL = 3, 2012 BTC_BCNT_RFK_TIMEOUT = 4, 2013 BTC_BCNT_HI_TX = 5, 2014 BTC_BCNT_HI_RX = 6, 2015 BTC_BCNT_LO_TX = 7, 2016 BTC_BCNT_LO_RX = 8, 2017 BTC_BCNT_POLLUTED = 9, 2018 BTC_BCNT_STA_MAX 2019 }; 2020 2021 enum rtw89_btc_bt_sta_counter_v105 { 2022 BTC_BCNT_RFK_REQ_V105 = 0, 2023 BTC_BCNT_HI_TX_V105 = 1, 2024 BTC_BCNT_HI_RX_V105 = 2, 2025 BTC_BCNT_LO_TX_V105 = 3, 2026 BTC_BCNT_LO_RX_V105 = 4, 2027 BTC_BCNT_POLLUTED_V105 = 5, 2028 BTC_BCNT_STA_MAX_V105 2029 }; 2030 2031 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2032 u16 fver; /* btc_ver::fcxbtcrpt */ 2033 u16 rpt_cnt; /* tmr counters */ 2034 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2035 u32 wl_fw_cx_offload; 2036 u32 wl_fw_ver; 2037 u32 rpt_enable; 2038 u32 rpt_para; /* ms */ 2039 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2040 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2041 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2042 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2043 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2044 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2045 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2046 u32 c2h_cnt; /* fw send c2h counter */ 2047 u32 h2c_cnt; /* fw recv h2c counter */ 2048 } __packed; 2049 2050 struct rtw89_btc_fbtc_rpt_ctrl_info { 2051 __le32 cnt; /* fw report counter */ 2052 __le32 en; /* report map */ 2053 __le32 para; /* not used */ 2054 2055 __le32 cnt_c2h; /* fw send c2h counter */ 2056 __le32 cnt_h2c; /* fw recv h2c counter */ 2057 __le32 len_c2h; /* The total length of the last C2H */ 2058 2059 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2060 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2061 } __packed; 2062 2063 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2064 __le32 cx_ver; /* match which driver's coex version */ 2065 __le32 fw_ver; 2066 __le32 en; /* report map */ 2067 2068 __le16 cnt; /* fw report counter */ 2069 __le16 cnt_c2h; /* fw send c2h counter */ 2070 __le16 cnt_h2c; /* fw recv h2c counter */ 2071 __le16 len_c2h; /* The total length of the last C2H */ 2072 2073 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2074 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2075 } __packed; 2076 2077 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2078 __le32 cx_ver; /* match which driver's coex version */ 2079 __le32 cx_offload; 2080 __le32 fw_ver; 2081 } __packed; 2082 2083 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2084 __le32 cnt_empty; /* a2dp empty count */ 2085 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2086 __le32 cnt_tx; 2087 __le32 cnt_ack; 2088 __le32 cnt_nack; 2089 } __packed; 2090 2091 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2092 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2093 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2094 __le32 cnt_recv; /* fw recv mailbox counter */ 2095 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2096 } __packed; 2097 2098 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2099 u8 fver; 2100 u8 rsvd; 2101 __le16 rsvd1; 2102 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2103 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2104 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2105 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2106 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2107 } __packed; 2108 2109 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2110 u8 fver; 2111 u8 rsvd; 2112 __le16 rsvd1; 2113 2114 u8 gnt_val[RTW89_PHY_MAX][4]; 2115 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2116 2117 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2118 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2119 } __packed; 2120 2121 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2122 u8 fver; 2123 u8 rsvd; 2124 __le16 rsvd1; 2125 2126 u8 gnt_val[RTW89_PHY_MAX][4]; 2127 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2128 2129 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2130 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2131 } __packed; 2132 2133 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2134 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2135 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2136 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2137 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2138 }; 2139 2140 enum rtw89_fbtc_ext_ctrl_type { 2141 CXECTL_OFF = 0x0, /* tdma off */ 2142 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2143 CXECTL_EXT = 0x2, 2144 CXECTL_MAX 2145 }; 2146 2147 union rtw89_btc_fbtc_rxflct { 2148 u8 val; 2149 u8 type: 3; 2150 u8 tgln_n: 5; 2151 }; 2152 2153 enum rtw89_btc_cxst_state { 2154 CXST_OFF = 0x0, 2155 CXST_B2W = 0x1, 2156 CXST_W1 = 0x2, 2157 CXST_W2 = 0x3, 2158 CXST_W2B = 0x4, 2159 CXST_B1 = 0x5, 2160 CXST_B2 = 0x6, 2161 CXST_B3 = 0x7, 2162 CXST_B4 = 0x8, 2163 CXST_LK = 0x9, 2164 CXST_BLK = 0xa, 2165 CXST_E2G = 0xb, 2166 CXST_E5G = 0xc, 2167 CXST_EBT = 0xd, 2168 CXST_ENULL = 0xe, 2169 CXST_WLK = 0xf, 2170 CXST_W1FDD = 0x10, 2171 CXST_B1FDD = 0x11, 2172 CXST_MAX = 0x12, 2173 }; 2174 2175 enum rtw89_btc_cxevnt { 2176 CXEVNT_TDMA_ENTRY = 0x0, 2177 CXEVNT_WL_TMR, 2178 CXEVNT_B1_TMR, 2179 CXEVNT_B2_TMR, 2180 CXEVNT_B3_TMR, 2181 CXEVNT_B4_TMR, 2182 CXEVNT_W2B_TMR, 2183 CXEVNT_B2W_TMR, 2184 CXEVNT_BCN_EARLY, 2185 CXEVNT_A2DP_EMPTY, 2186 CXEVNT_LK_END, 2187 CXEVNT_RX_ISR, 2188 CXEVNT_RX_FC0, 2189 CXEVNT_RX_FC1, 2190 CXEVNT_BT_RELINK, 2191 CXEVNT_BT_RETRY, 2192 CXEVNT_E2G, 2193 CXEVNT_E5G, 2194 CXEVNT_EBT, 2195 CXEVNT_ENULL, 2196 CXEVNT_DRV_WLK, 2197 CXEVNT_BCN_OK, 2198 CXEVNT_BT_CHANGE, 2199 CXEVNT_EBT_EXTEND, 2200 CXEVNT_E2G_NULL1, 2201 CXEVNT_B1FDD_TMR, 2202 CXEVNT_MAX 2203 }; 2204 2205 enum { 2206 CXBCN_ALL = 0x0, 2207 CXBCN_ALL_OK, 2208 CXBCN_BT_SLOT, 2209 CXBCN_BT_OK, 2210 CXBCN_MAX 2211 }; 2212 2213 enum btc_slot_type { 2214 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2215 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2216 CXSTYPE_NUM, 2217 }; 2218 2219 enum { /* TIME */ 2220 CXT_BT = 0x0, 2221 CXT_WL = 0x1, 2222 CXT_MAX 2223 }; 2224 2225 enum { /* TIME-A2DP */ 2226 CXT_FLCTRL_OFF = 0x0, 2227 CXT_FLCTRL_ON = 0x1, 2228 CXT_FLCTRL_MAX 2229 }; 2230 2231 enum { /* STEP TYPE */ 2232 CXSTEP_NONE = 0x0, 2233 CXSTEP_EVNT = 0x1, 2234 CXSTEP_SLOT = 0x2, 2235 CXSTEP_MAX, 2236 }; 2237 2238 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2239 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2240 RPT_BT_AFH_SEQ_LE = 0x20 2241 }; 2242 2243 #define BTC_DBG_MAX1 32 2244 struct rtw89_btc_fbtc_gpio_dbg { 2245 u8 fver; /* btc_ver::fcxgpiodbg */ 2246 u8 rsvd; 2247 u16 rsvd2; 2248 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2249 u32 pre_state; /* the debug signal is 1 or 0 */ 2250 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2251 } __packed; 2252 2253 struct rtw89_btc_fbtc_mreg_val_v1 { 2254 u8 fver; /* btc_ver::fcxmreg */ 2255 u8 reg_num; 2256 __le16 rsvd; 2257 __le32 mreg_val[CXMREG_MAX]; 2258 } __packed; 2259 2260 struct rtw89_btc_fbtc_mreg_val_v2 { 2261 u8 fver; /* btc_ver::fcxmreg */ 2262 u8 reg_num; 2263 __le16 rsvd; 2264 __le32 mreg_val[CXMREG_MAX_V2]; 2265 } __packed; 2266 2267 union rtw89_btc_fbtc_mreg_val { 2268 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2269 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2270 }; 2271 2272 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2273 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2274 .offset = cpu_to_le32(__offset), } 2275 2276 struct rtw89_btc_fbtc_mreg { 2277 __le16 type; 2278 __le16 bytes; 2279 __le32 offset; 2280 } __packed; 2281 2282 struct rtw89_btc_fbtc_slot { 2283 __le16 dur; 2284 __le32 cxtbl; 2285 __le16 cxtype; 2286 } __packed; 2287 2288 struct rtw89_btc_fbtc_slots { 2289 u8 fver; /* btc_ver::fcxslots */ 2290 u8 tbl_num; 2291 __le16 rsvd; 2292 __le32 update_map; 2293 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2294 } __packed; 2295 2296 struct rtw89_btc_fbtc_slot_v7 { 2297 __le16 dur; /* slot duration */ 2298 __le16 cxtype; 2299 __le32 cxtbl; 2300 } __packed; 2301 2302 struct rtw89_btc_fbtc_slot_u16 { 2303 __le16 dur; /* slot duration */ 2304 __le16 cxtype; 2305 __le16 cxtbl_l16; /* coex table [15:0] */ 2306 __le16 cxtbl_h16; /* coex table [31:16] */ 2307 } __packed; 2308 2309 struct rtw89_btc_fbtc_1slot_v7 { 2310 u8 fver; 2311 u8 sid; /* slot id */ 2312 __le16 rsvd; 2313 struct rtw89_btc_fbtc_slot_v7 slot; 2314 } __packed; 2315 2316 struct rtw89_btc_fbtc_slots_v7 { 2317 u8 fver; 2318 u8 slot_cnt; 2319 u8 rsvd0; 2320 u8 rsvd1; 2321 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2322 __le32 update_map; 2323 } __packed; 2324 2325 union rtw89_btc_fbtc_slots_info { 2326 struct rtw89_btc_fbtc_slots v1; 2327 struct rtw89_btc_fbtc_slots_v7 v7; 2328 } __packed; 2329 2330 struct rtw89_btc_fbtc_step { 2331 u8 type; 2332 u8 val; 2333 __le16 difft; 2334 } __packed; 2335 2336 struct rtw89_btc_fbtc_steps_v2 { 2337 u8 fver; /* btc_ver::fcxstep */ 2338 u8 rsvd; 2339 __le16 cnt; 2340 __le16 pos_old; 2341 __le16 pos_new; 2342 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2343 } __packed; 2344 2345 struct rtw89_btc_fbtc_steps_v3 { 2346 u8 fver; 2347 u8 en; 2348 __le16 rsvd; 2349 __le32 cnt; 2350 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2351 } __packed; 2352 2353 union rtw89_btc_fbtc_steps_info { 2354 struct rtw89_btc_fbtc_steps_v2 v2; 2355 struct rtw89_btc_fbtc_steps_v3 v3; 2356 }; 2357 2358 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2359 u8 fver; /* btc_ver::fcxcysta */ 2360 u8 rsvd; 2361 __le16 cycles; /* total cycle number */ 2362 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2363 __le16 a2dpept; /* a2dp empty cnt */ 2364 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2365 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2366 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2367 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2368 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2369 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2370 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2371 __le16 tmax_a2dpept; /* max a2dp empty time */ 2372 __le16 tavg_lk; /* avg leak-slot time */ 2373 __le16 tmax_lk; /* max leak-slot time */ 2374 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2375 __le32 bcn_cnt[CXBCN_MAX]; 2376 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2377 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2378 __le32 skip_cnt; 2379 __le32 exception; 2380 __le32 except_cnt; 2381 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2382 } __packed; 2383 2384 struct rtw89_btc_fbtc_fdd_try_info { 2385 __le16 cycles[CXT_FLCTRL_MAX]; 2386 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2387 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2388 } __packed; 2389 2390 struct rtw89_btc_fbtc_cycle_time_info { 2391 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2392 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2393 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2394 } __packed; 2395 2396 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2397 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2398 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2399 } __packed; 2400 2401 struct rtw89_btc_fbtc_a2dp_trx_stat { 2402 u8 empty_cnt; 2403 u8 retry_cnt; 2404 u8 tx_rate; 2405 u8 tx_cnt; 2406 u8 ack_cnt; 2407 u8 nack_cnt; 2408 u8 rsvd1; 2409 u8 rsvd2; 2410 } __packed; 2411 2412 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2413 u8 empty_cnt; 2414 u8 retry_cnt; 2415 u8 tx_rate; 2416 u8 tx_cnt; 2417 u8 ack_cnt; 2418 u8 nack_cnt; 2419 u8 no_empty_cnt; 2420 u8 rsvd; 2421 } __packed; 2422 2423 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2424 __le16 cnt; /* a2dp empty cnt */ 2425 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2426 __le16 tavg; /* avg a2dp empty time */ 2427 __le16 tmax; /* max a2dp empty time */ 2428 } __packed; 2429 2430 struct rtw89_btc_fbtc_cycle_leak_info { 2431 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2432 __le16 tavg; /* avg leak-slot time */ 2433 __le16 tmax; /* max leak-slot time */ 2434 } __packed; 2435 2436 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2437 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2438 2439 struct rtw89_btc_fbtc_cycle_fddt_info { 2440 __le16 train_cycle; 2441 __le16 tp; 2442 2443 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2444 s8 bt_tx_power; /* decrease Tx power (dB) */ 2445 s8 bt_rx_gain; /* LNA constrain level */ 2446 u8 no_empty_cnt; 2447 2448 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2449 u8 cn; /* condition_num */ 2450 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2451 u8 train_result; /* refer to enum btc_fddt_check_map */ 2452 } __packed; 2453 2454 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2455 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2456 2457 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2458 __le16 train_cycle; 2459 __le16 tp; 2460 2461 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2462 s8 bt_tx_power; /* decrease Tx power (dB) */ 2463 s8 bt_rx_gain; /* LNA constrain level */ 2464 u8 no_empty_cnt; 2465 2466 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2467 u8 cn; /* condition_num */ 2468 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2469 u8 train_result; /* refer to enum btc_fddt_check_map */ 2470 } __packed; 2471 2472 struct rtw89_btc_fbtc_fddt_cell_status { 2473 s8 wl_tx_pwr; 2474 s8 bt_tx_pwr; 2475 s8 bt_rx_gain; 2476 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2477 } __packed; 2478 2479 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2480 u8 fver; 2481 u8 rsvd; 2482 __le16 cycles; /* total cycle number */ 2483 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2484 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2485 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2486 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2487 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2488 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2489 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2490 __le32 bcn_cnt[CXBCN_MAX]; 2491 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2492 __le32 skip_cnt; 2493 __le32 except_cnt; 2494 __le32 except_map; 2495 } __packed; 2496 2497 #define FDD_TRAIN_WL_DIRECTION 2 2498 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2499 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2500 2501 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2502 u8 fver; 2503 u8 rsvd; 2504 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2505 u8 except_cnt; 2506 2507 __le16 skip_cnt; 2508 __le16 cycles; /* total cycle number */ 2509 2510 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2511 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2512 __le16 bcn_cnt[CXBCN_MAX]; 2513 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2514 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2515 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2516 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2517 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2518 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2519 [FDD_TRAIN_WL_RSSI_LEVEL] 2520 [FDD_TRAIN_BT_RSSI_LEVEL]; 2521 __le32 except_map; 2522 } __packed; 2523 2524 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2525 u8 fver; 2526 u8 rsvd; 2527 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2528 u8 except_cnt; 2529 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2530 2531 __le16 skip_cnt; 2532 __le16 cycles; /* total cycle number */ 2533 2534 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2535 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2536 __le16 bcn_cnt[CXBCN_MAX]; 2537 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2538 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2539 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2540 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2541 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2542 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2543 [FDD_TRAIN_WL_RSSI_LEVEL] 2544 [FDD_TRAIN_BT_RSSI_LEVEL]; 2545 __le32 except_map; 2546 } __packed; 2547 2548 union rtw89_btc_fbtc_cysta_info { 2549 struct rtw89_btc_fbtc_cysta_v2 v2; 2550 struct rtw89_btc_fbtc_cysta_v3 v3; 2551 struct rtw89_btc_fbtc_cysta_v4 v4; 2552 struct rtw89_btc_fbtc_cysta_v5 v5; 2553 }; 2554 2555 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2556 u8 fver; /* btc_ver::fcxnullsta */ 2557 u8 rsvd; 2558 __le16 rsvd2; 2559 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2560 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2561 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2562 } __packed; 2563 2564 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2565 u8 fver; /* btc_ver::fcxnullsta */ 2566 u8 rsvd; 2567 __le16 rsvd2; 2568 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2569 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2570 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2571 } __packed; 2572 2573 union rtw89_btc_fbtc_cynullsta_info { 2574 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2575 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2576 }; 2577 2578 struct rtw89_btc_fbtc_btver { 2579 u8 fver; /* btc_ver::fcxbtver */ 2580 u8 rsvd; 2581 __le16 rsvd2; 2582 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2583 __le32 fw_ver; 2584 __le32 feature; 2585 } __packed; 2586 2587 struct rtw89_btc_fbtc_btafh { 2588 u8 fver; /* btc_ver::fcxbtafh */ 2589 u8 rsvd; 2590 __le16 rsvd2; 2591 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2592 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2593 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2594 } __packed; 2595 2596 struct rtw89_btc_fbtc_btafh_v2 { 2597 u8 fver; /* btc_ver::fcxbtafh */ 2598 u8 rsvd; 2599 u8 rsvd2; 2600 u8 map_type; 2601 u8 afh_l[4]; 2602 u8 afh_m[4]; 2603 u8 afh_h[4]; 2604 u8 afh_le_a[4]; 2605 u8 afh_le_b[4]; 2606 } __packed; 2607 2608 struct rtw89_btc_fbtc_btdevinfo { 2609 u8 fver; /* btc_ver::fcxbtdevinfo */ 2610 u8 rsvd; 2611 __le16 vendor_id; 2612 __le32 dev_name; /* only 24 bits valid */ 2613 __le32 flush_time; 2614 } __packed; 2615 2616 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2617 struct rtw89_btc_rf_trx_para { 2618 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2619 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2620 u8 bt_tx_power; /* decrease Tx power (dB) */ 2621 u8 bt_rx_gain; /* LNA constrain level */ 2622 }; 2623 2624 struct rtw89_btc_trx_info { 2625 u8 tx_lvl; 2626 u8 rx_lvl; 2627 u8 wl_rssi; 2628 u8 bt_rssi; 2629 2630 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2631 s8 rx_gain; /* rx gain table index (TBD.) */ 2632 s8 bt_tx_power; /* decrease Tx power (dB) */ 2633 s8 bt_rx_gain; /* LNA constrain level */ 2634 2635 u8 cn; /* condition_num */ 2636 s8 nhm; 2637 u8 bt_profile; 2638 u8 rsvd2; 2639 2640 u16 tx_rate; 2641 u16 rx_rate; 2642 2643 u32 tx_tp; 2644 u32 rx_tp; 2645 u32 rx_err_ratio; 2646 }; 2647 2648 union rtw89_btc_fbtc_slot_u { 2649 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2650 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2651 }; 2652 2653 struct rtw89_btc_dm { 2654 union rtw89_btc_fbtc_slot_u slot; 2655 union rtw89_btc_fbtc_slot_u slot_now; 2656 struct rtw89_btc_fbtc_tdma tdma; 2657 struct rtw89_btc_fbtc_tdma tdma_now; 2658 struct rtw89_mac_ax_coex_gnt gnt; 2659 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2660 struct rtw89_btc_rf_trx_para rf_trx_para; 2661 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2662 struct rtw89_btc_dm_step dm_step; 2663 struct rtw89_btc_wl_scc_ctrl wl_scc; 2664 struct rtw89_btc_trx_info trx_info; 2665 union rtw89_btc_dm_error_map error; 2666 u32 cnt_dm[BTC_DCNT_NUM]; 2667 u32 cnt_notify[BTC_NCNT_NUM]; 2668 2669 u32 update_slot_map; 2670 u32 set_ant_path; 2671 u32 e2g_slot_limit; 2672 u32 e2g_slot_nulltx_time; 2673 2674 u32 wl_only: 1; 2675 u32 wl_fw_cx_offload: 1; 2676 u32 freerun: 1; 2677 u32 fddt_train: 1; 2678 u32 wl_ps_ctrl: 2; 2679 u32 wl_mimo_ps: 1; 2680 u32 leak_ap: 1; 2681 u32 noisy_level: 3; 2682 u32 coex_info_map: 8; 2683 u32 bt_only: 1; 2684 u32 wl_btg_rx: 2; 2685 u32 trx_para_level: 8; 2686 u32 wl_stb_chg: 1; 2687 u32 pta_owner: 1; 2688 2689 u32 tdma_instant_excute: 1; 2690 u32 wl_btg_rx_rb: 2; 2691 2692 u16 slot_dur[CXST_MAX]; 2693 2694 u8 run_reason; 2695 u8 run_action; 2696 2697 u8 wl_pre_agc: 2; 2698 u8 wl_lna2: 1; 2699 u8 wl_pre_agc_rb: 2; 2700 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2701 }; 2702 2703 struct rtw89_btc_ctrl { 2704 u32 manual: 1; 2705 u32 igno_bt: 1; 2706 u32 always_freerun: 1; 2707 u32 trace_step: 16; 2708 u32 rsvd: 12; 2709 }; 2710 2711 struct rtw89_btc_ctrl_v7 { 2712 u8 manual; 2713 u8 igno_bt; 2714 u8 always_freerun; 2715 u8 rsvd; 2716 } __packed; 2717 2718 union rtw89_btc_ctrl_list { 2719 struct rtw89_btc_ctrl ctrl; 2720 struct rtw89_btc_ctrl_v7 ctrl_v7; 2721 }; 2722 2723 struct rtw89_btc_dbg { 2724 /* cmd "rb" */ 2725 bool rb_done; 2726 u32 rb_val; 2727 }; 2728 2729 enum rtw89_btc_btf_fw_event { 2730 BTF_EVNT_RPT = 0, 2731 BTF_EVNT_BT_INFO = 1, 2732 BTF_EVNT_BT_SCBD = 2, 2733 BTF_EVNT_BT_REG = 3, 2734 BTF_EVNT_CX_RUNINFO = 4, 2735 BTF_EVNT_BT_PSD = 5, 2736 BTF_EVNT_BUF_OVERFLOW, 2737 BTF_EVNT_C2H_LOOPBACK, 2738 BTF_EVNT_MAX, 2739 }; 2740 2741 enum btf_fw_event_report { 2742 BTC_RPT_TYPE_CTRL = 0x0, 2743 BTC_RPT_TYPE_TDMA, 2744 BTC_RPT_TYPE_SLOT, 2745 BTC_RPT_TYPE_CYSTA, 2746 BTC_RPT_TYPE_STEP, 2747 BTC_RPT_TYPE_NULLSTA, 2748 BTC_RPT_TYPE_MREG, 2749 BTC_RPT_TYPE_GPIO_DBG, 2750 BTC_RPT_TYPE_BT_VER, 2751 BTC_RPT_TYPE_BT_SCAN, 2752 BTC_RPT_TYPE_BT_AFH, 2753 BTC_RPT_TYPE_BT_DEVICE, 2754 BTC_RPT_TYPE_TEST, 2755 BTC_RPT_TYPE_MAX = 31 2756 }; 2757 2758 enum rtw_btc_btf_reg_type { 2759 REG_MAC = 0x0, 2760 REG_BB = 0x1, 2761 REG_RF = 0x2, 2762 REG_BT_RF = 0x3, 2763 REG_BT_MODEM = 0x4, 2764 REG_BT_BLUEWIZE = 0x5, 2765 REG_BT_VENDOR = 0x6, 2766 REG_BT_LE = 0x7, 2767 REG_MAX_TYPE, 2768 }; 2769 2770 struct rtw89_btc_rpt_cmn_info { 2771 u32 rx_cnt; 2772 u32 rx_len; 2773 u32 req_len; /* expected rsp len */ 2774 u8 req_fver; /* expected rsp fver */ 2775 u8 rsp_fver; /* fver from fw */ 2776 u8 valid; 2777 } __packed; 2778 2779 union rtw89_btc_fbtc_btafh_info { 2780 struct rtw89_btc_fbtc_btafh v1; 2781 struct rtw89_btc_fbtc_btafh_v2 v2; 2782 }; 2783 2784 struct rtw89_btc_report_ctrl_state { 2785 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2786 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2787 }; 2788 2789 struct rtw89_btc_rpt_fbtc_tdma { 2790 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2791 union rtw89_btc_fbtc_tdma_le32 finfo; 2792 }; 2793 2794 struct rtw89_btc_rpt_fbtc_slots { 2795 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2796 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 2797 }; 2798 2799 struct rtw89_btc_rpt_fbtc_cysta { 2800 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2801 union rtw89_btc_fbtc_cysta_info finfo; 2802 }; 2803 2804 struct rtw89_btc_rpt_fbtc_step { 2805 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2806 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2807 }; 2808 2809 struct rtw89_btc_rpt_fbtc_nullsta { 2810 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2811 union rtw89_btc_fbtc_cynullsta_info finfo; 2812 }; 2813 2814 struct rtw89_btc_rpt_fbtc_mreg { 2815 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2816 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2817 }; 2818 2819 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2820 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2821 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2822 }; 2823 2824 struct rtw89_btc_rpt_fbtc_btver { 2825 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2826 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2827 }; 2828 2829 struct rtw89_btc_rpt_fbtc_btscan { 2830 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2831 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2832 }; 2833 2834 struct rtw89_btc_rpt_fbtc_btafh { 2835 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2836 union rtw89_btc_fbtc_btafh_info finfo; 2837 }; 2838 2839 struct rtw89_btc_rpt_fbtc_btdev { 2840 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2841 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2842 }; 2843 2844 enum rtw89_btc_btfre_type { 2845 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2846 BTFRE_UNDEF_TYPE, 2847 BTFRE_EXCEPTION, 2848 BTFRE_MAX, 2849 }; 2850 2851 struct rtw89_btc_btf_fwinfo { 2852 u32 cnt_c2h; 2853 u32 cnt_h2c; 2854 u32 cnt_h2c_fail; 2855 u32 event[BTF_EVNT_MAX]; 2856 2857 u32 err[BTFRE_MAX]; 2858 u32 len_mismch; 2859 u32 fver_mismch; 2860 u32 rpt_en_map; 2861 2862 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2863 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2864 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2865 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2866 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2867 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2868 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2869 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2870 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2871 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2872 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2873 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2874 }; 2875 2876 struct rtw89_btc_ver { 2877 enum rtw89_core_chip_id chip_id; 2878 u32 fw_ver_code; 2879 2880 u8 fcxbtcrpt; 2881 u8 fcxtdma; 2882 u8 fcxslots; 2883 u8 fcxcysta; 2884 u8 fcxstep; 2885 u8 fcxnullsta; 2886 u8 fcxmreg; 2887 u8 fcxgpiodbg; 2888 u8 fcxbtver; 2889 u8 fcxbtscan; 2890 u8 fcxbtafh; 2891 u8 fcxbtdevinfo; 2892 u8 fwlrole; 2893 u8 frptmap; 2894 u8 fcxctrl; 2895 u8 fcxinit; 2896 2897 u8 drvinfo_type; 2898 u16 info_buf; 2899 u8 max_role_num; 2900 }; 2901 2902 #define RTW89_BTC_POLICY_MAXLEN 512 2903 2904 struct rtw89_btc { 2905 const struct rtw89_btc_ver *ver; 2906 2907 struct rtw89_btc_cx cx; 2908 struct rtw89_btc_dm dm; 2909 union rtw89_btc_ctrl_list ctrl; 2910 union rtw89_btc_module_info mdinfo; 2911 struct rtw89_btc_btf_fwinfo fwinfo; 2912 struct rtw89_btc_dbg dbg; 2913 2914 struct work_struct eapol_notify_work; 2915 struct work_struct arp_notify_work; 2916 struct work_struct dhcp_notify_work; 2917 struct work_struct icmp_notify_work; 2918 2919 u32 bt_req_len; 2920 2921 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2922 u8 ant_type; 2923 u8 btg_pos; 2924 u16 policy_len; 2925 u16 policy_type; 2926 bool bt_req_en; 2927 bool update_policy_force; 2928 bool lps; 2929 bool manual_ctrl; 2930 }; 2931 2932 enum rtw89_btc_hmsg { 2933 RTW89_BTC_HMSG_TMR_EN = 0x0, 2934 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 2935 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 2936 RTW89_BTC_HMSG_FW_EV = 0x3, 2937 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 2938 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 2939 2940 NUM_OF_RTW89_BTC_HMSG, 2941 }; 2942 2943 enum rtw89_ra_mode { 2944 RTW89_RA_MODE_CCK = BIT(0), 2945 RTW89_RA_MODE_OFDM = BIT(1), 2946 RTW89_RA_MODE_HT = BIT(2), 2947 RTW89_RA_MODE_VHT = BIT(3), 2948 RTW89_RA_MODE_HE = BIT(4), 2949 RTW89_RA_MODE_EHT = BIT(5), 2950 }; 2951 2952 enum rtw89_ra_report_mode { 2953 RTW89_RA_RPT_MODE_LEGACY, 2954 RTW89_RA_RPT_MODE_HT, 2955 RTW89_RA_RPT_MODE_VHT, 2956 RTW89_RA_RPT_MODE_HE, 2957 RTW89_RA_RPT_MODE_EHT, 2958 }; 2959 2960 enum rtw89_dig_noisy_level { 2961 RTW89_DIG_NOISY_LEVEL0 = -1, 2962 RTW89_DIG_NOISY_LEVEL1 = 0, 2963 RTW89_DIG_NOISY_LEVEL2 = 1, 2964 RTW89_DIG_NOISY_LEVEL3 = 2, 2965 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2966 }; 2967 2968 enum rtw89_gi_ltf { 2969 RTW89_GILTF_LGI_4XHE32 = 0, 2970 RTW89_GILTF_SGI_4XHE08 = 1, 2971 RTW89_GILTF_2XHE16 = 2, 2972 RTW89_GILTF_2XHE08 = 3, 2973 RTW89_GILTF_1XHE16 = 4, 2974 RTW89_GILTF_1XHE08 = 5, 2975 RTW89_GILTF_MAX 2976 }; 2977 2978 enum rtw89_rx_frame_type { 2979 RTW89_RX_TYPE_MGNT = 0, 2980 RTW89_RX_TYPE_CTRL = 1, 2981 RTW89_RX_TYPE_DATA = 2, 2982 RTW89_RX_TYPE_RSVD = 3, 2983 }; 2984 2985 enum rtw89_efuse_block { 2986 RTW89_EFUSE_BLOCK_SYS = 0, 2987 RTW89_EFUSE_BLOCK_RF = 1, 2988 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 2989 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 2990 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 2991 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 2992 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 2993 RTW89_EFUSE_BLOCK_ADIE = 7, 2994 2995 RTW89_EFUSE_BLOCK_NUM, 2996 RTW89_EFUSE_BLOCK_IGNORE, 2997 }; 2998 2999 struct rtw89_ra_info { 3000 u8 is_dis_ra:1; 3001 /* Bit0 : CCK 3002 * Bit1 : OFDM 3003 * Bit2 : HT 3004 * Bit3 : VHT 3005 * Bit4 : HE 3006 * Bit5 : EHT 3007 */ 3008 u8 mode_ctrl:6; 3009 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3010 u8 macid; 3011 u8 dcm_cap:1; 3012 u8 er_cap:1; 3013 u8 init_rate_lv:2; 3014 u8 upd_all:1; 3015 u8 en_sgi:1; 3016 u8 ldpc_cap:1; 3017 u8 stbc_cap:1; 3018 u8 ss_num:3; 3019 u8 giltf:3; 3020 u8 upd_bw_nss_mask:1; 3021 u8 upd_mask:1; 3022 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3023 /* BFee CSI */ 3024 u8 band_num; 3025 u8 ra_csi_rate_en:1; 3026 u8 fixed_csi_rate_en:1; 3027 u8 cr_tbl_sel:1; 3028 u8 fix_giltf_en:1; 3029 u8 fix_giltf:3; 3030 u8 rsvd2:1; 3031 u8 csi_mcs_ss_idx; 3032 u8 csi_mode:2; 3033 u8 csi_gi_ltf:3; 3034 u8 csi_bw:3; 3035 }; 3036 3037 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3038 #define RTW89_PPDU_MAC_INFO_SIZE 8 3039 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3040 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3041 3042 #define RTW89_MAX_RX_AGG_NUM 64 3043 #define RTW89_MAX_TX_AGG_NUM 128 3044 3045 struct rtw89_ampdu_params { 3046 u16 agg_num; 3047 bool amsdu; 3048 }; 3049 3050 struct rtw89_ra_report { 3051 struct rate_info txrate; 3052 u32 bit_rate; 3053 u16 hw_rate; 3054 bool might_fallback_legacy; 3055 }; 3056 3057 DECLARE_EWMA(rssi, 10, 16); 3058 DECLARE_EWMA(evm, 10, 16); 3059 DECLARE_EWMA(snr, 10, 16); 3060 3061 struct rtw89_ba_cam_entry { 3062 struct list_head list; 3063 u8 tid; 3064 }; 3065 3066 #define RTW89_MAX_ADDR_CAM_NUM 128 3067 #define RTW89_MAX_BSSID_CAM_NUM 20 3068 #define RTW89_MAX_SEC_CAM_NUM 128 3069 #define RTW89_MAX_BA_CAM_NUM 24 3070 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3071 3072 struct rtw89_addr_cam_entry { 3073 u8 addr_cam_idx; 3074 u8 offset; 3075 u8 len; 3076 u8 valid : 1; 3077 u8 addr_mask : 6; 3078 u8 wapi : 1; 3079 u8 mask_sel : 2; 3080 u8 bssid_cam_idx: 6; 3081 3082 u8 sec_ent_mode; 3083 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3084 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3085 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3086 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 3087 }; 3088 3089 struct rtw89_bssid_cam_entry { 3090 u8 bssid[ETH_ALEN]; 3091 u8 phy_idx; 3092 u8 bssid_cam_idx; 3093 u8 offset; 3094 u8 len; 3095 u8 valid : 1; 3096 u8 num; 3097 }; 3098 3099 struct rtw89_sec_cam_entry { 3100 u8 sec_cam_idx; 3101 u8 offset; 3102 u8 len; 3103 u8 type : 4; 3104 u8 ext_key : 1; 3105 u8 spp_mode : 1; 3106 /* 256 bits */ 3107 u8 key[32]; 3108 }; 3109 3110 struct rtw89_sta { 3111 u8 mac_id; 3112 bool disassoc; 3113 bool er_cap; 3114 struct rtw89_dev *rtwdev; 3115 struct rtw89_vif *rtwvif; 3116 struct rtw89_ra_info ra; 3117 struct rtw89_ra_report ra_report; 3118 int max_agg_wait; 3119 u8 prev_rssi; 3120 struct ewma_rssi avg_rssi; 3121 struct ewma_rssi rssi[RF_PATH_MAX]; 3122 struct ewma_snr avg_snr; 3123 struct ewma_evm evm_min[RF_PATH_MAX]; 3124 struct ewma_evm evm_max[RF_PATH_MAX]; 3125 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 3126 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 3127 struct ieee80211_rx_status rx_status; 3128 u16 rx_hw_rate; 3129 __le32 htc_template; 3130 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3131 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3132 struct list_head ba_cam_list; 3133 struct sk_buff_head roc_queue; 3134 3135 bool use_cfg_mask; 3136 struct cfg80211_bitrate_mask mask; 3137 3138 bool cctl_tx_time; 3139 u32 ampdu_max_time:4; 3140 bool cctl_tx_retry_limit; 3141 u32 data_tx_cnt_lmt:6; 3142 }; 3143 3144 struct rtw89_efuse { 3145 bool valid; 3146 bool power_k_valid; 3147 u8 xtal_cap; 3148 u8 addr[ETH_ALEN]; 3149 u8 rfe_type; 3150 char country_code[2]; 3151 }; 3152 3153 struct rtw89_phy_rate_pattern { 3154 u64 ra_mask; 3155 u16 rate; 3156 u8 ra_mode; 3157 bool enable; 3158 }; 3159 3160 struct rtw89_tx_wait_info { 3161 struct rcu_head rcu_head; 3162 struct completion completion; 3163 bool tx_done; 3164 }; 3165 3166 struct rtw89_tx_skb_data { 3167 struct rtw89_tx_wait_info __rcu *wait; 3168 u8 hci_priv[]; 3169 }; 3170 3171 #define RTW89_ROC_IDLE_TIMEOUT 500 3172 #define RTW89_ROC_TX_TIMEOUT 30 3173 enum rtw89_roc_state { 3174 RTW89_ROC_IDLE, 3175 RTW89_ROC_NORMAL, 3176 RTW89_ROC_MGMT, 3177 }; 3178 3179 struct rtw89_roc { 3180 struct ieee80211_channel chan; 3181 struct delayed_work roc_work; 3182 enum ieee80211_roc_type type; 3183 enum rtw89_roc_state state; 3184 int duration; 3185 }; 3186 3187 #define RTW89_P2P_MAX_NOA_NUM 2 3188 3189 struct rtw89_p2p_ie_head { 3190 u8 eid; 3191 u8 ie_len; 3192 u8 oui[3]; 3193 u8 oui_type; 3194 } __packed; 3195 3196 struct rtw89_noa_attr_head { 3197 u8 attr_type; 3198 __le16 attr_len; 3199 u8 index; 3200 u8 oppps_ctwindow; 3201 } __packed; 3202 3203 struct rtw89_p2p_noa_ie { 3204 struct rtw89_p2p_ie_head p2p_head; 3205 struct rtw89_noa_attr_head noa_head; 3206 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3207 } __packed; 3208 3209 struct rtw89_p2p_noa_setter { 3210 struct rtw89_p2p_noa_ie ie; 3211 u8 noa_count; 3212 u8 noa_index; 3213 }; 3214 3215 struct rtw89_vif { 3216 struct list_head list; 3217 struct rtw89_dev *rtwdev; 3218 struct rtw89_roc roc; 3219 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3220 enum rtw89_sub_entity_idx sub_entity_idx; 3221 enum rtw89_reg_6ghz_power reg_6ghz_power; 3222 3223 u8 mac_id; 3224 u8 port; 3225 u8 mac_addr[ETH_ALEN]; 3226 u8 bssid[ETH_ALEN]; 3227 u8 phy_idx; 3228 u8 mac_idx; 3229 u8 net_type; 3230 u8 wifi_role; 3231 u8 self_role; 3232 u8 wmm; 3233 u8 bcn_hit_cond; 3234 u8 hit_rule; 3235 u8 last_noa_nr; 3236 u64 sync_bcn_tsf; 3237 bool offchan; 3238 bool trigger; 3239 bool lsig_txop; 3240 u8 tgt_ind; 3241 u8 frm_tgt_ind; 3242 bool wowlan_pattern; 3243 bool wowlan_uc; 3244 bool wowlan_magic; 3245 bool is_hesta; 3246 bool last_a_ctrl; 3247 bool dyn_tb_bedge_en; 3248 bool pre_pwr_diff_en; 3249 bool pwr_diff_en; 3250 u8 def_tri_idx; 3251 u32 tdls_peer; 3252 struct work_struct update_beacon_work; 3253 struct rtw89_addr_cam_entry addr_cam; 3254 struct rtw89_bssid_cam_entry bssid_cam; 3255 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3256 struct rtw89_traffic_stats stats; 3257 struct rtw89_phy_rate_pattern rate_pattern; 3258 struct cfg80211_scan_request *scan_req; 3259 struct ieee80211_scan_ies *scan_ies; 3260 struct list_head general_pkt_list; 3261 struct rtw89_p2p_noa_setter p2p_noa; 3262 }; 3263 3264 enum rtw89_lv1_rcvy_step { 3265 RTW89_LV1_RCVY_STEP_1, 3266 RTW89_LV1_RCVY_STEP_2, 3267 }; 3268 3269 struct rtw89_hci_ops { 3270 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3271 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3272 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3273 void (*reset)(struct rtw89_dev *rtwdev); 3274 int (*start)(struct rtw89_dev *rtwdev); 3275 void (*stop)(struct rtw89_dev *rtwdev); 3276 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3277 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3278 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3279 3280 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3281 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3282 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3283 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3284 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3285 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3286 3287 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3288 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3289 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3290 int (*deinit)(struct rtw89_dev *rtwdev); 3291 3292 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3293 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3294 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3295 int (*napi_poll)(struct napi_struct *napi, int budget); 3296 3297 /* Deal with locks inside recovery_start and recovery_complete callbacks 3298 * by hci instance, and handle things which need to consider under SER. 3299 * e.g. turn on/off interrupts except for the one for halt notification. 3300 */ 3301 void (*recovery_start)(struct rtw89_dev *rtwdev); 3302 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3303 3304 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3305 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3306 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3307 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3308 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3309 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3310 void (*disable_intr)(struct rtw89_dev *rtwdev); 3311 void (*enable_intr)(struct rtw89_dev *rtwdev); 3312 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3313 }; 3314 3315 struct rtw89_hci_info { 3316 const struct rtw89_hci_ops *ops; 3317 enum rtw89_hci_type type; 3318 u32 rpwm_addr; 3319 u32 cpwm_addr; 3320 bool paused; 3321 }; 3322 3323 struct rtw89_chip_ops { 3324 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3325 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3326 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3327 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3328 void (*bb_reset)(struct rtw89_dev *rtwdev, 3329 enum rtw89_phy_idx phy_idx); 3330 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3331 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3332 u32 addr, u32 mask); 3333 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3334 u32 addr, u32 mask, u32 data); 3335 void (*set_channel)(struct rtw89_dev *rtwdev, 3336 const struct rtw89_chan *chan, 3337 enum rtw89_mac_idx mac_idx, 3338 enum rtw89_phy_idx phy_idx); 3339 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3340 struct rtw89_channel_help_params *p, 3341 const struct rtw89_chan *chan, 3342 enum rtw89_mac_idx mac_idx, 3343 enum rtw89_phy_idx phy_idx); 3344 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3345 enum rtw89_efuse_block block); 3346 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3347 void (*fem_setup)(struct rtw89_dev *rtwdev); 3348 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3349 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3350 void (*rfk_init)(struct rtw89_dev *rtwdev); 3351 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3352 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3353 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3354 enum rtw89_phy_idx phy_idx); 3355 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3356 void (*rfk_track)(struct rtw89_dev *rtwdev); 3357 void (*power_trim)(struct rtw89_dev *rtwdev); 3358 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3359 const struct rtw89_chan *chan, 3360 enum rtw89_phy_idx phy_idx); 3361 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3362 enum rtw89_phy_idx phy_idx); 3363 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3364 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3365 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3366 enum rtw89_phy_idx phy_idx); 3367 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3368 struct rtw89_rx_phy_ppdu *phy_ppdu, 3369 struct ieee80211_rx_status *status); 3370 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3371 enum rtw89_phy_idx phy_idx); 3372 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3373 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3374 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3375 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3376 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3377 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3378 struct rtw89_rx_desc_info *desc_info, 3379 u8 *data, u32 data_offset); 3380 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3381 struct rtw89_tx_desc_info *desc_info, 3382 void *txdesc); 3383 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3384 struct rtw89_tx_desc_info *desc_info, 3385 void *txdesc); 3386 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3387 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3388 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3389 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3390 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3391 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3392 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3393 struct rtw89_vif *rtwvif, 3394 struct rtw89_sta *rtwsta); 3395 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3396 struct rtw89_vif *rtwvif, 3397 struct rtw89_sta *rtwsta); 3398 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3399 struct ieee80211_vif *vif, 3400 struct ieee80211_sta *sta); 3401 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3402 struct ieee80211_vif *vif, 3403 struct ieee80211_sta *sta); 3404 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3405 struct rtw89_vif *rtwvif, 3406 struct rtw89_sta *rtwsta); 3407 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3408 struct rtw89_vif *rtwvif); 3409 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3410 bool valid, struct ieee80211_ampdu_params *params); 3411 3412 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3413 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3414 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3415 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3416 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3417 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3418 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3419 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3420 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3421 }; 3422 3423 enum rtw89_dma_ch { 3424 RTW89_DMA_ACH0 = 0, 3425 RTW89_DMA_ACH1 = 1, 3426 RTW89_DMA_ACH2 = 2, 3427 RTW89_DMA_ACH3 = 3, 3428 RTW89_DMA_ACH4 = 4, 3429 RTW89_DMA_ACH5 = 5, 3430 RTW89_DMA_ACH6 = 6, 3431 RTW89_DMA_ACH7 = 7, 3432 RTW89_DMA_B0MG = 8, 3433 RTW89_DMA_B0HI = 9, 3434 RTW89_DMA_B1MG = 10, 3435 RTW89_DMA_B1HI = 11, 3436 RTW89_DMA_H2C = 12, 3437 RTW89_DMA_CH_NUM = 13 3438 }; 3439 3440 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3441 3442 enum rtw89_mlo_dbcc_mode { 3443 MLO_DBCC_NOT_SUPPORT = 1, 3444 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3445 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3446 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3447 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3448 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3449 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3450 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3451 DBCC_LEGACY = 0xffffffff, 3452 }; 3453 3454 enum rtw89_scan_be_operation { 3455 RTW89_SCAN_OP_STOP, 3456 RTW89_SCAN_OP_START, 3457 RTW89_SCAN_OP_SETPARM, 3458 RTW89_SCAN_OP_GETRPT, 3459 RTW89_SCAN_OP_NUM 3460 }; 3461 3462 enum rtw89_scan_be_mode { 3463 RTW89_SCAN_MODE_SA, 3464 RTW89_SCAN_MODE_MACC, 3465 RTW89_SCAN_MODE_NUM 3466 }; 3467 3468 enum rtw89_scan_be_opmode { 3469 RTW89_SCAN_OPMODE_NONE, 3470 RTW89_SCAN_OPMODE_TBTT, 3471 RTW89_SCAN_OPMODE_INTV, 3472 RTW89_SCAN_OPMODE_CNT, 3473 RTW89_SCAN_OPMODE_NUM, 3474 }; 3475 3476 struct rtw89_scan_option { 3477 bool enable; 3478 bool target_ch_mode; 3479 u8 num_macc_role; 3480 u8 num_opch; 3481 u8 repeat; 3482 u16 norm_pd; 3483 u16 slow_pd; 3484 u16 norm_cy; 3485 u8 opch_end; 3486 u64 prohib_chan; 3487 enum rtw89_phy_idx band; 3488 enum rtw89_scan_be_operation operation; 3489 enum rtw89_scan_be_mode scan_mode; 3490 enum rtw89_mlo_dbcc_mode mlo_mode; 3491 }; 3492 3493 enum rtw89_qta_mode { 3494 RTW89_QTA_SCC, 3495 RTW89_QTA_DBCC, 3496 RTW89_QTA_DLFW, 3497 RTW89_QTA_WOW, 3498 3499 /* keep last */ 3500 RTW89_QTA_INVALID, 3501 }; 3502 3503 struct rtw89_hfc_ch_cfg { 3504 u16 min; 3505 u16 max; 3506 #define grp_0 0 3507 #define grp_1 1 3508 #define grp_num 2 3509 u8 grp; 3510 }; 3511 3512 struct rtw89_hfc_ch_info { 3513 u16 aval; 3514 u16 used; 3515 }; 3516 3517 struct rtw89_hfc_pub_cfg { 3518 u16 grp0; 3519 u16 grp1; 3520 u16 pub_max; 3521 u16 wp_thrd; 3522 }; 3523 3524 struct rtw89_hfc_pub_info { 3525 u16 g0_used; 3526 u16 g1_used; 3527 u16 g0_aval; 3528 u16 g1_aval; 3529 u16 pub_aval; 3530 u16 wp_aval; 3531 }; 3532 3533 struct rtw89_hfc_prec_cfg { 3534 u16 ch011_prec; 3535 u16 h2c_prec; 3536 u16 wp_ch07_prec; 3537 u16 wp_ch811_prec; 3538 u8 ch011_full_cond; 3539 u8 h2c_full_cond; 3540 u8 wp_ch07_full_cond; 3541 u8 wp_ch811_full_cond; 3542 }; 3543 3544 struct rtw89_hfc_param { 3545 bool en; 3546 bool h2c_en; 3547 u8 mode; 3548 const struct rtw89_hfc_ch_cfg *ch_cfg; 3549 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3550 struct rtw89_hfc_pub_cfg pub_cfg; 3551 struct rtw89_hfc_pub_info pub_info; 3552 struct rtw89_hfc_prec_cfg prec_cfg; 3553 }; 3554 3555 struct rtw89_hfc_param_ini { 3556 const struct rtw89_hfc_ch_cfg *ch_cfg; 3557 const struct rtw89_hfc_pub_cfg *pub_cfg; 3558 const struct rtw89_hfc_prec_cfg *prec_cfg; 3559 u8 mode; 3560 }; 3561 3562 struct rtw89_dle_size { 3563 u16 pge_size; 3564 u16 lnk_pge_num; 3565 u16 unlnk_pge_num; 3566 /* for WiFi 7 chips below */ 3567 u32 srt_ofst; 3568 }; 3569 3570 struct rtw89_wde_quota { 3571 u16 hif; 3572 u16 wcpu; 3573 u16 pkt_in; 3574 u16 cpu_io; 3575 }; 3576 3577 struct rtw89_ple_quota { 3578 u16 cma0_tx; 3579 u16 cma1_tx; 3580 u16 c2h; 3581 u16 h2c; 3582 u16 wcpu; 3583 u16 mpdu_proc; 3584 u16 cma0_dma; 3585 u16 cma1_dma; 3586 u16 bb_rpt; 3587 u16 wd_rel; 3588 u16 cpu_io; 3589 u16 tx_rpt; 3590 /* for WiFi 7 chips below */ 3591 u16 h2d; 3592 }; 3593 3594 struct rtw89_rsvd_quota { 3595 u16 mpdu_info_tbl; 3596 u16 b0_csi; 3597 u16 b1_csi; 3598 u16 b0_lmr; 3599 u16 b1_lmr; 3600 u16 b0_ftm; 3601 u16 b1_ftm; 3602 u16 b0_smr; 3603 u16 b1_smr; 3604 u16 others; 3605 }; 3606 3607 struct rtw89_dle_rsvd_size { 3608 u32 srt_ofst; 3609 u32 size; 3610 }; 3611 3612 struct rtw89_dle_mem { 3613 enum rtw89_qta_mode mode; 3614 const struct rtw89_dle_size *wde_size; 3615 const struct rtw89_dle_size *ple_size; 3616 const struct rtw89_wde_quota *wde_min_qt; 3617 const struct rtw89_wde_quota *wde_max_qt; 3618 const struct rtw89_ple_quota *ple_min_qt; 3619 const struct rtw89_ple_quota *ple_max_qt; 3620 /* for WiFi 7 chips below */ 3621 const struct rtw89_rsvd_quota *rsvd_qt; 3622 const struct rtw89_dle_rsvd_size *rsvd0_size; 3623 const struct rtw89_dle_rsvd_size *rsvd1_size; 3624 }; 3625 3626 struct rtw89_reg_def { 3627 u32 addr; 3628 u32 mask; 3629 }; 3630 3631 struct rtw89_reg2_def { 3632 u32 addr; 3633 u32 data; 3634 }; 3635 3636 struct rtw89_reg3_def { 3637 u32 addr; 3638 u32 mask; 3639 u32 data; 3640 }; 3641 3642 struct rtw89_reg5_def { 3643 u8 flag; /* recognized by parsers */ 3644 u8 path; 3645 u32 addr; 3646 u32 mask; 3647 u32 data; 3648 }; 3649 3650 struct rtw89_reg_imr { 3651 u32 addr; 3652 u32 clr; 3653 u32 set; 3654 }; 3655 3656 struct rtw89_phy_table { 3657 const struct rtw89_reg2_def *regs; 3658 u32 n_regs; 3659 enum rtw89_rf_path rf_path; 3660 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3661 enum rtw89_rf_path rf_path, void *data); 3662 }; 3663 3664 struct rtw89_txpwr_table { 3665 const void *data; 3666 u32 size; 3667 void (*load)(struct rtw89_dev *rtwdev, 3668 const struct rtw89_txpwr_table *tbl); 3669 }; 3670 3671 struct rtw89_txpwr_rule_2ghz { 3672 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3673 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3674 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3675 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3676 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3677 }; 3678 3679 struct rtw89_txpwr_rule_5ghz { 3680 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3681 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3682 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3683 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3684 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3685 }; 3686 3687 struct rtw89_txpwr_rule_6ghz { 3688 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3689 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3690 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3691 [RTW89_6G_CH_NUM]; 3692 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3693 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3694 [RTW89_6G_CH_NUM]; 3695 }; 3696 3697 struct rtw89_tx_shape { 3698 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3699 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3700 }; 3701 3702 struct rtw89_rfe_parms { 3703 const struct rtw89_txpwr_table *byr_tbl; 3704 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3705 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3706 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3707 struct rtw89_tx_shape tx_shape; 3708 }; 3709 3710 struct rtw89_rfe_parms_conf { 3711 const struct rtw89_rfe_parms *rfe_parms; 3712 u8 rfe_type; 3713 }; 3714 3715 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3716 3717 struct rtw89_txpwr_conf { 3718 u8 rfe_type; 3719 u8 ent_sz; 3720 u32 num_ents; 3721 const void *data; 3722 }; 3723 3724 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3725 3726 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3727 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3728 memcpy(&(entry), cursor, \ 3729 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3730 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3731 (cursor) += (conf)->ent_sz, \ 3732 memcpy(&(entry), cursor, \ 3733 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3734 3735 struct rtw89_txpwr_byrate_data { 3736 struct rtw89_txpwr_conf conf; 3737 struct rtw89_txpwr_table tbl; 3738 }; 3739 3740 struct rtw89_txpwr_lmt_2ghz_data { 3741 struct rtw89_txpwr_conf conf; 3742 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3743 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3744 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3745 }; 3746 3747 struct rtw89_txpwr_lmt_5ghz_data { 3748 struct rtw89_txpwr_conf conf; 3749 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3750 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3751 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3752 }; 3753 3754 struct rtw89_txpwr_lmt_6ghz_data { 3755 struct rtw89_txpwr_conf conf; 3756 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3757 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3758 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3759 [RTW89_6G_CH_NUM]; 3760 }; 3761 3762 struct rtw89_txpwr_lmt_ru_2ghz_data { 3763 struct rtw89_txpwr_conf conf; 3764 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3765 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3766 }; 3767 3768 struct rtw89_txpwr_lmt_ru_5ghz_data { 3769 struct rtw89_txpwr_conf conf; 3770 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3771 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3772 }; 3773 3774 struct rtw89_txpwr_lmt_ru_6ghz_data { 3775 struct rtw89_txpwr_conf conf; 3776 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3777 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3778 [RTW89_6G_CH_NUM]; 3779 }; 3780 3781 struct rtw89_tx_shape_lmt_data { 3782 struct rtw89_txpwr_conf conf; 3783 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3784 }; 3785 3786 struct rtw89_tx_shape_lmt_ru_data { 3787 struct rtw89_txpwr_conf conf; 3788 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3789 }; 3790 3791 struct rtw89_rfe_data { 3792 struct rtw89_txpwr_byrate_data byrate; 3793 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3794 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3795 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3796 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3797 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3798 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3799 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3800 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3801 struct rtw89_rfe_parms rfe_parms; 3802 }; 3803 3804 struct rtw89_page_regs { 3805 u32 hci_fc_ctrl; 3806 u32 ch_page_ctrl; 3807 u32 ach_page_ctrl; 3808 u32 ach_page_info; 3809 u32 pub_page_info3; 3810 u32 pub_page_ctrl1; 3811 u32 pub_page_ctrl2; 3812 u32 pub_page_info1; 3813 u32 pub_page_info2; 3814 u32 wp_page_ctrl1; 3815 u32 wp_page_ctrl2; 3816 u32 wp_page_info1; 3817 }; 3818 3819 struct rtw89_imr_info { 3820 u32 wdrls_imr_set; 3821 u32 wsec_imr_reg; 3822 u32 wsec_imr_set; 3823 u32 mpdu_tx_imr_set; 3824 u32 mpdu_rx_imr_set; 3825 u32 sta_sch_imr_set; 3826 u32 txpktctl_imr_b0_reg; 3827 u32 txpktctl_imr_b0_clr; 3828 u32 txpktctl_imr_b0_set; 3829 u32 txpktctl_imr_b1_reg; 3830 u32 txpktctl_imr_b1_clr; 3831 u32 txpktctl_imr_b1_set; 3832 u32 wde_imr_clr; 3833 u32 wde_imr_set; 3834 u32 ple_imr_clr; 3835 u32 ple_imr_set; 3836 u32 host_disp_imr_clr; 3837 u32 host_disp_imr_set; 3838 u32 cpu_disp_imr_clr; 3839 u32 cpu_disp_imr_set; 3840 u32 other_disp_imr_clr; 3841 u32 other_disp_imr_set; 3842 u32 bbrpt_com_err_imr_reg; 3843 u32 bbrpt_chinfo_err_imr_reg; 3844 u32 bbrpt_err_imr_set; 3845 u32 bbrpt_dfs_err_imr_reg; 3846 u32 ptcl_imr_clr; 3847 u32 ptcl_imr_set; 3848 u32 cdma_imr_0_reg; 3849 u32 cdma_imr_0_clr; 3850 u32 cdma_imr_0_set; 3851 u32 cdma_imr_1_reg; 3852 u32 cdma_imr_1_clr; 3853 u32 cdma_imr_1_set; 3854 u32 phy_intf_imr_reg; 3855 u32 phy_intf_imr_clr; 3856 u32 phy_intf_imr_set; 3857 u32 rmac_imr_reg; 3858 u32 rmac_imr_clr; 3859 u32 rmac_imr_set; 3860 u32 tmac_imr_reg; 3861 u32 tmac_imr_clr; 3862 u32 tmac_imr_set; 3863 }; 3864 3865 struct rtw89_imr_table { 3866 const struct rtw89_reg_imr *regs; 3867 u32 n_regs; 3868 }; 3869 3870 struct rtw89_xtal_info { 3871 u32 xcap_reg; 3872 u32 sc_xo_mask; 3873 u32 sc_xi_mask; 3874 }; 3875 3876 struct rtw89_rrsr_cfgs { 3877 struct rtw89_reg3_def ref_rate; 3878 struct rtw89_reg3_def rsc; 3879 }; 3880 3881 struct rtw89_dig_regs { 3882 u32 seg0_pd_reg; 3883 u32 pd_lower_bound_mask; 3884 u32 pd_spatial_reuse_en; 3885 u32 bmode_pd_reg; 3886 u32 bmode_cca_rssi_limit_en; 3887 u32 bmode_pd_lower_bound_reg; 3888 u32 bmode_rssi_nocca_low_th_mask; 3889 struct rtw89_reg_def p0_lna_init; 3890 struct rtw89_reg_def p1_lna_init; 3891 struct rtw89_reg_def p0_tia_init; 3892 struct rtw89_reg_def p1_tia_init; 3893 struct rtw89_reg_def p0_rxb_init; 3894 struct rtw89_reg_def p1_rxb_init; 3895 struct rtw89_reg_def p0_p20_pagcugc_en; 3896 struct rtw89_reg_def p0_s20_pagcugc_en; 3897 struct rtw89_reg_def p1_p20_pagcugc_en; 3898 struct rtw89_reg_def p1_s20_pagcugc_en; 3899 }; 3900 3901 struct rtw89_edcca_regs { 3902 u32 edcca_level; 3903 u32 edcca_mask; 3904 u32 edcca_p_mask; 3905 u32 ppdu_level; 3906 u32 ppdu_mask; 3907 u32 rpt_a; 3908 u32 rpt_b; 3909 u32 rpt_sel; 3910 u32 rpt_sel_mask; 3911 u32 rpt_sel_be; 3912 u32 rpt_sel_be_mask; 3913 u32 tx_collision_t2r_st; 3914 u32 tx_collision_t2r_st_mask; 3915 }; 3916 3917 struct rtw89_phy_ul_tb_info { 3918 bool dyn_tb_tri_en; 3919 u8 def_if_bandedge; 3920 }; 3921 3922 struct rtw89_antdiv_stats { 3923 struct ewma_rssi cck_rssi_avg; 3924 struct ewma_rssi ofdm_rssi_avg; 3925 struct ewma_rssi non_legacy_rssi_avg; 3926 u16 pkt_cnt_cck; 3927 u16 pkt_cnt_ofdm; 3928 u16 pkt_cnt_non_legacy; 3929 u32 evm; 3930 }; 3931 3932 struct rtw89_antdiv_info { 3933 struct rtw89_antdiv_stats target_stats; 3934 struct rtw89_antdiv_stats main_stats; 3935 struct rtw89_antdiv_stats aux_stats; 3936 u8 training_count; 3937 u8 rssi_pre; 3938 bool get_stats; 3939 }; 3940 3941 enum rtw89_chanctx_state { 3942 RTW89_CHANCTX_STATE_MCC_START, 3943 RTW89_CHANCTX_STATE_MCC_STOP, 3944 }; 3945 3946 enum rtw89_chanctx_callbacks { 3947 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 3948 RTW89_CHANCTX_CALLBACK_RFK, 3949 3950 NUM_OF_RTW89_CHANCTX_CALLBACKS, 3951 }; 3952 3953 struct rtw89_chanctx_listener { 3954 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 3955 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 3956 }; 3957 3958 struct rtw89_chip_info { 3959 enum rtw89_core_chip_id chip_id; 3960 enum rtw89_chip_gen chip_gen; 3961 const struct rtw89_chip_ops *ops; 3962 const struct rtw89_mac_gen_def *mac_def; 3963 const struct rtw89_phy_gen_def *phy_def; 3964 const char *fw_basename; 3965 u8 fw_format_max; 3966 bool try_ce_fw; 3967 u8 bbmcu_nr; 3968 u32 needed_fw_elms; 3969 u32 fifo_size; 3970 bool small_fifo_size; 3971 u32 dle_scc_rsvd_size; 3972 u16 max_amsdu_limit; 3973 bool dis_2g_40m_ul_ofdma; 3974 u32 rsvd_ple_ofst; 3975 const struct rtw89_hfc_param_ini *hfc_param_ini; 3976 const struct rtw89_dle_mem *dle_mem; 3977 u8 wde_qempty_acq_grpnum; 3978 u8 wde_qempty_mgq_grpsel; 3979 u32 rf_base_addr[2]; 3980 u8 support_chanctx_num; 3981 u8 support_bands; 3982 u16 support_bandwidths; 3983 bool support_unii4; 3984 bool ul_tb_waveform_ctrl; 3985 bool ul_tb_pwr_diff; 3986 bool hw_sec_hdr; 3987 u8 rf_path_num; 3988 u8 tx_nss; 3989 u8 rx_nss; 3990 u8 acam_num; 3991 u8 bcam_num; 3992 u8 scam_num; 3993 u8 bacam_num; 3994 u8 bacam_dynamic_num; 3995 enum rtw89_bacam_ver bacam_ver; 3996 u8 ppdu_max_usr; 3997 3998 u8 sec_ctrl_efuse_size; 3999 u32 physical_efuse_size; 4000 u32 logical_efuse_size; 4001 u32 limit_efuse_size; 4002 u32 dav_phy_efuse_size; 4003 u32 dav_log_efuse_size; 4004 u32 phycap_addr; 4005 u32 phycap_size; 4006 const struct rtw89_efuse_block_cfg *efuse_blocks; 4007 4008 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4009 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4010 const struct rtw89_phy_table *bb_table; 4011 const struct rtw89_phy_table *bb_gain_table; 4012 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4013 const struct rtw89_phy_table *nctl_table; 4014 const struct rtw89_rfk_tbl *nctl_post_table; 4015 const struct rtw89_phy_dig_gain_table *dig_table; 4016 const struct rtw89_dig_regs *dig_regs; 4017 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4018 4019 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4020 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4021 const struct rtw89_rfe_parms *dflt_parms; 4022 const struct rtw89_chanctx_listener *chanctx_listener; 4023 4024 u8 txpwr_factor_rf; 4025 u8 txpwr_factor_mac; 4026 4027 u32 para_ver; 4028 u32 wlcx_desired; 4029 u8 btcx_desired; 4030 u8 scbd; 4031 u8 mailbox; 4032 4033 u8 afh_guard_ch; 4034 const u8 *wl_rssi_thres; 4035 const u8 *bt_rssi_thres; 4036 u8 rssi_tol; 4037 4038 u8 mon_reg_num; 4039 const struct rtw89_btc_fbtc_mreg *mon_reg; 4040 u8 rf_para_ulink_num; 4041 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4042 u8 rf_para_dlink_num; 4043 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4044 u8 ps_mode_supported; 4045 u8 low_power_hci_modes; 4046 4047 u32 h2c_cctl_func_id; 4048 u32 hci_func_en_addr; 4049 u32 h2c_desc_size; 4050 u32 txwd_body_size; 4051 u32 txwd_info_size; 4052 u32 h2c_ctrl_reg; 4053 const u32 *h2c_regs; 4054 struct rtw89_reg_def h2c_counter_reg; 4055 u32 c2h_ctrl_reg; 4056 const u32 *c2h_regs; 4057 struct rtw89_reg_def c2h_counter_reg; 4058 const struct rtw89_page_regs *page_regs; 4059 u32 wow_reason_reg; 4060 bool cfo_src_fd; 4061 bool cfo_hw_comp; 4062 const struct rtw89_reg_def *dcfo_comp; 4063 u8 dcfo_comp_sft; 4064 const struct rtw89_imr_info *imr_info; 4065 const struct rtw89_imr_table *imr_dmac_table; 4066 const struct rtw89_imr_table *imr_cmac_table; 4067 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4068 struct rtw89_reg_def bss_clr_vld; 4069 u32 bss_clr_map_reg; 4070 u32 dma_ch_mask; 4071 const struct rtw89_edcca_regs *edcca_regs; 4072 const struct wiphy_wowlan_support *wowlan_stub; 4073 const struct rtw89_xtal_info *xtal_info; 4074 }; 4075 4076 union rtw89_bus_info { 4077 const struct rtw89_pci_info *pci; 4078 }; 4079 4080 struct rtw89_driver_info { 4081 const struct rtw89_chip_info *chip; 4082 union rtw89_bus_info bus; 4083 }; 4084 4085 enum rtw89_hcifc_mode { 4086 RTW89_HCIFC_POH = 0, 4087 RTW89_HCIFC_STF = 1, 4088 RTW89_HCIFC_SDIO = 2, 4089 4090 /* keep last */ 4091 RTW89_HCIFC_MODE_INVALID, 4092 }; 4093 4094 struct rtw89_dle_info { 4095 const struct rtw89_rsvd_quota *rsvd_qt; 4096 enum rtw89_qta_mode qta_mode; 4097 u16 ple_pg_size; 4098 u16 ple_free_pg; 4099 u16 c0_rx_qta; 4100 u16 c1_rx_qta; 4101 }; 4102 4103 enum rtw89_host_rpr_mode { 4104 RTW89_RPR_MODE_POH = 0, 4105 RTW89_RPR_MODE_STF 4106 }; 4107 4108 #define RTW89_COMPLETION_BUF_SIZE 40 4109 #define RTW89_WAIT_COND_IDLE UINT_MAX 4110 4111 struct rtw89_completion_data { 4112 bool err; 4113 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4114 }; 4115 4116 struct rtw89_wait_info { 4117 atomic_t cond; 4118 struct completion completion; 4119 struct rtw89_completion_data data; 4120 }; 4121 4122 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4123 4124 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4125 { 4126 init_completion(&wait->completion); 4127 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4128 } 4129 4130 struct rtw89_mac_info { 4131 struct rtw89_dle_info dle_info; 4132 struct rtw89_hfc_param hfc_param; 4133 enum rtw89_qta_mode qta_mode; 4134 u8 rpwm_seq_num; 4135 u8 cpwm_seq_num; 4136 4137 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4138 struct rtw89_wait_info fw_ofld_wait; 4139 }; 4140 4141 enum rtw89_fwdl_check_type { 4142 RTW89_FWDL_CHECK_FREERTOS_DONE, 4143 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4144 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4145 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4146 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4147 }; 4148 4149 enum rtw89_fw_type { 4150 RTW89_FW_NORMAL = 1, 4151 RTW89_FW_WOWLAN = 3, 4152 RTW89_FW_NORMAL_CE = 5, 4153 RTW89_FW_BBMCU0 = 64, 4154 RTW89_FW_BBMCU1 = 65, 4155 RTW89_FW_LOGFMT = 255, 4156 }; 4157 4158 enum rtw89_fw_feature { 4159 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4160 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4161 RTW89_FW_FEATURE_TX_WAKE, 4162 RTW89_FW_FEATURE_CRASH_TRIGGER, 4163 RTW89_FW_FEATURE_NO_PACKET_DROP, 4164 RTW89_FW_FEATURE_NO_DEEP_PS, 4165 RTW89_FW_FEATURE_NO_LPS_PG, 4166 RTW89_FW_FEATURE_BEACON_FILTER, 4167 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4168 }; 4169 4170 struct rtw89_fw_suit { 4171 enum rtw89_fw_type type; 4172 const u8 *data; 4173 u32 size; 4174 u8 major_ver; 4175 u8 minor_ver; 4176 u8 sub_ver; 4177 u8 sub_idex; 4178 u16 build_year; 4179 u16 build_mon; 4180 u16 build_date; 4181 u16 build_hour; 4182 u16 build_min; 4183 u8 cmd_ver; 4184 u8 hdr_ver; 4185 u32 commitid; 4186 }; 4187 4188 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4189 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4190 #define RTW89_FW_SUIT_VER_CODE(s) \ 4191 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4192 4193 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4194 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4195 (mfw_hdr)->ver.minor, \ 4196 (mfw_hdr)->ver.sub, \ 4197 (mfw_hdr)->ver.idx) 4198 4199 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4200 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4201 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4202 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4203 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4204 4205 struct rtw89_fw_req_info { 4206 const struct firmware *firmware; 4207 struct completion completion; 4208 }; 4209 4210 struct rtw89_fw_log { 4211 struct rtw89_fw_suit suit; 4212 bool enable; 4213 u32 last_fmt_id; 4214 u32 fmt_count; 4215 const __le32 *fmt_ids; 4216 const char *(*fmts)[]; 4217 }; 4218 4219 struct rtw89_fw_elm_info { 4220 struct rtw89_phy_table *bb_tbl; 4221 struct rtw89_phy_table *bb_gain; 4222 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4223 struct rtw89_phy_table *rf_nctl; 4224 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4225 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4226 }; 4227 4228 enum rtw89_fw_mss_dev_type { 4229 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4230 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4231 }; 4232 4233 struct rtw89_fw_secure { 4234 bool secure_boot; 4235 u32 sb_sel_mgn; 4236 u8 mss_dev_type; 4237 u8 mss_cust_idx; 4238 u8 mss_key_num; 4239 }; 4240 4241 struct rtw89_fw_info { 4242 struct rtw89_fw_req_info req; 4243 int fw_format; 4244 u8 h2c_seq; 4245 u8 rec_seq; 4246 u8 h2c_counter; 4247 u8 c2h_counter; 4248 struct rtw89_fw_suit normal; 4249 struct rtw89_fw_suit wowlan; 4250 struct rtw89_fw_suit bbmcu0; 4251 struct rtw89_fw_suit bbmcu1; 4252 struct rtw89_fw_log log; 4253 u32 feature_map; 4254 struct rtw89_fw_elm_info elm_info; 4255 struct rtw89_fw_secure sec; 4256 }; 4257 4258 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4259 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4260 4261 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4262 ((_fw)->feature_map |= BIT(_fw_feature)) 4263 4264 struct rtw89_cam_info { 4265 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4266 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4267 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4268 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4269 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4270 }; 4271 4272 enum rtw89_sar_sources { 4273 RTW89_SAR_SOURCE_NONE, 4274 RTW89_SAR_SOURCE_COMMON, 4275 4276 RTW89_SAR_SOURCE_NR, 4277 }; 4278 4279 enum rtw89_sar_subband { 4280 RTW89_SAR_2GHZ_SUBBAND, 4281 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4282 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4283 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4284 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4285 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4286 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4287 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4288 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4289 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4290 4291 RTW89_SAR_SUBBAND_NR, 4292 }; 4293 4294 struct rtw89_sar_cfg_common { 4295 bool set[RTW89_SAR_SUBBAND_NR]; 4296 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4297 }; 4298 4299 struct rtw89_sar_info { 4300 /* used to decide how to acces SAR cfg union */ 4301 enum rtw89_sar_sources src; 4302 4303 /* reserved for different knids of SAR cfg struct. 4304 * supposed that a single cfg struct cannot handle various SAR sources. 4305 */ 4306 union { 4307 struct rtw89_sar_cfg_common cfg_common; 4308 }; 4309 }; 4310 4311 enum rtw89_tas_state { 4312 RTW89_TAS_STATE_DPR_OFF, 4313 RTW89_TAS_STATE_DPR_ON, 4314 RTW89_TAS_STATE_DPR_FORBID, 4315 }; 4316 4317 #define RTW89_TAS_MAX_WINDOW 50 4318 struct rtw89_tas_info { 4319 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4320 s32 total_txpwr; 4321 u8 cur_idx; 4322 s8 dpr_gap; 4323 s8 delta; 4324 enum rtw89_tas_state state; 4325 bool enable; 4326 }; 4327 4328 struct rtw89_chanctx_cfg { 4329 enum rtw89_sub_entity_idx idx; 4330 int ref_count; 4331 }; 4332 4333 enum rtw89_chanctx_changes { 4334 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4335 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4336 RTW89_CHANCTX_P2P_PS_CHANGE, 4337 RTW89_CHANCTX_BT_SLOT_CHANGE, 4338 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4339 4340 NUM_OF_RTW89_CHANCTX_CHANGES, 4341 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4342 }; 4343 4344 enum rtw89_entity_mode { 4345 RTW89_ENTITY_MODE_SCC, 4346 RTW89_ENTITY_MODE_MCC_PREPARE, 4347 RTW89_ENTITY_MODE_MCC, 4348 4349 NUM_OF_RTW89_ENTITY_MODE, 4350 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4351 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4352 }; 4353 4354 struct rtw89_sub_entity { 4355 struct cfg80211_chan_def chandef; 4356 struct rtw89_chan chan; 4357 struct rtw89_chan_rcd rcd; 4358 4359 /* only assigned when running with chanctx_ops */ 4360 struct rtw89_chanctx_cfg *cfg; 4361 }; 4362 4363 struct rtw89_edcca_bak { 4364 u8 a; 4365 u8 p; 4366 u8 ppdu; 4367 u8 th_old; 4368 }; 4369 4370 enum rtw89_dm_type { 4371 RTW89_DM_DYNAMIC_EDCCA, 4372 }; 4373 4374 struct rtw89_hal { 4375 u32 rx_fltr; 4376 u8 cv; 4377 u8 acv; 4378 u32 antenna_tx; 4379 u32 antenna_rx; 4380 u8 tx_nss; 4381 u8 rx_nss; 4382 bool tx_path_diversity; 4383 bool ant_diversity; 4384 bool ant_diversity_fixed; 4385 bool support_cckpd; 4386 bool support_igi; 4387 atomic_t roc_entity_idx; 4388 4389 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4390 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4391 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4392 struct cfg80211_chan_def roc_chandef; 4393 4394 bool entity_active; 4395 bool entity_pause; 4396 enum rtw89_entity_mode entity_mode; 4397 4398 struct rtw89_edcca_bak edcca_bak; 4399 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4400 }; 4401 4402 #define RTW89_MAX_MAC_ID_NUM 128 4403 #define RTW89_MAX_PKT_OFLD_NUM 255 4404 4405 enum rtw89_flags { 4406 RTW89_FLAG_POWERON, 4407 RTW89_FLAG_DMAC_FUNC, 4408 RTW89_FLAG_CMAC0_FUNC, 4409 RTW89_FLAG_CMAC1_FUNC, 4410 RTW89_FLAG_FW_RDY, 4411 RTW89_FLAG_RUNNING, 4412 RTW89_FLAG_PROBE_DONE, 4413 RTW89_FLAG_BFEE_MON, 4414 RTW89_FLAG_BFEE_EN, 4415 RTW89_FLAG_BFEE_TIMER_KEEP, 4416 RTW89_FLAG_NAPI_RUNNING, 4417 RTW89_FLAG_LEISURE_PS, 4418 RTW89_FLAG_LOW_POWER_MODE, 4419 RTW89_FLAG_INACTIVE_PS, 4420 RTW89_FLAG_CRASH_SIMULATING, 4421 RTW89_FLAG_SER_HANDLING, 4422 RTW89_FLAG_WOWLAN, 4423 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4424 RTW89_FLAG_CHANGING_INTERFACE, 4425 4426 NUM_OF_RTW89_FLAGS, 4427 }; 4428 4429 enum rtw89_pkt_drop_sel { 4430 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4431 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4432 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4433 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4434 RTW89_PKT_DROP_SEL_MACID_ALL, 4435 RTW89_PKT_DROP_SEL_MG0_ONCE, 4436 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4437 RTW89_PKT_DROP_SEL_HIQ_PORT, 4438 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4439 RTW89_PKT_DROP_SEL_BAND, 4440 RTW89_PKT_DROP_SEL_BAND_ONCE, 4441 RTW89_PKT_DROP_SEL_REL_MACID, 4442 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4443 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4444 }; 4445 4446 struct rtw89_pkt_drop_params { 4447 enum rtw89_pkt_drop_sel sel; 4448 enum rtw89_mac_idx mac_band; 4449 u8 macid; 4450 u8 port; 4451 u8 mbssid; 4452 bool tf_trs; 4453 u32 macid_band_sel[4]; 4454 }; 4455 4456 struct rtw89_pkt_stat { 4457 u16 beacon_nr; 4458 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4459 }; 4460 4461 DECLARE_EWMA(thermal, 4, 4); 4462 4463 struct rtw89_phy_stat { 4464 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4465 struct rtw89_pkt_stat cur_pkt_stat; 4466 struct rtw89_pkt_stat last_pkt_stat; 4467 }; 4468 4469 enum rtw89_rfk_report_state { 4470 RTW89_RFK_STATE_START = 0x0, 4471 RTW89_RFK_STATE_OK = 0x1, 4472 RTW89_RFK_STATE_FAIL = 0x2, 4473 RTW89_RFK_STATE_TIMEOUT = 0x3, 4474 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4475 }; 4476 4477 struct rtw89_rfk_wait_info { 4478 struct completion completion; 4479 ktime_t start_time; 4480 enum rtw89_rfk_report_state state; 4481 u8 version; 4482 }; 4483 4484 #define RTW89_DACK_PATH_NR 2 4485 #define RTW89_DACK_IDX_NR 2 4486 #define RTW89_DACK_MSBK_NR 16 4487 struct rtw89_dack_info { 4488 bool dack_done; 4489 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4490 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4491 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4492 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4493 u32 dack_cnt; 4494 bool addck_timeout[RTW89_DACK_PATH_NR]; 4495 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4496 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4497 }; 4498 4499 #define RTW89_RFK_CHS_NR 3 4500 4501 struct rtw89_rfk_mcc_info { 4502 u8 ch[RTW89_RFK_CHS_NR]; 4503 u8 band[RTW89_RFK_CHS_NR]; 4504 u8 bw[RTW89_RFK_CHS_NR]; 4505 u8 table_idx; 4506 }; 4507 4508 #define RTW89_IQK_CHS_NR 2 4509 #define RTW89_IQK_PATH_NR 4 4510 4511 struct rtw89_lck_info { 4512 u8 thermal[RF_PATH_MAX]; 4513 }; 4514 4515 struct rtw89_rx_dck_info { 4516 u8 thermal[RF_PATH_MAX]; 4517 }; 4518 4519 struct rtw89_iqk_info { 4520 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4521 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4522 bool lok_fail[RTW89_IQK_PATH_NR]; 4523 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4524 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4525 u32 iqk_fail_cnt; 4526 bool is_iqk_init; 4527 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4528 u8 iqk_band[RTW89_IQK_PATH_NR]; 4529 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4530 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4531 u8 iqk_times; 4532 u8 version; 4533 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4534 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4535 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4536 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4537 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4538 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4539 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4540 bool is_nbiqk; 4541 bool iqk_fft_en; 4542 bool iqk_xym_en; 4543 bool iqk_sram_en; 4544 bool iqk_cfir_en; 4545 u32 syn1to2; 4546 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4547 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4548 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4549 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4550 }; 4551 4552 #define RTW89_DPK_RF_PATH 2 4553 #define RTW89_DPK_AVG_THERMAL_NUM 8 4554 #define RTW89_DPK_BKUP_NUM 2 4555 struct rtw89_dpk_bkup_para { 4556 enum rtw89_band band; 4557 enum rtw89_bandwidth bw; 4558 u8 ch; 4559 bool path_ok; 4560 u8 mdpd_en; 4561 u8 txagc_dpk; 4562 u8 ther_dpk; 4563 u8 gs; 4564 u16 pwsf; 4565 }; 4566 4567 struct rtw89_dpk_info { 4568 bool is_dpk_enable; 4569 bool is_dpk_reload_en; 4570 u8 dpk_gs[RTW89_PHY_MAX]; 4571 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4572 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4573 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4574 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4575 u8 cur_idx[RTW89_DPK_RF_PATH]; 4576 u8 cur_k_set; 4577 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4578 }; 4579 4580 struct rtw89_fem_info { 4581 bool elna_2g; 4582 bool elna_5g; 4583 bool epa_2g; 4584 bool epa_5g; 4585 bool epa_6g; 4586 }; 4587 4588 struct rtw89_phy_ch_info { 4589 u8 rssi_min; 4590 u16 rssi_min_macid; 4591 u8 pre_rssi_min; 4592 u8 rssi_max; 4593 u16 rssi_max_macid; 4594 u8 rxsc_160; 4595 u8 rxsc_80; 4596 u8 rxsc_40; 4597 u8 rxsc_20; 4598 u8 rxsc_l; 4599 u8 is_noisy; 4600 }; 4601 4602 struct rtw89_agc_gaincode_set { 4603 u8 lna_idx; 4604 u8 tia_idx; 4605 u8 rxb_idx; 4606 }; 4607 4608 #define IGI_RSSI_TH_NUM 5 4609 #define FA_TH_NUM 4 4610 #define LNA_GAIN_NUM 7 4611 #define TIA_GAIN_NUM 2 4612 struct rtw89_dig_info { 4613 struct rtw89_agc_gaincode_set cur_gaincode; 4614 bool force_gaincode_idx_en; 4615 struct rtw89_agc_gaincode_set force_gaincode; 4616 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4617 u16 fa_th[FA_TH_NUM]; 4618 u8 igi_rssi; 4619 u8 igi_fa_rssi; 4620 u8 fa_rssi_ofst; 4621 u8 dyn_igi_max; 4622 u8 dyn_igi_min; 4623 bool dyn_pd_th_en; 4624 u8 dyn_pd_th_max; 4625 u8 pd_low_th_ofst; 4626 u8 ib_pbk; 4627 s8 ib_pkpwr; 4628 s8 lna_gain_a[LNA_GAIN_NUM]; 4629 s8 lna_gain_g[LNA_GAIN_NUM]; 4630 s8 *lna_gain; 4631 s8 tia_gain_a[TIA_GAIN_NUM]; 4632 s8 tia_gain_g[TIA_GAIN_NUM]; 4633 s8 *tia_gain; 4634 bool is_linked_pre; 4635 bool bypass_dig; 4636 }; 4637 4638 enum rtw89_multi_cfo_mode { 4639 RTW89_PKT_BASED_AVG_MODE = 0, 4640 RTW89_ENTRY_BASED_AVG_MODE = 1, 4641 RTW89_TP_BASED_AVG_MODE = 2, 4642 }; 4643 4644 enum rtw89_phy_cfo_status { 4645 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4646 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4647 RTW89_PHY_DCFO_STATE_HOLD = 2, 4648 RTW89_PHY_DCFO_STATE_MAX 4649 }; 4650 4651 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4652 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4653 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4654 }; 4655 4656 struct rtw89_cfo_tracking_info { 4657 u16 cfo_timer_ms; 4658 bool cfo_trig_by_timer_en; 4659 enum rtw89_phy_cfo_status phy_cfo_status; 4660 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4661 u8 phy_cfo_trk_cnt; 4662 bool is_adjust; 4663 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4664 bool apply_compensation; 4665 u8 crystal_cap; 4666 u8 crystal_cap_default; 4667 u8 def_x_cap; 4668 s8 x_cap_ofst; 4669 u32 sta_cfo_tolerance; 4670 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4671 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4672 s32 cfo_avg_pre; 4673 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4674 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4675 s32 dcfo_avg; 4676 s32 dcfo_avg_pre; 4677 u32 packet_count; 4678 u32 packet_count_pre; 4679 s32 residual_cfo_acc; 4680 u8 phy_cfotrk_state; 4681 u8 phy_cfotrk_cnt; 4682 bool divergence_lock_en; 4683 u8 x_cap_lb; 4684 u8 x_cap_ub; 4685 u8 lock_cnt; 4686 }; 4687 4688 enum rtw89_tssi_mode { 4689 RTW89_TSSI_NORMAL = 0, 4690 RTW89_TSSI_SCAN = 1, 4691 }; 4692 4693 enum rtw89_tssi_alimk_band { 4694 TSSI_ALIMK_2G = 0, 4695 TSSI_ALIMK_5GL, 4696 TSSI_ALIMK_5GM, 4697 TSSI_ALIMK_5GH, 4698 TSSI_ALIMK_MAX 4699 }; 4700 4701 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4702 #define TSSI_TRIM_CH_GROUP_NUM 8 4703 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4704 4705 #define TSSI_CCK_CH_GROUP_NUM 6 4706 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4707 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4708 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4709 #define TSSI_MCS_CH_GROUP_NUM \ 4710 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4711 #define TSSI_MAX_CH_NUM 67 4712 #define TSSI_ALIMK_VALUE_NUM 8 4713 4714 struct rtw89_tssi_info { 4715 u8 thermal[RF_PATH_MAX]; 4716 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4717 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4718 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4719 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4720 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4721 s8 extra_ofst[RF_PATH_MAX]; 4722 bool tssi_tracking_check[RF_PATH_MAX]; 4723 u8 default_txagc_offset[RF_PATH_MAX]; 4724 u32 base_thermal[RF_PATH_MAX]; 4725 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4726 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4727 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4728 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4729 u32 tssi_alimk_time; 4730 }; 4731 4732 struct rtw89_power_trim_info { 4733 bool pg_thermal_trim; 4734 bool pg_pa_bias_trim; 4735 u8 thermal_trim[RF_PATH_MAX]; 4736 u8 pa_bias_trim[RF_PATH_MAX]; 4737 u8 pad_bias_trim[RF_PATH_MAX]; 4738 }; 4739 4740 struct rtw89_regd { 4741 char alpha2[3]; 4742 u8 txpwr_regd[RTW89_BAND_NUM]; 4743 }; 4744 4745 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4746 4747 struct rtw89_regulatory_info { 4748 const struct rtw89_regd *regd; 4749 enum rtw89_reg_6ghz_power reg_6ghz_power; 4750 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4751 }; 4752 4753 enum rtw89_ifs_clm_application { 4754 RTW89_IFS_CLM_INIT = 0, 4755 RTW89_IFS_CLM_BACKGROUND = 1, 4756 RTW89_IFS_CLM_ACS = 2, 4757 RTW89_IFS_CLM_DIG = 3, 4758 RTW89_IFS_CLM_TDMA_DIG = 4, 4759 RTW89_IFS_CLM_DBG = 5, 4760 RTW89_IFS_CLM_DBG_MANUAL = 6 4761 }; 4762 4763 enum rtw89_env_racing_lv { 4764 RTW89_RAC_RELEASE = 0, 4765 RTW89_RAC_LV_1 = 1, 4766 RTW89_RAC_LV_2 = 2, 4767 RTW89_RAC_LV_3 = 3, 4768 RTW89_RAC_LV_4 = 4, 4769 RTW89_RAC_MAX_NUM = 5 4770 }; 4771 4772 struct rtw89_ccx_para_info { 4773 enum rtw89_env_racing_lv rac_lv; 4774 u16 mntr_time; 4775 u8 nhm_manual_th_ofst; 4776 u8 nhm_manual_th0; 4777 enum rtw89_ifs_clm_application ifs_clm_app; 4778 u32 ifs_clm_manual_th_times; 4779 u32 ifs_clm_manual_th0; 4780 u8 fahm_manual_th_ofst; 4781 u8 fahm_manual_th0; 4782 u8 fahm_numer_opt; 4783 u8 fahm_denom_opt; 4784 }; 4785 4786 enum rtw89_ccx_edcca_opt_sc_idx { 4787 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4788 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4789 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4790 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4791 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4792 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4793 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4794 RTW89_CCX_EDCCA_SEG1_S3 = 7 4795 }; 4796 4797 enum rtw89_ccx_edcca_opt_bw_idx { 4798 RTW89_CCX_EDCCA_BW20_0 = 0, 4799 RTW89_CCX_EDCCA_BW20_1 = 1, 4800 RTW89_CCX_EDCCA_BW20_2 = 2, 4801 RTW89_CCX_EDCCA_BW20_3 = 3, 4802 RTW89_CCX_EDCCA_BW20_4 = 4, 4803 RTW89_CCX_EDCCA_BW20_5 = 5, 4804 RTW89_CCX_EDCCA_BW20_6 = 6, 4805 RTW89_CCX_EDCCA_BW20_7 = 7 4806 }; 4807 4808 #define RTW89_NHM_TH_NUM 11 4809 #define RTW89_FAHM_TH_NUM 11 4810 #define RTW89_NHM_RPT_NUM 12 4811 #define RTW89_FAHM_RPT_NUM 12 4812 #define RTW89_IFS_CLM_NUM 4 4813 struct rtw89_env_monitor_info { 4814 u8 ccx_watchdog_result; 4815 bool ccx_ongoing; 4816 u8 ccx_rac_lv; 4817 bool ccx_manual_ctrl; 4818 u16 ifs_clm_mntr_time; 4819 enum rtw89_ifs_clm_application ifs_clm_app; 4820 u16 ccx_period; 4821 u8 ccx_unit_idx; 4822 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4823 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4824 u16 ifs_clm_tx; 4825 u16 ifs_clm_edcca_excl_cca; 4826 u16 ifs_clm_ofdmfa; 4827 u16 ifs_clm_ofdmcca_excl_fa; 4828 u16 ifs_clm_cckfa; 4829 u16 ifs_clm_cckcca_excl_fa; 4830 u16 ifs_clm_total_ifs; 4831 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4832 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4833 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4834 u8 ifs_clm_tx_ratio; 4835 u8 ifs_clm_edcca_excl_cca_ratio; 4836 u8 ifs_clm_cck_fa_ratio; 4837 u8 ifs_clm_ofdm_fa_ratio; 4838 u8 ifs_clm_cck_cca_excl_fa_ratio; 4839 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4840 u16 ifs_clm_cck_fa_permil; 4841 u16 ifs_clm_ofdm_fa_permil; 4842 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4843 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4844 }; 4845 4846 enum rtw89_ser_rcvy_step { 4847 RTW89_SER_DRV_STOP_TX, 4848 RTW89_SER_DRV_STOP_RX, 4849 RTW89_SER_DRV_STOP_RUN, 4850 RTW89_SER_HAL_STOP_DMA, 4851 RTW89_SER_SUPPRESS_LOG, 4852 RTW89_NUM_OF_SER_FLAGS 4853 }; 4854 4855 struct rtw89_ser { 4856 u8 state; 4857 u8 alarm_event; 4858 bool prehandle_l1; 4859 4860 struct work_struct ser_hdl_work; 4861 struct delayed_work ser_alarm_work; 4862 const struct state_ent *st_tbl; 4863 const struct event_ent *ev_tbl; 4864 struct list_head msg_q; 4865 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4866 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4867 }; 4868 4869 enum rtw89_mac_ax_ps_mode { 4870 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4871 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4872 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4873 RTW89_MAC_AX_PS_MODE_MAX = 3, 4874 }; 4875 4876 enum rtw89_last_rpwm_mode { 4877 RTW89_LAST_RPWM_PS = 0x0, 4878 RTW89_LAST_RPWM_ACTIVE = 0x6, 4879 }; 4880 4881 struct rtw89_lps_parm { 4882 u8 macid; 4883 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4884 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4885 }; 4886 4887 struct rtw89_ppdu_sts_info { 4888 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4889 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4890 }; 4891 4892 struct rtw89_early_h2c { 4893 struct list_head list; 4894 u8 *h2c; 4895 u16 h2c_len; 4896 }; 4897 4898 struct rtw89_hw_scan_info { 4899 struct ieee80211_vif *scanning_vif; 4900 struct list_head pkt_list[NUM_NL80211_BANDS]; 4901 struct rtw89_chan op_chan; 4902 bool abort; 4903 u32 last_chan_idx; 4904 }; 4905 4906 enum rtw89_phy_bb_gain_band { 4907 RTW89_BB_GAIN_BAND_2G = 0, 4908 RTW89_BB_GAIN_BAND_5G_L = 1, 4909 RTW89_BB_GAIN_BAND_5G_M = 2, 4910 RTW89_BB_GAIN_BAND_5G_H = 3, 4911 RTW89_BB_GAIN_BAND_6G_L = 4, 4912 RTW89_BB_GAIN_BAND_6G_M = 5, 4913 RTW89_BB_GAIN_BAND_6G_H = 6, 4914 RTW89_BB_GAIN_BAND_6G_UH = 7, 4915 4916 RTW89_BB_GAIN_BAND_NR, 4917 }; 4918 4919 enum rtw89_phy_gain_band_be { 4920 RTW89_BB_GAIN_BAND_2G_BE = 0, 4921 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 4922 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 4923 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 4924 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 4925 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 4926 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 4927 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 4928 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 4929 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 4930 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 4931 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 4932 4933 RTW89_BB_GAIN_BAND_NR_BE, 4934 }; 4935 4936 enum rtw89_phy_bb_bw_be { 4937 RTW89_BB_BW_20_40 = 0, 4938 RTW89_BB_BW_80_160_320 = 1, 4939 4940 RTW89_BB_BW_NR_BE, 4941 }; 4942 4943 enum rtw89_bw20_sc { 4944 RTW89_BW20_SC_20M = 1, 4945 RTW89_BW20_SC_40M = 2, 4946 RTW89_BW20_SC_80M = 4, 4947 RTW89_BW20_SC_160M = 8, 4948 RTW89_BW20_SC_320M = 16, 4949 }; 4950 4951 enum rtw89_cmac_table_bw { 4952 RTW89_CMAC_BW_20M = 0, 4953 RTW89_CMAC_BW_40M = 1, 4954 RTW89_CMAC_BW_80M = 2, 4955 RTW89_CMAC_BW_160M = 3, 4956 RTW89_CMAC_BW_320M = 4, 4957 4958 RTW89_CMAC_BW_NR, 4959 }; 4960 4961 enum rtw89_phy_bb_rxsc_num { 4962 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4963 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4964 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4965 }; 4966 4967 struct rtw89_phy_bb_gain_info { 4968 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4969 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4970 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4971 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4972 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4973 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4974 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4975 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4976 [RTW89_BB_RXSC_NUM_40]; 4977 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4978 [RTW89_BB_RXSC_NUM_80]; 4979 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4980 [RTW89_BB_RXSC_NUM_160]; 4981 }; 4982 4983 struct rtw89_phy_bb_gain_info_be { 4984 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 4985 [LNA_GAIN_NUM]; 4986 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 4987 [TIA_GAIN_NUM]; 4988 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4989 [RF_PATH_MAX][LNA_GAIN_NUM]; 4990 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4991 [RF_PATH_MAX][LNA_GAIN_NUM]; 4992 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4993 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 4994 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4995 [RTW89_BW20_SC_20M]; 4996 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4997 [RTW89_BW20_SC_40M]; 4998 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 4999 [RTW89_BW20_SC_80M]; 5000 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5001 [RTW89_BW20_SC_160M]; 5002 }; 5003 5004 struct rtw89_phy_efuse_gain { 5005 bool offset_valid; 5006 bool comp_valid; 5007 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5008 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5009 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5010 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5011 }; 5012 5013 #define RTW89_MAX_PATTERN_NUM 18 5014 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5015 #define RTW89_MAX_PATTERN_SIZE 128 5016 5017 struct rtw89_wow_cam_info { 5018 bool r_w; 5019 u8 idx; 5020 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5021 u16 crc; 5022 bool negative_pattern_match; 5023 bool skip_mac_hdr; 5024 bool uc; 5025 bool mc; 5026 bool bc; 5027 bool valid; 5028 }; 5029 5030 struct rtw89_wow_param { 5031 struct ieee80211_vif *wow_vif; 5032 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5033 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5034 u8 pattern_cnt; 5035 }; 5036 5037 struct rtw89_mcc_limit { 5038 bool enable; 5039 u16 max_tob; /* TU; max time offset behind */ 5040 u16 max_toa; /* TU; max time offset ahead */ 5041 u16 max_dur; /* TU */ 5042 }; 5043 5044 struct rtw89_mcc_policy { 5045 u8 c2h_rpt; 5046 u8 tx_null_early; 5047 u8 dis_tx_null; 5048 u8 in_curr_ch; 5049 u8 dis_sw_retry; 5050 u8 sw_retry_count; 5051 }; 5052 5053 struct rtw89_mcc_role { 5054 struct rtw89_vif *rtwvif; 5055 struct rtw89_mcc_policy policy; 5056 struct rtw89_mcc_limit limit; 5057 5058 /* only valid when running with FW MRC mechanism */ 5059 u8 slot_idx; 5060 5061 /* byte-array in LE order for FW */ 5062 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5063 5064 u16 duration; /* TU */ 5065 u16 beacon_interval; /* TU */ 5066 bool is_2ghz; 5067 bool is_go; 5068 bool is_gc; 5069 }; 5070 5071 struct rtw89_mcc_bt_role { 5072 u16 duration; /* TU */ 5073 }; 5074 5075 struct rtw89_mcc_courtesy { 5076 bool enable; 5077 u8 slot_num; 5078 u8 macid_src; 5079 u8 macid_tgt; 5080 }; 5081 5082 enum rtw89_mcc_plan { 5083 RTW89_MCC_PLAN_TAIL_BT, 5084 RTW89_MCC_PLAN_MID_BT, 5085 RTW89_MCC_PLAN_NO_BT, 5086 5087 NUM_OF_RTW89_MCC_PLAN, 5088 }; 5089 5090 struct rtw89_mcc_pattern { 5091 s16 tob_ref; /* TU; time offset behind of reference role */ 5092 s16 toa_ref; /* TU; time offset ahead of reference role */ 5093 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5094 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5095 5096 enum rtw89_mcc_plan plan; 5097 struct rtw89_mcc_courtesy courtesy; 5098 }; 5099 5100 struct rtw89_mcc_sync { 5101 bool enable; 5102 u16 offset; /* TU */ 5103 u8 macid_src; 5104 u8 band_src; 5105 u8 port_src; 5106 u8 macid_tgt; 5107 u8 band_tgt; 5108 u8 port_tgt; 5109 }; 5110 5111 struct rtw89_mcc_config { 5112 struct rtw89_mcc_pattern pattern; 5113 struct rtw89_mcc_sync sync; 5114 u64 start_tsf; 5115 u16 mcc_interval; /* TU */ 5116 u16 beacon_offset; /* TU */ 5117 }; 5118 5119 enum rtw89_mcc_mode { 5120 RTW89_MCC_MODE_GO_STA, 5121 RTW89_MCC_MODE_GC_STA, 5122 }; 5123 5124 struct rtw89_mcc_info { 5125 struct rtw89_wait_info wait; 5126 5127 u8 group; 5128 enum rtw89_mcc_mode mode; 5129 struct rtw89_mcc_role role_ref; /* reference role */ 5130 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5131 struct rtw89_mcc_bt_role bt_role; 5132 struct rtw89_mcc_config config; 5133 }; 5134 5135 struct rtw89_dev { 5136 struct ieee80211_hw *hw; 5137 struct device *dev; 5138 const struct ieee80211_ops *ops; 5139 5140 bool dbcc_en; 5141 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5142 struct rtw89_hw_scan_info scan_info; 5143 const struct rtw89_chip_info *chip; 5144 const struct rtw89_pci_info *pci_info; 5145 const struct rtw89_rfe_parms *rfe_parms; 5146 struct rtw89_hal hal; 5147 struct rtw89_mcc_info mcc; 5148 struct rtw89_mac_info mac; 5149 struct rtw89_fw_info fw; 5150 struct rtw89_hci_info hci; 5151 struct rtw89_efuse efuse; 5152 struct rtw89_traffic_stats stats; 5153 struct rtw89_rfe_data *rfe_data; 5154 5155 /* ensures exclusive access from mac80211 callbacks */ 5156 struct mutex mutex; 5157 struct list_head rtwvifs_list; 5158 /* used to protect rf read write */ 5159 struct mutex rf_mutex; 5160 struct workqueue_struct *txq_wq; 5161 struct work_struct txq_work; 5162 struct delayed_work txq_reinvoke_work; 5163 /* used to protect ba_list and forbid_ba_list */ 5164 spinlock_t ba_lock; 5165 /* txqs to setup ba session */ 5166 struct list_head ba_list; 5167 /* txqs to forbid ba session */ 5168 struct list_head forbid_ba_list; 5169 struct work_struct ba_work; 5170 /* used to protect rpwm */ 5171 spinlock_t rpwm_lock; 5172 5173 struct rtw89_cam_info cam_info; 5174 5175 struct sk_buff_head c2h_queue; 5176 struct work_struct c2h_work; 5177 struct work_struct ips_work; 5178 struct work_struct load_firmware_work; 5179 struct work_struct cancel_6ghz_probe_work; 5180 5181 struct list_head early_h2c_list; 5182 5183 struct rtw89_ser ser; 5184 5185 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5186 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5187 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5188 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5189 5190 struct rtw89_phy_stat phystat; 5191 struct rtw89_rfk_wait_info rfk_wait; 5192 struct rtw89_dack_info dack; 5193 struct rtw89_iqk_info iqk; 5194 struct rtw89_dpk_info dpk; 5195 struct rtw89_rfk_mcc_info rfk_mcc; 5196 struct rtw89_lck_info lck; 5197 struct rtw89_rx_dck_info rx_dck; 5198 bool is_tssi_mode[RF_PATH_MAX]; 5199 bool is_bt_iqk_timeout; 5200 5201 struct rtw89_fem_info fem; 5202 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5203 struct rtw89_tssi_info tssi; 5204 struct rtw89_power_trim_info pwr_trim; 5205 5206 struct rtw89_cfo_tracking_info cfo_tracking; 5207 struct rtw89_env_monitor_info env_monitor; 5208 struct rtw89_dig_info dig; 5209 struct rtw89_phy_ch_info ch_info; 5210 union { 5211 struct rtw89_phy_bb_gain_info ax; 5212 struct rtw89_phy_bb_gain_info_be be; 5213 } bb_gain; 5214 struct rtw89_phy_efuse_gain efuse_gain; 5215 struct rtw89_phy_ul_tb_info ul_tb_info; 5216 struct rtw89_antdiv_info antdiv; 5217 5218 struct delayed_work track_work; 5219 struct delayed_work chanctx_work; 5220 struct delayed_work coex_act1_work; 5221 struct delayed_work coex_bt_devinfo_work; 5222 struct delayed_work coex_rfk_chk_work; 5223 struct delayed_work cfo_track_work; 5224 struct delayed_work forbid_ba_work; 5225 struct delayed_work roc_work; 5226 struct delayed_work antdiv_work; 5227 struct rtw89_ppdu_sts_info ppdu_sts; 5228 u8 total_sta_assoc; 5229 bool scanning; 5230 5231 struct rtw89_regulatory_info regulatory; 5232 struct rtw89_sar_info sar; 5233 struct rtw89_tas_info tas; 5234 5235 struct rtw89_btc btc; 5236 enum rtw89_ps_mode ps_mode; 5237 bool lps_enabled; 5238 5239 struct rtw89_wow_param wow; 5240 5241 /* napi structure */ 5242 struct net_device netdev; 5243 struct napi_struct napi; 5244 int napi_budget_countdown; 5245 5246 /* HCI related data, keep last */ 5247 u8 priv[] __aligned(sizeof(void *)); 5248 }; 5249 5250 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5251 struct rtw89_core_tx_request *tx_req) 5252 { 5253 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5254 } 5255 5256 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5257 { 5258 rtwdev->hci.ops->reset(rtwdev); 5259 } 5260 5261 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5262 { 5263 return rtwdev->hci.ops->start(rtwdev); 5264 } 5265 5266 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5267 { 5268 rtwdev->hci.ops->stop(rtwdev); 5269 } 5270 5271 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5272 { 5273 return rtwdev->hci.ops->deinit(rtwdev); 5274 } 5275 5276 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5277 { 5278 rtwdev->hci.ops->pause(rtwdev, pause); 5279 } 5280 5281 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5282 { 5283 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5284 } 5285 5286 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5287 { 5288 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5289 } 5290 5291 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5292 { 5293 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5294 } 5295 5296 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5297 { 5298 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5299 } 5300 5301 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5302 { 5303 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5304 } 5305 5306 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5307 bool drop) 5308 { 5309 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5310 return; 5311 5312 if (rtwdev->hci.ops->flush_queues) 5313 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5314 } 5315 5316 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5317 { 5318 if (rtwdev->hci.ops->recovery_start) 5319 rtwdev->hci.ops->recovery_start(rtwdev); 5320 } 5321 5322 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5323 { 5324 if (rtwdev->hci.ops->recovery_complete) 5325 rtwdev->hci.ops->recovery_complete(rtwdev); 5326 } 5327 5328 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5329 { 5330 if (rtwdev->hci.ops->enable_intr) 5331 rtwdev->hci.ops->enable_intr(rtwdev); 5332 } 5333 5334 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5335 { 5336 if (rtwdev->hci.ops->disable_intr) 5337 rtwdev->hci.ops->disable_intr(rtwdev); 5338 } 5339 5340 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5341 { 5342 if (rtwdev->hci.ops->ctrl_txdma_ch) 5343 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5344 } 5345 5346 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5347 { 5348 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5349 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5350 } 5351 5352 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5353 { 5354 if (rtwdev->hci.ops->ctrl_trxhci) 5355 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5356 } 5357 5358 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5359 { 5360 int ret = 0; 5361 5362 if (rtwdev->hci.ops->poll_txdma_ch_idle) 5363 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 5364 return ret; 5365 } 5366 5367 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5368 { 5369 if (rtwdev->hci.ops->clr_idx_all) 5370 rtwdev->hci.ops->clr_idx_all(rtwdev); 5371 } 5372 5373 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 5374 { 5375 int ret = 0; 5376 5377 if (rtwdev->hci.ops->rst_bdram) 5378 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 5379 return ret; 5380 } 5381 5382 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 5383 { 5384 if (rtwdev->hci.ops->clear) 5385 rtwdev->hci.ops->clear(rtwdev, pdev); 5386 } 5387 5388 static inline 5389 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5390 { 5391 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5392 5393 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5394 } 5395 5396 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5397 { 5398 return rtwdev->hci.ops->read8(rtwdev, addr); 5399 } 5400 5401 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5402 { 5403 return rtwdev->hci.ops->read16(rtwdev, addr); 5404 } 5405 5406 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5407 { 5408 return rtwdev->hci.ops->read32(rtwdev, addr); 5409 } 5410 5411 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5412 { 5413 rtwdev->hci.ops->write8(rtwdev, addr, data); 5414 } 5415 5416 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5417 { 5418 rtwdev->hci.ops->write16(rtwdev, addr, data); 5419 } 5420 5421 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5422 { 5423 rtwdev->hci.ops->write32(rtwdev, addr, data); 5424 } 5425 5426 static inline void 5427 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5428 { 5429 u8 val; 5430 5431 val = rtw89_read8(rtwdev, addr); 5432 rtw89_write8(rtwdev, addr, val | bit); 5433 } 5434 5435 static inline void 5436 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5437 { 5438 u16 val; 5439 5440 val = rtw89_read16(rtwdev, addr); 5441 rtw89_write16(rtwdev, addr, val | bit); 5442 } 5443 5444 static inline void 5445 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5446 { 5447 u32 val; 5448 5449 val = rtw89_read32(rtwdev, addr); 5450 rtw89_write32(rtwdev, addr, val | bit); 5451 } 5452 5453 static inline void 5454 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5455 { 5456 u8 val; 5457 5458 val = rtw89_read8(rtwdev, addr); 5459 rtw89_write8(rtwdev, addr, val & ~bit); 5460 } 5461 5462 static inline void 5463 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5464 { 5465 u16 val; 5466 5467 val = rtw89_read16(rtwdev, addr); 5468 rtw89_write16(rtwdev, addr, val & ~bit); 5469 } 5470 5471 static inline void 5472 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5473 { 5474 u32 val; 5475 5476 val = rtw89_read32(rtwdev, addr); 5477 rtw89_write32(rtwdev, addr, val & ~bit); 5478 } 5479 5480 static inline u32 5481 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5482 { 5483 u32 shift = __ffs(mask); 5484 u32 orig; 5485 u32 ret; 5486 5487 orig = rtw89_read32(rtwdev, addr); 5488 ret = (orig & mask) >> shift; 5489 5490 return ret; 5491 } 5492 5493 static inline u16 5494 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5495 { 5496 u32 shift = __ffs(mask); 5497 u32 orig; 5498 u32 ret; 5499 5500 orig = rtw89_read16(rtwdev, addr); 5501 ret = (orig & mask) >> shift; 5502 5503 return ret; 5504 } 5505 5506 static inline u8 5507 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5508 { 5509 u32 shift = __ffs(mask); 5510 u32 orig; 5511 u32 ret; 5512 5513 orig = rtw89_read8(rtwdev, addr); 5514 ret = (orig & mask) >> shift; 5515 5516 return ret; 5517 } 5518 5519 static inline void 5520 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5521 { 5522 u32 shift = __ffs(mask); 5523 u32 orig; 5524 u32 set; 5525 5526 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5527 5528 orig = rtw89_read32(rtwdev, addr); 5529 set = (orig & ~mask) | ((data << shift) & mask); 5530 rtw89_write32(rtwdev, addr, set); 5531 } 5532 5533 static inline void 5534 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5535 { 5536 u32 shift; 5537 u16 orig, set; 5538 5539 mask &= 0xffff; 5540 shift = __ffs(mask); 5541 5542 orig = rtw89_read16(rtwdev, addr); 5543 set = (orig & ~mask) | ((data << shift) & mask); 5544 rtw89_write16(rtwdev, addr, set); 5545 } 5546 5547 static inline void 5548 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5549 { 5550 u32 shift; 5551 u8 orig, set; 5552 5553 mask &= 0xff; 5554 shift = __ffs(mask); 5555 5556 orig = rtw89_read8(rtwdev, addr); 5557 set = (orig & ~mask) | ((data << shift) & mask); 5558 rtw89_write8(rtwdev, addr, set); 5559 } 5560 5561 static inline u32 5562 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5563 u32 addr, u32 mask) 5564 { 5565 u32 val; 5566 5567 mutex_lock(&rtwdev->rf_mutex); 5568 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5569 mutex_unlock(&rtwdev->rf_mutex); 5570 5571 return val; 5572 } 5573 5574 static inline void 5575 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5576 u32 addr, u32 mask, u32 data) 5577 { 5578 mutex_lock(&rtwdev->rf_mutex); 5579 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5580 mutex_unlock(&rtwdev->rf_mutex); 5581 } 5582 5583 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5584 { 5585 void *p = rtwtxq; 5586 5587 return container_of(p, struct ieee80211_txq, drv_priv); 5588 } 5589 5590 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5591 struct ieee80211_txq *txq) 5592 { 5593 struct rtw89_txq *rtwtxq; 5594 5595 if (!txq) 5596 return; 5597 5598 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5599 INIT_LIST_HEAD(&rtwtxq->list); 5600 } 5601 5602 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5603 { 5604 void *p = rtwvif; 5605 5606 return container_of(p, struct ieee80211_vif, drv_priv); 5607 } 5608 5609 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5610 { 5611 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5612 } 5613 5614 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5615 { 5616 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5617 } 5618 5619 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5620 { 5621 void *p = rtwsta; 5622 5623 return container_of(p, struct ieee80211_sta, drv_priv); 5624 } 5625 5626 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5627 { 5628 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5629 } 5630 5631 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5632 { 5633 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5634 } 5635 5636 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5637 { 5638 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5639 return RATE_INFO_BW_160; 5640 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5641 return RATE_INFO_BW_80; 5642 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5643 return RATE_INFO_BW_40; 5644 else 5645 return RATE_INFO_BW_20; 5646 } 5647 5648 static inline 5649 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5650 { 5651 switch (hw_band) { 5652 default: 5653 case RTW89_BAND_2G: 5654 return NL80211_BAND_2GHZ; 5655 case RTW89_BAND_5G: 5656 return NL80211_BAND_5GHZ; 5657 case RTW89_BAND_6G: 5658 return NL80211_BAND_6GHZ; 5659 } 5660 } 5661 5662 static inline 5663 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5664 { 5665 switch (nl_band) { 5666 default: 5667 case NL80211_BAND_2GHZ: 5668 return RTW89_BAND_2G; 5669 case NL80211_BAND_5GHZ: 5670 return RTW89_BAND_5G; 5671 case NL80211_BAND_6GHZ: 5672 return RTW89_BAND_6G; 5673 } 5674 } 5675 5676 static inline 5677 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5678 { 5679 switch (width) { 5680 default: 5681 WARN(1, "Not support bandwidth %d\n", width); 5682 fallthrough; 5683 case NL80211_CHAN_WIDTH_20_NOHT: 5684 case NL80211_CHAN_WIDTH_20: 5685 return RTW89_CHANNEL_WIDTH_20; 5686 case NL80211_CHAN_WIDTH_40: 5687 return RTW89_CHANNEL_WIDTH_40; 5688 case NL80211_CHAN_WIDTH_80: 5689 return RTW89_CHANNEL_WIDTH_80; 5690 case NL80211_CHAN_WIDTH_160: 5691 return RTW89_CHANNEL_WIDTH_160; 5692 } 5693 } 5694 5695 static inline 5696 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5697 { 5698 switch (rua) { 5699 default: 5700 WARN(1, "Invalid RU allocation: %d\n", rua); 5701 fallthrough; 5702 case 0 ... 36: 5703 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5704 case 37 ... 52: 5705 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5706 case 53 ... 60: 5707 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5708 case 61 ... 64: 5709 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5710 case 65 ... 66: 5711 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5712 case 67: 5713 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5714 case 68: 5715 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5716 } 5717 } 5718 5719 static inline 5720 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5721 struct rtw89_sta *rtwsta) 5722 { 5723 if (rtwsta) { 5724 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5725 5726 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5727 return &rtwsta->addr_cam; 5728 } 5729 return &rtwvif->addr_cam; 5730 } 5731 5732 static inline 5733 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5734 struct rtw89_sta *rtwsta) 5735 { 5736 if (rtwsta) { 5737 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5738 5739 if (sta->tdls) 5740 return &rtwsta->bssid_cam; 5741 } 5742 return &rtwvif->bssid_cam; 5743 } 5744 5745 static inline 5746 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5747 struct rtw89_channel_help_params *p, 5748 const struct rtw89_chan *chan, 5749 enum rtw89_mac_idx mac_idx, 5750 enum rtw89_phy_idx phy_idx) 5751 { 5752 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5753 mac_idx, phy_idx); 5754 } 5755 5756 static inline 5757 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 5758 struct rtw89_channel_help_params *p, 5759 const struct rtw89_chan *chan, 5760 enum rtw89_mac_idx mac_idx, 5761 enum rtw89_phy_idx phy_idx) 5762 { 5763 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 5764 mac_idx, phy_idx); 5765 } 5766 5767 static inline 5768 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 5769 enum rtw89_sub_entity_idx idx) 5770 { 5771 struct rtw89_hal *hal = &rtwdev->hal; 5772 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 5773 5774 if (roc_idx == idx) 5775 return &hal->roc_chandef; 5776 5777 return &hal->sub[idx].chandef; 5778 } 5779 5780 static inline 5781 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 5782 enum rtw89_sub_entity_idx idx) 5783 { 5784 struct rtw89_hal *hal = &rtwdev->hal; 5785 5786 return &hal->sub[idx].chan; 5787 } 5788 5789 static inline 5790 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 5791 enum rtw89_sub_entity_idx idx) 5792 { 5793 struct rtw89_hal *hal = &rtwdev->hal; 5794 5795 return &hal->sub[idx].rcd; 5796 } 5797 5798 static inline 5799 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 5800 { 5801 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 5802 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 5803 5804 if (rtwvif) 5805 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 5806 else 5807 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5808 } 5809 5810 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 5811 { 5812 const struct rtw89_chip_info *chip = rtwdev->chip; 5813 5814 if (chip->ops->fem_setup) 5815 chip->ops->fem_setup(rtwdev); 5816 } 5817 5818 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 5819 { 5820 const struct rtw89_chip_info *chip = rtwdev->chip; 5821 5822 if (chip->ops->rfe_gpio) 5823 chip->ops->rfe_gpio(rtwdev); 5824 } 5825 5826 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 5827 { 5828 const struct rtw89_chip_info *chip = rtwdev->chip; 5829 5830 if (chip->ops->rfk_hw_init) 5831 chip->ops->rfk_hw_init(rtwdev); 5832 } 5833 5834 static inline 5835 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5836 { 5837 const struct rtw89_chip_info *chip = rtwdev->chip; 5838 5839 if (chip->ops->bb_preinit) 5840 chip->ops->bb_preinit(rtwdev, phy_idx); 5841 } 5842 5843 static inline 5844 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 5845 { 5846 const struct rtw89_chip_info *chip = rtwdev->chip; 5847 5848 if (!chip->ops->bb_postinit) 5849 return; 5850 5851 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 5852 5853 if (rtwdev->dbcc_en) 5854 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 5855 } 5856 5857 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 5858 { 5859 const struct rtw89_chip_info *chip = rtwdev->chip; 5860 5861 if (chip->ops->bb_sethw) 5862 chip->ops->bb_sethw(rtwdev); 5863 } 5864 5865 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 5866 { 5867 const struct rtw89_chip_info *chip = rtwdev->chip; 5868 5869 if (chip->ops->rfk_init) 5870 chip->ops->rfk_init(rtwdev); 5871 } 5872 5873 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 5874 { 5875 const struct rtw89_chip_info *chip = rtwdev->chip; 5876 5877 if (chip->ops->rfk_init_late) 5878 chip->ops->rfk_init_late(rtwdev); 5879 } 5880 5881 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 5882 { 5883 const struct rtw89_chip_info *chip = rtwdev->chip; 5884 5885 if (chip->ops->rfk_channel) 5886 chip->ops->rfk_channel(rtwdev); 5887 } 5888 5889 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 5890 enum rtw89_phy_idx phy_idx) 5891 { 5892 const struct rtw89_chip_info *chip = rtwdev->chip; 5893 5894 if (chip->ops->rfk_band_changed) 5895 chip->ops->rfk_band_changed(rtwdev, phy_idx); 5896 } 5897 5898 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 5899 { 5900 const struct rtw89_chip_info *chip = rtwdev->chip; 5901 5902 if (chip->ops->rfk_scan) 5903 chip->ops->rfk_scan(rtwdev, start); 5904 } 5905 5906 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 5907 { 5908 const struct rtw89_chip_info *chip = rtwdev->chip; 5909 5910 if (chip->ops->rfk_track) 5911 chip->ops->rfk_track(rtwdev); 5912 } 5913 5914 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 5915 { 5916 const struct rtw89_chip_info *chip = rtwdev->chip; 5917 5918 if (chip->ops->set_txpwr_ctrl) 5919 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 5920 } 5921 5922 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 5923 { 5924 const struct rtw89_chip_info *chip = rtwdev->chip; 5925 5926 if (chip->ops->power_trim) 5927 chip->ops->power_trim(rtwdev); 5928 } 5929 5930 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 5931 enum rtw89_phy_idx phy_idx) 5932 { 5933 const struct rtw89_chip_info *chip = rtwdev->chip; 5934 5935 if (chip->ops->init_txpwr_unit) 5936 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 5937 } 5938 5939 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 5940 enum rtw89_rf_path rf_path) 5941 { 5942 const struct rtw89_chip_info *chip = rtwdev->chip; 5943 5944 if (!chip->ops->get_thermal) 5945 return 0x10; 5946 5947 return chip->ops->get_thermal(rtwdev, rf_path); 5948 } 5949 5950 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 5951 struct rtw89_rx_phy_ppdu *phy_ppdu, 5952 struct ieee80211_rx_status *status) 5953 { 5954 const struct rtw89_chip_info *chip = rtwdev->chip; 5955 5956 if (chip->ops->query_ppdu) 5957 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 5958 } 5959 5960 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 5961 enum rtw89_phy_idx phy_idx) 5962 { 5963 const struct rtw89_chip_info *chip = rtwdev->chip; 5964 5965 if (chip->ops->ctrl_nbtg_bt_tx) 5966 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 5967 } 5968 5969 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 5970 { 5971 const struct rtw89_chip_info *chip = rtwdev->chip; 5972 5973 if (chip->ops->cfg_txrx_path) 5974 chip->ops->cfg_txrx_path(rtwdev); 5975 } 5976 5977 static inline 5978 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5979 struct ieee80211_vif *vif) 5980 { 5981 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5982 const struct rtw89_chip_info *chip = rtwdev->chip; 5983 5984 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5985 return; 5986 5987 if (chip->ops->set_txpwr_ul_tb_offset) 5988 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5989 } 5990 5991 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 5992 const struct rtw89_txpwr_table *tbl) 5993 { 5994 tbl->load(rtwdev, tbl); 5995 } 5996 5997 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 5998 { 5999 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6000 6001 return regd->txpwr_regd[band]; 6002 } 6003 6004 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6005 enum rtw89_phy_idx phy_idx) 6006 { 6007 const struct rtw89_chip_info *chip = rtwdev->chip; 6008 6009 if (chip->ops->ctrl_btg_bt_rx) 6010 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6011 } 6012 6013 static inline 6014 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6015 struct rtw89_rx_desc_info *desc_info, 6016 u8 *data, u32 data_offset) 6017 { 6018 const struct rtw89_chip_info *chip = rtwdev->chip; 6019 6020 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6021 } 6022 6023 static inline 6024 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6025 struct rtw89_tx_desc_info *desc_info, 6026 void *txdesc) 6027 { 6028 const struct rtw89_chip_info *chip = rtwdev->chip; 6029 6030 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6031 } 6032 6033 static inline 6034 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6035 struct rtw89_tx_desc_info *desc_info, 6036 void *txdesc) 6037 { 6038 const struct rtw89_chip_info *chip = rtwdev->chip; 6039 6040 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6041 } 6042 6043 static inline 6044 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6045 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6046 { 6047 const struct rtw89_chip_info *chip = rtwdev->chip; 6048 6049 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6050 } 6051 6052 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6053 { 6054 const struct rtw89_chip_info *chip = rtwdev->chip; 6055 6056 chip->ops->cfg_ctrl_path(rtwdev, wl); 6057 } 6058 6059 static inline 6060 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6061 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6062 { 6063 const struct rtw89_chip_info *chip = rtwdev->chip; 6064 6065 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6066 } 6067 6068 static inline 6069 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6070 { 6071 const struct rtw89_chip_info *chip = rtwdev->chip; 6072 6073 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6074 } 6075 6076 static inline 6077 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6078 struct rtw89_vif *rtwvif, 6079 struct rtw89_sta *rtwsta) 6080 { 6081 const struct rtw89_chip_info *chip = rtwdev->chip; 6082 6083 if (!chip->ops->h2c_dctl_sec_cam) 6084 return 0; 6085 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 6086 } 6087 6088 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6089 { 6090 __le16 fc = hdr->frame_control; 6091 6092 if (ieee80211_has_tods(fc)) 6093 return hdr->addr1; 6094 else if (ieee80211_has_fromds(fc)) 6095 return hdr->addr2; 6096 else 6097 return hdr->addr3; 6098 } 6099 6100 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 6101 { 6102 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6103 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6104 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 6105 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6106 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 6107 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6108 return true; 6109 return false; 6110 } 6111 6112 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6113 enum rtw89_fw_type type) 6114 { 6115 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6116 6117 switch (type) { 6118 case RTW89_FW_WOWLAN: 6119 return &fw_info->wowlan; 6120 case RTW89_FW_LOGFMT: 6121 return &fw_info->log.suit; 6122 case RTW89_FW_BBMCU0: 6123 return &fw_info->bbmcu0; 6124 case RTW89_FW_BBMCU1: 6125 return &fw_info->bbmcu1; 6126 default: 6127 break; 6128 } 6129 6130 return &fw_info->normal; 6131 } 6132 6133 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6134 unsigned int length) 6135 { 6136 struct sk_buff *skb; 6137 6138 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6139 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6140 if (!skb) 6141 return NULL; 6142 6143 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6144 return skb; 6145 } 6146 6147 return dev_alloc_skb(length); 6148 } 6149 6150 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6151 struct rtw89_tx_skb_data *skb_data, 6152 bool tx_done) 6153 { 6154 struct rtw89_tx_wait_info *wait; 6155 6156 rcu_read_lock(); 6157 6158 wait = rcu_dereference(skb_data->wait); 6159 if (!wait) 6160 goto out; 6161 6162 wait->tx_done = tx_done; 6163 complete(&wait->completion); 6164 6165 out: 6166 rcu_read_unlock(); 6167 } 6168 6169 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6170 { 6171 switch (rtwdev->mlo_dbcc_mode) { 6172 case MLO_1_PLUS_1_1RF: 6173 case MLO_1_PLUS_1_2RF: 6174 case DBCC_LEGACY: 6175 return true; 6176 default: 6177 return false; 6178 } 6179 } 6180 6181 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6182 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6183 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6184 struct sk_buff *skb, bool fwdl); 6185 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6186 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6187 int qsel, unsigned int timeout); 6188 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6189 struct rtw89_tx_desc_info *desc_info, 6190 void *txdesc); 6191 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6192 struct rtw89_tx_desc_info *desc_info, 6193 void *txdesc); 6194 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6195 struct rtw89_tx_desc_info *desc_info, 6196 void *txdesc); 6197 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6198 struct rtw89_tx_desc_info *desc_info, 6199 void *txdesc); 6200 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6201 struct rtw89_tx_desc_info *desc_info, 6202 void *txdesc); 6203 void rtw89_core_rx(struct rtw89_dev *rtwdev, 6204 struct rtw89_rx_desc_info *desc_info, 6205 struct sk_buff *skb); 6206 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 6207 struct rtw89_rx_desc_info *desc_info, 6208 u8 *data, u32 data_offset); 6209 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 6210 struct rtw89_rx_desc_info *desc_info, 6211 u8 *data, u32 data_offset); 6212 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 6213 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 6214 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 6215 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 6216 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 6217 struct ieee80211_vif *vif, 6218 struct ieee80211_sta *sta); 6219 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 6220 struct ieee80211_vif *vif, 6221 struct ieee80211_sta *sta); 6222 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 6223 struct ieee80211_vif *vif, 6224 struct ieee80211_sta *sta); 6225 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 6226 struct ieee80211_vif *vif, 6227 struct ieee80211_sta *sta); 6228 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 6229 struct ieee80211_vif *vif, 6230 struct ieee80211_sta *sta); 6231 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6232 struct ieee80211_sta *sta, 6233 struct cfg80211_tid_config *tid_config); 6234 int rtw89_core_init(struct rtw89_dev *rtwdev); 6235 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 6236 int rtw89_core_register(struct rtw89_dev *rtwdev); 6237 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 6238 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6239 u32 bus_data_size, 6240 const struct rtw89_chip_info *chip); 6241 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 6242 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 6243 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 6244 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 6245 struct rtw89_chan *chan); 6246 int rtw89_set_channel(struct rtw89_dev *rtwdev); 6247 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6248 struct rtw89_chan *chan); 6249 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 6250 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 6251 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 6252 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 6253 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6254 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 6255 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6256 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 6257 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 6258 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 6259 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 6260 int rtw89_regd_init(struct rtw89_dev *rtwdev, 6261 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 6262 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 6263 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 6264 struct rtw89_traffic_stats *stats); 6265 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 6266 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6267 const struct rtw89_completion_data *data); 6268 int rtw89_core_start(struct rtw89_dev *rtwdev); 6269 void rtw89_core_stop(struct rtw89_dev *rtwdev); 6270 void rtw89_core_update_beacon_work(struct work_struct *work); 6271 void rtw89_roc_work(struct work_struct *work); 6272 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6273 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6274 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6275 const u8 *mac_addr, bool hw_scan); 6276 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6277 struct ieee80211_vif *vif, bool hw_scan); 6278 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 6279 struct rtw89_vif *rtwvif, bool active); 6280 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 6281 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 6282 6283 #endif 6284