1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_efuse_block_cfg; 21 struct rtw89_h2c_rf_tssi; 22 struct rtw89_fw_txpwr_track_cfg; 23 struct rtw89_phy_rfk_log_fmt; 24 struct rtw89_debugfs; 25 26 extern const struct ieee80211_ops rtw89_ops; 27 28 #define MASKBYTE0 0xff 29 #define MASKBYTE1 0xff00 30 #define MASKBYTE2 0xff0000 31 #define MASKBYTE3 0xff000000 32 #define MASKBYTE4 0xff00000000ULL 33 #define MASKHWORD 0xffff0000 34 #define MASKLWORD 0x0000ffff 35 #define MASKDWORD 0xffffffff 36 #define RFREG_MASK 0xfffff 37 #define INV_RF_DATA 0xffffffff 38 #define BYPASS_CR_DATA 0xbabecafe 39 40 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 41 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 42 #define CFO_TRACK_MAX_USER 64 43 #define MAX_RSSI 110 44 #define RSSI_FACTOR 1 45 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 46 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 47 #define DELTA_SWINGIDX_SIZE 30 48 49 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 50 #define RTW89_RADIOTAP_ROOM_EHT \ 51 (sizeof(struct ieee80211_radiotap_tlv) + \ 52 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 53 sizeof(struct ieee80211_radiotap_tlv) + \ 54 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 55 #define RTW89_RADIOTAP_ROOM \ 56 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 57 58 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 59 #define RTW89_HTC_VARIANT_HE 3 60 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 61 #define RTW89_HTC_VARIANT_HE_CID_OM 1 62 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 63 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 64 65 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 66 enum htc_om_channel_width { 67 HTC_OM_CHANNEL_WIDTH_20 = 0, 68 HTC_OM_CHANNEL_WIDTH_40 = 1, 69 HTC_OM_CHANNEL_WIDTH_80 = 2, 70 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 71 }; 72 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 73 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 74 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 75 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 76 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 77 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 78 79 #define RTW89_TF_PAD GENMASK(11, 0) 80 #define RTW89_TF_BASIC_USER_INFO_SZ 6 81 82 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 83 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 84 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 86 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 87 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 88 89 enum rtw89_subband { 90 RTW89_CH_2G = 0, 91 RTW89_CH_5G_BAND_1 = 1, 92 /* RTW89_CH_5G_BAND_2 = 2, unused */ 93 RTW89_CH_5G_BAND_3 = 3, 94 RTW89_CH_5G_BAND_4 = 4, 95 96 RTW89_CH_6G_BAND_IDX0, /* Low */ 97 RTW89_CH_6G_BAND_IDX1, /* Low */ 98 RTW89_CH_6G_BAND_IDX2, /* Mid */ 99 RTW89_CH_6G_BAND_IDX3, /* Mid */ 100 RTW89_CH_6G_BAND_IDX4, /* High */ 101 RTW89_CH_6G_BAND_IDX5, /* High */ 102 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 103 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 104 105 RTW89_SUBBAND_NR, 106 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 107 }; 108 109 enum rtw89_gain_offset { 110 RTW89_GAIN_OFFSET_2G_CCK, 111 RTW89_GAIN_OFFSET_2G_OFDM, 112 RTW89_GAIN_OFFSET_5G_LOW, 113 RTW89_GAIN_OFFSET_5G_MID, 114 RTW89_GAIN_OFFSET_5G_HIGH, 115 RTW89_GAIN_OFFSET_6G_L0, 116 RTW89_GAIN_OFFSET_6G_L1, 117 RTW89_GAIN_OFFSET_6G_M0, 118 RTW89_GAIN_OFFSET_6G_M1, 119 RTW89_GAIN_OFFSET_6G_H0, 120 RTW89_GAIN_OFFSET_6G_H1, 121 RTW89_GAIN_OFFSET_6G_UH0, 122 RTW89_GAIN_OFFSET_6G_UH1, 123 124 RTW89_GAIN_OFFSET_NR, 125 }; 126 127 enum rtw89_hci_type { 128 RTW89_HCI_TYPE_PCIE, 129 RTW89_HCI_TYPE_USB, 130 RTW89_HCI_TYPE_SDIO, 131 }; 132 133 enum rtw89_core_chip_id { 134 RTL8852A, 135 RTL8852B, 136 RTL8852BT, 137 RTL8852C, 138 RTL8851B, 139 RTL8922A, 140 }; 141 142 enum rtw89_chip_gen { 143 RTW89_CHIP_AX, 144 RTW89_CHIP_BE, 145 146 RTW89_CHIP_GEN_NUM, 147 }; 148 149 enum rtw89_cv { 150 CHIP_CAV, 151 CHIP_CBV, 152 CHIP_CCV, 153 CHIP_CDV, 154 CHIP_CEV, 155 CHIP_CFV, 156 CHIP_CV_MAX, 157 CHIP_CV_INVALID = CHIP_CV_MAX, 158 }; 159 160 enum rtw89_bacam_ver { 161 RTW89_BACAM_V0, 162 RTW89_BACAM_V1, 163 164 RTW89_BACAM_V0_EXT = 99, 165 }; 166 167 enum rtw89_core_tx_type { 168 RTW89_CORE_TX_TYPE_DATA, 169 RTW89_CORE_TX_TYPE_MGMT, 170 RTW89_CORE_TX_TYPE_FWCMD, 171 }; 172 173 enum rtw89_core_rx_type { 174 RTW89_CORE_RX_TYPE_WIFI = 0, 175 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 176 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 177 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 178 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 179 RTW89_CORE_RX_TYPE_SS2FW = 5, 180 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 181 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 182 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 183 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 184 RTW89_CORE_RX_TYPE_C2H = 10, 185 RTW89_CORE_RX_TYPE_CSI = 11, 186 RTW89_CORE_RX_TYPE_CQI = 12, 187 RTW89_CORE_RX_TYPE_H2C = 13, 188 RTW89_CORE_RX_TYPE_FWDL = 14, 189 }; 190 191 enum rtw89_txq_flags { 192 RTW89_TXQ_F_AMPDU = 0, 193 RTW89_TXQ_F_BLOCK_BA = 1, 194 RTW89_TXQ_F_FORBID_BA = 2, 195 }; 196 197 enum rtw89_net_type { 198 RTW89_NET_TYPE_NO_LINK = 0, 199 RTW89_NET_TYPE_AD_HOC = 1, 200 RTW89_NET_TYPE_INFRA = 2, 201 RTW89_NET_TYPE_AP_MODE = 3, 202 }; 203 204 enum rtw89_wifi_role { 205 RTW89_WIFI_ROLE_NONE, 206 RTW89_WIFI_ROLE_STATION, 207 RTW89_WIFI_ROLE_AP, 208 RTW89_WIFI_ROLE_AP_VLAN, 209 RTW89_WIFI_ROLE_ADHOC, 210 RTW89_WIFI_ROLE_ADHOC_MASTER, 211 RTW89_WIFI_ROLE_MESH_POINT, 212 RTW89_WIFI_ROLE_MONITOR, 213 RTW89_WIFI_ROLE_P2P_DEVICE, 214 RTW89_WIFI_ROLE_P2P_CLIENT, 215 RTW89_WIFI_ROLE_P2P_GO, 216 RTW89_WIFI_ROLE_NAN, 217 RTW89_WIFI_ROLE_MLME_MAX 218 }; 219 220 enum rtw89_upd_mode { 221 RTW89_ROLE_CREATE, 222 RTW89_ROLE_REMOVE, 223 RTW89_ROLE_TYPE_CHANGE, 224 RTW89_ROLE_INFO_CHANGE, 225 RTW89_ROLE_CON_DISCONN, 226 RTW89_ROLE_BAND_SW, 227 RTW89_ROLE_FW_RESTORE, 228 }; 229 230 enum rtw89_self_role { 231 RTW89_SELF_ROLE_CLIENT, 232 RTW89_SELF_ROLE_AP, 233 RTW89_SELF_ROLE_AP_CLIENT 234 }; 235 236 enum rtw89_msk_sO_el { 237 RTW89_NO_MSK, 238 RTW89_SMA, 239 RTW89_TMA, 240 RTW89_BSSID 241 }; 242 243 enum rtw89_sch_tx_sel { 244 RTW89_SCH_TX_SEL_ALL, 245 RTW89_SCH_TX_SEL_HIQ, 246 RTW89_SCH_TX_SEL_MG0, 247 RTW89_SCH_TX_SEL_MACID, 248 }; 249 250 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 251 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 252 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 253 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 254 */ 255 enum rtw89_add_cam_sec_mode { 256 RTW89_ADDR_CAM_SEC_NONE = 0, 257 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 258 RTW89_ADDR_CAM_SEC_NORMAL = 2, 259 RTW89_ADDR_CAM_SEC_4GROUP = 3, 260 }; 261 262 enum rtw89_sec_key_type { 263 RTW89_SEC_KEY_TYPE_NONE = 0, 264 RTW89_SEC_KEY_TYPE_WEP40 = 1, 265 RTW89_SEC_KEY_TYPE_WEP104 = 2, 266 RTW89_SEC_KEY_TYPE_TKIP = 3, 267 RTW89_SEC_KEY_TYPE_WAPI = 4, 268 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 269 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 270 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 271 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 272 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 273 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 274 }; 275 276 enum rtw89_port { 277 RTW89_PORT_0 = 0, 278 RTW89_PORT_1 = 1, 279 RTW89_PORT_2 = 2, 280 RTW89_PORT_3 = 3, 281 RTW89_PORT_4 = 4, 282 RTW89_PORT_NUM 283 }; 284 285 enum rtw89_band { 286 RTW89_BAND_2G = 0, 287 RTW89_BAND_5G = 1, 288 RTW89_BAND_6G = 2, 289 RTW89_BAND_NUM, 290 }; 291 292 enum rtw89_hw_rate { 293 RTW89_HW_RATE_CCK1 = 0x0, 294 RTW89_HW_RATE_CCK2 = 0x1, 295 RTW89_HW_RATE_CCK5_5 = 0x2, 296 RTW89_HW_RATE_CCK11 = 0x3, 297 RTW89_HW_RATE_OFDM6 = 0x4, 298 RTW89_HW_RATE_OFDM9 = 0x5, 299 RTW89_HW_RATE_OFDM12 = 0x6, 300 RTW89_HW_RATE_OFDM18 = 0x7, 301 RTW89_HW_RATE_OFDM24 = 0x8, 302 RTW89_HW_RATE_OFDM36 = 0x9, 303 RTW89_HW_RATE_OFDM48 = 0xA, 304 RTW89_HW_RATE_OFDM54 = 0xB, 305 RTW89_HW_RATE_MCS0 = 0x80, 306 RTW89_HW_RATE_MCS1 = 0x81, 307 RTW89_HW_RATE_MCS2 = 0x82, 308 RTW89_HW_RATE_MCS3 = 0x83, 309 RTW89_HW_RATE_MCS4 = 0x84, 310 RTW89_HW_RATE_MCS5 = 0x85, 311 RTW89_HW_RATE_MCS6 = 0x86, 312 RTW89_HW_RATE_MCS7 = 0x87, 313 RTW89_HW_RATE_MCS8 = 0x88, 314 RTW89_HW_RATE_MCS9 = 0x89, 315 RTW89_HW_RATE_MCS10 = 0x8A, 316 RTW89_HW_RATE_MCS11 = 0x8B, 317 RTW89_HW_RATE_MCS12 = 0x8C, 318 RTW89_HW_RATE_MCS13 = 0x8D, 319 RTW89_HW_RATE_MCS14 = 0x8E, 320 RTW89_HW_RATE_MCS15 = 0x8F, 321 RTW89_HW_RATE_MCS16 = 0x90, 322 RTW89_HW_RATE_MCS17 = 0x91, 323 RTW89_HW_RATE_MCS18 = 0x92, 324 RTW89_HW_RATE_MCS19 = 0x93, 325 RTW89_HW_RATE_MCS20 = 0x94, 326 RTW89_HW_RATE_MCS21 = 0x95, 327 RTW89_HW_RATE_MCS22 = 0x96, 328 RTW89_HW_RATE_MCS23 = 0x97, 329 RTW89_HW_RATE_MCS24 = 0x98, 330 RTW89_HW_RATE_MCS25 = 0x99, 331 RTW89_HW_RATE_MCS26 = 0x9A, 332 RTW89_HW_RATE_MCS27 = 0x9B, 333 RTW89_HW_RATE_MCS28 = 0x9C, 334 RTW89_HW_RATE_MCS29 = 0x9D, 335 RTW89_HW_RATE_MCS30 = 0x9E, 336 RTW89_HW_RATE_MCS31 = 0x9F, 337 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 338 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 339 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 340 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 341 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 342 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 343 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 344 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 345 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 346 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 347 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 348 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 349 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 350 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 351 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 352 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 353 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 354 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 355 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 356 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 357 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 358 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 359 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 360 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 361 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 362 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 363 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 364 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 365 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 366 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 367 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 368 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 369 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 370 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 371 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 372 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 373 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 374 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 375 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 376 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 377 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 378 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 379 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 380 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 381 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 382 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 383 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 384 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 385 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 386 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 387 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 388 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 389 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 390 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 391 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 392 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 393 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 394 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 395 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 396 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 397 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 398 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 399 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 400 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 401 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 402 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 403 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 404 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 405 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 406 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 407 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 408 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 409 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 410 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 411 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 412 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 413 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 414 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 415 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 416 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 417 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 418 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 419 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 420 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 421 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 422 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 423 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 424 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 425 426 RTW89_HW_RATE_V1_MCS0 = 0x100, 427 RTW89_HW_RATE_V1_MCS1 = 0x101, 428 RTW89_HW_RATE_V1_MCS2 = 0x102, 429 RTW89_HW_RATE_V1_MCS3 = 0x103, 430 RTW89_HW_RATE_V1_MCS4 = 0x104, 431 RTW89_HW_RATE_V1_MCS5 = 0x105, 432 RTW89_HW_RATE_V1_MCS6 = 0x106, 433 RTW89_HW_RATE_V1_MCS7 = 0x107, 434 RTW89_HW_RATE_V1_MCS8 = 0x108, 435 RTW89_HW_RATE_V1_MCS9 = 0x109, 436 RTW89_HW_RATE_V1_MCS10 = 0x10A, 437 RTW89_HW_RATE_V1_MCS11 = 0x10B, 438 RTW89_HW_RATE_V1_MCS12 = 0x10C, 439 RTW89_HW_RATE_V1_MCS13 = 0x10D, 440 RTW89_HW_RATE_V1_MCS14 = 0x10E, 441 RTW89_HW_RATE_V1_MCS15 = 0x10F, 442 RTW89_HW_RATE_V1_MCS16 = 0x110, 443 RTW89_HW_RATE_V1_MCS17 = 0x111, 444 RTW89_HW_RATE_V1_MCS18 = 0x112, 445 RTW89_HW_RATE_V1_MCS19 = 0x113, 446 RTW89_HW_RATE_V1_MCS20 = 0x114, 447 RTW89_HW_RATE_V1_MCS21 = 0x115, 448 RTW89_HW_RATE_V1_MCS22 = 0x116, 449 RTW89_HW_RATE_V1_MCS23 = 0x117, 450 RTW89_HW_RATE_V1_MCS24 = 0x118, 451 RTW89_HW_RATE_V1_MCS25 = 0x119, 452 RTW89_HW_RATE_V1_MCS26 = 0x11A, 453 RTW89_HW_RATE_V1_MCS27 = 0x11B, 454 RTW89_HW_RATE_V1_MCS28 = 0x11C, 455 RTW89_HW_RATE_V1_MCS29 = 0x11D, 456 RTW89_HW_RATE_V1_MCS30 = 0x11E, 457 RTW89_HW_RATE_V1_MCS31 = 0x11F, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 469 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 481 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 493 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 505 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 517 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 529 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 541 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 553 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 583 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 597 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 611 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 612 613 RTW89_HW_RATE_NR, 614 RTW89_HW_RATE_INVAL, 615 616 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 617 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 618 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 619 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 620 }; 621 622 /* 2G channels, 623 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 624 */ 625 #define RTW89_2G_CH_NUM 14 626 627 /* 5G channels, 628 * 36, 38, 40, 42, 44, 46, 48, 50, 629 * 52, 54, 56, 58, 60, 62, 64, 630 * 100, 102, 104, 106, 108, 110, 112, 114, 631 * 116, 118, 120, 122, 124, 126, 128, 130, 632 * 132, 134, 136, 138, 140, 142, 144, 633 * 149, 151, 153, 155, 157, 159, 161, 163, 634 * 165, 167, 169, 171, 173, 175, 177 635 */ 636 #define RTW89_5G_CH_NUM 53 637 638 /* 6G channels, 639 * 1, 3, 5, 7, 9, 11, 13, 15, 640 * 17, 19, 21, 23, 25, 27, 29, 33, 641 * 35, 37, 39, 41, 43, 45, 47, 49, 642 * 51, 53, 55, 57, 59, 61, 65, 67, 643 * 69, 71, 73, 75, 77, 79, 81, 83, 644 * 85, 87, 89, 91, 93, 97, 99, 101, 645 * 103, 105, 107, 109, 111, 113, 115, 117, 646 * 119, 121, 123, 125, 129, 131, 133, 135, 647 * 137, 139, 141, 143, 145, 147, 149, 151, 648 * 153, 155, 157, 161, 163, 165, 167, 169, 649 * 171, 173, 175, 177, 179, 181, 183, 185, 650 * 187, 189, 193, 195, 197, 199, 201, 203, 651 * 205, 207, 209, 211, 213, 215, 217, 219, 652 * 221, 225, 227, 229, 231, 233, 235, 237, 653 * 239, 241, 243, 245, 247, 249, 251, 253, 654 */ 655 #define RTW89_6G_CH_NUM 120 656 657 enum rtw89_rate_section { 658 RTW89_RS_CCK, 659 RTW89_RS_OFDM, 660 RTW89_RS_MCS, /* for HT/VHT/HE */ 661 RTW89_RS_HEDCM, 662 RTW89_RS_OFFSET, 663 RTW89_RS_NUM, 664 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 665 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 666 }; 667 668 enum rtw89_rate_offset_indexes { 669 RTW89_RATE_OFFSET_HE, 670 RTW89_RATE_OFFSET_VHT, 671 RTW89_RATE_OFFSET_HT, 672 RTW89_RATE_OFFSET_OFDM, 673 RTW89_RATE_OFFSET_CCK, 674 RTW89_RATE_OFFSET_DLRU_EHT, 675 RTW89_RATE_OFFSET_DLRU_HE, 676 RTW89_RATE_OFFSET_EHT, 677 __RTW89_RATE_OFFSET_NUM, 678 679 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 680 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 681 }; 682 683 enum rtw89_rate_num { 684 RTW89_RATE_CCK_NUM = 4, 685 RTW89_RATE_OFDM_NUM = 8, 686 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 687 688 RTW89_RATE_MCS_NUM_AX = 12, 689 RTW89_RATE_MCS_NUM_BE = 16, 690 __RTW89_RATE_MCS_NUM = 16, 691 }; 692 693 enum rtw89_nss { 694 RTW89_NSS_1 = 0, 695 RTW89_NSS_2 = 1, 696 /* HE DCM only support 1ss and 2ss */ 697 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 698 RTW89_NSS_3 = 2, 699 RTW89_NSS_4 = 3, 700 RTW89_NSS_NUM, 701 }; 702 703 enum rtw89_ntx { 704 RTW89_1TX = 0, 705 RTW89_2TX = 1, 706 RTW89_NTX_NUM, 707 }; 708 709 enum rtw89_beamforming_type { 710 RTW89_NONBF = 0, 711 RTW89_BF = 1, 712 RTW89_BF_NUM, 713 }; 714 715 enum rtw89_ofdma_type { 716 RTW89_NON_OFDMA = 0, 717 RTW89_OFDMA = 1, 718 RTW89_OFDMA_NUM, 719 }; 720 721 enum rtw89_regulation_type { 722 RTW89_WW = 0, 723 RTW89_ETSI = 1, 724 RTW89_FCC = 2, 725 RTW89_MKK = 3, 726 RTW89_NA = 4, 727 RTW89_IC = 5, 728 RTW89_KCC = 6, 729 RTW89_ACMA = 7, 730 RTW89_NCC = 8, 731 RTW89_MEXICO = 9, 732 RTW89_CHILE = 10, 733 RTW89_UKRAINE = 11, 734 RTW89_CN = 12, 735 RTW89_QATAR = 13, 736 RTW89_UK = 14, 737 RTW89_THAILAND = 15, 738 RTW89_REGD_NUM, 739 }; 740 741 enum rtw89_reg_6ghz_power { 742 RTW89_REG_6GHZ_POWER_VLP = 0, 743 RTW89_REG_6GHZ_POWER_LPI = 1, 744 RTW89_REG_6GHZ_POWER_STD = 2, 745 746 NUM_OF_RTW89_REG_6GHZ_POWER, 747 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 748 }; 749 750 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 751 752 /* calculate based on ieee80211 Transmit Power Envelope */ 753 struct rtw89_reg_6ghz_tpe { 754 bool valid; 755 s8 constraint; /* unit: dBm */ 756 }; 757 758 enum rtw89_fw_pkt_ofld_type { 759 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 760 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 761 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 762 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 763 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 764 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 765 RTW89_PKT_OFLD_TYPE_NDP = 6, 766 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 767 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 768 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 769 RTW89_PKT_OFLD_TYPE_NUM, 770 }; 771 772 struct rtw89_txpwr_byrate { 773 s8 cck[RTW89_RATE_CCK_NUM]; 774 s8 ofdm[RTW89_RATE_OFDM_NUM]; 775 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 776 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 777 s8 offset[__RTW89_RATE_OFFSET_NUM]; 778 s8 trap; 779 }; 780 781 struct rtw89_rate_desc { 782 enum rtw89_nss nss; 783 enum rtw89_rate_section rs; 784 enum rtw89_ofdma_type ofdma; 785 u8 idx; 786 }; 787 788 #define PHY_STS_HDR_LEN 8 789 #define RF_PATH_MAX 4 790 #define RTW89_MAX_PPDU_CNT 8 791 struct rtw89_rx_phy_ppdu { 792 void *buf; 793 u32 len; 794 u8 rssi_avg; 795 u8 rssi[RF_PATH_MAX]; 796 u8 mac_id; 797 u8 chan_idx; 798 u8 ie; 799 u16 rate; 800 u8 rpl_avg; 801 u8 rpl_path[RF_PATH_MAX]; 802 u8 rpl_fd[RF_PATH_MAX]; 803 u8 bw_idx; 804 u8 rx_path_en; 805 struct { 806 bool has; 807 u8 avg_snr; 808 u8 evm_max; 809 u8 evm_min; 810 } ofdm; 811 bool has_data; 812 bool has_bcn; 813 bool ldpc; 814 bool stbc; 815 bool to_self; 816 bool valid; 817 bool hdr_2_en; 818 }; 819 820 enum rtw89_mac_idx { 821 RTW89_MAC_0 = 0, 822 RTW89_MAC_1 = 1, 823 RTW89_MAC_NUM, 824 }; 825 826 enum rtw89_phy_idx { 827 RTW89_PHY_0 = 0, 828 RTW89_PHY_1 = 1, 829 RTW89_PHY_MAX 830 }; 831 832 #define __RTW89_MLD_MAX_LINK_NUM 2 833 834 enum rtw89_chanctx_idx { 835 RTW89_CHANCTX_0 = 0, 836 RTW89_CHANCTX_1 = 1, 837 838 NUM_OF_RTW89_CHANCTX, 839 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 840 }; 841 842 enum rtw89_rf_path { 843 RF_PATH_A = 0, 844 RF_PATH_B = 1, 845 RF_PATH_C = 2, 846 RF_PATH_D = 3, 847 RF_PATH_AB, 848 RF_PATH_AC, 849 RF_PATH_AD, 850 RF_PATH_BC, 851 RF_PATH_BD, 852 RF_PATH_CD, 853 RF_PATH_ABC, 854 RF_PATH_ABD, 855 RF_PATH_ACD, 856 RF_PATH_BCD, 857 RF_PATH_ABCD, 858 }; 859 860 enum rtw89_rf_path_bit { 861 RF_A = BIT(0), 862 RF_B = BIT(1), 863 RF_C = BIT(2), 864 RF_D = BIT(3), 865 866 RF_AB = (RF_A | RF_B), 867 RF_AC = (RF_A | RF_C), 868 RF_AD = (RF_A | RF_D), 869 RF_BC = (RF_B | RF_C), 870 RF_BD = (RF_B | RF_D), 871 RF_CD = (RF_C | RF_D), 872 873 RF_ABC = (RF_A | RF_B | RF_C), 874 RF_ABD = (RF_A | RF_B | RF_D), 875 RF_ACD = (RF_A | RF_C | RF_D), 876 RF_BCD = (RF_B | RF_C | RF_D), 877 878 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 879 }; 880 881 enum rtw89_bandwidth { 882 RTW89_CHANNEL_WIDTH_20 = 0, 883 RTW89_CHANNEL_WIDTH_40 = 1, 884 RTW89_CHANNEL_WIDTH_80 = 2, 885 RTW89_CHANNEL_WIDTH_160 = 3, 886 RTW89_CHANNEL_WIDTH_320 = 4, 887 888 /* keep index order above */ 889 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 890 891 RTW89_CHANNEL_WIDTH_80_80 = 5, 892 RTW89_CHANNEL_WIDTH_5 = 6, 893 RTW89_CHANNEL_WIDTH_10 = 7, 894 }; 895 896 enum rtw89_ps_mode { 897 RTW89_PS_MODE_NONE = 0, 898 RTW89_PS_MODE_RFOFF = 1, 899 RTW89_PS_MODE_CLK_GATED = 2, 900 RTW89_PS_MODE_PWR_GATED = 3, 901 }; 902 903 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 904 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 905 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 906 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 907 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 908 909 enum rtw89_pe_duration { 910 RTW89_PE_DURATION_0 = 0, 911 RTW89_PE_DURATION_8 = 1, 912 RTW89_PE_DURATION_16 = 2, 913 RTW89_PE_DURATION_16_20 = 3, 914 }; 915 916 enum rtw89_ru_bandwidth { 917 RTW89_RU26 = 0, 918 RTW89_RU52 = 1, 919 RTW89_RU106 = 2, 920 RTW89_RU52_26 = 3, 921 RTW89_RU106_26 = 4, 922 RTW89_RU_NUM, 923 }; 924 925 enum rtw89_sc_offset { 926 RTW89_SC_DONT_CARE = 0, 927 RTW89_SC_20_UPPER = 1, 928 RTW89_SC_20_LOWER = 2, 929 RTW89_SC_20_UPMOST = 3, 930 RTW89_SC_20_LOWEST = 4, 931 RTW89_SC_20_UP2X = 5, 932 RTW89_SC_20_LOW2X = 6, 933 RTW89_SC_20_UP3X = 7, 934 RTW89_SC_20_LOW3X = 8, 935 RTW89_SC_40_UPPER = 9, 936 RTW89_SC_40_LOWER = 10, 937 }; 938 939 /* only mgd features can be added to the enum */ 940 enum rtw89_wow_flags { 941 RTW89_WOW_FLAG_EN_MAGIC_PKT, 942 RTW89_WOW_FLAG_EN_REKEY_PKT, 943 RTW89_WOW_FLAG_EN_DISCONNECT, 944 RTW89_WOW_FLAG_EN_PATTERN, 945 RTW89_WOW_FLAG_NUM, 946 }; 947 948 struct rtw89_chan { 949 u8 channel; 950 u8 primary_channel; 951 enum rtw89_band band_type; 952 enum rtw89_bandwidth band_width; 953 954 /* The follow-up are derived from the above. We must ensure that it 955 * is assigned correctly in rtw89_chan_create() if new one is added. 956 */ 957 u32 freq; 958 enum rtw89_subband subband_type; 959 enum rtw89_sc_offset pri_ch_idx; 960 u8 pri_sb_idx; 961 }; 962 963 struct rtw89_chan_rcd { 964 u8 prev_primary_channel; 965 enum rtw89_band prev_band_type; 966 bool band_changed; 967 }; 968 969 struct rtw89_channel_help_params { 970 u32 tx_en; 971 }; 972 973 struct rtw89_port_reg { 974 u32 port_cfg; 975 u32 tbtt_prohib; 976 u32 bcn_area; 977 u32 bcn_early; 978 u32 tbtt_early; 979 u32 tbtt_agg; 980 u32 bcn_space; 981 u32 bcn_forcetx; 982 u32 bcn_err_cnt; 983 u32 bcn_err_flag; 984 u32 dtim_ctrl; 985 u32 tbtt_shift; 986 u32 bcn_cnt_tmr; 987 u32 tsftr_l; 988 u32 tsftr_h; 989 u32 md_tsft; 990 u32 bss_color; 991 u32 mbssid; 992 u32 mbssid_drop; 993 u32 tsf_sync; 994 u32 ptcl_dbg; 995 u32 ptcl_dbg_info; 996 u32 bcn_drop_all; 997 u32 hiq_win[RTW89_PORT_NUM]; 998 }; 999 1000 struct rtw89_txwd_body { 1001 __le32 dword0; 1002 __le32 dword1; 1003 __le32 dword2; 1004 __le32 dword3; 1005 __le32 dword4; 1006 __le32 dword5; 1007 } __packed; 1008 1009 struct rtw89_txwd_body_v1 { 1010 __le32 dword0; 1011 __le32 dword1; 1012 __le32 dword2; 1013 __le32 dword3; 1014 __le32 dword4; 1015 __le32 dword5; 1016 __le32 dword6; 1017 __le32 dword7; 1018 } __packed; 1019 1020 struct rtw89_txwd_body_v2 { 1021 __le32 dword0; 1022 __le32 dword1; 1023 __le32 dword2; 1024 __le32 dword3; 1025 __le32 dword4; 1026 __le32 dword5; 1027 __le32 dword6; 1028 __le32 dword7; 1029 } __packed; 1030 1031 struct rtw89_txwd_info { 1032 __le32 dword0; 1033 __le32 dword1; 1034 __le32 dword2; 1035 __le32 dword3; 1036 __le32 dword4; 1037 __le32 dword5; 1038 } __packed; 1039 1040 struct rtw89_txwd_info_v2 { 1041 __le32 dword0; 1042 __le32 dword1; 1043 __le32 dword2; 1044 __le32 dword3; 1045 __le32 dword4; 1046 __le32 dword5; 1047 __le32 dword6; 1048 __le32 dword7; 1049 } __packed; 1050 1051 struct rtw89_rx_desc_info { 1052 u16 pkt_size; 1053 u8 pkt_type; 1054 u8 drv_info_size; 1055 u8 phy_rpt_size; 1056 u8 hdr_cnv_size; 1057 u8 shift; 1058 u8 wl_hd_iv_len; 1059 bool long_rxdesc; 1060 bool bb_sel; 1061 bool mac_info_valid; 1062 u16 data_rate; 1063 u8 gi_ltf; 1064 u8 bw; 1065 u32 free_run_cnt; 1066 u8 user_id; 1067 bool sr_en; 1068 u8 ppdu_cnt; 1069 u8 ppdu_type; 1070 bool icv_err; 1071 bool crc32_err; 1072 bool hw_dec; 1073 bool sw_dec; 1074 bool addr1_match; 1075 u8 frag; 1076 u16 seq; 1077 u8 frame_type; 1078 u8 rx_pl_id; 1079 bool addr_cam_valid; 1080 u8 addr_cam_id; 1081 u8 sec_cam_id; 1082 u8 mac_id; 1083 u16 offset; 1084 u16 rxd_len; 1085 bool ready; 1086 }; 1087 1088 struct rtw89_rxdesc_short { 1089 __le32 dword0; 1090 __le32 dword1; 1091 __le32 dword2; 1092 __le32 dword3; 1093 } __packed; 1094 1095 struct rtw89_rxdesc_short_v2 { 1096 __le32 dword0; 1097 __le32 dword1; 1098 __le32 dword2; 1099 __le32 dword3; 1100 __le32 dword4; 1101 __le32 dword5; 1102 } __packed; 1103 1104 struct rtw89_rxdesc_long { 1105 __le32 dword0; 1106 __le32 dword1; 1107 __le32 dword2; 1108 __le32 dword3; 1109 __le32 dword4; 1110 __le32 dword5; 1111 __le32 dword6; 1112 __le32 dword7; 1113 } __packed; 1114 1115 struct rtw89_rxdesc_long_v2 { 1116 __le32 dword0; 1117 __le32 dword1; 1118 __le32 dword2; 1119 __le32 dword3; 1120 __le32 dword4; 1121 __le32 dword5; 1122 __le32 dword6; 1123 __le32 dword7; 1124 __le32 dword8; 1125 __le32 dword9; 1126 } __packed; 1127 1128 struct rtw89_tx_desc_info { 1129 u16 pkt_size; 1130 u8 wp_offset; 1131 u8 mac_id; 1132 u8 qsel; 1133 u8 ch_dma; 1134 u8 hdr_llc_len; 1135 bool is_bmc; 1136 bool en_wd_info; 1137 bool wd_page; 1138 bool use_rate; 1139 bool dis_data_fb; 1140 bool tid_indicate; 1141 bool agg_en; 1142 bool bk; 1143 u8 ampdu_density; 1144 u8 ampdu_num; 1145 bool sec_en; 1146 u8 addr_info_nr; 1147 u8 sec_keyid; 1148 u8 sec_type; 1149 u8 sec_cam_idx; 1150 u8 sec_seq[6]; 1151 u16 data_rate; 1152 u16 data_retry_lowest_rate; 1153 bool fw_dl; 1154 u16 seq; 1155 bool a_ctrl_bsr; 1156 u8 hw_ssn_sel; 1157 #define RTW89_MGMT_HW_SSN_SEL 1 1158 u8 hw_seq_mode; 1159 #define RTW89_MGMT_HW_SEQ_MODE 1 1160 bool hiq; 1161 u8 port; 1162 bool er_cap; 1163 bool stbc; 1164 bool ldpc; 1165 bool upd_wlan_hdr; 1166 }; 1167 1168 struct rtw89_core_tx_request { 1169 enum rtw89_core_tx_type tx_type; 1170 1171 struct sk_buff *skb; 1172 struct rtw89_vif_link *rtwvif_link; 1173 struct rtw89_sta_link *rtwsta_link; 1174 struct rtw89_tx_desc_info desc_info; 1175 }; 1176 1177 struct rtw89_txq { 1178 struct list_head list; 1179 unsigned long flags; 1180 int wait_cnt; 1181 }; 1182 1183 struct rtw89_mac_ax_gnt { 1184 u8 gnt_bt_sw_en; 1185 u8 gnt_bt; 1186 u8 gnt_wl_sw_en; 1187 u8 gnt_wl; 1188 } __packed; 1189 1190 struct rtw89_mac_ax_wl_act { 1191 u8 wlan_act_en; 1192 u8 wlan_act; 1193 }; 1194 1195 #define RTW89_MAC_AX_COEX_GNT_NR 2 1196 struct rtw89_mac_ax_coex_gnt { 1197 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1198 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1199 }; 1200 1201 enum rtw89_btc_ncnt { 1202 BTC_NCNT_POWER_ON = 0x0, 1203 BTC_NCNT_POWER_OFF, 1204 BTC_NCNT_INIT_COEX, 1205 BTC_NCNT_SCAN_START, 1206 BTC_NCNT_SCAN_FINISH, 1207 BTC_NCNT_SPECIAL_PACKET, 1208 BTC_NCNT_SWITCH_BAND, 1209 BTC_NCNT_RFK_TIMEOUT, 1210 BTC_NCNT_SHOW_COEX_INFO, 1211 BTC_NCNT_ROLE_INFO, 1212 BTC_NCNT_CONTROL, 1213 BTC_NCNT_RADIO_STATE, 1214 BTC_NCNT_CUSTOMERIZE, 1215 BTC_NCNT_WL_RFK, 1216 BTC_NCNT_WL_STA, 1217 BTC_NCNT_WL_STA_LAST, 1218 BTC_NCNT_FWINFO, 1219 BTC_NCNT_TIMER, 1220 BTC_NCNT_SWITCH_CHBW, 1221 BTC_NCNT_RESUME_DL_FW, 1222 BTC_NCNT_COUNTRYCODE, 1223 BTC_NCNT_NUM, 1224 }; 1225 1226 enum rtw89_btc_btinfo { 1227 BTC_BTINFO_L0 = 0, 1228 BTC_BTINFO_L1, 1229 BTC_BTINFO_L2, 1230 BTC_BTINFO_L3, 1231 BTC_BTINFO_H0, 1232 BTC_BTINFO_H1, 1233 BTC_BTINFO_H2, 1234 BTC_BTINFO_H3, 1235 BTC_BTINFO_MAX 1236 }; 1237 1238 enum rtw89_btc_dcnt { 1239 BTC_DCNT_RUN = 0x0, 1240 BTC_DCNT_CX_RUNINFO, 1241 BTC_DCNT_RPT, 1242 BTC_DCNT_RPT_HANG, 1243 BTC_DCNT_CYCLE, 1244 BTC_DCNT_CYCLE_HANG, 1245 BTC_DCNT_W1, 1246 BTC_DCNT_W1_HANG, 1247 BTC_DCNT_B1, 1248 BTC_DCNT_B1_HANG, 1249 BTC_DCNT_TDMA_NONSYNC, 1250 BTC_DCNT_SLOT_NONSYNC, 1251 BTC_DCNT_BTCNT_HANG, 1252 BTC_DCNT_BTTX_HANG, 1253 BTC_DCNT_WL_SLOT_DRIFT, 1254 BTC_DCNT_WL_STA_LAST, 1255 BTC_DCNT_BT_SLOT_DRIFT, 1256 BTC_DCNT_BT_SLOT_FLOOD, 1257 BTC_DCNT_FDDT_TRIG, 1258 BTC_DCNT_E2G, 1259 BTC_DCNT_E2G_HANG, 1260 BTC_DCNT_WL_FW_VER_MATCH, 1261 BTC_DCNT_NULL_TX_FAIL, 1262 BTC_DCNT_WL_STA_NTFY, 1263 BTC_DCNT_NUM, 1264 }; 1265 1266 enum rtw89_btc_wl_state_cnt { 1267 BTC_WCNT_SCANAP = 0x0, 1268 BTC_WCNT_DHCP, 1269 BTC_WCNT_EAPOL, 1270 BTC_WCNT_ARP, 1271 BTC_WCNT_SCBDUPDATE, 1272 BTC_WCNT_RFK_REQ, 1273 BTC_WCNT_RFK_GO, 1274 BTC_WCNT_RFK_REJECT, 1275 BTC_WCNT_RFK_TIMEOUT, 1276 BTC_WCNT_CH_UPDATE, 1277 BTC_WCNT_DBCC_ALL_2G, 1278 BTC_WCNT_DBCC_CHG, 1279 BTC_WCNT_RX_OK_LAST, 1280 BTC_WCNT_RX_OK_LAST2S, 1281 BTC_WCNT_RX_ERR_LAST, 1282 BTC_WCNT_RX_ERR_LAST2S, 1283 BTC_WCNT_RX_LAST, 1284 BTC_WCNT_NUM 1285 }; 1286 1287 enum rtw89_btc_bt_state_cnt { 1288 BTC_BCNT_RETRY = 0x0, 1289 BTC_BCNT_REINIT, 1290 BTC_BCNT_REENABLE, 1291 BTC_BCNT_SCBDREAD, 1292 BTC_BCNT_RELINK, 1293 BTC_BCNT_IGNOWL, 1294 BTC_BCNT_INQPAG, 1295 BTC_BCNT_INQ, 1296 BTC_BCNT_PAGE, 1297 BTC_BCNT_ROLESW, 1298 BTC_BCNT_AFH, 1299 BTC_BCNT_INFOUPDATE, 1300 BTC_BCNT_INFOSAME, 1301 BTC_BCNT_SCBDUPDATE, 1302 BTC_BCNT_HIPRI_TX, 1303 BTC_BCNT_HIPRI_RX, 1304 BTC_BCNT_LOPRI_TX, 1305 BTC_BCNT_LOPRI_RX, 1306 BTC_BCNT_POLUT, 1307 BTC_BCNT_POLUT_NOW, 1308 BTC_BCNT_POLUT_DIFF, 1309 BTC_BCNT_RATECHG, 1310 BTC_BCNT_NUM, 1311 }; 1312 1313 enum rtw89_btc_bt_profile { 1314 BTC_BT_NOPROFILE = 0, 1315 BTC_BT_HFP = BIT(0), 1316 BTC_BT_HID = BIT(1), 1317 BTC_BT_A2DP = BIT(2), 1318 BTC_BT_PAN = BIT(3), 1319 BTC_PROFILE_MAX = 4, 1320 }; 1321 1322 struct rtw89_btc_ant_info { 1323 u8 type; /* shared, dedicated */ 1324 u8 num; 1325 u8 isolation; 1326 1327 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1328 u8 diversity: 1; 1329 u8 btg_pos: 2; 1330 u8 stream_cnt: 4; 1331 }; 1332 1333 struct rtw89_btc_ant_info_v7 { 1334 u8 type; /* shared, dedicated(non-shared) */ 1335 u8 num; /* antenna count */ 1336 u8 isolation; 1337 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1338 1339 u8 diversity; /* only for wifi use 1-antenna */ 1340 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1341 u8 stream_cnt; /* spatial_stream count */ 1342 u8 rsvd; 1343 } __packed; 1344 1345 enum rtw89_tfc_dir { 1346 RTW89_TFC_UL, 1347 RTW89_TFC_DL, 1348 }; 1349 1350 struct rtw89_btc_wl_smap { 1351 u32 busy: 1; 1352 u32 scan: 1; 1353 u32 connecting: 1; 1354 u32 roaming: 1; 1355 u32 dbccing: 1; 1356 u32 _4way: 1; 1357 u32 rf_off: 1; 1358 u32 lps: 2; 1359 u32 ips: 1; 1360 u32 init_ok: 1; 1361 u32 traffic_dir : 2; 1362 u32 rf_off_pre: 1; 1363 u32 lps_pre: 2; 1364 u32 lps_exiting: 1; 1365 u32 emlsr: 1; 1366 }; 1367 1368 enum rtw89_tfc_lv { 1369 RTW89_TFC_IDLE, 1370 RTW89_TFC_ULTRA_LOW, 1371 RTW89_TFC_LOW, 1372 RTW89_TFC_MID, 1373 RTW89_TFC_HIGH, 1374 }; 1375 1376 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1377 DECLARE_EWMA(tp, 10, 2); 1378 1379 struct rtw89_traffic_stats { 1380 /* units in bytes */ 1381 u64 tx_unicast; 1382 u64 rx_unicast; 1383 u32 tx_avg_len; 1384 u32 rx_avg_len; 1385 1386 /* count for packets */ 1387 u64 tx_cnt; 1388 u64 rx_cnt; 1389 1390 /* units in Mbps */ 1391 u32 tx_throughput; 1392 u32 rx_throughput; 1393 u32 tx_throughput_raw; 1394 u32 rx_throughput_raw; 1395 1396 u32 rx_tf_acc; 1397 u32 rx_tf_periodic; 1398 1399 enum rtw89_tfc_lv tx_tfc_lv; 1400 enum rtw89_tfc_lv rx_tfc_lv; 1401 struct ewma_tp tx_ewma_tp; 1402 struct ewma_tp rx_ewma_tp; 1403 1404 u16 tx_rate; 1405 u16 rx_rate; 1406 }; 1407 1408 struct rtw89_btc_chdef { 1409 u8 center_ch; 1410 u8 band; 1411 u8 chan; 1412 enum rtw89_sc_offset offset; 1413 enum rtw89_bandwidth bw; 1414 }; 1415 1416 struct rtw89_btc_statistic { 1417 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1418 struct rtw89_traffic_stats traffic; 1419 }; 1420 1421 #define BTC_WL_RSSI_THMAX 4 1422 1423 struct rtw89_btc_wl_link_info { 1424 struct rtw89_btc_chdef chdef; 1425 struct rtw89_btc_statistic stat; 1426 enum rtw89_tfc_dir dir; 1427 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1428 u8 mac_addr[ETH_ALEN]; 1429 u8 busy; 1430 u8 ch; 1431 u8 bw; 1432 u8 band; 1433 u8 role; 1434 u8 pid; 1435 u8 phy; 1436 u8 dtim_period; 1437 u8 mode; 1438 u8 tx_1ss_limit; 1439 1440 u8 mac_id; 1441 u8 tx_retry; 1442 1443 u32 bcn_period; 1444 u32 busy_t; 1445 u32 tx_time; 1446 u32 client_cnt; 1447 u32 rx_rate_drop_cnt; 1448 u32 noa_duration; 1449 1450 u32 active: 1; 1451 u32 noa: 1; 1452 u32 client_ps: 1; 1453 u32 connected: 2; 1454 }; 1455 1456 union rtw89_btc_wl_state_map { 1457 u32 val; 1458 struct rtw89_btc_wl_smap map; 1459 }; 1460 1461 struct rtw89_btc_bt_hfp_desc { 1462 u32 exist: 1; 1463 u32 type: 2; 1464 u32 rsvd: 29; 1465 }; 1466 1467 struct rtw89_btc_bt_hid_desc { 1468 u32 exist: 1; 1469 u32 slot_info: 2; 1470 u32 pair_cnt: 2; 1471 u32 type: 8; 1472 u32 rsvd: 19; 1473 }; 1474 1475 struct rtw89_btc_bt_a2dp_desc { 1476 u8 exist: 1; 1477 u8 exist_last: 1; 1478 u8 play_latency: 1; 1479 u8 type: 3; 1480 u8 active: 1; 1481 u8 sink: 1; 1482 u32 handle_update: 1; 1483 u32 devinfo_query: 1; 1484 u32 no_empty_streak_2s: 8; 1485 u32 no_empty_streak_max: 8; 1486 u32 rsvd: 6; 1487 1488 u8 bitpool; 1489 u16 vendor_id; 1490 u32 device_name; 1491 u32 flush_time; 1492 }; 1493 1494 struct rtw89_btc_bt_pan_desc { 1495 u32 exist: 1; 1496 u32 type: 1; 1497 u32 active: 1; 1498 u32 rsvd: 29; 1499 }; 1500 1501 struct rtw89_btc_bt_rfk_info { 1502 u32 run: 1; 1503 u32 req: 1; 1504 u32 timeout: 1; 1505 u32 rsvd: 29; 1506 }; 1507 1508 union rtw89_btc_bt_rfk_info_map { 1509 u32 val; 1510 struct rtw89_btc_bt_rfk_info map; 1511 }; 1512 1513 struct rtw89_btc_bt_ver_info { 1514 u32 fw_coex; /* match with which coex_ver */ 1515 u32 fw; 1516 }; 1517 1518 struct rtw89_btc_bool_sta_chg { 1519 u32 now: 1; 1520 u32 last: 1; 1521 u32 remain: 1; 1522 u32 srvd: 29; 1523 }; 1524 1525 struct rtw89_btc_u8_sta_chg { 1526 u8 now; 1527 u8 last; 1528 u8 remain; 1529 u8 rsvd; 1530 }; 1531 1532 struct rtw89_btc_wl_scan_info { 1533 u8 band[RTW89_PHY_MAX]; 1534 u8 phy_map; 1535 u8 rsvd; 1536 }; 1537 1538 struct rtw89_btc_wl_dbcc_info { 1539 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1540 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1541 u8 real_band[RTW89_PHY_MAX]; 1542 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1543 }; 1544 1545 struct rtw89_btc_wl_active_role { 1546 u8 connected: 1; 1547 u8 pid: 3; 1548 u8 phy: 1; 1549 u8 noa: 1; 1550 u8 band: 2; 1551 1552 u8 client_ps: 1; 1553 u8 bw: 7; 1554 1555 u8 role; 1556 u8 ch; 1557 1558 u16 tx_lvl; 1559 u16 rx_lvl; 1560 u16 tx_rate; 1561 u16 rx_rate; 1562 }; 1563 1564 struct rtw89_btc_wl_active_role_v1 { 1565 u8 connected: 1; 1566 u8 pid: 3; 1567 u8 phy: 1; 1568 u8 noa: 1; 1569 u8 band: 2; 1570 1571 u8 client_ps: 1; 1572 u8 bw: 7; 1573 1574 u8 role; 1575 u8 ch; 1576 1577 u16 tx_lvl; 1578 u16 rx_lvl; 1579 u16 tx_rate; 1580 u16 rx_rate; 1581 1582 u32 noa_duration; /* ms */ 1583 }; 1584 1585 struct rtw89_btc_wl_active_role_v2 { 1586 u8 connected: 1; 1587 u8 pid: 3; 1588 u8 phy: 1; 1589 u8 noa: 1; 1590 u8 band: 2; 1591 1592 u8 client_ps: 1; 1593 u8 bw: 7; 1594 1595 u8 role; 1596 u8 ch; 1597 1598 u32 noa_duration; /* ms */ 1599 }; 1600 1601 struct rtw89_btc_wl_active_role_v7 { 1602 u8 connected; 1603 u8 pid; 1604 u8 phy; 1605 u8 noa; 1606 1607 u8 band; 1608 u8 client_ps; 1609 u8 bw; 1610 u8 role; 1611 1612 u8 ch; 1613 u8 noa_dur; 1614 u8 client_cnt; 1615 u8 rsvd2; 1616 } __packed; 1617 1618 struct rtw89_btc_wl_role_info_bpos { 1619 u16 none: 1; 1620 u16 station: 1; 1621 u16 ap: 1; 1622 u16 vap: 1; 1623 u16 adhoc: 1; 1624 u16 adhoc_master: 1; 1625 u16 mesh: 1; 1626 u16 moniter: 1; 1627 u16 p2p_device: 1; 1628 u16 p2p_gc: 1; 1629 u16 p2p_go: 1; 1630 u16 nan: 1; 1631 }; 1632 1633 struct rtw89_btc_wl_scc_ctrl { 1634 u8 null_role1; 1635 u8 null_role2; 1636 u8 ebt_null; /* if tx null at EBT slot */ 1637 }; 1638 1639 union rtw89_btc_wl_role_info_map { 1640 u16 val; 1641 struct rtw89_btc_wl_role_info_bpos role; 1642 }; 1643 1644 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1645 u8 connect_cnt; 1646 u8 link_mode; 1647 union rtw89_btc_wl_role_info_map role_map; 1648 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1649 }; 1650 1651 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1652 u8 connect_cnt; 1653 u8 link_mode; 1654 union rtw89_btc_wl_role_info_map role_map; 1655 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1656 u32 mrole_type; /* btc_wl_mrole_type */ 1657 u32 mrole_noa_duration; /* ms */ 1658 1659 u32 dbcc_en: 1; 1660 u32 dbcc_chg: 1; 1661 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1662 u32 link_mode_chg: 1; 1663 u32 rsvd: 27; 1664 }; 1665 1666 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1667 u8 connect_cnt; 1668 u8 link_mode; 1669 union rtw89_btc_wl_role_info_map role_map; 1670 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1671 u32 mrole_type; /* btc_wl_mrole_type */ 1672 u32 mrole_noa_duration; /* ms */ 1673 1674 u32 dbcc_en: 1; 1675 u32 dbcc_chg: 1; 1676 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1677 u32 link_mode_chg: 1; 1678 u32 rsvd: 27; 1679 }; 1680 1681 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1682 u8 connected; 1683 u8 pid; 1684 u8 phy; 1685 u8 noa; 1686 1687 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1688 u8 active; /* 0:rlink is under doze */ 1689 u8 bw; /* enum channel_width */ 1690 u8 role; /*enum role_type */ 1691 1692 u8 ch; 1693 u8 noa_dur; /* ms */ 1694 u8 client_cnt; /* for Role = P2P-Go/AP */ 1695 u8 mode; /* wifi protocol */ 1696 } __packed; 1697 1698 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1699 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1700 u8 connect_cnt; 1701 u8 link_mode; 1702 u8 link_mode_chg; 1703 u8 p2p_2g; 1704 1705 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1706 1707 u32 role_map; 1708 u32 mrole_type; /* btc_wl_mrole_type */ 1709 u32 mrole_noa_duration; /* ms */ 1710 u32 dbcc_en; 1711 u32 dbcc_chg; 1712 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1713 } __packed; 1714 1715 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1716 u8 connect_cnt; 1717 u8 link_mode; 1718 u8 link_mode_chg; 1719 u8 p2p_2g; 1720 1721 u8 pta_req_band; 1722 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1723 u8 dbcc_chg; 1724 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1725 1726 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1727 1728 u32 role_map; 1729 u32 mrole_type; /* btc_wl_mrole_type */ 1730 u32 mrole_noa_duration; /* ms */ 1731 } __packed; 1732 1733 struct rtw89_btc_wl_ver_info { 1734 u32 fw_coex; /* match with which coex_ver */ 1735 u32 fw; 1736 u32 mac; 1737 u32 bb; 1738 u32 rf; 1739 }; 1740 1741 struct rtw89_btc_wl_afh_info { 1742 u8 en; 1743 u8 ch; 1744 u8 bw; 1745 u8 rsvd; 1746 } __packed; 1747 1748 struct rtw89_btc_wl_rfk_info { 1749 u32 state: 2; 1750 u32 path_map: 4; 1751 u32 phy_map: 2; 1752 u32 band: 2; 1753 u32 type: 8; 1754 u32 rsvd: 14; 1755 1756 u32 start_time; 1757 u32 proc_time; 1758 }; 1759 1760 struct rtw89_btc_bt_smap { 1761 u32 connect: 1; 1762 u32 ble_connect: 1; 1763 u32 acl_busy: 1; 1764 u32 sco_busy: 1; 1765 u32 mesh_busy: 1; 1766 u32 inq_pag: 1; 1767 }; 1768 1769 union rtw89_btc_bt_state_map { 1770 u32 val; 1771 struct rtw89_btc_bt_smap map; 1772 }; 1773 1774 #define BTC_BT_RSSI_THMAX 4 1775 #define BTC_BT_AFH_GROUP 12 1776 #define BTC_BT_AFH_LE_GROUP 5 1777 1778 struct rtw89_btc_bt_link_info { 1779 struct rtw89_btc_u8_sta_chg profile_cnt; 1780 struct rtw89_btc_bool_sta_chg multi_link; 1781 struct rtw89_btc_bool_sta_chg relink; 1782 struct rtw89_btc_bt_hfp_desc hfp_desc; 1783 struct rtw89_btc_bt_hid_desc hid_desc; 1784 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1785 struct rtw89_btc_bt_pan_desc pan_desc; 1786 union rtw89_btc_bt_state_map status; 1787 1788 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1789 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1790 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1791 u8 afh_map[BTC_BT_AFH_GROUP]; 1792 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1793 1794 u32 role_sw: 1; 1795 u32 slave_role: 1; 1796 u32 afh_update: 1; 1797 u32 cqddr: 1; 1798 u32 rssi: 8; 1799 u32 tx_3m: 1; 1800 u32 rsvd: 19; 1801 }; 1802 1803 struct rtw89_btc_3rdcx_info { 1804 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1805 u8 hw_coex; 1806 u16 rsvd; 1807 }; 1808 1809 struct rtw89_btc_dm_emap { 1810 u32 init: 1; 1811 u32 pta_owner: 1; 1812 u32 wl_rfk_timeout: 1; 1813 u32 bt_rfk_timeout: 1; 1814 u32 wl_fw_hang: 1; 1815 u32 cycle_hang: 1; 1816 u32 w1_hang: 1; 1817 u32 b1_hang: 1; 1818 u32 tdma_no_sync: 1; 1819 u32 slot_no_sync: 1; 1820 u32 wl_slot_drift: 1; 1821 u32 bt_slot_drift: 1; 1822 u32 role_num_mismatch: 1; 1823 u32 null1_tx_late: 1; 1824 u32 bt_afh_conflict: 1; 1825 u32 bt_leafh_conflict: 1; 1826 u32 bt_slot_flood: 1; 1827 u32 wl_e2g_hang: 1; 1828 u32 wl_ver_mismatch: 1; 1829 u32 bt_ver_mismatch: 1; 1830 u32 rfe_type0: 1; 1831 u32 h2c_buffer_over: 1; 1832 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1833 u32 wl_no_sta_ntfy: 1; 1834 1835 u32 h2c_bmap_mismatch: 1; 1836 u32 c2h_bmap_mismatch: 1; 1837 u32 h2c_struct_invalid: 1; 1838 u32 c2h_struct_invalid: 1; 1839 u32 h2c_c2h_buffer_mismatch: 1; 1840 }; 1841 1842 union rtw89_btc_dm_error_map { 1843 u32 val; 1844 struct rtw89_btc_dm_emap map; 1845 }; 1846 1847 struct rtw89_btc_rf_para { 1848 u32 tx_pwr_freerun; 1849 u32 rx_gain_freerun; 1850 u32 tx_pwr_perpkt; 1851 u32 rx_gain_perpkt; 1852 }; 1853 1854 struct rtw89_btc_wl_nhm { 1855 u8 instant_wl_nhm_dbm; 1856 u8 instant_wl_nhm_per_mhz; 1857 u16 valid_record_times; 1858 s8 record_pwr[16]; 1859 u8 record_ratio[16]; 1860 s8 pwr; /* dbm_per_MHz */ 1861 u8 ratio; 1862 u8 current_status; 1863 u8 refresh; 1864 bool start_flag; 1865 s8 pwr_max; 1866 s8 pwr_min; 1867 }; 1868 1869 struct rtw89_btc_wl_info { 1870 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1871 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1872 struct rtw89_btc_wl_rfk_info rfk_info; 1873 struct rtw89_btc_wl_ver_info ver_info; 1874 struct rtw89_btc_wl_afh_info afh_info; 1875 struct rtw89_btc_wl_role_info role_info; 1876 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1877 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1878 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1879 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1880 struct rtw89_btc_wl_scan_info scan_info; 1881 struct rtw89_btc_wl_dbcc_info dbcc_info; 1882 struct rtw89_btc_rf_para rf_para; 1883 struct rtw89_btc_wl_nhm nhm; 1884 union rtw89_btc_wl_state_map status; 1885 1886 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1887 u8 rssi_level; 1888 u8 cn_report; 1889 u8 coex_mode; 1890 u8 pta_req_mac; 1891 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */ 1892 1893 bool is_5g_hi_channel; 1894 bool pta_reg_mac_chg; 1895 bool bg_mode; 1896 bool he_mode; 1897 bool scbd_change; 1898 bool fw_ver_mismatch; 1899 bool client_cnt_inc_2g; 1900 u32 scbd; 1901 }; 1902 1903 struct rtw89_btc_module { 1904 struct rtw89_btc_ant_info ant; 1905 u8 rfe_type; 1906 u8 cv; 1907 1908 u8 bt_solo: 1; 1909 u8 bt_pos: 1; 1910 u8 switch_type: 1; 1911 u8 wa_type: 3; 1912 1913 u8 kt_ver_adie; 1914 }; 1915 1916 struct rtw89_btc_module_v7 { 1917 u8 rfe_type; 1918 u8 kt_ver; 1919 u8 bt_solo; 1920 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1921 1922 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1923 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1924 u8 kt_ver_adie; 1925 u8 rsvd; 1926 1927 struct rtw89_btc_ant_info_v7 ant; 1928 } __packed; 1929 1930 union rtw89_btc_module_info { 1931 struct rtw89_btc_module md; 1932 struct rtw89_btc_module_v7 md_v7; 1933 }; 1934 1935 #define RTW89_BTC_DM_MAXSTEP 30 1936 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1937 1938 struct rtw89_btc_dm_step { 1939 u16 step[RTW89_BTC_DM_MAXSTEP]; 1940 u8 step_pos; 1941 bool step_ov; 1942 }; 1943 1944 struct rtw89_btc_init_info { 1945 struct rtw89_btc_module module; 1946 u8 wl_guard_ch; 1947 1948 u8 wl_only: 1; 1949 u8 wl_init_ok: 1; 1950 u8 dbcc_en: 1; 1951 u8 cx_other: 1; 1952 u8 bt_only: 1; 1953 1954 u16 rsvd; 1955 }; 1956 1957 struct rtw89_btc_init_info_v7 { 1958 u8 wl_guard_ch; 1959 u8 wl_only; 1960 u8 wl_init_ok; 1961 u8 rsvd3; 1962 1963 u8 cx_other; 1964 u8 bt_only; 1965 u8 pta_mode; 1966 u8 pta_direction; 1967 1968 struct rtw89_btc_module_v7 module; 1969 } __packed; 1970 1971 union rtw89_btc_init_info_u { 1972 struct rtw89_btc_init_info init; 1973 struct rtw89_btc_init_info_v7 init_v7; 1974 }; 1975 1976 struct rtw89_btc_wl_tx_limit_para { 1977 u16 enable; 1978 u32 tx_time; /* unit: us */ 1979 u16 tx_retry; 1980 }; 1981 1982 enum rtw89_btc_bt_scan_type { 1983 BTC_SCAN_INQ = 0, 1984 BTC_SCAN_PAGE, 1985 BTC_SCAN_BLE, 1986 BTC_SCAN_INIT, 1987 BTC_SCAN_TV, 1988 BTC_SCAN_ADV, 1989 BTC_SCAN_MAX1, 1990 }; 1991 1992 enum rtw89_btc_ble_scan_type { 1993 CXSCAN_BG = 0, 1994 CXSCAN_INIT, 1995 CXSCAN_LE, 1996 CXSCAN_MAX 1997 }; 1998 1999 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2000 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2001 2002 struct rtw89_btc_bt_scan_info_v1 { 2003 __le16 win; 2004 __le16 intvl; 2005 __le32 flags; 2006 } __packed; 2007 2008 struct rtw89_btc_bt_scan_info_v2 { 2009 __le16 win; 2010 __le16 intvl; 2011 } __packed; 2012 2013 struct rtw89_btc_fbtc_btscan_v1 { 2014 u8 fver; /* btc_ver::fcxbtscan */ 2015 u8 rsvd; 2016 __le16 rsvd2; 2017 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2018 } __packed; 2019 2020 struct rtw89_btc_fbtc_btscan_v2 { 2021 u8 fver; /* btc_ver::fcxbtscan */ 2022 u8 type; 2023 __le16 rsvd2; 2024 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2025 } __packed; 2026 2027 struct rtw89_btc_fbtc_btscan_v7 { 2028 u8 fver; /* btc_ver::fcxbtscan */ 2029 u8 type; 2030 u8 rsvd0; 2031 u8 rsvd1; 2032 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2033 } __packed; 2034 2035 union rtw89_btc_fbtc_btscan { 2036 struct rtw89_btc_fbtc_btscan_v1 v1; 2037 struct rtw89_btc_fbtc_btscan_v2 v2; 2038 struct rtw89_btc_fbtc_btscan_v7 v7; 2039 }; 2040 2041 struct rtw89_btc_bt_info { 2042 struct rtw89_btc_bt_link_info link_info; 2043 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2044 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2045 struct rtw89_btc_bt_ver_info ver_info; 2046 struct rtw89_btc_bool_sta_chg enable; 2047 struct rtw89_btc_bool_sta_chg inq_pag; 2048 struct rtw89_btc_rf_para rf_para; 2049 union rtw89_btc_bt_rfk_info_map rfk_info; 2050 2051 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2052 u8 rssi_level; 2053 2054 u32 scbd; 2055 u32 feature; 2056 2057 u32 mbx_avl: 1; 2058 u32 whql_test: 1; 2059 u32 igno_wl: 1; 2060 u32 reinit: 1; 2061 u32 ble_scan_en: 1; 2062 u32 btg_type: 1; 2063 u32 inq: 1; 2064 u32 pag: 1; 2065 u32 run_patch_code: 1; 2066 u32 hi_lna_rx: 1; 2067 u32 scan_rx_low_pri: 1; 2068 u32 scan_info_update: 1; 2069 u32 lna_constrain: 3; 2070 u32 rsvd: 17; 2071 }; 2072 2073 struct rtw89_btc_cx { 2074 struct rtw89_btc_wl_info wl; 2075 struct rtw89_btc_bt_info bt; 2076 struct rtw89_btc_3rdcx_info other; 2077 u32 state_map; 2078 u32 cnt_bt[BTC_BCNT_NUM]; 2079 u32 cnt_wl[BTC_WCNT_NUM]; 2080 }; 2081 2082 struct rtw89_btc_fbtc_tdma { 2083 u8 type; /* btc_ver::fcxtdma */ 2084 u8 rxflctrl; 2085 u8 txpause; 2086 u8 wtgle_n; 2087 u8 leak_n; 2088 u8 ext_ctrl; 2089 u8 rxflctrl_role; 2090 u8 option_ctrl; 2091 } __packed; 2092 2093 struct rtw89_btc_fbtc_tdma_v3 { 2094 u8 fver; /* btc_ver::fcxtdma */ 2095 u8 rsvd; 2096 __le16 rsvd1; 2097 struct rtw89_btc_fbtc_tdma tdma; 2098 } __packed; 2099 2100 union rtw89_btc_fbtc_tdma_le32 { 2101 struct rtw89_btc_fbtc_tdma v1; 2102 struct rtw89_btc_fbtc_tdma_v3 v3; 2103 }; 2104 2105 #define CXMREG_MAX 30 2106 #define CXMREG_MAX_V2 20 2107 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2108 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2109 2110 enum rtw89_btc_bt_sta_counter { 2111 BTC_BCNT_RFK_REQ = 0, 2112 BTC_BCNT_RFK_GO = 1, 2113 BTC_BCNT_RFK_REJECT = 2, 2114 BTC_BCNT_RFK_FAIL = 3, 2115 BTC_BCNT_RFK_TIMEOUT = 4, 2116 BTC_BCNT_HI_TX = 5, 2117 BTC_BCNT_HI_RX = 6, 2118 BTC_BCNT_LO_TX = 7, 2119 BTC_BCNT_LO_RX = 8, 2120 BTC_BCNT_POLLUTED = 9, 2121 BTC_BCNT_STA_MAX 2122 }; 2123 2124 enum rtw89_btc_bt_sta_counter_v105 { 2125 BTC_BCNT_RFK_REQ_V105 = 0, 2126 BTC_BCNT_HI_TX_V105 = 1, 2127 BTC_BCNT_HI_RX_V105 = 2, 2128 BTC_BCNT_LO_TX_V105 = 3, 2129 BTC_BCNT_LO_RX_V105 = 4, 2130 BTC_BCNT_POLLUTED_V105 = 5, 2131 BTC_BCNT_STA_MAX_V105 2132 }; 2133 2134 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2135 u16 fver; /* btc_ver::fcxbtcrpt */ 2136 u16 rpt_cnt; /* tmr counters */ 2137 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2138 u32 wl_fw_cx_offload; 2139 u32 wl_fw_ver; 2140 u32 rpt_enable; 2141 u32 rpt_para; /* ms */ 2142 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2143 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2144 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2145 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2146 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2147 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2148 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2149 u32 c2h_cnt; /* fw send c2h counter */ 2150 u32 h2c_cnt; /* fw recv h2c counter */ 2151 } __packed; 2152 2153 struct rtw89_btc_fbtc_rpt_ctrl_info { 2154 __le32 cnt; /* fw report counter */ 2155 __le32 en; /* report map */ 2156 __le32 para; /* not used */ 2157 2158 __le32 cnt_c2h; /* fw send c2h counter */ 2159 __le32 cnt_h2c; /* fw recv h2c counter */ 2160 __le32 len_c2h; /* The total length of the last C2H */ 2161 2162 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2163 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2164 } __packed; 2165 2166 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2167 __le32 cx_ver; /* match which driver's coex version */ 2168 __le32 fw_ver; 2169 __le32 en; /* report map */ 2170 2171 __le16 cnt; /* fw report counter */ 2172 __le16 cnt_c2h; /* fw send c2h counter */ 2173 __le16 cnt_h2c; /* fw recv h2c counter */ 2174 __le16 len_c2h; /* The total length of the last C2H */ 2175 2176 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2177 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2178 } __packed; 2179 2180 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2181 __le16 cnt; /* fw report counter */ 2182 __le16 cnt_c2h; /* fw send c2h counter */ 2183 __le16 cnt_h2c; /* fw recv h2c counter */ 2184 __le16 len_c2h; /* The total length of the last C2H */ 2185 2186 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2187 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2188 2189 __le32 cx_ver; /* match which driver's coex version */ 2190 __le32 fw_ver; 2191 __le32 en; /* report map */ 2192 } __packed; 2193 2194 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2195 __le32 cx_ver; /* match which driver's coex version */ 2196 __le32 cx_offload; 2197 __le32 fw_ver; 2198 } __packed; 2199 2200 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2201 __le32 cnt_empty; /* a2dp empty count */ 2202 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2203 __le32 cnt_tx; 2204 __le32 cnt_ack; 2205 __le32 cnt_nack; 2206 } __packed; 2207 2208 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2209 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2210 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2211 __le32 cnt_recv; /* fw recv mailbox counter */ 2212 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2213 } __packed; 2214 2215 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2216 u8 fver; 2217 u8 rsvd; 2218 __le16 rsvd1; 2219 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2220 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2221 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2222 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2223 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2224 } __packed; 2225 2226 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2227 u8 fver; 2228 u8 rsvd; 2229 __le16 rsvd1; 2230 2231 u8 gnt_val[RTW89_PHY_MAX][4]; 2232 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2233 2234 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2235 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2236 } __packed; 2237 2238 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2239 u8 fver; 2240 u8 rsvd; 2241 __le16 rsvd1; 2242 2243 u8 gnt_val[RTW89_PHY_MAX][4]; 2244 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2245 2246 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2247 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2248 } __packed; 2249 2250 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2251 u8 fver; 2252 u8 rsvd0; 2253 u8 rsvd1; 2254 u8 rsvd2; 2255 2256 u8 gnt_val[RTW89_PHY_MAX][4]; 2257 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2258 2259 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2260 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2261 } __packed; 2262 2263 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2264 u8 fver; 2265 u8 rsvd0; 2266 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2267 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2268 2269 u8 gnt_val[RTW89_PHY_MAX][4]; 2270 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2271 2272 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2273 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2274 } __packed; 2275 2276 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2277 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2278 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2279 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2280 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2281 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2282 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2283 }; 2284 2285 enum rtw89_fbtc_ext_ctrl_type { 2286 CXECTL_OFF = 0x0, /* tdma off */ 2287 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2288 CXECTL_EXT = 0x2, 2289 CXECTL_MAX 2290 }; 2291 2292 union rtw89_btc_fbtc_rxflct { 2293 u8 val; 2294 u8 type: 3; 2295 u8 tgln_n: 5; 2296 }; 2297 2298 enum rtw89_btc_cxst_state { 2299 CXST_OFF = 0x0, 2300 CXST_B2W = 0x1, 2301 CXST_W1 = 0x2, 2302 CXST_W2 = 0x3, 2303 CXST_W2B = 0x4, 2304 CXST_B1 = 0x5, 2305 CXST_B2 = 0x6, 2306 CXST_B3 = 0x7, 2307 CXST_B4 = 0x8, 2308 CXST_LK = 0x9, 2309 CXST_BLK = 0xa, 2310 CXST_E2G = 0xb, 2311 CXST_E5G = 0xc, 2312 CXST_EBT = 0xd, 2313 CXST_ENULL = 0xe, 2314 CXST_WLK = 0xf, 2315 CXST_W1FDD = 0x10, 2316 CXST_B1FDD = 0x11, 2317 CXST_MAX = 0x12, 2318 }; 2319 2320 enum rtw89_btc_cxevnt { 2321 CXEVNT_TDMA_ENTRY = 0x0, 2322 CXEVNT_WL_TMR, 2323 CXEVNT_B1_TMR, 2324 CXEVNT_B2_TMR, 2325 CXEVNT_B3_TMR, 2326 CXEVNT_B4_TMR, 2327 CXEVNT_W2B_TMR, 2328 CXEVNT_B2W_TMR, 2329 CXEVNT_BCN_EARLY, 2330 CXEVNT_A2DP_EMPTY, 2331 CXEVNT_LK_END, 2332 CXEVNT_RX_ISR, 2333 CXEVNT_RX_FC0, 2334 CXEVNT_RX_FC1, 2335 CXEVNT_BT_RELINK, 2336 CXEVNT_BT_RETRY, 2337 CXEVNT_E2G, 2338 CXEVNT_E5G, 2339 CXEVNT_EBT, 2340 CXEVNT_ENULL, 2341 CXEVNT_DRV_WLK, 2342 CXEVNT_BCN_OK, 2343 CXEVNT_BT_CHANGE, 2344 CXEVNT_EBT_EXTEND, 2345 CXEVNT_E2G_NULL1, 2346 CXEVNT_B1FDD_TMR, 2347 CXEVNT_MAX 2348 }; 2349 2350 enum { 2351 CXBCN_ALL = 0x0, 2352 CXBCN_ALL_OK, 2353 CXBCN_BT_SLOT, 2354 CXBCN_BT_OK, 2355 CXBCN_MAX 2356 }; 2357 2358 enum btc_slot_type { 2359 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2360 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2361 CXSTYPE_NUM, 2362 }; 2363 2364 enum { /* TIME */ 2365 CXT_BT = 0x0, 2366 CXT_WL = 0x1, 2367 CXT_MAX 2368 }; 2369 2370 enum { /* TIME-A2DP */ 2371 CXT_FLCTRL_OFF = 0x0, 2372 CXT_FLCTRL_ON = 0x1, 2373 CXT_FLCTRL_MAX 2374 }; 2375 2376 enum { /* STEP TYPE */ 2377 CXSTEP_NONE = 0x0, 2378 CXSTEP_EVNT = 0x1, 2379 CXSTEP_SLOT = 0x2, 2380 CXSTEP_MAX, 2381 }; 2382 2383 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2384 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2385 RPT_BT_AFH_SEQ_LE = 0x20 2386 }; 2387 2388 #define BTC_DBG_MAX1 32 2389 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2390 u8 fver; /* btc_ver::fcxgpiodbg */ 2391 u8 rsvd; 2392 __le16 rsvd2; 2393 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2394 __le32 pre_state; /* the debug signal is 1 or 0 */ 2395 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2396 } __packed; 2397 2398 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2399 u8 fver; 2400 u8 rsvd0; 2401 u8 rsvd1; 2402 u8 rsvd2; 2403 2404 u8 gpio_map[BTC_DBG_MAX1]; 2405 2406 __le32 en_map; 2407 __le32 pre_state; 2408 } __packed; 2409 2410 union rtw89_btc_fbtc_gpio_dbg { 2411 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2412 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2413 }; 2414 2415 struct rtw89_btc_fbtc_mreg_val_v1 { 2416 u8 fver; /* btc_ver::fcxmreg */ 2417 u8 reg_num; 2418 __le16 rsvd; 2419 __le32 mreg_val[CXMREG_MAX]; 2420 } __packed; 2421 2422 struct rtw89_btc_fbtc_mreg_val_v2 { 2423 u8 fver; /* btc_ver::fcxmreg */ 2424 u8 reg_num; 2425 __le16 rsvd; 2426 __le32 mreg_val[CXMREG_MAX_V2]; 2427 } __packed; 2428 2429 struct rtw89_btc_fbtc_mreg_val_v7 { 2430 u8 fver; 2431 u8 reg_num; 2432 u8 rsvd0; 2433 u8 rsvd1; 2434 __le32 mreg_val[CXMREG_MAX_V2]; 2435 } __packed; 2436 2437 union rtw89_btc_fbtc_mreg_val { 2438 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2439 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2440 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2441 }; 2442 2443 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2444 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2445 .offset = cpu_to_le32(__offset), } 2446 2447 struct rtw89_btc_fbtc_mreg { 2448 __le16 type; 2449 __le16 bytes; 2450 __le32 offset; 2451 } __packed; 2452 2453 struct rtw89_btc_fbtc_slot { 2454 __le16 dur; 2455 __le32 cxtbl; 2456 __le16 cxtype; 2457 } __packed; 2458 2459 struct rtw89_btc_fbtc_slots { 2460 u8 fver; /* btc_ver::fcxslots */ 2461 u8 tbl_num; 2462 __le16 rsvd; 2463 __le32 update_map; 2464 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2465 } __packed; 2466 2467 struct rtw89_btc_fbtc_slot_v7 { 2468 __le16 dur; /* slot duration */ 2469 __le16 cxtype; 2470 __le32 cxtbl; 2471 } __packed; 2472 2473 struct rtw89_btc_fbtc_slot_u16 { 2474 __le16 dur; /* slot duration */ 2475 __le16 cxtype; 2476 __le16 cxtbl_l16; /* coex table [15:0] */ 2477 __le16 cxtbl_h16; /* coex table [31:16] */ 2478 } __packed; 2479 2480 struct rtw89_btc_fbtc_1slot_v7 { 2481 u8 fver; 2482 u8 sid; /* slot id */ 2483 __le16 rsvd; 2484 struct rtw89_btc_fbtc_slot_v7 slot; 2485 } __packed; 2486 2487 struct rtw89_btc_fbtc_slots_v7 { 2488 u8 fver; 2489 u8 slot_cnt; 2490 u8 rsvd0; 2491 u8 rsvd1; 2492 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2493 __le32 update_map; 2494 } __packed; 2495 2496 union rtw89_btc_fbtc_slots_info { 2497 struct rtw89_btc_fbtc_slots v1; 2498 struct rtw89_btc_fbtc_slots_v7 v7; 2499 } __packed; 2500 2501 struct rtw89_btc_fbtc_step { 2502 u8 type; 2503 u8 val; 2504 __le16 difft; 2505 } __packed; 2506 2507 struct rtw89_btc_fbtc_steps_v2 { 2508 u8 fver; /* btc_ver::fcxstep */ 2509 u8 rsvd; 2510 __le16 cnt; 2511 __le16 pos_old; 2512 __le16 pos_new; 2513 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2514 } __packed; 2515 2516 struct rtw89_btc_fbtc_steps_v3 { 2517 u8 fver; 2518 u8 en; 2519 __le16 rsvd; 2520 __le32 cnt; 2521 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2522 } __packed; 2523 2524 union rtw89_btc_fbtc_steps_info { 2525 struct rtw89_btc_fbtc_steps_v2 v2; 2526 struct rtw89_btc_fbtc_steps_v3 v3; 2527 }; 2528 2529 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2530 u8 fver; /* btc_ver::fcxcysta */ 2531 u8 rsvd; 2532 __le16 cycles; /* total cycle number */ 2533 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2534 __le16 a2dpept; /* a2dp empty cnt */ 2535 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2536 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2537 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2538 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2539 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2540 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2541 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2542 __le16 tmax_a2dpept; /* max a2dp empty time */ 2543 __le16 tavg_lk; /* avg leak-slot time */ 2544 __le16 tmax_lk; /* max leak-slot time */ 2545 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2546 __le32 bcn_cnt[CXBCN_MAX]; 2547 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2548 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2549 __le32 skip_cnt; 2550 __le32 exception; 2551 __le32 except_cnt; 2552 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2553 } __packed; 2554 2555 struct rtw89_btc_fbtc_fdd_try_info { 2556 __le16 cycles[CXT_FLCTRL_MAX]; 2557 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2558 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2559 } __packed; 2560 2561 struct rtw89_btc_fbtc_cycle_time_info { 2562 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2563 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2564 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2565 } __packed; 2566 2567 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2568 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2569 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2570 } __packed; 2571 2572 struct rtw89_btc_fbtc_a2dp_trx_stat { 2573 u8 empty_cnt; 2574 u8 retry_cnt; 2575 u8 tx_rate; 2576 u8 tx_cnt; 2577 u8 ack_cnt; 2578 u8 nack_cnt; 2579 u8 rsvd1; 2580 u8 rsvd2; 2581 } __packed; 2582 2583 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2584 u8 empty_cnt; 2585 u8 retry_cnt; 2586 u8 tx_rate; 2587 u8 tx_cnt; 2588 u8 ack_cnt; 2589 u8 nack_cnt; 2590 u8 no_empty_cnt; 2591 u8 rsvd; 2592 } __packed; 2593 2594 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2595 __le16 cnt; /* a2dp empty cnt */ 2596 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2597 __le16 tavg; /* avg a2dp empty time */ 2598 __le16 tmax; /* max a2dp empty time */ 2599 } __packed; 2600 2601 struct rtw89_btc_fbtc_cycle_leak_info { 2602 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2603 __le16 tavg; /* avg leak-slot time */ 2604 __le16 tmax; /* max leak-slot time */ 2605 } __packed; 2606 2607 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2608 __le16 tavg; 2609 __le16 tamx; 2610 __le32 cnt_rximr; 2611 } __packed; 2612 2613 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2614 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2615 2616 struct rtw89_btc_fbtc_cycle_fddt_info { 2617 __le16 train_cycle; 2618 __le16 tp; 2619 2620 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2621 s8 bt_tx_power; /* decrease Tx power (dB) */ 2622 s8 bt_rx_gain; /* LNA constrain level */ 2623 u8 no_empty_cnt; 2624 2625 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2626 u8 cn; /* condition_num */ 2627 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2628 u8 train_result; /* refer to enum btc_fddt_check_map */ 2629 } __packed; 2630 2631 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2632 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2633 2634 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2635 __le16 train_cycle; 2636 __le16 tp; 2637 2638 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2639 s8 bt_tx_power; /* decrease Tx power (dB) */ 2640 s8 bt_rx_gain; /* LNA constrain level */ 2641 u8 no_empty_cnt; 2642 2643 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2644 u8 cn; /* condition_num */ 2645 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2646 u8 train_result; /* refer to enum btc_fddt_check_map */ 2647 } __packed; 2648 2649 struct rtw89_btc_fbtc_fddt_cell_status { 2650 s8 wl_tx_pwr; 2651 s8 bt_tx_pwr; 2652 s8 bt_rx_gain; 2653 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2654 } __packed; 2655 2656 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2657 u8 fver; 2658 u8 rsvd; 2659 __le16 cycles; /* total cycle number */ 2660 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2661 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2662 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2663 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2664 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2665 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2666 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2667 __le32 bcn_cnt[CXBCN_MAX]; 2668 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2669 __le32 skip_cnt; 2670 __le32 except_cnt; 2671 __le32 except_map; 2672 } __packed; 2673 2674 #define FDD_TRAIN_WL_DIRECTION 2 2675 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2676 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2677 2678 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2679 u8 fver; 2680 u8 rsvd; 2681 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2682 u8 except_cnt; 2683 2684 __le16 skip_cnt; 2685 __le16 cycles; /* total cycle number */ 2686 2687 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2688 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2689 __le16 bcn_cnt[CXBCN_MAX]; 2690 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2691 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2692 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2693 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2694 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2695 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2696 [FDD_TRAIN_WL_RSSI_LEVEL] 2697 [FDD_TRAIN_BT_RSSI_LEVEL]; 2698 __le32 except_map; 2699 } __packed; 2700 2701 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2702 u8 fver; 2703 u8 rsvd; 2704 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2705 u8 except_cnt; 2706 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2707 2708 __le16 skip_cnt; 2709 __le16 cycles; /* total cycle number */ 2710 2711 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2712 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2713 __le16 bcn_cnt[CXBCN_MAX]; 2714 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2715 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2716 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2717 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2718 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2719 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2720 [FDD_TRAIN_WL_RSSI_LEVEL] 2721 [FDD_TRAIN_BT_RSSI_LEVEL]; 2722 __le32 except_map; 2723 } __packed; 2724 2725 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2726 u8 fver; 2727 u8 rsvd; 2728 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2729 u8 except_cnt; 2730 2731 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2732 2733 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2734 2735 __le16 skip_cnt; 2736 __le16 cycles; /* total cycle number */ 2737 2738 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2739 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2740 __le16 bcn_cnt[CXBCN_MAX]; 2741 2742 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2743 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2744 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2745 2746 __le32 except_map; 2747 } __packed; 2748 2749 union rtw89_btc_fbtc_cysta_info { 2750 struct rtw89_btc_fbtc_cysta_v2 v2; 2751 struct rtw89_btc_fbtc_cysta_v3 v3; 2752 struct rtw89_btc_fbtc_cysta_v4 v4; 2753 struct rtw89_btc_fbtc_cysta_v5 v5; 2754 struct rtw89_btc_fbtc_cysta_v7 v7; 2755 }; 2756 2757 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2758 u8 fver; /* btc_ver::fcxnullsta */ 2759 u8 rsvd; 2760 __le16 rsvd2; 2761 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2762 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2763 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2764 } __packed; 2765 2766 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2767 u8 fver; /* btc_ver::fcxnullsta */ 2768 u8 rsvd; 2769 __le16 rsvd2; 2770 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2771 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2772 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2773 } __packed; 2774 2775 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2776 u8 fver; 2777 u8 rsvd0; 2778 u8 rsvd1; 2779 u8 rsvd2; 2780 2781 __le32 tmax[2]; 2782 __le32 tavg[2]; 2783 __le32 result[2][5]; 2784 } __packed; 2785 2786 union rtw89_btc_fbtc_cynullsta_info { 2787 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2788 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2789 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2790 }; 2791 2792 struct rtw89_btc_fbtc_btver_v1 { 2793 u8 fver; /* btc_ver::fcxbtver */ 2794 u8 rsvd; 2795 __le16 rsvd2; 2796 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2797 __le32 fw_ver; 2798 __le32 feature; 2799 } __packed; 2800 2801 struct rtw89_btc_fbtc_btver_v7 { 2802 u8 fver; 2803 u8 rsvd0; 2804 u8 rsvd1; 2805 u8 rsvd2; 2806 2807 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2808 __le32 fw_ver; 2809 __le32 feature; 2810 } __packed; 2811 2812 union rtw89_btc_fbtc_btver { 2813 struct rtw89_btc_fbtc_btver_v1 v1; 2814 struct rtw89_btc_fbtc_btver_v7 v7; 2815 } __packed; 2816 2817 struct rtw89_btc_fbtc_btafh { 2818 u8 fver; /* btc_ver::fcxbtafh */ 2819 u8 rsvd; 2820 __le16 rsvd2; 2821 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2822 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2823 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2824 } __packed; 2825 2826 struct rtw89_btc_fbtc_btafh_v2 { 2827 u8 fver; /* btc_ver::fcxbtafh */ 2828 u8 rsvd; 2829 u8 rsvd2; 2830 u8 map_type; 2831 u8 afh_l[4]; 2832 u8 afh_m[4]; 2833 u8 afh_h[4]; 2834 u8 afh_le_a[4]; 2835 u8 afh_le_b[4]; 2836 } __packed; 2837 2838 struct rtw89_btc_fbtc_btafh_v7 { 2839 u8 fver; 2840 u8 map_type; 2841 u8 rsvd0; 2842 u8 rsvd1; 2843 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2844 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2845 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2846 u8 afh_le_a[4]; 2847 u8 afh_le_b[4]; 2848 } __packed; 2849 2850 struct rtw89_btc_fbtc_btdevinfo { 2851 u8 fver; /* btc_ver::fcxbtdevinfo */ 2852 u8 rsvd; 2853 __le16 vendor_id; 2854 __le32 dev_name; /* only 24 bits valid */ 2855 __le32 flush_time; 2856 } __packed; 2857 2858 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2859 struct rtw89_btc_rf_trx_para { 2860 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2861 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2862 u8 bt_tx_power; /* decrease Tx power (dB) */ 2863 u8 bt_rx_gain; /* LNA constrain level */ 2864 }; 2865 2866 struct rtw89_btc_trx_info { 2867 u8 tx_lvl; 2868 u8 rx_lvl; 2869 u8 wl_rssi; 2870 u8 bt_rssi; 2871 2872 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2873 s8 rx_gain; /* rx gain table index (TBD.) */ 2874 s8 bt_tx_power; /* decrease Tx power (dB) */ 2875 s8 bt_rx_gain; /* LNA constrain level */ 2876 2877 u8 cn; /* condition_num */ 2878 s8 nhm; 2879 u8 bt_profile; 2880 u8 rsvd2; 2881 2882 u16 tx_rate; 2883 u16 rx_rate; 2884 2885 u32 tx_tp; 2886 u32 rx_tp; 2887 u32 rx_err_ratio; 2888 }; 2889 2890 union rtw89_btc_fbtc_slot_u { 2891 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2892 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2893 }; 2894 2895 struct rtw89_btc_dm { 2896 union rtw89_btc_fbtc_slot_u slot; 2897 union rtw89_btc_fbtc_slot_u slot_now; 2898 struct rtw89_btc_fbtc_tdma tdma; 2899 struct rtw89_btc_fbtc_tdma tdma_now; 2900 struct rtw89_mac_ax_coex_gnt gnt; 2901 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2902 struct rtw89_btc_rf_trx_para rf_trx_para; 2903 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2904 struct rtw89_btc_dm_step dm_step; 2905 struct rtw89_btc_wl_scc_ctrl wl_scc; 2906 struct rtw89_btc_trx_info trx_info; 2907 union rtw89_btc_dm_error_map error; 2908 u32 cnt_dm[BTC_DCNT_NUM]; 2909 u32 cnt_notify[BTC_NCNT_NUM]; 2910 2911 u32 update_slot_map; 2912 u32 set_ant_path; 2913 u32 e2g_slot_limit; 2914 u32 e2g_slot_nulltx_time; 2915 2916 u32 wl_only: 1; 2917 u32 wl_fw_cx_offload: 1; 2918 u32 freerun: 1; 2919 u32 fddt_train: 1; 2920 u32 wl_ps_ctrl: 2; 2921 u32 wl_mimo_ps: 1; 2922 u32 leak_ap: 1; 2923 u32 noisy_level: 3; 2924 u32 coex_info_map: 8; 2925 u32 bt_only: 1; 2926 u32 wl_btg_rx: 2; 2927 u32 trx_para_level: 8; 2928 u32 wl_stb_chg: 1; 2929 u32 pta_owner: 1; 2930 2931 u32 tdma_instant_excute: 1; 2932 u32 wl_btg_rx_rb: 2; 2933 2934 u16 slot_dur[CXST_MAX]; 2935 u16 bt_slot_flood; 2936 2937 u8 run_reason; 2938 u8 run_action; 2939 2940 u8 wl_pre_agc: 2; 2941 u8 wl_lna2: 1; 2942 u8 freerun_chk: 1; 2943 u8 wl_pre_agc_rb: 2; 2944 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2945 u8 slot_req_more: 1; 2946 }; 2947 2948 struct rtw89_btc_ctrl { 2949 u32 manual: 1; 2950 u32 igno_bt: 1; 2951 u32 always_freerun: 1; 2952 u32 trace_step: 16; 2953 u32 rsvd: 12; 2954 }; 2955 2956 struct rtw89_btc_ctrl_v7 { 2957 u8 manual; 2958 u8 igno_bt; 2959 u8 always_freerun; 2960 u8 rsvd; 2961 } __packed; 2962 2963 union rtw89_btc_ctrl_list { 2964 struct rtw89_btc_ctrl ctrl; 2965 struct rtw89_btc_ctrl_v7 ctrl_v7; 2966 }; 2967 2968 struct rtw89_btc_dbg { 2969 /* cmd "rb" */ 2970 bool rb_done; 2971 u32 rb_val; 2972 }; 2973 2974 enum rtw89_btc_btf_fw_event { 2975 BTF_EVNT_RPT = 0, 2976 BTF_EVNT_BT_INFO = 1, 2977 BTF_EVNT_BT_SCBD = 2, 2978 BTF_EVNT_BT_REG = 3, 2979 BTF_EVNT_CX_RUNINFO = 4, 2980 BTF_EVNT_BT_PSD = 5, 2981 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 2982 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 2983 BTF_EVNT_BUF_OVERFLOW, 2984 BTF_EVNT_C2H_LOOPBACK, 2985 BTF_EVNT_MAX, 2986 }; 2987 2988 enum btf_fw_event_report { 2989 BTC_RPT_TYPE_CTRL = 0x0, 2990 BTC_RPT_TYPE_TDMA, 2991 BTC_RPT_TYPE_SLOT, 2992 BTC_RPT_TYPE_CYSTA, 2993 BTC_RPT_TYPE_STEP, 2994 BTC_RPT_TYPE_NULLSTA, 2995 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 2996 BTC_RPT_TYPE_MREG, 2997 BTC_RPT_TYPE_GPIO_DBG, 2998 BTC_RPT_TYPE_BT_VER, 2999 BTC_RPT_TYPE_BT_SCAN, 3000 BTC_RPT_TYPE_BT_AFH, 3001 BTC_RPT_TYPE_BT_DEVICE, 3002 BTC_RPT_TYPE_TEST, 3003 BTC_RPT_TYPE_MAX = 31, 3004 3005 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3006 __BTC_RPT_TYPE_V0_MAX = 12, 3007 }; 3008 3009 enum rtw_btc_btf_reg_type { 3010 REG_MAC = 0x0, 3011 REG_BB = 0x1, 3012 REG_RF = 0x2, 3013 REG_BT_RF = 0x3, 3014 REG_BT_MODEM = 0x4, 3015 REG_BT_BLUEWIZE = 0x5, 3016 REG_BT_VENDOR = 0x6, 3017 REG_BT_LE = 0x7, 3018 REG_MAX_TYPE, 3019 }; 3020 3021 struct rtw89_btc_rpt_cmn_info { 3022 u32 rx_cnt; 3023 u32 rx_len; 3024 u32 req_len; /* expected rsp len */ 3025 u8 req_fver; /* expected rsp fver */ 3026 u8 rsp_fver; /* fver from fw */ 3027 u8 valid; 3028 } __packed; 3029 3030 union rtw89_btc_fbtc_btafh_info { 3031 struct rtw89_btc_fbtc_btafh v1; 3032 struct rtw89_btc_fbtc_btafh_v2 v2; 3033 }; 3034 3035 struct rtw89_btc_report_ctrl_state { 3036 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3037 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3038 }; 3039 3040 struct rtw89_btc_rpt_fbtc_tdma { 3041 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3042 union rtw89_btc_fbtc_tdma_le32 finfo; 3043 }; 3044 3045 struct rtw89_btc_rpt_fbtc_slots { 3046 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3047 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3048 }; 3049 3050 struct rtw89_btc_rpt_fbtc_cysta { 3051 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3052 union rtw89_btc_fbtc_cysta_info finfo; 3053 }; 3054 3055 struct rtw89_btc_rpt_fbtc_step { 3056 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3057 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3058 }; 3059 3060 struct rtw89_btc_rpt_fbtc_nullsta { 3061 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3062 union rtw89_btc_fbtc_cynullsta_info finfo; 3063 }; 3064 3065 struct rtw89_btc_rpt_fbtc_mreg { 3066 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3067 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3068 }; 3069 3070 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3071 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3072 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3073 }; 3074 3075 struct rtw89_btc_rpt_fbtc_btver { 3076 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3077 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3078 }; 3079 3080 struct rtw89_btc_rpt_fbtc_btscan { 3081 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3082 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3083 }; 3084 3085 struct rtw89_btc_rpt_fbtc_btafh { 3086 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3087 union rtw89_btc_fbtc_btafh_info finfo; 3088 }; 3089 3090 struct rtw89_btc_rpt_fbtc_btdev { 3091 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3092 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3093 }; 3094 3095 enum rtw89_btc_btfre_type { 3096 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3097 BTFRE_UNDEF_TYPE, 3098 BTFRE_EXCEPTION, 3099 BTFRE_MAX, 3100 }; 3101 3102 struct rtw89_btc_btf_fwinfo { 3103 u32 cnt_c2h; 3104 u32 cnt_h2c; 3105 u32 cnt_h2c_fail; 3106 u32 event[BTF_EVNT_MAX]; 3107 3108 u32 err[BTFRE_MAX]; 3109 u32 len_mismch; 3110 u32 fver_mismch; 3111 u32 rpt_en_map; 3112 3113 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3114 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3115 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3116 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3117 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3118 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3119 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3120 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3121 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3122 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3123 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3124 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3125 }; 3126 3127 struct rtw89_btc_ver { 3128 enum rtw89_core_chip_id chip_id; 3129 u32 fw_ver_code; 3130 3131 u8 fcxbtcrpt; 3132 u8 fcxtdma; 3133 u8 fcxslots; 3134 u8 fcxcysta; 3135 u8 fcxstep; 3136 u8 fcxnullsta; 3137 u8 fcxmreg; 3138 u8 fcxgpiodbg; 3139 u8 fcxbtver; 3140 u8 fcxbtscan; 3141 u8 fcxbtafh; 3142 u8 fcxbtdevinfo; 3143 u8 fwlrole; 3144 u8 frptmap; 3145 u8 fcxctrl; 3146 u8 fcxinit; 3147 3148 u8 fwevntrptl; 3149 u8 fwc2hfunc; 3150 u8 drvinfo_type; 3151 u16 info_buf; 3152 u8 max_role_num; 3153 }; 3154 3155 #define RTW89_BTC_POLICY_MAXLEN 512 3156 3157 struct rtw89_btc { 3158 const struct rtw89_btc_ver *ver; 3159 3160 struct rtw89_btc_cx cx; 3161 struct rtw89_btc_dm dm; 3162 union rtw89_btc_ctrl_list ctrl; 3163 union rtw89_btc_module_info mdinfo; 3164 struct rtw89_btc_btf_fwinfo fwinfo; 3165 struct rtw89_btc_dbg dbg; 3166 3167 struct work_struct eapol_notify_work; 3168 struct work_struct arp_notify_work; 3169 struct work_struct dhcp_notify_work; 3170 struct work_struct icmp_notify_work; 3171 3172 u32 bt_req_len; 3173 3174 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3175 u8 ant_type; 3176 u8 btg_pos; 3177 u16 policy_len; 3178 u16 policy_type; 3179 u32 hubmsg_cnt; 3180 bool bt_req_en; 3181 bool update_policy_force; 3182 bool lps; 3183 bool manual_ctrl; 3184 }; 3185 3186 enum rtw89_btc_hmsg { 3187 RTW89_BTC_HMSG_TMR_EN = 0x0, 3188 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3189 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3190 RTW89_BTC_HMSG_FW_EV = 0x3, 3191 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3192 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3193 3194 NUM_OF_RTW89_BTC_HMSG, 3195 }; 3196 3197 enum rtw89_ra_mode { 3198 RTW89_RA_MODE_CCK = BIT(0), 3199 RTW89_RA_MODE_OFDM = BIT(1), 3200 RTW89_RA_MODE_HT = BIT(2), 3201 RTW89_RA_MODE_VHT = BIT(3), 3202 RTW89_RA_MODE_HE = BIT(4), 3203 RTW89_RA_MODE_EHT = BIT(5), 3204 }; 3205 3206 enum rtw89_ra_report_mode { 3207 RTW89_RA_RPT_MODE_LEGACY, 3208 RTW89_RA_RPT_MODE_HT, 3209 RTW89_RA_RPT_MODE_VHT, 3210 RTW89_RA_RPT_MODE_HE, 3211 RTW89_RA_RPT_MODE_EHT, 3212 }; 3213 3214 enum rtw89_dig_noisy_level { 3215 RTW89_DIG_NOISY_LEVEL0 = -1, 3216 RTW89_DIG_NOISY_LEVEL1 = 0, 3217 RTW89_DIG_NOISY_LEVEL2 = 1, 3218 RTW89_DIG_NOISY_LEVEL3 = 2, 3219 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3220 }; 3221 3222 enum rtw89_gi_ltf { 3223 RTW89_GILTF_LGI_4XHE32 = 0, 3224 RTW89_GILTF_SGI_4XHE08 = 1, 3225 RTW89_GILTF_2XHE16 = 2, 3226 RTW89_GILTF_2XHE08 = 3, 3227 RTW89_GILTF_1XHE16 = 4, 3228 RTW89_GILTF_1XHE08 = 5, 3229 RTW89_GILTF_MAX 3230 }; 3231 3232 enum rtw89_rx_frame_type { 3233 RTW89_RX_TYPE_MGNT = 0, 3234 RTW89_RX_TYPE_CTRL = 1, 3235 RTW89_RX_TYPE_DATA = 2, 3236 RTW89_RX_TYPE_RSVD = 3, 3237 }; 3238 3239 enum rtw89_efuse_block { 3240 RTW89_EFUSE_BLOCK_SYS = 0, 3241 RTW89_EFUSE_BLOCK_RF = 1, 3242 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3243 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3244 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3245 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3246 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3247 RTW89_EFUSE_BLOCK_ADIE = 7, 3248 3249 RTW89_EFUSE_BLOCK_NUM, 3250 RTW89_EFUSE_BLOCK_IGNORE, 3251 }; 3252 3253 struct rtw89_ra_info { 3254 u8 is_dis_ra:1; 3255 /* Bit0 : CCK 3256 * Bit1 : OFDM 3257 * Bit2 : HT 3258 * Bit3 : VHT 3259 * Bit4 : HE 3260 * Bit5 : EHT 3261 */ 3262 u8 mode_ctrl:6; 3263 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3264 u8 macid; 3265 u8 dcm_cap:1; 3266 u8 er_cap:1; 3267 u8 init_rate_lv:2; 3268 u8 upd_all:1; 3269 u8 en_sgi:1; 3270 u8 ldpc_cap:1; 3271 u8 stbc_cap:1; 3272 u8 ss_num:3; 3273 u8 giltf:3; 3274 u8 upd_bw_nss_mask:1; 3275 u8 upd_mask:1; 3276 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3277 /* BFee CSI */ 3278 u8 band_num; 3279 u8 ra_csi_rate_en:1; 3280 u8 fixed_csi_rate_en:1; 3281 u8 cr_tbl_sel:1; 3282 u8 fix_giltf_en:1; 3283 u8 fix_giltf:3; 3284 u8 rsvd2:1; 3285 u8 csi_mcs_ss_idx; 3286 u8 csi_mode:2; 3287 u8 csi_gi_ltf:3; 3288 u8 csi_bw:3; 3289 }; 3290 3291 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3292 #define RTW89_PPDU_MAC_INFO_SIZE 8 3293 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3294 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3295 3296 #define RTW89_MAX_RX_AGG_NUM 64 3297 #define RTW89_MAX_TX_AGG_NUM 128 3298 3299 struct rtw89_ampdu_params { 3300 u16 agg_num; 3301 bool amsdu; 3302 }; 3303 3304 struct rtw89_ra_report { 3305 struct rate_info txrate; 3306 u32 bit_rate; 3307 u16 hw_rate; 3308 bool might_fallback_legacy; 3309 }; 3310 3311 DECLARE_EWMA(rssi, 10, 16); 3312 DECLARE_EWMA(evm, 10, 16); 3313 DECLARE_EWMA(snr, 10, 16); 3314 3315 struct rtw89_ba_cam_entry { 3316 struct list_head list; 3317 u8 tid; 3318 }; 3319 3320 #define RTW89_MAX_ADDR_CAM_NUM 128 3321 #define RTW89_MAX_BSSID_CAM_NUM 20 3322 #define RTW89_MAX_SEC_CAM_NUM 128 3323 #define RTW89_MAX_BA_CAM_NUM 24 3324 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3325 3326 struct rtw89_addr_cam_entry { 3327 u8 addr_cam_idx; 3328 u8 offset; 3329 u8 len; 3330 u8 valid : 1; 3331 u8 addr_mask : 6; 3332 u8 wapi : 1; 3333 u8 mask_sel : 2; 3334 u8 bssid_cam_idx: 6; 3335 3336 u8 sec_ent_mode; 3337 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3338 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3339 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3340 }; 3341 3342 struct rtw89_bssid_cam_entry { 3343 u8 bssid[ETH_ALEN]; 3344 u8 phy_idx; 3345 u8 bssid_cam_idx; 3346 u8 offset; 3347 u8 len; 3348 u8 valid : 1; 3349 u8 num; 3350 }; 3351 3352 struct rtw89_sec_cam_entry { 3353 u8 sec_cam_idx; 3354 u8 offset; 3355 u8 len; 3356 u8 type : 4; 3357 u8 ext_key : 1; 3358 u8 spp_mode : 1; 3359 /* 256 bits */ 3360 u8 key[32]; 3361 }; 3362 3363 struct rtw89_sta_link { 3364 struct rtw89_sta *rtwsta; 3365 unsigned int link_id; 3366 3367 u8 mac_id; 3368 bool er_cap; 3369 struct rtw89_vif_link *rtwvif_link; 3370 struct rtw89_ra_info ra; 3371 struct rtw89_ra_report ra_report; 3372 int max_agg_wait; 3373 u8 prev_rssi; 3374 struct ewma_rssi avg_rssi; 3375 struct ewma_rssi rssi[RF_PATH_MAX]; 3376 struct ewma_snr avg_snr; 3377 struct ewma_evm evm_1ss; 3378 struct ewma_evm evm_min[RF_PATH_MAX]; 3379 struct ewma_evm evm_max[RF_PATH_MAX]; 3380 struct ieee80211_rx_status rx_status; 3381 u16 rx_hw_rate; 3382 __le32 htc_template; 3383 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3384 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3385 struct list_head ba_cam_list; 3386 3387 bool use_cfg_mask; 3388 struct cfg80211_bitrate_mask mask; 3389 3390 bool cctl_tx_time; 3391 u32 ampdu_max_time:4; 3392 bool cctl_tx_retry_limit; 3393 u32 data_tx_cnt_lmt:6; 3394 }; 3395 3396 struct rtw89_efuse { 3397 bool valid; 3398 bool power_k_valid; 3399 u8 xtal_cap; 3400 u8 addr[ETH_ALEN]; 3401 u8 rfe_type; 3402 char country_code[2]; 3403 }; 3404 3405 struct rtw89_phy_rate_pattern { 3406 u64 ra_mask; 3407 u16 rate; 3408 u8 ra_mode; 3409 bool enable; 3410 }; 3411 3412 struct rtw89_tx_wait_info { 3413 struct rcu_head rcu_head; 3414 struct completion completion; 3415 bool tx_done; 3416 }; 3417 3418 struct rtw89_tx_skb_data { 3419 struct rtw89_tx_wait_info __rcu *wait; 3420 u8 hci_priv[]; 3421 }; 3422 3423 #define RTW89_ROC_IDLE_TIMEOUT 500 3424 #define RTW89_ROC_TX_TIMEOUT 30 3425 enum rtw89_roc_state { 3426 RTW89_ROC_IDLE, 3427 RTW89_ROC_NORMAL, 3428 RTW89_ROC_MGMT, 3429 }; 3430 3431 #define RTW89_ROC_BY_LINK_INDEX 0 3432 3433 struct rtw89_roc { 3434 struct ieee80211_channel chan; 3435 struct delayed_work roc_work; 3436 enum ieee80211_roc_type type; 3437 enum rtw89_roc_state state; 3438 int duration; 3439 }; 3440 3441 #define RTW89_P2P_MAX_NOA_NUM 2 3442 3443 struct rtw89_p2p_ie_head { 3444 u8 eid; 3445 u8 ie_len; 3446 u8 oui[3]; 3447 u8 oui_type; 3448 } __packed; 3449 3450 struct rtw89_noa_attr_head { 3451 u8 attr_type; 3452 __le16 attr_len; 3453 u8 index; 3454 u8 oppps_ctwindow; 3455 } __packed; 3456 3457 struct rtw89_p2p_noa_ie { 3458 struct rtw89_p2p_ie_head p2p_head; 3459 struct rtw89_noa_attr_head noa_head; 3460 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3461 } __packed; 3462 3463 struct rtw89_p2p_noa_setter { 3464 struct rtw89_p2p_noa_ie ie; 3465 u8 noa_count; 3466 u8 noa_index; 3467 }; 3468 3469 struct rtw89_vif_link { 3470 struct rtw89_vif *rtwvif; 3471 unsigned int link_id; 3472 3473 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3474 enum rtw89_chanctx_idx chanctx_idx; 3475 enum rtw89_reg_6ghz_power reg_6ghz_power; 3476 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3477 3478 u8 mac_id; 3479 u8 port; 3480 u8 mac_addr[ETH_ALEN]; 3481 u8 bssid[ETH_ALEN]; 3482 u8 phy_idx; 3483 u8 mac_idx; 3484 u8 net_type; 3485 u8 wifi_role; 3486 u8 self_role; 3487 u8 wmm; 3488 u8 bcn_hit_cond; 3489 u8 hit_rule; 3490 u8 last_noa_nr; 3491 u64 sync_bcn_tsf; 3492 bool trigger; 3493 bool lsig_txop; 3494 u8 tgt_ind; 3495 u8 frm_tgt_ind; 3496 bool wowlan_pattern; 3497 bool wowlan_uc; 3498 bool wowlan_magic; 3499 bool is_hesta; 3500 bool last_a_ctrl; 3501 bool dyn_tb_bedge_en; 3502 bool pre_pwr_diff_en; 3503 bool pwr_diff_en; 3504 u8 def_tri_idx; 3505 struct work_struct update_beacon_work; 3506 struct rtw89_addr_cam_entry addr_cam; 3507 struct rtw89_bssid_cam_entry bssid_cam; 3508 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3509 struct rtw89_phy_rate_pattern rate_pattern; 3510 struct list_head general_pkt_list; 3511 struct rtw89_p2p_noa_setter p2p_noa; 3512 }; 3513 3514 enum rtw89_lv1_rcvy_step { 3515 RTW89_LV1_RCVY_STEP_1, 3516 RTW89_LV1_RCVY_STEP_2, 3517 }; 3518 3519 struct rtw89_hci_ops { 3520 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3521 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3522 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3523 void (*reset)(struct rtw89_dev *rtwdev); 3524 int (*start)(struct rtw89_dev *rtwdev); 3525 void (*stop)(struct rtw89_dev *rtwdev); 3526 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3527 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3528 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3529 3530 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3531 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3532 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3533 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3534 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3535 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3536 3537 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3538 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3539 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3540 int (*deinit)(struct rtw89_dev *rtwdev); 3541 3542 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3543 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3544 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3545 int (*napi_poll)(struct napi_struct *napi, int budget); 3546 3547 /* Deal with locks inside recovery_start and recovery_complete callbacks 3548 * by hci instance, and handle things which need to consider under SER. 3549 * e.g. turn on/off interrupts except for the one for halt notification. 3550 */ 3551 void (*recovery_start)(struct rtw89_dev *rtwdev); 3552 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3553 3554 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3555 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3556 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3557 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3558 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3559 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3560 void (*disable_intr)(struct rtw89_dev *rtwdev); 3561 void (*enable_intr)(struct rtw89_dev *rtwdev); 3562 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3563 }; 3564 3565 struct rtw89_hci_info { 3566 const struct rtw89_hci_ops *ops; 3567 enum rtw89_hci_type type; 3568 u32 rpwm_addr; 3569 u32 cpwm_addr; 3570 bool paused; 3571 }; 3572 3573 struct rtw89_chip_ops { 3574 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3575 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3576 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3577 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3578 void (*bb_reset)(struct rtw89_dev *rtwdev, 3579 enum rtw89_phy_idx phy_idx); 3580 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3581 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3582 u32 addr, u32 mask); 3583 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3584 u32 addr, u32 mask, u32 data); 3585 void (*set_channel)(struct rtw89_dev *rtwdev, 3586 const struct rtw89_chan *chan, 3587 enum rtw89_mac_idx mac_idx, 3588 enum rtw89_phy_idx phy_idx); 3589 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3590 struct rtw89_channel_help_params *p, 3591 const struct rtw89_chan *chan, 3592 enum rtw89_mac_idx mac_idx, 3593 enum rtw89_phy_idx phy_idx); 3594 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3595 enum rtw89_efuse_block block); 3596 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3597 void (*fem_setup)(struct rtw89_dev *rtwdev); 3598 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3599 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3600 void (*rfk_init)(struct rtw89_dev *rtwdev); 3601 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3602 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3603 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3604 enum rtw89_phy_idx phy_idx, 3605 const struct rtw89_chan *chan); 3606 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3607 bool start); 3608 void (*rfk_track)(struct rtw89_dev *rtwdev); 3609 void (*power_trim)(struct rtw89_dev *rtwdev); 3610 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3611 const struct rtw89_chan *chan, 3612 enum rtw89_phy_idx phy_idx); 3613 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3614 enum rtw89_phy_idx phy_idx); 3615 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3616 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3617 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3618 enum rtw89_phy_idx phy_idx); 3619 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3620 struct rtw89_rx_phy_ppdu *phy_ppdu, 3621 struct ieee80211_rx_status *status); 3622 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3623 struct rtw89_rx_phy_ppdu *phy_ppdu); 3624 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3625 enum rtw89_phy_idx phy_idx); 3626 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3627 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3628 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3629 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3630 enum rtw89_phy_idx phy_idx); 3631 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3632 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3633 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3634 struct rtw89_rx_desc_info *desc_info, 3635 u8 *data, u32 data_offset); 3636 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3637 struct rtw89_tx_desc_info *desc_info, 3638 void *txdesc); 3639 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3640 struct rtw89_tx_desc_info *desc_info, 3641 void *txdesc); 3642 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3643 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3644 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3645 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3646 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3647 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3648 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3649 struct rtw89_vif_link *rtwvif_link, 3650 struct rtw89_sta_link *rtwsta_link); 3651 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3652 struct rtw89_vif_link *rtwvif_link, 3653 struct rtw89_sta_link *rtwsta_link); 3654 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3655 struct rtw89_vif_link *rtwvif_link, 3656 struct rtw89_sta_link *rtwsta_link); 3657 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3658 struct rtw89_vif_link *rtwvif_link, 3659 struct rtw89_sta_link *rtwsta_link); 3660 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3661 struct rtw89_vif_link *rtwvif_link, 3662 struct rtw89_sta_link *rtwsta_link); 3663 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3664 struct rtw89_vif_link *rtwvif_link); 3665 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3666 struct rtw89_vif_link *rtwvif_link, 3667 struct rtw89_sta_link *rtwsta_link, 3668 bool valid, struct ieee80211_ampdu_params *params); 3669 3670 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3671 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3672 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3673 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3674 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3675 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3676 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3677 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3678 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3679 }; 3680 3681 enum rtw89_dma_ch { 3682 RTW89_DMA_ACH0 = 0, 3683 RTW89_DMA_ACH1 = 1, 3684 RTW89_DMA_ACH2 = 2, 3685 RTW89_DMA_ACH3 = 3, 3686 RTW89_DMA_ACH4 = 4, 3687 RTW89_DMA_ACH5 = 5, 3688 RTW89_DMA_ACH6 = 6, 3689 RTW89_DMA_ACH7 = 7, 3690 RTW89_DMA_B0MG = 8, 3691 RTW89_DMA_B0HI = 9, 3692 RTW89_DMA_B1MG = 10, 3693 RTW89_DMA_B1HI = 11, 3694 RTW89_DMA_H2C = 12, 3695 RTW89_DMA_CH_NUM = 13 3696 }; 3697 3698 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3699 3700 enum rtw89_mlo_dbcc_mode { 3701 MLO_DBCC_NOT_SUPPORT = 1, 3702 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3703 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3704 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3705 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3706 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3707 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3708 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3709 DBCC_LEGACY = 0xffffffff, 3710 }; 3711 3712 enum rtw89_scan_be_operation { 3713 RTW89_SCAN_OP_STOP, 3714 RTW89_SCAN_OP_START, 3715 RTW89_SCAN_OP_SETPARM, 3716 RTW89_SCAN_OP_GETRPT, 3717 RTW89_SCAN_OP_NUM 3718 }; 3719 3720 enum rtw89_scan_be_mode { 3721 RTW89_SCAN_MODE_SA, 3722 RTW89_SCAN_MODE_MACC, 3723 RTW89_SCAN_MODE_NUM 3724 }; 3725 3726 enum rtw89_scan_be_opmode { 3727 RTW89_SCAN_OPMODE_NONE, 3728 RTW89_SCAN_OPMODE_TBTT, 3729 RTW89_SCAN_OPMODE_INTV, 3730 RTW89_SCAN_OPMODE_CNT, 3731 RTW89_SCAN_OPMODE_NUM, 3732 }; 3733 3734 struct rtw89_scan_option { 3735 bool enable; 3736 bool target_ch_mode; 3737 u8 num_macc_role; 3738 u8 num_opch; 3739 u8 repeat; 3740 u16 norm_pd; 3741 u16 slow_pd; 3742 u16 norm_cy; 3743 u8 opch_end; 3744 u16 delay; 3745 u64 prohib_chan; 3746 enum rtw89_phy_idx band; 3747 enum rtw89_scan_be_operation operation; 3748 enum rtw89_scan_be_mode scan_mode; 3749 enum rtw89_mlo_dbcc_mode mlo_mode; 3750 }; 3751 3752 enum rtw89_qta_mode { 3753 RTW89_QTA_SCC, 3754 RTW89_QTA_DBCC, 3755 RTW89_QTA_DLFW, 3756 RTW89_QTA_WOW, 3757 3758 /* keep last */ 3759 RTW89_QTA_INVALID, 3760 }; 3761 3762 struct rtw89_hfc_ch_cfg { 3763 u16 min; 3764 u16 max; 3765 #define grp_0 0 3766 #define grp_1 1 3767 #define grp_num 2 3768 u8 grp; 3769 }; 3770 3771 struct rtw89_hfc_ch_info { 3772 u16 aval; 3773 u16 used; 3774 }; 3775 3776 struct rtw89_hfc_pub_cfg { 3777 u16 grp0; 3778 u16 grp1; 3779 u16 pub_max; 3780 u16 wp_thrd; 3781 }; 3782 3783 struct rtw89_hfc_pub_info { 3784 u16 g0_used; 3785 u16 g1_used; 3786 u16 g0_aval; 3787 u16 g1_aval; 3788 u16 pub_aval; 3789 u16 wp_aval; 3790 }; 3791 3792 struct rtw89_hfc_prec_cfg { 3793 u16 ch011_prec; 3794 u16 h2c_prec; 3795 u16 wp_ch07_prec; 3796 u16 wp_ch811_prec; 3797 u8 ch011_full_cond; 3798 u8 h2c_full_cond; 3799 u8 wp_ch07_full_cond; 3800 u8 wp_ch811_full_cond; 3801 }; 3802 3803 struct rtw89_hfc_param { 3804 bool en; 3805 bool h2c_en; 3806 u8 mode; 3807 const struct rtw89_hfc_ch_cfg *ch_cfg; 3808 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3809 struct rtw89_hfc_pub_cfg pub_cfg; 3810 struct rtw89_hfc_pub_info pub_info; 3811 struct rtw89_hfc_prec_cfg prec_cfg; 3812 }; 3813 3814 struct rtw89_hfc_param_ini { 3815 const struct rtw89_hfc_ch_cfg *ch_cfg; 3816 const struct rtw89_hfc_pub_cfg *pub_cfg; 3817 const struct rtw89_hfc_prec_cfg *prec_cfg; 3818 u8 mode; 3819 }; 3820 3821 struct rtw89_dle_size { 3822 u16 pge_size; 3823 u16 lnk_pge_num; 3824 u16 unlnk_pge_num; 3825 /* for WiFi 7 chips below */ 3826 u32 srt_ofst; 3827 }; 3828 3829 struct rtw89_wde_quota { 3830 u16 hif; 3831 u16 wcpu; 3832 u16 pkt_in; 3833 u16 cpu_io; 3834 }; 3835 3836 struct rtw89_ple_quota { 3837 u16 cma0_tx; 3838 u16 cma1_tx; 3839 u16 c2h; 3840 u16 h2c; 3841 u16 wcpu; 3842 u16 mpdu_proc; 3843 u16 cma0_dma; 3844 u16 cma1_dma; 3845 u16 bb_rpt; 3846 u16 wd_rel; 3847 u16 cpu_io; 3848 u16 tx_rpt; 3849 /* for WiFi 7 chips below */ 3850 u16 h2d; 3851 }; 3852 3853 struct rtw89_rsvd_quota { 3854 u16 mpdu_info_tbl; 3855 u16 b0_csi; 3856 u16 b1_csi; 3857 u16 b0_lmr; 3858 u16 b1_lmr; 3859 u16 b0_ftm; 3860 u16 b1_ftm; 3861 u16 b0_smr; 3862 u16 b1_smr; 3863 u16 others; 3864 }; 3865 3866 struct rtw89_dle_rsvd_size { 3867 u32 srt_ofst; 3868 u32 size; 3869 }; 3870 3871 struct rtw89_dle_mem { 3872 enum rtw89_qta_mode mode; 3873 const struct rtw89_dle_size *wde_size; 3874 const struct rtw89_dle_size *ple_size; 3875 const struct rtw89_wde_quota *wde_min_qt; 3876 const struct rtw89_wde_quota *wde_max_qt; 3877 const struct rtw89_ple_quota *ple_min_qt; 3878 const struct rtw89_ple_quota *ple_max_qt; 3879 /* for WiFi 7 chips below */ 3880 const struct rtw89_rsvd_quota *rsvd_qt; 3881 const struct rtw89_dle_rsvd_size *rsvd0_size; 3882 const struct rtw89_dle_rsvd_size *rsvd1_size; 3883 }; 3884 3885 struct rtw89_reg_def { 3886 u32 addr; 3887 u32 mask; 3888 }; 3889 3890 struct rtw89_reg2_def { 3891 u32 addr; 3892 u32 data; 3893 }; 3894 3895 struct rtw89_reg3_def { 3896 u32 addr; 3897 u32 mask; 3898 u32 data; 3899 }; 3900 3901 struct rtw89_reg5_def { 3902 u8 flag; /* recognized by parsers */ 3903 u8 path; 3904 u32 addr; 3905 u32 mask; 3906 u32 data; 3907 }; 3908 3909 struct rtw89_reg_imr { 3910 u32 addr; 3911 u32 clr; 3912 u32 set; 3913 }; 3914 3915 struct rtw89_phy_table { 3916 const struct rtw89_reg2_def *regs; 3917 u32 n_regs; 3918 enum rtw89_rf_path rf_path; 3919 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3920 enum rtw89_rf_path rf_path, void *data); 3921 }; 3922 3923 struct rtw89_txpwr_table { 3924 const void *data; 3925 u32 size; 3926 void (*load)(struct rtw89_dev *rtwdev, 3927 const struct rtw89_txpwr_table *tbl); 3928 }; 3929 3930 struct rtw89_txpwr_rule_2ghz { 3931 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3932 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3933 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3934 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3935 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3936 }; 3937 3938 struct rtw89_txpwr_rule_5ghz { 3939 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3940 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3941 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3942 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3943 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3944 }; 3945 3946 struct rtw89_txpwr_rule_6ghz { 3947 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3948 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3949 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3950 [RTW89_6G_CH_NUM]; 3951 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3952 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3953 [RTW89_6G_CH_NUM]; 3954 }; 3955 3956 struct rtw89_tx_shape { 3957 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3958 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3959 }; 3960 3961 struct rtw89_rfe_parms { 3962 const struct rtw89_txpwr_table *byr_tbl; 3963 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3964 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3965 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3966 struct rtw89_tx_shape tx_shape; 3967 }; 3968 3969 struct rtw89_rfe_parms_conf { 3970 const struct rtw89_rfe_parms *rfe_parms; 3971 u8 rfe_type; 3972 }; 3973 3974 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3975 3976 struct rtw89_txpwr_conf { 3977 u8 rfe_type; 3978 u8 ent_sz; 3979 u32 num_ents; 3980 const void *data; 3981 }; 3982 3983 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 3984 const struct rtw89_txpwr_conf *conf) 3985 { 3986 u8 valid_size = min(size, conf->ent_sz); 3987 3988 memcpy(entry, cursor, valid_size); 3989 return true; 3990 } 3991 3992 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3993 3994 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3995 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 3996 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3997 (cursor) += (conf)->ent_sz) \ 3998 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 3999 4000 struct rtw89_txpwr_byrate_data { 4001 struct rtw89_txpwr_conf conf; 4002 struct rtw89_txpwr_table tbl; 4003 }; 4004 4005 struct rtw89_txpwr_lmt_2ghz_data { 4006 struct rtw89_txpwr_conf conf; 4007 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4008 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4009 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4010 }; 4011 4012 struct rtw89_txpwr_lmt_5ghz_data { 4013 struct rtw89_txpwr_conf conf; 4014 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4015 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4016 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4017 }; 4018 4019 struct rtw89_txpwr_lmt_6ghz_data { 4020 struct rtw89_txpwr_conf conf; 4021 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4022 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4023 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4024 [RTW89_6G_CH_NUM]; 4025 }; 4026 4027 struct rtw89_txpwr_lmt_ru_2ghz_data { 4028 struct rtw89_txpwr_conf conf; 4029 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4030 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4031 }; 4032 4033 struct rtw89_txpwr_lmt_ru_5ghz_data { 4034 struct rtw89_txpwr_conf conf; 4035 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4036 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4037 }; 4038 4039 struct rtw89_txpwr_lmt_ru_6ghz_data { 4040 struct rtw89_txpwr_conf conf; 4041 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4042 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4043 [RTW89_6G_CH_NUM]; 4044 }; 4045 4046 struct rtw89_tx_shape_lmt_data { 4047 struct rtw89_txpwr_conf conf; 4048 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4049 }; 4050 4051 struct rtw89_tx_shape_lmt_ru_data { 4052 struct rtw89_txpwr_conf conf; 4053 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4054 }; 4055 4056 struct rtw89_rfe_data { 4057 struct rtw89_txpwr_byrate_data byrate; 4058 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4059 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4060 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4061 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4062 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4063 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4064 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4065 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4066 struct rtw89_rfe_parms rfe_parms; 4067 }; 4068 4069 struct rtw89_page_regs { 4070 u32 hci_fc_ctrl; 4071 u32 ch_page_ctrl; 4072 u32 ach_page_ctrl; 4073 u32 ach_page_info; 4074 u32 pub_page_info3; 4075 u32 pub_page_ctrl1; 4076 u32 pub_page_ctrl2; 4077 u32 pub_page_info1; 4078 u32 pub_page_info2; 4079 u32 wp_page_ctrl1; 4080 u32 wp_page_ctrl2; 4081 u32 wp_page_info1; 4082 }; 4083 4084 struct rtw89_imr_info { 4085 u32 wdrls_imr_set; 4086 u32 wsec_imr_reg; 4087 u32 wsec_imr_set; 4088 u32 mpdu_tx_imr_set; 4089 u32 mpdu_rx_imr_set; 4090 u32 sta_sch_imr_set; 4091 u32 txpktctl_imr_b0_reg; 4092 u32 txpktctl_imr_b0_clr; 4093 u32 txpktctl_imr_b0_set; 4094 u32 txpktctl_imr_b1_reg; 4095 u32 txpktctl_imr_b1_clr; 4096 u32 txpktctl_imr_b1_set; 4097 u32 wde_imr_clr; 4098 u32 wde_imr_set; 4099 u32 ple_imr_clr; 4100 u32 ple_imr_set; 4101 u32 host_disp_imr_clr; 4102 u32 host_disp_imr_set; 4103 u32 cpu_disp_imr_clr; 4104 u32 cpu_disp_imr_set; 4105 u32 other_disp_imr_clr; 4106 u32 other_disp_imr_set; 4107 u32 bbrpt_com_err_imr_reg; 4108 u32 bbrpt_chinfo_err_imr_reg; 4109 u32 bbrpt_err_imr_set; 4110 u32 bbrpt_dfs_err_imr_reg; 4111 u32 ptcl_imr_clr; 4112 u32 ptcl_imr_set; 4113 u32 cdma_imr_0_reg; 4114 u32 cdma_imr_0_clr; 4115 u32 cdma_imr_0_set; 4116 u32 cdma_imr_1_reg; 4117 u32 cdma_imr_1_clr; 4118 u32 cdma_imr_1_set; 4119 u32 phy_intf_imr_reg; 4120 u32 phy_intf_imr_clr; 4121 u32 phy_intf_imr_set; 4122 u32 rmac_imr_reg; 4123 u32 rmac_imr_clr; 4124 u32 rmac_imr_set; 4125 u32 tmac_imr_reg; 4126 u32 tmac_imr_clr; 4127 u32 tmac_imr_set; 4128 }; 4129 4130 struct rtw89_imr_table { 4131 const struct rtw89_reg_imr *regs; 4132 u32 n_regs; 4133 }; 4134 4135 struct rtw89_xtal_info { 4136 u32 xcap_reg; 4137 u32 sc_xo_mask; 4138 u32 sc_xi_mask; 4139 }; 4140 4141 struct rtw89_rrsr_cfgs { 4142 struct rtw89_reg3_def ref_rate; 4143 struct rtw89_reg3_def rsc; 4144 }; 4145 4146 struct rtw89_rfkill_regs { 4147 struct rtw89_reg3_def pinmux; 4148 struct rtw89_reg3_def mode; 4149 }; 4150 4151 struct rtw89_dig_regs { 4152 u32 seg0_pd_reg; 4153 u32 pd_lower_bound_mask; 4154 u32 pd_spatial_reuse_en; 4155 u32 bmode_pd_reg; 4156 u32 bmode_cca_rssi_limit_en; 4157 u32 bmode_pd_lower_bound_reg; 4158 u32 bmode_rssi_nocca_low_th_mask; 4159 struct rtw89_reg_def p0_lna_init; 4160 struct rtw89_reg_def p1_lna_init; 4161 struct rtw89_reg_def p0_tia_init; 4162 struct rtw89_reg_def p1_tia_init; 4163 struct rtw89_reg_def p0_rxb_init; 4164 struct rtw89_reg_def p1_rxb_init; 4165 struct rtw89_reg_def p0_p20_pagcugc_en; 4166 struct rtw89_reg_def p0_s20_pagcugc_en; 4167 struct rtw89_reg_def p1_p20_pagcugc_en; 4168 struct rtw89_reg_def p1_s20_pagcugc_en; 4169 }; 4170 4171 struct rtw89_edcca_regs { 4172 u32 edcca_level; 4173 u32 edcca_mask; 4174 u32 edcca_p_mask; 4175 u32 ppdu_level; 4176 u32 ppdu_mask; 4177 u32 rpt_a; 4178 u32 rpt_b; 4179 u32 rpt_sel; 4180 u32 rpt_sel_mask; 4181 u32 rpt_sel_be; 4182 u32 rpt_sel_be_mask; 4183 u32 tx_collision_t2r_st; 4184 u32 tx_collision_t2r_st_mask; 4185 }; 4186 4187 struct rtw89_phy_ul_tb_info { 4188 bool dyn_tb_tri_en; 4189 u8 def_if_bandedge; 4190 }; 4191 4192 struct rtw89_antdiv_stats { 4193 struct ewma_rssi cck_rssi_avg; 4194 struct ewma_rssi ofdm_rssi_avg; 4195 struct ewma_rssi non_legacy_rssi_avg; 4196 u16 pkt_cnt_cck; 4197 u16 pkt_cnt_ofdm; 4198 u16 pkt_cnt_non_legacy; 4199 u32 evm; 4200 }; 4201 4202 struct rtw89_antdiv_info { 4203 struct rtw89_antdiv_stats target_stats; 4204 struct rtw89_antdiv_stats main_stats; 4205 struct rtw89_antdiv_stats aux_stats; 4206 u8 training_count; 4207 u8 rssi_pre; 4208 bool get_stats; 4209 }; 4210 4211 enum rtw89_chanctx_state { 4212 RTW89_CHANCTX_STATE_MCC_START, 4213 RTW89_CHANCTX_STATE_MCC_STOP, 4214 }; 4215 4216 enum rtw89_chanctx_callbacks { 4217 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4218 RTW89_CHANCTX_CALLBACK_RFK, 4219 4220 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4221 }; 4222 4223 struct rtw89_chanctx_listener { 4224 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4225 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4226 }; 4227 4228 struct rtw89_chip_info { 4229 enum rtw89_core_chip_id chip_id; 4230 enum rtw89_chip_gen chip_gen; 4231 const struct rtw89_chip_ops *ops; 4232 const struct rtw89_mac_gen_def *mac_def; 4233 const struct rtw89_phy_gen_def *phy_def; 4234 const char *fw_basename; 4235 u8 fw_format_max; 4236 bool try_ce_fw; 4237 u8 bbmcu_nr; 4238 u32 needed_fw_elms; 4239 u32 fifo_size; 4240 bool small_fifo_size; 4241 u32 dle_scc_rsvd_size; 4242 u16 max_amsdu_limit; 4243 bool dis_2g_40m_ul_ofdma; 4244 u32 rsvd_ple_ofst; 4245 const struct rtw89_hfc_param_ini *hfc_param_ini; 4246 const struct rtw89_dle_mem *dle_mem; 4247 u8 wde_qempty_acq_grpnum; 4248 u8 wde_qempty_mgq_grpsel; 4249 u32 rf_base_addr[2]; 4250 u8 thermal_th[2]; 4251 u8 support_macid_num; 4252 u8 support_link_num; 4253 u8 support_chanctx_num; 4254 u8 support_bands; 4255 u16 support_bandwidths; 4256 bool support_unii4; 4257 bool support_rnr; 4258 bool ul_tb_waveform_ctrl; 4259 bool ul_tb_pwr_diff; 4260 bool hw_sec_hdr; 4261 bool hw_mgmt_tx_encrypt; 4262 u8 rf_path_num; 4263 u8 tx_nss; 4264 u8 rx_nss; 4265 u8 acam_num; 4266 u8 bcam_num; 4267 u8 scam_num; 4268 u8 bacam_num; 4269 u8 bacam_dynamic_num; 4270 enum rtw89_bacam_ver bacam_ver; 4271 u8 ppdu_max_usr; 4272 4273 u8 sec_ctrl_efuse_size; 4274 u32 physical_efuse_size; 4275 u32 logical_efuse_size; 4276 u32 limit_efuse_size; 4277 u32 dav_phy_efuse_size; 4278 u32 dav_log_efuse_size; 4279 u32 phycap_addr; 4280 u32 phycap_size; 4281 const struct rtw89_efuse_block_cfg *efuse_blocks; 4282 4283 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4284 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4285 const struct rtw89_phy_table *bb_table; 4286 const struct rtw89_phy_table *bb_gain_table; 4287 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4288 const struct rtw89_phy_table *nctl_table; 4289 const struct rtw89_rfk_tbl *nctl_post_table; 4290 const struct rtw89_phy_dig_gain_table *dig_table; 4291 const struct rtw89_dig_regs *dig_regs; 4292 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4293 4294 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4295 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4296 const struct rtw89_rfe_parms *dflt_parms; 4297 const struct rtw89_chanctx_listener *chanctx_listener; 4298 4299 u8 txpwr_factor_rf; 4300 u8 txpwr_factor_mac; 4301 4302 u32 para_ver; 4303 u32 wlcx_desired; 4304 u8 btcx_desired; 4305 u8 scbd; 4306 u8 mailbox; 4307 4308 u8 afh_guard_ch; 4309 const u8 *wl_rssi_thres; 4310 const u8 *bt_rssi_thres; 4311 u8 rssi_tol; 4312 4313 u8 mon_reg_num; 4314 const struct rtw89_btc_fbtc_mreg *mon_reg; 4315 u8 rf_para_ulink_num; 4316 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4317 u8 rf_para_dlink_num; 4318 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4319 u8 ps_mode_supported; 4320 u8 low_power_hci_modes; 4321 4322 u32 h2c_cctl_func_id; 4323 u32 hci_func_en_addr; 4324 u32 h2c_desc_size; 4325 u32 txwd_body_size; 4326 u32 txwd_info_size; 4327 u32 h2c_ctrl_reg; 4328 const u32 *h2c_regs; 4329 struct rtw89_reg_def h2c_counter_reg; 4330 u32 c2h_ctrl_reg; 4331 const u32 *c2h_regs; 4332 struct rtw89_reg_def c2h_counter_reg; 4333 const struct rtw89_page_regs *page_regs; 4334 const u32 *wow_reason_reg; 4335 bool cfo_src_fd; 4336 bool cfo_hw_comp; 4337 const struct rtw89_reg_def *dcfo_comp; 4338 u8 dcfo_comp_sft; 4339 const struct rtw89_imr_info *imr_info; 4340 const struct rtw89_imr_table *imr_dmac_table; 4341 const struct rtw89_imr_table *imr_cmac_table; 4342 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4343 struct rtw89_reg_def bss_clr_vld; 4344 u32 bss_clr_map_reg; 4345 const struct rtw89_rfkill_regs *rfkill_init; 4346 struct rtw89_reg_def rfkill_get; 4347 u32 dma_ch_mask; 4348 const struct rtw89_edcca_regs *edcca_regs; 4349 const struct wiphy_wowlan_support *wowlan_stub; 4350 const struct rtw89_xtal_info *xtal_info; 4351 }; 4352 4353 union rtw89_bus_info { 4354 const struct rtw89_pci_info *pci; 4355 }; 4356 4357 struct rtw89_driver_info { 4358 const struct rtw89_chip_info *chip; 4359 const struct dmi_system_id *quirks; 4360 union rtw89_bus_info bus; 4361 }; 4362 4363 enum rtw89_hcifc_mode { 4364 RTW89_HCIFC_POH = 0, 4365 RTW89_HCIFC_STF = 1, 4366 RTW89_HCIFC_SDIO = 2, 4367 4368 /* keep last */ 4369 RTW89_HCIFC_MODE_INVALID, 4370 }; 4371 4372 struct rtw89_dle_info { 4373 const struct rtw89_rsvd_quota *rsvd_qt; 4374 enum rtw89_qta_mode qta_mode; 4375 u16 ple_pg_size; 4376 u16 ple_free_pg; 4377 u16 c0_rx_qta; 4378 u16 c1_rx_qta; 4379 }; 4380 4381 enum rtw89_host_rpr_mode { 4382 RTW89_RPR_MODE_POH = 0, 4383 RTW89_RPR_MODE_STF 4384 }; 4385 4386 #define RTW89_COMPLETION_BUF_SIZE 40 4387 #define RTW89_WAIT_COND_IDLE UINT_MAX 4388 4389 struct rtw89_completion_data { 4390 bool err; 4391 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4392 }; 4393 4394 struct rtw89_wait_info { 4395 atomic_t cond; 4396 struct completion completion; 4397 struct rtw89_completion_data data; 4398 }; 4399 4400 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4401 4402 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4403 { 4404 init_completion(&wait->completion); 4405 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4406 } 4407 4408 struct rtw89_mac_info { 4409 struct rtw89_dle_info dle_info; 4410 struct rtw89_hfc_param hfc_param; 4411 enum rtw89_qta_mode qta_mode; 4412 u8 rpwm_seq_num; 4413 u8 cpwm_seq_num; 4414 4415 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4416 struct rtw89_wait_info fw_ofld_wait; 4417 /* see RTW89_PS_WAIT_COND series for wait condition */ 4418 struct rtw89_wait_info ps_wait; 4419 }; 4420 4421 enum rtw89_fwdl_check_type { 4422 RTW89_FWDL_CHECK_FREERTOS_DONE, 4423 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4424 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4425 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4426 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4427 }; 4428 4429 enum rtw89_fw_type { 4430 RTW89_FW_NORMAL = 1, 4431 RTW89_FW_WOWLAN = 3, 4432 RTW89_FW_NORMAL_CE = 5, 4433 RTW89_FW_BBMCU0 = 64, 4434 RTW89_FW_BBMCU1 = 65, 4435 RTW89_FW_LOGFMT = 255, 4436 }; 4437 4438 enum rtw89_fw_feature { 4439 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4440 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4441 RTW89_FW_FEATURE_TX_WAKE, 4442 RTW89_FW_FEATURE_CRASH_TRIGGER, 4443 RTW89_FW_FEATURE_NO_PACKET_DROP, 4444 RTW89_FW_FEATURE_NO_DEEP_PS, 4445 RTW89_FW_FEATURE_NO_LPS_PG, 4446 RTW89_FW_FEATURE_BEACON_FILTER, 4447 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4448 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4449 RTW89_FW_FEATURE_WOW_REASON_V1, 4450 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4451 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4452 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4453 }; 4454 4455 struct rtw89_fw_suit { 4456 enum rtw89_fw_type type; 4457 const u8 *data; 4458 u32 size; 4459 u8 major_ver; 4460 u8 minor_ver; 4461 u8 sub_ver; 4462 u8 sub_idex; 4463 u16 build_year; 4464 u16 build_mon; 4465 u16 build_date; 4466 u16 build_hour; 4467 u16 build_min; 4468 u8 cmd_ver; 4469 u8 hdr_ver; 4470 u32 commitid; 4471 }; 4472 4473 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4474 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4475 #define RTW89_FW_SUIT_VER_CODE(s) \ 4476 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4477 4478 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4479 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4480 (mfw_hdr)->ver.minor, \ 4481 (mfw_hdr)->ver.sub, \ 4482 (mfw_hdr)->ver.idx) 4483 4484 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4485 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4486 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4487 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4488 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4489 4490 struct rtw89_fw_req_info { 4491 const struct firmware *firmware; 4492 struct completion completion; 4493 }; 4494 4495 struct rtw89_fw_log { 4496 struct rtw89_fw_suit suit; 4497 bool enable; 4498 u32 last_fmt_id; 4499 u32 fmt_count; 4500 const __le32 *fmt_ids; 4501 const char *(*fmts)[]; 4502 }; 4503 4504 struct rtw89_fw_elm_info { 4505 struct rtw89_phy_table *bb_tbl; 4506 struct rtw89_phy_table *bb_gain; 4507 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4508 struct rtw89_phy_table *rf_nctl; 4509 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4510 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4511 }; 4512 4513 enum rtw89_fw_mss_dev_type { 4514 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4515 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4516 }; 4517 4518 struct rtw89_fw_secure { 4519 bool secure_boot: 1; 4520 bool can_mss_v1: 1; 4521 bool can_mss_v0: 1; 4522 u32 sb_sel_mgn; 4523 u8 mss_dev_type; 4524 u8 mss_cust_idx; 4525 u8 mss_key_num; 4526 u8 mss_idx; /* v0 */ 4527 }; 4528 4529 struct rtw89_fw_info { 4530 struct rtw89_fw_req_info req; 4531 int fw_format; 4532 u8 h2c_seq; 4533 u8 rec_seq; 4534 u8 h2c_counter; 4535 u8 c2h_counter; 4536 struct rtw89_fw_suit normal; 4537 struct rtw89_fw_suit wowlan; 4538 struct rtw89_fw_suit bbmcu0; 4539 struct rtw89_fw_suit bbmcu1; 4540 struct rtw89_fw_log log; 4541 u32 feature_map; 4542 struct rtw89_fw_elm_info elm_info; 4543 struct rtw89_fw_secure sec; 4544 }; 4545 4546 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4547 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4548 4549 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4550 ((_fw)->feature_map |= BIT(_fw_feature)) 4551 4552 struct rtw89_cam_info { 4553 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4554 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4555 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4556 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4557 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4558 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4559 }; 4560 4561 enum rtw89_sar_sources { 4562 RTW89_SAR_SOURCE_NONE, 4563 RTW89_SAR_SOURCE_COMMON, 4564 4565 RTW89_SAR_SOURCE_NR, 4566 }; 4567 4568 enum rtw89_sar_subband { 4569 RTW89_SAR_2GHZ_SUBBAND, 4570 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4571 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4572 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4573 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4574 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4575 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4576 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4577 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4578 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4579 4580 RTW89_SAR_SUBBAND_NR, 4581 }; 4582 4583 struct rtw89_sar_cfg_common { 4584 bool set[RTW89_SAR_SUBBAND_NR]; 4585 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4586 }; 4587 4588 struct rtw89_sar_info { 4589 /* used to decide how to acces SAR cfg union */ 4590 enum rtw89_sar_sources src; 4591 4592 /* reserved for different knids of SAR cfg struct. 4593 * supposed that a single cfg struct cannot handle various SAR sources. 4594 */ 4595 union { 4596 struct rtw89_sar_cfg_common cfg_common; 4597 }; 4598 }; 4599 4600 enum rtw89_tas_state { 4601 RTW89_TAS_STATE_DPR_OFF, 4602 RTW89_TAS_STATE_DPR_ON, 4603 RTW89_TAS_STATE_DPR_FORBID, 4604 }; 4605 4606 #define RTW89_TAS_MAX_WINDOW 50 4607 struct rtw89_tas_info { 4608 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4609 s32 total_txpwr; 4610 u8 cur_idx; 4611 s8 dpr_gap; 4612 s8 delta; 4613 enum rtw89_tas_state state; 4614 bool enable; 4615 }; 4616 4617 struct rtw89_chanctx_cfg { 4618 enum rtw89_chanctx_idx idx; 4619 int ref_count; 4620 }; 4621 4622 enum rtw89_chanctx_changes { 4623 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4624 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4625 RTW89_CHANCTX_P2P_PS_CHANGE, 4626 RTW89_CHANCTX_BT_SLOT_CHANGE, 4627 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4628 4629 NUM_OF_RTW89_CHANCTX_CHANGES, 4630 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4631 }; 4632 4633 enum rtw89_entity_mode { 4634 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4635 RTW89_ENTITY_MODE_MCC_PREPARE, 4636 RTW89_ENTITY_MODE_MCC, 4637 4638 NUM_OF_RTW89_ENTITY_MODE, 4639 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4640 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4641 }; 4642 4643 #define RTW89_MAX_INTERFACE_NUM 2 4644 4645 /* only valid when running with chanctx_ops */ 4646 struct rtw89_entity_mgnt { 4647 struct list_head active_list; 4648 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4649 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4650 [__RTW89_MLD_MAX_LINK_NUM]; 4651 }; 4652 4653 struct rtw89_chanctx { 4654 struct cfg80211_chan_def chandef; 4655 struct rtw89_chan chan; 4656 struct rtw89_chan_rcd rcd; 4657 4658 /* only assigned when running with chanctx_ops */ 4659 struct rtw89_chanctx_cfg *cfg; 4660 }; 4661 4662 struct rtw89_edcca_bak { 4663 u8 a; 4664 u8 p; 4665 u8 ppdu; 4666 u8 th_old; 4667 }; 4668 4669 enum rtw89_dm_type { 4670 RTW89_DM_DYNAMIC_EDCCA, 4671 RTW89_DM_THERMAL_PROTECT, 4672 }; 4673 4674 #define RTW89_THERMAL_PROT_LV_MAX 5 4675 #define RTW89_THERMAL_PROT_STEP 19 /* -19% for each level */ 4676 4677 struct rtw89_hal { 4678 u32 rx_fltr; 4679 u8 cv; 4680 u8 acv; 4681 u32 antenna_tx; 4682 u32 antenna_rx; 4683 u8 tx_nss; 4684 u8 rx_nss; 4685 bool tx_path_diversity; 4686 bool ant_diversity; 4687 bool ant_diversity_fixed; 4688 bool support_cckpd; 4689 bool support_igi; 4690 atomic_t roc_chanctx_idx; 4691 4692 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4693 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4694 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4695 struct cfg80211_chan_def roc_chandef; 4696 4697 bool entity_active[RTW89_PHY_MAX]; 4698 bool entity_pause; 4699 enum rtw89_entity_mode entity_mode; 4700 struct rtw89_entity_mgnt entity_mgnt; 4701 4702 struct rtw89_edcca_bak edcca_bak; 4703 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4704 4705 u8 thermal_prot_th; 4706 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 4707 }; 4708 4709 #define RTW89_MAX_MAC_ID_NUM 128 4710 #define RTW89_MAX_PKT_OFLD_NUM 255 4711 4712 enum rtw89_flags { 4713 RTW89_FLAG_POWERON, 4714 RTW89_FLAG_DMAC_FUNC, 4715 RTW89_FLAG_CMAC0_FUNC, 4716 RTW89_FLAG_CMAC1_FUNC, 4717 RTW89_FLAG_FW_RDY, 4718 RTW89_FLAG_RUNNING, 4719 RTW89_FLAG_PROBE_DONE, 4720 RTW89_FLAG_BFEE_MON, 4721 RTW89_FLAG_BFEE_EN, 4722 RTW89_FLAG_BFEE_TIMER_KEEP, 4723 RTW89_FLAG_NAPI_RUNNING, 4724 RTW89_FLAG_LEISURE_PS, 4725 RTW89_FLAG_LOW_POWER_MODE, 4726 RTW89_FLAG_INACTIVE_PS, 4727 RTW89_FLAG_CRASH_SIMULATING, 4728 RTW89_FLAG_SER_HANDLING, 4729 RTW89_FLAG_WOWLAN, 4730 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4731 RTW89_FLAG_CHANGING_INTERFACE, 4732 RTW89_FLAG_HW_RFKILL_STATE, 4733 4734 NUM_OF_RTW89_FLAGS, 4735 }; 4736 4737 enum rtw89_quirks { 4738 RTW89_QUIRK_PCI_BER, 4739 RTW89_QUIRK_THERMAL_PROT_120C, 4740 RTW89_QUIRK_THERMAL_PROT_110C, 4741 4742 NUM_OF_RTW89_QUIRKS, 4743 }; 4744 4745 enum rtw89_custid { 4746 RTW89_CUSTID_NONE, 4747 RTW89_CUSTID_ACER, 4748 RTW89_CUSTID_AMD, 4749 RTW89_CUSTID_ASUS, 4750 RTW89_CUSTID_DELL, 4751 RTW89_CUSTID_HP, 4752 RTW89_CUSTID_LENOVO, 4753 }; 4754 4755 enum rtw89_pkt_drop_sel { 4756 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4757 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4758 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4759 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4760 RTW89_PKT_DROP_SEL_MACID_ALL, 4761 RTW89_PKT_DROP_SEL_MG0_ONCE, 4762 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4763 RTW89_PKT_DROP_SEL_HIQ_PORT, 4764 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4765 RTW89_PKT_DROP_SEL_BAND, 4766 RTW89_PKT_DROP_SEL_BAND_ONCE, 4767 RTW89_PKT_DROP_SEL_REL_MACID, 4768 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4769 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4770 }; 4771 4772 struct rtw89_pkt_drop_params { 4773 enum rtw89_pkt_drop_sel sel; 4774 enum rtw89_mac_idx mac_band; 4775 u8 macid; 4776 u8 port; 4777 u8 mbssid; 4778 bool tf_trs; 4779 u32 macid_band_sel[4]; 4780 }; 4781 4782 struct rtw89_pkt_stat { 4783 u16 beacon_nr; 4784 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4785 }; 4786 4787 DECLARE_EWMA(thermal, 4, 4); 4788 4789 struct rtw89_phy_stat { 4790 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4791 u8 last_thermal_max; 4792 struct ewma_rssi bcn_rssi; 4793 struct rtw89_pkt_stat cur_pkt_stat; 4794 struct rtw89_pkt_stat last_pkt_stat; 4795 }; 4796 4797 enum rtw89_rfk_report_state { 4798 RTW89_RFK_STATE_START = 0x0, 4799 RTW89_RFK_STATE_OK = 0x1, 4800 RTW89_RFK_STATE_FAIL = 0x2, 4801 RTW89_RFK_STATE_TIMEOUT = 0x3, 4802 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4803 }; 4804 4805 struct rtw89_rfk_wait_info { 4806 struct completion completion; 4807 ktime_t start_time; 4808 enum rtw89_rfk_report_state state; 4809 u8 version; 4810 }; 4811 4812 #define RTW89_DACK_PATH_NR 2 4813 #define RTW89_DACK_IDX_NR 2 4814 #define RTW89_DACK_MSBK_NR 16 4815 struct rtw89_dack_info { 4816 bool dack_done; 4817 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4818 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4819 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4820 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4821 u32 dack_cnt; 4822 bool addck_timeout[RTW89_DACK_PATH_NR]; 4823 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4824 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4825 }; 4826 4827 enum rtw89_rfk_chs_nrs { 4828 __RTW89_RFK_CHS_NR_V0 = 2, 4829 __RTW89_RFK_CHS_NR_V1 = 3, 4830 4831 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 4832 }; 4833 4834 struct rtw89_rfk_mcc_info_data { 4835 u8 ch[RTW89_RFK_CHS_NR]; 4836 u8 band[RTW89_RFK_CHS_NR]; 4837 u8 bw[RTW89_RFK_CHS_NR]; 4838 u8 table_idx; 4839 }; 4840 4841 struct rtw89_rfk_mcc_info { 4842 struct rtw89_rfk_mcc_info_data data[2]; 4843 }; 4844 4845 #define RTW89_IQK_CHS_NR 2 4846 #define RTW89_IQK_PATH_NR 4 4847 4848 struct rtw89_lck_info { 4849 u8 thermal[RF_PATH_MAX]; 4850 }; 4851 4852 struct rtw89_rx_dck_info { 4853 u8 thermal[RF_PATH_MAX]; 4854 }; 4855 4856 struct rtw89_iqk_info { 4857 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4858 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4859 bool lok_fail[RTW89_IQK_PATH_NR]; 4860 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4861 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4862 u32 iqk_fail_cnt; 4863 bool is_iqk_init; 4864 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4865 u8 iqk_band[RTW89_IQK_PATH_NR]; 4866 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4867 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4868 u8 iqk_times; 4869 u8 version; 4870 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4871 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4872 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4873 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4874 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4875 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4876 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4877 bool is_nbiqk; 4878 bool iqk_fft_en; 4879 bool iqk_xym_en; 4880 bool iqk_sram_en; 4881 bool iqk_cfir_en; 4882 u32 syn1to2; 4883 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4884 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4885 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4886 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4887 }; 4888 4889 #define RTW89_DPK_RF_PATH 2 4890 #define RTW89_DPK_AVG_THERMAL_NUM 8 4891 #define RTW89_DPK_BKUP_NUM 2 4892 struct rtw89_dpk_bkup_para { 4893 enum rtw89_band band; 4894 enum rtw89_bandwidth bw; 4895 u8 ch; 4896 bool path_ok; 4897 u8 mdpd_en; 4898 u8 txagc_dpk; 4899 u8 ther_dpk; 4900 u8 gs; 4901 u16 pwsf; 4902 }; 4903 4904 struct rtw89_dpk_info { 4905 bool is_dpk_enable; 4906 bool is_dpk_reload_en; 4907 u8 dpk_gs[RTW89_PHY_MAX]; 4908 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4909 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4910 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4911 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4912 u8 cur_idx[RTW89_DPK_RF_PATH]; 4913 u8 cur_k_set; 4914 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4915 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 4916 u32 dpk_order[RTW89_DPK_RF_PATH]; 4917 }; 4918 4919 struct rtw89_fem_info { 4920 bool elna_2g; 4921 bool elna_5g; 4922 bool epa_2g; 4923 bool epa_5g; 4924 bool epa_6g; 4925 }; 4926 4927 struct rtw89_phy_ch_info { 4928 u8 rssi_min; 4929 u16 rssi_min_macid; 4930 u8 pre_rssi_min; 4931 u8 rssi_max; 4932 u16 rssi_max_macid; 4933 u8 rxsc_160; 4934 u8 rxsc_80; 4935 u8 rxsc_40; 4936 u8 rxsc_20; 4937 u8 rxsc_l; 4938 u8 is_noisy; 4939 }; 4940 4941 struct rtw89_agc_gaincode_set { 4942 u8 lna_idx; 4943 u8 tia_idx; 4944 u8 rxb_idx; 4945 }; 4946 4947 #define IGI_RSSI_TH_NUM 5 4948 #define FA_TH_NUM 4 4949 #define TIA_LNA_OP1DB_NUM 8 4950 #define LNA_GAIN_NUM 7 4951 #define TIA_GAIN_NUM 2 4952 struct rtw89_dig_info { 4953 struct rtw89_agc_gaincode_set cur_gaincode; 4954 bool force_gaincode_idx_en; 4955 struct rtw89_agc_gaincode_set force_gaincode; 4956 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4957 u16 fa_th[FA_TH_NUM]; 4958 u8 igi_rssi; 4959 u8 igi_fa_rssi; 4960 u8 fa_rssi_ofst; 4961 u8 dyn_igi_max; 4962 u8 dyn_igi_min; 4963 bool dyn_pd_th_en; 4964 u8 dyn_pd_th_max; 4965 u8 pd_low_th_ofst; 4966 u8 ib_pbk; 4967 s8 ib_pkpwr; 4968 s8 lna_gain_a[LNA_GAIN_NUM]; 4969 s8 lna_gain_g[LNA_GAIN_NUM]; 4970 s8 *lna_gain; 4971 s8 tia_gain_a[TIA_GAIN_NUM]; 4972 s8 tia_gain_g[TIA_GAIN_NUM]; 4973 s8 *tia_gain; 4974 bool is_linked_pre; 4975 bool bypass_dig; 4976 }; 4977 4978 enum rtw89_multi_cfo_mode { 4979 RTW89_PKT_BASED_AVG_MODE = 0, 4980 RTW89_ENTRY_BASED_AVG_MODE = 1, 4981 RTW89_TP_BASED_AVG_MODE = 2, 4982 }; 4983 4984 enum rtw89_phy_cfo_status { 4985 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4986 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4987 RTW89_PHY_DCFO_STATE_HOLD = 2, 4988 RTW89_PHY_DCFO_STATE_MAX 4989 }; 4990 4991 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4992 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4993 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4994 }; 4995 4996 struct rtw89_cfo_tracking_info { 4997 u16 cfo_timer_ms; 4998 bool cfo_trig_by_timer_en; 4999 enum rtw89_phy_cfo_status phy_cfo_status; 5000 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5001 u8 phy_cfo_trk_cnt; 5002 bool is_adjust; 5003 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5004 bool apply_compensation; 5005 u8 crystal_cap; 5006 u8 crystal_cap_default; 5007 u8 def_x_cap; 5008 s8 x_cap_ofst; 5009 u32 sta_cfo_tolerance; 5010 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5011 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5012 s32 cfo_avg_pre; 5013 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5014 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5015 s32 dcfo_avg; 5016 s32 dcfo_avg_pre; 5017 u32 packet_count; 5018 u32 packet_count_pre; 5019 s32 residual_cfo_acc; 5020 u8 phy_cfotrk_state; 5021 u8 phy_cfotrk_cnt; 5022 bool divergence_lock_en; 5023 u8 x_cap_lb; 5024 u8 x_cap_ub; 5025 u8 lock_cnt; 5026 }; 5027 5028 enum rtw89_tssi_mode { 5029 RTW89_TSSI_NORMAL = 0, 5030 RTW89_TSSI_SCAN = 1, 5031 }; 5032 5033 enum rtw89_tssi_alimk_band { 5034 TSSI_ALIMK_2G = 0, 5035 TSSI_ALIMK_5GL, 5036 TSSI_ALIMK_5GM, 5037 TSSI_ALIMK_5GH, 5038 TSSI_ALIMK_MAX 5039 }; 5040 5041 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5042 #define TSSI_TRIM_CH_GROUP_NUM 8 5043 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5044 5045 #define TSSI_CCK_CH_GROUP_NUM 6 5046 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5047 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5048 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5049 #define TSSI_MCS_CH_GROUP_NUM \ 5050 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5051 #define TSSI_MAX_CH_NUM 67 5052 #define TSSI_ALIMK_VALUE_NUM 8 5053 5054 struct rtw89_tssi_info { 5055 u8 thermal[RF_PATH_MAX]; 5056 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5057 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5058 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5059 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5060 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5061 s8 extra_ofst[RF_PATH_MAX]; 5062 bool tssi_tracking_check[RF_PATH_MAX]; 5063 u8 default_txagc_offset[RF_PATH_MAX]; 5064 u32 base_thermal[RF_PATH_MAX]; 5065 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5066 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5067 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5068 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5069 u32 tssi_alimk_time; 5070 }; 5071 5072 struct rtw89_power_trim_info { 5073 bool pg_thermal_trim; 5074 bool pg_pa_bias_trim; 5075 u8 thermal_trim[RF_PATH_MAX]; 5076 u8 pa_bias_trim[RF_PATH_MAX]; 5077 u8 pad_bias_trim[RF_PATH_MAX]; 5078 }; 5079 5080 struct rtw89_regd { 5081 char alpha2[3]; 5082 u8 txpwr_regd[RTW89_BAND_NUM]; 5083 }; 5084 5085 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5086 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5087 #define RTW89_5GHZ_UNII4_START_INDEX 25 5088 5089 struct rtw89_regulatory_info { 5090 const struct rtw89_regd *regd; 5091 enum rtw89_reg_6ghz_power reg_6ghz_power; 5092 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5093 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5094 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5095 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5096 }; 5097 5098 enum rtw89_ifs_clm_application { 5099 RTW89_IFS_CLM_INIT = 0, 5100 RTW89_IFS_CLM_BACKGROUND = 1, 5101 RTW89_IFS_CLM_ACS = 2, 5102 RTW89_IFS_CLM_DIG = 3, 5103 RTW89_IFS_CLM_TDMA_DIG = 4, 5104 RTW89_IFS_CLM_DBG = 5, 5105 RTW89_IFS_CLM_DBG_MANUAL = 6 5106 }; 5107 5108 enum rtw89_env_racing_lv { 5109 RTW89_RAC_RELEASE = 0, 5110 RTW89_RAC_LV_1 = 1, 5111 RTW89_RAC_LV_2 = 2, 5112 RTW89_RAC_LV_3 = 3, 5113 RTW89_RAC_LV_4 = 4, 5114 RTW89_RAC_MAX_NUM = 5 5115 }; 5116 5117 struct rtw89_ccx_para_info { 5118 enum rtw89_env_racing_lv rac_lv; 5119 u16 mntr_time; 5120 u8 nhm_manual_th_ofst; 5121 u8 nhm_manual_th0; 5122 enum rtw89_ifs_clm_application ifs_clm_app; 5123 u32 ifs_clm_manual_th_times; 5124 u32 ifs_clm_manual_th0; 5125 u8 fahm_manual_th_ofst; 5126 u8 fahm_manual_th0; 5127 u8 fahm_numer_opt; 5128 u8 fahm_denom_opt; 5129 }; 5130 5131 enum rtw89_ccx_edcca_opt_sc_idx { 5132 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5133 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5134 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5135 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5136 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5137 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5138 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5139 RTW89_CCX_EDCCA_SEG1_S3 = 7 5140 }; 5141 5142 enum rtw89_ccx_edcca_opt_bw_idx { 5143 RTW89_CCX_EDCCA_BW20_0 = 0, 5144 RTW89_CCX_EDCCA_BW20_1 = 1, 5145 RTW89_CCX_EDCCA_BW20_2 = 2, 5146 RTW89_CCX_EDCCA_BW20_3 = 3, 5147 RTW89_CCX_EDCCA_BW20_4 = 4, 5148 RTW89_CCX_EDCCA_BW20_5 = 5, 5149 RTW89_CCX_EDCCA_BW20_6 = 6, 5150 RTW89_CCX_EDCCA_BW20_7 = 7 5151 }; 5152 5153 #define RTW89_NHM_TH_NUM 11 5154 #define RTW89_FAHM_TH_NUM 11 5155 #define RTW89_NHM_RPT_NUM 12 5156 #define RTW89_FAHM_RPT_NUM 12 5157 #define RTW89_IFS_CLM_NUM 4 5158 struct rtw89_env_monitor_info { 5159 u8 ccx_watchdog_result; 5160 bool ccx_ongoing; 5161 u8 ccx_rac_lv; 5162 bool ccx_manual_ctrl; 5163 u16 ifs_clm_mntr_time; 5164 enum rtw89_ifs_clm_application ifs_clm_app; 5165 u16 ccx_period; 5166 u8 ccx_unit_idx; 5167 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5168 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5169 u16 ifs_clm_tx; 5170 u16 ifs_clm_edcca_excl_cca; 5171 u16 ifs_clm_ofdmfa; 5172 u16 ifs_clm_ofdmcca_excl_fa; 5173 u16 ifs_clm_cckfa; 5174 u16 ifs_clm_cckcca_excl_fa; 5175 u16 ifs_clm_total_ifs; 5176 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5177 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5178 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5179 u8 ifs_clm_tx_ratio; 5180 u8 ifs_clm_edcca_excl_cca_ratio; 5181 u8 ifs_clm_cck_fa_ratio; 5182 u8 ifs_clm_ofdm_fa_ratio; 5183 u8 ifs_clm_cck_cca_excl_fa_ratio; 5184 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5185 u16 ifs_clm_cck_fa_permil; 5186 u16 ifs_clm_ofdm_fa_permil; 5187 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5188 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5189 }; 5190 5191 enum rtw89_ser_rcvy_step { 5192 RTW89_SER_DRV_STOP_TX, 5193 RTW89_SER_DRV_STOP_RX, 5194 RTW89_SER_DRV_STOP_RUN, 5195 RTW89_SER_HAL_STOP_DMA, 5196 RTW89_SER_SUPPRESS_LOG, 5197 RTW89_NUM_OF_SER_FLAGS 5198 }; 5199 5200 struct rtw89_ser { 5201 u8 state; 5202 u8 alarm_event; 5203 bool prehandle_l1; 5204 5205 struct work_struct ser_hdl_work; 5206 struct delayed_work ser_alarm_work; 5207 const struct state_ent *st_tbl; 5208 const struct event_ent *ev_tbl; 5209 struct list_head msg_q; 5210 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5211 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5212 }; 5213 5214 enum rtw89_mac_ax_ps_mode { 5215 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5216 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5217 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5218 RTW89_MAC_AX_PS_MODE_MAX = 3, 5219 }; 5220 5221 enum rtw89_last_rpwm_mode { 5222 RTW89_LAST_RPWM_PS = 0x0, 5223 RTW89_LAST_RPWM_ACTIVE = 0x6, 5224 }; 5225 5226 struct rtw89_lps_parm { 5227 u8 macid; 5228 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5229 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5230 }; 5231 5232 struct rtw89_ppdu_sts_info { 5233 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 5234 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 5235 }; 5236 5237 struct rtw89_early_h2c { 5238 struct list_head list; 5239 u8 *h2c; 5240 u16 h2c_len; 5241 }; 5242 5243 struct rtw89_hw_scan_info { 5244 struct rtw89_vif_link *scanning_vif; 5245 struct list_head pkt_list[NUM_NL80211_BANDS]; 5246 struct rtw89_chan op_chan; 5247 bool abort; 5248 u32 last_chan_idx; 5249 }; 5250 5251 enum rtw89_phy_bb_gain_band { 5252 RTW89_BB_GAIN_BAND_2G = 0, 5253 RTW89_BB_GAIN_BAND_5G_L = 1, 5254 RTW89_BB_GAIN_BAND_5G_M = 2, 5255 RTW89_BB_GAIN_BAND_5G_H = 3, 5256 RTW89_BB_GAIN_BAND_6G_L = 4, 5257 RTW89_BB_GAIN_BAND_6G_M = 5, 5258 RTW89_BB_GAIN_BAND_6G_H = 6, 5259 RTW89_BB_GAIN_BAND_6G_UH = 7, 5260 5261 RTW89_BB_GAIN_BAND_NR, 5262 }; 5263 5264 enum rtw89_phy_gain_band_be { 5265 RTW89_BB_GAIN_BAND_2G_BE = 0, 5266 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5267 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5268 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5269 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5270 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5271 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5272 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5273 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5274 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5275 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5276 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5277 5278 RTW89_BB_GAIN_BAND_NR_BE, 5279 }; 5280 5281 enum rtw89_phy_bb_bw_be { 5282 RTW89_BB_BW_20_40 = 0, 5283 RTW89_BB_BW_80_160_320 = 1, 5284 5285 RTW89_BB_BW_NR_BE, 5286 }; 5287 5288 enum rtw89_bw20_sc { 5289 RTW89_BW20_SC_20M = 1, 5290 RTW89_BW20_SC_40M = 2, 5291 RTW89_BW20_SC_80M = 4, 5292 RTW89_BW20_SC_160M = 8, 5293 RTW89_BW20_SC_320M = 16, 5294 }; 5295 5296 enum rtw89_cmac_table_bw { 5297 RTW89_CMAC_BW_20M = 0, 5298 RTW89_CMAC_BW_40M = 1, 5299 RTW89_CMAC_BW_80M = 2, 5300 RTW89_CMAC_BW_160M = 3, 5301 RTW89_CMAC_BW_320M = 4, 5302 5303 RTW89_CMAC_BW_NR, 5304 }; 5305 5306 enum rtw89_phy_bb_rxsc_num { 5307 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5308 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5309 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5310 }; 5311 5312 struct rtw89_phy_bb_gain_info { 5313 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5314 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5315 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5316 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5317 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5318 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5319 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5320 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5321 [RTW89_BB_RXSC_NUM_40]; 5322 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5323 [RTW89_BB_RXSC_NUM_80]; 5324 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5325 [RTW89_BB_RXSC_NUM_160]; 5326 }; 5327 5328 struct rtw89_phy_bb_gain_info_be { 5329 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5330 [LNA_GAIN_NUM]; 5331 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5332 [TIA_GAIN_NUM]; 5333 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5334 [RF_PATH_MAX][LNA_GAIN_NUM]; 5335 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5336 [RF_PATH_MAX][LNA_GAIN_NUM]; 5337 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5338 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5339 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5340 [RTW89_BW20_SC_20M]; 5341 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5342 [RTW89_BW20_SC_40M]; 5343 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5344 [RTW89_BW20_SC_80M]; 5345 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5346 [RTW89_BW20_SC_160M]; 5347 }; 5348 5349 struct rtw89_phy_efuse_gain { 5350 bool offset_valid; 5351 bool comp_valid; 5352 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5353 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5354 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5355 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5356 }; 5357 5358 #define RTW89_MAX_PATTERN_NUM 18 5359 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5360 #define RTW89_MAX_PATTERN_SIZE 128 5361 5362 struct rtw89_wow_cam_info { 5363 bool r_w; 5364 u8 idx; 5365 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5366 u16 crc; 5367 bool negative_pattern_match; 5368 bool skip_mac_hdr; 5369 bool uc; 5370 bool mc; 5371 bool bc; 5372 bool valid; 5373 }; 5374 5375 struct rtw89_wow_key_info { 5376 u8 ptk_tx_iv[8]; 5377 u8 valid_check; 5378 u8 symbol_check_en; 5379 u8 gtk_keyidx; 5380 u8 rsvd[5]; 5381 u8 ptk_rx_iv[8]; 5382 u8 gtk_rx_iv[4][8]; 5383 } __packed; 5384 5385 struct rtw89_wow_gtk_info { 5386 u8 kck[32]; 5387 u8 kek[32]; 5388 u8 tk1[16]; 5389 u8 txmickey[8]; 5390 u8 rxmickey[8]; 5391 __le32 igtk_keyid; 5392 __le64 ipn; 5393 u8 igtk[2][32]; 5394 u8 psk[32]; 5395 } __packed; 5396 5397 struct rtw89_wow_aoac_report { 5398 u8 rpt_ver; 5399 u8 sec_type; 5400 u8 key_idx; 5401 u8 pattern_idx; 5402 u8 rekey_ok; 5403 u8 ptk_tx_iv[8]; 5404 u8 eapol_key_replay_count[8]; 5405 u8 gtk[32]; 5406 u8 ptk_rx_iv[8]; 5407 u8 gtk_rx_iv[4][8]; 5408 u64 igtk_key_id; 5409 u64 igtk_ipn; 5410 u8 igtk[32]; 5411 u8 csa_pri_ch; 5412 u8 csa_bw; 5413 u8 csa_ch_offset; 5414 u8 csa_chsw_failed; 5415 u8 csa_ch_band; 5416 }; 5417 5418 struct rtw89_wow_param { 5419 struct rtw89_vif_link *rtwvif_link; 5420 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5421 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5422 struct rtw89_wow_key_info key_info; 5423 struct rtw89_wow_gtk_info gtk_info; 5424 struct rtw89_wow_aoac_report aoac_rpt; 5425 u8 pattern_cnt; 5426 u8 ptk_alg; 5427 u8 gtk_alg; 5428 u8 ptk_keyidx; 5429 u8 akm; 5430 5431 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5432 struct rtw89_wait_info wait; 5433 5434 bool pno_inited; 5435 struct list_head pno_pkt_list; 5436 struct cfg80211_sched_scan_request *nd_config; 5437 }; 5438 5439 struct rtw89_mcc_limit { 5440 bool enable; 5441 u16 max_tob; /* TU; max time offset behind */ 5442 u16 max_toa; /* TU; max time offset ahead */ 5443 u16 max_dur; /* TU */ 5444 }; 5445 5446 struct rtw89_mcc_policy { 5447 u8 c2h_rpt; 5448 u8 tx_null_early; 5449 u8 dis_tx_null; 5450 u8 in_curr_ch; 5451 u8 dis_sw_retry; 5452 u8 sw_retry_count; 5453 }; 5454 5455 struct rtw89_mcc_role { 5456 struct rtw89_vif_link *rtwvif_link; 5457 struct rtw89_mcc_policy policy; 5458 struct rtw89_mcc_limit limit; 5459 5460 /* only valid when running with FW MRC mechanism */ 5461 u8 slot_idx; 5462 5463 /* byte-array in LE order for FW */ 5464 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5465 5466 u16 duration; /* TU */ 5467 u16 beacon_interval; /* TU */ 5468 bool is_2ghz; 5469 bool is_go; 5470 bool is_gc; 5471 }; 5472 5473 struct rtw89_mcc_bt_role { 5474 u16 duration; /* TU */ 5475 }; 5476 5477 struct rtw89_mcc_courtesy { 5478 bool enable; 5479 u8 slot_num; 5480 u8 macid_src; 5481 u8 macid_tgt; 5482 }; 5483 5484 enum rtw89_mcc_plan { 5485 RTW89_MCC_PLAN_TAIL_BT, 5486 RTW89_MCC_PLAN_MID_BT, 5487 RTW89_MCC_PLAN_NO_BT, 5488 5489 NUM_OF_RTW89_MCC_PLAN, 5490 }; 5491 5492 struct rtw89_mcc_pattern { 5493 s16 tob_ref; /* TU; time offset behind of reference role */ 5494 s16 toa_ref; /* TU; time offset ahead of reference role */ 5495 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5496 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5497 5498 enum rtw89_mcc_plan plan; 5499 struct rtw89_mcc_courtesy courtesy; 5500 }; 5501 5502 struct rtw89_mcc_sync { 5503 bool enable; 5504 u16 offset; /* TU */ 5505 u8 macid_src; 5506 u8 band_src; 5507 u8 port_src; 5508 u8 macid_tgt; 5509 u8 band_tgt; 5510 u8 port_tgt; 5511 }; 5512 5513 struct rtw89_mcc_config { 5514 struct rtw89_mcc_pattern pattern; 5515 struct rtw89_mcc_sync sync; 5516 u64 start_tsf; 5517 u16 mcc_interval; /* TU */ 5518 u16 beacon_offset; /* TU */ 5519 }; 5520 5521 enum rtw89_mcc_mode { 5522 RTW89_MCC_MODE_GO_STA, 5523 RTW89_MCC_MODE_GC_STA, 5524 }; 5525 5526 struct rtw89_mcc_info { 5527 struct rtw89_wait_info wait; 5528 5529 u8 group; 5530 enum rtw89_mcc_mode mode; 5531 struct rtw89_mcc_role role_ref; /* reference role */ 5532 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5533 struct rtw89_mcc_bt_role bt_role; 5534 struct rtw89_mcc_config config; 5535 }; 5536 5537 struct rtw89_dev { 5538 struct ieee80211_hw *hw; 5539 struct device *dev; 5540 const struct ieee80211_ops *ops; 5541 5542 bool dbcc_en; 5543 bool support_mlo; 5544 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5545 struct rtw89_hw_scan_info scan_info; 5546 const struct rtw89_chip_info *chip; 5547 const struct rtw89_pci_info *pci_info; 5548 const struct rtw89_rfe_parms *rfe_parms; 5549 struct rtw89_hal hal; 5550 struct rtw89_mcc_info mcc; 5551 struct rtw89_mac_info mac; 5552 struct rtw89_fw_info fw; 5553 struct rtw89_hci_info hci; 5554 struct rtw89_efuse efuse; 5555 struct rtw89_traffic_stats stats; 5556 struct rtw89_rfe_data *rfe_data; 5557 enum rtw89_custid custid; 5558 5559 /* ensures exclusive access from mac80211 callbacks */ 5560 struct mutex mutex; 5561 struct list_head rtwvifs_list; 5562 /* used to protect rf read write */ 5563 struct mutex rf_mutex; 5564 struct workqueue_struct *txq_wq; 5565 struct work_struct txq_work; 5566 struct delayed_work txq_reinvoke_work; 5567 /* used to protect ba_list and forbid_ba_list */ 5568 spinlock_t ba_lock; 5569 /* txqs to setup ba session */ 5570 struct list_head ba_list; 5571 /* txqs to forbid ba session */ 5572 struct list_head forbid_ba_list; 5573 struct work_struct ba_work; 5574 /* used to protect rpwm */ 5575 spinlock_t rpwm_lock; 5576 5577 struct rtw89_cam_info cam_info; 5578 5579 struct sk_buff_head c2h_queue; 5580 struct work_struct c2h_work; 5581 struct work_struct ips_work; 5582 struct work_struct load_firmware_work; 5583 struct work_struct cancel_6ghz_probe_work; 5584 5585 struct list_head early_h2c_list; 5586 5587 struct rtw89_ser ser; 5588 5589 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5590 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5591 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5592 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5593 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5594 5595 struct rtw89_phy_stat phystat; 5596 struct rtw89_rfk_wait_info rfk_wait; 5597 struct rtw89_dack_info dack; 5598 struct rtw89_iqk_info iqk; 5599 struct rtw89_dpk_info dpk; 5600 struct rtw89_rfk_mcc_info rfk_mcc; 5601 struct rtw89_lck_info lck; 5602 struct rtw89_rx_dck_info rx_dck; 5603 bool is_tssi_mode[RF_PATH_MAX]; 5604 bool is_bt_iqk_timeout; 5605 5606 struct rtw89_fem_info fem; 5607 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5608 struct rtw89_tssi_info tssi; 5609 struct rtw89_power_trim_info pwr_trim; 5610 5611 struct rtw89_cfo_tracking_info cfo_tracking; 5612 struct rtw89_env_monitor_info env_monitor; 5613 struct rtw89_dig_info dig; 5614 struct rtw89_phy_ch_info ch_info; 5615 union { 5616 struct rtw89_phy_bb_gain_info ax; 5617 struct rtw89_phy_bb_gain_info_be be; 5618 } bb_gain; 5619 struct rtw89_phy_efuse_gain efuse_gain; 5620 struct rtw89_phy_ul_tb_info ul_tb_info; 5621 struct rtw89_antdiv_info antdiv; 5622 5623 struct delayed_work track_work; 5624 struct delayed_work chanctx_work; 5625 struct delayed_work coex_act1_work; 5626 struct delayed_work coex_bt_devinfo_work; 5627 struct delayed_work coex_rfk_chk_work; 5628 struct delayed_work cfo_track_work; 5629 struct delayed_work forbid_ba_work; 5630 struct delayed_work roc_work; 5631 struct delayed_work antdiv_work; 5632 struct rtw89_ppdu_sts_info ppdu_sts; 5633 u8 total_sta_assoc; 5634 bool scanning; 5635 5636 struct rtw89_regulatory_info regulatory; 5637 struct rtw89_sar_info sar; 5638 struct rtw89_tas_info tas; 5639 5640 struct rtw89_btc btc; 5641 enum rtw89_ps_mode ps_mode; 5642 bool lps_enabled; 5643 5644 struct rtw89_wow_param wow; 5645 5646 /* napi structure */ 5647 struct net_device *netdev; 5648 struct napi_struct napi; 5649 int napi_budget_countdown; 5650 5651 struct rtw89_debugfs *debugfs; 5652 5653 /* HCI related data, keep last */ 5654 u8 priv[] __aligned(sizeof(void *)); 5655 }; 5656 5657 struct rtw89_vif { 5658 struct rtw89_dev *rtwdev; 5659 struct list_head list; 5660 struct list_head mgnt_entry; 5661 5662 u8 mac_addr[ETH_ALEN]; 5663 __be32 ip_addr; 5664 5665 struct rtw89_traffic_stats stats; 5666 u32 tdls_peer; 5667 5668 struct ieee80211_scan_ies *scan_ies; 5669 struct cfg80211_scan_request *scan_req; 5670 5671 struct rtw89_roc roc; 5672 bool offchan; 5673 5674 u8 links_inst_valid_num; 5675 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5676 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5677 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 5678 }; 5679 5680 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 5681 const struct rtw89_vif *rtwvif, 5682 unsigned int link_id) 5683 { 5684 *rtwvif_link = rtwvif->links[link_id]; 5685 return !!*rtwvif_link; 5686 } 5687 5688 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 5689 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5690 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 5691 5692 struct rtw89_sta { 5693 struct rtw89_dev *rtwdev; 5694 struct rtw89_vif *rtwvif; 5695 5696 bool disassoc; 5697 5698 struct sk_buff_head roc_queue; 5699 5700 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 5701 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 5702 5703 u8 links_inst_valid_num; 5704 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5705 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5706 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 5707 }; 5708 5709 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 5710 const struct rtw89_sta *rtwsta, 5711 unsigned int link_id) 5712 { 5713 *rtwsta_link = rtwsta->links[link_id]; 5714 return !!*rtwsta_link; 5715 } 5716 5717 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 5718 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5719 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 5720 5721 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 5722 { 5723 /* const after init, so no need to check if active first */ 5724 return rtwvif->links_inst[0].mac_id; 5725 } 5726 5727 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 5728 { 5729 /* const after init, so no need to check if active first */ 5730 return rtwvif->links_inst[0].port; 5731 } 5732 5733 static inline struct rtw89_vif_link * 5734 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 5735 { 5736 if (index >= rtwvif->links_inst_valid_num || 5737 !test_bit(index, rtwvif->links_inst_map)) 5738 return NULL; 5739 return &rtwvif->links_inst[index]; 5740 } 5741 5742 static inline 5743 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 5744 { 5745 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5746 5747 return rtwvif_link - rtwvif->links_inst; 5748 } 5749 5750 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 5751 { 5752 /* const after init, so no need to check if active first */ 5753 return rtwsta->links_inst[0].mac_id; 5754 } 5755 5756 static inline struct rtw89_sta_link * 5757 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 5758 { 5759 if (index >= rtwsta->links_inst_valid_num || 5760 !test_bit(index, rtwsta->links_inst_map)) 5761 return NULL; 5762 return &rtwsta->links_inst[index]; 5763 } 5764 5765 static inline 5766 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 5767 { 5768 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5769 5770 return rtwsta_link - rtwsta->links_inst; 5771 } 5772 5773 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5774 struct rtw89_core_tx_request *tx_req) 5775 { 5776 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5777 } 5778 5779 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5780 { 5781 rtwdev->hci.ops->reset(rtwdev); 5782 } 5783 5784 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5785 { 5786 return rtwdev->hci.ops->start(rtwdev); 5787 } 5788 5789 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5790 { 5791 rtwdev->hci.ops->stop(rtwdev); 5792 } 5793 5794 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5795 { 5796 return rtwdev->hci.ops->deinit(rtwdev); 5797 } 5798 5799 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5800 { 5801 rtwdev->hci.ops->pause(rtwdev, pause); 5802 } 5803 5804 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5805 { 5806 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5807 } 5808 5809 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5810 { 5811 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5812 } 5813 5814 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5815 { 5816 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5817 } 5818 5819 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5820 { 5821 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5822 } 5823 5824 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5825 { 5826 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5827 } 5828 5829 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5830 bool drop) 5831 { 5832 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5833 return; 5834 5835 if (rtwdev->hci.ops->flush_queues) 5836 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5837 } 5838 5839 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5840 { 5841 if (rtwdev->hci.ops->recovery_start) 5842 rtwdev->hci.ops->recovery_start(rtwdev); 5843 } 5844 5845 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5846 { 5847 if (rtwdev->hci.ops->recovery_complete) 5848 rtwdev->hci.ops->recovery_complete(rtwdev); 5849 } 5850 5851 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5852 { 5853 if (rtwdev->hci.ops->enable_intr) 5854 rtwdev->hci.ops->enable_intr(rtwdev); 5855 } 5856 5857 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5858 { 5859 if (rtwdev->hci.ops->disable_intr) 5860 rtwdev->hci.ops->disable_intr(rtwdev); 5861 } 5862 5863 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5864 { 5865 if (rtwdev->hci.ops->ctrl_txdma_ch) 5866 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5867 } 5868 5869 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5870 { 5871 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5872 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5873 } 5874 5875 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5876 { 5877 if (rtwdev->hci.ops->ctrl_trxhci) 5878 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5879 } 5880 5881 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5882 { 5883 int ret = 0; 5884 5885 if (rtwdev->hci.ops->poll_txdma_ch_idle) 5886 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 5887 return ret; 5888 } 5889 5890 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5891 { 5892 if (rtwdev->hci.ops->clr_idx_all) 5893 rtwdev->hci.ops->clr_idx_all(rtwdev); 5894 } 5895 5896 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 5897 { 5898 int ret = 0; 5899 5900 if (rtwdev->hci.ops->rst_bdram) 5901 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 5902 return ret; 5903 } 5904 5905 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 5906 { 5907 if (rtwdev->hci.ops->clear) 5908 rtwdev->hci.ops->clear(rtwdev, pdev); 5909 } 5910 5911 static inline 5912 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5913 { 5914 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5915 5916 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5917 } 5918 5919 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5920 { 5921 return rtwdev->hci.ops->read8(rtwdev, addr); 5922 } 5923 5924 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5925 { 5926 return rtwdev->hci.ops->read16(rtwdev, addr); 5927 } 5928 5929 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5930 { 5931 return rtwdev->hci.ops->read32(rtwdev, addr); 5932 } 5933 5934 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5935 { 5936 rtwdev->hci.ops->write8(rtwdev, addr, data); 5937 } 5938 5939 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5940 { 5941 rtwdev->hci.ops->write16(rtwdev, addr, data); 5942 } 5943 5944 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5945 { 5946 rtwdev->hci.ops->write32(rtwdev, addr, data); 5947 } 5948 5949 static inline void 5950 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5951 { 5952 u8 val; 5953 5954 val = rtw89_read8(rtwdev, addr); 5955 rtw89_write8(rtwdev, addr, val | bit); 5956 } 5957 5958 static inline void 5959 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5960 { 5961 u16 val; 5962 5963 val = rtw89_read16(rtwdev, addr); 5964 rtw89_write16(rtwdev, addr, val | bit); 5965 } 5966 5967 static inline void 5968 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5969 { 5970 u32 val; 5971 5972 val = rtw89_read32(rtwdev, addr); 5973 rtw89_write32(rtwdev, addr, val | bit); 5974 } 5975 5976 static inline void 5977 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5978 { 5979 u8 val; 5980 5981 val = rtw89_read8(rtwdev, addr); 5982 rtw89_write8(rtwdev, addr, val & ~bit); 5983 } 5984 5985 static inline void 5986 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5987 { 5988 u16 val; 5989 5990 val = rtw89_read16(rtwdev, addr); 5991 rtw89_write16(rtwdev, addr, val & ~bit); 5992 } 5993 5994 static inline void 5995 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5996 { 5997 u32 val; 5998 5999 val = rtw89_read32(rtwdev, addr); 6000 rtw89_write32(rtwdev, addr, val & ~bit); 6001 } 6002 6003 static inline u32 6004 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6005 { 6006 u32 shift = __ffs(mask); 6007 u32 orig; 6008 u32 ret; 6009 6010 orig = rtw89_read32(rtwdev, addr); 6011 ret = (orig & mask) >> shift; 6012 6013 return ret; 6014 } 6015 6016 static inline u16 6017 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6018 { 6019 u32 shift = __ffs(mask); 6020 u32 orig; 6021 u32 ret; 6022 6023 orig = rtw89_read16(rtwdev, addr); 6024 ret = (orig & mask) >> shift; 6025 6026 return ret; 6027 } 6028 6029 static inline u8 6030 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6031 { 6032 u32 shift = __ffs(mask); 6033 u32 orig; 6034 u32 ret; 6035 6036 orig = rtw89_read8(rtwdev, addr); 6037 ret = (orig & mask) >> shift; 6038 6039 return ret; 6040 } 6041 6042 static inline void 6043 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6044 { 6045 u32 shift = __ffs(mask); 6046 u32 orig; 6047 u32 set; 6048 6049 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6050 6051 orig = rtw89_read32(rtwdev, addr); 6052 set = (orig & ~mask) | ((data << shift) & mask); 6053 rtw89_write32(rtwdev, addr, set); 6054 } 6055 6056 static inline void 6057 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6058 { 6059 u32 shift; 6060 u16 orig, set; 6061 6062 mask &= 0xffff; 6063 shift = __ffs(mask); 6064 6065 orig = rtw89_read16(rtwdev, addr); 6066 set = (orig & ~mask) | ((data << shift) & mask); 6067 rtw89_write16(rtwdev, addr, set); 6068 } 6069 6070 static inline void 6071 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6072 { 6073 u32 shift; 6074 u8 orig, set; 6075 6076 mask &= 0xff; 6077 shift = __ffs(mask); 6078 6079 orig = rtw89_read8(rtwdev, addr); 6080 set = (orig & ~mask) | ((data << shift) & mask); 6081 rtw89_write8(rtwdev, addr, set); 6082 } 6083 6084 static inline u32 6085 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6086 u32 addr, u32 mask) 6087 { 6088 u32 val; 6089 6090 mutex_lock(&rtwdev->rf_mutex); 6091 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6092 mutex_unlock(&rtwdev->rf_mutex); 6093 6094 return val; 6095 } 6096 6097 static inline void 6098 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6099 u32 addr, u32 mask, u32 data) 6100 { 6101 mutex_lock(&rtwdev->rf_mutex); 6102 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6103 mutex_unlock(&rtwdev->rf_mutex); 6104 } 6105 6106 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6107 { 6108 void *p = rtwtxq; 6109 6110 return container_of(p, struct ieee80211_txq, drv_priv); 6111 } 6112 6113 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6114 struct ieee80211_txq *txq) 6115 { 6116 struct rtw89_txq *rtwtxq; 6117 6118 if (!txq) 6119 return; 6120 6121 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6122 INIT_LIST_HEAD(&rtwtxq->list); 6123 } 6124 6125 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6126 { 6127 void *p = rtwvif; 6128 6129 return container_of(p, struct ieee80211_vif, drv_priv); 6130 } 6131 6132 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6133 { 6134 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6135 } 6136 6137 static inline 6138 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6139 { 6140 return rtwvif_to_vif(rtwvif_link->rtwvif); 6141 } 6142 6143 static inline 6144 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6145 { 6146 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6147 } 6148 6149 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6150 { 6151 return (struct rtw89_vif *)vif->drv_priv; 6152 } 6153 6154 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6155 { 6156 return vif ? vif_to_rtwvif(vif) : NULL; 6157 } 6158 6159 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6160 { 6161 void *p = rtwsta; 6162 6163 return container_of(p, struct ieee80211_sta, drv_priv); 6164 } 6165 6166 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6167 { 6168 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6169 } 6170 6171 static inline 6172 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6173 { 6174 return rtwsta_to_sta(rtwsta_link->rtwsta); 6175 } 6176 6177 static inline 6178 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6179 { 6180 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6181 } 6182 6183 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6184 { 6185 return (struct rtw89_sta *)sta->drv_priv; 6186 } 6187 6188 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6189 { 6190 return sta ? sta_to_rtwsta(sta) : NULL; 6191 } 6192 6193 static inline struct ieee80211_bss_conf * 6194 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6195 { 6196 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6197 struct ieee80211_bss_conf *bss_conf; 6198 6199 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6200 if (unlikely(!bss_conf)) { 6201 *nolink = true; 6202 return &vif->bss_conf; 6203 } 6204 6205 *nolink = false; 6206 return bss_conf; 6207 } 6208 6209 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6210 ({ \ 6211 typeof(rtwvif_link) p = rtwvif_link; \ 6212 struct ieee80211_bss_conf *bss_conf; \ 6213 bool nolink; \ 6214 \ 6215 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6216 if (unlikely(nolink) && (assert)) \ 6217 rtw89_err(p->rtwvif->rtwdev, \ 6218 "%s: cannot find exact bss_conf for link_id %u\n",\ 6219 __func__, p->link_id); \ 6220 bss_conf; \ 6221 }) 6222 6223 static inline struct ieee80211_link_sta * 6224 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6225 { 6226 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6227 struct ieee80211_link_sta *link_sta; 6228 6229 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6230 if (unlikely(!link_sta)) { 6231 *nolink = true; 6232 return &sta->deflink; 6233 } 6234 6235 *nolink = false; 6236 return link_sta; 6237 } 6238 6239 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6240 ({ \ 6241 typeof(rtwsta_link) p = rtwsta_link; \ 6242 struct ieee80211_link_sta *link_sta; \ 6243 bool nolink; \ 6244 \ 6245 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6246 if (unlikely(nolink) && (assert)) \ 6247 rtw89_err(p->rtwsta->rtwdev, \ 6248 "%s: cannot find exact link_sta for link_id %u\n",\ 6249 __func__, p->link_id); \ 6250 link_sta; \ 6251 }) 6252 6253 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6254 { 6255 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6256 return RATE_INFO_BW_160; 6257 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6258 return RATE_INFO_BW_80; 6259 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6260 return RATE_INFO_BW_40; 6261 else 6262 return RATE_INFO_BW_20; 6263 } 6264 6265 static inline 6266 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6267 { 6268 switch (hw_band) { 6269 default: 6270 case RTW89_BAND_2G: 6271 return NL80211_BAND_2GHZ; 6272 case RTW89_BAND_5G: 6273 return NL80211_BAND_5GHZ; 6274 case RTW89_BAND_6G: 6275 return NL80211_BAND_6GHZ; 6276 } 6277 } 6278 6279 static inline 6280 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6281 { 6282 switch (nl_band) { 6283 default: 6284 case NL80211_BAND_2GHZ: 6285 return RTW89_BAND_2G; 6286 case NL80211_BAND_5GHZ: 6287 return RTW89_BAND_5G; 6288 case NL80211_BAND_6GHZ: 6289 return RTW89_BAND_6G; 6290 } 6291 } 6292 6293 static inline 6294 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6295 { 6296 switch (width) { 6297 default: 6298 WARN(1, "Not support bandwidth %d\n", width); 6299 fallthrough; 6300 case NL80211_CHAN_WIDTH_20_NOHT: 6301 case NL80211_CHAN_WIDTH_20: 6302 return RTW89_CHANNEL_WIDTH_20; 6303 case NL80211_CHAN_WIDTH_40: 6304 return RTW89_CHANNEL_WIDTH_40; 6305 case NL80211_CHAN_WIDTH_80: 6306 return RTW89_CHANNEL_WIDTH_80; 6307 case NL80211_CHAN_WIDTH_160: 6308 return RTW89_CHANNEL_WIDTH_160; 6309 } 6310 } 6311 6312 static inline 6313 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6314 { 6315 switch (rua) { 6316 default: 6317 WARN(1, "Invalid RU allocation: %d\n", rua); 6318 fallthrough; 6319 case 0 ... 36: 6320 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6321 case 37 ... 52: 6322 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6323 case 53 ... 60: 6324 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6325 case 61 ... 64: 6326 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6327 case 65 ... 66: 6328 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6329 case 67: 6330 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6331 case 68: 6332 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6333 } 6334 } 6335 6336 static inline 6337 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6338 struct rtw89_sta_link *rtwsta_link) 6339 { 6340 if (rtwsta_link) { 6341 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6342 6343 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6344 return &rtwsta_link->addr_cam; 6345 } 6346 return &rtwvif_link->addr_cam; 6347 } 6348 6349 static inline 6350 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6351 struct rtw89_sta_link *rtwsta_link) 6352 { 6353 if (rtwsta_link) { 6354 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6355 6356 if (sta->tdls) 6357 return &rtwsta_link->bssid_cam; 6358 } 6359 return &rtwvif_link->bssid_cam; 6360 } 6361 6362 static inline 6363 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6364 struct rtw89_channel_help_params *p, 6365 const struct rtw89_chan *chan, 6366 enum rtw89_mac_idx mac_idx, 6367 enum rtw89_phy_idx phy_idx) 6368 { 6369 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6370 mac_idx, phy_idx); 6371 } 6372 6373 static inline 6374 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6375 struct rtw89_channel_help_params *p, 6376 const struct rtw89_chan *chan, 6377 enum rtw89_mac_idx mac_idx, 6378 enum rtw89_phy_idx phy_idx) 6379 { 6380 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6381 mac_idx, phy_idx); 6382 } 6383 6384 static inline 6385 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6386 enum rtw89_chanctx_idx idx) 6387 { 6388 struct rtw89_hal *hal = &rtwdev->hal; 6389 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6390 6391 if (roc_idx == idx) 6392 return &hal->roc_chandef; 6393 6394 return &hal->chanctx[idx].chandef; 6395 } 6396 6397 static inline 6398 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6399 enum rtw89_chanctx_idx idx) 6400 { 6401 struct rtw89_hal *hal = &rtwdev->hal; 6402 6403 return &hal->chanctx[idx].chan; 6404 } 6405 6406 static inline 6407 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6408 enum rtw89_chanctx_idx idx) 6409 { 6410 struct rtw89_hal *hal = &rtwdev->hal; 6411 6412 return &hal->chanctx[idx].rcd; 6413 } 6414 6415 static inline 6416 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6417 { 6418 const struct rtw89_chanctx *chanctx = 6419 container_of_const(chan, struct rtw89_chanctx, chan); 6420 6421 return &chanctx->rcd; 6422 } 6423 6424 static inline 6425 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6426 { 6427 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6428 6429 if (rtwvif_link) 6430 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6431 else 6432 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6433 } 6434 6435 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6436 { 6437 const struct rtw89_chip_info *chip = rtwdev->chip; 6438 6439 if (chip->ops->fem_setup) 6440 chip->ops->fem_setup(rtwdev); 6441 } 6442 6443 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6444 { 6445 const struct rtw89_chip_info *chip = rtwdev->chip; 6446 6447 if (chip->ops->rfe_gpio) 6448 chip->ops->rfe_gpio(rtwdev); 6449 } 6450 6451 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6452 { 6453 const struct rtw89_chip_info *chip = rtwdev->chip; 6454 6455 if (chip->ops->rfk_hw_init) 6456 chip->ops->rfk_hw_init(rtwdev); 6457 } 6458 6459 static inline 6460 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6461 { 6462 const struct rtw89_chip_info *chip = rtwdev->chip; 6463 6464 if (chip->ops->bb_preinit) 6465 chip->ops->bb_preinit(rtwdev, phy_idx); 6466 } 6467 6468 static inline 6469 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6470 { 6471 const struct rtw89_chip_info *chip = rtwdev->chip; 6472 6473 if (!chip->ops->bb_postinit) 6474 return; 6475 6476 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6477 6478 if (rtwdev->dbcc_en) 6479 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6480 } 6481 6482 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6483 { 6484 const struct rtw89_chip_info *chip = rtwdev->chip; 6485 6486 if (chip->ops->bb_sethw) 6487 chip->ops->bb_sethw(rtwdev); 6488 } 6489 6490 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6491 { 6492 const struct rtw89_chip_info *chip = rtwdev->chip; 6493 6494 if (chip->ops->rfk_init) 6495 chip->ops->rfk_init(rtwdev); 6496 } 6497 6498 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6499 { 6500 const struct rtw89_chip_info *chip = rtwdev->chip; 6501 6502 if (chip->ops->rfk_init_late) 6503 chip->ops->rfk_init_late(rtwdev); 6504 } 6505 6506 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6507 struct rtw89_vif_link *rtwvif_link) 6508 { 6509 const struct rtw89_chip_info *chip = rtwdev->chip; 6510 6511 if (chip->ops->rfk_channel) 6512 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6513 } 6514 6515 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6516 enum rtw89_phy_idx phy_idx, 6517 const struct rtw89_chan *chan) 6518 { 6519 const struct rtw89_chip_info *chip = rtwdev->chip; 6520 6521 if (chip->ops->rfk_band_changed) 6522 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6523 } 6524 6525 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6526 struct rtw89_vif_link *rtwvif_link, bool start) 6527 { 6528 const struct rtw89_chip_info *chip = rtwdev->chip; 6529 6530 if (chip->ops->rfk_scan) 6531 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6532 } 6533 6534 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6535 { 6536 const struct rtw89_chip_info *chip = rtwdev->chip; 6537 6538 if (chip->ops->rfk_track) 6539 chip->ops->rfk_track(rtwdev); 6540 } 6541 6542 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6543 { 6544 const struct rtw89_chip_info *chip = rtwdev->chip; 6545 6546 if (!chip->ops->set_txpwr_ctrl) 6547 return; 6548 6549 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6550 if (rtwdev->dbcc_en) 6551 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6552 } 6553 6554 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6555 { 6556 const struct rtw89_chip_info *chip = rtwdev->chip; 6557 6558 if (chip->ops->power_trim) 6559 chip->ops->power_trim(rtwdev); 6560 } 6561 6562 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6563 enum rtw89_phy_idx phy_idx) 6564 { 6565 const struct rtw89_chip_info *chip = rtwdev->chip; 6566 6567 if (chip->ops->init_txpwr_unit) 6568 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6569 } 6570 6571 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6572 { 6573 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6574 if (rtwdev->dbcc_en) 6575 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6576 } 6577 6578 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6579 enum rtw89_rf_path rf_path) 6580 { 6581 const struct rtw89_chip_info *chip = rtwdev->chip; 6582 6583 if (!chip->ops->get_thermal) 6584 return 0x10; 6585 6586 return chip->ops->get_thermal(rtwdev, rf_path); 6587 } 6588 6589 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6590 struct rtw89_rx_phy_ppdu *phy_ppdu, 6591 struct ieee80211_rx_status *status) 6592 { 6593 const struct rtw89_chip_info *chip = rtwdev->chip; 6594 6595 if (chip->ops->query_ppdu) 6596 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6597 } 6598 6599 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 6600 struct rtw89_rx_phy_ppdu *phy_ppdu) 6601 { 6602 const struct rtw89_chip_info *chip = rtwdev->chip; 6603 6604 if (chip->ops->convert_rpl_to_rssi) 6605 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 6606 } 6607 6608 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6609 enum rtw89_phy_idx phy_idx) 6610 { 6611 const struct rtw89_chip_info *chip = rtwdev->chip; 6612 6613 if (chip->ops->ctrl_nbtg_bt_tx) 6614 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6615 } 6616 6617 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6618 { 6619 const struct rtw89_chip_info *chip = rtwdev->chip; 6620 6621 if (chip->ops->cfg_txrx_path) 6622 chip->ops->cfg_txrx_path(rtwdev); 6623 } 6624 6625 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 6626 enum rtw89_phy_idx phy_idx) 6627 { 6628 const struct rtw89_chip_info *chip = rtwdev->chip; 6629 6630 if (chip->ops->digital_pwr_comp) 6631 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 6632 } 6633 6634 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6635 const struct rtw89_txpwr_table *tbl) 6636 { 6637 tbl->load(rtwdev, tbl); 6638 } 6639 6640 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6641 { 6642 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6643 6644 return regd->txpwr_regd[band]; 6645 } 6646 6647 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6648 enum rtw89_phy_idx phy_idx) 6649 { 6650 const struct rtw89_chip_info *chip = rtwdev->chip; 6651 6652 if (chip->ops->ctrl_btg_bt_rx) 6653 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6654 } 6655 6656 static inline 6657 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6658 struct rtw89_rx_desc_info *desc_info, 6659 u8 *data, u32 data_offset) 6660 { 6661 const struct rtw89_chip_info *chip = rtwdev->chip; 6662 6663 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6664 } 6665 6666 static inline 6667 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6668 struct rtw89_tx_desc_info *desc_info, 6669 void *txdesc) 6670 { 6671 const struct rtw89_chip_info *chip = rtwdev->chip; 6672 6673 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6674 } 6675 6676 static inline 6677 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6678 struct rtw89_tx_desc_info *desc_info, 6679 void *txdesc) 6680 { 6681 const struct rtw89_chip_info *chip = rtwdev->chip; 6682 6683 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6684 } 6685 6686 static inline 6687 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6688 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6689 { 6690 const struct rtw89_chip_info *chip = rtwdev->chip; 6691 6692 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6693 } 6694 6695 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6696 { 6697 const struct rtw89_chip_info *chip = rtwdev->chip; 6698 6699 chip->ops->cfg_ctrl_path(rtwdev, wl); 6700 } 6701 6702 static inline 6703 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6704 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6705 { 6706 const struct rtw89_chip_info *chip = rtwdev->chip; 6707 6708 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6709 } 6710 6711 static inline 6712 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6713 { 6714 const struct rtw89_chip_info *chip = rtwdev->chip; 6715 6716 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6717 } 6718 6719 static inline 6720 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6721 struct rtw89_vif_link *rtwvif_link, 6722 struct rtw89_sta_link *rtwsta_link) 6723 { 6724 const struct rtw89_chip_info *chip = rtwdev->chip; 6725 6726 if (!chip->ops->h2c_dctl_sec_cam) 6727 return 0; 6728 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 6729 } 6730 6731 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6732 { 6733 __le16 fc = hdr->frame_control; 6734 6735 if (ieee80211_has_tods(fc)) 6736 return hdr->addr1; 6737 else if (ieee80211_has_fromds(fc)) 6738 return hdr->addr2; 6739 else 6740 return hdr->addr3; 6741 } 6742 6743 static inline 6744 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 6745 { 6746 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6747 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6748 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 6749 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6750 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 6751 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6752 return true; 6753 return false; 6754 } 6755 6756 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6757 enum rtw89_fw_type type) 6758 { 6759 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6760 6761 switch (type) { 6762 case RTW89_FW_WOWLAN: 6763 return &fw_info->wowlan; 6764 case RTW89_FW_LOGFMT: 6765 return &fw_info->log.suit; 6766 case RTW89_FW_BBMCU0: 6767 return &fw_info->bbmcu0; 6768 case RTW89_FW_BBMCU1: 6769 return &fw_info->bbmcu1; 6770 default: 6771 break; 6772 } 6773 6774 return &fw_info->normal; 6775 } 6776 6777 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6778 unsigned int length) 6779 { 6780 struct sk_buff *skb; 6781 6782 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6783 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6784 if (!skb) 6785 return NULL; 6786 6787 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6788 return skb; 6789 } 6790 6791 return dev_alloc_skb(length); 6792 } 6793 6794 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6795 struct rtw89_tx_skb_data *skb_data, 6796 bool tx_done) 6797 { 6798 struct rtw89_tx_wait_info *wait; 6799 6800 rcu_read_lock(); 6801 6802 wait = rcu_dereference(skb_data->wait); 6803 if (!wait) 6804 goto out; 6805 6806 wait->tx_done = tx_done; 6807 complete(&wait->completion); 6808 6809 out: 6810 rcu_read_unlock(); 6811 } 6812 6813 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6814 { 6815 switch (rtwdev->mlo_dbcc_mode) { 6816 case MLO_1_PLUS_1_1RF: 6817 case MLO_1_PLUS_1_2RF: 6818 case DBCC_LEGACY: 6819 return true; 6820 default: 6821 return false; 6822 } 6823 } 6824 6825 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 6826 { 6827 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6828 6829 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 6830 return true; 6831 6832 return false; 6833 } 6834 6835 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6836 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6837 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6838 struct sk_buff *skb, bool fwdl); 6839 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6840 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6841 int qsel, unsigned int timeout); 6842 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6843 struct rtw89_tx_desc_info *desc_info, 6844 void *txdesc); 6845 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6846 struct rtw89_tx_desc_info *desc_info, 6847 void *txdesc); 6848 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6849 struct rtw89_tx_desc_info *desc_info, 6850 void *txdesc); 6851 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6852 struct rtw89_tx_desc_info *desc_info, 6853 void *txdesc); 6854 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6855 struct rtw89_tx_desc_info *desc_info, 6856 void *txdesc); 6857 void rtw89_core_rx(struct rtw89_dev *rtwdev, 6858 struct rtw89_rx_desc_info *desc_info, 6859 struct sk_buff *skb); 6860 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 6861 struct rtw89_rx_desc_info *desc_info, 6862 u8 *data, u32 data_offset); 6863 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 6864 struct rtw89_rx_desc_info *desc_info, 6865 u8 *data, u32 data_offset); 6866 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 6867 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 6868 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 6869 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 6870 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 6871 struct rtw89_vif_link *rtwvif_link, 6872 struct rtw89_sta_link *rtwsta_link); 6873 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 6874 struct rtw89_vif_link *rtwvif_link, 6875 struct rtw89_sta_link *rtwsta_link); 6876 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 6877 struct rtw89_vif_link *rtwvif_link, 6878 struct rtw89_sta_link *rtwsta_link); 6879 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 6880 struct rtw89_vif_link *rtwvif_link, 6881 struct rtw89_sta_link *rtwsta_link); 6882 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 6883 struct rtw89_vif_link *rtwvif_link, 6884 struct rtw89_sta_link *rtwsta_link); 6885 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6886 struct ieee80211_sta *sta, 6887 struct cfg80211_tid_config *tid_config); 6888 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 6889 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 6890 int rtw89_core_init(struct rtw89_dev *rtwdev); 6891 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 6892 int rtw89_core_register(struct rtw89_dev *rtwdev); 6893 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 6894 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6895 u32 bus_data_size, 6896 const struct rtw89_chip_info *chip); 6897 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 6898 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 6899 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 6900 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6901 u8 mac_id, u8 port); 6902 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6903 struct rtw89_sta *rtwsta, u8 mac_id); 6904 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 6905 unsigned int link_id); 6906 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 6907 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 6908 unsigned int link_id); 6909 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 6910 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 6911 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 6912 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 6913 struct rtw89_chan *chan); 6914 int rtw89_set_channel(struct rtw89_dev *rtwdev); 6915 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 6916 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 6917 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 6918 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 6919 struct rtw89_sta_link *rtwsta_link, u8 tid, 6920 u8 *cam_idx); 6921 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 6922 struct rtw89_sta_link *rtwsta_link, u8 tid, 6923 u8 *cam_idx); 6924 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 6925 struct ieee80211_sta *sta); 6926 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 6927 struct ieee80211_sta *sta); 6928 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 6929 struct ieee80211_sta *sta); 6930 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 6931 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 6932 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 6933 struct rtw89_vif_link *rtwvif_link); 6934 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 6935 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 6936 int rtw89_regd_init(struct rtw89_dev *rtwdev, 6937 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 6938 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 6939 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 6940 struct rtw89_traffic_stats *stats); 6941 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 6942 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6943 const struct rtw89_completion_data *data); 6944 int rtw89_core_start(struct rtw89_dev *rtwdev); 6945 void rtw89_core_stop(struct rtw89_dev *rtwdev); 6946 void rtw89_core_update_beacon_work(struct work_struct *work); 6947 void rtw89_roc_work(struct work_struct *work); 6948 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6949 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6950 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 6951 const u8 *mac_addr, bool hw_scan); 6952 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6953 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 6954 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 6955 bool active); 6956 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 6957 struct rtw89_vif_link *rtwvif_link, 6958 struct ieee80211_bss_conf *bss_conf); 6959 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 6960 6961 #endif 6962