1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_fw_blacklist; 21 struct rtw89_efuse_block_cfg; 22 struct rtw89_h2c_rf_tssi; 23 struct rtw89_fw_txpwr_track_cfg; 24 struct rtw89_phy_rfk_log_fmt; 25 struct rtw89_debugfs; 26 struct rtw89_regd_data; 27 28 extern const struct ieee80211_ops rtw89_ops; 29 30 #define MASKBYTE0 0xff 31 #define MASKBYTE1 0xff00 32 #define MASKBYTE2 0xff0000 33 #define MASKBYTE3 0xff000000 34 #define MASKBYTE4 0xff00000000ULL 35 #define MASKHWORD 0xffff0000 36 #define MASKLWORD 0x0000ffff 37 #define MASKDWORD 0xffffffff 38 #define RFREG_MASK 0xfffff 39 #define INV_RF_DATA 0xffffffff 40 #define BYPASS_CR_DATA 0xbabecafe 41 42 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 43 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 44 #define CFO_TRACK_MAX_USER 64 45 #define MAX_RSSI 110 46 #define RSSI_FACTOR 1 47 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 48 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 49 #define DELTA_SWINGIDX_SIZE 30 50 51 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 52 #define RTW89_RADIOTAP_ROOM_EHT \ 53 (sizeof(struct ieee80211_radiotap_tlv) + \ 54 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 55 sizeof(struct ieee80211_radiotap_tlv) + \ 56 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 57 #define RTW89_RADIOTAP_ROOM \ 58 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 59 60 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 61 #define RTW89_HTC_VARIANT_HE 3 62 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 63 #define RTW89_HTC_VARIANT_HE_CID_OM 1 64 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 65 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 66 67 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 68 enum htc_om_channel_width { 69 HTC_OM_CHANNEL_WIDTH_20 = 0, 70 HTC_OM_CHANNEL_WIDTH_40 = 1, 71 HTC_OM_CHANNEL_WIDTH_80 = 2, 72 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 73 }; 74 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 75 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 76 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 77 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 78 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 79 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 80 81 #define RTW89_TF_PAD GENMASK(11, 0) 82 #define RTW89_TF_BASIC_USER_INFO_SZ 6 83 84 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 86 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 87 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 88 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 89 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 90 91 enum rtw89_subband { 92 RTW89_CH_2G = 0, 93 RTW89_CH_5G_BAND_1 = 1, 94 /* RTW89_CH_5G_BAND_2 = 2, unused */ 95 RTW89_CH_5G_BAND_3 = 3, 96 RTW89_CH_5G_BAND_4 = 4, 97 98 RTW89_CH_6G_BAND_IDX0, /* Low */ 99 RTW89_CH_6G_BAND_IDX1, /* Low */ 100 RTW89_CH_6G_BAND_IDX2, /* Mid */ 101 RTW89_CH_6G_BAND_IDX3, /* Mid */ 102 RTW89_CH_6G_BAND_IDX4, /* High */ 103 RTW89_CH_6G_BAND_IDX5, /* High */ 104 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 105 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 106 107 RTW89_SUBBAND_NR, 108 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 109 }; 110 111 enum rtw89_gain_offset { 112 RTW89_GAIN_OFFSET_2G_CCK, 113 RTW89_GAIN_OFFSET_2G_OFDM, 114 RTW89_GAIN_OFFSET_5G_LOW, 115 RTW89_GAIN_OFFSET_5G_MID, 116 RTW89_GAIN_OFFSET_5G_HIGH, 117 RTW89_GAIN_OFFSET_6G_L0, 118 RTW89_GAIN_OFFSET_6G_L1, 119 RTW89_GAIN_OFFSET_6G_M0, 120 RTW89_GAIN_OFFSET_6G_M1, 121 RTW89_GAIN_OFFSET_6G_H0, 122 RTW89_GAIN_OFFSET_6G_H1, 123 RTW89_GAIN_OFFSET_6G_UH0, 124 RTW89_GAIN_OFFSET_6G_UH1, 125 126 RTW89_GAIN_OFFSET_NR, 127 }; 128 129 enum rtw89_hci_type { 130 RTW89_HCI_TYPE_PCIE, 131 RTW89_HCI_TYPE_USB, 132 RTW89_HCI_TYPE_SDIO, 133 }; 134 135 enum rtw89_core_chip_id { 136 RTL8852A, 137 RTL8852B, 138 RTL8852BT, 139 RTL8852C, 140 RTL8851B, 141 RTL8922A, 142 }; 143 144 enum rtw89_chip_gen { 145 RTW89_CHIP_AX, 146 RTW89_CHIP_BE, 147 148 RTW89_CHIP_GEN_NUM, 149 }; 150 151 enum rtw89_cv { 152 CHIP_CAV, 153 CHIP_CBV, 154 CHIP_CCV, 155 CHIP_CDV, 156 CHIP_CEV, 157 CHIP_CFV, 158 CHIP_CV_MAX, 159 CHIP_CV_INVALID = CHIP_CV_MAX, 160 }; 161 162 enum rtw89_bacam_ver { 163 RTW89_BACAM_V0, 164 RTW89_BACAM_V1, 165 166 RTW89_BACAM_V0_EXT = 99, 167 }; 168 169 enum rtw89_core_tx_type { 170 RTW89_CORE_TX_TYPE_DATA, 171 RTW89_CORE_TX_TYPE_MGMT, 172 RTW89_CORE_TX_TYPE_FWCMD, 173 }; 174 175 enum rtw89_core_rx_type { 176 RTW89_CORE_RX_TYPE_WIFI = 0, 177 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 178 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 179 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 180 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 181 RTW89_CORE_RX_TYPE_SS2FW = 5, 182 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 183 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 184 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 185 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 186 RTW89_CORE_RX_TYPE_C2H = 10, 187 RTW89_CORE_RX_TYPE_CSI = 11, 188 RTW89_CORE_RX_TYPE_CQI = 12, 189 RTW89_CORE_RX_TYPE_H2C = 13, 190 RTW89_CORE_RX_TYPE_FWDL = 14, 191 }; 192 193 enum rtw89_txq_flags { 194 RTW89_TXQ_F_AMPDU = 0, 195 RTW89_TXQ_F_BLOCK_BA = 1, 196 RTW89_TXQ_F_FORBID_BA = 2, 197 }; 198 199 enum rtw89_net_type { 200 RTW89_NET_TYPE_NO_LINK = 0, 201 RTW89_NET_TYPE_AD_HOC = 1, 202 RTW89_NET_TYPE_INFRA = 2, 203 RTW89_NET_TYPE_AP_MODE = 3, 204 }; 205 206 enum rtw89_wifi_role { 207 RTW89_WIFI_ROLE_NONE, 208 RTW89_WIFI_ROLE_STATION, 209 RTW89_WIFI_ROLE_AP, 210 RTW89_WIFI_ROLE_AP_VLAN, 211 RTW89_WIFI_ROLE_ADHOC, 212 RTW89_WIFI_ROLE_ADHOC_MASTER, 213 RTW89_WIFI_ROLE_MESH_POINT, 214 RTW89_WIFI_ROLE_MONITOR, 215 RTW89_WIFI_ROLE_P2P_DEVICE, 216 RTW89_WIFI_ROLE_P2P_CLIENT, 217 RTW89_WIFI_ROLE_P2P_GO, 218 RTW89_WIFI_ROLE_NAN, 219 RTW89_WIFI_ROLE_MLME_MAX 220 }; 221 222 enum rtw89_upd_mode { 223 RTW89_ROLE_CREATE, 224 RTW89_ROLE_REMOVE, 225 RTW89_ROLE_TYPE_CHANGE, 226 RTW89_ROLE_INFO_CHANGE, 227 RTW89_ROLE_CON_DISCONN, 228 RTW89_ROLE_BAND_SW, 229 RTW89_ROLE_FW_RESTORE, 230 }; 231 232 enum rtw89_self_role { 233 RTW89_SELF_ROLE_CLIENT, 234 RTW89_SELF_ROLE_AP, 235 RTW89_SELF_ROLE_AP_CLIENT 236 }; 237 238 enum rtw89_msk_sO_el { 239 RTW89_NO_MSK, 240 RTW89_SMA, 241 RTW89_TMA, 242 RTW89_BSSID 243 }; 244 245 enum rtw89_sch_tx_sel { 246 RTW89_SCH_TX_SEL_ALL, 247 RTW89_SCH_TX_SEL_HIQ, 248 RTW89_SCH_TX_SEL_MG0, 249 RTW89_SCH_TX_SEL_MACID, 250 }; 251 252 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 253 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 254 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 255 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 256 */ 257 enum rtw89_add_cam_sec_mode { 258 RTW89_ADDR_CAM_SEC_NONE = 0, 259 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 260 RTW89_ADDR_CAM_SEC_NORMAL = 2, 261 RTW89_ADDR_CAM_SEC_4GROUP = 3, 262 }; 263 264 enum rtw89_sec_key_type { 265 RTW89_SEC_KEY_TYPE_NONE = 0, 266 RTW89_SEC_KEY_TYPE_WEP40 = 1, 267 RTW89_SEC_KEY_TYPE_WEP104 = 2, 268 RTW89_SEC_KEY_TYPE_TKIP = 3, 269 RTW89_SEC_KEY_TYPE_WAPI = 4, 270 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 271 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 272 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 273 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 274 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 275 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 276 }; 277 278 enum rtw89_port { 279 RTW89_PORT_0 = 0, 280 RTW89_PORT_1 = 1, 281 RTW89_PORT_2 = 2, 282 RTW89_PORT_3 = 3, 283 RTW89_PORT_4 = 4, 284 RTW89_PORT_NUM 285 }; 286 287 enum rtw89_band { 288 RTW89_BAND_2G = 0, 289 RTW89_BAND_5G = 1, 290 RTW89_BAND_6G = 2, 291 RTW89_BAND_NUM, 292 }; 293 294 enum rtw89_hw_rate { 295 RTW89_HW_RATE_CCK1 = 0x0, 296 RTW89_HW_RATE_CCK2 = 0x1, 297 RTW89_HW_RATE_CCK5_5 = 0x2, 298 RTW89_HW_RATE_CCK11 = 0x3, 299 RTW89_HW_RATE_OFDM6 = 0x4, 300 RTW89_HW_RATE_OFDM9 = 0x5, 301 RTW89_HW_RATE_OFDM12 = 0x6, 302 RTW89_HW_RATE_OFDM18 = 0x7, 303 RTW89_HW_RATE_OFDM24 = 0x8, 304 RTW89_HW_RATE_OFDM36 = 0x9, 305 RTW89_HW_RATE_OFDM48 = 0xA, 306 RTW89_HW_RATE_OFDM54 = 0xB, 307 RTW89_HW_RATE_MCS0 = 0x80, 308 RTW89_HW_RATE_MCS1 = 0x81, 309 RTW89_HW_RATE_MCS2 = 0x82, 310 RTW89_HW_RATE_MCS3 = 0x83, 311 RTW89_HW_RATE_MCS4 = 0x84, 312 RTW89_HW_RATE_MCS5 = 0x85, 313 RTW89_HW_RATE_MCS6 = 0x86, 314 RTW89_HW_RATE_MCS7 = 0x87, 315 RTW89_HW_RATE_MCS8 = 0x88, 316 RTW89_HW_RATE_MCS9 = 0x89, 317 RTW89_HW_RATE_MCS10 = 0x8A, 318 RTW89_HW_RATE_MCS11 = 0x8B, 319 RTW89_HW_RATE_MCS12 = 0x8C, 320 RTW89_HW_RATE_MCS13 = 0x8D, 321 RTW89_HW_RATE_MCS14 = 0x8E, 322 RTW89_HW_RATE_MCS15 = 0x8F, 323 RTW89_HW_RATE_MCS16 = 0x90, 324 RTW89_HW_RATE_MCS17 = 0x91, 325 RTW89_HW_RATE_MCS18 = 0x92, 326 RTW89_HW_RATE_MCS19 = 0x93, 327 RTW89_HW_RATE_MCS20 = 0x94, 328 RTW89_HW_RATE_MCS21 = 0x95, 329 RTW89_HW_RATE_MCS22 = 0x96, 330 RTW89_HW_RATE_MCS23 = 0x97, 331 RTW89_HW_RATE_MCS24 = 0x98, 332 RTW89_HW_RATE_MCS25 = 0x99, 333 RTW89_HW_RATE_MCS26 = 0x9A, 334 RTW89_HW_RATE_MCS27 = 0x9B, 335 RTW89_HW_RATE_MCS28 = 0x9C, 336 RTW89_HW_RATE_MCS29 = 0x9D, 337 RTW89_HW_RATE_MCS30 = 0x9E, 338 RTW89_HW_RATE_MCS31 = 0x9F, 339 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 340 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 341 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 342 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 343 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 344 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 345 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 346 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 347 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 348 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 349 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 350 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 351 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 352 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 353 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 354 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 355 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 356 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 357 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 358 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 359 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 360 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 361 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 362 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 363 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 364 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 365 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 366 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 367 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 368 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 369 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 370 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 371 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 372 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 373 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 374 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 375 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 376 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 377 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 378 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 379 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 380 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 381 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 382 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 383 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 384 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 385 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 386 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 387 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 388 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 389 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 390 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 391 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 392 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 393 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 394 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 395 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 396 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 397 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 398 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 399 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 400 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 401 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 402 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 403 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 404 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 405 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 406 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 407 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 408 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 409 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 410 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 411 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 412 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 413 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 414 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 415 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 416 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 417 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 418 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 419 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 420 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 421 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 422 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 423 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 424 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 425 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 426 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 427 428 RTW89_HW_RATE_V1_MCS0 = 0x100, 429 RTW89_HW_RATE_V1_MCS1 = 0x101, 430 RTW89_HW_RATE_V1_MCS2 = 0x102, 431 RTW89_HW_RATE_V1_MCS3 = 0x103, 432 RTW89_HW_RATE_V1_MCS4 = 0x104, 433 RTW89_HW_RATE_V1_MCS5 = 0x105, 434 RTW89_HW_RATE_V1_MCS6 = 0x106, 435 RTW89_HW_RATE_V1_MCS7 = 0x107, 436 RTW89_HW_RATE_V1_MCS8 = 0x108, 437 RTW89_HW_RATE_V1_MCS9 = 0x109, 438 RTW89_HW_RATE_V1_MCS10 = 0x10A, 439 RTW89_HW_RATE_V1_MCS11 = 0x10B, 440 RTW89_HW_RATE_V1_MCS12 = 0x10C, 441 RTW89_HW_RATE_V1_MCS13 = 0x10D, 442 RTW89_HW_RATE_V1_MCS14 = 0x10E, 443 RTW89_HW_RATE_V1_MCS15 = 0x10F, 444 RTW89_HW_RATE_V1_MCS16 = 0x110, 445 RTW89_HW_RATE_V1_MCS17 = 0x111, 446 RTW89_HW_RATE_V1_MCS18 = 0x112, 447 RTW89_HW_RATE_V1_MCS19 = 0x113, 448 RTW89_HW_RATE_V1_MCS20 = 0x114, 449 RTW89_HW_RATE_V1_MCS21 = 0x115, 450 RTW89_HW_RATE_V1_MCS22 = 0x116, 451 RTW89_HW_RATE_V1_MCS23 = 0x117, 452 RTW89_HW_RATE_V1_MCS24 = 0x118, 453 RTW89_HW_RATE_V1_MCS25 = 0x119, 454 RTW89_HW_RATE_V1_MCS26 = 0x11A, 455 RTW89_HW_RATE_V1_MCS27 = 0x11B, 456 RTW89_HW_RATE_V1_MCS28 = 0x11C, 457 RTW89_HW_RATE_V1_MCS29 = 0x11D, 458 RTW89_HW_RATE_V1_MCS30 = 0x11E, 459 RTW89_HW_RATE_V1_MCS31 = 0x11F, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 469 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 470 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 471 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 481 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 482 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 483 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 493 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 494 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 495 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 505 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 506 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 507 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 517 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 518 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 519 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 529 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 530 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 531 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 541 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 542 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 543 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 553 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 554 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 555 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 570 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 571 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 583 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 584 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 585 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 597 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 598 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 599 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 611 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 612 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 613 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 614 615 RTW89_HW_RATE_NR, 616 RTW89_HW_RATE_INVAL, 617 618 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 619 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 620 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 621 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 622 }; 623 624 /* 2G channels, 625 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 626 */ 627 #define RTW89_2G_CH_NUM 14 628 629 /* 5G channels, 630 * 36, 38, 40, 42, 44, 46, 48, 50, 631 * 52, 54, 56, 58, 60, 62, 64, 632 * 100, 102, 104, 106, 108, 110, 112, 114, 633 * 116, 118, 120, 122, 124, 126, 128, 130, 634 * 132, 134, 136, 138, 140, 142, 144, 635 * 149, 151, 153, 155, 157, 159, 161, 163, 636 * 165, 167, 169, 171, 173, 175, 177 637 */ 638 #define RTW89_5G_CH_NUM 53 639 640 /* 6G channels, 641 * 1, 3, 5, 7, 9, 11, 13, 15, 642 * 17, 19, 21, 23, 25, 27, 29, 33, 643 * 35, 37, 39, 41, 43, 45, 47, 49, 644 * 51, 53, 55, 57, 59, 61, 65, 67, 645 * 69, 71, 73, 75, 77, 79, 81, 83, 646 * 85, 87, 89, 91, 93, 97, 99, 101, 647 * 103, 105, 107, 109, 111, 113, 115, 117, 648 * 119, 121, 123, 125, 129, 131, 133, 135, 649 * 137, 139, 141, 143, 145, 147, 149, 151, 650 * 153, 155, 157, 161, 163, 165, 167, 169, 651 * 171, 173, 175, 177, 179, 181, 183, 185, 652 * 187, 189, 193, 195, 197, 199, 201, 203, 653 * 205, 207, 209, 211, 213, 215, 217, 219, 654 * 221, 225, 227, 229, 231, 233, 235, 237, 655 * 239, 241, 243, 245, 247, 249, 251, 253, 656 */ 657 #define RTW89_6G_CH_NUM 120 658 659 enum rtw89_rate_section { 660 RTW89_RS_CCK, 661 RTW89_RS_OFDM, 662 RTW89_RS_MCS, /* for HT/VHT/HE */ 663 RTW89_RS_HEDCM, 664 RTW89_RS_OFFSET, 665 RTW89_RS_NUM, 666 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 667 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 668 }; 669 670 enum rtw89_rate_offset_indexes { 671 RTW89_RATE_OFFSET_HE, 672 RTW89_RATE_OFFSET_VHT, 673 RTW89_RATE_OFFSET_HT, 674 RTW89_RATE_OFFSET_OFDM, 675 RTW89_RATE_OFFSET_CCK, 676 RTW89_RATE_OFFSET_DLRU_EHT, 677 RTW89_RATE_OFFSET_DLRU_HE, 678 RTW89_RATE_OFFSET_EHT, 679 __RTW89_RATE_OFFSET_NUM, 680 681 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 682 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 683 }; 684 685 enum rtw89_rate_num { 686 RTW89_RATE_CCK_NUM = 4, 687 RTW89_RATE_OFDM_NUM = 8, 688 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 689 690 RTW89_RATE_MCS_NUM_AX = 12, 691 RTW89_RATE_MCS_NUM_BE = 16, 692 __RTW89_RATE_MCS_NUM = 16, 693 }; 694 695 enum rtw89_nss { 696 RTW89_NSS_1 = 0, 697 RTW89_NSS_2 = 1, 698 /* HE DCM only support 1ss and 2ss */ 699 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 700 RTW89_NSS_3 = 2, 701 RTW89_NSS_4 = 3, 702 RTW89_NSS_NUM, 703 }; 704 705 enum rtw89_ntx { 706 RTW89_1TX = 0, 707 RTW89_2TX = 1, 708 RTW89_NTX_NUM, 709 }; 710 711 enum rtw89_beamforming_type { 712 RTW89_NONBF = 0, 713 RTW89_BF = 1, 714 RTW89_BF_NUM, 715 }; 716 717 enum rtw89_ofdma_type { 718 RTW89_NON_OFDMA = 0, 719 RTW89_OFDMA = 1, 720 RTW89_OFDMA_NUM, 721 }; 722 723 /* neither insert new in the middle, nor change any given definition */ 724 enum rtw89_regulation_type { 725 RTW89_WW = 0, 726 RTW89_ETSI = 1, 727 RTW89_FCC = 2, 728 RTW89_MKK = 3, 729 RTW89_NA = 4, 730 RTW89_IC = 5, 731 RTW89_KCC = 6, 732 RTW89_ACMA = 7, 733 RTW89_NCC = 8, 734 RTW89_MEXICO = 9, 735 RTW89_CHILE = 10, 736 RTW89_UKRAINE = 11, 737 RTW89_CN = 12, 738 RTW89_QATAR = 13, 739 RTW89_UK = 14, 740 RTW89_THAILAND = 15, 741 RTW89_REGD_NUM, 742 }; 743 744 enum rtw89_reg_6ghz_power { 745 RTW89_REG_6GHZ_POWER_VLP = 0, 746 RTW89_REG_6GHZ_POWER_LPI = 1, 747 RTW89_REG_6GHZ_POWER_STD = 2, 748 749 NUM_OF_RTW89_REG_6GHZ_POWER, 750 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 751 }; 752 753 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 754 755 /* calculate based on ieee80211 Transmit Power Envelope */ 756 struct rtw89_reg_6ghz_tpe { 757 bool valid; 758 s8 constraint; /* unit: dBm */ 759 }; 760 761 enum rtw89_fw_pkt_ofld_type { 762 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 763 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 764 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 765 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 766 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 767 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 768 RTW89_PKT_OFLD_TYPE_NDP = 6, 769 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 770 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 771 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 772 RTW89_PKT_OFLD_TYPE_NUM, 773 }; 774 775 struct rtw89_txpwr_byrate { 776 s8 cck[RTW89_RATE_CCK_NUM]; 777 s8 ofdm[RTW89_RATE_OFDM_NUM]; 778 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 779 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 780 s8 offset[__RTW89_RATE_OFFSET_NUM]; 781 s8 trap; 782 }; 783 784 struct rtw89_rate_desc { 785 enum rtw89_nss nss; 786 enum rtw89_rate_section rs; 787 enum rtw89_ofdma_type ofdma; 788 u8 idx; 789 }; 790 791 #define PHY_STS_HDR_LEN 8 792 #define RF_PATH_MAX 4 793 #define RTW89_MAX_PPDU_CNT 8 794 struct rtw89_rx_phy_ppdu { 795 void *buf; 796 u32 len; 797 u8 rssi_avg; 798 u8 rssi[RF_PATH_MAX]; 799 u8 mac_id; 800 u8 chan_idx; 801 u8 ie; 802 u16 rate; 803 u8 rpl_avg; 804 u8 rpl_path[RF_PATH_MAX]; 805 u8 rpl_fd[RF_PATH_MAX]; 806 u8 bw_idx; 807 u8 rx_path_en; 808 struct { 809 bool has; 810 u8 avg_snr; 811 u8 evm_max; 812 u8 evm_min; 813 } ofdm; 814 bool has_data; 815 bool has_bcn; 816 bool ldpc; 817 bool stbc; 818 bool to_self; 819 bool valid; 820 bool hdr_2_en; 821 }; 822 823 enum rtw89_mac_idx { 824 RTW89_MAC_0 = 0, 825 RTW89_MAC_1 = 1, 826 RTW89_MAC_NUM, 827 }; 828 829 enum rtw89_phy_idx { 830 RTW89_PHY_0 = 0, 831 RTW89_PHY_1 = 1, 832 RTW89_PHY_NUM, 833 }; 834 835 #define __RTW89_MLD_MAX_LINK_NUM 2 836 #define RTW89_MLD_NON_STA_LINK_NUM 1 837 838 enum rtw89_chanctx_idx { 839 RTW89_CHANCTX_0 = 0, 840 RTW89_CHANCTX_1 = 1, 841 842 NUM_OF_RTW89_CHANCTX, 843 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 844 }; 845 846 enum rtw89_rf_path { 847 RF_PATH_A = 0, 848 RF_PATH_B = 1, 849 RF_PATH_C = 2, 850 RF_PATH_D = 3, 851 RF_PATH_AB, 852 RF_PATH_AC, 853 RF_PATH_AD, 854 RF_PATH_BC, 855 RF_PATH_BD, 856 RF_PATH_CD, 857 RF_PATH_ABC, 858 RF_PATH_ABD, 859 RF_PATH_ACD, 860 RF_PATH_BCD, 861 RF_PATH_ABCD, 862 }; 863 864 enum rtw89_rf_path_bit { 865 RF_A = BIT(0), 866 RF_B = BIT(1), 867 RF_C = BIT(2), 868 RF_D = BIT(3), 869 870 RF_AB = (RF_A | RF_B), 871 RF_AC = (RF_A | RF_C), 872 RF_AD = (RF_A | RF_D), 873 RF_BC = (RF_B | RF_C), 874 RF_BD = (RF_B | RF_D), 875 RF_CD = (RF_C | RF_D), 876 877 RF_ABC = (RF_A | RF_B | RF_C), 878 RF_ABD = (RF_A | RF_B | RF_D), 879 RF_ACD = (RF_A | RF_C | RF_D), 880 RF_BCD = (RF_B | RF_C | RF_D), 881 882 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 883 }; 884 885 enum rtw89_bandwidth { 886 RTW89_CHANNEL_WIDTH_20 = 0, 887 RTW89_CHANNEL_WIDTH_40 = 1, 888 RTW89_CHANNEL_WIDTH_80 = 2, 889 RTW89_CHANNEL_WIDTH_160 = 3, 890 RTW89_CHANNEL_WIDTH_320 = 4, 891 892 /* keep index order above */ 893 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 894 895 RTW89_CHANNEL_WIDTH_80_80 = 5, 896 RTW89_CHANNEL_WIDTH_5 = 6, 897 RTW89_CHANNEL_WIDTH_10 = 7, 898 }; 899 900 enum rtw89_ps_mode { 901 RTW89_PS_MODE_NONE = 0, 902 RTW89_PS_MODE_RFOFF = 1, 903 RTW89_PS_MODE_CLK_GATED = 2, 904 RTW89_PS_MODE_PWR_GATED = 3, 905 }; 906 907 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 908 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 909 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 910 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 911 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 912 913 enum rtw89_pe_duration { 914 RTW89_PE_DURATION_0 = 0, 915 RTW89_PE_DURATION_8 = 1, 916 RTW89_PE_DURATION_16 = 2, 917 RTW89_PE_DURATION_16_20 = 3, 918 }; 919 920 enum rtw89_ru_bandwidth { 921 RTW89_RU26 = 0, 922 RTW89_RU52 = 1, 923 RTW89_RU106 = 2, 924 RTW89_RU52_26 = 3, 925 RTW89_RU106_26 = 4, 926 RTW89_RU_NUM, 927 }; 928 929 enum rtw89_sc_offset { 930 RTW89_SC_DONT_CARE = 0, 931 RTW89_SC_20_UPPER = 1, 932 RTW89_SC_20_LOWER = 2, 933 RTW89_SC_20_UPMOST = 3, 934 RTW89_SC_20_LOWEST = 4, 935 RTW89_SC_20_UP2X = 5, 936 RTW89_SC_20_LOW2X = 6, 937 RTW89_SC_20_UP3X = 7, 938 RTW89_SC_20_LOW3X = 8, 939 RTW89_SC_40_UPPER = 9, 940 RTW89_SC_40_LOWER = 10, 941 }; 942 943 /* only mgd features can be added to the enum */ 944 enum rtw89_wow_flags { 945 RTW89_WOW_FLAG_EN_MAGIC_PKT, 946 RTW89_WOW_FLAG_EN_REKEY_PKT, 947 RTW89_WOW_FLAG_EN_DISCONNECT, 948 RTW89_WOW_FLAG_EN_PATTERN, 949 RTW89_WOW_FLAG_NUM, 950 }; 951 952 struct rtw89_chan { 953 u8 channel; 954 u8 primary_channel; 955 enum rtw89_band band_type; 956 enum rtw89_bandwidth band_width; 957 958 /* The follow-up are derived from the above. We must ensure that it 959 * is assigned correctly in rtw89_chan_create() if new one is added. 960 */ 961 u32 freq; 962 enum rtw89_subband subband_type; 963 enum rtw89_sc_offset pri_ch_idx; 964 u8 pri_sb_idx; 965 }; 966 967 struct rtw89_chan_rcd { 968 u8 prev_primary_channel; 969 enum rtw89_band prev_band_type; 970 bool band_changed; 971 }; 972 973 struct rtw89_channel_help_params { 974 u32 tx_en; 975 }; 976 977 struct rtw89_port_reg { 978 u32 port_cfg; 979 u32 tbtt_prohib; 980 u32 bcn_area; 981 u32 bcn_early; 982 u32 tbtt_early; 983 u32 tbtt_agg; 984 u32 bcn_space; 985 u32 bcn_forcetx; 986 u32 bcn_err_cnt; 987 u32 bcn_err_flag; 988 u32 dtim_ctrl; 989 u32 tbtt_shift; 990 u32 bcn_cnt_tmr; 991 u32 tsftr_l; 992 u32 tsftr_h; 993 u32 md_tsft; 994 u32 bss_color; 995 u32 mbssid; 996 u32 mbssid_drop; 997 u32 tsf_sync; 998 u32 ptcl_dbg; 999 u32 ptcl_dbg_info; 1000 u32 bcn_drop_all; 1001 u32 hiq_win[RTW89_PORT_NUM]; 1002 }; 1003 1004 struct rtw89_txwd_body { 1005 __le32 dword0; 1006 __le32 dword1; 1007 __le32 dword2; 1008 __le32 dword3; 1009 __le32 dword4; 1010 __le32 dword5; 1011 } __packed; 1012 1013 struct rtw89_txwd_body_v1 { 1014 __le32 dword0; 1015 __le32 dword1; 1016 __le32 dword2; 1017 __le32 dword3; 1018 __le32 dword4; 1019 __le32 dword5; 1020 __le32 dword6; 1021 __le32 dword7; 1022 } __packed; 1023 1024 struct rtw89_txwd_body_v2 { 1025 __le32 dword0; 1026 __le32 dword1; 1027 __le32 dword2; 1028 __le32 dword3; 1029 __le32 dword4; 1030 __le32 dword5; 1031 __le32 dword6; 1032 __le32 dword7; 1033 } __packed; 1034 1035 struct rtw89_txwd_info { 1036 __le32 dword0; 1037 __le32 dword1; 1038 __le32 dword2; 1039 __le32 dword3; 1040 __le32 dword4; 1041 __le32 dword5; 1042 } __packed; 1043 1044 struct rtw89_txwd_info_v2 { 1045 __le32 dword0; 1046 __le32 dword1; 1047 __le32 dword2; 1048 __le32 dword3; 1049 __le32 dword4; 1050 __le32 dword5; 1051 __le32 dword6; 1052 __le32 dword7; 1053 } __packed; 1054 1055 struct rtw89_rx_desc_info { 1056 u16 pkt_size; 1057 u8 pkt_type; 1058 u8 drv_info_size; 1059 u8 phy_rpt_size; 1060 u8 hdr_cnv_size; 1061 u8 shift; 1062 u8 wl_hd_iv_len; 1063 bool long_rxdesc; 1064 bool bb_sel; 1065 bool mac_info_valid; 1066 u16 data_rate; 1067 u8 gi_ltf; 1068 u8 bw; 1069 u32 free_run_cnt; 1070 u8 user_id; 1071 bool sr_en; 1072 u8 ppdu_cnt; 1073 u8 ppdu_type; 1074 bool icv_err; 1075 bool crc32_err; 1076 bool hw_dec; 1077 bool sw_dec; 1078 bool addr1_match; 1079 u8 frag; 1080 u16 seq; 1081 u8 frame_type; 1082 u8 rx_pl_id; 1083 bool addr_cam_valid; 1084 u8 addr_cam_id; 1085 u8 sec_cam_id; 1086 u8 mac_id; 1087 u16 offset; 1088 u16 rxd_len; 1089 bool ready; 1090 u16 rssi; 1091 }; 1092 1093 struct rtw89_rxdesc_short { 1094 __le32 dword0; 1095 __le32 dword1; 1096 __le32 dword2; 1097 __le32 dword3; 1098 } __packed; 1099 1100 struct rtw89_rxdesc_short_v2 { 1101 __le32 dword0; 1102 __le32 dword1; 1103 __le32 dword2; 1104 __le32 dword3; 1105 __le32 dword4; 1106 __le32 dword5; 1107 } __packed; 1108 1109 struct rtw89_rxdesc_long { 1110 __le32 dword0; 1111 __le32 dword1; 1112 __le32 dword2; 1113 __le32 dword3; 1114 __le32 dword4; 1115 __le32 dword5; 1116 __le32 dword6; 1117 __le32 dword7; 1118 } __packed; 1119 1120 struct rtw89_rxdesc_long_v2 { 1121 __le32 dword0; 1122 __le32 dword1; 1123 __le32 dword2; 1124 __le32 dword3; 1125 __le32 dword4; 1126 __le32 dword5; 1127 __le32 dword6; 1128 __le32 dword7; 1129 __le32 dword8; 1130 __le32 dword9; 1131 } __packed; 1132 1133 struct rtw89_rxdesc_phy_rpt_v2 { 1134 __le32 dword0; 1135 __le32 dword1; 1136 } __packed; 1137 1138 struct rtw89_tx_desc_info { 1139 u16 pkt_size; 1140 u8 wp_offset; 1141 u8 mac_id; 1142 u8 qsel; 1143 u8 ch_dma; 1144 u8 hdr_llc_len; 1145 bool is_bmc; 1146 bool en_wd_info; 1147 bool wd_page; 1148 bool use_rate; 1149 bool dis_data_fb; 1150 bool tid_indicate; 1151 bool agg_en; 1152 bool bk; 1153 u8 ampdu_density; 1154 u8 ampdu_num; 1155 bool sec_en; 1156 u8 addr_info_nr; 1157 u8 sec_keyid; 1158 u8 sec_type; 1159 u8 sec_cam_idx; 1160 u8 sec_seq[6]; 1161 u16 data_rate; 1162 u16 data_retry_lowest_rate; 1163 bool fw_dl; 1164 u16 seq; 1165 bool a_ctrl_bsr; 1166 u8 hw_ssn_sel; 1167 #define RTW89_MGMT_HW_SSN_SEL 1 1168 u8 hw_seq_mode; 1169 #define RTW89_MGMT_HW_SEQ_MODE 1 1170 bool hiq; 1171 u8 port; 1172 bool er_cap; 1173 bool stbc; 1174 bool ldpc; 1175 bool upd_wlan_hdr; 1176 bool mlo; 1177 }; 1178 1179 struct rtw89_core_tx_request { 1180 enum rtw89_core_tx_type tx_type; 1181 1182 struct sk_buff *skb; 1183 struct ieee80211_vif *vif; 1184 struct ieee80211_sta *sta; 1185 struct rtw89_vif_link *rtwvif_link; 1186 struct rtw89_sta_link *rtwsta_link; 1187 struct rtw89_tx_desc_info desc_info; 1188 }; 1189 1190 struct rtw89_txq { 1191 struct list_head list; 1192 unsigned long flags; 1193 int wait_cnt; 1194 }; 1195 1196 struct rtw89_mac_ax_gnt { 1197 u8 gnt_bt_sw_en; 1198 u8 gnt_bt; 1199 u8 gnt_wl_sw_en; 1200 u8 gnt_wl; 1201 } __packed; 1202 1203 struct rtw89_mac_ax_wl_act { 1204 u8 wlan_act_en; 1205 u8 wlan_act; 1206 }; 1207 1208 #define RTW89_MAC_AX_COEX_GNT_NR 2 1209 struct rtw89_mac_ax_coex_gnt { 1210 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1211 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1212 }; 1213 1214 enum rtw89_btc_ncnt { 1215 BTC_NCNT_POWER_ON = 0x0, 1216 BTC_NCNT_POWER_OFF, 1217 BTC_NCNT_INIT_COEX, 1218 BTC_NCNT_SCAN_START, 1219 BTC_NCNT_SCAN_FINISH, 1220 BTC_NCNT_SPECIAL_PACKET, 1221 BTC_NCNT_SWITCH_BAND, 1222 BTC_NCNT_RFK_TIMEOUT, 1223 BTC_NCNT_SHOW_COEX_INFO, 1224 BTC_NCNT_ROLE_INFO, 1225 BTC_NCNT_CONTROL, 1226 BTC_NCNT_RADIO_STATE, 1227 BTC_NCNT_CUSTOMERIZE, 1228 BTC_NCNT_WL_RFK, 1229 BTC_NCNT_WL_STA, 1230 BTC_NCNT_WL_STA_LAST, 1231 BTC_NCNT_FWINFO, 1232 BTC_NCNT_TIMER, 1233 BTC_NCNT_SWITCH_CHBW, 1234 BTC_NCNT_RESUME_DL_FW, 1235 BTC_NCNT_COUNTRYCODE, 1236 BTC_NCNT_NUM, 1237 }; 1238 1239 enum rtw89_btc_btinfo { 1240 BTC_BTINFO_L0 = 0, 1241 BTC_BTINFO_L1, 1242 BTC_BTINFO_L2, 1243 BTC_BTINFO_L3, 1244 BTC_BTINFO_H0, 1245 BTC_BTINFO_H1, 1246 BTC_BTINFO_H2, 1247 BTC_BTINFO_H3, 1248 BTC_BTINFO_MAX 1249 }; 1250 1251 enum rtw89_btc_dcnt { 1252 BTC_DCNT_RUN = 0x0, 1253 BTC_DCNT_CX_RUNINFO, 1254 BTC_DCNT_RPT, 1255 BTC_DCNT_RPT_HANG, 1256 BTC_DCNT_CYCLE, 1257 BTC_DCNT_CYCLE_HANG, 1258 BTC_DCNT_W1, 1259 BTC_DCNT_W1_HANG, 1260 BTC_DCNT_B1, 1261 BTC_DCNT_B1_HANG, 1262 BTC_DCNT_TDMA_NONSYNC, 1263 BTC_DCNT_SLOT_NONSYNC, 1264 BTC_DCNT_BTCNT_HANG, 1265 BTC_DCNT_BTTX_HANG, 1266 BTC_DCNT_WL_SLOT_DRIFT, 1267 BTC_DCNT_WL_STA_LAST, 1268 BTC_DCNT_BT_SLOT_DRIFT, 1269 BTC_DCNT_BT_SLOT_FLOOD, 1270 BTC_DCNT_FDDT_TRIG, 1271 BTC_DCNT_E2G, 1272 BTC_DCNT_E2G_HANG, 1273 BTC_DCNT_WL_FW_VER_MATCH, 1274 BTC_DCNT_NULL_TX_FAIL, 1275 BTC_DCNT_WL_STA_NTFY, 1276 BTC_DCNT_NUM, 1277 }; 1278 1279 enum rtw89_btc_wl_state_cnt { 1280 BTC_WCNT_SCANAP = 0x0, 1281 BTC_WCNT_DHCP, 1282 BTC_WCNT_EAPOL, 1283 BTC_WCNT_ARP, 1284 BTC_WCNT_SCBDUPDATE, 1285 BTC_WCNT_RFK_REQ, 1286 BTC_WCNT_RFK_GO, 1287 BTC_WCNT_RFK_REJECT, 1288 BTC_WCNT_RFK_TIMEOUT, 1289 BTC_WCNT_CH_UPDATE, 1290 BTC_WCNT_DBCC_ALL_2G, 1291 BTC_WCNT_DBCC_CHG, 1292 BTC_WCNT_RX_OK_LAST, 1293 BTC_WCNT_RX_OK_LAST2S, 1294 BTC_WCNT_RX_ERR_LAST, 1295 BTC_WCNT_RX_ERR_LAST2S, 1296 BTC_WCNT_RX_LAST, 1297 BTC_WCNT_NUM 1298 }; 1299 1300 enum rtw89_btc_bt_state_cnt { 1301 BTC_BCNT_RETRY = 0x0, 1302 BTC_BCNT_REINIT, 1303 BTC_BCNT_REENABLE, 1304 BTC_BCNT_SCBDREAD, 1305 BTC_BCNT_RELINK, 1306 BTC_BCNT_IGNOWL, 1307 BTC_BCNT_INQPAG, 1308 BTC_BCNT_INQ, 1309 BTC_BCNT_PAGE, 1310 BTC_BCNT_ROLESW, 1311 BTC_BCNT_AFH, 1312 BTC_BCNT_INFOUPDATE, 1313 BTC_BCNT_INFOSAME, 1314 BTC_BCNT_SCBDUPDATE, 1315 BTC_BCNT_HIPRI_TX, 1316 BTC_BCNT_HIPRI_RX, 1317 BTC_BCNT_LOPRI_TX, 1318 BTC_BCNT_LOPRI_RX, 1319 BTC_BCNT_POLUT, 1320 BTC_BCNT_POLUT_NOW, 1321 BTC_BCNT_POLUT_DIFF, 1322 BTC_BCNT_RATECHG, 1323 BTC_BCNT_NUM, 1324 }; 1325 1326 enum rtw89_btc_bt_profile { 1327 BTC_BT_NOPROFILE = 0, 1328 BTC_BT_HFP = BIT(0), 1329 BTC_BT_HID = BIT(1), 1330 BTC_BT_A2DP = BIT(2), 1331 BTC_BT_PAN = BIT(3), 1332 BTC_PROFILE_MAX = 4, 1333 }; 1334 1335 struct rtw89_btc_ant_info { 1336 u8 type; /* shared, dedicated */ 1337 u8 num; 1338 u8 isolation; 1339 1340 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1341 u8 diversity: 1; 1342 u8 btg_pos: 2; 1343 u8 stream_cnt: 4; 1344 }; 1345 1346 struct rtw89_btc_ant_info_v7 { 1347 u8 type; /* shared, dedicated(non-shared) */ 1348 u8 num; /* antenna count */ 1349 u8 isolation; 1350 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1351 1352 u8 diversity; /* only for wifi use 1-antenna */ 1353 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1354 u8 stream_cnt; /* spatial_stream count */ 1355 u8 rsvd; 1356 } __packed; 1357 1358 enum rtw89_tfc_dir { 1359 RTW89_TFC_UL, 1360 RTW89_TFC_DL, 1361 }; 1362 1363 struct rtw89_btc_wl_smap { 1364 u32 busy: 1; 1365 u32 scan: 1; 1366 u32 connecting: 1; 1367 u32 roaming: 1; 1368 u32 dbccing: 1; 1369 u32 _4way: 1; 1370 u32 rf_off: 1; 1371 u32 lps: 2; 1372 u32 ips: 1; 1373 u32 init_ok: 1; 1374 u32 traffic_dir : 2; 1375 u32 rf_off_pre: 1; 1376 u32 lps_pre: 2; 1377 u32 lps_exiting: 1; 1378 u32 emlsr: 1; 1379 }; 1380 1381 enum rtw89_tfc_lv { 1382 RTW89_TFC_IDLE, 1383 RTW89_TFC_ULTRA_LOW, 1384 RTW89_TFC_LOW, 1385 RTW89_TFC_MID, 1386 RTW89_TFC_HIGH, 1387 }; 1388 1389 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1390 DECLARE_EWMA(tp, 10, 2); 1391 1392 struct rtw89_traffic_stats { 1393 /* units in bytes */ 1394 u64 tx_unicast; 1395 u64 rx_unicast; 1396 u32 tx_avg_len; 1397 u32 rx_avg_len; 1398 1399 /* count for packets */ 1400 u64 tx_cnt; 1401 u64 rx_cnt; 1402 1403 /* units in Mbps */ 1404 u32 tx_throughput; 1405 u32 rx_throughput; 1406 u32 tx_throughput_raw; 1407 u32 rx_throughput_raw; 1408 1409 u32 rx_tf_acc; 1410 u32 rx_tf_periodic; 1411 1412 enum rtw89_tfc_lv tx_tfc_lv; 1413 enum rtw89_tfc_lv rx_tfc_lv; 1414 struct ewma_tp tx_ewma_tp; 1415 struct ewma_tp rx_ewma_tp; 1416 1417 u16 tx_rate; 1418 u16 rx_rate; 1419 }; 1420 1421 struct rtw89_btc_chdef { 1422 u8 center_ch; 1423 u8 band; 1424 u8 chan; 1425 enum rtw89_sc_offset offset; 1426 enum rtw89_bandwidth bw; 1427 }; 1428 1429 struct rtw89_btc_statistic { 1430 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1431 struct rtw89_traffic_stats traffic; 1432 }; 1433 1434 #define BTC_WL_RSSI_THMAX 4 1435 1436 struct rtw89_btc_wl_link_info { 1437 struct rtw89_btc_chdef chdef; 1438 struct rtw89_btc_statistic stat; 1439 enum rtw89_tfc_dir dir; 1440 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1441 u8 mac_addr[ETH_ALEN]; 1442 u8 busy; 1443 u8 ch; 1444 u8 bw; 1445 u8 band; 1446 u8 role; 1447 u8 pid; 1448 u8 phy; 1449 u8 dtim_period; 1450 u8 mode; 1451 u8 tx_1ss_limit; 1452 1453 u8 mac_id; 1454 u8 tx_retry; 1455 1456 u32 bcn_period; 1457 u32 busy_t; 1458 u32 tx_time; 1459 u32 client_cnt; 1460 u32 rx_rate_drop_cnt; 1461 u32 noa_duration; 1462 1463 u32 active: 1; 1464 u32 noa: 1; 1465 u32 client_ps: 1; 1466 u32 connected: 2; 1467 }; 1468 1469 union rtw89_btc_wl_state_map { 1470 u32 val; 1471 struct rtw89_btc_wl_smap map; 1472 }; 1473 1474 struct rtw89_btc_bt_hfp_desc { 1475 u32 exist: 1; 1476 u32 type: 2; 1477 u32 rsvd: 29; 1478 }; 1479 1480 struct rtw89_btc_bt_hid_desc { 1481 u32 exist: 1; 1482 u32 slot_info: 2; 1483 u32 pair_cnt: 2; 1484 u32 type: 8; 1485 u32 rsvd: 19; 1486 }; 1487 1488 struct rtw89_btc_bt_a2dp_desc { 1489 u8 exist: 1; 1490 u8 exist_last: 1; 1491 u8 play_latency: 1; 1492 u8 type: 3; 1493 u8 active: 1; 1494 u8 sink: 1; 1495 u32 handle_update: 1; 1496 u32 devinfo_query: 1; 1497 u32 no_empty_streak_2s: 8; 1498 u32 no_empty_streak_max: 8; 1499 u32 rsvd: 6; 1500 1501 u8 bitpool; 1502 u16 vendor_id; 1503 u32 device_name; 1504 u32 flush_time; 1505 }; 1506 1507 struct rtw89_btc_bt_pan_desc { 1508 u32 exist: 1; 1509 u32 type: 1; 1510 u32 active: 1; 1511 u32 rsvd: 29; 1512 }; 1513 1514 struct rtw89_btc_bt_rfk_info { 1515 u32 run: 1; 1516 u32 req: 1; 1517 u32 timeout: 1; 1518 u32 rsvd: 29; 1519 }; 1520 1521 union rtw89_btc_bt_rfk_info_map { 1522 u32 val; 1523 struct rtw89_btc_bt_rfk_info map; 1524 }; 1525 1526 struct rtw89_btc_bt_ver_info { 1527 u32 fw_coex; /* match with which coex_ver */ 1528 u32 fw; 1529 }; 1530 1531 struct rtw89_btc_bool_sta_chg { 1532 u32 now: 1; 1533 u32 last: 1; 1534 u32 remain: 1; 1535 u32 srvd: 29; 1536 }; 1537 1538 struct rtw89_btc_u8_sta_chg { 1539 u8 now; 1540 u8 last; 1541 u8 remain; 1542 u8 rsvd; 1543 }; 1544 1545 struct rtw89_btc_wl_scan_info { 1546 u8 band[RTW89_PHY_NUM]; 1547 u8 phy_map; 1548 u8 rsvd; 1549 }; 1550 1551 struct rtw89_btc_wl_dbcc_info { 1552 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1553 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1554 u8 real_band[RTW89_PHY_NUM]; 1555 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1556 }; 1557 1558 struct rtw89_btc_wl_active_role { 1559 u8 connected: 1; 1560 u8 pid: 3; 1561 u8 phy: 1; 1562 u8 noa: 1; 1563 u8 band: 2; 1564 1565 u8 client_ps: 1; 1566 u8 bw: 7; 1567 1568 u8 role; 1569 u8 ch; 1570 1571 u16 tx_lvl; 1572 u16 rx_lvl; 1573 u16 tx_rate; 1574 u16 rx_rate; 1575 }; 1576 1577 struct rtw89_btc_wl_active_role_v1 { 1578 u8 connected: 1; 1579 u8 pid: 3; 1580 u8 phy: 1; 1581 u8 noa: 1; 1582 u8 band: 2; 1583 1584 u8 client_ps: 1; 1585 u8 bw: 7; 1586 1587 u8 role; 1588 u8 ch; 1589 1590 u16 tx_lvl; 1591 u16 rx_lvl; 1592 u16 tx_rate; 1593 u16 rx_rate; 1594 1595 u32 noa_duration; /* ms */ 1596 }; 1597 1598 struct rtw89_btc_wl_active_role_v2 { 1599 u8 connected: 1; 1600 u8 pid: 3; 1601 u8 phy: 1; 1602 u8 noa: 1; 1603 u8 band: 2; 1604 1605 u8 client_ps: 1; 1606 u8 bw: 7; 1607 1608 u8 role; 1609 u8 ch; 1610 1611 u32 noa_duration; /* ms */ 1612 }; 1613 1614 struct rtw89_btc_wl_active_role_v7 { 1615 u8 connected; 1616 u8 pid; 1617 u8 phy; 1618 u8 noa; 1619 1620 u8 band; 1621 u8 client_ps; 1622 u8 bw; 1623 u8 role; 1624 1625 u8 ch; 1626 u8 noa_dur; 1627 u8 client_cnt; 1628 u8 rsvd2; 1629 } __packed; 1630 1631 struct rtw89_btc_wl_role_info_bpos { 1632 u16 none: 1; 1633 u16 station: 1; 1634 u16 ap: 1; 1635 u16 vap: 1; 1636 u16 adhoc: 1; 1637 u16 adhoc_master: 1; 1638 u16 mesh: 1; 1639 u16 moniter: 1; 1640 u16 p2p_device: 1; 1641 u16 p2p_gc: 1; 1642 u16 p2p_go: 1; 1643 u16 nan: 1; 1644 }; 1645 1646 struct rtw89_btc_wl_scc_ctrl { 1647 u8 null_role1; 1648 u8 null_role2; 1649 u8 ebt_null; /* if tx null at EBT slot */ 1650 }; 1651 1652 union rtw89_btc_wl_role_info_map { 1653 u16 val; 1654 struct rtw89_btc_wl_role_info_bpos role; 1655 }; 1656 1657 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1658 u8 connect_cnt; 1659 u8 link_mode; 1660 union rtw89_btc_wl_role_info_map role_map; 1661 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1662 }; 1663 1664 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1665 u8 connect_cnt; 1666 u8 link_mode; 1667 union rtw89_btc_wl_role_info_map role_map; 1668 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1669 u32 mrole_type; /* btc_wl_mrole_type */ 1670 u32 mrole_noa_duration; /* ms */ 1671 1672 u32 dbcc_en: 1; 1673 u32 dbcc_chg: 1; 1674 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1675 u32 link_mode_chg: 1; 1676 u32 rsvd: 27; 1677 }; 1678 1679 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1680 u8 connect_cnt; 1681 u8 link_mode; 1682 union rtw89_btc_wl_role_info_map role_map; 1683 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1684 u32 mrole_type; /* btc_wl_mrole_type */ 1685 u32 mrole_noa_duration; /* ms */ 1686 1687 u32 dbcc_en: 1; 1688 u32 dbcc_chg: 1; 1689 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1690 u32 link_mode_chg: 1; 1691 u32 rsvd: 27; 1692 }; 1693 1694 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1695 u8 connected; 1696 u8 pid; 1697 u8 phy; 1698 u8 noa; 1699 1700 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1701 u8 active; /* 0:rlink is under doze */ 1702 u8 bw; /* enum channel_width */ 1703 u8 role; /*enum role_type */ 1704 1705 u8 ch; 1706 u8 noa_dur; /* ms */ 1707 u8 client_cnt; /* for Role = P2P-Go/AP */ 1708 u8 mode; /* wifi protocol */ 1709 } __packed; 1710 1711 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1712 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1713 u8 connect_cnt; 1714 u8 link_mode; 1715 u8 link_mode_chg; 1716 u8 p2p_2g; 1717 1718 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1719 1720 u32 role_map; 1721 u32 mrole_type; /* btc_wl_mrole_type */ 1722 u32 mrole_noa_duration; /* ms */ 1723 u32 dbcc_en; 1724 u32 dbcc_chg; 1725 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1726 } __packed; 1727 1728 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1729 u8 connect_cnt; 1730 u8 link_mode; 1731 u8 link_mode_chg; 1732 u8 p2p_2g; 1733 1734 u8 pta_req_band; 1735 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1736 u8 dbcc_chg; 1737 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1738 1739 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1740 1741 u32 role_map; 1742 u32 mrole_type; /* btc_wl_mrole_type */ 1743 u32 mrole_noa_duration; /* ms */ 1744 } __packed; 1745 1746 struct rtw89_btc_wl_ver_info { 1747 u32 fw_coex; /* match with which coex_ver */ 1748 u32 fw; 1749 u32 mac; 1750 u32 bb; 1751 u32 rf; 1752 }; 1753 1754 struct rtw89_btc_wl_afh_info { 1755 u8 en; 1756 u8 ch; 1757 u8 bw; 1758 u8 rsvd; 1759 } __packed; 1760 1761 struct rtw89_btc_wl_rfk_info { 1762 u32 state: 2; 1763 u32 path_map: 4; 1764 u32 phy_map: 2; 1765 u32 band: 2; 1766 u32 type: 8; 1767 u32 con_rfk: 1; 1768 u32 rsvd: 13; 1769 1770 u32 start_time; 1771 u32 proc_time; 1772 }; 1773 1774 struct rtw89_btc_bt_smap { 1775 u32 connect: 1; 1776 u32 ble_connect: 1; 1777 u32 acl_busy: 1; 1778 u32 sco_busy: 1; 1779 u32 mesh_busy: 1; 1780 u32 inq_pag: 1; 1781 }; 1782 1783 union rtw89_btc_bt_state_map { 1784 u32 val; 1785 struct rtw89_btc_bt_smap map; 1786 }; 1787 1788 #define BTC_BT_RSSI_THMAX 4 1789 #define BTC_BT_AFH_GROUP 12 1790 #define BTC_BT_AFH_LE_GROUP 5 1791 1792 struct rtw89_btc_bt_link_info { 1793 struct rtw89_btc_u8_sta_chg profile_cnt; 1794 struct rtw89_btc_bool_sta_chg multi_link; 1795 struct rtw89_btc_bool_sta_chg relink; 1796 struct rtw89_btc_bt_hfp_desc hfp_desc; 1797 struct rtw89_btc_bt_hid_desc hid_desc; 1798 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1799 struct rtw89_btc_bt_pan_desc pan_desc; 1800 union rtw89_btc_bt_state_map status; 1801 1802 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1803 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1804 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1805 u8 afh_map[BTC_BT_AFH_GROUP]; 1806 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1807 1808 u32 role_sw: 1; 1809 u32 slave_role: 1; 1810 u32 afh_update: 1; 1811 u32 cqddr: 1; 1812 u32 rssi: 8; 1813 u32 tx_3m: 1; 1814 u32 rsvd: 19; 1815 }; 1816 1817 struct rtw89_btc_3rdcx_info { 1818 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1819 u8 hw_coex; 1820 u16 rsvd; 1821 }; 1822 1823 struct rtw89_btc_dm_emap { 1824 u32 init: 1; 1825 u32 pta_owner: 1; 1826 u32 wl_rfk_timeout: 1; 1827 u32 bt_rfk_timeout: 1; 1828 u32 wl_fw_hang: 1; 1829 u32 cycle_hang: 1; 1830 u32 w1_hang: 1; 1831 u32 b1_hang: 1; 1832 u32 tdma_no_sync: 1; 1833 u32 slot_no_sync: 1; 1834 u32 wl_slot_drift: 1; 1835 u32 bt_slot_drift: 1; 1836 u32 role_num_mismatch: 1; 1837 u32 null1_tx_late: 1; 1838 u32 bt_afh_conflict: 1; 1839 u32 bt_leafh_conflict: 1; 1840 u32 bt_slot_flood: 1; 1841 u32 wl_e2g_hang: 1; 1842 u32 wl_ver_mismatch: 1; 1843 u32 bt_ver_mismatch: 1; 1844 u32 rfe_type0: 1; 1845 u32 h2c_buffer_over: 1; 1846 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1847 u32 wl_no_sta_ntfy: 1; 1848 1849 u32 h2c_bmap_mismatch: 1; 1850 u32 c2h_bmap_mismatch: 1; 1851 u32 h2c_struct_invalid: 1; 1852 u32 c2h_struct_invalid: 1; 1853 u32 h2c_c2h_buffer_mismatch: 1; 1854 }; 1855 1856 union rtw89_btc_dm_error_map { 1857 u32 val; 1858 struct rtw89_btc_dm_emap map; 1859 }; 1860 1861 struct rtw89_btc_rf_para { 1862 u32 tx_pwr_freerun; 1863 u32 rx_gain_freerun; 1864 u32 tx_pwr_perpkt; 1865 u32 rx_gain_perpkt; 1866 }; 1867 1868 struct rtw89_btc_wl_nhm { 1869 u8 instant_wl_nhm_dbm; 1870 u8 instant_wl_nhm_per_mhz; 1871 u16 valid_record_times; 1872 s8 record_pwr[16]; 1873 u8 record_ratio[16]; 1874 s8 pwr; /* dbm_per_MHz */ 1875 u8 ratio; 1876 u8 current_status; 1877 u8 refresh; 1878 bool start_flag; 1879 s8 pwr_max; 1880 s8 pwr_min; 1881 }; 1882 1883 struct rtw89_btc_wl_info { 1884 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1885 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1886 struct rtw89_btc_wl_rfk_info rfk_info; 1887 struct rtw89_btc_wl_ver_info ver_info; 1888 struct rtw89_btc_wl_afh_info afh_info; 1889 struct rtw89_btc_wl_role_info role_info; 1890 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1891 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1892 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1893 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1894 struct rtw89_btc_wl_scan_info scan_info; 1895 struct rtw89_btc_wl_dbcc_info dbcc_info; 1896 struct rtw89_btc_rf_para rf_para; 1897 struct rtw89_btc_wl_nhm nhm; 1898 union rtw89_btc_wl_state_map status; 1899 1900 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1901 u8 rssi_level; 1902 u8 cn_report; 1903 u8 coex_mode; 1904 u8 pta_req_mac; 1905 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 1906 1907 bool is_5g_hi_channel; 1908 bool pta_reg_mac_chg; 1909 bool bg_mode; 1910 bool he_mode; 1911 bool scbd_change; 1912 bool fw_ver_mismatch; 1913 bool client_cnt_inc_2g; 1914 u32 scbd; 1915 }; 1916 1917 struct rtw89_btc_module { 1918 struct rtw89_btc_ant_info ant; 1919 u8 rfe_type; 1920 u8 cv; 1921 1922 u8 bt_solo: 1; 1923 u8 bt_pos: 1; 1924 u8 switch_type: 1; 1925 u8 wa_type: 3; 1926 1927 u8 kt_ver_adie; 1928 }; 1929 1930 struct rtw89_btc_module_v7 { 1931 u8 rfe_type; 1932 u8 kt_ver; 1933 u8 bt_solo; 1934 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1935 1936 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1937 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1938 u8 kt_ver_adie; 1939 u8 rsvd; 1940 1941 struct rtw89_btc_ant_info_v7 ant; 1942 } __packed; 1943 1944 union rtw89_btc_module_info { 1945 struct rtw89_btc_module md; 1946 struct rtw89_btc_module_v7 md_v7; 1947 }; 1948 1949 #define RTW89_BTC_DM_MAXSTEP 30 1950 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1951 1952 struct rtw89_btc_dm_step { 1953 u16 step[RTW89_BTC_DM_MAXSTEP]; 1954 u8 step_pos; 1955 bool step_ov; 1956 }; 1957 1958 struct rtw89_btc_init_info { 1959 struct rtw89_btc_module module; 1960 u8 wl_guard_ch; 1961 1962 u8 wl_only: 1; 1963 u8 wl_init_ok: 1; 1964 u8 dbcc_en: 1; 1965 u8 cx_other: 1; 1966 u8 bt_only: 1; 1967 1968 u16 rsvd; 1969 }; 1970 1971 struct rtw89_btc_init_info_v7 { 1972 u8 wl_guard_ch; 1973 u8 wl_only; 1974 u8 wl_init_ok; 1975 u8 rsvd3; 1976 1977 u8 cx_other; 1978 u8 bt_only; 1979 u8 pta_mode; 1980 u8 pta_direction; 1981 1982 struct rtw89_btc_module_v7 module; 1983 } __packed; 1984 1985 union rtw89_btc_init_info_u { 1986 struct rtw89_btc_init_info init; 1987 struct rtw89_btc_init_info_v7 init_v7; 1988 }; 1989 1990 struct rtw89_btc_wl_tx_limit_para { 1991 u16 enable; 1992 u32 tx_time; /* unit: us */ 1993 u16 tx_retry; 1994 }; 1995 1996 enum rtw89_btc_bt_scan_type { 1997 BTC_SCAN_INQ = 0, 1998 BTC_SCAN_PAGE, 1999 BTC_SCAN_BLE, 2000 BTC_SCAN_INIT, 2001 BTC_SCAN_TV, 2002 BTC_SCAN_ADV, 2003 BTC_SCAN_MAX1, 2004 }; 2005 2006 enum rtw89_btc_ble_scan_type { 2007 CXSCAN_BG = 0, 2008 CXSCAN_INIT, 2009 CXSCAN_LE, 2010 CXSCAN_MAX 2011 }; 2012 2013 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2014 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2015 2016 struct rtw89_btc_bt_scan_info_v1 { 2017 __le16 win; 2018 __le16 intvl; 2019 __le32 flags; 2020 } __packed; 2021 2022 struct rtw89_btc_bt_scan_info_v2 { 2023 __le16 win; 2024 __le16 intvl; 2025 } __packed; 2026 2027 struct rtw89_btc_fbtc_btscan_v1 { 2028 u8 fver; /* btc_ver::fcxbtscan */ 2029 u8 rsvd; 2030 __le16 rsvd2; 2031 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2032 } __packed; 2033 2034 struct rtw89_btc_fbtc_btscan_v2 { 2035 u8 fver; /* btc_ver::fcxbtscan */ 2036 u8 type; 2037 __le16 rsvd2; 2038 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2039 } __packed; 2040 2041 struct rtw89_btc_fbtc_btscan_v7 { 2042 u8 fver; /* btc_ver::fcxbtscan */ 2043 u8 type; 2044 u8 rsvd0; 2045 u8 rsvd1; 2046 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2047 } __packed; 2048 2049 union rtw89_btc_fbtc_btscan { 2050 struct rtw89_btc_fbtc_btscan_v1 v1; 2051 struct rtw89_btc_fbtc_btscan_v2 v2; 2052 struct rtw89_btc_fbtc_btscan_v7 v7; 2053 }; 2054 2055 struct rtw89_btc_bt_info { 2056 struct rtw89_btc_bt_link_info link_info; 2057 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2058 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2059 struct rtw89_btc_bt_ver_info ver_info; 2060 struct rtw89_btc_bool_sta_chg enable; 2061 struct rtw89_btc_bool_sta_chg inq_pag; 2062 struct rtw89_btc_rf_para rf_para; 2063 union rtw89_btc_bt_rfk_info_map rfk_info; 2064 2065 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2066 u8 rssi_level; 2067 2068 u32 scbd; 2069 u32 feature; 2070 2071 u32 mbx_avl: 1; 2072 u32 whql_test: 1; 2073 u32 igno_wl: 1; 2074 u32 reinit: 1; 2075 u32 ble_scan_en: 1; 2076 u32 btg_type: 1; 2077 u32 inq: 1; 2078 u32 pag: 1; 2079 u32 run_patch_code: 1; 2080 u32 hi_lna_rx: 1; 2081 u32 scan_rx_low_pri: 1; 2082 u32 scan_info_update: 1; 2083 u32 lna_constrain: 3; 2084 u32 rsvd: 17; 2085 }; 2086 2087 struct rtw89_btc_cx { 2088 struct rtw89_btc_wl_info wl; 2089 struct rtw89_btc_bt_info bt; 2090 struct rtw89_btc_3rdcx_info other; 2091 u32 state_map; 2092 u32 cnt_bt[BTC_BCNT_NUM]; 2093 u32 cnt_wl[BTC_WCNT_NUM]; 2094 }; 2095 2096 struct rtw89_btc_fbtc_tdma { 2097 u8 type; /* btc_ver::fcxtdma */ 2098 u8 rxflctrl; 2099 u8 txpause; 2100 u8 wtgle_n; 2101 u8 leak_n; 2102 u8 ext_ctrl; 2103 u8 rxflctrl_role; 2104 u8 option_ctrl; 2105 } __packed; 2106 2107 struct rtw89_btc_fbtc_tdma_v3 { 2108 u8 fver; /* btc_ver::fcxtdma */ 2109 u8 rsvd; 2110 __le16 rsvd1; 2111 struct rtw89_btc_fbtc_tdma tdma; 2112 } __packed; 2113 2114 union rtw89_btc_fbtc_tdma_le32 { 2115 struct rtw89_btc_fbtc_tdma v1; 2116 struct rtw89_btc_fbtc_tdma_v3 v3; 2117 }; 2118 2119 #define CXMREG_MAX 30 2120 #define CXMREG_MAX_V2 20 2121 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2122 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2123 2124 enum rtw89_btc_bt_sta_counter { 2125 BTC_BCNT_RFK_REQ = 0, 2126 BTC_BCNT_RFK_GO = 1, 2127 BTC_BCNT_RFK_REJECT = 2, 2128 BTC_BCNT_RFK_FAIL = 3, 2129 BTC_BCNT_RFK_TIMEOUT = 4, 2130 BTC_BCNT_HI_TX = 5, 2131 BTC_BCNT_HI_RX = 6, 2132 BTC_BCNT_LO_TX = 7, 2133 BTC_BCNT_LO_RX = 8, 2134 BTC_BCNT_POLLUTED = 9, 2135 BTC_BCNT_STA_MAX 2136 }; 2137 2138 enum rtw89_btc_bt_sta_counter_v105 { 2139 BTC_BCNT_RFK_REQ_V105 = 0, 2140 BTC_BCNT_HI_TX_V105 = 1, 2141 BTC_BCNT_HI_RX_V105 = 2, 2142 BTC_BCNT_LO_TX_V105 = 3, 2143 BTC_BCNT_LO_RX_V105 = 4, 2144 BTC_BCNT_POLLUTED_V105 = 5, 2145 BTC_BCNT_STA_MAX_V105 2146 }; 2147 2148 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2149 u16 fver; /* btc_ver::fcxbtcrpt */ 2150 u16 rpt_cnt; /* tmr counters */ 2151 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2152 u32 wl_fw_cx_offload; 2153 u32 wl_fw_ver; 2154 u32 rpt_enable; 2155 u32 rpt_para; /* ms */ 2156 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2157 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2158 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2159 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2160 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2161 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2162 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2163 u32 c2h_cnt; /* fw send c2h counter */ 2164 u32 h2c_cnt; /* fw recv h2c counter */ 2165 } __packed; 2166 2167 struct rtw89_btc_fbtc_rpt_ctrl_info { 2168 __le32 cnt; /* fw report counter */ 2169 __le32 en; /* report map */ 2170 __le32 para; /* not used */ 2171 2172 __le32 cnt_c2h; /* fw send c2h counter */ 2173 __le32 cnt_h2c; /* fw recv h2c counter */ 2174 __le32 len_c2h; /* The total length of the last C2H */ 2175 2176 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2177 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2178 } __packed; 2179 2180 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2181 __le32 cx_ver; /* match which driver's coex version */ 2182 __le32 fw_ver; 2183 __le32 en; /* report map */ 2184 2185 __le16 cnt; /* fw report counter */ 2186 __le16 cnt_c2h; /* fw send c2h counter */ 2187 __le16 cnt_h2c; /* fw recv h2c counter */ 2188 __le16 len_c2h; /* The total length of the last C2H */ 2189 2190 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2191 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2192 } __packed; 2193 2194 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2195 __le16 cnt; /* fw report counter */ 2196 __le16 cnt_c2h; /* fw send c2h counter */ 2197 __le16 cnt_h2c; /* fw recv h2c counter */ 2198 __le16 len_c2h; /* The total length of the last C2H */ 2199 2200 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2201 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2202 2203 __le32 cx_ver; /* match which driver's coex version */ 2204 __le32 fw_ver; 2205 __le32 en; /* report map */ 2206 } __packed; 2207 2208 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2209 __le32 cx_ver; /* match which driver's coex version */ 2210 __le32 cx_offload; 2211 __le32 fw_ver; 2212 } __packed; 2213 2214 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2215 __le32 cnt_empty; /* a2dp empty count */ 2216 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2217 __le32 cnt_tx; 2218 __le32 cnt_ack; 2219 __le32 cnt_nack; 2220 } __packed; 2221 2222 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2223 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2224 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2225 __le32 cnt_recv; /* fw recv mailbox counter */ 2226 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2227 } __packed; 2228 2229 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2230 u8 fver; 2231 u8 rsvd; 2232 __le16 rsvd1; 2233 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2234 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2235 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2236 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2237 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2238 } __packed; 2239 2240 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2241 u8 fver; 2242 u8 rsvd; 2243 __le16 rsvd1; 2244 2245 u8 gnt_val[RTW89_PHY_NUM][4]; 2246 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2247 2248 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2249 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2250 } __packed; 2251 2252 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2253 u8 fver; 2254 u8 rsvd; 2255 __le16 rsvd1; 2256 2257 u8 gnt_val[RTW89_PHY_NUM][4]; 2258 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2259 2260 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2261 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2262 } __packed; 2263 2264 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2265 u8 fver; 2266 u8 rsvd0; 2267 u8 rsvd1; 2268 u8 rsvd2; 2269 2270 u8 gnt_val[RTW89_PHY_NUM][4]; 2271 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2272 2273 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2274 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2275 } __packed; 2276 2277 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2278 u8 fver; 2279 u8 rsvd0; 2280 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2281 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2282 2283 u8 gnt_val[RTW89_PHY_NUM][4]; 2284 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2285 2286 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2287 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2288 } __packed; 2289 2290 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2291 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2292 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2293 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2294 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2295 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2296 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2297 }; 2298 2299 enum rtw89_fbtc_ext_ctrl_type { 2300 CXECTL_OFF = 0x0, /* tdma off */ 2301 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2302 CXECTL_EXT = 0x2, 2303 CXECTL_MAX 2304 }; 2305 2306 union rtw89_btc_fbtc_rxflct { 2307 u8 val; 2308 u8 type: 3; 2309 u8 tgln_n: 5; 2310 }; 2311 2312 enum rtw89_btc_cxst_state { 2313 CXST_OFF = 0x0, 2314 CXST_B2W = 0x1, 2315 CXST_W1 = 0x2, 2316 CXST_W2 = 0x3, 2317 CXST_W2B = 0x4, 2318 CXST_B1 = 0x5, 2319 CXST_B2 = 0x6, 2320 CXST_B3 = 0x7, 2321 CXST_B4 = 0x8, 2322 CXST_LK = 0x9, 2323 CXST_BLK = 0xa, 2324 CXST_E2G = 0xb, 2325 CXST_E5G = 0xc, 2326 CXST_EBT = 0xd, 2327 CXST_ENULL = 0xe, 2328 CXST_WLK = 0xf, 2329 CXST_W1FDD = 0x10, 2330 CXST_B1FDD = 0x11, 2331 CXST_MAX = 0x12, 2332 }; 2333 2334 enum rtw89_btc_cxevnt { 2335 CXEVNT_TDMA_ENTRY = 0x0, 2336 CXEVNT_WL_TMR, 2337 CXEVNT_B1_TMR, 2338 CXEVNT_B2_TMR, 2339 CXEVNT_B3_TMR, 2340 CXEVNT_B4_TMR, 2341 CXEVNT_W2B_TMR, 2342 CXEVNT_B2W_TMR, 2343 CXEVNT_BCN_EARLY, 2344 CXEVNT_A2DP_EMPTY, 2345 CXEVNT_LK_END, 2346 CXEVNT_RX_ISR, 2347 CXEVNT_RX_FC0, 2348 CXEVNT_RX_FC1, 2349 CXEVNT_BT_RELINK, 2350 CXEVNT_BT_RETRY, 2351 CXEVNT_E2G, 2352 CXEVNT_E5G, 2353 CXEVNT_EBT, 2354 CXEVNT_ENULL, 2355 CXEVNT_DRV_WLK, 2356 CXEVNT_BCN_OK, 2357 CXEVNT_BT_CHANGE, 2358 CXEVNT_EBT_EXTEND, 2359 CXEVNT_E2G_NULL1, 2360 CXEVNT_B1FDD_TMR, 2361 CXEVNT_MAX 2362 }; 2363 2364 enum { 2365 CXBCN_ALL = 0x0, 2366 CXBCN_ALL_OK, 2367 CXBCN_BT_SLOT, 2368 CXBCN_BT_OK, 2369 CXBCN_MAX 2370 }; 2371 2372 enum btc_slot_type { 2373 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2374 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2375 CXSTYPE_NUM, 2376 }; 2377 2378 enum { /* TIME */ 2379 CXT_BT = 0x0, 2380 CXT_WL = 0x1, 2381 CXT_MAX 2382 }; 2383 2384 enum { /* TIME-A2DP */ 2385 CXT_FLCTRL_OFF = 0x0, 2386 CXT_FLCTRL_ON = 0x1, 2387 CXT_FLCTRL_MAX 2388 }; 2389 2390 enum { /* STEP TYPE */ 2391 CXSTEP_NONE = 0x0, 2392 CXSTEP_EVNT = 0x1, 2393 CXSTEP_SLOT = 0x2, 2394 CXSTEP_MAX, 2395 }; 2396 2397 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2398 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2399 RPT_BT_AFH_SEQ_LE = 0x20 2400 }; 2401 2402 #define BTC_DBG_MAX1 32 2403 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2404 u8 fver; /* btc_ver::fcxgpiodbg */ 2405 u8 rsvd; 2406 __le16 rsvd2; 2407 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2408 __le32 pre_state; /* the debug signal is 1 or 0 */ 2409 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2410 } __packed; 2411 2412 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2413 u8 fver; 2414 u8 rsvd0; 2415 u8 rsvd1; 2416 u8 rsvd2; 2417 2418 u8 gpio_map[BTC_DBG_MAX1]; 2419 2420 __le32 en_map; 2421 __le32 pre_state; 2422 } __packed; 2423 2424 union rtw89_btc_fbtc_gpio_dbg { 2425 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2426 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2427 }; 2428 2429 struct rtw89_btc_fbtc_mreg_val_v1 { 2430 u8 fver; /* btc_ver::fcxmreg */ 2431 u8 reg_num; 2432 __le16 rsvd; 2433 __le32 mreg_val[CXMREG_MAX]; 2434 } __packed; 2435 2436 struct rtw89_btc_fbtc_mreg_val_v2 { 2437 u8 fver; /* btc_ver::fcxmreg */ 2438 u8 reg_num; 2439 __le16 rsvd; 2440 __le32 mreg_val[CXMREG_MAX_V2]; 2441 } __packed; 2442 2443 struct rtw89_btc_fbtc_mreg_val_v7 { 2444 u8 fver; 2445 u8 reg_num; 2446 u8 rsvd0; 2447 u8 rsvd1; 2448 __le32 mreg_val[CXMREG_MAX_V2]; 2449 } __packed; 2450 2451 union rtw89_btc_fbtc_mreg_val { 2452 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2453 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2454 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2455 }; 2456 2457 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2458 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2459 .offset = cpu_to_le32(__offset), } 2460 2461 struct rtw89_btc_fbtc_mreg { 2462 __le16 type; 2463 __le16 bytes; 2464 __le32 offset; 2465 } __packed; 2466 2467 struct rtw89_btc_fbtc_slot { 2468 __le16 dur; 2469 __le32 cxtbl; 2470 __le16 cxtype; 2471 } __packed; 2472 2473 struct rtw89_btc_fbtc_slots { 2474 u8 fver; /* btc_ver::fcxslots */ 2475 u8 tbl_num; 2476 __le16 rsvd; 2477 __le32 update_map; 2478 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2479 } __packed; 2480 2481 struct rtw89_btc_fbtc_slot_v7 { 2482 __le16 dur; /* slot duration */ 2483 __le16 cxtype; 2484 __le32 cxtbl; 2485 } __packed; 2486 2487 struct rtw89_btc_fbtc_slot_u16 { 2488 __le16 dur; /* slot duration */ 2489 __le16 cxtype; 2490 __le16 cxtbl_l16; /* coex table [15:0] */ 2491 __le16 cxtbl_h16; /* coex table [31:16] */ 2492 } __packed; 2493 2494 struct rtw89_btc_fbtc_1slot_v7 { 2495 u8 fver; 2496 u8 sid; /* slot id */ 2497 __le16 rsvd; 2498 struct rtw89_btc_fbtc_slot_v7 slot; 2499 } __packed; 2500 2501 struct rtw89_btc_fbtc_slots_v7 { 2502 u8 fver; 2503 u8 slot_cnt; 2504 u8 rsvd0; 2505 u8 rsvd1; 2506 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2507 __le32 update_map; 2508 } __packed; 2509 2510 union rtw89_btc_fbtc_slots_info { 2511 struct rtw89_btc_fbtc_slots v1; 2512 struct rtw89_btc_fbtc_slots_v7 v7; 2513 } __packed; 2514 2515 struct rtw89_btc_fbtc_step { 2516 u8 type; 2517 u8 val; 2518 __le16 difft; 2519 } __packed; 2520 2521 struct rtw89_btc_fbtc_steps_v2 { 2522 u8 fver; /* btc_ver::fcxstep */ 2523 u8 rsvd; 2524 __le16 cnt; 2525 __le16 pos_old; 2526 __le16 pos_new; 2527 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2528 } __packed; 2529 2530 struct rtw89_btc_fbtc_steps_v3 { 2531 u8 fver; 2532 u8 en; 2533 __le16 rsvd; 2534 __le32 cnt; 2535 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2536 } __packed; 2537 2538 union rtw89_btc_fbtc_steps_info { 2539 struct rtw89_btc_fbtc_steps_v2 v2; 2540 struct rtw89_btc_fbtc_steps_v3 v3; 2541 }; 2542 2543 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2544 u8 fver; /* btc_ver::fcxcysta */ 2545 u8 rsvd; 2546 __le16 cycles; /* total cycle number */ 2547 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2548 __le16 a2dpept; /* a2dp empty cnt */ 2549 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2550 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2551 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2552 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2553 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2554 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2555 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2556 __le16 tmax_a2dpept; /* max a2dp empty time */ 2557 __le16 tavg_lk; /* avg leak-slot time */ 2558 __le16 tmax_lk; /* max leak-slot time */ 2559 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2560 __le32 bcn_cnt[CXBCN_MAX]; 2561 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2562 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2563 __le32 skip_cnt; 2564 __le32 exception; 2565 __le32 except_cnt; 2566 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2567 } __packed; 2568 2569 struct rtw89_btc_fbtc_fdd_try_info { 2570 __le16 cycles[CXT_FLCTRL_MAX]; 2571 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2572 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2573 } __packed; 2574 2575 struct rtw89_btc_fbtc_cycle_time_info { 2576 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2577 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2578 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2579 } __packed; 2580 2581 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2582 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2583 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2584 } __packed; 2585 2586 struct rtw89_btc_fbtc_a2dp_trx_stat { 2587 u8 empty_cnt; 2588 u8 retry_cnt; 2589 u8 tx_rate; 2590 u8 tx_cnt; 2591 u8 ack_cnt; 2592 u8 nack_cnt; 2593 u8 rsvd1; 2594 u8 rsvd2; 2595 } __packed; 2596 2597 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2598 u8 empty_cnt; 2599 u8 retry_cnt; 2600 u8 tx_rate; 2601 u8 tx_cnt; 2602 u8 ack_cnt; 2603 u8 nack_cnt; 2604 u8 no_empty_cnt; 2605 u8 rsvd; 2606 } __packed; 2607 2608 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2609 __le16 cnt; /* a2dp empty cnt */ 2610 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2611 __le16 tavg; /* avg a2dp empty time */ 2612 __le16 tmax; /* max a2dp empty time */ 2613 } __packed; 2614 2615 struct rtw89_btc_fbtc_cycle_leak_info { 2616 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2617 __le16 tavg; /* avg leak-slot time */ 2618 __le16 tmax; /* max leak-slot time */ 2619 } __packed; 2620 2621 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2622 __le16 tavg; 2623 __le16 tamx; 2624 __le32 cnt_rximr; 2625 } __packed; 2626 2627 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2628 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2629 2630 struct rtw89_btc_fbtc_cycle_fddt_info { 2631 __le16 train_cycle; 2632 __le16 tp; 2633 2634 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2635 s8 bt_tx_power; /* decrease Tx power (dB) */ 2636 s8 bt_rx_gain; /* LNA constrain level */ 2637 u8 no_empty_cnt; 2638 2639 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2640 u8 cn; /* condition_num */ 2641 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2642 u8 train_result; /* refer to enum btc_fddt_check_map */ 2643 } __packed; 2644 2645 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2646 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2647 2648 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2649 __le16 train_cycle; 2650 __le16 tp; 2651 2652 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2653 s8 bt_tx_power; /* decrease Tx power (dB) */ 2654 s8 bt_rx_gain; /* LNA constrain level */ 2655 u8 no_empty_cnt; 2656 2657 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2658 u8 cn; /* condition_num */ 2659 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2660 u8 train_result; /* refer to enum btc_fddt_check_map */ 2661 } __packed; 2662 2663 struct rtw89_btc_fbtc_fddt_cell_status { 2664 s8 wl_tx_pwr; 2665 s8 bt_tx_pwr; 2666 s8 bt_rx_gain; 2667 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2668 } __packed; 2669 2670 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2671 u8 fver; 2672 u8 rsvd; 2673 __le16 cycles; /* total cycle number */ 2674 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2675 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2676 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2677 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2678 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2679 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2680 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2681 __le32 bcn_cnt[CXBCN_MAX]; 2682 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2683 __le32 skip_cnt; 2684 __le32 except_cnt; 2685 __le32 except_map; 2686 } __packed; 2687 2688 #define FDD_TRAIN_WL_DIRECTION 2 2689 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2690 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2691 2692 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2693 u8 fver; 2694 u8 rsvd; 2695 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2696 u8 except_cnt; 2697 2698 __le16 skip_cnt; 2699 __le16 cycles; /* total cycle number */ 2700 2701 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2702 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2703 __le16 bcn_cnt[CXBCN_MAX]; 2704 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2705 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2706 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2707 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2708 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2709 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2710 [FDD_TRAIN_WL_RSSI_LEVEL] 2711 [FDD_TRAIN_BT_RSSI_LEVEL]; 2712 __le32 except_map; 2713 } __packed; 2714 2715 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2716 u8 fver; 2717 u8 rsvd; 2718 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2719 u8 except_cnt; 2720 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2721 2722 __le16 skip_cnt; 2723 __le16 cycles; /* total cycle number */ 2724 2725 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2726 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2727 __le16 bcn_cnt[CXBCN_MAX]; 2728 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2729 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2730 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2731 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2732 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2733 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2734 [FDD_TRAIN_WL_RSSI_LEVEL] 2735 [FDD_TRAIN_BT_RSSI_LEVEL]; 2736 __le32 except_map; 2737 } __packed; 2738 2739 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2740 u8 fver; 2741 u8 rsvd; 2742 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2743 u8 except_cnt; 2744 2745 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2746 2747 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2748 2749 __le16 skip_cnt; 2750 __le16 cycles; /* total cycle number */ 2751 2752 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2753 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2754 __le16 bcn_cnt[CXBCN_MAX]; 2755 2756 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2757 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2758 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2759 2760 __le32 except_map; 2761 } __packed; 2762 2763 union rtw89_btc_fbtc_cysta_info { 2764 struct rtw89_btc_fbtc_cysta_v2 v2; 2765 struct rtw89_btc_fbtc_cysta_v3 v3; 2766 struct rtw89_btc_fbtc_cysta_v4 v4; 2767 struct rtw89_btc_fbtc_cysta_v5 v5; 2768 struct rtw89_btc_fbtc_cysta_v7 v7; 2769 }; 2770 2771 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2772 u8 fver; /* btc_ver::fcxnullsta */ 2773 u8 rsvd; 2774 __le16 rsvd2; 2775 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2776 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2777 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2778 } __packed; 2779 2780 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2781 u8 fver; /* btc_ver::fcxnullsta */ 2782 u8 rsvd; 2783 __le16 rsvd2; 2784 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2785 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2786 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2787 } __packed; 2788 2789 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2790 u8 fver; 2791 u8 rsvd0; 2792 u8 rsvd1; 2793 u8 rsvd2; 2794 2795 __le32 tmax[2]; 2796 __le32 tavg[2]; 2797 __le32 result[2][5]; 2798 } __packed; 2799 2800 union rtw89_btc_fbtc_cynullsta_info { 2801 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2802 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2803 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2804 }; 2805 2806 struct rtw89_btc_fbtc_btver_v1 { 2807 u8 fver; /* btc_ver::fcxbtver */ 2808 u8 rsvd; 2809 __le16 rsvd2; 2810 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2811 __le32 fw_ver; 2812 __le32 feature; 2813 } __packed; 2814 2815 struct rtw89_btc_fbtc_btver_v7 { 2816 u8 fver; 2817 u8 rsvd0; 2818 u8 rsvd1; 2819 u8 rsvd2; 2820 2821 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2822 __le32 fw_ver; 2823 __le32 feature; 2824 } __packed; 2825 2826 union rtw89_btc_fbtc_btver { 2827 struct rtw89_btc_fbtc_btver_v1 v1; 2828 struct rtw89_btc_fbtc_btver_v7 v7; 2829 } __packed; 2830 2831 struct rtw89_btc_fbtc_btafh { 2832 u8 fver; /* btc_ver::fcxbtafh */ 2833 u8 rsvd; 2834 __le16 rsvd2; 2835 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2836 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2837 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2838 } __packed; 2839 2840 struct rtw89_btc_fbtc_btafh_v2 { 2841 u8 fver; /* btc_ver::fcxbtafh */ 2842 u8 rsvd; 2843 u8 rsvd2; 2844 u8 map_type; 2845 u8 afh_l[4]; 2846 u8 afh_m[4]; 2847 u8 afh_h[4]; 2848 u8 afh_le_a[4]; 2849 u8 afh_le_b[4]; 2850 } __packed; 2851 2852 struct rtw89_btc_fbtc_btafh_v7 { 2853 u8 fver; 2854 u8 map_type; 2855 u8 rsvd0; 2856 u8 rsvd1; 2857 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2858 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2859 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2860 u8 afh_le_a[4]; 2861 u8 afh_le_b[4]; 2862 } __packed; 2863 2864 struct rtw89_btc_fbtc_btdevinfo { 2865 u8 fver; /* btc_ver::fcxbtdevinfo */ 2866 u8 rsvd; 2867 __le16 vendor_id; 2868 __le32 dev_name; /* only 24 bits valid */ 2869 __le32 flush_time; 2870 } __packed; 2871 2872 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2873 struct rtw89_btc_rf_trx_para { 2874 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2875 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2876 u8 bt_tx_power; /* decrease Tx power (dB) */ 2877 u8 bt_rx_gain; /* LNA constrain level */ 2878 }; 2879 2880 struct rtw89_btc_trx_info { 2881 u8 tx_lvl; 2882 u8 rx_lvl; 2883 u8 wl_rssi; 2884 u8 bt_rssi; 2885 2886 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2887 s8 rx_gain; /* rx gain table index (TBD.) */ 2888 s8 bt_tx_power; /* decrease Tx power (dB) */ 2889 s8 bt_rx_gain; /* LNA constrain level */ 2890 2891 u8 cn; /* condition_num */ 2892 s8 nhm; 2893 u8 bt_profile; 2894 u8 rsvd2; 2895 2896 u16 tx_rate; 2897 u16 rx_rate; 2898 2899 u32 tx_tp; 2900 u32 rx_tp; 2901 u32 rx_err_ratio; 2902 }; 2903 2904 union rtw89_btc_fbtc_slot_u { 2905 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2906 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2907 }; 2908 2909 struct rtw89_btc_dm { 2910 union rtw89_btc_fbtc_slot_u slot; 2911 union rtw89_btc_fbtc_slot_u slot_now; 2912 struct rtw89_btc_fbtc_tdma tdma; 2913 struct rtw89_btc_fbtc_tdma tdma_now; 2914 struct rtw89_mac_ax_coex_gnt gnt; 2915 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2916 struct rtw89_btc_rf_trx_para rf_trx_para; 2917 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2918 struct rtw89_btc_dm_step dm_step; 2919 struct rtw89_btc_wl_scc_ctrl wl_scc; 2920 struct rtw89_btc_trx_info trx_info; 2921 union rtw89_btc_dm_error_map error; 2922 u32 cnt_dm[BTC_DCNT_NUM]; 2923 u32 cnt_notify[BTC_NCNT_NUM]; 2924 2925 u32 update_slot_map; 2926 u32 set_ant_path; 2927 u32 e2g_slot_limit; 2928 u32 e2g_slot_nulltx_time; 2929 2930 u32 wl_only: 1; 2931 u32 wl_fw_cx_offload: 1; 2932 u32 freerun: 1; 2933 u32 fddt_train: 1; 2934 u32 wl_ps_ctrl: 2; 2935 u32 wl_mimo_ps: 1; 2936 u32 leak_ap: 1; 2937 u32 noisy_level: 3; 2938 u32 coex_info_map: 8; 2939 u32 bt_only: 1; 2940 u32 wl_btg_rx: 2; 2941 u32 trx_para_level: 8; 2942 u32 wl_stb_chg: 1; 2943 u32 pta_owner: 1; 2944 2945 u32 tdma_instant_excute: 1; 2946 u32 wl_btg_rx_rb: 2; 2947 2948 u16 slot_dur[CXST_MAX]; 2949 u16 bt_slot_flood; 2950 2951 u8 run_reason; 2952 u8 run_action; 2953 2954 u8 wl_pre_agc: 2; 2955 u8 wl_lna2: 1; 2956 u8 freerun_chk: 1; 2957 u8 wl_pre_agc_rb: 2; 2958 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2959 u8 slot_req_more: 1; 2960 }; 2961 2962 struct rtw89_btc_ctrl { 2963 u32 manual: 1; 2964 u32 igno_bt: 1; 2965 u32 always_freerun: 1; 2966 u32 trace_step: 16; 2967 u32 rsvd: 12; 2968 }; 2969 2970 struct rtw89_btc_ctrl_v7 { 2971 u8 manual; 2972 u8 igno_bt; 2973 u8 always_freerun; 2974 u8 rsvd; 2975 } __packed; 2976 2977 union rtw89_btc_ctrl_list { 2978 struct rtw89_btc_ctrl ctrl; 2979 struct rtw89_btc_ctrl_v7 ctrl_v7; 2980 }; 2981 2982 struct rtw89_btc_dbg { 2983 /* cmd "rb" */ 2984 bool rb_done; 2985 u32 rb_val; 2986 }; 2987 2988 enum rtw89_btc_btf_fw_event { 2989 BTF_EVNT_RPT = 0, 2990 BTF_EVNT_BT_INFO = 1, 2991 BTF_EVNT_BT_SCBD = 2, 2992 BTF_EVNT_BT_REG = 3, 2993 BTF_EVNT_CX_RUNINFO = 4, 2994 BTF_EVNT_BT_PSD = 5, 2995 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 2996 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 2997 BTF_EVNT_BUF_OVERFLOW, 2998 BTF_EVNT_C2H_LOOPBACK, 2999 BTF_EVNT_MAX, 3000 }; 3001 3002 enum btf_fw_event_report { 3003 BTC_RPT_TYPE_CTRL = 0x0, 3004 BTC_RPT_TYPE_TDMA, 3005 BTC_RPT_TYPE_SLOT, 3006 BTC_RPT_TYPE_CYSTA, 3007 BTC_RPT_TYPE_STEP, 3008 BTC_RPT_TYPE_NULLSTA, 3009 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3010 BTC_RPT_TYPE_MREG, 3011 BTC_RPT_TYPE_GPIO_DBG, 3012 BTC_RPT_TYPE_BT_VER, 3013 BTC_RPT_TYPE_BT_SCAN, 3014 BTC_RPT_TYPE_BT_AFH, 3015 BTC_RPT_TYPE_BT_DEVICE, 3016 BTC_RPT_TYPE_TEST, 3017 BTC_RPT_TYPE_MAX = 31, 3018 3019 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3020 __BTC_RPT_TYPE_V0_MAX = 12, 3021 }; 3022 3023 enum rtw_btc_btf_reg_type { 3024 REG_MAC = 0x0, 3025 REG_BB = 0x1, 3026 REG_RF = 0x2, 3027 REG_BT_RF = 0x3, 3028 REG_BT_MODEM = 0x4, 3029 REG_BT_BLUEWIZE = 0x5, 3030 REG_BT_VENDOR = 0x6, 3031 REG_BT_LE = 0x7, 3032 REG_MAX_TYPE, 3033 }; 3034 3035 struct rtw89_btc_rpt_cmn_info { 3036 u32 rx_cnt; 3037 u32 rx_len; 3038 u32 req_len; /* expected rsp len */ 3039 u8 req_fver; /* expected rsp fver */ 3040 u8 rsp_fver; /* fver from fw */ 3041 u8 valid; 3042 } __packed; 3043 3044 union rtw89_btc_fbtc_btafh_info { 3045 struct rtw89_btc_fbtc_btafh v1; 3046 struct rtw89_btc_fbtc_btafh_v2 v2; 3047 struct rtw89_btc_fbtc_btafh_v7 v7; 3048 }; 3049 3050 struct rtw89_btc_report_ctrl_state { 3051 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3052 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3053 }; 3054 3055 struct rtw89_btc_rpt_fbtc_tdma { 3056 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3057 union rtw89_btc_fbtc_tdma_le32 finfo; 3058 }; 3059 3060 struct rtw89_btc_rpt_fbtc_slots { 3061 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3062 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3063 }; 3064 3065 struct rtw89_btc_rpt_fbtc_cysta { 3066 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3067 union rtw89_btc_fbtc_cysta_info finfo; 3068 }; 3069 3070 struct rtw89_btc_rpt_fbtc_step { 3071 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3072 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3073 }; 3074 3075 struct rtw89_btc_rpt_fbtc_nullsta { 3076 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3077 union rtw89_btc_fbtc_cynullsta_info finfo; 3078 }; 3079 3080 struct rtw89_btc_rpt_fbtc_mreg { 3081 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3082 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3083 }; 3084 3085 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3086 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3087 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3088 }; 3089 3090 struct rtw89_btc_rpt_fbtc_btver { 3091 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3092 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3093 }; 3094 3095 struct rtw89_btc_rpt_fbtc_btscan { 3096 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3097 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3098 }; 3099 3100 struct rtw89_btc_rpt_fbtc_btafh { 3101 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3102 union rtw89_btc_fbtc_btafh_info finfo; 3103 }; 3104 3105 struct rtw89_btc_rpt_fbtc_btdev { 3106 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3107 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3108 }; 3109 3110 enum rtw89_btc_btfre_type { 3111 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3112 BTFRE_UNDEF_TYPE, 3113 BTFRE_EXCEPTION, 3114 BTFRE_MAX, 3115 }; 3116 3117 struct rtw89_btc_btf_fwinfo { 3118 u32 cnt_c2h; 3119 u32 cnt_h2c; 3120 u32 cnt_h2c_fail; 3121 u32 event[BTF_EVNT_MAX]; 3122 3123 u32 err[BTFRE_MAX]; 3124 u32 len_mismch; 3125 u32 fver_mismch; 3126 u32 rpt_en_map; 3127 3128 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3129 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3130 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3131 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3132 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3133 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3134 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3135 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3136 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3137 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3138 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3139 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3140 }; 3141 3142 struct rtw89_btc_ver { 3143 enum rtw89_core_chip_id chip_id; 3144 u32 fw_ver_code; 3145 3146 u8 fcxbtcrpt; 3147 u8 fcxtdma; 3148 u8 fcxslots; 3149 u8 fcxcysta; 3150 u8 fcxstep; 3151 u8 fcxnullsta; 3152 u8 fcxmreg; 3153 u8 fcxgpiodbg; 3154 u8 fcxbtver; 3155 u8 fcxbtscan; 3156 u8 fcxbtafh; 3157 u8 fcxbtdevinfo; 3158 u8 fwlrole; 3159 u8 frptmap; 3160 u8 fcxctrl; 3161 u8 fcxinit; 3162 3163 u8 fwevntrptl; 3164 u8 fwc2hfunc; 3165 u8 drvinfo_type; 3166 u16 info_buf; 3167 u8 max_role_num; 3168 }; 3169 3170 #define RTW89_BTC_POLICY_MAXLEN 512 3171 3172 struct rtw89_btc { 3173 const struct rtw89_btc_ver *ver; 3174 3175 struct rtw89_btc_cx cx; 3176 struct rtw89_btc_dm dm; 3177 union rtw89_btc_ctrl_list ctrl; 3178 union rtw89_btc_module_info mdinfo; 3179 struct rtw89_btc_btf_fwinfo fwinfo; 3180 struct rtw89_btc_dbg dbg; 3181 3182 struct wiphy_work eapol_notify_work; 3183 struct wiphy_work arp_notify_work; 3184 struct wiphy_work dhcp_notify_work; 3185 struct wiphy_work icmp_notify_work; 3186 3187 u32 bt_req_len; 3188 3189 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3190 u8 ant_type; 3191 u8 btg_pos; 3192 u16 policy_len; 3193 u16 policy_type; 3194 u32 hubmsg_cnt; 3195 bool bt_req_en; 3196 bool update_policy_force; 3197 bool lps; 3198 bool manual_ctrl; 3199 }; 3200 3201 enum rtw89_btc_hmsg { 3202 RTW89_BTC_HMSG_TMR_EN = 0x0, 3203 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3204 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3205 RTW89_BTC_HMSG_FW_EV = 0x3, 3206 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3207 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3208 3209 NUM_OF_RTW89_BTC_HMSG, 3210 }; 3211 3212 enum rtw89_ra_mode { 3213 RTW89_RA_MODE_CCK = BIT(0), 3214 RTW89_RA_MODE_OFDM = BIT(1), 3215 RTW89_RA_MODE_HT = BIT(2), 3216 RTW89_RA_MODE_VHT = BIT(3), 3217 RTW89_RA_MODE_HE = BIT(4), 3218 RTW89_RA_MODE_EHT = BIT(5), 3219 }; 3220 3221 enum rtw89_ra_report_mode { 3222 RTW89_RA_RPT_MODE_LEGACY, 3223 RTW89_RA_RPT_MODE_HT, 3224 RTW89_RA_RPT_MODE_VHT, 3225 RTW89_RA_RPT_MODE_HE, 3226 RTW89_RA_RPT_MODE_EHT, 3227 }; 3228 3229 enum rtw89_dig_noisy_level { 3230 RTW89_DIG_NOISY_LEVEL0 = -1, 3231 RTW89_DIG_NOISY_LEVEL1 = 0, 3232 RTW89_DIG_NOISY_LEVEL2 = 1, 3233 RTW89_DIG_NOISY_LEVEL3 = 2, 3234 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3235 }; 3236 3237 enum rtw89_gi_ltf { 3238 RTW89_GILTF_LGI_4XHE32 = 0, 3239 RTW89_GILTF_SGI_4XHE08 = 1, 3240 RTW89_GILTF_2XHE16 = 2, 3241 RTW89_GILTF_2XHE08 = 3, 3242 RTW89_GILTF_1XHE16 = 4, 3243 RTW89_GILTF_1XHE08 = 5, 3244 RTW89_GILTF_MAX 3245 }; 3246 3247 enum rtw89_rx_frame_type { 3248 RTW89_RX_TYPE_MGNT = 0, 3249 RTW89_RX_TYPE_CTRL = 1, 3250 RTW89_RX_TYPE_DATA = 2, 3251 RTW89_RX_TYPE_RSVD = 3, 3252 }; 3253 3254 enum rtw89_efuse_block { 3255 RTW89_EFUSE_BLOCK_SYS = 0, 3256 RTW89_EFUSE_BLOCK_RF = 1, 3257 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3258 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3259 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3260 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3261 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3262 RTW89_EFUSE_BLOCK_ADIE = 7, 3263 3264 RTW89_EFUSE_BLOCK_NUM, 3265 RTW89_EFUSE_BLOCK_IGNORE, 3266 }; 3267 3268 struct rtw89_ra_info { 3269 u8 is_dis_ra:1; 3270 /* Bit0 : CCK 3271 * Bit1 : OFDM 3272 * Bit2 : HT 3273 * Bit3 : VHT 3274 * Bit4 : HE 3275 * Bit5 : EHT 3276 */ 3277 u8 mode_ctrl:6; 3278 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3279 u8 macid; 3280 u8 dcm_cap:1; 3281 u8 er_cap:1; 3282 u8 init_rate_lv:2; 3283 u8 upd_all:1; 3284 u8 en_sgi:1; 3285 u8 ldpc_cap:1; 3286 u8 stbc_cap:1; 3287 u8 ss_num:3; 3288 u8 giltf:3; 3289 u8 upd_bw_nss_mask:1; 3290 u8 upd_mask:1; 3291 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3292 /* BFee CSI */ 3293 u8 band_num; 3294 u8 ra_csi_rate_en:1; 3295 u8 fixed_csi_rate_en:1; 3296 u8 cr_tbl_sel:1; 3297 u8 fix_giltf_en:1; 3298 u8 fix_giltf:3; 3299 u8 rsvd2:1; 3300 u8 csi_mcs_ss_idx; 3301 u8 csi_mode:2; 3302 u8 csi_gi_ltf:3; 3303 u8 csi_bw:3; 3304 }; 3305 3306 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3307 #define RTW89_PPDU_MAC_INFO_SIZE 8 3308 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3309 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3310 3311 #define RTW89_MAX_RX_AGG_NUM 64 3312 #define RTW89_MAX_TX_AGG_NUM 128 3313 3314 struct rtw89_ampdu_params { 3315 u16 agg_num; 3316 bool amsdu; 3317 }; 3318 3319 struct rtw89_ra_report { 3320 struct rate_info txrate; 3321 u32 bit_rate; 3322 u16 hw_rate; 3323 bool might_fallback_legacy; 3324 }; 3325 3326 DECLARE_EWMA(rssi, 10, 16); 3327 DECLARE_EWMA(evm, 10, 16); 3328 DECLARE_EWMA(snr, 10, 16); 3329 3330 struct rtw89_ba_cam_entry { 3331 struct list_head list; 3332 u8 tid; 3333 }; 3334 3335 #define RTW89_MAX_ADDR_CAM_NUM 128 3336 #define RTW89_MAX_BSSID_CAM_NUM 20 3337 #define RTW89_MAX_SEC_CAM_NUM 128 3338 #define RTW89_MAX_BA_CAM_NUM 24 3339 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3340 3341 struct rtw89_addr_cam_entry { 3342 u8 addr_cam_idx; 3343 u8 offset; 3344 u8 len; 3345 u8 valid : 1; 3346 u8 addr_mask : 6; 3347 u8 wapi : 1; 3348 u8 mask_sel : 2; 3349 u8 bssid_cam_idx: 6; 3350 3351 u8 sec_ent_mode; 3352 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3353 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3354 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3355 }; 3356 3357 struct rtw89_bssid_cam_entry { 3358 u8 bssid[ETH_ALEN]; 3359 u8 phy_idx; 3360 u8 bssid_cam_idx; 3361 u8 offset; 3362 u8 len; 3363 u8 valid : 1; 3364 u8 num; 3365 }; 3366 3367 struct rtw89_sec_cam_entry { 3368 u8 sec_cam_idx; 3369 u8 offset; 3370 u8 len; 3371 u8 type : 4; 3372 u8 ext_key : 1; 3373 u8 spp_mode : 1; 3374 /* 256 bits */ 3375 u8 key[32]; 3376 3377 struct ieee80211_key_conf *key_conf; 3378 }; 3379 3380 struct rtw89_sta_link { 3381 struct rtw89_sta *rtwsta; 3382 unsigned int link_id; 3383 3384 u8 mac_id; 3385 bool er_cap; 3386 struct rtw89_vif_link *rtwvif_link; 3387 struct rtw89_ra_info ra; 3388 struct rtw89_ra_report ra_report; 3389 int max_agg_wait; 3390 u8 prev_rssi; 3391 struct ewma_rssi avg_rssi; 3392 struct ewma_rssi rssi[RF_PATH_MAX]; 3393 struct ewma_snr avg_snr; 3394 struct ewma_evm evm_1ss; 3395 struct ewma_evm evm_min[RF_PATH_MAX]; 3396 struct ewma_evm evm_max[RF_PATH_MAX]; 3397 struct ieee80211_rx_status rx_status; 3398 u16 rx_hw_rate; 3399 __le32 htc_template; 3400 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3401 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3402 struct list_head ba_cam_list; 3403 3404 bool use_cfg_mask; 3405 struct cfg80211_bitrate_mask mask; 3406 3407 bool cctl_tx_time; 3408 u32 ampdu_max_time:4; 3409 bool cctl_tx_retry_limit; 3410 u32 data_tx_cnt_lmt:6; 3411 }; 3412 3413 struct rtw89_efuse { 3414 bool valid; 3415 bool power_k_valid; 3416 u8 xtal_cap; 3417 u8 addr[ETH_ALEN]; 3418 u8 rfe_type; 3419 char country_code[2]; 3420 }; 3421 3422 struct rtw89_phy_rate_pattern { 3423 u64 ra_mask; 3424 u16 rate; 3425 u8 ra_mode; 3426 bool enable; 3427 }; 3428 3429 struct rtw89_tx_wait_info { 3430 struct rcu_head rcu_head; 3431 struct completion completion; 3432 bool tx_done; 3433 }; 3434 3435 struct rtw89_tx_skb_data { 3436 struct rtw89_tx_wait_info __rcu *wait; 3437 u8 hci_priv[]; 3438 }; 3439 3440 #define RTW89_ROC_IDLE_TIMEOUT 500 3441 #define RTW89_ROC_TX_TIMEOUT 30 3442 enum rtw89_roc_state { 3443 RTW89_ROC_IDLE, 3444 RTW89_ROC_NORMAL, 3445 RTW89_ROC_MGMT, 3446 }; 3447 3448 #define RTW89_ROC_BY_LINK_INDEX 0 3449 3450 struct rtw89_roc { 3451 struct ieee80211_channel chan; 3452 struct wiphy_delayed_work roc_work; 3453 enum ieee80211_roc_type type; 3454 enum rtw89_roc_state state; 3455 int duration; 3456 }; 3457 3458 #define RTW89_P2P_MAX_NOA_NUM 2 3459 3460 struct rtw89_p2p_ie_head { 3461 u8 eid; 3462 u8 ie_len; 3463 u8 oui[3]; 3464 u8 oui_type; 3465 } __packed; 3466 3467 struct rtw89_noa_attr_head { 3468 u8 attr_type; 3469 __le16 attr_len; 3470 u8 index; 3471 u8 oppps_ctwindow; 3472 } __packed; 3473 3474 struct rtw89_p2p_noa_ie { 3475 struct rtw89_p2p_ie_head p2p_head; 3476 struct rtw89_noa_attr_head noa_head; 3477 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3478 } __packed; 3479 3480 struct rtw89_p2p_noa_setter { 3481 struct rtw89_p2p_noa_ie ie; 3482 u8 noa_count; 3483 u8 noa_index; 3484 }; 3485 3486 struct rtw89_vif_link { 3487 struct rtw89_vif *rtwvif; 3488 unsigned int link_id; 3489 3490 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3491 enum rtw89_chanctx_idx chanctx_idx; 3492 enum rtw89_reg_6ghz_power reg_6ghz_power; 3493 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3494 3495 u8 mac_id; 3496 u8 port; 3497 u8 mac_addr[ETH_ALEN]; 3498 u8 bssid[ETH_ALEN]; 3499 u8 phy_idx; 3500 u8 mac_idx; 3501 u8 net_type; 3502 u8 wifi_role; 3503 u8 self_role; 3504 u8 wmm; 3505 u8 bcn_hit_cond; 3506 u8 bcn_bw_idx; 3507 u8 hit_rule; 3508 u8 last_noa_nr; 3509 u64 sync_bcn_tsf; 3510 bool trigger; 3511 bool lsig_txop; 3512 u8 tgt_ind; 3513 u8 frm_tgt_ind; 3514 bool wowlan_pattern; 3515 bool wowlan_uc; 3516 bool wowlan_magic; 3517 bool is_hesta; 3518 bool last_a_ctrl; 3519 bool dyn_tb_bedge_en; 3520 bool pre_pwr_diff_en; 3521 bool pwr_diff_en; 3522 u8 def_tri_idx; 3523 struct wiphy_work update_beacon_work; 3524 struct rtw89_addr_cam_entry addr_cam; 3525 struct rtw89_bssid_cam_entry bssid_cam; 3526 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3527 struct rtw89_phy_rate_pattern rate_pattern; 3528 struct list_head general_pkt_list; 3529 struct rtw89_p2p_noa_setter p2p_noa; 3530 }; 3531 3532 enum rtw89_lv1_rcvy_step { 3533 RTW89_LV1_RCVY_STEP_1, 3534 RTW89_LV1_RCVY_STEP_2, 3535 }; 3536 3537 struct rtw89_hci_ops { 3538 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3539 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3540 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3541 void (*reset)(struct rtw89_dev *rtwdev); 3542 int (*start)(struct rtw89_dev *rtwdev); 3543 void (*stop)(struct rtw89_dev *rtwdev); 3544 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3545 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3546 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3547 3548 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3549 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3550 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3551 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3552 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3553 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3554 3555 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3556 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3557 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3558 int (*deinit)(struct rtw89_dev *rtwdev); 3559 3560 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3561 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3562 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3563 int (*napi_poll)(struct napi_struct *napi, int budget); 3564 3565 /* Deal with locks inside recovery_start and recovery_complete callbacks 3566 * by hci instance, and handle things which need to consider under SER. 3567 * e.g. turn on/off interrupts except for the one for halt notification. 3568 */ 3569 void (*recovery_start)(struct rtw89_dev *rtwdev); 3570 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3571 3572 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3573 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3574 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3575 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3576 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3577 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3578 void (*disable_intr)(struct rtw89_dev *rtwdev); 3579 void (*enable_intr)(struct rtw89_dev *rtwdev); 3580 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3581 }; 3582 3583 struct rtw89_hci_info { 3584 const struct rtw89_hci_ops *ops; 3585 enum rtw89_hci_type type; 3586 u32 rpwm_addr; 3587 u32 cpwm_addr; 3588 bool paused; 3589 }; 3590 3591 struct rtw89_chip_ops { 3592 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3593 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3594 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3595 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3596 void (*bb_reset)(struct rtw89_dev *rtwdev, 3597 enum rtw89_phy_idx phy_idx); 3598 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3599 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3600 u32 addr, u32 mask); 3601 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3602 u32 addr, u32 mask, u32 data); 3603 void (*set_channel)(struct rtw89_dev *rtwdev, 3604 const struct rtw89_chan *chan, 3605 enum rtw89_mac_idx mac_idx, 3606 enum rtw89_phy_idx phy_idx); 3607 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3608 struct rtw89_channel_help_params *p, 3609 const struct rtw89_chan *chan, 3610 enum rtw89_mac_idx mac_idx, 3611 enum rtw89_phy_idx phy_idx); 3612 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3613 enum rtw89_efuse_block block); 3614 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3615 void (*fem_setup)(struct rtw89_dev *rtwdev); 3616 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3617 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3618 void (*rfk_init)(struct rtw89_dev *rtwdev); 3619 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3620 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3621 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3622 enum rtw89_phy_idx phy_idx, 3623 const struct rtw89_chan *chan); 3624 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3625 bool start); 3626 void (*rfk_track)(struct rtw89_dev *rtwdev); 3627 void (*power_trim)(struct rtw89_dev *rtwdev); 3628 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3629 const struct rtw89_chan *chan, 3630 enum rtw89_phy_idx phy_idx); 3631 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3632 enum rtw89_phy_idx phy_idx); 3633 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3634 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3635 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3636 enum rtw89_phy_idx phy_idx); 3637 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3638 struct rtw89_rx_phy_ppdu *phy_ppdu, 3639 struct ieee80211_rx_status *status); 3640 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3641 struct rtw89_rx_phy_ppdu *phy_ppdu); 3642 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3643 struct rtw89_rx_desc_info *desc_info, 3644 struct ieee80211_rx_status *rx_status); 3645 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3646 enum rtw89_phy_idx phy_idx); 3647 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3648 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3649 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3650 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3651 enum rtw89_phy_idx phy_idx); 3652 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3653 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3654 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3655 struct rtw89_rx_desc_info *desc_info, 3656 u8 *data, u32 data_offset); 3657 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3658 struct rtw89_tx_desc_info *desc_info, 3659 void *txdesc); 3660 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3661 struct rtw89_tx_desc_info *desc_info, 3662 void *txdesc); 3663 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3664 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3665 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3666 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3667 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3668 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3669 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3670 struct rtw89_vif_link *rtwvif_link, 3671 struct rtw89_sta_link *rtwsta_link); 3672 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3673 struct rtw89_vif_link *rtwvif_link, 3674 struct rtw89_sta_link *rtwsta_link); 3675 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3676 struct rtw89_vif_link *rtwvif_link, 3677 struct rtw89_sta_link *rtwsta_link); 3678 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3679 struct rtw89_vif_link *rtwvif_link, 3680 struct rtw89_sta_link *rtwsta_link); 3681 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 3682 struct rtw89_sta_link *rtwsta_link); 3683 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3684 struct rtw89_vif_link *rtwvif_link, 3685 struct rtw89_sta_link *rtwsta_link); 3686 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3687 struct rtw89_vif_link *rtwvif_link); 3688 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3689 struct rtw89_vif_link *rtwvif_link, 3690 struct rtw89_sta_link *rtwsta_link, 3691 bool valid, struct ieee80211_ampdu_params *params); 3692 3693 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3694 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3695 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3696 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3697 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3698 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3699 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3700 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3701 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3702 }; 3703 3704 enum rtw89_dma_ch { 3705 RTW89_DMA_ACH0 = 0, 3706 RTW89_DMA_ACH1 = 1, 3707 RTW89_DMA_ACH2 = 2, 3708 RTW89_DMA_ACH3 = 3, 3709 RTW89_DMA_ACH4 = 4, 3710 RTW89_DMA_ACH5 = 5, 3711 RTW89_DMA_ACH6 = 6, 3712 RTW89_DMA_ACH7 = 7, 3713 RTW89_DMA_B0MG = 8, 3714 RTW89_DMA_B0HI = 9, 3715 RTW89_DMA_B1MG = 10, 3716 RTW89_DMA_B1HI = 11, 3717 RTW89_DMA_H2C = 12, 3718 RTW89_DMA_CH_NUM = 13 3719 }; 3720 3721 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3722 3723 enum rtw89_mlo_dbcc_mode { 3724 MLO_DBCC_NOT_SUPPORT = 1, 3725 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3726 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3727 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3728 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3729 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3730 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3731 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3732 DBCC_LEGACY = 0xffffffff, 3733 }; 3734 3735 enum rtw89_scan_be_operation { 3736 RTW89_SCAN_OP_STOP, 3737 RTW89_SCAN_OP_START, 3738 RTW89_SCAN_OP_SETPARM, 3739 RTW89_SCAN_OP_GETRPT, 3740 RTW89_SCAN_OP_NUM 3741 }; 3742 3743 enum rtw89_scan_be_mode { 3744 RTW89_SCAN_MODE_SA, 3745 RTW89_SCAN_MODE_MACC, 3746 RTW89_SCAN_MODE_NUM 3747 }; 3748 3749 enum rtw89_scan_be_opmode { 3750 RTW89_SCAN_OPMODE_NONE, 3751 RTW89_SCAN_OPMODE_TBTT, 3752 RTW89_SCAN_OPMODE_INTV, 3753 RTW89_SCAN_OPMODE_CNT, 3754 RTW89_SCAN_OPMODE_NUM, 3755 }; 3756 3757 struct rtw89_scan_option { 3758 bool enable; 3759 bool target_ch_mode; 3760 u8 num_macc_role; 3761 u8 num_opch; 3762 u8 repeat; 3763 u16 norm_pd; 3764 u16 slow_pd; 3765 u16 norm_cy; 3766 u8 opch_end; 3767 u16 delay; 3768 u64 prohib_chan; 3769 enum rtw89_phy_idx band; 3770 enum rtw89_scan_be_operation operation; 3771 enum rtw89_scan_be_mode scan_mode; 3772 enum rtw89_mlo_dbcc_mode mlo_mode; 3773 }; 3774 3775 enum rtw89_qta_mode { 3776 RTW89_QTA_SCC, 3777 RTW89_QTA_DBCC, 3778 RTW89_QTA_DLFW, 3779 RTW89_QTA_WOW, 3780 3781 /* keep last */ 3782 RTW89_QTA_INVALID, 3783 }; 3784 3785 struct rtw89_hfc_ch_cfg { 3786 u16 min; 3787 u16 max; 3788 #define grp_0 0 3789 #define grp_1 1 3790 #define grp_num 2 3791 u8 grp; 3792 }; 3793 3794 struct rtw89_hfc_ch_info { 3795 u16 aval; 3796 u16 used; 3797 }; 3798 3799 struct rtw89_hfc_pub_cfg { 3800 u16 grp0; 3801 u16 grp1; 3802 u16 pub_max; 3803 u16 wp_thrd; 3804 }; 3805 3806 struct rtw89_hfc_pub_info { 3807 u16 g0_used; 3808 u16 g1_used; 3809 u16 g0_aval; 3810 u16 g1_aval; 3811 u16 pub_aval; 3812 u16 wp_aval; 3813 }; 3814 3815 struct rtw89_hfc_prec_cfg { 3816 u16 ch011_prec; 3817 u16 h2c_prec; 3818 u16 wp_ch07_prec; 3819 u16 wp_ch811_prec; 3820 u8 ch011_full_cond; 3821 u8 h2c_full_cond; 3822 u8 wp_ch07_full_cond; 3823 u8 wp_ch811_full_cond; 3824 }; 3825 3826 struct rtw89_hfc_param { 3827 bool en; 3828 bool h2c_en; 3829 u8 mode; 3830 const struct rtw89_hfc_ch_cfg *ch_cfg; 3831 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3832 struct rtw89_hfc_pub_cfg pub_cfg; 3833 struct rtw89_hfc_pub_info pub_info; 3834 struct rtw89_hfc_prec_cfg prec_cfg; 3835 }; 3836 3837 struct rtw89_hfc_param_ini { 3838 const struct rtw89_hfc_ch_cfg *ch_cfg; 3839 const struct rtw89_hfc_pub_cfg *pub_cfg; 3840 const struct rtw89_hfc_prec_cfg *prec_cfg; 3841 u8 mode; 3842 }; 3843 3844 struct rtw89_dle_size { 3845 u16 pge_size; 3846 u16 lnk_pge_num; 3847 u16 unlnk_pge_num; 3848 /* for WiFi 7 chips below */ 3849 u32 srt_ofst; 3850 }; 3851 3852 struct rtw89_wde_quota { 3853 u16 hif; 3854 u16 wcpu; 3855 u16 pkt_in; 3856 u16 cpu_io; 3857 }; 3858 3859 struct rtw89_ple_quota { 3860 u16 cma0_tx; 3861 u16 cma1_tx; 3862 u16 c2h; 3863 u16 h2c; 3864 u16 wcpu; 3865 u16 mpdu_proc; 3866 u16 cma0_dma; 3867 u16 cma1_dma; 3868 u16 bb_rpt; 3869 u16 wd_rel; 3870 u16 cpu_io; 3871 u16 tx_rpt; 3872 /* for WiFi 7 chips below */ 3873 u16 h2d; 3874 }; 3875 3876 struct rtw89_rsvd_quota { 3877 u16 mpdu_info_tbl; 3878 u16 b0_csi; 3879 u16 b1_csi; 3880 u16 b0_lmr; 3881 u16 b1_lmr; 3882 u16 b0_ftm; 3883 u16 b1_ftm; 3884 u16 b0_smr; 3885 u16 b1_smr; 3886 u16 others; 3887 }; 3888 3889 struct rtw89_dle_rsvd_size { 3890 u32 srt_ofst; 3891 u32 size; 3892 }; 3893 3894 struct rtw89_dle_mem { 3895 enum rtw89_qta_mode mode; 3896 const struct rtw89_dle_size *wde_size; 3897 const struct rtw89_dle_size *ple_size; 3898 const struct rtw89_wde_quota *wde_min_qt; 3899 const struct rtw89_wde_quota *wde_max_qt; 3900 const struct rtw89_ple_quota *ple_min_qt; 3901 const struct rtw89_ple_quota *ple_max_qt; 3902 /* for WiFi 7 chips below */ 3903 const struct rtw89_rsvd_quota *rsvd_qt; 3904 const struct rtw89_dle_rsvd_size *rsvd0_size; 3905 const struct rtw89_dle_rsvd_size *rsvd1_size; 3906 }; 3907 3908 struct rtw89_reg_def { 3909 u32 addr; 3910 u32 mask; 3911 }; 3912 3913 struct rtw89_reg2_def { 3914 u32 addr; 3915 u32 data; 3916 }; 3917 3918 struct rtw89_reg3_def { 3919 u32 addr; 3920 u32 mask; 3921 u32 data; 3922 }; 3923 3924 struct rtw89_reg5_def { 3925 u8 flag; /* recognized by parsers */ 3926 u8 path; 3927 u32 addr; 3928 u32 mask; 3929 u32 data; 3930 }; 3931 3932 struct rtw89_reg_imr { 3933 u32 addr; 3934 u32 clr; 3935 u32 set; 3936 }; 3937 3938 struct rtw89_phy_table { 3939 const struct rtw89_reg2_def *regs; 3940 u32 n_regs; 3941 enum rtw89_rf_path rf_path; 3942 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3943 enum rtw89_rf_path rf_path, void *data); 3944 }; 3945 3946 struct rtw89_txpwr_table { 3947 const void *data; 3948 u32 size; 3949 void (*load)(struct rtw89_dev *rtwdev, 3950 const struct rtw89_txpwr_table *tbl); 3951 }; 3952 3953 struct rtw89_txpwr_rule_2ghz { 3954 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3955 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3956 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3957 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3958 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3959 }; 3960 3961 struct rtw89_txpwr_rule_5ghz { 3962 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3963 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3964 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3965 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3966 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3967 }; 3968 3969 struct rtw89_txpwr_rule_6ghz { 3970 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3971 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3972 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3973 [RTW89_6G_CH_NUM]; 3974 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3975 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3976 [RTW89_6G_CH_NUM]; 3977 }; 3978 3979 struct rtw89_tx_shape { 3980 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3981 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3982 }; 3983 3984 struct rtw89_rfe_parms { 3985 const struct rtw89_txpwr_table *byr_tbl; 3986 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3987 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3988 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3989 struct rtw89_tx_shape tx_shape; 3990 }; 3991 3992 struct rtw89_rfe_parms_conf { 3993 const struct rtw89_rfe_parms *rfe_parms; 3994 u8 rfe_type; 3995 }; 3996 3997 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3998 3999 struct rtw89_txpwr_conf { 4000 u8 rfe_type; 4001 u8 ent_sz; 4002 u32 num_ents; 4003 const void *data; 4004 }; 4005 4006 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4007 const struct rtw89_txpwr_conf *conf) 4008 { 4009 u8 valid_size = min(size, conf->ent_sz); 4010 4011 memcpy(entry, cursor, valid_size); 4012 return true; 4013 } 4014 4015 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4016 4017 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4018 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4019 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4020 (cursor) += (conf)->ent_sz) \ 4021 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4022 4023 struct rtw89_txpwr_byrate_data { 4024 struct rtw89_txpwr_conf conf; 4025 struct rtw89_txpwr_table tbl; 4026 }; 4027 4028 struct rtw89_txpwr_lmt_2ghz_data { 4029 struct rtw89_txpwr_conf conf; 4030 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4031 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4032 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4033 }; 4034 4035 struct rtw89_txpwr_lmt_5ghz_data { 4036 struct rtw89_txpwr_conf conf; 4037 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4038 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4039 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4040 }; 4041 4042 struct rtw89_txpwr_lmt_6ghz_data { 4043 struct rtw89_txpwr_conf conf; 4044 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4045 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4046 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4047 [RTW89_6G_CH_NUM]; 4048 }; 4049 4050 struct rtw89_txpwr_lmt_ru_2ghz_data { 4051 struct rtw89_txpwr_conf conf; 4052 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4053 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4054 }; 4055 4056 struct rtw89_txpwr_lmt_ru_5ghz_data { 4057 struct rtw89_txpwr_conf conf; 4058 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4059 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4060 }; 4061 4062 struct rtw89_txpwr_lmt_ru_6ghz_data { 4063 struct rtw89_txpwr_conf conf; 4064 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4065 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4066 [RTW89_6G_CH_NUM]; 4067 }; 4068 4069 struct rtw89_tx_shape_lmt_data { 4070 struct rtw89_txpwr_conf conf; 4071 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4072 }; 4073 4074 struct rtw89_tx_shape_lmt_ru_data { 4075 struct rtw89_txpwr_conf conf; 4076 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4077 }; 4078 4079 struct rtw89_rfe_data { 4080 struct rtw89_txpwr_byrate_data byrate; 4081 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4082 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4083 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4084 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4085 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4086 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4087 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4088 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4089 struct rtw89_rfe_parms rfe_parms; 4090 }; 4091 4092 struct rtw89_page_regs { 4093 u32 hci_fc_ctrl; 4094 u32 ch_page_ctrl; 4095 u32 ach_page_ctrl; 4096 u32 ach_page_info; 4097 u32 pub_page_info3; 4098 u32 pub_page_ctrl1; 4099 u32 pub_page_ctrl2; 4100 u32 pub_page_info1; 4101 u32 pub_page_info2; 4102 u32 wp_page_ctrl1; 4103 u32 wp_page_ctrl2; 4104 u32 wp_page_info1; 4105 }; 4106 4107 struct rtw89_imr_info { 4108 u32 wdrls_imr_set; 4109 u32 wsec_imr_reg; 4110 u32 wsec_imr_set; 4111 u32 mpdu_tx_imr_set; 4112 u32 mpdu_rx_imr_set; 4113 u32 sta_sch_imr_set; 4114 u32 txpktctl_imr_b0_reg; 4115 u32 txpktctl_imr_b0_clr; 4116 u32 txpktctl_imr_b0_set; 4117 u32 txpktctl_imr_b1_reg; 4118 u32 txpktctl_imr_b1_clr; 4119 u32 txpktctl_imr_b1_set; 4120 u32 wde_imr_clr; 4121 u32 wde_imr_set; 4122 u32 ple_imr_clr; 4123 u32 ple_imr_set; 4124 u32 host_disp_imr_clr; 4125 u32 host_disp_imr_set; 4126 u32 cpu_disp_imr_clr; 4127 u32 cpu_disp_imr_set; 4128 u32 other_disp_imr_clr; 4129 u32 other_disp_imr_set; 4130 u32 bbrpt_com_err_imr_reg; 4131 u32 bbrpt_chinfo_err_imr_reg; 4132 u32 bbrpt_err_imr_set; 4133 u32 bbrpt_dfs_err_imr_reg; 4134 u32 ptcl_imr_clr; 4135 u32 ptcl_imr_set; 4136 u32 cdma_imr_0_reg; 4137 u32 cdma_imr_0_clr; 4138 u32 cdma_imr_0_set; 4139 u32 cdma_imr_1_reg; 4140 u32 cdma_imr_1_clr; 4141 u32 cdma_imr_1_set; 4142 u32 phy_intf_imr_reg; 4143 u32 phy_intf_imr_clr; 4144 u32 phy_intf_imr_set; 4145 u32 rmac_imr_reg; 4146 u32 rmac_imr_clr; 4147 u32 rmac_imr_set; 4148 u32 tmac_imr_reg; 4149 u32 tmac_imr_clr; 4150 u32 tmac_imr_set; 4151 }; 4152 4153 struct rtw89_imr_table { 4154 const struct rtw89_reg_imr *regs; 4155 u32 n_regs; 4156 }; 4157 4158 struct rtw89_xtal_info { 4159 u32 xcap_reg; 4160 u32 sc_xo_mask; 4161 u32 sc_xi_mask; 4162 }; 4163 4164 struct rtw89_rrsr_cfgs { 4165 struct rtw89_reg3_def ref_rate; 4166 struct rtw89_reg3_def rsc; 4167 }; 4168 4169 struct rtw89_rfkill_regs { 4170 struct rtw89_reg3_def pinmux; 4171 struct rtw89_reg3_def mode; 4172 }; 4173 4174 struct rtw89_dig_regs { 4175 u32 seg0_pd_reg; 4176 u32 pd_lower_bound_mask; 4177 u32 pd_spatial_reuse_en; 4178 u32 bmode_pd_reg; 4179 u32 bmode_cca_rssi_limit_en; 4180 u32 bmode_pd_lower_bound_reg; 4181 u32 bmode_rssi_nocca_low_th_mask; 4182 struct rtw89_reg_def p0_lna_init; 4183 struct rtw89_reg_def p1_lna_init; 4184 struct rtw89_reg_def p0_tia_init; 4185 struct rtw89_reg_def p1_tia_init; 4186 struct rtw89_reg_def p0_rxb_init; 4187 struct rtw89_reg_def p1_rxb_init; 4188 struct rtw89_reg_def p0_p20_pagcugc_en; 4189 struct rtw89_reg_def p0_s20_pagcugc_en; 4190 struct rtw89_reg_def p1_p20_pagcugc_en; 4191 struct rtw89_reg_def p1_s20_pagcugc_en; 4192 }; 4193 4194 struct rtw89_edcca_regs { 4195 u32 edcca_level; 4196 u32 edcca_mask; 4197 u32 edcca_p_mask; 4198 u32 ppdu_level; 4199 u32 ppdu_mask; 4200 struct rtw89_edcca_p_regs { 4201 u32 rpt_a; 4202 u32 rpt_b; 4203 u32 rpt_sel; 4204 u32 rpt_sel_mask; 4205 } p[RTW89_PHY_NUM]; 4206 u32 rpt_sel_be; 4207 u32 rpt_sel_be_mask; 4208 u32 tx_collision_t2r_st; 4209 u32 tx_collision_t2r_st_mask; 4210 }; 4211 4212 struct rtw89_phy_ul_tb_info { 4213 bool dyn_tb_tri_en; 4214 u8 def_if_bandedge; 4215 }; 4216 4217 struct rtw89_antdiv_stats { 4218 struct ewma_rssi cck_rssi_avg; 4219 struct ewma_rssi ofdm_rssi_avg; 4220 struct ewma_rssi non_legacy_rssi_avg; 4221 u16 pkt_cnt_cck; 4222 u16 pkt_cnt_ofdm; 4223 u16 pkt_cnt_non_legacy; 4224 u32 evm; 4225 }; 4226 4227 struct rtw89_antdiv_info { 4228 struct rtw89_antdiv_stats target_stats; 4229 struct rtw89_antdiv_stats main_stats; 4230 struct rtw89_antdiv_stats aux_stats; 4231 u8 training_count; 4232 u8 rssi_pre; 4233 bool get_stats; 4234 }; 4235 4236 enum rtw89_chanctx_state { 4237 RTW89_CHANCTX_STATE_MCC_START, 4238 RTW89_CHANCTX_STATE_MCC_STOP, 4239 }; 4240 4241 enum rtw89_chanctx_callbacks { 4242 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4243 RTW89_CHANCTX_CALLBACK_RFK, 4244 RTW89_CHANCTX_CALLBACK_TAS, 4245 4246 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4247 }; 4248 4249 struct rtw89_chanctx_listener { 4250 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4251 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4252 }; 4253 4254 struct rtw89_chip_info { 4255 enum rtw89_core_chip_id chip_id; 4256 enum rtw89_chip_gen chip_gen; 4257 const struct rtw89_chip_ops *ops; 4258 const struct rtw89_mac_gen_def *mac_def; 4259 const struct rtw89_phy_gen_def *phy_def; 4260 const char *fw_basename; 4261 u8 fw_format_max; 4262 bool try_ce_fw; 4263 u8 bbmcu_nr; 4264 u32 needed_fw_elms; 4265 const struct rtw89_fw_blacklist *fw_blacklist; 4266 u32 fifo_size; 4267 bool small_fifo_size; 4268 u32 dle_scc_rsvd_size; 4269 u16 max_amsdu_limit; 4270 bool dis_2g_40m_ul_ofdma; 4271 u32 rsvd_ple_ofst; 4272 const struct rtw89_hfc_param_ini *hfc_param_ini; 4273 const struct rtw89_dle_mem *dle_mem; 4274 u8 wde_qempty_acq_grpnum; 4275 u8 wde_qempty_mgq_grpsel; 4276 u32 rf_base_addr[2]; 4277 u8 thermal_th[2]; 4278 u8 support_macid_num; 4279 u8 support_link_num; 4280 u8 support_chanctx_num; 4281 u8 support_bands; 4282 u16 support_bandwidths; 4283 bool support_unii4; 4284 bool support_rnr; 4285 bool support_ant_gain; 4286 bool support_tas; 4287 bool ul_tb_waveform_ctrl; 4288 bool ul_tb_pwr_diff; 4289 bool rx_freq_frome_ie; 4290 bool hw_sec_hdr; 4291 bool hw_mgmt_tx_encrypt; 4292 bool hw_tkip_crypto; 4293 u8 rf_path_num; 4294 u8 tx_nss; 4295 u8 rx_nss; 4296 u8 acam_num; 4297 u8 bcam_num; 4298 u8 scam_num; 4299 u8 bacam_num; 4300 u8 bacam_dynamic_num; 4301 enum rtw89_bacam_ver bacam_ver; 4302 u8 ppdu_max_usr; 4303 4304 u8 sec_ctrl_efuse_size; 4305 u32 physical_efuse_size; 4306 u32 logical_efuse_size; 4307 u32 limit_efuse_size; 4308 u32 dav_phy_efuse_size; 4309 u32 dav_log_efuse_size; 4310 u32 phycap_addr; 4311 u32 phycap_size; 4312 const struct rtw89_efuse_block_cfg *efuse_blocks; 4313 4314 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4315 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4316 const struct rtw89_phy_table *bb_table; 4317 const struct rtw89_phy_table *bb_gain_table; 4318 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4319 const struct rtw89_phy_table *nctl_table; 4320 const struct rtw89_rfk_tbl *nctl_post_table; 4321 const struct rtw89_phy_dig_gain_table *dig_table; 4322 const struct rtw89_dig_regs *dig_regs; 4323 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4324 4325 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4326 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4327 const struct rtw89_rfe_parms *dflt_parms; 4328 const struct rtw89_chanctx_listener *chanctx_listener; 4329 4330 u8 txpwr_factor_bb; 4331 u8 txpwr_factor_rf; 4332 u8 txpwr_factor_mac; 4333 4334 u32 para_ver; 4335 u32 wlcx_desired; 4336 u8 btcx_desired; 4337 u8 scbd; 4338 u8 mailbox; 4339 4340 u8 afh_guard_ch; 4341 const u8 *wl_rssi_thres; 4342 const u8 *bt_rssi_thres; 4343 u8 rssi_tol; 4344 4345 u8 mon_reg_num; 4346 const struct rtw89_btc_fbtc_mreg *mon_reg; 4347 u8 rf_para_ulink_num; 4348 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4349 u8 rf_para_dlink_num; 4350 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4351 u8 ps_mode_supported; 4352 u8 low_power_hci_modes; 4353 4354 u32 h2c_cctl_func_id; 4355 u32 hci_func_en_addr; 4356 u32 h2c_desc_size; 4357 u32 txwd_body_size; 4358 u32 txwd_info_size; 4359 u32 h2c_ctrl_reg; 4360 const u32 *h2c_regs; 4361 struct rtw89_reg_def h2c_counter_reg; 4362 u32 c2h_ctrl_reg; 4363 const u32 *c2h_regs; 4364 struct rtw89_reg_def c2h_counter_reg; 4365 const struct rtw89_page_regs *page_regs; 4366 const u32 *wow_reason_reg; 4367 bool cfo_src_fd; 4368 bool cfo_hw_comp; 4369 const struct rtw89_reg_def *dcfo_comp; 4370 u8 dcfo_comp_sft; 4371 const struct rtw89_imr_info *imr_info; 4372 const struct rtw89_imr_table *imr_dmac_table; 4373 const struct rtw89_imr_table *imr_cmac_table; 4374 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4375 struct rtw89_reg_def bss_clr_vld; 4376 u32 bss_clr_map_reg; 4377 const struct rtw89_rfkill_regs *rfkill_init; 4378 struct rtw89_reg_def rfkill_get; 4379 u32 dma_ch_mask; 4380 const struct rtw89_edcca_regs *edcca_regs; 4381 const struct wiphy_wowlan_support *wowlan_stub; 4382 const struct rtw89_xtal_info *xtal_info; 4383 }; 4384 4385 struct rtw89_chip_variant { 4386 bool no_mcs_12_13: 1; 4387 u32 fw_min_ver_code; 4388 }; 4389 4390 union rtw89_bus_info { 4391 const struct rtw89_pci_info *pci; 4392 }; 4393 4394 struct rtw89_driver_info { 4395 const struct rtw89_chip_info *chip; 4396 const struct rtw89_chip_variant *variant; 4397 const struct dmi_system_id *quirks; 4398 union rtw89_bus_info bus; 4399 }; 4400 4401 enum rtw89_hcifc_mode { 4402 RTW89_HCIFC_POH = 0, 4403 RTW89_HCIFC_STF = 1, 4404 RTW89_HCIFC_SDIO = 2, 4405 4406 /* keep last */ 4407 RTW89_HCIFC_MODE_INVALID, 4408 }; 4409 4410 struct rtw89_dle_info { 4411 const struct rtw89_rsvd_quota *rsvd_qt; 4412 enum rtw89_qta_mode qta_mode; 4413 u16 ple_pg_size; 4414 u16 ple_free_pg; 4415 u16 c0_rx_qta; 4416 u16 c1_rx_qta; 4417 }; 4418 4419 enum rtw89_host_rpr_mode { 4420 RTW89_RPR_MODE_POH = 0, 4421 RTW89_RPR_MODE_STF 4422 }; 4423 4424 #define RTW89_COMPLETION_BUF_SIZE 40 4425 #define RTW89_WAIT_COND_IDLE UINT_MAX 4426 4427 struct rtw89_completion_data { 4428 bool err; 4429 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4430 }; 4431 4432 struct rtw89_wait_info { 4433 atomic_t cond; 4434 struct completion completion; 4435 struct rtw89_completion_data data; 4436 }; 4437 4438 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4439 4440 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4441 { 4442 init_completion(&wait->completion); 4443 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4444 } 4445 4446 struct rtw89_mac_info { 4447 struct rtw89_dle_info dle_info; 4448 struct rtw89_hfc_param hfc_param; 4449 enum rtw89_qta_mode qta_mode; 4450 u8 rpwm_seq_num; 4451 u8 cpwm_seq_num; 4452 4453 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4454 struct rtw89_wait_info fw_ofld_wait; 4455 /* see RTW89_PS_WAIT_COND series for wait condition */ 4456 struct rtw89_wait_info ps_wait; 4457 }; 4458 4459 enum rtw89_fwdl_check_type { 4460 RTW89_FWDL_CHECK_FREERTOS_DONE, 4461 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4462 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4463 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4464 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4465 }; 4466 4467 enum rtw89_fw_type { 4468 RTW89_FW_NORMAL = 1, 4469 RTW89_FW_WOWLAN = 3, 4470 RTW89_FW_NORMAL_CE = 5, 4471 RTW89_FW_BBMCU0 = 64, 4472 RTW89_FW_BBMCU1 = 65, 4473 RTW89_FW_LOGFMT = 255, 4474 }; 4475 4476 enum rtw89_fw_feature { 4477 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4478 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4479 RTW89_FW_FEATURE_TX_WAKE, 4480 RTW89_FW_FEATURE_CRASH_TRIGGER, 4481 RTW89_FW_FEATURE_NO_PACKET_DROP, 4482 RTW89_FW_FEATURE_NO_DEEP_PS, 4483 RTW89_FW_FEATURE_NO_LPS_PG, 4484 RTW89_FW_FEATURE_BEACON_FILTER, 4485 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4486 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4487 RTW89_FW_FEATURE_WOW_REASON_V1, 4488 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4489 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4490 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4491 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4492 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4493 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4494 RTW89_FW_FEATURE_LPS_CH_INFO, 4495 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4496 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 4497 }; 4498 4499 struct rtw89_fw_suit { 4500 enum rtw89_fw_type type; 4501 const u8 *data; 4502 u32 size; 4503 u8 major_ver; 4504 u8 minor_ver; 4505 u8 sub_ver; 4506 u8 sub_idex; 4507 u16 build_year; 4508 u16 build_mon; 4509 u16 build_date; 4510 u16 build_hour; 4511 u16 build_min; 4512 u8 cmd_ver; 4513 u8 hdr_ver; 4514 u32 commitid; 4515 }; 4516 4517 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4518 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4519 #define RTW89_FW_SUIT_VER_CODE(s) \ 4520 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4521 4522 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4523 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4524 (mfw_hdr)->ver.minor, \ 4525 (mfw_hdr)->ver.sub, \ 4526 (mfw_hdr)->ver.idx) 4527 4528 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4529 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4530 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4531 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4532 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4533 4534 struct rtw89_fw_req_info { 4535 const struct firmware *firmware; 4536 struct completion completion; 4537 }; 4538 4539 struct rtw89_fw_log { 4540 struct rtw89_fw_suit suit; 4541 bool enable; 4542 u32 last_fmt_id; 4543 u32 fmt_count; 4544 const __le32 *fmt_ids; 4545 const char *(*fmts)[]; 4546 }; 4547 4548 struct rtw89_fw_elm_info { 4549 struct rtw89_phy_table *bb_tbl; 4550 struct rtw89_phy_table *bb_gain; 4551 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4552 struct rtw89_phy_table *rf_nctl; 4553 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4554 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4555 const struct rtw89_regd_data *regd; 4556 }; 4557 4558 enum rtw89_fw_mss_dev_type { 4559 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4560 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4561 }; 4562 4563 struct rtw89_fw_secure { 4564 bool secure_boot: 1; 4565 bool can_mss_v1: 1; 4566 bool can_mss_v0: 1; 4567 u32 sb_sel_mgn; 4568 u8 mss_dev_type; 4569 u8 mss_cust_idx; 4570 u8 mss_key_num; 4571 u8 mss_idx; /* v0 */ 4572 }; 4573 4574 struct rtw89_fw_info { 4575 struct rtw89_fw_req_info req; 4576 int fw_format; 4577 u8 h2c_seq; 4578 u8 rec_seq; 4579 u8 h2c_counter; 4580 u8 c2h_counter; 4581 struct rtw89_fw_suit normal; 4582 struct rtw89_fw_suit wowlan; 4583 struct rtw89_fw_suit bbmcu0; 4584 struct rtw89_fw_suit bbmcu1; 4585 struct rtw89_fw_log log; 4586 u32 feature_map; 4587 struct rtw89_fw_elm_info elm_info; 4588 struct rtw89_fw_secure sec; 4589 }; 4590 4591 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4592 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4593 4594 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4595 ((_fw)->feature_map |= BIT(_fw_feature)) 4596 4597 struct rtw89_cam_info { 4598 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4599 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4600 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4601 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4602 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4603 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4604 }; 4605 4606 enum rtw89_sar_sources { 4607 RTW89_SAR_SOURCE_NONE, 4608 RTW89_SAR_SOURCE_COMMON, 4609 4610 RTW89_SAR_SOURCE_NR, 4611 }; 4612 4613 enum rtw89_sar_subband { 4614 RTW89_SAR_2GHZ_SUBBAND, 4615 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4616 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4617 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4618 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4619 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4620 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4621 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4622 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4623 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4624 4625 RTW89_SAR_SUBBAND_NR, 4626 }; 4627 4628 struct rtw89_sar_cfg_common { 4629 bool set[RTW89_SAR_SUBBAND_NR]; 4630 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4631 }; 4632 4633 struct rtw89_sar_info { 4634 /* used to decide how to acces SAR cfg union */ 4635 enum rtw89_sar_sources src; 4636 4637 /* reserved for different knids of SAR cfg struct. 4638 * supposed that a single cfg struct cannot handle various SAR sources. 4639 */ 4640 union { 4641 struct rtw89_sar_cfg_common cfg_common; 4642 }; 4643 }; 4644 4645 enum rtw89_ant_gain_subband { 4646 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4647 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4648 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4649 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4650 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4651 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4652 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4653 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4654 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4655 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4656 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4657 4658 RTW89_ANT_GAIN_SUBBAND_NR, 4659 }; 4660 4661 enum rtw89_ant_gain_domain_type { 4662 RTW89_ANT_GAIN_ETSI = 0, 4663 4664 RTW89_ANT_GAIN_DOMAIN_NUM, 4665 }; 4666 4667 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4668 struct rtw89_ant_gain_info { 4669 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4670 u32 regd_enabled; 4671 bool block_country; 4672 }; 4673 4674 struct rtw89_6ghz_span { 4675 enum rtw89_sar_subband sar_subband_low; 4676 enum rtw89_sar_subband sar_subband_high; 4677 enum rtw89_ant_gain_subband ant_gain_subband_low; 4678 enum rtw89_ant_gain_subband ant_gain_subband_high; 4679 }; 4680 4681 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4682 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4683 4684 enum rtw89_tas_state { 4685 RTW89_TAS_STATE_DPR_OFF, 4686 RTW89_TAS_STATE_DPR_ON, 4687 RTW89_TAS_STATE_STATIC_SAR, 4688 }; 4689 4690 #define RTW89_TAS_TX_RATIO_WINDOW 6 4691 #define RTW89_TAS_TXPWR_WINDOW 180 4692 struct rtw89_tas_info { 4693 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 4694 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 4695 u8 txpwr_head_idx; 4696 u8 txpwr_tail_idx; 4697 u8 tx_ratio_idx; 4698 u16 total_tx_ratio; 4699 u64 total_txpwr; 4700 u64 instant_txpwr; 4701 u32 window_size; 4702 s8 dpr_on_threshold; 4703 s8 dpr_off_threshold; 4704 enum rtw89_tas_state backup_state; 4705 enum rtw89_tas_state state; 4706 bool keep_history; 4707 bool block_regd; 4708 bool enable; 4709 bool pause; 4710 }; 4711 4712 struct rtw89_chanctx_cfg { 4713 enum rtw89_chanctx_idx idx; 4714 int ref_count; 4715 }; 4716 4717 enum rtw89_chanctx_changes { 4718 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4719 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4720 RTW89_CHANCTX_P2P_PS_CHANGE, 4721 RTW89_CHANCTX_BT_SLOT_CHANGE, 4722 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4723 4724 NUM_OF_RTW89_CHANCTX_CHANGES, 4725 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4726 }; 4727 4728 enum rtw89_entity_mode { 4729 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4730 RTW89_ENTITY_MODE_MCC_PREPARE, 4731 RTW89_ENTITY_MODE_MCC, 4732 4733 NUM_OF_RTW89_ENTITY_MODE, 4734 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4735 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4736 }; 4737 4738 #define RTW89_MAX_INTERFACE_NUM 2 4739 4740 /* only valid when running with chanctx_ops */ 4741 struct rtw89_entity_mgnt { 4742 struct list_head active_list; 4743 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4744 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4745 [__RTW89_MLD_MAX_LINK_NUM]; 4746 }; 4747 4748 struct rtw89_chanctx { 4749 struct cfg80211_chan_def chandef; 4750 struct rtw89_chan chan; 4751 struct rtw89_chan_rcd rcd; 4752 4753 /* only assigned when running with chanctx_ops */ 4754 struct rtw89_chanctx_cfg *cfg; 4755 }; 4756 4757 struct rtw89_edcca_bak { 4758 u8 a; 4759 u8 p; 4760 u8 ppdu; 4761 u8 th_old; 4762 }; 4763 4764 enum rtw89_dm_type { 4765 RTW89_DM_DYNAMIC_EDCCA, 4766 RTW89_DM_THERMAL_PROTECT, 4767 RTW89_DM_TAS, 4768 }; 4769 4770 #define RTW89_THERMAL_PROT_LV_MAX 5 4771 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 4772 4773 struct rtw89_hal { 4774 u32 rx_fltr; 4775 u8 cv; 4776 u8 acv; 4777 u32 antenna_tx; 4778 u32 antenna_rx; 4779 u8 tx_nss; 4780 u8 rx_nss; 4781 bool tx_path_diversity; 4782 bool ant_diversity; 4783 bool ant_diversity_fixed; 4784 bool support_cckpd; 4785 bool support_igi; 4786 bool no_mcs_12_13; 4787 4788 atomic_t roc_chanctx_idx; 4789 4790 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4791 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4792 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4793 struct cfg80211_chan_def roc_chandef; 4794 4795 bool entity_active[RTW89_PHY_NUM]; 4796 bool entity_pause; 4797 enum rtw89_entity_mode entity_mode; 4798 struct rtw89_entity_mgnt entity_mgnt; 4799 4800 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4801 4802 u8 thermal_prot_th; 4803 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 4804 }; 4805 4806 #define RTW89_MAX_MAC_ID_NUM 128 4807 #define RTW89_MAX_PKT_OFLD_NUM 255 4808 4809 enum rtw89_flags { 4810 RTW89_FLAG_POWERON, 4811 RTW89_FLAG_DMAC_FUNC, 4812 RTW89_FLAG_CMAC0_FUNC, 4813 RTW89_FLAG_CMAC1_FUNC, 4814 RTW89_FLAG_FW_RDY, 4815 RTW89_FLAG_RUNNING, 4816 RTW89_FLAG_PROBE_DONE, 4817 RTW89_FLAG_BFEE_MON, 4818 RTW89_FLAG_BFEE_EN, 4819 RTW89_FLAG_BFEE_TIMER_KEEP, 4820 RTW89_FLAG_NAPI_RUNNING, 4821 RTW89_FLAG_LEISURE_PS, 4822 RTW89_FLAG_LOW_POWER_MODE, 4823 RTW89_FLAG_INACTIVE_PS, 4824 RTW89_FLAG_CRASH_SIMULATING, 4825 RTW89_FLAG_SER_HANDLING, 4826 RTW89_FLAG_WOWLAN, 4827 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4828 RTW89_FLAG_CHANGING_INTERFACE, 4829 RTW89_FLAG_HW_RFKILL_STATE, 4830 4831 NUM_OF_RTW89_FLAGS, 4832 }; 4833 4834 enum rtw89_quirks { 4835 RTW89_QUIRK_PCI_BER, 4836 RTW89_QUIRK_THERMAL_PROT_120C, 4837 RTW89_QUIRK_THERMAL_PROT_110C, 4838 4839 NUM_OF_RTW89_QUIRKS, 4840 }; 4841 4842 enum rtw89_custid { 4843 RTW89_CUSTID_NONE, 4844 RTW89_CUSTID_ACER, 4845 RTW89_CUSTID_AMD, 4846 RTW89_CUSTID_ASUS, 4847 RTW89_CUSTID_DELL, 4848 RTW89_CUSTID_HP, 4849 RTW89_CUSTID_LENOVO, 4850 }; 4851 4852 enum rtw89_pkt_drop_sel { 4853 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4854 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4855 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4856 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4857 RTW89_PKT_DROP_SEL_MACID_ALL, 4858 RTW89_PKT_DROP_SEL_MG0_ONCE, 4859 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4860 RTW89_PKT_DROP_SEL_HIQ_PORT, 4861 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4862 RTW89_PKT_DROP_SEL_BAND, 4863 RTW89_PKT_DROP_SEL_BAND_ONCE, 4864 RTW89_PKT_DROP_SEL_REL_MACID, 4865 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4866 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4867 }; 4868 4869 struct rtw89_pkt_drop_params { 4870 enum rtw89_pkt_drop_sel sel; 4871 enum rtw89_mac_idx mac_band; 4872 u8 macid; 4873 u8 port; 4874 u8 mbssid; 4875 bool tf_trs; 4876 u32 macid_band_sel[4]; 4877 }; 4878 4879 struct rtw89_pkt_stat { 4880 u16 beacon_nr; 4881 u8 beacon_rate; 4882 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4883 }; 4884 4885 DECLARE_EWMA(thermal, 4, 4); 4886 4887 struct rtw89_phy_stat { 4888 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4889 u8 last_thermal_max; 4890 struct ewma_rssi bcn_rssi; 4891 struct rtw89_pkt_stat cur_pkt_stat; 4892 struct rtw89_pkt_stat last_pkt_stat; 4893 }; 4894 4895 enum rtw89_rfk_report_state { 4896 RTW89_RFK_STATE_START = 0x0, 4897 RTW89_RFK_STATE_OK = 0x1, 4898 RTW89_RFK_STATE_FAIL = 0x2, 4899 RTW89_RFK_STATE_TIMEOUT = 0x3, 4900 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4901 }; 4902 4903 struct rtw89_rfk_wait_info { 4904 struct completion completion; 4905 ktime_t start_time; 4906 enum rtw89_rfk_report_state state; 4907 u8 version; 4908 }; 4909 4910 #define RTW89_DACK_PATH_NR 2 4911 #define RTW89_DACK_IDX_NR 2 4912 #define RTW89_DACK_MSBK_NR 16 4913 struct rtw89_dack_info { 4914 bool dack_done; 4915 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4916 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4917 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4918 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4919 u32 dack_cnt; 4920 bool addck_timeout[RTW89_DACK_PATH_NR]; 4921 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4922 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4923 }; 4924 4925 enum rtw89_rfk_chs_nrs { 4926 __RTW89_RFK_CHS_NR_V0 = 2, 4927 __RTW89_RFK_CHS_NR_V1 = 3, 4928 4929 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 4930 }; 4931 4932 struct rtw89_rfk_mcc_info_data { 4933 u8 ch[RTW89_RFK_CHS_NR]; 4934 u8 band[RTW89_RFK_CHS_NR]; 4935 u8 bw[RTW89_RFK_CHS_NR]; 4936 u8 table_idx; 4937 }; 4938 4939 struct rtw89_rfk_mcc_info { 4940 struct rtw89_rfk_mcc_info_data data[2]; 4941 }; 4942 4943 #define RTW89_IQK_CHS_NR 2 4944 #define RTW89_IQK_PATH_NR 4 4945 4946 struct rtw89_lck_info { 4947 u8 thermal[RF_PATH_MAX]; 4948 }; 4949 4950 struct rtw89_rx_dck_info { 4951 u8 thermal[RF_PATH_MAX]; 4952 }; 4953 4954 struct rtw89_iqk_info { 4955 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4956 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4957 bool lok_fail[RTW89_IQK_PATH_NR]; 4958 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4959 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4960 u32 iqk_fail_cnt; 4961 bool is_iqk_init; 4962 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4963 u8 iqk_band[RTW89_IQK_PATH_NR]; 4964 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4965 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4966 u8 iqk_times; 4967 u8 version; 4968 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4969 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4970 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4971 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4972 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4973 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4974 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4975 bool is_nbiqk; 4976 bool iqk_fft_en; 4977 bool iqk_xym_en; 4978 bool iqk_sram_en; 4979 bool iqk_cfir_en; 4980 u32 syn1to2; 4981 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4982 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4983 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4984 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4985 }; 4986 4987 #define RTW89_DPK_RF_PATH 2 4988 #define RTW89_DPK_AVG_THERMAL_NUM 8 4989 #define RTW89_DPK_BKUP_NUM 2 4990 struct rtw89_dpk_bkup_para { 4991 enum rtw89_band band; 4992 enum rtw89_bandwidth bw; 4993 u8 ch; 4994 bool path_ok; 4995 u8 mdpd_en; 4996 u8 txagc_dpk; 4997 u8 ther_dpk; 4998 u8 gs; 4999 u16 pwsf; 5000 }; 5001 5002 struct rtw89_dpk_info { 5003 bool is_dpk_enable; 5004 bool is_dpk_reload_en; 5005 u8 dpk_gs[RTW89_PHY_NUM]; 5006 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5007 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5008 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5009 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5010 u8 cur_idx[RTW89_DPK_RF_PATH]; 5011 u8 cur_k_set; 5012 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5013 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 5014 u32 dpk_order[RTW89_DPK_RF_PATH]; 5015 }; 5016 5017 struct rtw89_fem_info { 5018 bool elna_2g; 5019 bool elna_5g; 5020 bool epa_2g; 5021 bool epa_5g; 5022 bool epa_6g; 5023 }; 5024 5025 struct rtw89_phy_ch_info { 5026 u8 rssi_min; 5027 u16 rssi_min_macid; 5028 u8 pre_rssi_min; 5029 u8 rssi_max; 5030 u16 rssi_max_macid; 5031 u8 rxsc_160; 5032 u8 rxsc_80; 5033 u8 rxsc_40; 5034 u8 rxsc_20; 5035 u8 rxsc_l; 5036 u8 is_noisy; 5037 }; 5038 5039 struct rtw89_agc_gaincode_set { 5040 u8 lna_idx; 5041 u8 tia_idx; 5042 u8 rxb_idx; 5043 }; 5044 5045 #define IGI_RSSI_TH_NUM 5 5046 #define FA_TH_NUM 4 5047 #define TIA_LNA_OP1DB_NUM 8 5048 #define LNA_GAIN_NUM 7 5049 #define TIA_GAIN_NUM 2 5050 struct rtw89_dig_info { 5051 struct rtw89_agc_gaincode_set cur_gaincode; 5052 bool force_gaincode_idx_en; 5053 struct rtw89_agc_gaincode_set force_gaincode; 5054 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5055 u16 fa_th[FA_TH_NUM]; 5056 u8 igi_rssi; 5057 u8 igi_fa_rssi; 5058 u8 fa_rssi_ofst; 5059 u8 dyn_igi_max; 5060 u8 dyn_igi_min; 5061 bool dyn_pd_th_en; 5062 u8 dyn_pd_th_max; 5063 u8 pd_low_th_ofst; 5064 u8 ib_pbk; 5065 s8 ib_pkpwr; 5066 s8 lna_gain_a[LNA_GAIN_NUM]; 5067 s8 lna_gain_g[LNA_GAIN_NUM]; 5068 s8 *lna_gain; 5069 s8 tia_gain_a[TIA_GAIN_NUM]; 5070 s8 tia_gain_g[TIA_GAIN_NUM]; 5071 s8 *tia_gain; 5072 bool is_linked_pre; 5073 bool bypass_dig; 5074 }; 5075 5076 enum rtw89_multi_cfo_mode { 5077 RTW89_PKT_BASED_AVG_MODE = 0, 5078 RTW89_ENTRY_BASED_AVG_MODE = 1, 5079 RTW89_TP_BASED_AVG_MODE = 2, 5080 }; 5081 5082 enum rtw89_phy_cfo_status { 5083 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5084 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5085 RTW89_PHY_DCFO_STATE_HOLD = 2, 5086 RTW89_PHY_DCFO_STATE_MAX 5087 }; 5088 5089 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5090 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5091 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5092 }; 5093 5094 struct rtw89_cfo_tracking_info { 5095 u16 cfo_timer_ms; 5096 bool cfo_trig_by_timer_en; 5097 enum rtw89_phy_cfo_status phy_cfo_status; 5098 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5099 u8 phy_cfo_trk_cnt; 5100 bool is_adjust; 5101 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5102 bool apply_compensation; 5103 u8 crystal_cap; 5104 u8 crystal_cap_default; 5105 u8 def_x_cap; 5106 s8 x_cap_ofst; 5107 u32 sta_cfo_tolerance; 5108 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5109 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5110 s32 cfo_avg_pre; 5111 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5112 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5113 s32 dcfo_avg; 5114 s32 dcfo_avg_pre; 5115 u32 packet_count; 5116 u32 packet_count_pre; 5117 s32 residual_cfo_acc; 5118 u8 phy_cfotrk_state; 5119 u8 phy_cfotrk_cnt; 5120 bool divergence_lock_en; 5121 u8 x_cap_lb; 5122 u8 x_cap_ub; 5123 u8 lock_cnt; 5124 }; 5125 5126 enum rtw89_tssi_mode { 5127 RTW89_TSSI_NORMAL = 0, 5128 RTW89_TSSI_SCAN = 1, 5129 }; 5130 5131 enum rtw89_tssi_alimk_band { 5132 TSSI_ALIMK_2G = 0, 5133 TSSI_ALIMK_5GL, 5134 TSSI_ALIMK_5GM, 5135 TSSI_ALIMK_5GH, 5136 TSSI_ALIMK_MAX 5137 }; 5138 5139 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5140 #define TSSI_TRIM_CH_GROUP_NUM 8 5141 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5142 5143 #define TSSI_CCK_CH_GROUP_NUM 6 5144 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5145 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5146 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5147 #define TSSI_MCS_CH_GROUP_NUM \ 5148 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5149 #define TSSI_MAX_CH_NUM 67 5150 #define TSSI_ALIMK_VALUE_NUM 8 5151 5152 struct rtw89_tssi_info { 5153 u8 thermal[RF_PATH_MAX]; 5154 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5155 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5156 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5157 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5158 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5159 s8 extra_ofst[RF_PATH_MAX]; 5160 bool tssi_tracking_check[RF_PATH_MAX]; 5161 u8 default_txagc_offset[RF_PATH_MAX]; 5162 u32 base_thermal[RF_PATH_MAX]; 5163 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5164 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5165 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5166 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5167 u64 tssi_alimk_time; 5168 }; 5169 5170 struct rtw89_power_trim_info { 5171 bool pg_thermal_trim; 5172 bool pg_pa_bias_trim; 5173 u8 thermal_trim[RF_PATH_MAX]; 5174 u8 pa_bias_trim[RF_PATH_MAX]; 5175 u8 pad_bias_trim[RF_PATH_MAX]; 5176 }; 5177 5178 enum rtw89_regd_func { 5179 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 5180 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 5181 5182 NUM_OF_RTW89_REGD_FUNC, 5183 }; 5184 5185 struct rtw89_regd { 5186 char alpha2[3]; 5187 u8 txpwr_regd[RTW89_BAND_NUM]; 5188 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 5189 }; 5190 5191 struct rtw89_regd_data { 5192 unsigned int nr; 5193 struct rtw89_regd map[] __counted_by(nr); 5194 }; 5195 5196 struct rtw89_regd_ctrl { 5197 unsigned int nr; 5198 const struct rtw89_regd *map; 5199 }; 5200 5201 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5202 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5203 #define RTW89_5GHZ_UNII4_START_INDEX 25 5204 5205 struct rtw89_regulatory_info { 5206 struct rtw89_regd_ctrl ctrl; 5207 const struct rtw89_regd *regd; 5208 enum rtw89_reg_6ghz_power reg_6ghz_power; 5209 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5210 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5211 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5212 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5213 }; 5214 5215 enum rtw89_ifs_clm_application { 5216 RTW89_IFS_CLM_INIT = 0, 5217 RTW89_IFS_CLM_BACKGROUND = 1, 5218 RTW89_IFS_CLM_ACS = 2, 5219 RTW89_IFS_CLM_DIG = 3, 5220 RTW89_IFS_CLM_TDMA_DIG = 4, 5221 RTW89_IFS_CLM_DBG = 5, 5222 RTW89_IFS_CLM_DBG_MANUAL = 6 5223 }; 5224 5225 enum rtw89_env_racing_lv { 5226 RTW89_RAC_RELEASE = 0, 5227 RTW89_RAC_LV_1 = 1, 5228 RTW89_RAC_LV_2 = 2, 5229 RTW89_RAC_LV_3 = 3, 5230 RTW89_RAC_LV_4 = 4, 5231 RTW89_RAC_MAX_NUM = 5 5232 }; 5233 5234 struct rtw89_ccx_para_info { 5235 enum rtw89_env_racing_lv rac_lv; 5236 u16 mntr_time; 5237 u8 nhm_manual_th_ofst; 5238 u8 nhm_manual_th0; 5239 enum rtw89_ifs_clm_application ifs_clm_app; 5240 u32 ifs_clm_manual_th_times; 5241 u32 ifs_clm_manual_th0; 5242 u8 fahm_manual_th_ofst; 5243 u8 fahm_manual_th0; 5244 u8 fahm_numer_opt; 5245 u8 fahm_denom_opt; 5246 }; 5247 5248 enum rtw89_ccx_edcca_opt_sc_idx { 5249 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5250 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5251 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5252 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5253 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5254 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5255 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5256 RTW89_CCX_EDCCA_SEG1_S3 = 7 5257 }; 5258 5259 enum rtw89_ccx_edcca_opt_bw_idx { 5260 RTW89_CCX_EDCCA_BW20_0 = 0, 5261 RTW89_CCX_EDCCA_BW20_1 = 1, 5262 RTW89_CCX_EDCCA_BW20_2 = 2, 5263 RTW89_CCX_EDCCA_BW20_3 = 3, 5264 RTW89_CCX_EDCCA_BW20_4 = 4, 5265 RTW89_CCX_EDCCA_BW20_5 = 5, 5266 RTW89_CCX_EDCCA_BW20_6 = 6, 5267 RTW89_CCX_EDCCA_BW20_7 = 7 5268 }; 5269 5270 #define RTW89_NHM_TH_NUM 11 5271 #define RTW89_FAHM_TH_NUM 11 5272 #define RTW89_NHM_RPT_NUM 12 5273 #define RTW89_FAHM_RPT_NUM 12 5274 #define RTW89_IFS_CLM_NUM 4 5275 struct rtw89_env_monitor_info { 5276 u8 ccx_watchdog_result; 5277 bool ccx_ongoing; 5278 u8 ccx_rac_lv; 5279 bool ccx_manual_ctrl; 5280 u16 ifs_clm_mntr_time; 5281 enum rtw89_ifs_clm_application ifs_clm_app; 5282 u16 ccx_period; 5283 u8 ccx_unit_idx; 5284 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5285 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5286 u16 ifs_clm_tx; 5287 u16 ifs_clm_edcca_excl_cca; 5288 u16 ifs_clm_ofdmfa; 5289 u16 ifs_clm_ofdmcca_excl_fa; 5290 u16 ifs_clm_cckfa; 5291 u16 ifs_clm_cckcca_excl_fa; 5292 u16 ifs_clm_total_ifs; 5293 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5294 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5295 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5296 u8 ifs_clm_tx_ratio; 5297 u8 ifs_clm_edcca_excl_cca_ratio; 5298 u8 ifs_clm_cck_fa_ratio; 5299 u8 ifs_clm_ofdm_fa_ratio; 5300 u8 ifs_clm_cck_cca_excl_fa_ratio; 5301 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5302 u16 ifs_clm_cck_fa_permil; 5303 u16 ifs_clm_ofdm_fa_permil; 5304 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5305 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5306 }; 5307 5308 enum rtw89_ser_rcvy_step { 5309 RTW89_SER_DRV_STOP_TX, 5310 RTW89_SER_DRV_STOP_RX, 5311 RTW89_SER_DRV_STOP_RUN, 5312 RTW89_SER_HAL_STOP_DMA, 5313 RTW89_SER_SUPPRESS_LOG, 5314 RTW89_NUM_OF_SER_FLAGS 5315 }; 5316 5317 struct rtw89_ser { 5318 u8 state; 5319 u8 alarm_event; 5320 bool prehandle_l1; 5321 5322 struct work_struct ser_hdl_work; 5323 struct delayed_work ser_alarm_work; 5324 const struct state_ent *st_tbl; 5325 const struct event_ent *ev_tbl; 5326 struct list_head msg_q; 5327 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5328 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5329 }; 5330 5331 enum rtw89_mac_ax_ps_mode { 5332 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5333 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5334 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5335 RTW89_MAC_AX_PS_MODE_MAX = 3, 5336 }; 5337 5338 enum rtw89_last_rpwm_mode { 5339 RTW89_LAST_RPWM_PS = 0x0, 5340 RTW89_LAST_RPWM_ACTIVE = 0x6, 5341 }; 5342 5343 struct rtw89_lps_parm { 5344 u8 macid; 5345 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5346 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5347 }; 5348 5349 struct rtw89_ppdu_sts_info { 5350 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 5351 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 5352 }; 5353 5354 struct rtw89_early_h2c { 5355 struct list_head list; 5356 u8 *h2c; 5357 u16 h2c_len; 5358 }; 5359 5360 struct rtw89_hw_scan_info { 5361 struct rtw89_vif_link *scanning_vif; 5362 struct list_head pkt_list[NUM_NL80211_BANDS]; 5363 struct rtw89_chan op_chan; 5364 bool abort; 5365 u32 last_chan_idx; 5366 }; 5367 5368 enum rtw89_phy_bb_gain_band { 5369 RTW89_BB_GAIN_BAND_2G = 0, 5370 RTW89_BB_GAIN_BAND_5G_L = 1, 5371 RTW89_BB_GAIN_BAND_5G_M = 2, 5372 RTW89_BB_GAIN_BAND_5G_H = 3, 5373 RTW89_BB_GAIN_BAND_6G_L = 4, 5374 RTW89_BB_GAIN_BAND_6G_M = 5, 5375 RTW89_BB_GAIN_BAND_6G_H = 6, 5376 RTW89_BB_GAIN_BAND_6G_UH = 7, 5377 5378 RTW89_BB_GAIN_BAND_NR, 5379 }; 5380 5381 enum rtw89_phy_gain_band_be { 5382 RTW89_BB_GAIN_BAND_2G_BE = 0, 5383 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5384 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5385 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5386 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5387 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5388 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5389 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5390 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5391 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5392 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5393 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5394 5395 RTW89_BB_GAIN_BAND_NR_BE, 5396 }; 5397 5398 enum rtw89_phy_bb_bw_be { 5399 RTW89_BB_BW_20_40 = 0, 5400 RTW89_BB_BW_80_160_320 = 1, 5401 5402 RTW89_BB_BW_NR_BE, 5403 }; 5404 5405 enum rtw89_bw20_sc { 5406 RTW89_BW20_SC_20M = 1, 5407 RTW89_BW20_SC_40M = 2, 5408 RTW89_BW20_SC_80M = 4, 5409 RTW89_BW20_SC_160M = 8, 5410 RTW89_BW20_SC_320M = 16, 5411 }; 5412 5413 enum rtw89_cmac_table_bw { 5414 RTW89_CMAC_BW_20M = 0, 5415 RTW89_CMAC_BW_40M = 1, 5416 RTW89_CMAC_BW_80M = 2, 5417 RTW89_CMAC_BW_160M = 3, 5418 RTW89_CMAC_BW_320M = 4, 5419 5420 RTW89_CMAC_BW_NR, 5421 }; 5422 5423 enum rtw89_phy_bb_rxsc_num { 5424 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5425 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5426 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5427 }; 5428 5429 struct rtw89_phy_bb_gain_info { 5430 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5431 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5432 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5433 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5434 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5435 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5436 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5437 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5438 [RTW89_BB_RXSC_NUM_40]; 5439 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5440 [RTW89_BB_RXSC_NUM_80]; 5441 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5442 [RTW89_BB_RXSC_NUM_160]; 5443 }; 5444 5445 struct rtw89_phy_bb_gain_info_be { 5446 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5447 [LNA_GAIN_NUM]; 5448 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5449 [TIA_GAIN_NUM]; 5450 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5451 [RF_PATH_MAX][LNA_GAIN_NUM]; 5452 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5453 [RF_PATH_MAX][LNA_GAIN_NUM]; 5454 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5455 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5456 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5457 [RTW89_BW20_SC_20M]; 5458 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5459 [RTW89_BW20_SC_40M]; 5460 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5461 [RTW89_BW20_SC_80M]; 5462 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5463 [RTW89_BW20_SC_160M]; 5464 }; 5465 5466 struct rtw89_phy_efuse_gain { 5467 bool offset_valid; 5468 bool comp_valid; 5469 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5470 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5471 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5472 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5473 }; 5474 5475 #define RTW89_MAX_PATTERN_NUM 18 5476 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5477 #define RTW89_MAX_PATTERN_SIZE 128 5478 5479 struct rtw89_wow_cam_info { 5480 bool r_w; 5481 u8 idx; 5482 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5483 u16 crc; 5484 bool negative_pattern_match; 5485 bool skip_mac_hdr; 5486 bool uc; 5487 bool mc; 5488 bool bc; 5489 bool valid; 5490 }; 5491 5492 struct rtw89_wow_key_info { 5493 u8 ptk_tx_iv[8]; 5494 u8 valid_check; 5495 u8 symbol_check_en; 5496 u8 gtk_keyidx; 5497 u8 rsvd[5]; 5498 u8 ptk_rx_iv[8]; 5499 u8 gtk_rx_iv[4][8]; 5500 } __packed; 5501 5502 struct rtw89_wow_gtk_info { 5503 u8 kck[32]; 5504 u8 kek[32]; 5505 u8 tk1[16]; 5506 u8 txmickey[8]; 5507 u8 rxmickey[8]; 5508 __le32 igtk_keyid; 5509 __le64 ipn; 5510 u8 igtk[2][32]; 5511 u8 psk[32]; 5512 } __packed; 5513 5514 struct rtw89_wow_aoac_report { 5515 u8 rpt_ver; 5516 u8 sec_type; 5517 u8 key_idx; 5518 u8 pattern_idx; 5519 u8 rekey_ok; 5520 u8 ptk_tx_iv[8]; 5521 u8 eapol_key_replay_count[8]; 5522 u8 gtk[32]; 5523 u8 ptk_rx_iv[8]; 5524 u8 gtk_rx_iv[4][8]; 5525 u64 igtk_key_id; 5526 u64 igtk_ipn; 5527 u8 igtk[32]; 5528 u8 csa_pri_ch; 5529 u8 csa_bw; 5530 u8 csa_ch_offset; 5531 u8 csa_chsw_failed; 5532 u8 csa_ch_band; 5533 }; 5534 5535 struct rtw89_wow_param { 5536 struct rtw89_vif_link *rtwvif_link; 5537 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5538 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5539 struct rtw89_wow_key_info key_info; 5540 struct rtw89_wow_gtk_info gtk_info; 5541 struct rtw89_wow_aoac_report aoac_rpt; 5542 u8 pattern_cnt; 5543 u8 ptk_alg; 5544 u8 gtk_alg; 5545 u8 ptk_keyidx; 5546 u8 akm; 5547 5548 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5549 struct rtw89_wait_info wait; 5550 5551 bool pno_inited; 5552 struct list_head pno_pkt_list; 5553 struct cfg80211_sched_scan_request *nd_config; 5554 }; 5555 5556 struct rtw89_mcc_limit { 5557 bool enable; 5558 u16 max_tob; /* TU; max time offset behind */ 5559 u16 max_toa; /* TU; max time offset ahead */ 5560 u16 max_dur; /* TU */ 5561 }; 5562 5563 struct rtw89_mcc_policy { 5564 u8 c2h_rpt; 5565 u8 tx_null_early; 5566 u8 dis_tx_null; 5567 u8 in_curr_ch; 5568 u8 dis_sw_retry; 5569 u8 sw_retry_count; 5570 }; 5571 5572 struct rtw89_mcc_role { 5573 struct rtw89_vif_link *rtwvif_link; 5574 struct rtw89_mcc_policy policy; 5575 struct rtw89_mcc_limit limit; 5576 5577 /* only valid when running with FW MRC mechanism */ 5578 u8 slot_idx; 5579 5580 /* byte-array in LE order for FW */ 5581 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5582 5583 u16 duration; /* TU */ 5584 u16 beacon_interval; /* TU */ 5585 bool is_2ghz; 5586 bool is_go; 5587 bool is_gc; 5588 }; 5589 5590 struct rtw89_mcc_bt_role { 5591 u16 duration; /* TU */ 5592 }; 5593 5594 struct rtw89_mcc_courtesy { 5595 bool enable; 5596 u8 slot_num; 5597 u8 macid_src; 5598 u8 macid_tgt; 5599 }; 5600 5601 enum rtw89_mcc_plan { 5602 RTW89_MCC_PLAN_TAIL_BT, 5603 RTW89_MCC_PLAN_MID_BT, 5604 RTW89_MCC_PLAN_NO_BT, 5605 5606 NUM_OF_RTW89_MCC_PLAN, 5607 }; 5608 5609 struct rtw89_mcc_pattern { 5610 s16 tob_ref; /* TU; time offset behind of reference role */ 5611 s16 toa_ref; /* TU; time offset ahead of reference role */ 5612 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5613 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5614 5615 enum rtw89_mcc_plan plan; 5616 struct rtw89_mcc_courtesy courtesy; 5617 }; 5618 5619 struct rtw89_mcc_sync { 5620 bool enable; 5621 u16 offset; /* TU */ 5622 u8 macid_src; 5623 u8 band_src; 5624 u8 port_src; 5625 u8 macid_tgt; 5626 u8 band_tgt; 5627 u8 port_tgt; 5628 }; 5629 5630 struct rtw89_mcc_config { 5631 struct rtw89_mcc_pattern pattern; 5632 struct rtw89_mcc_sync sync; 5633 u64 start_tsf; 5634 u16 mcc_interval; /* TU */ 5635 u16 beacon_offset; /* TU */ 5636 }; 5637 5638 enum rtw89_mcc_mode { 5639 RTW89_MCC_MODE_GO_STA, 5640 RTW89_MCC_MODE_GC_STA, 5641 }; 5642 5643 struct rtw89_mcc_info { 5644 struct rtw89_wait_info wait; 5645 5646 u8 group; 5647 enum rtw89_mcc_mode mode; 5648 struct rtw89_mcc_role role_ref; /* reference role */ 5649 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5650 struct rtw89_mcc_bt_role bt_role; 5651 struct rtw89_mcc_config config; 5652 }; 5653 5654 struct rtw89_dev { 5655 struct ieee80211_hw *hw; 5656 struct device *dev; 5657 const struct ieee80211_ops *ops; 5658 5659 bool dbcc_en; 5660 bool support_mlo; 5661 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5662 struct rtw89_hw_scan_info scan_info; 5663 const struct rtw89_chip_info *chip; 5664 const struct rtw89_chip_variant *variant; 5665 const struct rtw89_pci_info *pci_info; 5666 const struct rtw89_rfe_parms *rfe_parms; 5667 struct rtw89_hal hal; 5668 struct rtw89_mcc_info mcc; 5669 struct rtw89_mac_info mac; 5670 struct rtw89_fw_info fw; 5671 struct rtw89_hci_info hci; 5672 struct rtw89_efuse efuse; 5673 struct rtw89_traffic_stats stats; 5674 struct rtw89_rfe_data *rfe_data; 5675 enum rtw89_custid custid; 5676 5677 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 5678 refcount_t refcount_ap_info; 5679 5680 struct list_head rtwvifs_list; 5681 /* used to protect rf read write */ 5682 struct mutex rf_mutex; 5683 struct workqueue_struct *txq_wq; 5684 struct work_struct txq_work; 5685 struct delayed_work txq_reinvoke_work; 5686 /* used to protect ba_list and forbid_ba_list */ 5687 spinlock_t ba_lock; 5688 /* txqs to setup ba session */ 5689 struct list_head ba_list; 5690 /* txqs to forbid ba session */ 5691 struct list_head forbid_ba_list; 5692 struct work_struct ba_work; 5693 /* used to protect rpwm */ 5694 spinlock_t rpwm_lock; 5695 5696 struct rtw89_cam_info cam_info; 5697 5698 struct sk_buff_head c2h_queue; 5699 struct wiphy_work c2h_work; 5700 struct wiphy_work ips_work; 5701 struct wiphy_work cancel_6ghz_probe_work; 5702 struct work_struct load_firmware_work; 5703 5704 struct list_head early_h2c_list; 5705 5706 struct rtw89_ser ser; 5707 5708 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5709 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5710 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5711 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5712 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5713 5714 struct rtw89_phy_stat phystat; 5715 struct rtw89_rfk_wait_info rfk_wait; 5716 struct rtw89_dack_info dack; 5717 struct rtw89_iqk_info iqk; 5718 struct rtw89_dpk_info dpk; 5719 struct rtw89_rfk_mcc_info rfk_mcc; 5720 struct rtw89_lck_info lck; 5721 struct rtw89_rx_dck_info rx_dck; 5722 bool is_tssi_mode[RF_PATH_MAX]; 5723 bool is_bt_iqk_timeout; 5724 5725 struct rtw89_fem_info fem; 5726 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5727 struct rtw89_tssi_info tssi; 5728 struct rtw89_power_trim_info pwr_trim; 5729 5730 struct rtw89_cfo_tracking_info cfo_tracking; 5731 union { 5732 struct rtw89_phy_bb_gain_info ax; 5733 struct rtw89_phy_bb_gain_info_be be; 5734 } bb_gain; 5735 struct rtw89_phy_efuse_gain efuse_gain; 5736 struct rtw89_phy_ul_tb_info ul_tb_info; 5737 struct rtw89_antdiv_info antdiv; 5738 5739 struct rtw89_bb_ctx { 5740 enum rtw89_phy_idx phy_idx; 5741 struct rtw89_env_monitor_info env_monitor; 5742 struct rtw89_dig_info dig; 5743 struct rtw89_phy_ch_info ch_info; 5744 struct rtw89_edcca_bak edcca_bak; 5745 } bbs[RTW89_PHY_NUM]; 5746 5747 struct wiphy_delayed_work track_work; 5748 struct wiphy_delayed_work chanctx_work; 5749 struct wiphy_delayed_work coex_act1_work; 5750 struct wiphy_delayed_work coex_bt_devinfo_work; 5751 struct wiphy_delayed_work coex_rfk_chk_work; 5752 struct wiphy_delayed_work cfo_track_work; 5753 struct delayed_work forbid_ba_work; 5754 struct wiphy_delayed_work antdiv_work; 5755 struct rtw89_ppdu_sts_info ppdu_sts; 5756 u8 total_sta_assoc; 5757 bool scanning; 5758 5759 struct rtw89_regulatory_info regulatory; 5760 struct rtw89_sar_info sar; 5761 struct rtw89_tas_info tas; 5762 struct rtw89_ant_gain_info ant_gain; 5763 5764 struct rtw89_btc btc; 5765 enum rtw89_ps_mode ps_mode; 5766 bool lps_enabled; 5767 5768 struct rtw89_wow_param wow; 5769 5770 /* napi structure */ 5771 struct net_device *netdev; 5772 struct napi_struct napi; 5773 int napi_budget_countdown; 5774 5775 struct rtw89_debugfs *debugfs; 5776 5777 /* HCI related data, keep last */ 5778 u8 priv[] __aligned(sizeof(void *)); 5779 }; 5780 5781 struct rtw89_link_conf_container { 5782 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 5783 }; 5784 5785 #define RTW89_VIF_IDLE_LINK_ID 0 5786 5787 struct rtw89_vif { 5788 struct rtw89_dev *rtwdev; 5789 struct list_head list; 5790 struct list_head mgnt_entry; 5791 struct rtw89_link_conf_container __rcu *snap_link_confs; 5792 5793 u8 mac_addr[ETH_ALEN]; 5794 __be32 ip_addr; 5795 5796 struct rtw89_traffic_stats stats; 5797 u32 tdls_peer; 5798 5799 struct ieee80211_scan_ies *scan_ies; 5800 struct cfg80211_scan_request *scan_req; 5801 5802 struct rtw89_roc roc; 5803 bool offchan; 5804 5805 u8 links_inst_valid_num; 5806 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5807 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5808 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 5809 }; 5810 5811 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 5812 const struct rtw89_vif *rtwvif, 5813 unsigned int link_id) 5814 { 5815 *rtwvif_link = rtwvif->links[link_id]; 5816 return !!*rtwvif_link; 5817 } 5818 5819 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 5820 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5821 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 5822 5823 enum rtw89_sta_flags { 5824 RTW89_REMOTE_STA_IN_PS, 5825 5826 NUM_OF_RTW89_STA_FLAGS, 5827 }; 5828 5829 struct rtw89_sta { 5830 struct rtw89_dev *rtwdev; 5831 struct rtw89_vif *rtwvif; 5832 5833 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 5834 5835 bool disassoc; 5836 5837 struct sk_buff_head roc_queue; 5838 5839 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 5840 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 5841 5842 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 5843 5844 u8 links_inst_valid_num; 5845 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5846 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5847 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 5848 }; 5849 5850 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 5851 const struct rtw89_sta *rtwsta, 5852 unsigned int link_id) 5853 { 5854 *rtwsta_link = rtwsta->links[link_id]; 5855 return !!*rtwsta_link; 5856 } 5857 5858 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 5859 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5860 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 5861 5862 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 5863 { 5864 /* const after init, so no need to check if active first */ 5865 return rtwvif->links_inst[0].mac_id; 5866 } 5867 5868 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 5869 { 5870 /* const after init, so no need to check if active first */ 5871 return rtwvif->links_inst[0].port; 5872 } 5873 5874 static inline struct rtw89_vif_link * 5875 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 5876 { 5877 if (index >= rtwvif->links_inst_valid_num || 5878 !test_bit(index, rtwvif->links_inst_map)) 5879 return NULL; 5880 return &rtwvif->links_inst[index]; 5881 } 5882 5883 static inline 5884 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 5885 { 5886 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5887 5888 return rtwvif_link - rtwvif->links_inst; 5889 } 5890 5891 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 5892 { 5893 /* const after init, so no need to check if active first */ 5894 return rtwsta->links_inst[0].mac_id; 5895 } 5896 5897 static inline struct rtw89_sta_link * 5898 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 5899 { 5900 if (index >= rtwsta->links_inst_valid_num || 5901 !test_bit(index, rtwsta->links_inst_map)) 5902 return NULL; 5903 return &rtwsta->links_inst[index]; 5904 } 5905 5906 static inline 5907 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 5908 { 5909 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5910 5911 return rtwsta_link - rtwsta->links_inst; 5912 } 5913 5914 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 5915 { 5916 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5917 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5918 5919 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5920 rtwsta_link); 5921 } 5922 5923 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 5924 { 5925 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5926 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5927 5928 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5929 NULL); 5930 synchronize_rcu(); 5931 } 5932 5933 static inline struct rtw89_sta_link * 5934 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 5935 { 5936 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 5937 } 5938 5939 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5940 struct rtw89_core_tx_request *tx_req) 5941 { 5942 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5943 } 5944 5945 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5946 { 5947 rtwdev->hci.ops->reset(rtwdev); 5948 } 5949 5950 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5951 { 5952 return rtwdev->hci.ops->start(rtwdev); 5953 } 5954 5955 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5956 { 5957 rtwdev->hci.ops->stop(rtwdev); 5958 } 5959 5960 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5961 { 5962 return rtwdev->hci.ops->deinit(rtwdev); 5963 } 5964 5965 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5966 { 5967 rtwdev->hci.ops->pause(rtwdev, pause); 5968 } 5969 5970 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5971 { 5972 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5973 } 5974 5975 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5976 { 5977 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5978 } 5979 5980 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5981 { 5982 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5983 } 5984 5985 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5986 { 5987 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5988 } 5989 5990 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5991 { 5992 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5993 } 5994 5995 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5996 bool drop) 5997 { 5998 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5999 return; 6000 6001 if (rtwdev->hci.ops->flush_queues) 6002 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 6003 } 6004 6005 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 6006 { 6007 if (rtwdev->hci.ops->recovery_start) 6008 rtwdev->hci.ops->recovery_start(rtwdev); 6009 } 6010 6011 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 6012 { 6013 if (rtwdev->hci.ops->recovery_complete) 6014 rtwdev->hci.ops->recovery_complete(rtwdev); 6015 } 6016 6017 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 6018 { 6019 if (rtwdev->hci.ops->enable_intr) 6020 rtwdev->hci.ops->enable_intr(rtwdev); 6021 } 6022 6023 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 6024 { 6025 if (rtwdev->hci.ops->disable_intr) 6026 rtwdev->hci.ops->disable_intr(rtwdev); 6027 } 6028 6029 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 6030 { 6031 if (rtwdev->hci.ops->ctrl_txdma_ch) 6032 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 6033 } 6034 6035 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6036 { 6037 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6038 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6039 } 6040 6041 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6042 { 6043 if (rtwdev->hci.ops->ctrl_trxhci) 6044 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6045 } 6046 6047 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6048 { 6049 int ret = 0; 6050 6051 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6052 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6053 return ret; 6054 } 6055 6056 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6057 { 6058 if (rtwdev->hci.ops->clr_idx_all) 6059 rtwdev->hci.ops->clr_idx_all(rtwdev); 6060 } 6061 6062 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6063 { 6064 int ret = 0; 6065 6066 if (rtwdev->hci.ops->rst_bdram) 6067 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6068 return ret; 6069 } 6070 6071 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6072 { 6073 if (rtwdev->hci.ops->clear) 6074 rtwdev->hci.ops->clear(rtwdev, pdev); 6075 } 6076 6077 static inline 6078 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6079 { 6080 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6081 6082 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 6083 } 6084 6085 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6086 { 6087 return rtwdev->hci.ops->read8(rtwdev, addr); 6088 } 6089 6090 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6091 { 6092 return rtwdev->hci.ops->read16(rtwdev, addr); 6093 } 6094 6095 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6096 { 6097 return rtwdev->hci.ops->read32(rtwdev, addr); 6098 } 6099 6100 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6101 { 6102 rtwdev->hci.ops->write8(rtwdev, addr, data); 6103 } 6104 6105 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6106 { 6107 rtwdev->hci.ops->write16(rtwdev, addr, data); 6108 } 6109 6110 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6111 { 6112 rtwdev->hci.ops->write32(rtwdev, addr, data); 6113 } 6114 6115 static inline void 6116 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6117 { 6118 u8 val; 6119 6120 val = rtw89_read8(rtwdev, addr); 6121 rtw89_write8(rtwdev, addr, val | bit); 6122 } 6123 6124 static inline void 6125 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6126 { 6127 u16 val; 6128 6129 val = rtw89_read16(rtwdev, addr); 6130 rtw89_write16(rtwdev, addr, val | bit); 6131 } 6132 6133 static inline void 6134 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6135 { 6136 u32 val; 6137 6138 val = rtw89_read32(rtwdev, addr); 6139 rtw89_write32(rtwdev, addr, val | bit); 6140 } 6141 6142 static inline void 6143 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6144 { 6145 u8 val; 6146 6147 val = rtw89_read8(rtwdev, addr); 6148 rtw89_write8(rtwdev, addr, val & ~bit); 6149 } 6150 6151 static inline void 6152 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6153 { 6154 u16 val; 6155 6156 val = rtw89_read16(rtwdev, addr); 6157 rtw89_write16(rtwdev, addr, val & ~bit); 6158 } 6159 6160 static inline void 6161 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6162 { 6163 u32 val; 6164 6165 val = rtw89_read32(rtwdev, addr); 6166 rtw89_write32(rtwdev, addr, val & ~bit); 6167 } 6168 6169 static inline u32 6170 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6171 { 6172 u32 shift = __ffs(mask); 6173 u32 orig; 6174 u32 ret; 6175 6176 orig = rtw89_read32(rtwdev, addr); 6177 ret = (orig & mask) >> shift; 6178 6179 return ret; 6180 } 6181 6182 static inline u16 6183 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6184 { 6185 u32 shift = __ffs(mask); 6186 u32 orig; 6187 u32 ret; 6188 6189 orig = rtw89_read16(rtwdev, addr); 6190 ret = (orig & mask) >> shift; 6191 6192 return ret; 6193 } 6194 6195 static inline u8 6196 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6197 { 6198 u32 shift = __ffs(mask); 6199 u32 orig; 6200 u32 ret; 6201 6202 orig = rtw89_read8(rtwdev, addr); 6203 ret = (orig & mask) >> shift; 6204 6205 return ret; 6206 } 6207 6208 static inline void 6209 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6210 { 6211 u32 shift = __ffs(mask); 6212 u32 orig; 6213 u32 set; 6214 6215 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6216 6217 orig = rtw89_read32(rtwdev, addr); 6218 set = (orig & ~mask) | ((data << shift) & mask); 6219 rtw89_write32(rtwdev, addr, set); 6220 } 6221 6222 static inline void 6223 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6224 { 6225 u32 shift; 6226 u16 orig, set; 6227 6228 mask &= 0xffff; 6229 shift = __ffs(mask); 6230 6231 orig = rtw89_read16(rtwdev, addr); 6232 set = (orig & ~mask) | ((data << shift) & mask); 6233 rtw89_write16(rtwdev, addr, set); 6234 } 6235 6236 static inline void 6237 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6238 { 6239 u32 shift; 6240 u8 orig, set; 6241 6242 mask &= 0xff; 6243 shift = __ffs(mask); 6244 6245 orig = rtw89_read8(rtwdev, addr); 6246 set = (orig & ~mask) | ((data << shift) & mask); 6247 rtw89_write8(rtwdev, addr, set); 6248 } 6249 6250 static inline u32 6251 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6252 u32 addr, u32 mask) 6253 { 6254 u32 val; 6255 6256 mutex_lock(&rtwdev->rf_mutex); 6257 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6258 mutex_unlock(&rtwdev->rf_mutex); 6259 6260 return val; 6261 } 6262 6263 static inline void 6264 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6265 u32 addr, u32 mask, u32 data) 6266 { 6267 mutex_lock(&rtwdev->rf_mutex); 6268 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6269 mutex_unlock(&rtwdev->rf_mutex); 6270 } 6271 6272 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6273 { 6274 void *p = rtwtxq; 6275 6276 return container_of(p, struct ieee80211_txq, drv_priv); 6277 } 6278 6279 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6280 struct ieee80211_txq *txq) 6281 { 6282 struct rtw89_txq *rtwtxq; 6283 6284 if (!txq) 6285 return; 6286 6287 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6288 INIT_LIST_HEAD(&rtwtxq->list); 6289 } 6290 6291 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6292 { 6293 void *p = rtwvif; 6294 6295 return container_of(p, struct ieee80211_vif, drv_priv); 6296 } 6297 6298 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6299 { 6300 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6301 } 6302 6303 static inline 6304 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6305 { 6306 return rtwvif_to_vif(rtwvif_link->rtwvif); 6307 } 6308 6309 static inline 6310 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6311 { 6312 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6313 } 6314 6315 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6316 { 6317 return (struct rtw89_vif *)vif->drv_priv; 6318 } 6319 6320 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6321 { 6322 return vif ? vif_to_rtwvif(vif) : NULL; 6323 } 6324 6325 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6326 { 6327 void *p = rtwsta; 6328 6329 return container_of(p, struct ieee80211_sta, drv_priv); 6330 } 6331 6332 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6333 { 6334 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6335 } 6336 6337 static inline 6338 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6339 { 6340 return rtwsta_to_sta(rtwsta_link->rtwsta); 6341 } 6342 6343 static inline 6344 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6345 { 6346 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6347 } 6348 6349 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6350 { 6351 return (struct rtw89_sta *)sta->drv_priv; 6352 } 6353 6354 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6355 { 6356 return sta ? sta_to_rtwsta(sta) : NULL; 6357 } 6358 6359 static inline struct ieee80211_bss_conf * 6360 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6361 { 6362 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6363 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6364 struct rtw89_link_conf_container *snap; 6365 struct ieee80211_bss_conf *bss_conf; 6366 6367 snap = rcu_dereference(rtwvif->snap_link_confs); 6368 if (snap) { 6369 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6370 goto out; 6371 } 6372 6373 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6374 6375 out: 6376 if (unlikely(!bss_conf)) { 6377 *nolink = true; 6378 return &vif->bss_conf; 6379 } 6380 6381 *nolink = false; 6382 return bss_conf; 6383 } 6384 6385 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6386 ({ \ 6387 typeof(rtwvif_link) p = rtwvif_link; \ 6388 struct ieee80211_bss_conf *bss_conf; \ 6389 bool nolink; \ 6390 \ 6391 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6392 if (unlikely(nolink) && (assert)) \ 6393 rtw89_err(p->rtwvif->rtwdev, \ 6394 "%s: cannot find exact bss_conf for link_id %u\n",\ 6395 __func__, p->link_id); \ 6396 bss_conf; \ 6397 }) 6398 6399 static inline struct ieee80211_link_sta * 6400 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6401 { 6402 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6403 struct ieee80211_link_sta *link_sta; 6404 6405 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6406 if (unlikely(!link_sta)) { 6407 *nolink = true; 6408 return &sta->deflink; 6409 } 6410 6411 *nolink = false; 6412 return link_sta; 6413 } 6414 6415 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6416 ({ \ 6417 typeof(rtwsta_link) p = rtwsta_link; \ 6418 struct ieee80211_link_sta *link_sta; \ 6419 bool nolink; \ 6420 \ 6421 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6422 if (unlikely(nolink) && (assert)) \ 6423 rtw89_err(p->rtwsta->rtwdev, \ 6424 "%s: cannot find exact link_sta for link_id %u\n",\ 6425 __func__, p->link_id); \ 6426 link_sta; \ 6427 }) 6428 6429 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6430 { 6431 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6432 return RATE_INFO_BW_160; 6433 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6434 return RATE_INFO_BW_80; 6435 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6436 return RATE_INFO_BW_40; 6437 else 6438 return RATE_INFO_BW_20; 6439 } 6440 6441 static inline 6442 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6443 { 6444 switch (hw_band) { 6445 default: 6446 case RTW89_BAND_2G: 6447 return NL80211_BAND_2GHZ; 6448 case RTW89_BAND_5G: 6449 return NL80211_BAND_5GHZ; 6450 case RTW89_BAND_6G: 6451 return NL80211_BAND_6GHZ; 6452 } 6453 } 6454 6455 static inline 6456 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6457 { 6458 switch (nl_band) { 6459 default: 6460 case NL80211_BAND_2GHZ: 6461 return RTW89_BAND_2G; 6462 case NL80211_BAND_5GHZ: 6463 return RTW89_BAND_5G; 6464 case NL80211_BAND_6GHZ: 6465 return RTW89_BAND_6G; 6466 } 6467 } 6468 6469 static inline 6470 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6471 { 6472 switch (width) { 6473 default: 6474 WARN(1, "Not support bandwidth %d\n", width); 6475 fallthrough; 6476 case NL80211_CHAN_WIDTH_20_NOHT: 6477 case NL80211_CHAN_WIDTH_20: 6478 return RTW89_CHANNEL_WIDTH_20; 6479 case NL80211_CHAN_WIDTH_40: 6480 return RTW89_CHANNEL_WIDTH_40; 6481 case NL80211_CHAN_WIDTH_80: 6482 return RTW89_CHANNEL_WIDTH_80; 6483 case NL80211_CHAN_WIDTH_160: 6484 return RTW89_CHANNEL_WIDTH_160; 6485 } 6486 } 6487 6488 static inline 6489 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6490 { 6491 switch (rua) { 6492 default: 6493 WARN(1, "Invalid RU allocation: %d\n", rua); 6494 fallthrough; 6495 case 0 ... 36: 6496 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6497 case 37 ... 52: 6498 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6499 case 53 ... 60: 6500 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6501 case 61 ... 64: 6502 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6503 case 65 ... 66: 6504 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6505 case 67: 6506 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6507 case 68: 6508 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6509 } 6510 } 6511 6512 static inline 6513 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6514 struct rtw89_sta_link *rtwsta_link) 6515 { 6516 if (rtwsta_link) { 6517 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6518 6519 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6520 return &rtwsta_link->addr_cam; 6521 } 6522 return &rtwvif_link->addr_cam; 6523 } 6524 6525 static inline 6526 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6527 struct rtw89_sta_link *rtwsta_link) 6528 { 6529 if (rtwsta_link) { 6530 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6531 6532 if (sta->tdls) 6533 return &rtwsta_link->bssid_cam; 6534 } 6535 return &rtwvif_link->bssid_cam; 6536 } 6537 6538 static inline 6539 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6540 struct rtw89_channel_help_params *p, 6541 const struct rtw89_chan *chan, 6542 enum rtw89_mac_idx mac_idx, 6543 enum rtw89_phy_idx phy_idx) 6544 { 6545 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6546 mac_idx, phy_idx); 6547 } 6548 6549 static inline 6550 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6551 struct rtw89_channel_help_params *p, 6552 const struct rtw89_chan *chan, 6553 enum rtw89_mac_idx mac_idx, 6554 enum rtw89_phy_idx phy_idx) 6555 { 6556 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6557 mac_idx, phy_idx); 6558 } 6559 6560 static inline 6561 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6562 enum rtw89_chanctx_idx idx) 6563 { 6564 struct rtw89_hal *hal = &rtwdev->hal; 6565 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6566 6567 if (roc_idx == idx) 6568 return &hal->roc_chandef; 6569 6570 return &hal->chanctx[idx].chandef; 6571 } 6572 6573 static inline 6574 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6575 enum rtw89_chanctx_idx idx) 6576 { 6577 struct rtw89_hal *hal = &rtwdev->hal; 6578 6579 return &hal->chanctx[idx].chan; 6580 } 6581 6582 static inline 6583 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6584 enum rtw89_chanctx_idx idx) 6585 { 6586 struct rtw89_hal *hal = &rtwdev->hal; 6587 6588 return &hal->chanctx[idx].rcd; 6589 } 6590 6591 static inline 6592 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6593 { 6594 const struct rtw89_chanctx *chanctx = 6595 container_of_const(chan, struct rtw89_chanctx, chan); 6596 6597 return &chanctx->rcd; 6598 } 6599 6600 static inline 6601 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6602 { 6603 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6604 6605 if (rtwvif_link) 6606 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6607 else 6608 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6609 } 6610 6611 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6612 { 6613 const struct rtw89_chip_info *chip = rtwdev->chip; 6614 6615 if (chip->ops->fem_setup) 6616 chip->ops->fem_setup(rtwdev); 6617 } 6618 6619 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6620 { 6621 const struct rtw89_chip_info *chip = rtwdev->chip; 6622 6623 if (chip->ops->rfe_gpio) 6624 chip->ops->rfe_gpio(rtwdev); 6625 } 6626 6627 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6628 { 6629 const struct rtw89_chip_info *chip = rtwdev->chip; 6630 6631 if (chip->ops->rfk_hw_init) 6632 chip->ops->rfk_hw_init(rtwdev); 6633 } 6634 6635 static inline 6636 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6637 { 6638 const struct rtw89_chip_info *chip = rtwdev->chip; 6639 6640 if (chip->ops->bb_preinit) 6641 chip->ops->bb_preinit(rtwdev, phy_idx); 6642 } 6643 6644 static inline 6645 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6646 { 6647 const struct rtw89_chip_info *chip = rtwdev->chip; 6648 6649 if (!chip->ops->bb_postinit) 6650 return; 6651 6652 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6653 6654 if (rtwdev->dbcc_en) 6655 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6656 } 6657 6658 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6659 { 6660 const struct rtw89_chip_info *chip = rtwdev->chip; 6661 6662 if (chip->ops->bb_sethw) 6663 chip->ops->bb_sethw(rtwdev); 6664 } 6665 6666 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6667 { 6668 const struct rtw89_chip_info *chip = rtwdev->chip; 6669 6670 if (chip->ops->rfk_init) 6671 chip->ops->rfk_init(rtwdev); 6672 } 6673 6674 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6675 { 6676 const struct rtw89_chip_info *chip = rtwdev->chip; 6677 6678 if (chip->ops->rfk_init_late) 6679 chip->ops->rfk_init_late(rtwdev); 6680 } 6681 6682 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6683 struct rtw89_vif_link *rtwvif_link) 6684 { 6685 const struct rtw89_chip_info *chip = rtwdev->chip; 6686 6687 if (chip->ops->rfk_channel) 6688 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6689 } 6690 6691 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6692 enum rtw89_phy_idx phy_idx, 6693 const struct rtw89_chan *chan) 6694 { 6695 const struct rtw89_chip_info *chip = rtwdev->chip; 6696 6697 if (chip->ops->rfk_band_changed) 6698 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6699 } 6700 6701 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6702 struct rtw89_vif_link *rtwvif_link, bool start) 6703 { 6704 const struct rtw89_chip_info *chip = rtwdev->chip; 6705 6706 if (chip->ops->rfk_scan) 6707 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6708 } 6709 6710 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6711 { 6712 const struct rtw89_chip_info *chip = rtwdev->chip; 6713 6714 if (chip->ops->rfk_track) 6715 chip->ops->rfk_track(rtwdev); 6716 } 6717 6718 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6719 { 6720 const struct rtw89_chip_info *chip = rtwdev->chip; 6721 6722 if (!chip->ops->set_txpwr_ctrl) 6723 return; 6724 6725 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6726 if (rtwdev->dbcc_en) 6727 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6728 } 6729 6730 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6731 { 6732 const struct rtw89_chip_info *chip = rtwdev->chip; 6733 6734 if (chip->ops->power_trim) 6735 chip->ops->power_trim(rtwdev); 6736 } 6737 6738 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6739 enum rtw89_phy_idx phy_idx) 6740 { 6741 const struct rtw89_chip_info *chip = rtwdev->chip; 6742 6743 if (chip->ops->init_txpwr_unit) 6744 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6745 } 6746 6747 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6748 { 6749 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6750 if (rtwdev->dbcc_en) 6751 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6752 } 6753 6754 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6755 enum rtw89_rf_path rf_path) 6756 { 6757 const struct rtw89_chip_info *chip = rtwdev->chip; 6758 6759 if (!chip->ops->get_thermal) 6760 return 0x10; 6761 6762 return chip->ops->get_thermal(rtwdev, rf_path); 6763 } 6764 6765 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6766 struct rtw89_rx_phy_ppdu *phy_ppdu, 6767 struct ieee80211_rx_status *status) 6768 { 6769 const struct rtw89_chip_info *chip = rtwdev->chip; 6770 6771 if (chip->ops->query_ppdu) 6772 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6773 } 6774 6775 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 6776 struct rtw89_rx_phy_ppdu *phy_ppdu) 6777 { 6778 const struct rtw89_chip_info *chip = rtwdev->chip; 6779 6780 if (chip->ops->convert_rpl_to_rssi) 6781 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 6782 } 6783 6784 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 6785 struct rtw89_rx_desc_info *desc_info, 6786 struct ieee80211_rx_status *rx_status) 6787 { 6788 const struct rtw89_chip_info *chip = rtwdev->chip; 6789 6790 if (chip->ops->phy_rpt_to_rssi) 6791 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 6792 } 6793 6794 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6795 enum rtw89_phy_idx phy_idx) 6796 { 6797 const struct rtw89_chip_info *chip = rtwdev->chip; 6798 6799 if (chip->ops->ctrl_nbtg_bt_tx) 6800 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6801 } 6802 6803 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6804 { 6805 const struct rtw89_chip_info *chip = rtwdev->chip; 6806 6807 if (chip->ops->cfg_txrx_path) 6808 chip->ops->cfg_txrx_path(rtwdev); 6809 } 6810 6811 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 6812 enum rtw89_phy_idx phy_idx) 6813 { 6814 const struct rtw89_chip_info *chip = rtwdev->chip; 6815 6816 if (chip->ops->digital_pwr_comp) 6817 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 6818 } 6819 6820 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6821 const struct rtw89_txpwr_table *tbl) 6822 { 6823 tbl->load(rtwdev, tbl); 6824 } 6825 6826 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6827 { 6828 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6829 6830 return regd->txpwr_regd[band]; 6831 } 6832 6833 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6834 enum rtw89_phy_idx phy_idx) 6835 { 6836 const struct rtw89_chip_info *chip = rtwdev->chip; 6837 6838 if (chip->ops->ctrl_btg_bt_rx) 6839 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6840 } 6841 6842 static inline 6843 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6844 struct rtw89_rx_desc_info *desc_info, 6845 u8 *data, u32 data_offset) 6846 { 6847 const struct rtw89_chip_info *chip = rtwdev->chip; 6848 6849 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6850 } 6851 6852 static inline 6853 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6854 struct rtw89_tx_desc_info *desc_info, 6855 void *txdesc) 6856 { 6857 const struct rtw89_chip_info *chip = rtwdev->chip; 6858 6859 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6860 } 6861 6862 static inline 6863 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6864 struct rtw89_tx_desc_info *desc_info, 6865 void *txdesc) 6866 { 6867 const struct rtw89_chip_info *chip = rtwdev->chip; 6868 6869 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6870 } 6871 6872 static inline 6873 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6874 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6875 { 6876 const struct rtw89_chip_info *chip = rtwdev->chip; 6877 6878 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6879 } 6880 6881 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6882 { 6883 const struct rtw89_chip_info *chip = rtwdev->chip; 6884 6885 chip->ops->cfg_ctrl_path(rtwdev, wl); 6886 } 6887 6888 static inline 6889 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6890 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6891 { 6892 const struct rtw89_chip_info *chip = rtwdev->chip; 6893 6894 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6895 } 6896 6897 static inline 6898 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6899 { 6900 const struct rtw89_chip_info *chip = rtwdev->chip; 6901 6902 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6903 } 6904 6905 static inline 6906 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6907 struct rtw89_vif_link *rtwvif_link, 6908 struct rtw89_sta_link *rtwsta_link) 6909 { 6910 const struct rtw89_chip_info *chip = rtwdev->chip; 6911 6912 if (!chip->ops->h2c_dctl_sec_cam) 6913 return 0; 6914 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 6915 } 6916 6917 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6918 { 6919 __le16 fc = hdr->frame_control; 6920 6921 if (ieee80211_has_tods(fc)) 6922 return hdr->addr1; 6923 else if (ieee80211_has_fromds(fc)) 6924 return hdr->addr2; 6925 else 6926 return hdr->addr3; 6927 } 6928 6929 static inline 6930 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 6931 { 6932 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6933 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6934 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 6935 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6936 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 6937 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6938 return true; 6939 return false; 6940 } 6941 6942 static inline 6943 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 6944 { 6945 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 6946 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 6947 return true; 6948 6949 return false; 6950 } 6951 6952 static inline 6953 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 6954 { 6955 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 6956 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 6957 return true; 6958 6959 return false; 6960 } 6961 6962 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6963 enum rtw89_fw_type type) 6964 { 6965 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6966 6967 switch (type) { 6968 case RTW89_FW_WOWLAN: 6969 return &fw_info->wowlan; 6970 case RTW89_FW_LOGFMT: 6971 return &fw_info->log.suit; 6972 case RTW89_FW_BBMCU0: 6973 return &fw_info->bbmcu0; 6974 case RTW89_FW_BBMCU1: 6975 return &fw_info->bbmcu1; 6976 default: 6977 break; 6978 } 6979 6980 return &fw_info->normal; 6981 } 6982 6983 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6984 unsigned int length) 6985 { 6986 struct sk_buff *skb; 6987 6988 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6989 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6990 if (!skb) 6991 return NULL; 6992 6993 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6994 return skb; 6995 } 6996 6997 return dev_alloc_skb(length); 6998 } 6999 7000 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7001 struct rtw89_tx_skb_data *skb_data, 7002 bool tx_done) 7003 { 7004 struct rtw89_tx_wait_info *wait; 7005 7006 rcu_read_lock(); 7007 7008 wait = rcu_dereference(skb_data->wait); 7009 if (!wait) 7010 goto out; 7011 7012 wait->tx_done = tx_done; 7013 complete(&wait->completion); 7014 7015 out: 7016 rcu_read_unlock(); 7017 } 7018 7019 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 7020 { 7021 switch (rtwdev->mlo_dbcc_mode) { 7022 case MLO_1_PLUS_1_1RF: 7023 case MLO_1_PLUS_1_2RF: 7024 case DBCC_LEGACY: 7025 return true; 7026 default: 7027 return false; 7028 } 7029 } 7030 7031 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 7032 { 7033 if (!rtwdev->dbcc_en) 7034 return BIT(RTW89_PHY_0); 7035 7036 switch (rtwdev->mlo_dbcc_mode) { 7037 case MLO_0_PLUS_2_1RF: 7038 case MLO_0_PLUS_2_2RF: 7039 return BIT(RTW89_PHY_1); 7040 case MLO_1_PLUS_1_1RF: 7041 case MLO_1_PLUS_1_2RF: 7042 case MLO_2_PLUS_2_2RF: 7043 case DBCC_LEGACY: 7044 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 7045 case MLO_2_PLUS_0_1RF: 7046 case MLO_2_PLUS_0_2RF: 7047 default: 7048 return BIT(RTW89_PHY_0); 7049 } 7050 } 7051 7052 #define rtw89_for_each_active_bb(rtwdev, bb) \ 7053 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 7054 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 7055 if (__active_bb_bitmap & BIT(__phy_idx) && \ 7056 (bb = &rtwdev->bbs[__phy_idx])) 7057 7058 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 7059 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 7060 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 7061 if ((bb = &rtwdev->bbs[__phy_idx])) 7062 7063 static inline 7064 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 7065 enum rtw89_phy_idx phy_idx) 7066 { 7067 if (phy_idx >= RTW89_PHY_NUM) 7068 return &rtwdev->bbs[RTW89_PHY_0]; 7069 7070 return &rtwdev->bbs[phy_idx]; 7071 } 7072 7073 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7074 { 7075 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7076 7077 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7078 return true; 7079 7080 return false; 7081 } 7082 7083 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7084 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7085 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7086 struct sk_buff *skb, bool fwdl); 7087 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7088 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7089 int qsel, unsigned int timeout); 7090 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7091 struct rtw89_tx_desc_info *desc_info, 7092 void *txdesc); 7093 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7094 struct rtw89_tx_desc_info *desc_info, 7095 void *txdesc); 7096 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7097 struct rtw89_tx_desc_info *desc_info, 7098 void *txdesc); 7099 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7100 struct rtw89_tx_desc_info *desc_info, 7101 void *txdesc); 7102 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7103 struct rtw89_tx_desc_info *desc_info, 7104 void *txdesc); 7105 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7106 struct rtw89_rx_desc_info *desc_info, 7107 struct sk_buff *skb); 7108 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7109 struct rtw89_rx_desc_info *desc_info, 7110 u8 *data, u32 data_offset); 7111 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7112 struct rtw89_rx_desc_info *desc_info, 7113 u8 *data, u32 data_offset); 7114 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7115 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7116 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7117 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7118 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7119 struct rtw89_vif_link *rtwvif_link, 7120 struct rtw89_sta_link *rtwsta_link); 7121 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7122 struct rtw89_vif_link *rtwvif_link, 7123 struct rtw89_sta_link *rtwsta_link); 7124 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7125 struct rtw89_vif_link *rtwvif_link, 7126 struct rtw89_sta_link *rtwsta_link); 7127 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7128 struct rtw89_vif_link *rtwvif_link, 7129 struct rtw89_sta_link *rtwsta_link); 7130 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7131 struct rtw89_vif_link *rtwvif_link, 7132 struct rtw89_sta_link *rtwsta_link); 7133 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7134 struct ieee80211_sta *sta, 7135 struct cfg80211_tid_config *tid_config); 7136 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7137 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7138 int rtw89_core_init(struct rtw89_dev *rtwdev); 7139 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7140 int rtw89_core_register(struct rtw89_dev *rtwdev); 7141 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7142 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7143 u32 bus_data_size, 7144 const struct rtw89_chip_info *chip, 7145 const struct rtw89_chip_variant *variant); 7146 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7147 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7148 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7149 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7150 u8 mac_id, u8 port); 7151 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7152 struct rtw89_sta *rtwsta, u8 mac_id); 7153 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7154 unsigned int link_id); 7155 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7156 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7157 unsigned int link_id); 7158 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7159 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7160 const struct rtw89_6ghz_span * 7161 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7162 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7163 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7164 struct rtw89_chan *chan); 7165 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7166 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7167 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7168 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7169 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7170 struct rtw89_sta_link *rtwsta_link, u8 tid, 7171 u8 *cam_idx); 7172 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7173 struct rtw89_sta_link *rtwsta_link, u8 tid, 7174 u8 *cam_idx); 7175 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7176 struct ieee80211_sta *sta); 7177 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7178 struct ieee80211_sta *sta); 7179 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7180 struct ieee80211_sta *sta); 7181 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7182 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7183 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7184 struct rtw89_vif_link *rtwvif_link); 7185 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 7186 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7187 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7188 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7189 struct rtw89_traffic_stats *stats); 7190 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 7191 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7192 const struct rtw89_completion_data *data); 7193 int rtw89_core_start(struct rtw89_dev *rtwdev); 7194 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7195 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7196 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 7197 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7198 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7199 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7200 const u8 *mac_addr, bool hw_scan); 7201 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7202 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7203 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7204 bool active); 7205 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7206 struct rtw89_vif_link *rtwvif_link, 7207 struct ieee80211_bss_conf *bss_conf); 7208 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7209 7210 #endif 7211