1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 struct rtw89_mac_gen_def; 18 struct rtw89_phy_gen_def; 19 struct rtw89_efuse_block_cfg; 20 21 extern const struct ieee80211_ops rtw89_ops; 22 23 #define MASKBYTE0 0xff 24 #define MASKBYTE1 0xff00 25 #define MASKBYTE2 0xff0000 26 #define MASKBYTE3 0xff000000 27 #define MASKBYTE4 0xff00000000ULL 28 #define MASKHWORD 0xffff0000 29 #define MASKLWORD 0x0000ffff 30 #define MASKDWORD 0xffffffff 31 #define RFREG_MASK 0xfffff 32 #define INV_RF_DATA 0xffffffff 33 34 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 35 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 36 #define CFO_TRACK_MAX_USER 64 37 #define MAX_RSSI 110 38 #define RSSI_FACTOR 1 39 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 40 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 41 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 42 #define RTW89_RADIOTAP_ROOM_EHT \ 43 (sizeof(struct ieee80211_radiotap_tlv) + \ 44 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 45 sizeof(struct ieee80211_radiotap_tlv) + \ 46 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 47 #define RTW89_RADIOTAP_ROOM \ 48 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 49 50 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 51 #define RTW89_HTC_VARIANT_HE 3 52 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 53 #define RTW89_HTC_VARIANT_HE_CID_OM 1 54 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 55 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 56 57 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 58 enum htc_om_channel_width { 59 HTC_OM_CHANNEL_WIDTH_20 = 0, 60 HTC_OM_CHANNEL_WIDTH_40 = 1, 61 HTC_OM_CHANNEL_WIDTH_80 = 2, 62 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 63 }; 64 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 65 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 66 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 67 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 68 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 69 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 70 71 #define RTW89_TF_PAD GENMASK(11, 0) 72 #define RTW89_TF_BASIC_USER_INFO_SZ 6 73 74 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 75 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 76 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 77 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 78 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 79 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 80 81 enum rtw89_subband { 82 RTW89_CH_2G = 0, 83 RTW89_CH_5G_BAND_1 = 1, 84 /* RTW89_CH_5G_BAND_2 = 2, unused */ 85 RTW89_CH_5G_BAND_3 = 3, 86 RTW89_CH_5G_BAND_4 = 4, 87 88 RTW89_CH_6G_BAND_IDX0, /* Low */ 89 RTW89_CH_6G_BAND_IDX1, /* Low */ 90 RTW89_CH_6G_BAND_IDX2, /* Mid */ 91 RTW89_CH_6G_BAND_IDX3, /* Mid */ 92 RTW89_CH_6G_BAND_IDX4, /* High */ 93 RTW89_CH_6G_BAND_IDX5, /* High */ 94 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 95 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 96 97 RTW89_SUBBAND_NR, 98 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 99 }; 100 101 enum rtw89_gain_offset { 102 RTW89_GAIN_OFFSET_2G_CCK, 103 RTW89_GAIN_OFFSET_2G_OFDM, 104 RTW89_GAIN_OFFSET_5G_LOW, 105 RTW89_GAIN_OFFSET_5G_MID, 106 RTW89_GAIN_OFFSET_5G_HIGH, 107 RTW89_GAIN_OFFSET_6G_L0, 108 RTW89_GAIN_OFFSET_6G_L1, 109 RTW89_GAIN_OFFSET_6G_M0, 110 RTW89_GAIN_OFFSET_6G_M1, 111 RTW89_GAIN_OFFSET_6G_H0, 112 RTW89_GAIN_OFFSET_6G_H1, 113 RTW89_GAIN_OFFSET_6G_UH0, 114 RTW89_GAIN_OFFSET_6G_UH1, 115 116 RTW89_GAIN_OFFSET_NR, 117 }; 118 119 enum rtw89_hci_type { 120 RTW89_HCI_TYPE_PCIE, 121 RTW89_HCI_TYPE_USB, 122 RTW89_HCI_TYPE_SDIO, 123 }; 124 125 enum rtw89_core_chip_id { 126 RTL8852A, 127 RTL8852B, 128 RTL8852C, 129 RTL8851B, 130 RTL8922A, 131 }; 132 133 enum rtw89_chip_gen { 134 RTW89_CHIP_AX, 135 RTW89_CHIP_BE, 136 137 RTW89_CHIP_GEN_NUM, 138 }; 139 140 enum rtw89_cv { 141 CHIP_CAV, 142 CHIP_CBV, 143 CHIP_CCV, 144 CHIP_CDV, 145 CHIP_CEV, 146 CHIP_CFV, 147 CHIP_CV_MAX, 148 CHIP_CV_INVALID = CHIP_CV_MAX, 149 }; 150 151 enum rtw89_bacam_ver { 152 RTW89_BACAM_V0, 153 RTW89_BACAM_V1, 154 155 RTW89_BACAM_V0_EXT = 99, 156 }; 157 158 enum rtw89_core_tx_type { 159 RTW89_CORE_TX_TYPE_DATA, 160 RTW89_CORE_TX_TYPE_MGMT, 161 RTW89_CORE_TX_TYPE_FWCMD, 162 }; 163 164 enum rtw89_core_rx_type { 165 RTW89_CORE_RX_TYPE_WIFI = 0, 166 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 167 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 168 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 169 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 170 RTW89_CORE_RX_TYPE_SS2FW = 5, 171 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 172 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 173 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 174 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 175 RTW89_CORE_RX_TYPE_C2H = 10, 176 RTW89_CORE_RX_TYPE_CSI = 11, 177 RTW89_CORE_RX_TYPE_CQI = 12, 178 RTW89_CORE_RX_TYPE_H2C = 13, 179 RTW89_CORE_RX_TYPE_FWDL = 14, 180 }; 181 182 enum rtw89_txq_flags { 183 RTW89_TXQ_F_AMPDU = 0, 184 RTW89_TXQ_F_BLOCK_BA = 1, 185 RTW89_TXQ_F_FORBID_BA = 2, 186 }; 187 188 enum rtw89_net_type { 189 RTW89_NET_TYPE_NO_LINK = 0, 190 RTW89_NET_TYPE_AD_HOC = 1, 191 RTW89_NET_TYPE_INFRA = 2, 192 RTW89_NET_TYPE_AP_MODE = 3, 193 }; 194 195 enum rtw89_wifi_role { 196 RTW89_WIFI_ROLE_NONE, 197 RTW89_WIFI_ROLE_STATION, 198 RTW89_WIFI_ROLE_AP, 199 RTW89_WIFI_ROLE_AP_VLAN, 200 RTW89_WIFI_ROLE_ADHOC, 201 RTW89_WIFI_ROLE_ADHOC_MASTER, 202 RTW89_WIFI_ROLE_MESH_POINT, 203 RTW89_WIFI_ROLE_MONITOR, 204 RTW89_WIFI_ROLE_P2P_DEVICE, 205 RTW89_WIFI_ROLE_P2P_CLIENT, 206 RTW89_WIFI_ROLE_P2P_GO, 207 RTW89_WIFI_ROLE_NAN, 208 RTW89_WIFI_ROLE_MLME_MAX 209 }; 210 211 enum rtw89_upd_mode { 212 RTW89_ROLE_CREATE, 213 RTW89_ROLE_REMOVE, 214 RTW89_ROLE_TYPE_CHANGE, 215 RTW89_ROLE_INFO_CHANGE, 216 RTW89_ROLE_CON_DISCONN, 217 RTW89_ROLE_BAND_SW, 218 RTW89_ROLE_FW_RESTORE, 219 }; 220 221 enum rtw89_self_role { 222 RTW89_SELF_ROLE_CLIENT, 223 RTW89_SELF_ROLE_AP, 224 RTW89_SELF_ROLE_AP_CLIENT 225 }; 226 227 enum rtw89_msk_sO_el { 228 RTW89_NO_MSK, 229 RTW89_SMA, 230 RTW89_TMA, 231 RTW89_BSSID 232 }; 233 234 enum rtw89_sch_tx_sel { 235 RTW89_SCH_TX_SEL_ALL, 236 RTW89_SCH_TX_SEL_HIQ, 237 RTW89_SCH_TX_SEL_MG0, 238 RTW89_SCH_TX_SEL_MACID, 239 }; 240 241 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 242 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 243 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 244 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 245 */ 246 enum rtw89_add_cam_sec_mode { 247 RTW89_ADDR_CAM_SEC_NONE = 0, 248 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 249 RTW89_ADDR_CAM_SEC_NORMAL = 2, 250 RTW89_ADDR_CAM_SEC_4GROUP = 3, 251 }; 252 253 enum rtw89_sec_key_type { 254 RTW89_SEC_KEY_TYPE_NONE = 0, 255 RTW89_SEC_KEY_TYPE_WEP40 = 1, 256 RTW89_SEC_KEY_TYPE_WEP104 = 2, 257 RTW89_SEC_KEY_TYPE_TKIP = 3, 258 RTW89_SEC_KEY_TYPE_WAPI = 4, 259 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 260 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 261 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 262 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 263 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 264 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 265 }; 266 267 enum rtw89_port { 268 RTW89_PORT_0 = 0, 269 RTW89_PORT_1 = 1, 270 RTW89_PORT_2 = 2, 271 RTW89_PORT_3 = 3, 272 RTW89_PORT_4 = 4, 273 RTW89_PORT_NUM 274 }; 275 276 enum rtw89_band { 277 RTW89_BAND_2G = 0, 278 RTW89_BAND_5G = 1, 279 RTW89_BAND_6G = 2, 280 RTW89_BAND_NUM, 281 }; 282 283 enum rtw89_hw_rate { 284 RTW89_HW_RATE_CCK1 = 0x0, 285 RTW89_HW_RATE_CCK2 = 0x1, 286 RTW89_HW_RATE_CCK5_5 = 0x2, 287 RTW89_HW_RATE_CCK11 = 0x3, 288 RTW89_HW_RATE_OFDM6 = 0x4, 289 RTW89_HW_RATE_OFDM9 = 0x5, 290 RTW89_HW_RATE_OFDM12 = 0x6, 291 RTW89_HW_RATE_OFDM18 = 0x7, 292 RTW89_HW_RATE_OFDM24 = 0x8, 293 RTW89_HW_RATE_OFDM36 = 0x9, 294 RTW89_HW_RATE_OFDM48 = 0xA, 295 RTW89_HW_RATE_OFDM54 = 0xB, 296 RTW89_HW_RATE_MCS0 = 0x80, 297 RTW89_HW_RATE_MCS1 = 0x81, 298 RTW89_HW_RATE_MCS2 = 0x82, 299 RTW89_HW_RATE_MCS3 = 0x83, 300 RTW89_HW_RATE_MCS4 = 0x84, 301 RTW89_HW_RATE_MCS5 = 0x85, 302 RTW89_HW_RATE_MCS6 = 0x86, 303 RTW89_HW_RATE_MCS7 = 0x87, 304 RTW89_HW_RATE_MCS8 = 0x88, 305 RTW89_HW_RATE_MCS9 = 0x89, 306 RTW89_HW_RATE_MCS10 = 0x8A, 307 RTW89_HW_RATE_MCS11 = 0x8B, 308 RTW89_HW_RATE_MCS12 = 0x8C, 309 RTW89_HW_RATE_MCS13 = 0x8D, 310 RTW89_HW_RATE_MCS14 = 0x8E, 311 RTW89_HW_RATE_MCS15 = 0x8F, 312 RTW89_HW_RATE_MCS16 = 0x90, 313 RTW89_HW_RATE_MCS17 = 0x91, 314 RTW89_HW_RATE_MCS18 = 0x92, 315 RTW89_HW_RATE_MCS19 = 0x93, 316 RTW89_HW_RATE_MCS20 = 0x94, 317 RTW89_HW_RATE_MCS21 = 0x95, 318 RTW89_HW_RATE_MCS22 = 0x96, 319 RTW89_HW_RATE_MCS23 = 0x97, 320 RTW89_HW_RATE_MCS24 = 0x98, 321 RTW89_HW_RATE_MCS25 = 0x99, 322 RTW89_HW_RATE_MCS26 = 0x9A, 323 RTW89_HW_RATE_MCS27 = 0x9B, 324 RTW89_HW_RATE_MCS28 = 0x9C, 325 RTW89_HW_RATE_MCS29 = 0x9D, 326 RTW89_HW_RATE_MCS30 = 0x9E, 327 RTW89_HW_RATE_MCS31 = 0x9F, 328 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 329 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 330 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 331 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 332 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 333 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 334 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 335 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 336 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 337 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 338 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 339 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 340 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 341 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 342 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 343 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 344 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 345 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 346 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 347 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 348 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 349 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 350 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 351 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 352 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 353 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 354 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 355 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 356 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 357 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 358 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 359 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 360 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 361 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 362 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 363 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 364 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 365 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 366 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 367 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 368 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 369 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 370 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 371 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 372 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 373 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 374 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 375 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 376 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 377 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 378 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 379 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 380 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 381 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 382 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 383 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 384 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 385 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 386 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 387 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 388 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 389 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 390 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 391 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 392 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 393 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 394 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 395 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 396 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 397 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 398 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 399 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 400 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 401 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 402 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 403 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 404 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 405 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 406 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 407 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 408 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 409 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 410 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 411 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 412 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 413 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 414 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 415 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 416 417 RTW89_HW_RATE_V1_MCS0 = 0x100, 418 RTW89_HW_RATE_V1_MCS1 = 0x101, 419 RTW89_HW_RATE_V1_MCS2 = 0x102, 420 RTW89_HW_RATE_V1_MCS3 = 0x103, 421 RTW89_HW_RATE_V1_MCS4 = 0x104, 422 RTW89_HW_RATE_V1_MCS5 = 0x105, 423 RTW89_HW_RATE_V1_MCS6 = 0x106, 424 RTW89_HW_RATE_V1_MCS7 = 0x107, 425 RTW89_HW_RATE_V1_MCS8 = 0x108, 426 RTW89_HW_RATE_V1_MCS9 = 0x109, 427 RTW89_HW_RATE_V1_MCS10 = 0x10A, 428 RTW89_HW_RATE_V1_MCS11 = 0x10B, 429 RTW89_HW_RATE_V1_MCS12 = 0x10C, 430 RTW89_HW_RATE_V1_MCS13 = 0x10D, 431 RTW89_HW_RATE_V1_MCS14 = 0x10E, 432 RTW89_HW_RATE_V1_MCS15 = 0x10F, 433 RTW89_HW_RATE_V1_MCS16 = 0x110, 434 RTW89_HW_RATE_V1_MCS17 = 0x111, 435 RTW89_HW_RATE_V1_MCS18 = 0x112, 436 RTW89_HW_RATE_V1_MCS19 = 0x113, 437 RTW89_HW_RATE_V1_MCS20 = 0x114, 438 RTW89_HW_RATE_V1_MCS21 = 0x115, 439 RTW89_HW_RATE_V1_MCS22 = 0x116, 440 RTW89_HW_RATE_V1_MCS23 = 0x117, 441 RTW89_HW_RATE_V1_MCS24 = 0x118, 442 RTW89_HW_RATE_V1_MCS25 = 0x119, 443 RTW89_HW_RATE_V1_MCS26 = 0x11A, 444 RTW89_HW_RATE_V1_MCS27 = 0x11B, 445 RTW89_HW_RATE_V1_MCS28 = 0x11C, 446 RTW89_HW_RATE_V1_MCS29 = 0x11D, 447 RTW89_HW_RATE_V1_MCS30 = 0x11E, 448 RTW89_HW_RATE_V1_MCS31 = 0x11F, 449 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 450 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 451 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 452 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 453 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 454 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 455 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 456 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 461 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 462 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 463 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 464 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 465 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 466 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 467 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 468 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 473 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 474 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 475 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 476 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 477 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 478 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 479 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 480 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 485 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 486 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 487 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 488 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 489 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 490 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 491 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 492 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 497 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 498 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 499 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 500 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 501 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 502 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 503 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 504 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 509 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 510 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 511 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 512 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 513 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 514 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 515 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 516 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 521 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 522 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 523 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 524 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 525 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 526 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 527 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 528 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 533 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 534 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 535 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 536 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 537 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 538 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 539 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 540 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 545 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 546 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 547 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 548 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 549 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 550 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 551 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 552 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 561 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 562 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 563 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 564 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 565 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 566 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 567 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 568 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 575 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 576 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 577 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 578 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 579 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 580 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 581 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 582 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 589 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 590 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 591 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 592 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 593 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 594 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 595 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 596 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 603 604 RTW89_HW_RATE_NR, 605 RTW89_HW_RATE_INVAL, 606 607 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 608 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 609 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 610 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 611 }; 612 613 /* 2G channels, 614 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 615 */ 616 #define RTW89_2G_CH_NUM 14 617 618 /* 5G channels, 619 * 36, 38, 40, 42, 44, 46, 48, 50, 620 * 52, 54, 56, 58, 60, 62, 64, 621 * 100, 102, 104, 106, 108, 110, 112, 114, 622 * 116, 118, 120, 122, 124, 126, 128, 130, 623 * 132, 134, 136, 138, 140, 142, 144, 624 * 149, 151, 153, 155, 157, 159, 161, 163, 625 * 165, 167, 169, 171, 173, 175, 177 626 */ 627 #define RTW89_5G_CH_NUM 53 628 629 /* 6G channels, 630 * 1, 3, 5, 7, 9, 11, 13, 15, 631 * 17, 19, 21, 23, 25, 27, 29, 33, 632 * 35, 37, 39, 41, 43, 45, 47, 49, 633 * 51, 53, 55, 57, 59, 61, 65, 67, 634 * 69, 71, 73, 75, 77, 79, 81, 83, 635 * 85, 87, 89, 91, 93, 97, 99, 101, 636 * 103, 105, 107, 109, 111, 113, 115, 117, 637 * 119, 121, 123, 125, 129, 131, 133, 135, 638 * 137, 139, 141, 143, 145, 147, 149, 151, 639 * 153, 155, 157, 161, 163, 165, 167, 169, 640 * 171, 173, 175, 177, 179, 181, 183, 185, 641 * 187, 189, 193, 195, 197, 199, 201, 203, 642 * 205, 207, 209, 211, 213, 215, 217, 219, 643 * 221, 225, 227, 229, 231, 233, 235, 237, 644 * 239, 241, 243, 245, 247, 249, 251, 253, 645 */ 646 #define RTW89_6G_CH_NUM 120 647 648 enum rtw89_rate_section { 649 RTW89_RS_CCK, 650 RTW89_RS_OFDM, 651 RTW89_RS_MCS, /* for HT/VHT/HE */ 652 RTW89_RS_HEDCM, 653 RTW89_RS_OFFSET, 654 RTW89_RS_NUM, 655 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 656 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 657 }; 658 659 enum rtw89_rate_offset_indexes { 660 RTW89_RATE_OFFSET_HE, 661 RTW89_RATE_OFFSET_VHT, 662 RTW89_RATE_OFFSET_HT, 663 RTW89_RATE_OFFSET_OFDM, 664 RTW89_RATE_OFFSET_CCK, 665 RTW89_RATE_OFFSET_DLRU_EHT, 666 RTW89_RATE_OFFSET_DLRU_HE, 667 RTW89_RATE_OFFSET_EHT, 668 __RTW89_RATE_OFFSET_NUM, 669 670 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 671 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 672 }; 673 674 enum rtw89_rate_num { 675 RTW89_RATE_CCK_NUM = 4, 676 RTW89_RATE_OFDM_NUM = 8, 677 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 678 679 RTW89_RATE_MCS_NUM_AX = 12, 680 RTW89_RATE_MCS_NUM_BE = 16, 681 __RTW89_RATE_MCS_NUM = 16, 682 }; 683 684 enum rtw89_nss { 685 RTW89_NSS_1 = 0, 686 RTW89_NSS_2 = 1, 687 /* HE DCM only support 1ss and 2ss */ 688 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 689 RTW89_NSS_3 = 2, 690 RTW89_NSS_4 = 3, 691 RTW89_NSS_NUM, 692 }; 693 694 enum rtw89_ntx { 695 RTW89_1TX = 0, 696 RTW89_2TX = 1, 697 RTW89_NTX_NUM, 698 }; 699 700 enum rtw89_beamforming_type { 701 RTW89_NONBF = 0, 702 RTW89_BF = 1, 703 RTW89_BF_NUM, 704 }; 705 706 enum rtw89_ofdma_type { 707 RTW89_NON_OFDMA = 0, 708 RTW89_OFDMA = 1, 709 RTW89_OFDMA_NUM, 710 }; 711 712 enum rtw89_regulation_type { 713 RTW89_WW = 0, 714 RTW89_ETSI = 1, 715 RTW89_FCC = 2, 716 RTW89_MKK = 3, 717 RTW89_NA = 4, 718 RTW89_IC = 5, 719 RTW89_KCC = 6, 720 RTW89_ACMA = 7, 721 RTW89_NCC = 8, 722 RTW89_MEXICO = 9, 723 RTW89_CHILE = 10, 724 RTW89_UKRAINE = 11, 725 RTW89_CN = 12, 726 RTW89_QATAR = 13, 727 RTW89_UK = 14, 728 RTW89_THAILAND = 15, 729 RTW89_REGD_NUM, 730 }; 731 732 enum rtw89_reg_6ghz_power { 733 RTW89_REG_6GHZ_POWER_VLP = 0, 734 RTW89_REG_6GHZ_POWER_LPI = 1, 735 RTW89_REG_6GHZ_POWER_STD = 2, 736 737 NUM_OF_RTW89_REG_6GHZ_POWER, 738 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 739 }; 740 741 enum rtw89_fw_pkt_ofld_type { 742 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 743 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 744 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 745 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 746 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 747 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 748 RTW89_PKT_OFLD_TYPE_NDP = 6, 749 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 750 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 751 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 752 RTW89_PKT_OFLD_TYPE_NUM, 753 }; 754 755 struct rtw89_txpwr_byrate { 756 s8 cck[RTW89_RATE_CCK_NUM]; 757 s8 ofdm[RTW89_RATE_OFDM_NUM]; 758 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 759 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 760 s8 offset[__RTW89_RATE_OFFSET_NUM]; 761 s8 trap; 762 }; 763 764 struct rtw89_rate_desc { 765 enum rtw89_nss nss; 766 enum rtw89_rate_section rs; 767 enum rtw89_ofdma_type ofdma; 768 u8 idx; 769 }; 770 771 #define PHY_STS_HDR_LEN 8 772 #define RF_PATH_MAX 4 773 #define RTW89_MAX_PPDU_CNT 8 774 struct rtw89_rx_phy_ppdu { 775 void *buf; 776 u32 len; 777 u8 rssi_avg; 778 u8 rssi[RF_PATH_MAX]; 779 u8 mac_id; 780 u8 chan_idx; 781 u8 ie; 782 u16 rate; 783 struct { 784 bool has; 785 u8 avg_snr; 786 u8 evm_max; 787 u8 evm_min; 788 } ofdm; 789 bool to_self; 790 bool valid; 791 }; 792 793 enum rtw89_mac_idx { 794 RTW89_MAC_0 = 0, 795 RTW89_MAC_1 = 1, 796 }; 797 798 enum rtw89_phy_idx { 799 RTW89_PHY_0 = 0, 800 RTW89_PHY_1 = 1, 801 RTW89_PHY_MAX 802 }; 803 804 enum rtw89_sub_entity_idx { 805 RTW89_SUB_ENTITY_0 = 0, 806 RTW89_SUB_ENTITY_1 = 1, 807 808 NUM_OF_RTW89_SUB_ENTITY, 809 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 810 }; 811 812 enum rtw89_rf_path { 813 RF_PATH_A = 0, 814 RF_PATH_B = 1, 815 RF_PATH_C = 2, 816 RF_PATH_D = 3, 817 RF_PATH_AB, 818 RF_PATH_AC, 819 RF_PATH_AD, 820 RF_PATH_BC, 821 RF_PATH_BD, 822 RF_PATH_CD, 823 RF_PATH_ABC, 824 RF_PATH_ABD, 825 RF_PATH_ACD, 826 RF_PATH_BCD, 827 RF_PATH_ABCD, 828 }; 829 830 enum rtw89_rf_path_bit { 831 RF_A = BIT(0), 832 RF_B = BIT(1), 833 RF_C = BIT(2), 834 RF_D = BIT(3), 835 836 RF_AB = (RF_A | RF_B), 837 RF_AC = (RF_A | RF_C), 838 RF_AD = (RF_A | RF_D), 839 RF_BC = (RF_B | RF_C), 840 RF_BD = (RF_B | RF_D), 841 RF_CD = (RF_C | RF_D), 842 843 RF_ABC = (RF_A | RF_B | RF_C), 844 RF_ABD = (RF_A | RF_B | RF_D), 845 RF_ACD = (RF_A | RF_C | RF_D), 846 RF_BCD = (RF_B | RF_C | RF_D), 847 848 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 849 }; 850 851 enum rtw89_bandwidth { 852 RTW89_CHANNEL_WIDTH_20 = 0, 853 RTW89_CHANNEL_WIDTH_40 = 1, 854 RTW89_CHANNEL_WIDTH_80 = 2, 855 RTW89_CHANNEL_WIDTH_160 = 3, 856 RTW89_CHANNEL_WIDTH_320 = 4, 857 858 /* keep index order above */ 859 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 860 861 RTW89_CHANNEL_WIDTH_80_80 = 5, 862 RTW89_CHANNEL_WIDTH_5 = 6, 863 RTW89_CHANNEL_WIDTH_10 = 7, 864 }; 865 866 enum rtw89_ps_mode { 867 RTW89_PS_MODE_NONE = 0, 868 RTW89_PS_MODE_RFOFF = 1, 869 RTW89_PS_MODE_CLK_GATED = 2, 870 RTW89_PS_MODE_PWR_GATED = 3, 871 }; 872 873 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 874 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 875 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 876 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 877 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 878 879 enum rtw89_ru_bandwidth { 880 RTW89_RU26 = 0, 881 RTW89_RU52 = 1, 882 RTW89_RU106 = 2, 883 RTW89_RU52_26 = 3, 884 RTW89_RU106_26 = 4, 885 RTW89_RU_NUM, 886 }; 887 888 enum rtw89_sc_offset { 889 RTW89_SC_DONT_CARE = 0, 890 RTW89_SC_20_UPPER = 1, 891 RTW89_SC_20_LOWER = 2, 892 RTW89_SC_20_UPMOST = 3, 893 RTW89_SC_20_LOWEST = 4, 894 RTW89_SC_20_UP2X = 5, 895 RTW89_SC_20_LOW2X = 6, 896 RTW89_SC_20_UP3X = 7, 897 RTW89_SC_20_LOW3X = 8, 898 RTW89_SC_40_UPPER = 9, 899 RTW89_SC_40_LOWER = 10, 900 }; 901 902 enum rtw89_wow_flags { 903 RTW89_WOW_FLAG_EN_MAGIC_PKT, 904 RTW89_WOW_FLAG_EN_REKEY_PKT, 905 RTW89_WOW_FLAG_EN_DISCONNECT, 906 RTW89_WOW_FLAG_NUM, 907 }; 908 909 struct rtw89_chan { 910 u8 channel; 911 u8 primary_channel; 912 enum rtw89_band band_type; 913 enum rtw89_bandwidth band_width; 914 915 /* The follow-up are derived from the above. We must ensure that it 916 * is assigned correctly in rtw89_chan_create() if new one is added. 917 */ 918 u32 freq; 919 enum rtw89_subband subband_type; 920 enum rtw89_sc_offset pri_ch_idx; 921 u8 pri_sb_idx; 922 }; 923 924 struct rtw89_chan_rcd { 925 u8 prev_primary_channel; 926 enum rtw89_band prev_band_type; 927 bool band_changed; 928 }; 929 930 struct rtw89_channel_help_params { 931 u32 tx_en; 932 }; 933 934 struct rtw89_port_reg { 935 u32 port_cfg; 936 u32 tbtt_prohib; 937 u32 bcn_area; 938 u32 bcn_early; 939 u32 tbtt_early; 940 u32 tbtt_agg; 941 u32 bcn_space; 942 u32 bcn_forcetx; 943 u32 bcn_err_cnt; 944 u32 bcn_err_flag; 945 u32 dtim_ctrl; 946 u32 tbtt_shift; 947 u32 bcn_cnt_tmr; 948 u32 tsftr_l; 949 u32 tsftr_h; 950 u32 md_tsft; 951 u32 bss_color; 952 u32 mbssid; 953 u32 mbssid_drop; 954 u32 tsf_sync; 955 u32 hiq_win[RTW89_PORT_NUM]; 956 }; 957 958 struct rtw89_txwd_body { 959 __le32 dword0; 960 __le32 dword1; 961 __le32 dword2; 962 __le32 dword3; 963 __le32 dword4; 964 __le32 dword5; 965 } __packed; 966 967 struct rtw89_txwd_body_v1 { 968 __le32 dword0; 969 __le32 dword1; 970 __le32 dword2; 971 __le32 dword3; 972 __le32 dword4; 973 __le32 dword5; 974 __le32 dword6; 975 __le32 dword7; 976 } __packed; 977 978 struct rtw89_txwd_body_v2 { 979 __le32 dword0; 980 __le32 dword1; 981 __le32 dword2; 982 __le32 dword3; 983 __le32 dword4; 984 __le32 dword5; 985 __le32 dword6; 986 __le32 dword7; 987 } __packed; 988 989 struct rtw89_txwd_info { 990 __le32 dword0; 991 __le32 dword1; 992 __le32 dword2; 993 __le32 dword3; 994 __le32 dword4; 995 __le32 dword5; 996 } __packed; 997 998 struct rtw89_txwd_info_v2 { 999 __le32 dword0; 1000 __le32 dword1; 1001 __le32 dword2; 1002 __le32 dword3; 1003 __le32 dword4; 1004 __le32 dword5; 1005 __le32 dword6; 1006 __le32 dword7; 1007 } __packed; 1008 1009 struct rtw89_rx_desc_info { 1010 u16 pkt_size; 1011 u8 pkt_type; 1012 u8 drv_info_size; 1013 u8 phy_rpt_size; 1014 u8 hdr_cnv_size; 1015 u8 shift; 1016 u8 wl_hd_iv_len; 1017 bool long_rxdesc; 1018 bool bb_sel; 1019 bool mac_info_valid; 1020 u16 data_rate; 1021 u8 gi_ltf; 1022 u8 bw; 1023 u32 free_run_cnt; 1024 u8 user_id; 1025 bool sr_en; 1026 u8 ppdu_cnt; 1027 u8 ppdu_type; 1028 bool icv_err; 1029 bool crc32_err; 1030 bool hw_dec; 1031 bool sw_dec; 1032 bool addr1_match; 1033 u8 frag; 1034 u16 seq; 1035 u8 frame_type; 1036 u8 rx_pl_id; 1037 bool addr_cam_valid; 1038 u8 addr_cam_id; 1039 u8 sec_cam_id; 1040 u8 mac_id; 1041 u16 offset; 1042 u16 rxd_len; 1043 bool ready; 1044 }; 1045 1046 struct rtw89_rxdesc_short { 1047 __le32 dword0; 1048 __le32 dword1; 1049 __le32 dword2; 1050 __le32 dword3; 1051 } __packed; 1052 1053 struct rtw89_rxdesc_short_v2 { 1054 __le32 dword0; 1055 __le32 dword1; 1056 __le32 dword2; 1057 __le32 dword3; 1058 __le32 dword4; 1059 __le32 dword5; 1060 } __packed; 1061 1062 struct rtw89_rxdesc_long { 1063 __le32 dword0; 1064 __le32 dword1; 1065 __le32 dword2; 1066 __le32 dword3; 1067 __le32 dword4; 1068 __le32 dword5; 1069 __le32 dword6; 1070 __le32 dword7; 1071 } __packed; 1072 1073 struct rtw89_rxdesc_long_v2 { 1074 __le32 dword0; 1075 __le32 dword1; 1076 __le32 dword2; 1077 __le32 dword3; 1078 __le32 dword4; 1079 __le32 dword5; 1080 __le32 dword6; 1081 __le32 dword7; 1082 __le32 dword8; 1083 __le32 dword9; 1084 } __packed; 1085 1086 struct rtw89_tx_desc_info { 1087 u16 pkt_size; 1088 u8 wp_offset; 1089 u8 mac_id; 1090 u8 qsel; 1091 u8 ch_dma; 1092 u8 hdr_llc_len; 1093 bool is_bmc; 1094 bool en_wd_info; 1095 bool wd_page; 1096 bool use_rate; 1097 bool dis_data_fb; 1098 bool tid_indicate; 1099 bool agg_en; 1100 bool bk; 1101 u8 ampdu_density; 1102 u8 ampdu_num; 1103 bool sec_en; 1104 u8 addr_info_nr; 1105 u8 sec_keyid; 1106 u8 sec_type; 1107 u8 sec_cam_idx; 1108 u8 sec_seq[6]; 1109 u16 data_rate; 1110 u16 data_retry_lowest_rate; 1111 bool fw_dl; 1112 u16 seq; 1113 bool a_ctrl_bsr; 1114 u8 hw_ssn_sel; 1115 #define RTW89_MGMT_HW_SSN_SEL 1 1116 u8 hw_seq_mode; 1117 #define RTW89_MGMT_HW_SEQ_MODE 1 1118 bool hiq; 1119 u8 port; 1120 bool er_cap; 1121 }; 1122 1123 struct rtw89_core_tx_request { 1124 enum rtw89_core_tx_type tx_type; 1125 1126 struct sk_buff *skb; 1127 struct ieee80211_vif *vif; 1128 struct ieee80211_sta *sta; 1129 struct rtw89_tx_desc_info desc_info; 1130 }; 1131 1132 struct rtw89_txq { 1133 struct list_head list; 1134 unsigned long flags; 1135 int wait_cnt; 1136 }; 1137 1138 struct rtw89_mac_ax_gnt { 1139 u8 gnt_bt_sw_en; 1140 u8 gnt_bt; 1141 u8 gnt_wl_sw_en; 1142 u8 gnt_wl; 1143 } __packed; 1144 1145 #define RTW89_MAC_AX_COEX_GNT_NR 2 1146 struct rtw89_mac_ax_coex_gnt { 1147 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1148 }; 1149 1150 enum rtw89_btc_ncnt { 1151 BTC_NCNT_POWER_ON = 0x0, 1152 BTC_NCNT_POWER_OFF, 1153 BTC_NCNT_INIT_COEX, 1154 BTC_NCNT_SCAN_START, 1155 BTC_NCNT_SCAN_FINISH, 1156 BTC_NCNT_SPECIAL_PACKET, 1157 BTC_NCNT_SWITCH_BAND, 1158 BTC_NCNT_RFK_TIMEOUT, 1159 BTC_NCNT_SHOW_COEX_INFO, 1160 BTC_NCNT_ROLE_INFO, 1161 BTC_NCNT_CONTROL, 1162 BTC_NCNT_RADIO_STATE, 1163 BTC_NCNT_CUSTOMERIZE, 1164 BTC_NCNT_WL_RFK, 1165 BTC_NCNT_WL_STA, 1166 BTC_NCNT_FWINFO, 1167 BTC_NCNT_TIMER, 1168 BTC_NCNT_NUM 1169 }; 1170 1171 enum rtw89_btc_btinfo { 1172 BTC_BTINFO_L0 = 0, 1173 BTC_BTINFO_L1, 1174 BTC_BTINFO_L2, 1175 BTC_BTINFO_L3, 1176 BTC_BTINFO_H0, 1177 BTC_BTINFO_H1, 1178 BTC_BTINFO_H2, 1179 BTC_BTINFO_H3, 1180 BTC_BTINFO_MAX 1181 }; 1182 1183 enum rtw89_btc_dcnt { 1184 BTC_DCNT_RUN = 0x0, 1185 BTC_DCNT_CX_RUNINFO, 1186 BTC_DCNT_RPT, 1187 BTC_DCNT_RPT_HANG, 1188 BTC_DCNT_CYCLE, 1189 BTC_DCNT_CYCLE_HANG, 1190 BTC_DCNT_W1, 1191 BTC_DCNT_W1_HANG, 1192 BTC_DCNT_B1, 1193 BTC_DCNT_B1_HANG, 1194 BTC_DCNT_TDMA_NONSYNC, 1195 BTC_DCNT_SLOT_NONSYNC, 1196 BTC_DCNT_BTCNT_HANG, 1197 BTC_DCNT_WL_SLOT_DRIFT, 1198 BTC_DCNT_WL_STA_LAST, 1199 BTC_DCNT_BT_SLOT_DRIFT, 1200 BTC_DCNT_BT_SLOT_FLOOD, 1201 BTC_DCNT_FDDT_TRIG, 1202 BTC_DCNT_E2G, 1203 BTC_DCNT_E2G_HANG, 1204 BTC_DCNT_NUM 1205 }; 1206 1207 enum rtw89_btc_wl_state_cnt { 1208 BTC_WCNT_SCANAP = 0x0, 1209 BTC_WCNT_DHCP, 1210 BTC_WCNT_EAPOL, 1211 BTC_WCNT_ARP, 1212 BTC_WCNT_SCBDUPDATE, 1213 BTC_WCNT_RFK_REQ, 1214 BTC_WCNT_RFK_GO, 1215 BTC_WCNT_RFK_REJECT, 1216 BTC_WCNT_RFK_TIMEOUT, 1217 BTC_WCNT_CH_UPDATE, 1218 BTC_WCNT_NUM 1219 }; 1220 1221 enum rtw89_btc_bt_state_cnt { 1222 BTC_BCNT_RETRY = 0x0, 1223 BTC_BCNT_REINIT, 1224 BTC_BCNT_REENABLE, 1225 BTC_BCNT_SCBDREAD, 1226 BTC_BCNT_RELINK, 1227 BTC_BCNT_IGNOWL, 1228 BTC_BCNT_INQPAG, 1229 BTC_BCNT_INQ, 1230 BTC_BCNT_PAGE, 1231 BTC_BCNT_ROLESW, 1232 BTC_BCNT_AFH, 1233 BTC_BCNT_INFOUPDATE, 1234 BTC_BCNT_INFOSAME, 1235 BTC_BCNT_SCBDUPDATE, 1236 BTC_BCNT_HIPRI_TX, 1237 BTC_BCNT_HIPRI_RX, 1238 BTC_BCNT_LOPRI_TX, 1239 BTC_BCNT_LOPRI_RX, 1240 BTC_BCNT_POLUT, 1241 BTC_BCNT_RATECHG, 1242 BTC_BCNT_NUM 1243 }; 1244 1245 enum rtw89_btc_bt_profile { 1246 BTC_BT_NOPROFILE = 0, 1247 BTC_BT_HFP = BIT(0), 1248 BTC_BT_HID = BIT(1), 1249 BTC_BT_A2DP = BIT(2), 1250 BTC_BT_PAN = BIT(3), 1251 BTC_PROFILE_MAX = 4, 1252 }; 1253 1254 struct rtw89_btc_ant_info { 1255 u8 type; /* shared, dedicated */ 1256 u8 num; 1257 u8 isolation; 1258 1259 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1260 u8 diversity: 1; 1261 u8 btg_pos: 2; 1262 u8 stream_cnt: 4; 1263 }; 1264 1265 enum rtw89_tfc_dir { 1266 RTW89_TFC_UL, 1267 RTW89_TFC_DL, 1268 }; 1269 1270 struct rtw89_btc_wl_smap { 1271 u32 busy: 1; 1272 u32 scan: 1; 1273 u32 connecting: 1; 1274 u32 roaming: 1; 1275 u32 _4way: 1; 1276 u32 rf_off: 1; 1277 u32 lps: 2; 1278 u32 ips: 1; 1279 u32 init_ok: 1; 1280 u32 traffic_dir : 2; 1281 u32 rf_off_pre: 1; 1282 u32 lps_pre: 2; 1283 }; 1284 1285 enum rtw89_tfc_lv { 1286 RTW89_TFC_IDLE, 1287 RTW89_TFC_ULTRA_LOW, 1288 RTW89_TFC_LOW, 1289 RTW89_TFC_MID, 1290 RTW89_TFC_HIGH, 1291 }; 1292 1293 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1294 DECLARE_EWMA(tp, 10, 2); 1295 1296 struct rtw89_traffic_stats { 1297 /* units in bytes */ 1298 u64 tx_unicast; 1299 u64 rx_unicast; 1300 u32 tx_avg_len; 1301 u32 rx_avg_len; 1302 1303 /* count for packets */ 1304 u64 tx_cnt; 1305 u64 rx_cnt; 1306 1307 /* units in Mbps */ 1308 u32 tx_throughput; 1309 u32 rx_throughput; 1310 u32 tx_throughput_raw; 1311 u32 rx_throughput_raw; 1312 1313 u32 rx_tf_acc; 1314 u32 rx_tf_periodic; 1315 1316 enum rtw89_tfc_lv tx_tfc_lv; 1317 enum rtw89_tfc_lv rx_tfc_lv; 1318 struct ewma_tp tx_ewma_tp; 1319 struct ewma_tp rx_ewma_tp; 1320 1321 u16 tx_rate; 1322 u16 rx_rate; 1323 }; 1324 1325 struct rtw89_btc_statistic { 1326 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1327 struct rtw89_traffic_stats traffic; 1328 }; 1329 1330 #define BTC_WL_RSSI_THMAX 4 1331 1332 struct rtw89_btc_wl_link_info { 1333 struct rtw89_btc_statistic stat; 1334 enum rtw89_tfc_dir dir; 1335 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1336 u8 mac_addr[ETH_ALEN]; 1337 u8 busy; 1338 u8 ch; 1339 u8 bw; 1340 u8 band; 1341 u8 role; 1342 u8 pid; 1343 u8 phy; 1344 u8 dtim_period; 1345 u8 mode; 1346 1347 u8 mac_id; 1348 u8 tx_retry; 1349 1350 u32 bcn_period; 1351 u32 busy_t; 1352 u32 tx_time; 1353 u32 client_cnt; 1354 u32 rx_rate_drop_cnt; 1355 1356 u32 active: 1; 1357 u32 noa: 1; 1358 u32 client_ps: 1; 1359 u32 connected: 2; 1360 }; 1361 1362 union rtw89_btc_wl_state_map { 1363 u32 val; 1364 struct rtw89_btc_wl_smap map; 1365 }; 1366 1367 struct rtw89_btc_bt_hfp_desc { 1368 u32 exist: 1; 1369 u32 type: 2; 1370 u32 rsvd: 29; 1371 }; 1372 1373 struct rtw89_btc_bt_hid_desc { 1374 u32 exist: 1; 1375 u32 slot_info: 2; 1376 u32 pair_cnt: 2; 1377 u32 type: 8; 1378 u32 rsvd: 19; 1379 }; 1380 1381 struct rtw89_btc_bt_a2dp_desc { 1382 u8 exist: 1; 1383 u8 exist_last: 1; 1384 u8 play_latency: 1; 1385 u8 type: 3; 1386 u8 active: 1; 1387 u8 sink: 1; 1388 1389 u8 bitpool; 1390 u16 vendor_id; 1391 u32 device_name; 1392 u32 flush_time; 1393 }; 1394 1395 struct rtw89_btc_bt_pan_desc { 1396 u32 exist: 1; 1397 u32 type: 1; 1398 u32 active: 1; 1399 u32 rsvd: 29; 1400 }; 1401 1402 struct rtw89_btc_bt_rfk_info { 1403 u32 run: 1; 1404 u32 req: 1; 1405 u32 timeout: 1; 1406 u32 rsvd: 29; 1407 }; 1408 1409 union rtw89_btc_bt_rfk_info_map { 1410 u32 val; 1411 struct rtw89_btc_bt_rfk_info map; 1412 }; 1413 1414 struct rtw89_btc_bt_ver_info { 1415 u32 fw_coex; /* match with which coex_ver */ 1416 u32 fw; 1417 }; 1418 1419 struct rtw89_btc_bool_sta_chg { 1420 u32 now: 1; 1421 u32 last: 1; 1422 u32 remain: 1; 1423 u32 srvd: 29; 1424 }; 1425 1426 struct rtw89_btc_u8_sta_chg { 1427 u8 now; 1428 u8 last; 1429 u8 remain; 1430 u8 rsvd; 1431 }; 1432 1433 struct rtw89_btc_wl_scan_info { 1434 u8 band[RTW89_PHY_MAX]; 1435 u8 phy_map; 1436 u8 rsvd; 1437 }; 1438 1439 struct rtw89_btc_wl_dbcc_info { 1440 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1441 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1442 u8 real_band[RTW89_PHY_MAX]; 1443 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1444 }; 1445 1446 struct rtw89_btc_wl_active_role { 1447 u8 connected: 1; 1448 u8 pid: 3; 1449 u8 phy: 1; 1450 u8 noa: 1; 1451 u8 band: 2; 1452 1453 u8 client_ps: 1; 1454 u8 bw: 7; 1455 1456 u8 role; 1457 u8 ch; 1458 1459 u16 tx_lvl; 1460 u16 rx_lvl; 1461 u16 tx_rate; 1462 u16 rx_rate; 1463 }; 1464 1465 struct rtw89_btc_wl_active_role_v1 { 1466 u8 connected: 1; 1467 u8 pid: 3; 1468 u8 phy: 1; 1469 u8 noa: 1; 1470 u8 band: 2; 1471 1472 u8 client_ps: 1; 1473 u8 bw: 7; 1474 1475 u8 role; 1476 u8 ch; 1477 1478 u16 tx_lvl; 1479 u16 rx_lvl; 1480 u16 tx_rate; 1481 u16 rx_rate; 1482 1483 u32 noa_duration; /* ms */ 1484 }; 1485 1486 struct rtw89_btc_wl_active_role_v2 { 1487 u8 connected: 1; 1488 u8 pid: 3; 1489 u8 phy: 1; 1490 u8 noa: 1; 1491 u8 band: 2; 1492 1493 u8 client_ps: 1; 1494 u8 bw: 7; 1495 1496 u8 role; 1497 u8 ch; 1498 1499 u32 noa_duration; /* ms */ 1500 }; 1501 1502 struct rtw89_btc_wl_role_info_bpos { 1503 u16 none: 1; 1504 u16 station: 1; 1505 u16 ap: 1; 1506 u16 vap: 1; 1507 u16 adhoc: 1; 1508 u16 adhoc_master: 1; 1509 u16 mesh: 1; 1510 u16 moniter: 1; 1511 u16 p2p_device: 1; 1512 u16 p2p_gc: 1; 1513 u16 p2p_go: 1; 1514 u16 nan: 1; 1515 }; 1516 1517 struct rtw89_btc_wl_scc_ctrl { 1518 u8 null_role1; 1519 u8 null_role2; 1520 u8 ebt_null; /* if tx null at EBT slot */ 1521 }; 1522 1523 union rtw89_btc_wl_role_info_map { 1524 u16 val; 1525 struct rtw89_btc_wl_role_info_bpos role; 1526 }; 1527 1528 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1529 u8 connect_cnt; 1530 u8 link_mode; 1531 union rtw89_btc_wl_role_info_map role_map; 1532 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1533 }; 1534 1535 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1536 u8 connect_cnt; 1537 u8 link_mode; 1538 union rtw89_btc_wl_role_info_map role_map; 1539 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1540 u32 mrole_type; /* btc_wl_mrole_type */ 1541 u32 mrole_noa_duration; /* ms */ 1542 1543 u32 dbcc_en: 1; 1544 u32 dbcc_chg: 1; 1545 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1546 u32 link_mode_chg: 1; 1547 u32 rsvd: 27; 1548 }; 1549 1550 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1551 u8 connect_cnt; 1552 u8 link_mode; 1553 union rtw89_btc_wl_role_info_map role_map; 1554 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1555 u32 mrole_type; /* btc_wl_mrole_type */ 1556 u32 mrole_noa_duration; /* ms */ 1557 1558 u32 dbcc_en: 1; 1559 u32 dbcc_chg: 1; 1560 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1561 u32 link_mode_chg: 1; 1562 u32 rsvd: 27; 1563 }; 1564 1565 struct rtw89_btc_wl_ver_info { 1566 u32 fw_coex; /* match with which coex_ver */ 1567 u32 fw; 1568 u32 mac; 1569 u32 bb; 1570 u32 rf; 1571 }; 1572 1573 struct rtw89_btc_wl_afh_info { 1574 u8 en; 1575 u8 ch; 1576 u8 bw; 1577 u8 rsvd; 1578 } __packed; 1579 1580 struct rtw89_btc_wl_rfk_info { 1581 u32 state: 2; 1582 u32 path_map: 4; 1583 u32 phy_map: 2; 1584 u32 band: 2; 1585 u32 type: 8; 1586 u32 rsvd: 14; 1587 }; 1588 1589 struct rtw89_btc_bt_smap { 1590 u32 connect: 1; 1591 u32 ble_connect: 1; 1592 u32 acl_busy: 1; 1593 u32 sco_busy: 1; 1594 u32 mesh_busy: 1; 1595 u32 inq_pag: 1; 1596 }; 1597 1598 union rtw89_btc_bt_state_map { 1599 u32 val; 1600 struct rtw89_btc_bt_smap map; 1601 }; 1602 1603 #define BTC_BT_RSSI_THMAX 4 1604 #define BTC_BT_AFH_GROUP 12 1605 #define BTC_BT_AFH_LE_GROUP 5 1606 1607 struct rtw89_btc_bt_link_info { 1608 struct rtw89_btc_u8_sta_chg profile_cnt; 1609 struct rtw89_btc_bool_sta_chg multi_link; 1610 struct rtw89_btc_bool_sta_chg relink; 1611 struct rtw89_btc_bt_hfp_desc hfp_desc; 1612 struct rtw89_btc_bt_hid_desc hid_desc; 1613 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1614 struct rtw89_btc_bt_pan_desc pan_desc; 1615 union rtw89_btc_bt_state_map status; 1616 1617 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1618 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1619 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1620 u8 afh_map[BTC_BT_AFH_GROUP]; 1621 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1622 1623 u32 role_sw: 1; 1624 u32 slave_role: 1; 1625 u32 afh_update: 1; 1626 u32 cqddr: 1; 1627 u32 rssi: 8; 1628 u32 tx_3m: 1; 1629 u32 rsvd: 19; 1630 }; 1631 1632 struct rtw89_btc_3rdcx_info { 1633 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1634 u8 hw_coex; 1635 u16 rsvd; 1636 }; 1637 1638 struct rtw89_btc_dm_emap { 1639 u32 init: 1; 1640 u32 pta_owner: 1; 1641 u32 wl_rfk_timeout: 1; 1642 u32 bt_rfk_timeout: 1; 1643 u32 wl_fw_hang: 1; 1644 u32 cycle_hang: 1; 1645 u32 w1_hang: 1; 1646 u32 b1_hang: 1; 1647 u32 tdma_no_sync: 1; 1648 u32 slot_no_sync: 1; 1649 u32 wl_slot_drift: 1; 1650 u32 bt_slot_drift: 1; 1651 u32 role_num_mismatch: 1; 1652 u32 null1_tx_late: 1; 1653 u32 bt_afh_conflict: 1; 1654 u32 bt_leafh_conflict: 1; 1655 u32 bt_slot_flood: 1; 1656 u32 wl_e2g_hang: 1; 1657 u32 wl_ver_mismatch: 1; 1658 u32 bt_ver_mismatch: 1; 1659 }; 1660 1661 union rtw89_btc_dm_error_map { 1662 u32 val; 1663 struct rtw89_btc_dm_emap map; 1664 }; 1665 1666 struct rtw89_btc_rf_para { 1667 u32 tx_pwr_freerun; 1668 u32 rx_gain_freerun; 1669 u32 tx_pwr_perpkt; 1670 u32 rx_gain_perpkt; 1671 }; 1672 1673 struct rtw89_btc_wl_nhm { 1674 u8 instant_wl_nhm_dbm; 1675 u8 instant_wl_nhm_per_mhz; 1676 u16 valid_record_times; 1677 s8 record_pwr[16]; 1678 u8 record_ratio[16]; 1679 s8 pwr; /* dbm_per_MHz */ 1680 u8 ratio; 1681 u8 current_status; 1682 u8 refresh; 1683 bool start_flag; 1684 s8 pwr_max; 1685 s8 pwr_min; 1686 }; 1687 1688 struct rtw89_btc_wl_info { 1689 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1690 struct rtw89_btc_wl_rfk_info rfk_info; 1691 struct rtw89_btc_wl_ver_info ver_info; 1692 struct rtw89_btc_wl_afh_info afh_info; 1693 struct rtw89_btc_wl_role_info role_info; 1694 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1695 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1696 struct rtw89_btc_wl_scan_info scan_info; 1697 struct rtw89_btc_wl_dbcc_info dbcc_info; 1698 struct rtw89_btc_rf_para rf_para; 1699 struct rtw89_btc_wl_nhm nhm; 1700 union rtw89_btc_wl_state_map status; 1701 1702 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1703 u8 rssi_level; 1704 u8 cn_report; 1705 1706 bool scbd_change; 1707 u32 scbd; 1708 }; 1709 1710 struct rtw89_btc_module { 1711 struct rtw89_btc_ant_info ant; 1712 u8 rfe_type; 1713 u8 cv; 1714 1715 u8 bt_solo: 1; 1716 u8 bt_pos: 1; 1717 u8 switch_type: 1; 1718 u8 wa_type: 3; 1719 1720 u8 kt_ver_adie; 1721 }; 1722 1723 #define RTW89_BTC_DM_MAXSTEP 30 1724 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1725 1726 struct rtw89_btc_dm_step { 1727 u16 step[RTW89_BTC_DM_MAXSTEP]; 1728 u8 step_pos; 1729 bool step_ov; 1730 }; 1731 1732 struct rtw89_btc_init_info { 1733 struct rtw89_btc_module module; 1734 u8 wl_guard_ch; 1735 1736 u8 wl_only: 1; 1737 u8 wl_init_ok: 1; 1738 u8 dbcc_en: 1; 1739 u8 cx_other: 1; 1740 u8 bt_only: 1; 1741 1742 u16 rsvd; 1743 }; 1744 1745 struct rtw89_btc_wl_tx_limit_para { 1746 u16 enable; 1747 u32 tx_time; /* unit: us */ 1748 u16 tx_retry; 1749 }; 1750 1751 enum rtw89_btc_bt_scan_type { 1752 BTC_SCAN_INQ = 0, 1753 BTC_SCAN_PAGE, 1754 BTC_SCAN_BLE, 1755 BTC_SCAN_INIT, 1756 BTC_SCAN_TV, 1757 BTC_SCAN_ADV, 1758 BTC_SCAN_MAX1, 1759 }; 1760 1761 enum rtw89_btc_ble_scan_type { 1762 CXSCAN_BG = 0, 1763 CXSCAN_INIT, 1764 CXSCAN_LE, 1765 CXSCAN_MAX 1766 }; 1767 1768 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1769 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1770 1771 struct rtw89_btc_bt_scan_info_v1 { 1772 __le16 win; 1773 __le16 intvl; 1774 __le32 flags; 1775 } __packed; 1776 1777 struct rtw89_btc_bt_scan_info_v2 { 1778 __le16 win; 1779 __le16 intvl; 1780 } __packed; 1781 1782 struct rtw89_btc_fbtc_btscan_v1 { 1783 u8 fver; /* btc_ver::fcxbtscan */ 1784 u8 rsvd; 1785 __le16 rsvd2; 1786 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1787 } __packed; 1788 1789 struct rtw89_btc_fbtc_btscan_v2 { 1790 u8 fver; /* btc_ver::fcxbtscan */ 1791 u8 type; 1792 __le16 rsvd2; 1793 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1794 } __packed; 1795 1796 union rtw89_btc_fbtc_btscan { 1797 struct rtw89_btc_fbtc_btscan_v1 v1; 1798 struct rtw89_btc_fbtc_btscan_v2 v2; 1799 }; 1800 1801 struct rtw89_btc_bt_info { 1802 struct rtw89_btc_bt_link_info link_info; 1803 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1804 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1805 struct rtw89_btc_bt_ver_info ver_info; 1806 struct rtw89_btc_bool_sta_chg enable; 1807 struct rtw89_btc_bool_sta_chg inq_pag; 1808 struct rtw89_btc_rf_para rf_para; 1809 union rtw89_btc_bt_rfk_info_map rfk_info; 1810 1811 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1812 1813 u32 scbd; 1814 u32 feature; 1815 1816 u32 mbx_avl: 1; 1817 u32 whql_test: 1; 1818 u32 igno_wl: 1; 1819 u32 reinit: 1; 1820 u32 ble_scan_en: 1; 1821 u32 btg_type: 1; 1822 u32 inq: 1; 1823 u32 pag: 1; 1824 u32 run_patch_code: 1; 1825 u32 hi_lna_rx: 1; 1826 u32 scan_rx_low_pri: 1; 1827 u32 scan_info_update: 1; 1828 u32 rsvd: 20; 1829 }; 1830 1831 struct rtw89_btc_cx { 1832 struct rtw89_btc_wl_info wl; 1833 struct rtw89_btc_bt_info bt; 1834 struct rtw89_btc_3rdcx_info other; 1835 u32 state_map; 1836 u32 cnt_bt[BTC_BCNT_NUM]; 1837 u32 cnt_wl[BTC_WCNT_NUM]; 1838 }; 1839 1840 struct rtw89_btc_fbtc_tdma { 1841 u8 type; /* btc_ver::fcxtdma */ 1842 u8 rxflctrl; 1843 u8 txpause; 1844 u8 wtgle_n; 1845 u8 leak_n; 1846 u8 ext_ctrl; 1847 u8 rxflctrl_role; 1848 u8 option_ctrl; 1849 } __packed; 1850 1851 struct rtw89_btc_fbtc_tdma_v3 { 1852 u8 fver; /* btc_ver::fcxtdma */ 1853 u8 rsvd; 1854 __le16 rsvd1; 1855 struct rtw89_btc_fbtc_tdma tdma; 1856 } __packed; 1857 1858 union rtw89_btc_fbtc_tdma_le32 { 1859 struct rtw89_btc_fbtc_tdma v1; 1860 struct rtw89_btc_fbtc_tdma_v3 v3; 1861 }; 1862 1863 #define CXMREG_MAX 30 1864 #define CXMREG_MAX_V2 20 1865 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1866 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1867 1868 enum rtw89_btc_bt_sta_counter { 1869 BTC_BCNT_RFK_REQ = 0, 1870 BTC_BCNT_RFK_GO = 1, 1871 BTC_BCNT_RFK_REJECT = 2, 1872 BTC_BCNT_RFK_FAIL = 3, 1873 BTC_BCNT_RFK_TIMEOUT = 4, 1874 BTC_BCNT_HI_TX = 5, 1875 BTC_BCNT_HI_RX = 6, 1876 BTC_BCNT_LO_TX = 7, 1877 BTC_BCNT_LO_RX = 8, 1878 BTC_BCNT_POLLUTED = 9, 1879 BTC_BCNT_STA_MAX 1880 }; 1881 1882 enum rtw89_btc_bt_sta_counter_v105 { 1883 BTC_BCNT_RFK_REQ_V105 = 0, 1884 BTC_BCNT_HI_TX_V105 = 1, 1885 BTC_BCNT_HI_RX_V105 = 2, 1886 BTC_BCNT_LO_TX_V105 = 3, 1887 BTC_BCNT_LO_RX_V105 = 4, 1888 BTC_BCNT_POLLUTED_V105 = 5, 1889 BTC_BCNT_STA_MAX_V105 1890 }; 1891 1892 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1893 u16 fver; /* btc_ver::fcxbtcrpt */ 1894 u16 rpt_cnt; /* tmr counters */ 1895 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1896 u32 wl_fw_cx_offload; 1897 u32 wl_fw_ver; 1898 u32 rpt_enable; 1899 u32 rpt_para; /* ms */ 1900 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1901 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1902 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1903 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1904 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1905 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1906 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1907 u32 c2h_cnt; /* fw send c2h counter */ 1908 u32 h2c_cnt; /* fw recv h2c counter */ 1909 } __packed; 1910 1911 struct rtw89_btc_fbtc_rpt_ctrl_info { 1912 __le32 cnt; /* fw report counter */ 1913 __le32 en; /* report map */ 1914 __le32 para; /* not used */ 1915 1916 __le32 cnt_c2h; /* fw send c2h counter */ 1917 __le32 cnt_h2c; /* fw recv h2c counter */ 1918 __le32 len_c2h; /* The total length of the last C2H */ 1919 1920 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1921 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1922 } __packed; 1923 1924 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1925 __le32 cx_ver; /* match which driver's coex version */ 1926 __le32 fw_ver; 1927 __le32 en; /* report map */ 1928 1929 __le16 cnt; /* fw report counter */ 1930 __le16 cnt_c2h; /* fw send c2h counter */ 1931 __le16 cnt_h2c; /* fw recv h2c counter */ 1932 __le16 len_c2h; /* The total length of the last C2H */ 1933 1934 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1935 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1936 } __packed; 1937 1938 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1939 __le32 cx_ver; /* match which driver's coex version */ 1940 __le32 cx_offload; 1941 __le32 fw_ver; 1942 } __packed; 1943 1944 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1945 __le32 cnt_empty; /* a2dp empty count */ 1946 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1947 __le32 cnt_tx; 1948 __le32 cnt_ack; 1949 __le32 cnt_nack; 1950 } __packed; 1951 1952 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1953 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1954 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1955 __le32 cnt_recv; /* fw recv mailbox counter */ 1956 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1957 } __packed; 1958 1959 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1960 u8 fver; 1961 u8 rsvd; 1962 __le16 rsvd1; 1963 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1964 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1965 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1966 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1967 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1968 } __packed; 1969 1970 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1971 u8 fver; 1972 u8 rsvd; 1973 __le16 rsvd1; 1974 1975 u8 gnt_val[RTW89_PHY_MAX][4]; 1976 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1977 1978 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1979 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1980 } __packed; 1981 1982 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1983 u8 fver; 1984 u8 rsvd; 1985 __le16 rsvd1; 1986 1987 u8 gnt_val[RTW89_PHY_MAX][4]; 1988 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1989 1990 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1991 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1992 } __packed; 1993 1994 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1995 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 1996 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 1997 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 1998 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 1999 }; 2000 2001 enum rtw89_fbtc_ext_ctrl_type { 2002 CXECTL_OFF = 0x0, /* tdma off */ 2003 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2004 CXECTL_EXT = 0x2, 2005 CXECTL_MAX 2006 }; 2007 2008 union rtw89_btc_fbtc_rxflct { 2009 u8 val; 2010 u8 type: 3; 2011 u8 tgln_n: 5; 2012 }; 2013 2014 enum rtw89_btc_cxst_state { 2015 CXST_OFF = 0x0, 2016 CXST_B2W = 0x1, 2017 CXST_W1 = 0x2, 2018 CXST_W2 = 0x3, 2019 CXST_W2B = 0x4, 2020 CXST_B1 = 0x5, 2021 CXST_B2 = 0x6, 2022 CXST_B3 = 0x7, 2023 CXST_B4 = 0x8, 2024 CXST_LK = 0x9, 2025 CXST_BLK = 0xa, 2026 CXST_E2G = 0xb, 2027 CXST_E5G = 0xc, 2028 CXST_EBT = 0xd, 2029 CXST_ENULL = 0xe, 2030 CXST_WLK = 0xf, 2031 CXST_W1FDD = 0x10, 2032 CXST_B1FDD = 0x11, 2033 CXST_MAX = 0x12, 2034 }; 2035 2036 enum rtw89_btc_cxevnt { 2037 CXEVNT_TDMA_ENTRY = 0x0, 2038 CXEVNT_WL_TMR, 2039 CXEVNT_B1_TMR, 2040 CXEVNT_B2_TMR, 2041 CXEVNT_B3_TMR, 2042 CXEVNT_B4_TMR, 2043 CXEVNT_W2B_TMR, 2044 CXEVNT_B2W_TMR, 2045 CXEVNT_BCN_EARLY, 2046 CXEVNT_A2DP_EMPTY, 2047 CXEVNT_LK_END, 2048 CXEVNT_RX_ISR, 2049 CXEVNT_RX_FC0, 2050 CXEVNT_RX_FC1, 2051 CXEVNT_BT_RELINK, 2052 CXEVNT_BT_RETRY, 2053 CXEVNT_E2G, 2054 CXEVNT_E5G, 2055 CXEVNT_EBT, 2056 CXEVNT_ENULL, 2057 CXEVNT_DRV_WLK, 2058 CXEVNT_BCN_OK, 2059 CXEVNT_BT_CHANGE, 2060 CXEVNT_EBT_EXTEND, 2061 CXEVNT_E2G_NULL1, 2062 CXEVNT_B1FDD_TMR, 2063 CXEVNT_MAX 2064 }; 2065 2066 enum { 2067 CXBCN_ALL = 0x0, 2068 CXBCN_ALL_OK, 2069 CXBCN_BT_SLOT, 2070 CXBCN_BT_OK, 2071 CXBCN_MAX 2072 }; 2073 2074 enum btc_slot_type { 2075 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2076 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2077 CXSTYPE_NUM, 2078 }; 2079 2080 enum { /* TIME */ 2081 CXT_BT = 0x0, 2082 CXT_WL = 0x1, 2083 CXT_MAX 2084 }; 2085 2086 enum { /* TIME-A2DP */ 2087 CXT_FLCTRL_OFF = 0x0, 2088 CXT_FLCTRL_ON = 0x1, 2089 CXT_FLCTRL_MAX 2090 }; 2091 2092 enum { /* STEP TYPE */ 2093 CXSTEP_NONE = 0x0, 2094 CXSTEP_EVNT = 0x1, 2095 CXSTEP_SLOT = 0x2, 2096 CXSTEP_MAX, 2097 }; 2098 2099 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2100 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2101 RPT_BT_AFH_SEQ_LE = 0x20 2102 }; 2103 2104 #define BTC_DBG_MAX1 32 2105 struct rtw89_btc_fbtc_gpio_dbg { 2106 u8 fver; /* btc_ver::fcxgpiodbg */ 2107 u8 rsvd; 2108 u16 rsvd2; 2109 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2110 u32 pre_state; /* the debug signal is 1 or 0 */ 2111 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2112 } __packed; 2113 2114 struct rtw89_btc_fbtc_mreg_val_v1 { 2115 u8 fver; /* btc_ver::fcxmreg */ 2116 u8 reg_num; 2117 __le16 rsvd; 2118 __le32 mreg_val[CXMREG_MAX]; 2119 } __packed; 2120 2121 struct rtw89_btc_fbtc_mreg_val_v2 { 2122 u8 fver; /* btc_ver::fcxmreg */ 2123 u8 reg_num; 2124 __le16 rsvd; 2125 __le32 mreg_val[CXMREG_MAX_V2]; 2126 } __packed; 2127 2128 union rtw89_btc_fbtc_mreg_val { 2129 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2130 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2131 }; 2132 2133 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2134 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2135 .offset = cpu_to_le32(__offset), } 2136 2137 struct rtw89_btc_fbtc_mreg { 2138 __le16 type; 2139 __le16 bytes; 2140 __le32 offset; 2141 } __packed; 2142 2143 struct rtw89_btc_fbtc_slot { 2144 __le16 dur; 2145 __le32 cxtbl; 2146 __le16 cxtype; 2147 } __packed; 2148 2149 struct rtw89_btc_fbtc_slots { 2150 u8 fver; /* btc_ver::fcxslots */ 2151 u8 tbl_num; 2152 __le16 rsvd; 2153 __le32 update_map; 2154 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2155 } __packed; 2156 2157 struct rtw89_btc_fbtc_step { 2158 u8 type; 2159 u8 val; 2160 __le16 difft; 2161 } __packed; 2162 2163 struct rtw89_btc_fbtc_steps_v2 { 2164 u8 fver; /* btc_ver::fcxstep */ 2165 u8 rsvd; 2166 __le16 cnt; 2167 __le16 pos_old; 2168 __le16 pos_new; 2169 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2170 } __packed; 2171 2172 struct rtw89_btc_fbtc_steps_v3 { 2173 u8 fver; 2174 u8 en; 2175 __le16 rsvd; 2176 __le32 cnt; 2177 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2178 } __packed; 2179 2180 union rtw89_btc_fbtc_steps_info { 2181 struct rtw89_btc_fbtc_steps_v2 v2; 2182 struct rtw89_btc_fbtc_steps_v3 v3; 2183 }; 2184 2185 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2186 u8 fver; /* btc_ver::fcxcysta */ 2187 u8 rsvd; 2188 __le16 cycles; /* total cycle number */ 2189 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2190 __le16 a2dpept; /* a2dp empty cnt */ 2191 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2192 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2193 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2194 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2195 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2196 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2197 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2198 __le16 tmax_a2dpept; /* max a2dp empty time */ 2199 __le16 tavg_lk; /* avg leak-slot time */ 2200 __le16 tmax_lk; /* max leak-slot time */ 2201 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2202 __le32 bcn_cnt[CXBCN_MAX]; 2203 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2204 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2205 __le32 skip_cnt; 2206 __le32 exception; 2207 __le32 except_cnt; 2208 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2209 } __packed; 2210 2211 struct rtw89_btc_fbtc_fdd_try_info { 2212 __le16 cycles[CXT_FLCTRL_MAX]; 2213 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2214 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2215 } __packed; 2216 2217 struct rtw89_btc_fbtc_cycle_time_info { 2218 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2219 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2220 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2221 } __packed; 2222 2223 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2224 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2225 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2226 } __packed; 2227 2228 struct rtw89_btc_fbtc_a2dp_trx_stat { 2229 u8 empty_cnt; 2230 u8 retry_cnt; 2231 u8 tx_rate; 2232 u8 tx_cnt; 2233 u8 ack_cnt; 2234 u8 nack_cnt; 2235 u8 rsvd1; 2236 u8 rsvd2; 2237 } __packed; 2238 2239 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2240 u8 empty_cnt; 2241 u8 retry_cnt; 2242 u8 tx_rate; 2243 u8 tx_cnt; 2244 u8 ack_cnt; 2245 u8 nack_cnt; 2246 u8 no_empty_cnt; 2247 u8 rsvd; 2248 } __packed; 2249 2250 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2251 __le16 cnt; /* a2dp empty cnt */ 2252 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2253 __le16 tavg; /* avg a2dp empty time */ 2254 __le16 tmax; /* max a2dp empty time */ 2255 } __packed; 2256 2257 struct rtw89_btc_fbtc_cycle_leak_info { 2258 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2259 __le16 tavg; /* avg leak-slot time */ 2260 __le16 tmax; /* max leak-slot time */ 2261 } __packed; 2262 2263 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2264 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2265 2266 struct rtw89_btc_fbtc_cycle_fddt_info { 2267 __le16 train_cycle; 2268 __le16 tp; 2269 2270 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2271 s8 bt_tx_power; /* decrease Tx power (dB) */ 2272 s8 bt_rx_gain; /* LNA constrain level */ 2273 u8 no_empty_cnt; 2274 2275 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2276 u8 cn; /* condition_num */ 2277 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2278 u8 train_result; /* refer to enum btc_fddt_check_map */ 2279 } __packed; 2280 2281 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2282 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2283 2284 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2285 __le16 train_cycle; 2286 __le16 tp; 2287 2288 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2289 s8 bt_tx_power; /* decrease Tx power (dB) */ 2290 s8 bt_rx_gain; /* LNA constrain level */ 2291 u8 no_empty_cnt; 2292 2293 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2294 u8 cn; /* condition_num */ 2295 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2296 u8 train_result; /* refer to enum btc_fddt_check_map */ 2297 } __packed; 2298 2299 struct rtw89_btc_fbtc_fddt_cell_status { 2300 s8 wl_tx_pwr; 2301 s8 bt_tx_pwr; 2302 s8 bt_rx_gain; 2303 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2304 } __packed; 2305 2306 struct rtw89_btc_fbtc_fddt_cell_status_v5 { 2307 s8 wl_tx_pwr; 2308 s8 bt_tx_pwr; 2309 s8 bt_rx_gain; 2310 } __packed; 2311 2312 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2313 u8 fver; 2314 u8 rsvd; 2315 __le16 cycles; /* total cycle number */ 2316 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2317 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2318 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2319 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2320 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2321 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2322 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2323 __le32 bcn_cnt[CXBCN_MAX]; 2324 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2325 __le32 skip_cnt; 2326 __le32 except_cnt; 2327 __le32 except_map; 2328 } __packed; 2329 2330 #define FDD_TRAIN_WL_DIRECTION 2 2331 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2332 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2333 2334 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2335 u8 fver; 2336 u8 rsvd; 2337 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2338 u8 except_cnt; 2339 2340 __le16 skip_cnt; 2341 __le16 cycles; /* total cycle number */ 2342 2343 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2344 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2345 __le16 bcn_cnt[CXBCN_MAX]; 2346 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2347 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2348 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2349 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2350 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2351 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2352 [FDD_TRAIN_WL_RSSI_LEVEL] 2353 [FDD_TRAIN_BT_RSSI_LEVEL]; 2354 __le32 except_map; 2355 } __packed; 2356 2357 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2358 u8 fver; 2359 u8 rsvd; 2360 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2361 u8 except_cnt; 2362 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2363 2364 __le16 skip_cnt; 2365 __le16 cycles; /* total cycle number */ 2366 2367 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2368 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2369 __le16 bcn_cnt[CXBCN_MAX]; 2370 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2371 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2372 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2373 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2374 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2375 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] 2376 [FDD_TRAIN_WL_RSSI_LEVEL] 2377 [FDD_TRAIN_BT_RSSI_LEVEL]; 2378 __le32 except_map; 2379 } __packed; 2380 2381 union rtw89_btc_fbtc_cysta_info { 2382 struct rtw89_btc_fbtc_cysta_v2 v2; 2383 struct rtw89_btc_fbtc_cysta_v3 v3; 2384 struct rtw89_btc_fbtc_cysta_v4 v4; 2385 struct rtw89_btc_fbtc_cysta_v5 v5; 2386 }; 2387 2388 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2389 u8 fver; /* btc_ver::fcxnullsta */ 2390 u8 rsvd; 2391 __le16 rsvd2; 2392 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2393 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2394 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2395 } __packed; 2396 2397 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2398 u8 fver; /* btc_ver::fcxnullsta */ 2399 u8 rsvd; 2400 __le16 rsvd2; 2401 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2402 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2403 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2404 } __packed; 2405 2406 union rtw89_btc_fbtc_cynullsta_info { 2407 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2408 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2409 }; 2410 2411 struct rtw89_btc_fbtc_btver { 2412 u8 fver; /* btc_ver::fcxbtver */ 2413 u8 rsvd; 2414 __le16 rsvd2; 2415 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2416 __le32 fw_ver; 2417 __le32 feature; 2418 } __packed; 2419 2420 struct rtw89_btc_fbtc_btafh { 2421 u8 fver; /* btc_ver::fcxbtafh */ 2422 u8 rsvd; 2423 __le16 rsvd2; 2424 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2425 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2426 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2427 } __packed; 2428 2429 struct rtw89_btc_fbtc_btafh_v2 { 2430 u8 fver; /* btc_ver::fcxbtafh */ 2431 u8 rsvd; 2432 u8 rsvd2; 2433 u8 map_type; 2434 u8 afh_l[4]; 2435 u8 afh_m[4]; 2436 u8 afh_h[4]; 2437 u8 afh_le_a[4]; 2438 u8 afh_le_b[4]; 2439 } __packed; 2440 2441 struct rtw89_btc_fbtc_btdevinfo { 2442 u8 fver; /* btc_ver::fcxbtdevinfo */ 2443 u8 rsvd; 2444 __le16 vendor_id; 2445 __le32 dev_name; /* only 24 bits valid */ 2446 __le32 flush_time; 2447 } __packed; 2448 2449 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2450 struct rtw89_btc_rf_trx_para { 2451 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2452 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2453 u8 bt_tx_power; /* decrease Tx power (dB) */ 2454 u8 bt_rx_gain; /* LNA constrain level */ 2455 }; 2456 2457 struct rtw89_btc_trx_info { 2458 u8 tx_lvl; 2459 u8 rx_lvl; 2460 u8 wl_rssi; 2461 u8 bt_rssi; 2462 2463 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2464 s8 rx_gain; /* rx gain table index (TBD.) */ 2465 s8 bt_tx_power; /* decrease Tx power (dB) */ 2466 s8 bt_rx_gain; /* LNA constrain level */ 2467 2468 u8 cn; /* condition_num */ 2469 s8 nhm; 2470 u8 bt_profile; 2471 u8 rsvd2; 2472 2473 u16 tx_rate; 2474 u16 rx_rate; 2475 2476 u32 tx_tp; 2477 u32 rx_tp; 2478 u32 rx_err_ratio; 2479 }; 2480 2481 struct rtw89_btc_dm { 2482 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2483 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2484 struct rtw89_btc_fbtc_tdma tdma; 2485 struct rtw89_btc_fbtc_tdma tdma_now; 2486 struct rtw89_mac_ax_coex_gnt gnt; 2487 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2488 struct rtw89_btc_rf_trx_para rf_trx_para; 2489 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2490 struct rtw89_btc_dm_step dm_step; 2491 struct rtw89_btc_wl_scc_ctrl wl_scc; 2492 struct rtw89_btc_trx_info trx_info; 2493 union rtw89_btc_dm_error_map error; 2494 u32 cnt_dm[BTC_DCNT_NUM]; 2495 u32 cnt_notify[BTC_NCNT_NUM]; 2496 2497 u32 update_slot_map; 2498 u32 set_ant_path; 2499 2500 u32 wl_only: 1; 2501 u32 wl_fw_cx_offload: 1; 2502 u32 freerun: 1; 2503 u32 fddt_train: 1; 2504 u32 wl_ps_ctrl: 2; 2505 u32 wl_mimo_ps: 1; 2506 u32 leak_ap: 1; 2507 u32 noisy_level: 3; 2508 u32 coex_info_map: 8; 2509 u32 bt_only: 1; 2510 u32 wl_btg_rx: 1; 2511 u32 trx_para_level: 8; 2512 u32 wl_stb_chg: 1; 2513 u32 pta_owner: 1; 2514 u32 tdma_instant_excute: 1; 2515 2516 u16 slot_dur[CXST_MAX]; 2517 2518 u8 run_reason; 2519 u8 run_action; 2520 2521 u8 wl_lna2: 1; 2522 }; 2523 2524 struct rtw89_btc_ctrl { 2525 u32 manual: 1; 2526 u32 igno_bt: 1; 2527 u32 always_freerun: 1; 2528 u32 trace_step: 16; 2529 u32 rsvd: 12; 2530 }; 2531 2532 struct rtw89_btc_dbg { 2533 /* cmd "rb" */ 2534 bool rb_done; 2535 u32 rb_val; 2536 }; 2537 2538 enum rtw89_btc_btf_fw_event { 2539 BTF_EVNT_RPT = 0, 2540 BTF_EVNT_BT_INFO = 1, 2541 BTF_EVNT_BT_SCBD = 2, 2542 BTF_EVNT_BT_REG = 3, 2543 BTF_EVNT_CX_RUNINFO = 4, 2544 BTF_EVNT_BT_PSD = 5, 2545 BTF_EVNT_BUF_OVERFLOW, 2546 BTF_EVNT_C2H_LOOPBACK, 2547 BTF_EVNT_MAX, 2548 }; 2549 2550 enum btf_fw_event_report { 2551 BTC_RPT_TYPE_CTRL = 0x0, 2552 BTC_RPT_TYPE_TDMA, 2553 BTC_RPT_TYPE_SLOT, 2554 BTC_RPT_TYPE_CYSTA, 2555 BTC_RPT_TYPE_STEP, 2556 BTC_RPT_TYPE_NULLSTA, 2557 BTC_RPT_TYPE_MREG, 2558 BTC_RPT_TYPE_GPIO_DBG, 2559 BTC_RPT_TYPE_BT_VER, 2560 BTC_RPT_TYPE_BT_SCAN, 2561 BTC_RPT_TYPE_BT_AFH, 2562 BTC_RPT_TYPE_BT_DEVICE, 2563 BTC_RPT_TYPE_TEST, 2564 BTC_RPT_TYPE_MAX = 31 2565 }; 2566 2567 enum rtw_btc_btf_reg_type { 2568 REG_MAC = 0x0, 2569 REG_BB = 0x1, 2570 REG_RF = 0x2, 2571 REG_BT_RF = 0x3, 2572 REG_BT_MODEM = 0x4, 2573 REG_BT_BLUEWIZE = 0x5, 2574 REG_BT_VENDOR = 0x6, 2575 REG_BT_LE = 0x7, 2576 REG_MAX_TYPE, 2577 }; 2578 2579 struct rtw89_btc_rpt_cmn_info { 2580 u32 rx_cnt; 2581 u32 rx_len; 2582 u32 req_len; /* expected rsp len */ 2583 u8 req_fver; /* expected rsp fver */ 2584 u8 rsp_fver; /* fver from fw */ 2585 u8 valid; 2586 } __packed; 2587 2588 union rtw89_btc_fbtc_btafh_info { 2589 struct rtw89_btc_fbtc_btafh v1; 2590 struct rtw89_btc_fbtc_btafh_v2 v2; 2591 }; 2592 2593 struct rtw89_btc_report_ctrl_state { 2594 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2595 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2596 }; 2597 2598 struct rtw89_btc_rpt_fbtc_tdma { 2599 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2600 union rtw89_btc_fbtc_tdma_le32 finfo; 2601 }; 2602 2603 struct rtw89_btc_rpt_fbtc_slots { 2604 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2605 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2606 }; 2607 2608 struct rtw89_btc_rpt_fbtc_cysta { 2609 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2610 union rtw89_btc_fbtc_cysta_info finfo; 2611 }; 2612 2613 struct rtw89_btc_rpt_fbtc_step { 2614 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2615 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2616 }; 2617 2618 struct rtw89_btc_rpt_fbtc_nullsta { 2619 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2620 union rtw89_btc_fbtc_cynullsta_info finfo; 2621 }; 2622 2623 struct rtw89_btc_rpt_fbtc_mreg { 2624 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2625 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2626 }; 2627 2628 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2629 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2630 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2631 }; 2632 2633 struct rtw89_btc_rpt_fbtc_btver { 2634 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2635 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2636 }; 2637 2638 struct rtw89_btc_rpt_fbtc_btscan { 2639 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2640 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2641 }; 2642 2643 struct rtw89_btc_rpt_fbtc_btafh { 2644 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2645 union rtw89_btc_fbtc_btafh_info finfo; 2646 }; 2647 2648 struct rtw89_btc_rpt_fbtc_btdev { 2649 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2650 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2651 }; 2652 2653 enum rtw89_btc_btfre_type { 2654 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2655 BTFRE_UNDEF_TYPE, 2656 BTFRE_EXCEPTION, 2657 BTFRE_MAX, 2658 }; 2659 2660 struct rtw89_btc_btf_fwinfo { 2661 u32 cnt_c2h; 2662 u32 cnt_h2c; 2663 u32 cnt_h2c_fail; 2664 u32 event[BTF_EVNT_MAX]; 2665 2666 u32 err[BTFRE_MAX]; 2667 u32 len_mismch; 2668 u32 fver_mismch; 2669 u32 rpt_en_map; 2670 2671 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2672 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2673 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2674 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2675 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2676 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2677 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2678 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2679 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2680 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2681 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2682 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2683 }; 2684 2685 struct rtw89_btc_ver { 2686 enum rtw89_core_chip_id chip_id; 2687 u32 fw_ver_code; 2688 2689 u8 fcxbtcrpt; 2690 u8 fcxtdma; 2691 u8 fcxslots; 2692 u8 fcxcysta; 2693 u8 fcxstep; 2694 u8 fcxnullsta; 2695 u8 fcxmreg; 2696 u8 fcxgpiodbg; 2697 u8 fcxbtver; 2698 u8 fcxbtscan; 2699 u8 fcxbtafh; 2700 u8 fcxbtdevinfo; 2701 u8 fwlrole; 2702 u8 frptmap; 2703 u8 fcxctrl; 2704 2705 u16 info_buf; 2706 u8 max_role_num; 2707 }; 2708 2709 #define RTW89_BTC_POLICY_MAXLEN 512 2710 2711 struct rtw89_btc { 2712 const struct rtw89_btc_ver *ver; 2713 2714 struct rtw89_btc_cx cx; 2715 struct rtw89_btc_dm dm; 2716 struct rtw89_btc_ctrl ctrl; 2717 struct rtw89_btc_module mdinfo; 2718 struct rtw89_btc_btf_fwinfo fwinfo; 2719 struct rtw89_btc_dbg dbg; 2720 2721 struct work_struct eapol_notify_work; 2722 struct work_struct arp_notify_work; 2723 struct work_struct dhcp_notify_work; 2724 struct work_struct icmp_notify_work; 2725 2726 u32 bt_req_len; 2727 2728 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2729 u16 policy_len; 2730 u16 policy_type; 2731 bool bt_req_en; 2732 bool update_policy_force; 2733 bool lps; 2734 }; 2735 2736 enum rtw89_btc_hmsg { 2737 RTW89_BTC_HMSG_TMR_EN = 0x0, 2738 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 2739 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 2740 RTW89_BTC_HMSG_FW_EV = 0x3, 2741 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 2742 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 2743 2744 NUM_OF_RTW89_BTC_HMSG, 2745 }; 2746 2747 enum rtw89_ra_mode { 2748 RTW89_RA_MODE_CCK = BIT(0), 2749 RTW89_RA_MODE_OFDM = BIT(1), 2750 RTW89_RA_MODE_HT = BIT(2), 2751 RTW89_RA_MODE_VHT = BIT(3), 2752 RTW89_RA_MODE_HE = BIT(4), 2753 RTW89_RA_MODE_EHT = BIT(5), 2754 }; 2755 2756 enum rtw89_ra_report_mode { 2757 RTW89_RA_RPT_MODE_LEGACY, 2758 RTW89_RA_RPT_MODE_HT, 2759 RTW89_RA_RPT_MODE_VHT, 2760 RTW89_RA_RPT_MODE_HE, 2761 RTW89_RA_RPT_MODE_EHT, 2762 }; 2763 2764 enum rtw89_dig_noisy_level { 2765 RTW89_DIG_NOISY_LEVEL0 = -1, 2766 RTW89_DIG_NOISY_LEVEL1 = 0, 2767 RTW89_DIG_NOISY_LEVEL2 = 1, 2768 RTW89_DIG_NOISY_LEVEL3 = 2, 2769 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2770 }; 2771 2772 enum rtw89_gi_ltf { 2773 RTW89_GILTF_LGI_4XHE32 = 0, 2774 RTW89_GILTF_SGI_4XHE08 = 1, 2775 RTW89_GILTF_2XHE16 = 2, 2776 RTW89_GILTF_2XHE08 = 3, 2777 RTW89_GILTF_1XHE16 = 4, 2778 RTW89_GILTF_1XHE08 = 5, 2779 RTW89_GILTF_MAX 2780 }; 2781 2782 enum rtw89_rx_frame_type { 2783 RTW89_RX_TYPE_MGNT = 0, 2784 RTW89_RX_TYPE_CTRL = 1, 2785 RTW89_RX_TYPE_DATA = 2, 2786 RTW89_RX_TYPE_RSVD = 3, 2787 }; 2788 2789 enum rtw89_efuse_block { 2790 RTW89_EFUSE_BLOCK_SYS = 0, 2791 RTW89_EFUSE_BLOCK_RF = 1, 2792 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 2793 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 2794 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 2795 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 2796 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 2797 RTW89_EFUSE_BLOCK_ADIE = 7, 2798 2799 RTW89_EFUSE_BLOCK_NUM, 2800 RTW89_EFUSE_BLOCK_IGNORE, 2801 }; 2802 2803 struct rtw89_ra_info { 2804 u8 is_dis_ra:1; 2805 /* Bit0 : CCK 2806 * Bit1 : OFDM 2807 * Bit2 : HT 2808 * Bit3 : VHT 2809 * Bit4 : HE 2810 * Bit5 : EHT 2811 */ 2812 u8 mode_ctrl:6; 2813 u8 bw_cap:3; /* enum rtw89_bandwidth */ 2814 u8 macid; 2815 u8 dcm_cap:1; 2816 u8 er_cap:1; 2817 u8 init_rate_lv:2; 2818 u8 upd_all:1; 2819 u8 en_sgi:1; 2820 u8 ldpc_cap:1; 2821 u8 stbc_cap:1; 2822 u8 ss_num:3; 2823 u8 giltf:3; 2824 u8 upd_bw_nss_mask:1; 2825 u8 upd_mask:1; 2826 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2827 /* BFee CSI */ 2828 u8 band_num; 2829 u8 ra_csi_rate_en:1; 2830 u8 fixed_csi_rate_en:1; 2831 u8 cr_tbl_sel:1; 2832 u8 fix_giltf_en:1; 2833 u8 fix_giltf:3; 2834 u8 rsvd2:1; 2835 u8 csi_mcs_ss_idx; 2836 u8 csi_mode:2; 2837 u8 csi_gi_ltf:3; 2838 u8 csi_bw:3; 2839 }; 2840 2841 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2842 #define RTW89_PPDU_MAC_INFO_SIZE 8 2843 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2844 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 2845 2846 #define RTW89_MAX_RX_AGG_NUM 64 2847 #define RTW89_MAX_TX_AGG_NUM 128 2848 2849 struct rtw89_ampdu_params { 2850 u16 agg_num; 2851 bool amsdu; 2852 }; 2853 2854 struct rtw89_ra_report { 2855 struct rate_info txrate; 2856 u32 bit_rate; 2857 u16 hw_rate; 2858 bool might_fallback_legacy; 2859 }; 2860 2861 DECLARE_EWMA(rssi, 10, 16); 2862 DECLARE_EWMA(evm, 10, 16); 2863 DECLARE_EWMA(snr, 10, 16); 2864 2865 struct rtw89_ba_cam_entry { 2866 struct list_head list; 2867 u8 tid; 2868 }; 2869 2870 #define RTW89_MAX_ADDR_CAM_NUM 128 2871 #define RTW89_MAX_BSSID_CAM_NUM 20 2872 #define RTW89_MAX_SEC_CAM_NUM 128 2873 #define RTW89_MAX_BA_CAM_NUM 8 2874 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2875 2876 struct rtw89_addr_cam_entry { 2877 u8 addr_cam_idx; 2878 u8 offset; 2879 u8 len; 2880 u8 valid : 1; 2881 u8 addr_mask : 6; 2882 u8 wapi : 1; 2883 u8 mask_sel : 2; 2884 u8 bssid_cam_idx: 6; 2885 2886 u8 sec_ent_mode; 2887 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2888 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2889 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2890 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2891 }; 2892 2893 struct rtw89_bssid_cam_entry { 2894 u8 bssid[ETH_ALEN]; 2895 u8 phy_idx; 2896 u8 bssid_cam_idx; 2897 u8 offset; 2898 u8 len; 2899 u8 valid : 1; 2900 u8 num; 2901 }; 2902 2903 struct rtw89_sec_cam_entry { 2904 u8 sec_cam_idx; 2905 u8 offset; 2906 u8 len; 2907 u8 type : 4; 2908 u8 ext_key : 1; 2909 u8 spp_mode : 1; 2910 /* 256 bits */ 2911 u8 key[32]; 2912 }; 2913 2914 struct rtw89_sta { 2915 u8 mac_id; 2916 bool disassoc; 2917 bool er_cap; 2918 struct rtw89_dev *rtwdev; 2919 struct rtw89_vif *rtwvif; 2920 struct rtw89_ra_info ra; 2921 struct rtw89_ra_report ra_report; 2922 int max_agg_wait; 2923 u8 prev_rssi; 2924 struct ewma_rssi avg_rssi; 2925 struct ewma_rssi rssi[RF_PATH_MAX]; 2926 struct ewma_snr avg_snr; 2927 struct ewma_evm evm_min[RF_PATH_MAX]; 2928 struct ewma_evm evm_max[RF_PATH_MAX]; 2929 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2930 struct ieee80211_rx_status rx_status; 2931 u16 rx_hw_rate; 2932 __le32 htc_template; 2933 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2934 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2935 struct list_head ba_cam_list; 2936 struct sk_buff_head roc_queue; 2937 2938 bool use_cfg_mask; 2939 struct cfg80211_bitrate_mask mask; 2940 2941 bool cctl_tx_time; 2942 u32 ampdu_max_time:4; 2943 bool cctl_tx_retry_limit; 2944 u32 data_tx_cnt_lmt:6; 2945 }; 2946 2947 struct rtw89_efuse { 2948 bool valid; 2949 bool power_k_valid; 2950 u8 xtal_cap; 2951 u8 addr[ETH_ALEN]; 2952 u8 rfe_type; 2953 char country_code[2]; 2954 }; 2955 2956 struct rtw89_phy_rate_pattern { 2957 u64 ra_mask; 2958 u16 rate; 2959 u8 ra_mode; 2960 bool enable; 2961 }; 2962 2963 struct rtw89_tx_wait_info { 2964 struct rcu_head rcu_head; 2965 struct completion completion; 2966 bool tx_done; 2967 }; 2968 2969 struct rtw89_tx_skb_data { 2970 struct rtw89_tx_wait_info __rcu *wait; 2971 u8 hci_priv[]; 2972 }; 2973 2974 #define RTW89_ROC_IDLE_TIMEOUT 500 2975 #define RTW89_ROC_TX_TIMEOUT 30 2976 enum rtw89_roc_state { 2977 RTW89_ROC_IDLE, 2978 RTW89_ROC_NORMAL, 2979 RTW89_ROC_MGMT, 2980 }; 2981 2982 struct rtw89_roc { 2983 struct ieee80211_channel chan; 2984 struct delayed_work roc_work; 2985 enum ieee80211_roc_type type; 2986 enum rtw89_roc_state state; 2987 int duration; 2988 }; 2989 2990 #define RTW89_P2P_MAX_NOA_NUM 2 2991 2992 struct rtw89_p2p_ie_head { 2993 u8 eid; 2994 u8 ie_len; 2995 u8 oui[3]; 2996 u8 oui_type; 2997 } __packed; 2998 2999 struct rtw89_noa_attr_head { 3000 u8 attr_type; 3001 __le16 attr_len; 3002 u8 index; 3003 u8 oppps_ctwindow; 3004 } __packed; 3005 3006 struct rtw89_p2p_noa_ie { 3007 struct rtw89_p2p_ie_head p2p_head; 3008 struct rtw89_noa_attr_head noa_head; 3009 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3010 } __packed; 3011 3012 struct rtw89_p2p_noa_setter { 3013 struct rtw89_p2p_noa_ie ie; 3014 u8 noa_count; 3015 u8 noa_index; 3016 }; 3017 3018 struct rtw89_vif { 3019 struct list_head list; 3020 struct rtw89_dev *rtwdev; 3021 struct rtw89_roc roc; 3022 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3023 enum rtw89_sub_entity_idx sub_entity_idx; 3024 enum rtw89_reg_6ghz_power reg_6ghz_power; 3025 3026 u8 mac_id; 3027 u8 port; 3028 u8 mac_addr[ETH_ALEN]; 3029 u8 bssid[ETH_ALEN]; 3030 u8 phy_idx; 3031 u8 mac_idx; 3032 u8 net_type; 3033 u8 wifi_role; 3034 u8 self_role; 3035 u8 wmm; 3036 u8 bcn_hit_cond; 3037 u8 hit_rule; 3038 u8 last_noa_nr; 3039 bool offchan; 3040 bool trigger; 3041 bool lsig_txop; 3042 u8 tgt_ind; 3043 u8 frm_tgt_ind; 3044 bool wowlan_pattern; 3045 bool wowlan_uc; 3046 bool wowlan_magic; 3047 bool is_hesta; 3048 bool last_a_ctrl; 3049 bool dyn_tb_bedge_en; 3050 bool pre_pwr_diff_en; 3051 bool pwr_diff_en; 3052 u8 def_tri_idx; 3053 u32 tdls_peer; 3054 struct work_struct update_beacon_work; 3055 struct rtw89_addr_cam_entry addr_cam; 3056 struct rtw89_bssid_cam_entry bssid_cam; 3057 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3058 struct rtw89_traffic_stats stats; 3059 struct rtw89_phy_rate_pattern rate_pattern; 3060 struct cfg80211_scan_request *scan_req; 3061 struct ieee80211_scan_ies *scan_ies; 3062 struct list_head general_pkt_list; 3063 struct rtw89_p2p_noa_setter p2p_noa; 3064 }; 3065 3066 enum rtw89_lv1_rcvy_step { 3067 RTW89_LV1_RCVY_STEP_1, 3068 RTW89_LV1_RCVY_STEP_2, 3069 }; 3070 3071 struct rtw89_hci_ops { 3072 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3073 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3074 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3075 void (*reset)(struct rtw89_dev *rtwdev); 3076 int (*start)(struct rtw89_dev *rtwdev); 3077 void (*stop)(struct rtw89_dev *rtwdev); 3078 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3079 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3080 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3081 3082 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3083 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3084 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3085 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3086 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3087 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3088 3089 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3090 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3091 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3092 int (*deinit)(struct rtw89_dev *rtwdev); 3093 3094 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3095 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3096 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3097 int (*napi_poll)(struct napi_struct *napi, int budget); 3098 3099 /* Deal with locks inside recovery_start and recovery_complete callbacks 3100 * by hci instance, and handle things which need to consider under SER. 3101 * e.g. turn on/off interrupts except for the one for halt notification. 3102 */ 3103 void (*recovery_start)(struct rtw89_dev *rtwdev); 3104 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3105 3106 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3107 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3108 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3109 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 3110 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3111 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3112 void (*disable_intr)(struct rtw89_dev *rtwdev); 3113 void (*enable_intr)(struct rtw89_dev *rtwdev); 3114 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3115 }; 3116 3117 struct rtw89_hci_info { 3118 const struct rtw89_hci_ops *ops; 3119 enum rtw89_hci_type type; 3120 u32 rpwm_addr; 3121 u32 cpwm_addr; 3122 bool paused; 3123 }; 3124 3125 struct rtw89_chip_ops { 3126 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3127 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3128 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3129 void (*bb_reset)(struct rtw89_dev *rtwdev, 3130 enum rtw89_phy_idx phy_idx); 3131 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3132 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3133 u32 addr, u32 mask); 3134 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3135 u32 addr, u32 mask, u32 data); 3136 void (*set_channel)(struct rtw89_dev *rtwdev, 3137 const struct rtw89_chan *chan, 3138 enum rtw89_mac_idx mac_idx, 3139 enum rtw89_phy_idx phy_idx); 3140 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3141 struct rtw89_channel_help_params *p, 3142 const struct rtw89_chan *chan, 3143 enum rtw89_mac_idx mac_idx, 3144 enum rtw89_phy_idx phy_idx); 3145 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3146 enum rtw89_efuse_block block); 3147 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3148 void (*fem_setup)(struct rtw89_dev *rtwdev); 3149 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3150 void (*rfk_init)(struct rtw89_dev *rtwdev); 3151 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3152 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3153 enum rtw89_phy_idx phy_idx); 3154 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3155 void (*rfk_track)(struct rtw89_dev *rtwdev); 3156 void (*power_trim)(struct rtw89_dev *rtwdev); 3157 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3158 const struct rtw89_chan *chan, 3159 enum rtw89_phy_idx phy_idx); 3160 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3161 enum rtw89_phy_idx phy_idx); 3162 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3163 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3164 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3165 enum rtw89_phy_idx phy_idx); 3166 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3167 struct rtw89_rx_phy_ppdu *phy_ppdu, 3168 struct ieee80211_rx_status *status); 3169 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3170 enum rtw89_phy_idx phy_idx); 3171 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3172 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3173 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3174 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3175 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3176 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3177 struct rtw89_rx_desc_info *desc_info, 3178 u8 *data, u32 data_offset); 3179 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3180 struct rtw89_tx_desc_info *desc_info, 3181 void *txdesc); 3182 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3183 struct rtw89_tx_desc_info *desc_info, 3184 void *txdesc); 3185 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3186 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3187 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3188 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3189 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3190 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3191 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3192 struct rtw89_vif *rtwvif, 3193 struct rtw89_sta *rtwsta); 3194 3195 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3196 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3197 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3198 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3199 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3200 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3201 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3202 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3203 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3204 }; 3205 3206 enum rtw89_dma_ch { 3207 RTW89_DMA_ACH0 = 0, 3208 RTW89_DMA_ACH1 = 1, 3209 RTW89_DMA_ACH2 = 2, 3210 RTW89_DMA_ACH3 = 3, 3211 RTW89_DMA_ACH4 = 4, 3212 RTW89_DMA_ACH5 = 5, 3213 RTW89_DMA_ACH6 = 6, 3214 RTW89_DMA_ACH7 = 7, 3215 RTW89_DMA_B0MG = 8, 3216 RTW89_DMA_B0HI = 9, 3217 RTW89_DMA_B1MG = 10, 3218 RTW89_DMA_B1HI = 11, 3219 RTW89_DMA_H2C = 12, 3220 RTW89_DMA_CH_NUM = 13 3221 }; 3222 3223 enum rtw89_qta_mode { 3224 RTW89_QTA_SCC, 3225 RTW89_QTA_DLFW, 3226 RTW89_QTA_WOW, 3227 3228 /* keep last */ 3229 RTW89_QTA_INVALID, 3230 }; 3231 3232 struct rtw89_hfc_ch_cfg { 3233 u16 min; 3234 u16 max; 3235 #define grp_0 0 3236 #define grp_1 1 3237 #define grp_num 2 3238 u8 grp; 3239 }; 3240 3241 struct rtw89_hfc_ch_info { 3242 u16 aval; 3243 u16 used; 3244 }; 3245 3246 struct rtw89_hfc_pub_cfg { 3247 u16 grp0; 3248 u16 grp1; 3249 u16 pub_max; 3250 u16 wp_thrd; 3251 }; 3252 3253 struct rtw89_hfc_pub_info { 3254 u16 g0_used; 3255 u16 g1_used; 3256 u16 g0_aval; 3257 u16 g1_aval; 3258 u16 pub_aval; 3259 u16 wp_aval; 3260 }; 3261 3262 struct rtw89_hfc_prec_cfg { 3263 u16 ch011_prec; 3264 u16 h2c_prec; 3265 u16 wp_ch07_prec; 3266 u16 wp_ch811_prec; 3267 u8 ch011_full_cond; 3268 u8 h2c_full_cond; 3269 u8 wp_ch07_full_cond; 3270 u8 wp_ch811_full_cond; 3271 }; 3272 3273 struct rtw89_hfc_param { 3274 bool en; 3275 bool h2c_en; 3276 u8 mode; 3277 const struct rtw89_hfc_ch_cfg *ch_cfg; 3278 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3279 struct rtw89_hfc_pub_cfg pub_cfg; 3280 struct rtw89_hfc_pub_info pub_info; 3281 struct rtw89_hfc_prec_cfg prec_cfg; 3282 }; 3283 3284 struct rtw89_hfc_param_ini { 3285 const struct rtw89_hfc_ch_cfg *ch_cfg; 3286 const struct rtw89_hfc_pub_cfg *pub_cfg; 3287 const struct rtw89_hfc_prec_cfg *prec_cfg; 3288 u8 mode; 3289 }; 3290 3291 struct rtw89_dle_size { 3292 u16 pge_size; 3293 u16 lnk_pge_num; 3294 u16 unlnk_pge_num; 3295 }; 3296 3297 struct rtw89_wde_quota { 3298 u16 hif; 3299 u16 wcpu; 3300 u16 pkt_in; 3301 u16 cpu_io; 3302 }; 3303 3304 struct rtw89_ple_quota { 3305 u16 cma0_tx; 3306 u16 cma1_tx; 3307 u16 c2h; 3308 u16 h2c; 3309 u16 wcpu; 3310 u16 mpdu_proc; 3311 u16 cma0_dma; 3312 u16 cma1_dma; 3313 u16 bb_rpt; 3314 u16 wd_rel; 3315 u16 cpu_io; 3316 u16 tx_rpt; 3317 }; 3318 3319 struct rtw89_dle_mem { 3320 enum rtw89_qta_mode mode; 3321 const struct rtw89_dle_size *wde_size; 3322 const struct rtw89_dle_size *ple_size; 3323 const struct rtw89_wde_quota *wde_min_qt; 3324 const struct rtw89_wde_quota *wde_max_qt; 3325 const struct rtw89_ple_quota *ple_min_qt; 3326 const struct rtw89_ple_quota *ple_max_qt; 3327 }; 3328 3329 struct rtw89_reg_def { 3330 u32 addr; 3331 u32 mask; 3332 }; 3333 3334 struct rtw89_reg2_def { 3335 u32 addr; 3336 u32 data; 3337 }; 3338 3339 struct rtw89_reg3_def { 3340 u32 addr; 3341 u32 mask; 3342 u32 data; 3343 }; 3344 3345 struct rtw89_reg5_def { 3346 u8 flag; /* recognized by parsers */ 3347 u8 path; 3348 u32 addr; 3349 u32 mask; 3350 u32 data; 3351 }; 3352 3353 struct rtw89_phy_table { 3354 const struct rtw89_reg2_def *regs; 3355 u32 n_regs; 3356 enum rtw89_rf_path rf_path; 3357 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3358 enum rtw89_rf_path rf_path, void *data); 3359 }; 3360 3361 struct rtw89_txpwr_table { 3362 const void *data; 3363 u32 size; 3364 void (*load)(struct rtw89_dev *rtwdev, 3365 const struct rtw89_txpwr_table *tbl); 3366 }; 3367 3368 struct rtw89_txpwr_rule_2ghz { 3369 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3370 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3371 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3372 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3373 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3374 }; 3375 3376 struct rtw89_txpwr_rule_5ghz { 3377 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3378 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3379 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3380 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3381 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3382 }; 3383 3384 struct rtw89_txpwr_rule_6ghz { 3385 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3386 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3387 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3388 [RTW89_6G_CH_NUM]; 3389 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3390 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3391 [RTW89_6G_CH_NUM]; 3392 }; 3393 3394 struct rtw89_tx_shape { 3395 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3396 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3397 }; 3398 3399 struct rtw89_rfe_parms { 3400 const struct rtw89_txpwr_table *byr_tbl; 3401 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3402 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3403 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3404 struct rtw89_tx_shape tx_shape; 3405 }; 3406 3407 struct rtw89_rfe_parms_conf { 3408 const struct rtw89_rfe_parms *rfe_parms; 3409 u8 rfe_type; 3410 }; 3411 3412 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3413 3414 struct rtw89_txpwr_conf { 3415 u8 rfe_type; 3416 u8 ent_sz; 3417 u32 num_ents; 3418 const void *data; 3419 }; 3420 3421 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3422 3423 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3424 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3425 memcpy(&(entry), cursor, \ 3426 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3427 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3428 (cursor) += (conf)->ent_sz, \ 3429 memcpy(&(entry), cursor, \ 3430 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3431 3432 struct rtw89_txpwr_byrate_data { 3433 struct rtw89_txpwr_conf conf; 3434 struct rtw89_txpwr_table tbl; 3435 }; 3436 3437 struct rtw89_txpwr_lmt_2ghz_data { 3438 struct rtw89_txpwr_conf conf; 3439 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3440 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3441 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3442 }; 3443 3444 struct rtw89_txpwr_lmt_5ghz_data { 3445 struct rtw89_txpwr_conf conf; 3446 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3447 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3448 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3449 }; 3450 3451 struct rtw89_txpwr_lmt_6ghz_data { 3452 struct rtw89_txpwr_conf conf; 3453 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3454 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3455 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3456 [RTW89_6G_CH_NUM]; 3457 }; 3458 3459 struct rtw89_txpwr_lmt_ru_2ghz_data { 3460 struct rtw89_txpwr_conf conf; 3461 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3462 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3463 }; 3464 3465 struct rtw89_txpwr_lmt_ru_5ghz_data { 3466 struct rtw89_txpwr_conf conf; 3467 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3468 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3469 }; 3470 3471 struct rtw89_txpwr_lmt_ru_6ghz_data { 3472 struct rtw89_txpwr_conf conf; 3473 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3474 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3475 [RTW89_6G_CH_NUM]; 3476 }; 3477 3478 struct rtw89_tx_shape_lmt_data { 3479 struct rtw89_txpwr_conf conf; 3480 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3481 }; 3482 3483 struct rtw89_tx_shape_lmt_ru_data { 3484 struct rtw89_txpwr_conf conf; 3485 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3486 }; 3487 3488 struct rtw89_rfe_data { 3489 struct rtw89_txpwr_byrate_data byrate; 3490 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3491 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3492 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3493 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3494 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3495 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3496 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3497 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3498 struct rtw89_rfe_parms rfe_parms; 3499 }; 3500 3501 struct rtw89_page_regs { 3502 u32 hci_fc_ctrl; 3503 u32 ch_page_ctrl; 3504 u32 ach_page_ctrl; 3505 u32 ach_page_info; 3506 u32 pub_page_info3; 3507 u32 pub_page_ctrl1; 3508 u32 pub_page_ctrl2; 3509 u32 pub_page_info1; 3510 u32 pub_page_info2; 3511 u32 wp_page_ctrl1; 3512 u32 wp_page_ctrl2; 3513 u32 wp_page_info1; 3514 }; 3515 3516 struct rtw89_imr_info { 3517 u32 wdrls_imr_set; 3518 u32 wsec_imr_reg; 3519 u32 wsec_imr_set; 3520 u32 mpdu_tx_imr_set; 3521 u32 mpdu_rx_imr_set; 3522 u32 sta_sch_imr_set; 3523 u32 txpktctl_imr_b0_reg; 3524 u32 txpktctl_imr_b0_clr; 3525 u32 txpktctl_imr_b0_set; 3526 u32 txpktctl_imr_b1_reg; 3527 u32 txpktctl_imr_b1_clr; 3528 u32 txpktctl_imr_b1_set; 3529 u32 wde_imr_clr; 3530 u32 wde_imr_set; 3531 u32 ple_imr_clr; 3532 u32 ple_imr_set; 3533 u32 host_disp_imr_clr; 3534 u32 host_disp_imr_set; 3535 u32 cpu_disp_imr_clr; 3536 u32 cpu_disp_imr_set; 3537 u32 other_disp_imr_clr; 3538 u32 other_disp_imr_set; 3539 u32 bbrpt_com_err_imr_reg; 3540 u32 bbrpt_chinfo_err_imr_reg; 3541 u32 bbrpt_err_imr_set; 3542 u32 bbrpt_dfs_err_imr_reg; 3543 u32 ptcl_imr_clr; 3544 u32 ptcl_imr_set; 3545 u32 cdma_imr_0_reg; 3546 u32 cdma_imr_0_clr; 3547 u32 cdma_imr_0_set; 3548 u32 cdma_imr_1_reg; 3549 u32 cdma_imr_1_clr; 3550 u32 cdma_imr_1_set; 3551 u32 phy_intf_imr_reg; 3552 u32 phy_intf_imr_clr; 3553 u32 phy_intf_imr_set; 3554 u32 rmac_imr_reg; 3555 u32 rmac_imr_clr; 3556 u32 rmac_imr_set; 3557 u32 tmac_imr_reg; 3558 u32 tmac_imr_clr; 3559 u32 tmac_imr_set; 3560 }; 3561 3562 struct rtw89_xtal_info { 3563 u32 xcap_reg; 3564 u32 sc_xo_mask; 3565 u32 sc_xi_mask; 3566 }; 3567 3568 struct rtw89_rrsr_cfgs { 3569 struct rtw89_reg3_def ref_rate; 3570 struct rtw89_reg3_def rsc; 3571 }; 3572 3573 struct rtw89_dig_regs { 3574 u32 seg0_pd_reg; 3575 u32 pd_lower_bound_mask; 3576 u32 pd_spatial_reuse_en; 3577 u32 bmode_pd_reg; 3578 u32 bmode_cca_rssi_limit_en; 3579 u32 bmode_pd_lower_bound_reg; 3580 u32 bmode_rssi_nocca_low_th_mask; 3581 struct rtw89_reg_def p0_lna_init; 3582 struct rtw89_reg_def p1_lna_init; 3583 struct rtw89_reg_def p0_tia_init; 3584 struct rtw89_reg_def p1_tia_init; 3585 struct rtw89_reg_def p0_rxb_init; 3586 struct rtw89_reg_def p1_rxb_init; 3587 struct rtw89_reg_def p0_p20_pagcugc_en; 3588 struct rtw89_reg_def p0_s20_pagcugc_en; 3589 struct rtw89_reg_def p1_p20_pagcugc_en; 3590 struct rtw89_reg_def p1_s20_pagcugc_en; 3591 }; 3592 3593 struct rtw89_phy_ul_tb_info { 3594 bool dyn_tb_tri_en; 3595 u8 def_if_bandedge; 3596 }; 3597 3598 struct rtw89_antdiv_stats { 3599 struct ewma_rssi cck_rssi_avg; 3600 struct ewma_rssi ofdm_rssi_avg; 3601 struct ewma_rssi non_legacy_rssi_avg; 3602 u16 pkt_cnt_cck; 3603 u16 pkt_cnt_ofdm; 3604 u16 pkt_cnt_non_legacy; 3605 u32 evm; 3606 }; 3607 3608 struct rtw89_antdiv_info { 3609 struct rtw89_antdiv_stats target_stats; 3610 struct rtw89_antdiv_stats main_stats; 3611 struct rtw89_antdiv_stats aux_stats; 3612 u8 training_count; 3613 u8 rssi_pre; 3614 bool get_stats; 3615 }; 3616 3617 enum rtw89_chanctx_state { 3618 RTW89_CHANCTX_STATE_MCC_START, 3619 RTW89_CHANCTX_STATE_MCC_STOP, 3620 }; 3621 3622 enum rtw89_chanctx_callbacks { 3623 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 3624 RTW89_CHANCTX_CALLBACK_RFK, 3625 3626 NUM_OF_RTW89_CHANCTX_CALLBACKS, 3627 }; 3628 3629 struct rtw89_chanctx_listener { 3630 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 3631 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 3632 }; 3633 3634 struct rtw89_chip_info { 3635 enum rtw89_core_chip_id chip_id; 3636 enum rtw89_chip_gen chip_gen; 3637 const struct rtw89_chip_ops *ops; 3638 const struct rtw89_mac_gen_def *mac_def; 3639 const struct rtw89_phy_gen_def *phy_def; 3640 const char *fw_basename; 3641 u8 fw_format_max; 3642 bool try_ce_fw; 3643 u8 bbmcu_nr; 3644 u32 needed_fw_elms; 3645 u32 fifo_size; 3646 bool small_fifo_size; 3647 u32 dle_scc_rsvd_size; 3648 u16 max_amsdu_limit; 3649 bool dis_2g_40m_ul_ofdma; 3650 u32 rsvd_ple_ofst; 3651 const struct rtw89_hfc_param_ini *hfc_param_ini; 3652 const struct rtw89_dle_mem *dle_mem; 3653 u8 wde_qempty_acq_num; 3654 u8 wde_qempty_mgq_sel; 3655 u32 rf_base_addr[2]; 3656 u8 support_chanctx_num; 3657 u8 support_bands; 3658 bool support_bw160; 3659 bool support_unii4; 3660 bool ul_tb_waveform_ctrl; 3661 bool ul_tb_pwr_diff; 3662 bool hw_sec_hdr; 3663 u8 rf_path_num; 3664 u8 tx_nss; 3665 u8 rx_nss; 3666 u8 acam_num; 3667 u8 bcam_num; 3668 u8 scam_num; 3669 u8 bacam_num; 3670 u8 bacam_dynamic_num; 3671 enum rtw89_bacam_ver bacam_ver; 3672 u8 ppdu_max_usr; 3673 3674 u8 sec_ctrl_efuse_size; 3675 u32 physical_efuse_size; 3676 u32 logical_efuse_size; 3677 u32 limit_efuse_size; 3678 u32 dav_phy_efuse_size; 3679 u32 dav_log_efuse_size; 3680 u32 phycap_addr; 3681 u32 phycap_size; 3682 const struct rtw89_efuse_block_cfg *efuse_blocks; 3683 3684 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3685 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3686 const struct rtw89_phy_table *bb_table; 3687 const struct rtw89_phy_table *bb_gain_table; 3688 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3689 const struct rtw89_phy_table *nctl_table; 3690 const struct rtw89_rfk_tbl *nctl_post_table; 3691 const struct rtw89_phy_dig_gain_table *dig_table; 3692 const struct rtw89_dig_regs *dig_regs; 3693 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3694 3695 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3696 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3697 const struct rtw89_rfe_parms *dflt_parms; 3698 const struct rtw89_chanctx_listener *chanctx_listener; 3699 3700 u8 txpwr_factor_rf; 3701 u8 txpwr_factor_mac; 3702 3703 u32 para_ver; 3704 u32 wlcx_desired; 3705 u8 btcx_desired; 3706 u8 scbd; 3707 u8 mailbox; 3708 3709 u8 afh_guard_ch; 3710 const u8 *wl_rssi_thres; 3711 const u8 *bt_rssi_thres; 3712 u8 rssi_tol; 3713 3714 u8 mon_reg_num; 3715 const struct rtw89_btc_fbtc_mreg *mon_reg; 3716 u8 rf_para_ulink_num; 3717 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3718 u8 rf_para_dlink_num; 3719 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3720 u8 ps_mode_supported; 3721 u8 low_power_hci_modes; 3722 3723 u32 h2c_cctl_func_id; 3724 u32 hci_func_en_addr; 3725 u32 h2c_desc_size; 3726 u32 txwd_body_size; 3727 u32 txwd_info_size; 3728 u32 h2c_ctrl_reg; 3729 const u32 *h2c_regs; 3730 struct rtw89_reg_def h2c_counter_reg; 3731 u32 c2h_ctrl_reg; 3732 const u32 *c2h_regs; 3733 struct rtw89_reg_def c2h_counter_reg; 3734 const struct rtw89_page_regs *page_regs; 3735 bool cfo_src_fd; 3736 bool cfo_hw_comp; 3737 const struct rtw89_reg_def *dcfo_comp; 3738 u8 dcfo_comp_sft; 3739 const struct rtw89_imr_info *imr_info; 3740 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3741 struct rtw89_reg_def bss_clr_vld; 3742 u32 bss_clr_map_reg; 3743 u32 dma_ch_mask; 3744 u32 edcca_lvl_reg; 3745 const struct wiphy_wowlan_support *wowlan_stub; 3746 const struct rtw89_xtal_info *xtal_info; 3747 }; 3748 3749 union rtw89_bus_info { 3750 const struct rtw89_pci_info *pci; 3751 }; 3752 3753 struct rtw89_driver_info { 3754 const struct rtw89_chip_info *chip; 3755 union rtw89_bus_info bus; 3756 }; 3757 3758 enum rtw89_hcifc_mode { 3759 RTW89_HCIFC_POH = 0, 3760 RTW89_HCIFC_STF = 1, 3761 RTW89_HCIFC_SDIO = 2, 3762 3763 /* keep last */ 3764 RTW89_HCIFC_MODE_INVALID, 3765 }; 3766 3767 struct rtw89_dle_info { 3768 enum rtw89_qta_mode qta_mode; 3769 u16 ple_pg_size; 3770 u16 c0_rx_qta; 3771 u16 c1_rx_qta; 3772 }; 3773 3774 enum rtw89_host_rpr_mode { 3775 RTW89_RPR_MODE_POH = 0, 3776 RTW89_RPR_MODE_STF 3777 }; 3778 3779 #define RTW89_COMPLETION_BUF_SIZE 24 3780 #define RTW89_WAIT_COND_IDLE UINT_MAX 3781 3782 struct rtw89_completion_data { 3783 bool err; 3784 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3785 }; 3786 3787 struct rtw89_wait_info { 3788 atomic_t cond; 3789 struct completion completion; 3790 struct rtw89_completion_data data; 3791 }; 3792 3793 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3794 3795 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3796 { 3797 init_completion(&wait->completion); 3798 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3799 } 3800 3801 struct rtw89_mac_info { 3802 struct rtw89_dle_info dle_info; 3803 struct rtw89_hfc_param hfc_param; 3804 enum rtw89_qta_mode qta_mode; 3805 u8 rpwm_seq_num; 3806 u8 cpwm_seq_num; 3807 3808 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 3809 struct rtw89_wait_info fw_ofld_wait; 3810 }; 3811 3812 enum rtw89_fwdl_check_type { 3813 RTW89_FWDL_CHECK_FREERTOS_DONE, 3814 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 3815 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 3816 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 3817 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 3818 }; 3819 3820 enum rtw89_fw_type { 3821 RTW89_FW_NORMAL = 1, 3822 RTW89_FW_WOWLAN = 3, 3823 RTW89_FW_NORMAL_CE = 5, 3824 RTW89_FW_BBMCU0 = 64, 3825 RTW89_FW_BBMCU1 = 65, 3826 RTW89_FW_LOGFMT = 255, 3827 }; 3828 3829 enum rtw89_fw_feature { 3830 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3831 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3832 RTW89_FW_FEATURE_TX_WAKE, 3833 RTW89_FW_FEATURE_CRASH_TRIGGER, 3834 RTW89_FW_FEATURE_NO_PACKET_DROP, 3835 RTW89_FW_FEATURE_NO_DEEP_PS, 3836 RTW89_FW_FEATURE_NO_LPS_PG, 3837 RTW89_FW_FEATURE_BEACON_FILTER, 3838 }; 3839 3840 struct rtw89_fw_suit { 3841 enum rtw89_fw_type type; 3842 const u8 *data; 3843 u32 size; 3844 u8 major_ver; 3845 u8 minor_ver; 3846 u8 sub_ver; 3847 u8 sub_idex; 3848 u16 build_year; 3849 u16 build_mon; 3850 u16 build_date; 3851 u16 build_hour; 3852 u16 build_min; 3853 u8 cmd_ver; 3854 u8 hdr_ver; 3855 u32 commitid; 3856 }; 3857 3858 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3859 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3860 #define RTW89_FW_SUIT_VER_CODE(s) \ 3861 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3862 3863 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3864 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3865 (mfw_hdr)->ver.minor, \ 3866 (mfw_hdr)->ver.sub, \ 3867 (mfw_hdr)->ver.idx) 3868 3869 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3870 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 3871 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 3872 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 3873 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 3874 3875 struct rtw89_fw_req_info { 3876 const struct firmware *firmware; 3877 struct completion completion; 3878 }; 3879 3880 struct rtw89_fw_log { 3881 struct rtw89_fw_suit suit; 3882 bool enable; 3883 u32 last_fmt_id; 3884 u32 fmt_count; 3885 const __le32 *fmt_ids; 3886 const char *(*fmts)[]; 3887 }; 3888 3889 struct rtw89_fw_elm_info { 3890 struct rtw89_phy_table *bb_tbl; 3891 struct rtw89_phy_table *bb_gain; 3892 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 3893 struct rtw89_phy_table *rf_nctl; 3894 }; 3895 3896 struct rtw89_fw_info { 3897 struct rtw89_fw_req_info req; 3898 int fw_format; 3899 u8 h2c_seq; 3900 u8 rec_seq; 3901 u8 h2c_counter; 3902 u8 c2h_counter; 3903 struct rtw89_fw_suit normal; 3904 struct rtw89_fw_suit wowlan; 3905 struct rtw89_fw_suit bbmcu0; 3906 struct rtw89_fw_suit bbmcu1; 3907 struct rtw89_fw_log log; 3908 u32 feature_map; 3909 struct rtw89_fw_elm_info elm_info; 3910 }; 3911 3912 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3913 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3914 3915 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3916 ((_fw)->feature_map |= BIT(_fw_feature)) 3917 3918 struct rtw89_cam_info { 3919 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3920 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3921 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3922 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3923 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3924 }; 3925 3926 enum rtw89_sar_sources { 3927 RTW89_SAR_SOURCE_NONE, 3928 RTW89_SAR_SOURCE_COMMON, 3929 3930 RTW89_SAR_SOURCE_NR, 3931 }; 3932 3933 enum rtw89_sar_subband { 3934 RTW89_SAR_2GHZ_SUBBAND, 3935 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3936 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 3937 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 3938 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 3939 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 3940 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 3941 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 3942 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 3943 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 3944 3945 RTW89_SAR_SUBBAND_NR, 3946 }; 3947 3948 struct rtw89_sar_cfg_common { 3949 bool set[RTW89_SAR_SUBBAND_NR]; 3950 s32 cfg[RTW89_SAR_SUBBAND_NR]; 3951 }; 3952 3953 struct rtw89_sar_info { 3954 /* used to decide how to acces SAR cfg union */ 3955 enum rtw89_sar_sources src; 3956 3957 /* reserved for different knids of SAR cfg struct. 3958 * supposed that a single cfg struct cannot handle various SAR sources. 3959 */ 3960 union { 3961 struct rtw89_sar_cfg_common cfg_common; 3962 }; 3963 }; 3964 3965 enum rtw89_tas_state { 3966 RTW89_TAS_STATE_DPR_OFF, 3967 RTW89_TAS_STATE_DPR_ON, 3968 RTW89_TAS_STATE_DPR_FORBID, 3969 }; 3970 3971 #define RTW89_TAS_MAX_WINDOW 50 3972 struct rtw89_tas_info { 3973 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 3974 s32 total_txpwr; 3975 u8 cur_idx; 3976 s8 dpr_gap; 3977 s8 delta; 3978 enum rtw89_tas_state state; 3979 bool enable; 3980 }; 3981 3982 struct rtw89_chanctx_cfg { 3983 enum rtw89_sub_entity_idx idx; 3984 }; 3985 3986 enum rtw89_chanctx_changes { 3987 RTW89_CHANCTX_REMOTE_STA_CHANGE, 3988 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 3989 RTW89_CHANCTX_P2P_PS_CHANGE, 3990 RTW89_CHANCTX_BT_SLOT_CHANGE, 3991 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 3992 3993 NUM_OF_RTW89_CHANCTX_CHANGES, 3994 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 3995 }; 3996 3997 enum rtw89_entity_mode { 3998 RTW89_ENTITY_MODE_SCC, 3999 RTW89_ENTITY_MODE_MCC_PREPARE, 4000 RTW89_ENTITY_MODE_MCC, 4001 4002 NUM_OF_RTW89_ENTITY_MODE, 4003 RTW89_ENTITY_MODE_INVALID = NUM_OF_RTW89_ENTITY_MODE, 4004 }; 4005 4006 struct rtw89_sub_entity { 4007 struct cfg80211_chan_def chandef; 4008 struct rtw89_chan chan; 4009 struct rtw89_chan_rcd rcd; 4010 struct rtw89_chanctx_cfg *cfg; 4011 }; 4012 4013 struct rtw89_hal { 4014 u32 rx_fltr; 4015 u8 cv; 4016 u8 acv; 4017 u32 antenna_tx; 4018 u32 antenna_rx; 4019 u8 tx_nss; 4020 u8 rx_nss; 4021 bool tx_path_diversity; 4022 bool ant_diversity; 4023 bool ant_diversity_fixed; 4024 bool support_cckpd; 4025 bool support_igi; 4026 atomic_t roc_entity_idx; 4027 4028 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4029 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4030 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4031 struct cfg80211_chan_def roc_chandef; 4032 4033 bool entity_active; 4034 bool entity_pause; 4035 enum rtw89_entity_mode entity_mode; 4036 4037 u32 edcca_bak; 4038 }; 4039 4040 #define RTW89_MAX_MAC_ID_NUM 128 4041 #define RTW89_MAX_PKT_OFLD_NUM 255 4042 4043 enum rtw89_flags { 4044 RTW89_FLAG_POWERON, 4045 RTW89_FLAG_FW_RDY, 4046 RTW89_FLAG_RUNNING, 4047 RTW89_FLAG_BFEE_MON, 4048 RTW89_FLAG_BFEE_EN, 4049 RTW89_FLAG_BFEE_TIMER_KEEP, 4050 RTW89_FLAG_NAPI_RUNNING, 4051 RTW89_FLAG_LEISURE_PS, 4052 RTW89_FLAG_LOW_POWER_MODE, 4053 RTW89_FLAG_INACTIVE_PS, 4054 RTW89_FLAG_CRASH_SIMULATING, 4055 RTW89_FLAG_SER_HANDLING, 4056 RTW89_FLAG_WOWLAN, 4057 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4058 RTW89_FLAG_CHANGING_INTERFACE, 4059 4060 NUM_OF_RTW89_FLAGS, 4061 }; 4062 4063 enum rtw89_pkt_drop_sel { 4064 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4065 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4066 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4067 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4068 RTW89_PKT_DROP_SEL_MACID_ALL, 4069 RTW89_PKT_DROP_SEL_MG0_ONCE, 4070 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4071 RTW89_PKT_DROP_SEL_HIQ_PORT, 4072 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4073 RTW89_PKT_DROP_SEL_BAND, 4074 RTW89_PKT_DROP_SEL_BAND_ONCE, 4075 RTW89_PKT_DROP_SEL_REL_MACID, 4076 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4077 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4078 }; 4079 4080 struct rtw89_pkt_drop_params { 4081 enum rtw89_pkt_drop_sel sel; 4082 enum rtw89_mac_idx mac_band; 4083 u8 macid; 4084 u8 port; 4085 u8 mbssid; 4086 bool tf_trs; 4087 u32 macid_band_sel[4]; 4088 }; 4089 4090 struct rtw89_pkt_stat { 4091 u16 beacon_nr; 4092 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4093 }; 4094 4095 DECLARE_EWMA(thermal, 4, 4); 4096 4097 struct rtw89_phy_stat { 4098 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4099 struct rtw89_pkt_stat cur_pkt_stat; 4100 struct rtw89_pkt_stat last_pkt_stat; 4101 }; 4102 4103 #define RTW89_DACK_PATH_NR 2 4104 #define RTW89_DACK_IDX_NR 2 4105 #define RTW89_DACK_MSBK_NR 16 4106 struct rtw89_dack_info { 4107 bool dack_done; 4108 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4109 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4110 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4111 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4112 u32 dack_cnt; 4113 bool addck_timeout[RTW89_DACK_PATH_NR]; 4114 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4115 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4116 }; 4117 4118 #define RTW89_IQK_CHS_NR 2 4119 #define RTW89_IQK_PATH_NR 4 4120 4121 struct rtw89_rfk_mcc_info { 4122 u8 ch[RTW89_IQK_CHS_NR]; 4123 u8 band[RTW89_IQK_CHS_NR]; 4124 u8 table_idx; 4125 }; 4126 4127 struct rtw89_lck_info { 4128 u8 thermal[RF_PATH_MAX]; 4129 }; 4130 4131 struct rtw89_rx_dck_info { 4132 u8 thermal[RF_PATH_MAX]; 4133 }; 4134 4135 struct rtw89_iqk_info { 4136 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4137 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4138 bool lok_fail[RTW89_IQK_PATH_NR]; 4139 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4140 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4141 u32 iqk_fail_cnt; 4142 bool is_iqk_init; 4143 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4144 u8 iqk_band[RTW89_IQK_PATH_NR]; 4145 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4146 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4147 u8 iqk_times; 4148 u8 version; 4149 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4150 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4151 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4152 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4153 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4154 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4155 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4156 bool is_nbiqk; 4157 bool iqk_fft_en; 4158 bool iqk_xym_en; 4159 bool iqk_sram_en; 4160 bool iqk_cfir_en; 4161 u32 syn1to2; 4162 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4163 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4164 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4165 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4166 }; 4167 4168 #define RTW89_DPK_RF_PATH 2 4169 #define RTW89_DPK_AVG_THERMAL_NUM 8 4170 #define RTW89_DPK_BKUP_NUM 2 4171 struct rtw89_dpk_bkup_para { 4172 enum rtw89_band band; 4173 enum rtw89_bandwidth bw; 4174 u8 ch; 4175 bool path_ok; 4176 u8 mdpd_en; 4177 u8 txagc_dpk; 4178 u8 ther_dpk; 4179 u8 gs; 4180 u16 pwsf; 4181 }; 4182 4183 struct rtw89_dpk_info { 4184 bool is_dpk_enable; 4185 bool is_dpk_reload_en; 4186 u8 dpk_gs[RTW89_PHY_MAX]; 4187 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4188 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4189 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4190 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4191 u8 cur_idx[RTW89_DPK_RF_PATH]; 4192 u8 cur_k_set; 4193 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4194 }; 4195 4196 struct rtw89_fem_info { 4197 bool elna_2g; 4198 bool elna_5g; 4199 bool epa_2g; 4200 bool epa_5g; 4201 bool epa_6g; 4202 }; 4203 4204 struct rtw89_phy_ch_info { 4205 u8 rssi_min; 4206 u16 rssi_min_macid; 4207 u8 pre_rssi_min; 4208 u8 rssi_max; 4209 u16 rssi_max_macid; 4210 u8 rxsc_160; 4211 u8 rxsc_80; 4212 u8 rxsc_40; 4213 u8 rxsc_20; 4214 u8 rxsc_l; 4215 u8 is_noisy; 4216 }; 4217 4218 struct rtw89_agc_gaincode_set { 4219 u8 lna_idx; 4220 u8 tia_idx; 4221 u8 rxb_idx; 4222 }; 4223 4224 #define IGI_RSSI_TH_NUM 5 4225 #define FA_TH_NUM 4 4226 #define LNA_GAIN_NUM 7 4227 #define TIA_GAIN_NUM 2 4228 struct rtw89_dig_info { 4229 struct rtw89_agc_gaincode_set cur_gaincode; 4230 bool force_gaincode_idx_en; 4231 struct rtw89_agc_gaincode_set force_gaincode; 4232 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4233 u16 fa_th[FA_TH_NUM]; 4234 u8 igi_rssi; 4235 u8 igi_fa_rssi; 4236 u8 fa_rssi_ofst; 4237 u8 dyn_igi_max; 4238 u8 dyn_igi_min; 4239 bool dyn_pd_th_en; 4240 u8 dyn_pd_th_max; 4241 u8 pd_low_th_ofst; 4242 u8 ib_pbk; 4243 s8 ib_pkpwr; 4244 s8 lna_gain_a[LNA_GAIN_NUM]; 4245 s8 lna_gain_g[LNA_GAIN_NUM]; 4246 s8 *lna_gain; 4247 s8 tia_gain_a[TIA_GAIN_NUM]; 4248 s8 tia_gain_g[TIA_GAIN_NUM]; 4249 s8 *tia_gain; 4250 bool is_linked_pre; 4251 bool bypass_dig; 4252 }; 4253 4254 enum rtw89_multi_cfo_mode { 4255 RTW89_PKT_BASED_AVG_MODE = 0, 4256 RTW89_ENTRY_BASED_AVG_MODE = 1, 4257 RTW89_TP_BASED_AVG_MODE = 2, 4258 }; 4259 4260 enum rtw89_phy_cfo_status { 4261 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4262 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4263 RTW89_PHY_DCFO_STATE_HOLD = 2, 4264 RTW89_PHY_DCFO_STATE_MAX 4265 }; 4266 4267 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4268 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4269 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4270 }; 4271 4272 struct rtw89_cfo_tracking_info { 4273 u16 cfo_timer_ms; 4274 bool cfo_trig_by_timer_en; 4275 enum rtw89_phy_cfo_status phy_cfo_status; 4276 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4277 u8 phy_cfo_trk_cnt; 4278 bool is_adjust; 4279 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4280 bool apply_compensation; 4281 u8 crystal_cap; 4282 u8 crystal_cap_default; 4283 u8 def_x_cap; 4284 s8 x_cap_ofst; 4285 u32 sta_cfo_tolerance; 4286 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4287 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4288 s32 cfo_avg_pre; 4289 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4290 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4291 s32 dcfo_avg; 4292 s32 dcfo_avg_pre; 4293 u32 packet_count; 4294 u32 packet_count_pre; 4295 s32 residual_cfo_acc; 4296 u8 phy_cfotrk_state; 4297 u8 phy_cfotrk_cnt; 4298 bool divergence_lock_en; 4299 u8 x_cap_lb; 4300 u8 x_cap_ub; 4301 u8 lock_cnt; 4302 }; 4303 4304 enum rtw89_tssi_alimk_band { 4305 TSSI_ALIMK_2G = 0, 4306 TSSI_ALIMK_5GL, 4307 TSSI_ALIMK_5GM, 4308 TSSI_ALIMK_5GH, 4309 TSSI_ALIMK_MAX 4310 }; 4311 4312 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4313 #define TSSI_TRIM_CH_GROUP_NUM 8 4314 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4315 4316 #define TSSI_CCK_CH_GROUP_NUM 6 4317 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4318 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4319 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4320 #define TSSI_MCS_CH_GROUP_NUM \ 4321 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4322 #define TSSI_MAX_CH_NUM 67 4323 #define TSSI_ALIMK_VALUE_NUM 8 4324 4325 struct rtw89_tssi_info { 4326 u8 thermal[RF_PATH_MAX]; 4327 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4328 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4329 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4330 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4331 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4332 s8 extra_ofst[RF_PATH_MAX]; 4333 bool tssi_tracking_check[RF_PATH_MAX]; 4334 u8 default_txagc_offset[RF_PATH_MAX]; 4335 u32 base_thermal[RF_PATH_MAX]; 4336 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4337 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4338 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4339 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4340 u32 tssi_alimk_time; 4341 }; 4342 4343 struct rtw89_power_trim_info { 4344 bool pg_thermal_trim; 4345 bool pg_pa_bias_trim; 4346 u8 thermal_trim[RF_PATH_MAX]; 4347 u8 pa_bias_trim[RF_PATH_MAX]; 4348 u8 pad_bias_trim[RF_PATH_MAX]; 4349 }; 4350 4351 struct rtw89_regd { 4352 char alpha2[3]; 4353 u8 txpwr_regd[RTW89_BAND_NUM]; 4354 }; 4355 4356 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4357 4358 struct rtw89_regulatory_info { 4359 const struct rtw89_regd *regd; 4360 enum rtw89_reg_6ghz_power reg_6ghz_power; 4361 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4362 }; 4363 4364 enum rtw89_ifs_clm_application { 4365 RTW89_IFS_CLM_INIT = 0, 4366 RTW89_IFS_CLM_BACKGROUND = 1, 4367 RTW89_IFS_CLM_ACS = 2, 4368 RTW89_IFS_CLM_DIG = 3, 4369 RTW89_IFS_CLM_TDMA_DIG = 4, 4370 RTW89_IFS_CLM_DBG = 5, 4371 RTW89_IFS_CLM_DBG_MANUAL = 6 4372 }; 4373 4374 enum rtw89_env_racing_lv { 4375 RTW89_RAC_RELEASE = 0, 4376 RTW89_RAC_LV_1 = 1, 4377 RTW89_RAC_LV_2 = 2, 4378 RTW89_RAC_LV_3 = 3, 4379 RTW89_RAC_LV_4 = 4, 4380 RTW89_RAC_MAX_NUM = 5 4381 }; 4382 4383 struct rtw89_ccx_para_info { 4384 enum rtw89_env_racing_lv rac_lv; 4385 u16 mntr_time; 4386 u8 nhm_manual_th_ofst; 4387 u8 nhm_manual_th0; 4388 enum rtw89_ifs_clm_application ifs_clm_app; 4389 u32 ifs_clm_manual_th_times; 4390 u32 ifs_clm_manual_th0; 4391 u8 fahm_manual_th_ofst; 4392 u8 fahm_manual_th0; 4393 u8 fahm_numer_opt; 4394 u8 fahm_denom_opt; 4395 }; 4396 4397 enum rtw89_ccx_edcca_opt_sc_idx { 4398 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4399 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4400 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4401 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4402 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4403 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4404 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4405 RTW89_CCX_EDCCA_SEG1_S3 = 7 4406 }; 4407 4408 enum rtw89_ccx_edcca_opt_bw_idx { 4409 RTW89_CCX_EDCCA_BW20_0 = 0, 4410 RTW89_CCX_EDCCA_BW20_1 = 1, 4411 RTW89_CCX_EDCCA_BW20_2 = 2, 4412 RTW89_CCX_EDCCA_BW20_3 = 3, 4413 RTW89_CCX_EDCCA_BW20_4 = 4, 4414 RTW89_CCX_EDCCA_BW20_5 = 5, 4415 RTW89_CCX_EDCCA_BW20_6 = 6, 4416 RTW89_CCX_EDCCA_BW20_7 = 7 4417 }; 4418 4419 #define RTW89_NHM_TH_NUM 11 4420 #define RTW89_FAHM_TH_NUM 11 4421 #define RTW89_NHM_RPT_NUM 12 4422 #define RTW89_FAHM_RPT_NUM 12 4423 #define RTW89_IFS_CLM_NUM 4 4424 struct rtw89_env_monitor_info { 4425 u8 ccx_watchdog_result; 4426 bool ccx_ongoing; 4427 u8 ccx_rac_lv; 4428 bool ccx_manual_ctrl; 4429 u16 ifs_clm_mntr_time; 4430 enum rtw89_ifs_clm_application ifs_clm_app; 4431 u16 ccx_period; 4432 u8 ccx_unit_idx; 4433 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4434 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4435 u16 ifs_clm_tx; 4436 u16 ifs_clm_edcca_excl_cca; 4437 u16 ifs_clm_ofdmfa; 4438 u16 ifs_clm_ofdmcca_excl_fa; 4439 u16 ifs_clm_cckfa; 4440 u16 ifs_clm_cckcca_excl_fa; 4441 u16 ifs_clm_total_ifs; 4442 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4443 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4444 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4445 u8 ifs_clm_tx_ratio; 4446 u8 ifs_clm_edcca_excl_cca_ratio; 4447 u8 ifs_clm_cck_fa_ratio; 4448 u8 ifs_clm_ofdm_fa_ratio; 4449 u8 ifs_clm_cck_cca_excl_fa_ratio; 4450 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4451 u16 ifs_clm_cck_fa_permil; 4452 u16 ifs_clm_ofdm_fa_permil; 4453 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4454 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4455 }; 4456 4457 enum rtw89_ser_rcvy_step { 4458 RTW89_SER_DRV_STOP_TX, 4459 RTW89_SER_DRV_STOP_RX, 4460 RTW89_SER_DRV_STOP_RUN, 4461 RTW89_SER_HAL_STOP_DMA, 4462 RTW89_SER_SUPPRESS_LOG, 4463 RTW89_NUM_OF_SER_FLAGS 4464 }; 4465 4466 struct rtw89_ser { 4467 u8 state; 4468 u8 alarm_event; 4469 bool prehandle_l1; 4470 4471 struct work_struct ser_hdl_work; 4472 struct delayed_work ser_alarm_work; 4473 const struct state_ent *st_tbl; 4474 const struct event_ent *ev_tbl; 4475 struct list_head msg_q; 4476 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4477 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4478 }; 4479 4480 enum rtw89_mac_ax_ps_mode { 4481 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4482 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4483 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4484 RTW89_MAC_AX_PS_MODE_MAX = 3, 4485 }; 4486 4487 enum rtw89_last_rpwm_mode { 4488 RTW89_LAST_RPWM_PS = 0x0, 4489 RTW89_LAST_RPWM_ACTIVE = 0x6, 4490 }; 4491 4492 struct rtw89_lps_parm { 4493 u8 macid; 4494 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4495 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4496 }; 4497 4498 struct rtw89_ppdu_sts_info { 4499 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4500 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4501 }; 4502 4503 struct rtw89_early_h2c { 4504 struct list_head list; 4505 u8 *h2c; 4506 u16 h2c_len; 4507 }; 4508 4509 struct rtw89_hw_scan_info { 4510 struct ieee80211_vif *scanning_vif; 4511 struct list_head pkt_list[NUM_NL80211_BANDS]; 4512 struct rtw89_chan op_chan; 4513 u32 last_chan_idx; 4514 }; 4515 4516 enum rtw89_phy_bb_gain_band { 4517 RTW89_BB_GAIN_BAND_2G = 0, 4518 RTW89_BB_GAIN_BAND_5G_L = 1, 4519 RTW89_BB_GAIN_BAND_5G_M = 2, 4520 RTW89_BB_GAIN_BAND_5G_H = 3, 4521 RTW89_BB_GAIN_BAND_6G_L = 4, 4522 RTW89_BB_GAIN_BAND_6G_M = 5, 4523 RTW89_BB_GAIN_BAND_6G_H = 6, 4524 RTW89_BB_GAIN_BAND_6G_UH = 7, 4525 4526 RTW89_BB_GAIN_BAND_NR, 4527 }; 4528 4529 enum rtw89_phy_bb_rxsc_num { 4530 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4531 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4532 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4533 }; 4534 4535 struct rtw89_phy_bb_gain_info { 4536 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4537 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4538 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4539 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4540 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4541 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4542 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4543 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4544 [RTW89_BB_RXSC_NUM_40]; 4545 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4546 [RTW89_BB_RXSC_NUM_80]; 4547 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4548 [RTW89_BB_RXSC_NUM_160]; 4549 }; 4550 4551 struct rtw89_phy_efuse_gain { 4552 bool offset_valid; 4553 bool comp_valid; 4554 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4555 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4556 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4557 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4558 }; 4559 4560 #define RTW89_MAX_PATTERN_NUM 18 4561 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4562 #define RTW89_MAX_PATTERN_SIZE 128 4563 4564 struct rtw89_wow_cam_info { 4565 bool r_w; 4566 u8 idx; 4567 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4568 u16 crc; 4569 bool negative_pattern_match; 4570 bool skip_mac_hdr; 4571 bool uc; 4572 bool mc; 4573 bool bc; 4574 bool valid; 4575 }; 4576 4577 struct rtw89_wow_param { 4578 struct ieee80211_vif *wow_vif; 4579 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4580 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4581 u8 pattern_cnt; 4582 }; 4583 4584 struct rtw89_mcc_limit { 4585 bool enable; 4586 u16 max_tob; /* TU; max time offset behind */ 4587 u16 max_toa; /* TU; max time offset ahead */ 4588 u16 max_dur; /* TU */ 4589 }; 4590 4591 struct rtw89_mcc_policy { 4592 u8 c2h_rpt; 4593 u8 tx_null_early; 4594 u8 dis_tx_null; 4595 u8 in_curr_ch; 4596 u8 dis_sw_retry; 4597 u8 sw_retry_count; 4598 }; 4599 4600 struct rtw89_mcc_role { 4601 struct rtw89_vif *rtwvif; 4602 struct rtw89_mcc_policy policy; 4603 struct rtw89_mcc_limit limit; 4604 4605 /* byte-array in LE order for FW */ 4606 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 4607 4608 u16 duration; /* TU */ 4609 u16 beacon_interval; /* TU */ 4610 bool is_2ghz; 4611 bool is_go; 4612 bool is_gc; 4613 }; 4614 4615 struct rtw89_mcc_bt_role { 4616 u16 duration; /* TU */ 4617 }; 4618 4619 struct rtw89_mcc_courtesy { 4620 bool enable; 4621 u8 slot_num; 4622 u8 macid_src; 4623 u8 macid_tgt; 4624 }; 4625 4626 enum rtw89_mcc_plan { 4627 RTW89_MCC_PLAN_TAIL_BT, 4628 RTW89_MCC_PLAN_MID_BT, 4629 RTW89_MCC_PLAN_NO_BT, 4630 4631 NUM_OF_RTW89_MCC_PLAN, 4632 }; 4633 4634 struct rtw89_mcc_pattern { 4635 s16 tob_ref; /* TU; time offset behind of reference role */ 4636 s16 toa_ref; /* TU; time offset ahead of reference role */ 4637 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 4638 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 4639 4640 enum rtw89_mcc_plan plan; 4641 struct rtw89_mcc_courtesy courtesy; 4642 }; 4643 4644 struct rtw89_mcc_sync { 4645 bool enable; 4646 u16 offset; /* TU */ 4647 u8 macid_src; 4648 u8 macid_tgt; 4649 }; 4650 4651 struct rtw89_mcc_config { 4652 struct rtw89_mcc_pattern pattern; 4653 struct rtw89_mcc_sync sync; 4654 u64 start_tsf; 4655 u16 mcc_interval; /* TU */ 4656 u16 beacon_offset; /* TU */ 4657 }; 4658 4659 enum rtw89_mcc_mode { 4660 RTW89_MCC_MODE_GO_STA, 4661 RTW89_MCC_MODE_GC_STA, 4662 }; 4663 4664 struct rtw89_mcc_info { 4665 struct rtw89_wait_info wait; 4666 4667 u8 group; 4668 enum rtw89_mcc_mode mode; 4669 struct rtw89_mcc_role role_ref; /* reference role */ 4670 struct rtw89_mcc_role role_aux; /* auxiliary role */ 4671 struct rtw89_mcc_bt_role bt_role; 4672 struct rtw89_mcc_config config; 4673 }; 4674 4675 struct rtw89_dev { 4676 struct ieee80211_hw *hw; 4677 struct device *dev; 4678 const struct ieee80211_ops *ops; 4679 4680 bool dbcc_en; 4681 struct rtw89_hw_scan_info scan_info; 4682 const struct rtw89_chip_info *chip; 4683 const struct rtw89_pci_info *pci_info; 4684 const struct rtw89_rfe_parms *rfe_parms; 4685 struct rtw89_hal hal; 4686 struct rtw89_mcc_info mcc; 4687 struct rtw89_mac_info mac; 4688 struct rtw89_fw_info fw; 4689 struct rtw89_hci_info hci; 4690 struct rtw89_efuse efuse; 4691 struct rtw89_traffic_stats stats; 4692 struct rtw89_rfe_data *rfe_data; 4693 4694 /* ensures exclusive access from mac80211 callbacks */ 4695 struct mutex mutex; 4696 struct list_head rtwvifs_list; 4697 /* used to protect rf read write */ 4698 struct mutex rf_mutex; 4699 struct workqueue_struct *txq_wq; 4700 struct work_struct txq_work; 4701 struct delayed_work txq_reinvoke_work; 4702 /* used to protect ba_list and forbid_ba_list */ 4703 spinlock_t ba_lock; 4704 /* txqs to setup ba session */ 4705 struct list_head ba_list; 4706 /* txqs to forbid ba session */ 4707 struct list_head forbid_ba_list; 4708 struct work_struct ba_work; 4709 /* used to protect rpwm */ 4710 spinlock_t rpwm_lock; 4711 4712 struct rtw89_cam_info cam_info; 4713 4714 struct sk_buff_head c2h_queue; 4715 struct work_struct c2h_work; 4716 struct work_struct ips_work; 4717 struct work_struct load_firmware_work; 4718 struct work_struct cancel_6ghz_probe_work; 4719 4720 struct list_head early_h2c_list; 4721 4722 struct rtw89_ser ser; 4723 4724 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4725 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 4726 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 4727 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 4728 4729 struct rtw89_phy_stat phystat; 4730 struct rtw89_dack_info dack; 4731 struct rtw89_iqk_info iqk; 4732 struct rtw89_dpk_info dpk; 4733 struct rtw89_rfk_mcc_info rfk_mcc; 4734 struct rtw89_lck_info lck; 4735 struct rtw89_rx_dck_info rx_dck; 4736 bool is_tssi_mode[RF_PATH_MAX]; 4737 bool is_bt_iqk_timeout; 4738 4739 struct rtw89_fem_info fem; 4740 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 4741 struct rtw89_tssi_info tssi; 4742 struct rtw89_power_trim_info pwr_trim; 4743 4744 struct rtw89_cfo_tracking_info cfo_tracking; 4745 struct rtw89_env_monitor_info env_monitor; 4746 struct rtw89_dig_info dig; 4747 struct rtw89_phy_ch_info ch_info; 4748 struct rtw89_phy_bb_gain_info bb_gain; 4749 struct rtw89_phy_efuse_gain efuse_gain; 4750 struct rtw89_phy_ul_tb_info ul_tb_info; 4751 struct rtw89_antdiv_info antdiv; 4752 4753 struct delayed_work track_work; 4754 struct delayed_work chanctx_work; 4755 struct delayed_work coex_act1_work; 4756 struct delayed_work coex_bt_devinfo_work; 4757 struct delayed_work coex_rfk_chk_work; 4758 struct delayed_work cfo_track_work; 4759 struct delayed_work forbid_ba_work; 4760 struct delayed_work roc_work; 4761 struct delayed_work antdiv_work; 4762 struct rtw89_ppdu_sts_info ppdu_sts; 4763 u8 total_sta_assoc; 4764 bool scanning; 4765 4766 struct rtw89_regulatory_info regulatory; 4767 struct rtw89_sar_info sar; 4768 struct rtw89_tas_info tas; 4769 4770 struct rtw89_btc btc; 4771 enum rtw89_ps_mode ps_mode; 4772 bool lps_enabled; 4773 4774 struct rtw89_wow_param wow; 4775 4776 /* napi structure */ 4777 struct net_device netdev; 4778 struct napi_struct napi; 4779 int napi_budget_countdown; 4780 4781 /* HCI related data, keep last */ 4782 u8 priv[] __aligned(sizeof(void *)); 4783 }; 4784 4785 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4786 struct rtw89_core_tx_request *tx_req) 4787 { 4788 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4789 } 4790 4791 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4792 { 4793 rtwdev->hci.ops->reset(rtwdev); 4794 } 4795 4796 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4797 { 4798 return rtwdev->hci.ops->start(rtwdev); 4799 } 4800 4801 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4802 { 4803 rtwdev->hci.ops->stop(rtwdev); 4804 } 4805 4806 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4807 { 4808 return rtwdev->hci.ops->deinit(rtwdev); 4809 } 4810 4811 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4812 { 4813 rtwdev->hci.ops->pause(rtwdev, pause); 4814 } 4815 4816 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4817 { 4818 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4819 } 4820 4821 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4822 { 4823 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4824 } 4825 4826 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4827 { 4828 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4829 } 4830 4831 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4832 { 4833 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4834 } 4835 4836 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 4837 { 4838 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 4839 } 4840 4841 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4842 bool drop) 4843 { 4844 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4845 return; 4846 4847 if (rtwdev->hci.ops->flush_queues) 4848 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4849 } 4850 4851 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4852 { 4853 if (rtwdev->hci.ops->recovery_start) 4854 rtwdev->hci.ops->recovery_start(rtwdev); 4855 } 4856 4857 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4858 { 4859 if (rtwdev->hci.ops->recovery_complete) 4860 rtwdev->hci.ops->recovery_complete(rtwdev); 4861 } 4862 4863 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4864 { 4865 if (rtwdev->hci.ops->enable_intr) 4866 rtwdev->hci.ops->enable_intr(rtwdev); 4867 } 4868 4869 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4870 { 4871 if (rtwdev->hci.ops->disable_intr) 4872 rtwdev->hci.ops->disable_intr(rtwdev); 4873 } 4874 4875 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4876 { 4877 if (rtwdev->hci.ops->ctrl_txdma_ch) 4878 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4879 } 4880 4881 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4882 { 4883 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4884 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4885 } 4886 4887 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4888 { 4889 if (rtwdev->hci.ops->ctrl_trxhci) 4890 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4891 } 4892 4893 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4894 { 4895 int ret = 0; 4896 4897 if (rtwdev->hci.ops->poll_txdma_ch) 4898 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4899 return ret; 4900 } 4901 4902 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4903 { 4904 if (rtwdev->hci.ops->clr_idx_all) 4905 rtwdev->hci.ops->clr_idx_all(rtwdev); 4906 } 4907 4908 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4909 { 4910 int ret = 0; 4911 4912 if (rtwdev->hci.ops->rst_bdram) 4913 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4914 return ret; 4915 } 4916 4917 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4918 { 4919 if (rtwdev->hci.ops->clear) 4920 rtwdev->hci.ops->clear(rtwdev, pdev); 4921 } 4922 4923 static inline 4924 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 4925 { 4926 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 4927 4928 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 4929 } 4930 4931 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 4932 { 4933 return rtwdev->hci.ops->read8(rtwdev, addr); 4934 } 4935 4936 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 4937 { 4938 return rtwdev->hci.ops->read16(rtwdev, addr); 4939 } 4940 4941 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 4942 { 4943 return rtwdev->hci.ops->read32(rtwdev, addr); 4944 } 4945 4946 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 4947 { 4948 rtwdev->hci.ops->write8(rtwdev, addr, data); 4949 } 4950 4951 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 4952 { 4953 rtwdev->hci.ops->write16(rtwdev, addr, data); 4954 } 4955 4956 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 4957 { 4958 rtwdev->hci.ops->write32(rtwdev, addr, data); 4959 } 4960 4961 static inline void 4962 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4963 { 4964 u8 val; 4965 4966 val = rtw89_read8(rtwdev, addr); 4967 rtw89_write8(rtwdev, addr, val | bit); 4968 } 4969 4970 static inline void 4971 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4972 { 4973 u16 val; 4974 4975 val = rtw89_read16(rtwdev, addr); 4976 rtw89_write16(rtwdev, addr, val | bit); 4977 } 4978 4979 static inline void 4980 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4981 { 4982 u32 val; 4983 4984 val = rtw89_read32(rtwdev, addr); 4985 rtw89_write32(rtwdev, addr, val | bit); 4986 } 4987 4988 static inline void 4989 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4990 { 4991 u8 val; 4992 4993 val = rtw89_read8(rtwdev, addr); 4994 rtw89_write8(rtwdev, addr, val & ~bit); 4995 } 4996 4997 static inline void 4998 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4999 { 5000 u16 val; 5001 5002 val = rtw89_read16(rtwdev, addr); 5003 rtw89_write16(rtwdev, addr, val & ~bit); 5004 } 5005 5006 static inline void 5007 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5008 { 5009 u32 val; 5010 5011 val = rtw89_read32(rtwdev, addr); 5012 rtw89_write32(rtwdev, addr, val & ~bit); 5013 } 5014 5015 static inline u32 5016 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5017 { 5018 u32 shift = __ffs(mask); 5019 u32 orig; 5020 u32 ret; 5021 5022 orig = rtw89_read32(rtwdev, addr); 5023 ret = (orig & mask) >> shift; 5024 5025 return ret; 5026 } 5027 5028 static inline u16 5029 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5030 { 5031 u32 shift = __ffs(mask); 5032 u32 orig; 5033 u32 ret; 5034 5035 orig = rtw89_read16(rtwdev, addr); 5036 ret = (orig & mask) >> shift; 5037 5038 return ret; 5039 } 5040 5041 static inline u8 5042 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5043 { 5044 u32 shift = __ffs(mask); 5045 u32 orig; 5046 u32 ret; 5047 5048 orig = rtw89_read8(rtwdev, addr); 5049 ret = (orig & mask) >> shift; 5050 5051 return ret; 5052 } 5053 5054 static inline void 5055 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5056 { 5057 u32 shift = __ffs(mask); 5058 u32 orig; 5059 u32 set; 5060 5061 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5062 5063 orig = rtw89_read32(rtwdev, addr); 5064 set = (orig & ~mask) | ((data << shift) & mask); 5065 rtw89_write32(rtwdev, addr, set); 5066 } 5067 5068 static inline void 5069 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5070 { 5071 u32 shift; 5072 u16 orig, set; 5073 5074 mask &= 0xffff; 5075 shift = __ffs(mask); 5076 5077 orig = rtw89_read16(rtwdev, addr); 5078 set = (orig & ~mask) | ((data << shift) & mask); 5079 rtw89_write16(rtwdev, addr, set); 5080 } 5081 5082 static inline void 5083 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5084 { 5085 u32 shift; 5086 u8 orig, set; 5087 5088 mask &= 0xff; 5089 shift = __ffs(mask); 5090 5091 orig = rtw89_read8(rtwdev, addr); 5092 set = (orig & ~mask) | ((data << shift) & mask); 5093 rtw89_write8(rtwdev, addr, set); 5094 } 5095 5096 static inline u32 5097 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5098 u32 addr, u32 mask) 5099 { 5100 u32 val; 5101 5102 mutex_lock(&rtwdev->rf_mutex); 5103 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5104 mutex_unlock(&rtwdev->rf_mutex); 5105 5106 return val; 5107 } 5108 5109 static inline void 5110 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5111 u32 addr, u32 mask, u32 data) 5112 { 5113 mutex_lock(&rtwdev->rf_mutex); 5114 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5115 mutex_unlock(&rtwdev->rf_mutex); 5116 } 5117 5118 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5119 { 5120 void *p = rtwtxq; 5121 5122 return container_of(p, struct ieee80211_txq, drv_priv); 5123 } 5124 5125 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5126 struct ieee80211_txq *txq) 5127 { 5128 struct rtw89_txq *rtwtxq; 5129 5130 if (!txq) 5131 return; 5132 5133 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5134 INIT_LIST_HEAD(&rtwtxq->list); 5135 } 5136 5137 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5138 { 5139 void *p = rtwvif; 5140 5141 return container_of(p, struct ieee80211_vif, drv_priv); 5142 } 5143 5144 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5145 { 5146 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5147 } 5148 5149 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5150 { 5151 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5152 } 5153 5154 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5155 { 5156 void *p = rtwsta; 5157 5158 return container_of(p, struct ieee80211_sta, drv_priv); 5159 } 5160 5161 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5162 { 5163 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5164 } 5165 5166 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5167 { 5168 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5169 } 5170 5171 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5172 { 5173 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5174 return RATE_INFO_BW_160; 5175 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5176 return RATE_INFO_BW_80; 5177 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5178 return RATE_INFO_BW_40; 5179 else 5180 return RATE_INFO_BW_20; 5181 } 5182 5183 static inline 5184 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5185 { 5186 switch (hw_band) { 5187 default: 5188 case RTW89_BAND_2G: 5189 return NL80211_BAND_2GHZ; 5190 case RTW89_BAND_5G: 5191 return NL80211_BAND_5GHZ; 5192 case RTW89_BAND_6G: 5193 return NL80211_BAND_6GHZ; 5194 } 5195 } 5196 5197 static inline 5198 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5199 { 5200 switch (nl_band) { 5201 default: 5202 case NL80211_BAND_2GHZ: 5203 return RTW89_BAND_2G; 5204 case NL80211_BAND_5GHZ: 5205 return RTW89_BAND_5G; 5206 case NL80211_BAND_6GHZ: 5207 return RTW89_BAND_6G; 5208 } 5209 } 5210 5211 static inline 5212 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5213 { 5214 switch (width) { 5215 default: 5216 WARN(1, "Not support bandwidth %d\n", width); 5217 fallthrough; 5218 case NL80211_CHAN_WIDTH_20_NOHT: 5219 case NL80211_CHAN_WIDTH_20: 5220 return RTW89_CHANNEL_WIDTH_20; 5221 case NL80211_CHAN_WIDTH_40: 5222 return RTW89_CHANNEL_WIDTH_40; 5223 case NL80211_CHAN_WIDTH_80: 5224 return RTW89_CHANNEL_WIDTH_80; 5225 case NL80211_CHAN_WIDTH_160: 5226 return RTW89_CHANNEL_WIDTH_160; 5227 } 5228 } 5229 5230 static inline 5231 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5232 { 5233 switch (rua) { 5234 default: 5235 WARN(1, "Invalid RU allocation: %d\n", rua); 5236 fallthrough; 5237 case 0 ... 36: 5238 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5239 case 37 ... 52: 5240 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5241 case 53 ... 60: 5242 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5243 case 61 ... 64: 5244 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5245 case 65 ... 66: 5246 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5247 case 67: 5248 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5249 case 68: 5250 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5251 } 5252 } 5253 5254 static inline 5255 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5256 struct rtw89_sta *rtwsta) 5257 { 5258 if (rtwsta) { 5259 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5260 5261 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5262 return &rtwsta->addr_cam; 5263 } 5264 return &rtwvif->addr_cam; 5265 } 5266 5267 static inline 5268 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5269 struct rtw89_sta *rtwsta) 5270 { 5271 if (rtwsta) { 5272 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5273 5274 if (sta->tdls) 5275 return &rtwsta->bssid_cam; 5276 } 5277 return &rtwvif->bssid_cam; 5278 } 5279 5280 static inline 5281 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5282 struct rtw89_channel_help_params *p, 5283 const struct rtw89_chan *chan, 5284 enum rtw89_mac_idx mac_idx, 5285 enum rtw89_phy_idx phy_idx) 5286 { 5287 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5288 mac_idx, phy_idx); 5289 } 5290 5291 static inline 5292 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 5293 struct rtw89_channel_help_params *p, 5294 const struct rtw89_chan *chan, 5295 enum rtw89_mac_idx mac_idx, 5296 enum rtw89_phy_idx phy_idx) 5297 { 5298 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 5299 mac_idx, phy_idx); 5300 } 5301 5302 static inline 5303 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 5304 enum rtw89_sub_entity_idx idx) 5305 { 5306 struct rtw89_hal *hal = &rtwdev->hal; 5307 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 5308 5309 if (roc_idx == idx) 5310 return &hal->roc_chandef; 5311 5312 return &hal->sub[idx].chandef; 5313 } 5314 5315 static inline 5316 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 5317 enum rtw89_sub_entity_idx idx) 5318 { 5319 struct rtw89_hal *hal = &rtwdev->hal; 5320 5321 return &hal->sub[idx].chan; 5322 } 5323 5324 static inline 5325 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 5326 enum rtw89_sub_entity_idx idx) 5327 { 5328 struct rtw89_hal *hal = &rtwdev->hal; 5329 5330 return &hal->sub[idx].rcd; 5331 } 5332 5333 static inline 5334 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 5335 { 5336 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 5337 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 5338 5339 if (rtwvif) 5340 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 5341 else 5342 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5343 } 5344 5345 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 5346 { 5347 const struct rtw89_chip_info *chip = rtwdev->chip; 5348 5349 if (chip->ops->fem_setup) 5350 chip->ops->fem_setup(rtwdev); 5351 } 5352 5353 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 5354 { 5355 const struct rtw89_chip_info *chip = rtwdev->chip; 5356 5357 if (chip->ops->rfe_gpio) 5358 chip->ops->rfe_gpio(rtwdev); 5359 } 5360 5361 static inline 5362 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5363 { 5364 const struct rtw89_chip_info *chip = rtwdev->chip; 5365 5366 if (chip->ops->bb_preinit) 5367 chip->ops->bb_preinit(rtwdev, phy_idx); 5368 } 5369 5370 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 5371 { 5372 const struct rtw89_chip_info *chip = rtwdev->chip; 5373 5374 if (chip->ops->bb_sethw) 5375 chip->ops->bb_sethw(rtwdev); 5376 } 5377 5378 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 5379 { 5380 const struct rtw89_chip_info *chip = rtwdev->chip; 5381 5382 if (chip->ops->rfk_init) 5383 chip->ops->rfk_init(rtwdev); 5384 } 5385 5386 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 5387 { 5388 const struct rtw89_chip_info *chip = rtwdev->chip; 5389 5390 if (chip->ops->rfk_channel) 5391 chip->ops->rfk_channel(rtwdev); 5392 } 5393 5394 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 5395 enum rtw89_phy_idx phy_idx) 5396 { 5397 const struct rtw89_chip_info *chip = rtwdev->chip; 5398 5399 if (chip->ops->rfk_band_changed) 5400 chip->ops->rfk_band_changed(rtwdev, phy_idx); 5401 } 5402 5403 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 5404 { 5405 const struct rtw89_chip_info *chip = rtwdev->chip; 5406 5407 if (chip->ops->rfk_scan) 5408 chip->ops->rfk_scan(rtwdev, start); 5409 } 5410 5411 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 5412 { 5413 const struct rtw89_chip_info *chip = rtwdev->chip; 5414 5415 if (chip->ops->rfk_track) 5416 chip->ops->rfk_track(rtwdev); 5417 } 5418 5419 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 5420 { 5421 const struct rtw89_chip_info *chip = rtwdev->chip; 5422 5423 if (chip->ops->set_txpwr_ctrl) 5424 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 5425 } 5426 5427 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 5428 { 5429 const struct rtw89_chip_info *chip = rtwdev->chip; 5430 5431 if (chip->ops->power_trim) 5432 chip->ops->power_trim(rtwdev); 5433 } 5434 5435 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 5436 enum rtw89_phy_idx phy_idx) 5437 { 5438 const struct rtw89_chip_info *chip = rtwdev->chip; 5439 5440 if (chip->ops->init_txpwr_unit) 5441 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 5442 } 5443 5444 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 5445 enum rtw89_rf_path rf_path) 5446 { 5447 const struct rtw89_chip_info *chip = rtwdev->chip; 5448 5449 if (!chip->ops->get_thermal) 5450 return 0x10; 5451 5452 return chip->ops->get_thermal(rtwdev, rf_path); 5453 } 5454 5455 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 5456 struct rtw89_rx_phy_ppdu *phy_ppdu, 5457 struct ieee80211_rx_status *status) 5458 { 5459 const struct rtw89_chip_info *chip = rtwdev->chip; 5460 5461 if (chip->ops->query_ppdu) 5462 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 5463 } 5464 5465 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 5466 enum rtw89_phy_idx phy_idx) 5467 { 5468 const struct rtw89_chip_info *chip = rtwdev->chip; 5469 5470 if (chip->ops->ctrl_nbtg_bt_tx) 5471 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 5472 } 5473 5474 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 5475 { 5476 const struct rtw89_chip_info *chip = rtwdev->chip; 5477 5478 if (chip->ops->cfg_txrx_path) 5479 chip->ops->cfg_txrx_path(rtwdev); 5480 } 5481 5482 static inline 5483 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5484 struct ieee80211_vif *vif) 5485 { 5486 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5487 const struct rtw89_chip_info *chip = rtwdev->chip; 5488 5489 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5490 return; 5491 5492 if (chip->ops->set_txpwr_ul_tb_offset) 5493 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5494 } 5495 5496 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 5497 const struct rtw89_txpwr_table *tbl) 5498 { 5499 tbl->load(rtwdev, tbl); 5500 } 5501 5502 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 5503 { 5504 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 5505 5506 return regd->txpwr_regd[band]; 5507 } 5508 5509 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 5510 enum rtw89_phy_idx phy_idx) 5511 { 5512 const struct rtw89_chip_info *chip = rtwdev->chip; 5513 5514 if (chip->ops->ctrl_btg_bt_rx) 5515 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 5516 } 5517 5518 static inline 5519 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 5520 struct rtw89_rx_desc_info *desc_info, 5521 u8 *data, u32 data_offset) 5522 { 5523 const struct rtw89_chip_info *chip = rtwdev->chip; 5524 5525 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 5526 } 5527 5528 static inline 5529 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 5530 struct rtw89_tx_desc_info *desc_info, 5531 void *txdesc) 5532 { 5533 const struct rtw89_chip_info *chip = rtwdev->chip; 5534 5535 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 5536 } 5537 5538 static inline 5539 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 5540 struct rtw89_tx_desc_info *desc_info, 5541 void *txdesc) 5542 { 5543 const struct rtw89_chip_info *chip = rtwdev->chip; 5544 5545 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 5546 } 5547 5548 static inline 5549 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5550 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5551 { 5552 const struct rtw89_chip_info *chip = rtwdev->chip; 5553 5554 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 5555 } 5556 5557 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5558 { 5559 const struct rtw89_chip_info *chip = rtwdev->chip; 5560 5561 chip->ops->cfg_ctrl_path(rtwdev, wl); 5562 } 5563 5564 static inline 5565 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 5566 u32 *tx_en, enum rtw89_sch_tx_sel sel) 5567 { 5568 const struct rtw89_chip_info *chip = rtwdev->chip; 5569 5570 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 5571 } 5572 5573 static inline 5574 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 5575 { 5576 const struct rtw89_chip_info *chip = rtwdev->chip; 5577 5578 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 5579 } 5580 5581 static inline 5582 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 5583 struct rtw89_vif *rtwvif, 5584 struct rtw89_sta *rtwsta) 5585 { 5586 const struct rtw89_chip_info *chip = rtwdev->chip; 5587 5588 if (!chip->ops->h2c_dctl_sec_cam) 5589 return 0; 5590 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 5591 } 5592 5593 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 5594 { 5595 __le16 fc = hdr->frame_control; 5596 5597 if (ieee80211_has_tods(fc)) 5598 return hdr->addr1; 5599 else if (ieee80211_has_fromds(fc)) 5600 return hdr->addr2; 5601 else 5602 return hdr->addr3; 5603 } 5604 5605 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 5606 { 5607 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5608 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 5609 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 5610 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5611 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 5612 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 5613 return true; 5614 return false; 5615 } 5616 5617 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 5618 enum rtw89_fw_type type) 5619 { 5620 struct rtw89_fw_info *fw_info = &rtwdev->fw; 5621 5622 switch (type) { 5623 case RTW89_FW_WOWLAN: 5624 return &fw_info->wowlan; 5625 case RTW89_FW_LOGFMT: 5626 return &fw_info->log.suit; 5627 case RTW89_FW_BBMCU0: 5628 return &fw_info->bbmcu0; 5629 case RTW89_FW_BBMCU1: 5630 return &fw_info->bbmcu1; 5631 default: 5632 break; 5633 } 5634 5635 return &fw_info->normal; 5636 } 5637 5638 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 5639 unsigned int length) 5640 { 5641 struct sk_buff *skb; 5642 5643 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 5644 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 5645 if (!skb) 5646 return NULL; 5647 5648 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 5649 return skb; 5650 } 5651 5652 return dev_alloc_skb(length); 5653 } 5654 5655 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 5656 struct rtw89_tx_skb_data *skb_data, 5657 bool tx_done) 5658 { 5659 struct rtw89_tx_wait_info *wait; 5660 5661 rcu_read_lock(); 5662 5663 wait = rcu_dereference(skb_data->wait); 5664 if (!wait) 5665 goto out; 5666 5667 wait->tx_done = tx_done; 5668 complete(&wait->completion); 5669 5670 out: 5671 rcu_read_unlock(); 5672 } 5673 5674 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5675 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 5676 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 5677 struct sk_buff *skb, bool fwdl); 5678 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 5679 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5680 int qsel, unsigned int timeout); 5681 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 5682 struct rtw89_tx_desc_info *desc_info, 5683 void *txdesc); 5684 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 5685 struct rtw89_tx_desc_info *desc_info, 5686 void *txdesc); 5687 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 5688 struct rtw89_tx_desc_info *desc_info, 5689 void *txdesc); 5690 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 5691 struct rtw89_tx_desc_info *desc_info, 5692 void *txdesc); 5693 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 5694 struct rtw89_tx_desc_info *desc_info, 5695 void *txdesc); 5696 void rtw89_core_rx(struct rtw89_dev *rtwdev, 5697 struct rtw89_rx_desc_info *desc_info, 5698 struct sk_buff *skb); 5699 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 5700 struct rtw89_rx_desc_info *desc_info, 5701 u8 *data, u32 data_offset); 5702 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 5703 struct rtw89_rx_desc_info *desc_info, 5704 u8 *data, u32 data_offset); 5705 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 5706 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 5707 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 5708 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 5709 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 5710 struct ieee80211_vif *vif, 5711 struct ieee80211_sta *sta); 5712 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 5713 struct ieee80211_vif *vif, 5714 struct ieee80211_sta *sta); 5715 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 5716 struct ieee80211_vif *vif, 5717 struct ieee80211_sta *sta); 5718 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 5719 struct ieee80211_vif *vif, 5720 struct ieee80211_sta *sta); 5721 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 5722 struct ieee80211_vif *vif, 5723 struct ieee80211_sta *sta); 5724 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5725 struct ieee80211_sta *sta, 5726 struct cfg80211_tid_config *tid_config); 5727 int rtw89_core_init(struct rtw89_dev *rtwdev); 5728 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 5729 int rtw89_core_register(struct rtw89_dev *rtwdev); 5730 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 5731 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5732 u32 bus_data_size, 5733 const struct rtw89_chip_info *chip); 5734 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 5735 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 5736 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 5737 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 5738 struct rtw89_chan *chan); 5739 void rtw89_set_channel(struct rtw89_dev *rtwdev); 5740 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5741 struct rtw89_chan *chan); 5742 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 5743 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 5744 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 5745 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 5746 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5747 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 5748 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5749 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 5750 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 5751 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 5752 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 5753 int rtw89_regd_init(struct rtw89_dev *rtwdev, 5754 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 5755 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 5756 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 5757 struct rtw89_traffic_stats *stats); 5758 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 5759 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5760 const struct rtw89_completion_data *data); 5761 int rtw89_core_start(struct rtw89_dev *rtwdev); 5762 void rtw89_core_stop(struct rtw89_dev *rtwdev); 5763 void rtw89_core_update_beacon_work(struct work_struct *work); 5764 void rtw89_roc_work(struct work_struct *work); 5765 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5766 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5767 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5768 const u8 *mac_addr, bool hw_scan); 5769 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5770 struct ieee80211_vif *vif, bool hw_scan); 5771 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 5772 struct rtw89_vif *rtwvif, bool active); 5773 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 5774 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 5775 5776 #endif 5777