1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_fw_blacklist; 21 struct rtw89_efuse_block_cfg; 22 struct rtw89_h2c_rf_tssi; 23 struct rtw89_fw_txpwr_track_cfg; 24 struct rtw89_phy_rfk_log_fmt; 25 struct rtw89_debugfs; 26 struct rtw89_regd_data; 27 28 extern const struct ieee80211_ops rtw89_ops; 29 30 #define MASKBYTE0 0xff 31 #define MASKBYTE1 0xff00 32 #define MASKBYTE2 0xff0000 33 #define MASKBYTE3 0xff000000 34 #define MASKBYTE4 0xff00000000ULL 35 #define MASKHWORD 0xffff0000 36 #define MASKLWORD 0x0000ffff 37 #define MASKDWORD 0xffffffff 38 #define RFREG_MASK 0xfffff 39 #define INV_RF_DATA 0xffffffff 40 #define BYPASS_CR_DATA 0xbabecafe 41 42 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 43 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100) 44 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 45 #define CFO_TRACK_MAX_USER 64 46 #define MAX_RSSI 110 47 #define RSSI_FACTOR 1 48 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 49 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 50 #define DELTA_SWINGIDX_SIZE 30 51 52 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 53 #define RTW89_RADIOTAP_ROOM_EHT \ 54 (sizeof(struct ieee80211_radiotap_tlv) + \ 55 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 56 sizeof(struct ieee80211_radiotap_tlv) + \ 57 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 58 #define RTW89_RADIOTAP_ROOM \ 59 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 60 61 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 62 #define RTW89_HTC_VARIANT_HE 3 63 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 64 #define RTW89_HTC_VARIANT_HE_CID_OM 1 65 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 66 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 67 68 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 69 enum htc_om_channel_width { 70 HTC_OM_CHANNEL_WIDTH_20 = 0, 71 HTC_OM_CHANNEL_WIDTH_40 = 1, 72 HTC_OM_CHANNEL_WIDTH_80 = 2, 73 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 74 }; 75 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 76 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 77 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 78 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 79 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 80 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 81 82 #define RTW89_TF_PAD GENMASK(11, 0) 83 #define RTW89_TF_BASIC_USER_INFO_SZ 6 84 85 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 86 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 87 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 88 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 89 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 90 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 91 92 enum rtw89_subband { 93 RTW89_CH_2G = 0, 94 RTW89_CH_5G_BAND_1 = 1, 95 /* RTW89_CH_5G_BAND_2 = 2, unused */ 96 RTW89_CH_5G_BAND_3 = 3, 97 RTW89_CH_5G_BAND_4 = 4, 98 99 RTW89_CH_6G_BAND_IDX0, /* Low */ 100 RTW89_CH_6G_BAND_IDX1, /* Low */ 101 RTW89_CH_6G_BAND_IDX2, /* Mid */ 102 RTW89_CH_6G_BAND_IDX3, /* Mid */ 103 RTW89_CH_6G_BAND_IDX4, /* High */ 104 RTW89_CH_6G_BAND_IDX5, /* High */ 105 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 106 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 107 108 RTW89_SUBBAND_NR, 109 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 110 }; 111 112 enum rtw89_gain_offset { 113 RTW89_GAIN_OFFSET_2G_CCK, 114 RTW89_GAIN_OFFSET_2G_OFDM, 115 RTW89_GAIN_OFFSET_5G_LOW, 116 RTW89_GAIN_OFFSET_5G_MID, 117 RTW89_GAIN_OFFSET_5G_HIGH, 118 RTW89_GAIN_OFFSET_6G_L0, 119 RTW89_GAIN_OFFSET_6G_L1, 120 RTW89_GAIN_OFFSET_6G_M0, 121 RTW89_GAIN_OFFSET_6G_M1, 122 RTW89_GAIN_OFFSET_6G_H0, 123 RTW89_GAIN_OFFSET_6G_H1, 124 RTW89_GAIN_OFFSET_6G_UH0, 125 RTW89_GAIN_OFFSET_6G_UH1, 126 127 RTW89_GAIN_OFFSET_NR, 128 }; 129 130 enum rtw89_hci_type { 131 RTW89_HCI_TYPE_PCIE, 132 RTW89_HCI_TYPE_USB, 133 RTW89_HCI_TYPE_SDIO, 134 135 RTW89_HCI_TYPE_NUM, 136 }; 137 138 enum rtw89_hci_dle_type { 139 RTW89_HCI_DLE_TYPE_PCIE, 140 RTW89_HCI_DLE_TYPE_USB2, 141 RTW89_HCI_DLE_TYPE_USB3, 142 RTW89_HCI_DLE_TYPE_SDIO, 143 144 RTW89_HCI_DLE_TYPE_NUM, 145 }; 146 147 enum rtw89_core_chip_id { 148 RTL8852A, 149 RTL8852B, 150 RTL8852BT, 151 RTL8852C, 152 RTL8851B, 153 RTL8922A, 154 }; 155 156 enum rtw89_chip_gen { 157 RTW89_CHIP_AX, 158 RTW89_CHIP_BE, 159 160 RTW89_CHIP_GEN_NUM, 161 }; 162 163 enum rtw89_cv { 164 CHIP_CAV, 165 CHIP_CBV, 166 CHIP_CCV, 167 CHIP_CDV, 168 CHIP_CEV, 169 CHIP_CFV, 170 CHIP_CV_MAX, 171 CHIP_CV_INVALID = CHIP_CV_MAX, 172 }; 173 174 enum rtw89_bacam_ver { 175 RTW89_BACAM_V0, 176 RTW89_BACAM_V1, 177 178 RTW89_BACAM_V0_EXT = 99, 179 }; 180 181 enum rtw89_core_tx_type { 182 RTW89_CORE_TX_TYPE_DATA, 183 RTW89_CORE_TX_TYPE_MGMT, 184 RTW89_CORE_TX_TYPE_FWCMD, 185 }; 186 187 enum rtw89_core_rx_type { 188 RTW89_CORE_RX_TYPE_WIFI = 0, 189 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 190 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 191 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 192 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 193 RTW89_CORE_RX_TYPE_SS2FW = 5, 194 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 195 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 196 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 197 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 198 RTW89_CORE_RX_TYPE_C2H = 10, 199 RTW89_CORE_RX_TYPE_CSI = 11, 200 RTW89_CORE_RX_TYPE_CQI = 12, 201 RTW89_CORE_RX_TYPE_H2C = 13, 202 RTW89_CORE_RX_TYPE_FWDL = 14, 203 }; 204 205 enum rtw89_txq_flags { 206 RTW89_TXQ_F_AMPDU = 0, 207 RTW89_TXQ_F_BLOCK_BA = 1, 208 RTW89_TXQ_F_FORBID_BA = 2, 209 }; 210 211 enum rtw89_net_type { 212 RTW89_NET_TYPE_NO_LINK = 0, 213 RTW89_NET_TYPE_AD_HOC = 1, 214 RTW89_NET_TYPE_INFRA = 2, 215 RTW89_NET_TYPE_AP_MODE = 3, 216 }; 217 218 enum rtw89_wifi_role { 219 RTW89_WIFI_ROLE_NONE, 220 RTW89_WIFI_ROLE_STATION, 221 RTW89_WIFI_ROLE_AP, 222 RTW89_WIFI_ROLE_AP_VLAN, 223 RTW89_WIFI_ROLE_ADHOC, 224 RTW89_WIFI_ROLE_ADHOC_MASTER, 225 RTW89_WIFI_ROLE_MESH_POINT, 226 RTW89_WIFI_ROLE_MONITOR, 227 RTW89_WIFI_ROLE_P2P_DEVICE, 228 RTW89_WIFI_ROLE_P2P_CLIENT, 229 RTW89_WIFI_ROLE_P2P_GO, 230 RTW89_WIFI_ROLE_NAN, 231 RTW89_WIFI_ROLE_MLME_MAX 232 }; 233 234 enum rtw89_upd_mode { 235 RTW89_ROLE_CREATE, 236 RTW89_ROLE_REMOVE, 237 RTW89_ROLE_TYPE_CHANGE, 238 RTW89_ROLE_INFO_CHANGE, 239 RTW89_ROLE_CON_DISCONN, 240 RTW89_ROLE_BAND_SW, 241 RTW89_ROLE_FW_RESTORE, 242 }; 243 244 enum rtw89_self_role { 245 RTW89_SELF_ROLE_CLIENT, 246 RTW89_SELF_ROLE_AP, 247 RTW89_SELF_ROLE_AP_CLIENT 248 }; 249 250 enum rtw89_msk_sO_el { 251 RTW89_NO_MSK, 252 RTW89_SMA, 253 RTW89_TMA, 254 RTW89_BSSID 255 }; 256 257 enum rtw89_sch_tx_sel { 258 RTW89_SCH_TX_SEL_ALL, 259 RTW89_SCH_TX_SEL_HIQ, 260 RTW89_SCH_TX_SEL_MG0, 261 RTW89_SCH_TX_SEL_MACID, 262 }; 263 264 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 265 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 266 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 267 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 268 */ 269 enum rtw89_add_cam_sec_mode { 270 RTW89_ADDR_CAM_SEC_NONE = 0, 271 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 272 RTW89_ADDR_CAM_SEC_NORMAL = 2, 273 RTW89_ADDR_CAM_SEC_4GROUP = 3, 274 }; 275 276 enum rtw89_sec_key_type { 277 RTW89_SEC_KEY_TYPE_NONE = 0, 278 RTW89_SEC_KEY_TYPE_WEP40 = 1, 279 RTW89_SEC_KEY_TYPE_WEP104 = 2, 280 RTW89_SEC_KEY_TYPE_TKIP = 3, 281 RTW89_SEC_KEY_TYPE_WAPI = 4, 282 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 283 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 284 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 285 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 286 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 287 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 288 }; 289 290 enum rtw89_port { 291 RTW89_PORT_0 = 0, 292 RTW89_PORT_1 = 1, 293 RTW89_PORT_2 = 2, 294 RTW89_PORT_3 = 3, 295 RTW89_PORT_4 = 4, 296 RTW89_PORT_NUM 297 }; 298 299 enum rtw89_band { 300 RTW89_BAND_2G = 0, 301 RTW89_BAND_5G = 1, 302 RTW89_BAND_6G = 2, 303 RTW89_BAND_NUM, 304 }; 305 306 enum rtw89_hw_rate { 307 RTW89_HW_RATE_CCK1 = 0x0, 308 RTW89_HW_RATE_CCK2 = 0x1, 309 RTW89_HW_RATE_CCK5_5 = 0x2, 310 RTW89_HW_RATE_CCK11 = 0x3, 311 RTW89_HW_RATE_OFDM6 = 0x4, 312 RTW89_HW_RATE_OFDM9 = 0x5, 313 RTW89_HW_RATE_OFDM12 = 0x6, 314 RTW89_HW_RATE_OFDM18 = 0x7, 315 RTW89_HW_RATE_OFDM24 = 0x8, 316 RTW89_HW_RATE_OFDM36 = 0x9, 317 RTW89_HW_RATE_OFDM48 = 0xA, 318 RTW89_HW_RATE_OFDM54 = 0xB, 319 RTW89_HW_RATE_MCS0 = 0x80, 320 RTW89_HW_RATE_MCS1 = 0x81, 321 RTW89_HW_RATE_MCS2 = 0x82, 322 RTW89_HW_RATE_MCS3 = 0x83, 323 RTW89_HW_RATE_MCS4 = 0x84, 324 RTW89_HW_RATE_MCS5 = 0x85, 325 RTW89_HW_RATE_MCS6 = 0x86, 326 RTW89_HW_RATE_MCS7 = 0x87, 327 RTW89_HW_RATE_MCS8 = 0x88, 328 RTW89_HW_RATE_MCS9 = 0x89, 329 RTW89_HW_RATE_MCS10 = 0x8A, 330 RTW89_HW_RATE_MCS11 = 0x8B, 331 RTW89_HW_RATE_MCS12 = 0x8C, 332 RTW89_HW_RATE_MCS13 = 0x8D, 333 RTW89_HW_RATE_MCS14 = 0x8E, 334 RTW89_HW_RATE_MCS15 = 0x8F, 335 RTW89_HW_RATE_MCS16 = 0x90, 336 RTW89_HW_RATE_MCS17 = 0x91, 337 RTW89_HW_RATE_MCS18 = 0x92, 338 RTW89_HW_RATE_MCS19 = 0x93, 339 RTW89_HW_RATE_MCS20 = 0x94, 340 RTW89_HW_RATE_MCS21 = 0x95, 341 RTW89_HW_RATE_MCS22 = 0x96, 342 RTW89_HW_RATE_MCS23 = 0x97, 343 RTW89_HW_RATE_MCS24 = 0x98, 344 RTW89_HW_RATE_MCS25 = 0x99, 345 RTW89_HW_RATE_MCS26 = 0x9A, 346 RTW89_HW_RATE_MCS27 = 0x9B, 347 RTW89_HW_RATE_MCS28 = 0x9C, 348 RTW89_HW_RATE_MCS29 = 0x9D, 349 RTW89_HW_RATE_MCS30 = 0x9E, 350 RTW89_HW_RATE_MCS31 = 0x9F, 351 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 352 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 353 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 354 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 355 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 356 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 357 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 358 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 359 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 360 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 361 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 362 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 363 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 364 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 365 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 366 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 367 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 368 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 369 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 370 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 371 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 372 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 373 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 374 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 375 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 376 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 377 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 378 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 379 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 380 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 381 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 382 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 383 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 384 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 385 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 386 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 387 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 388 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 389 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 390 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 391 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 392 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 393 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 394 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 395 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 396 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 397 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 398 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 399 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 400 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 401 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 402 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 403 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 404 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 405 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 406 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 407 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 408 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 409 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 410 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 411 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 412 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 413 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 414 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 415 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 416 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 417 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 418 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 419 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 420 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 421 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 422 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 423 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 424 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 425 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 426 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 427 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 428 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 429 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 430 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 431 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 432 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 433 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 434 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 435 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 436 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 437 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 438 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 439 440 RTW89_HW_RATE_V1_MCS0 = 0x100, 441 RTW89_HW_RATE_V1_MCS1 = 0x101, 442 RTW89_HW_RATE_V1_MCS2 = 0x102, 443 RTW89_HW_RATE_V1_MCS3 = 0x103, 444 RTW89_HW_RATE_V1_MCS4 = 0x104, 445 RTW89_HW_RATE_V1_MCS5 = 0x105, 446 RTW89_HW_RATE_V1_MCS6 = 0x106, 447 RTW89_HW_RATE_V1_MCS7 = 0x107, 448 RTW89_HW_RATE_V1_MCS8 = 0x108, 449 RTW89_HW_RATE_V1_MCS9 = 0x109, 450 RTW89_HW_RATE_V1_MCS10 = 0x10A, 451 RTW89_HW_RATE_V1_MCS11 = 0x10B, 452 RTW89_HW_RATE_V1_MCS12 = 0x10C, 453 RTW89_HW_RATE_V1_MCS13 = 0x10D, 454 RTW89_HW_RATE_V1_MCS14 = 0x10E, 455 RTW89_HW_RATE_V1_MCS15 = 0x10F, 456 RTW89_HW_RATE_V1_MCS16 = 0x110, 457 RTW89_HW_RATE_V1_MCS17 = 0x111, 458 RTW89_HW_RATE_V1_MCS18 = 0x112, 459 RTW89_HW_RATE_V1_MCS19 = 0x113, 460 RTW89_HW_RATE_V1_MCS20 = 0x114, 461 RTW89_HW_RATE_V1_MCS21 = 0x115, 462 RTW89_HW_RATE_V1_MCS22 = 0x116, 463 RTW89_HW_RATE_V1_MCS23 = 0x117, 464 RTW89_HW_RATE_V1_MCS24 = 0x118, 465 RTW89_HW_RATE_V1_MCS25 = 0x119, 466 RTW89_HW_RATE_V1_MCS26 = 0x11A, 467 RTW89_HW_RATE_V1_MCS27 = 0x11B, 468 RTW89_HW_RATE_V1_MCS28 = 0x11C, 469 RTW89_HW_RATE_V1_MCS29 = 0x11D, 470 RTW89_HW_RATE_V1_MCS30 = 0x11E, 471 RTW89_HW_RATE_V1_MCS31 = 0x11F, 472 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 473 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 474 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 475 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 476 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 477 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 478 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 479 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 480 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 481 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 482 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 483 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 484 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 485 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 486 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 487 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 488 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 489 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 490 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 491 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 492 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 493 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 494 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 495 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 496 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 497 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 498 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 499 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 500 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 501 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 502 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 503 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 504 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 505 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 506 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 507 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 508 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 509 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 510 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 511 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 512 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 513 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 514 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 515 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 516 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 517 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 518 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 519 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 520 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 521 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 522 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 523 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 524 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 525 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 526 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 527 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 528 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 529 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 530 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 531 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 532 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 533 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 534 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 535 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 536 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 537 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 538 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 539 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 540 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 541 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 542 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 543 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 544 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 545 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 546 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 547 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 548 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 549 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 550 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 551 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 552 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 553 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 554 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 555 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 556 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 557 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 558 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 559 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 560 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 561 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 562 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 563 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 564 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 565 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 566 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 567 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 570 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 571 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 572 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 573 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 574 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 575 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 576 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 577 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 578 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 579 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 580 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 581 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 582 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 583 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 584 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 585 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 586 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 587 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 588 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 589 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 590 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 591 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 592 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 593 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 594 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 595 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 596 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 597 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 598 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 599 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 600 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 601 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 602 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 603 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 604 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 605 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 606 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 607 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 608 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 609 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 610 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 611 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 612 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 613 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 614 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 615 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 616 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 617 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 618 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 619 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 620 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 621 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 622 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 623 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 624 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 625 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 626 627 RTW89_HW_RATE_NR, 628 RTW89_HW_RATE_INVAL, 629 630 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 631 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 632 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 633 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 634 }; 635 636 /* 2G channels, 637 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 638 */ 639 #define RTW89_2G_CH_NUM 14 640 641 /* 5G channels, 642 * 36, 38, 40, 42, 44, 46, 48, 50, 643 * 52, 54, 56, 58, 60, 62, 64, 644 * 100, 102, 104, 106, 108, 110, 112, 114, 645 * 116, 118, 120, 122, 124, 126, 128, 130, 646 * 132, 134, 136, 138, 140, 142, 144, 647 * 149, 151, 153, 155, 157, 159, 161, 163, 648 * 165, 167, 169, 171, 173, 175, 177 649 */ 650 #define RTW89_5G_CH_NUM 53 651 652 /* 6G channels, 653 * 1, 3, 5, 7, 9, 11, 13, 15, 654 * 17, 19, 21, 23, 25, 27, 29, 33, 655 * 35, 37, 39, 41, 43, 45, 47, 49, 656 * 51, 53, 55, 57, 59, 61, 65, 67, 657 * 69, 71, 73, 75, 77, 79, 81, 83, 658 * 85, 87, 89, 91, 93, 97, 99, 101, 659 * 103, 105, 107, 109, 111, 113, 115, 117, 660 * 119, 121, 123, 125, 129, 131, 133, 135, 661 * 137, 139, 141, 143, 145, 147, 149, 151, 662 * 153, 155, 157, 161, 163, 165, 167, 169, 663 * 171, 173, 175, 177, 179, 181, 183, 185, 664 * 187, 189, 193, 195, 197, 199, 201, 203, 665 * 205, 207, 209, 211, 213, 215, 217, 219, 666 * 221, 225, 227, 229, 231, 233, 235, 237, 667 * 239, 241, 243, 245, 247, 249, 251, 253, 668 */ 669 #define RTW89_6G_CH_NUM 120 670 671 enum rtw89_rate_section { 672 RTW89_RS_CCK, 673 RTW89_RS_OFDM, 674 RTW89_RS_MCS, /* for HT/VHT/HE */ 675 RTW89_RS_HEDCM, 676 RTW89_RS_OFFSET, 677 RTW89_RS_NUM, 678 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 679 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 680 }; 681 682 enum rtw89_rate_offset_indexes { 683 RTW89_RATE_OFFSET_HE, 684 RTW89_RATE_OFFSET_VHT, 685 RTW89_RATE_OFFSET_HT, 686 RTW89_RATE_OFFSET_OFDM, 687 RTW89_RATE_OFFSET_CCK, 688 RTW89_RATE_OFFSET_DLRU_EHT, 689 RTW89_RATE_OFFSET_DLRU_HE, 690 RTW89_RATE_OFFSET_EHT, 691 __RTW89_RATE_OFFSET_NUM, 692 693 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 694 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 695 }; 696 697 enum rtw89_rate_num { 698 RTW89_RATE_CCK_NUM = 4, 699 RTW89_RATE_OFDM_NUM = 8, 700 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 701 702 RTW89_RATE_MCS_NUM_AX = 12, 703 RTW89_RATE_MCS_NUM_BE = 16, 704 __RTW89_RATE_MCS_NUM = 16, 705 }; 706 707 enum rtw89_nss { 708 RTW89_NSS_1 = 0, 709 RTW89_NSS_2 = 1, 710 /* HE DCM only support 1ss and 2ss */ 711 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 712 RTW89_NSS_3 = 2, 713 RTW89_NSS_4 = 3, 714 RTW89_NSS_NUM, 715 }; 716 717 enum rtw89_ntx { 718 RTW89_1TX = 0, 719 RTW89_2TX = 1, 720 RTW89_NTX_NUM, 721 }; 722 723 enum rtw89_beamforming_type { 724 RTW89_NONBF = 0, 725 RTW89_BF = 1, 726 RTW89_BF_NUM, 727 }; 728 729 enum rtw89_ofdma_type { 730 RTW89_NON_OFDMA = 0, 731 RTW89_OFDMA = 1, 732 RTW89_OFDMA_NUM, 733 }; 734 735 /* neither insert new in the middle, nor change any given definition */ 736 enum rtw89_regulation_type { 737 RTW89_WW = 0, 738 RTW89_ETSI = 1, 739 RTW89_FCC = 2, 740 RTW89_MKK = 3, 741 RTW89_NA = 4, 742 RTW89_IC = 5, 743 RTW89_KCC = 6, 744 RTW89_ACMA = 7, 745 RTW89_NCC = 8, 746 RTW89_MEXICO = 9, 747 RTW89_CHILE = 10, 748 RTW89_UKRAINE = 11, 749 RTW89_CN = 12, 750 RTW89_QATAR = 13, 751 RTW89_UK = 14, 752 RTW89_THAILAND = 15, 753 RTW89_REGD_NUM, 754 }; 755 756 enum rtw89_reg_6ghz_power { 757 RTW89_REG_6GHZ_POWER_VLP = 0, 758 RTW89_REG_6GHZ_POWER_LPI = 1, 759 RTW89_REG_6GHZ_POWER_STD = 2, 760 761 NUM_OF_RTW89_REG_6GHZ_POWER, 762 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 763 }; 764 765 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 766 767 /* calculate based on ieee80211 Transmit Power Envelope */ 768 struct rtw89_reg_6ghz_tpe { 769 bool valid; 770 s8 constraint; /* unit: dBm */ 771 }; 772 773 enum rtw89_fw_pkt_ofld_type { 774 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 775 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 776 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 777 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 778 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 779 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 780 RTW89_PKT_OFLD_TYPE_NDP = 6, 781 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 782 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 783 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 784 RTW89_PKT_OFLD_TYPE_NUM, 785 }; 786 787 struct rtw89_txpwr_byrate { 788 s8 cck[RTW89_RATE_CCK_NUM]; 789 s8 ofdm[RTW89_RATE_OFDM_NUM]; 790 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 791 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 792 s8 offset[__RTW89_RATE_OFFSET_NUM]; 793 s8 trap; 794 }; 795 796 struct rtw89_rate_desc { 797 enum rtw89_nss nss; 798 enum rtw89_rate_section rs; 799 enum rtw89_ofdma_type ofdma; 800 u8 idx; 801 }; 802 803 #define PHY_STS_HDR_LEN 8 804 #define RF_PATH_MAX 4 805 #define RTW89_MAX_PPDU_CNT 8 806 struct rtw89_rx_phy_ppdu { 807 void *buf; 808 u32 len; 809 u8 rssi_avg; 810 u8 rssi[RF_PATH_MAX]; 811 u8 mac_id; 812 u8 chan_idx; 813 u8 phy_idx; 814 u8 ie; 815 u16 rate; 816 u8 rpl_avg; 817 u8 rpl_path[RF_PATH_MAX]; 818 u8 rpl_fd[RF_PATH_MAX]; 819 u8 bw_idx; 820 u8 rx_path_en; 821 struct { 822 bool has; 823 u8 avg_snr; 824 u8 evm_max; 825 u8 evm_min; 826 } ofdm; 827 bool has_data; 828 bool has_bcn; 829 bool ldpc; 830 bool stbc; 831 bool to_self; 832 bool valid; 833 bool hdr_2_en; 834 }; 835 836 enum rtw89_mac_idx { 837 RTW89_MAC_0 = 0, 838 RTW89_MAC_1 = 1, 839 RTW89_MAC_NUM, 840 }; 841 842 enum rtw89_phy_idx { 843 RTW89_PHY_0 = 0, 844 RTW89_PHY_1 = 1, 845 RTW89_PHY_NUM, 846 }; 847 848 #define __RTW89_MLD_MAX_LINK_NUM 2 849 #define RTW89_MLD_NON_STA_LINK_NUM 1 850 851 enum rtw89_chanctx_idx { 852 RTW89_CHANCTX_0 = 0, 853 RTW89_CHANCTX_1 = 1, 854 855 NUM_OF_RTW89_CHANCTX, 856 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 857 }; 858 859 enum rtw89_rf_path { 860 RF_PATH_A = 0, 861 RF_PATH_B = 1, 862 RF_PATH_C = 2, 863 RF_PATH_D = 3, 864 RF_PATH_AB, 865 RF_PATH_AC, 866 RF_PATH_AD, 867 RF_PATH_BC, 868 RF_PATH_BD, 869 RF_PATH_CD, 870 RF_PATH_ABC, 871 RF_PATH_ABD, 872 RF_PATH_ACD, 873 RF_PATH_BCD, 874 RF_PATH_ABCD, 875 }; 876 877 enum rtw89_rf_path_bit { 878 RF_A = BIT(0), 879 RF_B = BIT(1), 880 RF_C = BIT(2), 881 RF_D = BIT(3), 882 883 RF_AB = (RF_A | RF_B), 884 RF_AC = (RF_A | RF_C), 885 RF_AD = (RF_A | RF_D), 886 RF_BC = (RF_B | RF_C), 887 RF_BD = (RF_B | RF_D), 888 RF_CD = (RF_C | RF_D), 889 890 RF_ABC = (RF_A | RF_B | RF_C), 891 RF_ABD = (RF_A | RF_B | RF_D), 892 RF_ACD = (RF_A | RF_C | RF_D), 893 RF_BCD = (RF_B | RF_C | RF_D), 894 895 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 896 }; 897 898 enum rtw89_bandwidth { 899 RTW89_CHANNEL_WIDTH_20 = 0, 900 RTW89_CHANNEL_WIDTH_40 = 1, 901 RTW89_CHANNEL_WIDTH_80 = 2, 902 RTW89_CHANNEL_WIDTH_160 = 3, 903 RTW89_CHANNEL_WIDTH_320 = 4, 904 905 /* keep index order above */ 906 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 907 908 RTW89_CHANNEL_WIDTH_80_80 = 5, 909 RTW89_CHANNEL_WIDTH_5 = 6, 910 RTW89_CHANNEL_WIDTH_10 = 7, 911 }; 912 913 enum rtw89_ps_mode { 914 RTW89_PS_MODE_NONE = 0, 915 RTW89_PS_MODE_RFOFF = 1, 916 RTW89_PS_MODE_CLK_GATED = 2, 917 RTW89_PS_MODE_PWR_GATED = 3, 918 }; 919 920 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 921 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 922 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 923 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 924 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 925 926 enum rtw89_pe_duration { 927 RTW89_PE_DURATION_0 = 0, 928 RTW89_PE_DURATION_8 = 1, 929 RTW89_PE_DURATION_16 = 2, 930 RTW89_PE_DURATION_16_20 = 3, 931 }; 932 933 enum rtw89_ru_bandwidth { 934 RTW89_RU26 = 0, 935 RTW89_RU52 = 1, 936 RTW89_RU106 = 2, 937 RTW89_RU52_26 = 3, 938 RTW89_RU106_26 = 4, 939 RTW89_RU_NUM, 940 }; 941 942 enum rtw89_sc_offset { 943 RTW89_SC_DONT_CARE = 0, 944 RTW89_SC_20_UPPER = 1, 945 RTW89_SC_20_LOWER = 2, 946 RTW89_SC_20_UPMOST = 3, 947 RTW89_SC_20_LOWEST = 4, 948 RTW89_SC_20_UP2X = 5, 949 RTW89_SC_20_LOW2X = 6, 950 RTW89_SC_20_UP3X = 7, 951 RTW89_SC_20_LOW3X = 8, 952 RTW89_SC_40_UPPER = 9, 953 RTW89_SC_40_LOWER = 10, 954 }; 955 956 /* only mgd features can be added to the enum */ 957 enum rtw89_wow_flags { 958 RTW89_WOW_FLAG_EN_MAGIC_PKT, 959 RTW89_WOW_FLAG_EN_REKEY_PKT, 960 RTW89_WOW_FLAG_EN_DISCONNECT, 961 RTW89_WOW_FLAG_EN_PATTERN, 962 RTW89_WOW_FLAG_NUM, 963 }; 964 965 struct rtw89_chan { 966 u8 channel; 967 u8 primary_channel; 968 enum rtw89_band band_type; 969 enum rtw89_bandwidth band_width; 970 971 /* The follow-up are derived from the above. We must ensure that it 972 * is assigned correctly in rtw89_chan_create() if new one is added. 973 */ 974 u32 freq; 975 enum rtw89_subband subband_type; 976 enum rtw89_sc_offset pri_ch_idx; 977 u8 pri_sb_idx; 978 }; 979 980 struct rtw89_chan_rcd { 981 u8 prev_primary_channel; 982 enum rtw89_band prev_band_type; 983 bool band_changed; 984 }; 985 986 struct rtw89_channel_help_params { 987 u32 tx_en; 988 }; 989 990 struct rtw89_port_reg { 991 u32 port_cfg; 992 u32 tbtt_prohib; 993 u32 bcn_area; 994 u32 bcn_early; 995 u32 tbtt_early; 996 u32 tbtt_agg; 997 u32 bcn_space; 998 u32 bcn_forcetx; 999 u32 bcn_err_cnt; 1000 u32 bcn_err_flag; 1001 u32 dtim_ctrl; 1002 u32 tbtt_shift; 1003 u32 bcn_cnt_tmr; 1004 u32 tsftr_l; 1005 u32 tsftr_h; 1006 u32 md_tsft; 1007 u32 bss_color; 1008 u32 mbssid; 1009 u32 mbssid_drop; 1010 u32 tsf_sync; 1011 u32 ptcl_dbg; 1012 u32 ptcl_dbg_info; 1013 u32 bcn_drop_all; 1014 u32 hiq_win[RTW89_PORT_NUM]; 1015 }; 1016 1017 struct rtw89_txwd_body { 1018 __le32 dword0; 1019 __le32 dword1; 1020 __le32 dword2; 1021 __le32 dword3; 1022 __le32 dword4; 1023 __le32 dword5; 1024 } __packed; 1025 1026 struct rtw89_txwd_body_v1 { 1027 __le32 dword0; 1028 __le32 dword1; 1029 __le32 dword2; 1030 __le32 dword3; 1031 __le32 dword4; 1032 __le32 dword5; 1033 __le32 dword6; 1034 __le32 dword7; 1035 } __packed; 1036 1037 struct rtw89_txwd_body_v2 { 1038 __le32 dword0; 1039 __le32 dword1; 1040 __le32 dword2; 1041 __le32 dword3; 1042 __le32 dword4; 1043 __le32 dword5; 1044 __le32 dword6; 1045 __le32 dword7; 1046 } __packed; 1047 1048 struct rtw89_txwd_info { 1049 __le32 dword0; 1050 __le32 dword1; 1051 __le32 dword2; 1052 __le32 dword3; 1053 __le32 dword4; 1054 __le32 dword5; 1055 } __packed; 1056 1057 struct rtw89_txwd_info_v2 { 1058 __le32 dword0; 1059 __le32 dword1; 1060 __le32 dword2; 1061 __le32 dword3; 1062 __le32 dword4; 1063 __le32 dword5; 1064 __le32 dword6; 1065 __le32 dword7; 1066 } __packed; 1067 1068 struct rtw89_rx_desc_info { 1069 u16 pkt_size; 1070 u8 pkt_type; 1071 u8 drv_info_size; 1072 u8 phy_rpt_size; 1073 u8 hdr_cnv_size; 1074 u8 shift; 1075 u8 wl_hd_iv_len; 1076 bool long_rxdesc; 1077 bool bb_sel; 1078 bool mac_info_valid; 1079 u16 data_rate; 1080 u8 gi_ltf; 1081 u8 bw; 1082 u32 free_run_cnt; 1083 u8 user_id; 1084 bool sr_en; 1085 u8 ppdu_cnt; 1086 u8 ppdu_type; 1087 bool icv_err; 1088 bool crc32_err; 1089 bool hw_dec; 1090 bool sw_dec; 1091 bool addr1_match; 1092 u8 frag; 1093 u16 seq; 1094 u8 frame_type; 1095 u8 rx_pl_id; 1096 bool addr_cam_valid; 1097 u8 addr_cam_id; 1098 u8 sec_cam_id; 1099 u8 mac_id; 1100 u16 offset; 1101 u16 rxd_len; 1102 bool ready; 1103 u16 rssi; 1104 }; 1105 1106 struct rtw89_rxdesc_short { 1107 __le32 dword0; 1108 __le32 dword1; 1109 __le32 dword2; 1110 __le32 dword3; 1111 } __packed; 1112 1113 struct rtw89_rxdesc_short_v2 { 1114 __le32 dword0; 1115 __le32 dword1; 1116 __le32 dword2; 1117 __le32 dword3; 1118 __le32 dword4; 1119 __le32 dword5; 1120 } __packed; 1121 1122 struct rtw89_rxdesc_long { 1123 __le32 dword0; 1124 __le32 dword1; 1125 __le32 dword2; 1126 __le32 dword3; 1127 __le32 dword4; 1128 __le32 dword5; 1129 __le32 dword6; 1130 __le32 dword7; 1131 } __packed; 1132 1133 struct rtw89_rxdesc_long_v2 { 1134 __le32 dword0; 1135 __le32 dword1; 1136 __le32 dword2; 1137 __le32 dword3; 1138 __le32 dword4; 1139 __le32 dword5; 1140 __le32 dword6; 1141 __le32 dword7; 1142 __le32 dword8; 1143 __le32 dword9; 1144 } __packed; 1145 1146 struct rtw89_rxdesc_phy_rpt_v2 { 1147 __le32 dword0; 1148 __le32 dword1; 1149 } __packed; 1150 1151 struct rtw89_tx_desc_info { 1152 u16 pkt_size; 1153 u8 wp_offset; 1154 u8 mac_id; 1155 u8 qsel; 1156 u8 ch_dma; 1157 u8 hdr_llc_len; 1158 bool is_bmc; 1159 bool en_wd_info; 1160 bool wd_page; 1161 bool use_rate; 1162 bool dis_data_fb; 1163 bool tid_indicate; 1164 bool agg_en; 1165 bool bk; 1166 u8 ampdu_density; 1167 u8 ampdu_num; 1168 bool sec_en; 1169 u8 addr_info_nr; 1170 u8 sec_keyid; 1171 u8 sec_type; 1172 u8 sec_cam_idx; 1173 u8 sec_seq[6]; 1174 u16 data_rate; 1175 u16 data_retry_lowest_rate; 1176 bool fw_dl; 1177 u16 seq; 1178 bool a_ctrl_bsr; 1179 u8 hw_ssn_sel; 1180 #define RTW89_MGMT_HW_SSN_SEL 1 1181 u8 hw_seq_mode; 1182 #define RTW89_MGMT_HW_SEQ_MODE 1 1183 bool hiq; 1184 u8 port; 1185 bool er_cap; 1186 bool stbc; 1187 bool ldpc; 1188 bool upd_wlan_hdr; 1189 bool mlo; 1190 bool sw_mld; 1191 }; 1192 1193 struct rtw89_core_tx_request { 1194 enum rtw89_core_tx_type tx_type; 1195 1196 struct sk_buff *skb; 1197 struct ieee80211_vif *vif; 1198 struct ieee80211_sta *sta; 1199 struct rtw89_vif_link *rtwvif_link; 1200 struct rtw89_sta_link *rtwsta_link; 1201 struct rtw89_tx_desc_info desc_info; 1202 }; 1203 1204 struct rtw89_txq { 1205 struct list_head list; 1206 unsigned long flags; 1207 int wait_cnt; 1208 }; 1209 1210 struct rtw89_mac_ax_gnt { 1211 u8 gnt_bt_sw_en; 1212 u8 gnt_bt; 1213 u8 gnt_wl_sw_en; 1214 u8 gnt_wl; 1215 } __packed; 1216 1217 struct rtw89_mac_ax_wl_act { 1218 u8 wlan_act_en; 1219 u8 wlan_act; 1220 } __packed; 1221 1222 #define RTW89_MAC_AX_COEX_GNT_NR 2 1223 struct rtw89_mac_ax_coex_gnt { 1224 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1225 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1226 }; 1227 1228 enum rtw89_btc_ncnt { 1229 BTC_NCNT_POWER_ON = 0x0, 1230 BTC_NCNT_POWER_OFF, 1231 BTC_NCNT_INIT_COEX, 1232 BTC_NCNT_SCAN_START, 1233 BTC_NCNT_SCAN_FINISH, 1234 BTC_NCNT_SPECIAL_PACKET, 1235 BTC_NCNT_SWITCH_BAND, 1236 BTC_NCNT_RFK_TIMEOUT, 1237 BTC_NCNT_SHOW_COEX_INFO, 1238 BTC_NCNT_ROLE_INFO, 1239 BTC_NCNT_CONTROL, 1240 BTC_NCNT_RADIO_STATE, 1241 BTC_NCNT_CUSTOMERIZE, 1242 BTC_NCNT_WL_RFK, 1243 BTC_NCNT_WL_STA, 1244 BTC_NCNT_WL_STA_LAST, 1245 BTC_NCNT_FWINFO, 1246 BTC_NCNT_TIMER, 1247 BTC_NCNT_SWITCH_CHBW, 1248 BTC_NCNT_RESUME_DL_FW, 1249 BTC_NCNT_COUNTRYCODE, 1250 BTC_NCNT_NUM, 1251 }; 1252 1253 enum rtw89_btc_btinfo { 1254 BTC_BTINFO_L0 = 0, 1255 BTC_BTINFO_L1, 1256 BTC_BTINFO_L2, 1257 BTC_BTINFO_L3, 1258 BTC_BTINFO_H0, 1259 BTC_BTINFO_H1, 1260 BTC_BTINFO_H2, 1261 BTC_BTINFO_H3, 1262 BTC_BTINFO_MAX 1263 }; 1264 1265 enum rtw89_btc_dcnt { 1266 BTC_DCNT_RUN = 0x0, 1267 BTC_DCNT_CX_RUNINFO, 1268 BTC_DCNT_RPT, 1269 BTC_DCNT_RPT_HANG, 1270 BTC_DCNT_CYCLE, 1271 BTC_DCNT_CYCLE_HANG, 1272 BTC_DCNT_W1, 1273 BTC_DCNT_W1_HANG, 1274 BTC_DCNT_B1, 1275 BTC_DCNT_B1_HANG, 1276 BTC_DCNT_TDMA_NONSYNC, 1277 BTC_DCNT_SLOT_NONSYNC, 1278 BTC_DCNT_BTCNT_HANG, 1279 BTC_DCNT_BTTX_HANG, 1280 BTC_DCNT_WL_SLOT_DRIFT, 1281 BTC_DCNT_WL_STA_LAST, 1282 BTC_DCNT_BT_SLOT_DRIFT, 1283 BTC_DCNT_BT_SLOT_FLOOD, 1284 BTC_DCNT_FDDT_TRIG, 1285 BTC_DCNT_E2G, 1286 BTC_DCNT_E2G_HANG, 1287 BTC_DCNT_WL_FW_VER_MATCH, 1288 BTC_DCNT_NULL_TX_FAIL, 1289 BTC_DCNT_WL_STA_NTFY, 1290 BTC_DCNT_NUM, 1291 }; 1292 1293 enum rtw89_btc_wl_state_cnt { 1294 BTC_WCNT_SCANAP = 0x0, 1295 BTC_WCNT_DHCP, 1296 BTC_WCNT_EAPOL, 1297 BTC_WCNT_ARP, 1298 BTC_WCNT_SCBDUPDATE, 1299 BTC_WCNT_RFK_REQ, 1300 BTC_WCNT_RFK_GO, 1301 BTC_WCNT_RFK_REJECT, 1302 BTC_WCNT_RFK_TIMEOUT, 1303 BTC_WCNT_CH_UPDATE, 1304 BTC_WCNT_DBCC_ALL_2G, 1305 BTC_WCNT_DBCC_CHG, 1306 BTC_WCNT_RX_OK_LAST, 1307 BTC_WCNT_RX_OK_LAST2S, 1308 BTC_WCNT_RX_ERR_LAST, 1309 BTC_WCNT_RX_ERR_LAST2S, 1310 BTC_WCNT_RX_LAST, 1311 BTC_WCNT_NUM 1312 }; 1313 1314 enum rtw89_btc_bt_state_cnt { 1315 BTC_BCNT_RETRY = 0x0, 1316 BTC_BCNT_REINIT, 1317 BTC_BCNT_REENABLE, 1318 BTC_BCNT_SCBDREAD, 1319 BTC_BCNT_RELINK, 1320 BTC_BCNT_IGNOWL, 1321 BTC_BCNT_INQPAG, 1322 BTC_BCNT_INQ, 1323 BTC_BCNT_PAGE, 1324 BTC_BCNT_ROLESW, 1325 BTC_BCNT_AFH, 1326 BTC_BCNT_INFOUPDATE, 1327 BTC_BCNT_INFOSAME, 1328 BTC_BCNT_SCBDUPDATE, 1329 BTC_BCNT_HIPRI_TX, 1330 BTC_BCNT_HIPRI_RX, 1331 BTC_BCNT_LOPRI_TX, 1332 BTC_BCNT_LOPRI_RX, 1333 BTC_BCNT_POLUT, 1334 BTC_BCNT_POLUT_NOW, 1335 BTC_BCNT_POLUT_DIFF, 1336 BTC_BCNT_RATECHG, 1337 BTC_BCNT_BTTXPWR_UPDATE, 1338 BTC_BCNT_NUM, 1339 }; 1340 1341 enum rtw89_btc_bt_profile { 1342 BTC_BT_NOPROFILE = 0, 1343 BTC_BT_HFP = BIT(0), 1344 BTC_BT_HID = BIT(1), 1345 BTC_BT_A2DP = BIT(2), 1346 BTC_BT_PAN = BIT(3), 1347 BTC_PROFILE_MAX = 4, 1348 }; 1349 1350 struct rtw89_btc_ant_info { 1351 u8 type; /* shared, dedicated */ 1352 u8 num; 1353 u8 isolation; 1354 1355 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1356 u8 diversity: 1; 1357 u8 btg_pos: 2; 1358 u8 stream_cnt: 4; 1359 }; 1360 1361 struct rtw89_btc_ant_info_v7 { 1362 u8 type; /* shared, dedicated(non-shared) */ 1363 u8 num; /* antenna count */ 1364 u8 isolation; 1365 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1366 1367 u8 diversity; /* only for wifi use 1-antenna */ 1368 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1369 u8 stream_cnt; /* spatial_stream count */ 1370 u8 rsvd; 1371 } __packed; 1372 1373 enum rtw89_tfc_dir { 1374 RTW89_TFC_UL, 1375 RTW89_TFC_DL, 1376 }; 1377 1378 struct rtw89_btc_wl_smap { 1379 u32 busy: 1; 1380 u32 scan: 1; 1381 u32 connecting: 1; 1382 u32 roaming: 1; 1383 u32 dbccing: 1; 1384 u32 _4way: 1; 1385 u32 rf_off: 1; 1386 u32 lps: 2; 1387 u32 ips: 1; 1388 u32 init_ok: 1; 1389 u32 traffic_dir : 2; 1390 u32 rf_off_pre: 1; 1391 u32 lps_pre: 2; 1392 u32 lps_exiting: 1; 1393 u32 emlsr: 1; 1394 }; 1395 1396 enum rtw89_tfc_interval { 1397 RTW89_TFC_INTERVAL_100MS, 1398 RTW89_TFC_INTERVAL_2SEC, 1399 }; 1400 1401 enum rtw89_tfc_lv { 1402 RTW89_TFC_IDLE, 1403 RTW89_TFC_ULTRA_LOW, 1404 RTW89_TFC_LOW, 1405 RTW89_TFC_MID, 1406 RTW89_TFC_HIGH, 1407 }; 1408 1409 DECLARE_EWMA(tp, 10, 2); 1410 1411 struct rtw89_traffic_stats { 1412 /* units in bytes */ 1413 u64 tx_unicast; 1414 u64 rx_unicast; 1415 u32 tx_avg_len; 1416 u32 rx_avg_len; 1417 1418 /* count for packets */ 1419 u64 tx_cnt; 1420 u64 rx_cnt; 1421 1422 /* units in Mbps */ 1423 u32 tx_throughput; 1424 u32 rx_throughput; 1425 u32 tx_throughput_raw; 1426 u32 rx_throughput_raw; 1427 1428 u32 rx_tf_acc; 1429 u32 rx_tf_periodic; 1430 1431 enum rtw89_tfc_lv tx_tfc_lv; 1432 enum rtw89_tfc_lv rx_tfc_lv; 1433 struct ewma_tp tx_ewma_tp; 1434 struct ewma_tp rx_ewma_tp; 1435 1436 u16 tx_rate; 1437 u16 rx_rate; 1438 }; 1439 1440 struct rtw89_btc_chdef { 1441 u8 center_ch; 1442 u8 band; 1443 u8 chan; 1444 enum rtw89_sc_offset offset; 1445 enum rtw89_bandwidth bw; 1446 }; 1447 1448 struct rtw89_btc_statistic { 1449 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1450 struct rtw89_traffic_stats traffic; 1451 }; 1452 1453 #define BTC_WL_RSSI_THMAX 4 1454 1455 struct rtw89_btc_wl_link_info { 1456 struct rtw89_btc_chdef chdef; 1457 struct rtw89_btc_statistic stat; 1458 enum rtw89_tfc_dir dir; 1459 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1460 u8 mac_addr[ETH_ALEN]; 1461 u8 busy; 1462 u8 ch; 1463 u8 bw; 1464 u8 band; 1465 u8 role; 1466 u8 pid; 1467 u8 phy; 1468 u8 dtim_period; 1469 u8 mode; 1470 u8 tx_1ss_limit; 1471 1472 u8 mac_id; 1473 u8 tx_retry; 1474 1475 u32 bcn_period; 1476 u32 busy_t; 1477 u32 tx_time; 1478 u32 client_cnt; 1479 u32 rx_rate_drop_cnt; 1480 u32 noa_duration; 1481 1482 u32 active: 1; 1483 u32 noa: 1; 1484 u32 client_ps: 1; 1485 u32 connected: 2; 1486 }; 1487 1488 union rtw89_btc_wl_state_map { 1489 u32 val; 1490 struct rtw89_btc_wl_smap map; 1491 }; 1492 1493 struct rtw89_btc_bt_hfp_desc { 1494 u32 exist: 1; 1495 u32 type: 2; 1496 u32 rsvd: 29; 1497 }; 1498 1499 struct rtw89_btc_bt_hid_desc { 1500 u32 exist: 1; 1501 u32 slot_info: 2; 1502 u32 pair_cnt: 2; 1503 u32 type: 8; 1504 u32 rsvd: 19; 1505 }; 1506 1507 struct rtw89_btc_bt_a2dp_desc { 1508 u8 exist: 1; 1509 u8 exist_last: 1; 1510 u8 play_latency: 1; 1511 u8 type: 3; 1512 u8 active: 1; 1513 u8 sink: 1; 1514 u32 handle_update: 1; 1515 u32 devinfo_query: 1; 1516 u32 no_empty_streak_2s: 8; 1517 u32 no_empty_streak_max: 8; 1518 u32 rsvd: 6; 1519 1520 u8 bitpool; 1521 u16 vendor_id; 1522 u32 device_name; 1523 u32 flush_time; 1524 }; 1525 1526 struct rtw89_btc_bt_pan_desc { 1527 u32 exist: 1; 1528 u32 type: 1; 1529 u32 active: 1; 1530 u32 rsvd: 29; 1531 }; 1532 1533 struct rtw89_btc_bt_rfk_info { 1534 u32 run: 1; 1535 u32 req: 1; 1536 u32 timeout: 1; 1537 u32 rsvd: 29; 1538 }; 1539 1540 union rtw89_btc_bt_rfk_info_map { 1541 u32 val; 1542 struct rtw89_btc_bt_rfk_info map; 1543 }; 1544 1545 struct rtw89_btc_bt_ver_info { 1546 u32 fw_coex; /* match with which coex_ver */ 1547 u32 fw; 1548 }; 1549 1550 struct rtw89_btc_bool_sta_chg { 1551 u32 now: 1; 1552 u32 last: 1; 1553 u32 remain: 1; 1554 u32 srvd: 29; 1555 }; 1556 1557 struct rtw89_btc_u8_sta_chg { 1558 u8 now; 1559 u8 last; 1560 u8 remain; 1561 u8 rsvd; 1562 }; 1563 1564 struct rtw89_btc_wl_scan_info { 1565 u8 band[RTW89_PHY_NUM]; 1566 u8 phy_map; 1567 u8 rsvd; 1568 }; 1569 1570 struct rtw89_btc_wl_dbcc_info { 1571 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1572 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1573 u8 real_band[RTW89_PHY_NUM]; 1574 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1575 }; 1576 1577 struct rtw89_btc_wl_mlo_info { 1578 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */ 1579 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */ 1580 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */ 1581 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */ 1582 1583 u8 wtype; /* enum phl_mr_wtype */ 1584 u8 mrcx_mode; 1585 u8 mrcx_act_hwb_map; 1586 u8 mrcx_bt_slot_rsp; 1587 1588 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */ 1589 u8 mlo_en; /* MLO enable */ 1590 u8 mlo_adie; /* a-die count */ 1591 u8 dual_hw_band_en; /* both 2 HW-band link exist */ 1592 1593 u32 link_status; /* enum mlo_dbcc_mode_type */ 1594 }; 1595 1596 struct rtw89_btc_wl_active_role { 1597 u8 connected: 1; 1598 u8 pid: 3; 1599 u8 phy: 1; 1600 u8 noa: 1; 1601 u8 band: 2; 1602 1603 u8 client_ps: 1; 1604 u8 bw: 7; 1605 1606 u8 role; 1607 u8 ch; 1608 1609 u16 tx_lvl; 1610 u16 rx_lvl; 1611 u16 tx_rate; 1612 u16 rx_rate; 1613 }; 1614 1615 struct rtw89_btc_wl_active_role_v1 { 1616 u8 connected: 1; 1617 u8 pid: 3; 1618 u8 phy: 1; 1619 u8 noa: 1; 1620 u8 band: 2; 1621 1622 u8 client_ps: 1; 1623 u8 bw: 7; 1624 1625 u8 role; 1626 u8 ch; 1627 1628 u16 tx_lvl; 1629 u16 rx_lvl; 1630 u16 tx_rate; 1631 u16 rx_rate; 1632 1633 u32 noa_duration; /* ms */ 1634 }; 1635 1636 struct rtw89_btc_wl_active_role_v2 { 1637 u8 connected: 1; 1638 u8 pid: 3; 1639 u8 phy: 1; 1640 u8 noa: 1; 1641 u8 band: 2; 1642 1643 u8 client_ps: 1; 1644 u8 bw: 7; 1645 1646 u8 role; 1647 u8 ch; 1648 1649 u32 noa_duration; /* ms */ 1650 }; 1651 1652 struct rtw89_btc_wl_active_role_v7 { 1653 u8 connected; 1654 u8 pid; 1655 u8 phy; 1656 u8 noa; 1657 1658 u8 band; 1659 u8 client_ps; 1660 u8 bw; 1661 u8 role; 1662 1663 u8 ch; 1664 u8 noa_dur; 1665 u8 client_cnt; 1666 u8 rsvd2; 1667 } __packed; 1668 1669 struct rtw89_btc_wl_role_info_bpos { 1670 u16 none: 1; 1671 u16 station: 1; 1672 u16 ap: 1; 1673 u16 vap: 1; 1674 u16 adhoc: 1; 1675 u16 adhoc_master: 1; 1676 u16 mesh: 1; 1677 u16 moniter: 1; 1678 u16 p2p_device: 1; 1679 u16 p2p_gc: 1; 1680 u16 p2p_go: 1; 1681 u16 nan: 1; 1682 }; 1683 1684 struct rtw89_btc_wl_scc_ctrl { 1685 u8 null_role1; 1686 u8 null_role2; 1687 u8 ebt_null; /* if tx null at EBT slot */ 1688 }; 1689 1690 union rtw89_btc_wl_role_info_map { 1691 u16 val; 1692 struct rtw89_btc_wl_role_info_bpos role; 1693 }; 1694 1695 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1696 u8 connect_cnt; 1697 u8 link_mode; 1698 union rtw89_btc_wl_role_info_map role_map; 1699 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1700 }; 1701 1702 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1703 u8 connect_cnt; 1704 u8 link_mode; 1705 union rtw89_btc_wl_role_info_map role_map; 1706 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1707 u32 mrole_type; /* btc_wl_mrole_type */ 1708 u32 mrole_noa_duration; /* ms */ 1709 1710 u32 dbcc_en: 1; 1711 u32 dbcc_chg: 1; 1712 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1713 u32 link_mode_chg: 1; 1714 u32 rsvd: 27; 1715 }; 1716 1717 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1718 u8 connect_cnt; 1719 u8 link_mode; 1720 union rtw89_btc_wl_role_info_map role_map; 1721 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1722 u32 mrole_type; /* btc_wl_mrole_type */ 1723 u32 mrole_noa_duration; /* ms */ 1724 1725 u32 dbcc_en: 1; 1726 u32 dbcc_chg: 1; 1727 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1728 u32 link_mode_chg: 1; 1729 u32 rsvd: 27; 1730 }; 1731 1732 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1733 u8 connected; 1734 u8 pid; 1735 u8 phy; 1736 u8 noa; 1737 1738 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1739 u8 active; /* 0:rlink is under doze */ 1740 u8 bw; /* enum channel_width */ 1741 u8 role; /*enum role_type */ 1742 1743 u8 ch; 1744 u8 noa_dur; /* ms */ 1745 u8 client_cnt; /* for Role = P2P-Go/AP */ 1746 u8 mode; /* wifi protocol */ 1747 } __packed; 1748 1749 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1750 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1751 u8 connect_cnt; 1752 u8 link_mode; 1753 u8 link_mode_chg; 1754 u8 p2p_2g; 1755 1756 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1757 1758 u32 role_map; 1759 u32 mrole_type; /* btc_wl_mrole_type */ 1760 u32 mrole_noa_duration; /* ms */ 1761 u32 dbcc_en; 1762 u32 dbcc_chg; 1763 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1764 } __packed; 1765 1766 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1767 u8 connect_cnt; 1768 u8 link_mode; 1769 u8 link_mode_chg; 1770 u8 p2p_2g; 1771 1772 u8 pta_req_band; 1773 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1774 u8 dbcc_chg; 1775 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1776 1777 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1778 1779 u32 role_map; 1780 u32 mrole_type; /* btc_wl_mrole_type */ 1781 u32 mrole_noa_duration; /* ms */ 1782 } __packed; 1783 1784 struct rtw89_btc_wl_ver_info { 1785 u32 fw_coex; /* match with which coex_ver */ 1786 u32 fw; 1787 u32 mac; 1788 u32 bb; 1789 u32 rf; 1790 }; 1791 1792 struct rtw89_btc_wl_afh_info { 1793 u8 en; 1794 u8 ch; 1795 u8 bw; 1796 u8 rsvd; 1797 } __packed; 1798 1799 struct rtw89_btc_wl_rfk_info { 1800 u32 state: 2; 1801 u32 path_map: 4; 1802 u32 phy_map: 2; 1803 u32 band: 2; 1804 u32 type: 8; 1805 u32 con_rfk: 1; 1806 u32 rsvd: 13; 1807 1808 u32 start_time; 1809 u32 proc_time; 1810 }; 1811 1812 struct rtw89_btc_bt_smap { 1813 u32 connect: 1; 1814 u32 ble_connect: 1; 1815 u32 acl_busy: 1; 1816 u32 sco_busy: 1; 1817 u32 mesh_busy: 1; 1818 u32 inq_pag: 1; 1819 }; 1820 1821 union rtw89_btc_bt_state_map { 1822 u32 val; 1823 struct rtw89_btc_bt_smap map; 1824 }; 1825 1826 #define BTC_BT_RSSI_THMAX 4 1827 #define BTC_BT_AFH_GROUP 12 1828 #define BTC_BT_AFH_LE_GROUP 5 1829 1830 struct rtw89_btc_bt_txpwr_desc { 1831 s8 br_dbm; 1832 s8 le_dbm; 1833 u8 br_gain_index; 1834 u8 le_gain_index; 1835 }; 1836 1837 struct rtw89_btc_bt_link_info { 1838 struct rtw89_btc_u8_sta_chg profile_cnt; 1839 struct rtw89_btc_bool_sta_chg multi_link; 1840 struct rtw89_btc_bool_sta_chg relink; 1841 struct rtw89_btc_bt_hfp_desc hfp_desc; 1842 struct rtw89_btc_bt_hid_desc hid_desc; 1843 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1844 struct rtw89_btc_bt_pan_desc pan_desc; 1845 union rtw89_btc_bt_state_map status; 1846 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc; 1847 1848 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1849 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1850 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1851 u8 afh_map[BTC_BT_AFH_GROUP]; 1852 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1853 1854 u32 role_sw: 1; 1855 u32 slave_role: 1; 1856 u32 afh_update: 1; 1857 u32 cqddr: 1; 1858 u32 rssi: 8; 1859 u32 tx_3m: 1; 1860 u32 rsvd: 19; 1861 }; 1862 1863 struct rtw89_btc_3rdcx_info { 1864 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1865 u8 hw_coex; 1866 u16 rsvd; 1867 }; 1868 1869 struct rtw89_btc_dm_emap { 1870 u32 init: 1; 1871 u32 pta_owner: 1; 1872 u32 wl_rfk_timeout: 1; 1873 u32 bt_rfk_timeout: 1; 1874 u32 wl_fw_hang: 1; 1875 u32 cycle_hang: 1; 1876 u32 w1_hang: 1; 1877 u32 b1_hang: 1; 1878 u32 tdma_no_sync: 1; 1879 u32 slot_no_sync: 1; 1880 u32 wl_slot_drift: 1; 1881 u32 bt_slot_drift: 1; 1882 u32 role_num_mismatch: 1; 1883 u32 null1_tx_late: 1; 1884 u32 bt_afh_conflict: 1; 1885 u32 bt_leafh_conflict: 1; 1886 u32 bt_slot_flood: 1; 1887 u32 wl_e2g_hang: 1; 1888 u32 wl_ver_mismatch: 1; 1889 u32 bt_ver_mismatch: 1; 1890 u32 rfe_type0: 1; 1891 u32 h2c_buffer_over: 1; 1892 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1893 u32 wl_no_sta_ntfy: 1; 1894 1895 u32 h2c_bmap_mismatch: 1; 1896 u32 c2h_bmap_mismatch: 1; 1897 u32 h2c_struct_invalid: 1; 1898 u32 c2h_struct_invalid: 1; 1899 u32 h2c_c2h_buffer_mismatch: 1; 1900 }; 1901 1902 union rtw89_btc_dm_error_map { 1903 u32 val; 1904 struct rtw89_btc_dm_emap map; 1905 }; 1906 1907 struct rtw89_btc_rf_para { 1908 u32 tx_pwr_freerun; 1909 u32 rx_gain_freerun; 1910 u32 tx_pwr_perpkt; 1911 u32 rx_gain_perpkt; 1912 }; 1913 1914 struct rtw89_btc_wl_nhm { 1915 u8 instant_wl_nhm_dbm; 1916 u8 instant_wl_nhm_per_mhz; 1917 u16 valid_record_times; 1918 s8 record_pwr[16]; 1919 u8 record_ratio[16]; 1920 s8 pwr; /* dbm_per_MHz */ 1921 u8 ratio; 1922 u8 current_status; 1923 u8 refresh; 1924 bool start_flag; 1925 s8 pwr_max; 1926 s8 pwr_min; 1927 }; 1928 1929 struct rtw89_btc_wl_info { 1930 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1931 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1932 struct rtw89_btc_wl_rfk_info rfk_info; 1933 struct rtw89_btc_wl_ver_info ver_info; 1934 struct rtw89_btc_wl_afh_info afh_info; 1935 struct rtw89_btc_wl_role_info role_info; 1936 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1937 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1938 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1939 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1940 struct rtw89_btc_wl_scan_info scan_info; 1941 struct rtw89_btc_wl_dbcc_info dbcc_info; 1942 struct rtw89_btc_wl_mlo_info mlo_info; 1943 struct rtw89_btc_rf_para rf_para; 1944 struct rtw89_btc_wl_nhm nhm; 1945 union rtw89_btc_wl_state_map status; 1946 1947 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1948 u8 rssi_level; 1949 u8 cn_report; 1950 u8 coex_mode; 1951 u8 pta_req_mac; 1952 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 1953 1954 bool is_5g_hi_channel; 1955 bool go_client_exist; 1956 bool noa_exist; 1957 bool pta_reg_mac_chg; 1958 bool bg_mode; 1959 bool he_mode; 1960 bool scbd_change; 1961 bool fw_ver_mismatch; 1962 bool client_cnt_inc_2g; 1963 bool link_mode_chg; 1964 bool dbcc_chg; 1965 u32 scbd; 1966 }; 1967 1968 struct rtw89_btc_module { 1969 struct rtw89_btc_ant_info ant; 1970 u8 rfe_type; 1971 u8 cv; 1972 1973 u8 bt_solo: 1; 1974 u8 bt_pos: 1; 1975 u8 switch_type: 1; 1976 u8 wa_type: 3; 1977 1978 u8 kt_ver_adie; 1979 }; 1980 1981 struct rtw89_btc_module_v7 { 1982 u8 rfe_type; 1983 u8 kt_ver; 1984 u8 bt_solo; 1985 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1986 1987 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1988 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1989 u8 kt_ver_adie; 1990 u8 rsvd; 1991 1992 struct rtw89_btc_ant_info_v7 ant; 1993 } __packed; 1994 1995 union rtw89_btc_module_info { 1996 struct rtw89_btc_module md; 1997 struct rtw89_btc_module_v7 md_v7; 1998 }; 1999 2000 #define RTW89_BTC_DM_MAXSTEP 30 2001 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 2002 2003 struct rtw89_btc_dm_step { 2004 u16 step[RTW89_BTC_DM_MAXSTEP]; 2005 u8 step_pos; 2006 bool step_ov; 2007 }; 2008 2009 struct rtw89_btc_init_info { 2010 struct rtw89_btc_module module; 2011 u8 wl_guard_ch; 2012 2013 u8 wl_only: 1; 2014 u8 wl_init_ok: 1; 2015 u8 dbcc_en: 1; 2016 u8 cx_other: 1; 2017 u8 bt_only: 1; 2018 2019 u16 rsvd; 2020 }; 2021 2022 struct rtw89_btc_init_info_v7 { 2023 u8 wl_guard_ch; 2024 u8 wl_only; 2025 u8 wl_init_ok; 2026 u8 rsvd3; 2027 2028 u8 cx_other; 2029 u8 bt_only; 2030 u8 pta_mode; 2031 u8 pta_direction; 2032 2033 struct rtw89_btc_module_v7 module; 2034 } __packed; 2035 2036 union rtw89_btc_init_info_u { 2037 struct rtw89_btc_init_info init; 2038 struct rtw89_btc_init_info_v7 init_v7; 2039 }; 2040 2041 struct rtw89_btc_wl_tx_limit_para { 2042 u16 enable; 2043 u32 tx_time; /* unit: us */ 2044 u16 tx_retry; 2045 }; 2046 2047 enum rtw89_btc_bt_scan_type { 2048 BTC_SCAN_INQ = 0, 2049 BTC_SCAN_PAGE, 2050 BTC_SCAN_BLE, 2051 BTC_SCAN_INIT, 2052 BTC_SCAN_TV, 2053 BTC_SCAN_ADV, 2054 BTC_SCAN_MAX1, 2055 }; 2056 2057 enum rtw89_btc_ble_scan_type { 2058 CXSCAN_BG = 0, 2059 CXSCAN_INIT, 2060 CXSCAN_LE, 2061 CXSCAN_MAX 2062 }; 2063 2064 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2065 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2066 2067 struct rtw89_btc_bt_scan_info_v1 { 2068 __le16 win; 2069 __le16 intvl; 2070 __le32 flags; 2071 } __packed; 2072 2073 struct rtw89_btc_bt_scan_info_v2 { 2074 __le16 win; 2075 __le16 intvl; 2076 } __packed; 2077 2078 struct rtw89_btc_fbtc_btscan_v1 { 2079 u8 fver; /* btc_ver::fcxbtscan */ 2080 u8 rsvd; 2081 __le16 rsvd2; 2082 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2083 } __packed; 2084 2085 struct rtw89_btc_fbtc_btscan_v2 { 2086 u8 fver; /* btc_ver::fcxbtscan */ 2087 u8 type; 2088 __le16 rsvd2; 2089 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2090 } __packed; 2091 2092 struct rtw89_btc_fbtc_btscan_v7 { 2093 u8 fver; /* btc_ver::fcxbtscan */ 2094 u8 type; 2095 u8 rsvd0; 2096 u8 rsvd1; 2097 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2098 } __packed; 2099 2100 union rtw89_btc_fbtc_btscan { 2101 struct rtw89_btc_fbtc_btscan_v1 v1; 2102 struct rtw89_btc_fbtc_btscan_v2 v2; 2103 struct rtw89_btc_fbtc_btscan_v7 v7; 2104 }; 2105 2106 struct rtw89_btc_bt_info { 2107 struct rtw89_btc_bt_link_info link_info; 2108 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2109 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2110 struct rtw89_btc_bt_ver_info ver_info; 2111 struct rtw89_btc_bool_sta_chg enable; 2112 struct rtw89_btc_bool_sta_chg inq_pag; 2113 struct rtw89_btc_rf_para rf_para; 2114 union rtw89_btc_bt_rfk_info_map rfk_info; 2115 2116 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2117 u8 txpwr_info[BTC_BTINFO_MAX]; 2118 u8 rssi_level; 2119 2120 u32 scbd; 2121 u32 feature; 2122 2123 u32 mbx_avl: 1; 2124 u32 whql_test: 1; 2125 u32 igno_wl: 1; 2126 u32 reinit: 1; 2127 u32 ble_scan_en: 1; 2128 u32 btg_type: 1; 2129 u32 inq: 1; 2130 u32 pag: 1; 2131 u32 run_patch_code: 1; 2132 u32 hi_lna_rx: 1; 2133 u32 scan_rx_low_pri: 1; 2134 u32 scan_info_update: 1; 2135 u32 lna_constrain: 3; 2136 u32 rsvd: 17; 2137 }; 2138 2139 struct rtw89_btc_cx { 2140 struct rtw89_btc_wl_info wl; 2141 struct rtw89_btc_bt_info bt; 2142 struct rtw89_btc_3rdcx_info other; 2143 u32 state_map; 2144 u32 cnt_bt[BTC_BCNT_NUM]; 2145 u32 cnt_wl[BTC_WCNT_NUM]; 2146 }; 2147 2148 struct rtw89_btc_fbtc_tdma { 2149 u8 type; /* btc_ver::fcxtdma */ 2150 u8 rxflctrl; 2151 u8 txpause; 2152 u8 wtgle_n; 2153 u8 leak_n; 2154 u8 ext_ctrl; 2155 u8 rxflctrl_role; 2156 u8 option_ctrl; 2157 } __packed; 2158 2159 struct rtw89_btc_fbtc_tdma_v3 { 2160 u8 fver; /* btc_ver::fcxtdma */ 2161 u8 rsvd; 2162 __le16 rsvd1; 2163 struct rtw89_btc_fbtc_tdma tdma; 2164 } __packed; 2165 2166 union rtw89_btc_fbtc_tdma_le32 { 2167 struct rtw89_btc_fbtc_tdma v1; 2168 struct rtw89_btc_fbtc_tdma_v3 v3; 2169 }; 2170 2171 #define CXMREG_MAX 30 2172 #define CXMREG_MAX_V2 20 2173 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2174 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2175 2176 enum rtw89_btc_bt_sta_counter { 2177 BTC_BCNT_RFK_REQ = 0, 2178 BTC_BCNT_RFK_GO = 1, 2179 BTC_BCNT_RFK_REJECT = 2, 2180 BTC_BCNT_RFK_FAIL = 3, 2181 BTC_BCNT_RFK_TIMEOUT = 4, 2182 BTC_BCNT_HI_TX = 5, 2183 BTC_BCNT_HI_RX = 6, 2184 BTC_BCNT_LO_TX = 7, 2185 BTC_BCNT_LO_RX = 8, 2186 BTC_BCNT_POLLUTED = 9, 2187 BTC_BCNT_STA_MAX 2188 }; 2189 2190 enum rtw89_btc_bt_sta_counter_v105 { 2191 BTC_BCNT_RFK_REQ_V105 = 0, 2192 BTC_BCNT_HI_TX_V105 = 1, 2193 BTC_BCNT_HI_RX_V105 = 2, 2194 BTC_BCNT_LO_TX_V105 = 3, 2195 BTC_BCNT_LO_RX_V105 = 4, 2196 BTC_BCNT_POLLUTED_V105 = 5, 2197 BTC_BCNT_STA_MAX_V105 2198 }; 2199 2200 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2201 u16 fver; /* btc_ver::fcxbtcrpt */ 2202 u16 rpt_cnt; /* tmr counters */ 2203 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2204 u32 wl_fw_cx_offload; 2205 u32 wl_fw_ver; 2206 u32 rpt_enable; 2207 u32 rpt_para; /* ms */ 2208 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2209 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2210 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2211 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2212 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2213 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2214 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2215 u32 c2h_cnt; /* fw send c2h counter */ 2216 u32 h2c_cnt; /* fw recv h2c counter */ 2217 } __packed; 2218 2219 struct rtw89_btc_fbtc_rpt_ctrl_info { 2220 __le32 cnt; /* fw report counter */ 2221 __le32 en; /* report map */ 2222 __le32 para; /* not used */ 2223 2224 __le32 cnt_c2h; /* fw send c2h counter */ 2225 __le32 cnt_h2c; /* fw recv h2c counter */ 2226 __le32 len_c2h; /* The total length of the last C2H */ 2227 2228 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2229 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2230 } __packed; 2231 2232 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2233 __le32 cx_ver; /* match which driver's coex version */ 2234 __le32 fw_ver; 2235 __le32 en; /* report map */ 2236 2237 __le16 cnt; /* fw report counter */ 2238 __le16 cnt_c2h; /* fw send c2h counter */ 2239 __le16 cnt_h2c; /* fw recv h2c counter */ 2240 __le16 len_c2h; /* The total length of the last C2H */ 2241 2242 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2243 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2244 } __packed; 2245 2246 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2247 __le16 cnt; /* fw report counter */ 2248 __le16 cnt_c2h; /* fw send c2h counter */ 2249 __le16 cnt_h2c; /* fw recv h2c counter */ 2250 __le16 len_c2h; /* The total length of the last C2H */ 2251 2252 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2253 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2254 2255 __le32 cx_ver; /* match which driver's coex version */ 2256 __le32 fw_ver; 2257 __le32 en; /* report map */ 2258 } __packed; 2259 2260 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2261 __le32 cx_ver; /* match which driver's coex version */ 2262 __le32 cx_offload; 2263 __le32 fw_ver; 2264 } __packed; 2265 2266 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2267 __le32 cnt_empty; /* a2dp empty count */ 2268 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2269 __le32 cnt_tx; 2270 __le32 cnt_ack; 2271 __le32 cnt_nack; 2272 } __packed; 2273 2274 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2275 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2276 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2277 __le32 cnt_recv; /* fw recv mailbox counter */ 2278 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2279 } __packed; 2280 2281 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2282 u8 fver; 2283 u8 rsvd; 2284 __le16 rsvd1; 2285 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2286 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2287 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2288 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2289 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2290 } __packed; 2291 2292 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2293 u8 fver; 2294 u8 rsvd; 2295 __le16 rsvd1; 2296 2297 u8 gnt_val[RTW89_PHY_NUM][4]; 2298 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2299 2300 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2301 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2302 } __packed; 2303 2304 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2305 u8 fver; 2306 u8 rsvd; 2307 __le16 rsvd1; 2308 2309 u8 gnt_val[RTW89_PHY_NUM][4]; 2310 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2311 2312 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2313 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2314 } __packed; 2315 2316 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2317 u8 fver; 2318 u8 rsvd0; 2319 u8 rsvd1; 2320 u8 rsvd2; 2321 2322 u8 gnt_val[RTW89_PHY_NUM][4]; 2323 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2324 2325 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2326 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2327 } __packed; 2328 2329 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2330 u8 fver; 2331 u8 rsvd0; 2332 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2333 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2334 2335 u8 gnt_val[RTW89_PHY_NUM][4]; 2336 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2337 2338 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2339 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2340 } __packed; 2341 2342 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2343 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2344 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2345 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2346 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2347 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2348 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2349 }; 2350 2351 enum rtw89_fbtc_ext_ctrl_type { 2352 CXECTL_OFF = 0x0, /* tdma off */ 2353 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2354 CXECTL_EXT = 0x2, 2355 CXECTL_MAX 2356 }; 2357 2358 union rtw89_btc_fbtc_rxflct { 2359 u8 val; 2360 u8 type: 3; 2361 u8 tgln_n: 5; 2362 }; 2363 2364 enum rtw89_btc_cxst_state { 2365 CXST_OFF = 0x0, 2366 CXST_B2W = 0x1, 2367 CXST_W1 = 0x2, 2368 CXST_W2 = 0x3, 2369 CXST_W2B = 0x4, 2370 CXST_B1 = 0x5, 2371 CXST_B2 = 0x6, 2372 CXST_B3 = 0x7, 2373 CXST_B4 = 0x8, 2374 CXST_LK = 0x9, 2375 CXST_BLK = 0xa, 2376 CXST_E2G = 0xb, 2377 CXST_E5G = 0xc, 2378 CXST_EBT = 0xd, 2379 CXST_ENULL = 0xe, 2380 CXST_WLK = 0xf, 2381 CXST_W1FDD = 0x10, 2382 CXST_B1FDD = 0x11, 2383 CXST_MAX = 0x12, 2384 }; 2385 2386 enum rtw89_btc_cxevnt { 2387 CXEVNT_TDMA_ENTRY = 0x0, 2388 CXEVNT_WL_TMR, 2389 CXEVNT_B1_TMR, 2390 CXEVNT_B2_TMR, 2391 CXEVNT_B3_TMR, 2392 CXEVNT_B4_TMR, 2393 CXEVNT_W2B_TMR, 2394 CXEVNT_B2W_TMR, 2395 CXEVNT_BCN_EARLY, 2396 CXEVNT_A2DP_EMPTY, 2397 CXEVNT_LK_END, 2398 CXEVNT_RX_ISR, 2399 CXEVNT_RX_FC0, 2400 CXEVNT_RX_FC1, 2401 CXEVNT_BT_RELINK, 2402 CXEVNT_BT_RETRY, 2403 CXEVNT_E2G, 2404 CXEVNT_E5G, 2405 CXEVNT_EBT, 2406 CXEVNT_ENULL, 2407 CXEVNT_DRV_WLK, 2408 CXEVNT_BCN_OK, 2409 CXEVNT_BT_CHANGE, 2410 CXEVNT_EBT_EXTEND, 2411 CXEVNT_E2G_NULL1, 2412 CXEVNT_B1FDD_TMR, 2413 CXEVNT_MAX 2414 }; 2415 2416 enum { 2417 CXBCN_ALL = 0x0, 2418 CXBCN_ALL_OK, 2419 CXBCN_BT_SLOT, 2420 CXBCN_BT_OK, 2421 CXBCN_MAX 2422 }; 2423 2424 enum btc_slot_type { 2425 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2426 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2427 CXSTYPE_NUM, 2428 }; 2429 2430 enum { /* TIME */ 2431 CXT_BT = 0x0, 2432 CXT_WL = 0x1, 2433 CXT_MAX 2434 }; 2435 2436 enum { /* TIME-A2DP */ 2437 CXT_FLCTRL_OFF = 0x0, 2438 CXT_FLCTRL_ON = 0x1, 2439 CXT_FLCTRL_MAX 2440 }; 2441 2442 enum { /* STEP TYPE */ 2443 CXSTEP_NONE = 0x0, 2444 CXSTEP_EVNT = 0x1, 2445 CXSTEP_SLOT = 0x2, 2446 CXSTEP_MAX, 2447 }; 2448 2449 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2450 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2451 RPT_BT_AFH_SEQ_LE = 0x20 2452 }; 2453 2454 #define BTC_DBG_MAX1 32 2455 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2456 u8 fver; /* btc_ver::fcxgpiodbg */ 2457 u8 rsvd; 2458 __le16 rsvd2; 2459 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2460 __le32 pre_state; /* the debug signal is 1 or 0 */ 2461 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2462 } __packed; 2463 2464 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2465 u8 fver; 2466 u8 rsvd0; 2467 u8 rsvd1; 2468 u8 rsvd2; 2469 2470 u8 gpio_map[BTC_DBG_MAX1]; 2471 2472 __le32 en_map; 2473 __le32 pre_state; 2474 } __packed; 2475 2476 union rtw89_btc_fbtc_gpio_dbg { 2477 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2478 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2479 }; 2480 2481 struct rtw89_btc_fbtc_mreg_val_v1 { 2482 u8 fver; /* btc_ver::fcxmreg */ 2483 u8 reg_num; 2484 __le16 rsvd; 2485 __le32 mreg_val[CXMREG_MAX]; 2486 } __packed; 2487 2488 struct rtw89_btc_fbtc_mreg_val_v2 { 2489 u8 fver; /* btc_ver::fcxmreg */ 2490 u8 reg_num; 2491 __le16 rsvd; 2492 __le32 mreg_val[CXMREG_MAX_V2]; 2493 } __packed; 2494 2495 struct rtw89_btc_fbtc_mreg_val_v7 { 2496 u8 fver; 2497 u8 reg_num; 2498 u8 rsvd0; 2499 u8 rsvd1; 2500 __le32 mreg_val[CXMREG_MAX_V2]; 2501 } __packed; 2502 2503 union rtw89_btc_fbtc_mreg_val { 2504 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2505 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2506 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2507 }; 2508 2509 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2510 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2511 .offset = cpu_to_le32(__offset), } 2512 2513 struct rtw89_btc_fbtc_mreg { 2514 __le16 type; 2515 __le16 bytes; 2516 __le32 offset; 2517 } __packed; 2518 2519 struct rtw89_btc_fbtc_slot { 2520 __le16 dur; 2521 __le32 cxtbl; 2522 __le16 cxtype; 2523 } __packed; 2524 2525 struct rtw89_btc_fbtc_slots { 2526 u8 fver; /* btc_ver::fcxslots */ 2527 u8 tbl_num; 2528 __le16 rsvd; 2529 __le32 update_map; 2530 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2531 } __packed; 2532 2533 struct rtw89_btc_fbtc_slot_v7 { 2534 __le16 dur; /* slot duration */ 2535 __le16 cxtype; 2536 __le32 cxtbl; 2537 } __packed; 2538 2539 struct rtw89_btc_fbtc_slot_u16 { 2540 __le16 dur; /* slot duration */ 2541 __le16 cxtype; 2542 __le16 cxtbl_l16; /* coex table [15:0] */ 2543 __le16 cxtbl_h16; /* coex table [31:16] */ 2544 } __packed; 2545 2546 struct rtw89_btc_fbtc_1slot_v7 { 2547 u8 fver; 2548 u8 sid; /* slot id */ 2549 __le16 rsvd; 2550 struct rtw89_btc_fbtc_slot_v7 slot; 2551 } __packed; 2552 2553 struct rtw89_btc_fbtc_slots_v7 { 2554 u8 fver; 2555 u8 slot_cnt; 2556 u8 rsvd0; 2557 u8 rsvd1; 2558 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2559 __le32 update_map; 2560 } __packed; 2561 2562 union rtw89_btc_fbtc_slots_info { 2563 struct rtw89_btc_fbtc_slots v1; 2564 struct rtw89_btc_fbtc_slots_v7 v7; 2565 } __packed; 2566 2567 struct rtw89_btc_fbtc_step { 2568 u8 type; 2569 u8 val; 2570 __le16 difft; 2571 } __packed; 2572 2573 struct rtw89_btc_fbtc_steps_v2 { 2574 u8 fver; /* btc_ver::fcxstep */ 2575 u8 rsvd; 2576 __le16 cnt; 2577 __le16 pos_old; 2578 __le16 pos_new; 2579 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2580 } __packed; 2581 2582 struct rtw89_btc_fbtc_steps_v3 { 2583 u8 fver; 2584 u8 en; 2585 __le16 rsvd; 2586 __le32 cnt; 2587 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2588 } __packed; 2589 2590 union rtw89_btc_fbtc_steps_info { 2591 struct rtw89_btc_fbtc_steps_v2 v2; 2592 struct rtw89_btc_fbtc_steps_v3 v3; 2593 }; 2594 2595 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2596 u8 fver; /* btc_ver::fcxcysta */ 2597 u8 rsvd; 2598 __le16 cycles; /* total cycle number */ 2599 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2600 __le16 a2dpept; /* a2dp empty cnt */ 2601 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2602 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2603 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2604 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2605 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2606 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2607 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2608 __le16 tmax_a2dpept; /* max a2dp empty time */ 2609 __le16 tavg_lk; /* avg leak-slot time */ 2610 __le16 tmax_lk; /* max leak-slot time */ 2611 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2612 __le32 bcn_cnt[CXBCN_MAX]; 2613 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2614 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2615 __le32 skip_cnt; 2616 __le32 exception; 2617 __le32 except_cnt; 2618 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2619 } __packed; 2620 2621 struct rtw89_btc_fbtc_fdd_try_info { 2622 __le16 cycles[CXT_FLCTRL_MAX]; 2623 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2624 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2625 } __packed; 2626 2627 struct rtw89_btc_fbtc_cycle_time_info { 2628 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2629 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2630 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2631 } __packed; 2632 2633 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2634 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2635 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2636 } __packed; 2637 2638 struct rtw89_btc_fbtc_a2dp_trx_stat { 2639 u8 empty_cnt; 2640 u8 retry_cnt; 2641 u8 tx_rate; 2642 u8 tx_cnt; 2643 u8 ack_cnt; 2644 u8 nack_cnt; 2645 u8 rsvd1; 2646 u8 rsvd2; 2647 } __packed; 2648 2649 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2650 u8 empty_cnt; 2651 u8 retry_cnt; 2652 u8 tx_rate; 2653 u8 tx_cnt; 2654 u8 ack_cnt; 2655 u8 nack_cnt; 2656 u8 no_empty_cnt; 2657 u8 rsvd; 2658 } __packed; 2659 2660 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2661 __le16 cnt; /* a2dp empty cnt */ 2662 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2663 __le16 tavg; /* avg a2dp empty time */ 2664 __le16 tmax; /* max a2dp empty time */ 2665 } __packed; 2666 2667 struct rtw89_btc_fbtc_cycle_leak_info { 2668 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2669 __le16 tavg; /* avg leak-slot time */ 2670 __le16 tmax; /* max leak-slot time */ 2671 } __packed; 2672 2673 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2674 __le16 tavg; 2675 __le16 tamx; 2676 __le32 cnt_rximr; 2677 } __packed; 2678 2679 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2680 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2681 2682 struct rtw89_btc_fbtc_cycle_fddt_info { 2683 __le16 train_cycle; 2684 __le16 tp; 2685 2686 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2687 s8 bt_tx_power; /* decrease Tx power (dB) */ 2688 s8 bt_rx_gain; /* LNA constrain level */ 2689 u8 no_empty_cnt; 2690 2691 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2692 u8 cn; /* condition_num */ 2693 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2694 u8 train_result; /* refer to enum btc_fddt_check_map */ 2695 } __packed; 2696 2697 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2698 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2699 2700 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2701 __le16 train_cycle; 2702 __le16 tp; 2703 2704 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2705 s8 bt_tx_power; /* decrease Tx power (dB) */ 2706 s8 bt_rx_gain; /* LNA constrain level */ 2707 u8 no_empty_cnt; 2708 2709 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2710 u8 cn; /* condition_num */ 2711 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2712 u8 train_result; /* refer to enum btc_fddt_check_map */ 2713 } __packed; 2714 2715 struct rtw89_btc_fbtc_fddt_cell_status { 2716 s8 wl_tx_pwr; 2717 s8 bt_tx_pwr; 2718 s8 bt_rx_gain; 2719 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2720 } __packed; 2721 2722 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2723 u8 fver; 2724 u8 rsvd; 2725 __le16 cycles; /* total cycle number */ 2726 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2727 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2728 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2729 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2730 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2731 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2732 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2733 __le32 bcn_cnt[CXBCN_MAX]; 2734 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2735 __le32 skip_cnt; 2736 __le32 except_cnt; 2737 __le32 except_map; 2738 } __packed; 2739 2740 #define FDD_TRAIN_WL_DIRECTION 2 2741 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2742 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2743 2744 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2745 u8 fver; 2746 u8 rsvd; 2747 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2748 u8 except_cnt; 2749 2750 __le16 skip_cnt; 2751 __le16 cycles; /* total cycle number */ 2752 2753 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2754 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2755 __le16 bcn_cnt[CXBCN_MAX]; 2756 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2757 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2758 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2759 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2760 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2761 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2762 [FDD_TRAIN_WL_RSSI_LEVEL] 2763 [FDD_TRAIN_BT_RSSI_LEVEL]; 2764 __le32 except_map; 2765 } __packed; 2766 2767 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2768 u8 fver; 2769 u8 rsvd; 2770 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2771 u8 except_cnt; 2772 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2773 2774 __le16 skip_cnt; 2775 __le16 cycles; /* total cycle number */ 2776 2777 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2778 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2779 __le16 bcn_cnt[CXBCN_MAX]; 2780 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2781 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2782 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2783 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2784 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2785 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2786 [FDD_TRAIN_WL_RSSI_LEVEL] 2787 [FDD_TRAIN_BT_RSSI_LEVEL]; 2788 __le32 except_map; 2789 } __packed; 2790 2791 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2792 u8 fver; 2793 u8 rsvd; 2794 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2795 u8 except_cnt; 2796 2797 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2798 2799 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2800 2801 __le16 skip_cnt; 2802 __le16 cycles; /* total cycle number */ 2803 2804 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2805 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2806 __le16 bcn_cnt[CXBCN_MAX]; 2807 2808 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2809 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2810 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2811 2812 __le32 except_map; 2813 } __packed; 2814 2815 union rtw89_btc_fbtc_cysta_info { 2816 struct rtw89_btc_fbtc_cysta_v2 v2; 2817 struct rtw89_btc_fbtc_cysta_v3 v3; 2818 struct rtw89_btc_fbtc_cysta_v4 v4; 2819 struct rtw89_btc_fbtc_cysta_v5 v5; 2820 struct rtw89_btc_fbtc_cysta_v7 v7; 2821 }; 2822 2823 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2824 u8 fver; /* btc_ver::fcxnullsta */ 2825 u8 rsvd; 2826 __le16 rsvd2; 2827 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2828 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2829 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2830 } __packed; 2831 2832 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2833 u8 fver; /* btc_ver::fcxnullsta */ 2834 u8 rsvd; 2835 __le16 rsvd2; 2836 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2837 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2838 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2839 } __packed; 2840 2841 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2842 u8 fver; 2843 u8 rsvd0; 2844 u8 rsvd1; 2845 u8 rsvd2; 2846 2847 __le32 tmax[2]; 2848 __le32 tavg[2]; 2849 __le32 result[2][5]; 2850 } __packed; 2851 2852 union rtw89_btc_fbtc_cynullsta_info { 2853 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2854 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2855 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2856 }; 2857 2858 struct rtw89_btc_fbtc_btver_v1 { 2859 u8 fver; /* btc_ver::fcxbtver */ 2860 u8 rsvd; 2861 __le16 rsvd2; 2862 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2863 __le32 fw_ver; 2864 __le32 feature; 2865 } __packed; 2866 2867 struct rtw89_btc_fbtc_btver_v7 { 2868 u8 fver; 2869 u8 rsvd0; 2870 u8 rsvd1; 2871 u8 rsvd2; 2872 2873 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2874 __le32 fw_ver; 2875 __le32 feature; 2876 } __packed; 2877 2878 union rtw89_btc_fbtc_btver { 2879 struct rtw89_btc_fbtc_btver_v1 v1; 2880 struct rtw89_btc_fbtc_btver_v7 v7; 2881 } __packed; 2882 2883 struct rtw89_btc_fbtc_btafh { 2884 u8 fver; /* btc_ver::fcxbtafh */ 2885 u8 rsvd; 2886 __le16 rsvd2; 2887 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2888 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2889 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2890 } __packed; 2891 2892 struct rtw89_btc_fbtc_btafh_v2 { 2893 u8 fver; /* btc_ver::fcxbtafh */ 2894 u8 rsvd; 2895 u8 rsvd2; 2896 u8 map_type; 2897 u8 afh_l[4]; 2898 u8 afh_m[4]; 2899 u8 afh_h[4]; 2900 u8 afh_le_a[4]; 2901 u8 afh_le_b[4]; 2902 } __packed; 2903 2904 struct rtw89_btc_fbtc_btafh_v7 { 2905 u8 fver; 2906 u8 map_type; 2907 u8 rsvd0; 2908 u8 rsvd1; 2909 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2910 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2911 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2912 u8 afh_le_a[4]; 2913 u8 afh_le_b[4]; 2914 } __packed; 2915 2916 struct rtw89_btc_fbtc_btdevinfo { 2917 u8 fver; /* btc_ver::fcxbtdevinfo */ 2918 u8 rsvd; 2919 __le16 vendor_id; 2920 __le32 dev_name; /* only 24 bits valid */ 2921 __le32 flush_time; 2922 } __packed; 2923 2924 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2925 struct rtw89_btc_rf_trx_para { 2926 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2927 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2928 u8 bt_tx_power; /* decrease Tx power (dB) */ 2929 u8 bt_rx_gain; /* LNA constrain level */ 2930 }; 2931 2932 struct rtw89_btc_trx_info { 2933 u8 tx_lvl; 2934 u8 rx_lvl; 2935 u8 wl_rssi; 2936 u8 bt_rssi; 2937 2938 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2939 s8 rx_gain; /* rx gain table index (TBD.) */ 2940 s8 bt_tx_power; /* decrease Tx power (dB) */ 2941 s8 bt_rx_gain; /* LNA constrain level */ 2942 2943 u8 cn; /* condition_num */ 2944 s8 nhm; 2945 u8 bt_profile; 2946 u8 rsvd2; 2947 2948 u16 tx_rate; 2949 u16 rx_rate; 2950 2951 u32 tx_tp; 2952 u32 rx_tp; 2953 u32 rx_err_ratio; 2954 }; 2955 2956 enum btc_rf_path { 2957 BTC_RF_S0 = 0, 2958 BTC_RF_S1 = 1, 2959 BTC_RF_NUM, 2960 }; 2961 2962 struct rtw89_btc_fbtc_outsrc_set_info { 2963 u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */ 2964 u8 btg_rx[BTC_RF_NUM]; 2965 u8 nbtg_tx[BTC_RF_NUM]; 2966 2967 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */ 2968 struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */ 2969 2970 u8 pta_req_hw_band; 2971 u8 rf_gbt_source; 2972 } __packed; 2973 2974 union rtw89_btc_fbtc_slot_u { 2975 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2976 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2977 }; 2978 2979 struct rtw89_btc_dm { 2980 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */ 2981 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */ 2982 union rtw89_btc_fbtc_slot_u slot; 2983 union rtw89_btc_fbtc_slot_u slot_now; 2984 struct rtw89_btc_fbtc_tdma tdma; 2985 struct rtw89_btc_fbtc_tdma tdma_now; 2986 struct rtw89_mac_ax_coex_gnt gnt; 2987 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2988 struct rtw89_btc_rf_trx_para rf_trx_para; 2989 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2990 struct rtw89_btc_dm_step dm_step; 2991 struct rtw89_btc_wl_scc_ctrl wl_scc; 2992 struct rtw89_btc_trx_info trx_info; 2993 union rtw89_btc_dm_error_map error; 2994 u32 cnt_dm[BTC_DCNT_NUM]; 2995 u32 cnt_notify[BTC_NCNT_NUM]; 2996 2997 u32 update_slot_map; 2998 u32 set_ant_path; 2999 u32 e2g_slot_limit; 3000 u32 e2g_slot_nulltx_time; 3001 3002 u32 wl_only: 1; 3003 u32 wl_fw_cx_offload: 1; 3004 u32 freerun: 1; 3005 u32 fddt_train: 1; 3006 u32 wl_ps_ctrl: 2; 3007 u32 wl_mimo_ps: 1; 3008 u32 leak_ap: 1; 3009 u32 noisy_level: 3; 3010 u32 coex_info_map: 8; 3011 u32 bt_only: 1; 3012 u32 wl_btg_rx: 2; 3013 u32 trx_para_level: 8; 3014 u32 wl_stb_chg: 1; 3015 u32 pta_owner: 1; 3016 3017 u32 tdma_instant_excute: 1; 3018 u32 wl_btg_rx_rb: 2; 3019 3020 u16 slot_dur[CXST_MAX]; 3021 u16 bt_slot_flood; 3022 3023 u8 run_reason; 3024 u8 run_action; 3025 3026 u8 wl_pre_agc: 2; 3027 u8 wl_lna2: 1; 3028 u8 freerun_chk: 1; 3029 u8 wl_pre_agc_rb: 2; 3030 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 3031 u8 slot_req_more: 1; 3032 }; 3033 3034 struct rtw89_btc_ctrl { 3035 u32 manual: 1; 3036 u32 igno_bt: 1; 3037 u32 always_freerun: 1; 3038 u32 trace_step: 16; 3039 u32 rsvd: 12; 3040 }; 3041 3042 struct rtw89_btc_ctrl_v7 { 3043 u8 manual; 3044 u8 igno_bt; 3045 u8 always_freerun; 3046 u8 rsvd; 3047 } __packed; 3048 3049 union rtw89_btc_ctrl_list { 3050 struct rtw89_btc_ctrl ctrl; 3051 struct rtw89_btc_ctrl_v7 ctrl_v7; 3052 }; 3053 3054 struct rtw89_btc_dbg { 3055 /* cmd "rb" */ 3056 bool rb_done; 3057 u32 rb_val; 3058 }; 3059 3060 enum rtw89_btc_btf_fw_event { 3061 BTF_EVNT_RPT = 0, 3062 BTF_EVNT_BT_INFO = 1, 3063 BTF_EVNT_BT_SCBD = 2, 3064 BTF_EVNT_BT_REG = 3, 3065 BTF_EVNT_CX_RUNINFO = 4, 3066 BTF_EVNT_BT_PSD = 5, 3067 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 3068 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 3069 BTF_EVNT_BUF_OVERFLOW, 3070 BTF_EVNT_C2H_LOOPBACK, 3071 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */ 3072 BTF_EVNT_MAX, 3073 }; 3074 3075 enum btf_fw_event_report { 3076 BTC_RPT_TYPE_CTRL = 0x0, 3077 BTC_RPT_TYPE_TDMA, 3078 BTC_RPT_TYPE_SLOT, 3079 BTC_RPT_TYPE_CYSTA, 3080 BTC_RPT_TYPE_STEP, 3081 BTC_RPT_TYPE_NULLSTA, 3082 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3083 BTC_RPT_TYPE_MREG, 3084 BTC_RPT_TYPE_GPIO_DBG, 3085 BTC_RPT_TYPE_BT_VER, 3086 BTC_RPT_TYPE_BT_SCAN, 3087 BTC_RPT_TYPE_BT_AFH, 3088 BTC_RPT_TYPE_BT_DEVICE, 3089 BTC_RPT_TYPE_TEST, 3090 BTC_RPT_TYPE_MAX = 31, 3091 3092 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3093 __BTC_RPT_TYPE_V0_MAX = 12, 3094 }; 3095 3096 enum rtw_btc_btf_reg_type { 3097 REG_MAC = 0x0, 3098 REG_BB = 0x1, 3099 REG_RF = 0x2, 3100 REG_BT_RF = 0x3, 3101 REG_BT_MODEM = 0x4, 3102 REG_BT_BLUEWIZE = 0x5, 3103 REG_BT_VENDOR = 0x6, 3104 REG_BT_LE = 0x7, 3105 REG_MAX_TYPE, 3106 }; 3107 3108 struct rtw89_btc_rpt_cmn_info { 3109 u32 rx_cnt; 3110 u32 rx_len; 3111 u32 req_len; /* expected rsp len */ 3112 u8 req_fver; /* expected rsp fver */ 3113 u8 rsp_fver; /* fver from fw */ 3114 u8 valid; 3115 } __packed; 3116 3117 union rtw89_btc_fbtc_btafh_info { 3118 struct rtw89_btc_fbtc_btafh v1; 3119 struct rtw89_btc_fbtc_btafh_v2 v2; 3120 struct rtw89_btc_fbtc_btafh_v7 v7; 3121 }; 3122 3123 struct rtw89_btc_report_ctrl_state { 3124 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3125 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3126 }; 3127 3128 struct rtw89_btc_rpt_fbtc_tdma { 3129 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3130 union rtw89_btc_fbtc_tdma_le32 finfo; 3131 }; 3132 3133 struct rtw89_btc_rpt_fbtc_slots { 3134 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3135 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3136 }; 3137 3138 struct rtw89_btc_rpt_fbtc_cysta { 3139 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3140 union rtw89_btc_fbtc_cysta_info finfo; 3141 }; 3142 3143 struct rtw89_btc_rpt_fbtc_step { 3144 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3145 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3146 }; 3147 3148 struct rtw89_btc_rpt_fbtc_nullsta { 3149 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3150 union rtw89_btc_fbtc_cynullsta_info finfo; 3151 }; 3152 3153 struct rtw89_btc_rpt_fbtc_mreg { 3154 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3155 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3156 }; 3157 3158 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3159 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3160 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3161 }; 3162 3163 struct rtw89_btc_rpt_fbtc_btver { 3164 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3165 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3166 }; 3167 3168 struct rtw89_btc_rpt_fbtc_btscan { 3169 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3170 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3171 }; 3172 3173 struct rtw89_btc_rpt_fbtc_btafh { 3174 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3175 union rtw89_btc_fbtc_btafh_info finfo; 3176 }; 3177 3178 struct rtw89_btc_rpt_fbtc_btdev { 3179 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3180 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3181 }; 3182 3183 enum rtw89_btc_btfre_type { 3184 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3185 BTFRE_UNDEF_TYPE, 3186 BTFRE_EXCEPTION, 3187 BTFRE_MAX, 3188 }; 3189 3190 struct rtw89_btc_ver { 3191 enum rtw89_core_chip_id chip_id; 3192 u32 fw_ver_code; 3193 3194 u8 fcxbtcrpt; 3195 u8 fcxtdma; 3196 u8 fcxslots; 3197 u8 fcxcysta; 3198 u8 fcxstep; 3199 u8 fcxnullsta; 3200 u8 fcxmreg; 3201 u8 fcxgpiodbg; 3202 u8 fcxbtver; 3203 u8 fcxbtscan; 3204 u8 fcxbtafh; 3205 u8 fcxbtdevinfo; 3206 u8 fwlrole; 3207 u8 frptmap; 3208 u8 fcxctrl; 3209 u8 fcxinit; 3210 3211 u8 fwevntrptl; 3212 u8 fwc2hfunc; 3213 u8 drvinfo_type; 3214 u16 info_buf; 3215 u8 max_role_num; 3216 u8 fcxosi; 3217 u8 fcxmlo; 3218 u8 bt_desired; 3219 }; 3220 3221 struct rtw89_btc_btf_fwinfo { 3222 u32 cnt_c2h; 3223 u32 cnt_h2c; 3224 u32 cnt_h2c_fail; 3225 u32 event[BTF_EVNT_MAX]; 3226 3227 u32 err[BTFRE_MAX]; 3228 u32 len_mismch; 3229 u32 fver_mismch; 3230 u32 rpt_en_map; 3231 3232 struct rtw89_btc_ver fw_subver; 3233 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3234 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3235 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3236 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3237 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3238 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3239 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3240 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3241 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3242 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3243 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3244 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3245 }; 3246 3247 #define RTW89_BTC_POLICY_MAXLEN 512 3248 3249 struct rtw89_btc { 3250 const struct rtw89_btc_ver *ver; 3251 3252 struct rtw89_btc_cx cx; 3253 struct rtw89_btc_dm dm; 3254 union rtw89_btc_ctrl_list ctrl; 3255 union rtw89_btc_module_info mdinfo; 3256 struct rtw89_btc_btf_fwinfo fwinfo; 3257 struct rtw89_btc_dbg dbg; 3258 3259 struct wiphy_work eapol_notify_work; 3260 struct wiphy_work arp_notify_work; 3261 struct wiphy_work dhcp_notify_work; 3262 struct wiphy_work icmp_notify_work; 3263 3264 u32 bt_req_len; 3265 3266 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3267 u8 ant_type; 3268 u8 btg_pos; 3269 u16 policy_len; 3270 u16 policy_type; 3271 u32 hubmsg_cnt; 3272 bool bt_req_en; 3273 bool update_policy_force; 3274 bool lps; 3275 bool manual_ctrl; 3276 }; 3277 3278 enum rtw89_btc_hmsg { 3279 RTW89_BTC_HMSG_TMR_EN = 0x0, 3280 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3281 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3282 RTW89_BTC_HMSG_FW_EV = 0x3, 3283 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3284 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3285 3286 NUM_OF_RTW89_BTC_HMSG, 3287 }; 3288 3289 enum rtw89_ra_mode { 3290 RTW89_RA_MODE_CCK = BIT(0), 3291 RTW89_RA_MODE_OFDM = BIT(1), 3292 RTW89_RA_MODE_HT = BIT(2), 3293 RTW89_RA_MODE_VHT = BIT(3), 3294 RTW89_RA_MODE_HE = BIT(4), 3295 RTW89_RA_MODE_EHT = BIT(5), 3296 }; 3297 3298 enum rtw89_ra_report_mode { 3299 RTW89_RA_RPT_MODE_LEGACY, 3300 RTW89_RA_RPT_MODE_HT, 3301 RTW89_RA_RPT_MODE_VHT, 3302 RTW89_RA_RPT_MODE_HE, 3303 RTW89_RA_RPT_MODE_EHT, 3304 }; 3305 3306 enum rtw89_dig_noisy_level { 3307 RTW89_DIG_NOISY_LEVEL0 = -1, 3308 RTW89_DIG_NOISY_LEVEL1 = 0, 3309 RTW89_DIG_NOISY_LEVEL2 = 1, 3310 RTW89_DIG_NOISY_LEVEL3 = 2, 3311 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3312 }; 3313 3314 enum rtw89_gi_ltf { 3315 RTW89_GILTF_LGI_4XHE32 = 0, 3316 RTW89_GILTF_SGI_4XHE08 = 1, 3317 RTW89_GILTF_2XHE16 = 2, 3318 RTW89_GILTF_2XHE08 = 3, 3319 RTW89_GILTF_1XHE16 = 4, 3320 RTW89_GILTF_1XHE08 = 5, 3321 RTW89_GILTF_MAX 3322 }; 3323 3324 enum rtw89_rx_frame_type { 3325 RTW89_RX_TYPE_MGNT = 0, 3326 RTW89_RX_TYPE_CTRL = 1, 3327 RTW89_RX_TYPE_DATA = 2, 3328 RTW89_RX_TYPE_RSVD = 3, 3329 }; 3330 3331 enum rtw89_efuse_block { 3332 RTW89_EFUSE_BLOCK_SYS = 0, 3333 RTW89_EFUSE_BLOCK_RF = 1, 3334 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3335 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3336 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3337 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3338 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3339 RTW89_EFUSE_BLOCK_ADIE = 7, 3340 3341 RTW89_EFUSE_BLOCK_NUM, 3342 RTW89_EFUSE_BLOCK_IGNORE, 3343 }; 3344 3345 struct rtw89_ra_info { 3346 u8 is_dis_ra:1; 3347 /* Bit0 : CCK 3348 * Bit1 : OFDM 3349 * Bit2 : HT 3350 * Bit3 : VHT 3351 * Bit4 : HE 3352 * Bit5 : EHT 3353 */ 3354 u8 mode_ctrl:6; 3355 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3356 u8 macid; 3357 u8 dcm_cap:1; 3358 u8 er_cap:1; 3359 u8 init_rate_lv:2; 3360 u8 upd_all:1; 3361 u8 en_sgi:1; 3362 u8 ldpc_cap:1; 3363 u8 stbc_cap:1; 3364 u8 ss_num:3; 3365 u8 giltf:3; 3366 u8 upd_bw_nss_mask:1; 3367 u8 upd_mask:1; 3368 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3369 /* BFee CSI */ 3370 u8 band_num; 3371 u8 ra_csi_rate_en:1; 3372 u8 fixed_csi_rate_en:1; 3373 u8 cr_tbl_sel:1; 3374 u8 fix_giltf_en:1; 3375 u8 fix_giltf:3; 3376 u8 rsvd2:1; 3377 u8 csi_mcs_ss_idx; 3378 u8 csi_mode:2; 3379 u8 csi_gi_ltf:3; 3380 u8 csi_bw:3; 3381 }; 3382 3383 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3384 #define RTW89_PPDU_MAC_INFO_SIZE 8 3385 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3386 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3387 3388 #define RTW89_MAX_RX_AGG_NUM 64 3389 #define RTW89_MAX_TX_AGG_NUM 128 3390 3391 struct rtw89_ampdu_params { 3392 u16 agg_num; 3393 bool amsdu; 3394 }; 3395 3396 struct rtw89_ra_report { 3397 struct rate_info txrate; 3398 u32 bit_rate; 3399 u16 hw_rate; 3400 bool might_fallback_legacy; 3401 }; 3402 3403 DECLARE_EWMA(rssi, 10, 16); 3404 DECLARE_EWMA(evm, 10, 16); 3405 DECLARE_EWMA(snr, 10, 16); 3406 3407 struct rtw89_ba_cam_entry { 3408 struct list_head list; 3409 u8 tid; 3410 }; 3411 3412 #define RTW89_MAX_ADDR_CAM_NUM 128 3413 #define RTW89_MAX_BSSID_CAM_NUM 20 3414 #define RTW89_MAX_SEC_CAM_NUM 128 3415 #define RTW89_MAX_BA_CAM_NUM 24 3416 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3417 3418 struct rtw89_addr_cam_entry { 3419 u8 addr_cam_idx; 3420 u8 offset; 3421 u8 len; 3422 u8 valid : 1; 3423 u8 addr_mask : 6; 3424 u8 wapi : 1; 3425 u8 mask_sel : 2; 3426 u8 bssid_cam_idx: 6; 3427 3428 u8 sec_ent_mode; 3429 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3430 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3431 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3432 }; 3433 3434 struct rtw89_bssid_cam_entry { 3435 u8 bssid[ETH_ALEN]; 3436 u8 phy_idx; 3437 u8 bssid_cam_idx; 3438 u8 offset; 3439 u8 len; 3440 u8 valid : 1; 3441 u8 num; 3442 }; 3443 3444 struct rtw89_sec_cam_entry { 3445 u8 sec_cam_idx; 3446 u8 offset; 3447 u8 len; 3448 u8 type : 4; 3449 u8 ext_key : 1; 3450 u8 spp_mode : 1; 3451 /* 256 bits */ 3452 u8 key[32]; 3453 3454 struct ieee80211_key_conf *key_conf; 3455 }; 3456 3457 struct rtw89_sta_link { 3458 struct rtw89_sta *rtwsta; 3459 struct list_head dlink_schd; 3460 unsigned int link_id; 3461 3462 u8 mac_id; 3463 u8 tx_retry; 3464 bool er_cap; 3465 struct rtw89_vif_link *rtwvif_link; 3466 struct rtw89_ra_info ra; 3467 struct rtw89_ra_report ra_report; 3468 int max_agg_wait; 3469 u8 prev_rssi; 3470 struct ewma_rssi avg_rssi; 3471 struct ewma_rssi rssi[RF_PATH_MAX]; 3472 struct ewma_snr avg_snr; 3473 struct ewma_evm evm_1ss; 3474 struct ewma_evm evm_min[RF_PATH_MAX]; 3475 struct ewma_evm evm_max[RF_PATH_MAX]; 3476 struct ieee80211_rx_status rx_status; 3477 u16 rx_hw_rate; 3478 __le32 htc_template; 3479 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3480 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3481 struct list_head ba_cam_list; 3482 3483 bool use_cfg_mask; 3484 struct cfg80211_bitrate_mask mask; 3485 3486 bool cctl_tx_time; 3487 u32 ampdu_max_time:4; 3488 bool cctl_tx_retry_limit; 3489 u32 data_tx_cnt_lmt:6; 3490 }; 3491 3492 struct rtw89_efuse { 3493 bool valid; 3494 bool power_k_valid; 3495 u8 xtal_cap; 3496 u8 addr[ETH_ALEN]; 3497 u8 rfe_type; 3498 char country_code[2]; 3499 u8 adc_td; 3500 }; 3501 3502 struct rtw89_phy_rate_pattern { 3503 u64 ra_mask; 3504 u16 rate; 3505 u8 ra_mode; 3506 bool enable; 3507 }; 3508 3509 struct rtw89_tx_wait_info { 3510 struct rcu_head rcu_head; 3511 struct completion completion; 3512 bool tx_done; 3513 }; 3514 3515 struct rtw89_tx_skb_data { 3516 struct rtw89_tx_wait_info __rcu *wait; 3517 u8 hci_priv[]; 3518 }; 3519 3520 #define RTW89_SCAN_NULL_TIMEOUT 30 3521 3522 #define RTW89_ROC_IDLE_TIMEOUT 500 3523 #define RTW89_ROC_TX_TIMEOUT 30 3524 enum rtw89_roc_state { 3525 RTW89_ROC_IDLE, 3526 RTW89_ROC_NORMAL, 3527 RTW89_ROC_MGMT, 3528 }; 3529 3530 struct rtw89_roc { 3531 struct ieee80211_channel chan; 3532 struct wiphy_delayed_work roc_work; 3533 enum ieee80211_roc_type type; 3534 enum rtw89_roc_state state; 3535 int duration; 3536 unsigned int link_id; 3537 }; 3538 3539 #define RTW89_P2P_MAX_NOA_NUM 2 3540 3541 struct rtw89_p2p_ie_head { 3542 u8 eid; 3543 u8 ie_len; 3544 u8 oui[3]; 3545 u8 oui_type; 3546 } __packed; 3547 3548 struct rtw89_noa_attr_head { 3549 u8 attr_type; 3550 __le16 attr_len; 3551 u8 index; 3552 u8 oppps_ctwindow; 3553 } __packed; 3554 3555 struct rtw89_p2p_noa_ie { 3556 struct rtw89_p2p_ie_head p2p_head; 3557 struct rtw89_noa_attr_head noa_head; 3558 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3559 } __packed; 3560 3561 struct rtw89_p2p_noa_setter { 3562 struct rtw89_p2p_noa_ie ie; 3563 u8 noa_count; 3564 u8 noa_index; 3565 }; 3566 3567 struct rtw89_ps_noa_once_handler { 3568 bool in_duration; 3569 u64 tsf_begin; 3570 u64 tsf_end; 3571 struct wiphy_delayed_work set_work; 3572 struct wiphy_delayed_work clr_work; 3573 }; 3574 3575 struct rtw89_vif_link { 3576 struct rtw89_vif *rtwvif; 3577 struct list_head dlink_schd; 3578 unsigned int link_id; 3579 3580 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3581 enum rtw89_chanctx_idx chanctx_idx; 3582 enum rtw89_reg_6ghz_power reg_6ghz_power; 3583 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3584 3585 u8 mac_id; 3586 u8 port; 3587 u8 mac_addr[ETH_ALEN]; 3588 u8 bssid[ETH_ALEN]; 3589 u8 phy_idx; 3590 u8 mac_idx; 3591 u8 net_type; 3592 u8 wifi_role; 3593 u8 self_role; 3594 u8 wmm; 3595 u8 bcn_hit_cond; 3596 u8 bcn_bw_idx; 3597 u8 hit_rule; 3598 u8 last_noa_nr; 3599 u64 sync_bcn_tsf; 3600 u64 last_sync_bcn_tsf; 3601 bool rand_tsf_done; 3602 bool trigger; 3603 bool lsig_txop; 3604 u8 tgt_ind; 3605 u8 frm_tgt_ind; 3606 bool wowlan_pattern; 3607 bool wowlan_uc; 3608 bool wowlan_magic; 3609 bool is_hesta; 3610 bool last_a_ctrl; 3611 bool dyn_tb_bedge_en; 3612 bool pre_pwr_diff_en; 3613 bool pwr_diff_en; 3614 u8 def_tri_idx; 3615 struct wiphy_work update_beacon_work; 3616 struct wiphy_delayed_work csa_beacon_work; 3617 struct rtw89_addr_cam_entry addr_cam; 3618 struct rtw89_bssid_cam_entry bssid_cam; 3619 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3620 struct rtw89_phy_rate_pattern rate_pattern; 3621 struct list_head general_pkt_list; 3622 struct rtw89_p2p_noa_setter p2p_noa; 3623 struct rtw89_ps_noa_once_handler noa_once; 3624 struct wiphy_delayed_work mcc_gc_detect_beacon_work; 3625 u8 detect_bcn_count; 3626 }; 3627 3628 enum rtw89_lv1_rcvy_step { 3629 RTW89_LV1_RCVY_STEP_1, 3630 RTW89_LV1_RCVY_STEP_2, 3631 }; 3632 3633 struct rtw89_hci_ops { 3634 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3635 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3636 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3637 void (*reset)(struct rtw89_dev *rtwdev); 3638 int (*start)(struct rtw89_dev *rtwdev); 3639 void (*stop)(struct rtw89_dev *rtwdev); 3640 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3641 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3642 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3643 3644 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3645 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3646 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3647 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3648 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3649 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3650 3651 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3652 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3653 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3654 int (*deinit)(struct rtw89_dev *rtwdev); 3655 3656 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3657 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3658 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3659 int (*napi_poll)(struct napi_struct *napi, int budget); 3660 3661 /* Deal with locks inside recovery_start and recovery_complete callbacks 3662 * by hci instance, and handle things which need to consider under SER. 3663 * e.g. turn on/off interrupts except for the one for halt notification. 3664 */ 3665 void (*recovery_start)(struct rtw89_dev *rtwdev); 3666 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3667 3668 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3669 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3670 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3671 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3672 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3673 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3674 void (*disable_intr)(struct rtw89_dev *rtwdev); 3675 void (*enable_intr)(struct rtw89_dev *rtwdev); 3676 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3677 }; 3678 3679 struct rtw89_hci_info { 3680 const struct rtw89_hci_ops *ops; 3681 enum rtw89_hci_type type; 3682 enum rtw89_hci_dle_type dle_type; 3683 u32 rpwm_addr; 3684 u32 cpwm_addr; 3685 bool paused; 3686 }; 3687 3688 struct rtw89_chip_ops { 3689 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3690 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3691 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3692 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3693 void (*bb_reset)(struct rtw89_dev *rtwdev, 3694 enum rtw89_phy_idx phy_idx); 3695 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3696 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3697 u32 addr, u32 mask); 3698 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3699 u32 addr, u32 mask, u32 data); 3700 void (*set_channel)(struct rtw89_dev *rtwdev, 3701 const struct rtw89_chan *chan, 3702 enum rtw89_mac_idx mac_idx, 3703 enum rtw89_phy_idx phy_idx); 3704 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3705 struct rtw89_channel_help_params *p, 3706 const struct rtw89_chan *chan, 3707 enum rtw89_mac_idx mac_idx, 3708 enum rtw89_phy_idx phy_idx); 3709 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3710 enum rtw89_efuse_block block); 3711 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3712 void (*fem_setup)(struct rtw89_dev *rtwdev); 3713 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3714 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3715 void (*rfk_init)(struct rtw89_dev *rtwdev); 3716 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3717 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3718 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3719 enum rtw89_phy_idx phy_idx, 3720 const struct rtw89_chan *chan); 3721 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3722 bool start); 3723 void (*rfk_track)(struct rtw89_dev *rtwdev); 3724 void (*power_trim)(struct rtw89_dev *rtwdev); 3725 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3726 const struct rtw89_chan *chan, 3727 enum rtw89_phy_idx phy_idx); 3728 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3729 enum rtw89_phy_idx phy_idx); 3730 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3731 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3732 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev, 3733 const struct rtw89_chan *chan); 3734 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3735 enum rtw89_phy_idx phy_idx); 3736 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3737 struct rtw89_rx_phy_ppdu *phy_ppdu, 3738 struct ieee80211_rx_status *status); 3739 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3740 struct rtw89_rx_phy_ppdu *phy_ppdu); 3741 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3742 struct rtw89_rx_desc_info *desc_info, 3743 struct ieee80211_rx_status *rx_status); 3744 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3745 enum rtw89_phy_idx phy_idx); 3746 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3747 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3748 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3749 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3750 enum rtw89_phy_idx phy_idx); 3751 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3752 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3753 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3754 struct rtw89_rx_desc_info *desc_info, 3755 u8 *data, u32 data_offset); 3756 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3757 struct rtw89_tx_desc_info *desc_info, 3758 void *txdesc); 3759 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3760 struct rtw89_tx_desc_info *desc_info, 3761 void *txdesc); 3762 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3763 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3764 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3765 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3766 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3767 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3768 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3769 struct rtw89_vif_link *rtwvif_link, 3770 struct rtw89_sta_link *rtwsta_link); 3771 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3772 struct rtw89_vif_link *rtwvif_link, 3773 struct rtw89_sta_link *rtwsta_link); 3774 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3775 struct rtw89_vif_link *rtwvif_link, 3776 struct rtw89_sta_link *rtwsta_link); 3777 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3778 struct rtw89_vif_link *rtwvif_link, 3779 struct rtw89_sta_link *rtwsta_link); 3780 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 3781 struct rtw89_sta_link *rtwsta_link); 3782 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev, 3783 struct rtw89_vif_link *rtwvif_link, 3784 u16 punctured); 3785 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3786 struct rtw89_vif_link *rtwvif_link, 3787 struct rtw89_sta_link *rtwsta_link); 3788 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3789 struct rtw89_vif_link *rtwvif_link); 3790 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3791 struct rtw89_vif_link *rtwvif_link, 3792 struct rtw89_sta_link *rtwsta_link, 3793 bool valid, struct ieee80211_ampdu_params *params); 3794 3795 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3796 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3797 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3798 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3799 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3800 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3801 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3802 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3803 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3804 }; 3805 3806 enum rtw89_dma_ch { 3807 RTW89_DMA_ACH0 = 0, 3808 RTW89_DMA_ACH1 = 1, 3809 RTW89_DMA_ACH2 = 2, 3810 RTW89_DMA_ACH3 = 3, 3811 RTW89_DMA_ACH4 = 4, 3812 RTW89_DMA_ACH5 = 5, 3813 RTW89_DMA_ACH6 = 6, 3814 RTW89_DMA_ACH7 = 7, 3815 RTW89_DMA_B0MG = 8, 3816 RTW89_DMA_B0HI = 9, 3817 RTW89_DMA_B1MG = 10, 3818 RTW89_DMA_B1HI = 11, 3819 RTW89_DMA_H2C = 12, 3820 RTW89_DMA_CH_NUM = 13 3821 }; 3822 3823 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3824 3825 enum rtw89_mlo_dbcc_mode { 3826 MLO_DBCC_NOT_SUPPORT = 1, 3827 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3828 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3829 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3830 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3831 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3832 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3833 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3834 DBCC_LEGACY = 0xffffffff, 3835 }; 3836 3837 enum rtw89_scan_be_operation { 3838 RTW89_SCAN_OP_STOP, 3839 RTW89_SCAN_OP_START, 3840 RTW89_SCAN_OP_SETPARM, 3841 RTW89_SCAN_OP_GETRPT, 3842 RTW89_SCAN_OP_NUM 3843 }; 3844 3845 enum rtw89_scan_be_mode { 3846 RTW89_SCAN_MODE_SA, 3847 RTW89_SCAN_MODE_MACC, 3848 RTW89_SCAN_MODE_NUM 3849 }; 3850 3851 enum rtw89_scan_be_opmode { 3852 RTW89_SCAN_OPMODE_NONE, 3853 RTW89_SCAN_OPMODE_TBTT, 3854 RTW89_SCAN_OPMODE_INTV, 3855 RTW89_SCAN_OPMODE_CNT, 3856 RTW89_SCAN_OPMODE_NUM, 3857 }; 3858 3859 struct rtw89_scan_option { 3860 bool enable; 3861 bool target_ch_mode; 3862 u8 num_macc_role; 3863 u8 num_opch; 3864 u8 repeat; 3865 u16 norm_pd; 3866 u16 slow_pd; 3867 u16 norm_cy; 3868 u8 opch_end; 3869 u16 delay; /* in unit of ms */ 3870 u64 prohib_chan; 3871 enum rtw89_phy_idx band; 3872 enum rtw89_scan_be_operation operation; 3873 enum rtw89_scan_be_mode scan_mode; 3874 enum rtw89_mlo_dbcc_mode mlo_mode; 3875 }; 3876 3877 enum rtw89_qta_mode { 3878 RTW89_QTA_SCC, 3879 RTW89_QTA_DBCC, 3880 RTW89_QTA_DLFW, 3881 RTW89_QTA_WOW, 3882 3883 /* keep last */ 3884 RTW89_QTA_INVALID, 3885 }; 3886 3887 struct rtw89_hfc_ch_cfg { 3888 u16 min; 3889 u16 max; 3890 #define grp_0 0 3891 #define grp_1 1 3892 #define grp_num 2 3893 u8 grp; 3894 }; 3895 3896 struct rtw89_hfc_ch_info { 3897 u16 aval; 3898 u16 used; 3899 }; 3900 3901 struct rtw89_hfc_pub_cfg { 3902 u16 grp0; 3903 u16 grp1; 3904 u16 pub_max; 3905 u16 wp_thrd; 3906 }; 3907 3908 struct rtw89_hfc_pub_info { 3909 u16 g0_used; 3910 u16 g1_used; 3911 u16 g0_aval; 3912 u16 g1_aval; 3913 u16 pub_aval; 3914 u16 wp_aval; 3915 }; 3916 3917 struct rtw89_hfc_prec_cfg { 3918 u16 ch011_prec; 3919 u16 h2c_prec; 3920 u16 wp_ch07_prec; 3921 u16 wp_ch811_prec; 3922 u8 ch011_full_cond; 3923 u8 h2c_full_cond; 3924 u8 wp_ch07_full_cond; 3925 u8 wp_ch811_full_cond; 3926 }; 3927 3928 struct rtw89_hfc_param { 3929 bool en; 3930 bool h2c_en; 3931 u8 mode; 3932 const struct rtw89_hfc_ch_cfg *ch_cfg; 3933 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3934 struct rtw89_hfc_pub_cfg pub_cfg; 3935 struct rtw89_hfc_pub_info pub_info; 3936 struct rtw89_hfc_prec_cfg prec_cfg; 3937 }; 3938 3939 struct rtw89_hfc_param_ini { 3940 const struct rtw89_hfc_ch_cfg *ch_cfg; 3941 const struct rtw89_hfc_pub_cfg *pub_cfg; 3942 const struct rtw89_hfc_prec_cfg *prec_cfg; 3943 u8 mode; 3944 }; 3945 3946 struct rtw89_dle_size { 3947 u16 pge_size; 3948 u16 lnk_pge_num; 3949 u16 unlnk_pge_num; 3950 /* for WiFi 7 chips below */ 3951 u32 srt_ofst; 3952 }; 3953 3954 struct rtw89_wde_quota { 3955 u16 hif; 3956 u16 wcpu; 3957 u16 pkt_in; 3958 u16 cpu_io; 3959 }; 3960 3961 struct rtw89_ple_quota { 3962 u16 cma0_tx; 3963 u16 cma1_tx; 3964 u16 c2h; 3965 u16 h2c; 3966 u16 wcpu; 3967 u16 mpdu_proc; 3968 u16 cma0_dma; 3969 u16 cma1_dma; 3970 u16 bb_rpt; 3971 u16 wd_rel; 3972 u16 cpu_io; 3973 u16 tx_rpt; 3974 /* for WiFi 7 chips below */ 3975 u16 h2d; 3976 }; 3977 3978 struct rtw89_rsvd_quota { 3979 u16 mpdu_info_tbl; 3980 u16 b0_csi; 3981 u16 b1_csi; 3982 u16 b0_lmr; 3983 u16 b1_lmr; 3984 u16 b0_ftm; 3985 u16 b1_ftm; 3986 u16 b0_smr; 3987 u16 b1_smr; 3988 u16 others; 3989 }; 3990 3991 struct rtw89_dle_rsvd_size { 3992 u32 srt_ofst; 3993 u32 size; 3994 }; 3995 3996 struct rtw89_dle_mem { 3997 enum rtw89_qta_mode mode; 3998 const struct rtw89_dle_size *wde_size; 3999 const struct rtw89_dle_size *ple_size; 4000 const struct rtw89_wde_quota *wde_min_qt; 4001 const struct rtw89_wde_quota *wde_max_qt; 4002 const struct rtw89_ple_quota *ple_min_qt; 4003 const struct rtw89_ple_quota *ple_max_qt; 4004 /* for WiFi 7 chips below */ 4005 const struct rtw89_rsvd_quota *rsvd_qt; 4006 const struct rtw89_dle_rsvd_size *rsvd0_size; 4007 const struct rtw89_dle_rsvd_size *rsvd1_size; 4008 }; 4009 4010 struct rtw89_reg_def { 4011 u32 addr; 4012 u32 mask; 4013 }; 4014 4015 struct rtw89_reg2_def { 4016 u32 addr; 4017 u32 data; 4018 }; 4019 4020 struct rtw89_reg3_def { 4021 u32 addr; 4022 u32 mask; 4023 u32 data; 4024 }; 4025 4026 struct rtw89_reg5_def { 4027 u8 flag; /* recognized by parsers */ 4028 u8 path; 4029 u32 addr; 4030 u32 mask; 4031 u32 data; 4032 }; 4033 4034 struct rtw89_reg_imr { 4035 u32 addr; 4036 u32 clr; 4037 u32 set; 4038 }; 4039 4040 struct rtw89_phy_table { 4041 const struct rtw89_reg2_def *regs; 4042 u32 n_regs; 4043 enum rtw89_rf_path rf_path; 4044 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 4045 enum rtw89_rf_path rf_path, void *data); 4046 }; 4047 4048 struct rtw89_txpwr_table { 4049 const void *data; 4050 u32 size; 4051 void (*load)(struct rtw89_dev *rtwdev, 4052 const struct rtw89_txpwr_table *tbl); 4053 }; 4054 4055 struct rtw89_txpwr_rule_2ghz { 4056 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4057 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4058 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4059 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4060 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4061 }; 4062 4063 struct rtw89_txpwr_rule_5ghz { 4064 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4065 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4066 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4067 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4068 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4069 }; 4070 4071 struct rtw89_txpwr_rule_6ghz { 4072 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4073 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4074 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4075 [RTW89_6G_CH_NUM]; 4076 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4077 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4078 [RTW89_6G_CH_NUM]; 4079 }; 4080 4081 struct rtw89_tx_shape { 4082 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4083 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4084 }; 4085 4086 struct rtw89_rfe_parms { 4087 const struct rtw89_txpwr_table *byr_tbl; 4088 struct rtw89_txpwr_rule_2ghz rule_2ghz; 4089 struct rtw89_txpwr_rule_5ghz rule_5ghz; 4090 struct rtw89_txpwr_rule_6ghz rule_6ghz; 4091 struct rtw89_txpwr_rule_2ghz rule_da_2ghz; 4092 struct rtw89_txpwr_rule_5ghz rule_da_5ghz; 4093 struct rtw89_txpwr_rule_6ghz rule_da_6ghz; 4094 struct rtw89_tx_shape tx_shape; 4095 bool has_da; 4096 }; 4097 4098 struct rtw89_rfe_parms_conf { 4099 const struct rtw89_rfe_parms *rfe_parms; 4100 u8 rfe_type; 4101 }; 4102 4103 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 4104 4105 struct rtw89_txpwr_conf { 4106 u8 rfe_type; 4107 u8 ent_sz; 4108 u32 num_ents; 4109 const void *data; 4110 }; 4111 4112 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4113 const struct rtw89_txpwr_conf *conf) 4114 { 4115 u8 valid_size = min(size, conf->ent_sz); 4116 4117 memcpy(entry, cursor, valid_size); 4118 return true; 4119 } 4120 4121 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4122 4123 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4124 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4125 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4126 (cursor) += (conf)->ent_sz) \ 4127 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4128 4129 struct rtw89_txpwr_byrate_data { 4130 struct rtw89_txpwr_conf conf; 4131 struct rtw89_txpwr_table tbl; 4132 }; 4133 4134 struct rtw89_txpwr_lmt_2ghz_data { 4135 struct rtw89_txpwr_conf conf; 4136 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4137 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4138 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4139 }; 4140 4141 struct rtw89_txpwr_lmt_5ghz_data { 4142 struct rtw89_txpwr_conf conf; 4143 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4144 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4145 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4146 }; 4147 4148 struct rtw89_txpwr_lmt_6ghz_data { 4149 struct rtw89_txpwr_conf conf; 4150 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4151 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4152 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4153 [RTW89_6G_CH_NUM]; 4154 }; 4155 4156 struct rtw89_txpwr_lmt_ru_2ghz_data { 4157 struct rtw89_txpwr_conf conf; 4158 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4159 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4160 }; 4161 4162 struct rtw89_txpwr_lmt_ru_5ghz_data { 4163 struct rtw89_txpwr_conf conf; 4164 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4165 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4166 }; 4167 4168 struct rtw89_txpwr_lmt_ru_6ghz_data { 4169 struct rtw89_txpwr_conf conf; 4170 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4171 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4172 [RTW89_6G_CH_NUM]; 4173 }; 4174 4175 struct rtw89_tx_shape_lmt_data { 4176 struct rtw89_txpwr_conf conf; 4177 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4178 }; 4179 4180 struct rtw89_tx_shape_lmt_ru_data { 4181 struct rtw89_txpwr_conf conf; 4182 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4183 }; 4184 4185 struct rtw89_rfe_data { 4186 struct rtw89_txpwr_byrate_data byrate; 4187 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4188 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4189 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4190 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz; 4191 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz; 4192 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz; 4193 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4194 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4195 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4196 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz; 4197 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz; 4198 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz; 4199 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4200 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4201 struct rtw89_rfe_parms rfe_parms; 4202 }; 4203 4204 struct rtw89_page_regs { 4205 u32 hci_fc_ctrl; 4206 u32 ch_page_ctrl; 4207 u32 ach_page_ctrl; 4208 u32 ach_page_info; 4209 u32 pub_page_info3; 4210 u32 pub_page_ctrl1; 4211 u32 pub_page_ctrl2; 4212 u32 pub_page_info1; 4213 u32 pub_page_info2; 4214 u32 wp_page_ctrl1; 4215 u32 wp_page_ctrl2; 4216 u32 wp_page_info1; 4217 }; 4218 4219 struct rtw89_imr_info { 4220 u32 wdrls_imr_set; 4221 u32 wsec_imr_reg; 4222 u32 wsec_imr_set; 4223 u32 mpdu_tx_imr_set; 4224 u32 mpdu_rx_imr_set; 4225 u32 sta_sch_imr_set; 4226 u32 txpktctl_imr_b0_reg; 4227 u32 txpktctl_imr_b0_clr; 4228 u32 txpktctl_imr_b0_set; 4229 u32 txpktctl_imr_b1_reg; 4230 u32 txpktctl_imr_b1_clr; 4231 u32 txpktctl_imr_b1_set; 4232 u32 wde_imr_clr; 4233 u32 wde_imr_set; 4234 u32 ple_imr_clr; 4235 u32 ple_imr_set; 4236 u32 host_disp_imr_clr; 4237 u32 host_disp_imr_set; 4238 u32 cpu_disp_imr_clr; 4239 u32 cpu_disp_imr_set; 4240 u32 other_disp_imr_clr; 4241 u32 other_disp_imr_set; 4242 u32 bbrpt_com_err_imr_reg; 4243 u32 bbrpt_chinfo_err_imr_reg; 4244 u32 bbrpt_err_imr_set; 4245 u32 bbrpt_dfs_err_imr_reg; 4246 u32 ptcl_imr_clr; 4247 u32 ptcl_imr_set; 4248 u32 cdma_imr_0_reg; 4249 u32 cdma_imr_0_clr; 4250 u32 cdma_imr_0_set; 4251 u32 cdma_imr_1_reg; 4252 u32 cdma_imr_1_clr; 4253 u32 cdma_imr_1_set; 4254 u32 phy_intf_imr_reg; 4255 u32 phy_intf_imr_clr; 4256 u32 phy_intf_imr_set; 4257 u32 rmac_imr_reg; 4258 u32 rmac_imr_clr; 4259 u32 rmac_imr_set; 4260 u32 tmac_imr_reg; 4261 u32 tmac_imr_clr; 4262 u32 tmac_imr_set; 4263 }; 4264 4265 struct rtw89_imr_table { 4266 const struct rtw89_reg_imr *regs; 4267 u32 n_regs; 4268 }; 4269 4270 struct rtw89_xtal_info { 4271 u32 xcap_reg; 4272 u32 sc_xo_mask; 4273 u32 sc_xi_mask; 4274 }; 4275 4276 struct rtw89_rrsr_cfgs { 4277 struct rtw89_reg3_def ref_rate; 4278 struct rtw89_reg3_def rsc; 4279 }; 4280 4281 struct rtw89_rfkill_regs { 4282 struct rtw89_reg3_def pinmux; 4283 struct rtw89_reg3_def mode; 4284 }; 4285 4286 struct rtw89_dig_regs { 4287 u32 seg0_pd_reg; 4288 u32 pd_lower_bound_mask; 4289 u32 pd_spatial_reuse_en; 4290 u32 bmode_pd_reg; 4291 u32 bmode_cca_rssi_limit_en; 4292 u32 bmode_pd_lower_bound_reg; 4293 u32 bmode_rssi_nocca_low_th_mask; 4294 struct rtw89_reg_def p0_lna_init; 4295 struct rtw89_reg_def p1_lna_init; 4296 struct rtw89_reg_def p0_tia_init; 4297 struct rtw89_reg_def p1_tia_init; 4298 struct rtw89_reg_def p0_rxb_init; 4299 struct rtw89_reg_def p1_rxb_init; 4300 struct rtw89_reg_def p0_p20_pagcugc_en; 4301 struct rtw89_reg_def p0_s20_pagcugc_en; 4302 struct rtw89_reg_def p1_p20_pagcugc_en; 4303 struct rtw89_reg_def p1_s20_pagcugc_en; 4304 }; 4305 4306 struct rtw89_edcca_regs { 4307 u32 edcca_level; 4308 u32 edcca_mask; 4309 u32 edcca_p_mask; 4310 u32 ppdu_level; 4311 u32 ppdu_mask; 4312 struct rtw89_edcca_p_regs { 4313 u32 rpt_a; 4314 u32 rpt_b; 4315 u32 rpt_sel; 4316 u32 rpt_sel_mask; 4317 } p[RTW89_PHY_NUM]; 4318 u32 rpt_sel_be; 4319 u32 rpt_sel_be_mask; 4320 u32 tx_collision_t2r_st; 4321 u32 tx_collision_t2r_st_mask; 4322 }; 4323 4324 struct rtw89_phy_ul_tb_info { 4325 bool dyn_tb_tri_en; 4326 u8 def_if_bandedge; 4327 }; 4328 4329 struct rtw89_antdiv_stats { 4330 struct ewma_rssi cck_rssi_avg; 4331 struct ewma_rssi ofdm_rssi_avg; 4332 struct ewma_rssi non_legacy_rssi_avg; 4333 u16 pkt_cnt_cck; 4334 u16 pkt_cnt_ofdm; 4335 u16 pkt_cnt_non_legacy; 4336 u32 evm; 4337 }; 4338 4339 struct rtw89_antdiv_info { 4340 struct rtw89_antdiv_stats target_stats; 4341 struct rtw89_antdiv_stats main_stats; 4342 struct rtw89_antdiv_stats aux_stats; 4343 u8 training_count; 4344 u8 rssi_pre; 4345 bool get_stats; 4346 }; 4347 4348 enum rtw89_chanctx_state { 4349 RTW89_CHANCTX_STATE_MCC_START, 4350 RTW89_CHANCTX_STATE_MCC_STOP, 4351 }; 4352 4353 enum rtw89_chanctx_callbacks { 4354 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4355 RTW89_CHANCTX_CALLBACK_RFK, 4356 RTW89_CHANCTX_CALLBACK_TAS, 4357 4358 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4359 }; 4360 4361 struct rtw89_chanctx_listener { 4362 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4363 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4364 }; 4365 4366 struct rtw89_chip_info { 4367 enum rtw89_core_chip_id chip_id; 4368 enum rtw89_chip_gen chip_gen; 4369 const struct rtw89_chip_ops *ops; 4370 const struct rtw89_mac_gen_def *mac_def; 4371 const struct rtw89_phy_gen_def *phy_def; 4372 const char *fw_basename; 4373 u8 fw_format_max; 4374 bool try_ce_fw; 4375 u8 bbmcu_nr; 4376 u32 needed_fw_elms; 4377 const struct rtw89_fw_blacklist *fw_blacklist; 4378 u32 fifo_size; 4379 bool small_fifo_size; 4380 u32 dle_scc_rsvd_size; 4381 u16 max_amsdu_limit; 4382 bool dis_2g_40m_ul_ofdma; 4383 u32 rsvd_ple_ofst; 4384 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM]; 4385 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM]; 4386 u8 wde_qempty_acq_grpnum; 4387 u8 wde_qempty_mgq_grpsel; 4388 u32 rf_base_addr[2]; 4389 u8 thermal_th[2]; 4390 u8 support_macid_num; 4391 u8 support_link_num; 4392 u8 support_chanctx_num; 4393 u8 support_bands; 4394 u16 support_bandwidths; 4395 bool support_unii4; 4396 bool support_rnr; 4397 bool support_ant_gain; 4398 bool support_tas; 4399 bool support_sar_by_ant; 4400 bool ul_tb_waveform_ctrl; 4401 bool ul_tb_pwr_diff; 4402 bool rx_freq_frome_ie; 4403 bool hw_sec_hdr; 4404 bool hw_mgmt_tx_encrypt; 4405 bool hw_tkip_crypto; 4406 bool hw_mlo_bmc_crypto; 4407 u8 rf_path_num; 4408 u8 tx_nss; 4409 u8 rx_nss; 4410 u8 acam_num; 4411 u8 bcam_num; 4412 u8 scam_num; 4413 u8 bacam_num; 4414 u8 bacam_dynamic_num; 4415 enum rtw89_bacam_ver bacam_ver; 4416 u8 ppdu_max_usr; 4417 4418 u8 sec_ctrl_efuse_size; 4419 u32 physical_efuse_size; 4420 u32 logical_efuse_size; 4421 u32 limit_efuse_size; 4422 u32 dav_phy_efuse_size; 4423 u32 dav_log_efuse_size; 4424 u32 phycap_addr; 4425 u32 phycap_size; 4426 const struct rtw89_efuse_block_cfg *efuse_blocks; 4427 4428 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4429 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4430 const struct rtw89_phy_table *bb_table; 4431 const struct rtw89_phy_table *bb_gain_table; 4432 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4433 const struct rtw89_phy_table *nctl_table; 4434 const struct rtw89_rfk_tbl *nctl_post_table; 4435 const struct rtw89_phy_dig_gain_table *dig_table; 4436 const struct rtw89_dig_regs *dig_regs; 4437 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4438 4439 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4440 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4441 const struct rtw89_rfe_parms *dflt_parms; 4442 const struct rtw89_chanctx_listener *chanctx_listener; 4443 4444 u8 txpwr_factor_bb; 4445 u8 txpwr_factor_rf; 4446 u8 txpwr_factor_mac; 4447 4448 u32 para_ver; 4449 u32 wlcx_desired; 4450 u8 scbd; 4451 u8 mailbox; 4452 4453 u8 afh_guard_ch; 4454 const u8 *wl_rssi_thres; 4455 const u8 *bt_rssi_thres; 4456 u8 rssi_tol; 4457 4458 u8 mon_reg_num; 4459 const struct rtw89_btc_fbtc_mreg *mon_reg; 4460 u8 rf_para_ulink_num; 4461 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4462 u8 rf_para_dlink_num; 4463 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4464 u8 ps_mode_supported; 4465 u8 low_power_hci_modes; 4466 4467 u32 h2c_cctl_func_id; 4468 u32 hci_func_en_addr; 4469 u32 h2c_desc_size; 4470 u32 txwd_body_size; 4471 u32 txwd_info_size; 4472 u32 h2c_ctrl_reg; 4473 const u32 *h2c_regs; 4474 struct rtw89_reg_def h2c_counter_reg; 4475 u32 c2h_ctrl_reg; 4476 const u32 *c2h_regs; 4477 struct rtw89_reg_def c2h_counter_reg; 4478 const struct rtw89_page_regs *page_regs; 4479 const u32 *wow_reason_reg; 4480 bool cfo_src_fd; 4481 bool cfo_hw_comp; 4482 const struct rtw89_reg_def *dcfo_comp; 4483 u8 dcfo_comp_sft; 4484 const struct rtw89_imr_info *imr_info; 4485 const struct rtw89_imr_table *imr_dmac_table; 4486 const struct rtw89_imr_table *imr_cmac_table; 4487 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4488 struct rtw89_reg_def bss_clr_vld; 4489 u32 bss_clr_map_reg; 4490 const struct rtw89_rfkill_regs *rfkill_init; 4491 struct rtw89_reg_def rfkill_get; 4492 u32 dma_ch_mask; 4493 const struct rtw89_edcca_regs *edcca_regs; 4494 const struct wiphy_wowlan_support *wowlan_stub; 4495 const struct rtw89_xtal_info *xtal_info; 4496 }; 4497 4498 struct rtw89_chip_variant { 4499 bool no_mcs_12_13: 1; 4500 u32 fw_min_ver_code; 4501 }; 4502 4503 union rtw89_bus_info { 4504 const struct rtw89_pci_info *pci; 4505 }; 4506 4507 struct rtw89_driver_info { 4508 const struct rtw89_chip_info *chip; 4509 const struct rtw89_chip_variant *variant; 4510 const struct dmi_system_id *quirks; 4511 union rtw89_bus_info bus; 4512 }; 4513 4514 enum rtw89_hcifc_mode { 4515 RTW89_HCIFC_POH = 0, 4516 RTW89_HCIFC_STF = 1, 4517 RTW89_HCIFC_SDIO = 2, 4518 4519 /* keep last */ 4520 RTW89_HCIFC_MODE_INVALID, 4521 }; 4522 4523 struct rtw89_dle_info { 4524 const struct rtw89_rsvd_quota *rsvd_qt; 4525 enum rtw89_qta_mode qta_mode; 4526 u16 ple_pg_size; 4527 u16 ple_free_pg; 4528 u16 c0_rx_qta; 4529 u16 c1_rx_qta; 4530 }; 4531 4532 enum rtw89_host_rpr_mode { 4533 RTW89_RPR_MODE_POH = 0, 4534 RTW89_RPR_MODE_STF 4535 }; 4536 4537 #define RTW89_COMPLETION_BUF_SIZE 40 4538 #define RTW89_WAIT_COND_IDLE UINT_MAX 4539 4540 struct rtw89_completion_data { 4541 bool err; 4542 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4543 }; 4544 4545 struct rtw89_wait_info { 4546 atomic_t cond; 4547 struct completion completion; 4548 struct rtw89_completion_data data; 4549 }; 4550 4551 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4552 4553 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4554 { 4555 init_completion(&wait->completion); 4556 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4557 } 4558 4559 struct rtw89_mac_info { 4560 struct rtw89_dle_info dle_info; 4561 struct rtw89_hfc_param hfc_param; 4562 enum rtw89_qta_mode qta_mode; 4563 u8 rpwm_seq_num; 4564 u8 cpwm_seq_num; 4565 4566 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4567 struct rtw89_wait_info fw_ofld_wait; 4568 /* see RTW89_PS_WAIT_COND series for wait condition */ 4569 struct rtw89_wait_info ps_wait; 4570 }; 4571 4572 enum rtw89_fwdl_check_type { 4573 RTW89_FWDL_CHECK_FREERTOS_DONE, 4574 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4575 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4576 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4577 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4578 }; 4579 4580 enum rtw89_fw_type { 4581 RTW89_FW_NORMAL = 1, 4582 RTW89_FW_WOWLAN = 3, 4583 RTW89_FW_NORMAL_CE = 5, 4584 RTW89_FW_BBMCU0 = 64, 4585 RTW89_FW_BBMCU1 = 65, 4586 RTW89_FW_LOGFMT = 255, 4587 }; 4588 4589 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \ 4590 RTW89_FW_FEATURE_##_grp##_MIN, \ 4591 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \ 4592 _features \ 4593 __RTW89_FW_FEATURE_##_grp##_E, \ 4594 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1 4595 4596 enum rtw89_fw_feature { 4597 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4598 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4599 RTW89_FW_FEATURE_TX_WAKE, 4600 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER, 4601 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0, 4602 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1, 4603 ), 4604 RTW89_FW_FEATURE_NO_PACKET_DROP, 4605 RTW89_FW_FEATURE_NO_DEEP_PS, 4606 RTW89_FW_FEATURE_NO_LPS_PG, 4607 RTW89_FW_FEATURE_BEACON_FILTER, 4608 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4609 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4610 RTW89_FW_FEATURE_WOW_REASON_V1, 4611 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4612 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4613 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4614 RTW89_FW_FEATURE_RFK_IQK_V0, 4615 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4616 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4617 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4618 RTW89_FW_FEATURE_LPS_CH_INFO, 4619 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4620 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 4621 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1, 4622 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP, 4623 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0, 4624 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG, 4625 }; 4626 4627 struct rtw89_fw_suit { 4628 enum rtw89_fw_type type; 4629 const u8 *data; 4630 u32 size; 4631 u8 major_ver; 4632 u8 minor_ver; 4633 u8 sub_ver; 4634 u8 sub_idex; 4635 u16 build_year; 4636 u16 build_mon; 4637 u16 build_date; 4638 u16 build_hour; 4639 u16 build_min; 4640 u8 cmd_ver; 4641 u8 hdr_ver; 4642 u32 commitid; 4643 }; 4644 4645 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4646 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4647 #define RTW89_FW_SUIT_VER_CODE(s) \ 4648 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4649 4650 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4651 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4652 (mfw_hdr)->ver.minor, \ 4653 (mfw_hdr)->ver.sub, \ 4654 (mfw_hdr)->ver.idx) 4655 4656 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4657 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4658 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4659 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4660 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4661 4662 struct rtw89_fw_req_info { 4663 const struct firmware *firmware; 4664 struct completion completion; 4665 }; 4666 4667 struct rtw89_fw_log { 4668 struct rtw89_fw_suit suit; 4669 bool enable; 4670 u32 last_fmt_id; 4671 u32 fmt_count; 4672 const __le32 *fmt_ids; 4673 const char *(*fmts)[]; 4674 }; 4675 4676 struct rtw89_fw_elm_info { 4677 struct rtw89_phy_table *bb_tbl; 4678 struct rtw89_phy_table *bb_gain; 4679 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4680 struct rtw89_phy_table *rf_nctl; 4681 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4682 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4683 const struct rtw89_regd_data *regd; 4684 }; 4685 4686 enum rtw89_fw_mss_dev_type { 4687 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4688 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4689 }; 4690 4691 struct rtw89_fw_secure { 4692 bool secure_boot: 1; 4693 bool can_mss_v1: 1; 4694 bool can_mss_v0: 1; 4695 u32 sb_sel_mgn; 4696 u8 mss_dev_type; 4697 u8 mss_cust_idx; 4698 u8 mss_key_num; 4699 u8 mss_idx; /* v0 */ 4700 }; 4701 4702 struct rtw89_fw_info { 4703 struct rtw89_fw_req_info req; 4704 int fw_format; 4705 u8 h2c_seq; 4706 u8 rec_seq; 4707 u8 h2c_counter; 4708 u8 c2h_counter; 4709 struct rtw89_fw_suit normal; 4710 struct rtw89_fw_suit wowlan; 4711 struct rtw89_fw_suit bbmcu0; 4712 struct rtw89_fw_suit bbmcu1; 4713 struct rtw89_fw_log log; 4714 u32 feature_map; 4715 struct rtw89_fw_elm_info elm_info; 4716 struct rtw89_fw_secure sec; 4717 }; 4718 4719 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4720 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4721 4722 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \ 4723 (!!((_fw)->feature_map & GENMASK(RTW89_FW_FEATURE_ ## _grp ## _MAX, \ 4724 RTW89_FW_FEATURE_ ## _grp ## _MIN))) 4725 4726 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4727 ((_fw)->feature_map |= BIT(_fw_feature)) 4728 4729 struct rtw89_cam_info { 4730 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4731 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4732 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4733 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4734 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4735 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4736 }; 4737 4738 enum rtw89_sar_sources { 4739 RTW89_SAR_SOURCE_NONE, 4740 RTW89_SAR_SOURCE_COMMON, 4741 RTW89_SAR_SOURCE_ACPI, 4742 4743 RTW89_SAR_SOURCE_NR, 4744 }; 4745 4746 enum rtw89_sar_subband { 4747 RTW89_SAR_2GHZ_SUBBAND, 4748 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4749 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4750 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4751 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4752 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4753 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4754 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4755 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4756 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4757 4758 RTW89_SAR_SUBBAND_NR, 4759 }; 4760 4761 struct rtw89_sar_cfg_common { 4762 bool set[RTW89_SAR_SUBBAND_NR]; 4763 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4764 }; 4765 4766 enum rtw89_acpi_sar_subband { 4767 RTW89_ACPI_SAR_2GHZ_SUBBAND, 4768 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */ 4769 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */ 4770 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4771 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4772 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4773 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4774 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4775 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4776 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4777 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4778 4779 NUM_OF_RTW89_ACPI_SAR_SUBBAND, 4780 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1, 4781 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1, 4782 }; 4783 4784 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */ 4785 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX 4786 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN 4787 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6 4788 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1) 4789 4790 struct rtw89_sar_entry_from_acpi { 4791 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4792 }; 4793 4794 struct rtw89_sar_table_from_acpi { 4795 /* If this table is active, must fill all fields according to either 4796 * configuration in BIOS or some default values for SAR to work well. 4797 */ 4798 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM]; 4799 }; 4800 4801 struct rtw89_sar_indicator_from_acpi { 4802 bool enable_sync; 4803 unsigned int fields; 4804 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath); 4805 4806 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path. 4807 * Not design with pointers since addresses will be invalid after 4808 * sync content with local container instance. 4809 */ 4810 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4811 }; 4812 4813 struct rtw89_sar_cfg_acpi { 4814 u8 downgrade_2tx; 4815 unsigned int valid_num; 4816 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL]; 4817 struct rtw89_sar_indicator_from_acpi indicator; 4818 }; 4819 4820 struct rtw89_sar_info { 4821 /* used to decide how to access SAR cfg union */ 4822 enum rtw89_sar_sources src; 4823 4824 /* reserved for different knids of SAR cfg struct. 4825 * supposed that a single cfg struct cannot handle various SAR sources. 4826 */ 4827 union { 4828 struct rtw89_sar_cfg_common cfg_common; 4829 struct rtw89_sar_cfg_acpi cfg_acpi; 4830 }; 4831 }; 4832 4833 enum rtw89_ant_gain_subband { 4834 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4835 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4836 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4837 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4838 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4839 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4840 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4841 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4842 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4843 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4844 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4845 4846 RTW89_ANT_GAIN_SUBBAND_NR, 4847 }; 4848 4849 enum rtw89_ant_gain_domain_type { 4850 RTW89_ANT_GAIN_ETSI = 0, 4851 4852 RTW89_ANT_GAIN_DOMAIN_NUM, 4853 }; 4854 4855 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4856 struct rtw89_ant_gain_info { 4857 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4858 u32 regd_enabled; 4859 bool block_country; 4860 }; 4861 4862 struct rtw89_6ghz_span { 4863 enum rtw89_sar_subband sar_subband_low; 4864 enum rtw89_sar_subband sar_subband_high; 4865 enum rtw89_acpi_sar_subband acpi_sar_subband_low; 4866 enum rtw89_acpi_sar_subband acpi_sar_subband_high; 4867 enum rtw89_ant_gain_subband ant_gain_subband_low; 4868 enum rtw89_ant_gain_subband ant_gain_subband_high; 4869 }; 4870 4871 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4872 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high) 4873 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4874 4875 enum rtw89_tas_state { 4876 RTW89_TAS_STATE_DPR_OFF, 4877 RTW89_TAS_STATE_DPR_ON, 4878 RTW89_TAS_STATE_STATIC_SAR, 4879 }; 4880 4881 #define RTW89_TAS_TX_RATIO_WINDOW 6 4882 #define RTW89_TAS_TXPWR_WINDOW 180 4883 struct rtw89_tas_info { 4884 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 4885 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 4886 u8 enabled_countries; 4887 u8 txpwr_head_idx; 4888 u8 txpwr_tail_idx; 4889 u8 tx_ratio_idx; 4890 u16 total_tx_ratio; 4891 u64 total_txpwr; 4892 u64 instant_txpwr; 4893 u32 window_size; 4894 s8 dpr_on_threshold; 4895 s8 dpr_off_threshold; 4896 enum rtw89_tas_state backup_state; 4897 enum rtw89_tas_state state; 4898 bool keep_history; 4899 bool block_regd; 4900 bool enable; 4901 bool pause; 4902 }; 4903 4904 struct rtw89_chanctx_cfg { 4905 enum rtw89_chanctx_idx idx; 4906 int ref_count; 4907 }; 4908 4909 enum rtw89_chanctx_changes { 4910 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4911 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4912 RTW89_CHANCTX_P2P_PS_CHANGE, 4913 RTW89_CHANCTX_BT_SLOT_CHANGE, 4914 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4915 4916 NUM_OF_RTW89_CHANCTX_CHANGES, 4917 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4918 }; 4919 4920 enum rtw89_entity_mode { 4921 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4922 RTW89_ENTITY_MODE_MCC_PREPARE, 4923 RTW89_ENTITY_MODE_MCC, 4924 4925 NUM_OF_RTW89_ENTITY_MODE, 4926 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4927 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4928 }; 4929 4930 #define RTW89_MAX_INTERFACE_NUM 2 4931 4932 /* only valid when running with chanctx_ops */ 4933 struct rtw89_entity_mgnt { 4934 struct list_head active_list; 4935 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4936 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4937 [__RTW89_MLD_MAX_LINK_NUM]; 4938 }; 4939 4940 struct rtw89_chanctx { 4941 struct cfg80211_chan_def chandef; 4942 struct rtw89_chan chan; 4943 struct rtw89_chan_rcd rcd; 4944 4945 /* only assigned when running with chanctx_ops */ 4946 struct rtw89_chanctx_cfg *cfg; 4947 }; 4948 4949 struct rtw89_edcca_bak { 4950 u8 a; 4951 u8 p; 4952 u8 ppdu; 4953 u8 th_old; 4954 }; 4955 4956 enum rtw89_dm_type { 4957 RTW89_DM_DYNAMIC_EDCCA, 4958 RTW89_DM_THERMAL_PROTECT, 4959 RTW89_DM_TAS, 4960 RTW89_DM_MLO, 4961 }; 4962 4963 #define RTW89_THERMAL_PROT_LV_MAX 5 4964 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 4965 4966 struct rtw89_hal { 4967 u32 rx_fltr; 4968 u8 cv; 4969 u8 acv; 4970 u32 antenna_tx; 4971 u32 antenna_rx; 4972 u8 tx_nss; 4973 u8 rx_nss; 4974 bool tx_path_diversity; 4975 bool ant_diversity; 4976 bool ant_diversity_fixed; 4977 bool support_cckpd; 4978 bool support_igi; 4979 bool no_mcs_12_13; 4980 4981 atomic_t roc_chanctx_idx; 4982 u8 roc_link_index; 4983 4984 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4985 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4986 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4987 struct cfg80211_chan_def roc_chandef; 4988 4989 bool entity_active[RTW89_PHY_NUM]; 4990 bool entity_pause; 4991 enum rtw89_entity_mode entity_mode; 4992 struct rtw89_entity_mgnt entity_mgnt; 4993 4994 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4995 4996 u8 thermal_prot_th; 4997 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 4998 }; 4999 5000 #define RTW89_MAX_MAC_ID_NUM 128 5001 #define RTW89_MAX_PKT_OFLD_NUM 255 5002 5003 enum rtw89_flags { 5004 RTW89_FLAG_POWERON, 5005 RTW89_FLAG_DMAC_FUNC, 5006 RTW89_FLAG_CMAC0_FUNC, 5007 RTW89_FLAG_CMAC1_FUNC, 5008 RTW89_FLAG_FW_RDY, 5009 RTW89_FLAG_RUNNING, 5010 RTW89_FLAG_PROBE_DONE, 5011 RTW89_FLAG_BFEE_MON, 5012 RTW89_FLAG_BFEE_EN, 5013 RTW89_FLAG_BFEE_TIMER_KEEP, 5014 RTW89_FLAG_NAPI_RUNNING, 5015 RTW89_FLAG_LEISURE_PS, 5016 RTW89_FLAG_LOW_POWER_MODE, 5017 RTW89_FLAG_INACTIVE_PS, 5018 RTW89_FLAG_CRASH_SIMULATING, 5019 RTW89_FLAG_SER_HANDLING, 5020 RTW89_FLAG_WOWLAN, 5021 RTW89_FLAG_FORBIDDEN_TRACK_WORK, 5022 RTW89_FLAG_CHANGING_INTERFACE, 5023 RTW89_FLAG_HW_RFKILL_STATE, 5024 RTW89_FLAG_UNPLUGGED, 5025 5026 NUM_OF_RTW89_FLAGS, 5027 }; 5028 5029 enum rtw89_quirks { 5030 RTW89_QUIRK_PCI_BER, 5031 RTW89_QUIRK_THERMAL_PROT_120C, 5032 RTW89_QUIRK_THERMAL_PROT_110C, 5033 5034 NUM_OF_RTW89_QUIRKS, 5035 }; 5036 5037 enum rtw89_custid { 5038 RTW89_CUSTID_NONE, 5039 RTW89_CUSTID_ACER, 5040 RTW89_CUSTID_AMD, 5041 RTW89_CUSTID_ASUS, 5042 RTW89_CUSTID_DELL, 5043 RTW89_CUSTID_HP, 5044 RTW89_CUSTID_LENOVO, 5045 }; 5046 5047 enum rtw89_pkt_drop_sel { 5048 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5049 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5050 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5051 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5052 RTW89_PKT_DROP_SEL_MACID_ALL, 5053 RTW89_PKT_DROP_SEL_MG0_ONCE, 5054 RTW89_PKT_DROP_SEL_HIQ_ONCE, 5055 RTW89_PKT_DROP_SEL_HIQ_PORT, 5056 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 5057 RTW89_PKT_DROP_SEL_BAND, 5058 RTW89_PKT_DROP_SEL_BAND_ONCE, 5059 RTW89_PKT_DROP_SEL_REL_MACID, 5060 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 5061 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 5062 }; 5063 5064 struct rtw89_pkt_drop_params { 5065 enum rtw89_pkt_drop_sel sel; 5066 enum rtw89_mac_idx mac_band; 5067 u8 macid; 5068 u8 port; 5069 u8 mbssid; 5070 bool tf_trs; 5071 u32 macid_band_sel[4]; 5072 }; 5073 5074 struct rtw89_pkt_stat { 5075 u16 beacon_nr; 5076 u8 beacon_rate; 5077 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 5078 }; 5079 5080 DECLARE_EWMA(thermal, 4, 4); 5081 5082 struct rtw89_phy_stat { 5083 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 5084 u8 last_thermal_max; 5085 struct ewma_rssi bcn_rssi; 5086 struct rtw89_pkt_stat cur_pkt_stat; 5087 struct rtw89_pkt_stat last_pkt_stat; 5088 }; 5089 5090 enum rtw89_rfk_report_state { 5091 RTW89_RFK_STATE_START = 0x0, 5092 RTW89_RFK_STATE_OK = 0x1, 5093 RTW89_RFK_STATE_FAIL = 0x2, 5094 RTW89_RFK_STATE_TIMEOUT = 0x3, 5095 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 5096 }; 5097 5098 struct rtw89_rfk_wait_info { 5099 struct completion completion; 5100 ktime_t start_time; 5101 enum rtw89_rfk_report_state state; 5102 u8 version; 5103 }; 5104 5105 #define RTW89_DACK_PATH_NR 2 5106 #define RTW89_DACK_IDX_NR 2 5107 #define RTW89_DACK_MSBK_NR 16 5108 struct rtw89_dack_info { 5109 bool dack_done; 5110 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 5111 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5112 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5113 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5114 u32 dack_cnt; 5115 bool addck_timeout[RTW89_DACK_PATH_NR]; 5116 bool dadck_timeout[RTW89_DACK_PATH_NR]; 5117 bool msbk_timeout[RTW89_DACK_PATH_NR]; 5118 }; 5119 5120 enum rtw89_rfk_chs_nrs { 5121 __RTW89_RFK_CHS_NR_V0 = 2, 5122 __RTW89_RFK_CHS_NR_V1 = 3, 5123 5124 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 5125 }; 5126 5127 struct rtw89_rfk_mcc_info_data { 5128 u8 ch[RTW89_RFK_CHS_NR]; 5129 u8 band[RTW89_RFK_CHS_NR]; 5130 u8 bw[RTW89_RFK_CHS_NR]; 5131 u8 table_idx; 5132 }; 5133 5134 struct rtw89_rfk_mcc_info { 5135 struct rtw89_rfk_mcc_info_data data[2]; 5136 }; 5137 5138 #define RTW89_IQK_CHS_NR 2 5139 #define RTW89_IQK_PATH_NR 4 5140 5141 struct rtw89_lck_info { 5142 u8 thermal[RF_PATH_MAX]; 5143 }; 5144 5145 struct rtw89_rx_dck_info { 5146 u8 thermal[RF_PATH_MAX]; 5147 }; 5148 5149 struct rtw89_iqk_info { 5150 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5151 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5152 bool lok_fail[RTW89_IQK_PATH_NR]; 5153 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5154 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5155 u32 iqk_fail_cnt; 5156 bool is_iqk_init; 5157 u32 iqk_channel[RTW89_IQK_CHS_NR]; 5158 u8 iqk_band[RTW89_IQK_PATH_NR]; 5159 u8 iqk_ch[RTW89_IQK_PATH_NR]; 5160 u8 iqk_bw[RTW89_IQK_PATH_NR]; 5161 u8 iqk_times; 5162 u8 version; 5163 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 5164 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 5165 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 5166 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 5167 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 5168 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 5169 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 5170 bool is_nbiqk; 5171 bool iqk_fft_en; 5172 bool iqk_xym_en; 5173 bool iqk_sram_en; 5174 bool iqk_cfir_en; 5175 u32 syn1to2; 5176 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5177 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 5178 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5179 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5180 }; 5181 5182 #define RTW89_DPK_RF_PATH 2 5183 #define RTW89_DPK_AVG_THERMAL_NUM 8 5184 #define RTW89_DPK_BKUP_NUM 2 5185 struct rtw89_dpk_bkup_para { 5186 enum rtw89_band band; 5187 enum rtw89_bandwidth bw; 5188 u8 ch; 5189 u8 path_ok; 5190 u8 mdpd_en; 5191 u8 txagc_dpk; 5192 u8 ther_dpk; 5193 u8 gs; 5194 u16 pwsf; 5195 }; 5196 5197 struct rtw89_dpk_info { 5198 bool is_dpk_enable; 5199 bool is_dpk_reload_en; 5200 u8 dpk_gs[RTW89_PHY_NUM]; 5201 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5202 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5203 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5204 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5205 u8 cur_idx[RTW89_DPK_RF_PATH]; 5206 u8 cur_k_set; 5207 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5208 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 5209 u32 dpk_order[RTW89_DPK_RF_PATH]; 5210 }; 5211 5212 struct rtw89_fem_info { 5213 bool elna_2g; 5214 bool elna_5g; 5215 bool epa_2g; 5216 bool epa_5g; 5217 bool epa_6g; 5218 }; 5219 5220 struct rtw89_phy_ch_info { 5221 u8 rssi_min; 5222 u16 rssi_min_macid; 5223 u8 pre_rssi_min; 5224 u8 rssi_max; 5225 u16 rssi_max_macid; 5226 u8 rxsc_160; 5227 u8 rxsc_80; 5228 u8 rxsc_40; 5229 u8 rxsc_20; 5230 u8 rxsc_l; 5231 u8 is_noisy; 5232 }; 5233 5234 struct rtw89_agc_gaincode_set { 5235 u8 lna_idx; 5236 u8 tia_idx; 5237 u8 rxb_idx; 5238 }; 5239 5240 #define IGI_RSSI_TH_NUM 5 5241 #define FA_TH_NUM 4 5242 #define TIA_LNA_OP1DB_NUM 8 5243 #define LNA_GAIN_NUM 7 5244 #define TIA_GAIN_NUM 2 5245 struct rtw89_dig_info { 5246 struct rtw89_agc_gaincode_set cur_gaincode; 5247 bool force_gaincode_idx_en; 5248 struct rtw89_agc_gaincode_set force_gaincode; 5249 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5250 u16 fa_th[FA_TH_NUM]; 5251 u8 igi_rssi; 5252 u8 igi_fa_rssi; 5253 u8 fa_rssi_ofst; 5254 u8 dyn_igi_max; 5255 u8 dyn_igi_min; 5256 bool dyn_pd_th_en; 5257 u8 dyn_pd_th_max; 5258 u8 pd_low_th_ofst; 5259 u8 ib_pbk; 5260 s8 ib_pkpwr; 5261 s8 lna_gain_a[LNA_GAIN_NUM]; 5262 s8 lna_gain_g[LNA_GAIN_NUM]; 5263 s8 *lna_gain; 5264 s8 tia_gain_a[TIA_GAIN_NUM]; 5265 s8 tia_gain_g[TIA_GAIN_NUM]; 5266 s8 *tia_gain; 5267 u32 bak_dig; 5268 bool is_linked_pre; 5269 bool bypass_dig; 5270 bool pause_dig; 5271 }; 5272 5273 enum rtw89_multi_cfo_mode { 5274 RTW89_PKT_BASED_AVG_MODE = 0, 5275 RTW89_ENTRY_BASED_AVG_MODE = 1, 5276 RTW89_TP_BASED_AVG_MODE = 2, 5277 }; 5278 5279 enum rtw89_phy_cfo_status { 5280 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5281 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5282 RTW89_PHY_DCFO_STATE_HOLD = 2, 5283 RTW89_PHY_DCFO_STATE_MAX 5284 }; 5285 5286 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5287 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5288 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5289 }; 5290 5291 struct rtw89_cfo_tracking_info { 5292 u16 cfo_timer_ms; 5293 bool cfo_trig_by_timer_en; 5294 enum rtw89_phy_cfo_status phy_cfo_status; 5295 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5296 u8 phy_cfo_trk_cnt; 5297 bool is_adjust; 5298 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5299 bool apply_compensation; 5300 u8 crystal_cap; 5301 u8 crystal_cap_default; 5302 u8 def_x_cap; 5303 s8 x_cap_ofst; 5304 u32 sta_cfo_tolerance; 5305 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5306 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5307 s32 cfo_avg_pre; 5308 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5309 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5310 s32 dcfo_avg; 5311 s32 dcfo_avg_pre; 5312 u32 packet_count; 5313 u32 packet_count_pre; 5314 s32 residual_cfo_acc; 5315 u8 phy_cfotrk_state; 5316 u8 phy_cfotrk_cnt; 5317 bool divergence_lock_en; 5318 u8 x_cap_lb; 5319 u8 x_cap_ub; 5320 u8 lock_cnt; 5321 }; 5322 5323 enum rtw89_tssi_mode { 5324 RTW89_TSSI_NORMAL = 0, 5325 RTW89_TSSI_SCAN = 1, 5326 }; 5327 5328 enum rtw89_tssi_alimk_band { 5329 TSSI_ALIMK_2G = 0, 5330 TSSI_ALIMK_5GL, 5331 TSSI_ALIMK_5GM, 5332 TSSI_ALIMK_5GH, 5333 TSSI_ALIMK_MAX 5334 }; 5335 5336 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5337 #define TSSI_TRIM_CH_GROUP_NUM 8 5338 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5339 5340 #define TSSI_CCK_CH_GROUP_NUM 6 5341 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5342 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5343 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5344 #define TSSI_MCS_CH_GROUP_NUM \ 5345 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5346 #define TSSI_MAX_CH_NUM 67 5347 #define TSSI_ALIMK_VALUE_NUM 8 5348 5349 struct rtw89_tssi_info { 5350 u8 thermal[RF_PATH_MAX]; 5351 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5352 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5353 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5354 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5355 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5356 s8 extra_ofst[RF_PATH_MAX]; 5357 bool tssi_tracking_check[RF_PATH_MAX]; 5358 u8 default_txagc_offset[RF_PATH_MAX]; 5359 u32 base_thermal[RF_PATH_MAX]; 5360 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5361 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5362 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5363 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5364 u64 tssi_alimk_time; 5365 }; 5366 5367 struct rtw89_power_trim_info { 5368 bool pg_thermal_trim; 5369 bool pg_pa_bias_trim; 5370 u8 thermal_trim[RF_PATH_MAX]; 5371 u8 pa_bias_trim[RF_PATH_MAX]; 5372 u8 pad_bias_trim[RF_PATH_MAX]; 5373 }; 5374 5375 enum rtw89_regd_func { 5376 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 5377 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 5378 5379 NUM_OF_RTW89_REGD_FUNC, 5380 }; 5381 5382 struct rtw89_regd { 5383 char alpha2[3]; 5384 u8 txpwr_regd[RTW89_BAND_NUM]; 5385 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 5386 }; 5387 5388 struct rtw89_regd_data { 5389 unsigned int nr; 5390 struct rtw89_regd map[] __counted_by(nr); 5391 }; 5392 5393 struct rtw89_regd_ctrl { 5394 unsigned int nr; 5395 const struct rtw89_regd *map; 5396 }; 5397 5398 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5399 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5400 #define RTW89_5GHZ_UNII4_START_INDEX 25 5401 5402 struct rtw89_regulatory_info { 5403 struct rtw89_regd_ctrl ctrl; 5404 const struct rtw89_regd *regd; 5405 enum rtw89_reg_6ghz_power reg_6ghz_power; 5406 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5407 bool txpwr_uk_follow_etsi; 5408 5409 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5410 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5411 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5412 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM); 5413 }; 5414 5415 enum rtw89_ifs_clm_application { 5416 RTW89_IFS_CLM_INIT = 0, 5417 RTW89_IFS_CLM_BACKGROUND = 1, 5418 RTW89_IFS_CLM_ACS = 2, 5419 RTW89_IFS_CLM_DIG = 3, 5420 RTW89_IFS_CLM_TDMA_DIG = 4, 5421 RTW89_IFS_CLM_DBG = 5, 5422 RTW89_IFS_CLM_DBG_MANUAL = 6 5423 }; 5424 5425 enum rtw89_env_racing_lv { 5426 RTW89_RAC_RELEASE = 0, 5427 RTW89_RAC_LV_1 = 1, 5428 RTW89_RAC_LV_2 = 2, 5429 RTW89_RAC_LV_3 = 3, 5430 RTW89_RAC_LV_4 = 4, 5431 RTW89_RAC_MAX_NUM = 5 5432 }; 5433 5434 struct rtw89_ccx_para_info { 5435 enum rtw89_env_racing_lv rac_lv; 5436 u16 mntr_time; 5437 u8 nhm_manual_th_ofst; 5438 u8 nhm_manual_th0; 5439 enum rtw89_ifs_clm_application ifs_clm_app; 5440 u32 ifs_clm_manual_th_times; 5441 u32 ifs_clm_manual_th0; 5442 u8 fahm_manual_th_ofst; 5443 u8 fahm_manual_th0; 5444 u8 fahm_numer_opt; 5445 u8 fahm_denom_opt; 5446 }; 5447 5448 enum rtw89_ccx_edcca_opt_sc_idx { 5449 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5450 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5451 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5452 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5453 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5454 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5455 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5456 RTW89_CCX_EDCCA_SEG1_S3 = 7 5457 }; 5458 5459 enum rtw89_ccx_edcca_opt_bw_idx { 5460 RTW89_CCX_EDCCA_BW20_0 = 0, 5461 RTW89_CCX_EDCCA_BW20_1 = 1, 5462 RTW89_CCX_EDCCA_BW20_2 = 2, 5463 RTW89_CCX_EDCCA_BW20_3 = 3, 5464 RTW89_CCX_EDCCA_BW20_4 = 4, 5465 RTW89_CCX_EDCCA_BW20_5 = 5, 5466 RTW89_CCX_EDCCA_BW20_6 = 6, 5467 RTW89_CCX_EDCCA_BW20_7 = 7 5468 }; 5469 5470 #define RTW89_NHM_TH_NUM 11 5471 #define RTW89_FAHM_TH_NUM 11 5472 #define RTW89_NHM_RPT_NUM 12 5473 #define RTW89_FAHM_RPT_NUM 12 5474 #define RTW89_IFS_CLM_NUM 4 5475 struct rtw89_env_monitor_info { 5476 u8 ccx_watchdog_result; 5477 bool ccx_ongoing; 5478 u8 ccx_rac_lv; 5479 bool ccx_manual_ctrl; 5480 u16 ifs_clm_mntr_time; 5481 enum rtw89_ifs_clm_application ifs_clm_app; 5482 u16 ccx_period; 5483 u8 ccx_unit_idx; 5484 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5485 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5486 u16 ifs_clm_tx; 5487 u16 ifs_clm_edcca_excl_cca; 5488 u16 ifs_clm_ofdmfa; 5489 u16 ifs_clm_ofdmcca_excl_fa; 5490 u16 ifs_clm_cckfa; 5491 u16 ifs_clm_cckcca_excl_fa; 5492 u16 ifs_clm_total_ifs; 5493 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5494 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5495 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5496 u8 ifs_clm_tx_ratio; 5497 u8 ifs_clm_edcca_excl_cca_ratio; 5498 u8 ifs_clm_cck_fa_ratio; 5499 u8 ifs_clm_ofdm_fa_ratio; 5500 u8 ifs_clm_cck_cca_excl_fa_ratio; 5501 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5502 u16 ifs_clm_cck_fa_permil; 5503 u16 ifs_clm_ofdm_fa_permil; 5504 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5505 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5506 }; 5507 5508 enum rtw89_ser_rcvy_step { 5509 RTW89_SER_DRV_STOP_TX, 5510 RTW89_SER_DRV_STOP_RX, 5511 RTW89_SER_DRV_STOP_RUN, 5512 RTW89_SER_HAL_STOP_DMA, 5513 RTW89_SER_SUPPRESS_LOG, 5514 RTW89_NUM_OF_SER_FLAGS 5515 }; 5516 5517 struct rtw89_ser { 5518 u8 state; 5519 u8 alarm_event; 5520 bool prehandle_l1; 5521 5522 struct work_struct ser_hdl_work; 5523 struct delayed_work ser_alarm_work; 5524 const struct state_ent *st_tbl; 5525 const struct event_ent *ev_tbl; 5526 struct list_head msg_q; 5527 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5528 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5529 }; 5530 5531 enum rtw89_mac_ax_ps_mode { 5532 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5533 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5534 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5535 RTW89_MAC_AX_PS_MODE_MAX = 3, 5536 }; 5537 5538 enum rtw89_last_rpwm_mode { 5539 RTW89_LAST_RPWM_PS = 0x0, 5540 RTW89_LAST_RPWM_ACTIVE = 0x6, 5541 }; 5542 5543 struct rtw89_lps_parm { 5544 u8 macid; 5545 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5546 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5547 }; 5548 5549 struct rtw89_ppdu_sts_info { 5550 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 5551 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 5552 }; 5553 5554 struct rtw89_early_h2c { 5555 struct list_head list; 5556 u8 *h2c; 5557 u16 h2c_len; 5558 }; 5559 5560 struct rtw89_hw_scan_extra_op { 5561 bool set; 5562 u8 macid; 5563 u8 port; 5564 struct rtw89_chan chan; 5565 struct rtw89_vif_link *rtwvif_link; 5566 }; 5567 5568 struct rtw89_hw_scan_info { 5569 struct rtw89_vif_link *scanning_vif; 5570 struct list_head pkt_list[NUM_NL80211_BANDS]; 5571 struct list_head chan_list; 5572 struct rtw89_chan op_chan; 5573 struct rtw89_hw_scan_extra_op extra_op; 5574 bool connected; 5575 bool abort; 5576 u16 delay; /* in unit of ms */ 5577 u8 seq: 2; 5578 }; 5579 5580 enum rtw89_phy_bb_gain_band { 5581 RTW89_BB_GAIN_BAND_2G = 0, 5582 RTW89_BB_GAIN_BAND_5G_L = 1, 5583 RTW89_BB_GAIN_BAND_5G_M = 2, 5584 RTW89_BB_GAIN_BAND_5G_H = 3, 5585 RTW89_BB_GAIN_BAND_6G_L = 4, 5586 RTW89_BB_GAIN_BAND_6G_M = 5, 5587 RTW89_BB_GAIN_BAND_6G_H = 6, 5588 RTW89_BB_GAIN_BAND_6G_UH = 7, 5589 5590 RTW89_BB_GAIN_BAND_NR, 5591 }; 5592 5593 enum rtw89_phy_gain_band_be { 5594 RTW89_BB_GAIN_BAND_2G_BE = 0, 5595 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5596 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5597 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5598 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5599 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5600 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5601 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5602 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5603 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5604 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5605 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5606 5607 RTW89_BB_GAIN_BAND_NR_BE, 5608 }; 5609 5610 enum rtw89_phy_bb_bw_be { 5611 RTW89_BB_BW_20_40 = 0, 5612 RTW89_BB_BW_80_160_320 = 1, 5613 5614 RTW89_BB_BW_NR_BE, 5615 }; 5616 5617 enum rtw89_bw20_sc { 5618 RTW89_BW20_SC_20M = 1, 5619 RTW89_BW20_SC_40M = 2, 5620 RTW89_BW20_SC_80M = 4, 5621 RTW89_BW20_SC_160M = 8, 5622 RTW89_BW20_SC_320M = 16, 5623 }; 5624 5625 enum rtw89_cmac_table_bw { 5626 RTW89_CMAC_BW_20M = 0, 5627 RTW89_CMAC_BW_40M = 1, 5628 RTW89_CMAC_BW_80M = 2, 5629 RTW89_CMAC_BW_160M = 3, 5630 RTW89_CMAC_BW_320M = 4, 5631 5632 RTW89_CMAC_BW_NR, 5633 }; 5634 5635 enum rtw89_phy_bb_rxsc_num { 5636 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5637 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5638 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5639 }; 5640 5641 struct rtw89_phy_bb_gain_info { 5642 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5643 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5644 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5645 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5646 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5647 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5648 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5649 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5650 [RTW89_BB_RXSC_NUM_40]; 5651 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5652 [RTW89_BB_RXSC_NUM_80]; 5653 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5654 [RTW89_BB_RXSC_NUM_160]; 5655 }; 5656 5657 struct rtw89_phy_bb_gain_info_be { 5658 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5659 [LNA_GAIN_NUM]; 5660 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5661 [TIA_GAIN_NUM]; 5662 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5663 [RF_PATH_MAX][LNA_GAIN_NUM]; 5664 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5665 [RF_PATH_MAX][LNA_GAIN_NUM]; 5666 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5667 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5668 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5669 [RTW89_BW20_SC_20M]; 5670 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5671 [RTW89_BW20_SC_40M]; 5672 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5673 [RTW89_BW20_SC_80M]; 5674 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5675 [RTW89_BW20_SC_160M]; 5676 }; 5677 5678 struct rtw89_phy_efuse_gain { 5679 bool offset_valid; 5680 bool comp_valid; 5681 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5682 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5683 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5684 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5685 }; 5686 5687 #define RTW89_MAX_PATTERN_NUM 18 5688 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5689 #define RTW89_MAX_PATTERN_SIZE 128 5690 5691 struct rtw89_wow_cam_info { 5692 bool r_w; 5693 u8 idx; 5694 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5695 u16 crc; 5696 bool negative_pattern_match; 5697 bool skip_mac_hdr; 5698 bool uc; 5699 bool mc; 5700 bool bc; 5701 bool valid; 5702 }; 5703 5704 struct rtw89_wow_key_info { 5705 u8 ptk_tx_iv[8]; 5706 u8 valid_check; 5707 u8 symbol_check_en; 5708 u8 gtk_keyidx; 5709 u8 rsvd[5]; 5710 u8 ptk_rx_iv[8]; 5711 u8 gtk_rx_iv[4][8]; 5712 } __packed; 5713 5714 struct rtw89_wow_gtk_info { 5715 u8 kck[32]; 5716 u8 kek[32]; 5717 u8 tk1[16]; 5718 u8 txmickey[8]; 5719 u8 rxmickey[8]; 5720 __le32 igtk_keyid; 5721 __le64 ipn; 5722 u8 igtk[2][32]; 5723 u8 psk[32]; 5724 } __packed; 5725 5726 struct rtw89_wow_aoac_report { 5727 u8 rpt_ver; 5728 u8 sec_type; 5729 u8 key_idx; 5730 u8 pattern_idx; 5731 u8 rekey_ok; 5732 u8 ptk_tx_iv[8]; 5733 u8 eapol_key_replay_count[8]; 5734 u8 gtk[32]; 5735 u8 ptk_rx_iv[8]; 5736 u8 gtk_rx_iv[4][8]; 5737 u64 igtk_key_id; 5738 u64 igtk_ipn; 5739 u8 igtk[32]; 5740 u8 csa_pri_ch; 5741 u8 csa_bw; 5742 u8 csa_ch_offset; 5743 u8 csa_chsw_failed; 5744 u8 csa_ch_band; 5745 }; 5746 5747 struct rtw89_wow_param { 5748 struct rtw89_vif_link *rtwvif_link; 5749 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5750 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5751 struct rtw89_wow_key_info key_info; 5752 struct rtw89_wow_gtk_info gtk_info; 5753 struct rtw89_wow_aoac_report aoac_rpt; 5754 u8 pattern_cnt; 5755 u8 ptk_alg; 5756 u8 gtk_alg; 5757 u8 ptk_keyidx; 5758 u8 akm; 5759 5760 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5761 struct rtw89_wait_info wait; 5762 5763 bool pno_inited; 5764 struct list_head pno_pkt_list; 5765 struct cfg80211_sched_scan_request *nd_config; 5766 }; 5767 5768 struct rtw89_mcc_limit { 5769 bool enable; 5770 u16 max_tob; /* TU; max time offset behind */ 5771 u16 max_toa; /* TU; max time offset ahead */ 5772 u16 max_dur; /* TU */ 5773 }; 5774 5775 struct rtw89_mcc_policy { 5776 u8 c2h_rpt; 5777 u8 tx_null_early; 5778 u8 dis_tx_null; 5779 u8 in_curr_ch; 5780 u8 dis_sw_retry; 5781 u8 sw_retry_count; 5782 }; 5783 5784 struct rtw89_mcc_role { 5785 struct rtw89_vif_link *rtwvif_link; 5786 struct rtw89_mcc_policy policy; 5787 struct rtw89_mcc_limit limit; 5788 5789 const struct rtw89_mcc_courtesy_cfg *crtz; 5790 5791 /* only valid when running with FW MRC mechanism */ 5792 u8 slot_idx; 5793 5794 /* byte-array in LE order for FW */ 5795 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5796 u8 probe_count; 5797 5798 u16 duration; /* TU */ 5799 u16 beacon_interval; /* TU */ 5800 bool is_2ghz; 5801 bool is_go; 5802 bool is_gc; 5803 bool ignore_bcn; 5804 }; 5805 5806 struct rtw89_mcc_bt_role { 5807 u16 duration; /* TU */ 5808 }; 5809 5810 struct rtw89_mcc_courtesy_cfg { 5811 u8 slot_num; 5812 u8 macid_tgt; 5813 }; 5814 5815 struct rtw89_mcc_courtesy { 5816 struct rtw89_mcc_courtesy_cfg ref; 5817 struct rtw89_mcc_courtesy_cfg aux; 5818 }; 5819 5820 enum rtw89_mcc_plan { 5821 RTW89_MCC_PLAN_TAIL_BT, 5822 RTW89_MCC_PLAN_MID_BT, 5823 RTW89_MCC_PLAN_NO_BT, 5824 5825 NUM_OF_RTW89_MCC_PLAN, 5826 }; 5827 5828 struct rtw89_mcc_pattern { 5829 s16 tob_ref; /* TU; time offset behind of reference role */ 5830 s16 toa_ref; /* TU; time offset ahead of reference role */ 5831 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5832 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5833 5834 enum rtw89_mcc_plan plan; 5835 struct rtw89_mcc_courtesy courtesy; 5836 }; 5837 5838 struct rtw89_mcc_sync { 5839 bool enable; 5840 u16 offset; /* TU */ 5841 u8 macid_src; 5842 u8 band_src; 5843 u8 port_src; 5844 u8 macid_tgt; 5845 u8 band_tgt; 5846 u8 port_tgt; 5847 }; 5848 5849 struct rtw89_mcc_config { 5850 struct rtw89_mcc_pattern pattern; 5851 struct rtw89_mcc_sync sync; 5852 u64 start_tsf; 5853 u64 start_tsf_in_aux_domain; 5854 u64 prepare_delay; 5855 u16 mcc_interval; /* TU */ 5856 u16 beacon_offset; /* TU */ 5857 }; 5858 5859 enum rtw89_mcc_mode { 5860 RTW89_MCC_MODE_GO_STA, 5861 RTW89_MCC_MODE_GC_STA, 5862 }; 5863 5864 struct rtw89_mcc_info { 5865 struct rtw89_wait_info wait; 5866 5867 u8 group; 5868 enum rtw89_mcc_mode mode; 5869 struct rtw89_mcc_role role_ref; /* reference role */ 5870 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5871 struct rtw89_mcc_bt_role bt_role; 5872 struct rtw89_mcc_config config; 5873 }; 5874 5875 enum rtw89_mlo_mode { 5876 RTW89_MLO_MODE_MLSR = 0, 5877 5878 NUM_OF_RTW89_MLO_MODE, 5879 }; 5880 5881 struct rtw89_mlo_info { 5882 struct rtw89_wait_info wait; 5883 }; 5884 5885 struct rtw89_dev { 5886 struct ieee80211_hw *hw; 5887 struct device *dev; 5888 const struct ieee80211_ops *ops; 5889 5890 bool dbcc_en; 5891 bool support_mlo; 5892 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5893 struct rtw89_hw_scan_info scan_info; 5894 const struct rtw89_chip_info *chip; 5895 const struct rtw89_chip_variant *variant; 5896 const struct rtw89_pci_info *pci_info; 5897 const struct rtw89_rfe_parms *rfe_parms; 5898 struct rtw89_hal hal; 5899 struct rtw89_mcc_info mcc; 5900 struct rtw89_mlo_info mlo; 5901 struct rtw89_mac_info mac; 5902 struct rtw89_fw_info fw; 5903 struct rtw89_hci_info hci; 5904 struct rtw89_efuse efuse; 5905 struct rtw89_traffic_stats stats; 5906 struct rtw89_rfe_data *rfe_data; 5907 enum rtw89_custid custid; 5908 5909 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 5910 refcount_t refcount_ap_info; 5911 5912 struct list_head rtwvifs_list; 5913 /* used to protect rf read write */ 5914 struct mutex rf_mutex; 5915 struct workqueue_struct *txq_wq; 5916 struct work_struct txq_work; 5917 struct delayed_work txq_reinvoke_work; 5918 /* used to protect ba_list and forbid_ba_list */ 5919 spinlock_t ba_lock; 5920 /* txqs to setup ba session */ 5921 struct list_head ba_list; 5922 /* txqs to forbid ba session */ 5923 struct list_head forbid_ba_list; 5924 struct work_struct ba_work; 5925 /* used to protect rpwm */ 5926 spinlock_t rpwm_lock; 5927 5928 struct rtw89_cam_info cam_info; 5929 5930 struct sk_buff_head c2h_queue; 5931 struct wiphy_work c2h_work; 5932 struct wiphy_work ips_work; 5933 struct wiphy_work cancel_6ghz_probe_work; 5934 struct work_struct load_firmware_work; 5935 5936 struct list_head early_h2c_list; 5937 5938 struct rtw89_ser ser; 5939 5940 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5941 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5942 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5943 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5944 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5945 5946 struct rtw89_phy_stat phystat; 5947 struct rtw89_rfk_wait_info rfk_wait; 5948 struct rtw89_dack_info dack; 5949 struct rtw89_iqk_info iqk; 5950 struct rtw89_dpk_info dpk; 5951 struct rtw89_rfk_mcc_info rfk_mcc; 5952 struct rtw89_lck_info lck; 5953 struct rtw89_rx_dck_info rx_dck; 5954 bool is_tssi_mode[RF_PATH_MAX]; 5955 bool is_bt_iqk_timeout; 5956 5957 struct rtw89_fem_info fem; 5958 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5959 struct rtw89_tssi_info tssi; 5960 struct rtw89_power_trim_info pwr_trim; 5961 5962 struct rtw89_cfo_tracking_info cfo_tracking; 5963 union { 5964 struct rtw89_phy_bb_gain_info ax; 5965 struct rtw89_phy_bb_gain_info_be be; 5966 } bb_gain; 5967 struct rtw89_phy_efuse_gain efuse_gain; 5968 struct rtw89_phy_ul_tb_info ul_tb_info; 5969 struct rtw89_antdiv_info antdiv; 5970 5971 struct rtw89_bb_ctx { 5972 enum rtw89_phy_idx phy_idx; 5973 struct rtw89_env_monitor_info env_monitor; 5974 struct rtw89_dig_info dig; 5975 struct rtw89_phy_ch_info ch_info; 5976 struct rtw89_edcca_bak edcca_bak; 5977 } bbs[RTW89_PHY_NUM]; 5978 5979 struct wiphy_delayed_work track_work; 5980 struct wiphy_delayed_work track_ps_work; 5981 struct wiphy_delayed_work chanctx_work; 5982 struct wiphy_delayed_work coex_act1_work; 5983 struct wiphy_delayed_work coex_bt_devinfo_work; 5984 struct wiphy_delayed_work coex_rfk_chk_work; 5985 struct wiphy_delayed_work cfo_track_work; 5986 struct wiphy_delayed_work mcc_prepare_done_work; 5987 struct delayed_work forbid_ba_work; 5988 struct wiphy_delayed_work antdiv_work; 5989 struct rtw89_ppdu_sts_info ppdu_sts; 5990 u8 total_sta_assoc; 5991 bool scanning; 5992 5993 struct rtw89_regulatory_info regulatory; 5994 struct rtw89_sar_info sar; 5995 struct rtw89_tas_info tas; 5996 struct rtw89_ant_gain_info ant_gain; 5997 5998 struct rtw89_btc btc; 5999 enum rtw89_ps_mode ps_mode; 6000 bool lps_enabled; 6001 6002 struct rtw89_wow_param wow; 6003 6004 /* napi structure */ 6005 struct net_device *netdev; 6006 struct napi_struct napi; 6007 int napi_budget_countdown; 6008 6009 struct rtw89_debugfs *debugfs; 6010 6011 /* HCI related data, keep last */ 6012 u8 priv[] __aligned(sizeof(void *)); 6013 }; 6014 6015 struct rtw89_link_conf_container { 6016 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 6017 }; 6018 6019 #define RTW89_VIF_IDLE_LINK_ID 0 6020 6021 struct rtw89_vif { 6022 struct rtw89_dev *rtwdev; 6023 struct list_head list; 6024 struct list_head mgnt_entry; 6025 struct rtw89_link_conf_container __rcu *snap_link_confs; 6026 6027 u8 mac_addr[ETH_ALEN]; 6028 __be32 ip_addr; 6029 6030 struct rtw89_traffic_stats stats; 6031 struct rtw89_traffic_stats stats_ps; 6032 u32 tdls_peer; 6033 6034 struct ieee80211_scan_ies *scan_ies; 6035 struct cfg80211_scan_request *scan_req; 6036 6037 struct rtw89_roc roc; 6038 bool offchan; 6039 6040 enum rtw89_mlo_mode mlo_mode; 6041 6042 struct list_head dlink_pool; 6043 u8 links_inst_valid_num; 6044 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6045 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6046 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 6047 }; 6048 6049 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 6050 const struct rtw89_vif *rtwvif, 6051 unsigned int link_id) 6052 { 6053 *rtwvif_link = rtwvif->links[link_id]; 6054 return !!*rtwvif_link; 6055 } 6056 6057 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 6058 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6059 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 6060 6061 enum rtw89_sta_flags { 6062 RTW89_REMOTE_STA_IN_PS, 6063 6064 NUM_OF_RTW89_STA_FLAGS, 6065 }; 6066 6067 struct rtw89_sta { 6068 struct rtw89_dev *rtwdev; 6069 struct rtw89_vif *rtwvif; 6070 6071 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 6072 6073 bool disassoc; 6074 6075 struct sk_buff_head roc_queue; 6076 6077 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 6078 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 6079 6080 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 6081 6082 struct list_head dlink_pool; 6083 u8 links_inst_valid_num; 6084 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6085 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6086 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 6087 }; 6088 6089 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 6090 const struct rtw89_sta *rtwsta, 6091 unsigned int link_id) 6092 { 6093 *rtwsta_link = rtwsta->links[link_id]; 6094 return !!*rtwsta_link; 6095 } 6096 6097 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 6098 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6099 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 6100 6101 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 6102 { 6103 /* const after init, so no need to check if active first */ 6104 return rtwvif->links_inst[0].mac_id; 6105 } 6106 6107 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 6108 { 6109 /* const after init, so no need to check if active first */ 6110 return rtwvif->links_inst[0].port; 6111 } 6112 6113 static inline struct rtw89_vif_link * 6114 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 6115 { 6116 if (index >= rtwvif->links_inst_valid_num || 6117 !test_bit(index, rtwvif->links_inst_map)) 6118 return NULL; 6119 return &rtwvif->links_inst[index]; 6120 } 6121 6122 static inline 6123 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 6124 { 6125 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6126 6127 return rtwvif_link - rtwvif->links_inst; 6128 } 6129 6130 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 6131 { 6132 /* const after init, so no need to check if active first */ 6133 return rtwsta->links_inst[0].mac_id; 6134 } 6135 6136 static inline struct rtw89_sta_link * 6137 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 6138 { 6139 if (index >= rtwsta->links_inst_valid_num || 6140 !test_bit(index, rtwsta->links_inst_map)) 6141 return NULL; 6142 return &rtwsta->links_inst[index]; 6143 } 6144 6145 static inline 6146 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 6147 { 6148 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6149 6150 return rtwsta_link - rtwsta->links_inst; 6151 } 6152 6153 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 6154 { 6155 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6156 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6157 6158 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6159 rtwsta_link); 6160 } 6161 6162 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 6163 { 6164 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6165 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6166 6167 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6168 NULL); 6169 synchronize_rcu(); 6170 } 6171 6172 static inline struct rtw89_sta_link * 6173 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 6174 { 6175 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 6176 } 6177 6178 #define rtw89_get_designated_link(links_holder) \ 6179 ({ \ 6180 typeof(links_holder) p = links_holder; \ 6181 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 6182 }) 6183 6184 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 6185 struct rtw89_core_tx_request *tx_req) 6186 { 6187 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 6188 } 6189 6190 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 6191 { 6192 rtwdev->hci.ops->reset(rtwdev); 6193 } 6194 6195 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 6196 { 6197 return rtwdev->hci.ops->start(rtwdev); 6198 } 6199 6200 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 6201 { 6202 rtwdev->hci.ops->stop(rtwdev); 6203 } 6204 6205 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 6206 { 6207 return rtwdev->hci.ops->deinit(rtwdev); 6208 } 6209 6210 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 6211 { 6212 rtwdev->hci.ops->pause(rtwdev, pause); 6213 } 6214 6215 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 6216 { 6217 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 6218 } 6219 6220 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 6221 { 6222 rtwdev->hci.ops->recalc_int_mit(rtwdev); 6223 } 6224 6225 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 6226 { 6227 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 6228 } 6229 6230 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 6231 { 6232 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 6233 } 6234 6235 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 6236 { 6237 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 6238 } 6239 6240 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 6241 bool drop) 6242 { 6243 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6244 return; 6245 6246 if (rtwdev->hci.ops->flush_queues) 6247 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 6248 } 6249 6250 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 6251 { 6252 if (rtwdev->hci.ops->recovery_start) 6253 rtwdev->hci.ops->recovery_start(rtwdev); 6254 } 6255 6256 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 6257 { 6258 if (rtwdev->hci.ops->recovery_complete) 6259 rtwdev->hci.ops->recovery_complete(rtwdev); 6260 } 6261 6262 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 6263 { 6264 if (rtwdev->hci.ops->enable_intr) 6265 rtwdev->hci.ops->enable_intr(rtwdev); 6266 } 6267 6268 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 6269 { 6270 if (rtwdev->hci.ops->disable_intr) 6271 rtwdev->hci.ops->disable_intr(rtwdev); 6272 } 6273 6274 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 6275 { 6276 if (rtwdev->hci.ops->ctrl_txdma_ch) 6277 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 6278 } 6279 6280 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6281 { 6282 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6283 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6284 } 6285 6286 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6287 { 6288 if (rtwdev->hci.ops->ctrl_trxhci) 6289 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6290 } 6291 6292 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6293 { 6294 int ret = 0; 6295 6296 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6297 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6298 return ret; 6299 } 6300 6301 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6302 { 6303 if (rtwdev->hci.ops->clr_idx_all) 6304 rtwdev->hci.ops->clr_idx_all(rtwdev); 6305 } 6306 6307 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6308 { 6309 int ret = 0; 6310 6311 if (rtwdev->hci.ops->rst_bdram) 6312 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6313 return ret; 6314 } 6315 6316 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6317 { 6318 if (rtwdev->hci.ops->clear) 6319 rtwdev->hci.ops->clear(rtwdev, pdev); 6320 } 6321 6322 static inline 6323 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6324 { 6325 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6326 6327 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 6328 } 6329 6330 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6331 { 6332 return rtwdev->hci.ops->read8(rtwdev, addr); 6333 } 6334 6335 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6336 { 6337 return rtwdev->hci.ops->read16(rtwdev, addr); 6338 } 6339 6340 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6341 { 6342 return rtwdev->hci.ops->read32(rtwdev, addr); 6343 } 6344 6345 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6346 { 6347 rtwdev->hci.ops->write8(rtwdev, addr, data); 6348 } 6349 6350 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6351 { 6352 rtwdev->hci.ops->write16(rtwdev, addr, data); 6353 } 6354 6355 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6356 { 6357 rtwdev->hci.ops->write32(rtwdev, addr, data); 6358 } 6359 6360 static inline void 6361 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6362 { 6363 u8 val; 6364 6365 val = rtw89_read8(rtwdev, addr); 6366 rtw89_write8(rtwdev, addr, val | bit); 6367 } 6368 6369 static inline void 6370 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6371 { 6372 u16 val; 6373 6374 val = rtw89_read16(rtwdev, addr); 6375 rtw89_write16(rtwdev, addr, val | bit); 6376 } 6377 6378 static inline void 6379 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6380 { 6381 u32 val; 6382 6383 val = rtw89_read32(rtwdev, addr); 6384 rtw89_write32(rtwdev, addr, val | bit); 6385 } 6386 6387 static inline void 6388 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6389 { 6390 u8 val; 6391 6392 val = rtw89_read8(rtwdev, addr); 6393 rtw89_write8(rtwdev, addr, val & ~bit); 6394 } 6395 6396 static inline void 6397 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6398 { 6399 u16 val; 6400 6401 val = rtw89_read16(rtwdev, addr); 6402 rtw89_write16(rtwdev, addr, val & ~bit); 6403 } 6404 6405 static inline void 6406 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6407 { 6408 u32 val; 6409 6410 val = rtw89_read32(rtwdev, addr); 6411 rtw89_write32(rtwdev, addr, val & ~bit); 6412 } 6413 6414 static inline u32 6415 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6416 { 6417 u32 shift = __ffs(mask); 6418 u32 orig; 6419 u32 ret; 6420 6421 orig = rtw89_read32(rtwdev, addr); 6422 ret = (orig & mask) >> shift; 6423 6424 return ret; 6425 } 6426 6427 static inline u16 6428 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6429 { 6430 u32 shift = __ffs(mask); 6431 u32 orig; 6432 u32 ret; 6433 6434 orig = rtw89_read16(rtwdev, addr); 6435 ret = (orig & mask) >> shift; 6436 6437 return ret; 6438 } 6439 6440 static inline u8 6441 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6442 { 6443 u32 shift = __ffs(mask); 6444 u32 orig; 6445 u32 ret; 6446 6447 orig = rtw89_read8(rtwdev, addr); 6448 ret = (orig & mask) >> shift; 6449 6450 return ret; 6451 } 6452 6453 static inline void 6454 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6455 { 6456 u32 shift = __ffs(mask); 6457 u32 orig; 6458 u32 set; 6459 6460 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6461 6462 orig = rtw89_read32(rtwdev, addr); 6463 set = (orig & ~mask) | ((data << shift) & mask); 6464 rtw89_write32(rtwdev, addr, set); 6465 } 6466 6467 static inline void 6468 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6469 { 6470 u32 shift; 6471 u16 orig, set; 6472 6473 mask &= 0xffff; 6474 shift = __ffs(mask); 6475 6476 orig = rtw89_read16(rtwdev, addr); 6477 set = (orig & ~mask) | ((data << shift) & mask); 6478 rtw89_write16(rtwdev, addr, set); 6479 } 6480 6481 static inline void 6482 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6483 { 6484 u32 shift; 6485 u8 orig, set; 6486 6487 mask &= 0xff; 6488 shift = __ffs(mask); 6489 6490 orig = rtw89_read8(rtwdev, addr); 6491 set = (orig & ~mask) | ((data << shift) & mask); 6492 rtw89_write8(rtwdev, addr, set); 6493 } 6494 6495 static inline u32 6496 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6497 u32 addr, u32 mask) 6498 { 6499 u32 val; 6500 6501 mutex_lock(&rtwdev->rf_mutex); 6502 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6503 mutex_unlock(&rtwdev->rf_mutex); 6504 6505 return val; 6506 } 6507 6508 static inline void 6509 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6510 u32 addr, u32 mask, u32 data) 6511 { 6512 mutex_lock(&rtwdev->rf_mutex); 6513 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6514 mutex_unlock(&rtwdev->rf_mutex); 6515 } 6516 6517 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6518 { 6519 void *p = rtwtxq; 6520 6521 return container_of(p, struct ieee80211_txq, drv_priv); 6522 } 6523 6524 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6525 struct ieee80211_txq *txq) 6526 { 6527 struct rtw89_txq *rtwtxq; 6528 6529 if (!txq) 6530 return; 6531 6532 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6533 INIT_LIST_HEAD(&rtwtxq->list); 6534 } 6535 6536 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6537 { 6538 void *p = rtwvif; 6539 6540 return container_of(p, struct ieee80211_vif, drv_priv); 6541 } 6542 6543 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6544 { 6545 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6546 } 6547 6548 static inline 6549 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6550 { 6551 return rtwvif_to_vif(rtwvif_link->rtwvif); 6552 } 6553 6554 static inline 6555 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6556 { 6557 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6558 } 6559 6560 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6561 { 6562 return (struct rtw89_vif *)vif->drv_priv; 6563 } 6564 6565 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6566 { 6567 return vif ? vif_to_rtwvif(vif) : NULL; 6568 } 6569 6570 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6571 { 6572 void *p = rtwsta; 6573 6574 return container_of(p, struct ieee80211_sta, drv_priv); 6575 } 6576 6577 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6578 { 6579 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6580 } 6581 6582 static inline 6583 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6584 { 6585 return rtwsta_to_sta(rtwsta_link->rtwsta); 6586 } 6587 6588 static inline 6589 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6590 { 6591 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6592 } 6593 6594 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6595 { 6596 return (struct rtw89_sta *)sta->drv_priv; 6597 } 6598 6599 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6600 { 6601 return sta ? sta_to_rtwsta(sta) : NULL; 6602 } 6603 6604 static inline struct ieee80211_bss_conf * 6605 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6606 { 6607 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6608 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6609 struct rtw89_link_conf_container *snap; 6610 struct ieee80211_bss_conf *bss_conf; 6611 6612 snap = rcu_dereference(rtwvif->snap_link_confs); 6613 if (snap) { 6614 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6615 goto out; 6616 } 6617 6618 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6619 6620 out: 6621 if (unlikely(!bss_conf)) { 6622 *nolink = true; 6623 return &vif->bss_conf; 6624 } 6625 6626 *nolink = false; 6627 return bss_conf; 6628 } 6629 6630 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6631 ({ \ 6632 typeof(rtwvif_link) p = rtwvif_link; \ 6633 struct ieee80211_bss_conf *bss_conf; \ 6634 bool nolink; \ 6635 \ 6636 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6637 if (unlikely(nolink) && (assert)) \ 6638 rtw89_err(p->rtwvif->rtwdev, \ 6639 "%s: cannot find exact bss_conf for link_id %u\n",\ 6640 __func__, p->link_id); \ 6641 bss_conf; \ 6642 }) 6643 6644 static inline struct ieee80211_link_sta * 6645 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6646 { 6647 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6648 struct ieee80211_link_sta *link_sta; 6649 6650 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6651 if (unlikely(!link_sta)) { 6652 *nolink = true; 6653 return &sta->deflink; 6654 } 6655 6656 *nolink = false; 6657 return link_sta; 6658 } 6659 6660 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6661 ({ \ 6662 typeof(rtwsta_link) p = rtwsta_link; \ 6663 struct ieee80211_link_sta *link_sta; \ 6664 bool nolink; \ 6665 \ 6666 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6667 if (unlikely(nolink) && (assert)) \ 6668 rtw89_err(p->rtwsta->rtwdev, \ 6669 "%s: cannot find exact link_sta for link_id %u\n",\ 6670 __func__, p->link_id); \ 6671 link_sta; \ 6672 }) 6673 6674 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6675 { 6676 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6677 return RATE_INFO_BW_160; 6678 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6679 return RATE_INFO_BW_80; 6680 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6681 return RATE_INFO_BW_40; 6682 else 6683 return RATE_INFO_BW_20; 6684 } 6685 6686 static inline 6687 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6688 { 6689 switch (hw_band) { 6690 default: 6691 case RTW89_BAND_2G: 6692 return NL80211_BAND_2GHZ; 6693 case RTW89_BAND_5G: 6694 return NL80211_BAND_5GHZ; 6695 case RTW89_BAND_6G: 6696 return NL80211_BAND_6GHZ; 6697 } 6698 } 6699 6700 static inline 6701 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6702 { 6703 switch (nl_band) { 6704 default: 6705 case NL80211_BAND_2GHZ: 6706 return RTW89_BAND_2G; 6707 case NL80211_BAND_5GHZ: 6708 return RTW89_BAND_5G; 6709 case NL80211_BAND_6GHZ: 6710 return RTW89_BAND_6G; 6711 } 6712 } 6713 6714 static inline 6715 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6716 { 6717 switch (width) { 6718 default: 6719 WARN(1, "Not support bandwidth %d\n", width); 6720 fallthrough; 6721 case NL80211_CHAN_WIDTH_20_NOHT: 6722 case NL80211_CHAN_WIDTH_20: 6723 return RTW89_CHANNEL_WIDTH_20; 6724 case NL80211_CHAN_WIDTH_40: 6725 return RTW89_CHANNEL_WIDTH_40; 6726 case NL80211_CHAN_WIDTH_80: 6727 return RTW89_CHANNEL_WIDTH_80; 6728 case NL80211_CHAN_WIDTH_160: 6729 return RTW89_CHANNEL_WIDTH_160; 6730 } 6731 } 6732 6733 static inline 6734 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6735 { 6736 switch (rua) { 6737 default: 6738 WARN(1, "Invalid RU allocation: %d\n", rua); 6739 fallthrough; 6740 case 0 ... 36: 6741 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6742 case 37 ... 52: 6743 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6744 case 53 ... 60: 6745 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6746 case 61 ... 64: 6747 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6748 case 65 ... 66: 6749 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6750 case 67: 6751 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6752 case 68: 6753 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6754 } 6755 } 6756 6757 static inline 6758 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6759 struct rtw89_sta_link *rtwsta_link) 6760 { 6761 if (rtwsta_link) { 6762 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6763 6764 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6765 return &rtwsta_link->addr_cam; 6766 } 6767 return &rtwvif_link->addr_cam; 6768 } 6769 6770 static inline 6771 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6772 struct rtw89_sta_link *rtwsta_link) 6773 { 6774 if (rtwsta_link) { 6775 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6776 6777 if (sta->tdls) 6778 return &rtwsta_link->bssid_cam; 6779 } 6780 return &rtwvif_link->bssid_cam; 6781 } 6782 6783 static inline 6784 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6785 struct rtw89_channel_help_params *p, 6786 const struct rtw89_chan *chan, 6787 enum rtw89_mac_idx mac_idx, 6788 enum rtw89_phy_idx phy_idx) 6789 { 6790 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6791 mac_idx, phy_idx); 6792 } 6793 6794 static inline 6795 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6796 struct rtw89_channel_help_params *p, 6797 const struct rtw89_chan *chan, 6798 enum rtw89_mac_idx mac_idx, 6799 enum rtw89_phy_idx phy_idx) 6800 { 6801 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6802 mac_idx, phy_idx); 6803 } 6804 6805 static inline 6806 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6807 enum rtw89_chanctx_idx idx) 6808 { 6809 struct rtw89_hal *hal = &rtwdev->hal; 6810 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6811 6812 if (roc_idx == idx) 6813 return &hal->roc_chandef; 6814 6815 return &hal->chanctx[idx].chandef; 6816 } 6817 6818 static inline 6819 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6820 enum rtw89_chanctx_idx idx) 6821 { 6822 struct rtw89_hal *hal = &rtwdev->hal; 6823 6824 return &hal->chanctx[idx].chan; 6825 } 6826 6827 static inline 6828 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6829 enum rtw89_chanctx_idx idx) 6830 { 6831 struct rtw89_hal *hal = &rtwdev->hal; 6832 6833 return &hal->chanctx[idx].rcd; 6834 } 6835 6836 static inline 6837 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6838 { 6839 const struct rtw89_chanctx *chanctx = 6840 container_of_const(chan, struct rtw89_chanctx, chan); 6841 6842 return &chanctx->rcd; 6843 } 6844 6845 static inline 6846 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6847 { 6848 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6849 6850 if (rtwvif_link) 6851 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6852 else 6853 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6854 } 6855 6856 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6857 { 6858 const struct rtw89_chip_info *chip = rtwdev->chip; 6859 6860 if (chip->ops->fem_setup) 6861 chip->ops->fem_setup(rtwdev); 6862 } 6863 6864 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6865 { 6866 const struct rtw89_chip_info *chip = rtwdev->chip; 6867 6868 if (chip->ops->rfe_gpio) 6869 chip->ops->rfe_gpio(rtwdev); 6870 } 6871 6872 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6873 { 6874 const struct rtw89_chip_info *chip = rtwdev->chip; 6875 6876 if (chip->ops->rfk_hw_init) 6877 chip->ops->rfk_hw_init(rtwdev); 6878 } 6879 6880 static inline 6881 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6882 { 6883 const struct rtw89_chip_info *chip = rtwdev->chip; 6884 6885 if (chip->ops->bb_preinit) 6886 chip->ops->bb_preinit(rtwdev, phy_idx); 6887 } 6888 6889 static inline 6890 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6891 { 6892 const struct rtw89_chip_info *chip = rtwdev->chip; 6893 6894 if (!chip->ops->bb_postinit) 6895 return; 6896 6897 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6898 6899 if (rtwdev->dbcc_en) 6900 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6901 } 6902 6903 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6904 { 6905 const struct rtw89_chip_info *chip = rtwdev->chip; 6906 6907 if (chip->ops->bb_sethw) 6908 chip->ops->bb_sethw(rtwdev); 6909 } 6910 6911 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6912 { 6913 const struct rtw89_chip_info *chip = rtwdev->chip; 6914 6915 if (chip->ops->rfk_init) 6916 chip->ops->rfk_init(rtwdev); 6917 } 6918 6919 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6920 { 6921 const struct rtw89_chip_info *chip = rtwdev->chip; 6922 6923 if (chip->ops->rfk_init_late) 6924 chip->ops->rfk_init_late(rtwdev); 6925 } 6926 6927 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6928 struct rtw89_vif_link *rtwvif_link) 6929 { 6930 const struct rtw89_chip_info *chip = rtwdev->chip; 6931 6932 if (chip->ops->rfk_channel) 6933 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6934 } 6935 6936 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6937 enum rtw89_phy_idx phy_idx, 6938 const struct rtw89_chan *chan) 6939 { 6940 const struct rtw89_chip_info *chip = rtwdev->chip; 6941 6942 if (chip->ops->rfk_band_changed) 6943 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6944 } 6945 6946 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6947 struct rtw89_vif_link *rtwvif_link, bool start) 6948 { 6949 const struct rtw89_chip_info *chip = rtwdev->chip; 6950 6951 if (chip->ops->rfk_scan) 6952 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6953 } 6954 6955 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6956 { 6957 const struct rtw89_chip_info *chip = rtwdev->chip; 6958 6959 if (chip->ops->rfk_track) 6960 chip->ops->rfk_track(rtwdev); 6961 } 6962 6963 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6964 { 6965 const struct rtw89_chip_info *chip = rtwdev->chip; 6966 6967 if (!chip->ops->set_txpwr_ctrl) 6968 return; 6969 6970 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6971 if (rtwdev->dbcc_en) 6972 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6973 } 6974 6975 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6976 { 6977 const struct rtw89_chip_info *chip = rtwdev->chip; 6978 6979 if (chip->ops->power_trim) 6980 chip->ops->power_trim(rtwdev); 6981 } 6982 6983 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6984 enum rtw89_phy_idx phy_idx) 6985 { 6986 const struct rtw89_chip_info *chip = rtwdev->chip; 6987 6988 if (chip->ops->init_txpwr_unit) 6989 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6990 } 6991 6992 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6993 { 6994 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6995 if (rtwdev->dbcc_en) 6996 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6997 } 6998 6999 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 7000 enum rtw89_rf_path rf_path) 7001 { 7002 const struct rtw89_chip_info *chip = rtwdev->chip; 7003 7004 if (!chip->ops->get_thermal) 7005 return 0x10; 7006 7007 return chip->ops->get_thermal(rtwdev, rf_path); 7008 } 7009 7010 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev, 7011 const struct rtw89_chan *chan) 7012 { 7013 const struct rtw89_chip_info *chip = rtwdev->chip; 7014 7015 if (!chip->ops->chan_to_rf18_val) 7016 return 0; 7017 7018 return chip->ops->chan_to_rf18_val(rtwdev, chan); 7019 } 7020 7021 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 7022 struct rtw89_rx_phy_ppdu *phy_ppdu, 7023 struct ieee80211_rx_status *status) 7024 { 7025 const struct rtw89_chip_info *chip = rtwdev->chip; 7026 7027 if (chip->ops->query_ppdu) 7028 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 7029 } 7030 7031 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 7032 struct rtw89_rx_phy_ppdu *phy_ppdu) 7033 { 7034 const struct rtw89_chip_info *chip = rtwdev->chip; 7035 7036 if (chip->ops->convert_rpl_to_rssi) 7037 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 7038 } 7039 7040 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 7041 struct rtw89_rx_desc_info *desc_info, 7042 struct ieee80211_rx_status *rx_status) 7043 { 7044 const struct rtw89_chip_info *chip = rtwdev->chip; 7045 7046 if (chip->ops->phy_rpt_to_rssi) 7047 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 7048 } 7049 7050 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 7051 enum rtw89_phy_idx phy_idx) 7052 { 7053 const struct rtw89_chip_info *chip = rtwdev->chip; 7054 7055 if (chip->ops->ctrl_nbtg_bt_tx) 7056 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 7057 } 7058 7059 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 7060 { 7061 const struct rtw89_chip_info *chip = rtwdev->chip; 7062 7063 if (chip->ops->cfg_txrx_path) 7064 chip->ops->cfg_txrx_path(rtwdev); 7065 } 7066 7067 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 7068 enum rtw89_phy_idx phy_idx) 7069 { 7070 const struct rtw89_chip_info *chip = rtwdev->chip; 7071 7072 if (chip->ops->digital_pwr_comp) 7073 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 7074 } 7075 7076 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 7077 const struct rtw89_txpwr_table *tbl) 7078 { 7079 tbl->load(rtwdev, tbl); 7080 } 7081 7082 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 7083 { 7084 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 7085 const struct rtw89_regd *regd = regulatory->regd; 7086 u8 txpwr_regd = regd->txpwr_regd[band]; 7087 7088 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK) 7089 return RTW89_ETSI; 7090 7091 return txpwr_regd; 7092 } 7093 7094 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 7095 enum rtw89_phy_idx phy_idx) 7096 { 7097 const struct rtw89_chip_info *chip = rtwdev->chip; 7098 7099 if (chip->ops->ctrl_btg_bt_rx) 7100 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 7101 } 7102 7103 static inline 7104 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 7105 struct rtw89_rx_desc_info *desc_info, 7106 u8 *data, u32 data_offset) 7107 { 7108 const struct rtw89_chip_info *chip = rtwdev->chip; 7109 7110 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 7111 } 7112 7113 static inline 7114 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 7115 struct rtw89_tx_desc_info *desc_info, 7116 void *txdesc) 7117 { 7118 const struct rtw89_chip_info *chip = rtwdev->chip; 7119 7120 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 7121 } 7122 7123 static inline 7124 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 7125 struct rtw89_tx_desc_info *desc_info, 7126 void *txdesc) 7127 { 7128 const struct rtw89_chip_info *chip = rtwdev->chip; 7129 7130 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 7131 } 7132 7133 static inline 7134 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 7135 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 7136 { 7137 const struct rtw89_chip_info *chip = rtwdev->chip; 7138 7139 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 7140 } 7141 7142 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 7143 { 7144 const struct rtw89_chip_info *chip = rtwdev->chip; 7145 7146 chip->ops->cfg_ctrl_path(rtwdev, wl); 7147 } 7148 7149 static inline 7150 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 7151 u32 *tx_en, enum rtw89_sch_tx_sel sel) 7152 { 7153 const struct rtw89_chip_info *chip = rtwdev->chip; 7154 7155 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 7156 } 7157 7158 static inline 7159 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 7160 { 7161 const struct rtw89_chip_info *chip = rtwdev->chip; 7162 7163 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 7164 } 7165 7166 static inline 7167 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 7168 struct rtw89_vif_link *rtwvif_link, 7169 struct rtw89_sta_link *rtwsta_link) 7170 { 7171 const struct rtw89_chip_info *chip = rtwdev->chip; 7172 7173 if (!chip->ops->h2c_dctl_sec_cam) 7174 return 0; 7175 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 7176 } 7177 7178 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 7179 { 7180 __le16 fc = hdr->frame_control; 7181 7182 if (ieee80211_has_tods(fc)) 7183 return hdr->addr1; 7184 else if (ieee80211_has_fromds(fc)) 7185 return hdr->addr2; 7186 else 7187 return hdr->addr3; 7188 } 7189 7190 static inline 7191 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 7192 { 7193 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 7194 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 7195 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 7196 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 7197 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 7198 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 7199 return true; 7200 return false; 7201 } 7202 7203 static inline 7204 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 7205 { 7206 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 7207 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 7208 return true; 7209 7210 return false; 7211 } 7212 7213 static inline 7214 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 7215 { 7216 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 7217 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 7218 return true; 7219 7220 return false; 7221 } 7222 7223 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 7224 enum rtw89_fw_type type) 7225 { 7226 struct rtw89_fw_info *fw_info = &rtwdev->fw; 7227 7228 switch (type) { 7229 case RTW89_FW_WOWLAN: 7230 return &fw_info->wowlan; 7231 case RTW89_FW_LOGFMT: 7232 return &fw_info->log.suit; 7233 case RTW89_FW_BBMCU0: 7234 return &fw_info->bbmcu0; 7235 case RTW89_FW_BBMCU1: 7236 return &fw_info->bbmcu1; 7237 default: 7238 break; 7239 } 7240 7241 return &fw_info->normal; 7242 } 7243 7244 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 7245 unsigned int length) 7246 { 7247 struct sk_buff *skb; 7248 7249 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 7250 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 7251 if (!skb) 7252 return NULL; 7253 7254 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 7255 return skb; 7256 } 7257 7258 return dev_alloc_skb(length); 7259 } 7260 7261 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7262 struct rtw89_tx_skb_data *skb_data, 7263 bool tx_done) 7264 { 7265 struct rtw89_tx_wait_info *wait; 7266 7267 rcu_read_lock(); 7268 7269 wait = rcu_dereference(skb_data->wait); 7270 if (!wait) 7271 goto out; 7272 7273 wait->tx_done = tx_done; 7274 complete(&wait->completion); 7275 7276 out: 7277 rcu_read_unlock(); 7278 } 7279 7280 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 7281 { 7282 switch (rtwdev->mlo_dbcc_mode) { 7283 case MLO_1_PLUS_1_1RF: 7284 case MLO_1_PLUS_1_2RF: 7285 case DBCC_LEGACY: 7286 return true; 7287 default: 7288 return false; 7289 } 7290 } 7291 7292 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 7293 { 7294 if (!rtwdev->dbcc_en) 7295 return BIT(RTW89_PHY_0); 7296 7297 switch (rtwdev->mlo_dbcc_mode) { 7298 case MLO_0_PLUS_2_1RF: 7299 case MLO_0_PLUS_2_2RF: 7300 return BIT(RTW89_PHY_1); 7301 case MLO_1_PLUS_1_1RF: 7302 case MLO_1_PLUS_1_2RF: 7303 case MLO_2_PLUS_2_2RF: 7304 case DBCC_LEGACY: 7305 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 7306 case MLO_2_PLUS_0_1RF: 7307 case MLO_2_PLUS_0_2RF: 7308 default: 7309 return BIT(RTW89_PHY_0); 7310 } 7311 } 7312 7313 #define rtw89_for_each_active_bb(rtwdev, bb) \ 7314 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 7315 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 7316 if (__active_bb_bitmap & BIT(__phy_idx) && \ 7317 (bb = &rtwdev->bbs[__phy_idx])) 7318 7319 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 7320 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 7321 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 7322 if ((bb = &rtwdev->bbs[__phy_idx])) 7323 7324 static inline 7325 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 7326 enum rtw89_phy_idx phy_idx) 7327 { 7328 if (phy_idx >= RTW89_PHY_NUM) 7329 return &rtwdev->bbs[RTW89_PHY_0]; 7330 7331 return &rtwdev->bbs[phy_idx]; 7332 } 7333 7334 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7335 { 7336 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7337 7338 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7339 return true; 7340 7341 return false; 7342 } 7343 7344 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval) 7345 { 7346 switch (interval) { 7347 default: 7348 case RTW89_TFC_INTERVAL_2SEC: 7349 return bytes >> 18; /* bytes/2s --> Mbps */; 7350 case RTW89_TFC_INTERVAL_100MS: 7351 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */ 7352 } 7353 } 7354 7355 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7356 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7357 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7358 struct sk_buff *skb, bool fwdl); 7359 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7360 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7361 int qsel, unsigned int timeout); 7362 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7363 struct rtw89_tx_desc_info *desc_info, 7364 void *txdesc); 7365 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7366 struct rtw89_tx_desc_info *desc_info, 7367 void *txdesc); 7368 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7369 struct rtw89_tx_desc_info *desc_info, 7370 void *txdesc); 7371 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7372 struct rtw89_tx_desc_info *desc_info, 7373 void *txdesc); 7374 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7375 struct rtw89_tx_desc_info *desc_info, 7376 void *txdesc); 7377 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7378 struct rtw89_rx_desc_info *desc_info, 7379 struct sk_buff *skb); 7380 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7381 struct rtw89_rx_desc_info *desc_info, 7382 u8 *data, u32 data_offset); 7383 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7384 struct rtw89_rx_desc_info *desc_info, 7385 u8 *data, u32 data_offset); 7386 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7387 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7388 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7389 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7390 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7391 struct rtw89_vif_link *rtwvif_link, 7392 struct rtw89_sta_link *rtwsta_link); 7393 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7394 struct rtw89_vif_link *rtwvif_link, 7395 struct rtw89_sta_link *rtwsta_link); 7396 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7397 struct rtw89_vif_link *rtwvif_link, 7398 struct rtw89_sta_link *rtwsta_link); 7399 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7400 struct rtw89_vif_link *rtwvif_link, 7401 struct rtw89_sta_link *rtwsta_link); 7402 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7403 struct rtw89_vif_link *rtwvif_link, 7404 struct rtw89_sta_link *rtwsta_link); 7405 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7406 struct ieee80211_sta *sta, 7407 struct cfg80211_tid_config *tid_config); 7408 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7409 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7410 int rtw89_core_init(struct rtw89_dev *rtwdev); 7411 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7412 int rtw89_core_register(struct rtw89_dev *rtwdev); 7413 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7414 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7415 u32 bus_data_size, 7416 const struct rtw89_chip_info *chip, 7417 const struct rtw89_chip_variant *variant); 7418 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7419 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7420 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7421 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7422 u8 mac_id, u8 port); 7423 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7424 struct rtw89_sta *rtwsta, u8 mac_id); 7425 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7426 unsigned int link_id); 7427 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7428 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7429 unsigned int link_id); 7430 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7431 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7432 const struct rtw89_6ghz_span * 7433 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7434 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7435 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7436 struct rtw89_chan *chan); 7437 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7438 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7439 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7440 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7441 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7442 struct rtw89_sta_link *rtwsta_link, u8 tid, 7443 u8 *cam_idx); 7444 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7445 struct rtw89_sta_link *rtwsta_link, u8 tid, 7446 u8 *cam_idx); 7447 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7448 struct ieee80211_sta *sta); 7449 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7450 struct ieee80211_sta *sta); 7451 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7452 struct ieee80211_sta *sta); 7453 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7454 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7455 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7456 struct rtw89_vif_link *rtwvif_link); 7457 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 7458 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7459 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7460 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 7461 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7462 struct rtw89_traffic_stats *stats); 7463 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 7464 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7465 const struct rtw89_completion_data *data); 7466 int rtw89_core_start(struct rtw89_dev *rtwdev); 7467 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7468 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7469 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7470 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7471 bool qos, bool ps, int timeout); 7472 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 7473 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7474 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7475 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7476 const u8 *mac_addr, bool hw_scan); 7477 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7478 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7479 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7480 bool active); 7481 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7482 struct rtw89_vif_link *rtwvif_link, 7483 struct ieee80211_bss_conf *bss_conf); 7484 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7485 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7486 unsigned int link_id); 7487 7488 #endif 7489