xref: /linux/drivers/net/wireless/realtek/rtw89/core.h (revision 41fb0cf1bced59c1fe178cf6cc9f716b5da9e40e) 
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7 
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/firmware.h>
11 #include <linux/iopoll.h>
12 #include <linux/workqueue.h>
13 #include <net/mac80211.h>
14 
15 struct rtw89_dev;
16 
17 extern const struct ieee80211_ops rtw89_ops;
18 extern const struct rtw89_chip_info rtw8852a_chip_info;
19 
20 #define MASKBYTE0 0xff
21 #define MASKBYTE1 0xff00
22 #define MASKBYTE2 0xff0000
23 #define MASKBYTE3 0xff000000
24 #define MASKBYTE4 0xff00000000ULL
25 #define MASKHWORD 0xffff0000
26 #define MASKLWORD 0x0000ffff
27 #define MASKDWORD 0xffffffff
28 #define RFREG_MASK 0xfffff
29 #define INV_RF_DATA 0xffffffff
30 
31 #define RTW89_TRACK_WORK_PERIOD	round_jiffies_relative(HZ * 2)
32 #define CFO_TRACK_MAX_USER 64
33 #define MAX_RSSI 110
34 #define RSSI_FACTOR 1
35 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
36 #define RTW89_MAX_HW_PORT_NUM 5
37 
38 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
39 #define RTW89_HTC_VARIANT_HE 3
40 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
41 #define RTW89_HTC_VARIANT_HE_CID_OM 1
42 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
43 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
44 
45 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
46 enum htc_om_channel_width {
47 	HTC_OM_CHANNEL_WIDTH_20 = 0,
48 	HTC_OM_CHANNEL_WIDTH_40 = 1,
49 	HTC_OM_CHANNEL_WIDTH_80 = 2,
50 	HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
51 };
52 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
53 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
54 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
55 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
56 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
57 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
58 
59 enum rtw89_subband {
60 	RTW89_CH_2G = 0,
61 	RTW89_CH_5G_BAND_1 = 1,
62 	/* RTW89_CH_5G_BAND_2 = 2, unused */
63 	RTW89_CH_5G_BAND_3 = 3,
64 	RTW89_CH_5G_BAND_4 = 4,
65 
66 	RTW89_SUBBAND_NR,
67 };
68 
69 enum rtw89_hci_type {
70 	RTW89_HCI_TYPE_PCIE,
71 	RTW89_HCI_TYPE_USB,
72 	RTW89_HCI_TYPE_SDIO,
73 };
74 
75 enum rtw89_core_chip_id {
76 	RTL8852A,
77 	RTL8852B,
78 	RTL8852C,
79 };
80 
81 enum rtw89_cv {
82 	CHIP_CAV,
83 	CHIP_CBV,
84 	CHIP_CCV,
85 	CHIP_CDV,
86 	CHIP_CEV,
87 	CHIP_CFV,
88 	CHIP_CV_MAX,
89 	CHIP_CV_INVALID = CHIP_CV_MAX,
90 };
91 
92 enum rtw89_core_tx_type {
93 	RTW89_CORE_TX_TYPE_DATA,
94 	RTW89_CORE_TX_TYPE_MGMT,
95 	RTW89_CORE_TX_TYPE_FWCMD,
96 };
97 
98 enum rtw89_core_rx_type {
99 	RTW89_CORE_RX_TYPE_WIFI		= 0,
100 	RTW89_CORE_RX_TYPE_PPDU_STAT	= 1,
101 	RTW89_CORE_RX_TYPE_CHAN_INFO	= 2,
102 	RTW89_CORE_RX_TYPE_BB_SCOPE	= 3,
103 	RTW89_CORE_RX_TYPE_F2P_TXCMD	= 4,
104 	RTW89_CORE_RX_TYPE_SS2FW	= 5,
105 	RTW89_CORE_RX_TYPE_TX_REPORT	= 6,
106 	RTW89_CORE_RX_TYPE_TX_REL_HOST	= 7,
107 	RTW89_CORE_RX_TYPE_DFS_REPORT	= 8,
108 	RTW89_CORE_RX_TYPE_TX_REL_CPU	= 9,
109 	RTW89_CORE_RX_TYPE_C2H		= 10,
110 	RTW89_CORE_RX_TYPE_CSI		= 11,
111 	RTW89_CORE_RX_TYPE_CQI		= 12,
112 };
113 
114 enum rtw89_txq_flags {
115 	RTW89_TXQ_F_AMPDU		= 0,
116 	RTW89_TXQ_F_BLOCK_BA		= 1,
117 };
118 
119 enum rtw89_net_type {
120 	RTW89_NET_TYPE_NO_LINK		= 0,
121 	RTW89_NET_TYPE_AD_HOC		= 1,
122 	RTW89_NET_TYPE_INFRA		= 2,
123 	RTW89_NET_TYPE_AP_MODE		= 3,
124 };
125 
126 enum rtw89_wifi_role {
127 	RTW89_WIFI_ROLE_NONE,
128 	RTW89_WIFI_ROLE_STATION,
129 	RTW89_WIFI_ROLE_AP,
130 	RTW89_WIFI_ROLE_AP_VLAN,
131 	RTW89_WIFI_ROLE_ADHOC,
132 	RTW89_WIFI_ROLE_ADHOC_MASTER,
133 	RTW89_WIFI_ROLE_MESH_POINT,
134 	RTW89_WIFI_ROLE_MONITOR,
135 	RTW89_WIFI_ROLE_P2P_DEVICE,
136 	RTW89_WIFI_ROLE_P2P_CLIENT,
137 	RTW89_WIFI_ROLE_P2P_GO,
138 	RTW89_WIFI_ROLE_NAN,
139 	RTW89_WIFI_ROLE_MLME_MAX
140 };
141 
142 enum rtw89_upd_mode {
143 	RTW89_VIF_CREATE,
144 	RTW89_VIF_REMOVE,
145 	RTW89_VIF_TYPE_CHANGE,
146 	RTW89_VIF_INFO_CHANGE,
147 	RTW89_VIF_CON_DISCONN
148 };
149 
150 enum rtw89_self_role {
151 	RTW89_SELF_ROLE_CLIENT,
152 	RTW89_SELF_ROLE_AP,
153 	RTW89_SELF_ROLE_AP_CLIENT
154 };
155 
156 enum rtw89_msk_sO_el {
157 	RTW89_NO_MSK,
158 	RTW89_SMA,
159 	RTW89_TMA,
160 	RTW89_BSSID
161 };
162 
163 enum rtw89_sch_tx_sel {
164 	RTW89_SCH_TX_SEL_ALL,
165 	RTW89_SCH_TX_SEL_HIQ,
166 	RTW89_SCH_TX_SEL_MG0,
167 	RTW89_SCH_TX_SEL_MACID,
168 };
169 
170 /* RTW89_ADDR_CAM_SEC_NONE	: not enabled
171  * RTW89_ADDR_CAM_SEC_ALL_UNI	: 0 - 6 unicast
172  * RTW89_ADDR_CAM_SEC_NORMAL	: 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
173  * RTW89_ADDR_CAM_SEC_4GROUP	: 0 - 1 unicast, 2 - 5 group, 6 BIP
174  */
175 enum rtw89_add_cam_sec_mode {
176 	RTW89_ADDR_CAM_SEC_NONE		= 0,
177 	RTW89_ADDR_CAM_SEC_ALL_UNI	= 1,
178 	RTW89_ADDR_CAM_SEC_NORMAL	= 2,
179 	RTW89_ADDR_CAM_SEC_4GROUP	= 3,
180 };
181 
182 enum rtw89_sec_key_type {
183 	RTW89_SEC_KEY_TYPE_NONE		= 0,
184 	RTW89_SEC_KEY_TYPE_WEP40	= 1,
185 	RTW89_SEC_KEY_TYPE_WEP104	= 2,
186 	RTW89_SEC_KEY_TYPE_TKIP		= 3,
187 	RTW89_SEC_KEY_TYPE_WAPI		= 4,
188 	RTW89_SEC_KEY_TYPE_GCMSMS4	= 5,
189 	RTW89_SEC_KEY_TYPE_CCMP128	= 6,
190 	RTW89_SEC_KEY_TYPE_CCMP256	= 7,
191 	RTW89_SEC_KEY_TYPE_GCMP128	= 8,
192 	RTW89_SEC_KEY_TYPE_GCMP256	= 9,
193 	RTW89_SEC_KEY_TYPE_BIP_CCMP128	= 10,
194 };
195 
196 enum rtw89_port {
197 	RTW89_PORT_0 = 0,
198 	RTW89_PORT_1 = 1,
199 	RTW89_PORT_2 = 2,
200 	RTW89_PORT_3 = 3,
201 	RTW89_PORT_4 = 4,
202 	RTW89_PORT_NUM
203 };
204 
205 enum rtw89_band {
206 	RTW89_BAND_2G = 0,
207 	RTW89_BAND_5G = 1,
208 	RTW89_BAND_MAX,
209 };
210 
211 enum rtw89_hw_rate {
212 	RTW89_HW_RATE_CCK1	= 0x0,
213 	RTW89_HW_RATE_CCK2	= 0x1,
214 	RTW89_HW_RATE_CCK5_5	= 0x2,
215 	RTW89_HW_RATE_CCK11	= 0x3,
216 	RTW89_HW_RATE_OFDM6	= 0x4,
217 	RTW89_HW_RATE_OFDM9	= 0x5,
218 	RTW89_HW_RATE_OFDM12	= 0x6,
219 	RTW89_HW_RATE_OFDM18	= 0x7,
220 	RTW89_HW_RATE_OFDM24	= 0x8,
221 	RTW89_HW_RATE_OFDM36	= 0x9,
222 	RTW89_HW_RATE_OFDM48	= 0xA,
223 	RTW89_HW_RATE_OFDM54	= 0xB,
224 	RTW89_HW_RATE_MCS0	= 0x80,
225 	RTW89_HW_RATE_MCS1	= 0x81,
226 	RTW89_HW_RATE_MCS2	= 0x82,
227 	RTW89_HW_RATE_MCS3	= 0x83,
228 	RTW89_HW_RATE_MCS4	= 0x84,
229 	RTW89_HW_RATE_MCS5	= 0x85,
230 	RTW89_HW_RATE_MCS6	= 0x86,
231 	RTW89_HW_RATE_MCS7	= 0x87,
232 	RTW89_HW_RATE_MCS8	= 0x88,
233 	RTW89_HW_RATE_MCS9	= 0x89,
234 	RTW89_HW_RATE_MCS10	= 0x8A,
235 	RTW89_HW_RATE_MCS11	= 0x8B,
236 	RTW89_HW_RATE_MCS12	= 0x8C,
237 	RTW89_HW_RATE_MCS13	= 0x8D,
238 	RTW89_HW_RATE_MCS14	= 0x8E,
239 	RTW89_HW_RATE_MCS15	= 0x8F,
240 	RTW89_HW_RATE_MCS16	= 0x90,
241 	RTW89_HW_RATE_MCS17	= 0x91,
242 	RTW89_HW_RATE_MCS18	= 0x92,
243 	RTW89_HW_RATE_MCS19	= 0x93,
244 	RTW89_HW_RATE_MCS20	= 0x94,
245 	RTW89_HW_RATE_MCS21	= 0x95,
246 	RTW89_HW_RATE_MCS22	= 0x96,
247 	RTW89_HW_RATE_MCS23	= 0x97,
248 	RTW89_HW_RATE_MCS24	= 0x98,
249 	RTW89_HW_RATE_MCS25	= 0x99,
250 	RTW89_HW_RATE_MCS26	= 0x9A,
251 	RTW89_HW_RATE_MCS27	= 0x9B,
252 	RTW89_HW_RATE_MCS28	= 0x9C,
253 	RTW89_HW_RATE_MCS29	= 0x9D,
254 	RTW89_HW_RATE_MCS30	= 0x9E,
255 	RTW89_HW_RATE_MCS31	= 0x9F,
256 	RTW89_HW_RATE_VHT_NSS1_MCS0	= 0x100,
257 	RTW89_HW_RATE_VHT_NSS1_MCS1	= 0x101,
258 	RTW89_HW_RATE_VHT_NSS1_MCS2	= 0x102,
259 	RTW89_HW_RATE_VHT_NSS1_MCS3	= 0x103,
260 	RTW89_HW_RATE_VHT_NSS1_MCS4	= 0x104,
261 	RTW89_HW_RATE_VHT_NSS1_MCS5	= 0x105,
262 	RTW89_HW_RATE_VHT_NSS1_MCS6	= 0x106,
263 	RTW89_HW_RATE_VHT_NSS1_MCS7	= 0x107,
264 	RTW89_HW_RATE_VHT_NSS1_MCS8	= 0x108,
265 	RTW89_HW_RATE_VHT_NSS1_MCS9	= 0x109,
266 	RTW89_HW_RATE_VHT_NSS2_MCS0	= 0x110,
267 	RTW89_HW_RATE_VHT_NSS2_MCS1	= 0x111,
268 	RTW89_HW_RATE_VHT_NSS2_MCS2	= 0x112,
269 	RTW89_HW_RATE_VHT_NSS2_MCS3	= 0x113,
270 	RTW89_HW_RATE_VHT_NSS2_MCS4	= 0x114,
271 	RTW89_HW_RATE_VHT_NSS2_MCS5	= 0x115,
272 	RTW89_HW_RATE_VHT_NSS2_MCS6	= 0x116,
273 	RTW89_HW_RATE_VHT_NSS2_MCS7	= 0x117,
274 	RTW89_HW_RATE_VHT_NSS2_MCS8	= 0x118,
275 	RTW89_HW_RATE_VHT_NSS2_MCS9	= 0x119,
276 	RTW89_HW_RATE_VHT_NSS3_MCS0	= 0x120,
277 	RTW89_HW_RATE_VHT_NSS3_MCS1	= 0x121,
278 	RTW89_HW_RATE_VHT_NSS3_MCS2	= 0x122,
279 	RTW89_HW_RATE_VHT_NSS3_MCS3	= 0x123,
280 	RTW89_HW_RATE_VHT_NSS3_MCS4	= 0x124,
281 	RTW89_HW_RATE_VHT_NSS3_MCS5	= 0x125,
282 	RTW89_HW_RATE_VHT_NSS3_MCS6	= 0x126,
283 	RTW89_HW_RATE_VHT_NSS3_MCS7	= 0x127,
284 	RTW89_HW_RATE_VHT_NSS3_MCS8	= 0x128,
285 	RTW89_HW_RATE_VHT_NSS3_MCS9	= 0x129,
286 	RTW89_HW_RATE_VHT_NSS4_MCS0	= 0x130,
287 	RTW89_HW_RATE_VHT_NSS4_MCS1	= 0x131,
288 	RTW89_HW_RATE_VHT_NSS4_MCS2	= 0x132,
289 	RTW89_HW_RATE_VHT_NSS4_MCS3	= 0x133,
290 	RTW89_HW_RATE_VHT_NSS4_MCS4	= 0x134,
291 	RTW89_HW_RATE_VHT_NSS4_MCS5	= 0x135,
292 	RTW89_HW_RATE_VHT_NSS4_MCS6	= 0x136,
293 	RTW89_HW_RATE_VHT_NSS4_MCS7	= 0x137,
294 	RTW89_HW_RATE_VHT_NSS4_MCS8	= 0x138,
295 	RTW89_HW_RATE_VHT_NSS4_MCS9	= 0x139,
296 	RTW89_HW_RATE_HE_NSS1_MCS0	= 0x180,
297 	RTW89_HW_RATE_HE_NSS1_MCS1	= 0x181,
298 	RTW89_HW_RATE_HE_NSS1_MCS2	= 0x182,
299 	RTW89_HW_RATE_HE_NSS1_MCS3	= 0x183,
300 	RTW89_HW_RATE_HE_NSS1_MCS4	= 0x184,
301 	RTW89_HW_RATE_HE_NSS1_MCS5	= 0x185,
302 	RTW89_HW_RATE_HE_NSS1_MCS6	= 0x186,
303 	RTW89_HW_RATE_HE_NSS1_MCS7	= 0x187,
304 	RTW89_HW_RATE_HE_NSS1_MCS8	= 0x188,
305 	RTW89_HW_RATE_HE_NSS1_MCS9	= 0x189,
306 	RTW89_HW_RATE_HE_NSS1_MCS10	= 0x18A,
307 	RTW89_HW_RATE_HE_NSS1_MCS11	= 0x18B,
308 	RTW89_HW_RATE_HE_NSS2_MCS0	= 0x190,
309 	RTW89_HW_RATE_HE_NSS2_MCS1	= 0x191,
310 	RTW89_HW_RATE_HE_NSS2_MCS2	= 0x192,
311 	RTW89_HW_RATE_HE_NSS2_MCS3	= 0x193,
312 	RTW89_HW_RATE_HE_NSS2_MCS4	= 0x194,
313 	RTW89_HW_RATE_HE_NSS2_MCS5	= 0x195,
314 	RTW89_HW_RATE_HE_NSS2_MCS6	= 0x196,
315 	RTW89_HW_RATE_HE_NSS2_MCS7	= 0x197,
316 	RTW89_HW_RATE_HE_NSS2_MCS8	= 0x198,
317 	RTW89_HW_RATE_HE_NSS2_MCS9	= 0x199,
318 	RTW89_HW_RATE_HE_NSS2_MCS10	= 0x19A,
319 	RTW89_HW_RATE_HE_NSS2_MCS11	= 0x19B,
320 	RTW89_HW_RATE_HE_NSS3_MCS0	= 0x1A0,
321 	RTW89_HW_RATE_HE_NSS3_MCS1	= 0x1A1,
322 	RTW89_HW_RATE_HE_NSS3_MCS2	= 0x1A2,
323 	RTW89_HW_RATE_HE_NSS3_MCS3	= 0x1A3,
324 	RTW89_HW_RATE_HE_NSS3_MCS4	= 0x1A4,
325 	RTW89_HW_RATE_HE_NSS3_MCS5	= 0x1A5,
326 	RTW89_HW_RATE_HE_NSS3_MCS6	= 0x1A6,
327 	RTW89_HW_RATE_HE_NSS3_MCS7	= 0x1A7,
328 	RTW89_HW_RATE_HE_NSS3_MCS8	= 0x1A8,
329 	RTW89_HW_RATE_HE_NSS3_MCS9	= 0x1A9,
330 	RTW89_HW_RATE_HE_NSS3_MCS10	= 0x1AA,
331 	RTW89_HW_RATE_HE_NSS3_MCS11	= 0x1AB,
332 	RTW89_HW_RATE_HE_NSS4_MCS0	= 0x1B0,
333 	RTW89_HW_RATE_HE_NSS4_MCS1	= 0x1B1,
334 	RTW89_HW_RATE_HE_NSS4_MCS2	= 0x1B2,
335 	RTW89_HW_RATE_HE_NSS4_MCS3	= 0x1B3,
336 	RTW89_HW_RATE_HE_NSS4_MCS4	= 0x1B4,
337 	RTW89_HW_RATE_HE_NSS4_MCS5	= 0x1B5,
338 	RTW89_HW_RATE_HE_NSS4_MCS6	= 0x1B6,
339 	RTW89_HW_RATE_HE_NSS4_MCS7	= 0x1B7,
340 	RTW89_HW_RATE_HE_NSS4_MCS8	= 0x1B8,
341 	RTW89_HW_RATE_HE_NSS4_MCS9	= 0x1B9,
342 	RTW89_HW_RATE_HE_NSS4_MCS10	= 0x1BA,
343 	RTW89_HW_RATE_HE_NSS4_MCS11	= 0x1BB,
344 	RTW89_HW_RATE_NR,
345 
346 	RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
347 	RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
348 };
349 
350 /* 2G channels,
351  * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
352  */
353 #define RTW89_2G_CH_NUM 14
354 
355 /* 5G channels,
356  * 36, 38, 40, 42, 44, 46, 48, 50,
357  * 52, 54, 56, 58, 60, 62, 64,
358  * 100, 102, 104, 106, 108, 110, 112, 114,
359  * 116, 118, 120, 122, 124, 126, 128, 130,
360  * 132, 134, 136, 138, 140, 142, 144,
361  * 149, 151, 153, 155, 157, 159, 161, 163,
362  * 165, 167, 169, 171, 173, 175, 177
363  */
364 #define RTW89_5G_CH_NUM 53
365 
366 enum rtw89_rate_section {
367 	RTW89_RS_CCK,
368 	RTW89_RS_OFDM,
369 	RTW89_RS_MCS, /* for HT/VHT/HE */
370 	RTW89_RS_HEDCM,
371 	RTW89_RS_OFFSET,
372 	RTW89_RS_MAX,
373 	RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
374 };
375 
376 enum rtw89_rate_max {
377 	RTW89_RATE_CCK_MAX	= 4,
378 	RTW89_RATE_OFDM_MAX	= 8,
379 	RTW89_RATE_MCS_MAX	= 12,
380 	RTW89_RATE_HEDCM_MAX	= 4, /* for HEDCM MCS0/1/3/4 */
381 	RTW89_RATE_OFFSET_MAX	= 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */
382 };
383 
384 enum rtw89_nss {
385 	RTW89_NSS_1		= 0,
386 	RTW89_NSS_2		= 1,
387 	/* HE DCM only support 1ss and 2ss */
388 	RTW89_NSS_HEDCM_MAX	= RTW89_NSS_2 + 1,
389 	RTW89_NSS_3		= 2,
390 	RTW89_NSS_4		= 3,
391 	RTW89_NSS_MAX,
392 };
393 
394 enum rtw89_ntx {
395 	RTW89_1TX	= 0,
396 	RTW89_2TX	= 1,
397 	RTW89_NTX_NUM,
398 };
399 
400 enum rtw89_beamforming_type {
401 	RTW89_NONBF	= 0,
402 	RTW89_BF	= 1,
403 	RTW89_BF_NUM,
404 };
405 
406 enum rtw89_regulation_type {
407 	RTW89_WW	= 0,
408 	RTW89_ETSI	= 1,
409 	RTW89_FCC	= 2,
410 	RTW89_MKK	= 3,
411 	RTW89_NA	= 4,
412 	RTW89_IC	= 5,
413 	RTW89_KCC	= 6,
414 	RTW89_ACMA	= 7,
415 	RTW89_NCC	= 8,
416 	RTW89_MEXICO	= 9,
417 	RTW89_CHILE	= 10,
418 	RTW89_UKRAINE	= 11,
419 	RTW89_CN	= 12,
420 	RTW89_QATAR	= 13,
421 	RTW89_REGD_NUM,
422 };
423 
424 extern const u8 rtw89_rs_idx_max[RTW89_RS_MAX];
425 extern const u8 rtw89_rs_nss_max[RTW89_RS_MAX];
426 
427 struct rtw89_txpwr_byrate {
428 	s8 cck[RTW89_RATE_CCK_MAX];
429 	s8 ofdm[RTW89_RATE_OFDM_MAX];
430 	s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX];
431 	s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX];
432 	s8 offset[RTW89_RATE_OFFSET_MAX];
433 };
434 
435 enum rtw89_bandwidth_section_num {
436 	RTW89_BW20_SEC_NUM = 8,
437 	RTW89_BW40_SEC_NUM = 4,
438 	RTW89_BW80_SEC_NUM = 2,
439 };
440 
441 struct rtw89_txpwr_limit {
442 	s8 cck_20m[RTW89_BF_NUM];
443 	s8 cck_40m[RTW89_BF_NUM];
444 	s8 ofdm[RTW89_BF_NUM];
445 	s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM];
446 	s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM];
447 	s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM];
448 	s8 mcs_160m[RTW89_BF_NUM];
449 	s8 mcs_40m_0p5[RTW89_BF_NUM];
450 	s8 mcs_40m_2p5[RTW89_BF_NUM];
451 };
452 
453 #define RTW89_RU_SEC_NUM 8
454 
455 struct rtw89_txpwr_limit_ru {
456 	s8 ru26[RTW89_RU_SEC_NUM];
457 	s8 ru52[RTW89_RU_SEC_NUM];
458 	s8 ru106[RTW89_RU_SEC_NUM];
459 };
460 
461 struct rtw89_rate_desc {
462 	enum rtw89_nss nss;
463 	enum rtw89_rate_section rs;
464 	u8 idx;
465 };
466 
467 #define PHY_STS_HDR_LEN 8
468 #define RF_PATH_MAX 4
469 #define RTW89_MAX_PPDU_CNT 8
470 struct rtw89_rx_phy_ppdu {
471 	u8 *buf;
472 	u32 len;
473 	u8 rssi_avg;
474 	s8 rssi[RF_PATH_MAX];
475 	u8 mac_id;
476 	bool to_self;
477 	bool valid;
478 };
479 
480 enum rtw89_mac_idx {
481 	RTW89_MAC_0 = 0,
482 	RTW89_MAC_1 = 1,
483 };
484 
485 enum rtw89_phy_idx {
486 	RTW89_PHY_0 = 0,
487 	RTW89_PHY_1 = 1,
488 	RTW89_PHY_MAX
489 };
490 
491 enum rtw89_rf_path {
492 	RF_PATH_A = 0,
493 	RF_PATH_B = 1,
494 	RF_PATH_C = 2,
495 	RF_PATH_D = 3,
496 	RF_PATH_AB,
497 	RF_PATH_AC,
498 	RF_PATH_AD,
499 	RF_PATH_BC,
500 	RF_PATH_BD,
501 	RF_PATH_CD,
502 	RF_PATH_ABC,
503 	RF_PATH_ABD,
504 	RF_PATH_ACD,
505 	RF_PATH_BCD,
506 	RF_PATH_ABCD,
507 };
508 
509 enum rtw89_rf_path_bit {
510 	RF_A	= BIT(0),
511 	RF_B	= BIT(1),
512 	RF_C	= BIT(2),
513 	RF_D	= BIT(3),
514 
515 	RF_AB	= (RF_A | RF_B),
516 	RF_AC	= (RF_A | RF_C),
517 	RF_AD	= (RF_A | RF_D),
518 	RF_BC	= (RF_B | RF_C),
519 	RF_BD	= (RF_B | RF_D),
520 	RF_CD	= (RF_C | RF_D),
521 
522 	RF_ABC	= (RF_A | RF_B | RF_C),
523 	RF_ABD	= (RF_A | RF_B | RF_D),
524 	RF_ACD	= (RF_A | RF_C | RF_D),
525 	RF_BCD	= (RF_B | RF_C | RF_D),
526 
527 	RF_ABCD	= (RF_A | RF_B | RF_C | RF_D),
528 };
529 
530 enum rtw89_bandwidth {
531 	RTW89_CHANNEL_WIDTH_20	= 0,
532 	RTW89_CHANNEL_WIDTH_40	= 1,
533 	RTW89_CHANNEL_WIDTH_80	= 2,
534 	RTW89_CHANNEL_WIDTH_160	= 3,
535 	RTW89_CHANNEL_WIDTH_80_80	= 4,
536 	RTW89_CHANNEL_WIDTH_5	= 5,
537 	RTW89_CHANNEL_WIDTH_10	= 6,
538 };
539 
540 enum rtw89_ps_mode {
541 	RTW89_PS_MODE_NONE	= 0,
542 	RTW89_PS_MODE_RFOFF	= 1,
543 	RTW89_PS_MODE_CLK_GATED	= 2,
544 	RTW89_PS_MODE_PWR_GATED	= 3,
545 };
546 
547 #define RTW89_MAX_CHANNEL_WIDTH RTW89_CHANNEL_WIDTH_80
548 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
549 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1)
550 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1)
551 
552 enum rtw89_ru_bandwidth {
553 	RTW89_RU26 = 0,
554 	RTW89_RU52 = 1,
555 	RTW89_RU106 = 2,
556 	RTW89_RU_NUM,
557 };
558 
559 enum rtw89_sc_offset {
560 	RTW89_SC_DONT_CARE	= 0,
561 	RTW89_SC_20_UPPER	= 1,
562 	RTW89_SC_20_LOWER	= 2,
563 	RTW89_SC_20_UPMOST	= 3,
564 	RTW89_SC_20_LOWEST	= 4,
565 	RTW89_SC_40_UPPER	= 9,
566 	RTW89_SC_40_LOWER	= 10,
567 };
568 
569 struct rtw89_channel_params {
570 	u8 center_chan;
571 	u8 primary_chan;
572 	u8 bandwidth;
573 	u8 pri_ch_idx;
574 	u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1];
575 };
576 
577 struct rtw89_channel_help_params {
578 	u16 tx_en;
579 };
580 
581 struct rtw89_port_reg {
582 	u32 port_cfg;
583 	u32 tbtt_prohib;
584 	u32 bcn_area;
585 	u32 bcn_early;
586 	u32 tbtt_early;
587 	u32 tbtt_agg;
588 	u32 bcn_space;
589 	u32 bcn_forcetx;
590 	u32 bcn_err_cnt;
591 	u32 bcn_err_flag;
592 	u32 dtim_ctrl;
593 	u32 tbtt_shift;
594 	u32 bcn_cnt_tmr;
595 	u32 tsftr_l;
596 	u32 tsftr_h;
597 };
598 
599 struct rtw89_txwd_body {
600 	__le32 dword0;
601 	__le32 dword1;
602 	__le32 dword2;
603 	__le32 dword3;
604 	__le32 dword4;
605 	__le32 dword5;
606 } __packed;
607 
608 struct rtw89_txwd_info {
609 	__le32 dword0;
610 	__le32 dword1;
611 	__le32 dword2;
612 	__le32 dword3;
613 	__le32 dword4;
614 	__le32 dword5;
615 } __packed;
616 
617 struct rtw89_rx_desc_info {
618 	u16 pkt_size;
619 	u8 pkt_type;
620 	u8 drv_info_size;
621 	u8 shift;
622 	u8 wl_hd_iv_len;
623 	bool long_rxdesc;
624 	bool bb_sel;
625 	bool mac_info_valid;
626 	u16 data_rate;
627 	u8 gi_ltf;
628 	u8 bw;
629 	u32 free_run_cnt;
630 	u8 user_id;
631 	bool sr_en;
632 	u8 ppdu_cnt;
633 	u8 ppdu_type;
634 	bool icv_err;
635 	bool crc32_err;
636 	bool hw_dec;
637 	bool sw_dec;
638 	bool addr1_match;
639 	u8 frag;
640 	u16 seq;
641 	u8 frame_type;
642 	u8 rx_pl_id;
643 	bool addr_cam_valid;
644 	u8 addr_cam_id;
645 	u8 sec_cam_id;
646 	u8 mac_id;
647 	u16 offset;
648 	bool ready;
649 };
650 
651 struct rtw89_rxdesc_short {
652 	__le32 dword0;
653 	__le32 dword1;
654 	__le32 dword2;
655 	__le32 dword3;
656 } __packed;
657 
658 struct rtw89_rxdesc_long {
659 	__le32 dword0;
660 	__le32 dword1;
661 	__le32 dword2;
662 	__le32 dword3;
663 	__le32 dword4;
664 	__le32 dword5;
665 	__le32 dword6;
666 	__le32 dword7;
667 } __packed;
668 
669 struct rtw89_tx_desc_info {
670 	u16 pkt_size;
671 	u8 wp_offset;
672 	u8 qsel;
673 	u8 ch_dma;
674 	u8 hdr_llc_len;
675 	bool is_bmc;
676 	bool en_wd_info;
677 	bool wd_page;
678 	bool use_rate;
679 	bool dis_data_fb;
680 	bool tid_indicate;
681 	bool agg_en;
682 	bool bk;
683 	u8 ampdu_density;
684 	u8 ampdu_num;
685 	bool sec_en;
686 	u8 sec_type;
687 	u8 sec_cam_idx;
688 	u16 data_rate;
689 	u16 data_retry_lowest_rate;
690 	bool fw_dl;
691 	u16 seq;
692 	bool a_ctrl_bsr;
693 };
694 
695 struct rtw89_core_tx_request {
696 	enum rtw89_core_tx_type tx_type;
697 
698 	struct sk_buff *skb;
699 	struct ieee80211_vif *vif;
700 	struct ieee80211_sta *sta;
701 	struct rtw89_tx_desc_info desc_info;
702 };
703 
704 struct rtw89_txq {
705 	struct list_head list;
706 	unsigned long flags;
707 	int wait_cnt;
708 };
709 
710 struct rtw89_mac_ax_gnt {
711 	u8 gnt_bt_sw_en;
712 	u8 gnt_bt;
713 	u8 gnt_wl_sw_en;
714 	u8 gnt_wl;
715 };
716 
717 #define RTW89_MAC_AX_COEX_GNT_NR 2
718 struct rtw89_mac_ax_coex_gnt {
719 	struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
720 };
721 
722 enum rtw89_btc_ncnt {
723 	BTC_NCNT_POWER_ON = 0x0,
724 	BTC_NCNT_POWER_OFF,
725 	BTC_NCNT_INIT_COEX,
726 	BTC_NCNT_SCAN_START,
727 	BTC_NCNT_SCAN_FINISH,
728 	BTC_NCNT_SPECIAL_PACKET,
729 	BTC_NCNT_SWITCH_BAND,
730 	BTC_NCNT_RFK_TIMEOUT,
731 	BTC_NCNT_SHOW_COEX_INFO,
732 	BTC_NCNT_ROLE_INFO,
733 	BTC_NCNT_CONTROL,
734 	BTC_NCNT_RADIO_STATE,
735 	BTC_NCNT_CUSTOMERIZE,
736 	BTC_NCNT_WL_RFK,
737 	BTC_NCNT_WL_STA,
738 	BTC_NCNT_FWINFO,
739 	BTC_NCNT_TIMER,
740 	BTC_NCNT_NUM
741 };
742 
743 enum rtw89_btc_btinfo {
744 	BTC_BTINFO_L0 = 0,
745 	BTC_BTINFO_L1,
746 	BTC_BTINFO_L2,
747 	BTC_BTINFO_L3,
748 	BTC_BTINFO_H0,
749 	BTC_BTINFO_H1,
750 	BTC_BTINFO_H2,
751 	BTC_BTINFO_H3,
752 	BTC_BTINFO_MAX
753 };
754 
755 enum rtw89_btc_dcnt {
756 	BTC_DCNT_RUN = 0x0,
757 	BTC_DCNT_CX_RUNINFO,
758 	BTC_DCNT_RPT,
759 	BTC_DCNT_RPT_FREEZE,
760 	BTC_DCNT_CYCLE,
761 	BTC_DCNT_CYCLE_FREEZE,
762 	BTC_DCNT_W1,
763 	BTC_DCNT_W1_FREEZE,
764 	BTC_DCNT_B1,
765 	BTC_DCNT_B1_FREEZE,
766 	BTC_DCNT_TDMA_NONSYNC,
767 	BTC_DCNT_SLOT_NONSYNC,
768 	BTC_DCNT_BTCNT_FREEZE,
769 	BTC_DCNT_WL_SLOT_DRIFT,
770 	BTC_DCNT_WL_STA_LAST,
771 	BTC_DCNT_NUM,
772 };
773 
774 enum rtw89_btc_wl_state_cnt {
775 	BTC_WCNT_SCANAP = 0x0,
776 	BTC_WCNT_DHCP,
777 	BTC_WCNT_EAPOL,
778 	BTC_WCNT_ARP,
779 	BTC_WCNT_SCBDUPDATE,
780 	BTC_WCNT_RFK_REQ,
781 	BTC_WCNT_RFK_GO,
782 	BTC_WCNT_RFK_REJECT,
783 	BTC_WCNT_RFK_TIMEOUT,
784 	BTC_WCNT_CH_UPDATE,
785 	BTC_WCNT_NUM
786 };
787 
788 enum rtw89_btc_bt_state_cnt {
789 	BTC_BCNT_RETRY = 0x0,
790 	BTC_BCNT_REINIT,
791 	BTC_BCNT_REENABLE,
792 	BTC_BCNT_SCBDREAD,
793 	BTC_BCNT_RELINK,
794 	BTC_BCNT_IGNOWL,
795 	BTC_BCNT_INQPAG,
796 	BTC_BCNT_INQ,
797 	BTC_BCNT_PAGE,
798 	BTC_BCNT_ROLESW,
799 	BTC_BCNT_AFH,
800 	BTC_BCNT_INFOUPDATE,
801 	BTC_BCNT_INFOSAME,
802 	BTC_BCNT_SCBDUPDATE,
803 	BTC_BCNT_HIPRI_TX,
804 	BTC_BCNT_HIPRI_RX,
805 	BTC_BCNT_LOPRI_TX,
806 	BTC_BCNT_LOPRI_RX,
807 	BTC_BCNT_RATECHG,
808 	BTC_BCNT_NUM
809 };
810 
811 enum rtw89_btc_bt_profile {
812 	BTC_BT_NOPROFILE = 0,
813 	BTC_BT_HFP = BIT(0),
814 	BTC_BT_HID = BIT(1),
815 	BTC_BT_A2DP = BIT(2),
816 	BTC_BT_PAN = BIT(3),
817 	BTC_PROFILE_MAX = 4,
818 };
819 
820 struct rtw89_btc_ant_info {
821 	u8 type;  /* shared, dedicated */
822 	u8 num;
823 	u8 isolation;
824 
825 	u8 single_pos: 1;/* Single antenna at S0 or S1 */
826 	u8 diversity: 1;
827 };
828 
829 enum rtw89_tfc_dir {
830 	RTW89_TFC_UL,
831 	RTW89_TFC_DL,
832 };
833 
834 struct rtw89_btc_wl_smap {
835 	u32 busy: 1;
836 	u32 scan: 1;
837 	u32 connecting: 1;
838 	u32 roaming: 1;
839 	u32 _4way: 1;
840 	u32 rf_off: 1;
841 	u32 lps: 1;
842 	u32 ips: 1;
843 	u32 init_ok: 1;
844 	u32 traffic_dir : 2;
845 	u32 rf_off_pre: 1;
846 	u32 lps_pre: 1;
847 };
848 
849 enum rtw89_tfc_lv {
850 	RTW89_TFC_IDLE,
851 	RTW89_TFC_ULTRA_LOW,
852 	RTW89_TFC_LOW,
853 	RTW89_TFC_MID,
854 	RTW89_TFC_HIGH,
855 };
856 
857 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
858 DECLARE_EWMA(tp, 10, 2);
859 
860 struct rtw89_traffic_stats {
861 	/* units in bytes */
862 	u64 tx_unicast;
863 	u64 rx_unicast;
864 	u32 tx_avg_len;
865 	u32 rx_avg_len;
866 
867 	/* count for packets */
868 	u64 tx_cnt;
869 	u64 rx_cnt;
870 
871 	/* units in Mbps */
872 	u32 tx_throughput;
873 	u32 rx_throughput;
874 	u32 tx_throughput_raw;
875 	u32 rx_throughput_raw;
876 	enum rtw89_tfc_lv tx_tfc_lv;
877 	enum rtw89_tfc_lv rx_tfc_lv;
878 	struct ewma_tp tx_ewma_tp;
879 	struct ewma_tp rx_ewma_tp;
880 
881 	u16 tx_rate;
882 	u16 rx_rate;
883 };
884 
885 struct rtw89_btc_statistic {
886 	u8 rssi; /* 0%~110% (dBm = rssi -110) */
887 	struct rtw89_traffic_stats traffic;
888 };
889 
890 #define BTC_WL_RSSI_THMAX 4
891 
892 struct rtw89_btc_wl_link_info {
893 	struct rtw89_btc_statistic stat;
894 	enum rtw89_tfc_dir dir;
895 	u8 rssi_state[BTC_WL_RSSI_THMAX];
896 	u8 mac_addr[ETH_ALEN];
897 	u8 busy;
898 	u8 ch;
899 	u8 bw;
900 	u8 band;
901 	u8 role;
902 	u8 pid;
903 	u8 phy;
904 	u8 dtim_period;
905 	u8 mode;
906 
907 	u8 mac_id;
908 	u8 tx_retry;
909 
910 	u32 bcn_period;
911 	u32 busy_t;
912 	u32 tx_time;
913 	u32 client_cnt;
914 	u32 rx_rate_drop_cnt;
915 
916 	u32 active: 1;
917 	u32 noa: 1;
918 	u32 client_ps: 1;
919 	u32 connected: 2;
920 };
921 
922 union rtw89_btc_wl_state_map {
923 	u32 val;
924 	struct rtw89_btc_wl_smap map;
925 };
926 
927 struct rtw89_btc_bt_hfp_desc {
928 	u32 exist: 1;
929 	u32 type: 2;
930 	u32 rsvd: 29;
931 };
932 
933 struct rtw89_btc_bt_hid_desc {
934 	u32 exist: 1;
935 	u32 slot_info: 2;
936 	u32 pair_cnt: 2;
937 	u32 type: 8;
938 	u32 rsvd: 19;
939 };
940 
941 struct rtw89_btc_bt_a2dp_desc {
942 	u8 exist: 1;
943 	u8 exist_last: 1;
944 	u8 play_latency: 1;
945 	u8 type: 3;
946 	u8 active: 1;
947 	u8 sink: 1;
948 
949 	u8 bitpool;
950 	u16 vendor_id;
951 	u32 device_name;
952 	u32 flush_time;
953 };
954 
955 struct rtw89_btc_bt_pan_desc {
956 	u32 exist: 1;
957 	u32 type: 1;
958 	u32 active: 1;
959 	u32 rsvd: 29;
960 };
961 
962 struct rtw89_btc_bt_rfk_info {
963 	u32 run: 1;
964 	u32 req: 1;
965 	u32 timeout: 1;
966 	u32 rsvd: 29;
967 };
968 
969 union rtw89_btc_bt_rfk_info_map {
970 	u32 val;
971 	struct rtw89_btc_bt_rfk_info map;
972 };
973 
974 struct rtw89_btc_bt_ver_info {
975 	u32 fw_coex; /* match with which coex_ver */
976 	u32 fw;
977 };
978 
979 struct rtw89_btc_bool_sta_chg {
980 	u32 now: 1;
981 	u32 last: 1;
982 	u32 remain: 1;
983 	u32 srvd: 29;
984 };
985 
986 struct rtw89_btc_u8_sta_chg {
987 	u8 now;
988 	u8 last;
989 	u8 remain;
990 	u8 rsvd;
991 };
992 
993 struct rtw89_btc_wl_scan_info {
994 	u8 band[RTW89_PHY_MAX];
995 	u8 phy_map;
996 	u8 rsvd;
997 };
998 
999 struct rtw89_btc_wl_dbcc_info {
1000 	u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1001 	u8 scan_band[RTW89_PHY_MAX]; /* scan band in  each phy */
1002 	u8 real_band[RTW89_PHY_MAX];
1003 	u8 role[RTW89_PHY_MAX]; /* role in each phy */
1004 };
1005 
1006 struct rtw89_btc_wl_active_role {
1007 	u8 connected: 1;
1008 	u8 pid: 3;
1009 	u8 phy: 1;
1010 	u8 noa: 1;
1011 	u8 band: 2;
1012 
1013 	u8 client_ps: 1;
1014 	u8 bw: 7;
1015 
1016 	u8 role;
1017 	u8 ch;
1018 
1019 	u16 tx_lvl;
1020 	u16 rx_lvl;
1021 	u16 tx_rate;
1022 	u16 rx_rate;
1023 };
1024 
1025 struct rtw89_btc_wl_role_info_bpos {
1026 	u16 none: 1;
1027 	u16 station: 1;
1028 	u16 ap: 1;
1029 	u16 vap: 1;
1030 	u16 adhoc: 1;
1031 	u16 adhoc_master: 1;
1032 	u16 mesh: 1;
1033 	u16 moniter: 1;
1034 	u16 p2p_device: 1;
1035 	u16 p2p_gc: 1;
1036 	u16 p2p_go: 1;
1037 	u16 nan: 1;
1038 };
1039 
1040 union rtw89_btc_wl_role_info_map {
1041 	u16 val;
1042 	struct rtw89_btc_wl_role_info_bpos role;
1043 };
1044 
1045 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1046 	u8 connect_cnt;
1047 	u8 link_mode;
1048 	union rtw89_btc_wl_role_info_map role_map;
1049 	struct rtw89_btc_wl_active_role active_role[RTW89_MAX_HW_PORT_NUM];
1050 };
1051 
1052 struct rtw89_btc_wl_ver_info {
1053 	u32 fw_coex; /* match with which coex_ver */
1054 	u32 fw;
1055 	u32 mac;
1056 	u32 bb;
1057 	u32 rf;
1058 };
1059 
1060 struct rtw89_btc_wl_afh_info {
1061 	u8 en;
1062 	u8 ch;
1063 	u8 bw;
1064 	u8 rsvd;
1065 } __packed;
1066 
1067 struct rtw89_btc_wl_rfk_info {
1068 	u32 state: 2;
1069 	u32 path_map: 4;
1070 	u32 phy_map: 2;
1071 	u32 band: 2;
1072 	u32 type: 8;
1073 	u32 rsvd: 14;
1074 };
1075 
1076 struct rtw89_btc_bt_smap {
1077 	u32 connect: 1;
1078 	u32 ble_connect: 1;
1079 	u32 acl_busy: 1;
1080 	u32 sco_busy: 1;
1081 	u32 mesh_busy: 1;
1082 	u32 inq_pag: 1;
1083 };
1084 
1085 union rtw89_btc_bt_state_map {
1086 	u32 val;
1087 	struct rtw89_btc_bt_smap map;
1088 };
1089 
1090 #define BTC_BT_RSSI_THMAX 4
1091 #define BTC_BT_AFH_GROUP 12
1092 
1093 struct rtw89_btc_bt_link_info {
1094 	struct rtw89_btc_u8_sta_chg profile_cnt;
1095 	struct rtw89_btc_bool_sta_chg multi_link;
1096 	struct rtw89_btc_bool_sta_chg relink;
1097 	struct rtw89_btc_bt_hfp_desc hfp_desc;
1098 	struct rtw89_btc_bt_hid_desc hid_desc;
1099 	struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1100 	struct rtw89_btc_bt_pan_desc pan_desc;
1101 	union rtw89_btc_bt_state_map status;
1102 
1103 	u8 sut_pwr_level[BTC_PROFILE_MAX];
1104 	u8 golden_rx_shift[BTC_PROFILE_MAX];
1105 	u8 rssi_state[BTC_BT_RSSI_THMAX];
1106 	u8 afh_map[BTC_BT_AFH_GROUP];
1107 
1108 	u32 role_sw: 1;
1109 	u32 slave_role: 1;
1110 	u32 afh_update: 1;
1111 	u32 cqddr: 1;
1112 	u32 rssi: 8;
1113 	u32 tx_3m: 1;
1114 	u32 rsvd: 19;
1115 };
1116 
1117 struct rtw89_btc_3rdcx_info {
1118 	u8 type;   /* 0: none, 1:zigbee, 2:LTE  */
1119 	u8 hw_coex;
1120 	u16 rsvd;
1121 };
1122 
1123 struct rtw89_btc_dm_emap {
1124 	u32 init: 1;
1125 	u32 pta_owner: 1;
1126 	u32 wl_rfk_timeout: 1;
1127 	u32 bt_rfk_timeout: 1;
1128 
1129 	u32 wl_fw_hang: 1;
1130 	u32 offload_mismatch: 1;
1131 	u32 cycle_hang: 1;
1132 	u32 w1_hang: 1;
1133 
1134 	u32 b1_hang: 1;
1135 	u32 tdma_no_sync: 1;
1136 	u32 wl_slot_drift: 1;
1137 };
1138 
1139 union rtw89_btc_dm_error_map {
1140 	u32 val;
1141 	struct rtw89_btc_dm_emap map;
1142 };
1143 
1144 struct rtw89_btc_rf_para {
1145 	u32 tx_pwr_freerun;
1146 	u32 rx_gain_freerun;
1147 	u32 tx_pwr_perpkt;
1148 	u32 rx_gain_perpkt;
1149 };
1150 
1151 struct rtw89_btc_wl_info {
1152 	struct rtw89_btc_wl_link_info link_info[RTW89_MAX_HW_PORT_NUM];
1153 	struct rtw89_btc_wl_rfk_info rfk_info;
1154 	struct rtw89_btc_wl_ver_info  ver_info;
1155 	struct rtw89_btc_wl_afh_info afh_info;
1156 	struct rtw89_btc_wl_role_info role_info;
1157 	struct rtw89_btc_wl_scan_info scan_info;
1158 	struct rtw89_btc_wl_dbcc_info dbcc_info;
1159 	struct rtw89_btc_rf_para rf_para;
1160 	union rtw89_btc_wl_state_map status;
1161 
1162 	u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1163 	u8 rssi_level;
1164 
1165 	u32 scbd;
1166 };
1167 
1168 struct rtw89_btc_module {
1169 	struct rtw89_btc_ant_info ant;
1170 	u8 rfe_type;
1171 	u8 cv;
1172 
1173 	u8 bt_solo: 1;
1174 	u8 bt_pos: 1;
1175 	u8 switch_type: 1;
1176 
1177 	u8 rsvd;
1178 };
1179 
1180 #define RTW89_BTC_DM_MAXSTEP 30
1181 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1182 
1183 struct rtw89_btc_dm_step {
1184 	u16 step[RTW89_BTC_DM_MAXSTEP];
1185 	u8 step_pos;
1186 	bool step_ov;
1187 };
1188 
1189 struct rtw89_btc_init_info {
1190 	struct rtw89_btc_module module;
1191 	u8 wl_guard_ch;
1192 
1193 	u8 wl_only: 1;
1194 	u8 wl_init_ok: 1;
1195 	u8 dbcc_en: 1;
1196 	u8 cx_other: 1;
1197 	u8 bt_only: 1;
1198 
1199 	u16 rsvd;
1200 };
1201 
1202 struct rtw89_btc_wl_tx_limit_para {
1203 	u16 enable;
1204 	u32 tx_time;	/* unit: us */
1205 	u16 tx_retry;
1206 };
1207 
1208 struct rtw89_btc_bt_scan_info {
1209 	u16 win;
1210 	u16 intvl;
1211 	u32 enable: 1;
1212 	u32 interlace: 1;
1213 	u32 rsvd: 30;
1214 };
1215 
1216 enum rtw89_btc_bt_scan_type {
1217 	BTC_SCAN_INQ	= 0,
1218 	BTC_SCAN_PAGE,
1219 	BTC_SCAN_BLE,
1220 	BTC_SCAN_INIT,
1221 	BTC_SCAN_TV,
1222 	BTC_SCAN_ADV,
1223 	BTC_SCAN_MAX1,
1224 };
1225 
1226 struct rtw89_btc_bt_info {
1227 	struct rtw89_btc_bt_link_info link_info;
1228 	struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1];
1229 	struct rtw89_btc_bt_ver_info ver_info;
1230 	struct rtw89_btc_bool_sta_chg enable;
1231 	struct rtw89_btc_bool_sta_chg inq_pag;
1232 	struct rtw89_btc_rf_para rf_para;
1233 	union rtw89_btc_bt_rfk_info_map rfk_info;
1234 
1235 	u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1236 
1237 	u32 scbd;
1238 	u32 feature;
1239 
1240 	u32 mbx_avl: 1;
1241 	u32 whql_test: 1;
1242 	u32 igno_wl: 1;
1243 	u32 reinit: 1;
1244 	u32 ble_scan_en: 1;
1245 	u32 btg_type: 1;
1246 	u32 inq: 1;
1247 	u32 pag: 1;
1248 	u32 run_patch_code: 1;
1249 	u32 hi_lna_rx: 1;
1250 	u32 rsvd: 22;
1251 };
1252 
1253 struct rtw89_btc_cx {
1254 	struct rtw89_btc_wl_info wl;
1255 	struct rtw89_btc_bt_info bt;
1256 	struct rtw89_btc_3rdcx_info other;
1257 	u32 state_map;
1258 	u32 cnt_bt[BTC_BCNT_NUM];
1259 	u32 cnt_wl[BTC_WCNT_NUM];
1260 };
1261 
1262 struct rtw89_btc_fbtc_tdma {
1263 	u8 type;
1264 	u8 rxflctrl;
1265 	u8 txpause;
1266 	u8 wtgle_n;
1267 	u8 leak_n;
1268 	u8 ext_ctrl;
1269 	u8 rsvd0;
1270 	u8 rsvd1;
1271 } __packed;
1272 
1273 #define CXMREG_MAX 30
1274 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1275 #define BTCRPT_VER 1
1276 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1277 
1278 enum rtw89_btc_bt_rfk_counter {
1279 	BTC_BCNT_RFK_REQ = 0,
1280 	BTC_BCNT_RFK_GO = 1,
1281 	BTC_BCNT_RFK_REJECT = 2,
1282 	BTC_BCNT_RFK_FAIL = 3,
1283 	BTC_BCNT_RFK_TIMEOUT = 4,
1284 	BTC_BCNT_RFK_MAX
1285 };
1286 
1287 struct rtw89_btc_fbtc_rpt_ctrl {
1288 	u16 fver;
1289 	u16 rpt_cnt; /* tmr counters */
1290 	u32 wl_fw_coex_ver; /* match which driver's coex version */
1291 	u32 wl_fw_cx_offload;
1292 	u32 wl_fw_ver;
1293 	u32 rpt_enable;
1294 	u32 rpt_para; /* ms */
1295 	u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1296 	u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1297 	u32 mb_recv_cnt; /* fw recv mailbox counter */
1298 	u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1299 	u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1300 	u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1301 	u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX];
1302 	u32 c2h_cnt; /* fw send c2h counter  */
1303 	u32 h2c_cnt; /* fw recv h2c counter */
1304 } __packed;
1305 
1306 enum rtw89_fbtc_ext_ctrl_type {
1307 	CXECTL_OFF = 0x0, /* tdma off */
1308 	CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
1309 	CXECTL_EXT = 0x2,
1310 	CXECTL_MAX
1311 };
1312 
1313 union rtw89_btc_fbtc_rxflct {
1314 	u8 val;
1315 	u8 type: 3;
1316 	u8 tgln_n: 5;
1317 };
1318 
1319 enum rtw89_btc_cxst_state {
1320 	CXST_OFF = 0x0,
1321 	CXST_B2W = 0x1,
1322 	CXST_W1 = 0x2,
1323 	CXST_W2 = 0x3,
1324 	CXST_W2B = 0x4,
1325 	CXST_B1 = 0x5,
1326 	CXST_B2 = 0x6,
1327 	CXST_B3 = 0x7,
1328 	CXST_B4 = 0x8,
1329 	CXST_LK = 0x9,
1330 	CXST_BLK = 0xa,
1331 	CXST_E2G = 0xb,
1332 	CXST_E5G = 0xc,
1333 	CXST_EBT = 0xd,
1334 	CXST_ENULL = 0xe,
1335 	CXST_WLK = 0xf,
1336 	CXST_W1FDD = 0x10,
1337 	CXST_B1FDD = 0x11,
1338 	CXST_MAX = 0x12,
1339 };
1340 
1341 enum {
1342 	CXBCN_ALL = 0x0,
1343 	CXBCN_ALL_OK,
1344 	CXBCN_BT_SLOT,
1345 	CXBCN_BT_OK,
1346 	CXBCN_MAX
1347 };
1348 
1349 enum btc_slot_type {
1350 	SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
1351 	SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
1352 	CXSTYPE_NUM,
1353 };
1354 
1355 enum { /* TIME */
1356 	CXT_BT = 0x0,
1357 	CXT_WL = 0x1,
1358 	CXT_MAX
1359 };
1360 
1361 enum { /* TIME-A2DP */
1362 	CXT_FLCTRL_OFF = 0x0,
1363 	CXT_FLCTRL_ON = 0x1,
1364 	CXT_FLCTRL_MAX
1365 };
1366 
1367 enum { /* STEP TYPE */
1368 	CXSTEP_NONE = 0x0,
1369 	CXSTEP_EVNT = 0x1,
1370 	CXSTEP_SLOT = 0x2,
1371 	CXSTEP_MAX,
1372 };
1373 
1374 #define FCXGPIODBG_VER 1
1375 #define BTC_DBG_MAX1  32
1376 struct rtw89_btc_fbtc_gpio_dbg {
1377 	u8 fver;
1378 	u8 rsvd;
1379 	u16 rsvd2;
1380 	u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
1381 	u32 pre_state; /* the debug signal is 1 or 0  */
1382 	u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
1383 } __packed;
1384 
1385 #define FCXMREG_VER 1
1386 struct rtw89_btc_fbtc_mreg_val {
1387 	u8 fver;
1388 	u8 reg_num;
1389 	__le16 rsvd;
1390 	__le32 mreg_val[CXMREG_MAX];
1391 } __packed;
1392 
1393 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
1394 	{ .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
1395 	  .offset = cpu_to_le32(__offset), }
1396 
1397 struct rtw89_btc_fbtc_mreg {
1398 	__le16 type;
1399 	__le16 bytes;
1400 	__le32 offset;
1401 } __packed;
1402 
1403 struct rtw89_btc_fbtc_slot {
1404 	__le16 dur;
1405 	__le32 cxtbl;
1406 	__le16 cxtype;
1407 } __packed;
1408 
1409 #define FCXSLOTS_VER 1
1410 struct rtw89_btc_fbtc_slots {
1411 	u8 fver;
1412 	u8 tbl_num;
1413 	__le16 rsvd;
1414 	__le32 update_map;
1415 	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1416 } __packed;
1417 
1418 #define FCXSTEP_VER 2
1419 struct rtw89_btc_fbtc_step {
1420 	u8 type;
1421 	u8 val;
1422 	__le16 difft;
1423 } __packed;
1424 
1425 struct rtw89_btc_fbtc_steps {
1426 	u8 fver;
1427 	u8 rsvd;
1428 	__le16 cnt;
1429 	__le16 pos_old;
1430 	__le16 pos_new;
1431 	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
1432 } __packed;
1433 
1434 #define FCXCYSTA_VER 2
1435 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */
1436 	u8 fver;
1437 	u8 rsvd;
1438 	__le16 cycles; /* total cycle number */
1439 	__le16 cycles_a2dp[CXT_FLCTRL_MAX];
1440 	__le16 a2dpept; /* a2dp empty cnt */
1441 	__le16 a2dpeptto; /* a2dp empty timeout cnt*/
1442 	__le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
1443 	__le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
1444 	__le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
1445 	__le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
1446 	__le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
1447 	__le16 tavg_a2dpept; /* avg a2dp empty time */
1448 	__le16 tmax_a2dpept; /* max a2dp empty time */
1449 	__le16 tavg_lk; /* avg leak-slot time */
1450 	__le16 tmax_lk; /* max leak-slot time */
1451 	__le32 slot_cnt[CXST_MAX]; /* slot count */
1452 	__le32 bcn_cnt[CXBCN_MAX];
1453 	__le32 leakrx_cnt; /* the rximr occur at leak slot  */
1454 	__le32 collision_cnt; /* counter for event/timer occur at same time */
1455 	__le32 skip_cnt;
1456 	__le32 exception;
1457 	__le32 except_cnt;
1458 	__le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
1459 } __packed;
1460 
1461 #define FCXNULLSTA_VER 1
1462 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */
1463 	u8 fver;
1464 	u8 rsvd;
1465 	__le16 rsvd2;
1466 	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
1467 	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
1468 	__le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
1469 } __packed;
1470 
1471 #define FCX_BTVER_VER 1
1472 struct rtw89_btc_fbtc_btver {
1473 	u8 fver;
1474 	u8 rsvd;
1475 	__le16 rsvd2;
1476 	__le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
1477 	__le32 fw_ver;
1478 	__le32 feature;
1479 } __packed;
1480 
1481 #define FCX_BTSCAN_VER 1
1482 struct rtw89_btc_fbtc_btscan {
1483 	u8 fver;
1484 	u8 rsvd;
1485 	__le16 rsvd2;
1486 	u8 scan[6];
1487 } __packed;
1488 
1489 #define FCX_BTAFH_VER 1
1490 struct rtw89_btc_fbtc_btafh {
1491 	u8 fver;
1492 	u8 rsvd;
1493 	__le16 rsvd2;
1494 	u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
1495 	u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
1496 	u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
1497 } __packed;
1498 
1499 #define FCX_BTDEVINFO_VER 1
1500 struct rtw89_btc_fbtc_btdevinfo {
1501 	u8 fver;
1502 	u8 rsvd;
1503 	__le16 vendor_id;
1504 	__le32 dev_name; /* only 24 bits valid */
1505 	__le32 flush_time;
1506 } __packed;
1507 
1508 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
1509 struct rtw89_btc_rf_trx_para {
1510 	u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
1511 	u32 wl_rx_gain;  /* rx gain table index (TBD.) */
1512 	u8 bt_tx_power; /* decrease Tx power (dB) */
1513 	u8 bt_rx_gain;  /* LNA constrain level */
1514 };
1515 
1516 struct rtw89_btc_dm {
1517 	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
1518 	struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
1519 	struct rtw89_btc_fbtc_tdma tdma;
1520 	struct rtw89_btc_fbtc_tdma tdma_now;
1521 	struct rtw89_mac_ax_coex_gnt gnt;
1522 	struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
1523 	struct rtw89_btc_rf_trx_para rf_trx_para;
1524 	struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
1525 	struct rtw89_btc_dm_step dm_step;
1526 	union rtw89_btc_dm_error_map error;
1527 	u32 cnt_dm[BTC_DCNT_NUM];
1528 	u32 cnt_notify[BTC_NCNT_NUM];
1529 
1530 	u32 update_slot_map;
1531 	u32 set_ant_path;
1532 
1533 	u32 wl_only: 1;
1534 	u32 wl_fw_cx_offload: 1;
1535 	u32 freerun: 1;
1536 	u32 wl_ps_ctrl: 2;
1537 	u32 wl_mimo_ps: 1;
1538 	u32 leak_ap: 1;
1539 	u32 noisy_level: 3;
1540 	u32 coex_info_map: 8;
1541 	u32 bt_only: 1;
1542 	u32 wl_btg_rx: 1;
1543 	u32 trx_para_level: 8;
1544 	u32 wl_stb_chg: 1;
1545 	u32 rsvd: 3;
1546 
1547 	u16 slot_dur[CXST_MAX];
1548 
1549 	u8 run_reason;
1550 	u8 run_action;
1551 };
1552 
1553 struct rtw89_btc_ctrl {
1554 	u32 manual: 1;
1555 	u32 igno_bt: 1;
1556 	u32 always_freerun: 1;
1557 	u32 trace_step: 16;
1558 	u32 rsvd: 12;
1559 };
1560 
1561 struct rtw89_btc_dbg {
1562 	/* cmd "rb" */
1563 	bool rb_done;
1564 	u32 rb_val;
1565 };
1566 
1567 #define FCXTDMA_VER 1
1568 
1569 enum rtw89_btc_btf_fw_event {
1570 	BTF_EVNT_RPT = 0,
1571 	BTF_EVNT_BT_INFO = 1,
1572 	BTF_EVNT_BT_SCBD = 2,
1573 	BTF_EVNT_BT_REG = 3,
1574 	BTF_EVNT_CX_RUNINFO = 4,
1575 	BTF_EVNT_BT_PSD = 5,
1576 	BTF_EVNT_BUF_OVERFLOW,
1577 	BTF_EVNT_C2H_LOOPBACK,
1578 	BTF_EVNT_MAX,
1579 };
1580 
1581 enum btf_fw_event_report {
1582 	BTC_RPT_TYPE_CTRL = 0x0,
1583 	BTC_RPT_TYPE_TDMA,
1584 	BTC_RPT_TYPE_SLOT,
1585 	BTC_RPT_TYPE_CYSTA,
1586 	BTC_RPT_TYPE_STEP,
1587 	BTC_RPT_TYPE_NULLSTA,
1588 	BTC_RPT_TYPE_MREG,
1589 	BTC_RPT_TYPE_GPIO_DBG,
1590 	BTC_RPT_TYPE_BT_VER,
1591 	BTC_RPT_TYPE_BT_SCAN,
1592 	BTC_RPT_TYPE_BT_AFH,
1593 	BTC_RPT_TYPE_BT_DEVICE,
1594 	BTC_RPT_TYPE_TEST,
1595 	BTC_RPT_TYPE_MAX = 31
1596 };
1597 
1598 enum rtw_btc_btf_reg_type {
1599 	REG_MAC = 0x0,
1600 	REG_BB = 0x1,
1601 	REG_RF = 0x2,
1602 	REG_BT_RF = 0x3,
1603 	REG_BT_MODEM = 0x4,
1604 	REG_BT_BLUEWIZE = 0x5,
1605 	REG_BT_VENDOR = 0x6,
1606 	REG_BT_LE = 0x7,
1607 	REG_MAX_TYPE,
1608 };
1609 
1610 struct rtw89_btc_rpt_cmn_info {
1611 	u32 rx_cnt;
1612 	u32 rx_len;
1613 	u32 req_len; /* expected rsp len */
1614 	u8 req_fver; /* expected rsp fver */
1615 	u8 rsp_fver; /* fver from fw */
1616 	u8 valid;
1617 } __packed;
1618 
1619 struct rtw89_btc_report_ctrl_state {
1620 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1621 	struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */
1622 };
1623 
1624 struct rtw89_btc_rpt_fbtc_tdma {
1625 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1626 	struct rtw89_btc_fbtc_tdma finfo; /* info from fw */
1627 };
1628 
1629 struct rtw89_btc_rpt_fbtc_slots {
1630 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1631 	struct rtw89_btc_fbtc_slots finfo; /* info from fw */
1632 };
1633 
1634 struct rtw89_btc_rpt_fbtc_cysta {
1635 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1636 	struct rtw89_btc_fbtc_cysta finfo; /* info from fw */
1637 };
1638 
1639 struct rtw89_btc_rpt_fbtc_step {
1640 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1641 	struct rtw89_btc_fbtc_steps finfo; /* info from fw */
1642 };
1643 
1644 struct rtw89_btc_rpt_fbtc_nullsta {
1645 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1646 	struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */
1647 };
1648 
1649 struct rtw89_btc_rpt_fbtc_mreg {
1650 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1651 	struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
1652 };
1653 
1654 struct rtw89_btc_rpt_fbtc_gpio_dbg {
1655 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1656 	struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
1657 };
1658 
1659 struct rtw89_btc_rpt_fbtc_btver {
1660 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1661 	struct rtw89_btc_fbtc_btver finfo; /* info from fw */
1662 };
1663 
1664 struct rtw89_btc_rpt_fbtc_btscan {
1665 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1666 	struct rtw89_btc_fbtc_btscan finfo; /* info from fw */
1667 };
1668 
1669 struct rtw89_btc_rpt_fbtc_btafh {
1670 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1671 	struct rtw89_btc_fbtc_btafh finfo; /* info from fw */
1672 };
1673 
1674 struct rtw89_btc_rpt_fbtc_btdev {
1675 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
1676 	struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
1677 };
1678 
1679 enum rtw89_btc_btfre_type {
1680 	BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
1681 	BTFRE_UNDEF_TYPE,
1682 	BTFRE_EXCEPTION,
1683 	BTFRE_MAX,
1684 };
1685 
1686 struct rtw89_btc_btf_fwinfo {
1687 	u32 cnt_c2h;
1688 	u32 cnt_h2c;
1689 	u32 cnt_h2c_fail;
1690 	u32 event[BTF_EVNT_MAX];
1691 
1692 	u32 err[BTFRE_MAX];
1693 	u32 len_mismch;
1694 	u32 fver_mismch;
1695 	u32 rpt_en_map;
1696 
1697 	struct rtw89_btc_report_ctrl_state rpt_ctrl;
1698 	struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
1699 	struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
1700 	struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
1701 	struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
1702 	struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
1703 	struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
1704 	struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
1705 	struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
1706 	struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
1707 	struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
1708 	struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
1709 };
1710 
1711 #define RTW89_BTC_POLICY_MAXLEN 512
1712 
1713 struct rtw89_btc {
1714 	struct rtw89_btc_cx cx;
1715 	struct rtw89_btc_dm dm;
1716 	struct rtw89_btc_ctrl ctrl;
1717 	struct rtw89_btc_module mdinfo;
1718 	struct rtw89_btc_btf_fwinfo fwinfo;
1719 	struct rtw89_btc_dbg dbg;
1720 
1721 	struct work_struct eapol_notify_work;
1722 	struct work_struct arp_notify_work;
1723 	struct work_struct dhcp_notify_work;
1724 	struct work_struct icmp_notify_work;
1725 
1726 	u32 bt_req_len;
1727 
1728 	u8 policy[RTW89_BTC_POLICY_MAXLEN];
1729 	u16 policy_len;
1730 	u16 policy_type;
1731 	bool bt_req_en;
1732 	bool update_policy_force;
1733 	bool lps;
1734 };
1735 
1736 enum rtw89_ra_mode {
1737 	RTW89_RA_MODE_CCK = BIT(0),
1738 	RTW89_RA_MODE_OFDM = BIT(1),
1739 	RTW89_RA_MODE_HT = BIT(2),
1740 	RTW89_RA_MODE_VHT = BIT(3),
1741 	RTW89_RA_MODE_HE = BIT(4),
1742 };
1743 
1744 enum rtw89_ra_report_mode {
1745 	RTW89_RA_RPT_MODE_LEGACY,
1746 	RTW89_RA_RPT_MODE_HT,
1747 	RTW89_RA_RPT_MODE_VHT,
1748 	RTW89_RA_RPT_MODE_HE,
1749 };
1750 
1751 enum rtw89_dig_noisy_level {
1752 	RTW89_DIG_NOISY_LEVEL0 = -1,
1753 	RTW89_DIG_NOISY_LEVEL1 = 0,
1754 	RTW89_DIG_NOISY_LEVEL2 = 1,
1755 	RTW89_DIG_NOISY_LEVEL3 = 2,
1756 	RTW89_DIG_NOISY_LEVEL_MAX = 3,
1757 };
1758 
1759 enum rtw89_gi_ltf {
1760 	RTW89_GILTF_LGI_4XHE32 = 0,
1761 	RTW89_GILTF_SGI_4XHE08 = 1,
1762 	RTW89_GILTF_2XHE16 = 2,
1763 	RTW89_GILTF_2XHE08 = 3,
1764 	RTW89_GILTF_1XHE16 = 4,
1765 	RTW89_GILTF_1XHE08 = 5,
1766 	RTW89_GILTF_MAX
1767 };
1768 
1769 enum rtw89_rx_frame_type {
1770 	RTW89_RX_TYPE_MGNT = 0,
1771 	RTW89_RX_TYPE_CTRL = 1,
1772 	RTW89_RX_TYPE_DATA = 2,
1773 	RTW89_RX_TYPE_RSVD = 3,
1774 };
1775 
1776 struct rtw89_ra_info {
1777 	u8 is_dis_ra:1;
1778 	/* Bit0 : CCK
1779 	 * Bit1 : OFDM
1780 	 * Bit2 : HT
1781 	 * Bit3 : VHT
1782 	 * Bit4 : HE
1783 	 */
1784 	u8 mode_ctrl:5;
1785 	u8 bw_cap:2;
1786 	u8 macid;
1787 	u8 dcm_cap:1;
1788 	u8 er_cap:1;
1789 	u8 init_rate_lv:2;
1790 	u8 upd_all:1;
1791 	u8 en_sgi:1;
1792 	u8 ldpc_cap:1;
1793 	u8 stbc_cap:1;
1794 	u8 ss_num:3;
1795 	u8 giltf:3;
1796 	u8 upd_bw_nss_mask:1;
1797 	u8 upd_mask:1;
1798 	u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
1799 	/* BFee CSI */
1800 	u8 band_num;
1801 	u8 ra_csi_rate_en:1;
1802 	u8 fixed_csi_rate_en:1;
1803 	u8 cr_tbl_sel:1;
1804 	u8 rsvd2:5;
1805 	u8 csi_mcs_ss_idx;
1806 	u8 csi_mode:2;
1807 	u8 csi_gi_ltf:3;
1808 	u8 csi_bw:3;
1809 };
1810 
1811 #define RTW89_PPDU_MAX_USR 4
1812 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
1813 #define RTW89_PPDU_MAC_INFO_SIZE 8
1814 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
1815 
1816 #define RTW89_MAX_RX_AGG_NUM 64
1817 #define RTW89_MAX_TX_AGG_NUM 128
1818 
1819 struct rtw89_ampdu_params {
1820 	u16 agg_num;
1821 	bool amsdu;
1822 };
1823 
1824 struct rtw89_ra_report {
1825 	struct rate_info txrate;
1826 	u32 bit_rate;
1827 	u16 hw_rate;
1828 };
1829 
1830 DECLARE_EWMA(rssi, 10, 16);
1831 
1832 struct rtw89_sta {
1833 	u8 mac_id;
1834 	bool disassoc;
1835 	struct rtw89_vif *rtwvif;
1836 	struct rtw89_ra_info ra;
1837 	struct rtw89_ra_report ra_report;
1838 	int max_agg_wait;
1839 	u8 prev_rssi;
1840 	struct ewma_rssi avg_rssi;
1841 	struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
1842 	struct ieee80211_rx_status rx_status;
1843 	u16 rx_hw_rate;
1844 	__le32 htc_template;
1845 
1846 	bool use_cfg_mask;
1847 	struct cfg80211_bitrate_mask mask;
1848 
1849 	bool cctl_tx_time;
1850 	u32 ampdu_max_time:4;
1851 	bool cctl_tx_retry_limit;
1852 	u32 data_tx_cnt_lmt:6;
1853 };
1854 
1855 #define RTW89_MAX_ADDR_CAM_NUM		128
1856 #define RTW89_MAX_BSSID_CAM_NUM		20
1857 #define RTW89_MAX_SEC_CAM_NUM		128
1858 #define RTW89_SEC_CAM_IN_ADDR_CAM	7
1859 
1860 struct rtw89_addr_cam_entry {
1861 	u8 addr_cam_idx;
1862 	u8 offset;
1863 	u8 len;
1864 	u8 valid	: 1;
1865 	u8 addr_mask	: 6;
1866 	u8 wapi		: 1;
1867 	u8 mask_sel	: 2;
1868 	u8 bssid_cam_idx: 6;
1869 	u8 tma[ETH_ALEN];
1870 	u8 sma[ETH_ALEN];
1871 
1872 	u8 sec_ent_mode;
1873 	DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
1874 	u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
1875 	u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
1876 	struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
1877 };
1878 
1879 struct rtw89_bssid_cam_entry {
1880 	u8 bssid[ETH_ALEN];
1881 	u8 phy_idx;
1882 	u8 bssid_cam_idx;
1883 	u8 offset;
1884 	u8 len;
1885 	u8 valid : 1;
1886 	u8 num;
1887 };
1888 
1889 struct rtw89_sec_cam_entry {
1890 	u8 sec_cam_idx;
1891 	u8 offset;
1892 	u8 len;
1893 	u8 type : 4;
1894 	u8 ext_key : 1;
1895 	u8 spp_mode : 1;
1896 	/* 256 bits */
1897 	u8 key[32];
1898 };
1899 
1900 struct rtw89_efuse {
1901 	bool valid;
1902 	u8 xtal_cap;
1903 	u8 addr[ETH_ALEN];
1904 	u8 rfe_type;
1905 	char country_code[2];
1906 };
1907 
1908 struct rtw89_phy_rate_pattern {
1909 	u64 ra_mask;
1910 	u16 rate;
1911 	u8 ra_mode;
1912 	bool enable;
1913 };
1914 
1915 struct rtw89_vif {
1916 	struct list_head list;
1917 	u8 mac_id;
1918 	u8 port;
1919 	u8 mac_addr[ETH_ALEN];
1920 	u8 bssid[ETH_ALEN];
1921 	u8 phy_idx;
1922 	u8 mac_idx;
1923 	u8 net_type;
1924 	u8 wifi_role;
1925 	u8 self_role;
1926 	u8 wmm;
1927 	u8 bcn_hit_cond;
1928 	u8 hit_rule;
1929 	bool trigger;
1930 	bool lsig_txop;
1931 	u8 tgt_ind;
1932 	u8 frm_tgt_ind;
1933 	bool wowlan_pattern;
1934 	bool wowlan_uc;
1935 	bool wowlan_magic;
1936 	bool is_hesta;
1937 	bool last_a_ctrl;
1938 	union {
1939 		struct {
1940 			struct ieee80211_sta *ap;
1941 		} mgd;
1942 		struct {
1943 			struct list_head sta_list;
1944 		} ap;
1945 	};
1946 	struct rtw89_addr_cam_entry addr_cam;
1947 	struct rtw89_bssid_cam_entry bssid_cam;
1948 	struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
1949 	struct rtw89_traffic_stats stats;
1950 	struct rtw89_phy_rate_pattern rate_pattern;
1951 };
1952 
1953 enum rtw89_lv1_rcvy_step {
1954 	RTW89_LV1_RCVY_STEP_1,
1955 	RTW89_LV1_RCVY_STEP_2,
1956 };
1957 
1958 struct rtw89_hci_ops {
1959 	int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
1960 	void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
1961 	void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
1962 	void (*reset)(struct rtw89_dev *rtwdev);
1963 	int (*start)(struct rtw89_dev *rtwdev);
1964 	void (*stop)(struct rtw89_dev *rtwdev);
1965 	void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
1966 
1967 	u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
1968 	u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
1969 	u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
1970 	void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
1971 	void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
1972 	void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
1973 
1974 	int (*mac_pre_init)(struct rtw89_dev *rtwdev);
1975 	int (*mac_post_init)(struct rtw89_dev *rtwdev);
1976 	int (*deinit)(struct rtw89_dev *rtwdev);
1977 
1978 	u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
1979 	int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
1980 	void (*dump_err_status)(struct rtw89_dev *rtwdev);
1981 	int (*napi_poll)(struct napi_struct *napi, int budget);
1982 };
1983 
1984 struct rtw89_hci_info {
1985 	const struct rtw89_hci_ops *ops;
1986 	enum rtw89_hci_type type;
1987 	u32 rpwm_addr;
1988 	u32 cpwm_addr;
1989 };
1990 
1991 struct rtw89_chip_ops {
1992 	void (*bb_reset)(struct rtw89_dev *rtwdev,
1993 			 enum rtw89_phy_idx phy_idx);
1994 	void (*bb_sethw)(struct rtw89_dev *rtwdev);
1995 	u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1996 		       u32 addr, u32 mask);
1997 	bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
1998 			 u32 addr, u32 mask, u32 data);
1999 	void (*set_channel)(struct rtw89_dev *rtwdev,
2000 			    struct rtw89_channel_params *param);
2001 	void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
2002 				 struct rtw89_channel_help_params *p);
2003 	int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map);
2004 	int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
2005 	void (*fem_setup)(struct rtw89_dev *rtwdev);
2006 	void (*rfk_init)(struct rtw89_dev *rtwdev);
2007 	void (*rfk_channel)(struct rtw89_dev *rtwdev);
2008 	void (*rfk_band_changed)(struct rtw89_dev *rtwdev);
2009 	void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
2010 	void (*rfk_track)(struct rtw89_dev *rtwdev);
2011 	void (*power_trim)(struct rtw89_dev *rtwdev);
2012 	void (*set_txpwr)(struct rtw89_dev *rtwdev);
2013 	void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev);
2014 	int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
2015 	u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
2016 	void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg);
2017 	void (*query_ppdu)(struct rtw89_dev *rtwdev,
2018 			   struct rtw89_rx_phy_ppdu *phy_ppdu,
2019 			   struct ieee80211_rx_status *status);
2020 	void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en);
2021 	void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
2022 				       s16 pw_ofst, enum rtw89_mac_idx mac_idx);
2023 
2024 	void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
2025 	void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
2026 	void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
2027 	void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
2028 	s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
2029 	void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev);
2030 	void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
2031 	void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
2032 };
2033 
2034 enum rtw89_dma_ch {
2035 	RTW89_DMA_ACH0 = 0,
2036 	RTW89_DMA_ACH1 = 1,
2037 	RTW89_DMA_ACH2 = 2,
2038 	RTW89_DMA_ACH3 = 3,
2039 	RTW89_DMA_ACH4 = 4,
2040 	RTW89_DMA_ACH5 = 5,
2041 	RTW89_DMA_ACH6 = 6,
2042 	RTW89_DMA_ACH7 = 7,
2043 	RTW89_DMA_B0MG = 8,
2044 	RTW89_DMA_B0HI = 9,
2045 	RTW89_DMA_B1MG = 10,
2046 	RTW89_DMA_B1HI = 11,
2047 	RTW89_DMA_H2C = 12,
2048 	RTW89_DMA_CH_NUM = 13
2049 };
2050 
2051 enum rtw89_qta_mode {
2052 	RTW89_QTA_SCC,
2053 	RTW89_QTA_DLFW,
2054 
2055 	/* keep last */
2056 	RTW89_QTA_INVALID,
2057 };
2058 
2059 struct rtw89_hfc_ch_cfg {
2060 	u16 min;
2061 	u16 max;
2062 #define grp_0 0
2063 #define grp_1 1
2064 #define grp_num 2
2065 	u8 grp;
2066 };
2067 
2068 struct rtw89_hfc_ch_info {
2069 	u16 aval;
2070 	u16 used;
2071 };
2072 
2073 struct rtw89_hfc_pub_cfg {
2074 	u16 grp0;
2075 	u16 grp1;
2076 	u16 pub_max;
2077 	u16 wp_thrd;
2078 };
2079 
2080 struct rtw89_hfc_pub_info {
2081 	u16 g0_used;
2082 	u16 g1_used;
2083 	u16 g0_aval;
2084 	u16 g1_aval;
2085 	u16 pub_aval;
2086 	u16 wp_aval;
2087 };
2088 
2089 struct rtw89_hfc_prec_cfg {
2090 	u16 ch011_prec;
2091 	u16 h2c_prec;
2092 	u16 wp_ch07_prec;
2093 	u16 wp_ch811_prec;
2094 	u8 ch011_full_cond;
2095 	u8 h2c_full_cond;
2096 	u8 wp_ch07_full_cond;
2097 	u8 wp_ch811_full_cond;
2098 };
2099 
2100 struct rtw89_hfc_param {
2101 	bool en;
2102 	bool h2c_en;
2103 	u8 mode;
2104 	const struct rtw89_hfc_ch_cfg *ch_cfg;
2105 	struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
2106 	struct rtw89_hfc_pub_cfg pub_cfg;
2107 	struct rtw89_hfc_pub_info pub_info;
2108 	struct rtw89_hfc_prec_cfg prec_cfg;
2109 };
2110 
2111 struct rtw89_hfc_param_ini {
2112 	const struct rtw89_hfc_ch_cfg *ch_cfg;
2113 	const struct rtw89_hfc_pub_cfg *pub_cfg;
2114 	const struct rtw89_hfc_prec_cfg *prec_cfg;
2115 	u8 mode;
2116 };
2117 
2118 struct rtw89_dle_size {
2119 	u16 pge_size;
2120 	u16 lnk_pge_num;
2121 	u16 unlnk_pge_num;
2122 };
2123 
2124 struct rtw89_wde_quota {
2125 	u16 hif;
2126 	u16 wcpu;
2127 	u16 pkt_in;
2128 	u16 cpu_io;
2129 };
2130 
2131 struct rtw89_ple_quota {
2132 	u16 cma0_tx;
2133 	u16 cma1_tx;
2134 	u16 c2h;
2135 	u16 h2c;
2136 	u16 wcpu;
2137 	u16 mpdu_proc;
2138 	u16 cma0_dma;
2139 	u16 cma1_dma;
2140 	u16 bb_rpt;
2141 	u16 wd_rel;
2142 	u16 cpu_io;
2143 };
2144 
2145 struct rtw89_dle_mem {
2146 	enum rtw89_qta_mode mode;
2147 	const struct rtw89_dle_size *wde_size;
2148 	const struct rtw89_dle_size *ple_size;
2149 	const struct rtw89_wde_quota *wde_min_qt;
2150 	const struct rtw89_wde_quota *wde_max_qt;
2151 	const struct rtw89_ple_quota *ple_min_qt;
2152 	const struct rtw89_ple_quota *ple_max_qt;
2153 };
2154 
2155 struct rtw89_reg_def {
2156 	u32 addr;
2157 	u32 mask;
2158 };
2159 
2160 struct rtw89_reg2_def {
2161 	u32 addr;
2162 	u32 data;
2163 };
2164 
2165 struct rtw89_reg3_def {
2166 	u32 addr;
2167 	u32 mask;
2168 	u32 data;
2169 };
2170 
2171 struct rtw89_reg5_def {
2172 	u8 flag; /* recognized by parsers */
2173 	u8 path;
2174 	u32 addr;
2175 	u32 mask;
2176 	u32 data;
2177 };
2178 
2179 struct rtw89_phy_table {
2180 	const struct rtw89_reg2_def *regs;
2181 	u32 n_regs;
2182 	enum rtw89_rf_path rf_path;
2183 };
2184 
2185 struct rtw89_txpwr_table {
2186 	const void *data;
2187 	u32 size;
2188 	void (*load)(struct rtw89_dev *rtwdev,
2189 		     const struct rtw89_txpwr_table *tbl);
2190 };
2191 
2192 struct rtw89_chip_info {
2193 	enum rtw89_core_chip_id chip_id;
2194 	const struct rtw89_chip_ops *ops;
2195 	const char *fw_name;
2196 	u32 fifo_size;
2197 	u16 max_amsdu_limit;
2198 	bool dis_2g_40m_ul_ofdma;
2199 	const struct rtw89_hfc_param_ini *hfc_param_ini;
2200 	const struct rtw89_dle_mem *dle_mem;
2201 	u32 rf_base_addr[2];
2202 	u8 rf_path_num;
2203 	u8 tx_nss;
2204 	u8 rx_nss;
2205 	u8 acam_num;
2206 	u8 bcam_num;
2207 	u8 scam_num;
2208 
2209 	u8 sec_ctrl_efuse_size;
2210 	u32 physical_efuse_size;
2211 	u32 logical_efuse_size;
2212 	u32 limit_efuse_size;
2213 	u32 phycap_addr;
2214 	u32 phycap_size;
2215 
2216 	const struct rtw89_pwr_cfg * const *pwr_on_seq;
2217 	const struct rtw89_pwr_cfg * const *pwr_off_seq;
2218 	const struct rtw89_phy_table *bb_table;
2219 	const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
2220 	const struct rtw89_phy_table *nctl_table;
2221 	const struct rtw89_txpwr_table *byr_table;
2222 	const struct rtw89_phy_dig_gain_table *dig_table;
2223 	const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
2224 				[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2225 				[RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2226 	const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
2227 				[RTW89_RS_LMT_NUM][RTW89_BF_NUM]
2228 				[RTW89_REGD_NUM][RTW89_5G_CH_NUM];
2229 	const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2230 				   [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
2231 	const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM]
2232 				   [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
2233 
2234 	u8 txpwr_factor_rf;
2235 	u8 txpwr_factor_mac;
2236 
2237 	u32 para_ver;
2238 	u32 wlcx_desired;
2239 	u8 btcx_desired;
2240 	u8 scbd;
2241 	u8 mailbox;
2242 
2243 	u8 afh_guard_ch;
2244 	const u8 *wl_rssi_thres;
2245 	const u8 *bt_rssi_thres;
2246 	u8 rssi_tol;
2247 
2248 	u8 mon_reg_num;
2249 	const struct rtw89_btc_fbtc_mreg *mon_reg;
2250 	u8 rf_para_ulink_num;
2251 	const struct rtw89_btc_rf_trx_para *rf_para_ulink;
2252 	u8 rf_para_dlink_num;
2253 	const struct rtw89_btc_rf_trx_para *rf_para_dlink;
2254 	u8 ps_mode_supported;
2255 };
2256 
2257 enum rtw89_hcifc_mode {
2258 	RTW89_HCIFC_POH = 0,
2259 	RTW89_HCIFC_STF = 1,
2260 	RTW89_HCIFC_SDIO = 2,
2261 
2262 	/* keep last */
2263 	RTW89_HCIFC_MODE_INVALID,
2264 };
2265 
2266 struct rtw89_dle_info {
2267 	enum rtw89_qta_mode qta_mode;
2268 	u16 wde_pg_size;
2269 	u16 ple_pg_size;
2270 	u16 c0_rx_qta;
2271 	u16 c1_rx_qta;
2272 };
2273 
2274 enum rtw89_host_rpr_mode {
2275 	RTW89_RPR_MODE_POH = 0,
2276 	RTW89_RPR_MODE_STF
2277 };
2278 
2279 struct rtw89_mac_info {
2280 	struct rtw89_dle_info dle_info;
2281 	struct rtw89_hfc_param hfc_param;
2282 	enum rtw89_qta_mode qta_mode;
2283 	u8 rpwm_seq_num;
2284 	u8 cpwm_seq_num;
2285 };
2286 
2287 enum rtw89_fw_type {
2288 	RTW89_FW_NORMAL = 1,
2289 	RTW89_FW_WOWLAN = 3,
2290 };
2291 
2292 struct rtw89_fw_suit {
2293 	const u8 *data;
2294 	u32 size;
2295 	u8 major_ver;
2296 	u8 minor_ver;
2297 	u8 sub_ver;
2298 	u8 sub_idex;
2299 	u16 build_year;
2300 	u16 build_mon;
2301 	u16 build_date;
2302 	u16 build_hour;
2303 	u16 build_min;
2304 	u8 cmd_ver;
2305 };
2306 
2307 #define RTW89_FW_VER_CODE(major, minor, sub, idx)	\
2308 	(((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
2309 #define RTW89_FW_SUIT_VER_CODE(s)	\
2310 	RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
2311 
2312 struct rtw89_fw_info {
2313 	const struct firmware *firmware;
2314 	struct rtw89_dev *rtwdev;
2315 	struct completion completion;
2316 	u8 h2c_seq;
2317 	u8 rec_seq;
2318 	struct rtw89_fw_suit normal;
2319 	struct rtw89_fw_suit wowlan;
2320 	bool fw_log_enable;
2321 	bool old_ht_ra_format;
2322 };
2323 
2324 struct rtw89_cam_info {
2325 	DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
2326 	DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
2327 	DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
2328 };
2329 
2330 enum rtw89_sar_sources {
2331 	RTW89_SAR_SOURCE_NONE,
2332 	RTW89_SAR_SOURCE_COMMON,
2333 
2334 	RTW89_SAR_SOURCE_NR,
2335 };
2336 
2337 struct rtw89_sar_cfg_common {
2338 	bool set[RTW89_SUBBAND_NR];
2339 	s32 cfg[RTW89_SUBBAND_NR];
2340 };
2341 
2342 struct rtw89_sar_info {
2343 	/* used to decide how to acces SAR cfg union */
2344 	enum rtw89_sar_sources src;
2345 
2346 	/* reserved for different knids of SAR cfg struct.
2347 	 * supposed that a single cfg struct cannot handle various SAR sources.
2348 	 */
2349 	union {
2350 		struct rtw89_sar_cfg_common cfg_common;
2351 	};
2352 };
2353 
2354 struct rtw89_hal {
2355 	u32 rx_fltr;
2356 	u8 cv;
2357 	u8 current_channel;
2358 	u8 current_primary_channel;
2359 	enum rtw89_subband current_subband;
2360 	u8 current_band_width;
2361 	u8 current_band_type;
2362 	/* center channel for different available bandwidth,
2363 	 * val of (bw > current_band_width) is invalid
2364 	 */
2365 	u8 cch_by_bw[RTW89_MAX_CHANNEL_WIDTH + 1];
2366 	u32 sw_amsdu_max_size;
2367 	u32 antenna_tx;
2368 	u32 antenna_rx;
2369 	u8 tx_nss;
2370 	u8 rx_nss;
2371 };
2372 
2373 #define RTW89_MAX_MAC_ID_NUM 128
2374 
2375 enum rtw89_flags {
2376 	RTW89_FLAG_POWERON,
2377 	RTW89_FLAG_FW_RDY,
2378 	RTW89_FLAG_RUNNING,
2379 	RTW89_FLAG_BFEE_MON,
2380 	RTW89_FLAG_BFEE_EN,
2381 	RTW89_FLAG_NAPI_RUNNING,
2382 	RTW89_FLAG_LEISURE_PS,
2383 	RTW89_FLAG_LOW_POWER_MODE,
2384 	RTW89_FLAG_INACTIVE_PS,
2385 
2386 	NUM_OF_RTW89_FLAGS,
2387 };
2388 
2389 struct rtw89_pkt_stat {
2390 	u16 beacon_nr;
2391 	u32 rx_rate_cnt[RTW89_HW_RATE_NR];
2392 };
2393 
2394 DECLARE_EWMA(thermal, 4, 4);
2395 
2396 struct rtw89_phy_stat {
2397 	struct ewma_thermal avg_thermal[RF_PATH_MAX];
2398 	struct rtw89_pkt_stat cur_pkt_stat;
2399 	struct rtw89_pkt_stat last_pkt_stat;
2400 };
2401 
2402 #define RTW89_DACK_PATH_NR 2
2403 #define RTW89_DACK_IDX_NR 2
2404 #define RTW89_DACK_MSBK_NR 16
2405 struct rtw89_dack_info {
2406 	bool dack_done;
2407 	u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
2408 	u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2409 	u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2410 	u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
2411 	u32 dack_cnt;
2412 	bool addck_timeout[RTW89_DACK_PATH_NR];
2413 	bool dadck_timeout[RTW89_DACK_PATH_NR];
2414 	bool msbk_timeout[RTW89_DACK_PATH_NR];
2415 };
2416 
2417 #define RTW89_IQK_CHS_NR 2
2418 #define RTW89_IQK_PATH_NR 4
2419 struct rtw89_iqk_info {
2420 	bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2421 	bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2422 	bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2423 	bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2424 	u32 iqk_fail_cnt;
2425 	bool is_iqk_init;
2426 	u32 iqk_channel[RTW89_IQK_CHS_NR];
2427 	u8 iqk_band[RTW89_IQK_PATH_NR];
2428 	u8 iqk_ch[RTW89_IQK_PATH_NR];
2429 	u8 iqk_bw[RTW89_IQK_PATH_NR];
2430 	u8 kcount;
2431 	u8 iqk_times;
2432 	u8 version;
2433 	u32 nb_txcfir[RTW89_IQK_PATH_NR];
2434 	u32 nb_rxcfir[RTW89_IQK_PATH_NR];
2435 	u32 bp_txkresult[RTW89_IQK_PATH_NR];
2436 	u32 bp_rxkresult[RTW89_IQK_PATH_NR];
2437 	u32 bp_iqkenable[RTW89_IQK_PATH_NR];
2438 	bool is_wb_txiqk[RTW89_IQK_PATH_NR];
2439 	bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
2440 	bool is_nbiqk;
2441 	bool iqk_fft_en;
2442 	bool iqk_xym_en;
2443 	bool iqk_sram_en;
2444 	bool iqk_cfir_en;
2445 	u8 thermal[RTW89_IQK_PATH_NR];
2446 	bool thermal_rek_en;
2447 	u32 syn1to2;
2448 	u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
2449 	u8 iqk_table_idx[RTW89_IQK_PATH_NR];
2450 };
2451 
2452 #define RTW89_DPK_RF_PATH 2
2453 #define RTW89_DPK_AVG_THERMAL_NUM 8
2454 #define RTW89_DPK_BKUP_NUM 2
2455 struct rtw89_dpk_bkup_para {
2456 	enum rtw89_band band;
2457 	enum rtw89_bandwidth bw;
2458 	u8 ch;
2459 	bool path_ok;
2460 	u8 txagc_dpk;
2461 	u8 ther_dpk;
2462 	u8 gs;
2463 	u16 pwsf;
2464 };
2465 
2466 struct rtw89_dpk_info {
2467 	bool is_dpk_enable;
2468 	bool is_dpk_reload_en;
2469 	u16 dc_i[RTW89_DPK_RF_PATH];
2470 	u16 dc_q[RTW89_DPK_RF_PATH];
2471 	u8 corr_val[RTW89_DPK_RF_PATH];
2472 	u8 corr_idx[RTW89_DPK_RF_PATH];
2473 	u8 cur_idx[RTW89_DPK_RF_PATH];
2474 	struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
2475 };
2476 
2477 struct rtw89_fem_info {
2478 	bool elna_2g;
2479 	bool elna_5g;
2480 	bool epa_2g;
2481 	bool epa_5g;
2482 };
2483 
2484 struct rtw89_phy_ch_info {
2485 	u8 rssi_min;
2486 	u16 rssi_min_macid;
2487 	u8 pre_rssi_min;
2488 	u8 rssi_max;
2489 	u16 rssi_max_macid;
2490 	u8 rxsc_160;
2491 	u8 rxsc_80;
2492 	u8 rxsc_40;
2493 	u8 rxsc_20;
2494 	u8 rxsc_l;
2495 	u8 is_noisy;
2496 };
2497 
2498 struct rtw89_agc_gaincode_set {
2499 	u8 lna_idx;
2500 	u8 tia_idx;
2501 	u8 rxb_idx;
2502 };
2503 
2504 #define IGI_RSSI_TH_NUM 5
2505 #define FA_TH_NUM 4
2506 #define LNA_GAIN_NUM 7
2507 #define TIA_GAIN_NUM 2
2508 struct rtw89_dig_info {
2509 	struct rtw89_agc_gaincode_set cur_gaincode;
2510 	bool force_gaincode_idx_en;
2511 	struct rtw89_agc_gaincode_set force_gaincode;
2512 	u8 igi_rssi_th[IGI_RSSI_TH_NUM];
2513 	u16 fa_th[FA_TH_NUM];
2514 	u8 igi_rssi;
2515 	u8 igi_fa_rssi;
2516 	u8 fa_rssi_ofst;
2517 	u8 dyn_igi_max;
2518 	u8 dyn_igi_min;
2519 	bool dyn_pd_th_en;
2520 	u8 dyn_pd_th_max;
2521 	u8 pd_low_th_ofst;
2522 	u8 ib_pbk;
2523 	s8 ib_pkpwr;
2524 	s8 lna_gain_a[LNA_GAIN_NUM];
2525 	s8 lna_gain_g[LNA_GAIN_NUM];
2526 	s8 *lna_gain;
2527 	s8 tia_gain_a[TIA_GAIN_NUM];
2528 	s8 tia_gain_g[TIA_GAIN_NUM];
2529 	s8 *tia_gain;
2530 	bool is_linked_pre;
2531 	bool bypass_dig;
2532 };
2533 
2534 enum rtw89_multi_cfo_mode {
2535 	RTW89_PKT_BASED_AVG_MODE = 0,
2536 	RTW89_ENTRY_BASED_AVG_MODE = 1,
2537 	RTW89_TP_BASED_AVG_MODE = 2,
2538 };
2539 
2540 enum rtw89_phy_cfo_status {
2541 	RTW89_PHY_DCFO_STATE_NORMAL = 0,
2542 	RTW89_PHY_DCFO_STATE_ENHANCE = 1,
2543 	RTW89_PHY_DCFO_STATE_MAX
2544 };
2545 
2546 struct rtw89_cfo_tracking_info {
2547 	u16 cfo_timer_ms;
2548 	bool cfo_trig_by_timer_en;
2549 	enum rtw89_phy_cfo_status phy_cfo_status;
2550 	u8 phy_cfo_trk_cnt;
2551 	bool is_adjust;
2552 	enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
2553 	bool apply_compensation;
2554 	u8 crystal_cap;
2555 	u8 crystal_cap_default;
2556 	u8 def_x_cap;
2557 	s8 x_cap_ofst;
2558 	u32 sta_cfo_tolerance;
2559 	s32 cfo_tail[CFO_TRACK_MAX_USER];
2560 	u16 cfo_cnt[CFO_TRACK_MAX_USER];
2561 	s32 cfo_avg_pre;
2562 	s32 cfo_avg[CFO_TRACK_MAX_USER];
2563 	s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
2564 	u32 packet_count;
2565 	u32 packet_count_pre;
2566 	s32 residual_cfo_acc;
2567 	u8 phy_cfotrk_state;
2568 	u8 phy_cfotrk_cnt;
2569 };
2570 
2571 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
2572 #define TSSI_TRIM_CH_GROUP_NUM 8
2573 
2574 #define TSSI_CCK_CH_GROUP_NUM 6
2575 #define TSSI_MCS_2G_CH_GROUP_NUM 5
2576 #define TSSI_MCS_5G_CH_GROUP_NUM 14
2577 #define TSSI_MCS_CH_GROUP_NUM \
2578 	(TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
2579 
2580 struct rtw89_tssi_info {
2581 	u8 thermal[RF_PATH_MAX];
2582 	s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
2583 	s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
2584 	s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
2585 	s8 extra_ofst[RF_PATH_MAX];
2586 	bool tssi_tracking_check[RF_PATH_MAX];
2587 	u8 default_txagc_offset[RF_PATH_MAX];
2588 	u32 base_thermal[RF_PATH_MAX];
2589 };
2590 
2591 struct rtw89_power_trim_info {
2592 	bool pg_thermal_trim;
2593 	bool pg_pa_bias_trim;
2594 	u8 thermal_trim[RF_PATH_MAX];
2595 	u8 pa_bias_trim[RF_PATH_MAX];
2596 };
2597 
2598 struct rtw89_regulatory {
2599 	char alpha2[3];
2600 	u8 txpwr_regd[RTW89_BAND_MAX];
2601 };
2602 
2603 enum rtw89_ifs_clm_application {
2604 	RTW89_IFS_CLM_INIT = 0,
2605 	RTW89_IFS_CLM_BACKGROUND = 1,
2606 	RTW89_IFS_CLM_ACS = 2,
2607 	RTW89_IFS_CLM_DIG = 3,
2608 	RTW89_IFS_CLM_TDMA_DIG = 4,
2609 	RTW89_IFS_CLM_DBG = 5,
2610 	RTW89_IFS_CLM_DBG_MANUAL = 6
2611 };
2612 
2613 enum rtw89_env_racing_lv {
2614 	RTW89_RAC_RELEASE = 0,
2615 	RTW89_RAC_LV_1 = 1,
2616 	RTW89_RAC_LV_2 = 2,
2617 	RTW89_RAC_LV_3 = 3,
2618 	RTW89_RAC_LV_4 = 4,
2619 	RTW89_RAC_MAX_NUM = 5
2620 };
2621 
2622 struct rtw89_ccx_para_info {
2623 	enum rtw89_env_racing_lv rac_lv;
2624 	u16 mntr_time;
2625 	u8 nhm_manual_th_ofst;
2626 	u8 nhm_manual_th0;
2627 	enum rtw89_ifs_clm_application ifs_clm_app;
2628 	u32 ifs_clm_manual_th_times;
2629 	u32 ifs_clm_manual_th0;
2630 	u8 fahm_manual_th_ofst;
2631 	u8 fahm_manual_th0;
2632 	u8 fahm_numer_opt;
2633 	u8 fahm_denom_opt;
2634 };
2635 
2636 enum rtw89_ccx_edcca_opt_sc_idx {
2637 	RTW89_CCX_EDCCA_SEG0_P0 = 0,
2638 	RTW89_CCX_EDCCA_SEG0_S1 = 1,
2639 	RTW89_CCX_EDCCA_SEG0_S2 = 2,
2640 	RTW89_CCX_EDCCA_SEG0_S3 = 3,
2641 	RTW89_CCX_EDCCA_SEG1_P0 = 4,
2642 	RTW89_CCX_EDCCA_SEG1_S1 = 5,
2643 	RTW89_CCX_EDCCA_SEG1_S2 = 6,
2644 	RTW89_CCX_EDCCA_SEG1_S3 = 7
2645 };
2646 
2647 enum rtw89_ccx_edcca_opt_bw_idx {
2648 	RTW89_CCX_EDCCA_BW20_0 = 0,
2649 	RTW89_CCX_EDCCA_BW20_1 = 1,
2650 	RTW89_CCX_EDCCA_BW20_2 = 2,
2651 	RTW89_CCX_EDCCA_BW20_3 = 3,
2652 	RTW89_CCX_EDCCA_BW20_4 = 4,
2653 	RTW89_CCX_EDCCA_BW20_5 = 5,
2654 	RTW89_CCX_EDCCA_BW20_6 = 6,
2655 	RTW89_CCX_EDCCA_BW20_7 = 7
2656 };
2657 
2658 #define RTW89_NHM_TH_NUM 11
2659 #define RTW89_FAHM_TH_NUM 11
2660 #define RTW89_NHM_RPT_NUM 12
2661 #define RTW89_FAHM_RPT_NUM 12
2662 #define RTW89_IFS_CLM_NUM 4
2663 struct rtw89_env_monitor_info {
2664 	u32 ccx_trigger_time;
2665 	u64 start_time;
2666 	u8 ccx_rpt_stamp;
2667 	u8 ccx_watchdog_result;
2668 	bool ccx_ongoing;
2669 	u8 ccx_rac_lv;
2670 	bool ccx_manual_ctrl;
2671 	u8 ccx_pre_rssi;
2672 	u16 clm_mntr_time;
2673 	u16 nhm_mntr_time;
2674 	u16 ifs_clm_mntr_time;
2675 	enum rtw89_ifs_clm_application ifs_clm_app;
2676 	u16 fahm_mntr_time;
2677 	u16 edcca_clm_mntr_time;
2678 	u16 ccx_period;
2679 	u8 ccx_unit_idx;
2680 	enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx;
2681 	u8 nhm_th[RTW89_NHM_TH_NUM];
2682 	u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
2683 	u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
2684 	u8 fahm_numer_opt;
2685 	u8 fahm_denom_opt;
2686 	u8 fahm_th[RTW89_FAHM_TH_NUM];
2687 	u16 clm_result;
2688 	u16 nhm_result[RTW89_NHM_RPT_NUM];
2689 	u8 nhm_wgt[RTW89_NHM_RPT_NUM];
2690 	u16 nhm_tx_cnt;
2691 	u16 nhm_cca_cnt;
2692 	u16 nhm_idle_cnt;
2693 	u16 ifs_clm_tx;
2694 	u16 ifs_clm_edcca_excl_cca;
2695 	u16 ifs_clm_ofdmfa;
2696 	u16 ifs_clm_ofdmcca_excl_fa;
2697 	u16 ifs_clm_cckfa;
2698 	u16 ifs_clm_cckcca_excl_fa;
2699 	u16 ifs_clm_total_ifs;
2700 	u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
2701 	u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
2702 	u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
2703 	u16 fahm_result[RTW89_FAHM_RPT_NUM];
2704 	u16 fahm_denom_result;
2705 	u16 edcca_clm_result;
2706 	u8 clm_ratio;
2707 	u8 nhm_rpt[RTW89_NHM_RPT_NUM];
2708 	u8 nhm_tx_ratio;
2709 	u8 nhm_cca_ratio;
2710 	u8 nhm_idle_ratio;
2711 	u8 nhm_ratio;
2712 	u16 nhm_result_sum;
2713 	u8 nhm_pwr;
2714 	u8 ifs_clm_tx_ratio;
2715 	u8 ifs_clm_edcca_excl_cca_ratio;
2716 	u8 ifs_clm_cck_fa_ratio;
2717 	u8 ifs_clm_ofdm_fa_ratio;
2718 	u8 ifs_clm_cck_cca_excl_fa_ratio;
2719 	u8 ifs_clm_ofdm_cca_excl_fa_ratio;
2720 	u16 ifs_clm_cck_fa_permil;
2721 	u16 ifs_clm_ofdm_fa_permil;
2722 	u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
2723 	u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
2724 	u8 fahm_rpt[RTW89_FAHM_RPT_NUM];
2725 	u16 fahm_result_sum;
2726 	u8 fahm_ratio;
2727 	u8 fahm_denom_ratio;
2728 	u8 fahm_pwr;
2729 	u8 edcca_clm_ratio;
2730 };
2731 
2732 enum rtw89_ser_rcvy_step {
2733 	RTW89_SER_DRV_STOP_TX,
2734 	RTW89_SER_DRV_STOP_RX,
2735 	RTW89_SER_DRV_STOP_RUN,
2736 	RTW89_SER_HAL_STOP_DMA,
2737 	RTW89_NUM_OF_SER_FLAGS
2738 };
2739 
2740 struct rtw89_ser {
2741 	u8 state;
2742 	u8 alarm_event;
2743 
2744 	struct work_struct ser_hdl_work;
2745 	struct delayed_work ser_alarm_work;
2746 	struct state_ent *st_tbl;
2747 	struct event_ent *ev_tbl;
2748 	struct list_head msg_q;
2749 	spinlock_t msg_q_lock; /* lock when read/write ser msg */
2750 	DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
2751 };
2752 
2753 enum rtw89_mac_ax_ps_mode {
2754 	RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
2755 	RTW89_MAC_AX_PS_MODE_LEGACY = 1,
2756 	RTW89_MAC_AX_PS_MODE_WMMPS  = 2,
2757 	RTW89_MAC_AX_PS_MODE_MAX    = 3,
2758 };
2759 
2760 enum rtw89_last_rpwm_mode {
2761 	RTW89_LAST_RPWM_PS        = 0x0,
2762 	RTW89_LAST_RPWM_ACTIVE    = 0x6,
2763 };
2764 
2765 struct rtw89_lps_parm {
2766 	u8 macid;
2767 	u8 psmode; /* enum rtw89_mac_ax_ps_mode */
2768 	u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
2769 };
2770 
2771 struct rtw89_ppdu_sts_info {
2772 	struct sk_buff_head rx_queue[RTW89_PHY_MAX];
2773 	u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
2774 };
2775 
2776 struct rtw89_early_h2c {
2777 	struct list_head list;
2778 	u8 *h2c;
2779 	u16 h2c_len;
2780 };
2781 
2782 struct rtw89_dev {
2783 	struct ieee80211_hw *hw;
2784 	struct device *dev;
2785 
2786 	bool dbcc_en;
2787 	const struct rtw89_chip_info *chip;
2788 	struct rtw89_hal hal;
2789 	struct rtw89_mac_info mac;
2790 	struct rtw89_fw_info fw;
2791 	struct rtw89_hci_info hci;
2792 	struct rtw89_efuse efuse;
2793 	struct rtw89_traffic_stats stats;
2794 
2795 	/* ensures exclusive access from mac80211 callbacks */
2796 	struct mutex mutex;
2797 	struct list_head rtwvifs_list;
2798 	/* used to protect rf read write */
2799 	struct mutex rf_mutex;
2800 	struct workqueue_struct *txq_wq;
2801 	struct work_struct txq_work;
2802 	struct delayed_work txq_reinvoke_work;
2803 	/* used to protect ba_list */
2804 	spinlock_t ba_lock;
2805 	/* txqs to setup ba session */
2806 	struct list_head ba_list;
2807 	struct work_struct ba_work;
2808 
2809 	struct rtw89_cam_info cam_info;
2810 
2811 	struct sk_buff_head c2h_queue;
2812 	struct work_struct c2h_work;
2813 
2814 	struct list_head early_h2c_list;
2815 
2816 	struct rtw89_ser ser;
2817 
2818 	DECLARE_BITMAP(hw_port, RTW89_MAX_HW_PORT_NUM);
2819 	DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
2820 	DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
2821 
2822 	struct rtw89_phy_stat phystat;
2823 	struct rtw89_dack_info dack;
2824 	struct rtw89_iqk_info iqk;
2825 	struct rtw89_dpk_info dpk;
2826 	bool is_tssi_mode[RF_PATH_MAX];
2827 	bool is_bt_iqk_timeout;
2828 
2829 	struct rtw89_fem_info fem;
2830 	struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX];
2831 	struct rtw89_tssi_info tssi;
2832 	struct rtw89_power_trim_info pwr_trim;
2833 
2834 	struct rtw89_cfo_tracking_info cfo_tracking;
2835 	struct rtw89_env_monitor_info env_monitor;
2836 	struct rtw89_dig_info dig;
2837 	struct rtw89_phy_ch_info ch_info;
2838 	struct delayed_work track_work;
2839 	struct delayed_work coex_act1_work;
2840 	struct delayed_work coex_bt_devinfo_work;
2841 	struct delayed_work coex_rfk_chk_work;
2842 	struct delayed_work cfo_track_work;
2843 	struct rtw89_ppdu_sts_info ppdu_sts;
2844 	u8 total_sta_assoc;
2845 	bool scanning;
2846 
2847 	const struct rtw89_regulatory *regd;
2848 	struct rtw89_sar_info sar;
2849 
2850 	struct rtw89_btc btc;
2851 	enum rtw89_ps_mode ps_mode;
2852 	bool lps_enabled;
2853 
2854 	/* napi structure */
2855 	struct net_device netdev;
2856 	struct napi_struct napi;
2857 	int napi_budget_countdown;
2858 
2859 	/* HCI related data, keep last */
2860 	u8 priv[0] __aligned(sizeof(void *));
2861 };
2862 
2863 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
2864 				     struct rtw89_core_tx_request *tx_req)
2865 {
2866 	return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
2867 }
2868 
2869 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
2870 {
2871 	rtwdev->hci.ops->reset(rtwdev);
2872 }
2873 
2874 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
2875 {
2876 	return rtwdev->hci.ops->start(rtwdev);
2877 }
2878 
2879 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
2880 {
2881 	rtwdev->hci.ops->stop(rtwdev);
2882 }
2883 
2884 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
2885 {
2886 	return rtwdev->hci.ops->deinit(rtwdev);
2887 }
2888 
2889 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
2890 {
2891 	rtwdev->hci.ops->recalc_int_mit(rtwdev);
2892 }
2893 
2894 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
2895 {
2896 	return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
2897 }
2898 
2899 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
2900 {
2901 	return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
2902 }
2903 
2904 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
2905 					  bool drop)
2906 {
2907 	if (rtwdev->hci.ops->flush_queues)
2908 		return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
2909 }
2910 
2911 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
2912 {
2913 	return rtwdev->hci.ops->read8(rtwdev, addr);
2914 }
2915 
2916 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
2917 {
2918 	return rtwdev->hci.ops->read16(rtwdev, addr);
2919 }
2920 
2921 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
2922 {
2923 	return rtwdev->hci.ops->read32(rtwdev, addr);
2924 }
2925 
2926 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
2927 {
2928 	rtwdev->hci.ops->write8(rtwdev, addr, data);
2929 }
2930 
2931 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
2932 {
2933 	rtwdev->hci.ops->write16(rtwdev, addr, data);
2934 }
2935 
2936 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
2937 {
2938 	rtwdev->hci.ops->write32(rtwdev, addr, data);
2939 }
2940 
2941 static inline void
2942 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
2943 {
2944 	u8 val;
2945 
2946 	val = rtw89_read8(rtwdev, addr);
2947 	rtw89_write8(rtwdev, addr, val | bit);
2948 }
2949 
2950 static inline void
2951 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
2952 {
2953 	u16 val;
2954 
2955 	val = rtw89_read16(rtwdev, addr);
2956 	rtw89_write16(rtwdev, addr, val | bit);
2957 }
2958 
2959 static inline void
2960 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
2961 {
2962 	u32 val;
2963 
2964 	val = rtw89_read32(rtwdev, addr);
2965 	rtw89_write32(rtwdev, addr, val | bit);
2966 }
2967 
2968 static inline void
2969 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
2970 {
2971 	u8 val;
2972 
2973 	val = rtw89_read8(rtwdev, addr);
2974 	rtw89_write8(rtwdev, addr, val & ~bit);
2975 }
2976 
2977 static inline void
2978 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
2979 {
2980 	u16 val;
2981 
2982 	val = rtw89_read16(rtwdev, addr);
2983 	rtw89_write16(rtwdev, addr, val & ~bit);
2984 }
2985 
2986 static inline void
2987 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
2988 {
2989 	u32 val;
2990 
2991 	val = rtw89_read32(rtwdev, addr);
2992 	rtw89_write32(rtwdev, addr, val & ~bit);
2993 }
2994 
2995 static inline u32
2996 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
2997 {
2998 	u32 shift = __ffs(mask);
2999 	u32 orig;
3000 	u32 ret;
3001 
3002 	orig = rtw89_read32(rtwdev, addr);
3003 	ret = (orig & mask) >> shift;
3004 
3005 	return ret;
3006 }
3007 
3008 static inline u16
3009 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3010 {
3011 	u32 shift = __ffs(mask);
3012 	u32 orig;
3013 	u32 ret;
3014 
3015 	orig = rtw89_read16(rtwdev, addr);
3016 	ret = (orig & mask) >> shift;
3017 
3018 	return ret;
3019 }
3020 
3021 static inline u8
3022 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
3023 {
3024 	u32 shift = __ffs(mask);
3025 	u32 orig;
3026 	u32 ret;
3027 
3028 	orig = rtw89_read8(rtwdev, addr);
3029 	ret = (orig & mask) >> shift;
3030 
3031 	return ret;
3032 }
3033 
3034 static inline void
3035 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
3036 {
3037 	u32 shift = __ffs(mask);
3038 	u32 orig;
3039 	u32 set;
3040 
3041 	WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
3042 
3043 	orig = rtw89_read32(rtwdev, addr);
3044 	set = (orig & ~mask) | ((data << shift) & mask);
3045 	rtw89_write32(rtwdev, addr, set);
3046 }
3047 
3048 static inline void
3049 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
3050 {
3051 	u32 shift;
3052 	u16 orig, set;
3053 
3054 	mask &= 0xffff;
3055 	shift = __ffs(mask);
3056 
3057 	orig = rtw89_read16(rtwdev, addr);
3058 	set = (orig & ~mask) | ((data << shift) & mask);
3059 	rtw89_write16(rtwdev, addr, set);
3060 }
3061 
3062 static inline void
3063 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
3064 {
3065 	u32 shift;
3066 	u8 orig, set;
3067 
3068 	mask &= 0xff;
3069 	shift = __ffs(mask);
3070 
3071 	orig = rtw89_read8(rtwdev, addr);
3072 	set = (orig & ~mask) | ((data << shift) & mask);
3073 	rtw89_write8(rtwdev, addr, set);
3074 }
3075 
3076 static inline u32
3077 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3078 	      u32 addr, u32 mask)
3079 {
3080 	u32 val;
3081 
3082 	mutex_lock(&rtwdev->rf_mutex);
3083 	val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
3084 	mutex_unlock(&rtwdev->rf_mutex);
3085 
3086 	return val;
3087 }
3088 
3089 static inline void
3090 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3091 	       u32 addr, u32 mask, u32 data)
3092 {
3093 	mutex_lock(&rtwdev->rf_mutex);
3094 	rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
3095 	mutex_unlock(&rtwdev->rf_mutex);
3096 }
3097 
3098 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
3099 {
3100 	void *p = rtwtxq;
3101 
3102 	return container_of(p, struct ieee80211_txq, drv_priv);
3103 }
3104 
3105 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
3106 				       struct ieee80211_txq *txq)
3107 {
3108 	struct rtw89_txq *rtwtxq;
3109 
3110 	if (!txq)
3111 		return;
3112 
3113 	rtwtxq = (struct rtw89_txq *)txq->drv_priv;
3114 	INIT_LIST_HEAD(&rtwtxq->list);
3115 }
3116 
3117 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
3118 {
3119 	void *p = rtwvif;
3120 
3121 	return container_of(p, struct ieee80211_vif, drv_priv);
3122 }
3123 
3124 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
3125 {
3126 	void *p = rtwsta;
3127 
3128 	return container_of(p, struct ieee80211_sta, drv_priv);
3129 }
3130 
3131 static inline
3132 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
3133 				    struct rtw89_channel_help_params *p)
3134 {
3135 	rtwdev->chip->ops->set_channel_help(rtwdev, true, p);
3136 }
3137 
3138 static inline
3139 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
3140 				 struct rtw89_channel_help_params *p)
3141 {
3142 	rtwdev->chip->ops->set_channel_help(rtwdev, false, p);
3143 }
3144 
3145 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
3146 {
3147 	const struct rtw89_chip_info *chip = rtwdev->chip;
3148 
3149 	if (chip->ops->fem_setup)
3150 		chip->ops->fem_setup(rtwdev);
3151 }
3152 
3153 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
3154 {
3155 	const struct rtw89_chip_info *chip = rtwdev->chip;
3156 
3157 	if (chip->ops->bb_sethw)
3158 		chip->ops->bb_sethw(rtwdev);
3159 }
3160 
3161 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
3162 {
3163 	const struct rtw89_chip_info *chip = rtwdev->chip;
3164 
3165 	if (chip->ops->rfk_init)
3166 		chip->ops->rfk_init(rtwdev);
3167 }
3168 
3169 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
3170 {
3171 	const struct rtw89_chip_info *chip = rtwdev->chip;
3172 
3173 	if (chip->ops->rfk_channel)
3174 		chip->ops->rfk_channel(rtwdev);
3175 }
3176 
3177 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev)
3178 {
3179 	const struct rtw89_chip_info *chip = rtwdev->chip;
3180 
3181 	if (chip->ops->rfk_band_changed)
3182 		chip->ops->rfk_band_changed(rtwdev);
3183 }
3184 
3185 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
3186 {
3187 	const struct rtw89_chip_info *chip = rtwdev->chip;
3188 
3189 	if (chip->ops->rfk_scan)
3190 		chip->ops->rfk_scan(rtwdev, start);
3191 }
3192 
3193 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
3194 {
3195 	const struct rtw89_chip_info *chip = rtwdev->chip;
3196 
3197 	if (chip->ops->rfk_track)
3198 		chip->ops->rfk_track(rtwdev);
3199 }
3200 
3201 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
3202 {
3203 	const struct rtw89_chip_info *chip = rtwdev->chip;
3204 
3205 	if (chip->ops->set_txpwr_ctrl)
3206 		chip->ops->set_txpwr_ctrl(rtwdev);
3207 }
3208 
3209 static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev)
3210 {
3211 	const struct rtw89_chip_info *chip = rtwdev->chip;
3212 	u8 ch = rtwdev->hal.current_channel;
3213 
3214 	if (!ch)
3215 		return;
3216 
3217 	if (chip->ops->set_txpwr)
3218 		chip->ops->set_txpwr(rtwdev);
3219 }
3220 
3221 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
3222 {
3223 	const struct rtw89_chip_info *chip = rtwdev->chip;
3224 
3225 	if (chip->ops->power_trim)
3226 		chip->ops->power_trim(rtwdev);
3227 }
3228 
3229 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
3230 					      enum rtw89_phy_idx phy_idx)
3231 {
3232 	const struct rtw89_chip_info *chip = rtwdev->chip;
3233 
3234 	if (chip->ops->init_txpwr_unit)
3235 		chip->ops->init_txpwr_unit(rtwdev, phy_idx);
3236 }
3237 
3238 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
3239 					enum rtw89_rf_path rf_path)
3240 {
3241 	const struct rtw89_chip_info *chip = rtwdev->chip;
3242 
3243 	if (!chip->ops->get_thermal)
3244 		return 0x10;
3245 
3246 	return chip->ops->get_thermal(rtwdev, rf_path);
3247 }
3248 
3249 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
3250 					 struct rtw89_rx_phy_ppdu *phy_ppdu,
3251 					 struct ieee80211_rx_status *status)
3252 {
3253 	const struct rtw89_chip_info *chip = rtwdev->chip;
3254 
3255 	if (chip->ops->query_ppdu)
3256 		chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
3257 }
3258 
3259 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev,
3260 						 bool bt_en)
3261 {
3262 	const struct rtw89_chip_info *chip = rtwdev->chip;
3263 
3264 	if (chip->ops->bb_ctrl_btc_preagc)
3265 		chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en);
3266 }
3267 
3268 static inline
3269 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
3270 				       struct ieee80211_vif *vif)
3271 {
3272 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3273 	const struct rtw89_chip_info *chip = rtwdev->chip;
3274 
3275 	if (!vif->bss_conf.he_support || !vif->bss_conf.assoc)
3276 		return;
3277 
3278 	if (chip->ops->set_txpwr_ul_tb_offset)
3279 		chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
3280 }
3281 
3282 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
3283 					  const struct rtw89_txpwr_table *tbl)
3284 {
3285 	tbl->load(rtwdev, tbl);
3286 }
3287 
3288 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
3289 {
3290 	return rtwdev->regd->txpwr_regd[band];
3291 }
3292 
3293 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg)
3294 {
3295 	const struct rtw89_chip_info *chip = rtwdev->chip;
3296 
3297 	if (chip->ops->ctrl_btg)
3298 		chip->ops->ctrl_btg(rtwdev, btg);
3299 }
3300 
3301 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
3302 {
3303 	__le16 fc = hdr->frame_control;
3304 
3305 	if (ieee80211_has_tods(fc))
3306 		return hdr->addr1;
3307 	else if (ieee80211_has_fromds(fc))
3308 		return hdr->addr2;
3309 	else
3310 		return hdr->addr3;
3311 }
3312 
3313 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
3314 {
3315 	if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
3316 	    (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
3317 	    (sta->he_cap.he_cap_elem.phy_cap_info[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
3318 	    (sta->he_cap.he_cap_elem.phy_cap_info[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
3319 		return true;
3320 	return false;
3321 }
3322 
3323 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
3324 						      enum rtw89_fw_type type)
3325 {
3326 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
3327 
3328 	if (type == RTW89_FW_WOWLAN)
3329 		return &fw_info->wowlan;
3330 	return &fw_info->normal;
3331 }
3332 
3333 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
3334 			struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
3335 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
3336 		 struct sk_buff *skb, bool fwdl);
3337 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
3338 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
3339 			    struct rtw89_tx_desc_info *desc_info,
3340 			    void *txdesc);
3341 void rtw89_core_rx(struct rtw89_dev *rtwdev,
3342 		   struct rtw89_rx_desc_info *desc_info,
3343 		   struct sk_buff *skb);
3344 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
3345 			     struct rtw89_rx_desc_info *desc_info,
3346 			     u8 *data, u32 data_offset);
3347 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
3348 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
3349 void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
3350 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
3351 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
3352 		       struct ieee80211_vif *vif,
3353 		       struct ieee80211_sta *sta);
3354 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
3355 			 struct ieee80211_vif *vif,
3356 			 struct ieee80211_sta *sta);
3357 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
3358 			    struct ieee80211_vif *vif,
3359 			    struct ieee80211_sta *sta);
3360 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
3361 			      struct ieee80211_vif *vif,
3362 			      struct ieee80211_sta *sta);
3363 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
3364 			  struct ieee80211_vif *vif,
3365 			  struct ieee80211_sta *sta);
3366 int rtw89_core_init(struct rtw89_dev *rtwdev);
3367 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
3368 int rtw89_core_register(struct rtw89_dev *rtwdev);
3369 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
3370 void rtw89_set_channel(struct rtw89_dev *rtwdev);
3371 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
3372 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
3373 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
3374 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
3375 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
3376 u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate);
3377 int rtw89_regd_init(struct rtw89_dev *rtwdev,
3378 		    void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
3379 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
3380 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
3381 			      struct rtw89_traffic_stats *stats);
3382 int rtw89_core_start(struct rtw89_dev *rtwdev);
3383 void rtw89_core_stop(struct rtw89_dev *rtwdev);
3384 
3385 #endif
3386