1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 18 extern const struct ieee80211_ops rtw89_ops; 19 20 #define MASKBYTE0 0xff 21 #define MASKBYTE1 0xff00 22 #define MASKBYTE2 0xff0000 23 #define MASKBYTE3 0xff000000 24 #define MASKBYTE4 0xff00000000ULL 25 #define MASKHWORD 0xffff0000 26 #define MASKLWORD 0x0000ffff 27 #define MASKDWORD 0xffffffff 28 #define RFREG_MASK 0xfffff 29 #define INV_RF_DATA 0xffffffff 30 31 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 32 #define CFO_TRACK_MAX_USER 64 33 #define MAX_RSSI 110 34 #define RSSI_FACTOR 1 35 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 36 37 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 38 #define RTW89_HTC_VARIANT_HE 3 39 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 40 #define RTW89_HTC_VARIANT_HE_CID_OM 1 41 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 42 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 43 44 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 45 enum htc_om_channel_width { 46 HTC_OM_CHANNEL_WIDTH_20 = 0, 47 HTC_OM_CHANNEL_WIDTH_40 = 1, 48 HTC_OM_CHANNEL_WIDTH_80 = 2, 49 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 50 }; 51 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 52 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 53 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 54 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 55 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 56 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 57 58 enum rtw89_subband { 59 RTW89_CH_2G = 0, 60 RTW89_CH_5G_BAND_1 = 1, 61 /* RTW89_CH_5G_BAND_2 = 2, unused */ 62 RTW89_CH_5G_BAND_3 = 3, 63 RTW89_CH_5G_BAND_4 = 4, 64 65 RTW89_CH_6G_BAND_IDX0, /* Low */ 66 RTW89_CH_6G_BAND_IDX1, /* Low */ 67 RTW89_CH_6G_BAND_IDX2, /* Mid */ 68 RTW89_CH_6G_BAND_IDX3, /* Mid */ 69 RTW89_CH_6G_BAND_IDX4, /* High */ 70 RTW89_CH_6G_BAND_IDX5, /* High */ 71 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 72 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 73 74 RTW89_SUBBAND_NR, 75 }; 76 77 enum rtw89_hci_type { 78 RTW89_HCI_TYPE_PCIE, 79 RTW89_HCI_TYPE_USB, 80 RTW89_HCI_TYPE_SDIO, 81 }; 82 83 enum rtw89_core_chip_id { 84 RTL8852A, 85 RTL8852B, 86 RTL8852C, 87 }; 88 89 enum rtw89_cv { 90 CHIP_CAV, 91 CHIP_CBV, 92 CHIP_CCV, 93 CHIP_CDV, 94 CHIP_CEV, 95 CHIP_CFV, 96 CHIP_CV_MAX, 97 CHIP_CV_INVALID = CHIP_CV_MAX, 98 }; 99 100 enum rtw89_core_tx_type { 101 RTW89_CORE_TX_TYPE_DATA, 102 RTW89_CORE_TX_TYPE_MGMT, 103 RTW89_CORE_TX_TYPE_FWCMD, 104 }; 105 106 enum rtw89_core_rx_type { 107 RTW89_CORE_RX_TYPE_WIFI = 0, 108 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 109 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 110 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 111 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 112 RTW89_CORE_RX_TYPE_SS2FW = 5, 113 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 114 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 115 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 116 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 117 RTW89_CORE_RX_TYPE_C2H = 10, 118 RTW89_CORE_RX_TYPE_CSI = 11, 119 RTW89_CORE_RX_TYPE_CQI = 12, 120 }; 121 122 enum rtw89_txq_flags { 123 RTW89_TXQ_F_AMPDU = 0, 124 RTW89_TXQ_F_BLOCK_BA = 1, 125 }; 126 127 enum rtw89_net_type { 128 RTW89_NET_TYPE_NO_LINK = 0, 129 RTW89_NET_TYPE_AD_HOC = 1, 130 RTW89_NET_TYPE_INFRA = 2, 131 RTW89_NET_TYPE_AP_MODE = 3, 132 }; 133 134 enum rtw89_wifi_role { 135 RTW89_WIFI_ROLE_NONE, 136 RTW89_WIFI_ROLE_STATION, 137 RTW89_WIFI_ROLE_AP, 138 RTW89_WIFI_ROLE_AP_VLAN, 139 RTW89_WIFI_ROLE_ADHOC, 140 RTW89_WIFI_ROLE_ADHOC_MASTER, 141 RTW89_WIFI_ROLE_MESH_POINT, 142 RTW89_WIFI_ROLE_MONITOR, 143 RTW89_WIFI_ROLE_P2P_DEVICE, 144 RTW89_WIFI_ROLE_P2P_CLIENT, 145 RTW89_WIFI_ROLE_P2P_GO, 146 RTW89_WIFI_ROLE_NAN, 147 RTW89_WIFI_ROLE_MLME_MAX 148 }; 149 150 enum rtw89_upd_mode { 151 RTW89_ROLE_CREATE, 152 RTW89_ROLE_REMOVE, 153 RTW89_ROLE_TYPE_CHANGE, 154 RTW89_ROLE_INFO_CHANGE, 155 RTW89_ROLE_CON_DISCONN 156 }; 157 158 enum rtw89_self_role { 159 RTW89_SELF_ROLE_CLIENT, 160 RTW89_SELF_ROLE_AP, 161 RTW89_SELF_ROLE_AP_CLIENT 162 }; 163 164 enum rtw89_msk_sO_el { 165 RTW89_NO_MSK, 166 RTW89_SMA, 167 RTW89_TMA, 168 RTW89_BSSID 169 }; 170 171 enum rtw89_sch_tx_sel { 172 RTW89_SCH_TX_SEL_ALL, 173 RTW89_SCH_TX_SEL_HIQ, 174 RTW89_SCH_TX_SEL_MG0, 175 RTW89_SCH_TX_SEL_MACID, 176 }; 177 178 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 179 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 180 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 181 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 182 */ 183 enum rtw89_add_cam_sec_mode { 184 RTW89_ADDR_CAM_SEC_NONE = 0, 185 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 186 RTW89_ADDR_CAM_SEC_NORMAL = 2, 187 RTW89_ADDR_CAM_SEC_4GROUP = 3, 188 }; 189 190 enum rtw89_sec_key_type { 191 RTW89_SEC_KEY_TYPE_NONE = 0, 192 RTW89_SEC_KEY_TYPE_WEP40 = 1, 193 RTW89_SEC_KEY_TYPE_WEP104 = 2, 194 RTW89_SEC_KEY_TYPE_TKIP = 3, 195 RTW89_SEC_KEY_TYPE_WAPI = 4, 196 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 197 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 198 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 199 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 200 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 201 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 202 }; 203 204 enum rtw89_port { 205 RTW89_PORT_0 = 0, 206 RTW89_PORT_1 = 1, 207 RTW89_PORT_2 = 2, 208 RTW89_PORT_3 = 3, 209 RTW89_PORT_4 = 4, 210 RTW89_PORT_NUM 211 }; 212 213 enum rtw89_band { 214 RTW89_BAND_2G = 0, 215 RTW89_BAND_5G = 1, 216 RTW89_BAND_6G = 2, 217 RTW89_BAND_MAX, 218 }; 219 220 enum rtw89_hw_rate { 221 RTW89_HW_RATE_CCK1 = 0x0, 222 RTW89_HW_RATE_CCK2 = 0x1, 223 RTW89_HW_RATE_CCK5_5 = 0x2, 224 RTW89_HW_RATE_CCK11 = 0x3, 225 RTW89_HW_RATE_OFDM6 = 0x4, 226 RTW89_HW_RATE_OFDM9 = 0x5, 227 RTW89_HW_RATE_OFDM12 = 0x6, 228 RTW89_HW_RATE_OFDM18 = 0x7, 229 RTW89_HW_RATE_OFDM24 = 0x8, 230 RTW89_HW_RATE_OFDM36 = 0x9, 231 RTW89_HW_RATE_OFDM48 = 0xA, 232 RTW89_HW_RATE_OFDM54 = 0xB, 233 RTW89_HW_RATE_MCS0 = 0x80, 234 RTW89_HW_RATE_MCS1 = 0x81, 235 RTW89_HW_RATE_MCS2 = 0x82, 236 RTW89_HW_RATE_MCS3 = 0x83, 237 RTW89_HW_RATE_MCS4 = 0x84, 238 RTW89_HW_RATE_MCS5 = 0x85, 239 RTW89_HW_RATE_MCS6 = 0x86, 240 RTW89_HW_RATE_MCS7 = 0x87, 241 RTW89_HW_RATE_MCS8 = 0x88, 242 RTW89_HW_RATE_MCS9 = 0x89, 243 RTW89_HW_RATE_MCS10 = 0x8A, 244 RTW89_HW_RATE_MCS11 = 0x8B, 245 RTW89_HW_RATE_MCS12 = 0x8C, 246 RTW89_HW_RATE_MCS13 = 0x8D, 247 RTW89_HW_RATE_MCS14 = 0x8E, 248 RTW89_HW_RATE_MCS15 = 0x8F, 249 RTW89_HW_RATE_MCS16 = 0x90, 250 RTW89_HW_RATE_MCS17 = 0x91, 251 RTW89_HW_RATE_MCS18 = 0x92, 252 RTW89_HW_RATE_MCS19 = 0x93, 253 RTW89_HW_RATE_MCS20 = 0x94, 254 RTW89_HW_RATE_MCS21 = 0x95, 255 RTW89_HW_RATE_MCS22 = 0x96, 256 RTW89_HW_RATE_MCS23 = 0x97, 257 RTW89_HW_RATE_MCS24 = 0x98, 258 RTW89_HW_RATE_MCS25 = 0x99, 259 RTW89_HW_RATE_MCS26 = 0x9A, 260 RTW89_HW_RATE_MCS27 = 0x9B, 261 RTW89_HW_RATE_MCS28 = 0x9C, 262 RTW89_HW_RATE_MCS29 = 0x9D, 263 RTW89_HW_RATE_MCS30 = 0x9E, 264 RTW89_HW_RATE_MCS31 = 0x9F, 265 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 266 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 267 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 268 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 269 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 270 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 271 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 272 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 273 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 274 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 275 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 276 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 277 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 278 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 279 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 280 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 281 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 282 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 283 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 284 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 285 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 286 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 287 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 288 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 289 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 290 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 291 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 292 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 293 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 294 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 295 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 296 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 297 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 298 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 299 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 300 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 301 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 302 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 303 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 304 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 305 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 306 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 307 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 308 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 309 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 310 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 311 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 312 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 313 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 314 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 315 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 316 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 317 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 318 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 319 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 320 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 321 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 322 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 323 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 324 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 325 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 326 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 327 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 328 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 329 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 330 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 331 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 332 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 333 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 334 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 335 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 336 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 337 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 338 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 339 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 340 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 341 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 342 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 343 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 344 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 345 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 346 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 347 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 348 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 349 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 350 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 351 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 352 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 353 RTW89_HW_RATE_NR, 354 355 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 356 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 357 }; 358 359 /* 2G channels, 360 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 361 */ 362 #define RTW89_2G_CH_NUM 14 363 364 /* 5G channels, 365 * 36, 38, 40, 42, 44, 46, 48, 50, 366 * 52, 54, 56, 58, 60, 62, 64, 367 * 100, 102, 104, 106, 108, 110, 112, 114, 368 * 116, 118, 120, 122, 124, 126, 128, 130, 369 * 132, 134, 136, 138, 140, 142, 144, 370 * 149, 151, 153, 155, 157, 159, 161, 163, 371 * 165, 167, 169, 171, 173, 175, 177 372 */ 373 #define RTW89_5G_CH_NUM 53 374 375 /* 6G channels, 376 * 1, 3, 5, 7, 9, 11, 13, 15, 377 * 17, 19, 21, 23, 25, 27, 29, 33, 378 * 35, 37, 39, 41, 43, 45, 47, 49, 379 * 51, 53, 55, 57, 59, 61, 65, 67, 380 * 69, 71, 73, 75, 77, 79, 81, 83, 381 * 85, 87, 89, 91, 93, 97, 99, 101, 382 * 103, 105, 107, 109, 111, 113, 115, 117, 383 * 119, 121, 123, 125, 129, 131, 133, 135, 384 * 137, 139, 141, 143, 145, 147, 149, 151, 385 * 153, 155, 157, 161, 163, 165, 167, 169, 386 * 171, 173, 175, 177, 179, 181, 183, 185, 387 * 187, 189, 193, 195, 197, 199, 201, 203, 388 * 205, 207, 209, 211, 213, 215, 217, 219, 389 * 221, 225, 227, 229, 231, 233, 235, 237, 390 * 239, 241, 243, 245, 247, 249, 251, 253, 391 */ 392 #define RTW89_6G_CH_NUM 120 393 394 enum rtw89_rate_section { 395 RTW89_RS_CCK, 396 RTW89_RS_OFDM, 397 RTW89_RS_MCS, /* for HT/VHT/HE */ 398 RTW89_RS_HEDCM, 399 RTW89_RS_OFFSET, 400 RTW89_RS_MAX, 401 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 402 }; 403 404 enum rtw89_rate_max { 405 RTW89_RATE_CCK_MAX = 4, 406 RTW89_RATE_OFDM_MAX = 8, 407 RTW89_RATE_MCS_MAX = 12, 408 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 409 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 410 }; 411 412 enum rtw89_nss { 413 RTW89_NSS_1 = 0, 414 RTW89_NSS_2 = 1, 415 /* HE DCM only support 1ss and 2ss */ 416 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 417 RTW89_NSS_3 = 2, 418 RTW89_NSS_4 = 3, 419 RTW89_NSS_MAX, 420 }; 421 422 enum rtw89_ntx { 423 RTW89_1TX = 0, 424 RTW89_2TX = 1, 425 RTW89_NTX_NUM, 426 }; 427 428 enum rtw89_beamforming_type { 429 RTW89_NONBF = 0, 430 RTW89_BF = 1, 431 RTW89_BF_NUM, 432 }; 433 434 enum rtw89_regulation_type { 435 RTW89_WW = 0, 436 RTW89_ETSI = 1, 437 RTW89_FCC = 2, 438 RTW89_MKK = 3, 439 RTW89_NA = 4, 440 RTW89_IC = 5, 441 RTW89_KCC = 6, 442 RTW89_ACMA = 7, 443 RTW89_NCC = 8, 444 RTW89_MEXICO = 9, 445 RTW89_CHILE = 10, 446 RTW89_UKRAINE = 11, 447 RTW89_CN = 12, 448 RTW89_QATAR = 13, 449 RTW89_REGD_NUM, 450 }; 451 452 struct rtw89_txpwr_byrate { 453 s8 cck[RTW89_RATE_CCK_MAX]; 454 s8 ofdm[RTW89_RATE_OFDM_MAX]; 455 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 456 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 457 s8 offset[RTW89_RATE_OFFSET_MAX]; 458 }; 459 460 enum rtw89_bandwidth_section_num { 461 RTW89_BW20_SEC_NUM = 8, 462 RTW89_BW40_SEC_NUM = 4, 463 RTW89_BW80_SEC_NUM = 2, 464 }; 465 466 struct rtw89_txpwr_limit { 467 s8 cck_20m[RTW89_BF_NUM]; 468 s8 cck_40m[RTW89_BF_NUM]; 469 s8 ofdm[RTW89_BF_NUM]; 470 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 471 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 472 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 473 s8 mcs_160m[RTW89_BF_NUM]; 474 s8 mcs_40m_0p5[RTW89_BF_NUM]; 475 s8 mcs_40m_2p5[RTW89_BF_NUM]; 476 }; 477 478 #define RTW89_RU_SEC_NUM 8 479 480 struct rtw89_txpwr_limit_ru { 481 s8 ru26[RTW89_RU_SEC_NUM]; 482 s8 ru52[RTW89_RU_SEC_NUM]; 483 s8 ru106[RTW89_RU_SEC_NUM]; 484 }; 485 486 struct rtw89_rate_desc { 487 enum rtw89_nss nss; 488 enum rtw89_rate_section rs; 489 u8 idx; 490 }; 491 492 #define PHY_STS_HDR_LEN 8 493 #define RF_PATH_MAX 4 494 #define RTW89_MAX_PPDU_CNT 8 495 struct rtw89_rx_phy_ppdu { 496 u8 *buf; 497 u32 len; 498 u8 rssi_avg; 499 s8 rssi[RF_PATH_MAX]; 500 u8 mac_id; 501 u8 chan_idx; 502 u8 ie; 503 u16 rate; 504 bool to_self; 505 bool valid; 506 }; 507 508 enum rtw89_mac_idx { 509 RTW89_MAC_0 = 0, 510 RTW89_MAC_1 = 1, 511 }; 512 513 enum rtw89_phy_idx { 514 RTW89_PHY_0 = 0, 515 RTW89_PHY_1 = 1, 516 RTW89_PHY_MAX 517 }; 518 519 enum rtw89_rf_path { 520 RF_PATH_A = 0, 521 RF_PATH_B = 1, 522 RF_PATH_C = 2, 523 RF_PATH_D = 3, 524 RF_PATH_AB, 525 RF_PATH_AC, 526 RF_PATH_AD, 527 RF_PATH_BC, 528 RF_PATH_BD, 529 RF_PATH_CD, 530 RF_PATH_ABC, 531 RF_PATH_ABD, 532 RF_PATH_ACD, 533 RF_PATH_BCD, 534 RF_PATH_ABCD, 535 }; 536 537 enum rtw89_rf_path_bit { 538 RF_A = BIT(0), 539 RF_B = BIT(1), 540 RF_C = BIT(2), 541 RF_D = BIT(3), 542 543 RF_AB = (RF_A | RF_B), 544 RF_AC = (RF_A | RF_C), 545 RF_AD = (RF_A | RF_D), 546 RF_BC = (RF_B | RF_C), 547 RF_BD = (RF_B | RF_D), 548 RF_CD = (RF_C | RF_D), 549 550 RF_ABC = (RF_A | RF_B | RF_C), 551 RF_ABD = (RF_A | RF_B | RF_D), 552 RF_ACD = (RF_A | RF_C | RF_D), 553 RF_BCD = (RF_B | RF_C | RF_D), 554 555 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 556 }; 557 558 enum rtw89_bandwidth { 559 RTW89_CHANNEL_WIDTH_20 = 0, 560 RTW89_CHANNEL_WIDTH_40 = 1, 561 RTW89_CHANNEL_WIDTH_80 = 2, 562 RTW89_CHANNEL_WIDTH_160 = 3, 563 RTW89_CHANNEL_WIDTH_80_80 = 4, 564 RTW89_CHANNEL_WIDTH_5 = 5, 565 RTW89_CHANNEL_WIDTH_10 = 6, 566 }; 567 568 enum rtw89_ps_mode { 569 RTW89_PS_MODE_NONE = 0, 570 RTW89_PS_MODE_RFOFF = 1, 571 RTW89_PS_MODE_CLK_GATED = 2, 572 RTW89_PS_MODE_PWR_GATED = 3, 573 }; 574 575 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 576 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 577 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 578 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1) 579 580 enum rtw89_ru_bandwidth { 581 RTW89_RU26 = 0, 582 RTW89_RU52 = 1, 583 RTW89_RU106 = 2, 584 RTW89_RU_NUM, 585 }; 586 587 enum rtw89_sc_offset { 588 RTW89_SC_DONT_CARE = 0, 589 RTW89_SC_20_UPPER = 1, 590 RTW89_SC_20_LOWER = 2, 591 RTW89_SC_20_UPMOST = 3, 592 RTW89_SC_20_LOWEST = 4, 593 RTW89_SC_20_UP2X = 5, 594 RTW89_SC_20_LOW2X = 6, 595 RTW89_SC_20_UP3X = 7, 596 RTW89_SC_20_LOW3X = 8, 597 RTW89_SC_40_UPPER = 9, 598 RTW89_SC_40_LOWER = 10, 599 }; 600 601 struct rtw89_channel_params { 602 u8 center_chan; 603 u32 center_freq; 604 u8 primary_chan; 605 u8 bandwidth; 606 u8 pri_ch_idx; 607 u8 band_type; 608 u8 subband_type; 609 }; 610 611 struct rtw89_channel_help_params { 612 u32 tx_en; 613 }; 614 615 struct rtw89_port_reg { 616 u32 port_cfg; 617 u32 tbtt_prohib; 618 u32 bcn_area; 619 u32 bcn_early; 620 u32 tbtt_early; 621 u32 tbtt_agg; 622 u32 bcn_space; 623 u32 bcn_forcetx; 624 u32 bcn_err_cnt; 625 u32 bcn_err_flag; 626 u32 dtim_ctrl; 627 u32 tbtt_shift; 628 u32 bcn_cnt_tmr; 629 u32 tsftr_l; 630 u32 tsftr_h; 631 }; 632 633 struct rtw89_txwd_body { 634 __le32 dword0; 635 __le32 dword1; 636 __le32 dword2; 637 __le32 dword3; 638 __le32 dword4; 639 __le32 dword5; 640 } __packed; 641 642 struct rtw89_txwd_info { 643 __le32 dword0; 644 __le32 dword1; 645 __le32 dword2; 646 __le32 dword3; 647 __le32 dword4; 648 __le32 dword5; 649 } __packed; 650 651 struct rtw89_rx_desc_info { 652 u16 pkt_size; 653 u8 pkt_type; 654 u8 drv_info_size; 655 u8 shift; 656 u8 wl_hd_iv_len; 657 bool long_rxdesc; 658 bool bb_sel; 659 bool mac_info_valid; 660 u16 data_rate; 661 u8 gi_ltf; 662 u8 bw; 663 u32 free_run_cnt; 664 u8 user_id; 665 bool sr_en; 666 u8 ppdu_cnt; 667 u8 ppdu_type; 668 bool icv_err; 669 bool crc32_err; 670 bool hw_dec; 671 bool sw_dec; 672 bool addr1_match; 673 u8 frag; 674 u16 seq; 675 u8 frame_type; 676 u8 rx_pl_id; 677 bool addr_cam_valid; 678 u8 addr_cam_id; 679 u8 sec_cam_id; 680 u8 mac_id; 681 u16 offset; 682 bool ready; 683 }; 684 685 struct rtw89_rxdesc_short { 686 __le32 dword0; 687 __le32 dword1; 688 __le32 dword2; 689 __le32 dword3; 690 } __packed; 691 692 struct rtw89_rxdesc_long { 693 __le32 dword0; 694 __le32 dword1; 695 __le32 dword2; 696 __le32 dword3; 697 __le32 dword4; 698 __le32 dword5; 699 __le32 dword6; 700 __le32 dword7; 701 } __packed; 702 703 struct rtw89_tx_desc_info { 704 u16 pkt_size; 705 u8 wp_offset; 706 u8 mac_id; 707 u8 qsel; 708 u8 ch_dma; 709 u8 hdr_llc_len; 710 bool is_bmc; 711 bool en_wd_info; 712 bool wd_page; 713 bool use_rate; 714 bool dis_data_fb; 715 bool tid_indicate; 716 bool agg_en; 717 bool bk; 718 u8 ampdu_density; 719 u8 ampdu_num; 720 bool sec_en; 721 u8 sec_type; 722 u8 sec_cam_idx; 723 u16 data_rate; 724 u16 data_retry_lowest_rate; 725 bool fw_dl; 726 u16 seq; 727 bool a_ctrl_bsr; 728 u8 hw_ssn_sel; 729 #define RTW89_MGMT_HW_SSN_SEL 1 730 u8 hw_seq_mode; 731 #define RTW89_MGMT_HW_SEQ_MODE 1 732 bool hiq; 733 u8 port; 734 }; 735 736 struct rtw89_core_tx_request { 737 enum rtw89_core_tx_type tx_type; 738 739 struct sk_buff *skb; 740 struct ieee80211_vif *vif; 741 struct ieee80211_sta *sta; 742 struct rtw89_tx_desc_info desc_info; 743 }; 744 745 struct rtw89_txq { 746 struct list_head list; 747 unsigned long flags; 748 int wait_cnt; 749 }; 750 751 struct rtw89_mac_ax_gnt { 752 u8 gnt_bt_sw_en; 753 u8 gnt_bt; 754 u8 gnt_wl_sw_en; 755 u8 gnt_wl; 756 }; 757 758 #define RTW89_MAC_AX_COEX_GNT_NR 2 759 struct rtw89_mac_ax_coex_gnt { 760 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 761 }; 762 763 enum rtw89_btc_ncnt { 764 BTC_NCNT_POWER_ON = 0x0, 765 BTC_NCNT_POWER_OFF, 766 BTC_NCNT_INIT_COEX, 767 BTC_NCNT_SCAN_START, 768 BTC_NCNT_SCAN_FINISH, 769 BTC_NCNT_SPECIAL_PACKET, 770 BTC_NCNT_SWITCH_BAND, 771 BTC_NCNT_RFK_TIMEOUT, 772 BTC_NCNT_SHOW_COEX_INFO, 773 BTC_NCNT_ROLE_INFO, 774 BTC_NCNT_CONTROL, 775 BTC_NCNT_RADIO_STATE, 776 BTC_NCNT_CUSTOMERIZE, 777 BTC_NCNT_WL_RFK, 778 BTC_NCNT_WL_STA, 779 BTC_NCNT_FWINFO, 780 BTC_NCNT_TIMER, 781 BTC_NCNT_NUM 782 }; 783 784 enum rtw89_btc_btinfo { 785 BTC_BTINFO_L0 = 0, 786 BTC_BTINFO_L1, 787 BTC_BTINFO_L2, 788 BTC_BTINFO_L3, 789 BTC_BTINFO_H0, 790 BTC_BTINFO_H1, 791 BTC_BTINFO_H2, 792 BTC_BTINFO_H3, 793 BTC_BTINFO_MAX 794 }; 795 796 enum rtw89_btc_dcnt { 797 BTC_DCNT_RUN = 0x0, 798 BTC_DCNT_CX_RUNINFO, 799 BTC_DCNT_RPT, 800 BTC_DCNT_RPT_FREEZE, 801 BTC_DCNT_CYCLE, 802 BTC_DCNT_CYCLE_FREEZE, 803 BTC_DCNT_W1, 804 BTC_DCNT_W1_FREEZE, 805 BTC_DCNT_B1, 806 BTC_DCNT_B1_FREEZE, 807 BTC_DCNT_TDMA_NONSYNC, 808 BTC_DCNT_SLOT_NONSYNC, 809 BTC_DCNT_BTCNT_FREEZE, 810 BTC_DCNT_WL_SLOT_DRIFT, 811 BTC_DCNT_WL_STA_LAST, 812 BTC_DCNT_NUM, 813 }; 814 815 enum rtw89_btc_wl_state_cnt { 816 BTC_WCNT_SCANAP = 0x0, 817 BTC_WCNT_DHCP, 818 BTC_WCNT_EAPOL, 819 BTC_WCNT_ARP, 820 BTC_WCNT_SCBDUPDATE, 821 BTC_WCNT_RFK_REQ, 822 BTC_WCNT_RFK_GO, 823 BTC_WCNT_RFK_REJECT, 824 BTC_WCNT_RFK_TIMEOUT, 825 BTC_WCNT_CH_UPDATE, 826 BTC_WCNT_NUM 827 }; 828 829 enum rtw89_btc_bt_state_cnt { 830 BTC_BCNT_RETRY = 0x0, 831 BTC_BCNT_REINIT, 832 BTC_BCNT_REENABLE, 833 BTC_BCNT_SCBDREAD, 834 BTC_BCNT_RELINK, 835 BTC_BCNT_IGNOWL, 836 BTC_BCNT_INQPAG, 837 BTC_BCNT_INQ, 838 BTC_BCNT_PAGE, 839 BTC_BCNT_ROLESW, 840 BTC_BCNT_AFH, 841 BTC_BCNT_INFOUPDATE, 842 BTC_BCNT_INFOSAME, 843 BTC_BCNT_SCBDUPDATE, 844 BTC_BCNT_HIPRI_TX, 845 BTC_BCNT_HIPRI_RX, 846 BTC_BCNT_LOPRI_TX, 847 BTC_BCNT_LOPRI_RX, 848 BTC_BCNT_POLUT, 849 BTC_BCNT_RATECHG, 850 BTC_BCNT_NUM 851 }; 852 853 enum rtw89_btc_bt_profile { 854 BTC_BT_NOPROFILE = 0, 855 BTC_BT_HFP = BIT(0), 856 BTC_BT_HID = BIT(1), 857 BTC_BT_A2DP = BIT(2), 858 BTC_BT_PAN = BIT(3), 859 BTC_PROFILE_MAX = 4, 860 }; 861 862 struct rtw89_btc_ant_info { 863 u8 type; /* shared, dedicated */ 864 u8 num; 865 u8 isolation; 866 867 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 868 u8 diversity: 1; 869 }; 870 871 enum rtw89_tfc_dir { 872 RTW89_TFC_UL, 873 RTW89_TFC_DL, 874 }; 875 876 struct rtw89_btc_wl_smap { 877 u32 busy: 1; 878 u32 scan: 1; 879 u32 connecting: 1; 880 u32 roaming: 1; 881 u32 _4way: 1; 882 u32 rf_off: 1; 883 u32 lps: 1; 884 u32 ips: 1; 885 u32 init_ok: 1; 886 u32 traffic_dir : 2; 887 u32 rf_off_pre: 1; 888 u32 lps_pre: 1; 889 }; 890 891 enum rtw89_tfc_lv { 892 RTW89_TFC_IDLE, 893 RTW89_TFC_ULTRA_LOW, 894 RTW89_TFC_LOW, 895 RTW89_TFC_MID, 896 RTW89_TFC_HIGH, 897 }; 898 899 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 900 DECLARE_EWMA(tp, 10, 2); 901 902 struct rtw89_traffic_stats { 903 /* units in bytes */ 904 u64 tx_unicast; 905 u64 rx_unicast; 906 u32 tx_avg_len; 907 u32 rx_avg_len; 908 909 /* count for packets */ 910 u64 tx_cnt; 911 u64 rx_cnt; 912 913 /* units in Mbps */ 914 u32 tx_throughput; 915 u32 rx_throughput; 916 u32 tx_throughput_raw; 917 u32 rx_throughput_raw; 918 enum rtw89_tfc_lv tx_tfc_lv; 919 enum rtw89_tfc_lv rx_tfc_lv; 920 struct ewma_tp tx_ewma_tp; 921 struct ewma_tp rx_ewma_tp; 922 923 u16 tx_rate; 924 u16 rx_rate; 925 }; 926 927 struct rtw89_btc_statistic { 928 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 929 struct rtw89_traffic_stats traffic; 930 }; 931 932 #define BTC_WL_RSSI_THMAX 4 933 934 struct rtw89_btc_wl_link_info { 935 struct rtw89_btc_statistic stat; 936 enum rtw89_tfc_dir dir; 937 u8 rssi_state[BTC_WL_RSSI_THMAX]; 938 u8 mac_addr[ETH_ALEN]; 939 u8 busy; 940 u8 ch; 941 u8 bw; 942 u8 band; 943 u8 role; 944 u8 pid; 945 u8 phy; 946 u8 dtim_period; 947 u8 mode; 948 949 u8 mac_id; 950 u8 tx_retry; 951 952 u32 bcn_period; 953 u32 busy_t; 954 u32 tx_time; 955 u32 client_cnt; 956 u32 rx_rate_drop_cnt; 957 958 u32 active: 1; 959 u32 noa: 1; 960 u32 client_ps: 1; 961 u32 connected: 2; 962 }; 963 964 union rtw89_btc_wl_state_map { 965 u32 val; 966 struct rtw89_btc_wl_smap map; 967 }; 968 969 struct rtw89_btc_bt_hfp_desc { 970 u32 exist: 1; 971 u32 type: 2; 972 u32 rsvd: 29; 973 }; 974 975 struct rtw89_btc_bt_hid_desc { 976 u32 exist: 1; 977 u32 slot_info: 2; 978 u32 pair_cnt: 2; 979 u32 type: 8; 980 u32 rsvd: 19; 981 }; 982 983 struct rtw89_btc_bt_a2dp_desc { 984 u8 exist: 1; 985 u8 exist_last: 1; 986 u8 play_latency: 1; 987 u8 type: 3; 988 u8 active: 1; 989 u8 sink: 1; 990 991 u8 bitpool; 992 u16 vendor_id; 993 u32 device_name; 994 u32 flush_time; 995 }; 996 997 struct rtw89_btc_bt_pan_desc { 998 u32 exist: 1; 999 u32 type: 1; 1000 u32 active: 1; 1001 u32 rsvd: 29; 1002 }; 1003 1004 struct rtw89_btc_bt_rfk_info { 1005 u32 run: 1; 1006 u32 req: 1; 1007 u32 timeout: 1; 1008 u32 rsvd: 29; 1009 }; 1010 1011 union rtw89_btc_bt_rfk_info_map { 1012 u32 val; 1013 struct rtw89_btc_bt_rfk_info map; 1014 }; 1015 1016 struct rtw89_btc_bt_ver_info { 1017 u32 fw_coex; /* match with which coex_ver */ 1018 u32 fw; 1019 }; 1020 1021 struct rtw89_btc_bool_sta_chg { 1022 u32 now: 1; 1023 u32 last: 1; 1024 u32 remain: 1; 1025 u32 srvd: 29; 1026 }; 1027 1028 struct rtw89_btc_u8_sta_chg { 1029 u8 now; 1030 u8 last; 1031 u8 remain; 1032 u8 rsvd; 1033 }; 1034 1035 struct rtw89_btc_wl_scan_info { 1036 u8 band[RTW89_PHY_MAX]; 1037 u8 phy_map; 1038 u8 rsvd; 1039 }; 1040 1041 struct rtw89_btc_wl_dbcc_info { 1042 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1043 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1044 u8 real_band[RTW89_PHY_MAX]; 1045 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1046 }; 1047 1048 struct rtw89_btc_wl_active_role { 1049 u8 connected: 1; 1050 u8 pid: 3; 1051 u8 phy: 1; 1052 u8 noa: 1; 1053 u8 band: 2; 1054 1055 u8 client_ps: 1; 1056 u8 bw: 7; 1057 1058 u8 role; 1059 u8 ch; 1060 1061 u16 tx_lvl; 1062 u16 rx_lvl; 1063 u16 tx_rate; 1064 u16 rx_rate; 1065 }; 1066 1067 struct rtw89_btc_wl_role_info_bpos { 1068 u16 none: 1; 1069 u16 station: 1; 1070 u16 ap: 1; 1071 u16 vap: 1; 1072 u16 adhoc: 1; 1073 u16 adhoc_master: 1; 1074 u16 mesh: 1; 1075 u16 moniter: 1; 1076 u16 p2p_device: 1; 1077 u16 p2p_gc: 1; 1078 u16 p2p_go: 1; 1079 u16 nan: 1; 1080 }; 1081 1082 union rtw89_btc_wl_role_info_map { 1083 u16 val; 1084 struct rtw89_btc_wl_role_info_bpos role; 1085 }; 1086 1087 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1088 u8 connect_cnt; 1089 u8 link_mode; 1090 union rtw89_btc_wl_role_info_map role_map; 1091 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1092 }; 1093 1094 struct rtw89_btc_wl_ver_info { 1095 u32 fw_coex; /* match with which coex_ver */ 1096 u32 fw; 1097 u32 mac; 1098 u32 bb; 1099 u32 rf; 1100 }; 1101 1102 struct rtw89_btc_wl_afh_info { 1103 u8 en; 1104 u8 ch; 1105 u8 bw; 1106 u8 rsvd; 1107 } __packed; 1108 1109 struct rtw89_btc_wl_rfk_info { 1110 u32 state: 2; 1111 u32 path_map: 4; 1112 u32 phy_map: 2; 1113 u32 band: 2; 1114 u32 type: 8; 1115 u32 rsvd: 14; 1116 }; 1117 1118 struct rtw89_btc_bt_smap { 1119 u32 connect: 1; 1120 u32 ble_connect: 1; 1121 u32 acl_busy: 1; 1122 u32 sco_busy: 1; 1123 u32 mesh_busy: 1; 1124 u32 inq_pag: 1; 1125 }; 1126 1127 union rtw89_btc_bt_state_map { 1128 u32 val; 1129 struct rtw89_btc_bt_smap map; 1130 }; 1131 1132 #define BTC_BT_RSSI_THMAX 4 1133 #define BTC_BT_AFH_GROUP 12 1134 1135 struct rtw89_btc_bt_link_info { 1136 struct rtw89_btc_u8_sta_chg profile_cnt; 1137 struct rtw89_btc_bool_sta_chg multi_link; 1138 struct rtw89_btc_bool_sta_chg relink; 1139 struct rtw89_btc_bt_hfp_desc hfp_desc; 1140 struct rtw89_btc_bt_hid_desc hid_desc; 1141 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1142 struct rtw89_btc_bt_pan_desc pan_desc; 1143 union rtw89_btc_bt_state_map status; 1144 1145 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1146 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1147 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1148 u8 afh_map[BTC_BT_AFH_GROUP]; 1149 1150 u32 role_sw: 1; 1151 u32 slave_role: 1; 1152 u32 afh_update: 1; 1153 u32 cqddr: 1; 1154 u32 rssi: 8; 1155 u32 tx_3m: 1; 1156 u32 rsvd: 19; 1157 }; 1158 1159 struct rtw89_btc_3rdcx_info { 1160 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1161 u8 hw_coex; 1162 u16 rsvd; 1163 }; 1164 1165 struct rtw89_btc_dm_emap { 1166 u32 init: 1; 1167 u32 pta_owner: 1; 1168 u32 wl_rfk_timeout: 1; 1169 u32 bt_rfk_timeout: 1; 1170 1171 u32 wl_fw_hang: 1; 1172 u32 offload_mismatch: 1; 1173 u32 cycle_hang: 1; 1174 u32 w1_hang: 1; 1175 1176 u32 b1_hang: 1; 1177 u32 tdma_no_sync: 1; 1178 u32 wl_slot_drift: 1; 1179 }; 1180 1181 union rtw89_btc_dm_error_map { 1182 u32 val; 1183 struct rtw89_btc_dm_emap map; 1184 }; 1185 1186 struct rtw89_btc_rf_para { 1187 u32 tx_pwr_freerun; 1188 u32 rx_gain_freerun; 1189 u32 tx_pwr_perpkt; 1190 u32 rx_gain_perpkt; 1191 }; 1192 1193 struct rtw89_btc_wl_info { 1194 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1195 struct rtw89_btc_wl_rfk_info rfk_info; 1196 struct rtw89_btc_wl_ver_info ver_info; 1197 struct rtw89_btc_wl_afh_info afh_info; 1198 struct rtw89_btc_wl_role_info role_info; 1199 struct rtw89_btc_wl_scan_info scan_info; 1200 struct rtw89_btc_wl_dbcc_info dbcc_info; 1201 struct rtw89_btc_rf_para rf_para; 1202 union rtw89_btc_wl_state_map status; 1203 1204 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1205 u8 rssi_level; 1206 1207 u32 scbd; 1208 }; 1209 1210 struct rtw89_btc_module { 1211 struct rtw89_btc_ant_info ant; 1212 u8 rfe_type; 1213 u8 cv; 1214 1215 u8 bt_solo: 1; 1216 u8 bt_pos: 1; 1217 u8 switch_type: 1; 1218 1219 u8 rsvd; 1220 }; 1221 1222 #define RTW89_BTC_DM_MAXSTEP 30 1223 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1224 1225 struct rtw89_btc_dm_step { 1226 u16 step[RTW89_BTC_DM_MAXSTEP]; 1227 u8 step_pos; 1228 bool step_ov; 1229 }; 1230 1231 struct rtw89_btc_init_info { 1232 struct rtw89_btc_module module; 1233 u8 wl_guard_ch; 1234 1235 u8 wl_only: 1; 1236 u8 wl_init_ok: 1; 1237 u8 dbcc_en: 1; 1238 u8 cx_other: 1; 1239 u8 bt_only: 1; 1240 1241 u16 rsvd; 1242 }; 1243 1244 struct rtw89_btc_wl_tx_limit_para { 1245 u16 enable; 1246 u32 tx_time; /* unit: us */ 1247 u16 tx_retry; 1248 }; 1249 1250 struct rtw89_btc_bt_scan_info { 1251 u16 win; 1252 u16 intvl; 1253 u32 enable: 1; 1254 u32 interlace: 1; 1255 u32 rsvd: 30; 1256 }; 1257 1258 enum rtw89_btc_bt_scan_type { 1259 BTC_SCAN_INQ = 0, 1260 BTC_SCAN_PAGE, 1261 BTC_SCAN_BLE, 1262 BTC_SCAN_INIT, 1263 BTC_SCAN_TV, 1264 BTC_SCAN_ADV, 1265 BTC_SCAN_MAX1, 1266 }; 1267 1268 struct rtw89_btc_bt_info { 1269 struct rtw89_btc_bt_link_info link_info; 1270 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1271 struct rtw89_btc_bt_ver_info ver_info; 1272 struct rtw89_btc_bool_sta_chg enable; 1273 struct rtw89_btc_bool_sta_chg inq_pag; 1274 struct rtw89_btc_rf_para rf_para; 1275 union rtw89_btc_bt_rfk_info_map rfk_info; 1276 1277 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1278 1279 u32 scbd; 1280 u32 feature; 1281 1282 u32 mbx_avl: 1; 1283 u32 whql_test: 1; 1284 u32 igno_wl: 1; 1285 u32 reinit: 1; 1286 u32 ble_scan_en: 1; 1287 u32 btg_type: 1; 1288 u32 inq: 1; 1289 u32 pag: 1; 1290 u32 run_patch_code: 1; 1291 u32 hi_lna_rx: 1; 1292 u32 rsvd: 22; 1293 }; 1294 1295 struct rtw89_btc_cx { 1296 struct rtw89_btc_wl_info wl; 1297 struct rtw89_btc_bt_info bt; 1298 struct rtw89_btc_3rdcx_info other; 1299 u32 state_map; 1300 u32 cnt_bt[BTC_BCNT_NUM]; 1301 u32 cnt_wl[BTC_WCNT_NUM]; 1302 }; 1303 1304 struct rtw89_btc_fbtc_tdma { 1305 u8 type; 1306 u8 rxflctrl; 1307 u8 txpause; 1308 u8 wtgle_n; 1309 u8 leak_n; 1310 u8 ext_ctrl; 1311 u8 rsvd0; 1312 u8 rsvd1; 1313 } __packed; 1314 1315 #define CXMREG_MAX 30 1316 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1317 #define BTCRPT_VER 1 1318 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1319 1320 enum rtw89_btc_bt_rfk_counter { 1321 BTC_BCNT_RFK_REQ = 0, 1322 BTC_BCNT_RFK_GO = 1, 1323 BTC_BCNT_RFK_REJECT = 2, 1324 BTC_BCNT_RFK_FAIL = 3, 1325 BTC_BCNT_RFK_TIMEOUT = 4, 1326 BTC_BCNT_RFK_MAX 1327 }; 1328 1329 struct rtw89_btc_fbtc_rpt_ctrl { 1330 u16 fver; 1331 u16 rpt_cnt; /* tmr counters */ 1332 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1333 u32 wl_fw_cx_offload; 1334 u32 wl_fw_ver; 1335 u32 rpt_enable; 1336 u32 rpt_para; /* ms */ 1337 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1338 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1339 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1340 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1341 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1342 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1343 u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX]; 1344 u32 c2h_cnt; /* fw send c2h counter */ 1345 u32 h2c_cnt; /* fw recv h2c counter */ 1346 } __packed; 1347 1348 enum rtw89_fbtc_ext_ctrl_type { 1349 CXECTL_OFF = 0x0, /* tdma off */ 1350 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1351 CXECTL_EXT = 0x2, 1352 CXECTL_MAX 1353 }; 1354 1355 union rtw89_btc_fbtc_rxflct { 1356 u8 val; 1357 u8 type: 3; 1358 u8 tgln_n: 5; 1359 }; 1360 1361 enum rtw89_btc_cxst_state { 1362 CXST_OFF = 0x0, 1363 CXST_B2W = 0x1, 1364 CXST_W1 = 0x2, 1365 CXST_W2 = 0x3, 1366 CXST_W2B = 0x4, 1367 CXST_B1 = 0x5, 1368 CXST_B2 = 0x6, 1369 CXST_B3 = 0x7, 1370 CXST_B4 = 0x8, 1371 CXST_LK = 0x9, 1372 CXST_BLK = 0xa, 1373 CXST_E2G = 0xb, 1374 CXST_E5G = 0xc, 1375 CXST_EBT = 0xd, 1376 CXST_ENULL = 0xe, 1377 CXST_WLK = 0xf, 1378 CXST_W1FDD = 0x10, 1379 CXST_B1FDD = 0x11, 1380 CXST_MAX = 0x12, 1381 }; 1382 1383 enum { 1384 CXBCN_ALL = 0x0, 1385 CXBCN_ALL_OK, 1386 CXBCN_BT_SLOT, 1387 CXBCN_BT_OK, 1388 CXBCN_MAX 1389 }; 1390 1391 enum btc_slot_type { 1392 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1393 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1394 CXSTYPE_NUM, 1395 }; 1396 1397 enum { /* TIME */ 1398 CXT_BT = 0x0, 1399 CXT_WL = 0x1, 1400 CXT_MAX 1401 }; 1402 1403 enum { /* TIME-A2DP */ 1404 CXT_FLCTRL_OFF = 0x0, 1405 CXT_FLCTRL_ON = 0x1, 1406 CXT_FLCTRL_MAX 1407 }; 1408 1409 enum { /* STEP TYPE */ 1410 CXSTEP_NONE = 0x0, 1411 CXSTEP_EVNT = 0x1, 1412 CXSTEP_SLOT = 0x2, 1413 CXSTEP_MAX, 1414 }; 1415 1416 #define FCXGPIODBG_VER 1 1417 #define BTC_DBG_MAX1 32 1418 struct rtw89_btc_fbtc_gpio_dbg { 1419 u8 fver; 1420 u8 rsvd; 1421 u16 rsvd2; 1422 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1423 u32 pre_state; /* the debug signal is 1 or 0 */ 1424 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1425 } __packed; 1426 1427 #define FCXMREG_VER 1 1428 struct rtw89_btc_fbtc_mreg_val { 1429 u8 fver; 1430 u8 reg_num; 1431 __le16 rsvd; 1432 __le32 mreg_val[CXMREG_MAX]; 1433 } __packed; 1434 1435 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1436 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1437 .offset = cpu_to_le32(__offset), } 1438 1439 struct rtw89_btc_fbtc_mreg { 1440 __le16 type; 1441 __le16 bytes; 1442 __le32 offset; 1443 } __packed; 1444 1445 struct rtw89_btc_fbtc_slot { 1446 __le16 dur; 1447 __le32 cxtbl; 1448 __le16 cxtype; 1449 } __packed; 1450 1451 #define FCXSLOTS_VER 1 1452 struct rtw89_btc_fbtc_slots { 1453 u8 fver; 1454 u8 tbl_num; 1455 __le16 rsvd; 1456 __le32 update_map; 1457 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1458 } __packed; 1459 1460 #define FCXSTEP_VER 2 1461 struct rtw89_btc_fbtc_step { 1462 u8 type; 1463 u8 val; 1464 __le16 difft; 1465 } __packed; 1466 1467 struct rtw89_btc_fbtc_steps { 1468 u8 fver; 1469 u8 rsvd; 1470 __le16 cnt; 1471 __le16 pos_old; 1472 __le16 pos_new; 1473 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1474 } __packed; 1475 1476 #define FCXCYSTA_VER 2 1477 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ 1478 u8 fver; 1479 u8 rsvd; 1480 __le16 cycles; /* total cycle number */ 1481 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1482 __le16 a2dpept; /* a2dp empty cnt */ 1483 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1484 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1485 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1486 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1487 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1488 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1489 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1490 __le16 tmax_a2dpept; /* max a2dp empty time */ 1491 __le16 tavg_lk; /* avg leak-slot time */ 1492 __le16 tmax_lk; /* max leak-slot time */ 1493 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1494 __le32 bcn_cnt[CXBCN_MAX]; 1495 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1496 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1497 __le32 skip_cnt; 1498 __le32 exception; 1499 __le32 except_cnt; 1500 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1501 } __packed; 1502 1503 #define FCXNULLSTA_VER 1 1504 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ 1505 u8 fver; 1506 u8 rsvd; 1507 __le16 rsvd2; 1508 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1509 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1510 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1511 } __packed; 1512 1513 #define FCX_BTVER_VER 1 1514 struct rtw89_btc_fbtc_btver { 1515 u8 fver; 1516 u8 rsvd; 1517 __le16 rsvd2; 1518 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1519 __le32 fw_ver; 1520 __le32 feature; 1521 } __packed; 1522 1523 #define FCX_BTSCAN_VER 1 1524 struct rtw89_btc_fbtc_btscan { 1525 u8 fver; 1526 u8 rsvd; 1527 __le16 rsvd2; 1528 u8 scan[6]; 1529 } __packed; 1530 1531 #define FCX_BTAFH_VER 1 1532 struct rtw89_btc_fbtc_btafh { 1533 u8 fver; 1534 u8 rsvd; 1535 __le16 rsvd2; 1536 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1537 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1538 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1539 } __packed; 1540 1541 #define FCX_BTDEVINFO_VER 1 1542 struct rtw89_btc_fbtc_btdevinfo { 1543 u8 fver; 1544 u8 rsvd; 1545 __le16 vendor_id; 1546 __le32 dev_name; /* only 24 bits valid */ 1547 __le32 flush_time; 1548 } __packed; 1549 1550 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1551 struct rtw89_btc_rf_trx_para { 1552 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1553 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1554 u8 bt_tx_power; /* decrease Tx power (dB) */ 1555 u8 bt_rx_gain; /* LNA constrain level */ 1556 }; 1557 1558 struct rtw89_btc_dm { 1559 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1560 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1561 struct rtw89_btc_fbtc_tdma tdma; 1562 struct rtw89_btc_fbtc_tdma tdma_now; 1563 struct rtw89_mac_ax_coex_gnt gnt; 1564 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1565 struct rtw89_btc_rf_trx_para rf_trx_para; 1566 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1567 struct rtw89_btc_dm_step dm_step; 1568 union rtw89_btc_dm_error_map error; 1569 u32 cnt_dm[BTC_DCNT_NUM]; 1570 u32 cnt_notify[BTC_NCNT_NUM]; 1571 1572 u32 update_slot_map; 1573 u32 set_ant_path; 1574 1575 u32 wl_only: 1; 1576 u32 wl_fw_cx_offload: 1; 1577 u32 freerun: 1; 1578 u32 wl_ps_ctrl: 2; 1579 u32 wl_mimo_ps: 1; 1580 u32 leak_ap: 1; 1581 u32 noisy_level: 3; 1582 u32 coex_info_map: 8; 1583 u32 bt_only: 1; 1584 u32 wl_btg_rx: 1; 1585 u32 trx_para_level: 8; 1586 u32 wl_stb_chg: 1; 1587 u32 rsvd: 3; 1588 1589 u16 slot_dur[CXST_MAX]; 1590 1591 u8 run_reason; 1592 u8 run_action; 1593 }; 1594 1595 struct rtw89_btc_ctrl { 1596 u32 manual: 1; 1597 u32 igno_bt: 1; 1598 u32 always_freerun: 1; 1599 u32 trace_step: 16; 1600 u32 rsvd: 12; 1601 }; 1602 1603 struct rtw89_btc_dbg { 1604 /* cmd "rb" */ 1605 bool rb_done; 1606 u32 rb_val; 1607 }; 1608 1609 #define FCXTDMA_VER 1 1610 1611 enum rtw89_btc_btf_fw_event { 1612 BTF_EVNT_RPT = 0, 1613 BTF_EVNT_BT_INFO = 1, 1614 BTF_EVNT_BT_SCBD = 2, 1615 BTF_EVNT_BT_REG = 3, 1616 BTF_EVNT_CX_RUNINFO = 4, 1617 BTF_EVNT_BT_PSD = 5, 1618 BTF_EVNT_BUF_OVERFLOW, 1619 BTF_EVNT_C2H_LOOPBACK, 1620 BTF_EVNT_MAX, 1621 }; 1622 1623 enum btf_fw_event_report { 1624 BTC_RPT_TYPE_CTRL = 0x0, 1625 BTC_RPT_TYPE_TDMA, 1626 BTC_RPT_TYPE_SLOT, 1627 BTC_RPT_TYPE_CYSTA, 1628 BTC_RPT_TYPE_STEP, 1629 BTC_RPT_TYPE_NULLSTA, 1630 BTC_RPT_TYPE_MREG, 1631 BTC_RPT_TYPE_GPIO_DBG, 1632 BTC_RPT_TYPE_BT_VER, 1633 BTC_RPT_TYPE_BT_SCAN, 1634 BTC_RPT_TYPE_BT_AFH, 1635 BTC_RPT_TYPE_BT_DEVICE, 1636 BTC_RPT_TYPE_TEST, 1637 BTC_RPT_TYPE_MAX = 31 1638 }; 1639 1640 enum rtw_btc_btf_reg_type { 1641 REG_MAC = 0x0, 1642 REG_BB = 0x1, 1643 REG_RF = 0x2, 1644 REG_BT_RF = 0x3, 1645 REG_BT_MODEM = 0x4, 1646 REG_BT_BLUEWIZE = 0x5, 1647 REG_BT_VENDOR = 0x6, 1648 REG_BT_LE = 0x7, 1649 REG_MAX_TYPE, 1650 }; 1651 1652 struct rtw89_btc_rpt_cmn_info { 1653 u32 rx_cnt; 1654 u32 rx_len; 1655 u32 req_len; /* expected rsp len */ 1656 u8 req_fver; /* expected rsp fver */ 1657 u8 rsp_fver; /* fver from fw */ 1658 u8 valid; 1659 } __packed; 1660 1661 struct rtw89_btc_report_ctrl_state { 1662 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1663 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */ 1664 }; 1665 1666 struct rtw89_btc_rpt_fbtc_tdma { 1667 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1668 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ 1669 }; 1670 1671 struct rtw89_btc_rpt_fbtc_slots { 1672 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1673 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 1674 }; 1675 1676 struct rtw89_btc_rpt_fbtc_cysta { 1677 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1678 struct rtw89_btc_fbtc_cysta finfo; /* info from fw */ 1679 }; 1680 1681 struct rtw89_btc_rpt_fbtc_step { 1682 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1683 struct rtw89_btc_fbtc_steps finfo; /* info from fw */ 1684 }; 1685 1686 struct rtw89_btc_rpt_fbtc_nullsta { 1687 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1688 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ 1689 }; 1690 1691 struct rtw89_btc_rpt_fbtc_mreg { 1692 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1693 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 1694 }; 1695 1696 struct rtw89_btc_rpt_fbtc_gpio_dbg { 1697 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1698 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 1699 }; 1700 1701 struct rtw89_btc_rpt_fbtc_btver { 1702 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1703 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 1704 }; 1705 1706 struct rtw89_btc_rpt_fbtc_btscan { 1707 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1708 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 1709 }; 1710 1711 struct rtw89_btc_rpt_fbtc_btafh { 1712 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1713 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ 1714 }; 1715 1716 struct rtw89_btc_rpt_fbtc_btdev { 1717 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1718 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 1719 }; 1720 1721 enum rtw89_btc_btfre_type { 1722 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 1723 BTFRE_UNDEF_TYPE, 1724 BTFRE_EXCEPTION, 1725 BTFRE_MAX, 1726 }; 1727 1728 struct rtw89_btc_btf_fwinfo { 1729 u32 cnt_c2h; 1730 u32 cnt_h2c; 1731 u32 cnt_h2c_fail; 1732 u32 event[BTF_EVNT_MAX]; 1733 1734 u32 err[BTFRE_MAX]; 1735 u32 len_mismch; 1736 u32 fver_mismch; 1737 u32 rpt_en_map; 1738 1739 struct rtw89_btc_report_ctrl_state rpt_ctrl; 1740 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 1741 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 1742 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 1743 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 1744 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 1745 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 1746 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 1747 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 1748 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 1749 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 1750 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 1751 }; 1752 1753 #define RTW89_BTC_POLICY_MAXLEN 512 1754 1755 struct rtw89_btc { 1756 struct rtw89_btc_cx cx; 1757 struct rtw89_btc_dm dm; 1758 struct rtw89_btc_ctrl ctrl; 1759 struct rtw89_btc_module mdinfo; 1760 struct rtw89_btc_btf_fwinfo fwinfo; 1761 struct rtw89_btc_dbg dbg; 1762 1763 struct work_struct eapol_notify_work; 1764 struct work_struct arp_notify_work; 1765 struct work_struct dhcp_notify_work; 1766 struct work_struct icmp_notify_work; 1767 1768 u32 bt_req_len; 1769 1770 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 1771 u16 policy_len; 1772 u16 policy_type; 1773 bool bt_req_en; 1774 bool update_policy_force; 1775 bool lps; 1776 }; 1777 1778 enum rtw89_ra_mode { 1779 RTW89_RA_MODE_CCK = BIT(0), 1780 RTW89_RA_MODE_OFDM = BIT(1), 1781 RTW89_RA_MODE_HT = BIT(2), 1782 RTW89_RA_MODE_VHT = BIT(3), 1783 RTW89_RA_MODE_HE = BIT(4), 1784 }; 1785 1786 enum rtw89_ra_report_mode { 1787 RTW89_RA_RPT_MODE_LEGACY, 1788 RTW89_RA_RPT_MODE_HT, 1789 RTW89_RA_RPT_MODE_VHT, 1790 RTW89_RA_RPT_MODE_HE, 1791 }; 1792 1793 enum rtw89_dig_noisy_level { 1794 RTW89_DIG_NOISY_LEVEL0 = -1, 1795 RTW89_DIG_NOISY_LEVEL1 = 0, 1796 RTW89_DIG_NOISY_LEVEL2 = 1, 1797 RTW89_DIG_NOISY_LEVEL3 = 2, 1798 RTW89_DIG_NOISY_LEVEL_MAX = 3, 1799 }; 1800 1801 enum rtw89_gi_ltf { 1802 RTW89_GILTF_LGI_4XHE32 = 0, 1803 RTW89_GILTF_SGI_4XHE08 = 1, 1804 RTW89_GILTF_2XHE16 = 2, 1805 RTW89_GILTF_2XHE08 = 3, 1806 RTW89_GILTF_1XHE16 = 4, 1807 RTW89_GILTF_1XHE08 = 5, 1808 RTW89_GILTF_MAX 1809 }; 1810 1811 enum rtw89_rx_frame_type { 1812 RTW89_RX_TYPE_MGNT = 0, 1813 RTW89_RX_TYPE_CTRL = 1, 1814 RTW89_RX_TYPE_DATA = 2, 1815 RTW89_RX_TYPE_RSVD = 3, 1816 }; 1817 1818 struct rtw89_ra_info { 1819 u8 is_dis_ra:1; 1820 /* Bit0 : CCK 1821 * Bit1 : OFDM 1822 * Bit2 : HT 1823 * Bit3 : VHT 1824 * Bit4 : HE 1825 */ 1826 u8 mode_ctrl:5; 1827 u8 bw_cap:2; 1828 u8 macid; 1829 u8 dcm_cap:1; 1830 u8 er_cap:1; 1831 u8 init_rate_lv:2; 1832 u8 upd_all:1; 1833 u8 en_sgi:1; 1834 u8 ldpc_cap:1; 1835 u8 stbc_cap:1; 1836 u8 ss_num:3; 1837 u8 giltf:3; 1838 u8 upd_bw_nss_mask:1; 1839 u8 upd_mask:1; 1840 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 1841 /* BFee CSI */ 1842 u8 band_num; 1843 u8 ra_csi_rate_en:1; 1844 u8 fixed_csi_rate_en:1; 1845 u8 cr_tbl_sel:1; 1846 u8 rsvd2:5; 1847 u8 csi_mcs_ss_idx; 1848 u8 csi_mode:2; 1849 u8 csi_gi_ltf:3; 1850 u8 csi_bw:3; 1851 }; 1852 1853 #define RTW89_PPDU_MAX_USR 4 1854 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 1855 #define RTW89_PPDU_MAC_INFO_SIZE 8 1856 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 1857 1858 #define RTW89_MAX_RX_AGG_NUM 64 1859 #define RTW89_MAX_TX_AGG_NUM 128 1860 1861 struct rtw89_ampdu_params { 1862 u16 agg_num; 1863 bool amsdu; 1864 }; 1865 1866 struct rtw89_ra_report { 1867 struct rate_info txrate; 1868 u32 bit_rate; 1869 u16 hw_rate; 1870 }; 1871 1872 DECLARE_EWMA(rssi, 10, 16); 1873 1874 #define RTW89_BA_CAM_NUM 2 1875 1876 struct rtw89_ba_cam_entry { 1877 u8 tid; 1878 }; 1879 1880 #define RTW89_MAX_ADDR_CAM_NUM 128 1881 #define RTW89_MAX_BSSID_CAM_NUM 20 1882 #define RTW89_MAX_SEC_CAM_NUM 128 1883 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 1884 1885 struct rtw89_addr_cam_entry { 1886 u8 addr_cam_idx; 1887 u8 offset; 1888 u8 len; 1889 u8 valid : 1; 1890 u8 addr_mask : 6; 1891 u8 wapi : 1; 1892 u8 mask_sel : 2; 1893 u8 bssid_cam_idx: 6; 1894 1895 u8 sec_ent_mode; 1896 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 1897 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 1898 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 1899 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 1900 }; 1901 1902 struct rtw89_bssid_cam_entry { 1903 u8 bssid[ETH_ALEN]; 1904 u8 phy_idx; 1905 u8 bssid_cam_idx; 1906 u8 offset; 1907 u8 len; 1908 u8 valid : 1; 1909 u8 num; 1910 }; 1911 1912 struct rtw89_sec_cam_entry { 1913 u8 sec_cam_idx; 1914 u8 offset; 1915 u8 len; 1916 u8 type : 4; 1917 u8 ext_key : 1; 1918 u8 spp_mode : 1; 1919 /* 256 bits */ 1920 u8 key[32]; 1921 }; 1922 1923 struct rtw89_sta { 1924 u8 mac_id; 1925 bool disassoc; 1926 struct rtw89_vif *rtwvif; 1927 struct rtw89_ra_info ra; 1928 struct rtw89_ra_report ra_report; 1929 int max_agg_wait; 1930 u8 prev_rssi; 1931 struct ewma_rssi avg_rssi; 1932 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 1933 struct ieee80211_rx_status rx_status; 1934 u16 rx_hw_rate; 1935 __le32 htc_template; 1936 struct rtw89_addr_cam_entry addr_cam; /* AP mode only */ 1937 1938 bool use_cfg_mask; 1939 struct cfg80211_bitrate_mask mask; 1940 1941 bool cctl_tx_time; 1942 u32 ampdu_max_time:4; 1943 bool cctl_tx_retry_limit; 1944 u32 data_tx_cnt_lmt:6; 1945 1946 DECLARE_BITMAP(ba_cam_map, RTW89_BA_CAM_NUM); 1947 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_BA_CAM_NUM]; 1948 }; 1949 1950 struct rtw89_efuse { 1951 bool valid; 1952 u8 xtal_cap; 1953 u8 addr[ETH_ALEN]; 1954 u8 rfe_type; 1955 char country_code[2]; 1956 }; 1957 1958 struct rtw89_phy_rate_pattern { 1959 u64 ra_mask; 1960 u16 rate; 1961 u8 ra_mode; 1962 bool enable; 1963 }; 1964 1965 struct rtw89_vif { 1966 struct list_head list; 1967 struct rtw89_dev *rtwdev; 1968 u8 mac_id; 1969 u8 port; 1970 u8 mac_addr[ETH_ALEN]; 1971 u8 bssid[ETH_ALEN]; 1972 u8 phy_idx; 1973 u8 mac_idx; 1974 u8 net_type; 1975 u8 wifi_role; 1976 u8 self_role; 1977 u8 wmm; 1978 u8 bcn_hit_cond; 1979 u8 hit_rule; 1980 bool trigger; 1981 bool lsig_txop; 1982 u8 tgt_ind; 1983 u8 frm_tgt_ind; 1984 bool wowlan_pattern; 1985 bool wowlan_uc; 1986 bool wowlan_magic; 1987 bool is_hesta; 1988 bool last_a_ctrl; 1989 struct work_struct update_beacon_work; 1990 struct rtw89_addr_cam_entry addr_cam; 1991 struct rtw89_bssid_cam_entry bssid_cam; 1992 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 1993 struct rtw89_traffic_stats stats; 1994 struct rtw89_phy_rate_pattern rate_pattern; 1995 struct cfg80211_scan_request *scan_req; 1996 struct ieee80211_scan_ies *scan_ies; 1997 }; 1998 1999 enum rtw89_lv1_rcvy_step { 2000 RTW89_LV1_RCVY_STEP_1, 2001 RTW89_LV1_RCVY_STEP_2, 2002 }; 2003 2004 struct rtw89_hci_ops { 2005 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 2006 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 2007 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 2008 void (*reset)(struct rtw89_dev *rtwdev); 2009 int (*start)(struct rtw89_dev *rtwdev); 2010 void (*stop)(struct rtw89_dev *rtwdev); 2011 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 2012 2013 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 2014 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 2015 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 2016 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 2017 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 2018 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 2019 2020 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 2021 int (*mac_post_init)(struct rtw89_dev *rtwdev); 2022 int (*deinit)(struct rtw89_dev *rtwdev); 2023 2024 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 2025 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 2026 void (*dump_err_status)(struct rtw89_dev *rtwdev); 2027 int (*napi_poll)(struct napi_struct *napi, int budget); 2028 }; 2029 2030 struct rtw89_hci_info { 2031 const struct rtw89_hci_ops *ops; 2032 enum rtw89_hci_type type; 2033 u32 rpwm_addr; 2034 u32 cpwm_addr; 2035 }; 2036 2037 struct rtw89_chip_ops { 2038 void (*bb_reset)(struct rtw89_dev *rtwdev, 2039 enum rtw89_phy_idx phy_idx); 2040 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2041 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2042 u32 addr, u32 mask); 2043 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2044 u32 addr, u32 mask, u32 data); 2045 void (*set_channel)(struct rtw89_dev *rtwdev, 2046 struct rtw89_channel_params *param); 2047 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2048 struct rtw89_channel_help_params *p); 2049 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2050 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2051 void (*fem_setup)(struct rtw89_dev *rtwdev); 2052 void (*rfk_init)(struct rtw89_dev *rtwdev); 2053 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2054 void (*rfk_band_changed)(struct rtw89_dev *rtwdev); 2055 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2056 void (*rfk_track)(struct rtw89_dev *rtwdev); 2057 void (*power_trim)(struct rtw89_dev *rtwdev); 2058 void (*set_txpwr)(struct rtw89_dev *rtwdev); 2059 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev); 2060 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2061 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2062 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2063 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2064 struct rtw89_rx_phy_ppdu *phy_ppdu, 2065 struct ieee80211_rx_status *status); 2066 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2067 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2068 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 2069 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 2070 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 2071 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 2072 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 2073 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 2074 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 2075 u32 *tx_en, enum rtw89_sch_tx_sel sel); 2076 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 2077 2078 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2079 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2080 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2081 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2082 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2083 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); 2084 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2085 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2086 }; 2087 2088 enum rtw89_dma_ch { 2089 RTW89_DMA_ACH0 = 0, 2090 RTW89_DMA_ACH1 = 1, 2091 RTW89_DMA_ACH2 = 2, 2092 RTW89_DMA_ACH3 = 3, 2093 RTW89_DMA_ACH4 = 4, 2094 RTW89_DMA_ACH5 = 5, 2095 RTW89_DMA_ACH6 = 6, 2096 RTW89_DMA_ACH7 = 7, 2097 RTW89_DMA_B0MG = 8, 2098 RTW89_DMA_B0HI = 9, 2099 RTW89_DMA_B1MG = 10, 2100 RTW89_DMA_B1HI = 11, 2101 RTW89_DMA_H2C = 12, 2102 RTW89_DMA_CH_NUM = 13 2103 }; 2104 2105 enum rtw89_qta_mode { 2106 RTW89_QTA_SCC, 2107 RTW89_QTA_DLFW, 2108 2109 /* keep last */ 2110 RTW89_QTA_INVALID, 2111 }; 2112 2113 struct rtw89_hfc_ch_cfg { 2114 u16 min; 2115 u16 max; 2116 #define grp_0 0 2117 #define grp_1 1 2118 #define grp_num 2 2119 u8 grp; 2120 }; 2121 2122 struct rtw89_hfc_ch_info { 2123 u16 aval; 2124 u16 used; 2125 }; 2126 2127 struct rtw89_hfc_pub_cfg { 2128 u16 grp0; 2129 u16 grp1; 2130 u16 pub_max; 2131 u16 wp_thrd; 2132 }; 2133 2134 struct rtw89_hfc_pub_info { 2135 u16 g0_used; 2136 u16 g1_used; 2137 u16 g0_aval; 2138 u16 g1_aval; 2139 u16 pub_aval; 2140 u16 wp_aval; 2141 }; 2142 2143 struct rtw89_hfc_prec_cfg { 2144 u16 ch011_prec; 2145 u16 h2c_prec; 2146 u16 wp_ch07_prec; 2147 u16 wp_ch811_prec; 2148 u8 ch011_full_cond; 2149 u8 h2c_full_cond; 2150 u8 wp_ch07_full_cond; 2151 u8 wp_ch811_full_cond; 2152 }; 2153 2154 struct rtw89_hfc_param { 2155 bool en; 2156 bool h2c_en; 2157 u8 mode; 2158 const struct rtw89_hfc_ch_cfg *ch_cfg; 2159 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2160 struct rtw89_hfc_pub_cfg pub_cfg; 2161 struct rtw89_hfc_pub_info pub_info; 2162 struct rtw89_hfc_prec_cfg prec_cfg; 2163 }; 2164 2165 struct rtw89_hfc_param_ini { 2166 const struct rtw89_hfc_ch_cfg *ch_cfg; 2167 const struct rtw89_hfc_pub_cfg *pub_cfg; 2168 const struct rtw89_hfc_prec_cfg *prec_cfg; 2169 u8 mode; 2170 }; 2171 2172 struct rtw89_dle_size { 2173 u16 pge_size; 2174 u16 lnk_pge_num; 2175 u16 unlnk_pge_num; 2176 }; 2177 2178 struct rtw89_wde_quota { 2179 u16 hif; 2180 u16 wcpu; 2181 u16 pkt_in; 2182 u16 cpu_io; 2183 }; 2184 2185 struct rtw89_ple_quota { 2186 u16 cma0_tx; 2187 u16 cma1_tx; 2188 u16 c2h; 2189 u16 h2c; 2190 u16 wcpu; 2191 u16 mpdu_proc; 2192 u16 cma0_dma; 2193 u16 cma1_dma; 2194 u16 bb_rpt; 2195 u16 wd_rel; 2196 u16 cpu_io; 2197 u16 tx_rpt; 2198 }; 2199 2200 struct rtw89_dle_mem { 2201 enum rtw89_qta_mode mode; 2202 const struct rtw89_dle_size *wde_size; 2203 const struct rtw89_dle_size *ple_size; 2204 const struct rtw89_wde_quota *wde_min_qt; 2205 const struct rtw89_wde_quota *wde_max_qt; 2206 const struct rtw89_ple_quota *ple_min_qt; 2207 const struct rtw89_ple_quota *ple_max_qt; 2208 }; 2209 2210 struct rtw89_reg_def { 2211 u32 addr; 2212 u32 mask; 2213 }; 2214 2215 struct rtw89_reg2_def { 2216 u32 addr; 2217 u32 data; 2218 }; 2219 2220 struct rtw89_reg3_def { 2221 u32 addr; 2222 u32 mask; 2223 u32 data; 2224 }; 2225 2226 struct rtw89_reg5_def { 2227 u8 flag; /* recognized by parsers */ 2228 u8 path; 2229 u32 addr; 2230 u32 mask; 2231 u32 data; 2232 }; 2233 2234 struct rtw89_phy_table { 2235 const struct rtw89_reg2_def *regs; 2236 u32 n_regs; 2237 enum rtw89_rf_path rf_path; 2238 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 2239 enum rtw89_rf_path rf_path, void *data); 2240 }; 2241 2242 struct rtw89_txpwr_table { 2243 const void *data; 2244 u32 size; 2245 void (*load)(struct rtw89_dev *rtwdev, 2246 const struct rtw89_txpwr_table *tbl); 2247 }; 2248 2249 struct rtw89_page_regs { 2250 u32 hci_fc_ctrl; 2251 u32 ch_page_ctrl; 2252 u32 ach_page_ctrl; 2253 u32 ach_page_info; 2254 u32 pub_page_info3; 2255 u32 pub_page_ctrl1; 2256 u32 pub_page_ctrl2; 2257 u32 pub_page_info1; 2258 u32 pub_page_info2; 2259 u32 wp_page_ctrl1; 2260 u32 wp_page_ctrl2; 2261 u32 wp_page_info1; 2262 }; 2263 2264 struct rtw89_chip_info { 2265 enum rtw89_core_chip_id chip_id; 2266 const struct rtw89_chip_ops *ops; 2267 const char *fw_name; 2268 u32 fifo_size; 2269 u16 max_amsdu_limit; 2270 bool dis_2g_40m_ul_ofdma; 2271 const struct rtw89_hfc_param_ini *hfc_param_ini; 2272 const struct rtw89_dle_mem *dle_mem; 2273 u32 rf_base_addr[2]; 2274 u8 support_bands; 2275 bool support_bw160; 2276 u8 rf_path_num; 2277 u8 tx_nss; 2278 u8 rx_nss; 2279 u8 acam_num; 2280 u8 bcam_num; 2281 u8 scam_num; 2282 2283 u8 sec_ctrl_efuse_size; 2284 u32 physical_efuse_size; 2285 u32 logical_efuse_size; 2286 u32 limit_efuse_size; 2287 u32 dav_phy_efuse_size; 2288 u32 dav_log_efuse_size; 2289 u32 phycap_addr; 2290 u32 phycap_size; 2291 2292 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2293 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2294 const struct rtw89_phy_table *bb_table; 2295 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2296 const struct rtw89_phy_table *nctl_table; 2297 const struct rtw89_txpwr_table *byr_table; 2298 const struct rtw89_phy_dig_gain_table *dig_table; 2299 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2300 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2301 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2302 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2303 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2304 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2305 const s8 (*txpwr_lmt_6g)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 2306 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2307 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2308 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2309 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2310 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2311 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2312 const s8 (*txpwr_lmt_ru_6g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2313 [RTW89_REGD_NUM][RTW89_6G_CH_NUM]; 2314 2315 u8 txpwr_factor_rf; 2316 u8 txpwr_factor_mac; 2317 2318 u32 para_ver; 2319 u32 wlcx_desired; 2320 u8 btcx_desired; 2321 u8 scbd; 2322 u8 mailbox; 2323 2324 u8 afh_guard_ch; 2325 const u8 *wl_rssi_thres; 2326 const u8 *bt_rssi_thres; 2327 u8 rssi_tol; 2328 2329 u8 mon_reg_num; 2330 const struct rtw89_btc_fbtc_mreg *mon_reg; 2331 u8 rf_para_ulink_num; 2332 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2333 u8 rf_para_dlink_num; 2334 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2335 u8 ps_mode_supported; 2336 2337 u32 hci_func_en_addr; 2338 u32 h2c_ctrl_reg; 2339 const u32 *h2c_regs; 2340 u32 c2h_ctrl_reg; 2341 const u32 *c2h_regs; 2342 const struct rtw89_page_regs *page_regs; 2343 const struct rtw89_reg_def *dcfo_comp; 2344 u8 dcfo_comp_sft; 2345 }; 2346 2347 union rtw89_bus_info { 2348 const struct rtw89_pci_info *pci; 2349 }; 2350 2351 struct rtw89_driver_info { 2352 const struct rtw89_chip_info *chip; 2353 union rtw89_bus_info bus; 2354 }; 2355 2356 enum rtw89_hcifc_mode { 2357 RTW89_HCIFC_POH = 0, 2358 RTW89_HCIFC_STF = 1, 2359 RTW89_HCIFC_SDIO = 2, 2360 2361 /* keep last */ 2362 RTW89_HCIFC_MODE_INVALID, 2363 }; 2364 2365 struct rtw89_dle_info { 2366 enum rtw89_qta_mode qta_mode; 2367 u16 wde_pg_size; 2368 u16 ple_pg_size; 2369 u16 c0_rx_qta; 2370 u16 c1_rx_qta; 2371 }; 2372 2373 enum rtw89_host_rpr_mode { 2374 RTW89_RPR_MODE_POH = 0, 2375 RTW89_RPR_MODE_STF 2376 }; 2377 2378 struct rtw89_mac_info { 2379 struct rtw89_dle_info dle_info; 2380 struct rtw89_hfc_param hfc_param; 2381 enum rtw89_qta_mode qta_mode; 2382 u8 rpwm_seq_num; 2383 u8 cpwm_seq_num; 2384 }; 2385 2386 enum rtw89_fw_type { 2387 RTW89_FW_NORMAL = 1, 2388 RTW89_FW_WOWLAN = 3, 2389 }; 2390 2391 struct rtw89_fw_suit { 2392 const u8 *data; 2393 u32 size; 2394 u8 major_ver; 2395 u8 minor_ver; 2396 u8 sub_ver; 2397 u8 sub_idex; 2398 u16 build_year; 2399 u16 build_mon; 2400 u16 build_date; 2401 u16 build_hour; 2402 u16 build_min; 2403 u8 cmd_ver; 2404 }; 2405 2406 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 2407 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 2408 #define RTW89_FW_SUIT_VER_CODE(s) \ 2409 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 2410 2411 struct rtw89_fw_info { 2412 const struct firmware *firmware; 2413 struct rtw89_dev *rtwdev; 2414 struct completion completion; 2415 u8 h2c_seq; 2416 u8 rec_seq; 2417 struct rtw89_fw_suit normal; 2418 struct rtw89_fw_suit wowlan; 2419 bool fw_log_enable; 2420 bool old_ht_ra_format; 2421 bool scan_offload; 2422 bool tx_wake; 2423 }; 2424 2425 struct rtw89_cam_info { 2426 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 2427 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 2428 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 2429 }; 2430 2431 enum rtw89_sar_sources { 2432 RTW89_SAR_SOURCE_NONE, 2433 RTW89_SAR_SOURCE_COMMON, 2434 2435 RTW89_SAR_SOURCE_NR, 2436 }; 2437 2438 struct rtw89_sar_cfg_common { 2439 bool set[RTW89_SUBBAND_NR]; 2440 s32 cfg[RTW89_SUBBAND_NR]; 2441 }; 2442 2443 struct rtw89_sar_info { 2444 /* used to decide how to acces SAR cfg union */ 2445 enum rtw89_sar_sources src; 2446 2447 /* reserved for different knids of SAR cfg struct. 2448 * supposed that a single cfg struct cannot handle various SAR sources. 2449 */ 2450 union { 2451 struct rtw89_sar_cfg_common cfg_common; 2452 }; 2453 }; 2454 2455 struct rtw89_hal { 2456 u32 rx_fltr; 2457 u8 cv; 2458 u8 current_channel; 2459 u32 current_freq; 2460 u8 prev_primary_channel; 2461 u8 current_primary_channel; 2462 enum rtw89_subband current_subband; 2463 u8 current_band_width; 2464 u8 prev_band_type; 2465 u8 current_band_type; 2466 u32 sw_amsdu_max_size; 2467 u32 antenna_tx; 2468 u32 antenna_rx; 2469 u8 tx_nss; 2470 u8 rx_nss; 2471 bool support_cckpd; 2472 }; 2473 2474 #define RTW89_MAX_MAC_ID_NUM 128 2475 #define RTW89_MAX_PKT_OFLD_NUM 255 2476 2477 enum rtw89_flags { 2478 RTW89_FLAG_POWERON, 2479 RTW89_FLAG_FW_RDY, 2480 RTW89_FLAG_RUNNING, 2481 RTW89_FLAG_BFEE_MON, 2482 RTW89_FLAG_BFEE_EN, 2483 RTW89_FLAG_NAPI_RUNNING, 2484 RTW89_FLAG_LEISURE_PS, 2485 RTW89_FLAG_LOW_POWER_MODE, 2486 RTW89_FLAG_INACTIVE_PS, 2487 2488 NUM_OF_RTW89_FLAGS, 2489 }; 2490 2491 struct rtw89_pkt_stat { 2492 u16 beacon_nr; 2493 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 2494 }; 2495 2496 DECLARE_EWMA(thermal, 4, 4); 2497 2498 struct rtw89_phy_stat { 2499 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 2500 struct rtw89_pkt_stat cur_pkt_stat; 2501 struct rtw89_pkt_stat last_pkt_stat; 2502 }; 2503 2504 #define RTW89_DACK_PATH_NR 2 2505 #define RTW89_DACK_IDX_NR 2 2506 #define RTW89_DACK_MSBK_NR 16 2507 struct rtw89_dack_info { 2508 bool dack_done; 2509 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 2510 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2511 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2512 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2513 u32 dack_cnt; 2514 bool addck_timeout[RTW89_DACK_PATH_NR]; 2515 bool dadck_timeout[RTW89_DACK_PATH_NR]; 2516 bool msbk_timeout[RTW89_DACK_PATH_NR]; 2517 }; 2518 2519 #define RTW89_IQK_CHS_NR 2 2520 #define RTW89_IQK_PATH_NR 4 2521 struct rtw89_iqk_info { 2522 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2523 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2524 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2525 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2526 u32 iqk_fail_cnt; 2527 bool is_iqk_init; 2528 u32 iqk_channel[RTW89_IQK_CHS_NR]; 2529 u8 iqk_band[RTW89_IQK_PATH_NR]; 2530 u8 iqk_ch[RTW89_IQK_PATH_NR]; 2531 u8 iqk_bw[RTW89_IQK_PATH_NR]; 2532 u8 kcount; 2533 u8 iqk_times; 2534 u8 version; 2535 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 2536 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 2537 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 2538 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 2539 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 2540 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 2541 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 2542 bool is_nbiqk; 2543 bool iqk_fft_en; 2544 bool iqk_xym_en; 2545 bool iqk_sram_en; 2546 bool iqk_cfir_en; 2547 u8 thermal[RTW89_IQK_PATH_NR]; 2548 bool thermal_rek_en; 2549 u32 syn1to2; 2550 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2551 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 2552 }; 2553 2554 #define RTW89_DPK_RF_PATH 2 2555 #define RTW89_DPK_AVG_THERMAL_NUM 8 2556 #define RTW89_DPK_BKUP_NUM 2 2557 struct rtw89_dpk_bkup_para { 2558 enum rtw89_band band; 2559 enum rtw89_bandwidth bw; 2560 u8 ch; 2561 bool path_ok; 2562 u8 txagc_dpk; 2563 u8 ther_dpk; 2564 u8 gs; 2565 u16 pwsf; 2566 }; 2567 2568 struct rtw89_dpk_info { 2569 bool is_dpk_enable; 2570 bool is_dpk_reload_en; 2571 u16 dc_i[RTW89_DPK_RF_PATH]; 2572 u16 dc_q[RTW89_DPK_RF_PATH]; 2573 u8 corr_val[RTW89_DPK_RF_PATH]; 2574 u8 corr_idx[RTW89_DPK_RF_PATH]; 2575 u8 cur_idx[RTW89_DPK_RF_PATH]; 2576 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2577 }; 2578 2579 struct rtw89_fem_info { 2580 bool elna_2g; 2581 bool elna_5g; 2582 bool epa_2g; 2583 bool epa_5g; 2584 }; 2585 2586 struct rtw89_phy_ch_info { 2587 u8 rssi_min; 2588 u16 rssi_min_macid; 2589 u8 pre_rssi_min; 2590 u8 rssi_max; 2591 u16 rssi_max_macid; 2592 u8 rxsc_160; 2593 u8 rxsc_80; 2594 u8 rxsc_40; 2595 u8 rxsc_20; 2596 u8 rxsc_l; 2597 u8 is_noisy; 2598 }; 2599 2600 struct rtw89_agc_gaincode_set { 2601 u8 lna_idx; 2602 u8 tia_idx; 2603 u8 rxb_idx; 2604 }; 2605 2606 #define IGI_RSSI_TH_NUM 5 2607 #define FA_TH_NUM 4 2608 #define LNA_GAIN_NUM 7 2609 #define TIA_GAIN_NUM 2 2610 struct rtw89_dig_info { 2611 struct rtw89_agc_gaincode_set cur_gaincode; 2612 bool force_gaincode_idx_en; 2613 struct rtw89_agc_gaincode_set force_gaincode; 2614 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 2615 u16 fa_th[FA_TH_NUM]; 2616 u8 igi_rssi; 2617 u8 igi_fa_rssi; 2618 u8 fa_rssi_ofst; 2619 u8 dyn_igi_max; 2620 u8 dyn_igi_min; 2621 bool dyn_pd_th_en; 2622 u8 dyn_pd_th_max; 2623 u8 pd_low_th_ofst; 2624 u8 ib_pbk; 2625 s8 ib_pkpwr; 2626 s8 lna_gain_a[LNA_GAIN_NUM]; 2627 s8 lna_gain_g[LNA_GAIN_NUM]; 2628 s8 *lna_gain; 2629 s8 tia_gain_a[TIA_GAIN_NUM]; 2630 s8 tia_gain_g[TIA_GAIN_NUM]; 2631 s8 *tia_gain; 2632 bool is_linked_pre; 2633 bool bypass_dig; 2634 }; 2635 2636 enum rtw89_multi_cfo_mode { 2637 RTW89_PKT_BASED_AVG_MODE = 0, 2638 RTW89_ENTRY_BASED_AVG_MODE = 1, 2639 RTW89_TP_BASED_AVG_MODE = 2, 2640 }; 2641 2642 enum rtw89_phy_cfo_status { 2643 RTW89_PHY_DCFO_STATE_NORMAL = 0, 2644 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 2645 RTW89_PHY_DCFO_STATE_MAX 2646 }; 2647 2648 struct rtw89_cfo_tracking_info { 2649 u16 cfo_timer_ms; 2650 bool cfo_trig_by_timer_en; 2651 enum rtw89_phy_cfo_status phy_cfo_status; 2652 u8 phy_cfo_trk_cnt; 2653 bool is_adjust; 2654 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 2655 bool apply_compensation; 2656 u8 crystal_cap; 2657 u8 crystal_cap_default; 2658 u8 def_x_cap; 2659 s8 x_cap_ofst; 2660 u32 sta_cfo_tolerance; 2661 s32 cfo_tail[CFO_TRACK_MAX_USER]; 2662 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 2663 s32 cfo_avg_pre; 2664 s32 cfo_avg[CFO_TRACK_MAX_USER]; 2665 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 2666 u32 packet_count; 2667 u32 packet_count_pre; 2668 s32 residual_cfo_acc; 2669 u8 phy_cfotrk_state; 2670 u8 phy_cfotrk_cnt; 2671 bool divergence_lock_en; 2672 u8 x_cap_lb; 2673 u8 x_cap_ub; 2674 u8 lock_cnt; 2675 }; 2676 2677 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 2678 #define TSSI_TRIM_CH_GROUP_NUM 8 2679 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 2680 2681 #define TSSI_CCK_CH_GROUP_NUM 6 2682 #define TSSI_MCS_2G_CH_GROUP_NUM 5 2683 #define TSSI_MCS_5G_CH_GROUP_NUM 14 2684 #define TSSI_MCS_6G_CH_GROUP_NUM 32 2685 #define TSSI_MCS_CH_GROUP_NUM \ 2686 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 2687 2688 struct rtw89_tssi_info { 2689 u8 thermal[RF_PATH_MAX]; 2690 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 2691 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 2692 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 2693 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 2694 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 2695 s8 extra_ofst[RF_PATH_MAX]; 2696 bool tssi_tracking_check[RF_PATH_MAX]; 2697 u8 default_txagc_offset[RF_PATH_MAX]; 2698 u32 base_thermal[RF_PATH_MAX]; 2699 }; 2700 2701 struct rtw89_power_trim_info { 2702 bool pg_thermal_trim; 2703 bool pg_pa_bias_trim; 2704 u8 thermal_trim[RF_PATH_MAX]; 2705 u8 pa_bias_trim[RF_PATH_MAX]; 2706 }; 2707 2708 struct rtw89_regulatory { 2709 char alpha2[3]; 2710 u8 txpwr_regd[RTW89_BAND_MAX]; 2711 }; 2712 2713 enum rtw89_ifs_clm_application { 2714 RTW89_IFS_CLM_INIT = 0, 2715 RTW89_IFS_CLM_BACKGROUND = 1, 2716 RTW89_IFS_CLM_ACS = 2, 2717 RTW89_IFS_CLM_DIG = 3, 2718 RTW89_IFS_CLM_TDMA_DIG = 4, 2719 RTW89_IFS_CLM_DBG = 5, 2720 RTW89_IFS_CLM_DBG_MANUAL = 6 2721 }; 2722 2723 enum rtw89_env_racing_lv { 2724 RTW89_RAC_RELEASE = 0, 2725 RTW89_RAC_LV_1 = 1, 2726 RTW89_RAC_LV_2 = 2, 2727 RTW89_RAC_LV_3 = 3, 2728 RTW89_RAC_LV_4 = 4, 2729 RTW89_RAC_MAX_NUM = 5 2730 }; 2731 2732 struct rtw89_ccx_para_info { 2733 enum rtw89_env_racing_lv rac_lv; 2734 u16 mntr_time; 2735 u8 nhm_manual_th_ofst; 2736 u8 nhm_manual_th0; 2737 enum rtw89_ifs_clm_application ifs_clm_app; 2738 u32 ifs_clm_manual_th_times; 2739 u32 ifs_clm_manual_th0; 2740 u8 fahm_manual_th_ofst; 2741 u8 fahm_manual_th0; 2742 u8 fahm_numer_opt; 2743 u8 fahm_denom_opt; 2744 }; 2745 2746 enum rtw89_ccx_edcca_opt_sc_idx { 2747 RTW89_CCX_EDCCA_SEG0_P0 = 0, 2748 RTW89_CCX_EDCCA_SEG0_S1 = 1, 2749 RTW89_CCX_EDCCA_SEG0_S2 = 2, 2750 RTW89_CCX_EDCCA_SEG0_S3 = 3, 2751 RTW89_CCX_EDCCA_SEG1_P0 = 4, 2752 RTW89_CCX_EDCCA_SEG1_S1 = 5, 2753 RTW89_CCX_EDCCA_SEG1_S2 = 6, 2754 RTW89_CCX_EDCCA_SEG1_S3 = 7 2755 }; 2756 2757 enum rtw89_ccx_edcca_opt_bw_idx { 2758 RTW89_CCX_EDCCA_BW20_0 = 0, 2759 RTW89_CCX_EDCCA_BW20_1 = 1, 2760 RTW89_CCX_EDCCA_BW20_2 = 2, 2761 RTW89_CCX_EDCCA_BW20_3 = 3, 2762 RTW89_CCX_EDCCA_BW20_4 = 4, 2763 RTW89_CCX_EDCCA_BW20_5 = 5, 2764 RTW89_CCX_EDCCA_BW20_6 = 6, 2765 RTW89_CCX_EDCCA_BW20_7 = 7 2766 }; 2767 2768 #define RTW89_NHM_TH_NUM 11 2769 #define RTW89_FAHM_TH_NUM 11 2770 #define RTW89_NHM_RPT_NUM 12 2771 #define RTW89_FAHM_RPT_NUM 12 2772 #define RTW89_IFS_CLM_NUM 4 2773 struct rtw89_env_monitor_info { 2774 u32 ccx_trigger_time; 2775 u64 start_time; 2776 u8 ccx_rpt_stamp; 2777 u8 ccx_watchdog_result; 2778 bool ccx_ongoing; 2779 u8 ccx_rac_lv; 2780 bool ccx_manual_ctrl; 2781 u8 ccx_pre_rssi; 2782 u16 clm_mntr_time; 2783 u16 nhm_mntr_time; 2784 u16 ifs_clm_mntr_time; 2785 enum rtw89_ifs_clm_application ifs_clm_app; 2786 u16 fahm_mntr_time; 2787 u16 edcca_clm_mntr_time; 2788 u16 ccx_period; 2789 u8 ccx_unit_idx; 2790 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 2791 u8 nhm_th[RTW89_NHM_TH_NUM]; 2792 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 2793 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 2794 u8 fahm_numer_opt; 2795 u8 fahm_denom_opt; 2796 u8 fahm_th[RTW89_FAHM_TH_NUM]; 2797 u16 clm_result; 2798 u16 nhm_result[RTW89_NHM_RPT_NUM]; 2799 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 2800 u16 nhm_tx_cnt; 2801 u16 nhm_cca_cnt; 2802 u16 nhm_idle_cnt; 2803 u16 ifs_clm_tx; 2804 u16 ifs_clm_edcca_excl_cca; 2805 u16 ifs_clm_ofdmfa; 2806 u16 ifs_clm_ofdmcca_excl_fa; 2807 u16 ifs_clm_cckfa; 2808 u16 ifs_clm_cckcca_excl_fa; 2809 u16 ifs_clm_total_ifs; 2810 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 2811 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 2812 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 2813 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 2814 u16 fahm_denom_result; 2815 u16 edcca_clm_result; 2816 u8 clm_ratio; 2817 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 2818 u8 nhm_tx_ratio; 2819 u8 nhm_cca_ratio; 2820 u8 nhm_idle_ratio; 2821 u8 nhm_ratio; 2822 u16 nhm_result_sum; 2823 u8 nhm_pwr; 2824 u8 ifs_clm_tx_ratio; 2825 u8 ifs_clm_edcca_excl_cca_ratio; 2826 u8 ifs_clm_cck_fa_ratio; 2827 u8 ifs_clm_ofdm_fa_ratio; 2828 u8 ifs_clm_cck_cca_excl_fa_ratio; 2829 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 2830 u16 ifs_clm_cck_fa_permil; 2831 u16 ifs_clm_ofdm_fa_permil; 2832 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 2833 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 2834 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 2835 u16 fahm_result_sum; 2836 u8 fahm_ratio; 2837 u8 fahm_denom_ratio; 2838 u8 fahm_pwr; 2839 u8 edcca_clm_ratio; 2840 }; 2841 2842 enum rtw89_ser_rcvy_step { 2843 RTW89_SER_DRV_STOP_TX, 2844 RTW89_SER_DRV_STOP_RX, 2845 RTW89_SER_DRV_STOP_RUN, 2846 RTW89_SER_HAL_STOP_DMA, 2847 RTW89_NUM_OF_SER_FLAGS 2848 }; 2849 2850 struct rtw89_ser { 2851 u8 state; 2852 u8 alarm_event; 2853 2854 struct work_struct ser_hdl_work; 2855 struct delayed_work ser_alarm_work; 2856 struct state_ent *st_tbl; 2857 struct event_ent *ev_tbl; 2858 struct list_head msg_q; 2859 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 2860 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 2861 }; 2862 2863 enum rtw89_mac_ax_ps_mode { 2864 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 2865 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 2866 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 2867 RTW89_MAC_AX_PS_MODE_MAX = 3, 2868 }; 2869 2870 enum rtw89_last_rpwm_mode { 2871 RTW89_LAST_RPWM_PS = 0x0, 2872 RTW89_LAST_RPWM_ACTIVE = 0x6, 2873 }; 2874 2875 struct rtw89_lps_parm { 2876 u8 macid; 2877 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 2878 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 2879 }; 2880 2881 struct rtw89_ppdu_sts_info { 2882 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 2883 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 2884 }; 2885 2886 struct rtw89_early_h2c { 2887 struct list_head list; 2888 u8 *h2c; 2889 u16 h2c_len; 2890 }; 2891 2892 struct rtw89_hw_scan_info { 2893 struct ieee80211_vif *scanning_vif; 2894 struct list_head pkt_list[NUM_NL80211_BANDS]; 2895 u8 op_pri_ch; 2896 u8 op_chan; 2897 u8 op_bw; 2898 u8 op_band; 2899 }; 2900 2901 struct rtw89_dev { 2902 struct ieee80211_hw *hw; 2903 struct device *dev; 2904 2905 bool dbcc_en; 2906 struct rtw89_hw_scan_info scan_info; 2907 const struct rtw89_chip_info *chip; 2908 const struct rtw89_pci_info *pci_info; 2909 struct rtw89_hal hal; 2910 struct rtw89_mac_info mac; 2911 struct rtw89_fw_info fw; 2912 struct rtw89_hci_info hci; 2913 struct rtw89_efuse efuse; 2914 struct rtw89_traffic_stats stats; 2915 2916 /* ensures exclusive access from mac80211 callbacks */ 2917 struct mutex mutex; 2918 struct list_head rtwvifs_list; 2919 /* used to protect rf read write */ 2920 struct mutex rf_mutex; 2921 struct workqueue_struct *txq_wq; 2922 struct work_struct txq_work; 2923 struct delayed_work txq_reinvoke_work; 2924 /* used to protect ba_list */ 2925 spinlock_t ba_lock; 2926 /* txqs to setup ba session */ 2927 struct list_head ba_list; 2928 struct work_struct ba_work; 2929 /* used to protect rpwm */ 2930 spinlock_t rpwm_lock; 2931 2932 struct rtw89_cam_info cam_info; 2933 2934 struct sk_buff_head c2h_queue; 2935 struct work_struct c2h_work; 2936 struct work_struct ips_work; 2937 2938 struct list_head early_h2c_list; 2939 2940 struct rtw89_ser ser; 2941 2942 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 2943 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 2944 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 2945 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 2946 2947 struct rtw89_phy_stat phystat; 2948 struct rtw89_dack_info dack; 2949 struct rtw89_iqk_info iqk; 2950 struct rtw89_dpk_info dpk; 2951 bool is_tssi_mode[RF_PATH_MAX]; 2952 bool is_bt_iqk_timeout; 2953 2954 struct rtw89_fem_info fem; 2955 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 2956 struct rtw89_tssi_info tssi; 2957 struct rtw89_power_trim_info pwr_trim; 2958 2959 struct rtw89_cfo_tracking_info cfo_tracking; 2960 struct rtw89_env_monitor_info env_monitor; 2961 struct rtw89_dig_info dig; 2962 struct rtw89_phy_ch_info ch_info; 2963 struct delayed_work track_work; 2964 struct delayed_work coex_act1_work; 2965 struct delayed_work coex_bt_devinfo_work; 2966 struct delayed_work coex_rfk_chk_work; 2967 struct delayed_work cfo_track_work; 2968 struct rtw89_ppdu_sts_info ppdu_sts; 2969 u8 total_sta_assoc; 2970 bool scanning; 2971 2972 const struct rtw89_regulatory *regd; 2973 struct rtw89_sar_info sar; 2974 2975 struct rtw89_btc btc; 2976 enum rtw89_ps_mode ps_mode; 2977 bool lps_enabled; 2978 2979 /* napi structure */ 2980 struct net_device netdev; 2981 struct napi_struct napi; 2982 int napi_budget_countdown; 2983 2984 /* HCI related data, keep last */ 2985 u8 priv[] __aligned(sizeof(void *)); 2986 }; 2987 2988 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 2989 struct rtw89_core_tx_request *tx_req) 2990 { 2991 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 2992 } 2993 2994 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 2995 { 2996 rtwdev->hci.ops->reset(rtwdev); 2997 } 2998 2999 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 3000 { 3001 return rtwdev->hci.ops->start(rtwdev); 3002 } 3003 3004 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 3005 { 3006 rtwdev->hci.ops->stop(rtwdev); 3007 } 3008 3009 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 3010 { 3011 return rtwdev->hci.ops->deinit(rtwdev); 3012 } 3013 3014 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 3015 { 3016 rtwdev->hci.ops->recalc_int_mit(rtwdev); 3017 } 3018 3019 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 3020 { 3021 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 3022 } 3023 3024 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 3025 { 3026 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 3027 } 3028 3029 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 3030 bool drop) 3031 { 3032 if (rtwdev->hci.ops->flush_queues) 3033 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 3034 } 3035 3036 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 3037 { 3038 return rtwdev->hci.ops->read8(rtwdev, addr); 3039 } 3040 3041 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 3042 { 3043 return rtwdev->hci.ops->read16(rtwdev, addr); 3044 } 3045 3046 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 3047 { 3048 return rtwdev->hci.ops->read32(rtwdev, addr); 3049 } 3050 3051 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 3052 { 3053 rtwdev->hci.ops->write8(rtwdev, addr, data); 3054 } 3055 3056 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 3057 { 3058 rtwdev->hci.ops->write16(rtwdev, addr, data); 3059 } 3060 3061 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 3062 { 3063 rtwdev->hci.ops->write32(rtwdev, addr, data); 3064 } 3065 3066 static inline void 3067 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3068 { 3069 u8 val; 3070 3071 val = rtw89_read8(rtwdev, addr); 3072 rtw89_write8(rtwdev, addr, val | bit); 3073 } 3074 3075 static inline void 3076 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3077 { 3078 u16 val; 3079 3080 val = rtw89_read16(rtwdev, addr); 3081 rtw89_write16(rtwdev, addr, val | bit); 3082 } 3083 3084 static inline void 3085 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3086 { 3087 u32 val; 3088 3089 val = rtw89_read32(rtwdev, addr); 3090 rtw89_write32(rtwdev, addr, val | bit); 3091 } 3092 3093 static inline void 3094 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 3095 { 3096 u8 val; 3097 3098 val = rtw89_read8(rtwdev, addr); 3099 rtw89_write8(rtwdev, addr, val & ~bit); 3100 } 3101 3102 static inline void 3103 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 3104 { 3105 u16 val; 3106 3107 val = rtw89_read16(rtwdev, addr); 3108 rtw89_write16(rtwdev, addr, val & ~bit); 3109 } 3110 3111 static inline void 3112 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3113 { 3114 u32 val; 3115 3116 val = rtw89_read32(rtwdev, addr); 3117 rtw89_write32(rtwdev, addr, val & ~bit); 3118 } 3119 3120 static inline u32 3121 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3122 { 3123 u32 shift = __ffs(mask); 3124 u32 orig; 3125 u32 ret; 3126 3127 orig = rtw89_read32(rtwdev, addr); 3128 ret = (orig & mask) >> shift; 3129 3130 return ret; 3131 } 3132 3133 static inline u16 3134 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3135 { 3136 u32 shift = __ffs(mask); 3137 u32 orig; 3138 u32 ret; 3139 3140 orig = rtw89_read16(rtwdev, addr); 3141 ret = (orig & mask) >> shift; 3142 3143 return ret; 3144 } 3145 3146 static inline u8 3147 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3148 { 3149 u32 shift = __ffs(mask); 3150 u32 orig; 3151 u32 ret; 3152 3153 orig = rtw89_read8(rtwdev, addr); 3154 ret = (orig & mask) >> shift; 3155 3156 return ret; 3157 } 3158 3159 static inline void 3160 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 3161 { 3162 u32 shift = __ffs(mask); 3163 u32 orig; 3164 u32 set; 3165 3166 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 3167 3168 orig = rtw89_read32(rtwdev, addr); 3169 set = (orig & ~mask) | ((data << shift) & mask); 3170 rtw89_write32(rtwdev, addr, set); 3171 } 3172 3173 static inline void 3174 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 3175 { 3176 u32 shift; 3177 u16 orig, set; 3178 3179 mask &= 0xffff; 3180 shift = __ffs(mask); 3181 3182 orig = rtw89_read16(rtwdev, addr); 3183 set = (orig & ~mask) | ((data << shift) & mask); 3184 rtw89_write16(rtwdev, addr, set); 3185 } 3186 3187 static inline void 3188 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 3189 { 3190 u32 shift; 3191 u8 orig, set; 3192 3193 mask &= 0xff; 3194 shift = __ffs(mask); 3195 3196 orig = rtw89_read8(rtwdev, addr); 3197 set = (orig & ~mask) | ((data << shift) & mask); 3198 rtw89_write8(rtwdev, addr, set); 3199 } 3200 3201 static inline u32 3202 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3203 u32 addr, u32 mask) 3204 { 3205 u32 val; 3206 3207 mutex_lock(&rtwdev->rf_mutex); 3208 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 3209 mutex_unlock(&rtwdev->rf_mutex); 3210 3211 return val; 3212 } 3213 3214 static inline void 3215 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3216 u32 addr, u32 mask, u32 data) 3217 { 3218 mutex_lock(&rtwdev->rf_mutex); 3219 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 3220 mutex_unlock(&rtwdev->rf_mutex); 3221 } 3222 3223 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 3224 { 3225 void *p = rtwtxq; 3226 3227 return container_of(p, struct ieee80211_txq, drv_priv); 3228 } 3229 3230 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 3231 struct ieee80211_txq *txq) 3232 { 3233 struct rtw89_txq *rtwtxq; 3234 3235 if (!txq) 3236 return; 3237 3238 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3239 INIT_LIST_HEAD(&rtwtxq->list); 3240 } 3241 3242 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 3243 { 3244 void *p = rtwvif; 3245 3246 return container_of(p, struct ieee80211_vif, drv_priv); 3247 } 3248 3249 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 3250 { 3251 void *p = rtwsta; 3252 3253 return container_of(p, struct ieee80211_sta, drv_priv); 3254 } 3255 3256 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 3257 { 3258 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 3259 } 3260 3261 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 3262 { 3263 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 3264 } 3265 3266 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 3267 { 3268 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 3269 return RATE_INFO_BW_160; 3270 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 3271 return RATE_INFO_BW_80; 3272 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 3273 return RATE_INFO_BW_40; 3274 else 3275 return RATE_INFO_BW_20; 3276 } 3277 3278 static inline 3279 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 3280 { 3281 switch (width) { 3282 default: 3283 WARN(1, "Not support bandwidth %d\n", width); 3284 fallthrough; 3285 case NL80211_CHAN_WIDTH_20_NOHT: 3286 case NL80211_CHAN_WIDTH_20: 3287 return RTW89_CHANNEL_WIDTH_20; 3288 case NL80211_CHAN_WIDTH_40: 3289 return RTW89_CHANNEL_WIDTH_40; 3290 case NL80211_CHAN_WIDTH_80: 3291 return RTW89_CHANNEL_WIDTH_80; 3292 case NL80211_CHAN_WIDTH_160: 3293 return RTW89_CHANNEL_WIDTH_160; 3294 } 3295 } 3296 3297 static inline 3298 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 3299 struct rtw89_sta *rtwsta) 3300 { 3301 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE && rtwsta) 3302 return &rtwsta->addr_cam; 3303 return &rtwvif->addr_cam; 3304 } 3305 3306 static inline 3307 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 3308 struct rtw89_channel_help_params *p) 3309 { 3310 rtwdev->chip->ops->set_channel_help(rtwdev, true, p); 3311 } 3312 3313 static inline 3314 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 3315 struct rtw89_channel_help_params *p) 3316 { 3317 rtwdev->chip->ops->set_channel_help(rtwdev, false, p); 3318 } 3319 3320 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 3321 { 3322 const struct rtw89_chip_info *chip = rtwdev->chip; 3323 3324 if (chip->ops->fem_setup) 3325 chip->ops->fem_setup(rtwdev); 3326 } 3327 3328 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 3329 { 3330 const struct rtw89_chip_info *chip = rtwdev->chip; 3331 3332 if (chip->ops->bb_sethw) 3333 chip->ops->bb_sethw(rtwdev); 3334 } 3335 3336 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 3337 { 3338 const struct rtw89_chip_info *chip = rtwdev->chip; 3339 3340 if (chip->ops->rfk_init) 3341 chip->ops->rfk_init(rtwdev); 3342 } 3343 3344 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 3345 { 3346 const struct rtw89_chip_info *chip = rtwdev->chip; 3347 3348 if (chip->ops->rfk_channel) 3349 chip->ops->rfk_channel(rtwdev); 3350 } 3351 3352 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev) 3353 { 3354 const struct rtw89_chip_info *chip = rtwdev->chip; 3355 3356 if (chip->ops->rfk_band_changed) 3357 chip->ops->rfk_band_changed(rtwdev); 3358 } 3359 3360 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 3361 { 3362 const struct rtw89_chip_info *chip = rtwdev->chip; 3363 3364 if (chip->ops->rfk_scan) 3365 chip->ops->rfk_scan(rtwdev, start); 3366 } 3367 3368 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 3369 { 3370 const struct rtw89_chip_info *chip = rtwdev->chip; 3371 3372 if (chip->ops->rfk_track) 3373 chip->ops->rfk_track(rtwdev); 3374 } 3375 3376 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 3377 { 3378 const struct rtw89_chip_info *chip = rtwdev->chip; 3379 3380 if (chip->ops->set_txpwr_ctrl) 3381 chip->ops->set_txpwr_ctrl(rtwdev); 3382 } 3383 3384 static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev) 3385 { 3386 const struct rtw89_chip_info *chip = rtwdev->chip; 3387 u8 ch = rtwdev->hal.current_channel; 3388 3389 if (!ch) 3390 return; 3391 3392 if (chip->ops->set_txpwr) 3393 chip->ops->set_txpwr(rtwdev); 3394 } 3395 3396 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 3397 { 3398 const struct rtw89_chip_info *chip = rtwdev->chip; 3399 3400 if (chip->ops->power_trim) 3401 chip->ops->power_trim(rtwdev); 3402 } 3403 3404 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 3405 enum rtw89_phy_idx phy_idx) 3406 { 3407 const struct rtw89_chip_info *chip = rtwdev->chip; 3408 3409 if (chip->ops->init_txpwr_unit) 3410 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 3411 } 3412 3413 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 3414 enum rtw89_rf_path rf_path) 3415 { 3416 const struct rtw89_chip_info *chip = rtwdev->chip; 3417 3418 if (!chip->ops->get_thermal) 3419 return 0x10; 3420 3421 return chip->ops->get_thermal(rtwdev, rf_path); 3422 } 3423 3424 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 3425 struct rtw89_rx_phy_ppdu *phy_ppdu, 3426 struct ieee80211_rx_status *status) 3427 { 3428 const struct rtw89_chip_info *chip = rtwdev->chip; 3429 3430 if (chip->ops->query_ppdu) 3431 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 3432 } 3433 3434 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 3435 bool bt_en) 3436 { 3437 const struct rtw89_chip_info *chip = rtwdev->chip; 3438 3439 if (chip->ops->bb_ctrl_btc_preagc) 3440 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 3441 } 3442 3443 static inline 3444 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 3445 struct ieee80211_vif *vif) 3446 { 3447 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3448 const struct rtw89_chip_info *chip = rtwdev->chip; 3449 3450 if (!vif->bss_conf.he_support || !vif->bss_conf.assoc) 3451 return; 3452 3453 if (chip->ops->set_txpwr_ul_tb_offset) 3454 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 3455 } 3456 3457 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 3458 const struct rtw89_txpwr_table *tbl) 3459 { 3460 tbl->load(rtwdev, tbl); 3461 } 3462 3463 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 3464 { 3465 return rtwdev->regd->txpwr_regd[band]; 3466 } 3467 3468 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 3469 { 3470 const struct rtw89_chip_info *chip = rtwdev->chip; 3471 3472 if (chip->ops->ctrl_btg) 3473 chip->ops->ctrl_btg(rtwdev, btg); 3474 } 3475 3476 static inline 3477 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 3478 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 3479 { 3480 const struct rtw89_chip_info *chip = rtwdev->chip; 3481 3482 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 3483 } 3484 3485 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 3486 { 3487 const struct rtw89_chip_info *chip = rtwdev->chip; 3488 3489 chip->ops->cfg_ctrl_path(rtwdev, wl); 3490 } 3491 3492 static inline 3493 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3494 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3495 { 3496 const struct rtw89_chip_info *chip = rtwdev->chip; 3497 3498 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 3499 } 3500 3501 static inline 3502 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3503 { 3504 const struct rtw89_chip_info *chip = rtwdev->chip; 3505 3506 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 3507 } 3508 3509 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 3510 { 3511 __le16 fc = hdr->frame_control; 3512 3513 if (ieee80211_has_tods(fc)) 3514 return hdr->addr1; 3515 else if (ieee80211_has_fromds(fc)) 3516 return hdr->addr2; 3517 else 3518 return hdr->addr3; 3519 } 3520 3521 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 3522 { 3523 if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 3524 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 3525 (sta->he_cap.he_cap_elem.phy_cap_info[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 3526 (sta->he_cap.he_cap_elem.phy_cap_info[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 3527 return true; 3528 return false; 3529 } 3530 3531 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 3532 enum rtw89_fw_type type) 3533 { 3534 struct rtw89_fw_info *fw_info = &rtwdev->fw; 3535 3536 if (type == RTW89_FW_WOWLAN) 3537 return &fw_info->wowlan; 3538 return &fw_info->normal; 3539 } 3540 3541 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3542 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 3543 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 3544 struct sk_buff *skb, bool fwdl); 3545 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 3546 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 3547 struct rtw89_tx_desc_info *desc_info, 3548 void *txdesc); 3549 void rtw89_core_rx(struct rtw89_dev *rtwdev, 3550 struct rtw89_rx_desc_info *desc_info, 3551 struct sk_buff *skb); 3552 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 3553 struct rtw89_rx_desc_info *desc_info, 3554 u8 *data, u32 data_offset); 3555 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 3556 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 3557 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 3558 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 3559 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3560 struct ieee80211_vif *vif, 3561 struct ieee80211_sta *sta); 3562 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3563 struct ieee80211_vif *vif, 3564 struct ieee80211_sta *sta); 3565 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3566 struct ieee80211_vif *vif, 3567 struct ieee80211_sta *sta); 3568 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3569 struct ieee80211_vif *vif, 3570 struct ieee80211_sta *sta); 3571 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3572 struct ieee80211_vif *vif, 3573 struct ieee80211_sta *sta); 3574 int rtw89_core_init(struct rtw89_dev *rtwdev); 3575 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 3576 int rtw89_core_register(struct rtw89_dev *rtwdev); 3577 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 3578 void rtw89_set_channel(struct rtw89_dev *rtwdev); 3579 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 3580 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 3581 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 3582 int rtw89_core_acquire_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 3583 int rtw89_core_release_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 3584 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 3585 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 3586 u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate); 3587 int rtw89_regd_init(struct rtw89_dev *rtwdev, 3588 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 3589 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 3590 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3591 struct rtw89_traffic_stats *stats); 3592 int rtw89_core_start(struct rtw89_dev *rtwdev); 3593 void rtw89_core_stop(struct rtw89_dev *rtwdev); 3594 void rtw89_core_update_beacon_work(struct work_struct *work); 3595 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3596 const u8 *mac_addr, bool hw_scan); 3597 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3598 struct ieee80211_vif *vif, bool hw_scan); 3599 3600 #endif 3601