1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_efuse_block_cfg; 21 struct rtw89_h2c_rf_tssi; 22 struct rtw89_fw_txpwr_track_cfg; 23 struct rtw89_phy_rfk_log_fmt; 24 25 extern const struct ieee80211_ops rtw89_ops; 26 27 #define MASKBYTE0 0xff 28 #define MASKBYTE1 0xff00 29 #define MASKBYTE2 0xff0000 30 #define MASKBYTE3 0xff000000 31 #define MASKBYTE4 0xff00000000ULL 32 #define MASKHWORD 0xffff0000 33 #define MASKLWORD 0x0000ffff 34 #define MASKDWORD 0xffffffff 35 #define RFREG_MASK 0xfffff 36 #define INV_RF_DATA 0xffffffff 37 #define BYPASS_CR_DATA 0xbabecafe 38 39 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 40 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 41 #define CFO_TRACK_MAX_USER 64 42 #define MAX_RSSI 110 43 #define RSSI_FACTOR 1 44 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 45 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 46 #define DELTA_SWINGIDX_SIZE 30 47 48 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 49 #define RTW89_RADIOTAP_ROOM_EHT \ 50 (sizeof(struct ieee80211_radiotap_tlv) + \ 51 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 52 sizeof(struct ieee80211_radiotap_tlv) + \ 53 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 54 #define RTW89_RADIOTAP_ROOM \ 55 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 56 57 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 58 #define RTW89_HTC_VARIANT_HE 3 59 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 60 #define RTW89_HTC_VARIANT_HE_CID_OM 1 61 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 62 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 63 64 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 65 enum htc_om_channel_width { 66 HTC_OM_CHANNEL_WIDTH_20 = 0, 67 HTC_OM_CHANNEL_WIDTH_40 = 1, 68 HTC_OM_CHANNEL_WIDTH_80 = 2, 69 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 70 }; 71 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 72 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 73 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 74 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 75 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 76 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 77 78 #define RTW89_TF_PAD GENMASK(11, 0) 79 #define RTW89_TF_BASIC_USER_INFO_SZ 6 80 81 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 82 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 83 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 84 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 85 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 86 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 87 88 enum rtw89_subband { 89 RTW89_CH_2G = 0, 90 RTW89_CH_5G_BAND_1 = 1, 91 /* RTW89_CH_5G_BAND_2 = 2, unused */ 92 RTW89_CH_5G_BAND_3 = 3, 93 RTW89_CH_5G_BAND_4 = 4, 94 95 RTW89_CH_6G_BAND_IDX0, /* Low */ 96 RTW89_CH_6G_BAND_IDX1, /* Low */ 97 RTW89_CH_6G_BAND_IDX2, /* Mid */ 98 RTW89_CH_6G_BAND_IDX3, /* Mid */ 99 RTW89_CH_6G_BAND_IDX4, /* High */ 100 RTW89_CH_6G_BAND_IDX5, /* High */ 101 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 102 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 103 104 RTW89_SUBBAND_NR, 105 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 106 }; 107 108 enum rtw89_gain_offset { 109 RTW89_GAIN_OFFSET_2G_CCK, 110 RTW89_GAIN_OFFSET_2G_OFDM, 111 RTW89_GAIN_OFFSET_5G_LOW, 112 RTW89_GAIN_OFFSET_5G_MID, 113 RTW89_GAIN_OFFSET_5G_HIGH, 114 RTW89_GAIN_OFFSET_6G_L0, 115 RTW89_GAIN_OFFSET_6G_L1, 116 RTW89_GAIN_OFFSET_6G_M0, 117 RTW89_GAIN_OFFSET_6G_M1, 118 RTW89_GAIN_OFFSET_6G_H0, 119 RTW89_GAIN_OFFSET_6G_H1, 120 RTW89_GAIN_OFFSET_6G_UH0, 121 RTW89_GAIN_OFFSET_6G_UH1, 122 123 RTW89_GAIN_OFFSET_NR, 124 }; 125 126 enum rtw89_hci_type { 127 RTW89_HCI_TYPE_PCIE, 128 RTW89_HCI_TYPE_USB, 129 RTW89_HCI_TYPE_SDIO, 130 }; 131 132 enum rtw89_core_chip_id { 133 RTL8852A, 134 RTL8852B, 135 RTL8852C, 136 RTL8851B, 137 RTL8922A, 138 }; 139 140 enum rtw89_chip_gen { 141 RTW89_CHIP_AX, 142 RTW89_CHIP_BE, 143 144 RTW89_CHIP_GEN_NUM, 145 }; 146 147 enum rtw89_cv { 148 CHIP_CAV, 149 CHIP_CBV, 150 CHIP_CCV, 151 CHIP_CDV, 152 CHIP_CEV, 153 CHIP_CFV, 154 CHIP_CV_MAX, 155 CHIP_CV_INVALID = CHIP_CV_MAX, 156 }; 157 158 enum rtw89_bacam_ver { 159 RTW89_BACAM_V0, 160 RTW89_BACAM_V1, 161 162 RTW89_BACAM_V0_EXT = 99, 163 }; 164 165 enum rtw89_core_tx_type { 166 RTW89_CORE_TX_TYPE_DATA, 167 RTW89_CORE_TX_TYPE_MGMT, 168 RTW89_CORE_TX_TYPE_FWCMD, 169 }; 170 171 enum rtw89_core_rx_type { 172 RTW89_CORE_RX_TYPE_WIFI = 0, 173 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 174 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 175 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 176 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 177 RTW89_CORE_RX_TYPE_SS2FW = 5, 178 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 179 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 180 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 181 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 182 RTW89_CORE_RX_TYPE_C2H = 10, 183 RTW89_CORE_RX_TYPE_CSI = 11, 184 RTW89_CORE_RX_TYPE_CQI = 12, 185 RTW89_CORE_RX_TYPE_H2C = 13, 186 RTW89_CORE_RX_TYPE_FWDL = 14, 187 }; 188 189 enum rtw89_txq_flags { 190 RTW89_TXQ_F_AMPDU = 0, 191 RTW89_TXQ_F_BLOCK_BA = 1, 192 RTW89_TXQ_F_FORBID_BA = 2, 193 }; 194 195 enum rtw89_net_type { 196 RTW89_NET_TYPE_NO_LINK = 0, 197 RTW89_NET_TYPE_AD_HOC = 1, 198 RTW89_NET_TYPE_INFRA = 2, 199 RTW89_NET_TYPE_AP_MODE = 3, 200 }; 201 202 enum rtw89_wifi_role { 203 RTW89_WIFI_ROLE_NONE, 204 RTW89_WIFI_ROLE_STATION, 205 RTW89_WIFI_ROLE_AP, 206 RTW89_WIFI_ROLE_AP_VLAN, 207 RTW89_WIFI_ROLE_ADHOC, 208 RTW89_WIFI_ROLE_ADHOC_MASTER, 209 RTW89_WIFI_ROLE_MESH_POINT, 210 RTW89_WIFI_ROLE_MONITOR, 211 RTW89_WIFI_ROLE_P2P_DEVICE, 212 RTW89_WIFI_ROLE_P2P_CLIENT, 213 RTW89_WIFI_ROLE_P2P_GO, 214 RTW89_WIFI_ROLE_NAN, 215 RTW89_WIFI_ROLE_MLME_MAX 216 }; 217 218 enum rtw89_upd_mode { 219 RTW89_ROLE_CREATE, 220 RTW89_ROLE_REMOVE, 221 RTW89_ROLE_TYPE_CHANGE, 222 RTW89_ROLE_INFO_CHANGE, 223 RTW89_ROLE_CON_DISCONN, 224 RTW89_ROLE_BAND_SW, 225 RTW89_ROLE_FW_RESTORE, 226 }; 227 228 enum rtw89_self_role { 229 RTW89_SELF_ROLE_CLIENT, 230 RTW89_SELF_ROLE_AP, 231 RTW89_SELF_ROLE_AP_CLIENT 232 }; 233 234 enum rtw89_msk_sO_el { 235 RTW89_NO_MSK, 236 RTW89_SMA, 237 RTW89_TMA, 238 RTW89_BSSID 239 }; 240 241 enum rtw89_sch_tx_sel { 242 RTW89_SCH_TX_SEL_ALL, 243 RTW89_SCH_TX_SEL_HIQ, 244 RTW89_SCH_TX_SEL_MG0, 245 RTW89_SCH_TX_SEL_MACID, 246 }; 247 248 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 249 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 250 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 251 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 252 */ 253 enum rtw89_add_cam_sec_mode { 254 RTW89_ADDR_CAM_SEC_NONE = 0, 255 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 256 RTW89_ADDR_CAM_SEC_NORMAL = 2, 257 RTW89_ADDR_CAM_SEC_4GROUP = 3, 258 }; 259 260 enum rtw89_sec_key_type { 261 RTW89_SEC_KEY_TYPE_NONE = 0, 262 RTW89_SEC_KEY_TYPE_WEP40 = 1, 263 RTW89_SEC_KEY_TYPE_WEP104 = 2, 264 RTW89_SEC_KEY_TYPE_TKIP = 3, 265 RTW89_SEC_KEY_TYPE_WAPI = 4, 266 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 267 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 268 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 269 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 270 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 271 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 272 }; 273 274 enum rtw89_port { 275 RTW89_PORT_0 = 0, 276 RTW89_PORT_1 = 1, 277 RTW89_PORT_2 = 2, 278 RTW89_PORT_3 = 3, 279 RTW89_PORT_4 = 4, 280 RTW89_PORT_NUM 281 }; 282 283 enum rtw89_band { 284 RTW89_BAND_2G = 0, 285 RTW89_BAND_5G = 1, 286 RTW89_BAND_6G = 2, 287 RTW89_BAND_NUM, 288 }; 289 290 enum rtw89_hw_rate { 291 RTW89_HW_RATE_CCK1 = 0x0, 292 RTW89_HW_RATE_CCK2 = 0x1, 293 RTW89_HW_RATE_CCK5_5 = 0x2, 294 RTW89_HW_RATE_CCK11 = 0x3, 295 RTW89_HW_RATE_OFDM6 = 0x4, 296 RTW89_HW_RATE_OFDM9 = 0x5, 297 RTW89_HW_RATE_OFDM12 = 0x6, 298 RTW89_HW_RATE_OFDM18 = 0x7, 299 RTW89_HW_RATE_OFDM24 = 0x8, 300 RTW89_HW_RATE_OFDM36 = 0x9, 301 RTW89_HW_RATE_OFDM48 = 0xA, 302 RTW89_HW_RATE_OFDM54 = 0xB, 303 RTW89_HW_RATE_MCS0 = 0x80, 304 RTW89_HW_RATE_MCS1 = 0x81, 305 RTW89_HW_RATE_MCS2 = 0x82, 306 RTW89_HW_RATE_MCS3 = 0x83, 307 RTW89_HW_RATE_MCS4 = 0x84, 308 RTW89_HW_RATE_MCS5 = 0x85, 309 RTW89_HW_RATE_MCS6 = 0x86, 310 RTW89_HW_RATE_MCS7 = 0x87, 311 RTW89_HW_RATE_MCS8 = 0x88, 312 RTW89_HW_RATE_MCS9 = 0x89, 313 RTW89_HW_RATE_MCS10 = 0x8A, 314 RTW89_HW_RATE_MCS11 = 0x8B, 315 RTW89_HW_RATE_MCS12 = 0x8C, 316 RTW89_HW_RATE_MCS13 = 0x8D, 317 RTW89_HW_RATE_MCS14 = 0x8E, 318 RTW89_HW_RATE_MCS15 = 0x8F, 319 RTW89_HW_RATE_MCS16 = 0x90, 320 RTW89_HW_RATE_MCS17 = 0x91, 321 RTW89_HW_RATE_MCS18 = 0x92, 322 RTW89_HW_RATE_MCS19 = 0x93, 323 RTW89_HW_RATE_MCS20 = 0x94, 324 RTW89_HW_RATE_MCS21 = 0x95, 325 RTW89_HW_RATE_MCS22 = 0x96, 326 RTW89_HW_RATE_MCS23 = 0x97, 327 RTW89_HW_RATE_MCS24 = 0x98, 328 RTW89_HW_RATE_MCS25 = 0x99, 329 RTW89_HW_RATE_MCS26 = 0x9A, 330 RTW89_HW_RATE_MCS27 = 0x9B, 331 RTW89_HW_RATE_MCS28 = 0x9C, 332 RTW89_HW_RATE_MCS29 = 0x9D, 333 RTW89_HW_RATE_MCS30 = 0x9E, 334 RTW89_HW_RATE_MCS31 = 0x9F, 335 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 336 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 337 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 338 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 339 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 340 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 341 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 342 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 343 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 344 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 345 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 346 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 347 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 348 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 349 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 350 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 351 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 352 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 353 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 354 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 355 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 356 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 357 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 358 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 359 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 360 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 361 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 362 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 363 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 364 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 365 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 366 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 367 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 368 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 369 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 370 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 371 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 372 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 373 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 374 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 375 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 376 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 377 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 378 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 379 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 380 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 381 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 382 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 383 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 384 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 385 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 386 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 387 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 388 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 389 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 390 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 391 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 392 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 393 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 394 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 395 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 396 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 397 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 398 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 399 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 400 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 401 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 402 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 403 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 404 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 405 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 406 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 407 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 408 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 409 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 410 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 411 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 412 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 413 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 414 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 415 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 416 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 417 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 418 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 419 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 420 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 421 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 422 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 423 424 RTW89_HW_RATE_V1_MCS0 = 0x100, 425 RTW89_HW_RATE_V1_MCS1 = 0x101, 426 RTW89_HW_RATE_V1_MCS2 = 0x102, 427 RTW89_HW_RATE_V1_MCS3 = 0x103, 428 RTW89_HW_RATE_V1_MCS4 = 0x104, 429 RTW89_HW_RATE_V1_MCS5 = 0x105, 430 RTW89_HW_RATE_V1_MCS6 = 0x106, 431 RTW89_HW_RATE_V1_MCS7 = 0x107, 432 RTW89_HW_RATE_V1_MCS8 = 0x108, 433 RTW89_HW_RATE_V1_MCS9 = 0x109, 434 RTW89_HW_RATE_V1_MCS10 = 0x10A, 435 RTW89_HW_RATE_V1_MCS11 = 0x10B, 436 RTW89_HW_RATE_V1_MCS12 = 0x10C, 437 RTW89_HW_RATE_V1_MCS13 = 0x10D, 438 RTW89_HW_RATE_V1_MCS14 = 0x10E, 439 RTW89_HW_RATE_V1_MCS15 = 0x10F, 440 RTW89_HW_RATE_V1_MCS16 = 0x110, 441 RTW89_HW_RATE_V1_MCS17 = 0x111, 442 RTW89_HW_RATE_V1_MCS18 = 0x112, 443 RTW89_HW_RATE_V1_MCS19 = 0x113, 444 RTW89_HW_RATE_V1_MCS20 = 0x114, 445 RTW89_HW_RATE_V1_MCS21 = 0x115, 446 RTW89_HW_RATE_V1_MCS22 = 0x116, 447 RTW89_HW_RATE_V1_MCS23 = 0x117, 448 RTW89_HW_RATE_V1_MCS24 = 0x118, 449 RTW89_HW_RATE_V1_MCS25 = 0x119, 450 RTW89_HW_RATE_V1_MCS26 = 0x11A, 451 RTW89_HW_RATE_V1_MCS27 = 0x11B, 452 RTW89_HW_RATE_V1_MCS28 = 0x11C, 453 RTW89_HW_RATE_V1_MCS29 = 0x11D, 454 RTW89_HW_RATE_V1_MCS30 = 0x11E, 455 RTW89_HW_RATE_V1_MCS31 = 0x11F, 456 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 457 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 468 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 469 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 480 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 481 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 492 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 493 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 504 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 505 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 516 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 517 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 528 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 529 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 540 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 541 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 552 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 553 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 568 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 569 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 582 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 583 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 596 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 597 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 610 611 RTW89_HW_RATE_NR, 612 RTW89_HW_RATE_INVAL, 613 614 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 615 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 616 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 617 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 618 }; 619 620 /* 2G channels, 621 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 622 */ 623 #define RTW89_2G_CH_NUM 14 624 625 /* 5G channels, 626 * 36, 38, 40, 42, 44, 46, 48, 50, 627 * 52, 54, 56, 58, 60, 62, 64, 628 * 100, 102, 104, 106, 108, 110, 112, 114, 629 * 116, 118, 120, 122, 124, 126, 128, 130, 630 * 132, 134, 136, 138, 140, 142, 144, 631 * 149, 151, 153, 155, 157, 159, 161, 163, 632 * 165, 167, 169, 171, 173, 175, 177 633 */ 634 #define RTW89_5G_CH_NUM 53 635 636 /* 6G channels, 637 * 1, 3, 5, 7, 9, 11, 13, 15, 638 * 17, 19, 21, 23, 25, 27, 29, 33, 639 * 35, 37, 39, 41, 43, 45, 47, 49, 640 * 51, 53, 55, 57, 59, 61, 65, 67, 641 * 69, 71, 73, 75, 77, 79, 81, 83, 642 * 85, 87, 89, 91, 93, 97, 99, 101, 643 * 103, 105, 107, 109, 111, 113, 115, 117, 644 * 119, 121, 123, 125, 129, 131, 133, 135, 645 * 137, 139, 141, 143, 145, 147, 149, 151, 646 * 153, 155, 157, 161, 163, 165, 167, 169, 647 * 171, 173, 175, 177, 179, 181, 183, 185, 648 * 187, 189, 193, 195, 197, 199, 201, 203, 649 * 205, 207, 209, 211, 213, 215, 217, 219, 650 * 221, 225, 227, 229, 231, 233, 235, 237, 651 * 239, 241, 243, 245, 247, 249, 251, 253, 652 */ 653 #define RTW89_6G_CH_NUM 120 654 655 enum rtw89_rate_section { 656 RTW89_RS_CCK, 657 RTW89_RS_OFDM, 658 RTW89_RS_MCS, /* for HT/VHT/HE */ 659 RTW89_RS_HEDCM, 660 RTW89_RS_OFFSET, 661 RTW89_RS_NUM, 662 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 663 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 664 }; 665 666 enum rtw89_rate_offset_indexes { 667 RTW89_RATE_OFFSET_HE, 668 RTW89_RATE_OFFSET_VHT, 669 RTW89_RATE_OFFSET_HT, 670 RTW89_RATE_OFFSET_OFDM, 671 RTW89_RATE_OFFSET_CCK, 672 RTW89_RATE_OFFSET_DLRU_EHT, 673 RTW89_RATE_OFFSET_DLRU_HE, 674 RTW89_RATE_OFFSET_EHT, 675 __RTW89_RATE_OFFSET_NUM, 676 677 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 678 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 679 }; 680 681 enum rtw89_rate_num { 682 RTW89_RATE_CCK_NUM = 4, 683 RTW89_RATE_OFDM_NUM = 8, 684 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 685 686 RTW89_RATE_MCS_NUM_AX = 12, 687 RTW89_RATE_MCS_NUM_BE = 16, 688 __RTW89_RATE_MCS_NUM = 16, 689 }; 690 691 enum rtw89_nss { 692 RTW89_NSS_1 = 0, 693 RTW89_NSS_2 = 1, 694 /* HE DCM only support 1ss and 2ss */ 695 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 696 RTW89_NSS_3 = 2, 697 RTW89_NSS_4 = 3, 698 RTW89_NSS_NUM, 699 }; 700 701 enum rtw89_ntx { 702 RTW89_1TX = 0, 703 RTW89_2TX = 1, 704 RTW89_NTX_NUM, 705 }; 706 707 enum rtw89_beamforming_type { 708 RTW89_NONBF = 0, 709 RTW89_BF = 1, 710 RTW89_BF_NUM, 711 }; 712 713 enum rtw89_ofdma_type { 714 RTW89_NON_OFDMA = 0, 715 RTW89_OFDMA = 1, 716 RTW89_OFDMA_NUM, 717 }; 718 719 enum rtw89_regulation_type { 720 RTW89_WW = 0, 721 RTW89_ETSI = 1, 722 RTW89_FCC = 2, 723 RTW89_MKK = 3, 724 RTW89_NA = 4, 725 RTW89_IC = 5, 726 RTW89_KCC = 6, 727 RTW89_ACMA = 7, 728 RTW89_NCC = 8, 729 RTW89_MEXICO = 9, 730 RTW89_CHILE = 10, 731 RTW89_UKRAINE = 11, 732 RTW89_CN = 12, 733 RTW89_QATAR = 13, 734 RTW89_UK = 14, 735 RTW89_THAILAND = 15, 736 RTW89_REGD_NUM, 737 }; 738 739 enum rtw89_reg_6ghz_power { 740 RTW89_REG_6GHZ_POWER_VLP = 0, 741 RTW89_REG_6GHZ_POWER_LPI = 1, 742 RTW89_REG_6GHZ_POWER_STD = 2, 743 744 NUM_OF_RTW89_REG_6GHZ_POWER, 745 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 746 }; 747 748 enum rtw89_fw_pkt_ofld_type { 749 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 750 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 751 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 752 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 753 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 754 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 755 RTW89_PKT_OFLD_TYPE_NDP = 6, 756 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 757 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 758 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 759 RTW89_PKT_OFLD_TYPE_NUM, 760 }; 761 762 struct rtw89_txpwr_byrate { 763 s8 cck[RTW89_RATE_CCK_NUM]; 764 s8 ofdm[RTW89_RATE_OFDM_NUM]; 765 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 766 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 767 s8 offset[__RTW89_RATE_OFFSET_NUM]; 768 s8 trap; 769 }; 770 771 struct rtw89_rate_desc { 772 enum rtw89_nss nss; 773 enum rtw89_rate_section rs; 774 enum rtw89_ofdma_type ofdma; 775 u8 idx; 776 }; 777 778 #define PHY_STS_HDR_LEN 8 779 #define RF_PATH_MAX 4 780 #define RTW89_MAX_PPDU_CNT 8 781 struct rtw89_rx_phy_ppdu { 782 void *buf; 783 u32 len; 784 u8 rssi_avg; 785 u8 rssi[RF_PATH_MAX]; 786 u8 mac_id; 787 u8 chan_idx; 788 u8 ie; 789 u16 rate; 790 struct { 791 bool has; 792 u8 avg_snr; 793 u8 evm_max; 794 u8 evm_min; 795 } ofdm; 796 bool to_self; 797 bool valid; 798 }; 799 800 enum rtw89_mac_idx { 801 RTW89_MAC_0 = 0, 802 RTW89_MAC_1 = 1, 803 RTW89_MAC_NUM, 804 }; 805 806 enum rtw89_phy_idx { 807 RTW89_PHY_0 = 0, 808 RTW89_PHY_1 = 1, 809 RTW89_PHY_MAX 810 }; 811 812 enum rtw89_sub_entity_idx { 813 RTW89_SUB_ENTITY_0 = 0, 814 RTW89_SUB_ENTITY_1 = 1, 815 816 NUM_OF_RTW89_SUB_ENTITY, 817 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 818 }; 819 820 enum rtw89_rf_path { 821 RF_PATH_A = 0, 822 RF_PATH_B = 1, 823 RF_PATH_C = 2, 824 RF_PATH_D = 3, 825 RF_PATH_AB, 826 RF_PATH_AC, 827 RF_PATH_AD, 828 RF_PATH_BC, 829 RF_PATH_BD, 830 RF_PATH_CD, 831 RF_PATH_ABC, 832 RF_PATH_ABD, 833 RF_PATH_ACD, 834 RF_PATH_BCD, 835 RF_PATH_ABCD, 836 }; 837 838 enum rtw89_rf_path_bit { 839 RF_A = BIT(0), 840 RF_B = BIT(1), 841 RF_C = BIT(2), 842 RF_D = BIT(3), 843 844 RF_AB = (RF_A | RF_B), 845 RF_AC = (RF_A | RF_C), 846 RF_AD = (RF_A | RF_D), 847 RF_BC = (RF_B | RF_C), 848 RF_BD = (RF_B | RF_D), 849 RF_CD = (RF_C | RF_D), 850 851 RF_ABC = (RF_A | RF_B | RF_C), 852 RF_ABD = (RF_A | RF_B | RF_D), 853 RF_ACD = (RF_A | RF_C | RF_D), 854 RF_BCD = (RF_B | RF_C | RF_D), 855 856 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 857 }; 858 859 enum rtw89_bandwidth { 860 RTW89_CHANNEL_WIDTH_20 = 0, 861 RTW89_CHANNEL_WIDTH_40 = 1, 862 RTW89_CHANNEL_WIDTH_80 = 2, 863 RTW89_CHANNEL_WIDTH_160 = 3, 864 RTW89_CHANNEL_WIDTH_320 = 4, 865 866 /* keep index order above */ 867 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 868 869 RTW89_CHANNEL_WIDTH_80_80 = 5, 870 RTW89_CHANNEL_WIDTH_5 = 6, 871 RTW89_CHANNEL_WIDTH_10 = 7, 872 }; 873 874 enum rtw89_ps_mode { 875 RTW89_PS_MODE_NONE = 0, 876 RTW89_PS_MODE_RFOFF = 1, 877 RTW89_PS_MODE_CLK_GATED = 2, 878 RTW89_PS_MODE_PWR_GATED = 3, 879 }; 880 881 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 882 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 883 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 884 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 885 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 886 887 enum rtw89_ru_bandwidth { 888 RTW89_RU26 = 0, 889 RTW89_RU52 = 1, 890 RTW89_RU106 = 2, 891 RTW89_RU52_26 = 3, 892 RTW89_RU106_26 = 4, 893 RTW89_RU_NUM, 894 }; 895 896 enum rtw89_sc_offset { 897 RTW89_SC_DONT_CARE = 0, 898 RTW89_SC_20_UPPER = 1, 899 RTW89_SC_20_LOWER = 2, 900 RTW89_SC_20_UPMOST = 3, 901 RTW89_SC_20_LOWEST = 4, 902 RTW89_SC_20_UP2X = 5, 903 RTW89_SC_20_LOW2X = 6, 904 RTW89_SC_20_UP3X = 7, 905 RTW89_SC_20_LOW3X = 8, 906 RTW89_SC_40_UPPER = 9, 907 RTW89_SC_40_LOWER = 10, 908 }; 909 910 enum rtw89_wow_flags { 911 RTW89_WOW_FLAG_EN_MAGIC_PKT, 912 RTW89_WOW_FLAG_EN_REKEY_PKT, 913 RTW89_WOW_FLAG_EN_DISCONNECT, 914 RTW89_WOW_FLAG_NUM, 915 }; 916 917 struct rtw89_chan { 918 u8 channel; 919 u8 primary_channel; 920 enum rtw89_band band_type; 921 enum rtw89_bandwidth band_width; 922 923 /* The follow-up are derived from the above. We must ensure that it 924 * is assigned correctly in rtw89_chan_create() if new one is added. 925 */ 926 u32 freq; 927 enum rtw89_subband subband_type; 928 enum rtw89_sc_offset pri_ch_idx; 929 u8 pri_sb_idx; 930 }; 931 932 struct rtw89_chan_rcd { 933 u8 prev_primary_channel; 934 enum rtw89_band prev_band_type; 935 bool band_changed; 936 }; 937 938 struct rtw89_channel_help_params { 939 u32 tx_en; 940 }; 941 942 struct rtw89_port_reg { 943 u32 port_cfg; 944 u32 tbtt_prohib; 945 u32 bcn_area; 946 u32 bcn_early; 947 u32 tbtt_early; 948 u32 tbtt_agg; 949 u32 bcn_space; 950 u32 bcn_forcetx; 951 u32 bcn_err_cnt; 952 u32 bcn_err_flag; 953 u32 dtim_ctrl; 954 u32 tbtt_shift; 955 u32 bcn_cnt_tmr; 956 u32 tsftr_l; 957 u32 tsftr_h; 958 u32 md_tsft; 959 u32 bss_color; 960 u32 mbssid; 961 u32 mbssid_drop; 962 u32 tsf_sync; 963 u32 ptcl_dbg; 964 u32 ptcl_dbg_info; 965 u32 bcn_drop_all; 966 u32 hiq_win[RTW89_PORT_NUM]; 967 }; 968 969 struct rtw89_txwd_body { 970 __le32 dword0; 971 __le32 dword1; 972 __le32 dword2; 973 __le32 dword3; 974 __le32 dword4; 975 __le32 dword5; 976 } __packed; 977 978 struct rtw89_txwd_body_v1 { 979 __le32 dword0; 980 __le32 dword1; 981 __le32 dword2; 982 __le32 dword3; 983 __le32 dword4; 984 __le32 dword5; 985 __le32 dword6; 986 __le32 dword7; 987 } __packed; 988 989 struct rtw89_txwd_body_v2 { 990 __le32 dword0; 991 __le32 dword1; 992 __le32 dword2; 993 __le32 dword3; 994 __le32 dword4; 995 __le32 dword5; 996 __le32 dword6; 997 __le32 dword7; 998 } __packed; 999 1000 struct rtw89_txwd_info { 1001 __le32 dword0; 1002 __le32 dword1; 1003 __le32 dword2; 1004 __le32 dword3; 1005 __le32 dword4; 1006 __le32 dword5; 1007 } __packed; 1008 1009 struct rtw89_txwd_info_v2 { 1010 __le32 dword0; 1011 __le32 dword1; 1012 __le32 dword2; 1013 __le32 dword3; 1014 __le32 dword4; 1015 __le32 dword5; 1016 __le32 dword6; 1017 __le32 dword7; 1018 } __packed; 1019 1020 struct rtw89_rx_desc_info { 1021 u16 pkt_size; 1022 u8 pkt_type; 1023 u8 drv_info_size; 1024 u8 phy_rpt_size; 1025 u8 hdr_cnv_size; 1026 u8 shift; 1027 u8 wl_hd_iv_len; 1028 bool long_rxdesc; 1029 bool bb_sel; 1030 bool mac_info_valid; 1031 u16 data_rate; 1032 u8 gi_ltf; 1033 u8 bw; 1034 u32 free_run_cnt; 1035 u8 user_id; 1036 bool sr_en; 1037 u8 ppdu_cnt; 1038 u8 ppdu_type; 1039 bool icv_err; 1040 bool crc32_err; 1041 bool hw_dec; 1042 bool sw_dec; 1043 bool addr1_match; 1044 u8 frag; 1045 u16 seq; 1046 u8 frame_type; 1047 u8 rx_pl_id; 1048 bool addr_cam_valid; 1049 u8 addr_cam_id; 1050 u8 sec_cam_id; 1051 u8 mac_id; 1052 u16 offset; 1053 u16 rxd_len; 1054 bool ready; 1055 }; 1056 1057 struct rtw89_rxdesc_short { 1058 __le32 dword0; 1059 __le32 dword1; 1060 __le32 dword2; 1061 __le32 dword3; 1062 } __packed; 1063 1064 struct rtw89_rxdesc_short_v2 { 1065 __le32 dword0; 1066 __le32 dword1; 1067 __le32 dword2; 1068 __le32 dword3; 1069 __le32 dword4; 1070 __le32 dword5; 1071 } __packed; 1072 1073 struct rtw89_rxdesc_long { 1074 __le32 dword0; 1075 __le32 dword1; 1076 __le32 dword2; 1077 __le32 dword3; 1078 __le32 dword4; 1079 __le32 dword5; 1080 __le32 dword6; 1081 __le32 dword7; 1082 } __packed; 1083 1084 struct rtw89_rxdesc_long_v2 { 1085 __le32 dword0; 1086 __le32 dword1; 1087 __le32 dword2; 1088 __le32 dword3; 1089 __le32 dword4; 1090 __le32 dword5; 1091 __le32 dword6; 1092 __le32 dword7; 1093 __le32 dword8; 1094 __le32 dword9; 1095 } __packed; 1096 1097 struct rtw89_tx_desc_info { 1098 u16 pkt_size; 1099 u8 wp_offset; 1100 u8 mac_id; 1101 u8 qsel; 1102 u8 ch_dma; 1103 u8 hdr_llc_len; 1104 bool is_bmc; 1105 bool en_wd_info; 1106 bool wd_page; 1107 bool use_rate; 1108 bool dis_data_fb; 1109 bool tid_indicate; 1110 bool agg_en; 1111 bool bk; 1112 u8 ampdu_density; 1113 u8 ampdu_num; 1114 bool sec_en; 1115 u8 addr_info_nr; 1116 u8 sec_keyid; 1117 u8 sec_type; 1118 u8 sec_cam_idx; 1119 u8 sec_seq[6]; 1120 u16 data_rate; 1121 u16 data_retry_lowest_rate; 1122 bool fw_dl; 1123 u16 seq; 1124 bool a_ctrl_bsr; 1125 u8 hw_ssn_sel; 1126 #define RTW89_MGMT_HW_SSN_SEL 1 1127 u8 hw_seq_mode; 1128 #define RTW89_MGMT_HW_SEQ_MODE 1 1129 bool hiq; 1130 u8 port; 1131 bool er_cap; 1132 }; 1133 1134 struct rtw89_core_tx_request { 1135 enum rtw89_core_tx_type tx_type; 1136 1137 struct sk_buff *skb; 1138 struct ieee80211_vif *vif; 1139 struct ieee80211_sta *sta; 1140 struct rtw89_tx_desc_info desc_info; 1141 }; 1142 1143 struct rtw89_txq { 1144 struct list_head list; 1145 unsigned long flags; 1146 int wait_cnt; 1147 }; 1148 1149 struct rtw89_mac_ax_gnt { 1150 u8 gnt_bt_sw_en; 1151 u8 gnt_bt; 1152 u8 gnt_wl_sw_en; 1153 u8 gnt_wl; 1154 } __packed; 1155 1156 struct rtw89_mac_ax_wl_act { 1157 u8 wlan_act_en; 1158 u8 wlan_act; 1159 }; 1160 1161 #define RTW89_MAC_AX_COEX_GNT_NR 2 1162 struct rtw89_mac_ax_coex_gnt { 1163 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1164 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1165 }; 1166 1167 enum rtw89_btc_ncnt { 1168 BTC_NCNT_POWER_ON = 0x0, 1169 BTC_NCNT_POWER_OFF, 1170 BTC_NCNT_INIT_COEX, 1171 BTC_NCNT_SCAN_START, 1172 BTC_NCNT_SCAN_FINISH, 1173 BTC_NCNT_SPECIAL_PACKET, 1174 BTC_NCNT_SWITCH_BAND, 1175 BTC_NCNT_RFK_TIMEOUT, 1176 BTC_NCNT_SHOW_COEX_INFO, 1177 BTC_NCNT_ROLE_INFO, 1178 BTC_NCNT_CONTROL, 1179 BTC_NCNT_RADIO_STATE, 1180 BTC_NCNT_CUSTOMERIZE, 1181 BTC_NCNT_WL_RFK, 1182 BTC_NCNT_WL_STA, 1183 BTC_NCNT_FWINFO, 1184 BTC_NCNT_TIMER, 1185 BTC_NCNT_NUM 1186 }; 1187 1188 enum rtw89_btc_btinfo { 1189 BTC_BTINFO_L0 = 0, 1190 BTC_BTINFO_L1, 1191 BTC_BTINFO_L2, 1192 BTC_BTINFO_L3, 1193 BTC_BTINFO_H0, 1194 BTC_BTINFO_H1, 1195 BTC_BTINFO_H2, 1196 BTC_BTINFO_H3, 1197 BTC_BTINFO_MAX 1198 }; 1199 1200 enum rtw89_btc_dcnt { 1201 BTC_DCNT_RUN = 0x0, 1202 BTC_DCNT_CX_RUNINFO, 1203 BTC_DCNT_RPT, 1204 BTC_DCNT_RPT_HANG, 1205 BTC_DCNT_CYCLE, 1206 BTC_DCNT_CYCLE_HANG, 1207 BTC_DCNT_W1, 1208 BTC_DCNT_W1_HANG, 1209 BTC_DCNT_B1, 1210 BTC_DCNT_B1_HANG, 1211 BTC_DCNT_TDMA_NONSYNC, 1212 BTC_DCNT_SLOT_NONSYNC, 1213 BTC_DCNT_BTCNT_HANG, 1214 BTC_DCNT_WL_SLOT_DRIFT, 1215 BTC_DCNT_WL_STA_LAST, 1216 BTC_DCNT_BT_SLOT_DRIFT, 1217 BTC_DCNT_BT_SLOT_FLOOD, 1218 BTC_DCNT_FDDT_TRIG, 1219 BTC_DCNT_E2G, 1220 BTC_DCNT_E2G_HANG, 1221 BTC_DCNT_NUM 1222 }; 1223 1224 enum rtw89_btc_wl_state_cnt { 1225 BTC_WCNT_SCANAP = 0x0, 1226 BTC_WCNT_DHCP, 1227 BTC_WCNT_EAPOL, 1228 BTC_WCNT_ARP, 1229 BTC_WCNT_SCBDUPDATE, 1230 BTC_WCNT_RFK_REQ, 1231 BTC_WCNT_RFK_GO, 1232 BTC_WCNT_RFK_REJECT, 1233 BTC_WCNT_RFK_TIMEOUT, 1234 BTC_WCNT_CH_UPDATE, 1235 BTC_WCNT_DBCC_ALL_2G, 1236 BTC_WCNT_DBCC_CHG, 1237 BTC_WCNT_RX_OK_LAST, 1238 BTC_WCNT_RX_OK_LAST2S, 1239 BTC_WCNT_RX_ERR_LAST, 1240 BTC_WCNT_RX_ERR_LAST2S, 1241 BTC_WCNT_RX_LAST, 1242 BTC_WCNT_NUM 1243 }; 1244 1245 enum rtw89_btc_bt_state_cnt { 1246 BTC_BCNT_RETRY = 0x0, 1247 BTC_BCNT_REINIT, 1248 BTC_BCNT_REENABLE, 1249 BTC_BCNT_SCBDREAD, 1250 BTC_BCNT_RELINK, 1251 BTC_BCNT_IGNOWL, 1252 BTC_BCNT_INQPAG, 1253 BTC_BCNT_INQ, 1254 BTC_BCNT_PAGE, 1255 BTC_BCNT_ROLESW, 1256 BTC_BCNT_AFH, 1257 BTC_BCNT_INFOUPDATE, 1258 BTC_BCNT_INFOSAME, 1259 BTC_BCNT_SCBDUPDATE, 1260 BTC_BCNT_HIPRI_TX, 1261 BTC_BCNT_HIPRI_RX, 1262 BTC_BCNT_LOPRI_TX, 1263 BTC_BCNT_LOPRI_RX, 1264 BTC_BCNT_POLUT, 1265 BTC_BCNT_RATECHG, 1266 BTC_BCNT_NUM 1267 }; 1268 1269 enum rtw89_btc_bt_profile { 1270 BTC_BT_NOPROFILE = 0, 1271 BTC_BT_HFP = BIT(0), 1272 BTC_BT_HID = BIT(1), 1273 BTC_BT_A2DP = BIT(2), 1274 BTC_BT_PAN = BIT(3), 1275 BTC_PROFILE_MAX = 4, 1276 }; 1277 1278 struct rtw89_btc_ant_info { 1279 u8 type; /* shared, dedicated */ 1280 u8 num; 1281 u8 isolation; 1282 1283 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1284 u8 diversity: 1; 1285 u8 btg_pos: 2; 1286 u8 stream_cnt: 4; 1287 }; 1288 1289 struct rtw89_btc_ant_info_v7 { 1290 u8 type; /* shared, dedicated(non-shared) */ 1291 u8 num; /* antenna count */ 1292 u8 isolation; 1293 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1294 1295 u8 diversity; /* only for wifi use 1-antenna */ 1296 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1297 u8 stream_cnt; /* spatial_stream count */ 1298 u8 rsvd; 1299 } __packed; 1300 1301 enum rtw89_tfc_dir { 1302 RTW89_TFC_UL, 1303 RTW89_TFC_DL, 1304 }; 1305 1306 struct rtw89_btc_wl_smap { 1307 u32 busy: 1; 1308 u32 scan: 1; 1309 u32 connecting: 1; 1310 u32 roaming: 1; 1311 u32 _4way: 1; 1312 u32 rf_off: 1; 1313 u32 lps: 2; 1314 u32 ips: 1; 1315 u32 init_ok: 1; 1316 u32 traffic_dir : 2; 1317 u32 rf_off_pre: 1; 1318 u32 lps_pre: 2; 1319 }; 1320 1321 enum rtw89_tfc_lv { 1322 RTW89_TFC_IDLE, 1323 RTW89_TFC_ULTRA_LOW, 1324 RTW89_TFC_LOW, 1325 RTW89_TFC_MID, 1326 RTW89_TFC_HIGH, 1327 }; 1328 1329 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1330 DECLARE_EWMA(tp, 10, 2); 1331 1332 struct rtw89_traffic_stats { 1333 /* units in bytes */ 1334 u64 tx_unicast; 1335 u64 rx_unicast; 1336 u32 tx_avg_len; 1337 u32 rx_avg_len; 1338 1339 /* count for packets */ 1340 u64 tx_cnt; 1341 u64 rx_cnt; 1342 1343 /* units in Mbps */ 1344 u32 tx_throughput; 1345 u32 rx_throughput; 1346 u32 tx_throughput_raw; 1347 u32 rx_throughput_raw; 1348 1349 u32 rx_tf_acc; 1350 u32 rx_tf_periodic; 1351 1352 enum rtw89_tfc_lv tx_tfc_lv; 1353 enum rtw89_tfc_lv rx_tfc_lv; 1354 struct ewma_tp tx_ewma_tp; 1355 struct ewma_tp rx_ewma_tp; 1356 1357 u16 tx_rate; 1358 u16 rx_rate; 1359 }; 1360 1361 struct rtw89_btc_chdef { 1362 u8 center_ch; 1363 u8 band; 1364 u8 chan; 1365 enum rtw89_sc_offset offset; 1366 enum rtw89_bandwidth bw; 1367 }; 1368 1369 struct rtw89_btc_statistic { 1370 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1371 struct rtw89_traffic_stats traffic; 1372 }; 1373 1374 #define BTC_WL_RSSI_THMAX 4 1375 1376 struct rtw89_btc_wl_link_info { 1377 struct rtw89_btc_chdef chdef; 1378 struct rtw89_btc_statistic stat; 1379 enum rtw89_tfc_dir dir; 1380 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1381 u8 mac_addr[ETH_ALEN]; 1382 u8 busy; 1383 u8 ch; 1384 u8 bw; 1385 u8 band; 1386 u8 role; 1387 u8 pid; 1388 u8 phy; 1389 u8 dtim_period; 1390 u8 mode; 1391 u8 tx_1ss_limit; 1392 1393 u8 mac_id; 1394 u8 tx_retry; 1395 1396 u32 bcn_period; 1397 u32 busy_t; 1398 u32 tx_time; 1399 u32 client_cnt; 1400 u32 rx_rate_drop_cnt; 1401 u32 noa_duration; 1402 1403 u32 active: 1; 1404 u32 noa: 1; 1405 u32 client_ps: 1; 1406 u32 connected: 2; 1407 }; 1408 1409 union rtw89_btc_wl_state_map { 1410 u32 val; 1411 struct rtw89_btc_wl_smap map; 1412 }; 1413 1414 struct rtw89_btc_bt_hfp_desc { 1415 u32 exist: 1; 1416 u32 type: 2; 1417 u32 rsvd: 29; 1418 }; 1419 1420 struct rtw89_btc_bt_hid_desc { 1421 u32 exist: 1; 1422 u32 slot_info: 2; 1423 u32 pair_cnt: 2; 1424 u32 type: 8; 1425 u32 rsvd: 19; 1426 }; 1427 1428 struct rtw89_btc_bt_a2dp_desc { 1429 u8 exist: 1; 1430 u8 exist_last: 1; 1431 u8 play_latency: 1; 1432 u8 type: 3; 1433 u8 active: 1; 1434 u8 sink: 1; 1435 1436 u8 bitpool; 1437 u16 vendor_id; 1438 u32 device_name; 1439 u32 flush_time; 1440 }; 1441 1442 struct rtw89_btc_bt_pan_desc { 1443 u32 exist: 1; 1444 u32 type: 1; 1445 u32 active: 1; 1446 u32 rsvd: 29; 1447 }; 1448 1449 struct rtw89_btc_bt_rfk_info { 1450 u32 run: 1; 1451 u32 req: 1; 1452 u32 timeout: 1; 1453 u32 rsvd: 29; 1454 }; 1455 1456 union rtw89_btc_bt_rfk_info_map { 1457 u32 val; 1458 struct rtw89_btc_bt_rfk_info map; 1459 }; 1460 1461 struct rtw89_btc_bt_ver_info { 1462 u32 fw_coex; /* match with which coex_ver */ 1463 u32 fw; 1464 }; 1465 1466 struct rtw89_btc_bool_sta_chg { 1467 u32 now: 1; 1468 u32 last: 1; 1469 u32 remain: 1; 1470 u32 srvd: 29; 1471 }; 1472 1473 struct rtw89_btc_u8_sta_chg { 1474 u8 now; 1475 u8 last; 1476 u8 remain; 1477 u8 rsvd; 1478 }; 1479 1480 struct rtw89_btc_wl_scan_info { 1481 u8 band[RTW89_PHY_MAX]; 1482 u8 phy_map; 1483 u8 rsvd; 1484 }; 1485 1486 struct rtw89_btc_wl_dbcc_info { 1487 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1488 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1489 u8 real_band[RTW89_PHY_MAX]; 1490 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1491 }; 1492 1493 struct rtw89_btc_wl_active_role { 1494 u8 connected: 1; 1495 u8 pid: 3; 1496 u8 phy: 1; 1497 u8 noa: 1; 1498 u8 band: 2; 1499 1500 u8 client_ps: 1; 1501 u8 bw: 7; 1502 1503 u8 role; 1504 u8 ch; 1505 1506 u16 tx_lvl; 1507 u16 rx_lvl; 1508 u16 tx_rate; 1509 u16 rx_rate; 1510 }; 1511 1512 struct rtw89_btc_wl_active_role_v1 { 1513 u8 connected: 1; 1514 u8 pid: 3; 1515 u8 phy: 1; 1516 u8 noa: 1; 1517 u8 band: 2; 1518 1519 u8 client_ps: 1; 1520 u8 bw: 7; 1521 1522 u8 role; 1523 u8 ch; 1524 1525 u16 tx_lvl; 1526 u16 rx_lvl; 1527 u16 tx_rate; 1528 u16 rx_rate; 1529 1530 u32 noa_duration; /* ms */ 1531 }; 1532 1533 struct rtw89_btc_wl_active_role_v2 { 1534 u8 connected: 1; 1535 u8 pid: 3; 1536 u8 phy: 1; 1537 u8 noa: 1; 1538 u8 band: 2; 1539 1540 u8 client_ps: 1; 1541 u8 bw: 7; 1542 1543 u8 role; 1544 u8 ch; 1545 1546 u32 noa_duration; /* ms */ 1547 }; 1548 1549 struct rtw89_btc_wl_role_info_bpos { 1550 u16 none: 1; 1551 u16 station: 1; 1552 u16 ap: 1; 1553 u16 vap: 1; 1554 u16 adhoc: 1; 1555 u16 adhoc_master: 1; 1556 u16 mesh: 1; 1557 u16 moniter: 1; 1558 u16 p2p_device: 1; 1559 u16 p2p_gc: 1; 1560 u16 p2p_go: 1; 1561 u16 nan: 1; 1562 }; 1563 1564 struct rtw89_btc_wl_scc_ctrl { 1565 u8 null_role1; 1566 u8 null_role2; 1567 u8 ebt_null; /* if tx null at EBT slot */ 1568 }; 1569 1570 union rtw89_btc_wl_role_info_map { 1571 u16 val; 1572 struct rtw89_btc_wl_role_info_bpos role; 1573 }; 1574 1575 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1576 u8 connect_cnt; 1577 u8 link_mode; 1578 union rtw89_btc_wl_role_info_map role_map; 1579 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1580 }; 1581 1582 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1583 u8 connect_cnt; 1584 u8 link_mode; 1585 union rtw89_btc_wl_role_info_map role_map; 1586 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1587 u32 mrole_type; /* btc_wl_mrole_type */ 1588 u32 mrole_noa_duration; /* ms */ 1589 1590 u32 dbcc_en: 1; 1591 u32 dbcc_chg: 1; 1592 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1593 u32 link_mode_chg: 1; 1594 u32 rsvd: 27; 1595 }; 1596 1597 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1598 u8 connect_cnt; 1599 u8 link_mode; 1600 union rtw89_btc_wl_role_info_map role_map; 1601 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1602 u32 mrole_type; /* btc_wl_mrole_type */ 1603 u32 mrole_noa_duration; /* ms */ 1604 1605 u32 dbcc_en: 1; 1606 u32 dbcc_chg: 1; 1607 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1608 u32 link_mode_chg: 1; 1609 u32 rsvd: 27; 1610 }; 1611 1612 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1613 u8 connected; 1614 u8 pid; 1615 u8 phy; 1616 u8 noa; 1617 1618 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1619 u8 active; /* 0:rlink is under doze */ 1620 u8 bw; /* enum channel_width */ 1621 u8 role; /*enum role_type */ 1622 1623 u8 ch; 1624 u8 noa_dur; /* ms */ 1625 u8 client_cnt; /* for Role = P2P-Go/AP */ 1626 u8 mode; /* wifi protocol */ 1627 } __packed; 1628 1629 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1630 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1631 u8 connect_cnt; 1632 u8 link_mode; 1633 u8 link_mode_chg; 1634 u8 p2p_2g; 1635 1636 u8 pta_req_band; 1637 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1638 u8 dbcc_chg; 1639 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1640 1641 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1642 1643 u32 role_map; 1644 u32 mrole_type; /* btc_wl_mrole_type */ 1645 u32 mrole_noa_duration; /* ms */ 1646 } __packed; 1647 1648 struct rtw89_btc_wl_ver_info { 1649 u32 fw_coex; /* match with which coex_ver */ 1650 u32 fw; 1651 u32 mac; 1652 u32 bb; 1653 u32 rf; 1654 }; 1655 1656 struct rtw89_btc_wl_afh_info { 1657 u8 en; 1658 u8 ch; 1659 u8 bw; 1660 u8 rsvd; 1661 } __packed; 1662 1663 struct rtw89_btc_wl_rfk_info { 1664 u32 state: 2; 1665 u32 path_map: 4; 1666 u32 phy_map: 2; 1667 u32 band: 2; 1668 u32 type: 8; 1669 u32 rsvd: 14; 1670 }; 1671 1672 struct rtw89_btc_bt_smap { 1673 u32 connect: 1; 1674 u32 ble_connect: 1; 1675 u32 acl_busy: 1; 1676 u32 sco_busy: 1; 1677 u32 mesh_busy: 1; 1678 u32 inq_pag: 1; 1679 }; 1680 1681 union rtw89_btc_bt_state_map { 1682 u32 val; 1683 struct rtw89_btc_bt_smap map; 1684 }; 1685 1686 #define BTC_BT_RSSI_THMAX 4 1687 #define BTC_BT_AFH_GROUP 12 1688 #define BTC_BT_AFH_LE_GROUP 5 1689 1690 struct rtw89_btc_bt_link_info { 1691 struct rtw89_btc_u8_sta_chg profile_cnt; 1692 struct rtw89_btc_bool_sta_chg multi_link; 1693 struct rtw89_btc_bool_sta_chg relink; 1694 struct rtw89_btc_bt_hfp_desc hfp_desc; 1695 struct rtw89_btc_bt_hid_desc hid_desc; 1696 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1697 struct rtw89_btc_bt_pan_desc pan_desc; 1698 union rtw89_btc_bt_state_map status; 1699 1700 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1701 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1702 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1703 u8 afh_map[BTC_BT_AFH_GROUP]; 1704 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1705 1706 u32 role_sw: 1; 1707 u32 slave_role: 1; 1708 u32 afh_update: 1; 1709 u32 cqddr: 1; 1710 u32 rssi: 8; 1711 u32 tx_3m: 1; 1712 u32 rsvd: 19; 1713 }; 1714 1715 struct rtw89_btc_3rdcx_info { 1716 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1717 u8 hw_coex; 1718 u16 rsvd; 1719 }; 1720 1721 struct rtw89_btc_dm_emap { 1722 u32 init: 1; 1723 u32 pta_owner: 1; 1724 u32 wl_rfk_timeout: 1; 1725 u32 bt_rfk_timeout: 1; 1726 u32 wl_fw_hang: 1; 1727 u32 cycle_hang: 1; 1728 u32 w1_hang: 1; 1729 u32 b1_hang: 1; 1730 u32 tdma_no_sync: 1; 1731 u32 slot_no_sync: 1; 1732 u32 wl_slot_drift: 1; 1733 u32 bt_slot_drift: 1; 1734 u32 role_num_mismatch: 1; 1735 u32 null1_tx_late: 1; 1736 u32 bt_afh_conflict: 1; 1737 u32 bt_leafh_conflict: 1; 1738 u32 bt_slot_flood: 1; 1739 u32 wl_e2g_hang: 1; 1740 u32 wl_ver_mismatch: 1; 1741 u32 bt_ver_mismatch: 1; 1742 u32 rfe_type0: 1; 1743 u32 h2c_buffer_over: 1; 1744 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1745 u32 wl_no_sta_ntfy: 1; 1746 1747 u32 h2c_bmap_mismatch: 1; 1748 u32 c2h_bmap_mismatch: 1; 1749 u32 h2c_struct_invalid: 1; 1750 u32 c2h_struct_invalid: 1; 1751 u32 h2c_c2h_buffer_mismatch: 1; 1752 }; 1753 1754 union rtw89_btc_dm_error_map { 1755 u32 val; 1756 struct rtw89_btc_dm_emap map; 1757 }; 1758 1759 struct rtw89_btc_rf_para { 1760 u32 tx_pwr_freerun; 1761 u32 rx_gain_freerun; 1762 u32 tx_pwr_perpkt; 1763 u32 rx_gain_perpkt; 1764 }; 1765 1766 struct rtw89_btc_wl_nhm { 1767 u8 instant_wl_nhm_dbm; 1768 u8 instant_wl_nhm_per_mhz; 1769 u16 valid_record_times; 1770 s8 record_pwr[16]; 1771 u8 record_ratio[16]; 1772 s8 pwr; /* dbm_per_MHz */ 1773 u8 ratio; 1774 u8 current_status; 1775 u8 refresh; 1776 bool start_flag; 1777 s8 pwr_max; 1778 s8 pwr_min; 1779 }; 1780 1781 struct rtw89_btc_wl_info { 1782 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1783 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1784 struct rtw89_btc_wl_rfk_info rfk_info; 1785 struct rtw89_btc_wl_ver_info ver_info; 1786 struct rtw89_btc_wl_afh_info afh_info; 1787 struct rtw89_btc_wl_role_info role_info; 1788 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1789 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1790 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1791 struct rtw89_btc_wl_scan_info scan_info; 1792 struct rtw89_btc_wl_dbcc_info dbcc_info; 1793 struct rtw89_btc_rf_para rf_para; 1794 struct rtw89_btc_wl_nhm nhm; 1795 union rtw89_btc_wl_state_map status; 1796 1797 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1798 u8 rssi_level; 1799 u8 cn_report; 1800 u8 coex_mode; 1801 u8 pta_req_mac; 1802 1803 bool is_5g_hi_channel; 1804 bool pta_reg_mac_chg; 1805 bool bg_mode; 1806 bool scbd_change; 1807 u32 scbd; 1808 }; 1809 1810 struct rtw89_btc_module { 1811 struct rtw89_btc_ant_info ant; 1812 u8 rfe_type; 1813 u8 cv; 1814 1815 u8 bt_solo: 1; 1816 u8 bt_pos: 1; 1817 u8 switch_type: 1; 1818 u8 wa_type: 3; 1819 1820 u8 kt_ver_adie; 1821 }; 1822 1823 struct rtw89_btc_module_v7 { 1824 u8 rfe_type; 1825 u8 kt_ver; 1826 u8 bt_solo; 1827 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1828 1829 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1830 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1831 u8 kt_ver_adie; 1832 u8 rsvd; 1833 1834 struct rtw89_btc_ant_info_v7 ant; 1835 } __packed; 1836 1837 union rtw89_btc_module_info { 1838 struct rtw89_btc_module md; 1839 struct rtw89_btc_module_v7 md_v7; 1840 }; 1841 1842 #define RTW89_BTC_DM_MAXSTEP 30 1843 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1844 1845 struct rtw89_btc_dm_step { 1846 u16 step[RTW89_BTC_DM_MAXSTEP]; 1847 u8 step_pos; 1848 bool step_ov; 1849 }; 1850 1851 struct rtw89_btc_init_info { 1852 struct rtw89_btc_module module; 1853 u8 wl_guard_ch; 1854 1855 u8 wl_only: 1; 1856 u8 wl_init_ok: 1; 1857 u8 dbcc_en: 1; 1858 u8 cx_other: 1; 1859 u8 bt_only: 1; 1860 1861 u16 rsvd; 1862 }; 1863 1864 struct rtw89_btc_init_info_v7 { 1865 u8 wl_guard_ch; 1866 u8 wl_only; 1867 u8 wl_init_ok; 1868 u8 rsvd3; 1869 1870 u8 cx_other; 1871 u8 bt_only; 1872 u8 pta_mode; 1873 u8 pta_direction; 1874 1875 struct rtw89_btc_module_v7 module; 1876 } __packed; 1877 1878 union rtw89_btc_init_info_u { 1879 struct rtw89_btc_init_info init; 1880 struct rtw89_btc_init_info_v7 init_v7; 1881 }; 1882 1883 struct rtw89_btc_wl_tx_limit_para { 1884 u16 enable; 1885 u32 tx_time; /* unit: us */ 1886 u16 tx_retry; 1887 }; 1888 1889 enum rtw89_btc_bt_scan_type { 1890 BTC_SCAN_INQ = 0, 1891 BTC_SCAN_PAGE, 1892 BTC_SCAN_BLE, 1893 BTC_SCAN_INIT, 1894 BTC_SCAN_TV, 1895 BTC_SCAN_ADV, 1896 BTC_SCAN_MAX1, 1897 }; 1898 1899 enum rtw89_btc_ble_scan_type { 1900 CXSCAN_BG = 0, 1901 CXSCAN_INIT, 1902 CXSCAN_LE, 1903 CXSCAN_MAX 1904 }; 1905 1906 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1907 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1908 1909 struct rtw89_btc_bt_scan_info_v1 { 1910 __le16 win; 1911 __le16 intvl; 1912 __le32 flags; 1913 } __packed; 1914 1915 struct rtw89_btc_bt_scan_info_v2 { 1916 __le16 win; 1917 __le16 intvl; 1918 } __packed; 1919 1920 struct rtw89_btc_fbtc_btscan_v1 { 1921 u8 fver; /* btc_ver::fcxbtscan */ 1922 u8 rsvd; 1923 __le16 rsvd2; 1924 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1925 } __packed; 1926 1927 struct rtw89_btc_fbtc_btscan_v2 { 1928 u8 fver; /* btc_ver::fcxbtscan */ 1929 u8 type; 1930 __le16 rsvd2; 1931 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1932 } __packed; 1933 1934 union rtw89_btc_fbtc_btscan { 1935 struct rtw89_btc_fbtc_btscan_v1 v1; 1936 struct rtw89_btc_fbtc_btscan_v2 v2; 1937 }; 1938 1939 struct rtw89_btc_bt_info { 1940 struct rtw89_btc_bt_link_info link_info; 1941 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1942 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1943 struct rtw89_btc_bt_ver_info ver_info; 1944 struct rtw89_btc_bool_sta_chg enable; 1945 struct rtw89_btc_bool_sta_chg inq_pag; 1946 struct rtw89_btc_rf_para rf_para; 1947 union rtw89_btc_bt_rfk_info_map rfk_info; 1948 1949 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1950 u8 rssi_level; 1951 1952 u32 scbd; 1953 u32 feature; 1954 1955 u32 mbx_avl: 1; 1956 u32 whql_test: 1; 1957 u32 igno_wl: 1; 1958 u32 reinit: 1; 1959 u32 ble_scan_en: 1; 1960 u32 btg_type: 1; 1961 u32 inq: 1; 1962 u32 pag: 1; 1963 u32 run_patch_code: 1; 1964 u32 hi_lna_rx: 1; 1965 u32 scan_rx_low_pri: 1; 1966 u32 scan_info_update: 1; 1967 u32 lna_constrain: 3; 1968 u32 rsvd: 17; 1969 }; 1970 1971 struct rtw89_btc_cx { 1972 struct rtw89_btc_wl_info wl; 1973 struct rtw89_btc_bt_info bt; 1974 struct rtw89_btc_3rdcx_info other; 1975 u32 state_map; 1976 u32 cnt_bt[BTC_BCNT_NUM]; 1977 u32 cnt_wl[BTC_WCNT_NUM]; 1978 }; 1979 1980 struct rtw89_btc_fbtc_tdma { 1981 u8 type; /* btc_ver::fcxtdma */ 1982 u8 rxflctrl; 1983 u8 txpause; 1984 u8 wtgle_n; 1985 u8 leak_n; 1986 u8 ext_ctrl; 1987 u8 rxflctrl_role; 1988 u8 option_ctrl; 1989 } __packed; 1990 1991 struct rtw89_btc_fbtc_tdma_v3 { 1992 u8 fver; /* btc_ver::fcxtdma */ 1993 u8 rsvd; 1994 __le16 rsvd1; 1995 struct rtw89_btc_fbtc_tdma tdma; 1996 } __packed; 1997 1998 union rtw89_btc_fbtc_tdma_le32 { 1999 struct rtw89_btc_fbtc_tdma v1; 2000 struct rtw89_btc_fbtc_tdma_v3 v3; 2001 }; 2002 2003 #define CXMREG_MAX 30 2004 #define CXMREG_MAX_V2 20 2005 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2006 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2007 2008 enum rtw89_btc_bt_sta_counter { 2009 BTC_BCNT_RFK_REQ = 0, 2010 BTC_BCNT_RFK_GO = 1, 2011 BTC_BCNT_RFK_REJECT = 2, 2012 BTC_BCNT_RFK_FAIL = 3, 2013 BTC_BCNT_RFK_TIMEOUT = 4, 2014 BTC_BCNT_HI_TX = 5, 2015 BTC_BCNT_HI_RX = 6, 2016 BTC_BCNT_LO_TX = 7, 2017 BTC_BCNT_LO_RX = 8, 2018 BTC_BCNT_POLLUTED = 9, 2019 BTC_BCNT_STA_MAX 2020 }; 2021 2022 enum rtw89_btc_bt_sta_counter_v105 { 2023 BTC_BCNT_RFK_REQ_V105 = 0, 2024 BTC_BCNT_HI_TX_V105 = 1, 2025 BTC_BCNT_HI_RX_V105 = 2, 2026 BTC_BCNT_LO_TX_V105 = 3, 2027 BTC_BCNT_LO_RX_V105 = 4, 2028 BTC_BCNT_POLLUTED_V105 = 5, 2029 BTC_BCNT_STA_MAX_V105 2030 }; 2031 2032 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2033 u16 fver; /* btc_ver::fcxbtcrpt */ 2034 u16 rpt_cnt; /* tmr counters */ 2035 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2036 u32 wl_fw_cx_offload; 2037 u32 wl_fw_ver; 2038 u32 rpt_enable; 2039 u32 rpt_para; /* ms */ 2040 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2041 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2042 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2043 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2044 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2045 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2046 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2047 u32 c2h_cnt; /* fw send c2h counter */ 2048 u32 h2c_cnt; /* fw recv h2c counter */ 2049 } __packed; 2050 2051 struct rtw89_btc_fbtc_rpt_ctrl_info { 2052 __le32 cnt; /* fw report counter */ 2053 __le32 en; /* report map */ 2054 __le32 para; /* not used */ 2055 2056 __le32 cnt_c2h; /* fw send c2h counter */ 2057 __le32 cnt_h2c; /* fw recv h2c counter */ 2058 __le32 len_c2h; /* The total length of the last C2H */ 2059 2060 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2061 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2062 } __packed; 2063 2064 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2065 __le32 cx_ver; /* match which driver's coex version */ 2066 __le32 fw_ver; 2067 __le32 en; /* report map */ 2068 2069 __le16 cnt; /* fw report counter */ 2070 __le16 cnt_c2h; /* fw send c2h counter */ 2071 __le16 cnt_h2c; /* fw recv h2c counter */ 2072 __le16 len_c2h; /* The total length of the last C2H */ 2073 2074 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2075 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2076 } __packed; 2077 2078 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2079 __le32 cx_ver; /* match which driver's coex version */ 2080 __le32 cx_offload; 2081 __le32 fw_ver; 2082 } __packed; 2083 2084 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2085 __le32 cnt_empty; /* a2dp empty count */ 2086 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2087 __le32 cnt_tx; 2088 __le32 cnt_ack; 2089 __le32 cnt_nack; 2090 } __packed; 2091 2092 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2093 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2094 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2095 __le32 cnt_recv; /* fw recv mailbox counter */ 2096 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2097 } __packed; 2098 2099 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2100 u8 fver; 2101 u8 rsvd; 2102 __le16 rsvd1; 2103 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2104 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2105 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2106 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2107 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2108 } __packed; 2109 2110 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2111 u8 fver; 2112 u8 rsvd; 2113 __le16 rsvd1; 2114 2115 u8 gnt_val[RTW89_PHY_MAX][4]; 2116 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2117 2118 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2119 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2120 } __packed; 2121 2122 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2123 u8 fver; 2124 u8 rsvd; 2125 __le16 rsvd1; 2126 2127 u8 gnt_val[RTW89_PHY_MAX][4]; 2128 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2129 2130 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2131 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2132 } __packed; 2133 2134 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2135 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2136 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2137 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2138 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2139 }; 2140 2141 enum rtw89_fbtc_ext_ctrl_type { 2142 CXECTL_OFF = 0x0, /* tdma off */ 2143 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2144 CXECTL_EXT = 0x2, 2145 CXECTL_MAX 2146 }; 2147 2148 union rtw89_btc_fbtc_rxflct { 2149 u8 val; 2150 u8 type: 3; 2151 u8 tgln_n: 5; 2152 }; 2153 2154 enum rtw89_btc_cxst_state { 2155 CXST_OFF = 0x0, 2156 CXST_B2W = 0x1, 2157 CXST_W1 = 0x2, 2158 CXST_W2 = 0x3, 2159 CXST_W2B = 0x4, 2160 CXST_B1 = 0x5, 2161 CXST_B2 = 0x6, 2162 CXST_B3 = 0x7, 2163 CXST_B4 = 0x8, 2164 CXST_LK = 0x9, 2165 CXST_BLK = 0xa, 2166 CXST_E2G = 0xb, 2167 CXST_E5G = 0xc, 2168 CXST_EBT = 0xd, 2169 CXST_ENULL = 0xe, 2170 CXST_WLK = 0xf, 2171 CXST_W1FDD = 0x10, 2172 CXST_B1FDD = 0x11, 2173 CXST_MAX = 0x12, 2174 }; 2175 2176 enum rtw89_btc_cxevnt { 2177 CXEVNT_TDMA_ENTRY = 0x0, 2178 CXEVNT_WL_TMR, 2179 CXEVNT_B1_TMR, 2180 CXEVNT_B2_TMR, 2181 CXEVNT_B3_TMR, 2182 CXEVNT_B4_TMR, 2183 CXEVNT_W2B_TMR, 2184 CXEVNT_B2W_TMR, 2185 CXEVNT_BCN_EARLY, 2186 CXEVNT_A2DP_EMPTY, 2187 CXEVNT_LK_END, 2188 CXEVNT_RX_ISR, 2189 CXEVNT_RX_FC0, 2190 CXEVNT_RX_FC1, 2191 CXEVNT_BT_RELINK, 2192 CXEVNT_BT_RETRY, 2193 CXEVNT_E2G, 2194 CXEVNT_E5G, 2195 CXEVNT_EBT, 2196 CXEVNT_ENULL, 2197 CXEVNT_DRV_WLK, 2198 CXEVNT_BCN_OK, 2199 CXEVNT_BT_CHANGE, 2200 CXEVNT_EBT_EXTEND, 2201 CXEVNT_E2G_NULL1, 2202 CXEVNT_B1FDD_TMR, 2203 CXEVNT_MAX 2204 }; 2205 2206 enum { 2207 CXBCN_ALL = 0x0, 2208 CXBCN_ALL_OK, 2209 CXBCN_BT_SLOT, 2210 CXBCN_BT_OK, 2211 CXBCN_MAX 2212 }; 2213 2214 enum btc_slot_type { 2215 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2216 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2217 CXSTYPE_NUM, 2218 }; 2219 2220 enum { /* TIME */ 2221 CXT_BT = 0x0, 2222 CXT_WL = 0x1, 2223 CXT_MAX 2224 }; 2225 2226 enum { /* TIME-A2DP */ 2227 CXT_FLCTRL_OFF = 0x0, 2228 CXT_FLCTRL_ON = 0x1, 2229 CXT_FLCTRL_MAX 2230 }; 2231 2232 enum { /* STEP TYPE */ 2233 CXSTEP_NONE = 0x0, 2234 CXSTEP_EVNT = 0x1, 2235 CXSTEP_SLOT = 0x2, 2236 CXSTEP_MAX, 2237 }; 2238 2239 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2240 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2241 RPT_BT_AFH_SEQ_LE = 0x20 2242 }; 2243 2244 #define BTC_DBG_MAX1 32 2245 struct rtw89_btc_fbtc_gpio_dbg { 2246 u8 fver; /* btc_ver::fcxgpiodbg */ 2247 u8 rsvd; 2248 u16 rsvd2; 2249 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2250 u32 pre_state; /* the debug signal is 1 or 0 */ 2251 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2252 } __packed; 2253 2254 struct rtw89_btc_fbtc_mreg_val_v1 { 2255 u8 fver; /* btc_ver::fcxmreg */ 2256 u8 reg_num; 2257 __le16 rsvd; 2258 __le32 mreg_val[CXMREG_MAX]; 2259 } __packed; 2260 2261 struct rtw89_btc_fbtc_mreg_val_v2 { 2262 u8 fver; /* btc_ver::fcxmreg */ 2263 u8 reg_num; 2264 __le16 rsvd; 2265 __le32 mreg_val[CXMREG_MAX_V2]; 2266 } __packed; 2267 2268 union rtw89_btc_fbtc_mreg_val { 2269 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2270 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2271 }; 2272 2273 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2274 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2275 .offset = cpu_to_le32(__offset), } 2276 2277 struct rtw89_btc_fbtc_mreg { 2278 __le16 type; 2279 __le16 bytes; 2280 __le32 offset; 2281 } __packed; 2282 2283 struct rtw89_btc_fbtc_slot { 2284 __le16 dur; 2285 __le32 cxtbl; 2286 __le16 cxtype; 2287 } __packed; 2288 2289 struct rtw89_btc_fbtc_slots { 2290 u8 fver; /* btc_ver::fcxslots */ 2291 u8 tbl_num; 2292 __le16 rsvd; 2293 __le32 update_map; 2294 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2295 } __packed; 2296 2297 struct rtw89_btc_fbtc_slot_v7 { 2298 __le16 dur; /* slot duration */ 2299 __le16 cxtype; 2300 __le32 cxtbl; 2301 } __packed; 2302 2303 struct rtw89_btc_fbtc_slot_u16 { 2304 __le16 dur; /* slot duration */ 2305 __le16 cxtype; 2306 __le16 cxtbl_l16; /* coex table [15:0] */ 2307 __le16 cxtbl_h16; /* coex table [31:16] */ 2308 } __packed; 2309 2310 struct rtw89_btc_fbtc_1slot_v7 { 2311 u8 fver; 2312 u8 sid; /* slot id */ 2313 __le16 rsvd; 2314 struct rtw89_btc_fbtc_slot_v7 slot; 2315 } __packed; 2316 2317 struct rtw89_btc_fbtc_slots_v7 { 2318 u8 fver; 2319 u8 slot_cnt; 2320 u8 rsvd0; 2321 u8 rsvd1; 2322 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2323 __le32 update_map; 2324 } __packed; 2325 2326 union rtw89_btc_fbtc_slots_info { 2327 struct rtw89_btc_fbtc_slots v1; 2328 struct rtw89_btc_fbtc_slots_v7 v7; 2329 } __packed; 2330 2331 struct rtw89_btc_fbtc_step { 2332 u8 type; 2333 u8 val; 2334 __le16 difft; 2335 } __packed; 2336 2337 struct rtw89_btc_fbtc_steps_v2 { 2338 u8 fver; /* btc_ver::fcxstep */ 2339 u8 rsvd; 2340 __le16 cnt; 2341 __le16 pos_old; 2342 __le16 pos_new; 2343 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2344 } __packed; 2345 2346 struct rtw89_btc_fbtc_steps_v3 { 2347 u8 fver; 2348 u8 en; 2349 __le16 rsvd; 2350 __le32 cnt; 2351 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2352 } __packed; 2353 2354 union rtw89_btc_fbtc_steps_info { 2355 struct rtw89_btc_fbtc_steps_v2 v2; 2356 struct rtw89_btc_fbtc_steps_v3 v3; 2357 }; 2358 2359 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2360 u8 fver; /* btc_ver::fcxcysta */ 2361 u8 rsvd; 2362 __le16 cycles; /* total cycle number */ 2363 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2364 __le16 a2dpept; /* a2dp empty cnt */ 2365 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2366 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2367 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2368 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2369 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2370 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2371 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2372 __le16 tmax_a2dpept; /* max a2dp empty time */ 2373 __le16 tavg_lk; /* avg leak-slot time */ 2374 __le16 tmax_lk; /* max leak-slot time */ 2375 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2376 __le32 bcn_cnt[CXBCN_MAX]; 2377 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2378 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2379 __le32 skip_cnt; 2380 __le32 exception; 2381 __le32 except_cnt; 2382 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2383 } __packed; 2384 2385 struct rtw89_btc_fbtc_fdd_try_info { 2386 __le16 cycles[CXT_FLCTRL_MAX]; 2387 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2388 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2389 } __packed; 2390 2391 struct rtw89_btc_fbtc_cycle_time_info { 2392 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2393 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2394 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2395 } __packed; 2396 2397 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2398 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2399 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2400 } __packed; 2401 2402 struct rtw89_btc_fbtc_a2dp_trx_stat { 2403 u8 empty_cnt; 2404 u8 retry_cnt; 2405 u8 tx_rate; 2406 u8 tx_cnt; 2407 u8 ack_cnt; 2408 u8 nack_cnt; 2409 u8 rsvd1; 2410 u8 rsvd2; 2411 } __packed; 2412 2413 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2414 u8 empty_cnt; 2415 u8 retry_cnt; 2416 u8 tx_rate; 2417 u8 tx_cnt; 2418 u8 ack_cnt; 2419 u8 nack_cnt; 2420 u8 no_empty_cnt; 2421 u8 rsvd; 2422 } __packed; 2423 2424 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2425 __le16 cnt; /* a2dp empty cnt */ 2426 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2427 __le16 tavg; /* avg a2dp empty time */ 2428 __le16 tmax; /* max a2dp empty time */ 2429 } __packed; 2430 2431 struct rtw89_btc_fbtc_cycle_leak_info { 2432 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2433 __le16 tavg; /* avg leak-slot time */ 2434 __le16 tmax; /* max leak-slot time */ 2435 } __packed; 2436 2437 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2438 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2439 2440 struct rtw89_btc_fbtc_cycle_fddt_info { 2441 __le16 train_cycle; 2442 __le16 tp; 2443 2444 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2445 s8 bt_tx_power; /* decrease Tx power (dB) */ 2446 s8 bt_rx_gain; /* LNA constrain level */ 2447 u8 no_empty_cnt; 2448 2449 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2450 u8 cn; /* condition_num */ 2451 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2452 u8 train_result; /* refer to enum btc_fddt_check_map */ 2453 } __packed; 2454 2455 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2456 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2457 2458 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2459 __le16 train_cycle; 2460 __le16 tp; 2461 2462 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2463 s8 bt_tx_power; /* decrease Tx power (dB) */ 2464 s8 bt_rx_gain; /* LNA constrain level */ 2465 u8 no_empty_cnt; 2466 2467 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2468 u8 cn; /* condition_num */ 2469 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2470 u8 train_result; /* refer to enum btc_fddt_check_map */ 2471 } __packed; 2472 2473 struct rtw89_btc_fbtc_fddt_cell_status { 2474 s8 wl_tx_pwr; 2475 s8 bt_tx_pwr; 2476 s8 bt_rx_gain; 2477 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2478 } __packed; 2479 2480 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2481 u8 fver; 2482 u8 rsvd; 2483 __le16 cycles; /* total cycle number */ 2484 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2485 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2486 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2487 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2488 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2489 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2490 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2491 __le32 bcn_cnt[CXBCN_MAX]; 2492 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2493 __le32 skip_cnt; 2494 __le32 except_cnt; 2495 __le32 except_map; 2496 } __packed; 2497 2498 #define FDD_TRAIN_WL_DIRECTION 2 2499 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2500 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2501 2502 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2503 u8 fver; 2504 u8 rsvd; 2505 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2506 u8 except_cnt; 2507 2508 __le16 skip_cnt; 2509 __le16 cycles; /* total cycle number */ 2510 2511 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2512 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2513 __le16 bcn_cnt[CXBCN_MAX]; 2514 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2515 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2516 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2517 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2518 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2519 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2520 [FDD_TRAIN_WL_RSSI_LEVEL] 2521 [FDD_TRAIN_BT_RSSI_LEVEL]; 2522 __le32 except_map; 2523 } __packed; 2524 2525 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2526 u8 fver; 2527 u8 rsvd; 2528 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2529 u8 except_cnt; 2530 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2531 2532 __le16 skip_cnt; 2533 __le16 cycles; /* total cycle number */ 2534 2535 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2536 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2537 __le16 bcn_cnt[CXBCN_MAX]; 2538 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2539 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2540 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2541 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2542 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2543 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2544 [FDD_TRAIN_WL_RSSI_LEVEL] 2545 [FDD_TRAIN_BT_RSSI_LEVEL]; 2546 __le32 except_map; 2547 } __packed; 2548 2549 union rtw89_btc_fbtc_cysta_info { 2550 struct rtw89_btc_fbtc_cysta_v2 v2; 2551 struct rtw89_btc_fbtc_cysta_v3 v3; 2552 struct rtw89_btc_fbtc_cysta_v4 v4; 2553 struct rtw89_btc_fbtc_cysta_v5 v5; 2554 }; 2555 2556 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2557 u8 fver; /* btc_ver::fcxnullsta */ 2558 u8 rsvd; 2559 __le16 rsvd2; 2560 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2561 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2562 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2563 } __packed; 2564 2565 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2566 u8 fver; /* btc_ver::fcxnullsta */ 2567 u8 rsvd; 2568 __le16 rsvd2; 2569 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2570 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2571 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2572 } __packed; 2573 2574 union rtw89_btc_fbtc_cynullsta_info { 2575 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2576 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2577 }; 2578 2579 struct rtw89_btc_fbtc_btver { 2580 u8 fver; /* btc_ver::fcxbtver */ 2581 u8 rsvd; 2582 __le16 rsvd2; 2583 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2584 __le32 fw_ver; 2585 __le32 feature; 2586 } __packed; 2587 2588 struct rtw89_btc_fbtc_btafh { 2589 u8 fver; /* btc_ver::fcxbtafh */ 2590 u8 rsvd; 2591 __le16 rsvd2; 2592 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2593 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2594 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2595 } __packed; 2596 2597 struct rtw89_btc_fbtc_btafh_v2 { 2598 u8 fver; /* btc_ver::fcxbtafh */ 2599 u8 rsvd; 2600 u8 rsvd2; 2601 u8 map_type; 2602 u8 afh_l[4]; 2603 u8 afh_m[4]; 2604 u8 afh_h[4]; 2605 u8 afh_le_a[4]; 2606 u8 afh_le_b[4]; 2607 } __packed; 2608 2609 struct rtw89_btc_fbtc_btdevinfo { 2610 u8 fver; /* btc_ver::fcxbtdevinfo */ 2611 u8 rsvd; 2612 __le16 vendor_id; 2613 __le32 dev_name; /* only 24 bits valid */ 2614 __le32 flush_time; 2615 } __packed; 2616 2617 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2618 struct rtw89_btc_rf_trx_para { 2619 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2620 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2621 u8 bt_tx_power; /* decrease Tx power (dB) */ 2622 u8 bt_rx_gain; /* LNA constrain level */ 2623 }; 2624 2625 struct rtw89_btc_trx_info { 2626 u8 tx_lvl; 2627 u8 rx_lvl; 2628 u8 wl_rssi; 2629 u8 bt_rssi; 2630 2631 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2632 s8 rx_gain; /* rx gain table index (TBD.) */ 2633 s8 bt_tx_power; /* decrease Tx power (dB) */ 2634 s8 bt_rx_gain; /* LNA constrain level */ 2635 2636 u8 cn; /* condition_num */ 2637 s8 nhm; 2638 u8 bt_profile; 2639 u8 rsvd2; 2640 2641 u16 tx_rate; 2642 u16 rx_rate; 2643 2644 u32 tx_tp; 2645 u32 rx_tp; 2646 u32 rx_err_ratio; 2647 }; 2648 2649 union rtw89_btc_fbtc_slot_u { 2650 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2651 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2652 }; 2653 2654 struct rtw89_btc_dm { 2655 union rtw89_btc_fbtc_slot_u slot; 2656 union rtw89_btc_fbtc_slot_u slot_now; 2657 struct rtw89_btc_fbtc_tdma tdma; 2658 struct rtw89_btc_fbtc_tdma tdma_now; 2659 struct rtw89_mac_ax_coex_gnt gnt; 2660 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2661 struct rtw89_btc_rf_trx_para rf_trx_para; 2662 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2663 struct rtw89_btc_dm_step dm_step; 2664 struct rtw89_btc_wl_scc_ctrl wl_scc; 2665 struct rtw89_btc_trx_info trx_info; 2666 union rtw89_btc_dm_error_map error; 2667 u32 cnt_dm[BTC_DCNT_NUM]; 2668 u32 cnt_notify[BTC_NCNT_NUM]; 2669 2670 u32 update_slot_map; 2671 u32 set_ant_path; 2672 u32 e2g_slot_limit; 2673 u32 e2g_slot_nulltx_time; 2674 2675 u32 wl_only: 1; 2676 u32 wl_fw_cx_offload: 1; 2677 u32 freerun: 1; 2678 u32 fddt_train: 1; 2679 u32 wl_ps_ctrl: 2; 2680 u32 wl_mimo_ps: 1; 2681 u32 leak_ap: 1; 2682 u32 noisy_level: 3; 2683 u32 coex_info_map: 8; 2684 u32 bt_only: 1; 2685 u32 wl_btg_rx: 2; 2686 u32 trx_para_level: 8; 2687 u32 wl_stb_chg: 1; 2688 u32 pta_owner: 1; 2689 2690 u32 tdma_instant_excute: 1; 2691 u32 wl_btg_rx_rb: 2; 2692 2693 u16 slot_dur[CXST_MAX]; 2694 2695 u8 run_reason; 2696 u8 run_action; 2697 2698 u8 wl_pre_agc: 2; 2699 u8 wl_lna2: 1; 2700 u8 wl_pre_agc_rb: 2; 2701 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2702 }; 2703 2704 struct rtw89_btc_ctrl { 2705 u32 manual: 1; 2706 u32 igno_bt: 1; 2707 u32 always_freerun: 1; 2708 u32 trace_step: 16; 2709 u32 rsvd: 12; 2710 }; 2711 2712 struct rtw89_btc_ctrl_v7 { 2713 u8 manual; 2714 u8 igno_bt; 2715 u8 always_freerun; 2716 u8 rsvd; 2717 } __packed; 2718 2719 union rtw89_btc_ctrl_list { 2720 struct rtw89_btc_ctrl ctrl; 2721 struct rtw89_btc_ctrl_v7 ctrl_v7; 2722 }; 2723 2724 struct rtw89_btc_dbg { 2725 /* cmd "rb" */ 2726 bool rb_done; 2727 u32 rb_val; 2728 }; 2729 2730 enum rtw89_btc_btf_fw_event { 2731 BTF_EVNT_RPT = 0, 2732 BTF_EVNT_BT_INFO = 1, 2733 BTF_EVNT_BT_SCBD = 2, 2734 BTF_EVNT_BT_REG = 3, 2735 BTF_EVNT_CX_RUNINFO = 4, 2736 BTF_EVNT_BT_PSD = 5, 2737 BTF_EVNT_BUF_OVERFLOW, 2738 BTF_EVNT_C2H_LOOPBACK, 2739 BTF_EVNT_MAX, 2740 }; 2741 2742 enum btf_fw_event_report { 2743 BTC_RPT_TYPE_CTRL = 0x0, 2744 BTC_RPT_TYPE_TDMA, 2745 BTC_RPT_TYPE_SLOT, 2746 BTC_RPT_TYPE_CYSTA, 2747 BTC_RPT_TYPE_STEP, 2748 BTC_RPT_TYPE_NULLSTA, 2749 BTC_RPT_TYPE_MREG, 2750 BTC_RPT_TYPE_GPIO_DBG, 2751 BTC_RPT_TYPE_BT_VER, 2752 BTC_RPT_TYPE_BT_SCAN, 2753 BTC_RPT_TYPE_BT_AFH, 2754 BTC_RPT_TYPE_BT_DEVICE, 2755 BTC_RPT_TYPE_TEST, 2756 BTC_RPT_TYPE_MAX = 31 2757 }; 2758 2759 enum rtw_btc_btf_reg_type { 2760 REG_MAC = 0x0, 2761 REG_BB = 0x1, 2762 REG_RF = 0x2, 2763 REG_BT_RF = 0x3, 2764 REG_BT_MODEM = 0x4, 2765 REG_BT_BLUEWIZE = 0x5, 2766 REG_BT_VENDOR = 0x6, 2767 REG_BT_LE = 0x7, 2768 REG_MAX_TYPE, 2769 }; 2770 2771 struct rtw89_btc_rpt_cmn_info { 2772 u32 rx_cnt; 2773 u32 rx_len; 2774 u32 req_len; /* expected rsp len */ 2775 u8 req_fver; /* expected rsp fver */ 2776 u8 rsp_fver; /* fver from fw */ 2777 u8 valid; 2778 } __packed; 2779 2780 union rtw89_btc_fbtc_btafh_info { 2781 struct rtw89_btc_fbtc_btafh v1; 2782 struct rtw89_btc_fbtc_btafh_v2 v2; 2783 }; 2784 2785 struct rtw89_btc_report_ctrl_state { 2786 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2787 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2788 }; 2789 2790 struct rtw89_btc_rpt_fbtc_tdma { 2791 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2792 union rtw89_btc_fbtc_tdma_le32 finfo; 2793 }; 2794 2795 struct rtw89_btc_rpt_fbtc_slots { 2796 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2797 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 2798 }; 2799 2800 struct rtw89_btc_rpt_fbtc_cysta { 2801 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2802 union rtw89_btc_fbtc_cysta_info finfo; 2803 }; 2804 2805 struct rtw89_btc_rpt_fbtc_step { 2806 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2807 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2808 }; 2809 2810 struct rtw89_btc_rpt_fbtc_nullsta { 2811 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2812 union rtw89_btc_fbtc_cynullsta_info finfo; 2813 }; 2814 2815 struct rtw89_btc_rpt_fbtc_mreg { 2816 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2817 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2818 }; 2819 2820 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2821 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2822 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2823 }; 2824 2825 struct rtw89_btc_rpt_fbtc_btver { 2826 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2827 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2828 }; 2829 2830 struct rtw89_btc_rpt_fbtc_btscan { 2831 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2832 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2833 }; 2834 2835 struct rtw89_btc_rpt_fbtc_btafh { 2836 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2837 union rtw89_btc_fbtc_btafh_info finfo; 2838 }; 2839 2840 struct rtw89_btc_rpt_fbtc_btdev { 2841 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2842 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2843 }; 2844 2845 enum rtw89_btc_btfre_type { 2846 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2847 BTFRE_UNDEF_TYPE, 2848 BTFRE_EXCEPTION, 2849 BTFRE_MAX, 2850 }; 2851 2852 struct rtw89_btc_btf_fwinfo { 2853 u32 cnt_c2h; 2854 u32 cnt_h2c; 2855 u32 cnt_h2c_fail; 2856 u32 event[BTF_EVNT_MAX]; 2857 2858 u32 err[BTFRE_MAX]; 2859 u32 len_mismch; 2860 u32 fver_mismch; 2861 u32 rpt_en_map; 2862 2863 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2864 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2865 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2866 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2867 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2868 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2869 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2870 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2871 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2872 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2873 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2874 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2875 }; 2876 2877 struct rtw89_btc_ver { 2878 enum rtw89_core_chip_id chip_id; 2879 u32 fw_ver_code; 2880 2881 u8 fcxbtcrpt; 2882 u8 fcxtdma; 2883 u8 fcxslots; 2884 u8 fcxcysta; 2885 u8 fcxstep; 2886 u8 fcxnullsta; 2887 u8 fcxmreg; 2888 u8 fcxgpiodbg; 2889 u8 fcxbtver; 2890 u8 fcxbtscan; 2891 u8 fcxbtafh; 2892 u8 fcxbtdevinfo; 2893 u8 fwlrole; 2894 u8 frptmap; 2895 u8 fcxctrl; 2896 u8 fcxinit; 2897 2898 u8 drvinfo_type; 2899 u16 info_buf; 2900 u8 max_role_num; 2901 }; 2902 2903 #define RTW89_BTC_POLICY_MAXLEN 512 2904 2905 struct rtw89_btc { 2906 const struct rtw89_btc_ver *ver; 2907 2908 struct rtw89_btc_cx cx; 2909 struct rtw89_btc_dm dm; 2910 union rtw89_btc_ctrl_list ctrl; 2911 union rtw89_btc_module_info mdinfo; 2912 struct rtw89_btc_btf_fwinfo fwinfo; 2913 struct rtw89_btc_dbg dbg; 2914 2915 struct work_struct eapol_notify_work; 2916 struct work_struct arp_notify_work; 2917 struct work_struct dhcp_notify_work; 2918 struct work_struct icmp_notify_work; 2919 2920 u32 bt_req_len; 2921 2922 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2923 u8 ant_type; 2924 u8 btg_pos; 2925 u16 policy_len; 2926 u16 policy_type; 2927 bool bt_req_en; 2928 bool update_policy_force; 2929 bool lps; 2930 bool manual_ctrl; 2931 }; 2932 2933 enum rtw89_btc_hmsg { 2934 RTW89_BTC_HMSG_TMR_EN = 0x0, 2935 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 2936 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 2937 RTW89_BTC_HMSG_FW_EV = 0x3, 2938 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 2939 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 2940 2941 NUM_OF_RTW89_BTC_HMSG, 2942 }; 2943 2944 enum rtw89_ra_mode { 2945 RTW89_RA_MODE_CCK = BIT(0), 2946 RTW89_RA_MODE_OFDM = BIT(1), 2947 RTW89_RA_MODE_HT = BIT(2), 2948 RTW89_RA_MODE_VHT = BIT(3), 2949 RTW89_RA_MODE_HE = BIT(4), 2950 RTW89_RA_MODE_EHT = BIT(5), 2951 }; 2952 2953 enum rtw89_ra_report_mode { 2954 RTW89_RA_RPT_MODE_LEGACY, 2955 RTW89_RA_RPT_MODE_HT, 2956 RTW89_RA_RPT_MODE_VHT, 2957 RTW89_RA_RPT_MODE_HE, 2958 RTW89_RA_RPT_MODE_EHT, 2959 }; 2960 2961 enum rtw89_dig_noisy_level { 2962 RTW89_DIG_NOISY_LEVEL0 = -1, 2963 RTW89_DIG_NOISY_LEVEL1 = 0, 2964 RTW89_DIG_NOISY_LEVEL2 = 1, 2965 RTW89_DIG_NOISY_LEVEL3 = 2, 2966 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2967 }; 2968 2969 enum rtw89_gi_ltf { 2970 RTW89_GILTF_LGI_4XHE32 = 0, 2971 RTW89_GILTF_SGI_4XHE08 = 1, 2972 RTW89_GILTF_2XHE16 = 2, 2973 RTW89_GILTF_2XHE08 = 3, 2974 RTW89_GILTF_1XHE16 = 4, 2975 RTW89_GILTF_1XHE08 = 5, 2976 RTW89_GILTF_MAX 2977 }; 2978 2979 enum rtw89_rx_frame_type { 2980 RTW89_RX_TYPE_MGNT = 0, 2981 RTW89_RX_TYPE_CTRL = 1, 2982 RTW89_RX_TYPE_DATA = 2, 2983 RTW89_RX_TYPE_RSVD = 3, 2984 }; 2985 2986 enum rtw89_efuse_block { 2987 RTW89_EFUSE_BLOCK_SYS = 0, 2988 RTW89_EFUSE_BLOCK_RF = 1, 2989 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 2990 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 2991 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 2992 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 2993 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 2994 RTW89_EFUSE_BLOCK_ADIE = 7, 2995 2996 RTW89_EFUSE_BLOCK_NUM, 2997 RTW89_EFUSE_BLOCK_IGNORE, 2998 }; 2999 3000 struct rtw89_ra_info { 3001 u8 is_dis_ra:1; 3002 /* Bit0 : CCK 3003 * Bit1 : OFDM 3004 * Bit2 : HT 3005 * Bit3 : VHT 3006 * Bit4 : HE 3007 * Bit5 : EHT 3008 */ 3009 u8 mode_ctrl:6; 3010 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3011 u8 macid; 3012 u8 dcm_cap:1; 3013 u8 er_cap:1; 3014 u8 init_rate_lv:2; 3015 u8 upd_all:1; 3016 u8 en_sgi:1; 3017 u8 ldpc_cap:1; 3018 u8 stbc_cap:1; 3019 u8 ss_num:3; 3020 u8 giltf:3; 3021 u8 upd_bw_nss_mask:1; 3022 u8 upd_mask:1; 3023 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3024 /* BFee CSI */ 3025 u8 band_num; 3026 u8 ra_csi_rate_en:1; 3027 u8 fixed_csi_rate_en:1; 3028 u8 cr_tbl_sel:1; 3029 u8 fix_giltf_en:1; 3030 u8 fix_giltf:3; 3031 u8 rsvd2:1; 3032 u8 csi_mcs_ss_idx; 3033 u8 csi_mode:2; 3034 u8 csi_gi_ltf:3; 3035 u8 csi_bw:3; 3036 }; 3037 3038 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3039 #define RTW89_PPDU_MAC_INFO_SIZE 8 3040 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3041 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3042 3043 #define RTW89_MAX_RX_AGG_NUM 64 3044 #define RTW89_MAX_TX_AGG_NUM 128 3045 3046 struct rtw89_ampdu_params { 3047 u16 agg_num; 3048 bool amsdu; 3049 }; 3050 3051 struct rtw89_ra_report { 3052 struct rate_info txrate; 3053 u32 bit_rate; 3054 u16 hw_rate; 3055 bool might_fallback_legacy; 3056 }; 3057 3058 DECLARE_EWMA(rssi, 10, 16); 3059 DECLARE_EWMA(evm, 10, 16); 3060 DECLARE_EWMA(snr, 10, 16); 3061 3062 struct rtw89_ba_cam_entry { 3063 struct list_head list; 3064 u8 tid; 3065 }; 3066 3067 #define RTW89_MAX_ADDR_CAM_NUM 128 3068 #define RTW89_MAX_BSSID_CAM_NUM 20 3069 #define RTW89_MAX_SEC_CAM_NUM 128 3070 #define RTW89_MAX_BA_CAM_NUM 24 3071 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3072 3073 struct rtw89_addr_cam_entry { 3074 u8 addr_cam_idx; 3075 u8 offset; 3076 u8 len; 3077 u8 valid : 1; 3078 u8 addr_mask : 6; 3079 u8 wapi : 1; 3080 u8 mask_sel : 2; 3081 u8 bssid_cam_idx: 6; 3082 3083 u8 sec_ent_mode; 3084 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3085 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3086 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3087 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 3088 }; 3089 3090 struct rtw89_bssid_cam_entry { 3091 u8 bssid[ETH_ALEN]; 3092 u8 phy_idx; 3093 u8 bssid_cam_idx; 3094 u8 offset; 3095 u8 len; 3096 u8 valid : 1; 3097 u8 num; 3098 }; 3099 3100 struct rtw89_sec_cam_entry { 3101 u8 sec_cam_idx; 3102 u8 offset; 3103 u8 len; 3104 u8 type : 4; 3105 u8 ext_key : 1; 3106 u8 spp_mode : 1; 3107 /* 256 bits */ 3108 u8 key[32]; 3109 }; 3110 3111 struct rtw89_sta { 3112 u8 mac_id; 3113 bool disassoc; 3114 bool er_cap; 3115 struct rtw89_dev *rtwdev; 3116 struct rtw89_vif *rtwvif; 3117 struct rtw89_ra_info ra; 3118 struct rtw89_ra_report ra_report; 3119 int max_agg_wait; 3120 u8 prev_rssi; 3121 struct ewma_rssi avg_rssi; 3122 struct ewma_rssi rssi[RF_PATH_MAX]; 3123 struct ewma_snr avg_snr; 3124 struct ewma_evm evm_min[RF_PATH_MAX]; 3125 struct ewma_evm evm_max[RF_PATH_MAX]; 3126 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 3127 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 3128 struct ieee80211_rx_status rx_status; 3129 u16 rx_hw_rate; 3130 __le32 htc_template; 3131 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3132 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3133 struct list_head ba_cam_list; 3134 struct sk_buff_head roc_queue; 3135 3136 bool use_cfg_mask; 3137 struct cfg80211_bitrate_mask mask; 3138 3139 bool cctl_tx_time; 3140 u32 ampdu_max_time:4; 3141 bool cctl_tx_retry_limit; 3142 u32 data_tx_cnt_lmt:6; 3143 }; 3144 3145 struct rtw89_efuse { 3146 bool valid; 3147 bool power_k_valid; 3148 u8 xtal_cap; 3149 u8 addr[ETH_ALEN]; 3150 u8 rfe_type; 3151 char country_code[2]; 3152 }; 3153 3154 struct rtw89_phy_rate_pattern { 3155 u64 ra_mask; 3156 u16 rate; 3157 u8 ra_mode; 3158 bool enable; 3159 }; 3160 3161 struct rtw89_tx_wait_info { 3162 struct rcu_head rcu_head; 3163 struct completion completion; 3164 bool tx_done; 3165 }; 3166 3167 struct rtw89_tx_skb_data { 3168 struct rtw89_tx_wait_info __rcu *wait; 3169 u8 hci_priv[]; 3170 }; 3171 3172 #define RTW89_ROC_IDLE_TIMEOUT 500 3173 #define RTW89_ROC_TX_TIMEOUT 30 3174 enum rtw89_roc_state { 3175 RTW89_ROC_IDLE, 3176 RTW89_ROC_NORMAL, 3177 RTW89_ROC_MGMT, 3178 }; 3179 3180 struct rtw89_roc { 3181 struct ieee80211_channel chan; 3182 struct delayed_work roc_work; 3183 enum ieee80211_roc_type type; 3184 enum rtw89_roc_state state; 3185 int duration; 3186 }; 3187 3188 #define RTW89_P2P_MAX_NOA_NUM 2 3189 3190 struct rtw89_p2p_ie_head { 3191 u8 eid; 3192 u8 ie_len; 3193 u8 oui[3]; 3194 u8 oui_type; 3195 } __packed; 3196 3197 struct rtw89_noa_attr_head { 3198 u8 attr_type; 3199 __le16 attr_len; 3200 u8 index; 3201 u8 oppps_ctwindow; 3202 } __packed; 3203 3204 struct rtw89_p2p_noa_ie { 3205 struct rtw89_p2p_ie_head p2p_head; 3206 struct rtw89_noa_attr_head noa_head; 3207 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3208 } __packed; 3209 3210 struct rtw89_p2p_noa_setter { 3211 struct rtw89_p2p_noa_ie ie; 3212 u8 noa_count; 3213 u8 noa_index; 3214 }; 3215 3216 struct rtw89_vif { 3217 struct list_head list; 3218 struct rtw89_dev *rtwdev; 3219 struct rtw89_roc roc; 3220 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3221 enum rtw89_sub_entity_idx sub_entity_idx; 3222 enum rtw89_reg_6ghz_power reg_6ghz_power; 3223 3224 u8 mac_id; 3225 u8 port; 3226 u8 mac_addr[ETH_ALEN]; 3227 u8 bssid[ETH_ALEN]; 3228 u8 phy_idx; 3229 u8 mac_idx; 3230 u8 net_type; 3231 u8 wifi_role; 3232 u8 self_role; 3233 u8 wmm; 3234 u8 bcn_hit_cond; 3235 u8 hit_rule; 3236 u8 last_noa_nr; 3237 u64 sync_bcn_tsf; 3238 bool offchan; 3239 bool trigger; 3240 bool lsig_txop; 3241 u8 tgt_ind; 3242 u8 frm_tgt_ind; 3243 bool wowlan_pattern; 3244 bool wowlan_uc; 3245 bool wowlan_magic; 3246 bool is_hesta; 3247 bool last_a_ctrl; 3248 bool dyn_tb_bedge_en; 3249 bool pre_pwr_diff_en; 3250 bool pwr_diff_en; 3251 u8 def_tri_idx; 3252 u32 tdls_peer; 3253 struct work_struct update_beacon_work; 3254 struct rtw89_addr_cam_entry addr_cam; 3255 struct rtw89_bssid_cam_entry bssid_cam; 3256 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3257 struct rtw89_traffic_stats stats; 3258 struct rtw89_phy_rate_pattern rate_pattern; 3259 struct cfg80211_scan_request *scan_req; 3260 struct ieee80211_scan_ies *scan_ies; 3261 struct list_head general_pkt_list; 3262 struct rtw89_p2p_noa_setter p2p_noa; 3263 }; 3264 3265 enum rtw89_lv1_rcvy_step { 3266 RTW89_LV1_RCVY_STEP_1, 3267 RTW89_LV1_RCVY_STEP_2, 3268 }; 3269 3270 struct rtw89_hci_ops { 3271 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3272 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3273 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3274 void (*reset)(struct rtw89_dev *rtwdev); 3275 int (*start)(struct rtw89_dev *rtwdev); 3276 void (*stop)(struct rtw89_dev *rtwdev); 3277 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3278 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3279 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3280 3281 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3282 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3283 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3284 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3285 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3286 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3287 3288 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3289 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3290 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3291 int (*deinit)(struct rtw89_dev *rtwdev); 3292 3293 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3294 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3295 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3296 int (*napi_poll)(struct napi_struct *napi, int budget); 3297 3298 /* Deal with locks inside recovery_start and recovery_complete callbacks 3299 * by hci instance, and handle things which need to consider under SER. 3300 * e.g. turn on/off interrupts except for the one for halt notification. 3301 */ 3302 void (*recovery_start)(struct rtw89_dev *rtwdev); 3303 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3304 3305 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3306 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3307 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3308 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3309 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3310 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3311 void (*disable_intr)(struct rtw89_dev *rtwdev); 3312 void (*enable_intr)(struct rtw89_dev *rtwdev); 3313 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3314 }; 3315 3316 struct rtw89_hci_info { 3317 const struct rtw89_hci_ops *ops; 3318 enum rtw89_hci_type type; 3319 u32 rpwm_addr; 3320 u32 cpwm_addr; 3321 bool paused; 3322 }; 3323 3324 struct rtw89_chip_ops { 3325 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3326 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3327 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3328 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3329 void (*bb_reset)(struct rtw89_dev *rtwdev, 3330 enum rtw89_phy_idx phy_idx); 3331 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3332 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3333 u32 addr, u32 mask); 3334 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3335 u32 addr, u32 mask, u32 data); 3336 void (*set_channel)(struct rtw89_dev *rtwdev, 3337 const struct rtw89_chan *chan, 3338 enum rtw89_mac_idx mac_idx, 3339 enum rtw89_phy_idx phy_idx); 3340 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3341 struct rtw89_channel_help_params *p, 3342 const struct rtw89_chan *chan, 3343 enum rtw89_mac_idx mac_idx, 3344 enum rtw89_phy_idx phy_idx); 3345 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3346 enum rtw89_efuse_block block); 3347 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3348 void (*fem_setup)(struct rtw89_dev *rtwdev); 3349 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3350 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3351 void (*rfk_init)(struct rtw89_dev *rtwdev); 3352 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3353 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3354 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3355 enum rtw89_phy_idx phy_idx); 3356 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3357 void (*rfk_track)(struct rtw89_dev *rtwdev); 3358 void (*power_trim)(struct rtw89_dev *rtwdev); 3359 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3360 const struct rtw89_chan *chan, 3361 enum rtw89_phy_idx phy_idx); 3362 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3363 enum rtw89_phy_idx phy_idx); 3364 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3365 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3366 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3367 enum rtw89_phy_idx phy_idx); 3368 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3369 struct rtw89_rx_phy_ppdu *phy_ppdu, 3370 struct ieee80211_rx_status *status); 3371 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3372 enum rtw89_phy_idx phy_idx); 3373 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3374 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3375 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3376 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3377 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3378 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3379 struct rtw89_rx_desc_info *desc_info, 3380 u8 *data, u32 data_offset); 3381 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3382 struct rtw89_tx_desc_info *desc_info, 3383 void *txdesc); 3384 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3385 struct rtw89_tx_desc_info *desc_info, 3386 void *txdesc); 3387 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3388 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3389 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3390 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3391 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3392 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3393 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3394 struct rtw89_vif *rtwvif, 3395 struct rtw89_sta *rtwsta); 3396 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3397 struct rtw89_vif *rtwvif, 3398 struct rtw89_sta *rtwsta); 3399 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3400 struct ieee80211_vif *vif, 3401 struct ieee80211_sta *sta); 3402 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3403 struct ieee80211_vif *vif, 3404 struct ieee80211_sta *sta); 3405 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3406 struct rtw89_vif *rtwvif, 3407 struct rtw89_sta *rtwsta); 3408 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3409 struct rtw89_vif *rtwvif); 3410 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 3411 bool valid, struct ieee80211_ampdu_params *params); 3412 3413 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3414 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3415 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3416 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3417 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3418 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3419 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3420 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3421 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3422 }; 3423 3424 enum rtw89_dma_ch { 3425 RTW89_DMA_ACH0 = 0, 3426 RTW89_DMA_ACH1 = 1, 3427 RTW89_DMA_ACH2 = 2, 3428 RTW89_DMA_ACH3 = 3, 3429 RTW89_DMA_ACH4 = 4, 3430 RTW89_DMA_ACH5 = 5, 3431 RTW89_DMA_ACH6 = 6, 3432 RTW89_DMA_ACH7 = 7, 3433 RTW89_DMA_B0MG = 8, 3434 RTW89_DMA_B0HI = 9, 3435 RTW89_DMA_B1MG = 10, 3436 RTW89_DMA_B1HI = 11, 3437 RTW89_DMA_H2C = 12, 3438 RTW89_DMA_CH_NUM = 13 3439 }; 3440 3441 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3442 3443 enum rtw89_mlo_dbcc_mode { 3444 MLO_DBCC_NOT_SUPPORT = 1, 3445 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3446 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3447 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3448 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3449 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3450 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3451 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3452 DBCC_LEGACY = 0xffffffff, 3453 }; 3454 3455 enum rtw89_scan_be_operation { 3456 RTW89_SCAN_OP_STOP, 3457 RTW89_SCAN_OP_START, 3458 RTW89_SCAN_OP_SETPARM, 3459 RTW89_SCAN_OP_GETRPT, 3460 RTW89_SCAN_OP_NUM 3461 }; 3462 3463 enum rtw89_scan_be_mode { 3464 RTW89_SCAN_MODE_SA, 3465 RTW89_SCAN_MODE_MACC, 3466 RTW89_SCAN_MODE_NUM 3467 }; 3468 3469 enum rtw89_scan_be_opmode { 3470 RTW89_SCAN_OPMODE_NONE, 3471 RTW89_SCAN_OPMODE_TBTT, 3472 RTW89_SCAN_OPMODE_INTV, 3473 RTW89_SCAN_OPMODE_CNT, 3474 RTW89_SCAN_OPMODE_NUM, 3475 }; 3476 3477 struct rtw89_scan_option { 3478 bool enable; 3479 bool target_ch_mode; 3480 u8 num_macc_role; 3481 u8 num_opch; 3482 u8 repeat; 3483 u16 norm_pd; 3484 u16 slow_pd; 3485 u16 norm_cy; 3486 u8 opch_end; 3487 u64 prohib_chan; 3488 enum rtw89_phy_idx band; 3489 enum rtw89_scan_be_operation operation; 3490 enum rtw89_scan_be_mode scan_mode; 3491 enum rtw89_mlo_dbcc_mode mlo_mode; 3492 }; 3493 3494 enum rtw89_qta_mode { 3495 RTW89_QTA_SCC, 3496 RTW89_QTA_DBCC, 3497 RTW89_QTA_DLFW, 3498 RTW89_QTA_WOW, 3499 3500 /* keep last */ 3501 RTW89_QTA_INVALID, 3502 }; 3503 3504 struct rtw89_hfc_ch_cfg { 3505 u16 min; 3506 u16 max; 3507 #define grp_0 0 3508 #define grp_1 1 3509 #define grp_num 2 3510 u8 grp; 3511 }; 3512 3513 struct rtw89_hfc_ch_info { 3514 u16 aval; 3515 u16 used; 3516 }; 3517 3518 struct rtw89_hfc_pub_cfg { 3519 u16 grp0; 3520 u16 grp1; 3521 u16 pub_max; 3522 u16 wp_thrd; 3523 }; 3524 3525 struct rtw89_hfc_pub_info { 3526 u16 g0_used; 3527 u16 g1_used; 3528 u16 g0_aval; 3529 u16 g1_aval; 3530 u16 pub_aval; 3531 u16 wp_aval; 3532 }; 3533 3534 struct rtw89_hfc_prec_cfg { 3535 u16 ch011_prec; 3536 u16 h2c_prec; 3537 u16 wp_ch07_prec; 3538 u16 wp_ch811_prec; 3539 u8 ch011_full_cond; 3540 u8 h2c_full_cond; 3541 u8 wp_ch07_full_cond; 3542 u8 wp_ch811_full_cond; 3543 }; 3544 3545 struct rtw89_hfc_param { 3546 bool en; 3547 bool h2c_en; 3548 u8 mode; 3549 const struct rtw89_hfc_ch_cfg *ch_cfg; 3550 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3551 struct rtw89_hfc_pub_cfg pub_cfg; 3552 struct rtw89_hfc_pub_info pub_info; 3553 struct rtw89_hfc_prec_cfg prec_cfg; 3554 }; 3555 3556 struct rtw89_hfc_param_ini { 3557 const struct rtw89_hfc_ch_cfg *ch_cfg; 3558 const struct rtw89_hfc_pub_cfg *pub_cfg; 3559 const struct rtw89_hfc_prec_cfg *prec_cfg; 3560 u8 mode; 3561 }; 3562 3563 struct rtw89_dle_size { 3564 u16 pge_size; 3565 u16 lnk_pge_num; 3566 u16 unlnk_pge_num; 3567 /* for WiFi 7 chips below */ 3568 u32 srt_ofst; 3569 }; 3570 3571 struct rtw89_wde_quota { 3572 u16 hif; 3573 u16 wcpu; 3574 u16 pkt_in; 3575 u16 cpu_io; 3576 }; 3577 3578 struct rtw89_ple_quota { 3579 u16 cma0_tx; 3580 u16 cma1_tx; 3581 u16 c2h; 3582 u16 h2c; 3583 u16 wcpu; 3584 u16 mpdu_proc; 3585 u16 cma0_dma; 3586 u16 cma1_dma; 3587 u16 bb_rpt; 3588 u16 wd_rel; 3589 u16 cpu_io; 3590 u16 tx_rpt; 3591 /* for WiFi 7 chips below */ 3592 u16 h2d; 3593 }; 3594 3595 struct rtw89_rsvd_quota { 3596 u16 mpdu_info_tbl; 3597 u16 b0_csi; 3598 u16 b1_csi; 3599 u16 b0_lmr; 3600 u16 b1_lmr; 3601 u16 b0_ftm; 3602 u16 b1_ftm; 3603 u16 b0_smr; 3604 u16 b1_smr; 3605 u16 others; 3606 }; 3607 3608 struct rtw89_dle_rsvd_size { 3609 u32 srt_ofst; 3610 u32 size; 3611 }; 3612 3613 struct rtw89_dle_mem { 3614 enum rtw89_qta_mode mode; 3615 const struct rtw89_dle_size *wde_size; 3616 const struct rtw89_dle_size *ple_size; 3617 const struct rtw89_wde_quota *wde_min_qt; 3618 const struct rtw89_wde_quota *wde_max_qt; 3619 const struct rtw89_ple_quota *ple_min_qt; 3620 const struct rtw89_ple_quota *ple_max_qt; 3621 /* for WiFi 7 chips below */ 3622 const struct rtw89_rsvd_quota *rsvd_qt; 3623 const struct rtw89_dle_rsvd_size *rsvd0_size; 3624 const struct rtw89_dle_rsvd_size *rsvd1_size; 3625 }; 3626 3627 struct rtw89_reg_def { 3628 u32 addr; 3629 u32 mask; 3630 }; 3631 3632 struct rtw89_reg2_def { 3633 u32 addr; 3634 u32 data; 3635 }; 3636 3637 struct rtw89_reg3_def { 3638 u32 addr; 3639 u32 mask; 3640 u32 data; 3641 }; 3642 3643 struct rtw89_reg5_def { 3644 u8 flag; /* recognized by parsers */ 3645 u8 path; 3646 u32 addr; 3647 u32 mask; 3648 u32 data; 3649 }; 3650 3651 struct rtw89_reg_imr { 3652 u32 addr; 3653 u32 clr; 3654 u32 set; 3655 }; 3656 3657 struct rtw89_phy_table { 3658 const struct rtw89_reg2_def *regs; 3659 u32 n_regs; 3660 enum rtw89_rf_path rf_path; 3661 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3662 enum rtw89_rf_path rf_path, void *data); 3663 }; 3664 3665 struct rtw89_txpwr_table { 3666 const void *data; 3667 u32 size; 3668 void (*load)(struct rtw89_dev *rtwdev, 3669 const struct rtw89_txpwr_table *tbl); 3670 }; 3671 3672 struct rtw89_txpwr_rule_2ghz { 3673 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3674 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3675 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3676 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3677 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3678 }; 3679 3680 struct rtw89_txpwr_rule_5ghz { 3681 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3682 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3683 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3684 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3685 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3686 }; 3687 3688 struct rtw89_txpwr_rule_6ghz { 3689 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3690 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3691 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3692 [RTW89_6G_CH_NUM]; 3693 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3694 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3695 [RTW89_6G_CH_NUM]; 3696 }; 3697 3698 struct rtw89_tx_shape { 3699 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3700 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3701 }; 3702 3703 struct rtw89_rfe_parms { 3704 const struct rtw89_txpwr_table *byr_tbl; 3705 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3706 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3707 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3708 struct rtw89_tx_shape tx_shape; 3709 }; 3710 3711 struct rtw89_rfe_parms_conf { 3712 const struct rtw89_rfe_parms *rfe_parms; 3713 u8 rfe_type; 3714 }; 3715 3716 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3717 3718 struct rtw89_txpwr_conf { 3719 u8 rfe_type; 3720 u8 ent_sz; 3721 u32 num_ents; 3722 const void *data; 3723 }; 3724 3725 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3726 3727 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3728 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3729 memcpy(&(entry), cursor, \ 3730 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3731 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3732 (cursor) += (conf)->ent_sz, \ 3733 memcpy(&(entry), cursor, \ 3734 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3735 3736 struct rtw89_txpwr_byrate_data { 3737 struct rtw89_txpwr_conf conf; 3738 struct rtw89_txpwr_table tbl; 3739 }; 3740 3741 struct rtw89_txpwr_lmt_2ghz_data { 3742 struct rtw89_txpwr_conf conf; 3743 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3744 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3745 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3746 }; 3747 3748 struct rtw89_txpwr_lmt_5ghz_data { 3749 struct rtw89_txpwr_conf conf; 3750 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3751 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3752 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3753 }; 3754 3755 struct rtw89_txpwr_lmt_6ghz_data { 3756 struct rtw89_txpwr_conf conf; 3757 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3758 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3759 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3760 [RTW89_6G_CH_NUM]; 3761 }; 3762 3763 struct rtw89_txpwr_lmt_ru_2ghz_data { 3764 struct rtw89_txpwr_conf conf; 3765 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3766 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3767 }; 3768 3769 struct rtw89_txpwr_lmt_ru_5ghz_data { 3770 struct rtw89_txpwr_conf conf; 3771 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3772 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3773 }; 3774 3775 struct rtw89_txpwr_lmt_ru_6ghz_data { 3776 struct rtw89_txpwr_conf conf; 3777 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3778 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3779 [RTW89_6G_CH_NUM]; 3780 }; 3781 3782 struct rtw89_tx_shape_lmt_data { 3783 struct rtw89_txpwr_conf conf; 3784 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3785 }; 3786 3787 struct rtw89_tx_shape_lmt_ru_data { 3788 struct rtw89_txpwr_conf conf; 3789 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3790 }; 3791 3792 struct rtw89_rfe_data { 3793 struct rtw89_txpwr_byrate_data byrate; 3794 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3795 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3796 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3797 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3798 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3799 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3800 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3801 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3802 struct rtw89_rfe_parms rfe_parms; 3803 }; 3804 3805 struct rtw89_page_regs { 3806 u32 hci_fc_ctrl; 3807 u32 ch_page_ctrl; 3808 u32 ach_page_ctrl; 3809 u32 ach_page_info; 3810 u32 pub_page_info3; 3811 u32 pub_page_ctrl1; 3812 u32 pub_page_ctrl2; 3813 u32 pub_page_info1; 3814 u32 pub_page_info2; 3815 u32 wp_page_ctrl1; 3816 u32 wp_page_ctrl2; 3817 u32 wp_page_info1; 3818 }; 3819 3820 struct rtw89_imr_info { 3821 u32 wdrls_imr_set; 3822 u32 wsec_imr_reg; 3823 u32 wsec_imr_set; 3824 u32 mpdu_tx_imr_set; 3825 u32 mpdu_rx_imr_set; 3826 u32 sta_sch_imr_set; 3827 u32 txpktctl_imr_b0_reg; 3828 u32 txpktctl_imr_b0_clr; 3829 u32 txpktctl_imr_b0_set; 3830 u32 txpktctl_imr_b1_reg; 3831 u32 txpktctl_imr_b1_clr; 3832 u32 txpktctl_imr_b1_set; 3833 u32 wde_imr_clr; 3834 u32 wde_imr_set; 3835 u32 ple_imr_clr; 3836 u32 ple_imr_set; 3837 u32 host_disp_imr_clr; 3838 u32 host_disp_imr_set; 3839 u32 cpu_disp_imr_clr; 3840 u32 cpu_disp_imr_set; 3841 u32 other_disp_imr_clr; 3842 u32 other_disp_imr_set; 3843 u32 bbrpt_com_err_imr_reg; 3844 u32 bbrpt_chinfo_err_imr_reg; 3845 u32 bbrpt_err_imr_set; 3846 u32 bbrpt_dfs_err_imr_reg; 3847 u32 ptcl_imr_clr; 3848 u32 ptcl_imr_set; 3849 u32 cdma_imr_0_reg; 3850 u32 cdma_imr_0_clr; 3851 u32 cdma_imr_0_set; 3852 u32 cdma_imr_1_reg; 3853 u32 cdma_imr_1_clr; 3854 u32 cdma_imr_1_set; 3855 u32 phy_intf_imr_reg; 3856 u32 phy_intf_imr_clr; 3857 u32 phy_intf_imr_set; 3858 u32 rmac_imr_reg; 3859 u32 rmac_imr_clr; 3860 u32 rmac_imr_set; 3861 u32 tmac_imr_reg; 3862 u32 tmac_imr_clr; 3863 u32 tmac_imr_set; 3864 }; 3865 3866 struct rtw89_imr_table { 3867 const struct rtw89_reg_imr *regs; 3868 u32 n_regs; 3869 }; 3870 3871 struct rtw89_xtal_info { 3872 u32 xcap_reg; 3873 u32 sc_xo_mask; 3874 u32 sc_xi_mask; 3875 }; 3876 3877 struct rtw89_rrsr_cfgs { 3878 struct rtw89_reg3_def ref_rate; 3879 struct rtw89_reg3_def rsc; 3880 }; 3881 3882 struct rtw89_dig_regs { 3883 u32 seg0_pd_reg; 3884 u32 pd_lower_bound_mask; 3885 u32 pd_spatial_reuse_en; 3886 u32 bmode_pd_reg; 3887 u32 bmode_cca_rssi_limit_en; 3888 u32 bmode_pd_lower_bound_reg; 3889 u32 bmode_rssi_nocca_low_th_mask; 3890 struct rtw89_reg_def p0_lna_init; 3891 struct rtw89_reg_def p1_lna_init; 3892 struct rtw89_reg_def p0_tia_init; 3893 struct rtw89_reg_def p1_tia_init; 3894 struct rtw89_reg_def p0_rxb_init; 3895 struct rtw89_reg_def p1_rxb_init; 3896 struct rtw89_reg_def p0_p20_pagcugc_en; 3897 struct rtw89_reg_def p0_s20_pagcugc_en; 3898 struct rtw89_reg_def p1_p20_pagcugc_en; 3899 struct rtw89_reg_def p1_s20_pagcugc_en; 3900 }; 3901 3902 struct rtw89_edcca_regs { 3903 u32 edcca_level; 3904 u32 edcca_mask; 3905 u32 edcca_p_mask; 3906 u32 ppdu_level; 3907 u32 ppdu_mask; 3908 u32 rpt_a; 3909 u32 rpt_b; 3910 u32 rpt_sel; 3911 u32 rpt_sel_mask; 3912 u32 rpt_sel_be; 3913 u32 rpt_sel_be_mask; 3914 u32 tx_collision_t2r_st; 3915 u32 tx_collision_t2r_st_mask; 3916 }; 3917 3918 struct rtw89_phy_ul_tb_info { 3919 bool dyn_tb_tri_en; 3920 u8 def_if_bandedge; 3921 }; 3922 3923 struct rtw89_antdiv_stats { 3924 struct ewma_rssi cck_rssi_avg; 3925 struct ewma_rssi ofdm_rssi_avg; 3926 struct ewma_rssi non_legacy_rssi_avg; 3927 u16 pkt_cnt_cck; 3928 u16 pkt_cnt_ofdm; 3929 u16 pkt_cnt_non_legacy; 3930 u32 evm; 3931 }; 3932 3933 struct rtw89_antdiv_info { 3934 struct rtw89_antdiv_stats target_stats; 3935 struct rtw89_antdiv_stats main_stats; 3936 struct rtw89_antdiv_stats aux_stats; 3937 u8 training_count; 3938 u8 rssi_pre; 3939 bool get_stats; 3940 }; 3941 3942 enum rtw89_chanctx_state { 3943 RTW89_CHANCTX_STATE_MCC_START, 3944 RTW89_CHANCTX_STATE_MCC_STOP, 3945 }; 3946 3947 enum rtw89_chanctx_callbacks { 3948 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 3949 RTW89_CHANCTX_CALLBACK_RFK, 3950 3951 NUM_OF_RTW89_CHANCTX_CALLBACKS, 3952 }; 3953 3954 struct rtw89_chanctx_listener { 3955 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 3956 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 3957 }; 3958 3959 struct rtw89_chip_info { 3960 enum rtw89_core_chip_id chip_id; 3961 enum rtw89_chip_gen chip_gen; 3962 const struct rtw89_chip_ops *ops; 3963 const struct rtw89_mac_gen_def *mac_def; 3964 const struct rtw89_phy_gen_def *phy_def; 3965 const char *fw_basename; 3966 u8 fw_format_max; 3967 bool try_ce_fw; 3968 u8 bbmcu_nr; 3969 u32 needed_fw_elms; 3970 u32 fifo_size; 3971 bool small_fifo_size; 3972 u32 dle_scc_rsvd_size; 3973 u16 max_amsdu_limit; 3974 bool dis_2g_40m_ul_ofdma; 3975 u32 rsvd_ple_ofst; 3976 const struct rtw89_hfc_param_ini *hfc_param_ini; 3977 const struct rtw89_dle_mem *dle_mem; 3978 u8 wde_qempty_acq_grpnum; 3979 u8 wde_qempty_mgq_grpsel; 3980 u32 rf_base_addr[2]; 3981 u8 support_chanctx_num; 3982 u8 support_bands; 3983 u16 support_bandwidths; 3984 bool support_unii4; 3985 bool support_rnr; 3986 bool ul_tb_waveform_ctrl; 3987 bool ul_tb_pwr_diff; 3988 bool hw_sec_hdr; 3989 u8 rf_path_num; 3990 u8 tx_nss; 3991 u8 rx_nss; 3992 u8 acam_num; 3993 u8 bcam_num; 3994 u8 scam_num; 3995 u8 bacam_num; 3996 u8 bacam_dynamic_num; 3997 enum rtw89_bacam_ver bacam_ver; 3998 u8 ppdu_max_usr; 3999 4000 u8 sec_ctrl_efuse_size; 4001 u32 physical_efuse_size; 4002 u32 logical_efuse_size; 4003 u32 limit_efuse_size; 4004 u32 dav_phy_efuse_size; 4005 u32 dav_log_efuse_size; 4006 u32 phycap_addr; 4007 u32 phycap_size; 4008 const struct rtw89_efuse_block_cfg *efuse_blocks; 4009 4010 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4011 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4012 const struct rtw89_phy_table *bb_table; 4013 const struct rtw89_phy_table *bb_gain_table; 4014 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4015 const struct rtw89_phy_table *nctl_table; 4016 const struct rtw89_rfk_tbl *nctl_post_table; 4017 const struct rtw89_phy_dig_gain_table *dig_table; 4018 const struct rtw89_dig_regs *dig_regs; 4019 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4020 4021 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4022 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4023 const struct rtw89_rfe_parms *dflt_parms; 4024 const struct rtw89_chanctx_listener *chanctx_listener; 4025 4026 u8 txpwr_factor_rf; 4027 u8 txpwr_factor_mac; 4028 4029 u32 para_ver; 4030 u32 wlcx_desired; 4031 u8 btcx_desired; 4032 u8 scbd; 4033 u8 mailbox; 4034 4035 u8 afh_guard_ch; 4036 const u8 *wl_rssi_thres; 4037 const u8 *bt_rssi_thres; 4038 u8 rssi_tol; 4039 4040 u8 mon_reg_num; 4041 const struct rtw89_btc_fbtc_mreg *mon_reg; 4042 u8 rf_para_ulink_num; 4043 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4044 u8 rf_para_dlink_num; 4045 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4046 u8 ps_mode_supported; 4047 u8 low_power_hci_modes; 4048 4049 u32 h2c_cctl_func_id; 4050 u32 hci_func_en_addr; 4051 u32 h2c_desc_size; 4052 u32 txwd_body_size; 4053 u32 txwd_info_size; 4054 u32 h2c_ctrl_reg; 4055 const u32 *h2c_regs; 4056 struct rtw89_reg_def h2c_counter_reg; 4057 u32 c2h_ctrl_reg; 4058 const u32 *c2h_regs; 4059 struct rtw89_reg_def c2h_counter_reg; 4060 const struct rtw89_page_regs *page_regs; 4061 u32 wow_reason_reg; 4062 bool cfo_src_fd; 4063 bool cfo_hw_comp; 4064 const struct rtw89_reg_def *dcfo_comp; 4065 u8 dcfo_comp_sft; 4066 const struct rtw89_imr_info *imr_info; 4067 const struct rtw89_imr_table *imr_dmac_table; 4068 const struct rtw89_imr_table *imr_cmac_table; 4069 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4070 struct rtw89_reg_def bss_clr_vld; 4071 u32 bss_clr_map_reg; 4072 u32 dma_ch_mask; 4073 const struct rtw89_edcca_regs *edcca_regs; 4074 const struct wiphy_wowlan_support *wowlan_stub; 4075 const struct rtw89_xtal_info *xtal_info; 4076 }; 4077 4078 union rtw89_bus_info { 4079 const struct rtw89_pci_info *pci; 4080 }; 4081 4082 struct rtw89_driver_info { 4083 const struct rtw89_chip_info *chip; 4084 const struct dmi_system_id *quirks; 4085 union rtw89_bus_info bus; 4086 }; 4087 4088 enum rtw89_hcifc_mode { 4089 RTW89_HCIFC_POH = 0, 4090 RTW89_HCIFC_STF = 1, 4091 RTW89_HCIFC_SDIO = 2, 4092 4093 /* keep last */ 4094 RTW89_HCIFC_MODE_INVALID, 4095 }; 4096 4097 struct rtw89_dle_info { 4098 const struct rtw89_rsvd_quota *rsvd_qt; 4099 enum rtw89_qta_mode qta_mode; 4100 u16 ple_pg_size; 4101 u16 ple_free_pg; 4102 u16 c0_rx_qta; 4103 u16 c1_rx_qta; 4104 }; 4105 4106 enum rtw89_host_rpr_mode { 4107 RTW89_RPR_MODE_POH = 0, 4108 RTW89_RPR_MODE_STF 4109 }; 4110 4111 #define RTW89_COMPLETION_BUF_SIZE 40 4112 #define RTW89_WAIT_COND_IDLE UINT_MAX 4113 4114 struct rtw89_completion_data { 4115 bool err; 4116 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4117 }; 4118 4119 struct rtw89_wait_info { 4120 atomic_t cond; 4121 struct completion completion; 4122 struct rtw89_completion_data data; 4123 }; 4124 4125 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4126 4127 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4128 { 4129 init_completion(&wait->completion); 4130 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4131 } 4132 4133 struct rtw89_mac_info { 4134 struct rtw89_dle_info dle_info; 4135 struct rtw89_hfc_param hfc_param; 4136 enum rtw89_qta_mode qta_mode; 4137 u8 rpwm_seq_num; 4138 u8 cpwm_seq_num; 4139 4140 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4141 struct rtw89_wait_info fw_ofld_wait; 4142 }; 4143 4144 enum rtw89_fwdl_check_type { 4145 RTW89_FWDL_CHECK_FREERTOS_DONE, 4146 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4147 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4148 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4149 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4150 }; 4151 4152 enum rtw89_fw_type { 4153 RTW89_FW_NORMAL = 1, 4154 RTW89_FW_WOWLAN = 3, 4155 RTW89_FW_NORMAL_CE = 5, 4156 RTW89_FW_BBMCU0 = 64, 4157 RTW89_FW_BBMCU1 = 65, 4158 RTW89_FW_LOGFMT = 255, 4159 }; 4160 4161 enum rtw89_fw_feature { 4162 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4163 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4164 RTW89_FW_FEATURE_TX_WAKE, 4165 RTW89_FW_FEATURE_CRASH_TRIGGER, 4166 RTW89_FW_FEATURE_NO_PACKET_DROP, 4167 RTW89_FW_FEATURE_NO_DEEP_PS, 4168 RTW89_FW_FEATURE_NO_LPS_PG, 4169 RTW89_FW_FEATURE_BEACON_FILTER, 4170 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4171 }; 4172 4173 struct rtw89_fw_suit { 4174 enum rtw89_fw_type type; 4175 const u8 *data; 4176 u32 size; 4177 u8 major_ver; 4178 u8 minor_ver; 4179 u8 sub_ver; 4180 u8 sub_idex; 4181 u16 build_year; 4182 u16 build_mon; 4183 u16 build_date; 4184 u16 build_hour; 4185 u16 build_min; 4186 u8 cmd_ver; 4187 u8 hdr_ver; 4188 u32 commitid; 4189 }; 4190 4191 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4192 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4193 #define RTW89_FW_SUIT_VER_CODE(s) \ 4194 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4195 4196 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4197 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4198 (mfw_hdr)->ver.minor, \ 4199 (mfw_hdr)->ver.sub, \ 4200 (mfw_hdr)->ver.idx) 4201 4202 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4203 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4204 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4205 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4206 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4207 4208 struct rtw89_fw_req_info { 4209 const struct firmware *firmware; 4210 struct completion completion; 4211 }; 4212 4213 struct rtw89_fw_log { 4214 struct rtw89_fw_suit suit; 4215 bool enable; 4216 u32 last_fmt_id; 4217 u32 fmt_count; 4218 const __le32 *fmt_ids; 4219 const char *(*fmts)[]; 4220 }; 4221 4222 struct rtw89_fw_elm_info { 4223 struct rtw89_phy_table *bb_tbl; 4224 struct rtw89_phy_table *bb_gain; 4225 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4226 struct rtw89_phy_table *rf_nctl; 4227 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4228 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4229 }; 4230 4231 enum rtw89_fw_mss_dev_type { 4232 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4233 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4234 }; 4235 4236 struct rtw89_fw_secure { 4237 bool secure_boot; 4238 u32 sb_sel_mgn; 4239 u8 mss_dev_type; 4240 u8 mss_cust_idx; 4241 u8 mss_key_num; 4242 }; 4243 4244 struct rtw89_fw_info { 4245 struct rtw89_fw_req_info req; 4246 int fw_format; 4247 u8 h2c_seq; 4248 u8 rec_seq; 4249 u8 h2c_counter; 4250 u8 c2h_counter; 4251 struct rtw89_fw_suit normal; 4252 struct rtw89_fw_suit wowlan; 4253 struct rtw89_fw_suit bbmcu0; 4254 struct rtw89_fw_suit bbmcu1; 4255 struct rtw89_fw_log log; 4256 u32 feature_map; 4257 struct rtw89_fw_elm_info elm_info; 4258 struct rtw89_fw_secure sec; 4259 }; 4260 4261 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4262 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4263 4264 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4265 ((_fw)->feature_map |= BIT(_fw_feature)) 4266 4267 struct rtw89_cam_info { 4268 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4269 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4270 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4271 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4272 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4273 }; 4274 4275 enum rtw89_sar_sources { 4276 RTW89_SAR_SOURCE_NONE, 4277 RTW89_SAR_SOURCE_COMMON, 4278 4279 RTW89_SAR_SOURCE_NR, 4280 }; 4281 4282 enum rtw89_sar_subband { 4283 RTW89_SAR_2GHZ_SUBBAND, 4284 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4285 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4286 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 4287 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4288 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4289 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4290 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4291 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4292 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4293 4294 RTW89_SAR_SUBBAND_NR, 4295 }; 4296 4297 struct rtw89_sar_cfg_common { 4298 bool set[RTW89_SAR_SUBBAND_NR]; 4299 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4300 }; 4301 4302 struct rtw89_sar_info { 4303 /* used to decide how to acces SAR cfg union */ 4304 enum rtw89_sar_sources src; 4305 4306 /* reserved for different knids of SAR cfg struct. 4307 * supposed that a single cfg struct cannot handle various SAR sources. 4308 */ 4309 union { 4310 struct rtw89_sar_cfg_common cfg_common; 4311 }; 4312 }; 4313 4314 enum rtw89_tas_state { 4315 RTW89_TAS_STATE_DPR_OFF, 4316 RTW89_TAS_STATE_DPR_ON, 4317 RTW89_TAS_STATE_DPR_FORBID, 4318 }; 4319 4320 #define RTW89_TAS_MAX_WINDOW 50 4321 struct rtw89_tas_info { 4322 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4323 s32 total_txpwr; 4324 u8 cur_idx; 4325 s8 dpr_gap; 4326 s8 delta; 4327 enum rtw89_tas_state state; 4328 bool enable; 4329 }; 4330 4331 struct rtw89_chanctx_cfg { 4332 enum rtw89_sub_entity_idx idx; 4333 int ref_count; 4334 }; 4335 4336 enum rtw89_chanctx_changes { 4337 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4338 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4339 RTW89_CHANCTX_P2P_PS_CHANGE, 4340 RTW89_CHANCTX_BT_SLOT_CHANGE, 4341 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4342 4343 NUM_OF_RTW89_CHANCTX_CHANGES, 4344 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4345 }; 4346 4347 enum rtw89_entity_mode { 4348 RTW89_ENTITY_MODE_SCC, 4349 RTW89_ENTITY_MODE_MCC_PREPARE, 4350 RTW89_ENTITY_MODE_MCC, 4351 4352 NUM_OF_RTW89_ENTITY_MODE, 4353 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4354 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4355 }; 4356 4357 struct rtw89_sub_entity { 4358 struct cfg80211_chan_def chandef; 4359 struct rtw89_chan chan; 4360 struct rtw89_chan_rcd rcd; 4361 4362 /* only assigned when running with chanctx_ops */ 4363 struct rtw89_chanctx_cfg *cfg; 4364 }; 4365 4366 struct rtw89_edcca_bak { 4367 u8 a; 4368 u8 p; 4369 u8 ppdu; 4370 u8 th_old; 4371 }; 4372 4373 enum rtw89_dm_type { 4374 RTW89_DM_DYNAMIC_EDCCA, 4375 }; 4376 4377 struct rtw89_hal { 4378 u32 rx_fltr; 4379 u8 cv; 4380 u8 acv; 4381 u32 antenna_tx; 4382 u32 antenna_rx; 4383 u8 tx_nss; 4384 u8 rx_nss; 4385 bool tx_path_diversity; 4386 bool ant_diversity; 4387 bool ant_diversity_fixed; 4388 bool support_cckpd; 4389 bool support_igi; 4390 atomic_t roc_entity_idx; 4391 4392 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4393 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 4394 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 4395 struct cfg80211_chan_def roc_chandef; 4396 4397 bool entity_active; 4398 bool entity_pause; 4399 enum rtw89_entity_mode entity_mode; 4400 4401 struct rtw89_edcca_bak edcca_bak; 4402 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4403 }; 4404 4405 #define RTW89_MAX_MAC_ID_NUM 128 4406 #define RTW89_MAX_PKT_OFLD_NUM 255 4407 4408 enum rtw89_flags { 4409 RTW89_FLAG_POWERON, 4410 RTW89_FLAG_DMAC_FUNC, 4411 RTW89_FLAG_CMAC0_FUNC, 4412 RTW89_FLAG_CMAC1_FUNC, 4413 RTW89_FLAG_FW_RDY, 4414 RTW89_FLAG_RUNNING, 4415 RTW89_FLAG_PROBE_DONE, 4416 RTW89_FLAG_BFEE_MON, 4417 RTW89_FLAG_BFEE_EN, 4418 RTW89_FLAG_BFEE_TIMER_KEEP, 4419 RTW89_FLAG_NAPI_RUNNING, 4420 RTW89_FLAG_LEISURE_PS, 4421 RTW89_FLAG_LOW_POWER_MODE, 4422 RTW89_FLAG_INACTIVE_PS, 4423 RTW89_FLAG_CRASH_SIMULATING, 4424 RTW89_FLAG_SER_HANDLING, 4425 RTW89_FLAG_WOWLAN, 4426 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4427 RTW89_FLAG_CHANGING_INTERFACE, 4428 4429 NUM_OF_RTW89_FLAGS, 4430 }; 4431 4432 enum rtw89_quirks { 4433 RTW89_QUIRK_PCI_BER, 4434 4435 NUM_OF_RTW89_QUIRKS, 4436 }; 4437 4438 enum rtw89_pkt_drop_sel { 4439 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4440 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4441 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4442 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4443 RTW89_PKT_DROP_SEL_MACID_ALL, 4444 RTW89_PKT_DROP_SEL_MG0_ONCE, 4445 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4446 RTW89_PKT_DROP_SEL_HIQ_PORT, 4447 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4448 RTW89_PKT_DROP_SEL_BAND, 4449 RTW89_PKT_DROP_SEL_BAND_ONCE, 4450 RTW89_PKT_DROP_SEL_REL_MACID, 4451 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4452 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4453 }; 4454 4455 struct rtw89_pkt_drop_params { 4456 enum rtw89_pkt_drop_sel sel; 4457 enum rtw89_mac_idx mac_band; 4458 u8 macid; 4459 u8 port; 4460 u8 mbssid; 4461 bool tf_trs; 4462 u32 macid_band_sel[4]; 4463 }; 4464 4465 struct rtw89_pkt_stat { 4466 u16 beacon_nr; 4467 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4468 }; 4469 4470 DECLARE_EWMA(thermal, 4, 4); 4471 4472 struct rtw89_phy_stat { 4473 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4474 struct rtw89_pkt_stat cur_pkt_stat; 4475 struct rtw89_pkt_stat last_pkt_stat; 4476 }; 4477 4478 enum rtw89_rfk_report_state { 4479 RTW89_RFK_STATE_START = 0x0, 4480 RTW89_RFK_STATE_OK = 0x1, 4481 RTW89_RFK_STATE_FAIL = 0x2, 4482 RTW89_RFK_STATE_TIMEOUT = 0x3, 4483 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4484 }; 4485 4486 struct rtw89_rfk_wait_info { 4487 struct completion completion; 4488 ktime_t start_time; 4489 enum rtw89_rfk_report_state state; 4490 u8 version; 4491 }; 4492 4493 #define RTW89_DACK_PATH_NR 2 4494 #define RTW89_DACK_IDX_NR 2 4495 #define RTW89_DACK_MSBK_NR 16 4496 struct rtw89_dack_info { 4497 bool dack_done; 4498 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4499 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4500 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4501 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4502 u32 dack_cnt; 4503 bool addck_timeout[RTW89_DACK_PATH_NR]; 4504 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4505 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4506 }; 4507 4508 #define RTW89_RFK_CHS_NR 3 4509 4510 struct rtw89_rfk_mcc_info { 4511 u8 ch[RTW89_RFK_CHS_NR]; 4512 u8 band[RTW89_RFK_CHS_NR]; 4513 u8 bw[RTW89_RFK_CHS_NR]; 4514 u8 table_idx; 4515 }; 4516 4517 #define RTW89_IQK_CHS_NR 2 4518 #define RTW89_IQK_PATH_NR 4 4519 4520 struct rtw89_lck_info { 4521 u8 thermal[RF_PATH_MAX]; 4522 }; 4523 4524 struct rtw89_rx_dck_info { 4525 u8 thermal[RF_PATH_MAX]; 4526 }; 4527 4528 struct rtw89_iqk_info { 4529 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4530 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4531 bool lok_fail[RTW89_IQK_PATH_NR]; 4532 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4533 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4534 u32 iqk_fail_cnt; 4535 bool is_iqk_init; 4536 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4537 u8 iqk_band[RTW89_IQK_PATH_NR]; 4538 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4539 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4540 u8 iqk_times; 4541 u8 version; 4542 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4543 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4544 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4545 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4546 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4547 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4548 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4549 bool is_nbiqk; 4550 bool iqk_fft_en; 4551 bool iqk_xym_en; 4552 bool iqk_sram_en; 4553 bool iqk_cfir_en; 4554 u32 syn1to2; 4555 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4556 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4557 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4558 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4559 }; 4560 4561 #define RTW89_DPK_RF_PATH 2 4562 #define RTW89_DPK_AVG_THERMAL_NUM 8 4563 #define RTW89_DPK_BKUP_NUM 2 4564 struct rtw89_dpk_bkup_para { 4565 enum rtw89_band band; 4566 enum rtw89_bandwidth bw; 4567 u8 ch; 4568 bool path_ok; 4569 u8 mdpd_en; 4570 u8 txagc_dpk; 4571 u8 ther_dpk; 4572 u8 gs; 4573 u16 pwsf; 4574 }; 4575 4576 struct rtw89_dpk_info { 4577 bool is_dpk_enable; 4578 bool is_dpk_reload_en; 4579 u8 dpk_gs[RTW89_PHY_MAX]; 4580 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4581 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4582 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4583 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4584 u8 cur_idx[RTW89_DPK_RF_PATH]; 4585 u8 cur_k_set; 4586 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4587 }; 4588 4589 struct rtw89_fem_info { 4590 bool elna_2g; 4591 bool elna_5g; 4592 bool epa_2g; 4593 bool epa_5g; 4594 bool epa_6g; 4595 }; 4596 4597 struct rtw89_phy_ch_info { 4598 u8 rssi_min; 4599 u16 rssi_min_macid; 4600 u8 pre_rssi_min; 4601 u8 rssi_max; 4602 u16 rssi_max_macid; 4603 u8 rxsc_160; 4604 u8 rxsc_80; 4605 u8 rxsc_40; 4606 u8 rxsc_20; 4607 u8 rxsc_l; 4608 u8 is_noisy; 4609 }; 4610 4611 struct rtw89_agc_gaincode_set { 4612 u8 lna_idx; 4613 u8 tia_idx; 4614 u8 rxb_idx; 4615 }; 4616 4617 #define IGI_RSSI_TH_NUM 5 4618 #define FA_TH_NUM 4 4619 #define LNA_GAIN_NUM 7 4620 #define TIA_GAIN_NUM 2 4621 struct rtw89_dig_info { 4622 struct rtw89_agc_gaincode_set cur_gaincode; 4623 bool force_gaincode_idx_en; 4624 struct rtw89_agc_gaincode_set force_gaincode; 4625 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4626 u16 fa_th[FA_TH_NUM]; 4627 u8 igi_rssi; 4628 u8 igi_fa_rssi; 4629 u8 fa_rssi_ofst; 4630 u8 dyn_igi_max; 4631 u8 dyn_igi_min; 4632 bool dyn_pd_th_en; 4633 u8 dyn_pd_th_max; 4634 u8 pd_low_th_ofst; 4635 u8 ib_pbk; 4636 s8 ib_pkpwr; 4637 s8 lna_gain_a[LNA_GAIN_NUM]; 4638 s8 lna_gain_g[LNA_GAIN_NUM]; 4639 s8 *lna_gain; 4640 s8 tia_gain_a[TIA_GAIN_NUM]; 4641 s8 tia_gain_g[TIA_GAIN_NUM]; 4642 s8 *tia_gain; 4643 bool is_linked_pre; 4644 bool bypass_dig; 4645 }; 4646 4647 enum rtw89_multi_cfo_mode { 4648 RTW89_PKT_BASED_AVG_MODE = 0, 4649 RTW89_ENTRY_BASED_AVG_MODE = 1, 4650 RTW89_TP_BASED_AVG_MODE = 2, 4651 }; 4652 4653 enum rtw89_phy_cfo_status { 4654 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4655 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4656 RTW89_PHY_DCFO_STATE_HOLD = 2, 4657 RTW89_PHY_DCFO_STATE_MAX 4658 }; 4659 4660 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4661 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4662 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4663 }; 4664 4665 struct rtw89_cfo_tracking_info { 4666 u16 cfo_timer_ms; 4667 bool cfo_trig_by_timer_en; 4668 enum rtw89_phy_cfo_status phy_cfo_status; 4669 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4670 u8 phy_cfo_trk_cnt; 4671 bool is_adjust; 4672 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4673 bool apply_compensation; 4674 u8 crystal_cap; 4675 u8 crystal_cap_default; 4676 u8 def_x_cap; 4677 s8 x_cap_ofst; 4678 u32 sta_cfo_tolerance; 4679 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4680 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4681 s32 cfo_avg_pre; 4682 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4683 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4684 s32 dcfo_avg; 4685 s32 dcfo_avg_pre; 4686 u32 packet_count; 4687 u32 packet_count_pre; 4688 s32 residual_cfo_acc; 4689 u8 phy_cfotrk_state; 4690 u8 phy_cfotrk_cnt; 4691 bool divergence_lock_en; 4692 u8 x_cap_lb; 4693 u8 x_cap_ub; 4694 u8 lock_cnt; 4695 }; 4696 4697 enum rtw89_tssi_mode { 4698 RTW89_TSSI_NORMAL = 0, 4699 RTW89_TSSI_SCAN = 1, 4700 }; 4701 4702 enum rtw89_tssi_alimk_band { 4703 TSSI_ALIMK_2G = 0, 4704 TSSI_ALIMK_5GL, 4705 TSSI_ALIMK_5GM, 4706 TSSI_ALIMK_5GH, 4707 TSSI_ALIMK_MAX 4708 }; 4709 4710 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4711 #define TSSI_TRIM_CH_GROUP_NUM 8 4712 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4713 4714 #define TSSI_CCK_CH_GROUP_NUM 6 4715 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4716 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4717 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4718 #define TSSI_MCS_CH_GROUP_NUM \ 4719 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4720 #define TSSI_MAX_CH_NUM 67 4721 #define TSSI_ALIMK_VALUE_NUM 8 4722 4723 struct rtw89_tssi_info { 4724 u8 thermal[RF_PATH_MAX]; 4725 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4726 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4727 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4728 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4729 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4730 s8 extra_ofst[RF_PATH_MAX]; 4731 bool tssi_tracking_check[RF_PATH_MAX]; 4732 u8 default_txagc_offset[RF_PATH_MAX]; 4733 u32 base_thermal[RF_PATH_MAX]; 4734 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4735 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4736 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4737 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4738 u32 tssi_alimk_time; 4739 }; 4740 4741 struct rtw89_power_trim_info { 4742 bool pg_thermal_trim; 4743 bool pg_pa_bias_trim; 4744 u8 thermal_trim[RF_PATH_MAX]; 4745 u8 pa_bias_trim[RF_PATH_MAX]; 4746 u8 pad_bias_trim[RF_PATH_MAX]; 4747 }; 4748 4749 struct rtw89_regd { 4750 char alpha2[3]; 4751 u8 txpwr_regd[RTW89_BAND_NUM]; 4752 }; 4753 4754 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 4755 4756 struct rtw89_regulatory_info { 4757 const struct rtw89_regd *regd; 4758 enum rtw89_reg_6ghz_power reg_6ghz_power; 4759 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 4760 }; 4761 4762 enum rtw89_ifs_clm_application { 4763 RTW89_IFS_CLM_INIT = 0, 4764 RTW89_IFS_CLM_BACKGROUND = 1, 4765 RTW89_IFS_CLM_ACS = 2, 4766 RTW89_IFS_CLM_DIG = 3, 4767 RTW89_IFS_CLM_TDMA_DIG = 4, 4768 RTW89_IFS_CLM_DBG = 5, 4769 RTW89_IFS_CLM_DBG_MANUAL = 6 4770 }; 4771 4772 enum rtw89_env_racing_lv { 4773 RTW89_RAC_RELEASE = 0, 4774 RTW89_RAC_LV_1 = 1, 4775 RTW89_RAC_LV_2 = 2, 4776 RTW89_RAC_LV_3 = 3, 4777 RTW89_RAC_LV_4 = 4, 4778 RTW89_RAC_MAX_NUM = 5 4779 }; 4780 4781 struct rtw89_ccx_para_info { 4782 enum rtw89_env_racing_lv rac_lv; 4783 u16 mntr_time; 4784 u8 nhm_manual_th_ofst; 4785 u8 nhm_manual_th0; 4786 enum rtw89_ifs_clm_application ifs_clm_app; 4787 u32 ifs_clm_manual_th_times; 4788 u32 ifs_clm_manual_th0; 4789 u8 fahm_manual_th_ofst; 4790 u8 fahm_manual_th0; 4791 u8 fahm_numer_opt; 4792 u8 fahm_denom_opt; 4793 }; 4794 4795 enum rtw89_ccx_edcca_opt_sc_idx { 4796 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4797 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4798 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4799 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4800 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4801 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4802 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4803 RTW89_CCX_EDCCA_SEG1_S3 = 7 4804 }; 4805 4806 enum rtw89_ccx_edcca_opt_bw_idx { 4807 RTW89_CCX_EDCCA_BW20_0 = 0, 4808 RTW89_CCX_EDCCA_BW20_1 = 1, 4809 RTW89_CCX_EDCCA_BW20_2 = 2, 4810 RTW89_CCX_EDCCA_BW20_3 = 3, 4811 RTW89_CCX_EDCCA_BW20_4 = 4, 4812 RTW89_CCX_EDCCA_BW20_5 = 5, 4813 RTW89_CCX_EDCCA_BW20_6 = 6, 4814 RTW89_CCX_EDCCA_BW20_7 = 7 4815 }; 4816 4817 #define RTW89_NHM_TH_NUM 11 4818 #define RTW89_FAHM_TH_NUM 11 4819 #define RTW89_NHM_RPT_NUM 12 4820 #define RTW89_FAHM_RPT_NUM 12 4821 #define RTW89_IFS_CLM_NUM 4 4822 struct rtw89_env_monitor_info { 4823 u8 ccx_watchdog_result; 4824 bool ccx_ongoing; 4825 u8 ccx_rac_lv; 4826 bool ccx_manual_ctrl; 4827 u16 ifs_clm_mntr_time; 4828 enum rtw89_ifs_clm_application ifs_clm_app; 4829 u16 ccx_period; 4830 u8 ccx_unit_idx; 4831 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4832 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4833 u16 ifs_clm_tx; 4834 u16 ifs_clm_edcca_excl_cca; 4835 u16 ifs_clm_ofdmfa; 4836 u16 ifs_clm_ofdmcca_excl_fa; 4837 u16 ifs_clm_cckfa; 4838 u16 ifs_clm_cckcca_excl_fa; 4839 u16 ifs_clm_total_ifs; 4840 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4841 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4842 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4843 u8 ifs_clm_tx_ratio; 4844 u8 ifs_clm_edcca_excl_cca_ratio; 4845 u8 ifs_clm_cck_fa_ratio; 4846 u8 ifs_clm_ofdm_fa_ratio; 4847 u8 ifs_clm_cck_cca_excl_fa_ratio; 4848 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4849 u16 ifs_clm_cck_fa_permil; 4850 u16 ifs_clm_ofdm_fa_permil; 4851 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4852 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4853 }; 4854 4855 enum rtw89_ser_rcvy_step { 4856 RTW89_SER_DRV_STOP_TX, 4857 RTW89_SER_DRV_STOP_RX, 4858 RTW89_SER_DRV_STOP_RUN, 4859 RTW89_SER_HAL_STOP_DMA, 4860 RTW89_SER_SUPPRESS_LOG, 4861 RTW89_NUM_OF_SER_FLAGS 4862 }; 4863 4864 struct rtw89_ser { 4865 u8 state; 4866 u8 alarm_event; 4867 bool prehandle_l1; 4868 4869 struct work_struct ser_hdl_work; 4870 struct delayed_work ser_alarm_work; 4871 const struct state_ent *st_tbl; 4872 const struct event_ent *ev_tbl; 4873 struct list_head msg_q; 4874 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4875 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4876 }; 4877 4878 enum rtw89_mac_ax_ps_mode { 4879 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4880 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4881 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4882 RTW89_MAC_AX_PS_MODE_MAX = 3, 4883 }; 4884 4885 enum rtw89_last_rpwm_mode { 4886 RTW89_LAST_RPWM_PS = 0x0, 4887 RTW89_LAST_RPWM_ACTIVE = 0x6, 4888 }; 4889 4890 struct rtw89_lps_parm { 4891 u8 macid; 4892 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4893 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4894 }; 4895 4896 struct rtw89_ppdu_sts_info { 4897 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4898 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4899 }; 4900 4901 struct rtw89_early_h2c { 4902 struct list_head list; 4903 u8 *h2c; 4904 u16 h2c_len; 4905 }; 4906 4907 struct rtw89_hw_scan_info { 4908 struct ieee80211_vif *scanning_vif; 4909 struct list_head pkt_list[NUM_NL80211_BANDS]; 4910 struct rtw89_chan op_chan; 4911 bool abort; 4912 u32 last_chan_idx; 4913 }; 4914 4915 enum rtw89_phy_bb_gain_band { 4916 RTW89_BB_GAIN_BAND_2G = 0, 4917 RTW89_BB_GAIN_BAND_5G_L = 1, 4918 RTW89_BB_GAIN_BAND_5G_M = 2, 4919 RTW89_BB_GAIN_BAND_5G_H = 3, 4920 RTW89_BB_GAIN_BAND_6G_L = 4, 4921 RTW89_BB_GAIN_BAND_6G_M = 5, 4922 RTW89_BB_GAIN_BAND_6G_H = 6, 4923 RTW89_BB_GAIN_BAND_6G_UH = 7, 4924 4925 RTW89_BB_GAIN_BAND_NR, 4926 }; 4927 4928 enum rtw89_phy_gain_band_be { 4929 RTW89_BB_GAIN_BAND_2G_BE = 0, 4930 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 4931 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 4932 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 4933 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 4934 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 4935 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 4936 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 4937 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 4938 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 4939 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 4940 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 4941 4942 RTW89_BB_GAIN_BAND_NR_BE, 4943 }; 4944 4945 enum rtw89_phy_bb_bw_be { 4946 RTW89_BB_BW_20_40 = 0, 4947 RTW89_BB_BW_80_160_320 = 1, 4948 4949 RTW89_BB_BW_NR_BE, 4950 }; 4951 4952 enum rtw89_bw20_sc { 4953 RTW89_BW20_SC_20M = 1, 4954 RTW89_BW20_SC_40M = 2, 4955 RTW89_BW20_SC_80M = 4, 4956 RTW89_BW20_SC_160M = 8, 4957 RTW89_BW20_SC_320M = 16, 4958 }; 4959 4960 enum rtw89_cmac_table_bw { 4961 RTW89_CMAC_BW_20M = 0, 4962 RTW89_CMAC_BW_40M = 1, 4963 RTW89_CMAC_BW_80M = 2, 4964 RTW89_CMAC_BW_160M = 3, 4965 RTW89_CMAC_BW_320M = 4, 4966 4967 RTW89_CMAC_BW_NR, 4968 }; 4969 4970 enum rtw89_phy_bb_rxsc_num { 4971 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4972 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4973 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4974 }; 4975 4976 struct rtw89_phy_bb_gain_info { 4977 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4978 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4979 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4980 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4981 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4982 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4983 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4984 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4985 [RTW89_BB_RXSC_NUM_40]; 4986 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4987 [RTW89_BB_RXSC_NUM_80]; 4988 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4989 [RTW89_BB_RXSC_NUM_160]; 4990 }; 4991 4992 struct rtw89_phy_bb_gain_info_be { 4993 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 4994 [LNA_GAIN_NUM]; 4995 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 4996 [TIA_GAIN_NUM]; 4997 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 4998 [RF_PATH_MAX][LNA_GAIN_NUM]; 4999 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5000 [RF_PATH_MAX][LNA_GAIN_NUM]; 5001 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5002 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5003 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5004 [RTW89_BW20_SC_20M]; 5005 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5006 [RTW89_BW20_SC_40M]; 5007 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5008 [RTW89_BW20_SC_80M]; 5009 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5010 [RTW89_BW20_SC_160M]; 5011 }; 5012 5013 struct rtw89_phy_efuse_gain { 5014 bool offset_valid; 5015 bool comp_valid; 5016 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5017 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5018 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5019 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5020 }; 5021 5022 #define RTW89_MAX_PATTERN_NUM 18 5023 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5024 #define RTW89_MAX_PATTERN_SIZE 128 5025 5026 struct rtw89_wow_cam_info { 5027 bool r_w; 5028 u8 idx; 5029 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5030 u16 crc; 5031 bool negative_pattern_match; 5032 bool skip_mac_hdr; 5033 bool uc; 5034 bool mc; 5035 bool bc; 5036 bool valid; 5037 }; 5038 5039 struct rtw89_wow_param { 5040 struct ieee80211_vif *wow_vif; 5041 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5042 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5043 u8 pattern_cnt; 5044 }; 5045 5046 struct rtw89_mcc_limit { 5047 bool enable; 5048 u16 max_tob; /* TU; max time offset behind */ 5049 u16 max_toa; /* TU; max time offset ahead */ 5050 u16 max_dur; /* TU */ 5051 }; 5052 5053 struct rtw89_mcc_policy { 5054 u8 c2h_rpt; 5055 u8 tx_null_early; 5056 u8 dis_tx_null; 5057 u8 in_curr_ch; 5058 u8 dis_sw_retry; 5059 u8 sw_retry_count; 5060 }; 5061 5062 struct rtw89_mcc_role { 5063 struct rtw89_vif *rtwvif; 5064 struct rtw89_mcc_policy policy; 5065 struct rtw89_mcc_limit limit; 5066 5067 /* only valid when running with FW MRC mechanism */ 5068 u8 slot_idx; 5069 5070 /* byte-array in LE order for FW */ 5071 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5072 5073 u16 duration; /* TU */ 5074 u16 beacon_interval; /* TU */ 5075 bool is_2ghz; 5076 bool is_go; 5077 bool is_gc; 5078 }; 5079 5080 struct rtw89_mcc_bt_role { 5081 u16 duration; /* TU */ 5082 }; 5083 5084 struct rtw89_mcc_courtesy { 5085 bool enable; 5086 u8 slot_num; 5087 u8 macid_src; 5088 u8 macid_tgt; 5089 }; 5090 5091 enum rtw89_mcc_plan { 5092 RTW89_MCC_PLAN_TAIL_BT, 5093 RTW89_MCC_PLAN_MID_BT, 5094 RTW89_MCC_PLAN_NO_BT, 5095 5096 NUM_OF_RTW89_MCC_PLAN, 5097 }; 5098 5099 struct rtw89_mcc_pattern { 5100 s16 tob_ref; /* TU; time offset behind of reference role */ 5101 s16 toa_ref; /* TU; time offset ahead of reference role */ 5102 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5103 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5104 5105 enum rtw89_mcc_plan plan; 5106 struct rtw89_mcc_courtesy courtesy; 5107 }; 5108 5109 struct rtw89_mcc_sync { 5110 bool enable; 5111 u16 offset; /* TU */ 5112 u8 macid_src; 5113 u8 band_src; 5114 u8 port_src; 5115 u8 macid_tgt; 5116 u8 band_tgt; 5117 u8 port_tgt; 5118 }; 5119 5120 struct rtw89_mcc_config { 5121 struct rtw89_mcc_pattern pattern; 5122 struct rtw89_mcc_sync sync; 5123 u64 start_tsf; 5124 u16 mcc_interval; /* TU */ 5125 u16 beacon_offset; /* TU */ 5126 }; 5127 5128 enum rtw89_mcc_mode { 5129 RTW89_MCC_MODE_GO_STA, 5130 RTW89_MCC_MODE_GC_STA, 5131 }; 5132 5133 struct rtw89_mcc_info { 5134 struct rtw89_wait_info wait; 5135 5136 u8 group; 5137 enum rtw89_mcc_mode mode; 5138 struct rtw89_mcc_role role_ref; /* reference role */ 5139 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5140 struct rtw89_mcc_bt_role bt_role; 5141 struct rtw89_mcc_config config; 5142 }; 5143 5144 struct rtw89_dev { 5145 struct ieee80211_hw *hw; 5146 struct device *dev; 5147 const struct ieee80211_ops *ops; 5148 5149 bool dbcc_en; 5150 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5151 struct rtw89_hw_scan_info scan_info; 5152 const struct rtw89_chip_info *chip; 5153 const struct rtw89_pci_info *pci_info; 5154 const struct rtw89_rfe_parms *rfe_parms; 5155 struct rtw89_hal hal; 5156 struct rtw89_mcc_info mcc; 5157 struct rtw89_mac_info mac; 5158 struct rtw89_fw_info fw; 5159 struct rtw89_hci_info hci; 5160 struct rtw89_efuse efuse; 5161 struct rtw89_traffic_stats stats; 5162 struct rtw89_rfe_data *rfe_data; 5163 5164 /* ensures exclusive access from mac80211 callbacks */ 5165 struct mutex mutex; 5166 struct list_head rtwvifs_list; 5167 /* used to protect rf read write */ 5168 struct mutex rf_mutex; 5169 struct workqueue_struct *txq_wq; 5170 struct work_struct txq_work; 5171 struct delayed_work txq_reinvoke_work; 5172 /* used to protect ba_list and forbid_ba_list */ 5173 spinlock_t ba_lock; 5174 /* txqs to setup ba session */ 5175 struct list_head ba_list; 5176 /* txqs to forbid ba session */ 5177 struct list_head forbid_ba_list; 5178 struct work_struct ba_work; 5179 /* used to protect rpwm */ 5180 spinlock_t rpwm_lock; 5181 5182 struct rtw89_cam_info cam_info; 5183 5184 struct sk_buff_head c2h_queue; 5185 struct work_struct c2h_work; 5186 struct work_struct ips_work; 5187 struct work_struct load_firmware_work; 5188 struct work_struct cancel_6ghz_probe_work; 5189 5190 struct list_head early_h2c_list; 5191 5192 struct rtw89_ser ser; 5193 5194 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5195 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5196 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5197 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5198 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5199 5200 struct rtw89_phy_stat phystat; 5201 struct rtw89_rfk_wait_info rfk_wait; 5202 struct rtw89_dack_info dack; 5203 struct rtw89_iqk_info iqk; 5204 struct rtw89_dpk_info dpk; 5205 struct rtw89_rfk_mcc_info rfk_mcc; 5206 struct rtw89_lck_info lck; 5207 struct rtw89_rx_dck_info rx_dck; 5208 bool is_tssi_mode[RF_PATH_MAX]; 5209 bool is_bt_iqk_timeout; 5210 5211 struct rtw89_fem_info fem; 5212 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5213 struct rtw89_tssi_info tssi; 5214 struct rtw89_power_trim_info pwr_trim; 5215 5216 struct rtw89_cfo_tracking_info cfo_tracking; 5217 struct rtw89_env_monitor_info env_monitor; 5218 struct rtw89_dig_info dig; 5219 struct rtw89_phy_ch_info ch_info; 5220 union { 5221 struct rtw89_phy_bb_gain_info ax; 5222 struct rtw89_phy_bb_gain_info_be be; 5223 } bb_gain; 5224 struct rtw89_phy_efuse_gain efuse_gain; 5225 struct rtw89_phy_ul_tb_info ul_tb_info; 5226 struct rtw89_antdiv_info antdiv; 5227 5228 struct delayed_work track_work; 5229 struct delayed_work chanctx_work; 5230 struct delayed_work coex_act1_work; 5231 struct delayed_work coex_bt_devinfo_work; 5232 struct delayed_work coex_rfk_chk_work; 5233 struct delayed_work cfo_track_work; 5234 struct delayed_work forbid_ba_work; 5235 struct delayed_work roc_work; 5236 struct delayed_work antdiv_work; 5237 struct rtw89_ppdu_sts_info ppdu_sts; 5238 u8 total_sta_assoc; 5239 bool scanning; 5240 5241 struct rtw89_regulatory_info regulatory; 5242 struct rtw89_sar_info sar; 5243 struct rtw89_tas_info tas; 5244 5245 struct rtw89_btc btc; 5246 enum rtw89_ps_mode ps_mode; 5247 bool lps_enabled; 5248 5249 struct rtw89_wow_param wow; 5250 5251 /* napi structure */ 5252 struct net_device netdev; 5253 struct napi_struct napi; 5254 int napi_budget_countdown; 5255 5256 /* HCI related data, keep last */ 5257 u8 priv[] __aligned(sizeof(void *)); 5258 }; 5259 5260 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5261 struct rtw89_core_tx_request *tx_req) 5262 { 5263 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5264 } 5265 5266 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5267 { 5268 rtwdev->hci.ops->reset(rtwdev); 5269 } 5270 5271 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5272 { 5273 return rtwdev->hci.ops->start(rtwdev); 5274 } 5275 5276 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5277 { 5278 rtwdev->hci.ops->stop(rtwdev); 5279 } 5280 5281 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5282 { 5283 return rtwdev->hci.ops->deinit(rtwdev); 5284 } 5285 5286 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5287 { 5288 rtwdev->hci.ops->pause(rtwdev, pause); 5289 } 5290 5291 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5292 { 5293 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5294 } 5295 5296 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5297 { 5298 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5299 } 5300 5301 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5302 { 5303 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5304 } 5305 5306 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5307 { 5308 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5309 } 5310 5311 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5312 { 5313 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5314 } 5315 5316 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5317 bool drop) 5318 { 5319 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5320 return; 5321 5322 if (rtwdev->hci.ops->flush_queues) 5323 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5324 } 5325 5326 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5327 { 5328 if (rtwdev->hci.ops->recovery_start) 5329 rtwdev->hci.ops->recovery_start(rtwdev); 5330 } 5331 5332 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5333 { 5334 if (rtwdev->hci.ops->recovery_complete) 5335 rtwdev->hci.ops->recovery_complete(rtwdev); 5336 } 5337 5338 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5339 { 5340 if (rtwdev->hci.ops->enable_intr) 5341 rtwdev->hci.ops->enable_intr(rtwdev); 5342 } 5343 5344 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5345 { 5346 if (rtwdev->hci.ops->disable_intr) 5347 rtwdev->hci.ops->disable_intr(rtwdev); 5348 } 5349 5350 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5351 { 5352 if (rtwdev->hci.ops->ctrl_txdma_ch) 5353 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5354 } 5355 5356 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5357 { 5358 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5359 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5360 } 5361 5362 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5363 { 5364 if (rtwdev->hci.ops->ctrl_trxhci) 5365 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5366 } 5367 5368 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5369 { 5370 int ret = 0; 5371 5372 if (rtwdev->hci.ops->poll_txdma_ch_idle) 5373 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 5374 return ret; 5375 } 5376 5377 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5378 { 5379 if (rtwdev->hci.ops->clr_idx_all) 5380 rtwdev->hci.ops->clr_idx_all(rtwdev); 5381 } 5382 5383 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 5384 { 5385 int ret = 0; 5386 5387 if (rtwdev->hci.ops->rst_bdram) 5388 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 5389 return ret; 5390 } 5391 5392 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 5393 { 5394 if (rtwdev->hci.ops->clear) 5395 rtwdev->hci.ops->clear(rtwdev, pdev); 5396 } 5397 5398 static inline 5399 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 5400 { 5401 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 5402 5403 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 5404 } 5405 5406 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 5407 { 5408 return rtwdev->hci.ops->read8(rtwdev, addr); 5409 } 5410 5411 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 5412 { 5413 return rtwdev->hci.ops->read16(rtwdev, addr); 5414 } 5415 5416 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 5417 { 5418 return rtwdev->hci.ops->read32(rtwdev, addr); 5419 } 5420 5421 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 5422 { 5423 rtwdev->hci.ops->write8(rtwdev, addr, data); 5424 } 5425 5426 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 5427 { 5428 rtwdev->hci.ops->write16(rtwdev, addr, data); 5429 } 5430 5431 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 5432 { 5433 rtwdev->hci.ops->write32(rtwdev, addr, data); 5434 } 5435 5436 static inline void 5437 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5438 { 5439 u8 val; 5440 5441 val = rtw89_read8(rtwdev, addr); 5442 rtw89_write8(rtwdev, addr, val | bit); 5443 } 5444 5445 static inline void 5446 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5447 { 5448 u16 val; 5449 5450 val = rtw89_read16(rtwdev, addr); 5451 rtw89_write16(rtwdev, addr, val | bit); 5452 } 5453 5454 static inline void 5455 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5456 { 5457 u32 val; 5458 5459 val = rtw89_read32(rtwdev, addr); 5460 rtw89_write32(rtwdev, addr, val | bit); 5461 } 5462 5463 static inline void 5464 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 5465 { 5466 u8 val; 5467 5468 val = rtw89_read8(rtwdev, addr); 5469 rtw89_write8(rtwdev, addr, val & ~bit); 5470 } 5471 5472 static inline void 5473 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 5474 { 5475 u16 val; 5476 5477 val = rtw89_read16(rtwdev, addr); 5478 rtw89_write16(rtwdev, addr, val & ~bit); 5479 } 5480 5481 static inline void 5482 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 5483 { 5484 u32 val; 5485 5486 val = rtw89_read32(rtwdev, addr); 5487 rtw89_write32(rtwdev, addr, val & ~bit); 5488 } 5489 5490 static inline u32 5491 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5492 { 5493 u32 shift = __ffs(mask); 5494 u32 orig; 5495 u32 ret; 5496 5497 orig = rtw89_read32(rtwdev, addr); 5498 ret = (orig & mask) >> shift; 5499 5500 return ret; 5501 } 5502 5503 static inline u16 5504 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5505 { 5506 u32 shift = __ffs(mask); 5507 u32 orig; 5508 u32 ret; 5509 5510 orig = rtw89_read16(rtwdev, addr); 5511 ret = (orig & mask) >> shift; 5512 5513 return ret; 5514 } 5515 5516 static inline u8 5517 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 5518 { 5519 u32 shift = __ffs(mask); 5520 u32 orig; 5521 u32 ret; 5522 5523 orig = rtw89_read8(rtwdev, addr); 5524 ret = (orig & mask) >> shift; 5525 5526 return ret; 5527 } 5528 5529 static inline void 5530 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5531 { 5532 u32 shift = __ffs(mask); 5533 u32 orig; 5534 u32 set; 5535 5536 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5537 5538 orig = rtw89_read32(rtwdev, addr); 5539 set = (orig & ~mask) | ((data << shift) & mask); 5540 rtw89_write32(rtwdev, addr, set); 5541 } 5542 5543 static inline void 5544 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5545 { 5546 u32 shift; 5547 u16 orig, set; 5548 5549 mask &= 0xffff; 5550 shift = __ffs(mask); 5551 5552 orig = rtw89_read16(rtwdev, addr); 5553 set = (orig & ~mask) | ((data << shift) & mask); 5554 rtw89_write16(rtwdev, addr, set); 5555 } 5556 5557 static inline void 5558 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5559 { 5560 u32 shift; 5561 u8 orig, set; 5562 5563 mask &= 0xff; 5564 shift = __ffs(mask); 5565 5566 orig = rtw89_read8(rtwdev, addr); 5567 set = (orig & ~mask) | ((data << shift) & mask); 5568 rtw89_write8(rtwdev, addr, set); 5569 } 5570 5571 static inline u32 5572 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5573 u32 addr, u32 mask) 5574 { 5575 u32 val; 5576 5577 mutex_lock(&rtwdev->rf_mutex); 5578 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5579 mutex_unlock(&rtwdev->rf_mutex); 5580 5581 return val; 5582 } 5583 5584 static inline void 5585 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5586 u32 addr, u32 mask, u32 data) 5587 { 5588 mutex_lock(&rtwdev->rf_mutex); 5589 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5590 mutex_unlock(&rtwdev->rf_mutex); 5591 } 5592 5593 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5594 { 5595 void *p = rtwtxq; 5596 5597 return container_of(p, struct ieee80211_txq, drv_priv); 5598 } 5599 5600 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5601 struct ieee80211_txq *txq) 5602 { 5603 struct rtw89_txq *rtwtxq; 5604 5605 if (!txq) 5606 return; 5607 5608 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5609 INIT_LIST_HEAD(&rtwtxq->list); 5610 } 5611 5612 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5613 { 5614 void *p = rtwvif; 5615 5616 return container_of(p, struct ieee80211_vif, drv_priv); 5617 } 5618 5619 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5620 { 5621 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5622 } 5623 5624 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5625 { 5626 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5627 } 5628 5629 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5630 { 5631 void *p = rtwsta; 5632 5633 return container_of(p, struct ieee80211_sta, drv_priv); 5634 } 5635 5636 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5637 { 5638 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5639 } 5640 5641 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5642 { 5643 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5644 } 5645 5646 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5647 { 5648 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5649 return RATE_INFO_BW_160; 5650 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5651 return RATE_INFO_BW_80; 5652 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5653 return RATE_INFO_BW_40; 5654 else 5655 return RATE_INFO_BW_20; 5656 } 5657 5658 static inline 5659 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5660 { 5661 switch (hw_band) { 5662 default: 5663 case RTW89_BAND_2G: 5664 return NL80211_BAND_2GHZ; 5665 case RTW89_BAND_5G: 5666 return NL80211_BAND_5GHZ; 5667 case RTW89_BAND_6G: 5668 return NL80211_BAND_6GHZ; 5669 } 5670 } 5671 5672 static inline 5673 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5674 { 5675 switch (nl_band) { 5676 default: 5677 case NL80211_BAND_2GHZ: 5678 return RTW89_BAND_2G; 5679 case NL80211_BAND_5GHZ: 5680 return RTW89_BAND_5G; 5681 case NL80211_BAND_6GHZ: 5682 return RTW89_BAND_6G; 5683 } 5684 } 5685 5686 static inline 5687 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5688 { 5689 switch (width) { 5690 default: 5691 WARN(1, "Not support bandwidth %d\n", width); 5692 fallthrough; 5693 case NL80211_CHAN_WIDTH_20_NOHT: 5694 case NL80211_CHAN_WIDTH_20: 5695 return RTW89_CHANNEL_WIDTH_20; 5696 case NL80211_CHAN_WIDTH_40: 5697 return RTW89_CHANNEL_WIDTH_40; 5698 case NL80211_CHAN_WIDTH_80: 5699 return RTW89_CHANNEL_WIDTH_80; 5700 case NL80211_CHAN_WIDTH_160: 5701 return RTW89_CHANNEL_WIDTH_160; 5702 } 5703 } 5704 5705 static inline 5706 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5707 { 5708 switch (rua) { 5709 default: 5710 WARN(1, "Invalid RU allocation: %d\n", rua); 5711 fallthrough; 5712 case 0 ... 36: 5713 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5714 case 37 ... 52: 5715 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5716 case 53 ... 60: 5717 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5718 case 61 ... 64: 5719 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5720 case 65 ... 66: 5721 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5722 case 67: 5723 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5724 case 68: 5725 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5726 } 5727 } 5728 5729 static inline 5730 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5731 struct rtw89_sta *rtwsta) 5732 { 5733 if (rtwsta) { 5734 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5735 5736 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5737 return &rtwsta->addr_cam; 5738 } 5739 return &rtwvif->addr_cam; 5740 } 5741 5742 static inline 5743 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5744 struct rtw89_sta *rtwsta) 5745 { 5746 if (rtwsta) { 5747 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5748 5749 if (sta->tdls) 5750 return &rtwsta->bssid_cam; 5751 } 5752 return &rtwvif->bssid_cam; 5753 } 5754 5755 static inline 5756 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5757 struct rtw89_channel_help_params *p, 5758 const struct rtw89_chan *chan, 5759 enum rtw89_mac_idx mac_idx, 5760 enum rtw89_phy_idx phy_idx) 5761 { 5762 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5763 mac_idx, phy_idx); 5764 } 5765 5766 static inline 5767 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 5768 struct rtw89_channel_help_params *p, 5769 const struct rtw89_chan *chan, 5770 enum rtw89_mac_idx mac_idx, 5771 enum rtw89_phy_idx phy_idx) 5772 { 5773 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 5774 mac_idx, phy_idx); 5775 } 5776 5777 static inline 5778 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 5779 enum rtw89_sub_entity_idx idx) 5780 { 5781 struct rtw89_hal *hal = &rtwdev->hal; 5782 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 5783 5784 if (roc_idx == idx) 5785 return &hal->roc_chandef; 5786 5787 return &hal->sub[idx].chandef; 5788 } 5789 5790 static inline 5791 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 5792 enum rtw89_sub_entity_idx idx) 5793 { 5794 struct rtw89_hal *hal = &rtwdev->hal; 5795 5796 return &hal->sub[idx].chan; 5797 } 5798 5799 static inline 5800 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 5801 enum rtw89_sub_entity_idx idx) 5802 { 5803 struct rtw89_hal *hal = &rtwdev->hal; 5804 5805 return &hal->sub[idx].rcd; 5806 } 5807 5808 static inline 5809 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 5810 { 5811 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 5812 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 5813 5814 if (rtwvif) 5815 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 5816 else 5817 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5818 } 5819 5820 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 5821 { 5822 const struct rtw89_chip_info *chip = rtwdev->chip; 5823 5824 if (chip->ops->fem_setup) 5825 chip->ops->fem_setup(rtwdev); 5826 } 5827 5828 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 5829 { 5830 const struct rtw89_chip_info *chip = rtwdev->chip; 5831 5832 if (chip->ops->rfe_gpio) 5833 chip->ops->rfe_gpio(rtwdev); 5834 } 5835 5836 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 5837 { 5838 const struct rtw89_chip_info *chip = rtwdev->chip; 5839 5840 if (chip->ops->rfk_hw_init) 5841 chip->ops->rfk_hw_init(rtwdev); 5842 } 5843 5844 static inline 5845 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5846 { 5847 const struct rtw89_chip_info *chip = rtwdev->chip; 5848 5849 if (chip->ops->bb_preinit) 5850 chip->ops->bb_preinit(rtwdev, phy_idx); 5851 } 5852 5853 static inline 5854 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 5855 { 5856 const struct rtw89_chip_info *chip = rtwdev->chip; 5857 5858 if (!chip->ops->bb_postinit) 5859 return; 5860 5861 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 5862 5863 if (rtwdev->dbcc_en) 5864 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 5865 } 5866 5867 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 5868 { 5869 const struct rtw89_chip_info *chip = rtwdev->chip; 5870 5871 if (chip->ops->bb_sethw) 5872 chip->ops->bb_sethw(rtwdev); 5873 } 5874 5875 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 5876 { 5877 const struct rtw89_chip_info *chip = rtwdev->chip; 5878 5879 if (chip->ops->rfk_init) 5880 chip->ops->rfk_init(rtwdev); 5881 } 5882 5883 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 5884 { 5885 const struct rtw89_chip_info *chip = rtwdev->chip; 5886 5887 if (chip->ops->rfk_init_late) 5888 chip->ops->rfk_init_late(rtwdev); 5889 } 5890 5891 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 5892 { 5893 const struct rtw89_chip_info *chip = rtwdev->chip; 5894 5895 if (chip->ops->rfk_channel) 5896 chip->ops->rfk_channel(rtwdev); 5897 } 5898 5899 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 5900 enum rtw89_phy_idx phy_idx) 5901 { 5902 const struct rtw89_chip_info *chip = rtwdev->chip; 5903 5904 if (chip->ops->rfk_band_changed) 5905 chip->ops->rfk_band_changed(rtwdev, phy_idx); 5906 } 5907 5908 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 5909 { 5910 const struct rtw89_chip_info *chip = rtwdev->chip; 5911 5912 if (chip->ops->rfk_scan) 5913 chip->ops->rfk_scan(rtwdev, start); 5914 } 5915 5916 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 5917 { 5918 const struct rtw89_chip_info *chip = rtwdev->chip; 5919 5920 if (chip->ops->rfk_track) 5921 chip->ops->rfk_track(rtwdev); 5922 } 5923 5924 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 5925 { 5926 const struct rtw89_chip_info *chip = rtwdev->chip; 5927 5928 if (chip->ops->set_txpwr_ctrl) 5929 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 5930 } 5931 5932 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 5933 { 5934 const struct rtw89_chip_info *chip = rtwdev->chip; 5935 5936 if (chip->ops->power_trim) 5937 chip->ops->power_trim(rtwdev); 5938 } 5939 5940 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 5941 enum rtw89_phy_idx phy_idx) 5942 { 5943 const struct rtw89_chip_info *chip = rtwdev->chip; 5944 5945 if (chip->ops->init_txpwr_unit) 5946 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 5947 } 5948 5949 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 5950 enum rtw89_rf_path rf_path) 5951 { 5952 const struct rtw89_chip_info *chip = rtwdev->chip; 5953 5954 if (!chip->ops->get_thermal) 5955 return 0x10; 5956 5957 return chip->ops->get_thermal(rtwdev, rf_path); 5958 } 5959 5960 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 5961 struct rtw89_rx_phy_ppdu *phy_ppdu, 5962 struct ieee80211_rx_status *status) 5963 { 5964 const struct rtw89_chip_info *chip = rtwdev->chip; 5965 5966 if (chip->ops->query_ppdu) 5967 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 5968 } 5969 5970 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 5971 enum rtw89_phy_idx phy_idx) 5972 { 5973 const struct rtw89_chip_info *chip = rtwdev->chip; 5974 5975 if (chip->ops->ctrl_nbtg_bt_tx) 5976 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 5977 } 5978 5979 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 5980 { 5981 const struct rtw89_chip_info *chip = rtwdev->chip; 5982 5983 if (chip->ops->cfg_txrx_path) 5984 chip->ops->cfg_txrx_path(rtwdev); 5985 } 5986 5987 static inline 5988 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5989 struct ieee80211_vif *vif) 5990 { 5991 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5992 const struct rtw89_chip_info *chip = rtwdev->chip; 5993 5994 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5995 return; 5996 5997 if (chip->ops->set_txpwr_ul_tb_offset) 5998 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5999 } 6000 6001 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6002 const struct rtw89_txpwr_table *tbl) 6003 { 6004 tbl->load(rtwdev, tbl); 6005 } 6006 6007 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6008 { 6009 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6010 6011 return regd->txpwr_regd[band]; 6012 } 6013 6014 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6015 enum rtw89_phy_idx phy_idx) 6016 { 6017 const struct rtw89_chip_info *chip = rtwdev->chip; 6018 6019 if (chip->ops->ctrl_btg_bt_rx) 6020 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6021 } 6022 6023 static inline 6024 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6025 struct rtw89_rx_desc_info *desc_info, 6026 u8 *data, u32 data_offset) 6027 { 6028 const struct rtw89_chip_info *chip = rtwdev->chip; 6029 6030 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6031 } 6032 6033 static inline 6034 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6035 struct rtw89_tx_desc_info *desc_info, 6036 void *txdesc) 6037 { 6038 const struct rtw89_chip_info *chip = rtwdev->chip; 6039 6040 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6041 } 6042 6043 static inline 6044 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6045 struct rtw89_tx_desc_info *desc_info, 6046 void *txdesc) 6047 { 6048 const struct rtw89_chip_info *chip = rtwdev->chip; 6049 6050 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6051 } 6052 6053 static inline 6054 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6055 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6056 { 6057 const struct rtw89_chip_info *chip = rtwdev->chip; 6058 6059 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6060 } 6061 6062 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6063 { 6064 const struct rtw89_chip_info *chip = rtwdev->chip; 6065 6066 chip->ops->cfg_ctrl_path(rtwdev, wl); 6067 } 6068 6069 static inline 6070 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6071 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6072 { 6073 const struct rtw89_chip_info *chip = rtwdev->chip; 6074 6075 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6076 } 6077 6078 static inline 6079 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6080 { 6081 const struct rtw89_chip_info *chip = rtwdev->chip; 6082 6083 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6084 } 6085 6086 static inline 6087 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6088 struct rtw89_vif *rtwvif, 6089 struct rtw89_sta *rtwsta) 6090 { 6091 const struct rtw89_chip_info *chip = rtwdev->chip; 6092 6093 if (!chip->ops->h2c_dctl_sec_cam) 6094 return 0; 6095 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 6096 } 6097 6098 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6099 { 6100 __le16 fc = hdr->frame_control; 6101 6102 if (ieee80211_has_tods(fc)) 6103 return hdr->addr1; 6104 else if (ieee80211_has_fromds(fc)) 6105 return hdr->addr2; 6106 else 6107 return hdr->addr3; 6108 } 6109 6110 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 6111 { 6112 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6113 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6114 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 6115 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6116 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 6117 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6118 return true; 6119 return false; 6120 } 6121 6122 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6123 enum rtw89_fw_type type) 6124 { 6125 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6126 6127 switch (type) { 6128 case RTW89_FW_WOWLAN: 6129 return &fw_info->wowlan; 6130 case RTW89_FW_LOGFMT: 6131 return &fw_info->log.suit; 6132 case RTW89_FW_BBMCU0: 6133 return &fw_info->bbmcu0; 6134 case RTW89_FW_BBMCU1: 6135 return &fw_info->bbmcu1; 6136 default: 6137 break; 6138 } 6139 6140 return &fw_info->normal; 6141 } 6142 6143 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6144 unsigned int length) 6145 { 6146 struct sk_buff *skb; 6147 6148 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6149 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6150 if (!skb) 6151 return NULL; 6152 6153 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6154 return skb; 6155 } 6156 6157 return dev_alloc_skb(length); 6158 } 6159 6160 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6161 struct rtw89_tx_skb_data *skb_data, 6162 bool tx_done) 6163 { 6164 struct rtw89_tx_wait_info *wait; 6165 6166 rcu_read_lock(); 6167 6168 wait = rcu_dereference(skb_data->wait); 6169 if (!wait) 6170 goto out; 6171 6172 wait->tx_done = tx_done; 6173 complete(&wait->completion); 6174 6175 out: 6176 rcu_read_unlock(); 6177 } 6178 6179 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6180 { 6181 switch (rtwdev->mlo_dbcc_mode) { 6182 case MLO_1_PLUS_1_1RF: 6183 case MLO_1_PLUS_1_2RF: 6184 case DBCC_LEGACY: 6185 return true; 6186 default: 6187 return false; 6188 } 6189 } 6190 6191 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6192 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6193 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6194 struct sk_buff *skb, bool fwdl); 6195 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6196 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6197 int qsel, unsigned int timeout); 6198 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6199 struct rtw89_tx_desc_info *desc_info, 6200 void *txdesc); 6201 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6202 struct rtw89_tx_desc_info *desc_info, 6203 void *txdesc); 6204 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6205 struct rtw89_tx_desc_info *desc_info, 6206 void *txdesc); 6207 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6208 struct rtw89_tx_desc_info *desc_info, 6209 void *txdesc); 6210 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6211 struct rtw89_tx_desc_info *desc_info, 6212 void *txdesc); 6213 void rtw89_core_rx(struct rtw89_dev *rtwdev, 6214 struct rtw89_rx_desc_info *desc_info, 6215 struct sk_buff *skb); 6216 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 6217 struct rtw89_rx_desc_info *desc_info, 6218 u8 *data, u32 data_offset); 6219 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 6220 struct rtw89_rx_desc_info *desc_info, 6221 u8 *data, u32 data_offset); 6222 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 6223 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 6224 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 6225 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 6226 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 6227 struct ieee80211_vif *vif, 6228 struct ieee80211_sta *sta); 6229 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 6230 struct ieee80211_vif *vif, 6231 struct ieee80211_sta *sta); 6232 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 6233 struct ieee80211_vif *vif, 6234 struct ieee80211_sta *sta); 6235 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 6236 struct ieee80211_vif *vif, 6237 struct ieee80211_sta *sta); 6238 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 6239 struct ieee80211_vif *vif, 6240 struct ieee80211_sta *sta); 6241 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 6242 struct ieee80211_sta *sta, 6243 struct cfg80211_tid_config *tid_config); 6244 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 6245 int rtw89_core_init(struct rtw89_dev *rtwdev); 6246 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 6247 int rtw89_core_register(struct rtw89_dev *rtwdev); 6248 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 6249 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 6250 u32 bus_data_size, 6251 const struct rtw89_chip_info *chip); 6252 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 6253 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 6254 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 6255 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 6256 struct rtw89_chan *chan); 6257 int rtw89_set_channel(struct rtw89_dev *rtwdev); 6258 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6259 struct rtw89_chan *chan); 6260 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 6261 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 6262 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 6263 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 6264 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6265 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 6266 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 6267 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 6268 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 6269 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 6270 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 6271 int rtw89_regd_init(struct rtw89_dev *rtwdev, 6272 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 6273 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 6274 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 6275 struct rtw89_traffic_stats *stats); 6276 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 6277 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 6278 const struct rtw89_completion_data *data); 6279 int rtw89_core_start(struct rtw89_dev *rtwdev); 6280 void rtw89_core_stop(struct rtw89_dev *rtwdev); 6281 void rtw89_core_update_beacon_work(struct work_struct *work); 6282 void rtw89_roc_work(struct work_struct *work); 6283 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6284 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 6285 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 6286 const u8 *mac_addr, bool hw_scan); 6287 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 6288 struct ieee80211_vif *vif, bool hw_scan); 6289 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 6290 struct rtw89_vif *rtwvif, bool active); 6291 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 6292 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 6293 6294 #endif 6295