xref: /linux/drivers/net/wireless/realtek/rtw89/core.h (revision 2b0cfa6e49566c8fa6759734cf821aa6e8271a9e)
1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020  Realtek Corporation
3  */
4 
5 #ifndef __RTW89_CORE_H__
6 #define __RTW89_CORE_H__
7 
8 #include <linux/average.h>
9 #include <linux/bitfield.h>
10 #include <linux/firmware.h>
11 #include <linux/iopoll.h>
12 #include <linux/workqueue.h>
13 #include <net/mac80211.h>
14 
15 struct rtw89_dev;
16 struct rtw89_pci_info;
17 struct rtw89_mac_gen_def;
18 struct rtw89_phy_gen_def;
19 struct rtw89_efuse_block_cfg;
20 struct rtw89_fw_txpwr_track_cfg;
21 struct rtw89_phy_rfk_log_fmt;
22 
23 extern const struct ieee80211_ops rtw89_ops;
24 
25 #define MASKBYTE0 0xff
26 #define MASKBYTE1 0xff00
27 #define MASKBYTE2 0xff0000
28 #define MASKBYTE3 0xff000000
29 #define MASKBYTE4 0xff00000000ULL
30 #define MASKHWORD 0xffff0000
31 #define MASKLWORD 0x0000ffff
32 #define MASKDWORD 0xffffffff
33 #define RFREG_MASK 0xfffff
34 #define INV_RF_DATA 0xffffffff
35 #define BYPASS_CR_DATA 0xbabecafe
36 
37 #define RTW89_TRACK_WORK_PERIOD	round_jiffies_relative(HZ * 2)
38 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4)
39 #define CFO_TRACK_MAX_USER 64
40 #define MAX_RSSI 110
41 #define RSSI_FACTOR 1
42 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
43 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR)
44 #define DELTA_SWINGIDX_SIZE 30
45 
46 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he)
47 #define RTW89_RADIOTAP_ROOM_EHT \
48 	(sizeof(struct ieee80211_radiotap_tlv) + \
49 	 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \
50 	 sizeof(struct ieee80211_radiotap_tlv) + \
51 	 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4))
52 #define RTW89_RADIOTAP_ROOM \
53 	ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64)
54 
55 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0)
56 #define RTW89_HTC_VARIANT_HE 3
57 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2)
58 #define RTW89_HTC_VARIANT_HE_CID_OM 1
59 #define RTW89_HTC_VARIANT_HE_CID_CAS 6
60 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6)
61 
62 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6)
63 enum htc_om_channel_width {
64 	HTC_OM_CHANNEL_WIDTH_20 = 0,
65 	HTC_OM_CHANNEL_WIDTH_40 = 1,
66 	HTC_OM_CHANNEL_WIDTH_80 = 2,
67 	HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3,
68 };
69 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9)
70 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11)
71 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12)
72 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15)
73 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16)
74 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17)
75 
76 #define RTW89_TF_PAD GENMASK(11, 0)
77 #define RTW89_TF_BASIC_USER_INFO_SZ 6
78 
79 #define RTW89_GET_TF_USER_INFO_AID12(data)	\
80 	le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0))
81 #define RTW89_GET_TF_USER_INFO_RUA(data)	\
82 	le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12))
83 #define RTW89_GET_TF_USER_INFO_UL_MCS(data)	\
84 	le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21))
85 
86 enum rtw89_subband {
87 	RTW89_CH_2G = 0,
88 	RTW89_CH_5G_BAND_1 = 1,
89 	/* RTW89_CH_5G_BAND_2 = 2, unused */
90 	RTW89_CH_5G_BAND_3 = 3,
91 	RTW89_CH_5G_BAND_4 = 4,
92 
93 	RTW89_CH_6G_BAND_IDX0, /* Low */
94 	RTW89_CH_6G_BAND_IDX1, /* Low */
95 	RTW89_CH_6G_BAND_IDX2, /* Mid */
96 	RTW89_CH_6G_BAND_IDX3, /* Mid */
97 	RTW89_CH_6G_BAND_IDX4, /* High */
98 	RTW89_CH_6G_BAND_IDX5, /* High */
99 	RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
100 	RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
101 
102 	RTW89_SUBBAND_NR,
103 	RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1,
104 };
105 
106 enum rtw89_gain_offset {
107 	RTW89_GAIN_OFFSET_2G_CCK,
108 	RTW89_GAIN_OFFSET_2G_OFDM,
109 	RTW89_GAIN_OFFSET_5G_LOW,
110 	RTW89_GAIN_OFFSET_5G_MID,
111 	RTW89_GAIN_OFFSET_5G_HIGH,
112 	RTW89_GAIN_OFFSET_6G_L0,
113 	RTW89_GAIN_OFFSET_6G_L1,
114 	RTW89_GAIN_OFFSET_6G_M0,
115 	RTW89_GAIN_OFFSET_6G_M1,
116 	RTW89_GAIN_OFFSET_6G_H0,
117 	RTW89_GAIN_OFFSET_6G_H1,
118 	RTW89_GAIN_OFFSET_6G_UH0,
119 	RTW89_GAIN_OFFSET_6G_UH1,
120 
121 	RTW89_GAIN_OFFSET_NR,
122 };
123 
124 enum rtw89_hci_type {
125 	RTW89_HCI_TYPE_PCIE,
126 	RTW89_HCI_TYPE_USB,
127 	RTW89_HCI_TYPE_SDIO,
128 };
129 
130 enum rtw89_core_chip_id {
131 	RTL8852A,
132 	RTL8852B,
133 	RTL8852C,
134 	RTL8851B,
135 	RTL8922A,
136 };
137 
138 enum rtw89_chip_gen {
139 	RTW89_CHIP_AX,
140 	RTW89_CHIP_BE,
141 
142 	RTW89_CHIP_GEN_NUM,
143 };
144 
145 enum rtw89_cv {
146 	CHIP_CAV,
147 	CHIP_CBV,
148 	CHIP_CCV,
149 	CHIP_CDV,
150 	CHIP_CEV,
151 	CHIP_CFV,
152 	CHIP_CV_MAX,
153 	CHIP_CV_INVALID = CHIP_CV_MAX,
154 };
155 
156 enum rtw89_bacam_ver {
157 	RTW89_BACAM_V0,
158 	RTW89_BACAM_V1,
159 
160 	RTW89_BACAM_V0_EXT = 99,
161 };
162 
163 enum rtw89_core_tx_type {
164 	RTW89_CORE_TX_TYPE_DATA,
165 	RTW89_CORE_TX_TYPE_MGMT,
166 	RTW89_CORE_TX_TYPE_FWCMD,
167 };
168 
169 enum rtw89_core_rx_type {
170 	RTW89_CORE_RX_TYPE_WIFI		= 0,
171 	RTW89_CORE_RX_TYPE_PPDU_STAT	= 1,
172 	RTW89_CORE_RX_TYPE_CHAN_INFO	= 2,
173 	RTW89_CORE_RX_TYPE_BB_SCOPE	= 3,
174 	RTW89_CORE_RX_TYPE_F2P_TXCMD	= 4,
175 	RTW89_CORE_RX_TYPE_SS2FW	= 5,
176 	RTW89_CORE_RX_TYPE_TX_REPORT	= 6,
177 	RTW89_CORE_RX_TYPE_TX_REL_HOST	= 7,
178 	RTW89_CORE_RX_TYPE_DFS_REPORT	= 8,
179 	RTW89_CORE_RX_TYPE_TX_REL_CPU	= 9,
180 	RTW89_CORE_RX_TYPE_C2H		= 10,
181 	RTW89_CORE_RX_TYPE_CSI		= 11,
182 	RTW89_CORE_RX_TYPE_CQI		= 12,
183 	RTW89_CORE_RX_TYPE_H2C		= 13,
184 	RTW89_CORE_RX_TYPE_FWDL		= 14,
185 };
186 
187 enum rtw89_txq_flags {
188 	RTW89_TXQ_F_AMPDU		= 0,
189 	RTW89_TXQ_F_BLOCK_BA		= 1,
190 	RTW89_TXQ_F_FORBID_BA		= 2,
191 };
192 
193 enum rtw89_net_type {
194 	RTW89_NET_TYPE_NO_LINK		= 0,
195 	RTW89_NET_TYPE_AD_HOC		= 1,
196 	RTW89_NET_TYPE_INFRA		= 2,
197 	RTW89_NET_TYPE_AP_MODE		= 3,
198 };
199 
200 enum rtw89_wifi_role {
201 	RTW89_WIFI_ROLE_NONE,
202 	RTW89_WIFI_ROLE_STATION,
203 	RTW89_WIFI_ROLE_AP,
204 	RTW89_WIFI_ROLE_AP_VLAN,
205 	RTW89_WIFI_ROLE_ADHOC,
206 	RTW89_WIFI_ROLE_ADHOC_MASTER,
207 	RTW89_WIFI_ROLE_MESH_POINT,
208 	RTW89_WIFI_ROLE_MONITOR,
209 	RTW89_WIFI_ROLE_P2P_DEVICE,
210 	RTW89_WIFI_ROLE_P2P_CLIENT,
211 	RTW89_WIFI_ROLE_P2P_GO,
212 	RTW89_WIFI_ROLE_NAN,
213 	RTW89_WIFI_ROLE_MLME_MAX
214 };
215 
216 enum rtw89_upd_mode {
217 	RTW89_ROLE_CREATE,
218 	RTW89_ROLE_REMOVE,
219 	RTW89_ROLE_TYPE_CHANGE,
220 	RTW89_ROLE_INFO_CHANGE,
221 	RTW89_ROLE_CON_DISCONN,
222 	RTW89_ROLE_BAND_SW,
223 	RTW89_ROLE_FW_RESTORE,
224 };
225 
226 enum rtw89_self_role {
227 	RTW89_SELF_ROLE_CLIENT,
228 	RTW89_SELF_ROLE_AP,
229 	RTW89_SELF_ROLE_AP_CLIENT
230 };
231 
232 enum rtw89_msk_sO_el {
233 	RTW89_NO_MSK,
234 	RTW89_SMA,
235 	RTW89_TMA,
236 	RTW89_BSSID
237 };
238 
239 enum rtw89_sch_tx_sel {
240 	RTW89_SCH_TX_SEL_ALL,
241 	RTW89_SCH_TX_SEL_HIQ,
242 	RTW89_SCH_TX_SEL_MG0,
243 	RTW89_SCH_TX_SEL_MACID,
244 };
245 
246 /* RTW89_ADDR_CAM_SEC_NONE	: not enabled
247  * RTW89_ADDR_CAM_SEC_ALL_UNI	: 0 - 6 unicast
248  * RTW89_ADDR_CAM_SEC_NORMAL	: 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
249  * RTW89_ADDR_CAM_SEC_4GROUP	: 0 - 1 unicast, 2 - 5 group, 6 BIP
250  */
251 enum rtw89_add_cam_sec_mode {
252 	RTW89_ADDR_CAM_SEC_NONE		= 0,
253 	RTW89_ADDR_CAM_SEC_ALL_UNI	= 1,
254 	RTW89_ADDR_CAM_SEC_NORMAL	= 2,
255 	RTW89_ADDR_CAM_SEC_4GROUP	= 3,
256 };
257 
258 enum rtw89_sec_key_type {
259 	RTW89_SEC_KEY_TYPE_NONE		= 0,
260 	RTW89_SEC_KEY_TYPE_WEP40	= 1,
261 	RTW89_SEC_KEY_TYPE_WEP104	= 2,
262 	RTW89_SEC_KEY_TYPE_TKIP		= 3,
263 	RTW89_SEC_KEY_TYPE_WAPI		= 4,
264 	RTW89_SEC_KEY_TYPE_GCMSMS4	= 5,
265 	RTW89_SEC_KEY_TYPE_CCMP128	= 6,
266 	RTW89_SEC_KEY_TYPE_CCMP256	= 7,
267 	RTW89_SEC_KEY_TYPE_GCMP128	= 8,
268 	RTW89_SEC_KEY_TYPE_GCMP256	= 9,
269 	RTW89_SEC_KEY_TYPE_BIP_CCMP128	= 10,
270 };
271 
272 enum rtw89_port {
273 	RTW89_PORT_0 = 0,
274 	RTW89_PORT_1 = 1,
275 	RTW89_PORT_2 = 2,
276 	RTW89_PORT_3 = 3,
277 	RTW89_PORT_4 = 4,
278 	RTW89_PORT_NUM
279 };
280 
281 enum rtw89_band {
282 	RTW89_BAND_2G = 0,
283 	RTW89_BAND_5G = 1,
284 	RTW89_BAND_6G = 2,
285 	RTW89_BAND_NUM,
286 };
287 
288 enum rtw89_hw_rate {
289 	RTW89_HW_RATE_CCK1	= 0x0,
290 	RTW89_HW_RATE_CCK2	= 0x1,
291 	RTW89_HW_RATE_CCK5_5	= 0x2,
292 	RTW89_HW_RATE_CCK11	= 0x3,
293 	RTW89_HW_RATE_OFDM6	= 0x4,
294 	RTW89_HW_RATE_OFDM9	= 0x5,
295 	RTW89_HW_RATE_OFDM12	= 0x6,
296 	RTW89_HW_RATE_OFDM18	= 0x7,
297 	RTW89_HW_RATE_OFDM24	= 0x8,
298 	RTW89_HW_RATE_OFDM36	= 0x9,
299 	RTW89_HW_RATE_OFDM48	= 0xA,
300 	RTW89_HW_RATE_OFDM54	= 0xB,
301 	RTW89_HW_RATE_MCS0	= 0x80,
302 	RTW89_HW_RATE_MCS1	= 0x81,
303 	RTW89_HW_RATE_MCS2	= 0x82,
304 	RTW89_HW_RATE_MCS3	= 0x83,
305 	RTW89_HW_RATE_MCS4	= 0x84,
306 	RTW89_HW_RATE_MCS5	= 0x85,
307 	RTW89_HW_RATE_MCS6	= 0x86,
308 	RTW89_HW_RATE_MCS7	= 0x87,
309 	RTW89_HW_RATE_MCS8	= 0x88,
310 	RTW89_HW_RATE_MCS9	= 0x89,
311 	RTW89_HW_RATE_MCS10	= 0x8A,
312 	RTW89_HW_RATE_MCS11	= 0x8B,
313 	RTW89_HW_RATE_MCS12	= 0x8C,
314 	RTW89_HW_RATE_MCS13	= 0x8D,
315 	RTW89_HW_RATE_MCS14	= 0x8E,
316 	RTW89_HW_RATE_MCS15	= 0x8F,
317 	RTW89_HW_RATE_MCS16	= 0x90,
318 	RTW89_HW_RATE_MCS17	= 0x91,
319 	RTW89_HW_RATE_MCS18	= 0x92,
320 	RTW89_HW_RATE_MCS19	= 0x93,
321 	RTW89_HW_RATE_MCS20	= 0x94,
322 	RTW89_HW_RATE_MCS21	= 0x95,
323 	RTW89_HW_RATE_MCS22	= 0x96,
324 	RTW89_HW_RATE_MCS23	= 0x97,
325 	RTW89_HW_RATE_MCS24	= 0x98,
326 	RTW89_HW_RATE_MCS25	= 0x99,
327 	RTW89_HW_RATE_MCS26	= 0x9A,
328 	RTW89_HW_RATE_MCS27	= 0x9B,
329 	RTW89_HW_RATE_MCS28	= 0x9C,
330 	RTW89_HW_RATE_MCS29	= 0x9D,
331 	RTW89_HW_RATE_MCS30	= 0x9E,
332 	RTW89_HW_RATE_MCS31	= 0x9F,
333 	RTW89_HW_RATE_VHT_NSS1_MCS0	= 0x100,
334 	RTW89_HW_RATE_VHT_NSS1_MCS1	= 0x101,
335 	RTW89_HW_RATE_VHT_NSS1_MCS2	= 0x102,
336 	RTW89_HW_RATE_VHT_NSS1_MCS3	= 0x103,
337 	RTW89_HW_RATE_VHT_NSS1_MCS4	= 0x104,
338 	RTW89_HW_RATE_VHT_NSS1_MCS5	= 0x105,
339 	RTW89_HW_RATE_VHT_NSS1_MCS6	= 0x106,
340 	RTW89_HW_RATE_VHT_NSS1_MCS7	= 0x107,
341 	RTW89_HW_RATE_VHT_NSS1_MCS8	= 0x108,
342 	RTW89_HW_RATE_VHT_NSS1_MCS9	= 0x109,
343 	RTW89_HW_RATE_VHT_NSS2_MCS0	= 0x110,
344 	RTW89_HW_RATE_VHT_NSS2_MCS1	= 0x111,
345 	RTW89_HW_RATE_VHT_NSS2_MCS2	= 0x112,
346 	RTW89_HW_RATE_VHT_NSS2_MCS3	= 0x113,
347 	RTW89_HW_RATE_VHT_NSS2_MCS4	= 0x114,
348 	RTW89_HW_RATE_VHT_NSS2_MCS5	= 0x115,
349 	RTW89_HW_RATE_VHT_NSS2_MCS6	= 0x116,
350 	RTW89_HW_RATE_VHT_NSS2_MCS7	= 0x117,
351 	RTW89_HW_RATE_VHT_NSS2_MCS8	= 0x118,
352 	RTW89_HW_RATE_VHT_NSS2_MCS9	= 0x119,
353 	RTW89_HW_RATE_VHT_NSS3_MCS0	= 0x120,
354 	RTW89_HW_RATE_VHT_NSS3_MCS1	= 0x121,
355 	RTW89_HW_RATE_VHT_NSS3_MCS2	= 0x122,
356 	RTW89_HW_RATE_VHT_NSS3_MCS3	= 0x123,
357 	RTW89_HW_RATE_VHT_NSS3_MCS4	= 0x124,
358 	RTW89_HW_RATE_VHT_NSS3_MCS5	= 0x125,
359 	RTW89_HW_RATE_VHT_NSS3_MCS6	= 0x126,
360 	RTW89_HW_RATE_VHT_NSS3_MCS7	= 0x127,
361 	RTW89_HW_RATE_VHT_NSS3_MCS8	= 0x128,
362 	RTW89_HW_RATE_VHT_NSS3_MCS9	= 0x129,
363 	RTW89_HW_RATE_VHT_NSS4_MCS0	= 0x130,
364 	RTW89_HW_RATE_VHT_NSS4_MCS1	= 0x131,
365 	RTW89_HW_RATE_VHT_NSS4_MCS2	= 0x132,
366 	RTW89_HW_RATE_VHT_NSS4_MCS3	= 0x133,
367 	RTW89_HW_RATE_VHT_NSS4_MCS4	= 0x134,
368 	RTW89_HW_RATE_VHT_NSS4_MCS5	= 0x135,
369 	RTW89_HW_RATE_VHT_NSS4_MCS6	= 0x136,
370 	RTW89_HW_RATE_VHT_NSS4_MCS7	= 0x137,
371 	RTW89_HW_RATE_VHT_NSS4_MCS8	= 0x138,
372 	RTW89_HW_RATE_VHT_NSS4_MCS9	= 0x139,
373 	RTW89_HW_RATE_HE_NSS1_MCS0	= 0x180,
374 	RTW89_HW_RATE_HE_NSS1_MCS1	= 0x181,
375 	RTW89_HW_RATE_HE_NSS1_MCS2	= 0x182,
376 	RTW89_HW_RATE_HE_NSS1_MCS3	= 0x183,
377 	RTW89_HW_RATE_HE_NSS1_MCS4	= 0x184,
378 	RTW89_HW_RATE_HE_NSS1_MCS5	= 0x185,
379 	RTW89_HW_RATE_HE_NSS1_MCS6	= 0x186,
380 	RTW89_HW_RATE_HE_NSS1_MCS7	= 0x187,
381 	RTW89_HW_RATE_HE_NSS1_MCS8	= 0x188,
382 	RTW89_HW_RATE_HE_NSS1_MCS9	= 0x189,
383 	RTW89_HW_RATE_HE_NSS1_MCS10	= 0x18A,
384 	RTW89_HW_RATE_HE_NSS1_MCS11	= 0x18B,
385 	RTW89_HW_RATE_HE_NSS2_MCS0	= 0x190,
386 	RTW89_HW_RATE_HE_NSS2_MCS1	= 0x191,
387 	RTW89_HW_RATE_HE_NSS2_MCS2	= 0x192,
388 	RTW89_HW_RATE_HE_NSS2_MCS3	= 0x193,
389 	RTW89_HW_RATE_HE_NSS2_MCS4	= 0x194,
390 	RTW89_HW_RATE_HE_NSS2_MCS5	= 0x195,
391 	RTW89_HW_RATE_HE_NSS2_MCS6	= 0x196,
392 	RTW89_HW_RATE_HE_NSS2_MCS7	= 0x197,
393 	RTW89_HW_RATE_HE_NSS2_MCS8	= 0x198,
394 	RTW89_HW_RATE_HE_NSS2_MCS9	= 0x199,
395 	RTW89_HW_RATE_HE_NSS2_MCS10	= 0x19A,
396 	RTW89_HW_RATE_HE_NSS2_MCS11	= 0x19B,
397 	RTW89_HW_RATE_HE_NSS3_MCS0	= 0x1A0,
398 	RTW89_HW_RATE_HE_NSS3_MCS1	= 0x1A1,
399 	RTW89_HW_RATE_HE_NSS3_MCS2	= 0x1A2,
400 	RTW89_HW_RATE_HE_NSS3_MCS3	= 0x1A3,
401 	RTW89_HW_RATE_HE_NSS3_MCS4	= 0x1A4,
402 	RTW89_HW_RATE_HE_NSS3_MCS5	= 0x1A5,
403 	RTW89_HW_RATE_HE_NSS3_MCS6	= 0x1A6,
404 	RTW89_HW_RATE_HE_NSS3_MCS7	= 0x1A7,
405 	RTW89_HW_RATE_HE_NSS3_MCS8	= 0x1A8,
406 	RTW89_HW_RATE_HE_NSS3_MCS9	= 0x1A9,
407 	RTW89_HW_RATE_HE_NSS3_MCS10	= 0x1AA,
408 	RTW89_HW_RATE_HE_NSS3_MCS11	= 0x1AB,
409 	RTW89_HW_RATE_HE_NSS4_MCS0	= 0x1B0,
410 	RTW89_HW_RATE_HE_NSS4_MCS1	= 0x1B1,
411 	RTW89_HW_RATE_HE_NSS4_MCS2	= 0x1B2,
412 	RTW89_HW_RATE_HE_NSS4_MCS3	= 0x1B3,
413 	RTW89_HW_RATE_HE_NSS4_MCS4	= 0x1B4,
414 	RTW89_HW_RATE_HE_NSS4_MCS5	= 0x1B5,
415 	RTW89_HW_RATE_HE_NSS4_MCS6	= 0x1B6,
416 	RTW89_HW_RATE_HE_NSS4_MCS7	= 0x1B7,
417 	RTW89_HW_RATE_HE_NSS4_MCS8	= 0x1B8,
418 	RTW89_HW_RATE_HE_NSS4_MCS9	= 0x1B9,
419 	RTW89_HW_RATE_HE_NSS4_MCS10	= 0x1BA,
420 	RTW89_HW_RATE_HE_NSS4_MCS11	= 0x1BB,
421 
422 	RTW89_HW_RATE_V1_MCS0		= 0x100,
423 	RTW89_HW_RATE_V1_MCS1		= 0x101,
424 	RTW89_HW_RATE_V1_MCS2		= 0x102,
425 	RTW89_HW_RATE_V1_MCS3		= 0x103,
426 	RTW89_HW_RATE_V1_MCS4		= 0x104,
427 	RTW89_HW_RATE_V1_MCS5		= 0x105,
428 	RTW89_HW_RATE_V1_MCS6		= 0x106,
429 	RTW89_HW_RATE_V1_MCS7		= 0x107,
430 	RTW89_HW_RATE_V1_MCS8		= 0x108,
431 	RTW89_HW_RATE_V1_MCS9		= 0x109,
432 	RTW89_HW_RATE_V1_MCS10		= 0x10A,
433 	RTW89_HW_RATE_V1_MCS11		= 0x10B,
434 	RTW89_HW_RATE_V1_MCS12		= 0x10C,
435 	RTW89_HW_RATE_V1_MCS13		= 0x10D,
436 	RTW89_HW_RATE_V1_MCS14		= 0x10E,
437 	RTW89_HW_RATE_V1_MCS15		= 0x10F,
438 	RTW89_HW_RATE_V1_MCS16		= 0x110,
439 	RTW89_HW_RATE_V1_MCS17		= 0x111,
440 	RTW89_HW_RATE_V1_MCS18		= 0x112,
441 	RTW89_HW_RATE_V1_MCS19		= 0x113,
442 	RTW89_HW_RATE_V1_MCS20		= 0x114,
443 	RTW89_HW_RATE_V1_MCS21		= 0x115,
444 	RTW89_HW_RATE_V1_MCS22		= 0x116,
445 	RTW89_HW_RATE_V1_MCS23		= 0x117,
446 	RTW89_HW_RATE_V1_MCS24		= 0x118,
447 	RTW89_HW_RATE_V1_MCS25		= 0x119,
448 	RTW89_HW_RATE_V1_MCS26		= 0x11A,
449 	RTW89_HW_RATE_V1_MCS27		= 0x11B,
450 	RTW89_HW_RATE_V1_MCS28		= 0x11C,
451 	RTW89_HW_RATE_V1_MCS29		= 0x11D,
452 	RTW89_HW_RATE_V1_MCS30		= 0x11E,
453 	RTW89_HW_RATE_V1_MCS31		= 0x11F,
454 	RTW89_HW_RATE_V1_VHT_NSS1_MCS0	= 0x200,
455 	RTW89_HW_RATE_V1_VHT_NSS1_MCS1	= 0x201,
456 	RTW89_HW_RATE_V1_VHT_NSS1_MCS2	= 0x202,
457 	RTW89_HW_RATE_V1_VHT_NSS1_MCS3	= 0x203,
458 	RTW89_HW_RATE_V1_VHT_NSS1_MCS4	= 0x204,
459 	RTW89_HW_RATE_V1_VHT_NSS1_MCS5	= 0x205,
460 	RTW89_HW_RATE_V1_VHT_NSS1_MCS6	= 0x206,
461 	RTW89_HW_RATE_V1_VHT_NSS1_MCS7	= 0x207,
462 	RTW89_HW_RATE_V1_VHT_NSS1_MCS8	= 0x208,
463 	RTW89_HW_RATE_V1_VHT_NSS1_MCS9	= 0x209,
464 	RTW89_HW_RATE_V1_VHT_NSS1_MCS10	= 0x20A,
465 	RTW89_HW_RATE_V1_VHT_NSS1_MCS11	= 0x20B,
466 	RTW89_HW_RATE_V1_VHT_NSS2_MCS0	= 0x220,
467 	RTW89_HW_RATE_V1_VHT_NSS2_MCS1	= 0x221,
468 	RTW89_HW_RATE_V1_VHT_NSS2_MCS2	= 0x222,
469 	RTW89_HW_RATE_V1_VHT_NSS2_MCS3	= 0x223,
470 	RTW89_HW_RATE_V1_VHT_NSS2_MCS4	= 0x224,
471 	RTW89_HW_RATE_V1_VHT_NSS2_MCS5	= 0x225,
472 	RTW89_HW_RATE_V1_VHT_NSS2_MCS6	= 0x226,
473 	RTW89_HW_RATE_V1_VHT_NSS2_MCS7	= 0x227,
474 	RTW89_HW_RATE_V1_VHT_NSS2_MCS8	= 0x228,
475 	RTW89_HW_RATE_V1_VHT_NSS2_MCS9	= 0x229,
476 	RTW89_HW_RATE_V1_VHT_NSS2_MCS10	= 0x22A,
477 	RTW89_HW_RATE_V1_VHT_NSS2_MCS11	= 0x22B,
478 	RTW89_HW_RATE_V1_VHT_NSS3_MCS0	= 0x240,
479 	RTW89_HW_RATE_V1_VHT_NSS3_MCS1	= 0x241,
480 	RTW89_HW_RATE_V1_VHT_NSS3_MCS2	= 0x242,
481 	RTW89_HW_RATE_V1_VHT_NSS3_MCS3	= 0x243,
482 	RTW89_HW_RATE_V1_VHT_NSS3_MCS4	= 0x244,
483 	RTW89_HW_RATE_V1_VHT_NSS3_MCS5	= 0x245,
484 	RTW89_HW_RATE_V1_VHT_NSS3_MCS6	= 0x246,
485 	RTW89_HW_RATE_V1_VHT_NSS3_MCS7	= 0x247,
486 	RTW89_HW_RATE_V1_VHT_NSS3_MCS8	= 0x248,
487 	RTW89_HW_RATE_V1_VHT_NSS3_MCS9	= 0x249,
488 	RTW89_HW_RATE_V1_VHT_NSS3_MCS10	= 0x24A,
489 	RTW89_HW_RATE_V1_VHT_NSS3_MCS11	= 0x24B,
490 	RTW89_HW_RATE_V1_VHT_NSS4_MCS0	= 0x260,
491 	RTW89_HW_RATE_V1_VHT_NSS4_MCS1	= 0x261,
492 	RTW89_HW_RATE_V1_VHT_NSS4_MCS2	= 0x262,
493 	RTW89_HW_RATE_V1_VHT_NSS4_MCS3	= 0x263,
494 	RTW89_HW_RATE_V1_VHT_NSS4_MCS4	= 0x264,
495 	RTW89_HW_RATE_V1_VHT_NSS4_MCS5	= 0x265,
496 	RTW89_HW_RATE_V1_VHT_NSS4_MCS6	= 0x266,
497 	RTW89_HW_RATE_V1_VHT_NSS4_MCS7	= 0x267,
498 	RTW89_HW_RATE_V1_VHT_NSS4_MCS8	= 0x268,
499 	RTW89_HW_RATE_V1_VHT_NSS4_MCS9	= 0x269,
500 	RTW89_HW_RATE_V1_VHT_NSS4_MCS10	= 0x26A,
501 	RTW89_HW_RATE_V1_VHT_NSS4_MCS11	= 0x26B,
502 	RTW89_HW_RATE_V1_HE_NSS1_MCS0	= 0x300,
503 	RTW89_HW_RATE_V1_HE_NSS1_MCS1	= 0x301,
504 	RTW89_HW_RATE_V1_HE_NSS1_MCS2	= 0x302,
505 	RTW89_HW_RATE_V1_HE_NSS1_MCS3	= 0x303,
506 	RTW89_HW_RATE_V1_HE_NSS1_MCS4	= 0x304,
507 	RTW89_HW_RATE_V1_HE_NSS1_MCS5	= 0x305,
508 	RTW89_HW_RATE_V1_HE_NSS1_MCS6	= 0x306,
509 	RTW89_HW_RATE_V1_HE_NSS1_MCS7	= 0x307,
510 	RTW89_HW_RATE_V1_HE_NSS1_MCS8	= 0x308,
511 	RTW89_HW_RATE_V1_HE_NSS1_MCS9	= 0x309,
512 	RTW89_HW_RATE_V1_HE_NSS1_MCS10	= 0x30A,
513 	RTW89_HW_RATE_V1_HE_NSS1_MCS11	= 0x30B,
514 	RTW89_HW_RATE_V1_HE_NSS2_MCS0	= 0x320,
515 	RTW89_HW_RATE_V1_HE_NSS2_MCS1	= 0x321,
516 	RTW89_HW_RATE_V1_HE_NSS2_MCS2	= 0x322,
517 	RTW89_HW_RATE_V1_HE_NSS2_MCS3	= 0x323,
518 	RTW89_HW_RATE_V1_HE_NSS2_MCS4	= 0x324,
519 	RTW89_HW_RATE_V1_HE_NSS2_MCS5	= 0x325,
520 	RTW89_HW_RATE_V1_HE_NSS2_MCS6	= 0x326,
521 	RTW89_HW_RATE_V1_HE_NSS2_MCS7	= 0x327,
522 	RTW89_HW_RATE_V1_HE_NSS2_MCS8	= 0x328,
523 	RTW89_HW_RATE_V1_HE_NSS2_MCS9	= 0x329,
524 	RTW89_HW_RATE_V1_HE_NSS2_MCS10	= 0x32A,
525 	RTW89_HW_RATE_V1_HE_NSS2_MCS11	= 0x32B,
526 	RTW89_HW_RATE_V1_HE_NSS3_MCS0	= 0x340,
527 	RTW89_HW_RATE_V1_HE_NSS3_MCS1	= 0x341,
528 	RTW89_HW_RATE_V1_HE_NSS3_MCS2	= 0x342,
529 	RTW89_HW_RATE_V1_HE_NSS3_MCS3	= 0x343,
530 	RTW89_HW_RATE_V1_HE_NSS3_MCS4	= 0x344,
531 	RTW89_HW_RATE_V1_HE_NSS3_MCS5	= 0x345,
532 	RTW89_HW_RATE_V1_HE_NSS3_MCS6	= 0x346,
533 	RTW89_HW_RATE_V1_HE_NSS3_MCS7	= 0x347,
534 	RTW89_HW_RATE_V1_HE_NSS3_MCS8	= 0x348,
535 	RTW89_HW_RATE_V1_HE_NSS3_MCS9	= 0x349,
536 	RTW89_HW_RATE_V1_HE_NSS3_MCS10	= 0x34A,
537 	RTW89_HW_RATE_V1_HE_NSS3_MCS11	= 0x34B,
538 	RTW89_HW_RATE_V1_HE_NSS4_MCS0	= 0x360,
539 	RTW89_HW_RATE_V1_HE_NSS4_MCS1	= 0x361,
540 	RTW89_HW_RATE_V1_HE_NSS4_MCS2	= 0x362,
541 	RTW89_HW_RATE_V1_HE_NSS4_MCS3	= 0x363,
542 	RTW89_HW_RATE_V1_HE_NSS4_MCS4	= 0x364,
543 	RTW89_HW_RATE_V1_HE_NSS4_MCS5	= 0x365,
544 	RTW89_HW_RATE_V1_HE_NSS4_MCS6	= 0x366,
545 	RTW89_HW_RATE_V1_HE_NSS4_MCS7	= 0x367,
546 	RTW89_HW_RATE_V1_HE_NSS4_MCS8	= 0x368,
547 	RTW89_HW_RATE_V1_HE_NSS4_MCS9	= 0x369,
548 	RTW89_HW_RATE_V1_HE_NSS4_MCS10	= 0x36A,
549 	RTW89_HW_RATE_V1_HE_NSS4_MCS11	= 0x36B,
550 	RTW89_HW_RATE_V1_EHT_NSS1_MCS0	= 0x400,
551 	RTW89_HW_RATE_V1_EHT_NSS1_MCS1	= 0x401,
552 	RTW89_HW_RATE_V1_EHT_NSS1_MCS2	= 0x402,
553 	RTW89_HW_RATE_V1_EHT_NSS1_MCS3	= 0x403,
554 	RTW89_HW_RATE_V1_EHT_NSS1_MCS4	= 0x404,
555 	RTW89_HW_RATE_V1_EHT_NSS1_MCS5	= 0x405,
556 	RTW89_HW_RATE_V1_EHT_NSS1_MCS6	= 0x406,
557 	RTW89_HW_RATE_V1_EHT_NSS1_MCS7	= 0x407,
558 	RTW89_HW_RATE_V1_EHT_NSS1_MCS8	= 0x408,
559 	RTW89_HW_RATE_V1_EHT_NSS1_MCS9	= 0x409,
560 	RTW89_HW_RATE_V1_EHT_NSS1_MCS10	= 0x40A,
561 	RTW89_HW_RATE_V1_EHT_NSS1_MCS11	= 0x40B,
562 	RTW89_HW_RATE_V1_EHT_NSS1_MCS12	= 0x40C,
563 	RTW89_HW_RATE_V1_EHT_NSS1_MCS13	= 0x40D,
564 	RTW89_HW_RATE_V1_EHT_NSS1_MCS14	= 0x40E,
565 	RTW89_HW_RATE_V1_EHT_NSS1_MCS15	= 0x40F,
566 	RTW89_HW_RATE_V1_EHT_NSS2_MCS0	= 0x420,
567 	RTW89_HW_RATE_V1_EHT_NSS2_MCS1	= 0x421,
568 	RTW89_HW_RATE_V1_EHT_NSS2_MCS2	= 0x422,
569 	RTW89_HW_RATE_V1_EHT_NSS2_MCS3	= 0x423,
570 	RTW89_HW_RATE_V1_EHT_NSS2_MCS4	= 0x424,
571 	RTW89_HW_RATE_V1_EHT_NSS2_MCS5	= 0x425,
572 	RTW89_HW_RATE_V1_EHT_NSS2_MCS6	= 0x426,
573 	RTW89_HW_RATE_V1_EHT_NSS2_MCS7	= 0x427,
574 	RTW89_HW_RATE_V1_EHT_NSS2_MCS8	= 0x428,
575 	RTW89_HW_RATE_V1_EHT_NSS2_MCS9	= 0x429,
576 	RTW89_HW_RATE_V1_EHT_NSS2_MCS10	= 0x42A,
577 	RTW89_HW_RATE_V1_EHT_NSS2_MCS11	= 0x42B,
578 	RTW89_HW_RATE_V1_EHT_NSS2_MCS12	= 0x42C,
579 	RTW89_HW_RATE_V1_EHT_NSS2_MCS13	= 0x42D,
580 	RTW89_HW_RATE_V1_EHT_NSS3_MCS0	= 0x440,
581 	RTW89_HW_RATE_V1_EHT_NSS3_MCS1	= 0x441,
582 	RTW89_HW_RATE_V1_EHT_NSS3_MCS2	= 0x442,
583 	RTW89_HW_RATE_V1_EHT_NSS3_MCS3	= 0x443,
584 	RTW89_HW_RATE_V1_EHT_NSS3_MCS4	= 0x444,
585 	RTW89_HW_RATE_V1_EHT_NSS3_MCS5	= 0x445,
586 	RTW89_HW_RATE_V1_EHT_NSS3_MCS6	= 0x446,
587 	RTW89_HW_RATE_V1_EHT_NSS3_MCS7	= 0x447,
588 	RTW89_HW_RATE_V1_EHT_NSS3_MCS8	= 0x448,
589 	RTW89_HW_RATE_V1_EHT_NSS3_MCS9	= 0x449,
590 	RTW89_HW_RATE_V1_EHT_NSS3_MCS10	= 0x44A,
591 	RTW89_HW_RATE_V1_EHT_NSS3_MCS11	= 0x44B,
592 	RTW89_HW_RATE_V1_EHT_NSS3_MCS12	= 0x44C,
593 	RTW89_HW_RATE_V1_EHT_NSS3_MCS13	= 0x44D,
594 	RTW89_HW_RATE_V1_EHT_NSS4_MCS0	= 0x460,
595 	RTW89_HW_RATE_V1_EHT_NSS4_MCS1	= 0x461,
596 	RTW89_HW_RATE_V1_EHT_NSS4_MCS2	= 0x462,
597 	RTW89_HW_RATE_V1_EHT_NSS4_MCS3	= 0x463,
598 	RTW89_HW_RATE_V1_EHT_NSS4_MCS4	= 0x464,
599 	RTW89_HW_RATE_V1_EHT_NSS4_MCS5	= 0x465,
600 	RTW89_HW_RATE_V1_EHT_NSS4_MCS6	= 0x466,
601 	RTW89_HW_RATE_V1_EHT_NSS4_MCS7	= 0x467,
602 	RTW89_HW_RATE_V1_EHT_NSS4_MCS8	= 0x468,
603 	RTW89_HW_RATE_V1_EHT_NSS4_MCS9	= 0x469,
604 	RTW89_HW_RATE_V1_EHT_NSS4_MCS10	= 0x46A,
605 	RTW89_HW_RATE_V1_EHT_NSS4_MCS11	= 0x46B,
606 	RTW89_HW_RATE_V1_EHT_NSS4_MCS12	= 0x46C,
607 	RTW89_HW_RATE_V1_EHT_NSS4_MCS13	= 0x46D,
608 
609 	RTW89_HW_RATE_NR,
610 	RTW89_HW_RATE_INVAL,
611 
612 	RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7),
613 	RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0),
614 	RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8),
615 	RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0),
616 };
617 
618 /* 2G channels,
619  * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
620  */
621 #define RTW89_2G_CH_NUM 14
622 
623 /* 5G channels,
624  * 36, 38, 40, 42, 44, 46, 48, 50,
625  * 52, 54, 56, 58, 60, 62, 64,
626  * 100, 102, 104, 106, 108, 110, 112, 114,
627  * 116, 118, 120, 122, 124, 126, 128, 130,
628  * 132, 134, 136, 138, 140, 142, 144,
629  * 149, 151, 153, 155, 157, 159, 161, 163,
630  * 165, 167, 169, 171, 173, 175, 177
631  */
632 #define RTW89_5G_CH_NUM 53
633 
634 /* 6G channels,
635  * 1, 3, 5, 7, 9, 11, 13, 15,
636  * 17, 19, 21, 23, 25, 27, 29, 33,
637  * 35, 37, 39, 41, 43, 45, 47, 49,
638  * 51, 53, 55, 57, 59, 61, 65, 67,
639  * 69, 71, 73, 75, 77, 79, 81, 83,
640  * 85, 87, 89, 91, 93, 97, 99, 101,
641  * 103, 105, 107, 109, 111, 113, 115, 117,
642  * 119, 121, 123, 125, 129, 131, 133, 135,
643  * 137, 139, 141, 143, 145, 147, 149, 151,
644  * 153, 155, 157, 161, 163, 165, 167, 169,
645  * 171, 173, 175, 177, 179, 181, 183, 185,
646  * 187, 189, 193, 195, 197, 199, 201, 203,
647  * 205, 207, 209, 211, 213, 215, 217, 219,
648  * 221, 225, 227, 229, 231, 233, 235, 237,
649  * 239, 241, 243, 245, 247, 249, 251, 253,
650  */
651 #define RTW89_6G_CH_NUM 120
652 
653 enum rtw89_rate_section {
654 	RTW89_RS_CCK,
655 	RTW89_RS_OFDM,
656 	RTW89_RS_MCS, /* for HT/VHT/HE */
657 	RTW89_RS_HEDCM,
658 	RTW89_RS_OFFSET,
659 	RTW89_RS_NUM,
660 	RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1,
661 	RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1,
662 };
663 
664 enum rtw89_rate_offset_indexes {
665 	RTW89_RATE_OFFSET_HE,
666 	RTW89_RATE_OFFSET_VHT,
667 	RTW89_RATE_OFFSET_HT,
668 	RTW89_RATE_OFFSET_OFDM,
669 	RTW89_RATE_OFFSET_CCK,
670 	RTW89_RATE_OFFSET_DLRU_EHT,
671 	RTW89_RATE_OFFSET_DLRU_HE,
672 	RTW89_RATE_OFFSET_EHT,
673 	__RTW89_RATE_OFFSET_NUM,
674 
675 	RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1,
676 	RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1,
677 };
678 
679 enum rtw89_rate_num {
680 	RTW89_RATE_CCK_NUM	= 4,
681 	RTW89_RATE_OFDM_NUM	= 8,
682 	RTW89_RATE_HEDCM_NUM	= 4, /* for HEDCM MCS0/1/3/4 */
683 
684 	RTW89_RATE_MCS_NUM_AX	= 12,
685 	RTW89_RATE_MCS_NUM_BE	= 16,
686 	__RTW89_RATE_MCS_NUM	= 16,
687 };
688 
689 enum rtw89_nss {
690 	RTW89_NSS_1		= 0,
691 	RTW89_NSS_2		= 1,
692 	/* HE DCM only support 1ss and 2ss */
693 	RTW89_NSS_HEDCM_NUM	= RTW89_NSS_2 + 1,
694 	RTW89_NSS_3		= 2,
695 	RTW89_NSS_4		= 3,
696 	RTW89_NSS_NUM,
697 };
698 
699 enum rtw89_ntx {
700 	RTW89_1TX	= 0,
701 	RTW89_2TX	= 1,
702 	RTW89_NTX_NUM,
703 };
704 
705 enum rtw89_beamforming_type {
706 	RTW89_NONBF	= 0,
707 	RTW89_BF	= 1,
708 	RTW89_BF_NUM,
709 };
710 
711 enum rtw89_ofdma_type {
712 	RTW89_NON_OFDMA	= 0,
713 	RTW89_OFDMA	= 1,
714 	RTW89_OFDMA_NUM,
715 };
716 
717 enum rtw89_regulation_type {
718 	RTW89_WW	= 0,
719 	RTW89_ETSI	= 1,
720 	RTW89_FCC	= 2,
721 	RTW89_MKK	= 3,
722 	RTW89_NA	= 4,
723 	RTW89_IC	= 5,
724 	RTW89_KCC	= 6,
725 	RTW89_ACMA	= 7,
726 	RTW89_NCC	= 8,
727 	RTW89_MEXICO	= 9,
728 	RTW89_CHILE	= 10,
729 	RTW89_UKRAINE	= 11,
730 	RTW89_CN	= 12,
731 	RTW89_QATAR	= 13,
732 	RTW89_UK	= 14,
733 	RTW89_THAILAND	= 15,
734 	RTW89_REGD_NUM,
735 };
736 
737 enum rtw89_reg_6ghz_power {
738 	RTW89_REG_6GHZ_POWER_VLP = 0,
739 	RTW89_REG_6GHZ_POWER_LPI = 1,
740 	RTW89_REG_6GHZ_POWER_STD = 2,
741 
742 	NUM_OF_RTW89_REG_6GHZ_POWER,
743 	RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP,
744 };
745 
746 enum rtw89_fw_pkt_ofld_type {
747 	RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0,
748 	RTW89_PKT_OFLD_TYPE_PS_POLL = 1,
749 	RTW89_PKT_OFLD_TYPE_NULL_DATA = 2,
750 	RTW89_PKT_OFLD_TYPE_QOS_NULL = 3,
751 	RTW89_PKT_OFLD_TYPE_CTS2SELF = 4,
752 	RTW89_PKT_OFLD_TYPE_ARP_RSP = 5,
753 	RTW89_PKT_OFLD_TYPE_NDP = 6,
754 	RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7,
755 	RTW89_PKT_OFLD_TYPE_SA_QUERY = 8,
756 	RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12,
757 	RTW89_PKT_OFLD_TYPE_NUM,
758 };
759 
760 struct rtw89_txpwr_byrate {
761 	s8 cck[RTW89_RATE_CCK_NUM];
762 	s8 ofdm[RTW89_RATE_OFDM_NUM];
763 	s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM];
764 	s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM];
765 	s8 offset[__RTW89_RATE_OFFSET_NUM];
766 	s8 trap;
767 };
768 
769 struct rtw89_rate_desc {
770 	enum rtw89_nss nss;
771 	enum rtw89_rate_section rs;
772 	enum rtw89_ofdma_type ofdma;
773 	u8 idx;
774 };
775 
776 #define PHY_STS_HDR_LEN 8
777 #define RF_PATH_MAX 4
778 #define RTW89_MAX_PPDU_CNT 8
779 struct rtw89_rx_phy_ppdu {
780 	void *buf;
781 	u32 len;
782 	u8 rssi_avg;
783 	u8 rssi[RF_PATH_MAX];
784 	u8 mac_id;
785 	u8 chan_idx;
786 	u8 ie;
787 	u16 rate;
788 	struct {
789 		bool has;
790 		u8 avg_snr;
791 		u8 evm_max;
792 		u8 evm_min;
793 	} ofdm;
794 	bool to_self;
795 	bool valid;
796 };
797 
798 enum rtw89_mac_idx {
799 	RTW89_MAC_0 = 0,
800 	RTW89_MAC_1 = 1,
801 };
802 
803 enum rtw89_phy_idx {
804 	RTW89_PHY_0 = 0,
805 	RTW89_PHY_1 = 1,
806 	RTW89_PHY_MAX
807 };
808 
809 enum rtw89_sub_entity_idx {
810 	RTW89_SUB_ENTITY_0 = 0,
811 	RTW89_SUB_ENTITY_1 = 1,
812 
813 	NUM_OF_RTW89_SUB_ENTITY,
814 	RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY,
815 };
816 
817 enum rtw89_rf_path {
818 	RF_PATH_A = 0,
819 	RF_PATH_B = 1,
820 	RF_PATH_C = 2,
821 	RF_PATH_D = 3,
822 	RF_PATH_AB,
823 	RF_PATH_AC,
824 	RF_PATH_AD,
825 	RF_PATH_BC,
826 	RF_PATH_BD,
827 	RF_PATH_CD,
828 	RF_PATH_ABC,
829 	RF_PATH_ABD,
830 	RF_PATH_ACD,
831 	RF_PATH_BCD,
832 	RF_PATH_ABCD,
833 };
834 
835 enum rtw89_rf_path_bit {
836 	RF_A	= BIT(0),
837 	RF_B	= BIT(1),
838 	RF_C	= BIT(2),
839 	RF_D	= BIT(3),
840 
841 	RF_AB	= (RF_A | RF_B),
842 	RF_AC	= (RF_A | RF_C),
843 	RF_AD	= (RF_A | RF_D),
844 	RF_BC	= (RF_B | RF_C),
845 	RF_BD	= (RF_B | RF_D),
846 	RF_CD	= (RF_C | RF_D),
847 
848 	RF_ABC	= (RF_A | RF_B | RF_C),
849 	RF_ABD	= (RF_A | RF_B | RF_D),
850 	RF_ACD	= (RF_A | RF_C | RF_D),
851 	RF_BCD	= (RF_B | RF_C | RF_D),
852 
853 	RF_ABCD	= (RF_A | RF_B | RF_C | RF_D),
854 };
855 
856 enum rtw89_bandwidth {
857 	RTW89_CHANNEL_WIDTH_20	= 0,
858 	RTW89_CHANNEL_WIDTH_40	= 1,
859 	RTW89_CHANNEL_WIDTH_80	= 2,
860 	RTW89_CHANNEL_WIDTH_160	= 3,
861 	RTW89_CHANNEL_WIDTH_320	= 4,
862 
863 	/* keep index order above */
864 	RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5,
865 
866 	RTW89_CHANNEL_WIDTH_80_80 = 5,
867 	RTW89_CHANNEL_WIDTH_5 = 6,
868 	RTW89_CHANNEL_WIDTH_10 = 7,
869 };
870 
871 enum rtw89_ps_mode {
872 	RTW89_PS_MODE_NONE	= 0,
873 	RTW89_PS_MODE_RFOFF	= 1,
874 	RTW89_PS_MODE_CLK_GATED	= 2,
875 	RTW89_PS_MODE_PWR_GATED	= 3,
876 };
877 
878 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1)
879 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1)
880 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
881 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
882 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1)
883 
884 enum rtw89_ru_bandwidth {
885 	RTW89_RU26 = 0,
886 	RTW89_RU52 = 1,
887 	RTW89_RU106 = 2,
888 	RTW89_RU52_26 = 3,
889 	RTW89_RU106_26 = 4,
890 	RTW89_RU_NUM,
891 };
892 
893 enum rtw89_sc_offset {
894 	RTW89_SC_DONT_CARE	= 0,
895 	RTW89_SC_20_UPPER	= 1,
896 	RTW89_SC_20_LOWER	= 2,
897 	RTW89_SC_20_UPMOST	= 3,
898 	RTW89_SC_20_LOWEST	= 4,
899 	RTW89_SC_20_UP2X	= 5,
900 	RTW89_SC_20_LOW2X	= 6,
901 	RTW89_SC_20_UP3X	= 7,
902 	RTW89_SC_20_LOW3X	= 8,
903 	RTW89_SC_40_UPPER	= 9,
904 	RTW89_SC_40_LOWER	= 10,
905 };
906 
907 enum rtw89_wow_flags {
908 	RTW89_WOW_FLAG_EN_MAGIC_PKT,
909 	RTW89_WOW_FLAG_EN_REKEY_PKT,
910 	RTW89_WOW_FLAG_EN_DISCONNECT,
911 	RTW89_WOW_FLAG_NUM,
912 };
913 
914 struct rtw89_chan {
915 	u8 channel;
916 	u8 primary_channel;
917 	enum rtw89_band band_type;
918 	enum rtw89_bandwidth band_width;
919 
920 	/* The follow-up are derived from the above. We must ensure that it
921 	 * is assigned correctly in rtw89_chan_create() if new one is added.
922 	 */
923 	u32 freq;
924 	enum rtw89_subband subband_type;
925 	enum rtw89_sc_offset pri_ch_idx;
926 	u8 pri_sb_idx;
927 };
928 
929 struct rtw89_chan_rcd {
930 	u8 prev_primary_channel;
931 	enum rtw89_band prev_band_type;
932 	bool band_changed;
933 };
934 
935 struct rtw89_channel_help_params {
936 	u32 tx_en;
937 };
938 
939 struct rtw89_port_reg {
940 	u32 port_cfg;
941 	u32 tbtt_prohib;
942 	u32 bcn_area;
943 	u32 bcn_early;
944 	u32 tbtt_early;
945 	u32 tbtt_agg;
946 	u32 bcn_space;
947 	u32 bcn_forcetx;
948 	u32 bcn_err_cnt;
949 	u32 bcn_err_flag;
950 	u32 dtim_ctrl;
951 	u32 tbtt_shift;
952 	u32 bcn_cnt_tmr;
953 	u32 tsftr_l;
954 	u32 tsftr_h;
955 	u32 md_tsft;
956 	u32 bss_color;
957 	u32 mbssid;
958 	u32 mbssid_drop;
959 	u32 tsf_sync;
960 	u32 hiq_win[RTW89_PORT_NUM];
961 };
962 
963 struct rtw89_txwd_body {
964 	__le32 dword0;
965 	__le32 dword1;
966 	__le32 dword2;
967 	__le32 dword3;
968 	__le32 dword4;
969 	__le32 dword5;
970 } __packed;
971 
972 struct rtw89_txwd_body_v1 {
973 	__le32 dword0;
974 	__le32 dword1;
975 	__le32 dword2;
976 	__le32 dword3;
977 	__le32 dword4;
978 	__le32 dword5;
979 	__le32 dword6;
980 	__le32 dword7;
981 } __packed;
982 
983 struct rtw89_txwd_body_v2 {
984 	__le32 dword0;
985 	__le32 dword1;
986 	__le32 dword2;
987 	__le32 dword3;
988 	__le32 dword4;
989 	__le32 dword5;
990 	__le32 dword6;
991 	__le32 dword7;
992 } __packed;
993 
994 struct rtw89_txwd_info {
995 	__le32 dword0;
996 	__le32 dword1;
997 	__le32 dword2;
998 	__le32 dword3;
999 	__le32 dword4;
1000 	__le32 dword5;
1001 } __packed;
1002 
1003 struct rtw89_txwd_info_v2 {
1004 	__le32 dword0;
1005 	__le32 dword1;
1006 	__le32 dword2;
1007 	__le32 dword3;
1008 	__le32 dword4;
1009 	__le32 dword5;
1010 	__le32 dword6;
1011 	__le32 dword7;
1012 } __packed;
1013 
1014 struct rtw89_rx_desc_info {
1015 	u16 pkt_size;
1016 	u8 pkt_type;
1017 	u8 drv_info_size;
1018 	u8 phy_rpt_size;
1019 	u8 hdr_cnv_size;
1020 	u8 shift;
1021 	u8 wl_hd_iv_len;
1022 	bool long_rxdesc;
1023 	bool bb_sel;
1024 	bool mac_info_valid;
1025 	u16 data_rate;
1026 	u8 gi_ltf;
1027 	u8 bw;
1028 	u32 free_run_cnt;
1029 	u8 user_id;
1030 	bool sr_en;
1031 	u8 ppdu_cnt;
1032 	u8 ppdu_type;
1033 	bool icv_err;
1034 	bool crc32_err;
1035 	bool hw_dec;
1036 	bool sw_dec;
1037 	bool addr1_match;
1038 	u8 frag;
1039 	u16 seq;
1040 	u8 frame_type;
1041 	u8 rx_pl_id;
1042 	bool addr_cam_valid;
1043 	u8 addr_cam_id;
1044 	u8 sec_cam_id;
1045 	u8 mac_id;
1046 	u16 offset;
1047 	u16 rxd_len;
1048 	bool ready;
1049 };
1050 
1051 struct rtw89_rxdesc_short {
1052 	__le32 dword0;
1053 	__le32 dword1;
1054 	__le32 dword2;
1055 	__le32 dword3;
1056 } __packed;
1057 
1058 struct rtw89_rxdesc_short_v2 {
1059 	__le32 dword0;
1060 	__le32 dword1;
1061 	__le32 dword2;
1062 	__le32 dword3;
1063 	__le32 dword4;
1064 	__le32 dword5;
1065 } __packed;
1066 
1067 struct rtw89_rxdesc_long {
1068 	__le32 dword0;
1069 	__le32 dword1;
1070 	__le32 dword2;
1071 	__le32 dword3;
1072 	__le32 dword4;
1073 	__le32 dword5;
1074 	__le32 dword6;
1075 	__le32 dword7;
1076 } __packed;
1077 
1078 struct rtw89_rxdesc_long_v2 {
1079 	__le32 dword0;
1080 	__le32 dword1;
1081 	__le32 dword2;
1082 	__le32 dword3;
1083 	__le32 dword4;
1084 	__le32 dword5;
1085 	__le32 dword6;
1086 	__le32 dword7;
1087 	__le32 dword8;
1088 	__le32 dword9;
1089 } __packed;
1090 
1091 struct rtw89_tx_desc_info {
1092 	u16 pkt_size;
1093 	u8 wp_offset;
1094 	u8 mac_id;
1095 	u8 qsel;
1096 	u8 ch_dma;
1097 	u8 hdr_llc_len;
1098 	bool is_bmc;
1099 	bool en_wd_info;
1100 	bool wd_page;
1101 	bool use_rate;
1102 	bool dis_data_fb;
1103 	bool tid_indicate;
1104 	bool agg_en;
1105 	bool bk;
1106 	u8 ampdu_density;
1107 	u8 ampdu_num;
1108 	bool sec_en;
1109 	u8 addr_info_nr;
1110 	u8 sec_keyid;
1111 	u8 sec_type;
1112 	u8 sec_cam_idx;
1113 	u8 sec_seq[6];
1114 	u16 data_rate;
1115 	u16 data_retry_lowest_rate;
1116 	bool fw_dl;
1117 	u16 seq;
1118 	bool a_ctrl_bsr;
1119 	u8 hw_ssn_sel;
1120 #define RTW89_MGMT_HW_SSN_SEL	1
1121 	u8 hw_seq_mode;
1122 #define RTW89_MGMT_HW_SEQ_MODE	1
1123 	bool hiq;
1124 	u8 port;
1125 	bool er_cap;
1126 };
1127 
1128 struct rtw89_core_tx_request {
1129 	enum rtw89_core_tx_type tx_type;
1130 
1131 	struct sk_buff *skb;
1132 	struct ieee80211_vif *vif;
1133 	struct ieee80211_sta *sta;
1134 	struct rtw89_tx_desc_info desc_info;
1135 };
1136 
1137 struct rtw89_txq {
1138 	struct list_head list;
1139 	unsigned long flags;
1140 	int wait_cnt;
1141 };
1142 
1143 struct rtw89_mac_ax_gnt {
1144 	u8 gnt_bt_sw_en;
1145 	u8 gnt_bt;
1146 	u8 gnt_wl_sw_en;
1147 	u8 gnt_wl;
1148 } __packed;
1149 
1150 #define RTW89_MAC_AX_COEX_GNT_NR 2
1151 struct rtw89_mac_ax_coex_gnt {
1152 	struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR];
1153 };
1154 
1155 enum rtw89_btc_ncnt {
1156 	BTC_NCNT_POWER_ON = 0x0,
1157 	BTC_NCNT_POWER_OFF,
1158 	BTC_NCNT_INIT_COEX,
1159 	BTC_NCNT_SCAN_START,
1160 	BTC_NCNT_SCAN_FINISH,
1161 	BTC_NCNT_SPECIAL_PACKET,
1162 	BTC_NCNT_SWITCH_BAND,
1163 	BTC_NCNT_RFK_TIMEOUT,
1164 	BTC_NCNT_SHOW_COEX_INFO,
1165 	BTC_NCNT_ROLE_INFO,
1166 	BTC_NCNT_CONTROL,
1167 	BTC_NCNT_RADIO_STATE,
1168 	BTC_NCNT_CUSTOMERIZE,
1169 	BTC_NCNT_WL_RFK,
1170 	BTC_NCNT_WL_STA,
1171 	BTC_NCNT_FWINFO,
1172 	BTC_NCNT_TIMER,
1173 	BTC_NCNT_NUM
1174 };
1175 
1176 enum rtw89_btc_btinfo {
1177 	BTC_BTINFO_L0 = 0,
1178 	BTC_BTINFO_L1,
1179 	BTC_BTINFO_L2,
1180 	BTC_BTINFO_L3,
1181 	BTC_BTINFO_H0,
1182 	BTC_BTINFO_H1,
1183 	BTC_BTINFO_H2,
1184 	BTC_BTINFO_H3,
1185 	BTC_BTINFO_MAX
1186 };
1187 
1188 enum rtw89_btc_dcnt {
1189 	BTC_DCNT_RUN = 0x0,
1190 	BTC_DCNT_CX_RUNINFO,
1191 	BTC_DCNT_RPT,
1192 	BTC_DCNT_RPT_HANG,
1193 	BTC_DCNT_CYCLE,
1194 	BTC_DCNT_CYCLE_HANG,
1195 	BTC_DCNT_W1,
1196 	BTC_DCNT_W1_HANG,
1197 	BTC_DCNT_B1,
1198 	BTC_DCNT_B1_HANG,
1199 	BTC_DCNT_TDMA_NONSYNC,
1200 	BTC_DCNT_SLOT_NONSYNC,
1201 	BTC_DCNT_BTCNT_HANG,
1202 	BTC_DCNT_WL_SLOT_DRIFT,
1203 	BTC_DCNT_WL_STA_LAST,
1204 	BTC_DCNT_BT_SLOT_DRIFT,
1205 	BTC_DCNT_BT_SLOT_FLOOD,
1206 	BTC_DCNT_FDDT_TRIG,
1207 	BTC_DCNT_E2G,
1208 	BTC_DCNT_E2G_HANG,
1209 	BTC_DCNT_NUM
1210 };
1211 
1212 enum rtw89_btc_wl_state_cnt {
1213 	BTC_WCNT_SCANAP = 0x0,
1214 	BTC_WCNT_DHCP,
1215 	BTC_WCNT_EAPOL,
1216 	BTC_WCNT_ARP,
1217 	BTC_WCNT_SCBDUPDATE,
1218 	BTC_WCNT_RFK_REQ,
1219 	BTC_WCNT_RFK_GO,
1220 	BTC_WCNT_RFK_REJECT,
1221 	BTC_WCNT_RFK_TIMEOUT,
1222 	BTC_WCNT_CH_UPDATE,
1223 	BTC_WCNT_NUM
1224 };
1225 
1226 enum rtw89_btc_bt_state_cnt {
1227 	BTC_BCNT_RETRY = 0x0,
1228 	BTC_BCNT_REINIT,
1229 	BTC_BCNT_REENABLE,
1230 	BTC_BCNT_SCBDREAD,
1231 	BTC_BCNT_RELINK,
1232 	BTC_BCNT_IGNOWL,
1233 	BTC_BCNT_INQPAG,
1234 	BTC_BCNT_INQ,
1235 	BTC_BCNT_PAGE,
1236 	BTC_BCNT_ROLESW,
1237 	BTC_BCNT_AFH,
1238 	BTC_BCNT_INFOUPDATE,
1239 	BTC_BCNT_INFOSAME,
1240 	BTC_BCNT_SCBDUPDATE,
1241 	BTC_BCNT_HIPRI_TX,
1242 	BTC_BCNT_HIPRI_RX,
1243 	BTC_BCNT_LOPRI_TX,
1244 	BTC_BCNT_LOPRI_RX,
1245 	BTC_BCNT_POLUT,
1246 	BTC_BCNT_RATECHG,
1247 	BTC_BCNT_NUM
1248 };
1249 
1250 enum rtw89_btc_bt_profile {
1251 	BTC_BT_NOPROFILE = 0,
1252 	BTC_BT_HFP = BIT(0),
1253 	BTC_BT_HID = BIT(1),
1254 	BTC_BT_A2DP = BIT(2),
1255 	BTC_BT_PAN = BIT(3),
1256 	BTC_PROFILE_MAX = 4,
1257 };
1258 
1259 struct rtw89_btc_ant_info {
1260 	u8 type;  /* shared, dedicated */
1261 	u8 num;
1262 	u8 isolation;
1263 
1264 	u8 single_pos: 1;/* Single antenna at S0 or S1 */
1265 	u8 diversity: 1;
1266 	u8 btg_pos: 2;
1267 	u8 stream_cnt: 4;
1268 };
1269 
1270 enum rtw89_tfc_dir {
1271 	RTW89_TFC_UL,
1272 	RTW89_TFC_DL,
1273 };
1274 
1275 struct rtw89_btc_wl_smap {
1276 	u32 busy: 1;
1277 	u32 scan: 1;
1278 	u32 connecting: 1;
1279 	u32 roaming: 1;
1280 	u32 _4way: 1;
1281 	u32 rf_off: 1;
1282 	u32 lps: 2;
1283 	u32 ips: 1;
1284 	u32 init_ok: 1;
1285 	u32 traffic_dir : 2;
1286 	u32 rf_off_pre: 1;
1287 	u32 lps_pre: 2;
1288 };
1289 
1290 enum rtw89_tfc_lv {
1291 	RTW89_TFC_IDLE,
1292 	RTW89_TFC_ULTRA_LOW,
1293 	RTW89_TFC_LOW,
1294 	RTW89_TFC_MID,
1295 	RTW89_TFC_HIGH,
1296 };
1297 
1298 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */
1299 DECLARE_EWMA(tp, 10, 2);
1300 
1301 struct rtw89_traffic_stats {
1302 	/* units in bytes */
1303 	u64 tx_unicast;
1304 	u64 rx_unicast;
1305 	u32 tx_avg_len;
1306 	u32 rx_avg_len;
1307 
1308 	/* count for packets */
1309 	u64 tx_cnt;
1310 	u64 rx_cnt;
1311 
1312 	/* units in Mbps */
1313 	u32 tx_throughput;
1314 	u32 rx_throughput;
1315 	u32 tx_throughput_raw;
1316 	u32 rx_throughput_raw;
1317 
1318 	u32 rx_tf_acc;
1319 	u32 rx_tf_periodic;
1320 
1321 	enum rtw89_tfc_lv tx_tfc_lv;
1322 	enum rtw89_tfc_lv rx_tfc_lv;
1323 	struct ewma_tp tx_ewma_tp;
1324 	struct ewma_tp rx_ewma_tp;
1325 
1326 	u16 tx_rate;
1327 	u16 rx_rate;
1328 };
1329 
1330 struct rtw89_btc_statistic {
1331 	u8 rssi; /* 0%~110% (dBm = rssi -110) */
1332 	struct rtw89_traffic_stats traffic;
1333 };
1334 
1335 #define BTC_WL_RSSI_THMAX 4
1336 
1337 struct rtw89_btc_wl_link_info {
1338 	struct rtw89_btc_statistic stat;
1339 	enum rtw89_tfc_dir dir;
1340 	u8 rssi_state[BTC_WL_RSSI_THMAX];
1341 	u8 mac_addr[ETH_ALEN];
1342 	u8 busy;
1343 	u8 ch;
1344 	u8 bw;
1345 	u8 band;
1346 	u8 role;
1347 	u8 pid;
1348 	u8 phy;
1349 	u8 dtim_period;
1350 	u8 mode;
1351 
1352 	u8 mac_id;
1353 	u8 tx_retry;
1354 
1355 	u32 bcn_period;
1356 	u32 busy_t;
1357 	u32 tx_time;
1358 	u32 client_cnt;
1359 	u32 rx_rate_drop_cnt;
1360 
1361 	u32 active: 1;
1362 	u32 noa: 1;
1363 	u32 client_ps: 1;
1364 	u32 connected: 2;
1365 };
1366 
1367 union rtw89_btc_wl_state_map {
1368 	u32 val;
1369 	struct rtw89_btc_wl_smap map;
1370 };
1371 
1372 struct rtw89_btc_bt_hfp_desc {
1373 	u32 exist: 1;
1374 	u32 type: 2;
1375 	u32 rsvd: 29;
1376 };
1377 
1378 struct rtw89_btc_bt_hid_desc {
1379 	u32 exist: 1;
1380 	u32 slot_info: 2;
1381 	u32 pair_cnt: 2;
1382 	u32 type: 8;
1383 	u32 rsvd: 19;
1384 };
1385 
1386 struct rtw89_btc_bt_a2dp_desc {
1387 	u8 exist: 1;
1388 	u8 exist_last: 1;
1389 	u8 play_latency: 1;
1390 	u8 type: 3;
1391 	u8 active: 1;
1392 	u8 sink: 1;
1393 
1394 	u8 bitpool;
1395 	u16 vendor_id;
1396 	u32 device_name;
1397 	u32 flush_time;
1398 };
1399 
1400 struct rtw89_btc_bt_pan_desc {
1401 	u32 exist: 1;
1402 	u32 type: 1;
1403 	u32 active: 1;
1404 	u32 rsvd: 29;
1405 };
1406 
1407 struct rtw89_btc_bt_rfk_info {
1408 	u32 run: 1;
1409 	u32 req: 1;
1410 	u32 timeout: 1;
1411 	u32 rsvd: 29;
1412 };
1413 
1414 union rtw89_btc_bt_rfk_info_map {
1415 	u32 val;
1416 	struct rtw89_btc_bt_rfk_info map;
1417 };
1418 
1419 struct rtw89_btc_bt_ver_info {
1420 	u32 fw_coex; /* match with which coex_ver */
1421 	u32 fw;
1422 };
1423 
1424 struct rtw89_btc_bool_sta_chg {
1425 	u32 now: 1;
1426 	u32 last: 1;
1427 	u32 remain: 1;
1428 	u32 srvd: 29;
1429 };
1430 
1431 struct rtw89_btc_u8_sta_chg {
1432 	u8 now;
1433 	u8 last;
1434 	u8 remain;
1435 	u8 rsvd;
1436 };
1437 
1438 struct rtw89_btc_wl_scan_info {
1439 	u8 band[RTW89_PHY_MAX];
1440 	u8 phy_map;
1441 	u8 rsvd;
1442 };
1443 
1444 struct rtw89_btc_wl_dbcc_info {
1445 	u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */
1446 	u8 scan_band[RTW89_PHY_MAX]; /* scan band in  each phy */
1447 	u8 real_band[RTW89_PHY_MAX];
1448 	u8 role[RTW89_PHY_MAX]; /* role in each phy */
1449 };
1450 
1451 struct rtw89_btc_wl_active_role {
1452 	u8 connected: 1;
1453 	u8 pid: 3;
1454 	u8 phy: 1;
1455 	u8 noa: 1;
1456 	u8 band: 2;
1457 
1458 	u8 client_ps: 1;
1459 	u8 bw: 7;
1460 
1461 	u8 role;
1462 	u8 ch;
1463 
1464 	u16 tx_lvl;
1465 	u16 rx_lvl;
1466 	u16 tx_rate;
1467 	u16 rx_rate;
1468 };
1469 
1470 struct rtw89_btc_wl_active_role_v1 {
1471 	u8 connected: 1;
1472 	u8 pid: 3;
1473 	u8 phy: 1;
1474 	u8 noa: 1;
1475 	u8 band: 2;
1476 
1477 	u8 client_ps: 1;
1478 	u8 bw: 7;
1479 
1480 	u8 role;
1481 	u8 ch;
1482 
1483 	u16 tx_lvl;
1484 	u16 rx_lvl;
1485 	u16 tx_rate;
1486 	u16 rx_rate;
1487 
1488 	u32 noa_duration; /* ms */
1489 };
1490 
1491 struct rtw89_btc_wl_active_role_v2 {
1492 	u8 connected: 1;
1493 	u8 pid: 3;
1494 	u8 phy: 1;
1495 	u8 noa: 1;
1496 	u8 band: 2;
1497 
1498 	u8 client_ps: 1;
1499 	u8 bw: 7;
1500 
1501 	u8 role;
1502 	u8 ch;
1503 
1504 	u32 noa_duration; /* ms */
1505 };
1506 
1507 struct rtw89_btc_wl_role_info_bpos {
1508 	u16 none: 1;
1509 	u16 station: 1;
1510 	u16 ap: 1;
1511 	u16 vap: 1;
1512 	u16 adhoc: 1;
1513 	u16 adhoc_master: 1;
1514 	u16 mesh: 1;
1515 	u16 moniter: 1;
1516 	u16 p2p_device: 1;
1517 	u16 p2p_gc: 1;
1518 	u16 p2p_go: 1;
1519 	u16 nan: 1;
1520 };
1521 
1522 struct rtw89_btc_wl_scc_ctrl {
1523 	u8 null_role1;
1524 	u8 null_role2;
1525 	u8 ebt_null; /* if tx null at EBT slot */
1526 };
1527 
1528 union rtw89_btc_wl_role_info_map {
1529 	u16 val;
1530 	struct rtw89_btc_wl_role_info_bpos role;
1531 };
1532 
1533 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */
1534 	u8 connect_cnt;
1535 	u8 link_mode;
1536 	union rtw89_btc_wl_role_info_map role_map;
1537 	struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM];
1538 };
1539 
1540 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */
1541 	u8 connect_cnt;
1542 	u8 link_mode;
1543 	union rtw89_btc_wl_role_info_map role_map;
1544 	struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM];
1545 	u32 mrole_type; /* btc_wl_mrole_type */
1546 	u32 mrole_noa_duration; /* ms */
1547 
1548 	u32 dbcc_en: 1;
1549 	u32 dbcc_chg: 1;
1550 	u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1551 	u32 link_mode_chg: 1;
1552 	u32 rsvd: 27;
1553 };
1554 
1555 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */
1556 	u8 connect_cnt;
1557 	u8 link_mode;
1558 	union rtw89_btc_wl_role_info_map role_map;
1559 	struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM];
1560 	u32 mrole_type; /* btc_wl_mrole_type */
1561 	u32 mrole_noa_duration; /* ms */
1562 
1563 	u32 dbcc_en: 1;
1564 	u32 dbcc_chg: 1;
1565 	u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */
1566 	u32 link_mode_chg: 1;
1567 	u32 rsvd: 27;
1568 };
1569 
1570 struct rtw89_btc_wl_ver_info {
1571 	u32 fw_coex; /* match with which coex_ver */
1572 	u32 fw;
1573 	u32 mac;
1574 	u32 bb;
1575 	u32 rf;
1576 };
1577 
1578 struct rtw89_btc_wl_afh_info {
1579 	u8 en;
1580 	u8 ch;
1581 	u8 bw;
1582 	u8 rsvd;
1583 } __packed;
1584 
1585 struct rtw89_btc_wl_rfk_info {
1586 	u32 state: 2;
1587 	u32 path_map: 4;
1588 	u32 phy_map: 2;
1589 	u32 band: 2;
1590 	u32 type: 8;
1591 	u32 rsvd: 14;
1592 };
1593 
1594 struct rtw89_btc_bt_smap {
1595 	u32 connect: 1;
1596 	u32 ble_connect: 1;
1597 	u32 acl_busy: 1;
1598 	u32 sco_busy: 1;
1599 	u32 mesh_busy: 1;
1600 	u32 inq_pag: 1;
1601 };
1602 
1603 union rtw89_btc_bt_state_map {
1604 	u32 val;
1605 	struct rtw89_btc_bt_smap map;
1606 };
1607 
1608 #define BTC_BT_RSSI_THMAX 4
1609 #define BTC_BT_AFH_GROUP 12
1610 #define BTC_BT_AFH_LE_GROUP 5
1611 
1612 struct rtw89_btc_bt_link_info {
1613 	struct rtw89_btc_u8_sta_chg profile_cnt;
1614 	struct rtw89_btc_bool_sta_chg multi_link;
1615 	struct rtw89_btc_bool_sta_chg relink;
1616 	struct rtw89_btc_bt_hfp_desc hfp_desc;
1617 	struct rtw89_btc_bt_hid_desc hid_desc;
1618 	struct rtw89_btc_bt_a2dp_desc a2dp_desc;
1619 	struct rtw89_btc_bt_pan_desc pan_desc;
1620 	union rtw89_btc_bt_state_map status;
1621 
1622 	u8 sut_pwr_level[BTC_PROFILE_MAX];
1623 	u8 golden_rx_shift[BTC_PROFILE_MAX];
1624 	u8 rssi_state[BTC_BT_RSSI_THMAX];
1625 	u8 afh_map[BTC_BT_AFH_GROUP];
1626 	u8 afh_map_le[BTC_BT_AFH_LE_GROUP];
1627 
1628 	u32 role_sw: 1;
1629 	u32 slave_role: 1;
1630 	u32 afh_update: 1;
1631 	u32 cqddr: 1;
1632 	u32 rssi: 8;
1633 	u32 tx_3m: 1;
1634 	u32 rsvd: 19;
1635 };
1636 
1637 struct rtw89_btc_3rdcx_info {
1638 	u8 type;   /* 0: none, 1:zigbee, 2:LTE  */
1639 	u8 hw_coex;
1640 	u16 rsvd;
1641 };
1642 
1643 struct rtw89_btc_dm_emap {
1644 	u32 init: 1;
1645 	u32 pta_owner: 1;
1646 	u32 wl_rfk_timeout: 1;
1647 	u32 bt_rfk_timeout: 1;
1648 	u32 wl_fw_hang: 1;
1649 	u32 cycle_hang: 1;
1650 	u32 w1_hang: 1;
1651 	u32 b1_hang: 1;
1652 	u32 tdma_no_sync: 1;
1653 	u32 slot_no_sync: 1;
1654 	u32 wl_slot_drift: 1;
1655 	u32 bt_slot_drift: 1;
1656 	u32 role_num_mismatch: 1;
1657 	u32 null1_tx_late: 1;
1658 	u32 bt_afh_conflict: 1;
1659 	u32 bt_leafh_conflict: 1;
1660 	u32 bt_slot_flood: 1;
1661 	u32 wl_e2g_hang: 1;
1662 	u32 wl_ver_mismatch: 1;
1663 	u32 bt_ver_mismatch: 1;
1664 };
1665 
1666 union rtw89_btc_dm_error_map {
1667 	u32 val;
1668 	struct rtw89_btc_dm_emap map;
1669 };
1670 
1671 struct rtw89_btc_rf_para {
1672 	u32 tx_pwr_freerun;
1673 	u32 rx_gain_freerun;
1674 	u32 tx_pwr_perpkt;
1675 	u32 rx_gain_perpkt;
1676 };
1677 
1678 struct rtw89_btc_wl_nhm {
1679 	u8 instant_wl_nhm_dbm;
1680 	u8 instant_wl_nhm_per_mhz;
1681 	u16 valid_record_times;
1682 	s8 record_pwr[16];
1683 	u8 record_ratio[16];
1684 	s8 pwr; /* dbm_per_MHz  */
1685 	u8 ratio;
1686 	u8 current_status;
1687 	u8 refresh;
1688 	bool start_flag;
1689 	s8 pwr_max;
1690 	s8 pwr_min;
1691 };
1692 
1693 struct rtw89_btc_wl_info {
1694 	struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM];
1695 	struct rtw89_btc_wl_rfk_info rfk_info;
1696 	struct rtw89_btc_wl_ver_info  ver_info;
1697 	struct rtw89_btc_wl_afh_info afh_info;
1698 	struct rtw89_btc_wl_role_info role_info;
1699 	struct rtw89_btc_wl_role_info_v1 role_info_v1;
1700 	struct rtw89_btc_wl_role_info_v2 role_info_v2;
1701 	struct rtw89_btc_wl_scan_info scan_info;
1702 	struct rtw89_btc_wl_dbcc_info dbcc_info;
1703 	struct rtw89_btc_rf_para rf_para;
1704 	struct rtw89_btc_wl_nhm nhm;
1705 	union rtw89_btc_wl_state_map status;
1706 
1707 	u8 port_id[RTW89_WIFI_ROLE_MLME_MAX];
1708 	u8 rssi_level;
1709 	u8 cn_report;
1710 	u8 coex_mode;
1711 
1712 	bool scbd_change;
1713 	u32 scbd;
1714 };
1715 
1716 struct rtw89_btc_module {
1717 	struct rtw89_btc_ant_info ant;
1718 	u8 rfe_type;
1719 	u8 cv;
1720 
1721 	u8 bt_solo: 1;
1722 	u8 bt_pos: 1;
1723 	u8 switch_type: 1;
1724 	u8 wa_type: 3;
1725 
1726 	u8 kt_ver_adie;
1727 };
1728 
1729 #define RTW89_BTC_DM_MAXSTEP 30
1730 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8)
1731 
1732 struct rtw89_btc_dm_step {
1733 	u16 step[RTW89_BTC_DM_MAXSTEP];
1734 	u8 step_pos;
1735 	bool step_ov;
1736 };
1737 
1738 struct rtw89_btc_init_info {
1739 	struct rtw89_btc_module module;
1740 	u8 wl_guard_ch;
1741 
1742 	u8 wl_only: 1;
1743 	u8 wl_init_ok: 1;
1744 	u8 dbcc_en: 1;
1745 	u8 cx_other: 1;
1746 	u8 bt_only: 1;
1747 
1748 	u16 rsvd;
1749 };
1750 
1751 struct rtw89_btc_wl_tx_limit_para {
1752 	u16 enable;
1753 	u32 tx_time;	/* unit: us */
1754 	u16 tx_retry;
1755 };
1756 
1757 enum rtw89_btc_bt_scan_type {
1758 	BTC_SCAN_INQ	= 0,
1759 	BTC_SCAN_PAGE,
1760 	BTC_SCAN_BLE,
1761 	BTC_SCAN_INIT,
1762 	BTC_SCAN_TV,
1763 	BTC_SCAN_ADV,
1764 	BTC_SCAN_MAX1,
1765 };
1766 
1767 enum rtw89_btc_ble_scan_type {
1768 	CXSCAN_BG = 0,
1769 	CXSCAN_INIT,
1770 	CXSCAN_LE,
1771 	CXSCAN_MAX
1772 };
1773 
1774 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0)
1775 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1)
1776 
1777 struct rtw89_btc_bt_scan_info_v1 {
1778 	__le16 win;
1779 	__le16 intvl;
1780 	__le32 flags;
1781 } __packed;
1782 
1783 struct rtw89_btc_bt_scan_info_v2 {
1784 	__le16 win;
1785 	__le16 intvl;
1786 } __packed;
1787 
1788 struct rtw89_btc_fbtc_btscan_v1 {
1789 	u8 fver; /* btc_ver::fcxbtscan */
1790 	u8 rsvd;
1791 	__le16 rsvd2;
1792 	struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1];
1793 } __packed;
1794 
1795 struct rtw89_btc_fbtc_btscan_v2 {
1796 	u8 fver; /* btc_ver::fcxbtscan */
1797 	u8 type;
1798 	__le16 rsvd2;
1799 	struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX];
1800 } __packed;
1801 
1802 union rtw89_btc_fbtc_btscan {
1803 	struct rtw89_btc_fbtc_btscan_v1 v1;
1804 	struct rtw89_btc_fbtc_btscan_v2 v2;
1805 };
1806 
1807 struct rtw89_btc_bt_info {
1808 	struct rtw89_btc_bt_link_info link_info;
1809 	struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1];
1810 	struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX];
1811 	struct rtw89_btc_bt_ver_info ver_info;
1812 	struct rtw89_btc_bool_sta_chg enable;
1813 	struct rtw89_btc_bool_sta_chg inq_pag;
1814 	struct rtw89_btc_rf_para rf_para;
1815 	union rtw89_btc_bt_rfk_info_map rfk_info;
1816 
1817 	u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */
1818 	u8 rssi_level;
1819 
1820 	u32 scbd;
1821 	u32 feature;
1822 
1823 	u32 mbx_avl: 1;
1824 	u32 whql_test: 1;
1825 	u32 igno_wl: 1;
1826 	u32 reinit: 1;
1827 	u32 ble_scan_en: 1;
1828 	u32 btg_type: 1;
1829 	u32 inq: 1;
1830 	u32 pag: 1;
1831 	u32 run_patch_code: 1;
1832 	u32 hi_lna_rx: 1;
1833 	u32 scan_rx_low_pri: 1;
1834 	u32 scan_info_update: 1;
1835 	u32 lna_constrain: 3;
1836 	u32 rsvd: 17;
1837 };
1838 
1839 struct rtw89_btc_cx {
1840 	struct rtw89_btc_wl_info wl;
1841 	struct rtw89_btc_bt_info bt;
1842 	struct rtw89_btc_3rdcx_info other;
1843 	u32 state_map;
1844 	u32 cnt_bt[BTC_BCNT_NUM];
1845 	u32 cnt_wl[BTC_WCNT_NUM];
1846 };
1847 
1848 struct rtw89_btc_fbtc_tdma {
1849 	u8 type; /* btc_ver::fcxtdma */
1850 	u8 rxflctrl;
1851 	u8 txpause;
1852 	u8 wtgle_n;
1853 	u8 leak_n;
1854 	u8 ext_ctrl;
1855 	u8 rxflctrl_role;
1856 	u8 option_ctrl;
1857 } __packed;
1858 
1859 struct rtw89_btc_fbtc_tdma_v3 {
1860 	u8 fver; /* btc_ver::fcxtdma */
1861 	u8 rsvd;
1862 	__le16 rsvd1;
1863 	struct rtw89_btc_fbtc_tdma tdma;
1864 } __packed;
1865 
1866 union rtw89_btc_fbtc_tdma_le32 {
1867 	struct rtw89_btc_fbtc_tdma v1;
1868 	struct rtw89_btc_fbtc_tdma_v3 v3;
1869 };
1870 
1871 #define CXMREG_MAX 30
1872 #define CXMREG_MAX_V2 20
1873 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/
1874 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */
1875 
1876 enum rtw89_btc_bt_sta_counter {
1877 	BTC_BCNT_RFK_REQ = 0,
1878 	BTC_BCNT_RFK_GO = 1,
1879 	BTC_BCNT_RFK_REJECT = 2,
1880 	BTC_BCNT_RFK_FAIL = 3,
1881 	BTC_BCNT_RFK_TIMEOUT = 4,
1882 	BTC_BCNT_HI_TX = 5,
1883 	BTC_BCNT_HI_RX = 6,
1884 	BTC_BCNT_LO_TX = 7,
1885 	BTC_BCNT_LO_RX = 8,
1886 	BTC_BCNT_POLLUTED = 9,
1887 	BTC_BCNT_STA_MAX
1888 };
1889 
1890 enum rtw89_btc_bt_sta_counter_v105 {
1891 	BTC_BCNT_RFK_REQ_V105 = 0,
1892 	BTC_BCNT_HI_TX_V105 = 1,
1893 	BTC_BCNT_HI_RX_V105 = 2,
1894 	BTC_BCNT_LO_TX_V105 = 3,
1895 	BTC_BCNT_LO_RX_V105 = 4,
1896 	BTC_BCNT_POLLUTED_V105 = 5,
1897 	BTC_BCNT_STA_MAX_V105
1898 };
1899 
1900 struct rtw89_btc_fbtc_rpt_ctrl_v1 {
1901 	u16 fver; /* btc_ver::fcxbtcrpt */
1902 	u16 rpt_cnt; /* tmr counters */
1903 	u32 wl_fw_coex_ver; /* match which driver's coex version */
1904 	u32 wl_fw_cx_offload;
1905 	u32 wl_fw_ver;
1906 	u32 rpt_enable;
1907 	u32 rpt_para; /* ms */
1908 	u32 mb_send_fail_cnt; /* fw send mailbox fail counter */
1909 	u32 mb_send_ok_cnt; /* fw send mailbox ok counter */
1910 	u32 mb_recv_cnt; /* fw recv mailbox counter */
1911 	u32 mb_a2dp_empty_cnt; /* a2dp empty count */
1912 	u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */
1913 	u32 mb_a2dp_full_cnt; /* a2dp empty full counter */
1914 	u32 bt_rfk_cnt[BTC_BCNT_HI_TX];
1915 	u32 c2h_cnt; /* fw send c2h counter  */
1916 	u32 h2c_cnt; /* fw recv h2c counter */
1917 } __packed;
1918 
1919 struct rtw89_btc_fbtc_rpt_ctrl_info {
1920 	__le32 cnt; /* fw report counter */
1921 	__le32 en; /* report map */
1922 	__le32 para; /* not used */
1923 
1924 	__le32 cnt_c2h; /* fw send c2h counter  */
1925 	__le32 cnt_h2c; /* fw recv h2c counter */
1926 	__le32 len_c2h; /* The total length of the last C2H  */
1927 
1928 	__le32 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
1929 	__le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1930 } __packed;
1931 
1932 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 {
1933 	__le32 cx_ver; /* match which driver's coex version */
1934 	__le32 fw_ver;
1935 	__le32 en; /* report map */
1936 
1937 	__le16 cnt; /* fw report counter */
1938 	__le16 cnt_c2h; /* fw send c2h counter  */
1939 	__le16 cnt_h2c; /* fw recv h2c counter */
1940 	__le16 len_c2h; /* The total length of the last C2H  */
1941 
1942 	__le16 cnt_aoac_rf_on;  /* rf-on counter for aoac switch notify */
1943 	__le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */
1944 } __packed;
1945 
1946 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info {
1947 	__le32 cx_ver; /* match which driver's coex version */
1948 	__le32 cx_offload;
1949 	__le32 fw_ver;
1950 } __packed;
1951 
1952 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty {
1953 	__le32 cnt_empty; /* a2dp empty count */
1954 	__le32 cnt_flowctrl; /* a2dp empty flow control counter */
1955 	__le32 cnt_tx;
1956 	__le32 cnt_ack;
1957 	__le32 cnt_nack;
1958 } __packed;
1959 
1960 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox {
1961 	__le32 cnt_send_ok; /* fw send mailbox ok counter */
1962 	__le32 cnt_send_fail; /* fw send mailbox fail counter */
1963 	__le32 cnt_recv; /* fw recv mailbox counter */
1964 	struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp;
1965 } __packed;
1966 
1967 struct rtw89_btc_fbtc_rpt_ctrl_v4 {
1968 	u8 fver;
1969 	u8 rsvd;
1970 	__le16 rsvd1;
1971 	struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info;
1972 	struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info;
1973 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1974 	__le32 bt_cnt[BTC_BCNT_STA_MAX];
1975 	struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX];
1976 } __packed;
1977 
1978 struct rtw89_btc_fbtc_rpt_ctrl_v5 {
1979 	u8 fver;
1980 	u8 rsvd;
1981 	__le16 rsvd1;
1982 
1983 	u8 gnt_val[RTW89_PHY_MAX][4];
1984 	__le16 bt_cnt[BTC_BCNT_STA_MAX];
1985 
1986 	struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1987 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
1988 } __packed;
1989 
1990 struct rtw89_btc_fbtc_rpt_ctrl_v105 {
1991 	u8 fver;
1992 	u8 rsvd;
1993 	__le16 rsvd1;
1994 
1995 	u8 gnt_val[RTW89_PHY_MAX][4];
1996 	__le16 bt_cnt[BTC_BCNT_STA_MAX_V105];
1997 
1998 	struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info;
1999 	struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info;
2000 } __packed;
2001 
2002 union rtw89_btc_fbtc_rpt_ctrl_ver_info {
2003 	struct rtw89_btc_fbtc_rpt_ctrl_v1 v1;
2004 	struct rtw89_btc_fbtc_rpt_ctrl_v4 v4;
2005 	struct rtw89_btc_fbtc_rpt_ctrl_v5 v5;
2006 	struct rtw89_btc_fbtc_rpt_ctrl_v105 v105;
2007 };
2008 
2009 enum rtw89_fbtc_ext_ctrl_type {
2010 	CXECTL_OFF = 0x0, /* tdma off */
2011 	CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */
2012 	CXECTL_EXT = 0x2,
2013 	CXECTL_MAX
2014 };
2015 
2016 union rtw89_btc_fbtc_rxflct {
2017 	u8 val;
2018 	u8 type: 3;
2019 	u8 tgln_n: 5;
2020 };
2021 
2022 enum rtw89_btc_cxst_state {
2023 	CXST_OFF = 0x0,
2024 	CXST_B2W = 0x1,
2025 	CXST_W1 = 0x2,
2026 	CXST_W2 = 0x3,
2027 	CXST_W2B = 0x4,
2028 	CXST_B1 = 0x5,
2029 	CXST_B2 = 0x6,
2030 	CXST_B3 = 0x7,
2031 	CXST_B4 = 0x8,
2032 	CXST_LK = 0x9,
2033 	CXST_BLK = 0xa,
2034 	CXST_E2G = 0xb,
2035 	CXST_E5G = 0xc,
2036 	CXST_EBT = 0xd,
2037 	CXST_ENULL = 0xe,
2038 	CXST_WLK = 0xf,
2039 	CXST_W1FDD = 0x10,
2040 	CXST_B1FDD = 0x11,
2041 	CXST_MAX = 0x12,
2042 };
2043 
2044 enum rtw89_btc_cxevnt {
2045 	CXEVNT_TDMA_ENTRY = 0x0,
2046 	CXEVNT_WL_TMR,
2047 	CXEVNT_B1_TMR,
2048 	CXEVNT_B2_TMR,
2049 	CXEVNT_B3_TMR,
2050 	CXEVNT_B4_TMR,
2051 	CXEVNT_W2B_TMR,
2052 	CXEVNT_B2W_TMR,
2053 	CXEVNT_BCN_EARLY,
2054 	CXEVNT_A2DP_EMPTY,
2055 	CXEVNT_LK_END,
2056 	CXEVNT_RX_ISR,
2057 	CXEVNT_RX_FC0,
2058 	CXEVNT_RX_FC1,
2059 	CXEVNT_BT_RELINK,
2060 	CXEVNT_BT_RETRY,
2061 	CXEVNT_E2G,
2062 	CXEVNT_E5G,
2063 	CXEVNT_EBT,
2064 	CXEVNT_ENULL,
2065 	CXEVNT_DRV_WLK,
2066 	CXEVNT_BCN_OK,
2067 	CXEVNT_BT_CHANGE,
2068 	CXEVNT_EBT_EXTEND,
2069 	CXEVNT_E2G_NULL1,
2070 	CXEVNT_B1FDD_TMR,
2071 	CXEVNT_MAX
2072 };
2073 
2074 enum {
2075 	CXBCN_ALL = 0x0,
2076 	CXBCN_ALL_OK,
2077 	CXBCN_BT_SLOT,
2078 	CXBCN_BT_OK,
2079 	CXBCN_MAX
2080 };
2081 
2082 enum btc_slot_type {
2083 	SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */
2084 	SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/
2085 	CXSTYPE_NUM,
2086 };
2087 
2088 enum { /* TIME */
2089 	CXT_BT = 0x0,
2090 	CXT_WL = 0x1,
2091 	CXT_MAX
2092 };
2093 
2094 enum { /* TIME-A2DP */
2095 	CXT_FLCTRL_OFF = 0x0,
2096 	CXT_FLCTRL_ON = 0x1,
2097 	CXT_FLCTRL_MAX
2098 };
2099 
2100 enum { /* STEP TYPE */
2101 	CXSTEP_NONE = 0x0,
2102 	CXSTEP_EVNT = 0x1,
2103 	CXSTEP_SLOT = 0x2,
2104 	CXSTEP_MAX,
2105 };
2106 
2107 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */
2108 	RPT_BT_AFH_SEQ_LEGACY = 0x10,
2109 	RPT_BT_AFH_SEQ_LE = 0x20
2110 };
2111 
2112 #define BTC_DBG_MAX1  32
2113 struct rtw89_btc_fbtc_gpio_dbg {
2114 	u8 fver; /* btc_ver::fcxgpiodbg */
2115 	u8 rsvd;
2116 	u16 rsvd2;
2117 	u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */
2118 	u32 pre_state; /* the debug signal is 1 or 0  */
2119 	u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */
2120 } __packed;
2121 
2122 struct rtw89_btc_fbtc_mreg_val_v1 {
2123 	u8 fver; /* btc_ver::fcxmreg */
2124 	u8 reg_num;
2125 	__le16 rsvd;
2126 	__le32 mreg_val[CXMREG_MAX];
2127 } __packed;
2128 
2129 struct rtw89_btc_fbtc_mreg_val_v2 {
2130 	u8 fver; /* btc_ver::fcxmreg */
2131 	u8 reg_num;
2132 	__le16 rsvd;
2133 	__le32 mreg_val[CXMREG_MAX_V2];
2134 } __packed;
2135 
2136 union rtw89_btc_fbtc_mreg_val {
2137 	struct rtw89_btc_fbtc_mreg_val_v1 v1;
2138 	struct rtw89_btc_fbtc_mreg_val_v2 v2;
2139 };
2140 
2141 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \
2142 	{ .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \
2143 	  .offset = cpu_to_le32(__offset), }
2144 
2145 struct rtw89_btc_fbtc_mreg {
2146 	__le16 type;
2147 	__le16 bytes;
2148 	__le32 offset;
2149 } __packed;
2150 
2151 struct rtw89_btc_fbtc_slot {
2152 	__le16 dur;
2153 	__le32 cxtbl;
2154 	__le16 cxtype;
2155 } __packed;
2156 
2157 struct rtw89_btc_fbtc_slots {
2158 	u8 fver; /* btc_ver::fcxslots */
2159 	u8 tbl_num;
2160 	__le16 rsvd;
2161 	__le32 update_map;
2162 	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2163 } __packed;
2164 
2165 struct rtw89_btc_fbtc_step {
2166 	u8 type;
2167 	u8 val;
2168 	__le16 difft;
2169 } __packed;
2170 
2171 struct rtw89_btc_fbtc_steps_v2 {
2172 	u8 fver; /* btc_ver::fcxstep */
2173 	u8 rsvd;
2174 	__le16 cnt;
2175 	__le16 pos_old;
2176 	__le16 pos_new;
2177 	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2178 } __packed;
2179 
2180 struct rtw89_btc_fbtc_steps_v3 {
2181 	u8 fver;
2182 	u8 en;
2183 	__le16 rsvd;
2184 	__le32 cnt;
2185 	struct rtw89_btc_fbtc_step step[FCXMAX_STEP];
2186 } __packed;
2187 
2188 union rtw89_btc_fbtc_steps_info {
2189 	struct rtw89_btc_fbtc_steps_v2 v2;
2190 	struct rtw89_btc_fbtc_steps_v3 v3;
2191 };
2192 
2193 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */
2194 	u8 fver; /* btc_ver::fcxcysta */
2195 	u8 rsvd;
2196 	__le16 cycles; /* total cycle number */
2197 	__le16 cycles_a2dp[CXT_FLCTRL_MAX];
2198 	__le16 a2dpept; /* a2dp empty cnt */
2199 	__le16 a2dpeptto; /* a2dp empty timeout cnt*/
2200 	__le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */
2201 	__le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */
2202 	__le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2203 	__le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */
2204 	__le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */
2205 	__le16 tavg_a2dpept; /* avg a2dp empty time */
2206 	__le16 tmax_a2dpept; /* max a2dp empty time */
2207 	__le16 tavg_lk; /* avg leak-slot time */
2208 	__le16 tmax_lk; /* max leak-slot time */
2209 	__le32 slot_cnt[CXST_MAX]; /* slot count */
2210 	__le32 bcn_cnt[CXBCN_MAX];
2211 	__le32 leakrx_cnt; /* the rximr occur at leak slot  */
2212 	__le32 collision_cnt; /* counter for event/timer occur at same time */
2213 	__le32 skip_cnt;
2214 	__le32 exception;
2215 	__le32 except_cnt;
2216 	__le16 tslot_cycle[BTC_CYCLE_SLOT_MAX];
2217 } __packed;
2218 
2219 struct rtw89_btc_fbtc_fdd_try_info {
2220 	__le16 cycles[CXT_FLCTRL_MAX];
2221 	__le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */
2222 	__le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */
2223 } __packed;
2224 
2225 struct rtw89_btc_fbtc_cycle_time_info {
2226 	__le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2227 	__le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2228 	__le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */
2229 } __packed;
2230 
2231 struct rtw89_btc_fbtc_cycle_time_info_v5 {
2232 	__le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */
2233 	__le16 tmax[CXT_MAX]; /* max wl/bt cycle time */
2234 } __packed;
2235 
2236 struct rtw89_btc_fbtc_a2dp_trx_stat {
2237 	u8 empty_cnt;
2238 	u8 retry_cnt;
2239 	u8 tx_rate;
2240 	u8 tx_cnt;
2241 	u8 ack_cnt;
2242 	u8 nack_cnt;
2243 	u8 rsvd1;
2244 	u8 rsvd2;
2245 } __packed;
2246 
2247 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 {
2248 	u8 empty_cnt;
2249 	u8 retry_cnt;
2250 	u8 tx_rate;
2251 	u8 tx_cnt;
2252 	u8 ack_cnt;
2253 	u8 nack_cnt;
2254 	u8 no_empty_cnt;
2255 	u8 rsvd;
2256 } __packed;
2257 
2258 struct rtw89_btc_fbtc_cycle_a2dp_empty_info {
2259 	__le16 cnt; /* a2dp empty cnt */
2260 	__le16 cnt_timeout; /* a2dp empty timeout cnt*/
2261 	__le16 tavg; /* avg a2dp empty time */
2262 	__le16 tmax; /* max a2dp empty time */
2263 } __packed;
2264 
2265 struct rtw89_btc_fbtc_cycle_leak_info {
2266 	__le32 cnt_rximr; /* the rximr occur at leak slot  */
2267 	__le16 tavg; /* avg leak-slot time */
2268 	__le16 tmax; /* max leak-slot time */
2269 } __packed;
2270 
2271 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0)
2272 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10)
2273 
2274 struct rtw89_btc_fbtc_cycle_fddt_info {
2275 	__le16 train_cycle;
2276 	__le16 tp;
2277 
2278 	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2279 	s8 bt_tx_power; /* decrease Tx power (dB) */
2280 	s8 bt_rx_gain;  /* LNA constrain level */
2281 	u8 no_empty_cnt;
2282 
2283 	u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2284 	u8 cn; /* condition_num */
2285 	u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2286 	u8 train_result; /* refer to enum btc_fddt_check_map */
2287 } __packed;
2288 
2289 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0)
2290 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4)
2291 
2292 struct rtw89_btc_fbtc_cycle_fddt_info_v5 {
2293 	__le16 train_cycle;
2294 	__le16 tp;
2295 
2296 	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2297 	s8 bt_tx_power; /* decrease Tx power (dB) */
2298 	s8 bt_rx_gain;  /* LNA constrain level */
2299 	u8 no_empty_cnt;
2300 
2301 	u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */
2302 	u8 cn; /* condition_num */
2303 	u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */
2304 	u8 train_result; /* refer to enum btc_fddt_check_map */
2305 } __packed;
2306 
2307 struct rtw89_btc_fbtc_fddt_cell_status {
2308 	s8 wl_tx_pwr;
2309 	s8 bt_tx_pwr;
2310 	s8 bt_rx_gain;
2311 	u8 state_phase; /* [0:3] train state, [4:7] train phase */
2312 } __packed;
2313 
2314 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */
2315 	u8 fver;
2316 	u8 rsvd;
2317 	__le16 cycles; /* total cycle number */
2318 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX];
2319 	struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2320 	struct rtw89_btc_fbtc_fdd_try_info fdd_try;
2321 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2322 	struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX];
2323 	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2324 	__le32 slot_cnt[CXST_MAX]; /* slot count */
2325 	__le32 bcn_cnt[CXBCN_MAX];
2326 	__le32 collision_cnt; /* counter for event/timer occur at the same time */
2327 	__le32 skip_cnt;
2328 	__le32 except_cnt;
2329 	__le32 except_map;
2330 } __packed;
2331 
2332 #define FDD_TRAIN_WL_DIRECTION 2
2333 #define FDD_TRAIN_WL_RSSI_LEVEL 5
2334 #define FDD_TRAIN_BT_RSSI_LEVEL 5
2335 
2336 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */
2337 	u8 fver;
2338 	u8 rsvd;
2339 	u8 collision_cnt; /* counter for event/timer occur at the same time */
2340 	u8 except_cnt;
2341 
2342 	__le16 skip_cnt;
2343 	__le16 cycles; /* total cycle number */
2344 
2345 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2346 	__le16 slot_cnt[CXST_MAX]; /* slot count */
2347 	__le16 bcn_cnt[CXBCN_MAX];
2348 	struct rtw89_btc_fbtc_cycle_time_info cycle_time;
2349 	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2350 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2351 	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2352 	struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX];
2353 	struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2354 							 [FDD_TRAIN_WL_RSSI_LEVEL]
2355 							 [FDD_TRAIN_BT_RSSI_LEVEL];
2356 	__le32 except_map;
2357 } __packed;
2358 
2359 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */
2360 	u8 fver;
2361 	u8 rsvd;
2362 	u8 collision_cnt; /* counter for event/timer occur at the same time */
2363 	u8 except_cnt;
2364 	u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX];
2365 
2366 	__le16 skip_cnt;
2367 	__le16 cycles; /* total cycle number */
2368 
2369 	__le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */
2370 	__le16 slot_cnt[CXST_MAX]; /* slot count */
2371 	__le16 bcn_cnt[CXBCN_MAX];
2372 	struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time;
2373 	struct rtw89_btc_fbtc_cycle_leak_info leak_slot;
2374 	struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept;
2375 	struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX];
2376 	struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX];
2377 	struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION]
2378 							 [FDD_TRAIN_WL_RSSI_LEVEL]
2379 							 [FDD_TRAIN_BT_RSSI_LEVEL];
2380 	__le32 except_map;
2381 } __packed;
2382 
2383 union rtw89_btc_fbtc_cysta_info {
2384 	struct rtw89_btc_fbtc_cysta_v2 v2;
2385 	struct rtw89_btc_fbtc_cysta_v3 v3;
2386 	struct rtw89_btc_fbtc_cysta_v4 v4;
2387 	struct rtw89_btc_fbtc_cysta_v5 v5;
2388 };
2389 
2390 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */
2391 	u8 fver; /* btc_ver::fcxnullsta */
2392 	u8 rsvd;
2393 	__le16 rsvd2;
2394 	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2395 	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2396 	__le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */
2397 } __packed;
2398 
2399 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */
2400 	u8 fver; /* btc_ver::fcxnullsta */
2401 	u8 rsvd;
2402 	__le16 rsvd2;
2403 	__le32 max_t[2]; /* max_t for 0:null0/1:null1 */
2404 	__le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */
2405 	__le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */
2406 } __packed;
2407 
2408 union rtw89_btc_fbtc_cynullsta_info {
2409 	struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */
2410 	struct rtw89_btc_fbtc_cynullsta_v2 v2;
2411 };
2412 
2413 struct rtw89_btc_fbtc_btver {
2414 	u8 fver; /* btc_ver::fcxbtver */
2415 	u8 rsvd;
2416 	__le16 rsvd2;
2417 	__le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */
2418 	__le32 fw_ver;
2419 	__le32 feature;
2420 } __packed;
2421 
2422 struct rtw89_btc_fbtc_btafh {
2423 	u8 fver; /* btc_ver::fcxbtafh */
2424 	u8 rsvd;
2425 	__le16 rsvd2;
2426 	u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */
2427 	u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */
2428 	u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */
2429 } __packed;
2430 
2431 struct rtw89_btc_fbtc_btafh_v2 {
2432 	u8 fver; /* btc_ver::fcxbtafh */
2433 	u8 rsvd;
2434 	u8 rsvd2;
2435 	u8 map_type;
2436 	u8 afh_l[4];
2437 	u8 afh_m[4];
2438 	u8 afh_h[4];
2439 	u8 afh_le_a[4];
2440 	u8 afh_le_b[4];
2441 } __packed;
2442 
2443 struct rtw89_btc_fbtc_btdevinfo {
2444 	u8 fver; /* btc_ver::fcxbtdevinfo */
2445 	u8 rsvd;
2446 	__le16 vendor_id;
2447 	__le32 dev_name; /* only 24 bits valid */
2448 	__le32 flush_time;
2449 } __packed;
2450 
2451 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0)
2452 struct rtw89_btc_rf_trx_para {
2453 	u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2454 	u32 wl_rx_gain;  /* rx gain table index (TBD.) */
2455 	u8 bt_tx_power; /* decrease Tx power (dB) */
2456 	u8 bt_rx_gain;  /* LNA constrain level */
2457 };
2458 
2459 struct rtw89_btc_trx_info {
2460 	u8 tx_lvl;
2461 	u8 rx_lvl;
2462 	u8 wl_rssi;
2463 	u8 bt_rssi;
2464 
2465 	s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */
2466 	s8 rx_gain;  /* rx gain table index (TBD.) */
2467 	s8 bt_tx_power; /* decrease Tx power (dB) */
2468 	s8 bt_rx_gain;  /* LNA constrain level */
2469 
2470 	u8 cn; /* condition_num */
2471 	s8 nhm;
2472 	u8 bt_profile;
2473 	u8 rsvd2;
2474 
2475 	u16 tx_rate;
2476 	u16 rx_rate;
2477 
2478 	u32 tx_tp;
2479 	u32 rx_tp;
2480 	u32 rx_err_ratio;
2481 };
2482 
2483 struct rtw89_btc_dm {
2484 	struct rtw89_btc_fbtc_slot slot[CXST_MAX];
2485 	struct rtw89_btc_fbtc_slot slot_now[CXST_MAX];
2486 	struct rtw89_btc_fbtc_tdma tdma;
2487 	struct rtw89_btc_fbtc_tdma tdma_now;
2488 	struct rtw89_mac_ax_coex_gnt gnt;
2489 	struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */
2490 	struct rtw89_btc_rf_trx_para rf_trx_para;
2491 	struct rtw89_btc_wl_tx_limit_para wl_tx_limit;
2492 	struct rtw89_btc_dm_step dm_step;
2493 	struct rtw89_btc_wl_scc_ctrl wl_scc;
2494 	struct rtw89_btc_trx_info trx_info;
2495 	union rtw89_btc_dm_error_map error;
2496 	u32 cnt_dm[BTC_DCNT_NUM];
2497 	u32 cnt_notify[BTC_NCNT_NUM];
2498 
2499 	u32 update_slot_map;
2500 	u32 set_ant_path;
2501 
2502 	u32 wl_only: 1;
2503 	u32 wl_fw_cx_offload: 1;
2504 	u32 freerun: 1;
2505 	u32 fddt_train: 1;
2506 	u32 wl_ps_ctrl: 2;
2507 	u32 wl_mimo_ps: 1;
2508 	u32 leak_ap: 1;
2509 	u32 noisy_level: 3;
2510 	u32 coex_info_map: 8;
2511 	u32 bt_only: 1;
2512 	u32 wl_btg_rx: 2;
2513 	u32 trx_para_level: 8;
2514 	u32 wl_stb_chg: 1;
2515 	u32 pta_owner: 1;
2516 
2517 	u32 tdma_instant_excute: 1;
2518 	u32 wl_btg_rx_rb: 2;
2519 
2520 	u16 slot_dur[CXST_MAX];
2521 
2522 	u8 run_reason;
2523 	u8 run_action;
2524 
2525 	u8 wl_pre_agc: 2;
2526 	u8 wl_lna2: 1;
2527 	u8 wl_pre_agc_rb: 2;
2528 };
2529 
2530 struct rtw89_btc_ctrl {
2531 	u32 manual: 1;
2532 	u32 igno_bt: 1;
2533 	u32 always_freerun: 1;
2534 	u32 trace_step: 16;
2535 	u32 rsvd: 12;
2536 };
2537 
2538 struct rtw89_btc_dbg {
2539 	/* cmd "rb" */
2540 	bool rb_done;
2541 	u32 rb_val;
2542 };
2543 
2544 enum rtw89_btc_btf_fw_event {
2545 	BTF_EVNT_RPT = 0,
2546 	BTF_EVNT_BT_INFO = 1,
2547 	BTF_EVNT_BT_SCBD = 2,
2548 	BTF_EVNT_BT_REG = 3,
2549 	BTF_EVNT_CX_RUNINFO = 4,
2550 	BTF_EVNT_BT_PSD = 5,
2551 	BTF_EVNT_BUF_OVERFLOW,
2552 	BTF_EVNT_C2H_LOOPBACK,
2553 	BTF_EVNT_MAX,
2554 };
2555 
2556 enum btf_fw_event_report {
2557 	BTC_RPT_TYPE_CTRL = 0x0,
2558 	BTC_RPT_TYPE_TDMA,
2559 	BTC_RPT_TYPE_SLOT,
2560 	BTC_RPT_TYPE_CYSTA,
2561 	BTC_RPT_TYPE_STEP,
2562 	BTC_RPT_TYPE_NULLSTA,
2563 	BTC_RPT_TYPE_MREG,
2564 	BTC_RPT_TYPE_GPIO_DBG,
2565 	BTC_RPT_TYPE_BT_VER,
2566 	BTC_RPT_TYPE_BT_SCAN,
2567 	BTC_RPT_TYPE_BT_AFH,
2568 	BTC_RPT_TYPE_BT_DEVICE,
2569 	BTC_RPT_TYPE_TEST,
2570 	BTC_RPT_TYPE_MAX = 31
2571 };
2572 
2573 enum rtw_btc_btf_reg_type {
2574 	REG_MAC = 0x0,
2575 	REG_BB = 0x1,
2576 	REG_RF = 0x2,
2577 	REG_BT_RF = 0x3,
2578 	REG_BT_MODEM = 0x4,
2579 	REG_BT_BLUEWIZE = 0x5,
2580 	REG_BT_VENDOR = 0x6,
2581 	REG_BT_LE = 0x7,
2582 	REG_MAX_TYPE,
2583 };
2584 
2585 struct rtw89_btc_rpt_cmn_info {
2586 	u32 rx_cnt;
2587 	u32 rx_len;
2588 	u32 req_len; /* expected rsp len */
2589 	u8 req_fver; /* expected rsp fver */
2590 	u8 rsp_fver; /* fver from fw */
2591 	u8 valid;
2592 } __packed;
2593 
2594 union rtw89_btc_fbtc_btafh_info {
2595 	struct rtw89_btc_fbtc_btafh v1;
2596 	struct rtw89_btc_fbtc_btafh_v2 v2;
2597 };
2598 
2599 struct rtw89_btc_report_ctrl_state {
2600 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2601 	union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo;
2602 };
2603 
2604 struct rtw89_btc_rpt_fbtc_tdma {
2605 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2606 	union rtw89_btc_fbtc_tdma_le32 finfo;
2607 };
2608 
2609 struct rtw89_btc_rpt_fbtc_slots {
2610 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2611 	struct rtw89_btc_fbtc_slots finfo; /* info from fw */
2612 };
2613 
2614 struct rtw89_btc_rpt_fbtc_cysta {
2615 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2616 	union rtw89_btc_fbtc_cysta_info finfo;
2617 };
2618 
2619 struct rtw89_btc_rpt_fbtc_step {
2620 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2621 	union rtw89_btc_fbtc_steps_info finfo; /* info from fw */
2622 };
2623 
2624 struct rtw89_btc_rpt_fbtc_nullsta {
2625 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2626 	union rtw89_btc_fbtc_cynullsta_info finfo;
2627 };
2628 
2629 struct rtw89_btc_rpt_fbtc_mreg {
2630 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2631 	union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */
2632 };
2633 
2634 struct rtw89_btc_rpt_fbtc_gpio_dbg {
2635 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2636 	struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */
2637 };
2638 
2639 struct rtw89_btc_rpt_fbtc_btver {
2640 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2641 	struct rtw89_btc_fbtc_btver finfo; /* info from fw */
2642 };
2643 
2644 struct rtw89_btc_rpt_fbtc_btscan {
2645 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2646 	union rtw89_btc_fbtc_btscan finfo; /* info from fw */
2647 };
2648 
2649 struct rtw89_btc_rpt_fbtc_btafh {
2650 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2651 	union rtw89_btc_fbtc_btafh_info finfo;
2652 };
2653 
2654 struct rtw89_btc_rpt_fbtc_btdev {
2655 	struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */
2656 	struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */
2657 };
2658 
2659 enum rtw89_btc_btfre_type {
2660 	BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */
2661 	BTFRE_UNDEF_TYPE,
2662 	BTFRE_EXCEPTION,
2663 	BTFRE_MAX,
2664 };
2665 
2666 struct rtw89_btc_btf_fwinfo {
2667 	u32 cnt_c2h;
2668 	u32 cnt_h2c;
2669 	u32 cnt_h2c_fail;
2670 	u32 event[BTF_EVNT_MAX];
2671 
2672 	u32 err[BTFRE_MAX];
2673 	u32 len_mismch;
2674 	u32 fver_mismch;
2675 	u32 rpt_en_map;
2676 
2677 	struct rtw89_btc_report_ctrl_state rpt_ctrl;
2678 	struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma;
2679 	struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots;
2680 	struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta;
2681 	struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step;
2682 	struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta;
2683 	struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval;
2684 	struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg;
2685 	struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver;
2686 	struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan;
2687 	struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh;
2688 	struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev;
2689 };
2690 
2691 struct rtw89_btc_ver {
2692 	enum rtw89_core_chip_id chip_id;
2693 	u32 fw_ver_code;
2694 
2695 	u8 fcxbtcrpt;
2696 	u8 fcxtdma;
2697 	u8 fcxslots;
2698 	u8 fcxcysta;
2699 	u8 fcxstep;
2700 	u8 fcxnullsta;
2701 	u8 fcxmreg;
2702 	u8 fcxgpiodbg;
2703 	u8 fcxbtver;
2704 	u8 fcxbtscan;
2705 	u8 fcxbtafh;
2706 	u8 fcxbtdevinfo;
2707 	u8 fwlrole;
2708 	u8 frptmap;
2709 	u8 fcxctrl;
2710 
2711 	u16 info_buf;
2712 	u8 max_role_num;
2713 };
2714 
2715 #define RTW89_BTC_POLICY_MAXLEN 512
2716 
2717 struct rtw89_btc {
2718 	const struct rtw89_btc_ver *ver;
2719 
2720 	struct rtw89_btc_cx cx;
2721 	struct rtw89_btc_dm dm;
2722 	struct rtw89_btc_ctrl ctrl;
2723 	struct rtw89_btc_module mdinfo;
2724 	struct rtw89_btc_btf_fwinfo fwinfo;
2725 	struct rtw89_btc_dbg dbg;
2726 
2727 	struct work_struct eapol_notify_work;
2728 	struct work_struct arp_notify_work;
2729 	struct work_struct dhcp_notify_work;
2730 	struct work_struct icmp_notify_work;
2731 
2732 	u32 bt_req_len;
2733 
2734 	u8 policy[RTW89_BTC_POLICY_MAXLEN];
2735 	u16 policy_len;
2736 	u16 policy_type;
2737 	bool bt_req_en;
2738 	bool update_policy_force;
2739 	bool lps;
2740 };
2741 
2742 enum rtw89_btc_hmsg {
2743 	RTW89_BTC_HMSG_TMR_EN = 0x0,
2744 	RTW89_BTC_HMSG_BT_REG_READBACK = 0x1,
2745 	RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2,
2746 	RTW89_BTC_HMSG_FW_EV = 0x3,
2747 	RTW89_BTC_HMSG_BT_LINK_CHG = 0x4,
2748 	RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5,
2749 
2750 	NUM_OF_RTW89_BTC_HMSG,
2751 };
2752 
2753 enum rtw89_ra_mode {
2754 	RTW89_RA_MODE_CCK = BIT(0),
2755 	RTW89_RA_MODE_OFDM = BIT(1),
2756 	RTW89_RA_MODE_HT = BIT(2),
2757 	RTW89_RA_MODE_VHT = BIT(3),
2758 	RTW89_RA_MODE_HE = BIT(4),
2759 	RTW89_RA_MODE_EHT = BIT(5),
2760 };
2761 
2762 enum rtw89_ra_report_mode {
2763 	RTW89_RA_RPT_MODE_LEGACY,
2764 	RTW89_RA_RPT_MODE_HT,
2765 	RTW89_RA_RPT_MODE_VHT,
2766 	RTW89_RA_RPT_MODE_HE,
2767 	RTW89_RA_RPT_MODE_EHT,
2768 };
2769 
2770 enum rtw89_dig_noisy_level {
2771 	RTW89_DIG_NOISY_LEVEL0 = -1,
2772 	RTW89_DIG_NOISY_LEVEL1 = 0,
2773 	RTW89_DIG_NOISY_LEVEL2 = 1,
2774 	RTW89_DIG_NOISY_LEVEL3 = 2,
2775 	RTW89_DIG_NOISY_LEVEL_MAX = 3,
2776 };
2777 
2778 enum rtw89_gi_ltf {
2779 	RTW89_GILTF_LGI_4XHE32 = 0,
2780 	RTW89_GILTF_SGI_4XHE08 = 1,
2781 	RTW89_GILTF_2XHE16 = 2,
2782 	RTW89_GILTF_2XHE08 = 3,
2783 	RTW89_GILTF_1XHE16 = 4,
2784 	RTW89_GILTF_1XHE08 = 5,
2785 	RTW89_GILTF_MAX
2786 };
2787 
2788 enum rtw89_rx_frame_type {
2789 	RTW89_RX_TYPE_MGNT = 0,
2790 	RTW89_RX_TYPE_CTRL = 1,
2791 	RTW89_RX_TYPE_DATA = 2,
2792 	RTW89_RX_TYPE_RSVD = 3,
2793 };
2794 
2795 enum rtw89_efuse_block {
2796 	RTW89_EFUSE_BLOCK_SYS = 0,
2797 	RTW89_EFUSE_BLOCK_RF = 1,
2798 	RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2,
2799 	RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3,
2800 	RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4,
2801 	RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5,
2802 	RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6,
2803 	RTW89_EFUSE_BLOCK_ADIE = 7,
2804 
2805 	RTW89_EFUSE_BLOCK_NUM,
2806 	RTW89_EFUSE_BLOCK_IGNORE,
2807 };
2808 
2809 struct rtw89_ra_info {
2810 	u8 is_dis_ra:1;
2811 	/* Bit0 : CCK
2812 	 * Bit1 : OFDM
2813 	 * Bit2 : HT
2814 	 * Bit3 : VHT
2815 	 * Bit4 : HE
2816 	 * Bit5 : EHT
2817 	 */
2818 	u8 mode_ctrl:6;
2819 	u8 bw_cap:3; /* enum rtw89_bandwidth */
2820 	u8 macid;
2821 	u8 dcm_cap:1;
2822 	u8 er_cap:1;
2823 	u8 init_rate_lv:2;
2824 	u8 upd_all:1;
2825 	u8 en_sgi:1;
2826 	u8 ldpc_cap:1;
2827 	u8 stbc_cap:1;
2828 	u8 ss_num:3;
2829 	u8 giltf:3;
2830 	u8 upd_bw_nss_mask:1;
2831 	u8 upd_mask:1;
2832 	u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */
2833 	/* BFee CSI */
2834 	u8 band_num;
2835 	u8 ra_csi_rate_en:1;
2836 	u8 fixed_csi_rate_en:1;
2837 	u8 cr_tbl_sel:1;
2838 	u8 fix_giltf_en:1;
2839 	u8 fix_giltf:3;
2840 	u8 rsvd2:1;
2841 	u8 csi_mcs_ss_idx;
2842 	u8 csi_mode:2;
2843 	u8 csi_gi_ltf:3;
2844 	u8 csi_bw:3;
2845 };
2846 
2847 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4
2848 #define RTW89_PPDU_MAC_INFO_SIZE 8
2849 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96
2850 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128
2851 
2852 #define RTW89_MAX_RX_AGG_NUM 64
2853 #define RTW89_MAX_TX_AGG_NUM 128
2854 
2855 struct rtw89_ampdu_params {
2856 	u16 agg_num;
2857 	bool amsdu;
2858 };
2859 
2860 struct rtw89_ra_report {
2861 	struct rate_info txrate;
2862 	u32 bit_rate;
2863 	u16 hw_rate;
2864 	bool might_fallback_legacy;
2865 };
2866 
2867 DECLARE_EWMA(rssi, 10, 16);
2868 DECLARE_EWMA(evm, 10, 16);
2869 DECLARE_EWMA(snr, 10, 16);
2870 
2871 struct rtw89_ba_cam_entry {
2872 	struct list_head list;
2873 	u8 tid;
2874 };
2875 
2876 #define RTW89_MAX_ADDR_CAM_NUM		128
2877 #define RTW89_MAX_BSSID_CAM_NUM		20
2878 #define RTW89_MAX_SEC_CAM_NUM		128
2879 #define RTW89_MAX_BA_CAM_NUM		24
2880 #define RTW89_SEC_CAM_IN_ADDR_CAM	7
2881 
2882 struct rtw89_addr_cam_entry {
2883 	u8 addr_cam_idx;
2884 	u8 offset;
2885 	u8 len;
2886 	u8 valid	: 1;
2887 	u8 addr_mask	: 6;
2888 	u8 wapi		: 1;
2889 	u8 mask_sel	: 2;
2890 	u8 bssid_cam_idx: 6;
2891 
2892 	u8 sec_ent_mode;
2893 	DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM);
2894 	u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM];
2895 	u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM];
2896 	struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM];
2897 };
2898 
2899 struct rtw89_bssid_cam_entry {
2900 	u8 bssid[ETH_ALEN];
2901 	u8 phy_idx;
2902 	u8 bssid_cam_idx;
2903 	u8 offset;
2904 	u8 len;
2905 	u8 valid : 1;
2906 	u8 num;
2907 };
2908 
2909 struct rtw89_sec_cam_entry {
2910 	u8 sec_cam_idx;
2911 	u8 offset;
2912 	u8 len;
2913 	u8 type : 4;
2914 	u8 ext_key : 1;
2915 	u8 spp_mode : 1;
2916 	/* 256 bits */
2917 	u8 key[32];
2918 };
2919 
2920 struct rtw89_sta {
2921 	u8 mac_id;
2922 	bool disassoc;
2923 	bool er_cap;
2924 	struct rtw89_dev *rtwdev;
2925 	struct rtw89_vif *rtwvif;
2926 	struct rtw89_ra_info ra;
2927 	struct rtw89_ra_report ra_report;
2928 	int max_agg_wait;
2929 	u8 prev_rssi;
2930 	struct ewma_rssi avg_rssi;
2931 	struct ewma_rssi rssi[RF_PATH_MAX];
2932 	struct ewma_snr avg_snr;
2933 	struct ewma_evm evm_min[RF_PATH_MAX];
2934 	struct ewma_evm evm_max[RF_PATH_MAX];
2935 	struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS];
2936 	DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS);
2937 	struct ieee80211_rx_status rx_status;
2938 	u16 rx_hw_rate;
2939 	__le32 htc_template;
2940 	struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */
2941 	struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */
2942 	struct list_head ba_cam_list;
2943 	struct sk_buff_head roc_queue;
2944 
2945 	bool use_cfg_mask;
2946 	struct cfg80211_bitrate_mask mask;
2947 
2948 	bool cctl_tx_time;
2949 	u32 ampdu_max_time:4;
2950 	bool cctl_tx_retry_limit;
2951 	u32 data_tx_cnt_lmt:6;
2952 };
2953 
2954 struct rtw89_efuse {
2955 	bool valid;
2956 	bool power_k_valid;
2957 	u8 xtal_cap;
2958 	u8 addr[ETH_ALEN];
2959 	u8 rfe_type;
2960 	char country_code[2];
2961 };
2962 
2963 struct rtw89_phy_rate_pattern {
2964 	u64 ra_mask;
2965 	u16 rate;
2966 	u8 ra_mode;
2967 	bool enable;
2968 };
2969 
2970 struct rtw89_tx_wait_info {
2971 	struct rcu_head rcu_head;
2972 	struct completion completion;
2973 	bool tx_done;
2974 };
2975 
2976 struct rtw89_tx_skb_data {
2977 	struct rtw89_tx_wait_info __rcu *wait;
2978 	u8 hci_priv[];
2979 };
2980 
2981 #define RTW89_ROC_IDLE_TIMEOUT 500
2982 #define RTW89_ROC_TX_TIMEOUT 30
2983 enum rtw89_roc_state {
2984 	RTW89_ROC_IDLE,
2985 	RTW89_ROC_NORMAL,
2986 	RTW89_ROC_MGMT,
2987 };
2988 
2989 struct rtw89_roc {
2990 	struct ieee80211_channel chan;
2991 	struct delayed_work roc_work;
2992 	enum ieee80211_roc_type type;
2993 	enum rtw89_roc_state state;
2994 	int duration;
2995 };
2996 
2997 #define RTW89_P2P_MAX_NOA_NUM 2
2998 
2999 struct rtw89_p2p_ie_head {
3000 	u8 eid;
3001 	u8 ie_len;
3002 	u8 oui[3];
3003 	u8 oui_type;
3004 } __packed;
3005 
3006 struct rtw89_noa_attr_head {
3007 	u8 attr_type;
3008 	__le16 attr_len;
3009 	u8 index;
3010 	u8 oppps_ctwindow;
3011 } __packed;
3012 
3013 struct rtw89_p2p_noa_ie {
3014 	struct rtw89_p2p_ie_head p2p_head;
3015 	struct rtw89_noa_attr_head noa_head;
3016 	struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM];
3017 } __packed;
3018 
3019 struct rtw89_p2p_noa_setter {
3020 	struct rtw89_p2p_noa_ie ie;
3021 	u8 noa_count;
3022 	u8 noa_index;
3023 };
3024 
3025 struct rtw89_vif {
3026 	struct list_head list;
3027 	struct rtw89_dev *rtwdev;
3028 	struct rtw89_roc roc;
3029 	bool chanctx_assigned; /* only valid when running with chanctx_ops */
3030 	enum rtw89_sub_entity_idx sub_entity_idx;
3031 	enum rtw89_reg_6ghz_power reg_6ghz_power;
3032 
3033 	u8 mac_id;
3034 	u8 port;
3035 	u8 mac_addr[ETH_ALEN];
3036 	u8 bssid[ETH_ALEN];
3037 	u8 phy_idx;
3038 	u8 mac_idx;
3039 	u8 net_type;
3040 	u8 wifi_role;
3041 	u8 self_role;
3042 	u8 wmm;
3043 	u8 bcn_hit_cond;
3044 	u8 hit_rule;
3045 	u8 last_noa_nr;
3046 	bool offchan;
3047 	bool trigger;
3048 	bool lsig_txop;
3049 	u8 tgt_ind;
3050 	u8 frm_tgt_ind;
3051 	bool wowlan_pattern;
3052 	bool wowlan_uc;
3053 	bool wowlan_magic;
3054 	bool is_hesta;
3055 	bool last_a_ctrl;
3056 	bool dyn_tb_bedge_en;
3057 	bool pre_pwr_diff_en;
3058 	bool pwr_diff_en;
3059 	u8 def_tri_idx;
3060 	u32 tdls_peer;
3061 	struct work_struct update_beacon_work;
3062 	struct rtw89_addr_cam_entry addr_cam;
3063 	struct rtw89_bssid_cam_entry bssid_cam;
3064 	struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS];
3065 	struct rtw89_traffic_stats stats;
3066 	struct rtw89_phy_rate_pattern rate_pattern;
3067 	struct cfg80211_scan_request *scan_req;
3068 	struct ieee80211_scan_ies *scan_ies;
3069 	struct list_head general_pkt_list;
3070 	struct rtw89_p2p_noa_setter p2p_noa;
3071 };
3072 
3073 enum rtw89_lv1_rcvy_step {
3074 	RTW89_LV1_RCVY_STEP_1,
3075 	RTW89_LV1_RCVY_STEP_2,
3076 };
3077 
3078 struct rtw89_hci_ops {
3079 	int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req);
3080 	void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch);
3081 	void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop);
3082 	void (*reset)(struct rtw89_dev *rtwdev);
3083 	int (*start)(struct rtw89_dev *rtwdev);
3084 	void (*stop)(struct rtw89_dev *rtwdev);
3085 	void (*pause)(struct rtw89_dev *rtwdev, bool pause);
3086 	void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power);
3087 	void (*recalc_int_mit)(struct rtw89_dev *rtwdev);
3088 
3089 	u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr);
3090 	u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr);
3091 	u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr);
3092 	void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data);
3093 	void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data);
3094 	void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data);
3095 
3096 	int (*mac_pre_init)(struct rtw89_dev *rtwdev);
3097 	int (*mac_pre_deinit)(struct rtw89_dev *rtwdev);
3098 	int (*mac_post_init)(struct rtw89_dev *rtwdev);
3099 	int (*deinit)(struct rtw89_dev *rtwdev);
3100 
3101 	u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch);
3102 	int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step);
3103 	void (*dump_err_status)(struct rtw89_dev *rtwdev);
3104 	int (*napi_poll)(struct napi_struct *napi, int budget);
3105 
3106 	/* Deal with locks inside recovery_start and recovery_complete callbacks
3107 	 * by hci instance, and handle things which need to consider under SER.
3108 	 * e.g. turn on/off interrupts except for the one for halt notification.
3109 	 */
3110 	void (*recovery_start)(struct rtw89_dev *rtwdev);
3111 	void (*recovery_complete)(struct rtw89_dev *rtwdev);
3112 
3113 	void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable);
3114 	void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable);
3115 	void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable);
3116 	int (*poll_txdma_ch)(struct rtw89_dev *rtwdev);
3117 	void (*clr_idx_all)(struct rtw89_dev *rtwdev);
3118 	void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev);
3119 	void (*disable_intr)(struct rtw89_dev *rtwdev);
3120 	void (*enable_intr)(struct rtw89_dev *rtwdev);
3121 	int (*rst_bdram)(struct rtw89_dev *rtwdev);
3122 };
3123 
3124 struct rtw89_hci_info {
3125 	const struct rtw89_hci_ops *ops;
3126 	enum rtw89_hci_type type;
3127 	u32 rpwm_addr;
3128 	u32 cpwm_addr;
3129 	bool paused;
3130 };
3131 
3132 struct rtw89_chip_ops {
3133 	int (*enable_bb_rf)(struct rtw89_dev *rtwdev);
3134 	int (*disable_bb_rf)(struct rtw89_dev *rtwdev);
3135 	void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3136 	void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3137 	void (*bb_reset)(struct rtw89_dev *rtwdev,
3138 			 enum rtw89_phy_idx phy_idx);
3139 	void (*bb_sethw)(struct rtw89_dev *rtwdev);
3140 	u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3141 		       u32 addr, u32 mask);
3142 	bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
3143 			 u32 addr, u32 mask, u32 data);
3144 	void (*set_channel)(struct rtw89_dev *rtwdev,
3145 			    const struct rtw89_chan *chan,
3146 			    enum rtw89_mac_idx mac_idx,
3147 			    enum rtw89_phy_idx phy_idx);
3148 	void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter,
3149 				 struct rtw89_channel_help_params *p,
3150 				 const struct rtw89_chan *chan,
3151 				 enum rtw89_mac_idx mac_idx,
3152 				 enum rtw89_phy_idx phy_idx);
3153 	int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map,
3154 			  enum rtw89_efuse_block block);
3155 	int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map);
3156 	void (*fem_setup)(struct rtw89_dev *rtwdev);
3157 	void (*rfe_gpio)(struct rtw89_dev *rtwdev);
3158 	void (*rfk_init)(struct rtw89_dev *rtwdev);
3159 	void (*rfk_channel)(struct rtw89_dev *rtwdev);
3160 	void (*rfk_band_changed)(struct rtw89_dev *rtwdev,
3161 				 enum rtw89_phy_idx phy_idx);
3162 	void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start);
3163 	void (*rfk_track)(struct rtw89_dev *rtwdev);
3164 	void (*power_trim)(struct rtw89_dev *rtwdev);
3165 	void (*set_txpwr)(struct rtw89_dev *rtwdev,
3166 			  const struct rtw89_chan *chan,
3167 			  enum rtw89_phy_idx phy_idx);
3168 	void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev,
3169 			       enum rtw89_phy_idx phy_idx);
3170 	int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
3171 	u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path);
3172 	void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en,
3173 			       enum rtw89_phy_idx phy_idx);
3174 	void (*query_ppdu)(struct rtw89_dev *rtwdev,
3175 			   struct rtw89_rx_phy_ppdu *phy_ppdu,
3176 			   struct ieee80211_rx_status *status);
3177 	void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en,
3178 				enum rtw89_phy_idx phy_idx);
3179 	void (*cfg_txrx_path)(struct rtw89_dev *rtwdev);
3180 	void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev,
3181 				       s8 pw_ofst, enum rtw89_mac_idx mac_idx);
3182 	int (*pwr_on_func)(struct rtw89_dev *rtwdev);
3183 	int (*pwr_off_func)(struct rtw89_dev *rtwdev);
3184 	void (*query_rxdesc)(struct rtw89_dev *rtwdev,
3185 			     struct rtw89_rx_desc_info *desc_info,
3186 			     u8 *data, u32 data_offset);
3187 	void (*fill_txdesc)(struct rtw89_dev *rtwdev,
3188 			    struct rtw89_tx_desc_info *desc_info,
3189 			    void *txdesc);
3190 	void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev,
3191 				  struct rtw89_tx_desc_info *desc_info,
3192 				  void *txdesc);
3193 	int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl);
3194 	int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev,
3195 			   const struct rtw89_mac_ax_coex_gnt *gnt_cfg);
3196 	int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx,
3197 			   u32 *tx_en, enum rtw89_sch_tx_sel sel);
3198 	int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en);
3199 	int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev,
3200 				struct rtw89_vif *rtwvif,
3201 				struct rtw89_sta *rtwsta);
3202 	int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev,
3203 				    struct rtw89_vif *rtwvif,
3204 				    struct rtw89_sta *rtwsta);
3205 	int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev,
3206 				  struct ieee80211_vif *vif,
3207 				  struct ieee80211_sta *sta);
3208 	int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev,
3209 				  struct ieee80211_vif *vif,
3210 				  struct ieee80211_sta *sta);
3211 	int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev,
3212 				    struct rtw89_vif *rtwvif,
3213 				    struct rtw89_sta *rtwsta);
3214 	int (*h2c_update_beacon)(struct rtw89_dev *rtwdev,
3215 				 struct rtw89_vif *rtwvif);
3216 	int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta,
3217 			  bool valid, struct ieee80211_ampdu_params *params);
3218 
3219 	void (*btc_set_rfe)(struct rtw89_dev *rtwdev);
3220 	void (*btc_init_cfg)(struct rtw89_dev *rtwdev);
3221 	void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state);
3222 	void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val);
3223 	s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val);
3224 	void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev);
3225 	void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state);
3226 	void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type);
3227 	void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level);
3228 };
3229 
3230 enum rtw89_dma_ch {
3231 	RTW89_DMA_ACH0 = 0,
3232 	RTW89_DMA_ACH1 = 1,
3233 	RTW89_DMA_ACH2 = 2,
3234 	RTW89_DMA_ACH3 = 3,
3235 	RTW89_DMA_ACH4 = 4,
3236 	RTW89_DMA_ACH5 = 5,
3237 	RTW89_DMA_ACH6 = 6,
3238 	RTW89_DMA_ACH7 = 7,
3239 	RTW89_DMA_B0MG = 8,
3240 	RTW89_DMA_B0HI = 9,
3241 	RTW89_DMA_B1MG = 10,
3242 	RTW89_DMA_B1HI = 11,
3243 	RTW89_DMA_H2C = 12,
3244 	RTW89_DMA_CH_NUM = 13
3245 };
3246 
3247 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0))
3248 
3249 enum rtw89_mlo_dbcc_mode {
3250 	MLO_DBCC_NOT_SUPPORT = 1,
3251 	MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1),
3252 	MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2),
3253 	MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1),
3254 	MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2),
3255 	MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1),
3256 	MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2),
3257 	MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2),
3258 	DBCC_LEGACY = 0xffffffff,
3259 };
3260 
3261 enum rtw89_qta_mode {
3262 	RTW89_QTA_SCC,
3263 	RTW89_QTA_DLFW,
3264 	RTW89_QTA_WOW,
3265 
3266 	/* keep last */
3267 	RTW89_QTA_INVALID,
3268 };
3269 
3270 struct rtw89_hfc_ch_cfg {
3271 	u16 min;
3272 	u16 max;
3273 #define grp_0 0
3274 #define grp_1 1
3275 #define grp_num 2
3276 	u8 grp;
3277 };
3278 
3279 struct rtw89_hfc_ch_info {
3280 	u16 aval;
3281 	u16 used;
3282 };
3283 
3284 struct rtw89_hfc_pub_cfg {
3285 	u16 grp0;
3286 	u16 grp1;
3287 	u16 pub_max;
3288 	u16 wp_thrd;
3289 };
3290 
3291 struct rtw89_hfc_pub_info {
3292 	u16 g0_used;
3293 	u16 g1_used;
3294 	u16 g0_aval;
3295 	u16 g1_aval;
3296 	u16 pub_aval;
3297 	u16 wp_aval;
3298 };
3299 
3300 struct rtw89_hfc_prec_cfg {
3301 	u16 ch011_prec;
3302 	u16 h2c_prec;
3303 	u16 wp_ch07_prec;
3304 	u16 wp_ch811_prec;
3305 	u8 ch011_full_cond;
3306 	u8 h2c_full_cond;
3307 	u8 wp_ch07_full_cond;
3308 	u8 wp_ch811_full_cond;
3309 };
3310 
3311 struct rtw89_hfc_param {
3312 	bool en;
3313 	bool h2c_en;
3314 	u8 mode;
3315 	const struct rtw89_hfc_ch_cfg *ch_cfg;
3316 	struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM];
3317 	struct rtw89_hfc_pub_cfg pub_cfg;
3318 	struct rtw89_hfc_pub_info pub_info;
3319 	struct rtw89_hfc_prec_cfg prec_cfg;
3320 };
3321 
3322 struct rtw89_hfc_param_ini {
3323 	const struct rtw89_hfc_ch_cfg *ch_cfg;
3324 	const struct rtw89_hfc_pub_cfg *pub_cfg;
3325 	const struct rtw89_hfc_prec_cfg *prec_cfg;
3326 	u8 mode;
3327 };
3328 
3329 struct rtw89_dle_size {
3330 	u16 pge_size;
3331 	u16 lnk_pge_num;
3332 	u16 unlnk_pge_num;
3333 	/* for WiFi 7 chips below */
3334 	u32 srt_ofst;
3335 };
3336 
3337 struct rtw89_wde_quota {
3338 	u16 hif;
3339 	u16 wcpu;
3340 	u16 pkt_in;
3341 	u16 cpu_io;
3342 };
3343 
3344 struct rtw89_ple_quota {
3345 	u16 cma0_tx;
3346 	u16 cma1_tx;
3347 	u16 c2h;
3348 	u16 h2c;
3349 	u16 wcpu;
3350 	u16 mpdu_proc;
3351 	u16 cma0_dma;
3352 	u16 cma1_dma;
3353 	u16 bb_rpt;
3354 	u16 wd_rel;
3355 	u16 cpu_io;
3356 	u16 tx_rpt;
3357 	/* for WiFi 7 chips below */
3358 	u16 h2d;
3359 };
3360 
3361 struct rtw89_rsvd_quota {
3362 	u16 mpdu_info_tbl;
3363 	u16 b0_csi;
3364 	u16 b1_csi;
3365 	u16 b0_lmr;
3366 	u16 b1_lmr;
3367 	u16 b0_ftm;
3368 	u16 b1_ftm;
3369 	u16 b0_smr;
3370 	u16 b1_smr;
3371 	u16 others;
3372 };
3373 
3374 struct rtw89_dle_rsvd_size {
3375 	u32 srt_ofst;
3376 	u32 size;
3377 };
3378 
3379 struct rtw89_dle_mem {
3380 	enum rtw89_qta_mode mode;
3381 	const struct rtw89_dle_size *wde_size;
3382 	const struct rtw89_dle_size *ple_size;
3383 	const struct rtw89_wde_quota *wde_min_qt;
3384 	const struct rtw89_wde_quota *wde_max_qt;
3385 	const struct rtw89_ple_quota *ple_min_qt;
3386 	const struct rtw89_ple_quota *ple_max_qt;
3387 	/* for WiFi 7 chips below */
3388 	const struct rtw89_rsvd_quota *rsvd_qt;
3389 	const struct rtw89_dle_rsvd_size *rsvd0_size;
3390 	const struct rtw89_dle_rsvd_size *rsvd1_size;
3391 };
3392 
3393 struct rtw89_reg_def {
3394 	u32 addr;
3395 	u32 mask;
3396 };
3397 
3398 struct rtw89_reg2_def {
3399 	u32 addr;
3400 	u32 data;
3401 };
3402 
3403 struct rtw89_reg3_def {
3404 	u32 addr;
3405 	u32 mask;
3406 	u32 data;
3407 };
3408 
3409 struct rtw89_reg5_def {
3410 	u8 flag; /* recognized by parsers */
3411 	u8 path;
3412 	u32 addr;
3413 	u32 mask;
3414 	u32 data;
3415 };
3416 
3417 struct rtw89_reg_imr {
3418 	u32 addr;
3419 	u32 clr;
3420 	u32 set;
3421 };
3422 
3423 struct rtw89_phy_table {
3424 	const struct rtw89_reg2_def *regs;
3425 	u32 n_regs;
3426 	enum rtw89_rf_path rf_path;
3427 	void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg,
3428 		       enum rtw89_rf_path rf_path, void *data);
3429 };
3430 
3431 struct rtw89_txpwr_table {
3432 	const void *data;
3433 	u32 size;
3434 	void (*load)(struct rtw89_dev *rtwdev,
3435 		     const struct rtw89_txpwr_table *tbl);
3436 };
3437 
3438 struct rtw89_txpwr_rule_2ghz {
3439 	const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3440 		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3441 		       [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3442 	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3443 			  [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3444 };
3445 
3446 struct rtw89_txpwr_rule_5ghz {
3447 	const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3448 		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3449 		       [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3450 	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3451 			  [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3452 };
3453 
3454 struct rtw89_txpwr_rule_6ghz {
3455 	const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3456 		       [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3457 		       [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3458 		       [RTW89_6G_CH_NUM];
3459 	const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM]
3460 			  [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3461 			  [RTW89_6G_CH_NUM];
3462 };
3463 
3464 struct rtw89_tx_shape {
3465 	const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
3466 	const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM];
3467 };
3468 
3469 struct rtw89_rfe_parms {
3470 	const struct rtw89_txpwr_table *byr_tbl;
3471 	struct rtw89_txpwr_rule_2ghz rule_2ghz;
3472 	struct rtw89_txpwr_rule_5ghz rule_5ghz;
3473 	struct rtw89_txpwr_rule_6ghz rule_6ghz;
3474 	struct rtw89_tx_shape tx_shape;
3475 };
3476 
3477 struct rtw89_rfe_parms_conf {
3478 	const struct rtw89_rfe_parms *rfe_parms;
3479 	u8 rfe_type;
3480 };
3481 
3482 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0
3483 
3484 struct rtw89_txpwr_conf {
3485 	u8 rfe_type;
3486 	u8 ent_sz;
3487 	u32 num_ents;
3488 	const void *data;
3489 };
3490 
3491 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data)
3492 
3493 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \
3494 	for (typecheck(const void *, cursor), (cursor) = (conf)->data, \
3495 	     memcpy(&(entry), cursor, \
3496 		    min_t(u8, sizeof(entry), (conf)->ent_sz)); \
3497 	     (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \
3498 	     (cursor) += (conf)->ent_sz, \
3499 	     memcpy(&(entry), cursor, \
3500 		    min_t(u8, sizeof(entry), (conf)->ent_sz)))
3501 
3502 struct rtw89_txpwr_byrate_data {
3503 	struct rtw89_txpwr_conf conf;
3504 	struct rtw89_txpwr_table tbl;
3505 };
3506 
3507 struct rtw89_txpwr_lmt_2ghz_data {
3508 	struct rtw89_txpwr_conf conf;
3509 	s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM]
3510 	    [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3511 	    [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3512 };
3513 
3514 struct rtw89_txpwr_lmt_5ghz_data {
3515 	struct rtw89_txpwr_conf conf;
3516 	s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM]
3517 	    [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3518 	    [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3519 };
3520 
3521 struct rtw89_txpwr_lmt_6ghz_data {
3522 	struct rtw89_txpwr_conf conf;
3523 	s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM]
3524 	    [RTW89_RS_LMT_NUM][RTW89_BF_NUM]
3525 	    [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3526 	    [RTW89_6G_CH_NUM];
3527 };
3528 
3529 struct rtw89_txpwr_lmt_ru_2ghz_data {
3530 	struct rtw89_txpwr_conf conf;
3531 	s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
3532 	    [RTW89_REGD_NUM][RTW89_2G_CH_NUM];
3533 };
3534 
3535 struct rtw89_txpwr_lmt_ru_5ghz_data {
3536 	struct rtw89_txpwr_conf conf;
3537 	s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
3538 	    [RTW89_REGD_NUM][RTW89_5G_CH_NUM];
3539 };
3540 
3541 struct rtw89_txpwr_lmt_ru_6ghz_data {
3542 	struct rtw89_txpwr_conf conf;
3543 	s8 v[RTW89_RU_NUM][RTW89_NTX_NUM]
3544 	    [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]
3545 	    [RTW89_6G_CH_NUM];
3546 };
3547 
3548 struct rtw89_tx_shape_lmt_data {
3549 	struct rtw89_txpwr_conf conf;
3550 	u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM];
3551 };
3552 
3553 struct rtw89_tx_shape_lmt_ru_data {
3554 	struct rtw89_txpwr_conf conf;
3555 	u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM];
3556 };
3557 
3558 struct rtw89_rfe_data {
3559 	struct rtw89_txpwr_byrate_data byrate;
3560 	struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz;
3561 	struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz;
3562 	struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz;
3563 	struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz;
3564 	struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz;
3565 	struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz;
3566 	struct rtw89_tx_shape_lmt_data tx_shape_lmt;
3567 	struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru;
3568 	struct rtw89_rfe_parms rfe_parms;
3569 };
3570 
3571 struct rtw89_page_regs {
3572 	u32 hci_fc_ctrl;
3573 	u32 ch_page_ctrl;
3574 	u32 ach_page_ctrl;
3575 	u32 ach_page_info;
3576 	u32 pub_page_info3;
3577 	u32 pub_page_ctrl1;
3578 	u32 pub_page_ctrl2;
3579 	u32 pub_page_info1;
3580 	u32 pub_page_info2;
3581 	u32 wp_page_ctrl1;
3582 	u32 wp_page_ctrl2;
3583 	u32 wp_page_info1;
3584 };
3585 
3586 struct rtw89_imr_info {
3587 	u32 wdrls_imr_set;
3588 	u32 wsec_imr_reg;
3589 	u32 wsec_imr_set;
3590 	u32 mpdu_tx_imr_set;
3591 	u32 mpdu_rx_imr_set;
3592 	u32 sta_sch_imr_set;
3593 	u32 txpktctl_imr_b0_reg;
3594 	u32 txpktctl_imr_b0_clr;
3595 	u32 txpktctl_imr_b0_set;
3596 	u32 txpktctl_imr_b1_reg;
3597 	u32 txpktctl_imr_b1_clr;
3598 	u32 txpktctl_imr_b1_set;
3599 	u32 wde_imr_clr;
3600 	u32 wde_imr_set;
3601 	u32 ple_imr_clr;
3602 	u32 ple_imr_set;
3603 	u32 host_disp_imr_clr;
3604 	u32 host_disp_imr_set;
3605 	u32 cpu_disp_imr_clr;
3606 	u32 cpu_disp_imr_set;
3607 	u32 other_disp_imr_clr;
3608 	u32 other_disp_imr_set;
3609 	u32 bbrpt_com_err_imr_reg;
3610 	u32 bbrpt_chinfo_err_imr_reg;
3611 	u32 bbrpt_err_imr_set;
3612 	u32 bbrpt_dfs_err_imr_reg;
3613 	u32 ptcl_imr_clr;
3614 	u32 ptcl_imr_set;
3615 	u32 cdma_imr_0_reg;
3616 	u32 cdma_imr_0_clr;
3617 	u32 cdma_imr_0_set;
3618 	u32 cdma_imr_1_reg;
3619 	u32 cdma_imr_1_clr;
3620 	u32 cdma_imr_1_set;
3621 	u32 phy_intf_imr_reg;
3622 	u32 phy_intf_imr_clr;
3623 	u32 phy_intf_imr_set;
3624 	u32 rmac_imr_reg;
3625 	u32 rmac_imr_clr;
3626 	u32 rmac_imr_set;
3627 	u32 tmac_imr_reg;
3628 	u32 tmac_imr_clr;
3629 	u32 tmac_imr_set;
3630 };
3631 
3632 struct rtw89_imr_table {
3633 	const struct rtw89_reg_imr *regs;
3634 	u32 n_regs;
3635 };
3636 
3637 struct rtw89_xtal_info {
3638 	u32 xcap_reg;
3639 	u32 sc_xo_mask;
3640 	u32 sc_xi_mask;
3641 };
3642 
3643 struct rtw89_rrsr_cfgs {
3644 	struct rtw89_reg3_def ref_rate;
3645 	struct rtw89_reg3_def rsc;
3646 };
3647 
3648 struct rtw89_dig_regs {
3649 	u32 seg0_pd_reg;
3650 	u32 pd_lower_bound_mask;
3651 	u32 pd_spatial_reuse_en;
3652 	u32 bmode_pd_reg;
3653 	u32 bmode_cca_rssi_limit_en;
3654 	u32 bmode_pd_lower_bound_reg;
3655 	u32 bmode_rssi_nocca_low_th_mask;
3656 	struct rtw89_reg_def p0_lna_init;
3657 	struct rtw89_reg_def p1_lna_init;
3658 	struct rtw89_reg_def p0_tia_init;
3659 	struct rtw89_reg_def p1_tia_init;
3660 	struct rtw89_reg_def p0_rxb_init;
3661 	struct rtw89_reg_def p1_rxb_init;
3662 	struct rtw89_reg_def p0_p20_pagcugc_en;
3663 	struct rtw89_reg_def p0_s20_pagcugc_en;
3664 	struct rtw89_reg_def p1_p20_pagcugc_en;
3665 	struct rtw89_reg_def p1_s20_pagcugc_en;
3666 };
3667 
3668 struct rtw89_edcca_regs {
3669 	u32 edcca_level;
3670 	u32 edcca_mask;
3671 	u32 edcca_p_mask;
3672 	u32 ppdu_level;
3673 	u32 ppdu_mask;
3674 	u32 rpt_a;
3675 	u32 rpt_b;
3676 	u32 rpt_sel;
3677 	u32 rpt_sel_mask;
3678 	u32 rpt_sel_be;
3679 	u32 rpt_sel_be_mask;
3680 	u32 tx_collision_t2r_st;
3681 	u32 tx_collision_t2r_st_mask;
3682 };
3683 
3684 struct rtw89_phy_ul_tb_info {
3685 	bool dyn_tb_tri_en;
3686 	u8 def_if_bandedge;
3687 };
3688 
3689 struct rtw89_antdiv_stats {
3690 	struct ewma_rssi cck_rssi_avg;
3691 	struct ewma_rssi ofdm_rssi_avg;
3692 	struct ewma_rssi non_legacy_rssi_avg;
3693 	u16 pkt_cnt_cck;
3694 	u16 pkt_cnt_ofdm;
3695 	u16 pkt_cnt_non_legacy;
3696 	u32 evm;
3697 };
3698 
3699 struct rtw89_antdiv_info {
3700 	struct rtw89_antdiv_stats target_stats;
3701 	struct rtw89_antdiv_stats main_stats;
3702 	struct rtw89_antdiv_stats aux_stats;
3703 	u8 training_count;
3704 	u8 rssi_pre;
3705 	bool get_stats;
3706 };
3707 
3708 enum rtw89_chanctx_state {
3709 	RTW89_CHANCTX_STATE_MCC_START,
3710 	RTW89_CHANCTX_STATE_MCC_STOP,
3711 };
3712 
3713 enum rtw89_chanctx_callbacks {
3714 	RTW89_CHANCTX_CALLBACK_PLACEHOLDER,
3715 	RTW89_CHANCTX_CALLBACK_RFK,
3716 
3717 	NUM_OF_RTW89_CHANCTX_CALLBACKS,
3718 };
3719 
3720 struct rtw89_chanctx_listener {
3721 	void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS])
3722 		(struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state);
3723 };
3724 
3725 struct rtw89_chip_info {
3726 	enum rtw89_core_chip_id chip_id;
3727 	enum rtw89_chip_gen chip_gen;
3728 	const struct rtw89_chip_ops *ops;
3729 	const struct rtw89_mac_gen_def *mac_def;
3730 	const struct rtw89_phy_gen_def *phy_def;
3731 	const char *fw_basename;
3732 	u8 fw_format_max;
3733 	bool try_ce_fw;
3734 	u8 bbmcu_nr;
3735 	u32 needed_fw_elms;
3736 	u32 fifo_size;
3737 	bool small_fifo_size;
3738 	u32 dle_scc_rsvd_size;
3739 	u16 max_amsdu_limit;
3740 	bool dis_2g_40m_ul_ofdma;
3741 	u32 rsvd_ple_ofst;
3742 	const struct rtw89_hfc_param_ini *hfc_param_ini;
3743 	const struct rtw89_dle_mem *dle_mem;
3744 	u8 wde_qempty_acq_grpnum;
3745 	u8 wde_qempty_mgq_grpsel;
3746 	u32 rf_base_addr[2];
3747 	u8 support_chanctx_num;
3748 	u8 support_bands;
3749 	u16 support_bandwidths;
3750 	bool support_unii4;
3751 	bool ul_tb_waveform_ctrl;
3752 	bool ul_tb_pwr_diff;
3753 	bool hw_sec_hdr;
3754 	u8 rf_path_num;
3755 	u8 tx_nss;
3756 	u8 rx_nss;
3757 	u8 acam_num;
3758 	u8 bcam_num;
3759 	u8 scam_num;
3760 	u8 bacam_num;
3761 	u8 bacam_dynamic_num;
3762 	enum rtw89_bacam_ver bacam_ver;
3763 	u8 ppdu_max_usr;
3764 
3765 	u8 sec_ctrl_efuse_size;
3766 	u32 physical_efuse_size;
3767 	u32 logical_efuse_size;
3768 	u32 limit_efuse_size;
3769 	u32 dav_phy_efuse_size;
3770 	u32 dav_log_efuse_size;
3771 	u32 phycap_addr;
3772 	u32 phycap_size;
3773 	const struct rtw89_efuse_block_cfg *efuse_blocks;
3774 
3775 	const struct rtw89_pwr_cfg * const *pwr_on_seq;
3776 	const struct rtw89_pwr_cfg * const *pwr_off_seq;
3777 	const struct rtw89_phy_table *bb_table;
3778 	const struct rtw89_phy_table *bb_gain_table;
3779 	const struct rtw89_phy_table *rf_table[RF_PATH_MAX];
3780 	const struct rtw89_phy_table *nctl_table;
3781 	const struct rtw89_rfk_tbl *nctl_post_table;
3782 	const struct rtw89_phy_dig_gain_table *dig_table;
3783 	const struct rtw89_dig_regs *dig_regs;
3784 	const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table;
3785 
3786 	/* NULL if no rfe-specific, or a null-terminated array by rfe_parms */
3787 	const struct rtw89_rfe_parms_conf *rfe_parms_conf;
3788 	const struct rtw89_rfe_parms *dflt_parms;
3789 	const struct rtw89_chanctx_listener *chanctx_listener;
3790 
3791 	u8 txpwr_factor_rf;
3792 	u8 txpwr_factor_mac;
3793 
3794 	u32 para_ver;
3795 	u32 wlcx_desired;
3796 	u8 btcx_desired;
3797 	u8 scbd;
3798 	u8 mailbox;
3799 
3800 	u8 afh_guard_ch;
3801 	const u8 *wl_rssi_thres;
3802 	const u8 *bt_rssi_thres;
3803 	u8 rssi_tol;
3804 
3805 	u8 mon_reg_num;
3806 	const struct rtw89_btc_fbtc_mreg *mon_reg;
3807 	u8 rf_para_ulink_num;
3808 	const struct rtw89_btc_rf_trx_para *rf_para_ulink;
3809 	u8 rf_para_dlink_num;
3810 	const struct rtw89_btc_rf_trx_para *rf_para_dlink;
3811 	u8 ps_mode_supported;
3812 	u8 low_power_hci_modes;
3813 
3814 	u32 h2c_cctl_func_id;
3815 	u32 hci_func_en_addr;
3816 	u32 h2c_desc_size;
3817 	u32 txwd_body_size;
3818 	u32 txwd_info_size;
3819 	u32 h2c_ctrl_reg;
3820 	const u32 *h2c_regs;
3821 	struct rtw89_reg_def h2c_counter_reg;
3822 	u32 c2h_ctrl_reg;
3823 	const u32 *c2h_regs;
3824 	struct rtw89_reg_def c2h_counter_reg;
3825 	const struct rtw89_page_regs *page_regs;
3826 	bool cfo_src_fd;
3827 	bool cfo_hw_comp;
3828 	const struct rtw89_reg_def *dcfo_comp;
3829 	u8 dcfo_comp_sft;
3830 	const struct rtw89_imr_info *imr_info;
3831 	const struct rtw89_imr_table *imr_dmac_table;
3832 	const struct rtw89_imr_table *imr_cmac_table;
3833 	const struct rtw89_rrsr_cfgs *rrsr_cfgs;
3834 	struct rtw89_reg_def bss_clr_vld;
3835 	u32 bss_clr_map_reg;
3836 	u32 dma_ch_mask;
3837 	const struct rtw89_edcca_regs *edcca_regs;
3838 	const struct wiphy_wowlan_support *wowlan_stub;
3839 	const struct rtw89_xtal_info *xtal_info;
3840 };
3841 
3842 union rtw89_bus_info {
3843 	const struct rtw89_pci_info *pci;
3844 };
3845 
3846 struct rtw89_driver_info {
3847 	const struct rtw89_chip_info *chip;
3848 	union rtw89_bus_info bus;
3849 };
3850 
3851 enum rtw89_hcifc_mode {
3852 	RTW89_HCIFC_POH = 0,
3853 	RTW89_HCIFC_STF = 1,
3854 	RTW89_HCIFC_SDIO = 2,
3855 
3856 	/* keep last */
3857 	RTW89_HCIFC_MODE_INVALID,
3858 };
3859 
3860 struct rtw89_dle_info {
3861 	const struct rtw89_rsvd_quota *rsvd_qt;
3862 	enum rtw89_qta_mode qta_mode;
3863 	u16 ple_pg_size;
3864 	u16 ple_free_pg;
3865 	u16 c0_rx_qta;
3866 	u16 c1_rx_qta;
3867 };
3868 
3869 enum rtw89_host_rpr_mode {
3870 	RTW89_RPR_MODE_POH = 0,
3871 	RTW89_RPR_MODE_STF
3872 };
3873 
3874 #define RTW89_COMPLETION_BUF_SIZE 24
3875 #define RTW89_WAIT_COND_IDLE UINT_MAX
3876 
3877 struct rtw89_completion_data {
3878 	bool err;
3879 	u8 buf[RTW89_COMPLETION_BUF_SIZE];
3880 };
3881 
3882 struct rtw89_wait_info {
3883 	atomic_t cond;
3884 	struct completion completion;
3885 	struct rtw89_completion_data data;
3886 };
3887 
3888 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100)
3889 
3890 static inline void rtw89_init_wait(struct rtw89_wait_info *wait)
3891 {
3892 	init_completion(&wait->completion);
3893 	atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
3894 }
3895 
3896 struct rtw89_mac_info {
3897 	struct rtw89_dle_info dle_info;
3898 	struct rtw89_hfc_param hfc_param;
3899 	enum rtw89_qta_mode qta_mode;
3900 	u8 rpwm_seq_num;
3901 	u8 cpwm_seq_num;
3902 
3903 	/* see RTW89_FW_OFLD_WAIT_COND series for wait condition */
3904 	struct rtw89_wait_info fw_ofld_wait;
3905 };
3906 
3907 enum rtw89_fwdl_check_type {
3908 	RTW89_FWDL_CHECK_FREERTOS_DONE,
3909 	RTW89_FWDL_CHECK_WCPU_FWDL_DONE,
3910 	RTW89_FWDL_CHECK_DCPU_FWDL_DONE,
3911 	RTW89_FWDL_CHECK_BB0_FWDL_DONE,
3912 	RTW89_FWDL_CHECK_BB1_FWDL_DONE,
3913 };
3914 
3915 enum rtw89_fw_type {
3916 	RTW89_FW_NORMAL = 1,
3917 	RTW89_FW_WOWLAN = 3,
3918 	RTW89_FW_NORMAL_CE = 5,
3919 	RTW89_FW_BBMCU0 = 64,
3920 	RTW89_FW_BBMCU1 = 65,
3921 	RTW89_FW_LOGFMT = 255,
3922 };
3923 
3924 enum rtw89_fw_feature {
3925 	RTW89_FW_FEATURE_OLD_HT_RA_FORMAT,
3926 	RTW89_FW_FEATURE_SCAN_OFFLOAD,
3927 	RTW89_FW_FEATURE_TX_WAKE,
3928 	RTW89_FW_FEATURE_CRASH_TRIGGER,
3929 	RTW89_FW_FEATURE_NO_PACKET_DROP,
3930 	RTW89_FW_FEATURE_NO_DEEP_PS,
3931 	RTW89_FW_FEATURE_NO_LPS_PG,
3932 	RTW89_FW_FEATURE_BEACON_FILTER,
3933 	RTW89_FW_FEATURE_MACID_PAUSE_SLEEP,
3934 };
3935 
3936 struct rtw89_fw_suit {
3937 	enum rtw89_fw_type type;
3938 	const u8 *data;
3939 	u32 size;
3940 	u8 major_ver;
3941 	u8 minor_ver;
3942 	u8 sub_ver;
3943 	u8 sub_idex;
3944 	u16 build_year;
3945 	u16 build_mon;
3946 	u16 build_date;
3947 	u16 build_hour;
3948 	u16 build_min;
3949 	u8 cmd_ver;
3950 	u8 hdr_ver;
3951 	u32 commitid;
3952 };
3953 
3954 #define RTW89_FW_VER_CODE(major, minor, sub, idx)	\
3955 	(((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx))
3956 #define RTW89_FW_SUIT_VER_CODE(s)	\
3957 	RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex)
3958 
3959 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr)		\
3960 	RTW89_FW_VER_CODE((mfw_hdr)->ver.major,	\
3961 			  (mfw_hdr)->ver.minor,	\
3962 			  (mfw_hdr)->ver.sub,	\
3963 			  (mfw_hdr)->ver.idx)
3964 
3965 #define RTW89_FW_HDR_VER_CODE(fw_hdr)				\
3966 	RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION),	\
3967 			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION),	\
3968 			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION),	\
3969 			  le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX))
3970 
3971 struct rtw89_fw_req_info {
3972 	const struct firmware *firmware;
3973 	struct completion completion;
3974 };
3975 
3976 struct rtw89_fw_log {
3977 	struct rtw89_fw_suit suit;
3978 	bool enable;
3979 	u32 last_fmt_id;
3980 	u32 fmt_count;
3981 	const __le32 *fmt_ids;
3982 	const char *(*fmts)[];
3983 };
3984 
3985 struct rtw89_fw_elm_info {
3986 	struct rtw89_phy_table *bb_tbl;
3987 	struct rtw89_phy_table *bb_gain;
3988 	struct rtw89_phy_table *rf_radio[RF_PATH_MAX];
3989 	struct rtw89_phy_table *rf_nctl;
3990 	struct rtw89_fw_txpwr_track_cfg *txpwr_trk;
3991 	struct rtw89_phy_rfk_log_fmt *rfk_log_fmt;
3992 };
3993 
3994 struct rtw89_fw_info {
3995 	struct rtw89_fw_req_info req;
3996 	int fw_format;
3997 	u8 h2c_seq;
3998 	u8 rec_seq;
3999 	u8 h2c_counter;
4000 	u8 c2h_counter;
4001 	struct rtw89_fw_suit normal;
4002 	struct rtw89_fw_suit wowlan;
4003 	struct rtw89_fw_suit bbmcu0;
4004 	struct rtw89_fw_suit bbmcu1;
4005 	struct rtw89_fw_log log;
4006 	u32 feature_map;
4007 	struct rtw89_fw_elm_info elm_info;
4008 };
4009 
4010 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \
4011 	(!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat)))
4012 
4013 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \
4014 	((_fw)->feature_map |= BIT(_fw_feature))
4015 
4016 struct rtw89_cam_info {
4017 	DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM);
4018 	DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM);
4019 	DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM);
4020 	DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM);
4021 	struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM];
4022 };
4023 
4024 enum rtw89_sar_sources {
4025 	RTW89_SAR_SOURCE_NONE,
4026 	RTW89_SAR_SOURCE_COMMON,
4027 
4028 	RTW89_SAR_SOURCE_NR,
4029 };
4030 
4031 enum rtw89_sar_subband {
4032 	RTW89_SAR_2GHZ_SUBBAND,
4033 	RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */
4034 	RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */
4035 	RTW89_SAR_5GHZ_SUBBAND_3,   /* U-NII-3 */
4036 	RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */
4037 	RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */
4038 	RTW89_SAR_6GHZ_SUBBAND_6,   /* U-NII-6 */
4039 	RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */
4040 	RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */
4041 	RTW89_SAR_6GHZ_SUBBAND_8,   /* U-NII-8 */
4042 
4043 	RTW89_SAR_SUBBAND_NR,
4044 };
4045 
4046 struct rtw89_sar_cfg_common {
4047 	bool set[RTW89_SAR_SUBBAND_NR];
4048 	s32 cfg[RTW89_SAR_SUBBAND_NR];
4049 };
4050 
4051 struct rtw89_sar_info {
4052 	/* used to decide how to acces SAR cfg union */
4053 	enum rtw89_sar_sources src;
4054 
4055 	/* reserved for different knids of SAR cfg struct.
4056 	 * supposed that a single cfg struct cannot handle various SAR sources.
4057 	 */
4058 	union {
4059 		struct rtw89_sar_cfg_common cfg_common;
4060 	};
4061 };
4062 
4063 enum rtw89_tas_state {
4064 	RTW89_TAS_STATE_DPR_OFF,
4065 	RTW89_TAS_STATE_DPR_ON,
4066 	RTW89_TAS_STATE_DPR_FORBID,
4067 };
4068 
4069 #define RTW89_TAS_MAX_WINDOW 50
4070 struct rtw89_tas_info {
4071 	s16 txpwr_history[RTW89_TAS_MAX_WINDOW];
4072 	s32 total_txpwr;
4073 	u8 cur_idx;
4074 	s8 dpr_gap;
4075 	s8 delta;
4076 	enum rtw89_tas_state state;
4077 	bool enable;
4078 };
4079 
4080 struct rtw89_chanctx_cfg {
4081 	enum rtw89_sub_entity_idx idx;
4082 };
4083 
4084 enum rtw89_chanctx_changes {
4085 	RTW89_CHANCTX_REMOTE_STA_CHANGE,
4086 	RTW89_CHANCTX_BCN_OFFSET_CHANGE,
4087 	RTW89_CHANCTX_P2P_PS_CHANGE,
4088 	RTW89_CHANCTX_BT_SLOT_CHANGE,
4089 	RTW89_CHANCTX_TSF32_TOGGLE_CHANGE,
4090 
4091 	NUM_OF_RTW89_CHANCTX_CHANGES,
4092 	RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES,
4093 };
4094 
4095 enum rtw89_entity_mode {
4096 	RTW89_ENTITY_MODE_SCC,
4097 	RTW89_ENTITY_MODE_MCC_PREPARE,
4098 	RTW89_ENTITY_MODE_MCC,
4099 
4100 	NUM_OF_RTW89_ENTITY_MODE,
4101 	RTW89_ENTITY_MODE_INVALID = NUM_OF_RTW89_ENTITY_MODE,
4102 };
4103 
4104 struct rtw89_sub_entity {
4105 	struct cfg80211_chan_def chandef;
4106 	struct rtw89_chan chan;
4107 	struct rtw89_chan_rcd rcd;
4108 	struct rtw89_chanctx_cfg *cfg;
4109 };
4110 
4111 struct rtw89_edcca_bak {
4112 	u8 a;
4113 	u8 p;
4114 	u8 ppdu;
4115 	u8 th_old;
4116 };
4117 
4118 enum rtw89_dm_type {
4119 	RTW89_DM_DYNAMIC_EDCCA,
4120 };
4121 
4122 struct rtw89_hal {
4123 	u32 rx_fltr;
4124 	u8 cv;
4125 	u8 acv;
4126 	u32 antenna_tx;
4127 	u32 antenna_rx;
4128 	u8 tx_nss;
4129 	u8 rx_nss;
4130 	bool tx_path_diversity;
4131 	bool ant_diversity;
4132 	bool ant_diversity_fixed;
4133 	bool support_cckpd;
4134 	bool support_igi;
4135 	atomic_t roc_entity_idx;
4136 
4137 	DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES);
4138 	DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY);
4139 	struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY];
4140 	struct cfg80211_chan_def roc_chandef;
4141 
4142 	bool entity_active;
4143 	bool entity_pause;
4144 	enum rtw89_entity_mode entity_mode;
4145 
4146 	struct rtw89_edcca_bak edcca_bak;
4147 	u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */
4148 };
4149 
4150 #define RTW89_MAX_MAC_ID_NUM 128
4151 #define RTW89_MAX_PKT_OFLD_NUM 255
4152 
4153 enum rtw89_flags {
4154 	RTW89_FLAG_POWERON,
4155 	RTW89_FLAG_DMAC_FUNC,
4156 	RTW89_FLAG_CMAC0_FUNC,
4157 	RTW89_FLAG_CMAC1_FUNC,
4158 	RTW89_FLAG_FW_RDY,
4159 	RTW89_FLAG_RUNNING,
4160 	RTW89_FLAG_BFEE_MON,
4161 	RTW89_FLAG_BFEE_EN,
4162 	RTW89_FLAG_BFEE_TIMER_KEEP,
4163 	RTW89_FLAG_NAPI_RUNNING,
4164 	RTW89_FLAG_LEISURE_PS,
4165 	RTW89_FLAG_LOW_POWER_MODE,
4166 	RTW89_FLAG_INACTIVE_PS,
4167 	RTW89_FLAG_CRASH_SIMULATING,
4168 	RTW89_FLAG_SER_HANDLING,
4169 	RTW89_FLAG_WOWLAN,
4170 	RTW89_FLAG_FORBIDDEN_TRACK_WROK,
4171 	RTW89_FLAG_CHANGING_INTERFACE,
4172 
4173 	NUM_OF_RTW89_FLAGS,
4174 };
4175 
4176 enum rtw89_pkt_drop_sel {
4177 	RTW89_PKT_DROP_SEL_MACID_BE_ONCE,
4178 	RTW89_PKT_DROP_SEL_MACID_BK_ONCE,
4179 	RTW89_PKT_DROP_SEL_MACID_VI_ONCE,
4180 	RTW89_PKT_DROP_SEL_MACID_VO_ONCE,
4181 	RTW89_PKT_DROP_SEL_MACID_ALL,
4182 	RTW89_PKT_DROP_SEL_MG0_ONCE,
4183 	RTW89_PKT_DROP_SEL_HIQ_ONCE,
4184 	RTW89_PKT_DROP_SEL_HIQ_PORT,
4185 	RTW89_PKT_DROP_SEL_HIQ_MBSSID,
4186 	RTW89_PKT_DROP_SEL_BAND,
4187 	RTW89_PKT_DROP_SEL_BAND_ONCE,
4188 	RTW89_PKT_DROP_SEL_REL_MACID,
4189 	RTW89_PKT_DROP_SEL_REL_HIQ_PORT,
4190 	RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID,
4191 };
4192 
4193 struct rtw89_pkt_drop_params {
4194 	enum rtw89_pkt_drop_sel sel;
4195 	enum rtw89_mac_idx mac_band;
4196 	u8 macid;
4197 	u8 port;
4198 	u8 mbssid;
4199 	bool tf_trs;
4200 	u32 macid_band_sel[4];
4201 };
4202 
4203 struct rtw89_pkt_stat {
4204 	u16 beacon_nr;
4205 	u32 rx_rate_cnt[RTW89_HW_RATE_NR];
4206 };
4207 
4208 DECLARE_EWMA(thermal, 4, 4);
4209 
4210 struct rtw89_phy_stat {
4211 	struct ewma_thermal avg_thermal[RF_PATH_MAX];
4212 	struct rtw89_pkt_stat cur_pkt_stat;
4213 	struct rtw89_pkt_stat last_pkt_stat;
4214 };
4215 
4216 #define RTW89_DACK_PATH_NR 2
4217 #define RTW89_DACK_IDX_NR 2
4218 #define RTW89_DACK_MSBK_NR 16
4219 struct rtw89_dack_info {
4220 	bool dack_done;
4221 	u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR];
4222 	u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4223 	u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4224 	u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR];
4225 	u32 dack_cnt;
4226 	bool addck_timeout[RTW89_DACK_PATH_NR];
4227 	bool dadck_timeout[RTW89_DACK_PATH_NR];
4228 	bool msbk_timeout[RTW89_DACK_PATH_NR];
4229 };
4230 
4231 #define RTW89_IQK_CHS_NR 2
4232 #define RTW89_IQK_PATH_NR 4
4233 
4234 struct rtw89_rfk_mcc_info {
4235 	u8 ch[RTW89_IQK_CHS_NR];
4236 	u8 band[RTW89_IQK_CHS_NR];
4237 	u8 table_idx;
4238 };
4239 
4240 struct rtw89_lck_info {
4241 	u8 thermal[RF_PATH_MAX];
4242 };
4243 
4244 struct rtw89_rx_dck_info {
4245 	u8 thermal[RF_PATH_MAX];
4246 };
4247 
4248 struct rtw89_iqk_info {
4249 	bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4250 	bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4251 	bool lok_fail[RTW89_IQK_PATH_NR];
4252 	bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4253 	bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4254 	u32 iqk_fail_cnt;
4255 	bool is_iqk_init;
4256 	u32 iqk_channel[RTW89_IQK_CHS_NR];
4257 	u8 iqk_band[RTW89_IQK_PATH_NR];
4258 	u8 iqk_ch[RTW89_IQK_PATH_NR];
4259 	u8 iqk_bw[RTW89_IQK_PATH_NR];
4260 	u8 iqk_times;
4261 	u8 version;
4262 	u32 nb_txcfir[RTW89_IQK_PATH_NR];
4263 	u32 nb_rxcfir[RTW89_IQK_PATH_NR];
4264 	u32 bp_txkresult[RTW89_IQK_PATH_NR];
4265 	u32 bp_rxkresult[RTW89_IQK_PATH_NR];
4266 	u32 bp_iqkenable[RTW89_IQK_PATH_NR];
4267 	bool is_wb_txiqk[RTW89_IQK_PATH_NR];
4268 	bool is_wb_rxiqk[RTW89_IQK_PATH_NR];
4269 	bool is_nbiqk;
4270 	bool iqk_fft_en;
4271 	bool iqk_xym_en;
4272 	bool iqk_sram_en;
4273 	bool iqk_cfir_en;
4274 	u32 syn1to2;
4275 	u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4276 	u8 iqk_table_idx[RTW89_IQK_PATH_NR];
4277 	u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4278 	u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR];
4279 };
4280 
4281 #define RTW89_DPK_RF_PATH 2
4282 #define RTW89_DPK_AVG_THERMAL_NUM 8
4283 #define RTW89_DPK_BKUP_NUM 2
4284 struct rtw89_dpk_bkup_para {
4285 	enum rtw89_band band;
4286 	enum rtw89_bandwidth bw;
4287 	u8 ch;
4288 	bool path_ok;
4289 	u8 mdpd_en;
4290 	u8 txagc_dpk;
4291 	u8 ther_dpk;
4292 	u8 gs;
4293 	u16 pwsf;
4294 };
4295 
4296 struct rtw89_dpk_info {
4297 	bool is_dpk_enable;
4298 	bool is_dpk_reload_en;
4299 	u8 dpk_gs[RTW89_PHY_MAX];
4300 	u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4301 	u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4302 	u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4303 	u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4304 	u8 cur_idx[RTW89_DPK_RF_PATH];
4305 	u8 cur_k_set;
4306 	struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM];
4307 };
4308 
4309 struct rtw89_fem_info {
4310 	bool elna_2g;
4311 	bool elna_5g;
4312 	bool epa_2g;
4313 	bool epa_5g;
4314 	bool epa_6g;
4315 };
4316 
4317 struct rtw89_phy_ch_info {
4318 	u8 rssi_min;
4319 	u16 rssi_min_macid;
4320 	u8 pre_rssi_min;
4321 	u8 rssi_max;
4322 	u16 rssi_max_macid;
4323 	u8 rxsc_160;
4324 	u8 rxsc_80;
4325 	u8 rxsc_40;
4326 	u8 rxsc_20;
4327 	u8 rxsc_l;
4328 	u8 is_noisy;
4329 };
4330 
4331 struct rtw89_agc_gaincode_set {
4332 	u8 lna_idx;
4333 	u8 tia_idx;
4334 	u8 rxb_idx;
4335 };
4336 
4337 #define IGI_RSSI_TH_NUM 5
4338 #define FA_TH_NUM 4
4339 #define LNA_GAIN_NUM 7
4340 #define TIA_GAIN_NUM 2
4341 struct rtw89_dig_info {
4342 	struct rtw89_agc_gaincode_set cur_gaincode;
4343 	bool force_gaincode_idx_en;
4344 	struct rtw89_agc_gaincode_set force_gaincode;
4345 	u8 igi_rssi_th[IGI_RSSI_TH_NUM];
4346 	u16 fa_th[FA_TH_NUM];
4347 	u8 igi_rssi;
4348 	u8 igi_fa_rssi;
4349 	u8 fa_rssi_ofst;
4350 	u8 dyn_igi_max;
4351 	u8 dyn_igi_min;
4352 	bool dyn_pd_th_en;
4353 	u8 dyn_pd_th_max;
4354 	u8 pd_low_th_ofst;
4355 	u8 ib_pbk;
4356 	s8 ib_pkpwr;
4357 	s8 lna_gain_a[LNA_GAIN_NUM];
4358 	s8 lna_gain_g[LNA_GAIN_NUM];
4359 	s8 *lna_gain;
4360 	s8 tia_gain_a[TIA_GAIN_NUM];
4361 	s8 tia_gain_g[TIA_GAIN_NUM];
4362 	s8 *tia_gain;
4363 	bool is_linked_pre;
4364 	bool bypass_dig;
4365 };
4366 
4367 enum rtw89_multi_cfo_mode {
4368 	RTW89_PKT_BASED_AVG_MODE = 0,
4369 	RTW89_ENTRY_BASED_AVG_MODE = 1,
4370 	RTW89_TP_BASED_AVG_MODE = 2,
4371 };
4372 
4373 enum rtw89_phy_cfo_status {
4374 	RTW89_PHY_DCFO_STATE_NORMAL = 0,
4375 	RTW89_PHY_DCFO_STATE_ENHANCE = 1,
4376 	RTW89_PHY_DCFO_STATE_HOLD = 2,
4377 	RTW89_PHY_DCFO_STATE_MAX
4378 };
4379 
4380 enum rtw89_phy_cfo_ul_ofdma_acc_mode {
4381 	RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0,
4382 	RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1
4383 };
4384 
4385 struct rtw89_cfo_tracking_info {
4386 	u16 cfo_timer_ms;
4387 	bool cfo_trig_by_timer_en;
4388 	enum rtw89_phy_cfo_status phy_cfo_status;
4389 	enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode;
4390 	u8 phy_cfo_trk_cnt;
4391 	bool is_adjust;
4392 	enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode;
4393 	bool apply_compensation;
4394 	u8 crystal_cap;
4395 	u8 crystal_cap_default;
4396 	u8 def_x_cap;
4397 	s8 x_cap_ofst;
4398 	u32 sta_cfo_tolerance;
4399 	s32 cfo_tail[CFO_TRACK_MAX_USER];
4400 	u16 cfo_cnt[CFO_TRACK_MAX_USER];
4401 	s32 cfo_avg_pre;
4402 	s32 cfo_avg[CFO_TRACK_MAX_USER];
4403 	s32 pre_cfo_avg[CFO_TRACK_MAX_USER];
4404 	s32 dcfo_avg;
4405 	s32 dcfo_avg_pre;
4406 	u32 packet_count;
4407 	u32 packet_count_pre;
4408 	s32 residual_cfo_acc;
4409 	u8 phy_cfotrk_state;
4410 	u8 phy_cfotrk_cnt;
4411 	bool divergence_lock_en;
4412 	u8 x_cap_lb;
4413 	u8 x_cap_ub;
4414 	u8 lock_cnt;
4415 };
4416 
4417 enum rtw89_tssi_alimk_band {
4418 	TSSI_ALIMK_2G = 0,
4419 	TSSI_ALIMK_5GL,
4420 	TSSI_ALIMK_5GM,
4421 	TSSI_ALIMK_5GH,
4422 	TSSI_ALIMK_MAX
4423 };
4424 
4425 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
4426 #define TSSI_TRIM_CH_GROUP_NUM 8
4427 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
4428 
4429 #define TSSI_CCK_CH_GROUP_NUM 6
4430 #define TSSI_MCS_2G_CH_GROUP_NUM 5
4431 #define TSSI_MCS_5G_CH_GROUP_NUM 14
4432 #define TSSI_MCS_6G_CH_GROUP_NUM 32
4433 #define TSSI_MCS_CH_GROUP_NUM \
4434 	(TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
4435 #define TSSI_MAX_CH_NUM 67
4436 #define TSSI_ALIMK_VALUE_NUM 8
4437 
4438 struct rtw89_tssi_info {
4439 	u8 thermal[RF_PATH_MAX];
4440 	s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
4441 	s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
4442 	s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
4443 	s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
4444 	s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
4445 	s8 extra_ofst[RF_PATH_MAX];
4446 	bool tssi_tracking_check[RF_PATH_MAX];
4447 	u8 default_txagc_offset[RF_PATH_MAX];
4448 	u32 base_thermal[RF_PATH_MAX];
4449 	bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
4450 	u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
4451 	u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
4452 	bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
4453 	u32 tssi_alimk_time;
4454 };
4455 
4456 struct rtw89_power_trim_info {
4457 	bool pg_thermal_trim;
4458 	bool pg_pa_bias_trim;
4459 	u8 thermal_trim[RF_PATH_MAX];
4460 	u8 pa_bias_trim[RF_PATH_MAX];
4461 	u8 pad_bias_trim[RF_PATH_MAX];
4462 };
4463 
4464 struct rtw89_regd {
4465 	char alpha2[3];
4466 	u8 txpwr_regd[RTW89_BAND_NUM];
4467 };
4468 
4469 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX
4470 
4471 struct rtw89_regulatory_info {
4472 	const struct rtw89_regd *regd;
4473 	enum rtw89_reg_6ghz_power reg_6ghz_power;
4474 	DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM);
4475 };
4476 
4477 enum rtw89_ifs_clm_application {
4478 	RTW89_IFS_CLM_INIT = 0,
4479 	RTW89_IFS_CLM_BACKGROUND = 1,
4480 	RTW89_IFS_CLM_ACS = 2,
4481 	RTW89_IFS_CLM_DIG = 3,
4482 	RTW89_IFS_CLM_TDMA_DIG = 4,
4483 	RTW89_IFS_CLM_DBG = 5,
4484 	RTW89_IFS_CLM_DBG_MANUAL = 6
4485 };
4486 
4487 enum rtw89_env_racing_lv {
4488 	RTW89_RAC_RELEASE = 0,
4489 	RTW89_RAC_LV_1 = 1,
4490 	RTW89_RAC_LV_2 = 2,
4491 	RTW89_RAC_LV_3 = 3,
4492 	RTW89_RAC_LV_4 = 4,
4493 	RTW89_RAC_MAX_NUM = 5
4494 };
4495 
4496 struct rtw89_ccx_para_info {
4497 	enum rtw89_env_racing_lv rac_lv;
4498 	u16 mntr_time;
4499 	u8 nhm_manual_th_ofst;
4500 	u8 nhm_manual_th0;
4501 	enum rtw89_ifs_clm_application ifs_clm_app;
4502 	u32 ifs_clm_manual_th_times;
4503 	u32 ifs_clm_manual_th0;
4504 	u8 fahm_manual_th_ofst;
4505 	u8 fahm_manual_th0;
4506 	u8 fahm_numer_opt;
4507 	u8 fahm_denom_opt;
4508 };
4509 
4510 enum rtw89_ccx_edcca_opt_sc_idx {
4511 	RTW89_CCX_EDCCA_SEG0_P0 = 0,
4512 	RTW89_CCX_EDCCA_SEG0_S1 = 1,
4513 	RTW89_CCX_EDCCA_SEG0_S2 = 2,
4514 	RTW89_CCX_EDCCA_SEG0_S3 = 3,
4515 	RTW89_CCX_EDCCA_SEG1_P0 = 4,
4516 	RTW89_CCX_EDCCA_SEG1_S1 = 5,
4517 	RTW89_CCX_EDCCA_SEG1_S2 = 6,
4518 	RTW89_CCX_EDCCA_SEG1_S3 = 7
4519 };
4520 
4521 enum rtw89_ccx_edcca_opt_bw_idx {
4522 	RTW89_CCX_EDCCA_BW20_0 = 0,
4523 	RTW89_CCX_EDCCA_BW20_1 = 1,
4524 	RTW89_CCX_EDCCA_BW20_2 = 2,
4525 	RTW89_CCX_EDCCA_BW20_3 = 3,
4526 	RTW89_CCX_EDCCA_BW20_4 = 4,
4527 	RTW89_CCX_EDCCA_BW20_5 = 5,
4528 	RTW89_CCX_EDCCA_BW20_6 = 6,
4529 	RTW89_CCX_EDCCA_BW20_7 = 7
4530 };
4531 
4532 #define RTW89_NHM_TH_NUM 11
4533 #define RTW89_FAHM_TH_NUM 11
4534 #define RTW89_NHM_RPT_NUM 12
4535 #define RTW89_FAHM_RPT_NUM 12
4536 #define RTW89_IFS_CLM_NUM 4
4537 struct rtw89_env_monitor_info {
4538 	u8 ccx_watchdog_result;
4539 	bool ccx_ongoing;
4540 	u8 ccx_rac_lv;
4541 	bool ccx_manual_ctrl;
4542 	u16 ifs_clm_mntr_time;
4543 	enum rtw89_ifs_clm_application ifs_clm_app;
4544 	u16 ccx_period;
4545 	u8 ccx_unit_idx;
4546 	u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM];
4547 	u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM];
4548 	u16 ifs_clm_tx;
4549 	u16 ifs_clm_edcca_excl_cca;
4550 	u16 ifs_clm_ofdmfa;
4551 	u16 ifs_clm_ofdmcca_excl_fa;
4552 	u16 ifs_clm_cckfa;
4553 	u16 ifs_clm_cckcca_excl_fa;
4554 	u16 ifs_clm_total_ifs;
4555 	u8 ifs_clm_his[RTW89_IFS_CLM_NUM];
4556 	u16 ifs_clm_avg[RTW89_IFS_CLM_NUM];
4557 	u16 ifs_clm_cca[RTW89_IFS_CLM_NUM];
4558 	u8 ifs_clm_tx_ratio;
4559 	u8 ifs_clm_edcca_excl_cca_ratio;
4560 	u8 ifs_clm_cck_fa_ratio;
4561 	u8 ifs_clm_ofdm_fa_ratio;
4562 	u8 ifs_clm_cck_cca_excl_fa_ratio;
4563 	u8 ifs_clm_ofdm_cca_excl_fa_ratio;
4564 	u16 ifs_clm_cck_fa_permil;
4565 	u16 ifs_clm_ofdm_fa_permil;
4566 	u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM];
4567 	u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM];
4568 };
4569 
4570 enum rtw89_ser_rcvy_step {
4571 	RTW89_SER_DRV_STOP_TX,
4572 	RTW89_SER_DRV_STOP_RX,
4573 	RTW89_SER_DRV_STOP_RUN,
4574 	RTW89_SER_HAL_STOP_DMA,
4575 	RTW89_SER_SUPPRESS_LOG,
4576 	RTW89_NUM_OF_SER_FLAGS
4577 };
4578 
4579 struct rtw89_ser {
4580 	u8 state;
4581 	u8 alarm_event;
4582 	bool prehandle_l1;
4583 
4584 	struct work_struct ser_hdl_work;
4585 	struct delayed_work ser_alarm_work;
4586 	const struct state_ent *st_tbl;
4587 	const struct event_ent *ev_tbl;
4588 	struct list_head msg_q;
4589 	spinlock_t msg_q_lock; /* lock when read/write ser msg */
4590 	DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS);
4591 };
4592 
4593 enum rtw89_mac_ax_ps_mode {
4594 	RTW89_MAC_AX_PS_MODE_ACTIVE = 0,
4595 	RTW89_MAC_AX_PS_MODE_LEGACY = 1,
4596 	RTW89_MAC_AX_PS_MODE_WMMPS  = 2,
4597 	RTW89_MAC_AX_PS_MODE_MAX    = 3,
4598 };
4599 
4600 enum rtw89_last_rpwm_mode {
4601 	RTW89_LAST_RPWM_PS        = 0x0,
4602 	RTW89_LAST_RPWM_ACTIVE    = 0x6,
4603 };
4604 
4605 struct rtw89_lps_parm {
4606 	u8 macid;
4607 	u8 psmode; /* enum rtw89_mac_ax_ps_mode */
4608 	u8 lastrpwm; /* enum rtw89_last_rpwm_mode */
4609 };
4610 
4611 struct rtw89_ppdu_sts_info {
4612 	struct sk_buff_head rx_queue[RTW89_PHY_MAX];
4613 	u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX];
4614 };
4615 
4616 struct rtw89_early_h2c {
4617 	struct list_head list;
4618 	u8 *h2c;
4619 	u16 h2c_len;
4620 };
4621 
4622 struct rtw89_hw_scan_info {
4623 	struct ieee80211_vif *scanning_vif;
4624 	struct list_head pkt_list[NUM_NL80211_BANDS];
4625 	struct rtw89_chan op_chan;
4626 	bool abort;
4627 	u32 last_chan_idx;
4628 };
4629 
4630 enum rtw89_phy_bb_gain_band {
4631 	RTW89_BB_GAIN_BAND_2G = 0,
4632 	RTW89_BB_GAIN_BAND_5G_L = 1,
4633 	RTW89_BB_GAIN_BAND_5G_M = 2,
4634 	RTW89_BB_GAIN_BAND_5G_H = 3,
4635 	RTW89_BB_GAIN_BAND_6G_L = 4,
4636 	RTW89_BB_GAIN_BAND_6G_M = 5,
4637 	RTW89_BB_GAIN_BAND_6G_H = 6,
4638 	RTW89_BB_GAIN_BAND_6G_UH = 7,
4639 
4640 	RTW89_BB_GAIN_BAND_NR,
4641 };
4642 
4643 enum rtw89_phy_gain_band_be {
4644 	RTW89_BB_GAIN_BAND_2G_BE = 0,
4645 	RTW89_BB_GAIN_BAND_5G_L_BE = 1,
4646 	RTW89_BB_GAIN_BAND_5G_M_BE = 2,
4647 	RTW89_BB_GAIN_BAND_5G_H_BE = 3,
4648 	RTW89_BB_GAIN_BAND_6G_L0_BE = 4,
4649 	RTW89_BB_GAIN_BAND_6G_L1_BE = 5,
4650 	RTW89_BB_GAIN_BAND_6G_M0_BE = 6,
4651 	RTW89_BB_GAIN_BAND_6G_M1_BE = 7,
4652 	RTW89_BB_GAIN_BAND_6G_H0_BE = 8,
4653 	RTW89_BB_GAIN_BAND_6G_H1_BE = 9,
4654 	RTW89_BB_GAIN_BAND_6G_UH0_BE = 10,
4655 	RTW89_BB_GAIN_BAND_6G_UH1_BE = 11,
4656 
4657 	RTW89_BB_GAIN_BAND_NR_BE,
4658 };
4659 
4660 enum rtw89_phy_bb_bw_be {
4661 	RTW89_BB_BW_20_40 = 0,
4662 	RTW89_BB_BW_80_160_320 = 1,
4663 
4664 	RTW89_BB_BW_NR_BE,
4665 };
4666 
4667 enum rtw89_bw20_sc {
4668 	RTW89_BW20_SC_20M = 1,
4669 	RTW89_BW20_SC_40M = 2,
4670 	RTW89_BW20_SC_80M = 4,
4671 	RTW89_BW20_SC_160M = 8,
4672 	RTW89_BW20_SC_320M = 16,
4673 };
4674 
4675 enum rtw89_cmac_table_bw {
4676 	RTW89_CMAC_BW_20M = 0,
4677 	RTW89_CMAC_BW_40M = 1,
4678 	RTW89_CMAC_BW_80M = 2,
4679 	RTW89_CMAC_BW_160M = 3,
4680 	RTW89_CMAC_BW_320M = 4,
4681 
4682 	RTW89_CMAC_BW_NR,
4683 };
4684 
4685 enum rtw89_phy_bb_rxsc_num {
4686 	RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */
4687 	RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */
4688 	RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */
4689 };
4690 
4691 struct rtw89_phy_bb_gain_info {
4692 	s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4693 	s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM];
4694 	s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4695 	s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM];
4696 	s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4697 			[LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */
4698 	s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX];
4699 	s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4700 		      [RTW89_BB_RXSC_NUM_40];
4701 	s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4702 		      [RTW89_BB_RXSC_NUM_80];
4703 	s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]
4704 		       [RTW89_BB_RXSC_NUM_160];
4705 };
4706 
4707 struct rtw89_phy_bb_gain_info_be {
4708 	s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
4709 		   [LNA_GAIN_NUM];
4710 	s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX]
4711 		   [TIA_GAIN_NUM];
4712 	s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
4713 			  [RF_PATH_MAX][LNA_GAIN_NUM];
4714 	s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
4715 		    [RF_PATH_MAX][LNA_GAIN_NUM];
4716 	s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE]
4717 			[RF_PATH_MAX][LNA_GAIN_NUM + 1];
4718 	s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
4719 		      [RTW89_BW20_SC_20M];
4720 	s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
4721 		      [RTW89_BW20_SC_40M];
4722 	s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
4723 		      [RTW89_BW20_SC_80M];
4724 	s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX]
4725 		       [RTW89_BW20_SC_160M];
4726 };
4727 
4728 struct rtw89_phy_efuse_gain {
4729 	bool offset_valid;
4730 	bool comp_valid;
4731 	s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */
4732 	s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */
4733 	s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */
4734 	s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */
4735 };
4736 
4737 #define RTW89_MAX_PATTERN_NUM             18
4738 #define RTW89_MAX_PATTERN_MASK_SIZE       4
4739 #define RTW89_MAX_PATTERN_SIZE            128
4740 
4741 struct rtw89_wow_cam_info {
4742 	bool r_w;
4743 	u8 idx;
4744 	u32 mask[RTW89_MAX_PATTERN_MASK_SIZE];
4745 	u16 crc;
4746 	bool negative_pattern_match;
4747 	bool skip_mac_hdr;
4748 	bool uc;
4749 	bool mc;
4750 	bool bc;
4751 	bool valid;
4752 };
4753 
4754 struct rtw89_wow_param {
4755 	struct ieee80211_vif *wow_vif;
4756 	DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM);
4757 	struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM];
4758 	u8 pattern_cnt;
4759 };
4760 
4761 struct rtw89_mcc_limit {
4762 	bool enable;
4763 	u16 max_tob; /* TU; max time offset behind */
4764 	u16 max_toa; /* TU; max time offset ahead */
4765 	u16 max_dur; /* TU */
4766 };
4767 
4768 struct rtw89_mcc_policy {
4769 	u8 c2h_rpt;
4770 	u8 tx_null_early;
4771 	u8 dis_tx_null;
4772 	u8 in_curr_ch;
4773 	u8 dis_sw_retry;
4774 	u8 sw_retry_count;
4775 };
4776 
4777 struct rtw89_mcc_role {
4778 	struct rtw89_vif *rtwvif;
4779 	struct rtw89_mcc_policy policy;
4780 	struct rtw89_mcc_limit limit;
4781 
4782 	/* byte-array in LE order for FW */
4783 	u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)];
4784 
4785 	u16 duration; /* TU */
4786 	u16 beacon_interval; /* TU */
4787 	bool is_2ghz;
4788 	bool is_go;
4789 	bool is_gc;
4790 };
4791 
4792 struct rtw89_mcc_bt_role {
4793 	u16 duration; /* TU */
4794 };
4795 
4796 struct rtw89_mcc_courtesy {
4797 	bool enable;
4798 	u8 slot_num;
4799 	u8 macid_src;
4800 	u8 macid_tgt;
4801 };
4802 
4803 enum rtw89_mcc_plan {
4804 	RTW89_MCC_PLAN_TAIL_BT,
4805 	RTW89_MCC_PLAN_MID_BT,
4806 	RTW89_MCC_PLAN_NO_BT,
4807 
4808 	NUM_OF_RTW89_MCC_PLAN,
4809 };
4810 
4811 struct rtw89_mcc_pattern {
4812 	s16 tob_ref; /* TU; time offset behind of reference role */
4813 	s16 toa_ref; /* TU; time offset ahead of reference role */
4814 	s16 tob_aux; /* TU; time offset behind of auxiliary role */
4815 	s16 toa_aux; /* TU; time offset ahead of auxiliary role */
4816 
4817 	enum rtw89_mcc_plan plan;
4818 	struct rtw89_mcc_courtesy courtesy;
4819 };
4820 
4821 struct rtw89_mcc_sync {
4822 	bool enable;
4823 	u16 offset; /* TU */
4824 	u8 macid_src;
4825 	u8 macid_tgt;
4826 };
4827 
4828 struct rtw89_mcc_config {
4829 	struct rtw89_mcc_pattern pattern;
4830 	struct rtw89_mcc_sync sync;
4831 	u64 start_tsf;
4832 	u16 mcc_interval; /* TU */
4833 	u16 beacon_offset; /* TU */
4834 };
4835 
4836 enum rtw89_mcc_mode {
4837 	RTW89_MCC_MODE_GO_STA,
4838 	RTW89_MCC_MODE_GC_STA,
4839 };
4840 
4841 struct rtw89_mcc_info {
4842 	struct rtw89_wait_info wait;
4843 
4844 	u8 group;
4845 	enum rtw89_mcc_mode mode;
4846 	struct rtw89_mcc_role role_ref; /* reference role */
4847 	struct rtw89_mcc_role role_aux; /* auxiliary role */
4848 	struct rtw89_mcc_bt_role bt_role;
4849 	struct rtw89_mcc_config config;
4850 };
4851 
4852 struct rtw89_dev {
4853 	struct ieee80211_hw *hw;
4854 	struct device *dev;
4855 	const struct ieee80211_ops *ops;
4856 
4857 	bool dbcc_en;
4858 	enum rtw89_mlo_dbcc_mode mlo_dbcc_mode;
4859 	struct rtw89_hw_scan_info scan_info;
4860 	const struct rtw89_chip_info *chip;
4861 	const struct rtw89_pci_info *pci_info;
4862 	const struct rtw89_rfe_parms *rfe_parms;
4863 	struct rtw89_hal hal;
4864 	struct rtw89_mcc_info mcc;
4865 	struct rtw89_mac_info mac;
4866 	struct rtw89_fw_info fw;
4867 	struct rtw89_hci_info hci;
4868 	struct rtw89_efuse efuse;
4869 	struct rtw89_traffic_stats stats;
4870 	struct rtw89_rfe_data *rfe_data;
4871 
4872 	/* ensures exclusive access from mac80211 callbacks */
4873 	struct mutex mutex;
4874 	struct list_head rtwvifs_list;
4875 	/* used to protect rf read write */
4876 	struct mutex rf_mutex;
4877 	struct workqueue_struct *txq_wq;
4878 	struct work_struct txq_work;
4879 	struct delayed_work txq_reinvoke_work;
4880 	/* used to protect ba_list and forbid_ba_list */
4881 	spinlock_t ba_lock;
4882 	/* txqs to setup ba session */
4883 	struct list_head ba_list;
4884 	/* txqs to forbid ba session */
4885 	struct list_head forbid_ba_list;
4886 	struct work_struct ba_work;
4887 	/* used to protect rpwm */
4888 	spinlock_t rpwm_lock;
4889 
4890 	struct rtw89_cam_info cam_info;
4891 
4892 	struct sk_buff_head c2h_queue;
4893 	struct work_struct c2h_work;
4894 	struct work_struct ips_work;
4895 	struct work_struct load_firmware_work;
4896 	struct work_struct cancel_6ghz_probe_work;
4897 
4898 	struct list_head early_h2c_list;
4899 
4900 	struct rtw89_ser ser;
4901 
4902 	DECLARE_BITMAP(hw_port, RTW89_PORT_NUM);
4903 	DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM);
4904 	DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS);
4905 	DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM);
4906 
4907 	struct rtw89_phy_stat phystat;
4908 	struct rtw89_dack_info dack;
4909 	struct rtw89_iqk_info iqk;
4910 	struct rtw89_dpk_info dpk;
4911 	struct rtw89_rfk_mcc_info rfk_mcc;
4912 	struct rtw89_lck_info lck;
4913 	struct rtw89_rx_dck_info rx_dck;
4914 	bool is_tssi_mode[RF_PATH_MAX];
4915 	bool is_bt_iqk_timeout;
4916 
4917 	struct rtw89_fem_info fem;
4918 	struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM];
4919 	struct rtw89_tssi_info tssi;
4920 	struct rtw89_power_trim_info pwr_trim;
4921 
4922 	struct rtw89_cfo_tracking_info cfo_tracking;
4923 	struct rtw89_env_monitor_info env_monitor;
4924 	struct rtw89_dig_info dig;
4925 	struct rtw89_phy_ch_info ch_info;
4926 	union {
4927 		struct rtw89_phy_bb_gain_info ax;
4928 		struct rtw89_phy_bb_gain_info_be be;
4929 	} bb_gain;
4930 	struct rtw89_phy_efuse_gain efuse_gain;
4931 	struct rtw89_phy_ul_tb_info ul_tb_info;
4932 	struct rtw89_antdiv_info antdiv;
4933 
4934 	struct delayed_work track_work;
4935 	struct delayed_work chanctx_work;
4936 	struct delayed_work coex_act1_work;
4937 	struct delayed_work coex_bt_devinfo_work;
4938 	struct delayed_work coex_rfk_chk_work;
4939 	struct delayed_work cfo_track_work;
4940 	struct delayed_work forbid_ba_work;
4941 	struct delayed_work roc_work;
4942 	struct delayed_work antdiv_work;
4943 	struct rtw89_ppdu_sts_info ppdu_sts;
4944 	u8 total_sta_assoc;
4945 	bool scanning;
4946 
4947 	struct rtw89_regulatory_info regulatory;
4948 	struct rtw89_sar_info sar;
4949 	struct rtw89_tas_info tas;
4950 
4951 	struct rtw89_btc btc;
4952 	enum rtw89_ps_mode ps_mode;
4953 	bool lps_enabled;
4954 
4955 	struct rtw89_wow_param wow;
4956 
4957 	/* napi structure */
4958 	struct net_device netdev;
4959 	struct napi_struct napi;
4960 	int napi_budget_countdown;
4961 
4962 	/* HCI related data, keep last */
4963 	u8 priv[] __aligned(sizeof(void *));
4964 };
4965 
4966 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev,
4967 				     struct rtw89_core_tx_request *tx_req)
4968 {
4969 	return rtwdev->hci.ops->tx_write(rtwdev, tx_req);
4970 }
4971 
4972 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev)
4973 {
4974 	rtwdev->hci.ops->reset(rtwdev);
4975 }
4976 
4977 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev)
4978 {
4979 	return rtwdev->hci.ops->start(rtwdev);
4980 }
4981 
4982 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev)
4983 {
4984 	rtwdev->hci.ops->stop(rtwdev);
4985 }
4986 
4987 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev)
4988 {
4989 	return rtwdev->hci.ops->deinit(rtwdev);
4990 }
4991 
4992 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause)
4993 {
4994 	rtwdev->hci.ops->pause(rtwdev, pause);
4995 }
4996 
4997 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power)
4998 {
4999 	rtwdev->hci.ops->switch_mode(rtwdev, low_power);
5000 }
5001 
5002 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev)
5003 {
5004 	rtwdev->hci.ops->recalc_int_mit(rtwdev);
5005 }
5006 
5007 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch)
5008 {
5009 	return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch);
5010 }
5011 
5012 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch)
5013 {
5014 	return rtwdev->hci.ops->tx_kick_off(rtwdev, txch);
5015 }
5016 
5017 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev)
5018 {
5019 	return rtwdev->hci.ops->mac_pre_deinit(rtwdev);
5020 }
5021 
5022 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues,
5023 					  bool drop)
5024 {
5025 	if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags))
5026 		return;
5027 
5028 	if (rtwdev->hci.ops->flush_queues)
5029 		return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop);
5030 }
5031 
5032 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev)
5033 {
5034 	if (rtwdev->hci.ops->recovery_start)
5035 		rtwdev->hci.ops->recovery_start(rtwdev);
5036 }
5037 
5038 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev)
5039 {
5040 	if (rtwdev->hci.ops->recovery_complete)
5041 		rtwdev->hci.ops->recovery_complete(rtwdev);
5042 }
5043 
5044 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev)
5045 {
5046 	if (rtwdev->hci.ops->enable_intr)
5047 		rtwdev->hci.ops->enable_intr(rtwdev);
5048 }
5049 
5050 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev)
5051 {
5052 	if (rtwdev->hci.ops->disable_intr)
5053 		rtwdev->hci.ops->disable_intr(rtwdev);
5054 }
5055 
5056 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable)
5057 {
5058 	if (rtwdev->hci.ops->ctrl_txdma_ch)
5059 		rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable);
5060 }
5061 
5062 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable)
5063 {
5064 	if (rtwdev->hci.ops->ctrl_txdma_fw_ch)
5065 		rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable);
5066 }
5067 
5068 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable)
5069 {
5070 	if (rtwdev->hci.ops->ctrl_trxhci)
5071 		rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable);
5072 }
5073 
5074 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev)
5075 {
5076 	int ret = 0;
5077 
5078 	if (rtwdev->hci.ops->poll_txdma_ch)
5079 		ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev);
5080 	return ret;
5081 }
5082 
5083 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev)
5084 {
5085 	if (rtwdev->hci.ops->clr_idx_all)
5086 		rtwdev->hci.ops->clr_idx_all(rtwdev);
5087 }
5088 
5089 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev)
5090 {
5091 	int ret = 0;
5092 
5093 	if (rtwdev->hci.ops->rst_bdram)
5094 		ret = rtwdev->hci.ops->rst_bdram(rtwdev);
5095 	return ret;
5096 }
5097 
5098 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev)
5099 {
5100 	if (rtwdev->hci.ops->clear)
5101 		rtwdev->hci.ops->clear(rtwdev, pdev);
5102 }
5103 
5104 static inline
5105 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb)
5106 {
5107 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
5108 
5109 	return (struct rtw89_tx_skb_data *)info->status.status_driver_data;
5110 }
5111 
5112 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr)
5113 {
5114 	return rtwdev->hci.ops->read8(rtwdev, addr);
5115 }
5116 
5117 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr)
5118 {
5119 	return rtwdev->hci.ops->read16(rtwdev, addr);
5120 }
5121 
5122 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr)
5123 {
5124 	return rtwdev->hci.ops->read32(rtwdev, addr);
5125 }
5126 
5127 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data)
5128 {
5129 	rtwdev->hci.ops->write8(rtwdev, addr, data);
5130 }
5131 
5132 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data)
5133 {
5134 	rtwdev->hci.ops->write16(rtwdev, addr, data);
5135 }
5136 
5137 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data)
5138 {
5139 	rtwdev->hci.ops->write32(rtwdev, addr, data);
5140 }
5141 
5142 static inline void
5143 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5144 {
5145 	u8 val;
5146 
5147 	val = rtw89_read8(rtwdev, addr);
5148 	rtw89_write8(rtwdev, addr, val | bit);
5149 }
5150 
5151 static inline void
5152 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5153 {
5154 	u16 val;
5155 
5156 	val = rtw89_read16(rtwdev, addr);
5157 	rtw89_write16(rtwdev, addr, val | bit);
5158 }
5159 
5160 static inline void
5161 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5162 {
5163 	u32 val;
5164 
5165 	val = rtw89_read32(rtwdev, addr);
5166 	rtw89_write32(rtwdev, addr, val | bit);
5167 }
5168 
5169 static inline void
5170 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit)
5171 {
5172 	u8 val;
5173 
5174 	val = rtw89_read8(rtwdev, addr);
5175 	rtw89_write8(rtwdev, addr, val & ~bit);
5176 }
5177 
5178 static inline void
5179 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit)
5180 {
5181 	u16 val;
5182 
5183 	val = rtw89_read16(rtwdev, addr);
5184 	rtw89_write16(rtwdev, addr, val & ~bit);
5185 }
5186 
5187 static inline void
5188 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit)
5189 {
5190 	u32 val;
5191 
5192 	val = rtw89_read32(rtwdev, addr);
5193 	rtw89_write32(rtwdev, addr, val & ~bit);
5194 }
5195 
5196 static inline u32
5197 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5198 {
5199 	u32 shift = __ffs(mask);
5200 	u32 orig;
5201 	u32 ret;
5202 
5203 	orig = rtw89_read32(rtwdev, addr);
5204 	ret = (orig & mask) >> shift;
5205 
5206 	return ret;
5207 }
5208 
5209 static inline u16
5210 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5211 {
5212 	u32 shift = __ffs(mask);
5213 	u32 orig;
5214 	u32 ret;
5215 
5216 	orig = rtw89_read16(rtwdev, addr);
5217 	ret = (orig & mask) >> shift;
5218 
5219 	return ret;
5220 }
5221 
5222 static inline u8
5223 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask)
5224 {
5225 	u32 shift = __ffs(mask);
5226 	u32 orig;
5227 	u32 ret;
5228 
5229 	orig = rtw89_read8(rtwdev, addr);
5230 	ret = (orig & mask) >> shift;
5231 
5232 	return ret;
5233 }
5234 
5235 static inline void
5236 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data)
5237 {
5238 	u32 shift = __ffs(mask);
5239 	u32 orig;
5240 	u32 set;
5241 
5242 	WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr);
5243 
5244 	orig = rtw89_read32(rtwdev, addr);
5245 	set = (orig & ~mask) | ((data << shift) & mask);
5246 	rtw89_write32(rtwdev, addr, set);
5247 }
5248 
5249 static inline void
5250 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data)
5251 {
5252 	u32 shift;
5253 	u16 orig, set;
5254 
5255 	mask &= 0xffff;
5256 	shift = __ffs(mask);
5257 
5258 	orig = rtw89_read16(rtwdev, addr);
5259 	set = (orig & ~mask) | ((data << shift) & mask);
5260 	rtw89_write16(rtwdev, addr, set);
5261 }
5262 
5263 static inline void
5264 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data)
5265 {
5266 	u32 shift;
5267 	u8 orig, set;
5268 
5269 	mask &= 0xff;
5270 	shift = __ffs(mask);
5271 
5272 	orig = rtw89_read8(rtwdev, addr);
5273 	set = (orig & ~mask) | ((data << shift) & mask);
5274 	rtw89_write8(rtwdev, addr, set);
5275 }
5276 
5277 static inline u32
5278 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
5279 	      u32 addr, u32 mask)
5280 {
5281 	u32 val;
5282 
5283 	mutex_lock(&rtwdev->rf_mutex);
5284 	val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask);
5285 	mutex_unlock(&rtwdev->rf_mutex);
5286 
5287 	return val;
5288 }
5289 
5290 static inline void
5291 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
5292 	       u32 addr, u32 mask, u32 data)
5293 {
5294 	mutex_lock(&rtwdev->rf_mutex);
5295 	rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data);
5296 	mutex_unlock(&rtwdev->rf_mutex);
5297 }
5298 
5299 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq)
5300 {
5301 	void *p = rtwtxq;
5302 
5303 	return container_of(p, struct ieee80211_txq, drv_priv);
5304 }
5305 
5306 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev,
5307 				       struct ieee80211_txq *txq)
5308 {
5309 	struct rtw89_txq *rtwtxq;
5310 
5311 	if (!txq)
5312 		return;
5313 
5314 	rtwtxq = (struct rtw89_txq *)txq->drv_priv;
5315 	INIT_LIST_HEAD(&rtwtxq->list);
5316 }
5317 
5318 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif)
5319 {
5320 	void *p = rtwvif;
5321 
5322 	return container_of(p, struct ieee80211_vif, drv_priv);
5323 }
5324 
5325 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif)
5326 {
5327 	return rtwvif ? rtwvif_to_vif(rtwvif) : NULL;
5328 }
5329 
5330 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif)
5331 {
5332 	return vif ? (struct rtw89_vif *)vif->drv_priv : NULL;
5333 }
5334 
5335 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta)
5336 {
5337 	void *p = rtwsta;
5338 
5339 	return container_of(p, struct ieee80211_sta, drv_priv);
5340 }
5341 
5342 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta)
5343 {
5344 	return rtwsta ? rtwsta_to_sta(rtwsta) : NULL;
5345 }
5346 
5347 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta)
5348 {
5349 	return sta ? (struct rtw89_sta *)sta->drv_priv : NULL;
5350 }
5351 
5352 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw)
5353 {
5354 	if (hw_bw == RTW89_CHANNEL_WIDTH_160)
5355 		return RATE_INFO_BW_160;
5356 	else if (hw_bw == RTW89_CHANNEL_WIDTH_80)
5357 		return RATE_INFO_BW_80;
5358 	else if (hw_bw == RTW89_CHANNEL_WIDTH_40)
5359 		return RATE_INFO_BW_40;
5360 	else
5361 		return RATE_INFO_BW_20;
5362 }
5363 
5364 static inline
5365 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band)
5366 {
5367 	switch (hw_band) {
5368 	default:
5369 	case RTW89_BAND_2G:
5370 		return NL80211_BAND_2GHZ;
5371 	case RTW89_BAND_5G:
5372 		return NL80211_BAND_5GHZ;
5373 	case RTW89_BAND_6G:
5374 		return NL80211_BAND_6GHZ;
5375 	}
5376 }
5377 
5378 static inline
5379 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band)
5380 {
5381 	switch (nl_band) {
5382 	default:
5383 	case NL80211_BAND_2GHZ:
5384 		return RTW89_BAND_2G;
5385 	case NL80211_BAND_5GHZ:
5386 		return RTW89_BAND_5G;
5387 	case NL80211_BAND_6GHZ:
5388 		return RTW89_BAND_6G;
5389 	}
5390 }
5391 
5392 static inline
5393 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width)
5394 {
5395 	switch (width) {
5396 	default:
5397 		WARN(1, "Not support bandwidth %d\n", width);
5398 		fallthrough;
5399 	case NL80211_CHAN_WIDTH_20_NOHT:
5400 	case NL80211_CHAN_WIDTH_20:
5401 		return RTW89_CHANNEL_WIDTH_20;
5402 	case NL80211_CHAN_WIDTH_40:
5403 		return RTW89_CHANNEL_WIDTH_40;
5404 	case NL80211_CHAN_WIDTH_80:
5405 		return RTW89_CHANNEL_WIDTH_80;
5406 	case NL80211_CHAN_WIDTH_160:
5407 		return RTW89_CHANNEL_WIDTH_160;
5408 	}
5409 }
5410 
5411 static inline
5412 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua)
5413 {
5414 	switch (rua) {
5415 	default:
5416 		WARN(1, "Invalid RU allocation: %d\n", rua);
5417 		fallthrough;
5418 	case 0 ... 36:
5419 		return NL80211_RATE_INFO_HE_RU_ALLOC_26;
5420 	case 37 ... 52:
5421 		return NL80211_RATE_INFO_HE_RU_ALLOC_52;
5422 	case 53 ... 60:
5423 		return NL80211_RATE_INFO_HE_RU_ALLOC_106;
5424 	case 61 ... 64:
5425 		return NL80211_RATE_INFO_HE_RU_ALLOC_242;
5426 	case 65 ... 66:
5427 		return NL80211_RATE_INFO_HE_RU_ALLOC_484;
5428 	case 67:
5429 		return NL80211_RATE_INFO_HE_RU_ALLOC_996;
5430 	case 68:
5431 		return NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
5432 	}
5433 }
5434 
5435 static inline
5436 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif,
5437 						   struct rtw89_sta *rtwsta)
5438 {
5439 	if (rtwsta) {
5440 		struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
5441 
5442 		if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls)
5443 			return &rtwsta->addr_cam;
5444 	}
5445 	return &rtwvif->addr_cam;
5446 }
5447 
5448 static inline
5449 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif,
5450 						     struct rtw89_sta *rtwsta)
5451 {
5452 	if (rtwsta) {
5453 		struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta);
5454 
5455 		if (sta->tdls)
5456 			return &rtwsta->bssid_cam;
5457 	}
5458 	return &rtwvif->bssid_cam;
5459 }
5460 
5461 static inline
5462 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev,
5463 				    struct rtw89_channel_help_params *p,
5464 				    const struct rtw89_chan *chan,
5465 				    enum rtw89_mac_idx mac_idx,
5466 				    enum rtw89_phy_idx phy_idx)
5467 {
5468 	rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan,
5469 					    mac_idx, phy_idx);
5470 }
5471 
5472 static inline
5473 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev,
5474 				 struct rtw89_channel_help_params *p,
5475 				 const struct rtw89_chan *chan,
5476 				 enum rtw89_mac_idx mac_idx,
5477 				 enum rtw89_phy_idx phy_idx)
5478 {
5479 	rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan,
5480 					    mac_idx, phy_idx);
5481 }
5482 
5483 static inline
5484 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev,
5485 						  enum rtw89_sub_entity_idx idx)
5486 {
5487 	struct rtw89_hal *hal = &rtwdev->hal;
5488 	enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx);
5489 
5490 	if (roc_idx == idx)
5491 		return &hal->roc_chandef;
5492 
5493 	return &hal->sub[idx].chandef;
5494 }
5495 
5496 static inline
5497 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev,
5498 					enum rtw89_sub_entity_idx idx)
5499 {
5500 	struct rtw89_hal *hal = &rtwdev->hal;
5501 
5502 	return &hal->sub[idx].chan;
5503 }
5504 
5505 static inline
5506 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev,
5507 						enum rtw89_sub_entity_idx idx)
5508 {
5509 	struct rtw89_hal *hal = &rtwdev->hal;
5510 
5511 	return &hal->sub[idx].rcd;
5512 }
5513 
5514 static inline
5515 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev)
5516 {
5517 	struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif;
5518 	struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif);
5519 
5520 	if (rtwvif)
5521 		return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx);
5522 	else
5523 		return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
5524 }
5525 
5526 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev)
5527 {
5528 	const struct rtw89_chip_info *chip = rtwdev->chip;
5529 
5530 	if (chip->ops->fem_setup)
5531 		chip->ops->fem_setup(rtwdev);
5532 }
5533 
5534 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev)
5535 {
5536 	const struct rtw89_chip_info *chip = rtwdev->chip;
5537 
5538 	if (chip->ops->rfe_gpio)
5539 		chip->ops->rfe_gpio(rtwdev);
5540 }
5541 
5542 static inline
5543 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx)
5544 {
5545 	const struct rtw89_chip_info *chip = rtwdev->chip;
5546 
5547 	if (chip->ops->bb_preinit)
5548 		chip->ops->bb_preinit(rtwdev, phy_idx);
5549 }
5550 
5551 static inline
5552 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev)
5553 {
5554 	const struct rtw89_chip_info *chip = rtwdev->chip;
5555 
5556 	if (!chip->ops->bb_postinit)
5557 		return;
5558 
5559 	chip->ops->bb_postinit(rtwdev, RTW89_PHY_0);
5560 
5561 	if (rtwdev->dbcc_en)
5562 		chip->ops->bb_postinit(rtwdev, RTW89_PHY_1);
5563 }
5564 
5565 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev)
5566 {
5567 	const struct rtw89_chip_info *chip = rtwdev->chip;
5568 
5569 	if (chip->ops->bb_sethw)
5570 		chip->ops->bb_sethw(rtwdev);
5571 }
5572 
5573 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev)
5574 {
5575 	const struct rtw89_chip_info *chip = rtwdev->chip;
5576 
5577 	if (chip->ops->rfk_init)
5578 		chip->ops->rfk_init(rtwdev);
5579 }
5580 
5581 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev)
5582 {
5583 	const struct rtw89_chip_info *chip = rtwdev->chip;
5584 
5585 	if (chip->ops->rfk_channel)
5586 		chip->ops->rfk_channel(rtwdev);
5587 }
5588 
5589 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev,
5590 					       enum rtw89_phy_idx phy_idx)
5591 {
5592 	const struct rtw89_chip_info *chip = rtwdev->chip;
5593 
5594 	if (chip->ops->rfk_band_changed)
5595 		chip->ops->rfk_band_changed(rtwdev, phy_idx);
5596 }
5597 
5598 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start)
5599 {
5600 	const struct rtw89_chip_info *chip = rtwdev->chip;
5601 
5602 	if (chip->ops->rfk_scan)
5603 		chip->ops->rfk_scan(rtwdev, start);
5604 }
5605 
5606 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev)
5607 {
5608 	const struct rtw89_chip_info *chip = rtwdev->chip;
5609 
5610 	if (chip->ops->rfk_track)
5611 		chip->ops->rfk_track(rtwdev);
5612 }
5613 
5614 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev)
5615 {
5616 	const struct rtw89_chip_info *chip = rtwdev->chip;
5617 
5618 	if (chip->ops->set_txpwr_ctrl)
5619 		chip->ops->set_txpwr_ctrl(rtwdev,  RTW89_PHY_0);
5620 }
5621 
5622 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev)
5623 {
5624 	const struct rtw89_chip_info *chip = rtwdev->chip;
5625 
5626 	if (chip->ops->power_trim)
5627 		chip->ops->power_trim(rtwdev);
5628 }
5629 
5630 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev,
5631 					      enum rtw89_phy_idx phy_idx)
5632 {
5633 	const struct rtw89_chip_info *chip = rtwdev->chip;
5634 
5635 	if (chip->ops->init_txpwr_unit)
5636 		chip->ops->init_txpwr_unit(rtwdev, phy_idx);
5637 }
5638 
5639 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev,
5640 					enum rtw89_rf_path rf_path)
5641 {
5642 	const struct rtw89_chip_info *chip = rtwdev->chip;
5643 
5644 	if (!chip->ops->get_thermal)
5645 		return 0x10;
5646 
5647 	return chip->ops->get_thermal(rtwdev, rf_path);
5648 }
5649 
5650 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev,
5651 					 struct rtw89_rx_phy_ppdu *phy_ppdu,
5652 					 struct ieee80211_rx_status *status)
5653 {
5654 	const struct rtw89_chip_info *chip = rtwdev->chip;
5655 
5656 	if (chip->ops->query_ppdu)
5657 		chip->ops->query_ppdu(rtwdev, phy_ppdu, status);
5658 }
5659 
5660 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en,
5661 					 enum rtw89_phy_idx phy_idx)
5662 {
5663 	const struct rtw89_chip_info *chip = rtwdev->chip;
5664 
5665 	if (chip->ops->ctrl_nbtg_bt_tx)
5666 		chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx);
5667 }
5668 
5669 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev)
5670 {
5671 	const struct rtw89_chip_info *chip = rtwdev->chip;
5672 
5673 	if (chip->ops->cfg_txrx_path)
5674 		chip->ops->cfg_txrx_path(rtwdev);
5675 }
5676 
5677 static inline
5678 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
5679 				       struct ieee80211_vif *vif)
5680 {
5681 	struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
5682 	const struct rtw89_chip_info *chip = rtwdev->chip;
5683 
5684 	if (!vif->bss_conf.he_support || !vif->cfg.assoc)
5685 		return;
5686 
5687 	if (chip->ops->set_txpwr_ul_tb_offset)
5688 		chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx);
5689 }
5690 
5691 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev,
5692 					  const struct rtw89_txpwr_table *tbl)
5693 {
5694 	tbl->load(rtwdev, tbl);
5695 }
5696 
5697 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band)
5698 {
5699 	const struct rtw89_regd *regd = rtwdev->regulatory.regd;
5700 
5701 	return regd->txpwr_regd[band];
5702 }
5703 
5704 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en,
5705 					enum rtw89_phy_idx phy_idx)
5706 {
5707 	const struct rtw89_chip_info *chip = rtwdev->chip;
5708 
5709 	if (chip->ops->ctrl_btg_bt_rx)
5710 		chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx);
5711 }
5712 
5713 static inline
5714 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev,
5715 			     struct rtw89_rx_desc_info *desc_info,
5716 			     u8 *data, u32 data_offset)
5717 {
5718 	const struct rtw89_chip_info *chip = rtwdev->chip;
5719 
5720 	chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset);
5721 }
5722 
5723 static inline
5724 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev,
5725 			    struct rtw89_tx_desc_info *desc_info,
5726 			    void *txdesc)
5727 {
5728 	const struct rtw89_chip_info *chip = rtwdev->chip;
5729 
5730 	chip->ops->fill_txdesc(rtwdev, desc_info, txdesc);
5731 }
5732 
5733 static inline
5734 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev,
5735 				  struct rtw89_tx_desc_info *desc_info,
5736 				  void *txdesc)
5737 {
5738 	const struct rtw89_chip_info *chip = rtwdev->chip;
5739 
5740 	chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc);
5741 }
5742 
5743 static inline
5744 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev,
5745 			    const struct rtw89_mac_ax_coex_gnt *gnt_cfg)
5746 {
5747 	const struct rtw89_chip_info *chip = rtwdev->chip;
5748 
5749 	chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg);
5750 }
5751 
5752 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl)
5753 {
5754 	const struct rtw89_chip_info *chip = rtwdev->chip;
5755 
5756 	chip->ops->cfg_ctrl_path(rtwdev, wl);
5757 }
5758 
5759 static inline
5760 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx,
5761 			   u32 *tx_en, enum rtw89_sch_tx_sel sel)
5762 {
5763 	const struct rtw89_chip_info *chip = rtwdev->chip;
5764 
5765 	return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel);
5766 }
5767 
5768 static inline
5769 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en)
5770 {
5771 	const struct rtw89_chip_info *chip = rtwdev->chip;
5772 
5773 	return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en);
5774 }
5775 
5776 static inline
5777 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev,
5778 				struct rtw89_vif *rtwvif,
5779 				struct rtw89_sta *rtwsta)
5780 {
5781 	const struct rtw89_chip_info *chip = rtwdev->chip;
5782 
5783 	if (!chip->ops->h2c_dctl_sec_cam)
5784 		return 0;
5785 	return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta);
5786 }
5787 
5788 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr)
5789 {
5790 	__le16 fc = hdr->frame_control;
5791 
5792 	if (ieee80211_has_tods(fc))
5793 		return hdr->addr1;
5794 	else if (ieee80211_has_fromds(fc))
5795 		return hdr->addr2;
5796 	else
5797 		return hdr->addr3;
5798 }
5799 
5800 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta)
5801 {
5802 	if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) ||
5803 	    (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) ||
5804 	    (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] &
5805 			IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) ||
5806 	    (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] &
5807 			IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER))
5808 		return true;
5809 	return false;
5810 }
5811 
5812 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev,
5813 						      enum rtw89_fw_type type)
5814 {
5815 	struct rtw89_fw_info *fw_info = &rtwdev->fw;
5816 
5817 	switch (type) {
5818 	case RTW89_FW_WOWLAN:
5819 		return &fw_info->wowlan;
5820 	case RTW89_FW_LOGFMT:
5821 		return &fw_info->log.suit;
5822 	case RTW89_FW_BBMCU0:
5823 		return &fw_info->bbmcu0;
5824 	case RTW89_FW_BBMCU1:
5825 		return &fw_info->bbmcu1;
5826 	default:
5827 		break;
5828 	}
5829 
5830 	return &fw_info->normal;
5831 }
5832 
5833 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev,
5834 						     unsigned int length)
5835 {
5836 	struct sk_buff *skb;
5837 
5838 	if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
5839 		skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM);
5840 		if (!skb)
5841 			return NULL;
5842 
5843 		skb_reserve(skb, RTW89_RADIOTAP_ROOM);
5844 		return skb;
5845 	}
5846 
5847 	return dev_alloc_skb(length);
5848 }
5849 
5850 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev,
5851 					       struct rtw89_tx_skb_data *skb_data,
5852 					       bool tx_done)
5853 {
5854 	struct rtw89_tx_wait_info *wait;
5855 
5856 	rcu_read_lock();
5857 
5858 	wait = rcu_dereference(skb_data->wait);
5859 	if (!wait)
5860 		goto out;
5861 
5862 	wait->tx_done = tx_done;
5863 	complete(&wait->completion);
5864 
5865 out:
5866 	rcu_read_unlock();
5867 }
5868 
5869 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev)
5870 {
5871 	switch (rtwdev->mlo_dbcc_mode) {
5872 	case MLO_1_PLUS_1_1RF:
5873 	case MLO_1_PLUS_1_2RF:
5874 	case DBCC_LEGACY:
5875 		return true;
5876 	default:
5877 		return false;
5878 	}
5879 }
5880 
5881 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
5882 			struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel);
5883 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
5884 		 struct sk_buff *skb, bool fwdl);
5885 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel);
5886 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
5887 				    int qsel, unsigned int timeout);
5888 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
5889 			    struct rtw89_tx_desc_info *desc_info,
5890 			    void *txdesc);
5891 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
5892 			       struct rtw89_tx_desc_info *desc_info,
5893 			       void *txdesc);
5894 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
5895 			       struct rtw89_tx_desc_info *desc_info,
5896 			       void *txdesc);
5897 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
5898 				     struct rtw89_tx_desc_info *desc_info,
5899 				     void *txdesc);
5900 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
5901 				     struct rtw89_tx_desc_info *desc_info,
5902 				     void *txdesc);
5903 void rtw89_core_rx(struct rtw89_dev *rtwdev,
5904 		   struct rtw89_rx_desc_info *desc_info,
5905 		   struct sk_buff *skb);
5906 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
5907 			     struct rtw89_rx_desc_info *desc_info,
5908 			     u8 *data, u32 data_offset);
5909 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
5910 				struct rtw89_rx_desc_info *desc_info,
5911 				u8 *data, u32 data_offset);
5912 void rtw89_core_napi_start(struct rtw89_dev *rtwdev);
5913 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev);
5914 void rtw89_core_napi_init(struct rtw89_dev *rtwdev);
5915 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev);
5916 int rtw89_core_sta_add(struct rtw89_dev *rtwdev,
5917 		       struct ieee80211_vif *vif,
5918 		       struct ieee80211_sta *sta);
5919 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev,
5920 			 struct ieee80211_vif *vif,
5921 			 struct ieee80211_sta *sta);
5922 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev,
5923 			    struct ieee80211_vif *vif,
5924 			    struct ieee80211_sta *sta);
5925 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev,
5926 			      struct ieee80211_vif *vif,
5927 			      struct ieee80211_sta *sta);
5928 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev,
5929 			  struct ieee80211_vif *vif,
5930 			  struct ieee80211_sta *sta);
5931 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
5932 			       struct ieee80211_sta *sta,
5933 			       struct cfg80211_tid_config *tid_config);
5934 int rtw89_core_init(struct rtw89_dev *rtwdev);
5935 void rtw89_core_deinit(struct rtw89_dev *rtwdev);
5936 int rtw89_core_register(struct rtw89_dev *rtwdev);
5937 void rtw89_core_unregister(struct rtw89_dev *rtwdev);
5938 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
5939 					   u32 bus_data_size,
5940 					   const struct rtw89_chip_info *chip);
5941 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev);
5942 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev);
5943 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef);
5944 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
5945 			      struct rtw89_chan *chan);
5946 void rtw89_set_channel(struct rtw89_dev *rtwdev);
5947 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5948 		       struct rtw89_chan *chan);
5949 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size);
5950 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit);
5951 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits);
5952 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
5953 				    struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
5954 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
5955 				    struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx);
5956 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc);
5957 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev);
5958 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate);
5959 int rtw89_regd_setup(struct rtw89_dev *rtwdev);
5960 int rtw89_regd_init(struct rtw89_dev *rtwdev,
5961 		    void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request));
5962 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request);
5963 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
5964 			      struct rtw89_traffic_stats *stats);
5965 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond);
5966 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
5967 			 const struct rtw89_completion_data *data);
5968 int rtw89_core_start(struct rtw89_dev *rtwdev);
5969 void rtw89_core_stop(struct rtw89_dev *rtwdev);
5970 void rtw89_core_update_beacon_work(struct work_struct *work);
5971 void rtw89_roc_work(struct work_struct *work);
5972 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5973 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif);
5974 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5975 			   const u8 *mac_addr, bool hw_scan);
5976 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
5977 			      struct ieee80211_vif *vif, bool hw_scan);
5978 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev,
5979 				 struct rtw89_vif *rtwvif, bool active);
5980 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif);
5981 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event);
5982 
5983 #endif
5984