1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_fw_blacklist; 21 struct rtw89_efuse_block_cfg; 22 struct rtw89_h2c_rf_tssi; 23 struct rtw89_fw_txpwr_track_cfg; 24 struct rtw89_phy_rfk_log_fmt; 25 struct rtw89_debugfs; 26 struct rtw89_regd_data; 27 28 extern const struct ieee80211_ops rtw89_ops; 29 30 #define MASKBYTE0 0xff 31 #define MASKBYTE1 0xff00 32 #define MASKBYTE2 0xff0000 33 #define MASKBYTE3 0xff000000 34 #define MASKBYTE4 0xff00000000ULL 35 #define MASKHWORD 0xffff0000 36 #define MASKLWORD 0x0000ffff 37 #define MASKDWORD 0xffffffff 38 #define RFREG_MASK 0xfffff 39 #define INV_RF_DATA 0xffffffff 40 #define BYPASS_CR_DATA 0xbabecafe 41 42 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 43 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 44 #define CFO_TRACK_MAX_USER 64 45 #define MAX_RSSI 110 46 #define RSSI_FACTOR 1 47 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 48 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 49 #define DELTA_SWINGIDX_SIZE 30 50 51 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 52 #define RTW89_RADIOTAP_ROOM_EHT \ 53 (sizeof(struct ieee80211_radiotap_tlv) + \ 54 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 55 sizeof(struct ieee80211_radiotap_tlv) + \ 56 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 57 #define RTW89_RADIOTAP_ROOM \ 58 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 59 60 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 61 #define RTW89_HTC_VARIANT_HE 3 62 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 63 #define RTW89_HTC_VARIANT_HE_CID_OM 1 64 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 65 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 66 67 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 68 enum htc_om_channel_width { 69 HTC_OM_CHANNEL_WIDTH_20 = 0, 70 HTC_OM_CHANNEL_WIDTH_40 = 1, 71 HTC_OM_CHANNEL_WIDTH_80 = 2, 72 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 73 }; 74 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 75 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 76 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 77 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 78 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 79 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 80 81 #define RTW89_TF_PAD GENMASK(11, 0) 82 #define RTW89_TF_BASIC_USER_INFO_SZ 6 83 84 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 86 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 87 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 88 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 89 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 90 91 enum rtw89_subband { 92 RTW89_CH_2G = 0, 93 RTW89_CH_5G_BAND_1 = 1, 94 /* RTW89_CH_5G_BAND_2 = 2, unused */ 95 RTW89_CH_5G_BAND_3 = 3, 96 RTW89_CH_5G_BAND_4 = 4, 97 98 RTW89_CH_6G_BAND_IDX0, /* Low */ 99 RTW89_CH_6G_BAND_IDX1, /* Low */ 100 RTW89_CH_6G_BAND_IDX2, /* Mid */ 101 RTW89_CH_6G_BAND_IDX3, /* Mid */ 102 RTW89_CH_6G_BAND_IDX4, /* High */ 103 RTW89_CH_6G_BAND_IDX5, /* High */ 104 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 105 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 106 107 RTW89_SUBBAND_NR, 108 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 109 }; 110 111 enum rtw89_gain_offset { 112 RTW89_GAIN_OFFSET_2G_CCK, 113 RTW89_GAIN_OFFSET_2G_OFDM, 114 RTW89_GAIN_OFFSET_5G_LOW, 115 RTW89_GAIN_OFFSET_5G_MID, 116 RTW89_GAIN_OFFSET_5G_HIGH, 117 RTW89_GAIN_OFFSET_6G_L0, 118 RTW89_GAIN_OFFSET_6G_L1, 119 RTW89_GAIN_OFFSET_6G_M0, 120 RTW89_GAIN_OFFSET_6G_M1, 121 RTW89_GAIN_OFFSET_6G_H0, 122 RTW89_GAIN_OFFSET_6G_H1, 123 RTW89_GAIN_OFFSET_6G_UH0, 124 RTW89_GAIN_OFFSET_6G_UH1, 125 126 RTW89_GAIN_OFFSET_NR, 127 }; 128 129 enum rtw89_hci_type { 130 RTW89_HCI_TYPE_PCIE, 131 RTW89_HCI_TYPE_USB, 132 RTW89_HCI_TYPE_SDIO, 133 }; 134 135 enum rtw89_core_chip_id { 136 RTL8852A, 137 RTL8852B, 138 RTL8852BT, 139 RTL8852C, 140 RTL8851B, 141 RTL8922A, 142 }; 143 144 enum rtw89_chip_gen { 145 RTW89_CHIP_AX, 146 RTW89_CHIP_BE, 147 148 RTW89_CHIP_GEN_NUM, 149 }; 150 151 enum rtw89_cv { 152 CHIP_CAV, 153 CHIP_CBV, 154 CHIP_CCV, 155 CHIP_CDV, 156 CHIP_CEV, 157 CHIP_CFV, 158 CHIP_CV_MAX, 159 CHIP_CV_INVALID = CHIP_CV_MAX, 160 }; 161 162 enum rtw89_bacam_ver { 163 RTW89_BACAM_V0, 164 RTW89_BACAM_V1, 165 166 RTW89_BACAM_V0_EXT = 99, 167 }; 168 169 enum rtw89_core_tx_type { 170 RTW89_CORE_TX_TYPE_DATA, 171 RTW89_CORE_TX_TYPE_MGMT, 172 RTW89_CORE_TX_TYPE_FWCMD, 173 }; 174 175 enum rtw89_core_rx_type { 176 RTW89_CORE_RX_TYPE_WIFI = 0, 177 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 178 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 179 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 180 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 181 RTW89_CORE_RX_TYPE_SS2FW = 5, 182 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 183 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 184 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 185 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 186 RTW89_CORE_RX_TYPE_C2H = 10, 187 RTW89_CORE_RX_TYPE_CSI = 11, 188 RTW89_CORE_RX_TYPE_CQI = 12, 189 RTW89_CORE_RX_TYPE_H2C = 13, 190 RTW89_CORE_RX_TYPE_FWDL = 14, 191 }; 192 193 enum rtw89_txq_flags { 194 RTW89_TXQ_F_AMPDU = 0, 195 RTW89_TXQ_F_BLOCK_BA = 1, 196 RTW89_TXQ_F_FORBID_BA = 2, 197 }; 198 199 enum rtw89_net_type { 200 RTW89_NET_TYPE_NO_LINK = 0, 201 RTW89_NET_TYPE_AD_HOC = 1, 202 RTW89_NET_TYPE_INFRA = 2, 203 RTW89_NET_TYPE_AP_MODE = 3, 204 }; 205 206 enum rtw89_wifi_role { 207 RTW89_WIFI_ROLE_NONE, 208 RTW89_WIFI_ROLE_STATION, 209 RTW89_WIFI_ROLE_AP, 210 RTW89_WIFI_ROLE_AP_VLAN, 211 RTW89_WIFI_ROLE_ADHOC, 212 RTW89_WIFI_ROLE_ADHOC_MASTER, 213 RTW89_WIFI_ROLE_MESH_POINT, 214 RTW89_WIFI_ROLE_MONITOR, 215 RTW89_WIFI_ROLE_P2P_DEVICE, 216 RTW89_WIFI_ROLE_P2P_CLIENT, 217 RTW89_WIFI_ROLE_P2P_GO, 218 RTW89_WIFI_ROLE_NAN, 219 RTW89_WIFI_ROLE_MLME_MAX 220 }; 221 222 enum rtw89_upd_mode { 223 RTW89_ROLE_CREATE, 224 RTW89_ROLE_REMOVE, 225 RTW89_ROLE_TYPE_CHANGE, 226 RTW89_ROLE_INFO_CHANGE, 227 RTW89_ROLE_CON_DISCONN, 228 RTW89_ROLE_BAND_SW, 229 RTW89_ROLE_FW_RESTORE, 230 }; 231 232 enum rtw89_self_role { 233 RTW89_SELF_ROLE_CLIENT, 234 RTW89_SELF_ROLE_AP, 235 RTW89_SELF_ROLE_AP_CLIENT 236 }; 237 238 enum rtw89_msk_sO_el { 239 RTW89_NO_MSK, 240 RTW89_SMA, 241 RTW89_TMA, 242 RTW89_BSSID 243 }; 244 245 enum rtw89_sch_tx_sel { 246 RTW89_SCH_TX_SEL_ALL, 247 RTW89_SCH_TX_SEL_HIQ, 248 RTW89_SCH_TX_SEL_MG0, 249 RTW89_SCH_TX_SEL_MACID, 250 }; 251 252 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 253 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 254 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 255 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 256 */ 257 enum rtw89_add_cam_sec_mode { 258 RTW89_ADDR_CAM_SEC_NONE = 0, 259 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 260 RTW89_ADDR_CAM_SEC_NORMAL = 2, 261 RTW89_ADDR_CAM_SEC_4GROUP = 3, 262 }; 263 264 enum rtw89_sec_key_type { 265 RTW89_SEC_KEY_TYPE_NONE = 0, 266 RTW89_SEC_KEY_TYPE_WEP40 = 1, 267 RTW89_SEC_KEY_TYPE_WEP104 = 2, 268 RTW89_SEC_KEY_TYPE_TKIP = 3, 269 RTW89_SEC_KEY_TYPE_WAPI = 4, 270 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 271 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 272 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 273 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 274 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 275 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 276 }; 277 278 enum rtw89_port { 279 RTW89_PORT_0 = 0, 280 RTW89_PORT_1 = 1, 281 RTW89_PORT_2 = 2, 282 RTW89_PORT_3 = 3, 283 RTW89_PORT_4 = 4, 284 RTW89_PORT_NUM 285 }; 286 287 enum rtw89_band { 288 RTW89_BAND_2G = 0, 289 RTW89_BAND_5G = 1, 290 RTW89_BAND_6G = 2, 291 RTW89_BAND_NUM, 292 }; 293 294 enum rtw89_hw_rate { 295 RTW89_HW_RATE_CCK1 = 0x0, 296 RTW89_HW_RATE_CCK2 = 0x1, 297 RTW89_HW_RATE_CCK5_5 = 0x2, 298 RTW89_HW_RATE_CCK11 = 0x3, 299 RTW89_HW_RATE_OFDM6 = 0x4, 300 RTW89_HW_RATE_OFDM9 = 0x5, 301 RTW89_HW_RATE_OFDM12 = 0x6, 302 RTW89_HW_RATE_OFDM18 = 0x7, 303 RTW89_HW_RATE_OFDM24 = 0x8, 304 RTW89_HW_RATE_OFDM36 = 0x9, 305 RTW89_HW_RATE_OFDM48 = 0xA, 306 RTW89_HW_RATE_OFDM54 = 0xB, 307 RTW89_HW_RATE_MCS0 = 0x80, 308 RTW89_HW_RATE_MCS1 = 0x81, 309 RTW89_HW_RATE_MCS2 = 0x82, 310 RTW89_HW_RATE_MCS3 = 0x83, 311 RTW89_HW_RATE_MCS4 = 0x84, 312 RTW89_HW_RATE_MCS5 = 0x85, 313 RTW89_HW_RATE_MCS6 = 0x86, 314 RTW89_HW_RATE_MCS7 = 0x87, 315 RTW89_HW_RATE_MCS8 = 0x88, 316 RTW89_HW_RATE_MCS9 = 0x89, 317 RTW89_HW_RATE_MCS10 = 0x8A, 318 RTW89_HW_RATE_MCS11 = 0x8B, 319 RTW89_HW_RATE_MCS12 = 0x8C, 320 RTW89_HW_RATE_MCS13 = 0x8D, 321 RTW89_HW_RATE_MCS14 = 0x8E, 322 RTW89_HW_RATE_MCS15 = 0x8F, 323 RTW89_HW_RATE_MCS16 = 0x90, 324 RTW89_HW_RATE_MCS17 = 0x91, 325 RTW89_HW_RATE_MCS18 = 0x92, 326 RTW89_HW_RATE_MCS19 = 0x93, 327 RTW89_HW_RATE_MCS20 = 0x94, 328 RTW89_HW_RATE_MCS21 = 0x95, 329 RTW89_HW_RATE_MCS22 = 0x96, 330 RTW89_HW_RATE_MCS23 = 0x97, 331 RTW89_HW_RATE_MCS24 = 0x98, 332 RTW89_HW_RATE_MCS25 = 0x99, 333 RTW89_HW_RATE_MCS26 = 0x9A, 334 RTW89_HW_RATE_MCS27 = 0x9B, 335 RTW89_HW_RATE_MCS28 = 0x9C, 336 RTW89_HW_RATE_MCS29 = 0x9D, 337 RTW89_HW_RATE_MCS30 = 0x9E, 338 RTW89_HW_RATE_MCS31 = 0x9F, 339 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 340 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 341 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 342 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 343 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 344 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 345 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 346 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 347 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 348 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 349 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 350 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 351 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 352 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 353 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 354 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 355 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 356 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 357 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 358 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 359 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 360 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 361 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 362 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 363 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 364 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 365 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 366 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 367 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 368 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 369 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 370 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 371 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 372 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 373 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 374 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 375 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 376 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 377 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 378 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 379 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 380 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 381 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 382 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 383 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 384 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 385 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 386 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 387 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 388 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 389 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 390 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 391 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 392 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 393 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 394 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 395 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 396 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 397 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 398 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 399 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 400 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 401 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 402 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 403 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 404 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 405 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 406 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 407 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 408 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 409 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 410 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 411 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 412 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 413 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 414 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 415 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 416 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 417 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 418 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 419 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 420 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 421 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 422 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 423 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 424 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 425 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 426 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 427 428 RTW89_HW_RATE_V1_MCS0 = 0x100, 429 RTW89_HW_RATE_V1_MCS1 = 0x101, 430 RTW89_HW_RATE_V1_MCS2 = 0x102, 431 RTW89_HW_RATE_V1_MCS3 = 0x103, 432 RTW89_HW_RATE_V1_MCS4 = 0x104, 433 RTW89_HW_RATE_V1_MCS5 = 0x105, 434 RTW89_HW_RATE_V1_MCS6 = 0x106, 435 RTW89_HW_RATE_V1_MCS7 = 0x107, 436 RTW89_HW_RATE_V1_MCS8 = 0x108, 437 RTW89_HW_RATE_V1_MCS9 = 0x109, 438 RTW89_HW_RATE_V1_MCS10 = 0x10A, 439 RTW89_HW_RATE_V1_MCS11 = 0x10B, 440 RTW89_HW_RATE_V1_MCS12 = 0x10C, 441 RTW89_HW_RATE_V1_MCS13 = 0x10D, 442 RTW89_HW_RATE_V1_MCS14 = 0x10E, 443 RTW89_HW_RATE_V1_MCS15 = 0x10F, 444 RTW89_HW_RATE_V1_MCS16 = 0x110, 445 RTW89_HW_RATE_V1_MCS17 = 0x111, 446 RTW89_HW_RATE_V1_MCS18 = 0x112, 447 RTW89_HW_RATE_V1_MCS19 = 0x113, 448 RTW89_HW_RATE_V1_MCS20 = 0x114, 449 RTW89_HW_RATE_V1_MCS21 = 0x115, 450 RTW89_HW_RATE_V1_MCS22 = 0x116, 451 RTW89_HW_RATE_V1_MCS23 = 0x117, 452 RTW89_HW_RATE_V1_MCS24 = 0x118, 453 RTW89_HW_RATE_V1_MCS25 = 0x119, 454 RTW89_HW_RATE_V1_MCS26 = 0x11A, 455 RTW89_HW_RATE_V1_MCS27 = 0x11B, 456 RTW89_HW_RATE_V1_MCS28 = 0x11C, 457 RTW89_HW_RATE_V1_MCS29 = 0x11D, 458 RTW89_HW_RATE_V1_MCS30 = 0x11E, 459 RTW89_HW_RATE_V1_MCS31 = 0x11F, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 469 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 470 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 471 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 481 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 482 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 483 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 493 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 494 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 495 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 505 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 506 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 507 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 517 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 518 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 519 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 529 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 530 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 531 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 541 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 542 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 543 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 553 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 554 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 555 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 570 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 571 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 583 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 584 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 585 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 597 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 598 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 599 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 611 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 612 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 613 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 614 615 RTW89_HW_RATE_NR, 616 RTW89_HW_RATE_INVAL, 617 618 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 619 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 620 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 621 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 622 }; 623 624 /* 2G channels, 625 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 626 */ 627 #define RTW89_2G_CH_NUM 14 628 629 /* 5G channels, 630 * 36, 38, 40, 42, 44, 46, 48, 50, 631 * 52, 54, 56, 58, 60, 62, 64, 632 * 100, 102, 104, 106, 108, 110, 112, 114, 633 * 116, 118, 120, 122, 124, 126, 128, 130, 634 * 132, 134, 136, 138, 140, 142, 144, 635 * 149, 151, 153, 155, 157, 159, 161, 163, 636 * 165, 167, 169, 171, 173, 175, 177 637 */ 638 #define RTW89_5G_CH_NUM 53 639 640 /* 6G channels, 641 * 1, 3, 5, 7, 9, 11, 13, 15, 642 * 17, 19, 21, 23, 25, 27, 29, 33, 643 * 35, 37, 39, 41, 43, 45, 47, 49, 644 * 51, 53, 55, 57, 59, 61, 65, 67, 645 * 69, 71, 73, 75, 77, 79, 81, 83, 646 * 85, 87, 89, 91, 93, 97, 99, 101, 647 * 103, 105, 107, 109, 111, 113, 115, 117, 648 * 119, 121, 123, 125, 129, 131, 133, 135, 649 * 137, 139, 141, 143, 145, 147, 149, 151, 650 * 153, 155, 157, 161, 163, 165, 167, 169, 651 * 171, 173, 175, 177, 179, 181, 183, 185, 652 * 187, 189, 193, 195, 197, 199, 201, 203, 653 * 205, 207, 209, 211, 213, 215, 217, 219, 654 * 221, 225, 227, 229, 231, 233, 235, 237, 655 * 239, 241, 243, 245, 247, 249, 251, 253, 656 */ 657 #define RTW89_6G_CH_NUM 120 658 659 enum rtw89_rate_section { 660 RTW89_RS_CCK, 661 RTW89_RS_OFDM, 662 RTW89_RS_MCS, /* for HT/VHT/HE */ 663 RTW89_RS_HEDCM, 664 RTW89_RS_OFFSET, 665 RTW89_RS_NUM, 666 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 667 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 668 }; 669 670 enum rtw89_rate_offset_indexes { 671 RTW89_RATE_OFFSET_HE, 672 RTW89_RATE_OFFSET_VHT, 673 RTW89_RATE_OFFSET_HT, 674 RTW89_RATE_OFFSET_OFDM, 675 RTW89_RATE_OFFSET_CCK, 676 RTW89_RATE_OFFSET_DLRU_EHT, 677 RTW89_RATE_OFFSET_DLRU_HE, 678 RTW89_RATE_OFFSET_EHT, 679 __RTW89_RATE_OFFSET_NUM, 680 681 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 682 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 683 }; 684 685 enum rtw89_rate_num { 686 RTW89_RATE_CCK_NUM = 4, 687 RTW89_RATE_OFDM_NUM = 8, 688 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 689 690 RTW89_RATE_MCS_NUM_AX = 12, 691 RTW89_RATE_MCS_NUM_BE = 16, 692 __RTW89_RATE_MCS_NUM = 16, 693 }; 694 695 enum rtw89_nss { 696 RTW89_NSS_1 = 0, 697 RTW89_NSS_2 = 1, 698 /* HE DCM only support 1ss and 2ss */ 699 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 700 RTW89_NSS_3 = 2, 701 RTW89_NSS_4 = 3, 702 RTW89_NSS_NUM, 703 }; 704 705 enum rtw89_ntx { 706 RTW89_1TX = 0, 707 RTW89_2TX = 1, 708 RTW89_NTX_NUM, 709 }; 710 711 enum rtw89_beamforming_type { 712 RTW89_NONBF = 0, 713 RTW89_BF = 1, 714 RTW89_BF_NUM, 715 }; 716 717 enum rtw89_ofdma_type { 718 RTW89_NON_OFDMA = 0, 719 RTW89_OFDMA = 1, 720 RTW89_OFDMA_NUM, 721 }; 722 723 /* neither insert new in the middle, nor change any given definition */ 724 enum rtw89_regulation_type { 725 RTW89_WW = 0, 726 RTW89_ETSI = 1, 727 RTW89_FCC = 2, 728 RTW89_MKK = 3, 729 RTW89_NA = 4, 730 RTW89_IC = 5, 731 RTW89_KCC = 6, 732 RTW89_ACMA = 7, 733 RTW89_NCC = 8, 734 RTW89_MEXICO = 9, 735 RTW89_CHILE = 10, 736 RTW89_UKRAINE = 11, 737 RTW89_CN = 12, 738 RTW89_QATAR = 13, 739 RTW89_UK = 14, 740 RTW89_THAILAND = 15, 741 RTW89_REGD_NUM, 742 }; 743 744 enum rtw89_reg_6ghz_power { 745 RTW89_REG_6GHZ_POWER_VLP = 0, 746 RTW89_REG_6GHZ_POWER_LPI = 1, 747 RTW89_REG_6GHZ_POWER_STD = 2, 748 749 NUM_OF_RTW89_REG_6GHZ_POWER, 750 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 751 }; 752 753 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 754 755 /* calculate based on ieee80211 Transmit Power Envelope */ 756 struct rtw89_reg_6ghz_tpe { 757 bool valid; 758 s8 constraint; /* unit: dBm */ 759 }; 760 761 enum rtw89_fw_pkt_ofld_type { 762 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 763 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 764 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 765 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 766 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 767 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 768 RTW89_PKT_OFLD_TYPE_NDP = 6, 769 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 770 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 771 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 772 RTW89_PKT_OFLD_TYPE_NUM, 773 }; 774 775 struct rtw89_txpwr_byrate { 776 s8 cck[RTW89_RATE_CCK_NUM]; 777 s8 ofdm[RTW89_RATE_OFDM_NUM]; 778 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 779 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 780 s8 offset[__RTW89_RATE_OFFSET_NUM]; 781 s8 trap; 782 }; 783 784 struct rtw89_rate_desc { 785 enum rtw89_nss nss; 786 enum rtw89_rate_section rs; 787 enum rtw89_ofdma_type ofdma; 788 u8 idx; 789 }; 790 791 #define PHY_STS_HDR_LEN 8 792 #define RF_PATH_MAX 4 793 #define RTW89_MAX_PPDU_CNT 8 794 struct rtw89_rx_phy_ppdu { 795 void *buf; 796 u32 len; 797 u8 rssi_avg; 798 u8 rssi[RF_PATH_MAX]; 799 u8 mac_id; 800 u8 chan_idx; 801 u8 phy_idx; 802 u8 ie; 803 u16 rate; 804 u8 rpl_avg; 805 u8 rpl_path[RF_PATH_MAX]; 806 u8 rpl_fd[RF_PATH_MAX]; 807 u8 bw_idx; 808 u8 rx_path_en; 809 struct { 810 bool has; 811 u8 avg_snr; 812 u8 evm_max; 813 u8 evm_min; 814 } ofdm; 815 bool has_data; 816 bool has_bcn; 817 bool ldpc; 818 bool stbc; 819 bool to_self; 820 bool valid; 821 bool hdr_2_en; 822 }; 823 824 enum rtw89_mac_idx { 825 RTW89_MAC_0 = 0, 826 RTW89_MAC_1 = 1, 827 RTW89_MAC_NUM, 828 }; 829 830 enum rtw89_phy_idx { 831 RTW89_PHY_0 = 0, 832 RTW89_PHY_1 = 1, 833 RTW89_PHY_NUM, 834 }; 835 836 #define __RTW89_MLD_MAX_LINK_NUM 2 837 #define RTW89_MLD_NON_STA_LINK_NUM 1 838 839 enum rtw89_chanctx_idx { 840 RTW89_CHANCTX_0 = 0, 841 RTW89_CHANCTX_1 = 1, 842 843 NUM_OF_RTW89_CHANCTX, 844 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 845 }; 846 847 enum rtw89_rf_path { 848 RF_PATH_A = 0, 849 RF_PATH_B = 1, 850 RF_PATH_C = 2, 851 RF_PATH_D = 3, 852 RF_PATH_AB, 853 RF_PATH_AC, 854 RF_PATH_AD, 855 RF_PATH_BC, 856 RF_PATH_BD, 857 RF_PATH_CD, 858 RF_PATH_ABC, 859 RF_PATH_ABD, 860 RF_PATH_ACD, 861 RF_PATH_BCD, 862 RF_PATH_ABCD, 863 }; 864 865 enum rtw89_rf_path_bit { 866 RF_A = BIT(0), 867 RF_B = BIT(1), 868 RF_C = BIT(2), 869 RF_D = BIT(3), 870 871 RF_AB = (RF_A | RF_B), 872 RF_AC = (RF_A | RF_C), 873 RF_AD = (RF_A | RF_D), 874 RF_BC = (RF_B | RF_C), 875 RF_BD = (RF_B | RF_D), 876 RF_CD = (RF_C | RF_D), 877 878 RF_ABC = (RF_A | RF_B | RF_C), 879 RF_ABD = (RF_A | RF_B | RF_D), 880 RF_ACD = (RF_A | RF_C | RF_D), 881 RF_BCD = (RF_B | RF_C | RF_D), 882 883 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 884 }; 885 886 enum rtw89_bandwidth { 887 RTW89_CHANNEL_WIDTH_20 = 0, 888 RTW89_CHANNEL_WIDTH_40 = 1, 889 RTW89_CHANNEL_WIDTH_80 = 2, 890 RTW89_CHANNEL_WIDTH_160 = 3, 891 RTW89_CHANNEL_WIDTH_320 = 4, 892 893 /* keep index order above */ 894 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 895 896 RTW89_CHANNEL_WIDTH_80_80 = 5, 897 RTW89_CHANNEL_WIDTH_5 = 6, 898 RTW89_CHANNEL_WIDTH_10 = 7, 899 }; 900 901 enum rtw89_ps_mode { 902 RTW89_PS_MODE_NONE = 0, 903 RTW89_PS_MODE_RFOFF = 1, 904 RTW89_PS_MODE_CLK_GATED = 2, 905 RTW89_PS_MODE_PWR_GATED = 3, 906 }; 907 908 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 909 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 910 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 911 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 912 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 913 914 enum rtw89_pe_duration { 915 RTW89_PE_DURATION_0 = 0, 916 RTW89_PE_DURATION_8 = 1, 917 RTW89_PE_DURATION_16 = 2, 918 RTW89_PE_DURATION_16_20 = 3, 919 }; 920 921 enum rtw89_ru_bandwidth { 922 RTW89_RU26 = 0, 923 RTW89_RU52 = 1, 924 RTW89_RU106 = 2, 925 RTW89_RU52_26 = 3, 926 RTW89_RU106_26 = 4, 927 RTW89_RU_NUM, 928 }; 929 930 enum rtw89_sc_offset { 931 RTW89_SC_DONT_CARE = 0, 932 RTW89_SC_20_UPPER = 1, 933 RTW89_SC_20_LOWER = 2, 934 RTW89_SC_20_UPMOST = 3, 935 RTW89_SC_20_LOWEST = 4, 936 RTW89_SC_20_UP2X = 5, 937 RTW89_SC_20_LOW2X = 6, 938 RTW89_SC_20_UP3X = 7, 939 RTW89_SC_20_LOW3X = 8, 940 RTW89_SC_40_UPPER = 9, 941 RTW89_SC_40_LOWER = 10, 942 }; 943 944 /* only mgd features can be added to the enum */ 945 enum rtw89_wow_flags { 946 RTW89_WOW_FLAG_EN_MAGIC_PKT, 947 RTW89_WOW_FLAG_EN_REKEY_PKT, 948 RTW89_WOW_FLAG_EN_DISCONNECT, 949 RTW89_WOW_FLAG_EN_PATTERN, 950 RTW89_WOW_FLAG_NUM, 951 }; 952 953 struct rtw89_chan { 954 u8 channel; 955 u8 primary_channel; 956 enum rtw89_band band_type; 957 enum rtw89_bandwidth band_width; 958 959 /* The follow-up are derived from the above. We must ensure that it 960 * is assigned correctly in rtw89_chan_create() if new one is added. 961 */ 962 u32 freq; 963 enum rtw89_subband subband_type; 964 enum rtw89_sc_offset pri_ch_idx; 965 u8 pri_sb_idx; 966 }; 967 968 struct rtw89_chan_rcd { 969 u8 prev_primary_channel; 970 enum rtw89_band prev_band_type; 971 bool band_changed; 972 }; 973 974 struct rtw89_channel_help_params { 975 u32 tx_en; 976 }; 977 978 struct rtw89_port_reg { 979 u32 port_cfg; 980 u32 tbtt_prohib; 981 u32 bcn_area; 982 u32 bcn_early; 983 u32 tbtt_early; 984 u32 tbtt_agg; 985 u32 bcn_space; 986 u32 bcn_forcetx; 987 u32 bcn_err_cnt; 988 u32 bcn_err_flag; 989 u32 dtim_ctrl; 990 u32 tbtt_shift; 991 u32 bcn_cnt_tmr; 992 u32 tsftr_l; 993 u32 tsftr_h; 994 u32 md_tsft; 995 u32 bss_color; 996 u32 mbssid; 997 u32 mbssid_drop; 998 u32 tsf_sync; 999 u32 ptcl_dbg; 1000 u32 ptcl_dbg_info; 1001 u32 bcn_drop_all; 1002 u32 hiq_win[RTW89_PORT_NUM]; 1003 }; 1004 1005 struct rtw89_txwd_body { 1006 __le32 dword0; 1007 __le32 dword1; 1008 __le32 dword2; 1009 __le32 dword3; 1010 __le32 dword4; 1011 __le32 dword5; 1012 } __packed; 1013 1014 struct rtw89_txwd_body_v1 { 1015 __le32 dword0; 1016 __le32 dword1; 1017 __le32 dword2; 1018 __le32 dword3; 1019 __le32 dword4; 1020 __le32 dword5; 1021 __le32 dword6; 1022 __le32 dword7; 1023 } __packed; 1024 1025 struct rtw89_txwd_body_v2 { 1026 __le32 dword0; 1027 __le32 dword1; 1028 __le32 dword2; 1029 __le32 dword3; 1030 __le32 dword4; 1031 __le32 dword5; 1032 __le32 dword6; 1033 __le32 dword7; 1034 } __packed; 1035 1036 struct rtw89_txwd_info { 1037 __le32 dword0; 1038 __le32 dword1; 1039 __le32 dword2; 1040 __le32 dword3; 1041 __le32 dword4; 1042 __le32 dword5; 1043 } __packed; 1044 1045 struct rtw89_txwd_info_v2 { 1046 __le32 dword0; 1047 __le32 dword1; 1048 __le32 dword2; 1049 __le32 dword3; 1050 __le32 dword4; 1051 __le32 dword5; 1052 __le32 dword6; 1053 __le32 dword7; 1054 } __packed; 1055 1056 struct rtw89_rx_desc_info { 1057 u16 pkt_size; 1058 u8 pkt_type; 1059 u8 drv_info_size; 1060 u8 phy_rpt_size; 1061 u8 hdr_cnv_size; 1062 u8 shift; 1063 u8 wl_hd_iv_len; 1064 bool long_rxdesc; 1065 bool bb_sel; 1066 bool mac_info_valid; 1067 u16 data_rate; 1068 u8 gi_ltf; 1069 u8 bw; 1070 u32 free_run_cnt; 1071 u8 user_id; 1072 bool sr_en; 1073 u8 ppdu_cnt; 1074 u8 ppdu_type; 1075 bool icv_err; 1076 bool crc32_err; 1077 bool hw_dec; 1078 bool sw_dec; 1079 bool addr1_match; 1080 u8 frag; 1081 u16 seq; 1082 u8 frame_type; 1083 u8 rx_pl_id; 1084 bool addr_cam_valid; 1085 u8 addr_cam_id; 1086 u8 sec_cam_id; 1087 u8 mac_id; 1088 u16 offset; 1089 u16 rxd_len; 1090 bool ready; 1091 u16 rssi; 1092 }; 1093 1094 struct rtw89_rxdesc_short { 1095 __le32 dword0; 1096 __le32 dword1; 1097 __le32 dword2; 1098 __le32 dword3; 1099 } __packed; 1100 1101 struct rtw89_rxdesc_short_v2 { 1102 __le32 dword0; 1103 __le32 dword1; 1104 __le32 dword2; 1105 __le32 dword3; 1106 __le32 dword4; 1107 __le32 dword5; 1108 } __packed; 1109 1110 struct rtw89_rxdesc_long { 1111 __le32 dword0; 1112 __le32 dword1; 1113 __le32 dword2; 1114 __le32 dword3; 1115 __le32 dword4; 1116 __le32 dword5; 1117 __le32 dword6; 1118 __le32 dword7; 1119 } __packed; 1120 1121 struct rtw89_rxdesc_long_v2 { 1122 __le32 dword0; 1123 __le32 dword1; 1124 __le32 dword2; 1125 __le32 dword3; 1126 __le32 dword4; 1127 __le32 dword5; 1128 __le32 dword6; 1129 __le32 dword7; 1130 __le32 dword8; 1131 __le32 dword9; 1132 } __packed; 1133 1134 struct rtw89_rxdesc_phy_rpt_v2 { 1135 __le32 dword0; 1136 __le32 dword1; 1137 } __packed; 1138 1139 struct rtw89_tx_desc_info { 1140 u16 pkt_size; 1141 u8 wp_offset; 1142 u8 mac_id; 1143 u8 qsel; 1144 u8 ch_dma; 1145 u8 hdr_llc_len; 1146 bool is_bmc; 1147 bool en_wd_info; 1148 bool wd_page; 1149 bool use_rate; 1150 bool dis_data_fb; 1151 bool tid_indicate; 1152 bool agg_en; 1153 bool bk; 1154 u8 ampdu_density; 1155 u8 ampdu_num; 1156 bool sec_en; 1157 u8 addr_info_nr; 1158 u8 sec_keyid; 1159 u8 sec_type; 1160 u8 sec_cam_idx; 1161 u8 sec_seq[6]; 1162 u16 data_rate; 1163 u16 data_retry_lowest_rate; 1164 bool fw_dl; 1165 u16 seq; 1166 bool a_ctrl_bsr; 1167 u8 hw_ssn_sel; 1168 #define RTW89_MGMT_HW_SSN_SEL 1 1169 u8 hw_seq_mode; 1170 #define RTW89_MGMT_HW_SEQ_MODE 1 1171 bool hiq; 1172 u8 port; 1173 bool er_cap; 1174 bool stbc; 1175 bool ldpc; 1176 bool upd_wlan_hdr; 1177 bool mlo; 1178 bool sw_mld; 1179 }; 1180 1181 struct rtw89_core_tx_request { 1182 enum rtw89_core_tx_type tx_type; 1183 1184 struct sk_buff *skb; 1185 struct ieee80211_vif *vif; 1186 struct ieee80211_sta *sta; 1187 struct rtw89_vif_link *rtwvif_link; 1188 struct rtw89_sta_link *rtwsta_link; 1189 struct rtw89_tx_desc_info desc_info; 1190 }; 1191 1192 struct rtw89_txq { 1193 struct list_head list; 1194 unsigned long flags; 1195 int wait_cnt; 1196 }; 1197 1198 struct rtw89_mac_ax_gnt { 1199 u8 gnt_bt_sw_en; 1200 u8 gnt_bt; 1201 u8 gnt_wl_sw_en; 1202 u8 gnt_wl; 1203 } __packed; 1204 1205 struct rtw89_mac_ax_wl_act { 1206 u8 wlan_act_en; 1207 u8 wlan_act; 1208 } __packed; 1209 1210 #define RTW89_MAC_AX_COEX_GNT_NR 2 1211 struct rtw89_mac_ax_coex_gnt { 1212 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1213 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1214 }; 1215 1216 enum rtw89_btc_ncnt { 1217 BTC_NCNT_POWER_ON = 0x0, 1218 BTC_NCNT_POWER_OFF, 1219 BTC_NCNT_INIT_COEX, 1220 BTC_NCNT_SCAN_START, 1221 BTC_NCNT_SCAN_FINISH, 1222 BTC_NCNT_SPECIAL_PACKET, 1223 BTC_NCNT_SWITCH_BAND, 1224 BTC_NCNT_RFK_TIMEOUT, 1225 BTC_NCNT_SHOW_COEX_INFO, 1226 BTC_NCNT_ROLE_INFO, 1227 BTC_NCNT_CONTROL, 1228 BTC_NCNT_RADIO_STATE, 1229 BTC_NCNT_CUSTOMERIZE, 1230 BTC_NCNT_WL_RFK, 1231 BTC_NCNT_WL_STA, 1232 BTC_NCNT_WL_STA_LAST, 1233 BTC_NCNT_FWINFO, 1234 BTC_NCNT_TIMER, 1235 BTC_NCNT_SWITCH_CHBW, 1236 BTC_NCNT_RESUME_DL_FW, 1237 BTC_NCNT_COUNTRYCODE, 1238 BTC_NCNT_NUM, 1239 }; 1240 1241 enum rtw89_btc_btinfo { 1242 BTC_BTINFO_L0 = 0, 1243 BTC_BTINFO_L1, 1244 BTC_BTINFO_L2, 1245 BTC_BTINFO_L3, 1246 BTC_BTINFO_H0, 1247 BTC_BTINFO_H1, 1248 BTC_BTINFO_H2, 1249 BTC_BTINFO_H3, 1250 BTC_BTINFO_MAX 1251 }; 1252 1253 enum rtw89_btc_dcnt { 1254 BTC_DCNT_RUN = 0x0, 1255 BTC_DCNT_CX_RUNINFO, 1256 BTC_DCNT_RPT, 1257 BTC_DCNT_RPT_HANG, 1258 BTC_DCNT_CYCLE, 1259 BTC_DCNT_CYCLE_HANG, 1260 BTC_DCNT_W1, 1261 BTC_DCNT_W1_HANG, 1262 BTC_DCNT_B1, 1263 BTC_DCNT_B1_HANG, 1264 BTC_DCNT_TDMA_NONSYNC, 1265 BTC_DCNT_SLOT_NONSYNC, 1266 BTC_DCNT_BTCNT_HANG, 1267 BTC_DCNT_BTTX_HANG, 1268 BTC_DCNT_WL_SLOT_DRIFT, 1269 BTC_DCNT_WL_STA_LAST, 1270 BTC_DCNT_BT_SLOT_DRIFT, 1271 BTC_DCNT_BT_SLOT_FLOOD, 1272 BTC_DCNT_FDDT_TRIG, 1273 BTC_DCNT_E2G, 1274 BTC_DCNT_E2G_HANG, 1275 BTC_DCNT_WL_FW_VER_MATCH, 1276 BTC_DCNT_NULL_TX_FAIL, 1277 BTC_DCNT_WL_STA_NTFY, 1278 BTC_DCNT_NUM, 1279 }; 1280 1281 enum rtw89_btc_wl_state_cnt { 1282 BTC_WCNT_SCANAP = 0x0, 1283 BTC_WCNT_DHCP, 1284 BTC_WCNT_EAPOL, 1285 BTC_WCNT_ARP, 1286 BTC_WCNT_SCBDUPDATE, 1287 BTC_WCNT_RFK_REQ, 1288 BTC_WCNT_RFK_GO, 1289 BTC_WCNT_RFK_REJECT, 1290 BTC_WCNT_RFK_TIMEOUT, 1291 BTC_WCNT_CH_UPDATE, 1292 BTC_WCNT_DBCC_ALL_2G, 1293 BTC_WCNT_DBCC_CHG, 1294 BTC_WCNT_RX_OK_LAST, 1295 BTC_WCNT_RX_OK_LAST2S, 1296 BTC_WCNT_RX_ERR_LAST, 1297 BTC_WCNT_RX_ERR_LAST2S, 1298 BTC_WCNT_RX_LAST, 1299 BTC_WCNT_NUM 1300 }; 1301 1302 enum rtw89_btc_bt_state_cnt { 1303 BTC_BCNT_RETRY = 0x0, 1304 BTC_BCNT_REINIT, 1305 BTC_BCNT_REENABLE, 1306 BTC_BCNT_SCBDREAD, 1307 BTC_BCNT_RELINK, 1308 BTC_BCNT_IGNOWL, 1309 BTC_BCNT_INQPAG, 1310 BTC_BCNT_INQ, 1311 BTC_BCNT_PAGE, 1312 BTC_BCNT_ROLESW, 1313 BTC_BCNT_AFH, 1314 BTC_BCNT_INFOUPDATE, 1315 BTC_BCNT_INFOSAME, 1316 BTC_BCNT_SCBDUPDATE, 1317 BTC_BCNT_HIPRI_TX, 1318 BTC_BCNT_HIPRI_RX, 1319 BTC_BCNT_LOPRI_TX, 1320 BTC_BCNT_LOPRI_RX, 1321 BTC_BCNT_POLUT, 1322 BTC_BCNT_POLUT_NOW, 1323 BTC_BCNT_POLUT_DIFF, 1324 BTC_BCNT_RATECHG, 1325 BTC_BCNT_BTTXPWR_UPDATE, 1326 BTC_BCNT_NUM, 1327 }; 1328 1329 enum rtw89_btc_bt_profile { 1330 BTC_BT_NOPROFILE = 0, 1331 BTC_BT_HFP = BIT(0), 1332 BTC_BT_HID = BIT(1), 1333 BTC_BT_A2DP = BIT(2), 1334 BTC_BT_PAN = BIT(3), 1335 BTC_PROFILE_MAX = 4, 1336 }; 1337 1338 struct rtw89_btc_ant_info { 1339 u8 type; /* shared, dedicated */ 1340 u8 num; 1341 u8 isolation; 1342 1343 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1344 u8 diversity: 1; 1345 u8 btg_pos: 2; 1346 u8 stream_cnt: 4; 1347 }; 1348 1349 struct rtw89_btc_ant_info_v7 { 1350 u8 type; /* shared, dedicated(non-shared) */ 1351 u8 num; /* antenna count */ 1352 u8 isolation; 1353 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1354 1355 u8 diversity; /* only for wifi use 1-antenna */ 1356 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1357 u8 stream_cnt; /* spatial_stream count */ 1358 u8 rsvd; 1359 } __packed; 1360 1361 enum rtw89_tfc_dir { 1362 RTW89_TFC_UL, 1363 RTW89_TFC_DL, 1364 }; 1365 1366 struct rtw89_btc_wl_smap { 1367 u32 busy: 1; 1368 u32 scan: 1; 1369 u32 connecting: 1; 1370 u32 roaming: 1; 1371 u32 dbccing: 1; 1372 u32 _4way: 1; 1373 u32 rf_off: 1; 1374 u32 lps: 2; 1375 u32 ips: 1; 1376 u32 init_ok: 1; 1377 u32 traffic_dir : 2; 1378 u32 rf_off_pre: 1; 1379 u32 lps_pre: 2; 1380 u32 lps_exiting: 1; 1381 u32 emlsr: 1; 1382 }; 1383 1384 enum rtw89_tfc_lv { 1385 RTW89_TFC_IDLE, 1386 RTW89_TFC_ULTRA_LOW, 1387 RTW89_TFC_LOW, 1388 RTW89_TFC_MID, 1389 RTW89_TFC_HIGH, 1390 }; 1391 1392 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1393 DECLARE_EWMA(tp, 10, 2); 1394 1395 struct rtw89_traffic_stats { 1396 /* units in bytes */ 1397 u64 tx_unicast; 1398 u64 rx_unicast; 1399 u32 tx_avg_len; 1400 u32 rx_avg_len; 1401 1402 /* count for packets */ 1403 u64 tx_cnt; 1404 u64 rx_cnt; 1405 1406 /* units in Mbps */ 1407 u32 tx_throughput; 1408 u32 rx_throughput; 1409 u32 tx_throughput_raw; 1410 u32 rx_throughput_raw; 1411 1412 u32 rx_tf_acc; 1413 u32 rx_tf_periodic; 1414 1415 enum rtw89_tfc_lv tx_tfc_lv; 1416 enum rtw89_tfc_lv rx_tfc_lv; 1417 struct ewma_tp tx_ewma_tp; 1418 struct ewma_tp rx_ewma_tp; 1419 1420 u16 tx_rate; 1421 u16 rx_rate; 1422 }; 1423 1424 struct rtw89_btc_chdef { 1425 u8 center_ch; 1426 u8 band; 1427 u8 chan; 1428 enum rtw89_sc_offset offset; 1429 enum rtw89_bandwidth bw; 1430 }; 1431 1432 struct rtw89_btc_statistic { 1433 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1434 struct rtw89_traffic_stats traffic; 1435 }; 1436 1437 #define BTC_WL_RSSI_THMAX 4 1438 1439 struct rtw89_btc_wl_link_info { 1440 struct rtw89_btc_chdef chdef; 1441 struct rtw89_btc_statistic stat; 1442 enum rtw89_tfc_dir dir; 1443 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1444 u8 mac_addr[ETH_ALEN]; 1445 u8 busy; 1446 u8 ch; 1447 u8 bw; 1448 u8 band; 1449 u8 role; 1450 u8 pid; 1451 u8 phy; 1452 u8 dtim_period; 1453 u8 mode; 1454 u8 tx_1ss_limit; 1455 1456 u8 mac_id; 1457 u8 tx_retry; 1458 1459 u32 bcn_period; 1460 u32 busy_t; 1461 u32 tx_time; 1462 u32 client_cnt; 1463 u32 rx_rate_drop_cnt; 1464 u32 noa_duration; 1465 1466 u32 active: 1; 1467 u32 noa: 1; 1468 u32 client_ps: 1; 1469 u32 connected: 2; 1470 }; 1471 1472 union rtw89_btc_wl_state_map { 1473 u32 val; 1474 struct rtw89_btc_wl_smap map; 1475 }; 1476 1477 struct rtw89_btc_bt_hfp_desc { 1478 u32 exist: 1; 1479 u32 type: 2; 1480 u32 rsvd: 29; 1481 }; 1482 1483 struct rtw89_btc_bt_hid_desc { 1484 u32 exist: 1; 1485 u32 slot_info: 2; 1486 u32 pair_cnt: 2; 1487 u32 type: 8; 1488 u32 rsvd: 19; 1489 }; 1490 1491 struct rtw89_btc_bt_a2dp_desc { 1492 u8 exist: 1; 1493 u8 exist_last: 1; 1494 u8 play_latency: 1; 1495 u8 type: 3; 1496 u8 active: 1; 1497 u8 sink: 1; 1498 u32 handle_update: 1; 1499 u32 devinfo_query: 1; 1500 u32 no_empty_streak_2s: 8; 1501 u32 no_empty_streak_max: 8; 1502 u32 rsvd: 6; 1503 1504 u8 bitpool; 1505 u16 vendor_id; 1506 u32 device_name; 1507 u32 flush_time; 1508 }; 1509 1510 struct rtw89_btc_bt_pan_desc { 1511 u32 exist: 1; 1512 u32 type: 1; 1513 u32 active: 1; 1514 u32 rsvd: 29; 1515 }; 1516 1517 struct rtw89_btc_bt_rfk_info { 1518 u32 run: 1; 1519 u32 req: 1; 1520 u32 timeout: 1; 1521 u32 rsvd: 29; 1522 }; 1523 1524 union rtw89_btc_bt_rfk_info_map { 1525 u32 val; 1526 struct rtw89_btc_bt_rfk_info map; 1527 }; 1528 1529 struct rtw89_btc_bt_ver_info { 1530 u32 fw_coex; /* match with which coex_ver */ 1531 u32 fw; 1532 }; 1533 1534 struct rtw89_btc_bool_sta_chg { 1535 u32 now: 1; 1536 u32 last: 1; 1537 u32 remain: 1; 1538 u32 srvd: 29; 1539 }; 1540 1541 struct rtw89_btc_u8_sta_chg { 1542 u8 now; 1543 u8 last; 1544 u8 remain; 1545 u8 rsvd; 1546 }; 1547 1548 struct rtw89_btc_wl_scan_info { 1549 u8 band[RTW89_PHY_NUM]; 1550 u8 phy_map; 1551 u8 rsvd; 1552 }; 1553 1554 struct rtw89_btc_wl_dbcc_info { 1555 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1556 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1557 u8 real_band[RTW89_PHY_NUM]; 1558 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1559 }; 1560 1561 struct rtw89_btc_wl_mlo_info { 1562 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */ 1563 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */ 1564 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */ 1565 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */ 1566 1567 u8 wtype; /* enum phl_mr_wtype */ 1568 u8 mrcx_mode; 1569 u8 mrcx_act_hwb_map; 1570 u8 mrcx_bt_slot_rsp; 1571 1572 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */ 1573 u8 mlo_en; /* MLO enable */ 1574 u8 mlo_adie; /* a-die count */ 1575 u8 dual_hw_band_en; /* both 2 HW-band link exist */ 1576 1577 u32 link_status; /* enum mlo_dbcc_mode_type */ 1578 }; 1579 1580 struct rtw89_btc_wl_active_role { 1581 u8 connected: 1; 1582 u8 pid: 3; 1583 u8 phy: 1; 1584 u8 noa: 1; 1585 u8 band: 2; 1586 1587 u8 client_ps: 1; 1588 u8 bw: 7; 1589 1590 u8 role; 1591 u8 ch; 1592 1593 u16 tx_lvl; 1594 u16 rx_lvl; 1595 u16 tx_rate; 1596 u16 rx_rate; 1597 }; 1598 1599 struct rtw89_btc_wl_active_role_v1 { 1600 u8 connected: 1; 1601 u8 pid: 3; 1602 u8 phy: 1; 1603 u8 noa: 1; 1604 u8 band: 2; 1605 1606 u8 client_ps: 1; 1607 u8 bw: 7; 1608 1609 u8 role; 1610 u8 ch; 1611 1612 u16 tx_lvl; 1613 u16 rx_lvl; 1614 u16 tx_rate; 1615 u16 rx_rate; 1616 1617 u32 noa_duration; /* ms */ 1618 }; 1619 1620 struct rtw89_btc_wl_active_role_v2 { 1621 u8 connected: 1; 1622 u8 pid: 3; 1623 u8 phy: 1; 1624 u8 noa: 1; 1625 u8 band: 2; 1626 1627 u8 client_ps: 1; 1628 u8 bw: 7; 1629 1630 u8 role; 1631 u8 ch; 1632 1633 u32 noa_duration; /* ms */ 1634 }; 1635 1636 struct rtw89_btc_wl_active_role_v7 { 1637 u8 connected; 1638 u8 pid; 1639 u8 phy; 1640 u8 noa; 1641 1642 u8 band; 1643 u8 client_ps; 1644 u8 bw; 1645 u8 role; 1646 1647 u8 ch; 1648 u8 noa_dur; 1649 u8 client_cnt; 1650 u8 rsvd2; 1651 } __packed; 1652 1653 struct rtw89_btc_wl_role_info_bpos { 1654 u16 none: 1; 1655 u16 station: 1; 1656 u16 ap: 1; 1657 u16 vap: 1; 1658 u16 adhoc: 1; 1659 u16 adhoc_master: 1; 1660 u16 mesh: 1; 1661 u16 moniter: 1; 1662 u16 p2p_device: 1; 1663 u16 p2p_gc: 1; 1664 u16 p2p_go: 1; 1665 u16 nan: 1; 1666 }; 1667 1668 struct rtw89_btc_wl_scc_ctrl { 1669 u8 null_role1; 1670 u8 null_role2; 1671 u8 ebt_null; /* if tx null at EBT slot */ 1672 }; 1673 1674 union rtw89_btc_wl_role_info_map { 1675 u16 val; 1676 struct rtw89_btc_wl_role_info_bpos role; 1677 }; 1678 1679 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1680 u8 connect_cnt; 1681 u8 link_mode; 1682 union rtw89_btc_wl_role_info_map role_map; 1683 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1684 }; 1685 1686 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1687 u8 connect_cnt; 1688 u8 link_mode; 1689 union rtw89_btc_wl_role_info_map role_map; 1690 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1691 u32 mrole_type; /* btc_wl_mrole_type */ 1692 u32 mrole_noa_duration; /* ms */ 1693 1694 u32 dbcc_en: 1; 1695 u32 dbcc_chg: 1; 1696 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1697 u32 link_mode_chg: 1; 1698 u32 rsvd: 27; 1699 }; 1700 1701 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1702 u8 connect_cnt; 1703 u8 link_mode; 1704 union rtw89_btc_wl_role_info_map role_map; 1705 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1706 u32 mrole_type; /* btc_wl_mrole_type */ 1707 u32 mrole_noa_duration; /* ms */ 1708 1709 u32 dbcc_en: 1; 1710 u32 dbcc_chg: 1; 1711 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1712 u32 link_mode_chg: 1; 1713 u32 rsvd: 27; 1714 }; 1715 1716 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1717 u8 connected; 1718 u8 pid; 1719 u8 phy; 1720 u8 noa; 1721 1722 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1723 u8 active; /* 0:rlink is under doze */ 1724 u8 bw; /* enum channel_width */ 1725 u8 role; /*enum role_type */ 1726 1727 u8 ch; 1728 u8 noa_dur; /* ms */ 1729 u8 client_cnt; /* for Role = P2P-Go/AP */ 1730 u8 mode; /* wifi protocol */ 1731 } __packed; 1732 1733 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1734 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1735 u8 connect_cnt; 1736 u8 link_mode; 1737 u8 link_mode_chg; 1738 u8 p2p_2g; 1739 1740 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1741 1742 u32 role_map; 1743 u32 mrole_type; /* btc_wl_mrole_type */ 1744 u32 mrole_noa_duration; /* ms */ 1745 u32 dbcc_en; 1746 u32 dbcc_chg; 1747 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1748 } __packed; 1749 1750 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1751 u8 connect_cnt; 1752 u8 link_mode; 1753 u8 link_mode_chg; 1754 u8 p2p_2g; 1755 1756 u8 pta_req_band; 1757 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1758 u8 dbcc_chg; 1759 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1760 1761 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1762 1763 u32 role_map; 1764 u32 mrole_type; /* btc_wl_mrole_type */ 1765 u32 mrole_noa_duration; /* ms */ 1766 } __packed; 1767 1768 struct rtw89_btc_wl_ver_info { 1769 u32 fw_coex; /* match with which coex_ver */ 1770 u32 fw; 1771 u32 mac; 1772 u32 bb; 1773 u32 rf; 1774 }; 1775 1776 struct rtw89_btc_wl_afh_info { 1777 u8 en; 1778 u8 ch; 1779 u8 bw; 1780 u8 rsvd; 1781 } __packed; 1782 1783 struct rtw89_btc_wl_rfk_info { 1784 u32 state: 2; 1785 u32 path_map: 4; 1786 u32 phy_map: 2; 1787 u32 band: 2; 1788 u32 type: 8; 1789 u32 con_rfk: 1; 1790 u32 rsvd: 13; 1791 1792 u32 start_time; 1793 u32 proc_time; 1794 }; 1795 1796 struct rtw89_btc_bt_smap { 1797 u32 connect: 1; 1798 u32 ble_connect: 1; 1799 u32 acl_busy: 1; 1800 u32 sco_busy: 1; 1801 u32 mesh_busy: 1; 1802 u32 inq_pag: 1; 1803 }; 1804 1805 union rtw89_btc_bt_state_map { 1806 u32 val; 1807 struct rtw89_btc_bt_smap map; 1808 }; 1809 1810 #define BTC_BT_RSSI_THMAX 4 1811 #define BTC_BT_AFH_GROUP 12 1812 #define BTC_BT_AFH_LE_GROUP 5 1813 1814 struct rtw89_btc_bt_txpwr_desc { 1815 s8 br_dbm; 1816 s8 le_dbm; 1817 u8 br_gain_index; 1818 u8 le_gain_index; 1819 }; 1820 1821 struct rtw89_btc_bt_link_info { 1822 struct rtw89_btc_u8_sta_chg profile_cnt; 1823 struct rtw89_btc_bool_sta_chg multi_link; 1824 struct rtw89_btc_bool_sta_chg relink; 1825 struct rtw89_btc_bt_hfp_desc hfp_desc; 1826 struct rtw89_btc_bt_hid_desc hid_desc; 1827 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1828 struct rtw89_btc_bt_pan_desc pan_desc; 1829 union rtw89_btc_bt_state_map status; 1830 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc; 1831 1832 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1833 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1834 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1835 u8 afh_map[BTC_BT_AFH_GROUP]; 1836 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1837 1838 u32 role_sw: 1; 1839 u32 slave_role: 1; 1840 u32 afh_update: 1; 1841 u32 cqddr: 1; 1842 u32 rssi: 8; 1843 u32 tx_3m: 1; 1844 u32 rsvd: 19; 1845 }; 1846 1847 struct rtw89_btc_3rdcx_info { 1848 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1849 u8 hw_coex; 1850 u16 rsvd; 1851 }; 1852 1853 struct rtw89_btc_dm_emap { 1854 u32 init: 1; 1855 u32 pta_owner: 1; 1856 u32 wl_rfk_timeout: 1; 1857 u32 bt_rfk_timeout: 1; 1858 u32 wl_fw_hang: 1; 1859 u32 cycle_hang: 1; 1860 u32 w1_hang: 1; 1861 u32 b1_hang: 1; 1862 u32 tdma_no_sync: 1; 1863 u32 slot_no_sync: 1; 1864 u32 wl_slot_drift: 1; 1865 u32 bt_slot_drift: 1; 1866 u32 role_num_mismatch: 1; 1867 u32 null1_tx_late: 1; 1868 u32 bt_afh_conflict: 1; 1869 u32 bt_leafh_conflict: 1; 1870 u32 bt_slot_flood: 1; 1871 u32 wl_e2g_hang: 1; 1872 u32 wl_ver_mismatch: 1; 1873 u32 bt_ver_mismatch: 1; 1874 u32 rfe_type0: 1; 1875 u32 h2c_buffer_over: 1; 1876 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1877 u32 wl_no_sta_ntfy: 1; 1878 1879 u32 h2c_bmap_mismatch: 1; 1880 u32 c2h_bmap_mismatch: 1; 1881 u32 h2c_struct_invalid: 1; 1882 u32 c2h_struct_invalid: 1; 1883 u32 h2c_c2h_buffer_mismatch: 1; 1884 }; 1885 1886 union rtw89_btc_dm_error_map { 1887 u32 val; 1888 struct rtw89_btc_dm_emap map; 1889 }; 1890 1891 struct rtw89_btc_rf_para { 1892 u32 tx_pwr_freerun; 1893 u32 rx_gain_freerun; 1894 u32 tx_pwr_perpkt; 1895 u32 rx_gain_perpkt; 1896 }; 1897 1898 struct rtw89_btc_wl_nhm { 1899 u8 instant_wl_nhm_dbm; 1900 u8 instant_wl_nhm_per_mhz; 1901 u16 valid_record_times; 1902 s8 record_pwr[16]; 1903 u8 record_ratio[16]; 1904 s8 pwr; /* dbm_per_MHz */ 1905 u8 ratio; 1906 u8 current_status; 1907 u8 refresh; 1908 bool start_flag; 1909 s8 pwr_max; 1910 s8 pwr_min; 1911 }; 1912 1913 struct rtw89_btc_wl_info { 1914 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1915 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1916 struct rtw89_btc_wl_rfk_info rfk_info; 1917 struct rtw89_btc_wl_ver_info ver_info; 1918 struct rtw89_btc_wl_afh_info afh_info; 1919 struct rtw89_btc_wl_role_info role_info; 1920 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1921 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1922 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1923 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1924 struct rtw89_btc_wl_scan_info scan_info; 1925 struct rtw89_btc_wl_dbcc_info dbcc_info; 1926 struct rtw89_btc_wl_mlo_info mlo_info; 1927 struct rtw89_btc_rf_para rf_para; 1928 struct rtw89_btc_wl_nhm nhm; 1929 union rtw89_btc_wl_state_map status; 1930 1931 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1932 u8 rssi_level; 1933 u8 cn_report; 1934 u8 coex_mode; 1935 u8 pta_req_mac; 1936 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 1937 1938 bool is_5g_hi_channel; 1939 bool go_client_exist; 1940 bool noa_exist; 1941 bool pta_reg_mac_chg; 1942 bool bg_mode; 1943 bool he_mode; 1944 bool scbd_change; 1945 bool fw_ver_mismatch; 1946 bool client_cnt_inc_2g; 1947 bool link_mode_chg; 1948 bool dbcc_chg; 1949 u32 scbd; 1950 }; 1951 1952 struct rtw89_btc_module { 1953 struct rtw89_btc_ant_info ant; 1954 u8 rfe_type; 1955 u8 cv; 1956 1957 u8 bt_solo: 1; 1958 u8 bt_pos: 1; 1959 u8 switch_type: 1; 1960 u8 wa_type: 3; 1961 1962 u8 kt_ver_adie; 1963 }; 1964 1965 struct rtw89_btc_module_v7 { 1966 u8 rfe_type; 1967 u8 kt_ver; 1968 u8 bt_solo; 1969 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1970 1971 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1972 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1973 u8 kt_ver_adie; 1974 u8 rsvd; 1975 1976 struct rtw89_btc_ant_info_v7 ant; 1977 } __packed; 1978 1979 union rtw89_btc_module_info { 1980 struct rtw89_btc_module md; 1981 struct rtw89_btc_module_v7 md_v7; 1982 }; 1983 1984 #define RTW89_BTC_DM_MAXSTEP 30 1985 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1986 1987 struct rtw89_btc_dm_step { 1988 u16 step[RTW89_BTC_DM_MAXSTEP]; 1989 u8 step_pos; 1990 bool step_ov; 1991 }; 1992 1993 struct rtw89_btc_init_info { 1994 struct rtw89_btc_module module; 1995 u8 wl_guard_ch; 1996 1997 u8 wl_only: 1; 1998 u8 wl_init_ok: 1; 1999 u8 dbcc_en: 1; 2000 u8 cx_other: 1; 2001 u8 bt_only: 1; 2002 2003 u16 rsvd; 2004 }; 2005 2006 struct rtw89_btc_init_info_v7 { 2007 u8 wl_guard_ch; 2008 u8 wl_only; 2009 u8 wl_init_ok; 2010 u8 rsvd3; 2011 2012 u8 cx_other; 2013 u8 bt_only; 2014 u8 pta_mode; 2015 u8 pta_direction; 2016 2017 struct rtw89_btc_module_v7 module; 2018 } __packed; 2019 2020 union rtw89_btc_init_info_u { 2021 struct rtw89_btc_init_info init; 2022 struct rtw89_btc_init_info_v7 init_v7; 2023 }; 2024 2025 struct rtw89_btc_wl_tx_limit_para { 2026 u16 enable; 2027 u32 tx_time; /* unit: us */ 2028 u16 tx_retry; 2029 }; 2030 2031 enum rtw89_btc_bt_scan_type { 2032 BTC_SCAN_INQ = 0, 2033 BTC_SCAN_PAGE, 2034 BTC_SCAN_BLE, 2035 BTC_SCAN_INIT, 2036 BTC_SCAN_TV, 2037 BTC_SCAN_ADV, 2038 BTC_SCAN_MAX1, 2039 }; 2040 2041 enum rtw89_btc_ble_scan_type { 2042 CXSCAN_BG = 0, 2043 CXSCAN_INIT, 2044 CXSCAN_LE, 2045 CXSCAN_MAX 2046 }; 2047 2048 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2049 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2050 2051 struct rtw89_btc_bt_scan_info_v1 { 2052 __le16 win; 2053 __le16 intvl; 2054 __le32 flags; 2055 } __packed; 2056 2057 struct rtw89_btc_bt_scan_info_v2 { 2058 __le16 win; 2059 __le16 intvl; 2060 } __packed; 2061 2062 struct rtw89_btc_fbtc_btscan_v1 { 2063 u8 fver; /* btc_ver::fcxbtscan */ 2064 u8 rsvd; 2065 __le16 rsvd2; 2066 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2067 } __packed; 2068 2069 struct rtw89_btc_fbtc_btscan_v2 { 2070 u8 fver; /* btc_ver::fcxbtscan */ 2071 u8 type; 2072 __le16 rsvd2; 2073 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2074 } __packed; 2075 2076 struct rtw89_btc_fbtc_btscan_v7 { 2077 u8 fver; /* btc_ver::fcxbtscan */ 2078 u8 type; 2079 u8 rsvd0; 2080 u8 rsvd1; 2081 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2082 } __packed; 2083 2084 union rtw89_btc_fbtc_btscan { 2085 struct rtw89_btc_fbtc_btscan_v1 v1; 2086 struct rtw89_btc_fbtc_btscan_v2 v2; 2087 struct rtw89_btc_fbtc_btscan_v7 v7; 2088 }; 2089 2090 struct rtw89_btc_bt_info { 2091 struct rtw89_btc_bt_link_info link_info; 2092 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2093 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2094 struct rtw89_btc_bt_ver_info ver_info; 2095 struct rtw89_btc_bool_sta_chg enable; 2096 struct rtw89_btc_bool_sta_chg inq_pag; 2097 struct rtw89_btc_rf_para rf_para; 2098 union rtw89_btc_bt_rfk_info_map rfk_info; 2099 2100 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2101 u8 txpwr_info[BTC_BTINFO_MAX]; 2102 u8 rssi_level; 2103 2104 u32 scbd; 2105 u32 feature; 2106 2107 u32 mbx_avl: 1; 2108 u32 whql_test: 1; 2109 u32 igno_wl: 1; 2110 u32 reinit: 1; 2111 u32 ble_scan_en: 1; 2112 u32 btg_type: 1; 2113 u32 inq: 1; 2114 u32 pag: 1; 2115 u32 run_patch_code: 1; 2116 u32 hi_lna_rx: 1; 2117 u32 scan_rx_low_pri: 1; 2118 u32 scan_info_update: 1; 2119 u32 lna_constrain: 3; 2120 u32 rsvd: 17; 2121 }; 2122 2123 struct rtw89_btc_cx { 2124 struct rtw89_btc_wl_info wl; 2125 struct rtw89_btc_bt_info bt; 2126 struct rtw89_btc_3rdcx_info other; 2127 u32 state_map; 2128 u32 cnt_bt[BTC_BCNT_NUM]; 2129 u32 cnt_wl[BTC_WCNT_NUM]; 2130 }; 2131 2132 struct rtw89_btc_fbtc_tdma { 2133 u8 type; /* btc_ver::fcxtdma */ 2134 u8 rxflctrl; 2135 u8 txpause; 2136 u8 wtgle_n; 2137 u8 leak_n; 2138 u8 ext_ctrl; 2139 u8 rxflctrl_role; 2140 u8 option_ctrl; 2141 } __packed; 2142 2143 struct rtw89_btc_fbtc_tdma_v3 { 2144 u8 fver; /* btc_ver::fcxtdma */ 2145 u8 rsvd; 2146 __le16 rsvd1; 2147 struct rtw89_btc_fbtc_tdma tdma; 2148 } __packed; 2149 2150 union rtw89_btc_fbtc_tdma_le32 { 2151 struct rtw89_btc_fbtc_tdma v1; 2152 struct rtw89_btc_fbtc_tdma_v3 v3; 2153 }; 2154 2155 #define CXMREG_MAX 30 2156 #define CXMREG_MAX_V2 20 2157 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2158 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2159 2160 enum rtw89_btc_bt_sta_counter { 2161 BTC_BCNT_RFK_REQ = 0, 2162 BTC_BCNT_RFK_GO = 1, 2163 BTC_BCNT_RFK_REJECT = 2, 2164 BTC_BCNT_RFK_FAIL = 3, 2165 BTC_BCNT_RFK_TIMEOUT = 4, 2166 BTC_BCNT_HI_TX = 5, 2167 BTC_BCNT_HI_RX = 6, 2168 BTC_BCNT_LO_TX = 7, 2169 BTC_BCNT_LO_RX = 8, 2170 BTC_BCNT_POLLUTED = 9, 2171 BTC_BCNT_STA_MAX 2172 }; 2173 2174 enum rtw89_btc_bt_sta_counter_v105 { 2175 BTC_BCNT_RFK_REQ_V105 = 0, 2176 BTC_BCNT_HI_TX_V105 = 1, 2177 BTC_BCNT_HI_RX_V105 = 2, 2178 BTC_BCNT_LO_TX_V105 = 3, 2179 BTC_BCNT_LO_RX_V105 = 4, 2180 BTC_BCNT_POLLUTED_V105 = 5, 2181 BTC_BCNT_STA_MAX_V105 2182 }; 2183 2184 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2185 u16 fver; /* btc_ver::fcxbtcrpt */ 2186 u16 rpt_cnt; /* tmr counters */ 2187 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2188 u32 wl_fw_cx_offload; 2189 u32 wl_fw_ver; 2190 u32 rpt_enable; 2191 u32 rpt_para; /* ms */ 2192 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2193 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2194 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2195 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2196 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2197 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2198 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2199 u32 c2h_cnt; /* fw send c2h counter */ 2200 u32 h2c_cnt; /* fw recv h2c counter */ 2201 } __packed; 2202 2203 struct rtw89_btc_fbtc_rpt_ctrl_info { 2204 __le32 cnt; /* fw report counter */ 2205 __le32 en; /* report map */ 2206 __le32 para; /* not used */ 2207 2208 __le32 cnt_c2h; /* fw send c2h counter */ 2209 __le32 cnt_h2c; /* fw recv h2c counter */ 2210 __le32 len_c2h; /* The total length of the last C2H */ 2211 2212 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2213 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2214 } __packed; 2215 2216 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2217 __le32 cx_ver; /* match which driver's coex version */ 2218 __le32 fw_ver; 2219 __le32 en; /* report map */ 2220 2221 __le16 cnt; /* fw report counter */ 2222 __le16 cnt_c2h; /* fw send c2h counter */ 2223 __le16 cnt_h2c; /* fw recv h2c counter */ 2224 __le16 len_c2h; /* The total length of the last C2H */ 2225 2226 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2227 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2228 } __packed; 2229 2230 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2231 __le16 cnt; /* fw report counter */ 2232 __le16 cnt_c2h; /* fw send c2h counter */ 2233 __le16 cnt_h2c; /* fw recv h2c counter */ 2234 __le16 len_c2h; /* The total length of the last C2H */ 2235 2236 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2237 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2238 2239 __le32 cx_ver; /* match which driver's coex version */ 2240 __le32 fw_ver; 2241 __le32 en; /* report map */ 2242 } __packed; 2243 2244 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2245 __le32 cx_ver; /* match which driver's coex version */ 2246 __le32 cx_offload; 2247 __le32 fw_ver; 2248 } __packed; 2249 2250 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2251 __le32 cnt_empty; /* a2dp empty count */ 2252 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2253 __le32 cnt_tx; 2254 __le32 cnt_ack; 2255 __le32 cnt_nack; 2256 } __packed; 2257 2258 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2259 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2260 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2261 __le32 cnt_recv; /* fw recv mailbox counter */ 2262 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2263 } __packed; 2264 2265 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2266 u8 fver; 2267 u8 rsvd; 2268 __le16 rsvd1; 2269 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2270 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2271 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2272 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2273 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2274 } __packed; 2275 2276 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2277 u8 fver; 2278 u8 rsvd; 2279 __le16 rsvd1; 2280 2281 u8 gnt_val[RTW89_PHY_NUM][4]; 2282 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2283 2284 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2285 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2286 } __packed; 2287 2288 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2289 u8 fver; 2290 u8 rsvd; 2291 __le16 rsvd1; 2292 2293 u8 gnt_val[RTW89_PHY_NUM][4]; 2294 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2295 2296 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2297 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2298 } __packed; 2299 2300 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2301 u8 fver; 2302 u8 rsvd0; 2303 u8 rsvd1; 2304 u8 rsvd2; 2305 2306 u8 gnt_val[RTW89_PHY_NUM][4]; 2307 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2308 2309 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2310 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2311 } __packed; 2312 2313 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2314 u8 fver; 2315 u8 rsvd0; 2316 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2317 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2318 2319 u8 gnt_val[RTW89_PHY_NUM][4]; 2320 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2321 2322 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2323 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2324 } __packed; 2325 2326 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2327 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2328 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2329 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2330 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2331 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2332 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2333 }; 2334 2335 enum rtw89_fbtc_ext_ctrl_type { 2336 CXECTL_OFF = 0x0, /* tdma off */ 2337 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2338 CXECTL_EXT = 0x2, 2339 CXECTL_MAX 2340 }; 2341 2342 union rtw89_btc_fbtc_rxflct { 2343 u8 val; 2344 u8 type: 3; 2345 u8 tgln_n: 5; 2346 }; 2347 2348 enum rtw89_btc_cxst_state { 2349 CXST_OFF = 0x0, 2350 CXST_B2W = 0x1, 2351 CXST_W1 = 0x2, 2352 CXST_W2 = 0x3, 2353 CXST_W2B = 0x4, 2354 CXST_B1 = 0x5, 2355 CXST_B2 = 0x6, 2356 CXST_B3 = 0x7, 2357 CXST_B4 = 0x8, 2358 CXST_LK = 0x9, 2359 CXST_BLK = 0xa, 2360 CXST_E2G = 0xb, 2361 CXST_E5G = 0xc, 2362 CXST_EBT = 0xd, 2363 CXST_ENULL = 0xe, 2364 CXST_WLK = 0xf, 2365 CXST_W1FDD = 0x10, 2366 CXST_B1FDD = 0x11, 2367 CXST_MAX = 0x12, 2368 }; 2369 2370 enum rtw89_btc_cxevnt { 2371 CXEVNT_TDMA_ENTRY = 0x0, 2372 CXEVNT_WL_TMR, 2373 CXEVNT_B1_TMR, 2374 CXEVNT_B2_TMR, 2375 CXEVNT_B3_TMR, 2376 CXEVNT_B4_TMR, 2377 CXEVNT_W2B_TMR, 2378 CXEVNT_B2W_TMR, 2379 CXEVNT_BCN_EARLY, 2380 CXEVNT_A2DP_EMPTY, 2381 CXEVNT_LK_END, 2382 CXEVNT_RX_ISR, 2383 CXEVNT_RX_FC0, 2384 CXEVNT_RX_FC1, 2385 CXEVNT_BT_RELINK, 2386 CXEVNT_BT_RETRY, 2387 CXEVNT_E2G, 2388 CXEVNT_E5G, 2389 CXEVNT_EBT, 2390 CXEVNT_ENULL, 2391 CXEVNT_DRV_WLK, 2392 CXEVNT_BCN_OK, 2393 CXEVNT_BT_CHANGE, 2394 CXEVNT_EBT_EXTEND, 2395 CXEVNT_E2G_NULL1, 2396 CXEVNT_B1FDD_TMR, 2397 CXEVNT_MAX 2398 }; 2399 2400 enum { 2401 CXBCN_ALL = 0x0, 2402 CXBCN_ALL_OK, 2403 CXBCN_BT_SLOT, 2404 CXBCN_BT_OK, 2405 CXBCN_MAX 2406 }; 2407 2408 enum btc_slot_type { 2409 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2410 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2411 CXSTYPE_NUM, 2412 }; 2413 2414 enum { /* TIME */ 2415 CXT_BT = 0x0, 2416 CXT_WL = 0x1, 2417 CXT_MAX 2418 }; 2419 2420 enum { /* TIME-A2DP */ 2421 CXT_FLCTRL_OFF = 0x0, 2422 CXT_FLCTRL_ON = 0x1, 2423 CXT_FLCTRL_MAX 2424 }; 2425 2426 enum { /* STEP TYPE */ 2427 CXSTEP_NONE = 0x0, 2428 CXSTEP_EVNT = 0x1, 2429 CXSTEP_SLOT = 0x2, 2430 CXSTEP_MAX, 2431 }; 2432 2433 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2434 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2435 RPT_BT_AFH_SEQ_LE = 0x20 2436 }; 2437 2438 #define BTC_DBG_MAX1 32 2439 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2440 u8 fver; /* btc_ver::fcxgpiodbg */ 2441 u8 rsvd; 2442 __le16 rsvd2; 2443 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2444 __le32 pre_state; /* the debug signal is 1 or 0 */ 2445 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2446 } __packed; 2447 2448 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2449 u8 fver; 2450 u8 rsvd0; 2451 u8 rsvd1; 2452 u8 rsvd2; 2453 2454 u8 gpio_map[BTC_DBG_MAX1]; 2455 2456 __le32 en_map; 2457 __le32 pre_state; 2458 } __packed; 2459 2460 union rtw89_btc_fbtc_gpio_dbg { 2461 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2462 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2463 }; 2464 2465 struct rtw89_btc_fbtc_mreg_val_v1 { 2466 u8 fver; /* btc_ver::fcxmreg */ 2467 u8 reg_num; 2468 __le16 rsvd; 2469 __le32 mreg_val[CXMREG_MAX]; 2470 } __packed; 2471 2472 struct rtw89_btc_fbtc_mreg_val_v2 { 2473 u8 fver; /* btc_ver::fcxmreg */ 2474 u8 reg_num; 2475 __le16 rsvd; 2476 __le32 mreg_val[CXMREG_MAX_V2]; 2477 } __packed; 2478 2479 struct rtw89_btc_fbtc_mreg_val_v7 { 2480 u8 fver; 2481 u8 reg_num; 2482 u8 rsvd0; 2483 u8 rsvd1; 2484 __le32 mreg_val[CXMREG_MAX_V2]; 2485 } __packed; 2486 2487 union rtw89_btc_fbtc_mreg_val { 2488 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2489 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2490 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2491 }; 2492 2493 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2494 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2495 .offset = cpu_to_le32(__offset), } 2496 2497 struct rtw89_btc_fbtc_mreg { 2498 __le16 type; 2499 __le16 bytes; 2500 __le32 offset; 2501 } __packed; 2502 2503 struct rtw89_btc_fbtc_slot { 2504 __le16 dur; 2505 __le32 cxtbl; 2506 __le16 cxtype; 2507 } __packed; 2508 2509 struct rtw89_btc_fbtc_slots { 2510 u8 fver; /* btc_ver::fcxslots */ 2511 u8 tbl_num; 2512 __le16 rsvd; 2513 __le32 update_map; 2514 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2515 } __packed; 2516 2517 struct rtw89_btc_fbtc_slot_v7 { 2518 __le16 dur; /* slot duration */ 2519 __le16 cxtype; 2520 __le32 cxtbl; 2521 } __packed; 2522 2523 struct rtw89_btc_fbtc_slot_u16 { 2524 __le16 dur; /* slot duration */ 2525 __le16 cxtype; 2526 __le16 cxtbl_l16; /* coex table [15:0] */ 2527 __le16 cxtbl_h16; /* coex table [31:16] */ 2528 } __packed; 2529 2530 struct rtw89_btc_fbtc_1slot_v7 { 2531 u8 fver; 2532 u8 sid; /* slot id */ 2533 __le16 rsvd; 2534 struct rtw89_btc_fbtc_slot_v7 slot; 2535 } __packed; 2536 2537 struct rtw89_btc_fbtc_slots_v7 { 2538 u8 fver; 2539 u8 slot_cnt; 2540 u8 rsvd0; 2541 u8 rsvd1; 2542 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2543 __le32 update_map; 2544 } __packed; 2545 2546 union rtw89_btc_fbtc_slots_info { 2547 struct rtw89_btc_fbtc_slots v1; 2548 struct rtw89_btc_fbtc_slots_v7 v7; 2549 } __packed; 2550 2551 struct rtw89_btc_fbtc_step { 2552 u8 type; 2553 u8 val; 2554 __le16 difft; 2555 } __packed; 2556 2557 struct rtw89_btc_fbtc_steps_v2 { 2558 u8 fver; /* btc_ver::fcxstep */ 2559 u8 rsvd; 2560 __le16 cnt; 2561 __le16 pos_old; 2562 __le16 pos_new; 2563 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2564 } __packed; 2565 2566 struct rtw89_btc_fbtc_steps_v3 { 2567 u8 fver; 2568 u8 en; 2569 __le16 rsvd; 2570 __le32 cnt; 2571 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2572 } __packed; 2573 2574 union rtw89_btc_fbtc_steps_info { 2575 struct rtw89_btc_fbtc_steps_v2 v2; 2576 struct rtw89_btc_fbtc_steps_v3 v3; 2577 }; 2578 2579 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2580 u8 fver; /* btc_ver::fcxcysta */ 2581 u8 rsvd; 2582 __le16 cycles; /* total cycle number */ 2583 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2584 __le16 a2dpept; /* a2dp empty cnt */ 2585 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2586 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2587 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2588 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2589 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2590 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2591 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2592 __le16 tmax_a2dpept; /* max a2dp empty time */ 2593 __le16 tavg_lk; /* avg leak-slot time */ 2594 __le16 tmax_lk; /* max leak-slot time */ 2595 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2596 __le32 bcn_cnt[CXBCN_MAX]; 2597 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2598 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2599 __le32 skip_cnt; 2600 __le32 exception; 2601 __le32 except_cnt; 2602 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2603 } __packed; 2604 2605 struct rtw89_btc_fbtc_fdd_try_info { 2606 __le16 cycles[CXT_FLCTRL_MAX]; 2607 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2608 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2609 } __packed; 2610 2611 struct rtw89_btc_fbtc_cycle_time_info { 2612 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2613 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2614 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2615 } __packed; 2616 2617 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2618 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2619 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2620 } __packed; 2621 2622 struct rtw89_btc_fbtc_a2dp_trx_stat { 2623 u8 empty_cnt; 2624 u8 retry_cnt; 2625 u8 tx_rate; 2626 u8 tx_cnt; 2627 u8 ack_cnt; 2628 u8 nack_cnt; 2629 u8 rsvd1; 2630 u8 rsvd2; 2631 } __packed; 2632 2633 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2634 u8 empty_cnt; 2635 u8 retry_cnt; 2636 u8 tx_rate; 2637 u8 tx_cnt; 2638 u8 ack_cnt; 2639 u8 nack_cnt; 2640 u8 no_empty_cnt; 2641 u8 rsvd; 2642 } __packed; 2643 2644 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2645 __le16 cnt; /* a2dp empty cnt */ 2646 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2647 __le16 tavg; /* avg a2dp empty time */ 2648 __le16 tmax; /* max a2dp empty time */ 2649 } __packed; 2650 2651 struct rtw89_btc_fbtc_cycle_leak_info { 2652 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2653 __le16 tavg; /* avg leak-slot time */ 2654 __le16 tmax; /* max leak-slot time */ 2655 } __packed; 2656 2657 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2658 __le16 tavg; 2659 __le16 tamx; 2660 __le32 cnt_rximr; 2661 } __packed; 2662 2663 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2664 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2665 2666 struct rtw89_btc_fbtc_cycle_fddt_info { 2667 __le16 train_cycle; 2668 __le16 tp; 2669 2670 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2671 s8 bt_tx_power; /* decrease Tx power (dB) */ 2672 s8 bt_rx_gain; /* LNA constrain level */ 2673 u8 no_empty_cnt; 2674 2675 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2676 u8 cn; /* condition_num */ 2677 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2678 u8 train_result; /* refer to enum btc_fddt_check_map */ 2679 } __packed; 2680 2681 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2682 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2683 2684 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2685 __le16 train_cycle; 2686 __le16 tp; 2687 2688 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2689 s8 bt_tx_power; /* decrease Tx power (dB) */ 2690 s8 bt_rx_gain; /* LNA constrain level */ 2691 u8 no_empty_cnt; 2692 2693 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2694 u8 cn; /* condition_num */ 2695 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2696 u8 train_result; /* refer to enum btc_fddt_check_map */ 2697 } __packed; 2698 2699 struct rtw89_btc_fbtc_fddt_cell_status { 2700 s8 wl_tx_pwr; 2701 s8 bt_tx_pwr; 2702 s8 bt_rx_gain; 2703 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2704 } __packed; 2705 2706 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2707 u8 fver; 2708 u8 rsvd; 2709 __le16 cycles; /* total cycle number */ 2710 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2711 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2712 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2713 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2714 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2715 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2716 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2717 __le32 bcn_cnt[CXBCN_MAX]; 2718 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2719 __le32 skip_cnt; 2720 __le32 except_cnt; 2721 __le32 except_map; 2722 } __packed; 2723 2724 #define FDD_TRAIN_WL_DIRECTION 2 2725 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2726 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2727 2728 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2729 u8 fver; 2730 u8 rsvd; 2731 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2732 u8 except_cnt; 2733 2734 __le16 skip_cnt; 2735 __le16 cycles; /* total cycle number */ 2736 2737 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2738 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2739 __le16 bcn_cnt[CXBCN_MAX]; 2740 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2741 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2742 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2743 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2744 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2745 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2746 [FDD_TRAIN_WL_RSSI_LEVEL] 2747 [FDD_TRAIN_BT_RSSI_LEVEL]; 2748 __le32 except_map; 2749 } __packed; 2750 2751 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2752 u8 fver; 2753 u8 rsvd; 2754 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2755 u8 except_cnt; 2756 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2757 2758 __le16 skip_cnt; 2759 __le16 cycles; /* total cycle number */ 2760 2761 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2762 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2763 __le16 bcn_cnt[CXBCN_MAX]; 2764 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2765 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2766 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2767 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2768 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2769 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2770 [FDD_TRAIN_WL_RSSI_LEVEL] 2771 [FDD_TRAIN_BT_RSSI_LEVEL]; 2772 __le32 except_map; 2773 } __packed; 2774 2775 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2776 u8 fver; 2777 u8 rsvd; 2778 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2779 u8 except_cnt; 2780 2781 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2782 2783 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2784 2785 __le16 skip_cnt; 2786 __le16 cycles; /* total cycle number */ 2787 2788 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2789 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2790 __le16 bcn_cnt[CXBCN_MAX]; 2791 2792 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2793 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2794 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2795 2796 __le32 except_map; 2797 } __packed; 2798 2799 union rtw89_btc_fbtc_cysta_info { 2800 struct rtw89_btc_fbtc_cysta_v2 v2; 2801 struct rtw89_btc_fbtc_cysta_v3 v3; 2802 struct rtw89_btc_fbtc_cysta_v4 v4; 2803 struct rtw89_btc_fbtc_cysta_v5 v5; 2804 struct rtw89_btc_fbtc_cysta_v7 v7; 2805 }; 2806 2807 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2808 u8 fver; /* btc_ver::fcxnullsta */ 2809 u8 rsvd; 2810 __le16 rsvd2; 2811 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2812 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2813 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2814 } __packed; 2815 2816 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2817 u8 fver; /* btc_ver::fcxnullsta */ 2818 u8 rsvd; 2819 __le16 rsvd2; 2820 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2821 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2822 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2823 } __packed; 2824 2825 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2826 u8 fver; 2827 u8 rsvd0; 2828 u8 rsvd1; 2829 u8 rsvd2; 2830 2831 __le32 tmax[2]; 2832 __le32 tavg[2]; 2833 __le32 result[2][5]; 2834 } __packed; 2835 2836 union rtw89_btc_fbtc_cynullsta_info { 2837 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2838 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2839 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2840 }; 2841 2842 struct rtw89_btc_fbtc_btver_v1 { 2843 u8 fver; /* btc_ver::fcxbtver */ 2844 u8 rsvd; 2845 __le16 rsvd2; 2846 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2847 __le32 fw_ver; 2848 __le32 feature; 2849 } __packed; 2850 2851 struct rtw89_btc_fbtc_btver_v7 { 2852 u8 fver; 2853 u8 rsvd0; 2854 u8 rsvd1; 2855 u8 rsvd2; 2856 2857 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2858 __le32 fw_ver; 2859 __le32 feature; 2860 } __packed; 2861 2862 union rtw89_btc_fbtc_btver { 2863 struct rtw89_btc_fbtc_btver_v1 v1; 2864 struct rtw89_btc_fbtc_btver_v7 v7; 2865 } __packed; 2866 2867 struct rtw89_btc_fbtc_btafh { 2868 u8 fver; /* btc_ver::fcxbtafh */ 2869 u8 rsvd; 2870 __le16 rsvd2; 2871 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2872 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2873 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2874 } __packed; 2875 2876 struct rtw89_btc_fbtc_btafh_v2 { 2877 u8 fver; /* btc_ver::fcxbtafh */ 2878 u8 rsvd; 2879 u8 rsvd2; 2880 u8 map_type; 2881 u8 afh_l[4]; 2882 u8 afh_m[4]; 2883 u8 afh_h[4]; 2884 u8 afh_le_a[4]; 2885 u8 afh_le_b[4]; 2886 } __packed; 2887 2888 struct rtw89_btc_fbtc_btafh_v7 { 2889 u8 fver; 2890 u8 map_type; 2891 u8 rsvd0; 2892 u8 rsvd1; 2893 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2894 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2895 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2896 u8 afh_le_a[4]; 2897 u8 afh_le_b[4]; 2898 } __packed; 2899 2900 struct rtw89_btc_fbtc_btdevinfo { 2901 u8 fver; /* btc_ver::fcxbtdevinfo */ 2902 u8 rsvd; 2903 __le16 vendor_id; 2904 __le32 dev_name; /* only 24 bits valid */ 2905 __le32 flush_time; 2906 } __packed; 2907 2908 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2909 struct rtw89_btc_rf_trx_para { 2910 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2911 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2912 u8 bt_tx_power; /* decrease Tx power (dB) */ 2913 u8 bt_rx_gain; /* LNA constrain level */ 2914 }; 2915 2916 struct rtw89_btc_trx_info { 2917 u8 tx_lvl; 2918 u8 rx_lvl; 2919 u8 wl_rssi; 2920 u8 bt_rssi; 2921 2922 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2923 s8 rx_gain; /* rx gain table index (TBD.) */ 2924 s8 bt_tx_power; /* decrease Tx power (dB) */ 2925 s8 bt_rx_gain; /* LNA constrain level */ 2926 2927 u8 cn; /* condition_num */ 2928 s8 nhm; 2929 u8 bt_profile; 2930 u8 rsvd2; 2931 2932 u16 tx_rate; 2933 u16 rx_rate; 2934 2935 u32 tx_tp; 2936 u32 rx_tp; 2937 u32 rx_err_ratio; 2938 }; 2939 2940 enum btc_rf_path { 2941 BTC_RF_S0 = 0, 2942 BTC_RF_S1 = 1, 2943 BTC_RF_NUM, 2944 }; 2945 2946 struct rtw89_btc_fbtc_outsrc_set_info { 2947 u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */ 2948 u8 btg_rx[BTC_RF_NUM]; 2949 u8 nbtg_tx[BTC_RF_NUM]; 2950 2951 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */ 2952 struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */ 2953 2954 u8 pta_req_hw_band; 2955 u8 rf_gbt_source; 2956 } __packed; 2957 2958 union rtw89_btc_fbtc_slot_u { 2959 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2960 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2961 }; 2962 2963 struct rtw89_btc_dm { 2964 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */ 2965 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */ 2966 union rtw89_btc_fbtc_slot_u slot; 2967 union rtw89_btc_fbtc_slot_u slot_now; 2968 struct rtw89_btc_fbtc_tdma tdma; 2969 struct rtw89_btc_fbtc_tdma tdma_now; 2970 struct rtw89_mac_ax_coex_gnt gnt; 2971 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2972 struct rtw89_btc_rf_trx_para rf_trx_para; 2973 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2974 struct rtw89_btc_dm_step dm_step; 2975 struct rtw89_btc_wl_scc_ctrl wl_scc; 2976 struct rtw89_btc_trx_info trx_info; 2977 union rtw89_btc_dm_error_map error; 2978 u32 cnt_dm[BTC_DCNT_NUM]; 2979 u32 cnt_notify[BTC_NCNT_NUM]; 2980 2981 u32 update_slot_map; 2982 u32 set_ant_path; 2983 u32 e2g_slot_limit; 2984 u32 e2g_slot_nulltx_time; 2985 2986 u32 wl_only: 1; 2987 u32 wl_fw_cx_offload: 1; 2988 u32 freerun: 1; 2989 u32 fddt_train: 1; 2990 u32 wl_ps_ctrl: 2; 2991 u32 wl_mimo_ps: 1; 2992 u32 leak_ap: 1; 2993 u32 noisy_level: 3; 2994 u32 coex_info_map: 8; 2995 u32 bt_only: 1; 2996 u32 wl_btg_rx: 2; 2997 u32 trx_para_level: 8; 2998 u32 wl_stb_chg: 1; 2999 u32 pta_owner: 1; 3000 3001 u32 tdma_instant_excute: 1; 3002 u32 wl_btg_rx_rb: 2; 3003 3004 u16 slot_dur[CXST_MAX]; 3005 u16 bt_slot_flood; 3006 3007 u8 run_reason; 3008 u8 run_action; 3009 3010 u8 wl_pre_agc: 2; 3011 u8 wl_lna2: 1; 3012 u8 freerun_chk: 1; 3013 u8 wl_pre_agc_rb: 2; 3014 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 3015 u8 slot_req_more: 1; 3016 }; 3017 3018 struct rtw89_btc_ctrl { 3019 u32 manual: 1; 3020 u32 igno_bt: 1; 3021 u32 always_freerun: 1; 3022 u32 trace_step: 16; 3023 u32 rsvd: 12; 3024 }; 3025 3026 struct rtw89_btc_ctrl_v7 { 3027 u8 manual; 3028 u8 igno_bt; 3029 u8 always_freerun; 3030 u8 rsvd; 3031 } __packed; 3032 3033 union rtw89_btc_ctrl_list { 3034 struct rtw89_btc_ctrl ctrl; 3035 struct rtw89_btc_ctrl_v7 ctrl_v7; 3036 }; 3037 3038 struct rtw89_btc_dbg { 3039 /* cmd "rb" */ 3040 bool rb_done; 3041 u32 rb_val; 3042 }; 3043 3044 enum rtw89_btc_btf_fw_event { 3045 BTF_EVNT_RPT = 0, 3046 BTF_EVNT_BT_INFO = 1, 3047 BTF_EVNT_BT_SCBD = 2, 3048 BTF_EVNT_BT_REG = 3, 3049 BTF_EVNT_CX_RUNINFO = 4, 3050 BTF_EVNT_BT_PSD = 5, 3051 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 3052 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 3053 BTF_EVNT_BUF_OVERFLOW, 3054 BTF_EVNT_C2H_LOOPBACK, 3055 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */ 3056 BTF_EVNT_MAX, 3057 }; 3058 3059 enum btf_fw_event_report { 3060 BTC_RPT_TYPE_CTRL = 0x0, 3061 BTC_RPT_TYPE_TDMA, 3062 BTC_RPT_TYPE_SLOT, 3063 BTC_RPT_TYPE_CYSTA, 3064 BTC_RPT_TYPE_STEP, 3065 BTC_RPT_TYPE_NULLSTA, 3066 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3067 BTC_RPT_TYPE_MREG, 3068 BTC_RPT_TYPE_GPIO_DBG, 3069 BTC_RPT_TYPE_BT_VER, 3070 BTC_RPT_TYPE_BT_SCAN, 3071 BTC_RPT_TYPE_BT_AFH, 3072 BTC_RPT_TYPE_BT_DEVICE, 3073 BTC_RPT_TYPE_TEST, 3074 BTC_RPT_TYPE_MAX = 31, 3075 3076 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3077 __BTC_RPT_TYPE_V0_MAX = 12, 3078 }; 3079 3080 enum rtw_btc_btf_reg_type { 3081 REG_MAC = 0x0, 3082 REG_BB = 0x1, 3083 REG_RF = 0x2, 3084 REG_BT_RF = 0x3, 3085 REG_BT_MODEM = 0x4, 3086 REG_BT_BLUEWIZE = 0x5, 3087 REG_BT_VENDOR = 0x6, 3088 REG_BT_LE = 0x7, 3089 REG_MAX_TYPE, 3090 }; 3091 3092 struct rtw89_btc_rpt_cmn_info { 3093 u32 rx_cnt; 3094 u32 rx_len; 3095 u32 req_len; /* expected rsp len */ 3096 u8 req_fver; /* expected rsp fver */ 3097 u8 rsp_fver; /* fver from fw */ 3098 u8 valid; 3099 } __packed; 3100 3101 union rtw89_btc_fbtc_btafh_info { 3102 struct rtw89_btc_fbtc_btafh v1; 3103 struct rtw89_btc_fbtc_btafh_v2 v2; 3104 struct rtw89_btc_fbtc_btafh_v7 v7; 3105 }; 3106 3107 struct rtw89_btc_report_ctrl_state { 3108 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3109 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3110 }; 3111 3112 struct rtw89_btc_rpt_fbtc_tdma { 3113 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3114 union rtw89_btc_fbtc_tdma_le32 finfo; 3115 }; 3116 3117 struct rtw89_btc_rpt_fbtc_slots { 3118 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3119 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3120 }; 3121 3122 struct rtw89_btc_rpt_fbtc_cysta { 3123 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3124 union rtw89_btc_fbtc_cysta_info finfo; 3125 }; 3126 3127 struct rtw89_btc_rpt_fbtc_step { 3128 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3129 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3130 }; 3131 3132 struct rtw89_btc_rpt_fbtc_nullsta { 3133 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3134 union rtw89_btc_fbtc_cynullsta_info finfo; 3135 }; 3136 3137 struct rtw89_btc_rpt_fbtc_mreg { 3138 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3139 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3140 }; 3141 3142 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3143 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3144 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3145 }; 3146 3147 struct rtw89_btc_rpt_fbtc_btver { 3148 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3149 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3150 }; 3151 3152 struct rtw89_btc_rpt_fbtc_btscan { 3153 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3154 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3155 }; 3156 3157 struct rtw89_btc_rpt_fbtc_btafh { 3158 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3159 union rtw89_btc_fbtc_btafh_info finfo; 3160 }; 3161 3162 struct rtw89_btc_rpt_fbtc_btdev { 3163 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3164 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3165 }; 3166 3167 enum rtw89_btc_btfre_type { 3168 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3169 BTFRE_UNDEF_TYPE, 3170 BTFRE_EXCEPTION, 3171 BTFRE_MAX, 3172 }; 3173 3174 struct rtw89_btc_ver { 3175 enum rtw89_core_chip_id chip_id; 3176 u32 fw_ver_code; 3177 3178 u8 fcxbtcrpt; 3179 u8 fcxtdma; 3180 u8 fcxslots; 3181 u8 fcxcysta; 3182 u8 fcxstep; 3183 u8 fcxnullsta; 3184 u8 fcxmreg; 3185 u8 fcxgpiodbg; 3186 u8 fcxbtver; 3187 u8 fcxbtscan; 3188 u8 fcxbtafh; 3189 u8 fcxbtdevinfo; 3190 u8 fwlrole; 3191 u8 frptmap; 3192 u8 fcxctrl; 3193 u8 fcxinit; 3194 3195 u8 fwevntrptl; 3196 u8 fwc2hfunc; 3197 u8 drvinfo_type; 3198 u16 info_buf; 3199 u8 max_role_num; 3200 u8 fcxosi; 3201 u8 fcxmlo; 3202 u8 bt_desired; 3203 }; 3204 3205 struct rtw89_btc_btf_fwinfo { 3206 u32 cnt_c2h; 3207 u32 cnt_h2c; 3208 u32 cnt_h2c_fail; 3209 u32 event[BTF_EVNT_MAX]; 3210 3211 u32 err[BTFRE_MAX]; 3212 u32 len_mismch; 3213 u32 fver_mismch; 3214 u32 rpt_en_map; 3215 3216 struct rtw89_btc_ver fw_subver; 3217 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3218 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3219 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3220 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3221 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3222 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3223 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3224 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3225 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3226 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3227 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3228 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3229 }; 3230 3231 #define RTW89_BTC_POLICY_MAXLEN 512 3232 3233 struct rtw89_btc { 3234 const struct rtw89_btc_ver *ver; 3235 3236 struct rtw89_btc_cx cx; 3237 struct rtw89_btc_dm dm; 3238 union rtw89_btc_ctrl_list ctrl; 3239 union rtw89_btc_module_info mdinfo; 3240 struct rtw89_btc_btf_fwinfo fwinfo; 3241 struct rtw89_btc_dbg dbg; 3242 3243 struct wiphy_work eapol_notify_work; 3244 struct wiphy_work arp_notify_work; 3245 struct wiphy_work dhcp_notify_work; 3246 struct wiphy_work icmp_notify_work; 3247 3248 u32 bt_req_len; 3249 3250 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3251 u8 ant_type; 3252 u8 btg_pos; 3253 u16 policy_len; 3254 u16 policy_type; 3255 u32 hubmsg_cnt; 3256 bool bt_req_en; 3257 bool update_policy_force; 3258 bool lps; 3259 bool manual_ctrl; 3260 }; 3261 3262 enum rtw89_btc_hmsg { 3263 RTW89_BTC_HMSG_TMR_EN = 0x0, 3264 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3265 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3266 RTW89_BTC_HMSG_FW_EV = 0x3, 3267 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3268 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3269 3270 NUM_OF_RTW89_BTC_HMSG, 3271 }; 3272 3273 enum rtw89_ra_mode { 3274 RTW89_RA_MODE_CCK = BIT(0), 3275 RTW89_RA_MODE_OFDM = BIT(1), 3276 RTW89_RA_MODE_HT = BIT(2), 3277 RTW89_RA_MODE_VHT = BIT(3), 3278 RTW89_RA_MODE_HE = BIT(4), 3279 RTW89_RA_MODE_EHT = BIT(5), 3280 }; 3281 3282 enum rtw89_ra_report_mode { 3283 RTW89_RA_RPT_MODE_LEGACY, 3284 RTW89_RA_RPT_MODE_HT, 3285 RTW89_RA_RPT_MODE_VHT, 3286 RTW89_RA_RPT_MODE_HE, 3287 RTW89_RA_RPT_MODE_EHT, 3288 }; 3289 3290 enum rtw89_dig_noisy_level { 3291 RTW89_DIG_NOISY_LEVEL0 = -1, 3292 RTW89_DIG_NOISY_LEVEL1 = 0, 3293 RTW89_DIG_NOISY_LEVEL2 = 1, 3294 RTW89_DIG_NOISY_LEVEL3 = 2, 3295 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3296 }; 3297 3298 enum rtw89_gi_ltf { 3299 RTW89_GILTF_LGI_4XHE32 = 0, 3300 RTW89_GILTF_SGI_4XHE08 = 1, 3301 RTW89_GILTF_2XHE16 = 2, 3302 RTW89_GILTF_2XHE08 = 3, 3303 RTW89_GILTF_1XHE16 = 4, 3304 RTW89_GILTF_1XHE08 = 5, 3305 RTW89_GILTF_MAX 3306 }; 3307 3308 enum rtw89_rx_frame_type { 3309 RTW89_RX_TYPE_MGNT = 0, 3310 RTW89_RX_TYPE_CTRL = 1, 3311 RTW89_RX_TYPE_DATA = 2, 3312 RTW89_RX_TYPE_RSVD = 3, 3313 }; 3314 3315 enum rtw89_efuse_block { 3316 RTW89_EFUSE_BLOCK_SYS = 0, 3317 RTW89_EFUSE_BLOCK_RF = 1, 3318 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3319 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3320 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3321 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3322 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3323 RTW89_EFUSE_BLOCK_ADIE = 7, 3324 3325 RTW89_EFUSE_BLOCK_NUM, 3326 RTW89_EFUSE_BLOCK_IGNORE, 3327 }; 3328 3329 struct rtw89_ra_info { 3330 u8 is_dis_ra:1; 3331 /* Bit0 : CCK 3332 * Bit1 : OFDM 3333 * Bit2 : HT 3334 * Bit3 : VHT 3335 * Bit4 : HE 3336 * Bit5 : EHT 3337 */ 3338 u8 mode_ctrl:6; 3339 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3340 u8 macid; 3341 u8 dcm_cap:1; 3342 u8 er_cap:1; 3343 u8 init_rate_lv:2; 3344 u8 upd_all:1; 3345 u8 en_sgi:1; 3346 u8 ldpc_cap:1; 3347 u8 stbc_cap:1; 3348 u8 ss_num:3; 3349 u8 giltf:3; 3350 u8 upd_bw_nss_mask:1; 3351 u8 upd_mask:1; 3352 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3353 /* BFee CSI */ 3354 u8 band_num; 3355 u8 ra_csi_rate_en:1; 3356 u8 fixed_csi_rate_en:1; 3357 u8 cr_tbl_sel:1; 3358 u8 fix_giltf_en:1; 3359 u8 fix_giltf:3; 3360 u8 rsvd2:1; 3361 u8 csi_mcs_ss_idx; 3362 u8 csi_mode:2; 3363 u8 csi_gi_ltf:3; 3364 u8 csi_bw:3; 3365 }; 3366 3367 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3368 #define RTW89_PPDU_MAC_INFO_SIZE 8 3369 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3370 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3371 3372 #define RTW89_MAX_RX_AGG_NUM 64 3373 #define RTW89_MAX_TX_AGG_NUM 128 3374 3375 struct rtw89_ampdu_params { 3376 u16 agg_num; 3377 bool amsdu; 3378 }; 3379 3380 struct rtw89_ra_report { 3381 struct rate_info txrate; 3382 u32 bit_rate; 3383 u16 hw_rate; 3384 bool might_fallback_legacy; 3385 }; 3386 3387 DECLARE_EWMA(rssi, 10, 16); 3388 DECLARE_EWMA(evm, 10, 16); 3389 DECLARE_EWMA(snr, 10, 16); 3390 3391 struct rtw89_ba_cam_entry { 3392 struct list_head list; 3393 u8 tid; 3394 }; 3395 3396 #define RTW89_MAX_ADDR_CAM_NUM 128 3397 #define RTW89_MAX_BSSID_CAM_NUM 20 3398 #define RTW89_MAX_SEC_CAM_NUM 128 3399 #define RTW89_MAX_BA_CAM_NUM 24 3400 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3401 3402 struct rtw89_addr_cam_entry { 3403 u8 addr_cam_idx; 3404 u8 offset; 3405 u8 len; 3406 u8 valid : 1; 3407 u8 addr_mask : 6; 3408 u8 wapi : 1; 3409 u8 mask_sel : 2; 3410 u8 bssid_cam_idx: 6; 3411 3412 u8 sec_ent_mode; 3413 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3414 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3415 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3416 }; 3417 3418 struct rtw89_bssid_cam_entry { 3419 u8 bssid[ETH_ALEN]; 3420 u8 phy_idx; 3421 u8 bssid_cam_idx; 3422 u8 offset; 3423 u8 len; 3424 u8 valid : 1; 3425 u8 num; 3426 }; 3427 3428 struct rtw89_sec_cam_entry { 3429 u8 sec_cam_idx; 3430 u8 offset; 3431 u8 len; 3432 u8 type : 4; 3433 u8 ext_key : 1; 3434 u8 spp_mode : 1; 3435 /* 256 bits */ 3436 u8 key[32]; 3437 3438 struct ieee80211_key_conf *key_conf; 3439 }; 3440 3441 struct rtw89_sta_link { 3442 struct rtw89_sta *rtwsta; 3443 struct list_head dlink_schd; 3444 unsigned int link_id; 3445 3446 u8 mac_id; 3447 u8 tx_retry; 3448 bool er_cap; 3449 struct rtw89_vif_link *rtwvif_link; 3450 struct rtw89_ra_info ra; 3451 struct rtw89_ra_report ra_report; 3452 int max_agg_wait; 3453 u8 prev_rssi; 3454 struct ewma_rssi avg_rssi; 3455 struct ewma_rssi rssi[RF_PATH_MAX]; 3456 struct ewma_snr avg_snr; 3457 struct ewma_evm evm_1ss; 3458 struct ewma_evm evm_min[RF_PATH_MAX]; 3459 struct ewma_evm evm_max[RF_PATH_MAX]; 3460 struct ieee80211_rx_status rx_status; 3461 u16 rx_hw_rate; 3462 __le32 htc_template; 3463 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3464 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3465 struct list_head ba_cam_list; 3466 3467 bool use_cfg_mask; 3468 struct cfg80211_bitrate_mask mask; 3469 3470 bool cctl_tx_time; 3471 u32 ampdu_max_time:4; 3472 bool cctl_tx_retry_limit; 3473 u32 data_tx_cnt_lmt:6; 3474 }; 3475 3476 struct rtw89_efuse { 3477 bool valid; 3478 bool power_k_valid; 3479 u8 xtal_cap; 3480 u8 addr[ETH_ALEN]; 3481 u8 rfe_type; 3482 char country_code[2]; 3483 }; 3484 3485 struct rtw89_phy_rate_pattern { 3486 u64 ra_mask; 3487 u16 rate; 3488 u8 ra_mode; 3489 bool enable; 3490 }; 3491 3492 struct rtw89_tx_wait_info { 3493 struct rcu_head rcu_head; 3494 struct completion completion; 3495 bool tx_done; 3496 }; 3497 3498 struct rtw89_tx_skb_data { 3499 struct rtw89_tx_wait_info __rcu *wait; 3500 u8 hci_priv[]; 3501 }; 3502 3503 #define RTW89_SCAN_NULL_TIMEOUT 30 3504 3505 #define RTW89_ROC_IDLE_TIMEOUT 500 3506 #define RTW89_ROC_TX_TIMEOUT 30 3507 enum rtw89_roc_state { 3508 RTW89_ROC_IDLE, 3509 RTW89_ROC_NORMAL, 3510 RTW89_ROC_MGMT, 3511 }; 3512 3513 struct rtw89_roc { 3514 struct ieee80211_channel chan; 3515 struct wiphy_delayed_work roc_work; 3516 enum ieee80211_roc_type type; 3517 enum rtw89_roc_state state; 3518 int duration; 3519 unsigned int link_id; 3520 }; 3521 3522 #define RTW89_P2P_MAX_NOA_NUM 2 3523 3524 struct rtw89_p2p_ie_head { 3525 u8 eid; 3526 u8 ie_len; 3527 u8 oui[3]; 3528 u8 oui_type; 3529 } __packed; 3530 3531 struct rtw89_noa_attr_head { 3532 u8 attr_type; 3533 __le16 attr_len; 3534 u8 index; 3535 u8 oppps_ctwindow; 3536 } __packed; 3537 3538 struct rtw89_p2p_noa_ie { 3539 struct rtw89_p2p_ie_head p2p_head; 3540 struct rtw89_noa_attr_head noa_head; 3541 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3542 } __packed; 3543 3544 struct rtw89_p2p_noa_setter { 3545 struct rtw89_p2p_noa_ie ie; 3546 u8 noa_count; 3547 u8 noa_index; 3548 }; 3549 3550 struct rtw89_ps_noa_once_handler { 3551 bool in_duration; 3552 u64 tsf_begin; 3553 u64 tsf_end; 3554 struct wiphy_delayed_work set_work; 3555 struct wiphy_delayed_work clr_work; 3556 }; 3557 3558 struct rtw89_vif_link { 3559 struct rtw89_vif *rtwvif; 3560 struct list_head dlink_schd; 3561 unsigned int link_id; 3562 3563 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3564 enum rtw89_chanctx_idx chanctx_idx; 3565 enum rtw89_reg_6ghz_power reg_6ghz_power; 3566 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3567 3568 u8 mac_id; 3569 u8 port; 3570 u8 mac_addr[ETH_ALEN]; 3571 u8 bssid[ETH_ALEN]; 3572 u8 phy_idx; 3573 u8 mac_idx; 3574 u8 net_type; 3575 u8 wifi_role; 3576 u8 self_role; 3577 u8 wmm; 3578 u8 bcn_hit_cond; 3579 u8 bcn_bw_idx; 3580 u8 hit_rule; 3581 u8 last_noa_nr; 3582 u64 sync_bcn_tsf; 3583 bool rand_tsf_done; 3584 bool trigger; 3585 bool lsig_txop; 3586 u8 tgt_ind; 3587 u8 frm_tgt_ind; 3588 bool wowlan_pattern; 3589 bool wowlan_uc; 3590 bool wowlan_magic; 3591 bool is_hesta; 3592 bool last_a_ctrl; 3593 bool dyn_tb_bedge_en; 3594 bool pre_pwr_diff_en; 3595 bool pwr_diff_en; 3596 u8 def_tri_idx; 3597 struct wiphy_work update_beacon_work; 3598 struct wiphy_delayed_work csa_beacon_work; 3599 struct rtw89_addr_cam_entry addr_cam; 3600 struct rtw89_bssid_cam_entry bssid_cam; 3601 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3602 struct rtw89_phy_rate_pattern rate_pattern; 3603 struct list_head general_pkt_list; 3604 struct rtw89_p2p_noa_setter p2p_noa; 3605 struct rtw89_ps_noa_once_handler noa_once; 3606 }; 3607 3608 enum rtw89_lv1_rcvy_step { 3609 RTW89_LV1_RCVY_STEP_1, 3610 RTW89_LV1_RCVY_STEP_2, 3611 }; 3612 3613 struct rtw89_hci_ops { 3614 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3615 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3616 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3617 void (*reset)(struct rtw89_dev *rtwdev); 3618 int (*start)(struct rtw89_dev *rtwdev); 3619 void (*stop)(struct rtw89_dev *rtwdev); 3620 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3621 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3622 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3623 3624 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3625 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3626 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3627 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3628 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3629 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3630 3631 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3632 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3633 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3634 int (*deinit)(struct rtw89_dev *rtwdev); 3635 3636 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3637 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3638 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3639 int (*napi_poll)(struct napi_struct *napi, int budget); 3640 3641 /* Deal with locks inside recovery_start and recovery_complete callbacks 3642 * by hci instance, and handle things which need to consider under SER. 3643 * e.g. turn on/off interrupts except for the one for halt notification. 3644 */ 3645 void (*recovery_start)(struct rtw89_dev *rtwdev); 3646 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3647 3648 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3649 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3650 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3651 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3652 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3653 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3654 void (*disable_intr)(struct rtw89_dev *rtwdev); 3655 void (*enable_intr)(struct rtw89_dev *rtwdev); 3656 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3657 }; 3658 3659 struct rtw89_hci_info { 3660 const struct rtw89_hci_ops *ops; 3661 enum rtw89_hci_type type; 3662 u32 rpwm_addr; 3663 u32 cpwm_addr; 3664 bool paused; 3665 }; 3666 3667 struct rtw89_chip_ops { 3668 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3669 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3670 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3671 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3672 void (*bb_reset)(struct rtw89_dev *rtwdev, 3673 enum rtw89_phy_idx phy_idx); 3674 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3675 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3676 u32 addr, u32 mask); 3677 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3678 u32 addr, u32 mask, u32 data); 3679 void (*set_channel)(struct rtw89_dev *rtwdev, 3680 const struct rtw89_chan *chan, 3681 enum rtw89_mac_idx mac_idx, 3682 enum rtw89_phy_idx phy_idx); 3683 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3684 struct rtw89_channel_help_params *p, 3685 const struct rtw89_chan *chan, 3686 enum rtw89_mac_idx mac_idx, 3687 enum rtw89_phy_idx phy_idx); 3688 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3689 enum rtw89_efuse_block block); 3690 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3691 void (*fem_setup)(struct rtw89_dev *rtwdev); 3692 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3693 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3694 void (*rfk_init)(struct rtw89_dev *rtwdev); 3695 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3696 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3697 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3698 enum rtw89_phy_idx phy_idx, 3699 const struct rtw89_chan *chan); 3700 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3701 bool start); 3702 void (*rfk_track)(struct rtw89_dev *rtwdev); 3703 void (*power_trim)(struct rtw89_dev *rtwdev); 3704 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3705 const struct rtw89_chan *chan, 3706 enum rtw89_phy_idx phy_idx); 3707 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3708 enum rtw89_phy_idx phy_idx); 3709 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3710 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3711 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev, 3712 const struct rtw89_chan *chan); 3713 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3714 enum rtw89_phy_idx phy_idx); 3715 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3716 struct rtw89_rx_phy_ppdu *phy_ppdu, 3717 struct ieee80211_rx_status *status); 3718 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3719 struct rtw89_rx_phy_ppdu *phy_ppdu); 3720 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3721 struct rtw89_rx_desc_info *desc_info, 3722 struct ieee80211_rx_status *rx_status); 3723 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3724 enum rtw89_phy_idx phy_idx); 3725 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3726 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3727 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3728 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3729 enum rtw89_phy_idx phy_idx); 3730 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3731 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3732 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3733 struct rtw89_rx_desc_info *desc_info, 3734 u8 *data, u32 data_offset); 3735 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3736 struct rtw89_tx_desc_info *desc_info, 3737 void *txdesc); 3738 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3739 struct rtw89_tx_desc_info *desc_info, 3740 void *txdesc); 3741 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3742 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3743 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3744 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3745 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3746 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3747 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3748 struct rtw89_vif_link *rtwvif_link, 3749 struct rtw89_sta_link *rtwsta_link); 3750 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3751 struct rtw89_vif_link *rtwvif_link, 3752 struct rtw89_sta_link *rtwsta_link); 3753 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3754 struct rtw89_vif_link *rtwvif_link, 3755 struct rtw89_sta_link *rtwsta_link); 3756 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3757 struct rtw89_vif_link *rtwvif_link, 3758 struct rtw89_sta_link *rtwsta_link); 3759 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 3760 struct rtw89_sta_link *rtwsta_link); 3761 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3762 struct rtw89_vif_link *rtwvif_link, 3763 struct rtw89_sta_link *rtwsta_link); 3764 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3765 struct rtw89_vif_link *rtwvif_link); 3766 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3767 struct rtw89_vif_link *rtwvif_link, 3768 struct rtw89_sta_link *rtwsta_link, 3769 bool valid, struct ieee80211_ampdu_params *params); 3770 3771 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3772 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3773 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3774 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3775 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3776 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3777 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3778 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3779 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3780 }; 3781 3782 enum rtw89_dma_ch { 3783 RTW89_DMA_ACH0 = 0, 3784 RTW89_DMA_ACH1 = 1, 3785 RTW89_DMA_ACH2 = 2, 3786 RTW89_DMA_ACH3 = 3, 3787 RTW89_DMA_ACH4 = 4, 3788 RTW89_DMA_ACH5 = 5, 3789 RTW89_DMA_ACH6 = 6, 3790 RTW89_DMA_ACH7 = 7, 3791 RTW89_DMA_B0MG = 8, 3792 RTW89_DMA_B0HI = 9, 3793 RTW89_DMA_B1MG = 10, 3794 RTW89_DMA_B1HI = 11, 3795 RTW89_DMA_H2C = 12, 3796 RTW89_DMA_CH_NUM = 13 3797 }; 3798 3799 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3800 3801 enum rtw89_mlo_dbcc_mode { 3802 MLO_DBCC_NOT_SUPPORT = 1, 3803 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3804 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3805 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3806 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3807 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3808 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3809 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3810 DBCC_LEGACY = 0xffffffff, 3811 }; 3812 3813 enum rtw89_scan_be_operation { 3814 RTW89_SCAN_OP_STOP, 3815 RTW89_SCAN_OP_START, 3816 RTW89_SCAN_OP_SETPARM, 3817 RTW89_SCAN_OP_GETRPT, 3818 RTW89_SCAN_OP_NUM 3819 }; 3820 3821 enum rtw89_scan_be_mode { 3822 RTW89_SCAN_MODE_SA, 3823 RTW89_SCAN_MODE_MACC, 3824 RTW89_SCAN_MODE_NUM 3825 }; 3826 3827 enum rtw89_scan_be_opmode { 3828 RTW89_SCAN_OPMODE_NONE, 3829 RTW89_SCAN_OPMODE_TBTT, 3830 RTW89_SCAN_OPMODE_INTV, 3831 RTW89_SCAN_OPMODE_CNT, 3832 RTW89_SCAN_OPMODE_NUM, 3833 }; 3834 3835 struct rtw89_scan_option { 3836 bool enable; 3837 bool target_ch_mode; 3838 u8 num_macc_role; 3839 u8 num_opch; 3840 u8 repeat; 3841 u16 norm_pd; 3842 u16 slow_pd; 3843 u16 norm_cy; 3844 u8 opch_end; 3845 u16 delay; 3846 u64 prohib_chan; 3847 enum rtw89_phy_idx band; 3848 enum rtw89_scan_be_operation operation; 3849 enum rtw89_scan_be_mode scan_mode; 3850 enum rtw89_mlo_dbcc_mode mlo_mode; 3851 }; 3852 3853 enum rtw89_qta_mode { 3854 RTW89_QTA_SCC, 3855 RTW89_QTA_DBCC, 3856 RTW89_QTA_DLFW, 3857 RTW89_QTA_WOW, 3858 3859 /* keep last */ 3860 RTW89_QTA_INVALID, 3861 }; 3862 3863 struct rtw89_hfc_ch_cfg { 3864 u16 min; 3865 u16 max; 3866 #define grp_0 0 3867 #define grp_1 1 3868 #define grp_num 2 3869 u8 grp; 3870 }; 3871 3872 struct rtw89_hfc_ch_info { 3873 u16 aval; 3874 u16 used; 3875 }; 3876 3877 struct rtw89_hfc_pub_cfg { 3878 u16 grp0; 3879 u16 grp1; 3880 u16 pub_max; 3881 u16 wp_thrd; 3882 }; 3883 3884 struct rtw89_hfc_pub_info { 3885 u16 g0_used; 3886 u16 g1_used; 3887 u16 g0_aval; 3888 u16 g1_aval; 3889 u16 pub_aval; 3890 u16 wp_aval; 3891 }; 3892 3893 struct rtw89_hfc_prec_cfg { 3894 u16 ch011_prec; 3895 u16 h2c_prec; 3896 u16 wp_ch07_prec; 3897 u16 wp_ch811_prec; 3898 u8 ch011_full_cond; 3899 u8 h2c_full_cond; 3900 u8 wp_ch07_full_cond; 3901 u8 wp_ch811_full_cond; 3902 }; 3903 3904 struct rtw89_hfc_param { 3905 bool en; 3906 bool h2c_en; 3907 u8 mode; 3908 const struct rtw89_hfc_ch_cfg *ch_cfg; 3909 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3910 struct rtw89_hfc_pub_cfg pub_cfg; 3911 struct rtw89_hfc_pub_info pub_info; 3912 struct rtw89_hfc_prec_cfg prec_cfg; 3913 }; 3914 3915 struct rtw89_hfc_param_ini { 3916 const struct rtw89_hfc_ch_cfg *ch_cfg; 3917 const struct rtw89_hfc_pub_cfg *pub_cfg; 3918 const struct rtw89_hfc_prec_cfg *prec_cfg; 3919 u8 mode; 3920 }; 3921 3922 struct rtw89_dle_size { 3923 u16 pge_size; 3924 u16 lnk_pge_num; 3925 u16 unlnk_pge_num; 3926 /* for WiFi 7 chips below */ 3927 u32 srt_ofst; 3928 }; 3929 3930 struct rtw89_wde_quota { 3931 u16 hif; 3932 u16 wcpu; 3933 u16 pkt_in; 3934 u16 cpu_io; 3935 }; 3936 3937 struct rtw89_ple_quota { 3938 u16 cma0_tx; 3939 u16 cma1_tx; 3940 u16 c2h; 3941 u16 h2c; 3942 u16 wcpu; 3943 u16 mpdu_proc; 3944 u16 cma0_dma; 3945 u16 cma1_dma; 3946 u16 bb_rpt; 3947 u16 wd_rel; 3948 u16 cpu_io; 3949 u16 tx_rpt; 3950 /* for WiFi 7 chips below */ 3951 u16 h2d; 3952 }; 3953 3954 struct rtw89_rsvd_quota { 3955 u16 mpdu_info_tbl; 3956 u16 b0_csi; 3957 u16 b1_csi; 3958 u16 b0_lmr; 3959 u16 b1_lmr; 3960 u16 b0_ftm; 3961 u16 b1_ftm; 3962 u16 b0_smr; 3963 u16 b1_smr; 3964 u16 others; 3965 }; 3966 3967 struct rtw89_dle_rsvd_size { 3968 u32 srt_ofst; 3969 u32 size; 3970 }; 3971 3972 struct rtw89_dle_mem { 3973 enum rtw89_qta_mode mode; 3974 const struct rtw89_dle_size *wde_size; 3975 const struct rtw89_dle_size *ple_size; 3976 const struct rtw89_wde_quota *wde_min_qt; 3977 const struct rtw89_wde_quota *wde_max_qt; 3978 const struct rtw89_ple_quota *ple_min_qt; 3979 const struct rtw89_ple_quota *ple_max_qt; 3980 /* for WiFi 7 chips below */ 3981 const struct rtw89_rsvd_quota *rsvd_qt; 3982 const struct rtw89_dle_rsvd_size *rsvd0_size; 3983 const struct rtw89_dle_rsvd_size *rsvd1_size; 3984 }; 3985 3986 struct rtw89_reg_def { 3987 u32 addr; 3988 u32 mask; 3989 }; 3990 3991 struct rtw89_reg2_def { 3992 u32 addr; 3993 u32 data; 3994 }; 3995 3996 struct rtw89_reg3_def { 3997 u32 addr; 3998 u32 mask; 3999 u32 data; 4000 }; 4001 4002 struct rtw89_reg5_def { 4003 u8 flag; /* recognized by parsers */ 4004 u8 path; 4005 u32 addr; 4006 u32 mask; 4007 u32 data; 4008 }; 4009 4010 struct rtw89_reg_imr { 4011 u32 addr; 4012 u32 clr; 4013 u32 set; 4014 }; 4015 4016 struct rtw89_phy_table { 4017 const struct rtw89_reg2_def *regs; 4018 u32 n_regs; 4019 enum rtw89_rf_path rf_path; 4020 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 4021 enum rtw89_rf_path rf_path, void *data); 4022 }; 4023 4024 struct rtw89_txpwr_table { 4025 const void *data; 4026 u32 size; 4027 void (*load)(struct rtw89_dev *rtwdev, 4028 const struct rtw89_txpwr_table *tbl); 4029 }; 4030 4031 struct rtw89_txpwr_rule_2ghz { 4032 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4033 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4034 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4035 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4036 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4037 }; 4038 4039 struct rtw89_txpwr_rule_5ghz { 4040 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4041 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4042 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4043 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4044 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4045 }; 4046 4047 struct rtw89_txpwr_rule_6ghz { 4048 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4049 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4050 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4051 [RTW89_6G_CH_NUM]; 4052 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4053 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4054 [RTW89_6G_CH_NUM]; 4055 }; 4056 4057 struct rtw89_tx_shape { 4058 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4059 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4060 }; 4061 4062 struct rtw89_rfe_parms { 4063 const struct rtw89_txpwr_table *byr_tbl; 4064 struct rtw89_txpwr_rule_2ghz rule_2ghz; 4065 struct rtw89_txpwr_rule_5ghz rule_5ghz; 4066 struct rtw89_txpwr_rule_6ghz rule_6ghz; 4067 struct rtw89_txpwr_rule_2ghz rule_da_2ghz; 4068 struct rtw89_txpwr_rule_5ghz rule_da_5ghz; 4069 struct rtw89_txpwr_rule_6ghz rule_da_6ghz; 4070 struct rtw89_tx_shape tx_shape; 4071 bool has_da; 4072 }; 4073 4074 struct rtw89_rfe_parms_conf { 4075 const struct rtw89_rfe_parms *rfe_parms; 4076 u8 rfe_type; 4077 }; 4078 4079 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 4080 4081 struct rtw89_txpwr_conf { 4082 u8 rfe_type; 4083 u8 ent_sz; 4084 u32 num_ents; 4085 const void *data; 4086 }; 4087 4088 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4089 const struct rtw89_txpwr_conf *conf) 4090 { 4091 u8 valid_size = min(size, conf->ent_sz); 4092 4093 memcpy(entry, cursor, valid_size); 4094 return true; 4095 } 4096 4097 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4098 4099 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4100 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4101 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4102 (cursor) += (conf)->ent_sz) \ 4103 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4104 4105 struct rtw89_txpwr_byrate_data { 4106 struct rtw89_txpwr_conf conf; 4107 struct rtw89_txpwr_table tbl; 4108 }; 4109 4110 struct rtw89_txpwr_lmt_2ghz_data { 4111 struct rtw89_txpwr_conf conf; 4112 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4113 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4114 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4115 }; 4116 4117 struct rtw89_txpwr_lmt_5ghz_data { 4118 struct rtw89_txpwr_conf conf; 4119 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4120 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4121 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4122 }; 4123 4124 struct rtw89_txpwr_lmt_6ghz_data { 4125 struct rtw89_txpwr_conf conf; 4126 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4127 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4128 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4129 [RTW89_6G_CH_NUM]; 4130 }; 4131 4132 struct rtw89_txpwr_lmt_ru_2ghz_data { 4133 struct rtw89_txpwr_conf conf; 4134 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4135 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4136 }; 4137 4138 struct rtw89_txpwr_lmt_ru_5ghz_data { 4139 struct rtw89_txpwr_conf conf; 4140 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4141 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4142 }; 4143 4144 struct rtw89_txpwr_lmt_ru_6ghz_data { 4145 struct rtw89_txpwr_conf conf; 4146 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4147 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4148 [RTW89_6G_CH_NUM]; 4149 }; 4150 4151 struct rtw89_tx_shape_lmt_data { 4152 struct rtw89_txpwr_conf conf; 4153 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4154 }; 4155 4156 struct rtw89_tx_shape_lmt_ru_data { 4157 struct rtw89_txpwr_conf conf; 4158 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4159 }; 4160 4161 struct rtw89_rfe_data { 4162 struct rtw89_txpwr_byrate_data byrate; 4163 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4164 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4165 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4166 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz; 4167 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz; 4168 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz; 4169 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4170 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4171 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4172 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz; 4173 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz; 4174 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz; 4175 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4176 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4177 struct rtw89_rfe_parms rfe_parms; 4178 }; 4179 4180 struct rtw89_page_regs { 4181 u32 hci_fc_ctrl; 4182 u32 ch_page_ctrl; 4183 u32 ach_page_ctrl; 4184 u32 ach_page_info; 4185 u32 pub_page_info3; 4186 u32 pub_page_ctrl1; 4187 u32 pub_page_ctrl2; 4188 u32 pub_page_info1; 4189 u32 pub_page_info2; 4190 u32 wp_page_ctrl1; 4191 u32 wp_page_ctrl2; 4192 u32 wp_page_info1; 4193 }; 4194 4195 struct rtw89_imr_info { 4196 u32 wdrls_imr_set; 4197 u32 wsec_imr_reg; 4198 u32 wsec_imr_set; 4199 u32 mpdu_tx_imr_set; 4200 u32 mpdu_rx_imr_set; 4201 u32 sta_sch_imr_set; 4202 u32 txpktctl_imr_b0_reg; 4203 u32 txpktctl_imr_b0_clr; 4204 u32 txpktctl_imr_b0_set; 4205 u32 txpktctl_imr_b1_reg; 4206 u32 txpktctl_imr_b1_clr; 4207 u32 txpktctl_imr_b1_set; 4208 u32 wde_imr_clr; 4209 u32 wde_imr_set; 4210 u32 ple_imr_clr; 4211 u32 ple_imr_set; 4212 u32 host_disp_imr_clr; 4213 u32 host_disp_imr_set; 4214 u32 cpu_disp_imr_clr; 4215 u32 cpu_disp_imr_set; 4216 u32 other_disp_imr_clr; 4217 u32 other_disp_imr_set; 4218 u32 bbrpt_com_err_imr_reg; 4219 u32 bbrpt_chinfo_err_imr_reg; 4220 u32 bbrpt_err_imr_set; 4221 u32 bbrpt_dfs_err_imr_reg; 4222 u32 ptcl_imr_clr; 4223 u32 ptcl_imr_set; 4224 u32 cdma_imr_0_reg; 4225 u32 cdma_imr_0_clr; 4226 u32 cdma_imr_0_set; 4227 u32 cdma_imr_1_reg; 4228 u32 cdma_imr_1_clr; 4229 u32 cdma_imr_1_set; 4230 u32 phy_intf_imr_reg; 4231 u32 phy_intf_imr_clr; 4232 u32 phy_intf_imr_set; 4233 u32 rmac_imr_reg; 4234 u32 rmac_imr_clr; 4235 u32 rmac_imr_set; 4236 u32 tmac_imr_reg; 4237 u32 tmac_imr_clr; 4238 u32 tmac_imr_set; 4239 }; 4240 4241 struct rtw89_imr_table { 4242 const struct rtw89_reg_imr *regs; 4243 u32 n_regs; 4244 }; 4245 4246 struct rtw89_xtal_info { 4247 u32 xcap_reg; 4248 u32 sc_xo_mask; 4249 u32 sc_xi_mask; 4250 }; 4251 4252 struct rtw89_rrsr_cfgs { 4253 struct rtw89_reg3_def ref_rate; 4254 struct rtw89_reg3_def rsc; 4255 }; 4256 4257 struct rtw89_rfkill_regs { 4258 struct rtw89_reg3_def pinmux; 4259 struct rtw89_reg3_def mode; 4260 }; 4261 4262 struct rtw89_dig_regs { 4263 u32 seg0_pd_reg; 4264 u32 pd_lower_bound_mask; 4265 u32 pd_spatial_reuse_en; 4266 u32 bmode_pd_reg; 4267 u32 bmode_cca_rssi_limit_en; 4268 u32 bmode_pd_lower_bound_reg; 4269 u32 bmode_rssi_nocca_low_th_mask; 4270 struct rtw89_reg_def p0_lna_init; 4271 struct rtw89_reg_def p1_lna_init; 4272 struct rtw89_reg_def p0_tia_init; 4273 struct rtw89_reg_def p1_tia_init; 4274 struct rtw89_reg_def p0_rxb_init; 4275 struct rtw89_reg_def p1_rxb_init; 4276 struct rtw89_reg_def p0_p20_pagcugc_en; 4277 struct rtw89_reg_def p0_s20_pagcugc_en; 4278 struct rtw89_reg_def p1_p20_pagcugc_en; 4279 struct rtw89_reg_def p1_s20_pagcugc_en; 4280 }; 4281 4282 struct rtw89_edcca_regs { 4283 u32 edcca_level; 4284 u32 edcca_mask; 4285 u32 edcca_p_mask; 4286 u32 ppdu_level; 4287 u32 ppdu_mask; 4288 struct rtw89_edcca_p_regs { 4289 u32 rpt_a; 4290 u32 rpt_b; 4291 u32 rpt_sel; 4292 u32 rpt_sel_mask; 4293 } p[RTW89_PHY_NUM]; 4294 u32 rpt_sel_be; 4295 u32 rpt_sel_be_mask; 4296 u32 tx_collision_t2r_st; 4297 u32 tx_collision_t2r_st_mask; 4298 }; 4299 4300 struct rtw89_phy_ul_tb_info { 4301 bool dyn_tb_tri_en; 4302 u8 def_if_bandedge; 4303 }; 4304 4305 struct rtw89_antdiv_stats { 4306 struct ewma_rssi cck_rssi_avg; 4307 struct ewma_rssi ofdm_rssi_avg; 4308 struct ewma_rssi non_legacy_rssi_avg; 4309 u16 pkt_cnt_cck; 4310 u16 pkt_cnt_ofdm; 4311 u16 pkt_cnt_non_legacy; 4312 u32 evm; 4313 }; 4314 4315 struct rtw89_antdiv_info { 4316 struct rtw89_antdiv_stats target_stats; 4317 struct rtw89_antdiv_stats main_stats; 4318 struct rtw89_antdiv_stats aux_stats; 4319 u8 training_count; 4320 u8 rssi_pre; 4321 bool get_stats; 4322 }; 4323 4324 enum rtw89_chanctx_state { 4325 RTW89_CHANCTX_STATE_MCC_START, 4326 RTW89_CHANCTX_STATE_MCC_STOP, 4327 }; 4328 4329 enum rtw89_chanctx_callbacks { 4330 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4331 RTW89_CHANCTX_CALLBACK_RFK, 4332 RTW89_CHANCTX_CALLBACK_TAS, 4333 4334 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4335 }; 4336 4337 struct rtw89_chanctx_listener { 4338 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4339 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4340 }; 4341 4342 struct rtw89_chip_info { 4343 enum rtw89_core_chip_id chip_id; 4344 enum rtw89_chip_gen chip_gen; 4345 const struct rtw89_chip_ops *ops; 4346 const struct rtw89_mac_gen_def *mac_def; 4347 const struct rtw89_phy_gen_def *phy_def; 4348 const char *fw_basename; 4349 u8 fw_format_max; 4350 bool try_ce_fw; 4351 u8 bbmcu_nr; 4352 u32 needed_fw_elms; 4353 const struct rtw89_fw_blacklist *fw_blacklist; 4354 u32 fifo_size; 4355 bool small_fifo_size; 4356 u32 dle_scc_rsvd_size; 4357 u16 max_amsdu_limit; 4358 bool dis_2g_40m_ul_ofdma; 4359 u32 rsvd_ple_ofst; 4360 const struct rtw89_hfc_param_ini *hfc_param_ini; 4361 const struct rtw89_dle_mem *dle_mem; 4362 u8 wde_qempty_acq_grpnum; 4363 u8 wde_qempty_mgq_grpsel; 4364 u32 rf_base_addr[2]; 4365 u8 thermal_th[2]; 4366 u8 support_macid_num; 4367 u8 support_link_num; 4368 u8 support_chanctx_num; 4369 u8 support_bands; 4370 u16 support_bandwidths; 4371 bool support_unii4; 4372 bool support_rnr; 4373 bool support_ant_gain; 4374 bool support_tas; 4375 bool support_sar_by_ant; 4376 bool ul_tb_waveform_ctrl; 4377 bool ul_tb_pwr_diff; 4378 bool rx_freq_frome_ie; 4379 bool hw_sec_hdr; 4380 bool hw_mgmt_tx_encrypt; 4381 bool hw_tkip_crypto; 4382 bool hw_mlo_bmc_crypto; 4383 u8 rf_path_num; 4384 u8 tx_nss; 4385 u8 rx_nss; 4386 u8 acam_num; 4387 u8 bcam_num; 4388 u8 scam_num; 4389 u8 bacam_num; 4390 u8 bacam_dynamic_num; 4391 enum rtw89_bacam_ver bacam_ver; 4392 u8 ppdu_max_usr; 4393 4394 u8 sec_ctrl_efuse_size; 4395 u32 physical_efuse_size; 4396 u32 logical_efuse_size; 4397 u32 limit_efuse_size; 4398 u32 dav_phy_efuse_size; 4399 u32 dav_log_efuse_size; 4400 u32 phycap_addr; 4401 u32 phycap_size; 4402 const struct rtw89_efuse_block_cfg *efuse_blocks; 4403 4404 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4405 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4406 const struct rtw89_phy_table *bb_table; 4407 const struct rtw89_phy_table *bb_gain_table; 4408 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4409 const struct rtw89_phy_table *nctl_table; 4410 const struct rtw89_rfk_tbl *nctl_post_table; 4411 const struct rtw89_phy_dig_gain_table *dig_table; 4412 const struct rtw89_dig_regs *dig_regs; 4413 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4414 4415 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4416 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4417 const struct rtw89_rfe_parms *dflt_parms; 4418 const struct rtw89_chanctx_listener *chanctx_listener; 4419 4420 u8 txpwr_factor_bb; 4421 u8 txpwr_factor_rf; 4422 u8 txpwr_factor_mac; 4423 4424 u32 para_ver; 4425 u32 wlcx_desired; 4426 u8 scbd; 4427 u8 mailbox; 4428 4429 u8 afh_guard_ch; 4430 const u8 *wl_rssi_thres; 4431 const u8 *bt_rssi_thres; 4432 u8 rssi_tol; 4433 4434 u8 mon_reg_num; 4435 const struct rtw89_btc_fbtc_mreg *mon_reg; 4436 u8 rf_para_ulink_num; 4437 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4438 u8 rf_para_dlink_num; 4439 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4440 u8 ps_mode_supported; 4441 u8 low_power_hci_modes; 4442 4443 u32 h2c_cctl_func_id; 4444 u32 hci_func_en_addr; 4445 u32 h2c_desc_size; 4446 u32 txwd_body_size; 4447 u32 txwd_info_size; 4448 u32 h2c_ctrl_reg; 4449 const u32 *h2c_regs; 4450 struct rtw89_reg_def h2c_counter_reg; 4451 u32 c2h_ctrl_reg; 4452 const u32 *c2h_regs; 4453 struct rtw89_reg_def c2h_counter_reg; 4454 const struct rtw89_page_regs *page_regs; 4455 const u32 *wow_reason_reg; 4456 bool cfo_src_fd; 4457 bool cfo_hw_comp; 4458 const struct rtw89_reg_def *dcfo_comp; 4459 u8 dcfo_comp_sft; 4460 const struct rtw89_imr_info *imr_info; 4461 const struct rtw89_imr_table *imr_dmac_table; 4462 const struct rtw89_imr_table *imr_cmac_table; 4463 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4464 struct rtw89_reg_def bss_clr_vld; 4465 u32 bss_clr_map_reg; 4466 const struct rtw89_rfkill_regs *rfkill_init; 4467 struct rtw89_reg_def rfkill_get; 4468 u32 dma_ch_mask; 4469 const struct rtw89_edcca_regs *edcca_regs; 4470 const struct wiphy_wowlan_support *wowlan_stub; 4471 const struct rtw89_xtal_info *xtal_info; 4472 }; 4473 4474 struct rtw89_chip_variant { 4475 bool no_mcs_12_13: 1; 4476 u32 fw_min_ver_code; 4477 }; 4478 4479 union rtw89_bus_info { 4480 const struct rtw89_pci_info *pci; 4481 }; 4482 4483 struct rtw89_driver_info { 4484 const struct rtw89_chip_info *chip; 4485 const struct rtw89_chip_variant *variant; 4486 const struct dmi_system_id *quirks; 4487 union rtw89_bus_info bus; 4488 }; 4489 4490 enum rtw89_hcifc_mode { 4491 RTW89_HCIFC_POH = 0, 4492 RTW89_HCIFC_STF = 1, 4493 RTW89_HCIFC_SDIO = 2, 4494 4495 /* keep last */ 4496 RTW89_HCIFC_MODE_INVALID, 4497 }; 4498 4499 struct rtw89_dle_info { 4500 const struct rtw89_rsvd_quota *rsvd_qt; 4501 enum rtw89_qta_mode qta_mode; 4502 u16 ple_pg_size; 4503 u16 ple_free_pg; 4504 u16 c0_rx_qta; 4505 u16 c1_rx_qta; 4506 }; 4507 4508 enum rtw89_host_rpr_mode { 4509 RTW89_RPR_MODE_POH = 0, 4510 RTW89_RPR_MODE_STF 4511 }; 4512 4513 #define RTW89_COMPLETION_BUF_SIZE 40 4514 #define RTW89_WAIT_COND_IDLE UINT_MAX 4515 4516 struct rtw89_completion_data { 4517 bool err; 4518 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4519 }; 4520 4521 struct rtw89_wait_info { 4522 atomic_t cond; 4523 struct completion completion; 4524 struct rtw89_completion_data data; 4525 }; 4526 4527 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4528 4529 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4530 { 4531 init_completion(&wait->completion); 4532 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4533 } 4534 4535 struct rtw89_mac_info { 4536 struct rtw89_dle_info dle_info; 4537 struct rtw89_hfc_param hfc_param; 4538 enum rtw89_qta_mode qta_mode; 4539 u8 rpwm_seq_num; 4540 u8 cpwm_seq_num; 4541 4542 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4543 struct rtw89_wait_info fw_ofld_wait; 4544 /* see RTW89_PS_WAIT_COND series for wait condition */ 4545 struct rtw89_wait_info ps_wait; 4546 }; 4547 4548 enum rtw89_fwdl_check_type { 4549 RTW89_FWDL_CHECK_FREERTOS_DONE, 4550 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4551 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4552 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4553 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4554 }; 4555 4556 enum rtw89_fw_type { 4557 RTW89_FW_NORMAL = 1, 4558 RTW89_FW_WOWLAN = 3, 4559 RTW89_FW_NORMAL_CE = 5, 4560 RTW89_FW_BBMCU0 = 64, 4561 RTW89_FW_BBMCU1 = 65, 4562 RTW89_FW_LOGFMT = 255, 4563 }; 4564 4565 enum rtw89_fw_feature { 4566 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4567 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4568 RTW89_FW_FEATURE_TX_WAKE, 4569 RTW89_FW_FEATURE_CRASH_TRIGGER, 4570 RTW89_FW_FEATURE_NO_PACKET_DROP, 4571 RTW89_FW_FEATURE_NO_DEEP_PS, 4572 RTW89_FW_FEATURE_NO_LPS_PG, 4573 RTW89_FW_FEATURE_BEACON_FILTER, 4574 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4575 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4576 RTW89_FW_FEATURE_WOW_REASON_V1, 4577 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4578 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4579 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4580 RTW89_FW_FEATURE_RFK_IQK_V0, 4581 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4582 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4583 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4584 RTW89_FW_FEATURE_LPS_CH_INFO, 4585 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4586 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 4587 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1, 4588 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP, 4589 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0, 4590 }; 4591 4592 struct rtw89_fw_suit { 4593 enum rtw89_fw_type type; 4594 const u8 *data; 4595 u32 size; 4596 u8 major_ver; 4597 u8 minor_ver; 4598 u8 sub_ver; 4599 u8 sub_idex; 4600 u16 build_year; 4601 u16 build_mon; 4602 u16 build_date; 4603 u16 build_hour; 4604 u16 build_min; 4605 u8 cmd_ver; 4606 u8 hdr_ver; 4607 u32 commitid; 4608 }; 4609 4610 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4611 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4612 #define RTW89_FW_SUIT_VER_CODE(s) \ 4613 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4614 4615 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4616 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4617 (mfw_hdr)->ver.minor, \ 4618 (mfw_hdr)->ver.sub, \ 4619 (mfw_hdr)->ver.idx) 4620 4621 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4622 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4623 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4624 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4625 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4626 4627 struct rtw89_fw_req_info { 4628 const struct firmware *firmware; 4629 struct completion completion; 4630 }; 4631 4632 struct rtw89_fw_log { 4633 struct rtw89_fw_suit suit; 4634 bool enable; 4635 u32 last_fmt_id; 4636 u32 fmt_count; 4637 const __le32 *fmt_ids; 4638 const char *(*fmts)[]; 4639 }; 4640 4641 struct rtw89_fw_elm_info { 4642 struct rtw89_phy_table *bb_tbl; 4643 struct rtw89_phy_table *bb_gain; 4644 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4645 struct rtw89_phy_table *rf_nctl; 4646 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4647 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4648 const struct rtw89_regd_data *regd; 4649 }; 4650 4651 enum rtw89_fw_mss_dev_type { 4652 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4653 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4654 }; 4655 4656 struct rtw89_fw_secure { 4657 bool secure_boot: 1; 4658 bool can_mss_v1: 1; 4659 bool can_mss_v0: 1; 4660 u32 sb_sel_mgn; 4661 u8 mss_dev_type; 4662 u8 mss_cust_idx; 4663 u8 mss_key_num; 4664 u8 mss_idx; /* v0 */ 4665 }; 4666 4667 struct rtw89_fw_info { 4668 struct rtw89_fw_req_info req; 4669 int fw_format; 4670 u8 h2c_seq; 4671 u8 rec_seq; 4672 u8 h2c_counter; 4673 u8 c2h_counter; 4674 struct rtw89_fw_suit normal; 4675 struct rtw89_fw_suit wowlan; 4676 struct rtw89_fw_suit bbmcu0; 4677 struct rtw89_fw_suit bbmcu1; 4678 struct rtw89_fw_log log; 4679 u32 feature_map; 4680 struct rtw89_fw_elm_info elm_info; 4681 struct rtw89_fw_secure sec; 4682 }; 4683 4684 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4685 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4686 4687 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4688 ((_fw)->feature_map |= BIT(_fw_feature)) 4689 4690 struct rtw89_cam_info { 4691 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4692 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4693 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4694 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4695 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4696 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4697 }; 4698 4699 enum rtw89_sar_sources { 4700 RTW89_SAR_SOURCE_NONE, 4701 RTW89_SAR_SOURCE_COMMON, 4702 RTW89_SAR_SOURCE_ACPI, 4703 4704 RTW89_SAR_SOURCE_NR, 4705 }; 4706 4707 enum rtw89_sar_subband { 4708 RTW89_SAR_2GHZ_SUBBAND, 4709 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4710 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4711 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4712 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4713 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4714 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4715 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4716 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4717 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4718 4719 RTW89_SAR_SUBBAND_NR, 4720 }; 4721 4722 struct rtw89_sar_cfg_common { 4723 bool set[RTW89_SAR_SUBBAND_NR]; 4724 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4725 }; 4726 4727 enum rtw89_acpi_sar_subband { 4728 RTW89_ACPI_SAR_2GHZ_SUBBAND, 4729 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */ 4730 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */ 4731 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4732 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4733 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4734 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4735 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4736 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4737 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4738 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4739 4740 NUM_OF_RTW89_ACPI_SAR_SUBBAND, 4741 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1, 4742 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1, 4743 }; 4744 4745 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */ 4746 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX 4747 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN 4748 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6 4749 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1) 4750 4751 struct rtw89_sar_entry_from_acpi { 4752 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4753 }; 4754 4755 struct rtw89_sar_table_from_acpi { 4756 /* If this table is active, must fill all fields according to either 4757 * configuration in BIOS or some default values for SAR to work well. 4758 */ 4759 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM]; 4760 }; 4761 4762 struct rtw89_sar_indicator_from_acpi { 4763 bool enable_sync; 4764 unsigned int fields; 4765 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath); 4766 4767 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path. 4768 * Not design with pointers since addresses will be invalid after 4769 * sync content with local container instance. 4770 */ 4771 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4772 }; 4773 4774 struct rtw89_sar_cfg_acpi { 4775 u8 downgrade_2tx; 4776 unsigned int valid_num; 4777 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL]; 4778 struct rtw89_sar_indicator_from_acpi indicator; 4779 }; 4780 4781 struct rtw89_sar_info { 4782 /* used to decide how to access SAR cfg union */ 4783 enum rtw89_sar_sources src; 4784 4785 /* reserved for different knids of SAR cfg struct. 4786 * supposed that a single cfg struct cannot handle various SAR sources. 4787 */ 4788 union { 4789 struct rtw89_sar_cfg_common cfg_common; 4790 struct rtw89_sar_cfg_acpi cfg_acpi; 4791 }; 4792 }; 4793 4794 enum rtw89_ant_gain_subband { 4795 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4796 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4797 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4798 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4799 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4800 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4801 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4802 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4803 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4804 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4805 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4806 4807 RTW89_ANT_GAIN_SUBBAND_NR, 4808 }; 4809 4810 enum rtw89_ant_gain_domain_type { 4811 RTW89_ANT_GAIN_ETSI = 0, 4812 4813 RTW89_ANT_GAIN_DOMAIN_NUM, 4814 }; 4815 4816 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4817 struct rtw89_ant_gain_info { 4818 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4819 u32 regd_enabled; 4820 bool block_country; 4821 }; 4822 4823 struct rtw89_6ghz_span { 4824 enum rtw89_sar_subband sar_subband_low; 4825 enum rtw89_sar_subband sar_subband_high; 4826 enum rtw89_acpi_sar_subband acpi_sar_subband_low; 4827 enum rtw89_acpi_sar_subband acpi_sar_subband_high; 4828 enum rtw89_ant_gain_subband ant_gain_subband_low; 4829 enum rtw89_ant_gain_subband ant_gain_subband_high; 4830 }; 4831 4832 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4833 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high) 4834 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4835 4836 enum rtw89_tas_state { 4837 RTW89_TAS_STATE_DPR_OFF, 4838 RTW89_TAS_STATE_DPR_ON, 4839 RTW89_TAS_STATE_STATIC_SAR, 4840 }; 4841 4842 #define RTW89_TAS_TX_RATIO_WINDOW 6 4843 #define RTW89_TAS_TXPWR_WINDOW 180 4844 struct rtw89_tas_info { 4845 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 4846 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 4847 u8 enabled_countries; 4848 u8 txpwr_head_idx; 4849 u8 txpwr_tail_idx; 4850 u8 tx_ratio_idx; 4851 u16 total_tx_ratio; 4852 u64 total_txpwr; 4853 u64 instant_txpwr; 4854 u32 window_size; 4855 s8 dpr_on_threshold; 4856 s8 dpr_off_threshold; 4857 enum rtw89_tas_state backup_state; 4858 enum rtw89_tas_state state; 4859 bool keep_history; 4860 bool block_regd; 4861 bool enable; 4862 bool pause; 4863 }; 4864 4865 struct rtw89_chanctx_cfg { 4866 enum rtw89_chanctx_idx idx; 4867 int ref_count; 4868 }; 4869 4870 enum rtw89_chanctx_changes { 4871 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4872 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4873 RTW89_CHANCTX_P2P_PS_CHANGE, 4874 RTW89_CHANCTX_BT_SLOT_CHANGE, 4875 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4876 4877 NUM_OF_RTW89_CHANCTX_CHANGES, 4878 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4879 }; 4880 4881 enum rtw89_entity_mode { 4882 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4883 RTW89_ENTITY_MODE_MCC_PREPARE, 4884 RTW89_ENTITY_MODE_MCC, 4885 4886 NUM_OF_RTW89_ENTITY_MODE, 4887 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4888 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4889 }; 4890 4891 #define RTW89_MAX_INTERFACE_NUM 2 4892 4893 /* only valid when running with chanctx_ops */ 4894 struct rtw89_entity_mgnt { 4895 struct list_head active_list; 4896 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4897 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4898 [__RTW89_MLD_MAX_LINK_NUM]; 4899 }; 4900 4901 struct rtw89_chanctx { 4902 struct cfg80211_chan_def chandef; 4903 struct rtw89_chan chan; 4904 struct rtw89_chan_rcd rcd; 4905 4906 /* only assigned when running with chanctx_ops */ 4907 struct rtw89_chanctx_cfg *cfg; 4908 }; 4909 4910 struct rtw89_edcca_bak { 4911 u8 a; 4912 u8 p; 4913 u8 ppdu; 4914 u8 th_old; 4915 }; 4916 4917 enum rtw89_dm_type { 4918 RTW89_DM_DYNAMIC_EDCCA, 4919 RTW89_DM_THERMAL_PROTECT, 4920 RTW89_DM_TAS, 4921 RTW89_DM_MLO, 4922 }; 4923 4924 #define RTW89_THERMAL_PROT_LV_MAX 5 4925 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 4926 4927 struct rtw89_hal { 4928 u32 rx_fltr; 4929 u8 cv; 4930 u8 acv; 4931 u32 antenna_tx; 4932 u32 antenna_rx; 4933 u8 tx_nss; 4934 u8 rx_nss; 4935 bool tx_path_diversity; 4936 bool ant_diversity; 4937 bool ant_diversity_fixed; 4938 bool support_cckpd; 4939 bool support_igi; 4940 bool no_mcs_12_13; 4941 4942 atomic_t roc_chanctx_idx; 4943 u8 roc_link_index; 4944 4945 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4946 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4947 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4948 struct cfg80211_chan_def roc_chandef; 4949 4950 bool entity_active[RTW89_PHY_NUM]; 4951 bool entity_pause; 4952 enum rtw89_entity_mode entity_mode; 4953 struct rtw89_entity_mgnt entity_mgnt; 4954 4955 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4956 4957 u8 thermal_prot_th; 4958 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 4959 }; 4960 4961 #define RTW89_MAX_MAC_ID_NUM 128 4962 #define RTW89_MAX_PKT_OFLD_NUM 255 4963 4964 enum rtw89_flags { 4965 RTW89_FLAG_POWERON, 4966 RTW89_FLAG_DMAC_FUNC, 4967 RTW89_FLAG_CMAC0_FUNC, 4968 RTW89_FLAG_CMAC1_FUNC, 4969 RTW89_FLAG_FW_RDY, 4970 RTW89_FLAG_RUNNING, 4971 RTW89_FLAG_PROBE_DONE, 4972 RTW89_FLAG_BFEE_MON, 4973 RTW89_FLAG_BFEE_EN, 4974 RTW89_FLAG_BFEE_TIMER_KEEP, 4975 RTW89_FLAG_NAPI_RUNNING, 4976 RTW89_FLAG_LEISURE_PS, 4977 RTW89_FLAG_LOW_POWER_MODE, 4978 RTW89_FLAG_INACTIVE_PS, 4979 RTW89_FLAG_CRASH_SIMULATING, 4980 RTW89_FLAG_SER_HANDLING, 4981 RTW89_FLAG_WOWLAN, 4982 RTW89_FLAG_FORBIDDEN_TRACK_WORK, 4983 RTW89_FLAG_CHANGING_INTERFACE, 4984 RTW89_FLAG_HW_RFKILL_STATE, 4985 4986 NUM_OF_RTW89_FLAGS, 4987 }; 4988 4989 enum rtw89_quirks { 4990 RTW89_QUIRK_PCI_BER, 4991 RTW89_QUIRK_THERMAL_PROT_120C, 4992 RTW89_QUIRK_THERMAL_PROT_110C, 4993 4994 NUM_OF_RTW89_QUIRKS, 4995 }; 4996 4997 enum rtw89_custid { 4998 RTW89_CUSTID_NONE, 4999 RTW89_CUSTID_ACER, 5000 RTW89_CUSTID_AMD, 5001 RTW89_CUSTID_ASUS, 5002 RTW89_CUSTID_DELL, 5003 RTW89_CUSTID_HP, 5004 RTW89_CUSTID_LENOVO, 5005 }; 5006 5007 enum rtw89_pkt_drop_sel { 5008 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5009 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5010 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5011 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5012 RTW89_PKT_DROP_SEL_MACID_ALL, 5013 RTW89_PKT_DROP_SEL_MG0_ONCE, 5014 RTW89_PKT_DROP_SEL_HIQ_ONCE, 5015 RTW89_PKT_DROP_SEL_HIQ_PORT, 5016 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 5017 RTW89_PKT_DROP_SEL_BAND, 5018 RTW89_PKT_DROP_SEL_BAND_ONCE, 5019 RTW89_PKT_DROP_SEL_REL_MACID, 5020 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 5021 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 5022 }; 5023 5024 struct rtw89_pkt_drop_params { 5025 enum rtw89_pkt_drop_sel sel; 5026 enum rtw89_mac_idx mac_band; 5027 u8 macid; 5028 u8 port; 5029 u8 mbssid; 5030 bool tf_trs; 5031 u32 macid_band_sel[4]; 5032 }; 5033 5034 struct rtw89_pkt_stat { 5035 u16 beacon_nr; 5036 u8 beacon_rate; 5037 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 5038 }; 5039 5040 DECLARE_EWMA(thermal, 4, 4); 5041 5042 struct rtw89_phy_stat { 5043 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 5044 u8 last_thermal_max; 5045 struct ewma_rssi bcn_rssi; 5046 struct rtw89_pkt_stat cur_pkt_stat; 5047 struct rtw89_pkt_stat last_pkt_stat; 5048 }; 5049 5050 enum rtw89_rfk_report_state { 5051 RTW89_RFK_STATE_START = 0x0, 5052 RTW89_RFK_STATE_OK = 0x1, 5053 RTW89_RFK_STATE_FAIL = 0x2, 5054 RTW89_RFK_STATE_TIMEOUT = 0x3, 5055 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 5056 }; 5057 5058 struct rtw89_rfk_wait_info { 5059 struct completion completion; 5060 ktime_t start_time; 5061 enum rtw89_rfk_report_state state; 5062 u8 version; 5063 }; 5064 5065 #define RTW89_DACK_PATH_NR 2 5066 #define RTW89_DACK_IDX_NR 2 5067 #define RTW89_DACK_MSBK_NR 16 5068 struct rtw89_dack_info { 5069 bool dack_done; 5070 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 5071 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5072 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5073 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5074 u32 dack_cnt; 5075 bool addck_timeout[RTW89_DACK_PATH_NR]; 5076 bool dadck_timeout[RTW89_DACK_PATH_NR]; 5077 bool msbk_timeout[RTW89_DACK_PATH_NR]; 5078 }; 5079 5080 enum rtw89_rfk_chs_nrs { 5081 __RTW89_RFK_CHS_NR_V0 = 2, 5082 __RTW89_RFK_CHS_NR_V1 = 3, 5083 5084 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 5085 }; 5086 5087 struct rtw89_rfk_mcc_info_data { 5088 u8 ch[RTW89_RFK_CHS_NR]; 5089 u8 band[RTW89_RFK_CHS_NR]; 5090 u8 bw[RTW89_RFK_CHS_NR]; 5091 u8 table_idx; 5092 }; 5093 5094 struct rtw89_rfk_mcc_info { 5095 struct rtw89_rfk_mcc_info_data data[2]; 5096 }; 5097 5098 #define RTW89_IQK_CHS_NR 2 5099 #define RTW89_IQK_PATH_NR 4 5100 5101 struct rtw89_lck_info { 5102 u8 thermal[RF_PATH_MAX]; 5103 }; 5104 5105 struct rtw89_rx_dck_info { 5106 u8 thermal[RF_PATH_MAX]; 5107 }; 5108 5109 struct rtw89_iqk_info { 5110 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5111 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5112 bool lok_fail[RTW89_IQK_PATH_NR]; 5113 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5114 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5115 u32 iqk_fail_cnt; 5116 bool is_iqk_init; 5117 u32 iqk_channel[RTW89_IQK_CHS_NR]; 5118 u8 iqk_band[RTW89_IQK_PATH_NR]; 5119 u8 iqk_ch[RTW89_IQK_PATH_NR]; 5120 u8 iqk_bw[RTW89_IQK_PATH_NR]; 5121 u8 iqk_times; 5122 u8 version; 5123 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 5124 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 5125 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 5126 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 5127 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 5128 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 5129 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 5130 bool is_nbiqk; 5131 bool iqk_fft_en; 5132 bool iqk_xym_en; 5133 bool iqk_sram_en; 5134 bool iqk_cfir_en; 5135 u32 syn1to2; 5136 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5137 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 5138 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5139 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5140 }; 5141 5142 #define RTW89_DPK_RF_PATH 2 5143 #define RTW89_DPK_AVG_THERMAL_NUM 8 5144 #define RTW89_DPK_BKUP_NUM 2 5145 struct rtw89_dpk_bkup_para { 5146 enum rtw89_band band; 5147 enum rtw89_bandwidth bw; 5148 u8 ch; 5149 bool path_ok; 5150 u8 mdpd_en; 5151 u8 txagc_dpk; 5152 u8 ther_dpk; 5153 u8 gs; 5154 u16 pwsf; 5155 }; 5156 5157 struct rtw89_dpk_info { 5158 bool is_dpk_enable; 5159 bool is_dpk_reload_en; 5160 u8 dpk_gs[RTW89_PHY_NUM]; 5161 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5162 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5163 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5164 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5165 u8 cur_idx[RTW89_DPK_RF_PATH]; 5166 u8 cur_k_set; 5167 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5168 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 5169 u32 dpk_order[RTW89_DPK_RF_PATH]; 5170 }; 5171 5172 struct rtw89_fem_info { 5173 bool elna_2g; 5174 bool elna_5g; 5175 bool epa_2g; 5176 bool epa_5g; 5177 bool epa_6g; 5178 }; 5179 5180 struct rtw89_phy_ch_info { 5181 u8 rssi_min; 5182 u16 rssi_min_macid; 5183 u8 pre_rssi_min; 5184 u8 rssi_max; 5185 u16 rssi_max_macid; 5186 u8 rxsc_160; 5187 u8 rxsc_80; 5188 u8 rxsc_40; 5189 u8 rxsc_20; 5190 u8 rxsc_l; 5191 u8 is_noisy; 5192 }; 5193 5194 struct rtw89_agc_gaincode_set { 5195 u8 lna_idx; 5196 u8 tia_idx; 5197 u8 rxb_idx; 5198 }; 5199 5200 #define IGI_RSSI_TH_NUM 5 5201 #define FA_TH_NUM 4 5202 #define TIA_LNA_OP1DB_NUM 8 5203 #define LNA_GAIN_NUM 7 5204 #define TIA_GAIN_NUM 2 5205 struct rtw89_dig_info { 5206 struct rtw89_agc_gaincode_set cur_gaincode; 5207 bool force_gaincode_idx_en; 5208 struct rtw89_agc_gaincode_set force_gaincode; 5209 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5210 u16 fa_th[FA_TH_NUM]; 5211 u8 igi_rssi; 5212 u8 igi_fa_rssi; 5213 u8 fa_rssi_ofst; 5214 u8 dyn_igi_max; 5215 u8 dyn_igi_min; 5216 bool dyn_pd_th_en; 5217 u8 dyn_pd_th_max; 5218 u8 pd_low_th_ofst; 5219 u8 ib_pbk; 5220 s8 ib_pkpwr; 5221 s8 lna_gain_a[LNA_GAIN_NUM]; 5222 s8 lna_gain_g[LNA_GAIN_NUM]; 5223 s8 *lna_gain; 5224 s8 tia_gain_a[TIA_GAIN_NUM]; 5225 s8 tia_gain_g[TIA_GAIN_NUM]; 5226 s8 *tia_gain; 5227 bool is_linked_pre; 5228 bool bypass_dig; 5229 }; 5230 5231 enum rtw89_multi_cfo_mode { 5232 RTW89_PKT_BASED_AVG_MODE = 0, 5233 RTW89_ENTRY_BASED_AVG_MODE = 1, 5234 RTW89_TP_BASED_AVG_MODE = 2, 5235 }; 5236 5237 enum rtw89_phy_cfo_status { 5238 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5239 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5240 RTW89_PHY_DCFO_STATE_HOLD = 2, 5241 RTW89_PHY_DCFO_STATE_MAX 5242 }; 5243 5244 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5245 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5246 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5247 }; 5248 5249 struct rtw89_cfo_tracking_info { 5250 u16 cfo_timer_ms; 5251 bool cfo_trig_by_timer_en; 5252 enum rtw89_phy_cfo_status phy_cfo_status; 5253 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5254 u8 phy_cfo_trk_cnt; 5255 bool is_adjust; 5256 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5257 bool apply_compensation; 5258 u8 crystal_cap; 5259 u8 crystal_cap_default; 5260 u8 def_x_cap; 5261 s8 x_cap_ofst; 5262 u32 sta_cfo_tolerance; 5263 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5264 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5265 s32 cfo_avg_pre; 5266 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5267 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5268 s32 dcfo_avg; 5269 s32 dcfo_avg_pre; 5270 u32 packet_count; 5271 u32 packet_count_pre; 5272 s32 residual_cfo_acc; 5273 u8 phy_cfotrk_state; 5274 u8 phy_cfotrk_cnt; 5275 bool divergence_lock_en; 5276 u8 x_cap_lb; 5277 u8 x_cap_ub; 5278 u8 lock_cnt; 5279 }; 5280 5281 enum rtw89_tssi_mode { 5282 RTW89_TSSI_NORMAL = 0, 5283 RTW89_TSSI_SCAN = 1, 5284 }; 5285 5286 enum rtw89_tssi_alimk_band { 5287 TSSI_ALIMK_2G = 0, 5288 TSSI_ALIMK_5GL, 5289 TSSI_ALIMK_5GM, 5290 TSSI_ALIMK_5GH, 5291 TSSI_ALIMK_MAX 5292 }; 5293 5294 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5295 #define TSSI_TRIM_CH_GROUP_NUM 8 5296 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5297 5298 #define TSSI_CCK_CH_GROUP_NUM 6 5299 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5300 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5301 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5302 #define TSSI_MCS_CH_GROUP_NUM \ 5303 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5304 #define TSSI_MAX_CH_NUM 67 5305 #define TSSI_ALIMK_VALUE_NUM 8 5306 5307 struct rtw89_tssi_info { 5308 u8 thermal[RF_PATH_MAX]; 5309 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5310 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5311 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5312 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5313 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5314 s8 extra_ofst[RF_PATH_MAX]; 5315 bool tssi_tracking_check[RF_PATH_MAX]; 5316 u8 default_txagc_offset[RF_PATH_MAX]; 5317 u32 base_thermal[RF_PATH_MAX]; 5318 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5319 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5320 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5321 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5322 u64 tssi_alimk_time; 5323 }; 5324 5325 struct rtw89_power_trim_info { 5326 bool pg_thermal_trim; 5327 bool pg_pa_bias_trim; 5328 u8 thermal_trim[RF_PATH_MAX]; 5329 u8 pa_bias_trim[RF_PATH_MAX]; 5330 u8 pad_bias_trim[RF_PATH_MAX]; 5331 }; 5332 5333 enum rtw89_regd_func { 5334 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 5335 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 5336 5337 NUM_OF_RTW89_REGD_FUNC, 5338 }; 5339 5340 struct rtw89_regd { 5341 char alpha2[3]; 5342 u8 txpwr_regd[RTW89_BAND_NUM]; 5343 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 5344 }; 5345 5346 struct rtw89_regd_data { 5347 unsigned int nr; 5348 struct rtw89_regd map[] __counted_by(nr); 5349 }; 5350 5351 struct rtw89_regd_ctrl { 5352 unsigned int nr; 5353 const struct rtw89_regd *map; 5354 }; 5355 5356 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5357 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5358 #define RTW89_5GHZ_UNII4_START_INDEX 25 5359 5360 struct rtw89_regulatory_info { 5361 struct rtw89_regd_ctrl ctrl; 5362 const struct rtw89_regd *regd; 5363 enum rtw89_reg_6ghz_power reg_6ghz_power; 5364 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5365 bool txpwr_uk_follow_etsi; 5366 5367 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5368 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5369 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5370 }; 5371 5372 enum rtw89_ifs_clm_application { 5373 RTW89_IFS_CLM_INIT = 0, 5374 RTW89_IFS_CLM_BACKGROUND = 1, 5375 RTW89_IFS_CLM_ACS = 2, 5376 RTW89_IFS_CLM_DIG = 3, 5377 RTW89_IFS_CLM_TDMA_DIG = 4, 5378 RTW89_IFS_CLM_DBG = 5, 5379 RTW89_IFS_CLM_DBG_MANUAL = 6 5380 }; 5381 5382 enum rtw89_env_racing_lv { 5383 RTW89_RAC_RELEASE = 0, 5384 RTW89_RAC_LV_1 = 1, 5385 RTW89_RAC_LV_2 = 2, 5386 RTW89_RAC_LV_3 = 3, 5387 RTW89_RAC_LV_4 = 4, 5388 RTW89_RAC_MAX_NUM = 5 5389 }; 5390 5391 struct rtw89_ccx_para_info { 5392 enum rtw89_env_racing_lv rac_lv; 5393 u16 mntr_time; 5394 u8 nhm_manual_th_ofst; 5395 u8 nhm_manual_th0; 5396 enum rtw89_ifs_clm_application ifs_clm_app; 5397 u32 ifs_clm_manual_th_times; 5398 u32 ifs_clm_manual_th0; 5399 u8 fahm_manual_th_ofst; 5400 u8 fahm_manual_th0; 5401 u8 fahm_numer_opt; 5402 u8 fahm_denom_opt; 5403 }; 5404 5405 enum rtw89_ccx_edcca_opt_sc_idx { 5406 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5407 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5408 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5409 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5410 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5411 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5412 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5413 RTW89_CCX_EDCCA_SEG1_S3 = 7 5414 }; 5415 5416 enum rtw89_ccx_edcca_opt_bw_idx { 5417 RTW89_CCX_EDCCA_BW20_0 = 0, 5418 RTW89_CCX_EDCCA_BW20_1 = 1, 5419 RTW89_CCX_EDCCA_BW20_2 = 2, 5420 RTW89_CCX_EDCCA_BW20_3 = 3, 5421 RTW89_CCX_EDCCA_BW20_4 = 4, 5422 RTW89_CCX_EDCCA_BW20_5 = 5, 5423 RTW89_CCX_EDCCA_BW20_6 = 6, 5424 RTW89_CCX_EDCCA_BW20_7 = 7 5425 }; 5426 5427 #define RTW89_NHM_TH_NUM 11 5428 #define RTW89_FAHM_TH_NUM 11 5429 #define RTW89_NHM_RPT_NUM 12 5430 #define RTW89_FAHM_RPT_NUM 12 5431 #define RTW89_IFS_CLM_NUM 4 5432 struct rtw89_env_monitor_info { 5433 u8 ccx_watchdog_result; 5434 bool ccx_ongoing; 5435 u8 ccx_rac_lv; 5436 bool ccx_manual_ctrl; 5437 u16 ifs_clm_mntr_time; 5438 enum rtw89_ifs_clm_application ifs_clm_app; 5439 u16 ccx_period; 5440 u8 ccx_unit_idx; 5441 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5442 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5443 u16 ifs_clm_tx; 5444 u16 ifs_clm_edcca_excl_cca; 5445 u16 ifs_clm_ofdmfa; 5446 u16 ifs_clm_ofdmcca_excl_fa; 5447 u16 ifs_clm_cckfa; 5448 u16 ifs_clm_cckcca_excl_fa; 5449 u16 ifs_clm_total_ifs; 5450 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5451 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5452 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5453 u8 ifs_clm_tx_ratio; 5454 u8 ifs_clm_edcca_excl_cca_ratio; 5455 u8 ifs_clm_cck_fa_ratio; 5456 u8 ifs_clm_ofdm_fa_ratio; 5457 u8 ifs_clm_cck_cca_excl_fa_ratio; 5458 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5459 u16 ifs_clm_cck_fa_permil; 5460 u16 ifs_clm_ofdm_fa_permil; 5461 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5462 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5463 }; 5464 5465 enum rtw89_ser_rcvy_step { 5466 RTW89_SER_DRV_STOP_TX, 5467 RTW89_SER_DRV_STOP_RX, 5468 RTW89_SER_DRV_STOP_RUN, 5469 RTW89_SER_HAL_STOP_DMA, 5470 RTW89_SER_SUPPRESS_LOG, 5471 RTW89_NUM_OF_SER_FLAGS 5472 }; 5473 5474 struct rtw89_ser { 5475 u8 state; 5476 u8 alarm_event; 5477 bool prehandle_l1; 5478 5479 struct work_struct ser_hdl_work; 5480 struct delayed_work ser_alarm_work; 5481 const struct state_ent *st_tbl; 5482 const struct event_ent *ev_tbl; 5483 struct list_head msg_q; 5484 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5485 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5486 }; 5487 5488 enum rtw89_mac_ax_ps_mode { 5489 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5490 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5491 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5492 RTW89_MAC_AX_PS_MODE_MAX = 3, 5493 }; 5494 5495 enum rtw89_last_rpwm_mode { 5496 RTW89_LAST_RPWM_PS = 0x0, 5497 RTW89_LAST_RPWM_ACTIVE = 0x6, 5498 }; 5499 5500 struct rtw89_lps_parm { 5501 u8 macid; 5502 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5503 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5504 }; 5505 5506 struct rtw89_ppdu_sts_info { 5507 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 5508 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 5509 }; 5510 5511 struct rtw89_early_h2c { 5512 struct list_head list; 5513 u8 *h2c; 5514 u16 h2c_len; 5515 }; 5516 5517 struct rtw89_hw_scan_extra_op { 5518 bool set; 5519 u8 macid; 5520 struct rtw89_chan chan; 5521 }; 5522 5523 struct rtw89_hw_scan_info { 5524 struct rtw89_vif_link *scanning_vif; 5525 struct list_head pkt_list[NUM_NL80211_BANDS]; 5526 struct list_head chan_list; 5527 struct rtw89_chan op_chan; 5528 struct rtw89_hw_scan_extra_op extra_op; 5529 bool connected; 5530 bool abort; 5531 }; 5532 5533 enum rtw89_phy_bb_gain_band { 5534 RTW89_BB_GAIN_BAND_2G = 0, 5535 RTW89_BB_GAIN_BAND_5G_L = 1, 5536 RTW89_BB_GAIN_BAND_5G_M = 2, 5537 RTW89_BB_GAIN_BAND_5G_H = 3, 5538 RTW89_BB_GAIN_BAND_6G_L = 4, 5539 RTW89_BB_GAIN_BAND_6G_M = 5, 5540 RTW89_BB_GAIN_BAND_6G_H = 6, 5541 RTW89_BB_GAIN_BAND_6G_UH = 7, 5542 5543 RTW89_BB_GAIN_BAND_NR, 5544 }; 5545 5546 enum rtw89_phy_gain_band_be { 5547 RTW89_BB_GAIN_BAND_2G_BE = 0, 5548 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5549 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5550 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5551 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5552 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5553 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5554 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5555 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5556 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5557 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5558 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5559 5560 RTW89_BB_GAIN_BAND_NR_BE, 5561 }; 5562 5563 enum rtw89_phy_bb_bw_be { 5564 RTW89_BB_BW_20_40 = 0, 5565 RTW89_BB_BW_80_160_320 = 1, 5566 5567 RTW89_BB_BW_NR_BE, 5568 }; 5569 5570 enum rtw89_bw20_sc { 5571 RTW89_BW20_SC_20M = 1, 5572 RTW89_BW20_SC_40M = 2, 5573 RTW89_BW20_SC_80M = 4, 5574 RTW89_BW20_SC_160M = 8, 5575 RTW89_BW20_SC_320M = 16, 5576 }; 5577 5578 enum rtw89_cmac_table_bw { 5579 RTW89_CMAC_BW_20M = 0, 5580 RTW89_CMAC_BW_40M = 1, 5581 RTW89_CMAC_BW_80M = 2, 5582 RTW89_CMAC_BW_160M = 3, 5583 RTW89_CMAC_BW_320M = 4, 5584 5585 RTW89_CMAC_BW_NR, 5586 }; 5587 5588 enum rtw89_phy_bb_rxsc_num { 5589 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5590 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5591 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5592 }; 5593 5594 struct rtw89_phy_bb_gain_info { 5595 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5596 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5597 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5598 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5599 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5600 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5601 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5602 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5603 [RTW89_BB_RXSC_NUM_40]; 5604 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5605 [RTW89_BB_RXSC_NUM_80]; 5606 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5607 [RTW89_BB_RXSC_NUM_160]; 5608 }; 5609 5610 struct rtw89_phy_bb_gain_info_be { 5611 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5612 [LNA_GAIN_NUM]; 5613 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5614 [TIA_GAIN_NUM]; 5615 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5616 [RF_PATH_MAX][LNA_GAIN_NUM]; 5617 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5618 [RF_PATH_MAX][LNA_GAIN_NUM]; 5619 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5620 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5621 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5622 [RTW89_BW20_SC_20M]; 5623 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5624 [RTW89_BW20_SC_40M]; 5625 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5626 [RTW89_BW20_SC_80M]; 5627 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5628 [RTW89_BW20_SC_160M]; 5629 }; 5630 5631 struct rtw89_phy_efuse_gain { 5632 bool offset_valid; 5633 bool comp_valid; 5634 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5635 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5636 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5637 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5638 }; 5639 5640 #define RTW89_MAX_PATTERN_NUM 18 5641 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5642 #define RTW89_MAX_PATTERN_SIZE 128 5643 5644 struct rtw89_wow_cam_info { 5645 bool r_w; 5646 u8 idx; 5647 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5648 u16 crc; 5649 bool negative_pattern_match; 5650 bool skip_mac_hdr; 5651 bool uc; 5652 bool mc; 5653 bool bc; 5654 bool valid; 5655 }; 5656 5657 struct rtw89_wow_key_info { 5658 u8 ptk_tx_iv[8]; 5659 u8 valid_check; 5660 u8 symbol_check_en; 5661 u8 gtk_keyidx; 5662 u8 rsvd[5]; 5663 u8 ptk_rx_iv[8]; 5664 u8 gtk_rx_iv[4][8]; 5665 } __packed; 5666 5667 struct rtw89_wow_gtk_info { 5668 u8 kck[32]; 5669 u8 kek[32]; 5670 u8 tk1[16]; 5671 u8 txmickey[8]; 5672 u8 rxmickey[8]; 5673 __le32 igtk_keyid; 5674 __le64 ipn; 5675 u8 igtk[2][32]; 5676 u8 psk[32]; 5677 } __packed; 5678 5679 struct rtw89_wow_aoac_report { 5680 u8 rpt_ver; 5681 u8 sec_type; 5682 u8 key_idx; 5683 u8 pattern_idx; 5684 u8 rekey_ok; 5685 u8 ptk_tx_iv[8]; 5686 u8 eapol_key_replay_count[8]; 5687 u8 gtk[32]; 5688 u8 ptk_rx_iv[8]; 5689 u8 gtk_rx_iv[4][8]; 5690 u64 igtk_key_id; 5691 u64 igtk_ipn; 5692 u8 igtk[32]; 5693 u8 csa_pri_ch; 5694 u8 csa_bw; 5695 u8 csa_ch_offset; 5696 u8 csa_chsw_failed; 5697 u8 csa_ch_band; 5698 }; 5699 5700 struct rtw89_wow_param { 5701 struct rtw89_vif_link *rtwvif_link; 5702 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5703 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5704 struct rtw89_wow_key_info key_info; 5705 struct rtw89_wow_gtk_info gtk_info; 5706 struct rtw89_wow_aoac_report aoac_rpt; 5707 u8 pattern_cnt; 5708 u8 ptk_alg; 5709 u8 gtk_alg; 5710 u8 ptk_keyidx; 5711 u8 akm; 5712 5713 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5714 struct rtw89_wait_info wait; 5715 5716 bool pno_inited; 5717 struct list_head pno_pkt_list; 5718 struct cfg80211_sched_scan_request *nd_config; 5719 }; 5720 5721 struct rtw89_mcc_limit { 5722 bool enable; 5723 u16 max_tob; /* TU; max time offset behind */ 5724 u16 max_toa; /* TU; max time offset ahead */ 5725 u16 max_dur; /* TU */ 5726 }; 5727 5728 struct rtw89_mcc_policy { 5729 u8 c2h_rpt; 5730 u8 tx_null_early; 5731 u8 dis_tx_null; 5732 u8 in_curr_ch; 5733 u8 dis_sw_retry; 5734 u8 sw_retry_count; 5735 }; 5736 5737 struct rtw89_mcc_role { 5738 struct rtw89_vif_link *rtwvif_link; 5739 struct rtw89_mcc_policy policy; 5740 struct rtw89_mcc_limit limit; 5741 5742 const struct rtw89_mcc_courtesy_cfg *crtz; 5743 5744 /* only valid when running with FW MRC mechanism */ 5745 u8 slot_idx; 5746 5747 /* byte-array in LE order for FW */ 5748 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5749 u8 probe_count; 5750 5751 u16 duration; /* TU */ 5752 u16 beacon_interval; /* TU */ 5753 bool is_2ghz; 5754 bool is_go; 5755 bool is_gc; 5756 }; 5757 5758 struct rtw89_mcc_bt_role { 5759 u16 duration; /* TU */ 5760 }; 5761 5762 struct rtw89_mcc_courtesy_cfg { 5763 u8 slot_num; 5764 u8 macid_tgt; 5765 }; 5766 5767 struct rtw89_mcc_courtesy { 5768 struct rtw89_mcc_courtesy_cfg ref; 5769 struct rtw89_mcc_courtesy_cfg aux; 5770 }; 5771 5772 enum rtw89_mcc_plan { 5773 RTW89_MCC_PLAN_TAIL_BT, 5774 RTW89_MCC_PLAN_MID_BT, 5775 RTW89_MCC_PLAN_NO_BT, 5776 5777 NUM_OF_RTW89_MCC_PLAN, 5778 }; 5779 5780 struct rtw89_mcc_pattern { 5781 s16 tob_ref; /* TU; time offset behind of reference role */ 5782 s16 toa_ref; /* TU; time offset ahead of reference role */ 5783 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5784 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5785 5786 enum rtw89_mcc_plan plan; 5787 struct rtw89_mcc_courtesy courtesy; 5788 }; 5789 5790 struct rtw89_mcc_sync { 5791 bool enable; 5792 u16 offset; /* TU */ 5793 u8 macid_src; 5794 u8 band_src; 5795 u8 port_src; 5796 u8 macid_tgt; 5797 u8 band_tgt; 5798 u8 port_tgt; 5799 }; 5800 5801 struct rtw89_mcc_config { 5802 struct rtw89_mcc_pattern pattern; 5803 struct rtw89_mcc_sync sync; 5804 u64 start_tsf; 5805 u64 start_tsf_in_aux_domain; 5806 u64 prepare_delay; 5807 u16 mcc_interval; /* TU */ 5808 u16 beacon_offset; /* TU */ 5809 }; 5810 5811 enum rtw89_mcc_mode { 5812 RTW89_MCC_MODE_GO_STA, 5813 RTW89_MCC_MODE_GC_STA, 5814 }; 5815 5816 struct rtw89_mcc_info { 5817 struct rtw89_wait_info wait; 5818 5819 u8 group; 5820 enum rtw89_mcc_mode mode; 5821 struct rtw89_mcc_role role_ref; /* reference role */ 5822 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5823 struct rtw89_mcc_bt_role bt_role; 5824 struct rtw89_mcc_config config; 5825 }; 5826 5827 enum rtw89_mlo_mode { 5828 RTW89_MLO_MODE_MLSR = 0, 5829 5830 NUM_OF_RTW89_MLO_MODE, 5831 }; 5832 5833 struct rtw89_mlo_info { 5834 struct rtw89_wait_info wait; 5835 }; 5836 5837 struct rtw89_dev { 5838 struct ieee80211_hw *hw; 5839 struct device *dev; 5840 const struct ieee80211_ops *ops; 5841 5842 bool dbcc_en; 5843 bool support_mlo; 5844 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5845 struct rtw89_hw_scan_info scan_info; 5846 const struct rtw89_chip_info *chip; 5847 const struct rtw89_chip_variant *variant; 5848 const struct rtw89_pci_info *pci_info; 5849 const struct rtw89_rfe_parms *rfe_parms; 5850 struct rtw89_hal hal; 5851 struct rtw89_mcc_info mcc; 5852 struct rtw89_mlo_info mlo; 5853 struct rtw89_mac_info mac; 5854 struct rtw89_fw_info fw; 5855 struct rtw89_hci_info hci; 5856 struct rtw89_efuse efuse; 5857 struct rtw89_traffic_stats stats; 5858 struct rtw89_rfe_data *rfe_data; 5859 enum rtw89_custid custid; 5860 5861 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 5862 refcount_t refcount_ap_info; 5863 5864 struct list_head rtwvifs_list; 5865 /* used to protect rf read write */ 5866 struct mutex rf_mutex; 5867 struct workqueue_struct *txq_wq; 5868 struct work_struct txq_work; 5869 struct delayed_work txq_reinvoke_work; 5870 /* used to protect ba_list and forbid_ba_list */ 5871 spinlock_t ba_lock; 5872 /* txqs to setup ba session */ 5873 struct list_head ba_list; 5874 /* txqs to forbid ba session */ 5875 struct list_head forbid_ba_list; 5876 struct work_struct ba_work; 5877 /* used to protect rpwm */ 5878 spinlock_t rpwm_lock; 5879 5880 struct rtw89_cam_info cam_info; 5881 5882 struct sk_buff_head c2h_queue; 5883 struct wiphy_work c2h_work; 5884 struct wiphy_work ips_work; 5885 struct wiphy_work cancel_6ghz_probe_work; 5886 struct work_struct load_firmware_work; 5887 5888 struct list_head early_h2c_list; 5889 5890 struct rtw89_ser ser; 5891 5892 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5893 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5894 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5895 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5896 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5897 5898 struct rtw89_phy_stat phystat; 5899 struct rtw89_rfk_wait_info rfk_wait; 5900 struct rtw89_dack_info dack; 5901 struct rtw89_iqk_info iqk; 5902 struct rtw89_dpk_info dpk; 5903 struct rtw89_rfk_mcc_info rfk_mcc; 5904 struct rtw89_lck_info lck; 5905 struct rtw89_rx_dck_info rx_dck; 5906 bool is_tssi_mode[RF_PATH_MAX]; 5907 bool is_bt_iqk_timeout; 5908 5909 struct rtw89_fem_info fem; 5910 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5911 struct rtw89_tssi_info tssi; 5912 struct rtw89_power_trim_info pwr_trim; 5913 5914 struct rtw89_cfo_tracking_info cfo_tracking; 5915 union { 5916 struct rtw89_phy_bb_gain_info ax; 5917 struct rtw89_phy_bb_gain_info_be be; 5918 } bb_gain; 5919 struct rtw89_phy_efuse_gain efuse_gain; 5920 struct rtw89_phy_ul_tb_info ul_tb_info; 5921 struct rtw89_antdiv_info antdiv; 5922 5923 struct rtw89_bb_ctx { 5924 enum rtw89_phy_idx phy_idx; 5925 struct rtw89_env_monitor_info env_monitor; 5926 struct rtw89_dig_info dig; 5927 struct rtw89_phy_ch_info ch_info; 5928 struct rtw89_edcca_bak edcca_bak; 5929 } bbs[RTW89_PHY_NUM]; 5930 5931 struct wiphy_delayed_work track_work; 5932 struct wiphy_delayed_work chanctx_work; 5933 struct wiphy_delayed_work coex_act1_work; 5934 struct wiphy_delayed_work coex_bt_devinfo_work; 5935 struct wiphy_delayed_work coex_rfk_chk_work; 5936 struct wiphy_delayed_work cfo_track_work; 5937 struct wiphy_delayed_work mcc_prepare_done_work; 5938 struct delayed_work forbid_ba_work; 5939 struct wiphy_delayed_work antdiv_work; 5940 struct rtw89_ppdu_sts_info ppdu_sts; 5941 u8 total_sta_assoc; 5942 bool scanning; 5943 5944 struct rtw89_regulatory_info regulatory; 5945 struct rtw89_sar_info sar; 5946 struct rtw89_tas_info tas; 5947 struct rtw89_ant_gain_info ant_gain; 5948 5949 struct rtw89_btc btc; 5950 enum rtw89_ps_mode ps_mode; 5951 bool lps_enabled; 5952 5953 struct rtw89_wow_param wow; 5954 5955 /* napi structure */ 5956 struct net_device *netdev; 5957 struct napi_struct napi; 5958 int napi_budget_countdown; 5959 5960 struct rtw89_debugfs *debugfs; 5961 5962 /* HCI related data, keep last */ 5963 u8 priv[] __aligned(sizeof(void *)); 5964 }; 5965 5966 struct rtw89_link_conf_container { 5967 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 5968 }; 5969 5970 #define RTW89_VIF_IDLE_LINK_ID 0 5971 5972 struct rtw89_vif { 5973 struct rtw89_dev *rtwdev; 5974 struct list_head list; 5975 struct list_head mgnt_entry; 5976 struct rtw89_link_conf_container __rcu *snap_link_confs; 5977 5978 u8 mac_addr[ETH_ALEN]; 5979 __be32 ip_addr; 5980 5981 struct rtw89_traffic_stats stats; 5982 u32 tdls_peer; 5983 5984 struct ieee80211_scan_ies *scan_ies; 5985 struct cfg80211_scan_request *scan_req; 5986 5987 struct rtw89_roc roc; 5988 bool offchan; 5989 5990 enum rtw89_mlo_mode mlo_mode; 5991 5992 struct list_head dlink_pool; 5993 u8 links_inst_valid_num; 5994 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5995 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5996 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 5997 }; 5998 5999 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 6000 const struct rtw89_vif *rtwvif, 6001 unsigned int link_id) 6002 { 6003 *rtwvif_link = rtwvif->links[link_id]; 6004 return !!*rtwvif_link; 6005 } 6006 6007 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 6008 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6009 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 6010 6011 enum rtw89_sta_flags { 6012 RTW89_REMOTE_STA_IN_PS, 6013 6014 NUM_OF_RTW89_STA_FLAGS, 6015 }; 6016 6017 struct rtw89_sta { 6018 struct rtw89_dev *rtwdev; 6019 struct rtw89_vif *rtwvif; 6020 6021 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 6022 6023 bool disassoc; 6024 6025 struct sk_buff_head roc_queue; 6026 6027 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 6028 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 6029 6030 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 6031 6032 struct list_head dlink_pool; 6033 u8 links_inst_valid_num; 6034 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6035 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6036 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 6037 }; 6038 6039 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 6040 const struct rtw89_sta *rtwsta, 6041 unsigned int link_id) 6042 { 6043 *rtwsta_link = rtwsta->links[link_id]; 6044 return !!*rtwsta_link; 6045 } 6046 6047 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 6048 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6049 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 6050 6051 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 6052 { 6053 /* const after init, so no need to check if active first */ 6054 return rtwvif->links_inst[0].mac_id; 6055 } 6056 6057 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 6058 { 6059 /* const after init, so no need to check if active first */ 6060 return rtwvif->links_inst[0].port; 6061 } 6062 6063 static inline struct rtw89_vif_link * 6064 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 6065 { 6066 if (index >= rtwvif->links_inst_valid_num || 6067 !test_bit(index, rtwvif->links_inst_map)) 6068 return NULL; 6069 return &rtwvif->links_inst[index]; 6070 } 6071 6072 static inline 6073 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 6074 { 6075 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6076 6077 return rtwvif_link - rtwvif->links_inst; 6078 } 6079 6080 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 6081 { 6082 /* const after init, so no need to check if active first */ 6083 return rtwsta->links_inst[0].mac_id; 6084 } 6085 6086 static inline struct rtw89_sta_link * 6087 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 6088 { 6089 if (index >= rtwsta->links_inst_valid_num || 6090 !test_bit(index, rtwsta->links_inst_map)) 6091 return NULL; 6092 return &rtwsta->links_inst[index]; 6093 } 6094 6095 static inline 6096 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 6097 { 6098 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6099 6100 return rtwsta_link - rtwsta->links_inst; 6101 } 6102 6103 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 6104 { 6105 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6106 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6107 6108 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6109 rtwsta_link); 6110 } 6111 6112 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 6113 { 6114 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6115 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6116 6117 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6118 NULL); 6119 synchronize_rcu(); 6120 } 6121 6122 static inline struct rtw89_sta_link * 6123 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 6124 { 6125 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 6126 } 6127 6128 #define rtw89_get_designated_link(links_holder) \ 6129 ({ \ 6130 typeof(links_holder) p = links_holder; \ 6131 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 6132 }) 6133 6134 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 6135 struct rtw89_core_tx_request *tx_req) 6136 { 6137 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 6138 } 6139 6140 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 6141 { 6142 rtwdev->hci.ops->reset(rtwdev); 6143 } 6144 6145 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 6146 { 6147 return rtwdev->hci.ops->start(rtwdev); 6148 } 6149 6150 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 6151 { 6152 rtwdev->hci.ops->stop(rtwdev); 6153 } 6154 6155 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 6156 { 6157 return rtwdev->hci.ops->deinit(rtwdev); 6158 } 6159 6160 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 6161 { 6162 rtwdev->hci.ops->pause(rtwdev, pause); 6163 } 6164 6165 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 6166 { 6167 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 6168 } 6169 6170 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 6171 { 6172 rtwdev->hci.ops->recalc_int_mit(rtwdev); 6173 } 6174 6175 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 6176 { 6177 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 6178 } 6179 6180 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 6181 { 6182 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 6183 } 6184 6185 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 6186 { 6187 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 6188 } 6189 6190 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 6191 bool drop) 6192 { 6193 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6194 return; 6195 6196 if (rtwdev->hci.ops->flush_queues) 6197 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 6198 } 6199 6200 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 6201 { 6202 if (rtwdev->hci.ops->recovery_start) 6203 rtwdev->hci.ops->recovery_start(rtwdev); 6204 } 6205 6206 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 6207 { 6208 if (rtwdev->hci.ops->recovery_complete) 6209 rtwdev->hci.ops->recovery_complete(rtwdev); 6210 } 6211 6212 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 6213 { 6214 if (rtwdev->hci.ops->enable_intr) 6215 rtwdev->hci.ops->enable_intr(rtwdev); 6216 } 6217 6218 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 6219 { 6220 if (rtwdev->hci.ops->disable_intr) 6221 rtwdev->hci.ops->disable_intr(rtwdev); 6222 } 6223 6224 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 6225 { 6226 if (rtwdev->hci.ops->ctrl_txdma_ch) 6227 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 6228 } 6229 6230 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6231 { 6232 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6233 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6234 } 6235 6236 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6237 { 6238 if (rtwdev->hci.ops->ctrl_trxhci) 6239 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6240 } 6241 6242 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6243 { 6244 int ret = 0; 6245 6246 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6247 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6248 return ret; 6249 } 6250 6251 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6252 { 6253 if (rtwdev->hci.ops->clr_idx_all) 6254 rtwdev->hci.ops->clr_idx_all(rtwdev); 6255 } 6256 6257 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6258 { 6259 int ret = 0; 6260 6261 if (rtwdev->hci.ops->rst_bdram) 6262 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6263 return ret; 6264 } 6265 6266 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6267 { 6268 if (rtwdev->hci.ops->clear) 6269 rtwdev->hci.ops->clear(rtwdev, pdev); 6270 } 6271 6272 static inline 6273 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6274 { 6275 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6276 6277 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 6278 } 6279 6280 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6281 { 6282 return rtwdev->hci.ops->read8(rtwdev, addr); 6283 } 6284 6285 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6286 { 6287 return rtwdev->hci.ops->read16(rtwdev, addr); 6288 } 6289 6290 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6291 { 6292 return rtwdev->hci.ops->read32(rtwdev, addr); 6293 } 6294 6295 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6296 { 6297 rtwdev->hci.ops->write8(rtwdev, addr, data); 6298 } 6299 6300 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6301 { 6302 rtwdev->hci.ops->write16(rtwdev, addr, data); 6303 } 6304 6305 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6306 { 6307 rtwdev->hci.ops->write32(rtwdev, addr, data); 6308 } 6309 6310 static inline void 6311 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6312 { 6313 u8 val; 6314 6315 val = rtw89_read8(rtwdev, addr); 6316 rtw89_write8(rtwdev, addr, val | bit); 6317 } 6318 6319 static inline void 6320 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6321 { 6322 u16 val; 6323 6324 val = rtw89_read16(rtwdev, addr); 6325 rtw89_write16(rtwdev, addr, val | bit); 6326 } 6327 6328 static inline void 6329 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6330 { 6331 u32 val; 6332 6333 val = rtw89_read32(rtwdev, addr); 6334 rtw89_write32(rtwdev, addr, val | bit); 6335 } 6336 6337 static inline void 6338 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6339 { 6340 u8 val; 6341 6342 val = rtw89_read8(rtwdev, addr); 6343 rtw89_write8(rtwdev, addr, val & ~bit); 6344 } 6345 6346 static inline void 6347 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6348 { 6349 u16 val; 6350 6351 val = rtw89_read16(rtwdev, addr); 6352 rtw89_write16(rtwdev, addr, val & ~bit); 6353 } 6354 6355 static inline void 6356 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6357 { 6358 u32 val; 6359 6360 val = rtw89_read32(rtwdev, addr); 6361 rtw89_write32(rtwdev, addr, val & ~bit); 6362 } 6363 6364 static inline u32 6365 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6366 { 6367 u32 shift = __ffs(mask); 6368 u32 orig; 6369 u32 ret; 6370 6371 orig = rtw89_read32(rtwdev, addr); 6372 ret = (orig & mask) >> shift; 6373 6374 return ret; 6375 } 6376 6377 static inline u16 6378 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6379 { 6380 u32 shift = __ffs(mask); 6381 u32 orig; 6382 u32 ret; 6383 6384 orig = rtw89_read16(rtwdev, addr); 6385 ret = (orig & mask) >> shift; 6386 6387 return ret; 6388 } 6389 6390 static inline u8 6391 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6392 { 6393 u32 shift = __ffs(mask); 6394 u32 orig; 6395 u32 ret; 6396 6397 orig = rtw89_read8(rtwdev, addr); 6398 ret = (orig & mask) >> shift; 6399 6400 return ret; 6401 } 6402 6403 static inline void 6404 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6405 { 6406 u32 shift = __ffs(mask); 6407 u32 orig; 6408 u32 set; 6409 6410 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6411 6412 orig = rtw89_read32(rtwdev, addr); 6413 set = (orig & ~mask) | ((data << shift) & mask); 6414 rtw89_write32(rtwdev, addr, set); 6415 } 6416 6417 static inline void 6418 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6419 { 6420 u32 shift; 6421 u16 orig, set; 6422 6423 mask &= 0xffff; 6424 shift = __ffs(mask); 6425 6426 orig = rtw89_read16(rtwdev, addr); 6427 set = (orig & ~mask) | ((data << shift) & mask); 6428 rtw89_write16(rtwdev, addr, set); 6429 } 6430 6431 static inline void 6432 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6433 { 6434 u32 shift; 6435 u8 orig, set; 6436 6437 mask &= 0xff; 6438 shift = __ffs(mask); 6439 6440 orig = rtw89_read8(rtwdev, addr); 6441 set = (orig & ~mask) | ((data << shift) & mask); 6442 rtw89_write8(rtwdev, addr, set); 6443 } 6444 6445 static inline u32 6446 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6447 u32 addr, u32 mask) 6448 { 6449 u32 val; 6450 6451 mutex_lock(&rtwdev->rf_mutex); 6452 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6453 mutex_unlock(&rtwdev->rf_mutex); 6454 6455 return val; 6456 } 6457 6458 static inline void 6459 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6460 u32 addr, u32 mask, u32 data) 6461 { 6462 mutex_lock(&rtwdev->rf_mutex); 6463 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6464 mutex_unlock(&rtwdev->rf_mutex); 6465 } 6466 6467 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6468 { 6469 void *p = rtwtxq; 6470 6471 return container_of(p, struct ieee80211_txq, drv_priv); 6472 } 6473 6474 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6475 struct ieee80211_txq *txq) 6476 { 6477 struct rtw89_txq *rtwtxq; 6478 6479 if (!txq) 6480 return; 6481 6482 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6483 INIT_LIST_HEAD(&rtwtxq->list); 6484 } 6485 6486 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6487 { 6488 void *p = rtwvif; 6489 6490 return container_of(p, struct ieee80211_vif, drv_priv); 6491 } 6492 6493 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6494 { 6495 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6496 } 6497 6498 static inline 6499 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6500 { 6501 return rtwvif_to_vif(rtwvif_link->rtwvif); 6502 } 6503 6504 static inline 6505 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6506 { 6507 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6508 } 6509 6510 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6511 { 6512 return (struct rtw89_vif *)vif->drv_priv; 6513 } 6514 6515 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6516 { 6517 return vif ? vif_to_rtwvif(vif) : NULL; 6518 } 6519 6520 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6521 { 6522 void *p = rtwsta; 6523 6524 return container_of(p, struct ieee80211_sta, drv_priv); 6525 } 6526 6527 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6528 { 6529 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6530 } 6531 6532 static inline 6533 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6534 { 6535 return rtwsta_to_sta(rtwsta_link->rtwsta); 6536 } 6537 6538 static inline 6539 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6540 { 6541 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6542 } 6543 6544 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6545 { 6546 return (struct rtw89_sta *)sta->drv_priv; 6547 } 6548 6549 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6550 { 6551 return sta ? sta_to_rtwsta(sta) : NULL; 6552 } 6553 6554 static inline struct ieee80211_bss_conf * 6555 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6556 { 6557 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6558 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6559 struct rtw89_link_conf_container *snap; 6560 struct ieee80211_bss_conf *bss_conf; 6561 6562 snap = rcu_dereference(rtwvif->snap_link_confs); 6563 if (snap) { 6564 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6565 goto out; 6566 } 6567 6568 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6569 6570 out: 6571 if (unlikely(!bss_conf)) { 6572 *nolink = true; 6573 return &vif->bss_conf; 6574 } 6575 6576 *nolink = false; 6577 return bss_conf; 6578 } 6579 6580 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6581 ({ \ 6582 typeof(rtwvif_link) p = rtwvif_link; \ 6583 struct ieee80211_bss_conf *bss_conf; \ 6584 bool nolink; \ 6585 \ 6586 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6587 if (unlikely(nolink) && (assert)) \ 6588 rtw89_err(p->rtwvif->rtwdev, \ 6589 "%s: cannot find exact bss_conf for link_id %u\n",\ 6590 __func__, p->link_id); \ 6591 bss_conf; \ 6592 }) 6593 6594 static inline struct ieee80211_link_sta * 6595 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6596 { 6597 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6598 struct ieee80211_link_sta *link_sta; 6599 6600 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6601 if (unlikely(!link_sta)) { 6602 *nolink = true; 6603 return &sta->deflink; 6604 } 6605 6606 *nolink = false; 6607 return link_sta; 6608 } 6609 6610 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6611 ({ \ 6612 typeof(rtwsta_link) p = rtwsta_link; \ 6613 struct ieee80211_link_sta *link_sta; \ 6614 bool nolink; \ 6615 \ 6616 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6617 if (unlikely(nolink) && (assert)) \ 6618 rtw89_err(p->rtwsta->rtwdev, \ 6619 "%s: cannot find exact link_sta for link_id %u\n",\ 6620 __func__, p->link_id); \ 6621 link_sta; \ 6622 }) 6623 6624 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6625 { 6626 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6627 return RATE_INFO_BW_160; 6628 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6629 return RATE_INFO_BW_80; 6630 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6631 return RATE_INFO_BW_40; 6632 else 6633 return RATE_INFO_BW_20; 6634 } 6635 6636 static inline 6637 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6638 { 6639 switch (hw_band) { 6640 default: 6641 case RTW89_BAND_2G: 6642 return NL80211_BAND_2GHZ; 6643 case RTW89_BAND_5G: 6644 return NL80211_BAND_5GHZ; 6645 case RTW89_BAND_6G: 6646 return NL80211_BAND_6GHZ; 6647 } 6648 } 6649 6650 static inline 6651 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6652 { 6653 switch (nl_band) { 6654 default: 6655 case NL80211_BAND_2GHZ: 6656 return RTW89_BAND_2G; 6657 case NL80211_BAND_5GHZ: 6658 return RTW89_BAND_5G; 6659 case NL80211_BAND_6GHZ: 6660 return RTW89_BAND_6G; 6661 } 6662 } 6663 6664 static inline 6665 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6666 { 6667 switch (width) { 6668 default: 6669 WARN(1, "Not support bandwidth %d\n", width); 6670 fallthrough; 6671 case NL80211_CHAN_WIDTH_20_NOHT: 6672 case NL80211_CHAN_WIDTH_20: 6673 return RTW89_CHANNEL_WIDTH_20; 6674 case NL80211_CHAN_WIDTH_40: 6675 return RTW89_CHANNEL_WIDTH_40; 6676 case NL80211_CHAN_WIDTH_80: 6677 return RTW89_CHANNEL_WIDTH_80; 6678 case NL80211_CHAN_WIDTH_160: 6679 return RTW89_CHANNEL_WIDTH_160; 6680 } 6681 } 6682 6683 static inline 6684 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6685 { 6686 switch (rua) { 6687 default: 6688 WARN(1, "Invalid RU allocation: %d\n", rua); 6689 fallthrough; 6690 case 0 ... 36: 6691 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6692 case 37 ... 52: 6693 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6694 case 53 ... 60: 6695 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6696 case 61 ... 64: 6697 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6698 case 65 ... 66: 6699 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6700 case 67: 6701 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6702 case 68: 6703 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6704 } 6705 } 6706 6707 static inline 6708 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6709 struct rtw89_sta_link *rtwsta_link) 6710 { 6711 if (rtwsta_link) { 6712 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6713 6714 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6715 return &rtwsta_link->addr_cam; 6716 } 6717 return &rtwvif_link->addr_cam; 6718 } 6719 6720 static inline 6721 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6722 struct rtw89_sta_link *rtwsta_link) 6723 { 6724 if (rtwsta_link) { 6725 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6726 6727 if (sta->tdls) 6728 return &rtwsta_link->bssid_cam; 6729 } 6730 return &rtwvif_link->bssid_cam; 6731 } 6732 6733 static inline 6734 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6735 struct rtw89_channel_help_params *p, 6736 const struct rtw89_chan *chan, 6737 enum rtw89_mac_idx mac_idx, 6738 enum rtw89_phy_idx phy_idx) 6739 { 6740 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6741 mac_idx, phy_idx); 6742 } 6743 6744 static inline 6745 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6746 struct rtw89_channel_help_params *p, 6747 const struct rtw89_chan *chan, 6748 enum rtw89_mac_idx mac_idx, 6749 enum rtw89_phy_idx phy_idx) 6750 { 6751 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6752 mac_idx, phy_idx); 6753 } 6754 6755 static inline 6756 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6757 enum rtw89_chanctx_idx idx) 6758 { 6759 struct rtw89_hal *hal = &rtwdev->hal; 6760 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6761 6762 if (roc_idx == idx) 6763 return &hal->roc_chandef; 6764 6765 return &hal->chanctx[idx].chandef; 6766 } 6767 6768 static inline 6769 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6770 enum rtw89_chanctx_idx idx) 6771 { 6772 struct rtw89_hal *hal = &rtwdev->hal; 6773 6774 return &hal->chanctx[idx].chan; 6775 } 6776 6777 static inline 6778 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6779 enum rtw89_chanctx_idx idx) 6780 { 6781 struct rtw89_hal *hal = &rtwdev->hal; 6782 6783 return &hal->chanctx[idx].rcd; 6784 } 6785 6786 static inline 6787 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6788 { 6789 const struct rtw89_chanctx *chanctx = 6790 container_of_const(chan, struct rtw89_chanctx, chan); 6791 6792 return &chanctx->rcd; 6793 } 6794 6795 static inline 6796 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6797 { 6798 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6799 6800 if (rtwvif_link) 6801 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6802 else 6803 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6804 } 6805 6806 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6807 { 6808 const struct rtw89_chip_info *chip = rtwdev->chip; 6809 6810 if (chip->ops->fem_setup) 6811 chip->ops->fem_setup(rtwdev); 6812 } 6813 6814 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6815 { 6816 const struct rtw89_chip_info *chip = rtwdev->chip; 6817 6818 if (chip->ops->rfe_gpio) 6819 chip->ops->rfe_gpio(rtwdev); 6820 } 6821 6822 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6823 { 6824 const struct rtw89_chip_info *chip = rtwdev->chip; 6825 6826 if (chip->ops->rfk_hw_init) 6827 chip->ops->rfk_hw_init(rtwdev); 6828 } 6829 6830 static inline 6831 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6832 { 6833 const struct rtw89_chip_info *chip = rtwdev->chip; 6834 6835 if (chip->ops->bb_preinit) 6836 chip->ops->bb_preinit(rtwdev, phy_idx); 6837 } 6838 6839 static inline 6840 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6841 { 6842 const struct rtw89_chip_info *chip = rtwdev->chip; 6843 6844 if (!chip->ops->bb_postinit) 6845 return; 6846 6847 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6848 6849 if (rtwdev->dbcc_en) 6850 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6851 } 6852 6853 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6854 { 6855 const struct rtw89_chip_info *chip = rtwdev->chip; 6856 6857 if (chip->ops->bb_sethw) 6858 chip->ops->bb_sethw(rtwdev); 6859 } 6860 6861 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6862 { 6863 const struct rtw89_chip_info *chip = rtwdev->chip; 6864 6865 if (chip->ops->rfk_init) 6866 chip->ops->rfk_init(rtwdev); 6867 } 6868 6869 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6870 { 6871 const struct rtw89_chip_info *chip = rtwdev->chip; 6872 6873 if (chip->ops->rfk_init_late) 6874 chip->ops->rfk_init_late(rtwdev); 6875 } 6876 6877 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6878 struct rtw89_vif_link *rtwvif_link) 6879 { 6880 const struct rtw89_chip_info *chip = rtwdev->chip; 6881 6882 if (chip->ops->rfk_channel) 6883 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6884 } 6885 6886 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6887 enum rtw89_phy_idx phy_idx, 6888 const struct rtw89_chan *chan) 6889 { 6890 const struct rtw89_chip_info *chip = rtwdev->chip; 6891 6892 if (chip->ops->rfk_band_changed) 6893 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6894 } 6895 6896 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6897 struct rtw89_vif_link *rtwvif_link, bool start) 6898 { 6899 const struct rtw89_chip_info *chip = rtwdev->chip; 6900 6901 if (chip->ops->rfk_scan) 6902 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6903 } 6904 6905 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6906 { 6907 const struct rtw89_chip_info *chip = rtwdev->chip; 6908 6909 if (chip->ops->rfk_track) 6910 chip->ops->rfk_track(rtwdev); 6911 } 6912 6913 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6914 { 6915 const struct rtw89_chip_info *chip = rtwdev->chip; 6916 6917 if (!chip->ops->set_txpwr_ctrl) 6918 return; 6919 6920 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6921 if (rtwdev->dbcc_en) 6922 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6923 } 6924 6925 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6926 { 6927 const struct rtw89_chip_info *chip = rtwdev->chip; 6928 6929 if (chip->ops->power_trim) 6930 chip->ops->power_trim(rtwdev); 6931 } 6932 6933 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6934 enum rtw89_phy_idx phy_idx) 6935 { 6936 const struct rtw89_chip_info *chip = rtwdev->chip; 6937 6938 if (chip->ops->init_txpwr_unit) 6939 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6940 } 6941 6942 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6943 { 6944 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6945 if (rtwdev->dbcc_en) 6946 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6947 } 6948 6949 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6950 enum rtw89_rf_path rf_path) 6951 { 6952 const struct rtw89_chip_info *chip = rtwdev->chip; 6953 6954 if (!chip->ops->get_thermal) 6955 return 0x10; 6956 6957 return chip->ops->get_thermal(rtwdev, rf_path); 6958 } 6959 6960 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev, 6961 const struct rtw89_chan *chan) 6962 { 6963 const struct rtw89_chip_info *chip = rtwdev->chip; 6964 6965 if (!chip->ops->chan_to_rf18_val) 6966 return 0; 6967 6968 return chip->ops->chan_to_rf18_val(rtwdev, chan); 6969 } 6970 6971 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6972 struct rtw89_rx_phy_ppdu *phy_ppdu, 6973 struct ieee80211_rx_status *status) 6974 { 6975 const struct rtw89_chip_info *chip = rtwdev->chip; 6976 6977 if (chip->ops->query_ppdu) 6978 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6979 } 6980 6981 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 6982 struct rtw89_rx_phy_ppdu *phy_ppdu) 6983 { 6984 const struct rtw89_chip_info *chip = rtwdev->chip; 6985 6986 if (chip->ops->convert_rpl_to_rssi) 6987 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 6988 } 6989 6990 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 6991 struct rtw89_rx_desc_info *desc_info, 6992 struct ieee80211_rx_status *rx_status) 6993 { 6994 const struct rtw89_chip_info *chip = rtwdev->chip; 6995 6996 if (chip->ops->phy_rpt_to_rssi) 6997 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 6998 } 6999 7000 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 7001 enum rtw89_phy_idx phy_idx) 7002 { 7003 const struct rtw89_chip_info *chip = rtwdev->chip; 7004 7005 if (chip->ops->ctrl_nbtg_bt_tx) 7006 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 7007 } 7008 7009 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 7010 { 7011 const struct rtw89_chip_info *chip = rtwdev->chip; 7012 7013 if (chip->ops->cfg_txrx_path) 7014 chip->ops->cfg_txrx_path(rtwdev); 7015 } 7016 7017 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 7018 enum rtw89_phy_idx phy_idx) 7019 { 7020 const struct rtw89_chip_info *chip = rtwdev->chip; 7021 7022 if (chip->ops->digital_pwr_comp) 7023 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 7024 } 7025 7026 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 7027 const struct rtw89_txpwr_table *tbl) 7028 { 7029 tbl->load(rtwdev, tbl); 7030 } 7031 7032 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 7033 { 7034 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 7035 const struct rtw89_regd *regd = regulatory->regd; 7036 u8 txpwr_regd = regd->txpwr_regd[band]; 7037 7038 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK) 7039 return RTW89_ETSI; 7040 7041 return txpwr_regd; 7042 } 7043 7044 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 7045 enum rtw89_phy_idx phy_idx) 7046 { 7047 const struct rtw89_chip_info *chip = rtwdev->chip; 7048 7049 if (chip->ops->ctrl_btg_bt_rx) 7050 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 7051 } 7052 7053 static inline 7054 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 7055 struct rtw89_rx_desc_info *desc_info, 7056 u8 *data, u32 data_offset) 7057 { 7058 const struct rtw89_chip_info *chip = rtwdev->chip; 7059 7060 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 7061 } 7062 7063 static inline 7064 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 7065 struct rtw89_tx_desc_info *desc_info, 7066 void *txdesc) 7067 { 7068 const struct rtw89_chip_info *chip = rtwdev->chip; 7069 7070 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 7071 } 7072 7073 static inline 7074 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 7075 struct rtw89_tx_desc_info *desc_info, 7076 void *txdesc) 7077 { 7078 const struct rtw89_chip_info *chip = rtwdev->chip; 7079 7080 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 7081 } 7082 7083 static inline 7084 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 7085 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 7086 { 7087 const struct rtw89_chip_info *chip = rtwdev->chip; 7088 7089 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 7090 } 7091 7092 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 7093 { 7094 const struct rtw89_chip_info *chip = rtwdev->chip; 7095 7096 chip->ops->cfg_ctrl_path(rtwdev, wl); 7097 } 7098 7099 static inline 7100 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 7101 u32 *tx_en, enum rtw89_sch_tx_sel sel) 7102 { 7103 const struct rtw89_chip_info *chip = rtwdev->chip; 7104 7105 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 7106 } 7107 7108 static inline 7109 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 7110 { 7111 const struct rtw89_chip_info *chip = rtwdev->chip; 7112 7113 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 7114 } 7115 7116 static inline 7117 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 7118 struct rtw89_vif_link *rtwvif_link, 7119 struct rtw89_sta_link *rtwsta_link) 7120 { 7121 const struct rtw89_chip_info *chip = rtwdev->chip; 7122 7123 if (!chip->ops->h2c_dctl_sec_cam) 7124 return 0; 7125 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 7126 } 7127 7128 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 7129 { 7130 __le16 fc = hdr->frame_control; 7131 7132 if (ieee80211_has_tods(fc)) 7133 return hdr->addr1; 7134 else if (ieee80211_has_fromds(fc)) 7135 return hdr->addr2; 7136 else 7137 return hdr->addr3; 7138 } 7139 7140 static inline 7141 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 7142 { 7143 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 7144 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 7145 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 7146 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 7147 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 7148 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 7149 return true; 7150 return false; 7151 } 7152 7153 static inline 7154 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 7155 { 7156 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 7157 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 7158 return true; 7159 7160 return false; 7161 } 7162 7163 static inline 7164 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 7165 { 7166 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 7167 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 7168 return true; 7169 7170 return false; 7171 } 7172 7173 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 7174 enum rtw89_fw_type type) 7175 { 7176 struct rtw89_fw_info *fw_info = &rtwdev->fw; 7177 7178 switch (type) { 7179 case RTW89_FW_WOWLAN: 7180 return &fw_info->wowlan; 7181 case RTW89_FW_LOGFMT: 7182 return &fw_info->log.suit; 7183 case RTW89_FW_BBMCU0: 7184 return &fw_info->bbmcu0; 7185 case RTW89_FW_BBMCU1: 7186 return &fw_info->bbmcu1; 7187 default: 7188 break; 7189 } 7190 7191 return &fw_info->normal; 7192 } 7193 7194 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 7195 unsigned int length) 7196 { 7197 struct sk_buff *skb; 7198 7199 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 7200 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 7201 if (!skb) 7202 return NULL; 7203 7204 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 7205 return skb; 7206 } 7207 7208 return dev_alloc_skb(length); 7209 } 7210 7211 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7212 struct rtw89_tx_skb_data *skb_data, 7213 bool tx_done) 7214 { 7215 struct rtw89_tx_wait_info *wait; 7216 7217 rcu_read_lock(); 7218 7219 wait = rcu_dereference(skb_data->wait); 7220 if (!wait) 7221 goto out; 7222 7223 wait->tx_done = tx_done; 7224 complete(&wait->completion); 7225 7226 out: 7227 rcu_read_unlock(); 7228 } 7229 7230 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 7231 { 7232 switch (rtwdev->mlo_dbcc_mode) { 7233 case MLO_1_PLUS_1_1RF: 7234 case MLO_1_PLUS_1_2RF: 7235 case DBCC_LEGACY: 7236 return true; 7237 default: 7238 return false; 7239 } 7240 } 7241 7242 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 7243 { 7244 if (!rtwdev->dbcc_en) 7245 return BIT(RTW89_PHY_0); 7246 7247 switch (rtwdev->mlo_dbcc_mode) { 7248 case MLO_0_PLUS_2_1RF: 7249 case MLO_0_PLUS_2_2RF: 7250 return BIT(RTW89_PHY_1); 7251 case MLO_1_PLUS_1_1RF: 7252 case MLO_1_PLUS_1_2RF: 7253 case MLO_2_PLUS_2_2RF: 7254 case DBCC_LEGACY: 7255 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 7256 case MLO_2_PLUS_0_1RF: 7257 case MLO_2_PLUS_0_2RF: 7258 default: 7259 return BIT(RTW89_PHY_0); 7260 } 7261 } 7262 7263 #define rtw89_for_each_active_bb(rtwdev, bb) \ 7264 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 7265 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 7266 if (__active_bb_bitmap & BIT(__phy_idx) && \ 7267 (bb = &rtwdev->bbs[__phy_idx])) 7268 7269 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 7270 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 7271 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 7272 if ((bb = &rtwdev->bbs[__phy_idx])) 7273 7274 static inline 7275 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 7276 enum rtw89_phy_idx phy_idx) 7277 { 7278 if (phy_idx >= RTW89_PHY_NUM) 7279 return &rtwdev->bbs[RTW89_PHY_0]; 7280 7281 return &rtwdev->bbs[phy_idx]; 7282 } 7283 7284 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7285 { 7286 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7287 7288 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7289 return true; 7290 7291 return false; 7292 } 7293 7294 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7295 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7296 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7297 struct sk_buff *skb, bool fwdl); 7298 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7299 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7300 int qsel, unsigned int timeout); 7301 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7302 struct rtw89_tx_desc_info *desc_info, 7303 void *txdesc); 7304 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7305 struct rtw89_tx_desc_info *desc_info, 7306 void *txdesc); 7307 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7308 struct rtw89_tx_desc_info *desc_info, 7309 void *txdesc); 7310 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7311 struct rtw89_tx_desc_info *desc_info, 7312 void *txdesc); 7313 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7314 struct rtw89_tx_desc_info *desc_info, 7315 void *txdesc); 7316 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7317 struct rtw89_rx_desc_info *desc_info, 7318 struct sk_buff *skb); 7319 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7320 struct rtw89_rx_desc_info *desc_info, 7321 u8 *data, u32 data_offset); 7322 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7323 struct rtw89_rx_desc_info *desc_info, 7324 u8 *data, u32 data_offset); 7325 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7326 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7327 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7328 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7329 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7330 struct rtw89_vif_link *rtwvif_link, 7331 struct rtw89_sta_link *rtwsta_link); 7332 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7333 struct rtw89_vif_link *rtwvif_link, 7334 struct rtw89_sta_link *rtwsta_link); 7335 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7336 struct rtw89_vif_link *rtwvif_link, 7337 struct rtw89_sta_link *rtwsta_link); 7338 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7339 struct rtw89_vif_link *rtwvif_link, 7340 struct rtw89_sta_link *rtwsta_link); 7341 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7342 struct rtw89_vif_link *rtwvif_link, 7343 struct rtw89_sta_link *rtwsta_link); 7344 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7345 struct ieee80211_sta *sta, 7346 struct cfg80211_tid_config *tid_config); 7347 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7348 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7349 int rtw89_core_init(struct rtw89_dev *rtwdev); 7350 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7351 int rtw89_core_register(struct rtw89_dev *rtwdev); 7352 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7353 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7354 u32 bus_data_size, 7355 const struct rtw89_chip_info *chip, 7356 const struct rtw89_chip_variant *variant); 7357 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7358 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7359 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7360 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7361 u8 mac_id, u8 port); 7362 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7363 struct rtw89_sta *rtwsta, u8 mac_id); 7364 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7365 unsigned int link_id); 7366 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7367 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7368 unsigned int link_id); 7369 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7370 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7371 const struct rtw89_6ghz_span * 7372 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7373 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7374 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7375 struct rtw89_chan *chan); 7376 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7377 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7378 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7379 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7380 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7381 struct rtw89_sta_link *rtwsta_link, u8 tid, 7382 u8 *cam_idx); 7383 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7384 struct rtw89_sta_link *rtwsta_link, u8 tid, 7385 u8 *cam_idx); 7386 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7387 struct ieee80211_sta *sta); 7388 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7389 struct ieee80211_sta *sta); 7390 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7391 struct ieee80211_sta *sta); 7392 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7393 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7394 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7395 struct rtw89_vif_link *rtwvif_link); 7396 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 7397 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7398 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7399 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 7400 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7401 struct rtw89_traffic_stats *stats); 7402 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 7403 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7404 const struct rtw89_completion_data *data); 7405 int rtw89_core_start(struct rtw89_dev *rtwdev); 7406 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7407 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7408 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7409 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7410 bool qos, bool ps, int timeout); 7411 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 7412 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7413 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7414 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7415 const u8 *mac_addr, bool hw_scan); 7416 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7417 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7418 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7419 bool active); 7420 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7421 struct rtw89_vif_link *rtwvif_link, 7422 struct ieee80211_bss_conf *bss_conf); 7423 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7424 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7425 unsigned int link_id); 7426 7427 #endif 7428