1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/leds.h> 14 #include <linux/led-class-multicolor.h> 15 #include <linux/workqueue.h> 16 #include <net/mac80211.h> 17 18 struct rtw89_dev; 19 struct rtw89_bb_ctx; 20 struct rtw89_pci_info; 21 struct rtw89_usb_info; 22 struct rtw89_mac_gen_def; 23 struct rtw89_phy_gen_def; 24 struct rtw89_fw_blacklist; 25 struct rtw89_efuse_block_cfg; 26 struct rtw89_h2c_rf_tssi; 27 struct rtw89_fw_txpwr_track_cfg; 28 struct rtw89_phy_rfk_log_fmt; 29 struct rtw89_phy_calc_efuse_gain; 30 union rtw89_phy_sts_ie09; 31 struct rtw89_phy_sts_ie10; 32 struct rtw89_debugfs; 33 struct rtw89_regd_data; 34 struct rtw89_wow_cam_info; 35 struct rtw89_bb_wrap_data; 36 struct rtw89_fw_cmd_ofld_info; 37 38 extern const struct ieee80211_ops rtw89_ops; 39 40 #define MASKBYTE0 0xff 41 #define MASKBYTE1 0xff00 42 #define MASKBYTE2 0xff0000 43 #define MASKBYTE3 0xff000000 44 #define MASKBYTE4 0xff00000000ULL 45 #define MASKHWORD 0xffff0000 46 #define MASKLWORD 0x0000ffff 47 #define MASKDWORD 0xffffffff 48 #define RFREG_MASK 0xfffff 49 #define INV_RF_DATA 0xffffffff 50 #define BYPASS_CR_DATA 0xbabecafe 51 #define RTW89_R32_EA 0xEAEAEAEA 52 #define RTW89_R32_DEAD 0xDEADBEEF 53 54 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 55 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100) 56 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 57 #define RTW89_PS_HANG_MAX_CNT 3 58 #define CFO_TRACK_MAX_USER 64 59 #define MAX_RSSI 110 60 #define RSSI_FACTOR 1 61 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 62 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 63 #define DELTA_SWINGIDX_SIZE 30 64 65 #define RTW89_RADIOTAP_ROOM_VHT sizeof(struct ieee80211_radiotap_vht) 66 #define RTW89_RADIOTAP_ROOM_HE (sizeof(struct ieee80211_radiotap_he) + \ 67 sizeof(struct ieee80211_radiotap_he_mu)) 68 #define RTW89_RADIOTAP_ROOM_EHT \ 69 (sizeof(struct ieee80211_radiotap_tlv) + \ 70 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 71 sizeof(struct ieee80211_radiotap_tlv) + \ 72 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 73 #define RTW89_RADIOTAP_ROOM \ 74 ALIGN(max3(RTW89_RADIOTAP_ROOM_VHT, RTW89_RADIOTAP_ROOM_HE, \ 75 RTW89_RADIOTAP_ROOM_EHT), 64) 76 77 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 78 #define RTW89_HTC_VARIANT_HE 3 79 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 80 #define RTW89_HTC_VARIANT_HE_CID_OM 1 81 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 82 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 83 84 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 85 enum htc_om_channel_width { 86 HTC_OM_CHANNEL_WIDTH_20 = 0, 87 HTC_OM_CHANNEL_WIDTH_40 = 1, 88 HTC_OM_CHANNEL_WIDTH_80 = 2, 89 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 90 }; 91 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 92 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 93 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 94 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 95 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 96 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 97 98 #define RTW89_TF_PAD GENMASK(11, 0) 99 #define RTW89_TF_BASIC_USER_INFO_SZ 6 100 101 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 102 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 103 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 104 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 105 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 106 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 107 108 enum rtw89_subband { 109 RTW89_CH_2G = 0, 110 RTW89_CH_5G_BAND_1 = 1, 111 /* RTW89_CH_5G_BAND_2 = 2, unused */ 112 RTW89_CH_5G_BAND_3 = 3, 113 RTW89_CH_5G_BAND_4 = 4, 114 115 RTW89_CH_6G_BAND_IDX0, /* Low */ 116 RTW89_CH_6G_BAND_IDX1, /* Low */ 117 RTW89_CH_6G_BAND_IDX2, /* Mid */ 118 RTW89_CH_6G_BAND_IDX3, /* Mid */ 119 RTW89_CH_6G_BAND_IDX4, /* High */ 120 RTW89_CH_6G_BAND_IDX5, /* High */ 121 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 122 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 123 124 RTW89_SUBBAND_NR, 125 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 126 }; 127 128 enum rtw89_tx_comp_band { 129 RTW89_TX_COMP_BAND_2GHZ, 130 RTW89_TX_COMP_BAND_5GHZ_L, 131 RTW89_TX_COMP_BAND_5GHZ_H, 132 RTW89_TX_COMP_BAND_6GHZ_M, 133 RTW89_TX_COMP_BAND_6GHZ_UH, 134 135 RTW89_TX_COMP_BAND_NR, 136 }; 137 138 enum rtw89_gain_offset { 139 RTW89_GAIN_OFFSET_2G_CCK, 140 RTW89_GAIN_OFFSET_2G_OFDM, 141 RTW89_GAIN_OFFSET_5G_LOW, 142 RTW89_GAIN_OFFSET_5G_MID, 143 RTW89_GAIN_OFFSET_5G_HIGH, 144 RTW89_GAIN_OFFSET_6G_L0, 145 RTW89_GAIN_OFFSET_6G_L1, 146 RTW89_GAIN_OFFSET_6G_M0, 147 RTW89_GAIN_OFFSET_6G_M1, 148 RTW89_GAIN_OFFSET_6G_H0, 149 RTW89_GAIN_OFFSET_6G_H1, 150 RTW89_GAIN_OFFSET_6G_UH0, 151 RTW89_GAIN_OFFSET_6G_UH1, 152 153 RTW89_GAIN_OFFSET_NR, 154 }; 155 156 enum rtw89_hci_type { 157 RTW89_HCI_TYPE_PCIE, 158 RTW89_HCI_TYPE_USB, 159 RTW89_HCI_TYPE_SDIO, 160 161 RTW89_HCI_TYPE_NUM, 162 }; 163 164 enum rtw89_hci_dle_type { 165 RTW89_HCI_DLE_TYPE_PCIE, 166 RTW89_HCI_DLE_TYPE_USB2, 167 RTW89_HCI_DLE_TYPE_USB3, 168 RTW89_HCI_DLE_TYPE_SDIO, 169 170 RTW89_HCI_DLE_TYPE_NUM, 171 }; 172 173 enum rtw89_core_chip_id { 174 RTL8852A, 175 RTL8852B, 176 RTL8852BT, 177 RTL8852C, 178 RTL8851B, 179 RTL8922A, 180 RTL8922D, 181 }; 182 183 enum rtw89_core_chip_cid { 184 RTL8922D_CID7025 = 0x74, 185 RTL8922D_CID7090 = 0x79, 186 }; 187 188 enum rtw89_core_chip_aid { 189 RTL8922D_AID1348 = 0x1348, 190 RTL8922D_AID7060 = 0x7060, 191 RTL8922D_AID7102 = 0x7102, 192 }; 193 194 enum rtw89_chip_gen { 195 RTW89_CHIP_AX, 196 RTW89_CHIP_BE, 197 198 RTW89_CHIP_GEN_NUM, 199 }; 200 201 enum rtw89_cv { 202 CHIP_CAV, 203 CHIP_CBV, 204 CHIP_CCV, 205 CHIP_CDV, 206 CHIP_CEV, 207 CHIP_CFV, 208 CHIP_CV_MAX, 209 CHIP_CV_INVALID = CHIP_CV_MAX, 210 }; 211 212 enum rtw89_bacam_ver { 213 RTW89_BACAM_V0, 214 RTW89_BACAM_V1, 215 216 RTW89_BACAM_V0_EXT = 99, 217 }; 218 219 enum rtw89_core_tx_type { 220 RTW89_CORE_TX_TYPE_DATA, 221 RTW89_CORE_TX_TYPE_MGMT, 222 RTW89_CORE_TX_TYPE_FWCMD, 223 }; 224 225 enum rtw89_core_rx_type { 226 RTW89_CORE_RX_TYPE_WIFI = 0, 227 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 228 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 229 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 230 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 231 RTW89_CORE_RX_TYPE_SS2FW = 5, 232 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 233 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 234 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 235 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 236 RTW89_CORE_RX_TYPE_C2H = 10, 237 RTW89_CORE_RX_TYPE_CSI = 11, 238 RTW89_CORE_RX_TYPE_CQI = 12, 239 RTW89_CORE_RX_TYPE_H2C = 13, 240 RTW89_CORE_RX_TYPE_FWDL = 14, 241 }; 242 243 enum rtw89_txq_flags { 244 RTW89_TXQ_F_AMPDU = 0, 245 RTW89_TXQ_F_BLOCK_BA = 1, 246 RTW89_TXQ_F_FORBID_BA = 2, 247 }; 248 249 enum rtw89_net_type { 250 RTW89_NET_TYPE_NO_LINK = 0, 251 RTW89_NET_TYPE_AD_HOC = 1, 252 RTW89_NET_TYPE_INFRA = 2, 253 RTW89_NET_TYPE_AP_MODE = 3, 254 }; 255 256 enum rtw89_wifi_role { 257 RTW89_WIFI_ROLE_NONE, 258 RTW89_WIFI_ROLE_STATION, 259 RTW89_WIFI_ROLE_AP, 260 RTW89_WIFI_ROLE_AP_VLAN, 261 RTW89_WIFI_ROLE_ADHOC, 262 RTW89_WIFI_ROLE_ADHOC_MASTER, 263 RTW89_WIFI_ROLE_MESH_POINT, 264 RTW89_WIFI_ROLE_MONITOR, 265 RTW89_WIFI_ROLE_P2P_DEVICE, 266 RTW89_WIFI_ROLE_P2P_CLIENT, 267 RTW89_WIFI_ROLE_P2P_GO, 268 RTW89_WIFI_ROLE_NAN, 269 RTW89_WIFI_ROLE_MLME_MAX 270 }; 271 272 enum rtw89_upd_mode { 273 RTW89_ROLE_CREATE, 274 RTW89_ROLE_REMOVE, 275 RTW89_ROLE_TYPE_CHANGE, 276 RTW89_ROLE_INFO_CHANGE, 277 RTW89_ROLE_CON_DISCONN, 278 RTW89_ROLE_BAND_SW, 279 RTW89_ROLE_FW_RESTORE, 280 }; 281 282 enum rtw89_self_role { 283 RTW89_SELF_ROLE_CLIENT, 284 RTW89_SELF_ROLE_AP, 285 RTW89_SELF_ROLE_AP_CLIENT 286 }; 287 288 enum rtw89_msk_sO_el { 289 RTW89_NO_MSK, 290 RTW89_SMA, 291 RTW89_TMA, 292 RTW89_BSSID 293 }; 294 295 enum rtw89_sch_tx_sel { 296 RTW89_SCH_TX_SEL_ALL, 297 RTW89_SCH_TX_SEL_HIQ, 298 RTW89_SCH_TX_SEL_MG0, 299 RTW89_SCH_TX_SEL_MACID, 300 }; 301 302 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 303 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 304 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 305 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 306 */ 307 enum rtw89_add_cam_sec_mode { 308 RTW89_ADDR_CAM_SEC_NONE = 0, 309 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 310 RTW89_ADDR_CAM_SEC_NORMAL = 2, 311 RTW89_ADDR_CAM_SEC_4GROUP = 3, 312 }; 313 314 enum rtw89_sec_key_type { 315 RTW89_SEC_KEY_TYPE_NONE = 0, 316 RTW89_SEC_KEY_TYPE_WEP40 = 1, 317 RTW89_SEC_KEY_TYPE_WEP104 = 2, 318 RTW89_SEC_KEY_TYPE_TKIP = 3, 319 RTW89_SEC_KEY_TYPE_WAPI = 4, 320 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 321 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 322 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 323 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 324 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 325 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 326 }; 327 328 enum rtw89_port { 329 RTW89_PORT_0 = 0, 330 RTW89_PORT_1 = 1, 331 RTW89_PORT_2 = 2, 332 RTW89_PORT_3 = 3, 333 RTW89_PORT_4 = 4, 334 RTW89_PORT_NUM 335 }; 336 337 enum rtw89_band { 338 RTW89_BAND_2G = 0, 339 RTW89_BAND_5G = 1, 340 RTW89_BAND_6G = 2, 341 RTW89_BAND_NUM, 342 }; 343 344 enum rtw89_hw_rate { 345 RTW89_HW_RATE_CCK1 = 0x0, 346 RTW89_HW_RATE_CCK2 = 0x1, 347 RTW89_HW_RATE_CCK5_5 = 0x2, 348 RTW89_HW_RATE_CCK11 = 0x3, 349 RTW89_HW_RATE_OFDM6 = 0x4, 350 RTW89_HW_RATE_OFDM9 = 0x5, 351 RTW89_HW_RATE_OFDM12 = 0x6, 352 RTW89_HW_RATE_OFDM18 = 0x7, 353 RTW89_HW_RATE_OFDM24 = 0x8, 354 RTW89_HW_RATE_OFDM36 = 0x9, 355 RTW89_HW_RATE_OFDM48 = 0xA, 356 RTW89_HW_RATE_OFDM54 = 0xB, 357 RTW89_HW_RATE_MCS0 = 0x80, 358 RTW89_HW_RATE_MCS1 = 0x81, 359 RTW89_HW_RATE_MCS2 = 0x82, 360 RTW89_HW_RATE_MCS3 = 0x83, 361 RTW89_HW_RATE_MCS4 = 0x84, 362 RTW89_HW_RATE_MCS5 = 0x85, 363 RTW89_HW_RATE_MCS6 = 0x86, 364 RTW89_HW_RATE_MCS7 = 0x87, 365 RTW89_HW_RATE_MCS8 = 0x88, 366 RTW89_HW_RATE_MCS9 = 0x89, 367 RTW89_HW_RATE_MCS10 = 0x8A, 368 RTW89_HW_RATE_MCS11 = 0x8B, 369 RTW89_HW_RATE_MCS12 = 0x8C, 370 RTW89_HW_RATE_MCS13 = 0x8D, 371 RTW89_HW_RATE_MCS14 = 0x8E, 372 RTW89_HW_RATE_MCS15 = 0x8F, 373 RTW89_HW_RATE_MCS16 = 0x90, 374 RTW89_HW_RATE_MCS17 = 0x91, 375 RTW89_HW_RATE_MCS18 = 0x92, 376 RTW89_HW_RATE_MCS19 = 0x93, 377 RTW89_HW_RATE_MCS20 = 0x94, 378 RTW89_HW_RATE_MCS21 = 0x95, 379 RTW89_HW_RATE_MCS22 = 0x96, 380 RTW89_HW_RATE_MCS23 = 0x97, 381 RTW89_HW_RATE_MCS24 = 0x98, 382 RTW89_HW_RATE_MCS25 = 0x99, 383 RTW89_HW_RATE_MCS26 = 0x9A, 384 RTW89_HW_RATE_MCS27 = 0x9B, 385 RTW89_HW_RATE_MCS28 = 0x9C, 386 RTW89_HW_RATE_MCS29 = 0x9D, 387 RTW89_HW_RATE_MCS30 = 0x9E, 388 RTW89_HW_RATE_MCS31 = 0x9F, 389 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 390 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 391 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 392 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 393 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 394 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 395 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 396 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 397 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 398 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 399 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 400 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 401 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 402 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 403 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 404 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 405 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 406 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 407 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 408 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 409 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 410 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 411 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 412 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 413 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 414 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 415 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 416 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 417 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 418 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 419 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 420 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 421 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 422 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 423 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 424 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 425 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 426 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 427 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 428 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 429 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 430 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 431 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 432 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 433 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 434 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 435 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 436 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 437 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 438 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 439 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 440 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 441 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 442 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 443 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 444 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 445 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 446 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 447 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 448 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 449 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 450 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 451 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 452 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 453 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 454 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 455 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 456 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 457 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 458 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 459 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 460 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 461 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 462 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 463 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 464 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 465 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 466 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 467 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 468 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 469 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 470 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 471 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 472 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 473 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 474 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 475 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 476 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 477 478 RTW89_HW_RATE_V1_MCS0 = 0x100, 479 RTW89_HW_RATE_V1_MCS1 = 0x101, 480 RTW89_HW_RATE_V1_MCS2 = 0x102, 481 RTW89_HW_RATE_V1_MCS3 = 0x103, 482 RTW89_HW_RATE_V1_MCS4 = 0x104, 483 RTW89_HW_RATE_V1_MCS5 = 0x105, 484 RTW89_HW_RATE_V1_MCS6 = 0x106, 485 RTW89_HW_RATE_V1_MCS7 = 0x107, 486 RTW89_HW_RATE_V1_MCS8 = 0x108, 487 RTW89_HW_RATE_V1_MCS9 = 0x109, 488 RTW89_HW_RATE_V1_MCS10 = 0x10A, 489 RTW89_HW_RATE_V1_MCS11 = 0x10B, 490 RTW89_HW_RATE_V1_MCS12 = 0x10C, 491 RTW89_HW_RATE_V1_MCS13 = 0x10D, 492 RTW89_HW_RATE_V1_MCS14 = 0x10E, 493 RTW89_HW_RATE_V1_MCS15 = 0x10F, 494 RTW89_HW_RATE_V1_MCS16 = 0x110, 495 RTW89_HW_RATE_V1_MCS17 = 0x111, 496 RTW89_HW_RATE_V1_MCS18 = 0x112, 497 RTW89_HW_RATE_V1_MCS19 = 0x113, 498 RTW89_HW_RATE_V1_MCS20 = 0x114, 499 RTW89_HW_RATE_V1_MCS21 = 0x115, 500 RTW89_HW_RATE_V1_MCS22 = 0x116, 501 RTW89_HW_RATE_V1_MCS23 = 0x117, 502 RTW89_HW_RATE_V1_MCS24 = 0x118, 503 RTW89_HW_RATE_V1_MCS25 = 0x119, 504 RTW89_HW_RATE_V1_MCS26 = 0x11A, 505 RTW89_HW_RATE_V1_MCS27 = 0x11B, 506 RTW89_HW_RATE_V1_MCS28 = 0x11C, 507 RTW89_HW_RATE_V1_MCS29 = 0x11D, 508 RTW89_HW_RATE_V1_MCS30 = 0x11E, 509 RTW89_HW_RATE_V1_MCS31 = 0x11F, 510 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 511 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 512 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 513 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 514 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 515 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 516 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 517 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 518 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 519 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 520 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 521 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 522 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 523 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 524 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 525 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 526 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 527 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 528 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 529 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 530 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 531 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 532 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 533 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 534 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 535 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 536 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 537 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 538 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 539 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 540 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 541 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 542 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 543 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 544 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 545 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 546 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 547 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 548 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 549 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 550 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 551 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 552 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 553 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 554 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 555 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 556 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 557 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 558 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 559 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 560 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 561 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 562 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 563 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 564 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 565 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 566 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 567 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 568 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 569 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 570 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 571 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 572 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 573 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 574 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 575 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 576 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 577 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 578 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 579 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 580 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 581 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 582 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 583 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 584 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 585 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 586 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 587 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 588 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 589 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 590 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 591 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 592 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 593 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 594 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 595 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 596 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 597 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 598 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 599 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 600 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 601 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 602 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 603 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 604 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 605 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 606 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 607 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 608 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 609 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 610 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 611 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 612 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 613 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 614 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 615 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 616 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 617 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 618 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 619 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 620 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 621 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 622 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 623 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 624 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 625 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 626 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 627 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 628 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 629 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 630 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 631 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 632 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 633 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 634 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 635 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 636 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 637 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 638 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 639 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 640 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 641 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 642 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 643 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 644 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 645 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 646 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 647 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 648 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 649 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 650 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 651 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 652 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 653 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 654 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 655 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 656 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 657 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 658 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 659 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 660 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 661 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 662 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 663 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 664 665 RTW89_HW_RATE_NR, 666 RTW89_HW_RATE_INVAL, 667 668 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 669 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 670 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 671 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 672 }; 673 674 /* 2G channels, 675 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 676 */ 677 #define RTW89_2G_CH_NUM 14 678 679 /* 5G channels, 680 * 36, 38, 40, 42, 44, 46, 48, 50, 681 * 52, 54, 56, 58, 60, 62, 64, 682 * 100, 102, 104, 106, 108, 110, 112, 114, 683 * 116, 118, 120, 122, 124, 126, 128, 130, 684 * 132, 134, 136, 138, 140, 142, 144, 685 * 149, 151, 153, 155, 157, 159, 161, 163, 686 * 165, 167, 169, 171, 173, 175, 177 687 */ 688 #define RTW89_5G_CH_NUM 53 689 690 /* 6G channels, 691 * 1, 3, 5, 7, 9, 11, 13, 15, 692 * 17, 19, 21, 23, 25, 27, 29, 33, 693 * 35, 37, 39, 41, 43, 45, 47, 49, 694 * 51, 53, 55, 57, 59, 61, 65, 67, 695 * 69, 71, 73, 75, 77, 79, 81, 83, 696 * 85, 87, 89, 91, 93, 97, 99, 101, 697 * 103, 105, 107, 109, 111, 113, 115, 117, 698 * 119, 121, 123, 125, 129, 131, 133, 135, 699 * 137, 139, 141, 143, 145, 147, 149, 151, 700 * 153, 155, 157, 161, 163, 165, 167, 169, 701 * 171, 173, 175, 177, 179, 181, 183, 185, 702 * 187, 189, 193, 195, 197, 199, 201, 203, 703 * 205, 207, 209, 211, 213, 215, 217, 219, 704 * 221, 225, 227, 229, 231, 233, 235, 237, 705 * 239, 241, 243, 245, 247, 249, 251, 253, 706 */ 707 #define RTW89_6G_CH_NUM 120 708 709 enum rtw89_rate_section { 710 RTW89_RS_CCK, 711 RTW89_RS_OFDM, 712 RTW89_RS_MCS, /* for HT/VHT/HE */ 713 RTW89_RS_HEDCM, 714 RTW89_RS_OFFSET, 715 RTW89_RS_NUM, 716 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 717 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 718 }; 719 720 enum rtw89_rate_offset_indexes { 721 RTW89_RATE_OFFSET_HE, 722 RTW89_RATE_OFFSET_VHT, 723 RTW89_RATE_OFFSET_HT, 724 RTW89_RATE_OFFSET_OFDM, 725 RTW89_RATE_OFFSET_CCK, 726 RTW89_RATE_OFFSET_DLRU_EHT, 727 RTW89_RATE_OFFSET_DLRU_HE, 728 RTW89_RATE_OFFSET_EHT, 729 __RTW89_RATE_OFFSET_NUM, 730 731 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 732 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 733 }; 734 735 enum rtw89_rate_num { 736 RTW89_RATE_CCK_NUM = 4, 737 RTW89_RATE_OFDM_NUM = 8, 738 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 739 740 RTW89_RATE_MCS_NUM_AX = 12, 741 RTW89_RATE_MCS_NUM_BE = 16, 742 __RTW89_RATE_MCS_NUM = 16, 743 }; 744 745 enum rtw89_nss { 746 RTW89_NSS_1 = 0, 747 RTW89_NSS_2 = 1, 748 /* HE DCM only support 1ss and 2ss */ 749 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 750 RTW89_NSS_3 = 2, 751 RTW89_NSS_4 = 3, 752 RTW89_NSS_NUM, 753 }; 754 755 enum rtw89_ntx { 756 RTW89_1TX = 0, 757 RTW89_2TX = 1, 758 RTW89_NTX_NUM, 759 }; 760 761 enum rtw89_beamforming_type { 762 RTW89_NONBF = 0, 763 RTW89_BF = 1, 764 RTW89_BF_NUM, 765 }; 766 767 enum rtw89_ofdma_type { 768 RTW89_NON_OFDMA = 0, 769 RTW89_OFDMA = 1, 770 RTW89_OFDMA_NUM, 771 }; 772 773 /* neither insert new in the middle, nor change any given definition */ 774 enum rtw89_regulation_type { 775 RTW89_WW = 0, 776 RTW89_ETSI = 1, 777 RTW89_FCC = 2, 778 RTW89_MKK = 3, 779 RTW89_NA = 4, 780 RTW89_IC = 5, 781 RTW89_KCC = 6, 782 RTW89_ACMA = 7, 783 RTW89_NCC = 8, 784 RTW89_MEXICO = 9, 785 RTW89_CHILE = 10, 786 RTW89_UKRAINE = 11, 787 RTW89_CN = 12, 788 RTW89_QATAR = 13, 789 RTW89_UK = 14, 790 RTW89_THAILAND = 15, 791 RTW89_REGD_NUM, 792 }; 793 794 enum rtw89_reg_6ghz_power { 795 RTW89_REG_6GHZ_POWER_VLP = 0, 796 RTW89_REG_6GHZ_POWER_LPI = 1, 797 RTW89_REG_6GHZ_POWER_STD = 2, 798 799 NUM_OF_RTW89_REG_6GHZ_POWER, 800 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 801 }; 802 803 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 804 805 /* calculate based on ieee80211 Transmit Power Envelope */ 806 struct rtw89_reg_6ghz_tpe { 807 bool valid; 808 s8 constraint; /* unit: dBm */ 809 }; 810 811 enum rtw89_fw_pkt_ofld_type { 812 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 813 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 814 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 815 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 816 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 817 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 818 RTW89_PKT_OFLD_TYPE_NDP = 6, 819 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 820 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 821 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 822 RTW89_PKT_OFLD_TYPE_NUM, 823 }; 824 825 struct rtw89_txpwr_byrate { 826 s8 cck[RTW89_RATE_CCK_NUM]; 827 s8 ofdm[RTW89_RATE_OFDM_NUM]; 828 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 829 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 830 s8 offset[__RTW89_RATE_OFFSET_NUM]; 831 s8 trap; 832 }; 833 834 struct rtw89_rate_desc { 835 enum rtw89_nss nss; 836 enum rtw89_rate_section rs; 837 enum rtw89_ofdma_type ofdma; 838 u8 idx; 839 }; 840 841 #define PHY_STS_HDR_LEN 8 842 #define RF_PATH_MAX 4 843 #define RTW89_MAX_PPDU_CNT 8 844 struct rtw89_rx_phy_ppdu { 845 void *buf; 846 u32 len; 847 u8 rssi_avg; 848 u8 rssi[RF_PATH_MAX]; 849 u8 mac_id; 850 u8 chan_idx; 851 u8 phy_idx; 852 u8 ie; /* enum rtw89_phy_status_bitmap */ 853 u16 rate; 854 u8 rpl_avg; 855 u8 rpl_path[RF_PATH_MAX]; 856 u8 rpl_fd[RF_PATH_MAX]; 857 u8 bw_idx; 858 u8 rx_path_en; 859 struct { 860 bool has; 861 u8 avg_snr; 862 u8 evm_max; 863 u8 evm_min; 864 } ofdm; 865 bool has_data; 866 bool has_bcn; 867 bool su; 868 bool ldpc; 869 bool stbc; 870 bool bf; 871 bool to_self; 872 bool valid; 873 bool hdr_2_en; 874 const union rtw89_phy_sts_ie09 *ie09; /* SIG-A */ 875 const struct rtw89_phy_sts_ie10 *ie10; /* SIG-B */ 876 }; 877 878 enum rtw89_mac_idx { 879 RTW89_MAC_0 = 0, 880 RTW89_MAC_1 = 1, 881 RTW89_MAC_NUM, 882 }; 883 884 enum rtw89_phy_idx { 885 RTW89_PHY_0 = 0, 886 RTW89_PHY_1 = 1, 887 RTW89_PHY_NUM, 888 }; 889 890 enum rtw89_fbtc_bt_index { 891 BTC_BT_1ST = 0x0, 892 BTC_BT_2ND = 0x1, 893 BTC_BT_EXT = 0x2, 894 BTC_ALL_BT = 0x2, 895 BTC_ALL_BT_EZL = 0x3 /* BT0+BT1+Ext-ZB(or Thread, or LTE) */ 896 }; 897 898 #define __RTW89_MLD_MAX_LINK_NUM 2 899 #define RTW89_MLD_NON_STA_LINK_NUM 1 900 901 enum rtw89_chanctx_idx { 902 RTW89_CHANCTX_0 = 0, 903 RTW89_CHANCTX_1 = 1, 904 905 NUM_OF_RTW89_CHANCTX, 906 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 907 }; 908 909 enum rtw89_rf_path { 910 RF_PATH_A = 0, 911 RF_PATH_B = 1, 912 RF_PATH_C = 2, 913 RF_PATH_D = 3, 914 RF_PATH_AB, 915 RF_PATH_AC, 916 RF_PATH_AD, 917 RF_PATH_BC, 918 RF_PATH_BD, 919 RF_PATH_CD, 920 RF_PATH_ABC, 921 RF_PATH_ABD, 922 RF_PATH_ACD, 923 RF_PATH_BCD, 924 RF_PATH_ABCD, 925 }; 926 927 enum rtw89_rf_path_bit { 928 RF_A = BIT(0), 929 RF_B = BIT(1), 930 RF_C = BIT(2), 931 RF_D = BIT(3), 932 933 RF_AB = (RF_A | RF_B), 934 RF_AC = (RF_A | RF_C), 935 RF_AD = (RF_A | RF_D), 936 RF_BC = (RF_B | RF_C), 937 RF_BD = (RF_B | RF_D), 938 RF_CD = (RF_C | RF_D), 939 940 RF_ABC = (RF_A | RF_B | RF_C), 941 RF_ABD = (RF_A | RF_B | RF_D), 942 RF_ACD = (RF_A | RF_C | RF_D), 943 RF_BCD = (RF_B | RF_C | RF_D), 944 945 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 946 }; 947 948 enum rtw89_bandwidth { 949 RTW89_CHANNEL_WIDTH_20 = 0, 950 RTW89_CHANNEL_WIDTH_40 = 1, 951 RTW89_CHANNEL_WIDTH_80 = 2, 952 RTW89_CHANNEL_WIDTH_160 = 3, 953 RTW89_CHANNEL_WIDTH_320 = 4, 954 955 /* keep index order above */ 956 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 957 958 RTW89_CHANNEL_WIDTH_80_80 = 5, 959 RTW89_CHANNEL_WIDTH_5 = 6, 960 RTW89_CHANNEL_WIDTH_10 = 7, 961 }; 962 963 enum rtw89_rx_ppdu_type { 964 RTW89_RX_PPDU_T_LCCK = 0, 965 RTW89_RX_PPDU_T_SCCK = 1, 966 RTW89_RX_PPDU_T_OFDM = 2, 967 RTW89_RX_PPDU_T_HT = 3, 968 RTW89_RX_PPDU_T_HTGF = 4, 969 RTW89_RX_PPDU_T_VHT_SU = 5, 970 RTW89_RX_PPDU_T_VHT_MU = 6, 971 RTW89_RX_PPDU_T_HE_SU = 7, 972 RTW89_RX_PPDU_T_HE_ERSU = 8, 973 RTW89_RX_PPDU_T_HE_MU = 9, 974 RTW89_RX_PPDU_T_HE_TB = 10, 975 RTW89_RX_PPDU_T_UNKNOWN = 15, 976 }; 977 978 enum rtw89_ps_mode { 979 RTW89_PS_MODE_NONE = 0, 980 RTW89_PS_MODE_RFOFF = 1, 981 RTW89_PS_MODE_CLK_GATED = 2, 982 RTW89_PS_MODE_PWR_GATED = 3, 983 }; 984 985 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 986 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 987 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 988 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 989 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 990 991 enum rtw89_pe_duration { 992 RTW89_PE_DURATION_0 = 0, 993 RTW89_PE_DURATION_8 = 1, 994 RTW89_PE_DURATION_16 = 2, 995 RTW89_PE_DURATION_16_20 = 3, 996 }; 997 998 enum rtw89_ru_bandwidth { 999 RTW89_RU26 = 0, 1000 RTW89_RU52 = 1, 1001 RTW89_RU106 = 2, 1002 RTW89_RU52_26 = 3, 1003 RTW89_RU106_26 = 4, 1004 RTW89_RU484_242 = 5, 1005 RTW89_RU996_484 = 6, 1006 RTW89_RU996_484_242 = 7, 1007 RTW89_RU_NUM, 1008 }; 1009 1010 enum rtw89_sc_offset { 1011 RTW89_SC_DONT_CARE = 0, 1012 RTW89_SC_20_UPPER = 1, 1013 RTW89_SC_20_LOWER = 2, 1014 RTW89_SC_20_UPMOST = 3, 1015 RTW89_SC_20_LOWEST = 4, 1016 RTW89_SC_20_UP2X = 5, 1017 RTW89_SC_20_LOW2X = 6, 1018 RTW89_SC_20_UP3X = 7, 1019 RTW89_SC_20_LOW3X = 8, 1020 RTW89_SC_40_UPPER = 9, 1021 RTW89_SC_40_LOWER = 10, 1022 }; 1023 1024 enum rtw89_rfsi_ctrl_band { 1025 RFSI_CTRL_BAND_5_6GHZ, 1026 RFSI_CTRL_BAND_2GHZ, 1027 1028 RFSI_CTRL_BAND_NUM, 1029 }; 1030 1031 /* only mgd features can be added to the enum */ 1032 enum rtw89_wow_flags { 1033 RTW89_WOW_FLAG_EN_MAGIC_PKT, 1034 RTW89_WOW_FLAG_EN_REKEY_PKT, 1035 RTW89_WOW_FLAG_EN_DISCONNECT, 1036 RTW89_WOW_FLAG_EN_PATTERN, 1037 RTW89_WOW_FLAG_NUM, 1038 }; 1039 1040 struct rtw89_chan { 1041 u8 channel; 1042 u8 primary_channel; 1043 enum rtw89_band band_type; 1044 enum rtw89_bandwidth band_width; 1045 1046 /* The follow-up are derived from the above. We must ensure that it 1047 * is assigned correctly in rtw89_chan_create() if new one is added. 1048 */ 1049 u32 freq; 1050 enum rtw89_subband subband_type; 1051 enum rtw89_tx_comp_band tx_comp_band; 1052 enum rtw89_sc_offset pri_ch_idx; 1053 u8 pri_sb_idx; 1054 enum rtw89_rfsi_ctrl_band rfsi_band; 1055 }; 1056 1057 struct rtw89_chan_rcd { 1058 u8 prev_primary_channel; 1059 enum rtw89_band prev_band_type; 1060 bool band_changed; 1061 }; 1062 1063 struct rtw89_channel_help_params { 1064 u32 tx_en; 1065 }; 1066 1067 struct rtw89_port_reg { 1068 u32 port_cfg; 1069 u32 tbtt_prohib; 1070 u32 bcn_area; 1071 u32 bcn_early; 1072 u32 tbtt_early; 1073 u32 tbtt_agg; 1074 u32 bcn_space; 1075 u32 bcn_forcetx; 1076 u32 bcn_err_cnt; 1077 u32 bcn_err_flag; 1078 u32 dtim_ctrl; 1079 u32 tbtt_shift; 1080 u32 bcn_cnt_tmr; 1081 u32 tsftr_l; 1082 u32 tsftr_h; 1083 u32 md_tsft; 1084 u32 bss_color; 1085 u32 mbssid; 1086 u32 mbssid_drop; 1087 u32 tsf_sync; 1088 u32 ptcl_dbg; 1089 u32 ptcl_dbg_info; 1090 u32 bcn_drop_all; 1091 u32 bcn_psr_rpt; 1092 u32 hiq_win[RTW89_PORT_NUM]; 1093 }; 1094 1095 struct rtw89_txwd_body { 1096 __le32 dword0; 1097 __le32 dword1; 1098 __le32 dword2; 1099 __le32 dword3; 1100 __le32 dword4; 1101 __le32 dword5; 1102 } __packed; 1103 1104 struct rtw89_txwd_body_v1 { 1105 __le32 dword0; 1106 __le32 dword1; 1107 __le32 dword2; 1108 __le32 dword3; 1109 __le32 dword4; 1110 __le32 dword5; 1111 __le32 dword6; 1112 __le32 dword7; 1113 } __packed; 1114 1115 struct rtw89_txwd_body_v2 { 1116 __le32 dword0; 1117 __le32 dword1; 1118 __le32 dword2; 1119 __le32 dword3; 1120 __le32 dword4; 1121 __le32 dword5; 1122 __le32 dword6; 1123 __le32 dword7; 1124 } __packed; 1125 1126 struct rtw89_txwd_info { 1127 __le32 dword0; 1128 __le32 dword1; 1129 __le32 dword2; 1130 __le32 dword3; 1131 __le32 dword4; 1132 __le32 dword5; 1133 } __packed; 1134 1135 struct rtw89_txwd_info_v2 { 1136 __le32 dword0; 1137 __le32 dword1; 1138 __le32 dword2; 1139 __le32 dword3; 1140 __le32 dword4; 1141 __le32 dword5; 1142 __le32 dword6; 1143 __le32 dword7; 1144 } __packed; 1145 1146 struct rtw89_rx_desc_info { 1147 u16 pkt_size; 1148 u8 pkt_type; 1149 u8 drv_info_size; 1150 u8 phy_rpt_size; 1151 u8 hdr_cnv_size; 1152 u8 shift; 1153 u8 wl_hd_iv_len; 1154 bool long_rxdesc; 1155 bool bb_sel; 1156 bool mac_info_valid; 1157 u16 data_rate; 1158 u8 gi_ltf; 1159 u8 bw; 1160 u32 free_run_cnt; 1161 u8 user_id; 1162 bool sr_en; 1163 u8 ppdu_cnt; 1164 u8 ppdu_type; 1165 bool icv_err; 1166 bool crc32_err; 1167 bool hw_dec; 1168 bool sw_dec; 1169 bool addr1_match; 1170 bool ampdu; 1171 u8 frag; 1172 u16 seq; 1173 u8 frame_type; 1174 u8 rx_pl_id; 1175 bool addr_cam_valid; 1176 u8 addr_cam_id; 1177 u8 sec_cam_id; 1178 u8 sec_type; 1179 u8 mac_id; 1180 u16 offset; 1181 u16 rxd_len; 1182 bool ready; 1183 u16 rssi; 1184 }; 1185 1186 struct rtw89_rxdesc_short { 1187 __le32 dword0; 1188 __le32 dword1; 1189 __le32 dword2; 1190 __le32 dword3; 1191 } __packed; 1192 1193 struct rtw89_rxdesc_short_v2 { 1194 __le32 dword0; 1195 __le32 dword1; 1196 __le32 dword2; 1197 __le32 dword3; 1198 __le32 dword4; 1199 __le32 dword5; 1200 } __packed; 1201 1202 struct rtw89_rxdesc_short_v3 { 1203 __le32 dword0; 1204 __le32 dword1; 1205 __le32 dword2; 1206 __le32 dword3; 1207 __le32 dword4; 1208 __le32 dword5; 1209 } __packed; 1210 1211 struct rtw89_rxdesc_long { 1212 __le32 dword0; 1213 __le32 dword1; 1214 __le32 dword2; 1215 __le32 dword3; 1216 __le32 dword4; 1217 __le32 dword5; 1218 __le32 dword6; 1219 __le32 dword7; 1220 } __packed; 1221 1222 struct rtw89_rxdesc_long_v2 { 1223 __le32 dword0; 1224 __le32 dword1; 1225 __le32 dword2; 1226 __le32 dword3; 1227 __le32 dword4; 1228 __le32 dword5; 1229 __le32 dword6; 1230 __le32 dword7; 1231 __le32 dword8; 1232 __le32 dword9; 1233 } __packed; 1234 1235 struct rtw89_rxdesc_long_v3 { 1236 __le32 dword0; 1237 __le32 dword1; 1238 __le32 dword2; 1239 __le32 dword3; 1240 __le32 dword4; 1241 __le32 dword5; 1242 __le32 dword6; 1243 __le32 dword7; 1244 __le32 dword8; 1245 __le32 dword9; 1246 } __packed; 1247 1248 struct rtw89_rxdesc_phy_rpt_v2 { 1249 __le32 dword0; 1250 __le32 dword1; 1251 } __packed; 1252 1253 struct rtw89_tx_desc_info { 1254 u16 pkt_size; 1255 u8 wp_offset; 1256 u8 mac_id; 1257 u8 qsel; 1258 u8 ch_dma; 1259 u8 hdr_llc_len; 1260 bool is_bmc; 1261 bool en_wd_info; 1262 bool wd_page; 1263 bool use_rate; 1264 bool dis_data_fb; 1265 bool tid_indicate; 1266 bool agg_en; 1267 bool bk; 1268 u8 ampdu_density; 1269 u8 ampdu_num; 1270 bool sec_en; 1271 bool report; 1272 bool tx_cnt_lmt_en; 1273 u8 sn: 4; 1274 u8 tx_cnt_lmt: 6; 1275 u8 addr_info_nr; 1276 u8 sec_keyid; 1277 u8 sec_type; 1278 u8 sec_cam_idx; 1279 u8 sec_seq[6]; 1280 u16 data_rate; 1281 u16 data_retry_lowest_rate; 1282 u8 data_bw; 1283 u8 gi_ltf; 1284 bool fw_dl; 1285 u16 seq; 1286 bool a_ctrl_bsr; 1287 u8 hw_ssn_sel; 1288 #define RTW89_MGMT_HW_SSN_SEL 1 1289 u8 hw_seq_mode; 1290 #define RTW89_MGMT_HW_SEQ_MODE 1 1291 bool hiq; 1292 u8 port; 1293 bool er_cap; 1294 bool stbc; 1295 bool ldpc; 1296 bool upd_wlan_hdr; 1297 bool mlo; 1298 bool sw_mld; 1299 }; 1300 1301 struct rtw89_core_tx_request { 1302 enum rtw89_core_tx_type tx_type; 1303 1304 struct sk_buff *skb; 1305 struct ieee80211_vif *vif; 1306 struct ieee80211_sta *sta; 1307 struct rtw89_vif_link *rtwvif_link; 1308 struct rtw89_sta_link *rtwsta_link; 1309 struct rtw89_tx_desc_info desc_info; 1310 1311 bool with_wait; 1312 }; 1313 1314 struct rtw89_txq { 1315 struct list_head list; 1316 unsigned long flags; 1317 int wait_cnt; 1318 }; 1319 1320 struct rtw89_mac_ax_gnt { 1321 u8 gnt_bt_sw_en; 1322 u8 gnt_bt; 1323 u8 gnt_wl_sw_en; 1324 u8 gnt_wl; 1325 } __packed; 1326 1327 struct rtw89_btc_gnt_ctrl { 1328 u8 gnt_zb_sw_en; 1329 u8 gnt_zb; 1330 u8 gnt_bt1_sw_en; 1331 u8 gnt_bt1; 1332 u8 gnt_bt0_sw_en; 1333 u8 gnt_bt0; 1334 u8 gnt_wl_sw_en; 1335 u8 gnt_wl; 1336 } __packed; 1337 1338 struct rtw89_mac_ax_wl_act { 1339 u8 wlan_act_en; 1340 u8 wlan_act; 1341 } __packed; 1342 1343 #define RTW89_MAC_AX_COEX_GNT_NR 2 1344 struct rtw89_mac_ax_coex_gnt { 1345 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1346 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1347 }; 1348 1349 enum rtw89_btc_ncnt { 1350 BTC_NCNT_POWER_ON = 0x0, 1351 BTC_NCNT_POWER_OFF, 1352 BTC_NCNT_INIT_COEX, 1353 BTC_NCNT_SCAN_START, 1354 BTC_NCNT_SCAN_FINISH, 1355 BTC_NCNT_SPECIAL_PACKET, 1356 BTC_NCNT_SWITCH_BAND, 1357 BTC_NCNT_RFK_TIMEOUT, 1358 BTC_NCNT_SHOW_COEX_INFO, 1359 BTC_NCNT_ROLE_INFO, 1360 BTC_NCNT_CONTROL, 1361 BTC_NCNT_RADIO_STATE, 1362 BTC_NCNT_CUSTOMERIZE, 1363 BTC_NCNT_WL_RFK, 1364 BTC_NCNT_WL_STA, 1365 BTC_NCNT_WL_STA_LAST, 1366 BTC_NCNT_FWINFO, 1367 BTC_NCNT_TIMER, 1368 BTC_NCNT_SWITCH_CHBW, 1369 BTC_NCNT_RESUME_DL_FW, 1370 BTC_NCNT_COUNTRYCODE, 1371 BTC_NCNT_NUM, 1372 }; 1373 1374 enum rtw89_btc_btinfo { 1375 BTC_BTINFO_L0 = 0, 1376 BTC_BTINFO_L1, 1377 BTC_BTINFO_L2, 1378 BTC_BTINFO_L3, 1379 BTC_BTINFO_H0, 1380 BTC_BTINFO_H1, 1381 BTC_BTINFO_H2, 1382 BTC_BTINFO_H3, 1383 BTC_BTINFO_MAX 1384 }; 1385 1386 #define BTC_BTINFO_BISTDMA 0x48 /* cmd value that identifies BISTDMA data */ 1387 1388 enum rtw89_btc_dcnt { 1389 BTC_DCNT_RUN = 0x0, 1390 BTC_DCNT_CX_RUNINFO, 1391 BTC_DCNT_RPT, 1392 BTC_DCNT_RPT_HANG, 1393 BTC_DCNT_CYCLE, 1394 BTC_DCNT_CYCLE_HANG, 1395 BTC_DCNT_W1, 1396 BTC_DCNT_W1_HANG, 1397 BTC_DCNT_B1, 1398 BTC_DCNT_B1_HANG, 1399 BTC_DCNT_TDMA_NONSYNC, 1400 BTC_DCNT_SLOT_NONSYNC, 1401 BTC_DCNT_BTCNT_HANG, 1402 BTC_DCNT_BTTX_HANG, 1403 BTC_DCNT_WL_SLOT_DRIFT, 1404 BTC_DCNT_WL_STA_LAST, 1405 BTC_DCNT_BT_SLOT_DRIFT, 1406 BTC_DCNT_BT_SLOT_FLOOD, 1407 BTC_DCNT_FDDT_TRIG, 1408 BTC_DCNT_E2G, 1409 BTC_DCNT_E2G_HANG, 1410 BTC_DCNT_WL_FW_VER_MATCH, 1411 BTC_DCNT_NULL_TX_FAIL, 1412 BTC_DCNT_WL_STA_NTFY, 1413 BTC_DCNT_W2B_SCBD_NOSYNC, 1414 BTC_DCNT_NUM, 1415 }; 1416 1417 enum rtw89_btc_wl_state_cnt { 1418 BTC_WCNT_SCANAP = 0x0, 1419 BTC_WCNT_DHCP, 1420 BTC_WCNT_EAPOL, 1421 BTC_WCNT_ARP, 1422 BTC_WCNT_SCBDUPDATE, 1423 BTC_WCNT_RFK_REQ, 1424 BTC_WCNT_RFK_GO, 1425 BTC_WCNT_RFK_REJECT, 1426 BTC_WCNT_RFK_TIMEOUT, 1427 BTC_WCNT_CH_UPDATE, 1428 BTC_WCNT_DBCC_ALL_2G, 1429 BTC_WCNT_DBCC_CHG, 1430 BTC_WCNT_RX_OK_LAST, 1431 BTC_WCNT_RX_OK_LAST2S, 1432 BTC_WCNT_RX_ERR_LAST, 1433 BTC_WCNT_RX_ERR_LAST2S, 1434 BTC_WCNT_RX_LAST, 1435 BTC_WCNT_SCBDUPDATE2, 1436 BTC_WCNT_NUM 1437 }; 1438 1439 enum rtw89_btc_bt_state_cnt { 1440 BTC_BCNT_RETRY = 0x0, 1441 BTC_BCNT_REINIT, 1442 BTC_BCNT_REENABLE, 1443 BTC_BCNT_SCBDREAD, 1444 BTC_BCNT_RELINK, 1445 BTC_BCNT_IGNOWL, 1446 BTC_BCNT_INQPAG, 1447 BTC_BCNT_INQ, 1448 BTC_BCNT_PAGE, 1449 BTC_BCNT_ROLESW, 1450 BTC_BCNT_AFH, 1451 BTC_BCNT_INFOUPDATE, 1452 BTC_BCNT_LEAUDIO_INFOUPDATE, 1453 BTC_BCNT_INFOSAME, 1454 BTC_BCNT_LEAUDIO_INFOSAME, 1455 BTC_BCNT_SCBDUPDATE, 1456 BTC_BCNT_HIPRI_TX, 1457 BTC_BCNT_HIPRI_RX, 1458 BTC_BCNT_LOPRI_TX, 1459 BTC_BCNT_LOPRI_RX, 1460 BTC_BCNT_POLUT_NOW, 1461 BTC_BCNT_POLUT_DIFF, 1462 BTC_BCNT_RATECHG, 1463 BTC_BCNT_AFH_CONFLICT, 1464 BTC_BCNT_AFH_LE_CONFLICT, 1465 BTC_BCNT_AFH_UPDATE, 1466 BTC_BCNT_AFH_LE_UPDATE, 1467 BTC_BCNT_AFH_CHN, 1468 BTC_BCNT_AFH_LE_CHN, 1469 BTC_BCNT_TXPWR_UPDATE, 1470 BTC_BCNT_PROTECT, 1471 BTC_BCNT_NUM, 1472 }; 1473 1474 enum rtw89_btc_bt_mech_type { 1475 BTC_MECH_TDD = 0, 1476 BTC_MECH_FDD = 1, 1477 }; 1478 1479 enum rtw89_btc_bt_rf_band { 1480 BTC_BT_B2G = 0x0, /* 2.4GHz */ 1481 BTC_BT_B5G = 0x1, /* 5GHz or 6GHz */ 1482 BTC_BT_BMAX = 0x2 1483 }; 1484 1485 enum rtw89_btc_io_offload_type { 1486 BTC_IO_OFLD_NO_SUPPORT = 0, 1487 BTC_IO_OFLD_MAC_API = 1, 1488 BTC_IO_OFLD_BTC_H2C = 2 1489 }; 1490 1491 enum rtw89_btc_bt_profile { 1492 BTC_BT_NOPROFILE = 0, 1493 BTC_BT_HFP = BIT(0), 1494 BTC_BT_HID = BIT(1), 1495 BTC_BT_A2DP = BIT(2), 1496 BTC_BT_PAN = BIT(3), 1497 BTC_BT_BIS = BIT(4), 1498 BTC_BT_CIS = BIT(5), 1499 BTC_BT_THREAD = BIT(6), 1500 BTC_BT_ULL = BIT(7), 1501 BTC_BT_LEGACY = 0xf, 1502 BTC_BT_FULL = 0x3f, 1503 BTC_PROFILE_MAX = 4, 1504 }; 1505 1506 struct rtw89_btc_ant_info_v0 { 1507 u8 type; /* shared, dedicated */ 1508 u8 num; 1509 u8 isolation; 1510 1511 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1512 u8 diversity: 1; 1513 u8 btg_pos: 2; 1514 u8 stream_cnt: 4; 1515 }; 1516 1517 struct rtw89_btc_ant_info_v7 { 1518 u8 type; /* shared, dedicated(non-shared) */ 1519 u8 num; /* antenna count */ 1520 u8 isolation; 1521 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1522 1523 u8 diversity; /* only for wifi use 1-antenna */ 1524 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1525 u8 stream_cnt; /* spatial_stream count */ 1526 u8 rsvd; 1527 } __packed; 1528 1529 struct rtw89_btc_ant_info_v10 { 1530 u8 type; /* shared, dedicated(non-shared) */ 1531 u8 num; /* antenna count */ 1532 u8 isolation; /* Ant-Iso between WL/BT */ 1533 u8 single_pos; /* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1534 1535 u8 stream_cnt; /* spatial_stream count: Tx[7:4], Rx[3:0] */ 1536 u8 btg_pos; /* BT0 btg-circuit at 0:WL-S0/1:WL-S1 */ 1537 u8 btg1_pos; /* BT1 btg-circuit at 0:WL-S0/1:WL-S1 */ 1538 u8 func[5]; /* function at 1~5 Ant refer to enum btc_bt_func_type */ 1539 u8 ant_xmap[2][4]; 1540 } __packed; 1541 1542 struct rtw89_btc_ant_info_v11 { 1543 u8 type; 1544 u8 num; 1545 u8 isolation; 1546 u8 single_pos; 1547 1548 u8 stream_cnt; 1549 u8 path_pos; /* WL path position: Tx[7:4], Rx[3:0] */ 1550 u8 btg_pos; 1551 u8 btg1_pos; 1552 u8 func[5]; 1553 u8 ant_xmap[2][4]; 1554 u8 rsvd0[3]; 1555 } __packed; 1556 1557 struct rtw89_btc_ant_info { 1558 u8 type; /* shared, dedicated(non-shared) */ 1559 u8 num; /* antenna count */ 1560 u8 isolation; /* Ant-Iso between WL/BT */ 1561 u8 single_pos; /* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1562 1563 u8 stream_cnt; /* spatial_stream count: Tx[7:4], Rx[3:0] */ 1564 u8 btg_pos; /* BT0 btg-circuit at 0:WL-S0/1:WL-S1 */ 1565 u8 btg1_pos; /* BT1 btg-circuit at 0:WL-S0/1:WL-S1 */ 1566 u8 path_pos; /* WL path position: Tx[7:4], Rx[3:0] */ 1567 u8 func[5]; /* function at 1~5 Ant refer to enum btc_bt_func_type */ 1568 u8 ant_xmap[2][4]; 1569 1570 u8 diversity; /* only for wifi use 1-antenna */ 1571 }; 1572 1573 enum rtw89_tfc_dir { 1574 RTW89_TFC_UL, 1575 RTW89_TFC_DL, 1576 }; 1577 1578 struct rtw89_btc_wl_smap { 1579 u32 busy: 1; 1580 u32 scan: 1; 1581 u32 dhcp: 1; 1582 u32 roaming: 1; 1583 u32 transacting: 1; 1584 u32 _4way: 1; 1585 u32 handshake: 1; 1586 u32 rf_off: 1; 1587 u32 rf_off_pre: 1; 1588 u32 ips: 1; 1589 u32 lps: 2; 1590 u32 lps_pre: 2; 1591 u32 lps_exiting: 1; 1592 u32 emlsr: 1; 1593 u32 init_ok: 1; 1594 u32 traffic_dir : 2; 1595 }; 1596 1597 enum rtw89_tfc_interval { 1598 RTW89_TFC_INTERVAL_100MS, 1599 RTW89_TFC_INTERVAL_2SEC, 1600 }; 1601 1602 enum rtw89_tfc_lv { 1603 RTW89_TFC_IDLE, 1604 RTW89_TFC_ULTRA_LOW, 1605 RTW89_TFC_LOW, 1606 RTW89_TFC_MID, 1607 RTW89_TFC_HIGH, 1608 }; 1609 1610 DECLARE_EWMA(tp, 10, 2); 1611 1612 #define RTW89_TCP_TH 40 1613 #define RTW89_UDP_RATIO_TH 70 1614 #define RTW89_RECENT_ACTIVE_HIST GENMASK(4, 0) 1615 1616 struct rtw89_traffic_stats { 1617 /* units in bytes */ 1618 u64 tx_unicast; 1619 u64 rx_unicast; 1620 u32 tx_avg_len; 1621 u32 rx_avg_len; 1622 1623 /* count for packets */ 1624 u64 tx_cnt; 1625 u64 rx_cnt; 1626 1627 /* units in Mbps */ 1628 u32 tx_throughput; 1629 u32 rx_throughput; 1630 u32 tx_throughput_raw; 1631 u32 rx_throughput_raw; 1632 1633 u32 rx_tf_acc; 1634 u32 rx_tf_periodic; 1635 1636 enum rtw89_tfc_lv tx_tfc_lv; 1637 enum rtw89_tfc_lv rx_tfc_lv; 1638 struct ewma_tp tx_ewma_tp; 1639 struct ewma_tp rx_ewma_tp; 1640 1641 u16 tx_rate; 1642 u16 rx_rate; 1643 1644 /* used by rtwvif only */ 1645 u64 tcp, udp, udp_ratio; 1646 u8 active_histogram; 1647 }; 1648 1649 struct rtw89_btc_chdef { 1650 u8 center_ch; 1651 u8 band; 1652 u8 chan; 1653 enum rtw89_sc_offset offset; 1654 enum rtw89_bandwidth bw; 1655 }; 1656 1657 struct rtw89_btc_statistic { 1658 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1659 struct rtw89_traffic_stats traffic; 1660 }; 1661 1662 #define BTC_WL_RSSI_THMAX 4 1663 1664 struct rtw89_btc_wl_link_info { 1665 struct rtw89_btc_chdef chdef; 1666 struct rtw89_btc_statistic stat; 1667 enum rtw89_tfc_dir dir; 1668 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1669 u8 mac_addr[ETH_ALEN]; 1670 u8 busy; 1671 u8 ch; 1672 u8 bw; 1673 u8 band; 1674 u8 role; 1675 u8 pid; 1676 u8 phy; 1677 u8 dtim_period; 1678 u8 mode; 1679 u8 tx_1ss_limit; 1680 1681 u8 mac_id; 1682 u8 tx_retry; 1683 1684 u32 bcn_period; 1685 u32 busy_t; 1686 u32 tx_time; 1687 u32 client_cnt; 1688 u32 rx_rate_drop_cnt; 1689 u32 noa_duration; 1690 1691 u32 active: 1; 1692 u32 noa: 1; 1693 u32 client_ps: 1; 1694 u32 connected: 2; 1695 }; 1696 1697 union rtw89_btc_wl_state_map { 1698 u32 val; 1699 struct rtw89_btc_wl_smap map; 1700 }; 1701 1702 struct rtw89_btc_bt_hfp_desc { 1703 u32 exist: 1; 1704 u32 type: 2; 1705 u32 rsvd: 29; 1706 }; 1707 1708 struct rtw89_btc_bt_hid_desc { 1709 u32 exist: 1; 1710 u32 slot_info: 2; 1711 u32 pair_cnt: 2; 1712 u32 type: 8; 1713 u32 rsvd: 19; 1714 }; 1715 1716 struct rtw89_btc_bt_a2dp_desc { 1717 u8 exist: 1; 1718 u8 exist_last: 1; 1719 u8 play_latency: 1; 1720 u8 type: 3; 1721 u8 active: 1; 1722 u8 sink: 1; 1723 u32 handle_update: 1; 1724 u32 devinfo_query: 1; 1725 u32 no_empty_streak_2s: 8; 1726 u32 no_empty_streak_max: 8; 1727 u32 rsvd: 6; 1728 1729 u8 bitpool; 1730 u16 vendor_id; 1731 u32 device_name; 1732 u32 flush_time; 1733 }; 1734 1735 struct rtw89_btc_bt_pan_desc { 1736 u32 exist: 1; 1737 u32 type: 1; 1738 u32 active: 1; 1739 u32 rsvd: 29; 1740 }; 1741 1742 struct rtw89_btc_bt_rfk_info { 1743 u32 run: 1; 1744 u32 req: 1; 1745 u32 timeout: 1; 1746 u32 rsvd: 29; 1747 }; 1748 1749 union rtw89_btc_bt_rfk_info_map { 1750 u32 val; 1751 struct rtw89_btc_bt_rfk_info map; 1752 }; 1753 1754 struct rtw89_btc_bt_ver_info { 1755 u32 fw_coex; /* match with which coex_ver */ 1756 u32 fw; 1757 }; 1758 1759 struct rtw89_btc_bool_sta_chg { 1760 u8 now: 1; 1761 u8 last: 1; 1762 u8 remain: 1; 1763 u8 srvd: 5; 1764 }; 1765 1766 struct rtw89_btc_u8_sta_chg { 1767 u8 now; 1768 u8 last; 1769 u8 chg; 1770 u8 rsvd; 1771 }; 1772 1773 struct rtw89_btc_wl_scan_info { 1774 u8 band[RTW89_PHY_NUM]; 1775 u8 phy_map; 1776 u8 hw_band_map; 1777 u8 type; 1778 u8 fw_scan; 1779 }; 1780 1781 struct rtw89_btc_wl_dbcc_info { 1782 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1783 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1784 u8 real_band[RTW89_PHY_NUM]; 1785 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1786 }; 1787 1788 struct rtw89_btc_wl_mlo_info_v2 { 1789 u8 wmode[RTW89_PHY_NUM]; 1790 u8 ch_type[RTW89_PHY_NUM]; 1791 u8 hwb_rf_band[RTW89_PHY_NUM]; 1792 u8 path_rf_band[RTW89_PHY_NUM]; 1793 1794 u8 wtype; 1795 u8 mrcx_mode; 1796 u8 mrcx_act_hwb_map; 1797 u8 mrcx_bt_slot_rsp; 1798 1799 u8 rf_combination; 1800 u8 mlo_en; 1801 u8 mlo_adie; 1802 u8 dual_hw_band_en; 1803 1804 __le32 link_status; 1805 } __packed; 1806 1807 struct rtw89_btc_wl_mlo_info { 1808 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */ 1809 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */ 1810 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */ 1811 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */ 1812 1813 u8 wtype; /* enum phl_mr_wtype */ 1814 u8 mrcx_mode; 1815 u8 mrcx_act_hwb_map; 1816 u8 mrcx_bt_slot_rsp; 1817 1818 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */ 1819 u8 mlo_en; /* MLO enable */ 1820 u8 mlo_adie; /* a-die count */ 1821 u8 dual_hw_band_en; /* both 2 HW-band link exist */ 1822 1823 u32 link_status; /* enum mlo_dbcc_mode_type */ 1824 }; 1825 1826 struct rtw89_btc_wl_active_role { 1827 u8 connected: 1; 1828 u8 pid: 3; 1829 u8 phy: 1; 1830 u8 noa: 1; 1831 u8 band: 2; 1832 1833 u8 client_ps: 1; 1834 u8 bw: 7; 1835 1836 u8 role; 1837 u8 ch; 1838 1839 u16 tx_lvl; 1840 u16 rx_lvl; 1841 u16 tx_rate; 1842 u16 rx_rate; 1843 }; 1844 1845 struct rtw89_btc_wl_active_role_v1 { 1846 u8 connected: 1; 1847 u8 pid: 3; 1848 u8 phy: 1; 1849 u8 noa: 1; 1850 u8 band: 2; 1851 1852 u8 client_ps: 1; 1853 u8 bw: 7; 1854 1855 u8 role; 1856 u8 ch; 1857 1858 u16 tx_lvl; 1859 u16 rx_lvl; 1860 u16 tx_rate; 1861 u16 rx_rate; 1862 1863 u32 noa_duration; /* ms */ 1864 }; 1865 1866 struct rtw89_btc_wl_active_role_v2 { 1867 u8 connected: 1; 1868 u8 pid: 3; 1869 u8 phy: 1; 1870 u8 noa: 1; 1871 u8 band: 2; 1872 1873 u8 client_ps: 1; 1874 u8 bw: 7; 1875 1876 u8 role; 1877 u8 ch; 1878 1879 u32 noa_duration; /* ms */ 1880 }; 1881 1882 struct rtw89_btc_wl_active_role_v7 { 1883 u8 connected; 1884 u8 pid; 1885 u8 phy; 1886 u8 noa; 1887 1888 u8 band; 1889 u8 client_ps; 1890 u8 bw; 1891 u8 role; 1892 1893 u8 ch; 1894 u8 noa_dur; 1895 u8 client_cnt; 1896 u8 rsvd2; 1897 } __packed; 1898 1899 struct rtw89_btc_wl_role_info_bpos { 1900 u16 none: 1; 1901 u16 station: 1; 1902 u16 ap: 1; 1903 u16 vap: 1; 1904 u16 adhoc: 1; 1905 u16 adhoc_master: 1; 1906 u16 mesh: 1; 1907 u16 moniter: 1; 1908 u16 p2p_device: 1; 1909 u16 p2p_gc: 1; 1910 u16 p2p_go: 1; 1911 u16 nan: 1; 1912 }; 1913 1914 struct rtw89_btc_eslot_ctrl { 1915 u8 en; /* 1: toggle tx-flow-ctrl (null 0/1), tx-pause by Ext-slot */ 1916 u8 nulltx_role1; 1917 u8 nulltx_role2; 1918 u8 nulltx_pre_time; /* null-tx time prior to EBT-start (from E2G-end) */ 1919 }; 1920 1921 union rtw89_btc_wl_role_info_map { 1922 u16 val; 1923 struct rtw89_btc_wl_role_info_bpos role; 1924 }; 1925 1926 struct rtw89_btc_wl_role_info_v0 { /* struct size must be n*4 bytes */ 1927 u8 connect_cnt; 1928 u8 link_mode; 1929 union rtw89_btc_wl_role_info_map role_map; 1930 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1931 }; 1932 1933 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1934 u8 connect_cnt; 1935 u8 link_mode; 1936 union rtw89_btc_wl_role_info_map role_map; 1937 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1938 u32 mrole_type; /* btc_wl_mrole_type */ 1939 u32 mrole_noa_duration; /* ms */ 1940 1941 u32 dbcc_en: 1; 1942 u32 dbcc_chg: 1; 1943 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1944 u32 link_mode_chg: 1; 1945 u32 rsvd: 27; 1946 }; 1947 1948 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1949 u8 connect_cnt; 1950 u8 link_mode; 1951 union rtw89_btc_wl_role_info_map role_map; 1952 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1953 u32 mrole_type; /* btc_wl_mrole_type */ 1954 u32 mrole_noa_duration; /* ms */ 1955 1956 u32 dbcc_en: 1; 1957 u32 dbcc_chg: 1; 1958 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1959 u32 link_mode_chg: 1; 1960 u32 rsvd: 27; 1961 }; 1962 1963 struct rtw89_btc_wl_rlink_v0 { /* H2C info, struct size must be n*4 bytes */ 1964 u8 connected; 1965 u8 pid; 1966 u8 phy; 1967 u8 noa; 1968 1969 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1970 u8 active; /* 0:rlink is under doze */ 1971 u8 bw; /* enum channel_width */ 1972 u8 role; /*enum role_type */ 1973 1974 u8 ch; 1975 u8 noa_dur; /* ms */ 1976 u8 client_cnt; /* for Role = P2P-Go/AP */ 1977 u8 mode; /* wifi protocol */ 1978 } __packed; 1979 1980 struct rtw89_btc_wl_rlink_v10 { /* H2C info, struct size must be n*4 bytes */ 1981 u8 connected; 1982 u8 pid; 1983 u8 phy; 1984 u8 noa; 1985 1986 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1987 u8 active; /* 0:rlink is under doze */ 1988 u8 bw; /* enum channel_width */ 1989 u8 role; /*enum role_type */ 1990 1991 u8 ch; 1992 u8 noa_dur; /* ms */ 1993 u8 client_cnt; /* for Role = P2P-Go/AP */ 1994 u8 mode; /* wifi protocol */ 1995 1996 u8 mac_id; 1997 u8 rsvd0; 1998 u8 rsvd1; 1999 u8 rsvd2; 2000 } __packed; 2001 2002 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 2003 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 2004 u8 connect_cnt; 2005 u8 link_mode; 2006 u8 link_mode_chg; 2007 u8 p2p_2g; 2008 2009 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 2010 2011 __le32 role_map; 2012 __le32 mrole_type; /* btc_wl_mrole_type */ 2013 __le32 mrole_noa_duration; /* ms */ 2014 __le32 dbcc_en; 2015 __le32 dbcc_chg; 2016 __le32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 2017 } __packed; 2018 2019 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 2020 u8 connect_cnt; 2021 u8 link_mode; 2022 u8 link_mode_chg; 2023 u8 p2p_2g; 2024 2025 u8 pta_req_band; 2026 u8 dbcc_en; /* 1+1 and 2.4G-included */ 2027 u8 dbcc_chg; 2028 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 2029 2030 struct rtw89_btc_wl_rlink_v0 rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2031 2032 __le32 role_map; 2033 __le32 mrole_type; /* btc_wl_mrole_type */ 2034 __le32 mrole_noa_duration; /* ms */ 2035 } __packed; 2036 2037 struct rtw89_btc_wl_role_info_v10 { /* H2C info, struct size must be n*4 bytes */ 2038 struct rtw89_btc_wl_rlink_v10 rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2039 u8 link_mode; 2040 u8 link_mode_hb1; 2041 u8 p2p_exist; 2042 u8 p2p_exist_hb1; 2043 2044 u8 pta_req_band; 2045 u8 dbcc_en; /* 1+1 and 2.4G-included */ 2046 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 2047 u8 rsvd; 2048 2049 __le32 role_map; 2050 __le32 role_map_hb1; 2051 __le32 mrole_type; /* btc_wl_mrole_type: [31:16]:band1, [15:0]:band0 */ 2052 } __packed; 2053 2054 struct rtw89_btc_wl_rlink { /* Logic dynamic using */ 2055 u8 connected; 2056 u8 pid; 2057 u8 phy; 2058 u8 noa; 2059 2060 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 2061 u8 active; /* 0:rlink is under doze */ 2062 u8 bw; /* enum channel_width */ 2063 u8 role; /*enum role_type */ 2064 2065 u8 ch; 2066 u8 noa_dur; /* ms */ 2067 u8 client_cnt; /* for Role = P2P-Go/AP */ 2068 u8 mode; /* wifi protocol */ 2069 2070 /*v0 v1*/ 2071 u16 tx_lvl; 2072 u16 rx_lvl; 2073 u16 tx_rate; 2074 u16 rx_rate; 2075 2076 /* v7 */ 2077 u8 client_ps; /*v7 v2 v1 v0*/ 2078 2079 /* v10 */ 2080 u8 mac_id; 2081 u8 rsvd0; 2082 u8 rsvd1; 2083 u8 rsvd2; 2084 }; 2085 2086 struct rtw89_btc_wl_role_info { /* Logic dynamic using */ 2087 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2088 u8 link_mode; 2089 u8 link_mode_hb1; 2090 u8 p2p_exist; 2091 u8 p2p_exist_hb1; 2092 2093 u8 pta_req_band; 2094 u8 dbcc_en; /* 1+1 and 2.4G-included */ 2095 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 2096 u8 rsvd; 2097 2098 u32 role_map; 2099 u32 role_map_hb1; 2100 u32 mrole_type; /* btc_wl_mrole_type: [31:16]:band1, [15:0]:band0 */ 2101 2102 /* Before v10 use this linkmode */ 2103 u8 link_mode_v0; 2104 2105 /* v7 */ 2106 u8 connect_cnt; 2107 u32 dbcc_chg; /* v7 v2*/ 2108 2109 /* v8 */ 2110 u8 link_mode_chg; /* v8, v7 v2*/ 2111 u8 p2p_2g; /* v8, v7 */ 2112 u32 mrole_noa_duration; /* v8, v7 v2*/ 2113 }; 2114 2115 struct rtw89_btc_wl_ver_info { 2116 char build_time[12]; 2117 char build_date[12]; 2118 u32 fw_coex; /* match with which coex_ver */ 2119 u32 fw; 2120 u32 mac; 2121 u32 bb; 2122 u32 rf; 2123 }; 2124 2125 struct rtw89_btc_wl_afh_info { 2126 u8 en; 2127 u8 ch; 2128 u8 bw; 2129 u8 band; 2130 } __packed; 2131 2132 struct rtw89_btc_wl_rfk_info { 2133 u32 state: 2; 2134 u32 path_map: 4; 2135 u32 phy_map: 2; 2136 u32 band: 2; 2137 u32 type: 8; 2138 u32 con_rfk: 1; 2139 u32 rsvd: 13; 2140 2141 u32 start_time; 2142 u32 proc_time; 2143 }; 2144 2145 struct rtw89_btc_bt_smap { 2146 u32 connect: 1; 2147 u32 ble_connect: 1; 2148 u32 acl_busy: 1; 2149 u32 sco_busy: 1; 2150 u32 mesh_busy: 1; 2151 u32 inq_pag: 1; 2152 u32 profile_map: 8; 2153 u32 rsvd: 18; 2154 }; 2155 2156 union rtw89_btc_bt_state_map { 2157 u32 val; 2158 struct rtw89_btc_bt_smap map; 2159 }; 2160 2161 #define BTC_BT_RSSI_THMAX 4 2162 #define BTC_BT_AFH_GROUP 12 2163 #define BTC_BT_AFH_LE_GROUP 5 2164 2165 struct rtw89_btc_bt_txpwr_desc { 2166 s8 br_dbm; 2167 s8 le_dbm; 2168 u8 br_gain_index; 2169 u8 le_gain_index; 2170 }; 2171 2172 struct rtw89_btc_bt_leaudio_info { 2173 u8 cmd; 2174 u8 len; 2175 u8 bis_cis; 2176 #define RTW89_BTC_LEAU_INFO_L2_BIS_EX BIT(0) 2177 #define RTW89_BTC_LEAU_INFO_L2_BIS_CNT GENMASK(3, 1) 2178 #define RTW89_BTC_LEAU_INFO_L2_CIS_EX BIT(4) 2179 #define RTW89_BTC_LEAU_INFO_L2_CIS_CNT GENMASK(7, 5) 2180 u8 rssi; 2181 __le32 hbrsvd; 2182 } __packed; 2183 2184 struct rtw89_btc_bt_bistdma_info_le { 2185 u8 cmd; 2186 u8 len; 2187 u8 bis; /* BIT(2) ~ BIT(7) is rsvd */ 2188 #define RTW89_BTC_BIS_INFO_L2_START_END BIT(0) /* 0: BIS start, 1: BIS end */ 2189 #define RTW89_BTC_BIS_INFO_L2_TRX BIT(1) /* 0: BIS Tx, 1: BIS Rx */ 2190 u8 diff_t_lb; 2191 u8 diff_t_hb; /* diff_t = (diff_t_hb * 256 + diff_t_lb) * 0.625 ms */ 2192 u8 hb1rsvd; 2193 u8 hb2rsvd; 2194 u8 hb3rsvd; 2195 } __packed; 2196 2197 struct rtw89_btc_bt_leaudio_desc { 2198 u32 bis_exist: 1; 2199 u32 bis_exist_last: 1; 2200 u32 cis_exist: 1; 2201 u32 cis_exist_last: 1; 2202 u32 bis_cnt: 3; 2203 u32 cis_cnt: 3; 2204 u32 rssi: 8; 2205 u32 bis_cnt_last: 3; 2206 u32 cis_cnt_last: 3; 2207 u32 bis_trx: 1; 2208 u32 bis_start_end: 1; 2209 u32 rsvd: 6; 2210 2211 u16 diff_t; 2212 }; 2213 2214 struct rtw89_btc_bt_link_info { 2215 struct rtw89_btc_u8_sta_chg link_cnt; 2216 struct rtw89_btc_bool_sta_chg multi_link; 2217 struct rtw89_btc_bool_sta_chg relink; 2218 struct rtw89_btc_bt_hfp_desc hfp_desc; 2219 struct rtw89_btc_bt_hid_desc hid_desc; 2220 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 2221 struct rtw89_btc_bt_pan_desc pan_desc; 2222 struct rtw89_btc_bt_leaudio_desc leaudio_desc; 2223 union rtw89_btc_bt_state_map status; 2224 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc; 2225 2226 u8 sut_pwr_level[BTC_PROFILE_MAX]; 2227 u8 golden_rx_shift[BTC_PROFILE_MAX]; 2228 u8 rssi_state[BTC_BT_RSSI_THMAX]; 2229 u8 afh_map[BTC_BT_AFH_GROUP]; 2230 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 2231 u8 rssi; 2232 2233 u8 role_sw: 1; 2234 u8 slave_role: 1; 2235 u8 afh_update: 1; 2236 u8 cqddr: 1; 2237 u8 tx_3m: 1; 2238 u8 inq: 1; 2239 u8 pag: 1; 2240 u8 igno_wl: 1; 2241 2242 u8 ble_scan_en: 1; 2243 u8 reinit: 1; 2244 u8 rsvd: 6; 2245 2246 u8 leaudio_raw_info[BTC_BTINFO_MAX]; /* raw LE audio info from BT mailbox */ 2247 u8 bistdma_raw_info[BTC_BTINFO_MAX]; /* raw BIS-TDMA info from BT mailbox */ 2248 }; 2249 2250 struct rtw89_btc_bind_bt_status { 2251 u8 a2dp_active: 1; 2252 u8 a2dp_sink: 1; 2253 u8 pan_active: 1; 2254 u8 connect: 1; 2255 u8 inq_page: 1; 2256 u8 multi_link: 1; 2257 u8 slave_role: 1; 2258 u8 page: 1; 2259 2260 u8 hfp_exist: 1; 2261 u8 hid_exist: 1; 2262 u8 a2dp_exist: 1; 2263 u8 pan_exist: 1; 2264 u8 bis_exist: 1; 2265 u8 cis_exist: 1; 2266 u8 thread_exist: 1; 2267 u8 ull_exist: 1; 2268 2269 u8 hid_cnt; 2270 u8 hid_type; 2271 u8 cis_cnt; 2272 u8 link_cnt; 2273 2274 u16 a2dp_vendor_id; 2275 }; 2276 2277 struct rtw89_btc_bind_info { 2278 u8 wl_hwb_sel; /* map */ 2279 u8 wl_link_mode; 2280 u8 wl_bg_mode; 2281 u8 rf_band; /* map, 0: no any rf-band bind */ 2282 u8 bt_sel; /* map */ 2283 u8 bt_link_weight; /* select the highest weight between bt/rf-band */ 2284 2285 u32 bt_profile; /* map */ 2286 struct rtw89_btc_bind_bt_status bt_smap; 2287 }; 2288 2289 struct rtw89_btc_extsoc_info { 2290 u8 chip_id; 2291 u8 max_tx_pwr; 2292 u8 rf_band_map; 2293 u8 ant_iso_to_wl; 2294 2295 u8 link_weight[BTC_BT_BMAX]; 2296 2297 u8 func_type; /* 0: none, 1:zigbee, 2:LTE */ 2298 u8 hw_coex; /* Hard-Wire coex interface support */ 2299 u8 pta_type; /* 0: RTK 4-wire mode, 1: 3-wire mode */ 2300 u8 pta_req_exist; 2301 2302 u32 hpta_cfg; 2303 u32 hmbx_cfg; 2304 u32 swout_cfg; 2305 u32 swin_cfg; 2306 u32 profile_map[BTC_BT_BMAX]; 2307 u32 bcnt[BTC_BCNT_NUM]; 2308 }; 2309 2310 struct rtw89_btc_dm_emap { 2311 u32 init: 1; 2312 u32 pta_owner: 1; 2313 u32 wl_rfk_timeout: 1; 2314 u32 bt_rfk_timeout: 1; 2315 u32 wl_fw_hang: 1; 2316 u32 cycle_hang: 1; 2317 u32 w1_hang: 1; 2318 u32 b1_hang: 1; 2319 u32 tdma_no_sync: 1; 2320 u32 slot_no_sync: 1; 2321 u32 wl_slot_drift: 1; 2322 u32 bt_slot_drift: 1; 2323 u32 role_num_mismatch: 1; 2324 u32 null1_tx_late: 1; 2325 u32 bt_afh_conflict: 1; 2326 u32 bt_leafh_conflict: 1; 2327 u32 bt_slot_flood: 1; 2328 u32 wl_e2g_hang: 1; 2329 u32 wl_ver_mismatch: 1; 2330 u32 bt_ver_mismatch: 1; 2331 u32 rfe_type0: 1; 2332 u32 h2c_buffer_over: 1; 2333 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 2334 u32 wl_no_sta_ntfy: 1; 2335 u32 w2b_scbd_no_sync: 1; 2336 2337 u32 h2c_bmap_mismatch: 1; 2338 u32 c2h_bmap_mismatch: 1; 2339 u32 h2c_struct_invalid: 1; 2340 u32 c2h_struct_invalid: 1; 2341 u32 h2c_c2h_buffer_mismatch: 1; 2342 }; 2343 2344 union rtw89_btc_dm_error_map { 2345 u32 val; 2346 struct rtw89_btc_dm_emap map; 2347 }; 2348 2349 struct rtw89_btc_rf_para { 2350 u32 tx_pwr_freerun; 2351 u32 rx_gain_freerun; 2352 u32 tx_pwr_perpkt; 2353 u32 rx_gain_perpkt; 2354 }; 2355 2356 struct rtw89_btc_wl_nhm { 2357 u8 instant_wl_nhm_dbm; 2358 u8 instant_wl_nhm_per_mhz; 2359 u16 valid_record_times; 2360 s8 record_pwr[16]; 2361 u8 record_ratio[16]; 2362 s8 pwr; /* dbm_per_MHz */ 2363 u8 ratio; 2364 u8 current_status; 2365 u8 refresh; 2366 bool start_flag; 2367 s8 pwr_max; 2368 s8 pwr_min; 2369 }; 2370 2371 struct rtw89_btc_wl_info { 2372 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 2373 struct rtw89_btc_chdef rf_ch_info[RTW89_PHY_NUM]; 2374 struct rtw89_btc_wl_rfk_info rfk_info; 2375 struct rtw89_btc_wl_ver_info ver_info; 2376 struct rtw89_btc_wl_afh_info afh_info[RTW89_MAC_NUM][RTW89_BAND_NUM]; 2377 struct rtw89_btc_wl_afh_info afh_info_last[RTW89_MAC_NUM][RTW89_BAND_NUM]; 2378 struct rtw89_btc_wl_role_info role_info; 2379 struct rtw89_btc_wl_scan_info scan_info; 2380 struct rtw89_btc_wl_dbcc_info dbcc_info; 2381 struct rtw89_btc_wl_mlo_info mlo_info; 2382 struct rtw89_btc_rf_para rf_para; 2383 struct rtw89_btc_wl_nhm nhm; 2384 union rtw89_btc_wl_state_map status; 2385 2386 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 2387 u8 rssi_level; 2388 u8 cn_report; 2389 u8 coex_mode; 2390 u8 pta_req_mac; 2391 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 2392 u8 rf_band_map[RTW89_PHY_NUM]; /* rf_band bit-map */ 2393 u8 ch_map[12]; 2394 u8 ch_map_le[5]; 2395 2396 bool is_5g_hi_ch; 2397 bool is_5g_hi_ch_hb1; 2398 bool go_client_exist; 2399 bool go_client_exist_hb1; 2400 bool noa_exist; 2401 bool noa_exist_hb1; 2402 bool pta_reg_mac_chg; 2403 bool bg_mode; 2404 bool bg_mode_hb1; 2405 bool he_mode; 2406 bool scbd_chg[BTC_ALL_BT]; 2407 bool fw_ver_mismatch; 2408 bool client_cnt_inc_2g; 2409 bool link_mode_chg; 2410 bool dbcc_chg; 2411 u32 scbd[BTC_ALL_BT]; 2412 u32 scbd_rb[BTC_ALL_BT]; 2413 u32 wcnt[BTC_WCNT_NUM]; 2414 }; 2415 2416 struct rtw89_btc_module_v0 { 2417 struct rtw89_btc_ant_info_v0 ant; 2418 u8 rfe_type; 2419 u8 cv; 2420 2421 u8 bt_solo: 1; 2422 u8 bt_pos: 1; 2423 u8 switch_type: 1; 2424 u8 wa_type: 3; 2425 2426 u8 kt_ver_adie; 2427 }; 2428 2429 struct rtw89_btc_module_v7 { 2430 u8 rfe_type; 2431 u8 kt_ver; 2432 u8 bt_solo; 2433 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 2434 2435 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 2436 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 2437 u8 kt_ver_adie; 2438 u8 rsvd; 2439 2440 struct rtw89_btc_ant_info_v7 ant; 2441 } __packed; 2442 2443 struct rtw89_btc_module_v10 { 2444 u8 rfe_type; 2445 u8 wa_type; /* Refer to enum btc_wa_type */ 2446 u8 kt_ver; 2447 u8 kt_ver_adie; 2448 2449 u8 bt0_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 2450 u8 bt0_sw_type; /* BT Ant-switch: None(non-share), Int(BTG), Ext(SPDT)*/ 2451 u8 bt1_pos; /* BTC_BT_ALONE or BTC_BT_BTG */ 2452 u8 bt1_sw_type; 2453 2454 struct rtw89_btc_ant_info_v10 ant; 2455 } __packed; 2456 2457 struct rtw89_btc_module_v11 { 2458 u8 rfe_type; 2459 u8 wa_type; 2460 u8 kt_ver; 2461 u8 kt_ver_adie; 2462 2463 u8 bt0_pos; 2464 u8 bt0_sw_type; 2465 u8 bt1_pos; 2466 u8 bt1_sw_type; 2467 2468 struct rtw89_btc_ant_info_v11 ant; 2469 } __packed; 2470 2471 union rtw89_btc_module_info { 2472 struct rtw89_btc_module_v0 md_v0; 2473 struct rtw89_btc_module_v7 md_v7; 2474 struct rtw89_btc_module_v10 md_v10; 2475 struct rtw89_btc_module_v11 md_v11; 2476 }; 2477 2478 struct rtw89_btc_module { 2479 u8 rfe_type; 2480 u8 wa_type; /* Refer to enum btc_wa_type */ 2481 u8 kt_ver; 2482 u8 kt_ver_adie; 2483 2484 u8 bt0_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 2485 u8 bt0_sw_type; /* BT Ant-switch: None(non-share), Int(BTG), Ext(SPDT)*/ 2486 u8 bt1_pos; /* BTC_BT_ALONE or BTC_BT_BTG */ 2487 u8 bt1_sw_type; 2488 2489 u8 bt_solo; 2490 2491 struct rtw89_btc_ant_info ant; 2492 }; 2493 2494 #define RTW89_BTC_DM_MAXSTEP 30 2495 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 2496 2497 struct rtw89_btc_dm_step { 2498 u16 step[RTW89_BTC_DM_MAXSTEP]; 2499 u8 step_pos; 2500 bool step_ov; 2501 }; 2502 2503 struct rtw89_btc_init_info_v0 { 2504 struct rtw89_btc_module_v0 module; 2505 u8 wl_guard_ch; 2506 2507 u8 wl_only: 1; 2508 u8 wl_init_ok: 1; 2509 u8 dbcc_en: 1; 2510 u8 cx_other: 1; 2511 u8 bt_only: 1; 2512 2513 u16 rsvd; 2514 } __packed; 2515 2516 struct rtw89_btc_init_info_v7 { 2517 u8 wl_guard_ch; 2518 u8 wl_only; 2519 u8 wl_init_ok; 2520 u8 rsvd3; 2521 2522 u8 cx_other; 2523 u8 bt_only; 2524 u8 pta_mode; 2525 u8 pta_direction; 2526 2527 struct rtw89_btc_module_v7 module; 2528 } __packed; 2529 2530 struct rtw89_btc_init_info_v107 { 2531 u8 wl_guard_ch; 2532 u8 wl_only; 2533 u8 wl_init_ok; 2534 u8 dbcc_en; 2535 2536 u8 cx_other; 2537 u8 bt_only; 2538 u8 rsvd; 2539 u8 rsvd1; 2540 2541 struct rtw89_btc_module_v7 module; 2542 } __packed; 2543 2544 struct rtw89_btc_init_info_v10 { 2545 u8 endian_type; /* 0: little-endian, 1:big-endian */ 2546 u8 init_mode; /* refer to enum BTC_MODE_xxx */ 2547 u8 wl_init_ok; 2548 u8 bt0_function; 2549 2550 u8 bt1_function; 2551 u8 bt2_function; 2552 u8 pta_mode; 2553 u8 pta_direction; 2554 2555 struct rtw89_btc_module_v10 module; 2556 } __packed; 2557 2558 struct rtw89_btc_init_info_v11 { 2559 u8 endian_type; /* 0: little-endian, 1:big-endian */ 2560 u8 init_mode; /* refer to enum BTC_MODE_xxx */ 2561 u8 wl_init_ok; 2562 u8 bt0_function; 2563 2564 u8 bt1_function; 2565 u8 bt2_function; 2566 u8 pta_mode; 2567 u8 pta_direction; 2568 2569 struct rtw89_btc_module_v11 module; 2570 }; 2571 2572 union rtw89_btc_init_info_u { 2573 struct rtw89_btc_init_info_v0 init_v0; 2574 struct rtw89_btc_init_info_v7 init_v7; 2575 struct rtw89_btc_init_info_v10 init_v10; 2576 struct rtw89_btc_init_info_v107 init_v107; 2577 struct rtw89_btc_init_info_v11 init_v11; 2578 }; 2579 2580 struct rtw89_btc_init_info { 2581 u8 endian_type; /* 0: little-endian, 1:big-endian */ 2582 u8 init_mode; /* refer to enum BTC_MODE_xxx */ 2583 u8 wl_init_ok; 2584 u8 bt0_function; 2585 2586 u8 bt1_function; 2587 u8 bt2_function; 2588 u8 pta_mode; 2589 u8 pta_direction; 2590 2591 u8 dbcc_en; 2592 u8 cx_other; 2593 u8 bt_only; 2594 u8 wl_only; 2595 2596 u8 wl_guard_ch; 2597 2598 struct rtw89_btc_module module; 2599 }; 2600 2601 struct rtw89_btc_wl_tx_limit_para { 2602 u16 enable; 2603 u32 tx_time; /* unit: us */ 2604 u16 tx_retry; 2605 }; 2606 2607 struct rtw89_btc_wl_trx_nss_para { 2608 u8 tx_limit; 2609 u8 rx_limit; 2610 u8 tx_ss; 2611 u8 rx_ss; 2612 u8 tx_path; 2613 u8 rx_path; 2614 }; 2615 2616 enum rtw89_btc_bt_scan_type { 2617 BTC_SCAN_INQ = 0, 2618 BTC_SCAN_PAGE, 2619 BTC_SCAN_BLE, 2620 BTC_SCAN_INIT, 2621 BTC_SCAN_TV, 2622 BTC_SCAN_ADV, 2623 BTC_SCAN_MAX1, 2624 }; 2625 2626 enum rtw89_btc_ble_scan_type { 2627 CXSCAN_BG = 0, 2628 CXSCAN_INIT, 2629 CXSCAN_LE, 2630 CXSCAN_MAX 2631 }; 2632 2633 enum rtw89_btc_bt_func_type { 2634 BTC_BTF_NONE = 0, 2635 BTC_BTF_BT = BIT(0), 2636 BTC_BTF_ZB = BIT(1), 2637 BTC_BTF_THREAD = BIT(2), 2638 BTC_BTF_24GPRO = BIT(3), /* 2.4GHz Proprietary */ 2639 BTC_BTF_ULL = BIT(4), 2640 }; 2641 2642 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2643 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2644 #define RTW89_BTC_BT_DEF_BR_TX_PWR 4 2645 #define RTW89_BTC_BT_DEF_LE_TX_PWR 4 2646 #define RTW89_BTC_DEFAULT_ANISO 10 2647 #define RTW89_BTC_BT_DEF_LE_TX_PWR_1 10 2648 2649 struct rtw89_btc_bt_scan_info_v1 { 2650 __le16 win; 2651 __le16 intvl; 2652 __le32 flags; 2653 } __packed; 2654 2655 struct rtw89_btc_bt_scan_info_v2 { 2656 __le16 win; 2657 __le16 intvl; 2658 } __packed; 2659 2660 struct rtw89_btc_fbtc_btscan_v1 { 2661 u8 fver; /* btc_ver::fcxbtscan */ 2662 u8 rsvd; 2663 __le16 rsvd2; 2664 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2665 } __packed; 2666 2667 struct rtw89_btc_fbtc_btscan_v2 { 2668 u8 fver; /* btc_ver::fcxbtscan */ 2669 u8 type; 2670 __le16 rsvd2; 2671 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2672 } __packed; 2673 2674 struct rtw89_btc_fbtc_btscan_v7 { 2675 u8 fver; /* btc_ver::fcxbtscan */ 2676 u8 type; 2677 u8 rsvd0; 2678 u8 rsvd1; 2679 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2680 } __packed; 2681 2682 struct rtw89_btc_fbtc_btscan_v8 { 2683 u8 fver; /* btc_ver::fcxbtscan */ 2684 u8 type; 2685 u8 bt_id; /* 0:BT0, 1:BT1 */ 2686 u8 rsvd1; 2687 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2688 } __packed; 2689 2690 union rtw89_btc_fbtc_btscan { 2691 struct rtw89_btc_fbtc_btscan_v1 v1; 2692 struct rtw89_btc_fbtc_btscan_v2 v2; 2693 struct rtw89_btc_fbtc_btscan_v7 v7; 2694 struct rtw89_btc_fbtc_btscan_v8 v8; 2695 }; 2696 2697 struct rtw89_btc_bt_info { 2698 struct rtw89_btc_bt_link_info link_info; 2699 struct rtw89_btc_bt_link_info link_info_56g; 2700 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2701 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2702 struct rtw89_btc_bt_ver_info ver_info; 2703 struct rtw89_btc_bool_sta_chg enable; 2704 struct rtw89_btc_bool_sta_chg inq_pag; 2705 struct rtw89_btc_rf_para rf_para; 2706 union rtw89_btc_bt_rfk_info_map rfk_info; 2707 2708 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox (2.4G) */ 2709 u8 raw_info_56g[BTC_BTINFO_MAX]; /* raw bt info from mailbox (5/6G) */ 2710 u8 txpwr_info[BTC_BTINFO_MAX]; 2711 u8 link_weight[BTC_BT_BMAX]; /* Link Weight for RF-band/HWB selection */ 2712 u8 rssi_level; 2713 u8 rf_band_map; 2714 u8 func_type; 2715 u8 tx_power_now; 2716 u8 tx_power_now_6g; 2717 u8 ant_iso_to_wl; /* ant isolation between BTx and WL */ 2718 2719 u8 fw_ver_mismatch: 1; 2720 u8 band_56G_support: 1; 2721 u8 hi_lna_rx: 1; 2722 u8 lna_constrain: 3; 2723 u8 hi_lna_rx_6g: 1; 2724 u8 lna_constrain_6g: 3; 2725 u8 rsvd: 6; 2726 2727 u32 scbd; 2728 u32 scbd_rb; 2729 u32 scbd_c2h; 2730 u32 feature; 2731 2732 u32 mbx_avl: 1; 2733 u32 whql_test: 1; 2734 u32 igno_wl: 1; 2735 u32 reinit: 1; 2736 u32 ble_scan_en: 1; 2737 u32 btg_type: 1; 2738 u32 inq: 1; 2739 u32 pag: 1; 2740 u32 run_patch_code: 1; 2741 u32 scan_rx_low_pri: 1; 2742 u32 scan_info_update: 1; 2743 u32 rsvd1: 22; 2744 2745 u32 bcnt[BTC_BCNT_NUM]; 2746 }; 2747 2748 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2749 struct rtw89_btc_rf_trx_para_v0 { 2750 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2751 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2752 u8 bt_tx_power; /* decrease Tx power (dB) */ 2753 u8 bt_rx_gain; /* LNA constrain level */ 2754 }; 2755 2756 struct rtw89_btc_rf_trx_para_v9 { 2757 u32 wl_tx_power[RTW89_PHY_NUM]; /* absolute Tx power (dBm), 1's complement -5->0x85 */ 2758 u32 wl_rx_gain[RTW89_PHY_NUM]; /* rx gain table index (TBD.) */ 2759 u32 bt_tx_power[BTC_ALL_BT]; /* decrease Tx power (dB) */ 2760 u32 bt_rx_gain[BTC_ALL_BT]; /* LNA constrain level */ 2761 u32 zb_tx_power[BTC_ALL_BT]; /* 15.4 devrease Tx power (dB) */ 2762 u32 zb_rx_gain[BTC_ALL_BT]; /* 15.4 constrain level */ 2763 }; 2764 2765 struct rtw89_btc_cx { 2766 struct rtw89_btc_wl_info wl; 2767 struct rtw89_btc_bt_info bt0; 2768 struct rtw89_btc_bt_info bt1; 2769 struct rtw89_btc_extsoc_info bt_ext; 2770 struct rtw89_btc_rf_trx_para_v9 rf_para; 2771 u32 state_map; 2772 }; 2773 2774 struct rtw89_btc_fbtc_tdma { 2775 u8 type; /* btc_ver::fcxtdma */ 2776 u8 rxflctrl; 2777 u8 txflctrl; 2778 u8 bind; 2779 u8 leak_n; 2780 u8 ext_ctrl; 2781 u8 rxflctrl_role; 2782 u8 option_ctrl; 2783 } __packed; 2784 2785 struct rtw89_btc_fbtc_tdma_v3 { 2786 u8 fver; /* btc_ver::fcxtdma */ 2787 u8 rsvd; 2788 __le16 rsvd1; 2789 struct rtw89_btc_fbtc_tdma tdma; 2790 } __packed; 2791 2792 union rtw89_btc_fbtc_tdma_le32 { 2793 struct rtw89_btc_fbtc_tdma v1; 2794 struct rtw89_btc_fbtc_tdma_v3 v3; 2795 }; 2796 2797 #define CXMREG_MAX 30 2798 #define CXMREG_MAX_V2 20 2799 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2800 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2801 2802 enum rtw89_btc_bt_sta_counter { 2803 BTC_BCNT_RFK_REQ = 0, 2804 BTC_BCNT_RFK_GO = 1, 2805 BTC_BCNT_RFK_REJECT = 2, 2806 BTC_BCNT_RFK_FAIL = 3, 2807 BTC_BCNT_RFK_TIMEOUT = 4, 2808 BTC_BCNT_HI_TX = 5, 2809 BTC_BCNT_HI_RX = 6, 2810 BTC_BCNT_LO_TX = 7, 2811 BTC_BCNT_LO_RX = 8, 2812 BTC_BCNT_POLLUTED = 9, 2813 BTC_BCNT_STA_MAX 2814 }; 2815 2816 enum rtw89_btc_bt_sta_counter_v105 { 2817 BTC_BCNT_RFK_REQ_V105 = 0, 2818 BTC_BCNT_HI_TX_V105 = 1, 2819 BTC_BCNT_HI_RX_V105 = 2, 2820 BTC_BCNT_LO_TX_V105 = 3, 2821 BTC_BCNT_LO_RX_V105 = 4, 2822 BTC_BCNT_POLLUTED_V105 = 5, 2823 BTC_BCNT_STA_MAX_V105 2824 }; 2825 2826 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2827 u16 fver; /* btc_ver::fcxbtcrpt */ 2828 u16 rpt_cnt; /* tmr counters */ 2829 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2830 u32 wl_fw_cx_offload; 2831 u32 wl_fw_ver; 2832 u32 rpt_enable; 2833 u32 rpt_para; /* ms */ 2834 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2835 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2836 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2837 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2838 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2839 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2840 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2841 u32 c2h_cnt; /* fw send c2h counter */ 2842 u32 h2c_cnt; /* fw recv h2c counter */ 2843 } __packed; 2844 2845 struct rtw89_btc_fbtc_rpt_ctrl_info { 2846 __le32 cnt; /* fw report counter */ 2847 __le32 en; /* report map */ 2848 __le32 para; /* not used */ 2849 2850 __le32 cnt_c2h; /* fw send c2h counter */ 2851 __le32 cnt_h2c; /* fw recv h2c counter */ 2852 __le32 len_c2h; /* The total length of the last C2H */ 2853 2854 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2855 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2856 } __packed; 2857 2858 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2859 __le32 cx_ver; /* match which driver's coex version */ 2860 __le32 fw_ver; 2861 __le32 en; /* report map */ 2862 2863 __le16 cnt; /* fw report counter */ 2864 __le16 cnt_c2h; /* fw send c2h counter */ 2865 __le16 cnt_h2c; /* fw recv h2c counter */ 2866 __le16 len_c2h; /* The total length of the last C2H */ 2867 2868 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2869 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2870 } __packed; 2871 2872 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2873 __le16 cnt; /* fw report counter */ 2874 __le16 cnt_c2h; /* fw send c2h counter */ 2875 __le16 cnt_h2c; /* fw recv h2c counter */ 2876 __le16 len_c2h; /* The total length of the last C2H */ 2877 2878 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2879 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2880 2881 __le32 cx_ver; /* match which driver's coex version */ 2882 __le32 fw_ver; 2883 __le32 en; /* report map */ 2884 } __packed; 2885 2886 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2887 __le32 cx_ver; /* match which driver's coex version */ 2888 __le32 cx_offload; 2889 __le32 fw_ver; 2890 } __packed; 2891 2892 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2893 __le32 cnt_empty; /* a2dp empty count */ 2894 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2895 __le32 cnt_tx; 2896 __le32 cnt_ack; 2897 __le32 cnt_nack; 2898 } __packed; 2899 2900 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2901 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2902 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2903 __le32 cnt_recv; /* fw recv mailbox counter */ 2904 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2905 } __packed; 2906 2907 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2908 u8 fver; 2909 u8 rsvd; 2910 __le16 rsvd1; 2911 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2912 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2913 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2914 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2915 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2916 } __packed; 2917 2918 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2919 u8 fver; 2920 u8 rsvd; 2921 __le16 rsvd1; 2922 2923 u8 gnt_val[RTW89_PHY_NUM][4]; 2924 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2925 2926 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2927 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2928 } __packed; 2929 2930 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2931 u8 fver; 2932 u8 rsvd; 2933 __le16 rsvd1; 2934 2935 u8 gnt_val[RTW89_PHY_NUM][4]; 2936 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2937 2938 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2939 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2940 } __packed; 2941 2942 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2943 u8 fver; 2944 u8 rsvd0; 2945 u8 rsvd1; 2946 u8 rsvd2; 2947 2948 u8 gnt_val[RTW89_PHY_NUM][4]; 2949 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2950 2951 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2952 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2953 } __packed; 2954 2955 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2956 u8 fver; 2957 u8 rsvd0; 2958 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2959 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2960 2961 u8 gnt_val[RTW89_PHY_NUM][4]; 2962 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2963 2964 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2965 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2966 } __packed; 2967 2968 #define RTW89_BTC_TIME_DATE_FMT 12 2969 struct rtw89_btc_fbtc_rpt_ctrl_v9 { 2970 u8 fver; 2971 u8 ext_req_exist; 2972 u8 pta_owner; 2973 u8 rsvd; 2974 2975 u8 build_time[RTW89_BTC_TIME_DATE_FMT]; 2976 u8 build_date[RTW89_BTC_TIME_DATE_FMT]; 2977 2978 u8 gnt_val[RTW89_PHY_NUM][4]; /* gwl/gbt012 refer to struct btc_gnt_ctrl */ 2979 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2980 2981 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2982 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2983 } __packed; 2984 2985 struct rtw89_btc_fbtc_rpt_ctrl_v11 { 2986 u8 fver; 2987 u8 rsvd0; 2988 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2989 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2990 2991 u8 build_time[12]; 2992 u8 build_date[12]; 2993 2994 u8 gnt_val[RTW89_PHY_NUM][8]; /* gwl/gbt012 refer to struct btc_gnt_ctrl */ 2995 __le16 bt_cnt[BTC_ALL_BT_EZL][BTC_BCNT_STA_MAX_V105]; 2996 2997 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2998 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2999 3000 __le32 error_code; 3001 __le32 scbd_w2b[2]; 3002 __le32 scbd_b2w[2]; 3003 } __packed; 3004 3005 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 3006 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 3007 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 3008 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 3009 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 3010 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 3011 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 3012 struct rtw89_btc_fbtc_rpt_ctrl_v9 v9; 3013 struct rtw89_btc_fbtc_rpt_ctrl_v11 v11; 3014 }; 3015 3016 enum rtw89_fbtc_ext_ctrl_type { 3017 CXECTL_OFF = 0x0, /* tdma off */ 3018 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 3019 CXECTL_EXT = 0x2, 3020 CXECTL_MAX 3021 }; 3022 3023 union rtw89_btc_fbtc_rxflct { 3024 u8 val; 3025 u8 type: 3; 3026 u8 tgln_n: 5; 3027 }; 3028 3029 enum rtw89_btc_cxst_state { 3030 CXST_OFF = 0x0, 3031 CXST_B2W = 0x1, 3032 CXST_W1 = 0x2, 3033 CXST_W2 = 0x3, 3034 CXST_W2B = 0x4, 3035 CXST_B1 = 0x5, 3036 CXST_B2 = 0x6, 3037 CXST_B3 = 0x7, 3038 CXST_B4 = 0x8, 3039 CXST_LK = 0x9, 3040 CXST_BLK = 0xa, 3041 CXST_E2G = 0xb, 3042 CXST_E5G = 0xc, 3043 CXST_EBT = 0xd, 3044 CXST_ENULL = 0xe, 3045 CXST_WLK = 0xf, 3046 CXST_W1FDD = 0x10, 3047 CXST_B1FDD = 0x11, 3048 CXST_MAX = 0x12, 3049 }; 3050 3051 enum rtw89_btc_cxevnt { 3052 CXEVNT_TDMA_ENTRY = 0x0, 3053 CXEVNT_WL_TMR, 3054 CXEVNT_B1_TMR, 3055 CXEVNT_B2_TMR, 3056 CXEVNT_B3_TMR, 3057 CXEVNT_B4_TMR, 3058 CXEVNT_W2B_TMR, 3059 CXEVNT_B2W_TMR, 3060 CXEVNT_BCN_EARLY, 3061 CXEVNT_A2DP_EMPTY, 3062 CXEVNT_LK_END, 3063 CXEVNT_RX_ISR, 3064 CXEVNT_RX_FC0, 3065 CXEVNT_RX_FC1, 3066 CXEVNT_BT_RELINK, 3067 CXEVNT_BT_RETRY, 3068 CXEVNT_E2G, 3069 CXEVNT_E5G, 3070 CXEVNT_EBT, 3071 CXEVNT_ENULL, 3072 CXEVNT_DRV_WLK, 3073 CXEVNT_BCN_OK, 3074 CXEVNT_BT_CHANGE, 3075 CXEVNT_EBT_EXTEND, 3076 CXEVNT_E2G_NULL1, 3077 CXEVNT_B1FDD_TMR, 3078 CXEVNT_MAX 3079 }; 3080 3081 enum { 3082 CXBCN_ALL = 0x0, 3083 CXBCN_ALL_OK, 3084 CXBCN_BT_SLOT, 3085 CXBCN_BT_OK, 3086 CXBCN_MAX 3087 }; 3088 3089 enum btc_slot_type { 3090 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 3091 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 3092 CXSTYPE_NUM, 3093 }; 3094 3095 enum { /* TIME */ 3096 CXT_BT = 0x0, 3097 CXT_WL = 0x1, 3098 CXT_MAX 3099 }; 3100 3101 enum { /* TIME-A2DP */ 3102 CXT_FLCTRL_OFF = 0x0, 3103 CXT_FLCTRL_ON = 0x1, 3104 CXT_FLCTRL_MAX 3105 }; 3106 3107 enum { /* STEP TYPE */ 3108 CXSTEP_NONE = 0x0, 3109 CXSTEP_EVNT = 0x1, 3110 CXSTEP_SLOT = 0x2, 3111 CXSTEP_MAX, 3112 }; 3113 3114 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 3115 RPT_BT_AFH_SEQ_LEGACY = 0x10, 3116 RPT_BT_AFH_SEQ_LE = 0x20 3117 }; 3118 3119 enum btc_wl_gpio_debug { 3120 BTC_DBG_GNT_BT = 0, 3121 BTC_DBG_GNT_WL = 1, 3122 BTC_DBG_GNT_BT1 = 2, 3123 BTC_DBG_GNT_WL1 = 3, 3124 /* The following signals should 0-1 tiggle by each function-call */ 3125 BTC_DBG_BCN_EARLY = 4, 3126 BTC_DBG_WL_NULL0 = 5, 3127 BTC_DBG_WL_NULL1 = 6, 3128 BTC_DBG_WL_RXISR = 7, 3129 BTC_DBG_TDMA_ENTRY = 8, 3130 BTC_DBG_A2DP_EMPTY = 9, 3131 BTC_DBG_BT_RETRY = 10, 3132 /* The following signals should 0-1 tiggle by state L/H */ 3133 BTC_DBG_BT_RELINK = 11, 3134 BTC_DBG_SLOT_WL = 12, 3135 BTC_DBG_SLOT_BT = 13, 3136 /* The following signals should 0-1 tiggle by external*/ 3137 BTC_DBG_WL_ERR = 14, 3138 BTC_DBG_WL_OK = 15, 3139 /* The following signals appear only 1-active at same time*/ 3140 BTC_DBG_SLOT_B2W = 16, 3141 BTC_DBG_SLOT_W1 = 17, 3142 BTC_DBG_SLOT_W2 = 18, 3143 BTC_DBG_SLOT_W2B = 19, 3144 BTC_DBG_SLOT_B1 = 20, 3145 BTC_DBG_SLOT_B2 = 21, 3146 BTC_DBG_SLOT_B3 = 22, 3147 BTC_DBG_SLOT_B4 = 23, 3148 BTC_DBG_SLOT_LK = 24, 3149 BTC_DBG_SLOT_E2G = 25, 3150 BTC_DBG_SLOT_E5G = 26, 3151 BTC_DBG_SLOT_EBT = 27, 3152 BTC_DBG_SLOT_WLK = 28, 3153 BTC_DBG_SLOT_B1FDD = 29, 3154 BTC_DBG_BT_CHANGE = 30, 3155 /* The following signals should 0-1 tiggle by external*/ 3156 BTC_DBG_WL_CCA = 31, 3157 3158 BTC_DBG_NUM, 3159 }; 3160 3161 struct rtw89_btc_fbtc_gpio_dbg_v1 { 3162 u8 fver; /* btc_ver::fcxgpiodbg */ 3163 u8 rsvd; 3164 __le16 rsvd2; 3165 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 3166 __le32 pre_state; /* the debug signal is 1 or 0 */ 3167 u8 gpio_map[BTC_DBG_NUM]; /*the debug signals to GPIO-Position */ 3168 } __packed; 3169 3170 struct rtw89_btc_fbtc_gpio_dbg_v7 { 3171 u8 fver; 3172 u8 rsvd0; 3173 u8 rsvd1; 3174 u8 rsvd2; 3175 3176 u8 gpio_map[BTC_DBG_NUM]; 3177 3178 __le32 en_map; 3179 __le32 pre_state; 3180 } __packed; 3181 3182 union rtw89_btc_fbtc_gpio_dbg { 3183 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 3184 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 3185 }; 3186 3187 /* 3188 * SET_GPIO_CTRL payload (max len = 7 bytes) 3189 * 3190 * type = CXDGPIO_EN_MAP 3191 * data.val[31:0] = debug signal enable map 3192 * 3193 * type = CXDGPIO_MUX_MAP 3194 * data.mux.sig = debug signal id 3195 * data.mux.gpio = GPIO id 3196 * 3197 * type = CXDGPIO_EXT_HPTA / CXDGPIO_EXT_HMBX / CXDGPIO_EXT_SWOUT 3198 * data.map.map_low = GPIO 7~0 map 3199 * data.map.map_high = GPIO 15~8 map 3200 * 3201 * type = CXDGPIO_EXT_SWIN 3202 * data.swin.in_map_low = GPIO 7~0 input-en-map 3203 * data.swin.in_map_high = GPIO 15~8 input-en-map 3204 * data.swin.int_map_low = GPIO 7~0 interrupt source map 3205 * data.swin.int_map_high = GPIO 15~8 interrupt source map 3206 */ 3207 #define CXDGPIO_SET_L4 4 3208 #define CXDGPIO_SET_L2 2 3209 struct rtw89_fbtc_h2c_set_gpio_en_map { 3210 u8 type; /* gpio_type */ 3211 u8 fver; /* FCX_VER_GPIODBG */ 3212 u8 dlen; 3213 u32 en_map; 3214 }; 3215 3216 struct rtw89_fbtc_h2c_set_gpio_mux { 3217 u8 type; /* gpio_type */ 3218 u8 fver; /* FCX_VER_GPIODBG */ 3219 u8 dlen; 3220 u8 sig; 3221 u8 gpio; 3222 }; 3223 3224 struct rtw89_fbtc_h2c_set_gpio_ext_pta { 3225 u8 type; /* gpio_type */ 3226 u8 fver; /* FCX_VER_GPIODBG */ 3227 u8 dlen; 3228 u8 map_low; 3229 u8 map_high; 3230 }; 3231 3232 struct rtw89_fbtc_h2c_set_gpio_ext_mb { 3233 u8 type; /* gpio_type */ 3234 u8 fver; /* FCX_VER_GPIODBG */ 3235 u8 dlen; 3236 u8 map_low; 3237 u8 map_high; 3238 }; 3239 3240 struct rtw89_fbtc_h2c_set_gpio_ext_swout { 3241 u8 type; /* gpio_type */ 3242 u8 fver; /* FCX_VER_GPIODBG */ 3243 u8 dlen; 3244 u8 map_low; 3245 u8 map_high; 3246 }; 3247 3248 struct rtw89_fbtc_h2c_set_gpio_ext_swin { 3249 u8 type; /* gpio_type */ 3250 u8 fver; /* FCX_VER_GPIODBG */ 3251 u8 dlen; 3252 u8 in_map_low; 3253 u8 in_map_high; 3254 u8 int_map_low; 3255 u8 int_map_high; 3256 }; 3257 3258 struct rtw89_fbtc_h2c_set_gpio_2b { 3259 u8 type; /* gpio_type */ 3260 u8 fver; /* FCX_VER_GPIODBG */ 3261 u8 dlen; 3262 u8 data[CXDGPIO_SET_L2]; 3263 } __packed; 3264 3265 struct rtw89_fbtc_h2c_set_gpio_4b { 3266 u8 type; /* gpio_type */ 3267 u8 fver; /* FCX_VER_GPIODBG */ 3268 u8 dlen; 3269 u8 data[CXDGPIO_SET_L4]; 3270 } __packed; 3271 3272 union rtw89_fbtc_h2c_set_gpio_en_map_u { 3273 struct rtw89_fbtc_h2c_set_gpio_4b fmt; 3274 struct rtw89_fbtc_h2c_set_gpio_en_map data; 3275 }; 3276 3277 union rtw89_fbtc_h2c_set_gpio_mux_u { 3278 struct rtw89_fbtc_h2c_set_gpio_2b fmt; 3279 struct rtw89_fbtc_h2c_set_gpio_mux data; 3280 }; 3281 3282 union rtw89_fbtc_h2c_set_gpio_ext_pta_u { 3283 struct rtw89_fbtc_h2c_set_gpio_2b fmt; 3284 struct rtw89_fbtc_h2c_set_gpio_ext_pta data; 3285 }; 3286 3287 union rtw89_fbtc_h2c_set_gpio_ext_swin_u { 3288 struct rtw89_fbtc_h2c_set_gpio_4b fmt; 3289 struct rtw89_fbtc_h2c_set_gpio_ext_swin data; 3290 }; 3291 3292 struct rtw89_fbtc_h2c_set_gpio { 3293 union rtw89_fbtc_h2c_set_gpio_en_map_u en_map; 3294 union rtw89_fbtc_h2c_set_gpio_mux_u mux; 3295 union rtw89_fbtc_h2c_set_gpio_ext_pta_u ext_pta; 3296 union rtw89_fbtc_h2c_set_gpio_ext_pta_u ext_mb; 3297 union rtw89_fbtc_h2c_set_gpio_ext_pta_u ext_swout; 3298 union rtw89_fbtc_h2c_set_gpio_ext_swin_u ext_swin; 3299 }; 3300 3301 struct rtw89_btc_fbtc_mreg_val_v1 { 3302 u8 fver; /* btc_ver::fcxmreg */ 3303 u8 reg_num; 3304 __le16 rsvd; 3305 __le32 mreg_val[CXMREG_MAX]; 3306 } __packed; 3307 3308 struct rtw89_btc_fbtc_mreg_val_v2 { 3309 u8 fver; /* btc_ver::fcxmreg */ 3310 u8 reg_num; 3311 __le16 rsvd; 3312 __le32 mreg_val[CXMREG_MAX_V2]; 3313 } __packed; 3314 3315 struct rtw89_btc_fbtc_mreg_val_v7 { 3316 u8 fver; 3317 u8 reg_num; 3318 u8 rsvd0; 3319 u8 rsvd1; 3320 __le32 mreg_val[CXMREG_MAX_V2]; 3321 } __packed; 3322 3323 union rtw89_btc_fbtc_mreg_val { 3324 struct rtw89_btc_fbtc_mreg_val_v1 v1; 3325 struct rtw89_btc_fbtc_mreg_val_v2 v2; 3326 struct rtw89_btc_fbtc_mreg_val_v7 v7; 3327 }; 3328 3329 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 3330 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 3331 .offset = cpu_to_le32(__offset), } 3332 3333 struct rtw89_btc_fbtc_mreg { 3334 __le16 type; 3335 __le16 bytes; 3336 __le32 offset; 3337 } __packed; 3338 3339 struct rtw89_btc_fbtc_slot { 3340 __le16 dur; 3341 __le32 cxtbl; 3342 __le16 cxtype; 3343 } __packed; 3344 3345 struct rtw89_btc_fbtc_slots { 3346 u8 fver; /* btc_ver::fcxslots */ 3347 u8 tbl_num; 3348 __le16 rsvd; 3349 __le32 update_map; 3350 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 3351 } __packed; 3352 3353 struct rtw89_btc_fbtc_slot_v7 { 3354 __le16 dur; /* slot duration */ 3355 __le16 cxtype; 3356 __le32 cxtbl; 3357 } __packed; 3358 3359 struct rtw89_btc_fbtc_slots_v2 { 3360 u8 fver; /* btc_ver::fcxslots */ 3361 u8 tbl_num; 3362 __le16 rsvd; 3363 __le32 update_map; 3364 struct rtw89_btc_fbtc_slot_v7 slot[CXST_MAX]; 3365 } __packed; 3366 3367 struct rtw89_btc_fbtc_slot_u16 { 3368 __le16 dur; /* slot duration */ 3369 __le16 cxtype; 3370 __le16 cxtbl_l16; /* coex table [15:0] */ 3371 __le16 cxtbl_h16; /* coex table [31:16] */ 3372 } __packed; 3373 3374 struct rtw89_btc_fbtc_1slot_v7 { 3375 u8 fver; 3376 u8 sid; /* slot id */ 3377 __le16 rsvd; 3378 struct rtw89_btc_fbtc_slot_v7 slot; 3379 } __packed; 3380 3381 struct rtw89_btc_fbtc_slots_v7 { 3382 u8 fver; 3383 u8 slot_cnt; 3384 u8 rsvd0; 3385 u8 rsvd1; 3386 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 3387 __le32 update_map; 3388 } __packed; 3389 3390 union rtw89_btc_fbtc_slots_info { 3391 struct rtw89_btc_fbtc_slots v1; 3392 struct rtw89_btc_fbtc_slots_v2 v2; 3393 struct rtw89_btc_fbtc_slots_v7 v7; 3394 } __packed; 3395 3396 struct rtw89_btc_fbtc_step { 3397 u8 type; 3398 u8 val; 3399 __le16 difft; 3400 } __packed; 3401 3402 struct rtw89_btc_fbtc_steps_v2 { 3403 u8 fver; /* btc_ver::fcxstep */ 3404 u8 rsvd; 3405 __le16 cnt; 3406 __le16 pos_old; 3407 __le16 pos_new; 3408 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 3409 } __packed; 3410 3411 struct rtw89_btc_fbtc_steps_v3 { 3412 u8 fver; 3413 u8 en; 3414 __le16 rsvd; 3415 __le32 cnt; 3416 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 3417 } __packed; 3418 3419 union rtw89_btc_fbtc_steps_info { 3420 struct rtw89_btc_fbtc_steps_v2 v2; 3421 struct rtw89_btc_fbtc_steps_v3 v3; 3422 }; 3423 3424 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 3425 u8 fver; /* btc_ver::fcxcysta */ 3426 u8 rsvd; 3427 __le16 cycles; /* total cycle number */ 3428 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 3429 __le16 a2dpept; /* a2dp empty cnt */ 3430 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 3431 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 3432 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 3433 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 3434 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 3435 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 3436 __le16 tavg_a2dpept; /* avg a2dp empty time */ 3437 __le16 tmax_a2dpept; /* max a2dp empty time */ 3438 __le16 tavg_lk; /* avg leak-slot time */ 3439 __le16 tmax_lk; /* max leak-slot time */ 3440 __le32 slot_cnt[CXST_MAX]; /* slot count */ 3441 __le32 bcn_cnt[CXBCN_MAX]; 3442 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 3443 __le32 collision_cnt; /* counter for event/timer occur at same time */ 3444 __le32 skip_cnt; 3445 __le32 exception; 3446 __le32 except_cnt; 3447 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 3448 } __packed; 3449 3450 struct rtw89_btc_fbtc_fdd_try_info { 3451 __le16 cycles[CXT_FLCTRL_MAX]; 3452 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 3453 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 3454 } __packed; 3455 3456 struct rtw89_btc_fbtc_cycle_time_info { 3457 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 3458 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 3459 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 3460 } __packed; 3461 3462 struct rtw89_btc_fbtc_cycle_time_info_v5 { 3463 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 3464 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 3465 } __packed; 3466 3467 struct rtw89_btc_fbtc_a2dp_trx_stat { 3468 u8 empty_cnt; 3469 u8 retry_cnt; 3470 u8 tx_rate; 3471 u8 tx_cnt; 3472 u8 ack_cnt; 3473 u8 nack_cnt; 3474 u8 rsvd1; 3475 u8 rsvd2; 3476 } __packed; 3477 3478 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 3479 u8 empty_cnt; 3480 u8 retry_cnt; 3481 u8 tx_rate; 3482 u8 tx_cnt; 3483 u8 ack_cnt; 3484 u8 nack_cnt; 3485 u8 no_empty_cnt; 3486 u8 rsvd; 3487 } __packed; 3488 3489 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 3490 __le16 cnt; /* a2dp empty cnt */ 3491 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 3492 __le16 tavg; /* avg a2dp empty time */ 3493 __le16 tmax; /* max a2dp empty time */ 3494 } __packed; 3495 3496 struct rtw89_btc_fbtc_cycle_leak_info { 3497 __le32 cnt_rximr; /* the rximr occur at leak slot */ 3498 __le16 tavg; /* avg leak-slot time */ 3499 __le16 tmax; /* max leak-slot time */ 3500 } __packed; 3501 3502 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 3503 __le16 tavg; 3504 __le16 tamx; 3505 __le32 cnt_rximr; 3506 } __packed; 3507 3508 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 3509 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 3510 3511 struct rtw89_btc_fbtc_cycle_fddt_info { 3512 __le16 train_cycle; 3513 __le16 tp; 3514 3515 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 3516 s8 bt_tx_power; /* decrease Tx power (dB) */ 3517 s8 bt_rx_gain; /* LNA constrain level */ 3518 u8 no_empty_cnt; 3519 3520 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 3521 u8 cn; /* condition_num */ 3522 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 3523 u8 train_result; /* refer to enum btc_fddt_check_map */ 3524 } __packed; 3525 3526 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 3527 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 3528 3529 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 3530 __le16 train_cycle; 3531 __le16 tp; 3532 3533 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 3534 s8 bt_tx_power; /* decrease Tx power (dB) */ 3535 s8 bt_rx_gain; /* LNA constrain level */ 3536 u8 no_empty_cnt; 3537 3538 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 3539 u8 cn; /* condition_num */ 3540 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 3541 u8 train_result; /* refer to enum btc_fddt_check_map */ 3542 } __packed; 3543 3544 struct rtw89_btc_fbtc_fddt_cell_status { 3545 s8 wl_tx_pwr; 3546 s8 bt_tx_pwr; 3547 s8 bt_rx_gain; 3548 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 3549 } __packed; 3550 3551 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 3552 u8 fver; 3553 u8 rsvd; 3554 __le16 cycles; /* total cycle number */ 3555 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 3556 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 3557 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 3558 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3559 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3560 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 3561 __le32 slot_cnt[CXST_MAX]; /* slot count */ 3562 __le32 bcn_cnt[CXBCN_MAX]; 3563 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 3564 __le32 skip_cnt; 3565 __le32 except_cnt; 3566 __le32 except_map; 3567 } __packed; 3568 3569 #define FDD_TRAIN_WL_DIRECTION 2 3570 #define FDD_TRAIN_WL_RSSI_LEVEL 5 3571 #define FDD_TRAIN_BT_RSSI_LEVEL 5 3572 3573 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 3574 u8 fver; 3575 u8 rsvd; 3576 u8 collision_cnt; /* counter for event/timer occur at the same time */ 3577 u8 except_cnt; 3578 3579 __le16 skip_cnt; 3580 __le16 cycles; /* total cycle number */ 3581 3582 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 3583 __le16 slot_cnt[CXST_MAX]; /* slot count */ 3584 __le16 bcn_cnt[CXBCN_MAX]; 3585 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 3586 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 3587 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3588 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3589 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 3590 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 3591 [FDD_TRAIN_WL_RSSI_LEVEL] 3592 [FDD_TRAIN_BT_RSSI_LEVEL]; 3593 __le32 except_map; 3594 } __packed; 3595 3596 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 3597 u8 fver; 3598 u8 rsvd; 3599 u8 collision_cnt; /* counter for event/timer occur at the same time */ 3600 u8 except_cnt; 3601 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 3602 3603 __le16 skip_cnt; 3604 __le16 cycles; /* total cycle number */ 3605 3606 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 3607 __le16 slot_cnt[CXST_MAX]; /* slot count */ 3608 __le16 bcn_cnt[CXBCN_MAX]; 3609 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 3610 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 3611 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3612 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3613 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 3614 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 3615 [FDD_TRAIN_WL_RSSI_LEVEL] 3616 [FDD_TRAIN_BT_RSSI_LEVEL]; 3617 __le32 except_map; 3618 } __packed; 3619 3620 struct rtw89_btc_fbtc_cysta_v105 { 3621 u8 fver; 3622 u8 rsvd; 3623 u8 collision_cnt; 3624 u8 except_cnt; 3625 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 3626 3627 __le16 skip_cnt; 3628 __le16 cycles; 3629 3630 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 3631 __le16 slot_cnt[CXST_MAX]; 3632 __le16 bcn_cnt[CXBCN_MAX]; 3633 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 3634 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 3635 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3636 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3637 __le32 except_map; 3638 } __packed; 3639 3640 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 3641 u8 fver; 3642 u8 rsvd; 3643 u8 collision_cnt; /* counter for event/timer occur at the same time */ 3644 u8 except_cnt; 3645 3646 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 3647 3648 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 3649 3650 __le16 skip_cnt; 3651 __le16 cycles; /* total cycle number */ 3652 3653 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 3654 __le16 slot_cnt[CXST_MAX]; /* slot count */ 3655 __le16 bcn_cnt[CXBCN_MAX]; 3656 3657 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 3658 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 3659 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 3660 3661 __le32 except_map; 3662 } __packed; 3663 3664 union rtw89_btc_fbtc_cysta_info { 3665 struct rtw89_btc_fbtc_cysta_v2 v2; 3666 struct rtw89_btc_fbtc_cysta_v3 v3; 3667 struct rtw89_btc_fbtc_cysta_v4 v4; 3668 struct rtw89_btc_fbtc_cysta_v5 v5; 3669 struct rtw89_btc_fbtc_cysta_v105 v105; 3670 struct rtw89_btc_fbtc_cysta_v7 v7; 3671 }; 3672 3673 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 3674 u8 fver; /* btc_ver::fcxnullsta */ 3675 u8 rsvd; 3676 __le16 rsvd2; 3677 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 3678 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 3679 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 3680 } __packed; 3681 3682 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 3683 u8 fver; /* btc_ver::fcxnullsta */ 3684 u8 rsvd; 3685 __le16 rsvd2; 3686 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 3687 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 3688 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 3689 } __packed; 3690 3691 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 3692 u8 fver; 3693 u8 rsvd0; 3694 u8 rsvd1; 3695 u8 rsvd2; 3696 3697 __le32 tmax[2]; 3698 __le32 tavg[2]; 3699 __le32 result[2][5]; 3700 } __packed; 3701 3702 union rtw89_btc_fbtc_cynullsta_info { 3703 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 3704 struct rtw89_btc_fbtc_cynullsta_v2 v2; 3705 struct rtw89_btc_fbtc_cynullsta_v7 v7; 3706 }; 3707 3708 struct rtw89_btc_fbtc_btver_v1 { 3709 u8 fver; /* btc_ver::fcxbtver */ 3710 u8 rsvd; 3711 __le16 rsvd2; 3712 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 3713 __le32 fw_ver; 3714 __le32 feature; 3715 } __packed; 3716 3717 struct rtw89_btc_fbtc_btver_v7 { 3718 u8 fver; 3719 u8 rsvd0; 3720 u8 rsvd1; 3721 u8 rsvd2; 3722 3723 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 3724 __le32 fw_ver; 3725 __le32 feature; 3726 } __packed; 3727 3728 struct rtw89_btc_fbtc_btver_v8 { 3729 u8 fver; 3730 u8 bt_id; /* 0:BT0, 1:BT1 */ 3731 u8 rsvd1; 3732 u8 rsvd2; 3733 3734 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 3735 __le32 fw_ver; 3736 __le32 feature; 3737 } __packed; 3738 3739 union rtw89_btc_fbtc_btver { 3740 struct rtw89_btc_fbtc_btver_v1 v1; 3741 struct rtw89_btc_fbtc_btver_v7 v7; 3742 struct rtw89_btc_fbtc_btver_v8 v8; 3743 } __packed; 3744 3745 struct rtw89_btc_fbtc_btafh { 3746 u8 fver; /* btc_ver::fcxbtafh */ 3747 u8 rsvd; 3748 __le16 rsvd2; 3749 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 3750 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 3751 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 3752 } __packed; 3753 3754 struct rtw89_btc_fbtc_btafh_v2 { 3755 u8 fver; /* btc_ver::fcxbtafh */ 3756 u8 rsvd; 3757 u8 rsvd2; 3758 u8 map_type; 3759 u8 afh_l[4]; 3760 u8 afh_m[4]; 3761 u8 afh_h[4]; 3762 u8 afh_le_a[4]; 3763 u8 afh_le_b[4]; 3764 } __packed; 3765 3766 struct rtw89_btc_fbtc_btafh_v7 { 3767 u8 fver; 3768 u8 map_type; 3769 u8 rsvd0; 3770 u8 rsvd1; 3771 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 3772 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 3773 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 3774 u8 afh_le_a[4]; 3775 u8 afh_le_b[4]; 3776 } __packed; 3777 3778 struct rtw89_btc_fbtc_btafh_v8 { 3779 u8 fver; 3780 u8 map_type; 3781 u8 bt_id; /* 0:BT0, 1:BT1 */ 3782 u8 rsvd1; 3783 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 3784 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 3785 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 3786 u8 afh_le_a[4]; 3787 u8 afh_le_b[4]; 3788 } __packed; 3789 3790 struct rtw89_btc_fbtc_btdevinfo { 3791 u8 fver; /* btc_ver::fcxbtdevinfo */ 3792 u8 rsvd; 3793 __le16 vendor_id; 3794 __le32 dev_name; /* only 24 bits valid */ 3795 __le32 flush_time; 3796 } __packed; 3797 3798 struct rtw89_btc_trx_info { 3799 u8 tx_lvl; 3800 u8 rx_lvl; 3801 u8 wl_rssi; 3802 u8 bt_rssi; 3803 3804 s8 wl_tx_power[RTW89_PHY_NUM]; /* absolute Tx power (dBm), 0xff-> no BTC control */ 3805 s8 wl_rx_gain[RTW89_PHY_NUM]; /* rx gain table index (TBD.) */ 3806 s8 bt_tx_power[BTC_ALL_BT]; /* decrease Tx power (dB) */ 3807 s8 bt_rx_gain[BTC_ALL_BT]; /* LNA constrain level */ 3808 s8 zb_tx_power[BTC_ALL_BT]; 3809 s8 zb_rx_gain[BTC_ALL_BT]; 3810 3811 u8 cn; /* condition_num */ 3812 s8 nhm; 3813 u8 bt_profile; 3814 u8 rsvd2; 3815 3816 u16 tx_rate; 3817 u16 rx_rate; 3818 3819 u32 tx_tp; 3820 u32 rx_tp; 3821 u32 rx_err_ratio; 3822 }; 3823 3824 enum btc_rf_path { 3825 BTC_RF_S0 = 0, 3826 BTC_RF_S1 = 1, 3827 BTC_RF_NUM, 3828 }; 3829 3830 struct rtw89_btc_fbtc_outsrc_set_info_v1 { 3831 u8 rf_band[BTC_RF_NUM]; 3832 u8 btg_rx[BTC_RF_NUM]; 3833 u8 nbtg_tx[BTC_RF_NUM]; 3834 3835 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; 3836 struct rtw89_mac_ax_wl_act wlact_set[BTC_ALL_BT]; 3837 3838 u8 pta_req_hw_band; 3839 u8 rf_gbt_source; 3840 u8 bt_enable_state; 3841 u8 wl_btg_standby_chg; 3842 3843 u8 fbd_group_en[RTW89_MAC_NUM][2]; 3844 __le16 rf_center_freq[RTW89_MAC_NUM]; 3845 __le16 fbd_group_bound[RTW89_MAC_NUM][2]; 3846 __le16 freq_diff_thres[RTW89_MAC_NUM][BTC_ALL_BT]; 3847 } __packed; 3848 3849 struct rtw89_btc_fbtc_outsrc_set_info_v6 { 3850 u8 rf_band[BTC_RF_NUM]; 3851 u8 btg_rx[BTC_RF_NUM]; 3852 u8 nbtg_tx[BTC_RF_NUM]; 3853 3854 struct rtw89_btc_gnt_ctrl gnt_set[RTW89_MAC_AX_COEX_GNT_NR]; 3855 struct rtw89_mac_ax_wl_act wlact_set[BTC_ALL_BT_EZL]; 3856 3857 u8 pta_req_hw_band; 3858 u8 rf_gbt_source; 3859 u8 bt_enable_state; 3860 u8 bt_plut_type; 3861 u8 wl_tx_limit_en; 3862 u8 fc_exec; 3863 u8 wl_btg_standby_chg; 3864 u8 rsvd; 3865 u8 bb_path_sel_bt[BTC_RF_NUM]; 3866 u8 bb_phy_sel_bt[RTW89_PHY_NUM]; 3867 u8 fbd_group_en[RTW89_MAC_NUM][2]; 3868 __le16 rf_center_freq[RTW89_MAC_NUM]; 3869 __le16 freq_diff_thres[RTW89_MAC_NUM][BTC_ALL_BT_EZL]; 3870 __le16 fbd_group_bound[RTW89_MAC_NUM][2]; 3871 __le32 wl_tx_limit_time; 3872 } __packed; 3873 3874 struct rtw89_btc_fbtc_outsrc_set_info { 3875 u8 rf_band[BTC_RF_NUM]; /* 0:2GHz/1:5GHz for MPI_bb_hwsi_ignore_gnt_wl() */ 3876 u8 btg_rx[BTC_RF_NUM]; /* for MPI_bb_btg_bt_rx() */ 3877 u8 nbtg_tx[BTC_RF_NUM]; /* for MPI_bb_nbtg_bt_tx pre=AGC control */ 3878 3879 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */ 3880 struct rtw89_btc_gnt_ctrl gnt_set_be[RTW89_MAC_AX_COEX_GNT_NR]; 3881 struct rtw89_mac_ax_wl_act wlact_set[BTC_ALL_BT_EZL]; 3882 3883 u8 pta_req_hw_band; /* Bind PTA to HWB0 or HWB1, only for 8922a 1-PTA */ 3884 u8 rf_gbt_source; /* gbt from S0 or S1 for RF 0x2[9], only for 8922a */ 3885 3886 /* The followngs are for 8922c/d new Multi-PTA design */ 3887 /* 0:BT0/1:BT1/2:ZB on/off for MAC(0xe580[0]/0xe680[0])/ RF 0x4[3:2] */ 3888 u8 bt_enable_state; 3889 u8 bt_plut_type; /* BT polluted type, refer to enum btc_plt_map */ 3890 3891 u8 wl_tx_limit_en; 3892 u8 fc_exec; 3893 u8 wl_btg_standby_chg; /* keep RX-IQGen on in standby mode */ 3894 u8 rsvd; 3895 3896 u8 bb_path_sel_bt[BTC_RF_NUM]; /* bb s0(1) select GNT_BT0 or BT1 */ 3897 u8 bb_phy_sel_bt[RTW89_PHY_NUM]; /* bb phy0(1) select GNT_BT0 or BT1 */ 3898 3899 /* forbidden group-> bit[1]:fbd rf-band, bit[0]: fbd enable */ 3900 u8 fbd_group_en[RTW89_MAC_NUM][2]; /* HWB0/1 +.Group0/1 */ 3901 3902 /* bit[15]-> 0:2G/1:5G,6G, bit[14:0]-> WL HWBx ch freq in MHz */ 3903 u16 rf_center_freq[RTW89_MAC_NUM]; /* HWB0/1 */ 3904 3905 /* 11-bit in MHz, freq diff threshold */ 3906 u16 freq_diff_thres[RTW89_MAC_NUM][BTC_ALL_BT_EZL]; /* HWB0/1 vs.BT0/1/2 */ 3907 3908 /* forbidden group boundary: [15:8]->UP, [7:0]->LO */ 3909 u16 fbd_group_bound[RTW89_MAC_NUM][2]; /* HWB0/1 +.Group0/1 */ 3910 3911 u32 wl_tx_limit_time; 3912 }; 3913 3914 union rtw89_btc_fbtc_slot_u { 3915 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 3916 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 3917 }; 3918 3919 struct rtw89_btc_fddr_cell { 3920 u8 en; 3921 u8 wl_rx_max; 3922 u8 wl_rx_min; 3923 }; 3924 3925 struct rtw89_btc_fddr_result { 3926 u8 wl_rx_limit; 3927 u8 wl_rx_limit_step[6]; /* record search process */ 3928 u8 search_cnt; /* the rx-limit serach count */ 3929 u32 wl_tp; 3930 u32 wl_tp_step[6]; /* record search process */ 3931 }; 3932 3933 struct rtw89_btc_fddr_train_info { 3934 u8 rx_limit_pre; 3935 u8 rx_limit_now; 3936 3937 u32 tp_rec_cnt; 3938 u32 tp_avg_cnt; 3939 3940 u32 wl_tp_pre; 3941 u32 wl_tp_now; 3942 }; 3943 3944 struct rtw89_btc_fddr_info { 3945 u8 state; /* refer to enum btc_fddr_state */ 3946 u8 cell_now; /* wl rssi_level after filter LNA != 6 */ 3947 u8 cell_change; 3948 u8 wl_low_rate; 3949 3950 u8 tp_setup_time; /* calculate TP after this value (in second) */ 3951 u8 tp_hold_time; /* TP calculation period (in second) */ 3952 u8 wl_rssi_thres[BTC_WL_RSSI_THMAX]; /* index 0 -> Max RSSI */ 3953 3954 u8 search_mode; /* 0: search, 1:look-up */ 3955 u8 search_dir; /* 0: Max->Min, 1:Min->Max */ 3956 3957 struct rtw89_btc_fddr_train_info tctrl; /* train flag */ 3958 struct rtw89_btc_fddr_result cell_result[BTC_WL_RSSI_THMAX + 1]; 3959 struct rtw89_btc_fddr_cell cell[BTC_WL_RSSI_THMAX + 1]; /* parameters */ 3960 3961 u16 wl_rx_rate_thres; /* switch to TDD if rx_rate < this threshold */ 3962 3963 u32 nrsn_map; /* the reason map for no-run fdd-traing */ 3964 u32 wl_rx_rate_now; 3965 }; 3966 3967 struct rtw89_btc_rpt_ctrl_a2dp_empty { 3968 u32 cnt_empty; /* a2dp empty count */ 3969 u32 cnt_flowctrl; /* a2dp empty flow control counter */ 3970 u32 cnt_tx; 3971 u32 cnt_ack; 3972 u32 cnt_nack; 3973 }; 3974 3975 struct rtw89_btc_fddt_bt_stat { 3976 struct rtw89_btc_rpt_ctrl_a2dp_empty a2dp_last; 3977 u32 retry_last; 3978 }; 3979 3980 struct rtw89_btc_fddt_cell { 3981 s8 wl_pwr_min; 3982 s8 wl_pwr_max; 3983 s8 bt_pwr_dec_max; 3984 s8 bt_rx_gain; 3985 }; 3986 3987 struct rtw89_btc_fddt_fail_check { /* for cell stay in training */ 3988 u8 check_map; /* check pass condition if bit-map = 1 */ 3989 u8 bt_no_empty_cnt; /* 0-fail if no bt-empty >= th in train_cycle */ 3990 u8 wl_tp_ratio; /* 1-fail if wl tp rise ratio < th */ 3991 u8 wl_kpibtr_ratio; /* 2-fail if phase_now_tp < phase_last_tp * kpibtr_ratio */ 3992 }; 3993 3994 struct rtw89_btc_fddt_break_check { /* for cell stay in training or train-ok */ 3995 u8 check_map; /* check break condition if bit-map = 1 */ 3996 u8 bt_no_empty_cnt; /* 0-break if no empty count >= th */ 3997 u8 wl_tp_ratio; /* 1-break if wl tp ratio < th (%) */ 3998 u8 wl_tp_low_bound; /* 2-break if wl tp (in Mbps) < th */ 3999 4000 u8 cn; /* 3-break if (cn >= cn_limit) >= th cycle */ 4001 u8 cell_chg; /* 4-break if non-matched-RSSI >= th cycle */ 4002 s8 nhm_limit; /* 5-break if nhm >= th --> ill-condition */ 4003 u8 cn_limit; /* if condition number >= th --> ill-condition */ 4004 }; 4005 4006 struct rtw89_btc_fddt_time_ctrl { 4007 /* 1 TDD cycle = w1 + b1, FDD 1cycle = w1fdd-slot + b1fdd-slot */ 4008 u8 m_cycle; /* KPI Moving-Average-Cycle: 1~32 cycles */ 4009 u8 w_cycle; /* Start to calcul WKPI after this if train-phase change */ 4010 u8 k_cycle; /* Total kpi-estimate cycles for each training-step */ 4011 u8 rsvd; 4012 }; 4013 4014 struct rtw89_btc_fddt_train_info { 4015 struct rtw89_btc_fddt_time_ctrl t_ctrl; 4016 struct rtw89_btc_fddt_break_check b_chk; 4017 struct rtw89_btc_fddt_fail_check f_chk; 4018 struct rtw89_btc_fddt_cell cell_ul[5][5]; 4019 struct rtw89_btc_fddt_cell cell_dl[5][5]; 4020 }; 4021 4022 struct rtw89_btc_fddt_info { 4023 u8 type; /* refer to enum btc_fddt_type */ 4024 u8 result; /* fw send fdd-training status by c2h */ 4025 u8 state; /* refer to enum btc_fddt_state */ 4026 4027 u8 wl_iot[6]; /* wl bssid */ 4028 u16 bt_iot; /* bt vendor-id */ 4029 4030 u32 nrsn_map; /* the reason map for no-run fdd-traing */ 4031 struct rtw89_btc_fddt_bt_stat bt_stat; /* bt statistics */ 4032 struct rtw89_btc_fddt_train_info train; 4033 struct rtw89_btc_fddt_train_info train_now; 4034 }; 4035 4036 struct rtw89_btc_dm { 4037 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */ 4038 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */ 4039 union rtw89_btc_fbtc_slot_u slot; 4040 union rtw89_btc_fbtc_slot_u slot_now; 4041 struct rtw89_btc_fbtc_tdma tdma; 4042 struct rtw89_btc_fbtc_tdma tdma_now; 4043 struct rtw89_btc_gnt_ctrl gnt_set[RTW89_MAC_AX_COEX_GNT_NR]; 4044 struct rtw89_btc_gnt_ctrl gnt_val[RTW89_MAC_AX_COEX_GNT_NR]; 4045 struct rtw89_mac_ax_wl_act wlact_set[BTC_ALL_BT_EZL]; 4046 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 4047 struct rtw89_btc_rf_trx_para_v9 rf_trx_para; 4048 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 4049 struct rtw89_btc_dm_step dm_step; 4050 struct rtw89_btc_eslot_ctrl eslot_ctrl; 4051 struct rtw89_btc_trx_info trx_info; 4052 union rtw89_btc_dm_error_map error; 4053 struct rtw89_btc_bind_info tdd_bind; 4054 struct rtw89_btc_bind_info fdd_bind; 4055 struct rtw89_btc_fddt_info fddt_info; 4056 struct rtw89_btc_fddr_info fddr_info; 4057 struct rtw89_btc_wl_trx_nss_para wl_trx_nss; 4058 u32 cnt_dm[BTC_DCNT_NUM]; 4059 u32 cnt_notify[BTC_NCNT_NUM]; 4060 u8 ant_xmap[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT ANT interact-map */ 4061 u8 xtk_xmap[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* 1: If RSSI<(BT-Pin -SIR) */ 4062 u8 sit_xmap[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT space interact-map */ 4063 u8 fit_xmap[RTW89_PHY_NUM][BTC_ALL_BT_EZL]; /* HWB-BT freq interact-map */ 4064 u8 tdd_map[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT tdd-map */ 4065 u8 fdd_map[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT fdd-map */ 4066 u8 corx_map[BTC_RF_NUM][BTC_ALL_BT_EZL]; /* WL-BT Co-Rx */ 4067 4068 u8 sit_xmap_last[BTC_RF_NUM][BTC_ALL_BT_EZL]; 4069 u8 fit_xmap_last[RTW89_PHY_NUM][BTC_ALL_BT_EZL]; 4070 4071 u8 tdd_rssi_thres; /* The FDD/TDD switch RSSI (in %) */ 4072 u8 sir_thres; /* WL(Signal) to BT(interference Pin) ratio */ 4073 u8 sir_state[BTC_ALL_BT_EZL]; /* 1: WL RSSI > BTx-interference */ 4074 4075 u32 update_slot_map; 4076 u32 set_ant_path; 4077 u32 e2g_slot_limit; 4078 u32 e2g_slot_nulltx_time; 4079 4080 u32 wl_only: 1; 4081 u32 wl_fw_cx_offload: 1; 4082 u32 freerun: 1; 4083 u32 fddt_train: 1; 4084 u32 wl_ps_ctrl: 2; 4085 u32 wl_mimo_ps: 1; 4086 u32 leak_ap: 1; 4087 u32 noisy_level: 3; 4088 u32 coex_info_map: 8; 4089 u32 bt_only: 1; 4090 u32 wl_btg_rx: 2; 4091 u32 trx_para_level: 8; 4092 u32 wl_stb_chg: 1; 4093 u32 pta_owner: 1; 4094 4095 u32 tdma_instant_excute: 1; 4096 u32 wl_btg_rx_rb: 2; 4097 4098 u16 slot_dur[CXST_MAX]; 4099 u16 bt_slot_flood; 4100 4101 u8 run_reason; 4102 u8 run_action; 4103 u8 wl_tx_pwr_phy_map; 4104 u8 vid; 4105 u8 client_ps_tdma_on; 4106 u8 wl_trx_nss_en; 4107 4108 u8 wl_pre_agc: 2; 4109 u8 wl_lna2: 1; 4110 u8 freerun_chk: 1; 4111 u8 wl_pre_agc_rb: 2; 4112 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 4113 4114 u8 slot_req_more: 1; 4115 u8 out_of_band: 1; 4116 u8 fdd_en: 1; 4117 u8 tdd_en: 1; 4118 u8 lps_ctrl_scbd: 1; 4119 u8 lps_ctrl_change: 1; 4120 u8 bis_tdma: 1; /* BIS TDMA mode active */ 4121 u8 scbd_write_instant; 4122 bool scbd_b2w_update; 4123 bool scbd_w2b_update; 4124 bool pre_agc_chg; 4125 }; 4126 4127 struct rtw89_fbtc_wl_ctrl_info { 4128 u8 rf_band_map[RTW89_MAC_NUM]; 4129 u8 rf_ch[RTW89_MAC_NUM]; 4130 4131 u8 client_pstdma_on; 4132 u8 fw_scan; 4133 u8 rfk_state; 4134 u8 rfk_type; 4135 4136 u32 smap_val; 4137 }; 4138 4139 struct rtw89_btc_ctrl { 4140 u32 manual; 4141 u32 igno_bt: 1; 4142 u32 always_freerun: 1; 4143 u32 trace_step: 16; 4144 4145 u8 wl_only; 4146 u8 bt_only; 4147 4148 u8 ntfy_type; 4149 struct rtw89_fbtc_wl_ctrl_info wl_ctrl_info; 4150 }; 4151 4152 struct rtw89_btc_ctrl_v0 { 4153 u32 manual: 1; 4154 u32 igno_bt: 1; 4155 u32 always_freerun: 1; 4156 u32 trace_step: 16; 4157 u32 rsvd: 12; 4158 } __packed; 4159 4160 struct rtw89_btc_ctrl_v7 { 4161 u8 manual; 4162 u8 igno_bt; 4163 u8 always_freerun; 4164 u8 rsvd; 4165 } __packed; 4166 4167 struct rtw89_fbtc_wl_ctrl_info_v9 { 4168 u8 rf_band_map[RTW89_MAC_NUM]; 4169 u8 rf_ch[RTW89_MAC_NUM]; 4170 4171 u8 client_pstdma_on; 4172 u8 fw_scan; 4173 u8 rfk_state; 4174 u8 rfk_type; 4175 4176 __le32 smap_val; 4177 } __packed; 4178 4179 struct rtw89_btc_ctrl_v9 { 4180 u8 manual; 4181 u8 always_freerun; 4182 u8 wl_only; 4183 u8 bt_only; 4184 4185 u8 ntfy_type; 4186 u8 rsvd0; 4187 u8 rsvd1; 4188 u8 rsvd2; 4189 4190 struct rtw89_fbtc_wl_ctrl_info_v9 wl_ctrl_info; 4191 } __packed; 4192 4193 struct rtw89_btc_dbg { 4194 /* cmd "rb" */ 4195 bool rb_done; 4196 u32 rb_val; 4197 }; 4198 4199 enum rtw89_btc_btf_fw_event { 4200 BTF_EVNT_RPT = 0, 4201 BTF_EVNT_BT_INFO = 1, 4202 BTF_EVNT_BT_SCBD = 2, 4203 BTF_EVNT_BT_REG = 3, 4204 BTF_EVNT_CX_RUNINFO = 4, 4205 BTF_EVNT_BT_PSD = 5, 4206 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 4207 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 4208 BTF_EVNT_BUF_OVERFLOW, 4209 BTF_EVNT_C2H_LOOPBACK, 4210 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */ 4211 BTF_EVNT_ZB_INFO = 11, 4212 BTF_EVNT_ZB_CH = 12, 4213 BTF_EVNT_ZB_QUERY_TXPWR = 13, 4214 BTF_EVNT_MAX, 4215 }; 4216 4217 enum btf_fw_event_report { 4218 BTC_RPT_TYPE_CTRL = 0x0, 4219 BTC_RPT_TYPE_TDMA, 4220 BTC_RPT_TYPE_SLOT, 4221 BTC_RPT_TYPE_CYSTA, 4222 BTC_RPT_TYPE_STEP, 4223 BTC_RPT_TYPE_NULLSTA, 4224 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 4225 BTC_RPT_TYPE_MREG, 4226 BTC_RPT_TYPE_GPIO_DBG, 4227 BTC_RPT_TYPE_BT_VER, 4228 BTC_RPT_TYPE_BT_SCAN, 4229 BTC_RPT_TYPE_BT_AFH, 4230 BTC_RPT_TYPE_BT_DEVICE, 4231 BTC_RPT_TYPE_TEST, 4232 BTC_RPT_TYPE_MAX = 31, 4233 4234 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 4235 __BTC_RPT_TYPE_V0_MAX = 12, 4236 }; 4237 4238 enum rtw_btc_btf_reg_type { 4239 REG_MAC = 0x0, 4240 REG_BB = 0x1, 4241 REG_RF = 0x2, 4242 REG_BT_RF = 0x3, 4243 REG_BT_MODEM = 0x4, 4244 REG_BT_BLUEWIZE = 0x5, 4245 REG_BT_VENDOR = 0x6, 4246 REG_BT_LE = 0x7, 4247 REG_MAX_TYPE, 4248 }; 4249 4250 struct rtw89_btc_rpt_cmn_info { 4251 u32 rx_cnt; 4252 u32 rx_len; 4253 u32 req_len; /* expected rsp len */ 4254 u8 req_fver; /* expected rsp fver */ 4255 u8 rsp_fver; /* fver from fw */ 4256 u8 valid; 4257 } __packed; 4258 4259 union rtw89_btc_fbtc_btafh_info { 4260 struct rtw89_btc_fbtc_btafh v1; 4261 struct rtw89_btc_fbtc_btafh_v2 v2; 4262 struct rtw89_btc_fbtc_btafh_v7 v7; 4263 struct rtw89_btc_fbtc_btafh_v8 v8; 4264 }; 4265 4266 struct rtw89_btc_report_ctrl_state { 4267 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4268 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 4269 }; 4270 4271 struct rtw89_btc_rpt_fbtc_tdma { 4272 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4273 union rtw89_btc_fbtc_tdma_le32 finfo; 4274 }; 4275 4276 struct rtw89_btc_rpt_fbtc_slots { 4277 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4278 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 4279 }; 4280 4281 struct rtw89_btc_rpt_fbtc_cysta { 4282 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4283 union rtw89_btc_fbtc_cysta_info finfo; 4284 }; 4285 4286 struct rtw89_btc_rpt_fbtc_step { 4287 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4288 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 4289 }; 4290 4291 struct rtw89_btc_rpt_fbtc_nullsta { 4292 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4293 union rtw89_btc_fbtc_cynullsta_info finfo; 4294 }; 4295 4296 struct rtw89_btc_rpt_fbtc_mreg { 4297 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4298 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 4299 }; 4300 4301 struct rtw89_btc_rpt_fbtc_gpio_dbg { 4302 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4303 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 4304 }; 4305 4306 struct rtw89_btc_rpt_fbtc_btver { 4307 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4308 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 4309 }; 4310 4311 struct rtw89_btc_rpt_fbtc_btscan { 4312 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4313 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 4314 }; 4315 4316 struct rtw89_btc_rpt_fbtc_btafh { 4317 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4318 union rtw89_btc_fbtc_btafh_info finfo; 4319 }; 4320 4321 struct rtw89_btc_rpt_fbtc_btdev { 4322 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 4323 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 4324 }; 4325 4326 enum rtw89_btc_btfre_type { 4327 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 4328 BTFRE_UNDEF_TYPE, 4329 BTFRE_EXCEPTION, 4330 BTFRE_MAX, 4331 }; 4332 4333 struct rtw89_btc_ver { 4334 enum rtw89_core_chip_id chip_id; 4335 u32 fw_ver_code; 4336 4337 u8 fcxbtcrpt; 4338 u8 fcxtdma; 4339 u8 fcxslots; 4340 u8 fcxcysta; 4341 u8 fcxstep; 4342 u8 fcxnullsta; 4343 u8 fcxmreg; 4344 u8 fcxgpiodbg; 4345 u8 fcxbtver; 4346 u8 fcxbtscan; 4347 u8 fcxbtafh; 4348 u8 fcxbtdevinfo; 4349 u8 fwlrole; 4350 u8 frptmap; 4351 u8 fcxctrl; 4352 u8 fcxinit; 4353 4354 u8 fwevntrptl; 4355 u8 fwc2hfunc; 4356 u8 drvinfo_ver; 4357 u16 info_buf; 4358 u8 max_role_num; 4359 u8 fcxosi; 4360 u8 fcxmlo; 4361 u8 bt_desired; 4362 u8 fcxtrx; 4363 }; 4364 4365 struct rtw89_btc_btf_fwinfo { 4366 u32 cnt_c2h; 4367 u32 cnt_h2c; 4368 u32 cnt_h2c_fail; 4369 u32 event[BTF_EVNT_MAX]; 4370 4371 u32 err[BTFRE_MAX]; 4372 u32 len_mismch; 4373 u32 fver_mismch; 4374 u32 rpt_en_map; 4375 4376 struct rtw89_btc_ver fw_subver; 4377 struct rtw89_btc_report_ctrl_state rpt_ctrl; 4378 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 4379 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 4380 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 4381 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 4382 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 4383 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 4384 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 4385 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 4386 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 4387 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 4388 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 4389 }; 4390 4391 #define RTW89_BTC_POLICY_MAXLEN 512 4392 #define BTC_H2C_MAXLENC 2020 4393 4394 struct rtw89_btc { 4395 const struct rtw89_btc_ver *ver; 4396 4397 struct rtw89_btc_cx cx; 4398 struct rtw89_btc_dm dm; 4399 struct rtw89_btc_ctrl ctrl; 4400 struct rtw89_btc_module mdinfo; 4401 struct rtw89_btc_btf_fwinfo fwinfo; 4402 struct rtw89_btc_dbg dbg; 4403 struct rtw89_fbtc_h2c_set_gpio gpio; 4404 4405 struct wiphy_work eapol_notify_work; 4406 struct wiphy_work arp_notify_work; 4407 struct wiphy_work dhcp_notify_work; 4408 struct wiphy_work icmp_notify_work; 4409 4410 u32 bt_req_len[RTW89_PHY_NUM]; 4411 4412 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 4413 u8 hbuf[BTC_H2C_MAXLENC]; /* H2C Macro buffer */ 4414 u8 hbuf_cnt; /* H2C cmd count in buffer */ 4415 u8 ant_type; 4416 u8 btg_pos; 4417 u8 io_oflld_type; 4418 u16 policy_len; 4419 u16 policy_type; 4420 u16 hbuf_len; /* H2C used length, it sshould be <= BTC_H2C_MAXLEN */ 4421 u32 hubmsg_cnt; 4422 bool bt_req_en; 4423 bool update_policy_force; 4424 bool btc_ctrl_lps; 4425 bool manual_ctrl; 4426 bool cli_h2c_cmd; 4427 }; 4428 4429 enum rtw89_btc_hmsg { 4430 RTW89_BTC_HMSG_TMR_EN = 0x0, 4431 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 4432 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 4433 RTW89_BTC_HMSG_FW_EV = 0x3, 4434 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 4435 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 4436 4437 NUM_OF_RTW89_BTC_HMSG, 4438 }; 4439 4440 enum rtw89_ra_mode { 4441 RTW89_RA_MODE_CCK = BIT(0), 4442 RTW89_RA_MODE_OFDM = BIT(1), 4443 RTW89_RA_MODE_HT = BIT(2), 4444 RTW89_RA_MODE_VHT = BIT(3), 4445 RTW89_RA_MODE_HE = BIT(4), 4446 RTW89_RA_MODE_EHT = BIT(5), 4447 }; 4448 4449 enum rtw89_ra_report_mode { 4450 RTW89_RA_RPT_MODE_LEGACY, 4451 RTW89_RA_RPT_MODE_HT, 4452 RTW89_RA_RPT_MODE_VHT, 4453 RTW89_RA_RPT_MODE_HE, 4454 RTW89_RA_RPT_MODE_EHT, 4455 }; 4456 4457 enum rtw89_dig_noisy_level { 4458 RTW89_DIG_NOISY_LEVEL0 = -1, 4459 RTW89_DIG_NOISY_LEVEL1 = 0, 4460 RTW89_DIG_NOISY_LEVEL2 = 1, 4461 RTW89_DIG_NOISY_LEVEL3 = 2, 4462 RTW89_DIG_NOISY_LEVEL_MAX = 3, 4463 }; 4464 4465 enum rtw89_gi_ltf { 4466 RTW89_GILTF_LGI_4XHE32 = 0, 4467 RTW89_GILTF_SGI_4XHE08 = 1, 4468 RTW89_GILTF_2XHE16 = 2, 4469 RTW89_GILTF_2XHE08 = 3, 4470 RTW89_GILTF_1XHE16 = 4, 4471 RTW89_GILTF_1XHE08 = 5, 4472 RTW89_GILTF_MAX 4473 }; 4474 4475 enum rtw89_rx_frame_type { 4476 RTW89_RX_TYPE_MGNT = 0, 4477 RTW89_RX_TYPE_CTRL = 1, 4478 RTW89_RX_TYPE_DATA = 2, 4479 RTW89_RX_TYPE_RSVD = 3, 4480 }; 4481 4482 enum rtw89_efuse_block { 4483 RTW89_EFUSE_BLOCK_SYS = 0, 4484 RTW89_EFUSE_BLOCK_RF = 1, 4485 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 4486 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 4487 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 4488 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 4489 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 4490 RTW89_EFUSE_BLOCK_ADIE = 7, 4491 4492 RTW89_EFUSE_BLOCK_NUM, 4493 RTW89_EFUSE_BLOCK_IGNORE, 4494 }; 4495 4496 struct rtw89_ra_info { 4497 u8 is_dis_ra:1; 4498 /* Bit0 : CCK 4499 * Bit1 : OFDM 4500 * Bit2 : HT 4501 * Bit3 : VHT 4502 * Bit4 : HE 4503 * Bit5 : EHT 4504 */ 4505 u8 mode_ctrl:6; 4506 u8 bw_cap:3; /* enum rtw89_bandwidth */ 4507 u8 macid; 4508 u8 dcm_cap:1; 4509 u8 er_cap:1; 4510 u8 init_rate_lv:2; 4511 u8 upd_all:1; 4512 u8 en_sgi:1; 4513 u8 ldpc_cap:1; 4514 u8 stbc_cap:1; 4515 u8 ss_num:3; 4516 u8 giltf:3; 4517 u8 upd_bw_nss_mask:1; 4518 u8 upd_mask:1; 4519 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 4520 /* BFee CSI */ 4521 u8 band_num; 4522 u8 ra_csi_rate_en:1; 4523 u8 fixed_csi_rate_en:1; 4524 u8 cr_tbl_sel:1; 4525 u8 fix_giltf_en:1; 4526 u8 fix_giltf:3; 4527 u8 partial_bw_er:1; 4528 u8 csi_mcs_ss_idx; 4529 u8 csi_mode:2; 4530 u8 csi_gi_ltf:3; 4531 u8 csi_bw:3; 4532 /* after v1 */ 4533 u8 is_noisy:1; 4534 u8 psra_en:1; 4535 u8 rsvd0:1; 4536 u8 macid_msb:2; 4537 u8 band:2; /* enum rtw89_band */ 4538 u8 is_new_dbgreg:1; 4539 }; 4540 4541 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 4542 #define RTW89_PPDU_MAC_INFO_SIZE 8 4543 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 4544 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 4545 4546 struct rtw89_ampdu_params { 4547 u16 agg_num; 4548 bool amsdu; 4549 }; 4550 4551 struct rtw89_ra_report { 4552 struct rate_info txrate; 4553 u32 bit_rate; 4554 u16 hw_rate; 4555 u8 retry_ratio; 4556 bool might_fallback_legacy; 4557 }; 4558 4559 DECLARE_EWMA(rssi, 10, 16); 4560 DECLARE_EWMA(evm, 10, 16); 4561 DECLARE_EWMA(snr, 10, 16); 4562 4563 struct rtw89_ba_cam_entry { 4564 struct list_head list; 4565 u8 tid; 4566 }; 4567 4568 #define RTW89_MAX_ADDR_CAM_NUM 128 4569 #define RTW89_MAX_BSSID_CAM_NUM 20 4570 #define RTW89_MAX_SEC_CAM_NUM 128 4571 #define RTW89_MAX_BA_CAM_NUM 24 4572 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 4573 4574 struct rtw89_addr_cam_entry { 4575 u8 addr_cam_idx; 4576 u8 offset; 4577 u8 len; 4578 u8 valid : 1; 4579 u8 addr_mask : 6; 4580 u8 wapi : 1; 4581 u8 mask_sel : 2; 4582 u8 bssid_cam_idx: 6; 4583 4584 u8 sec_ent_mode; 4585 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 4586 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 4587 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 4588 }; 4589 4590 struct rtw89_bssid_cam_entry { 4591 u8 bssid[ETH_ALEN]; 4592 u8 phy_idx; 4593 u8 bssid_cam_idx; 4594 u8 offset; 4595 u8 len; 4596 u8 valid : 1; 4597 u8 num; 4598 }; 4599 4600 struct rtw89_sec_cam_entry { 4601 u8 sec_cam_idx; 4602 u8 offset; 4603 u8 len; 4604 u8 type : 4; 4605 u8 ext_key : 1; 4606 u8 spp_mode : 1; 4607 /* 256 bits */ 4608 u8 key[32]; 4609 4610 struct ieee80211_key_conf *key_conf; 4611 }; 4612 4613 struct rtw89_sta_link { 4614 struct rtw89_sta *rtwsta; 4615 struct list_head dlink_schd; 4616 unsigned int link_id; 4617 4618 u8 mac_id; 4619 u8 tx_retry; 4620 bool er_cap; 4621 struct rtw89_vif_link *rtwvif_link; 4622 struct rtw89_ra_info ra; 4623 struct rtw89_ra_report ra_report; 4624 int max_agg_wait; 4625 u8 prev_rssi; 4626 struct ewma_rssi avg_rssi; 4627 struct ewma_rssi rssi[RF_PATH_MAX]; 4628 struct ewma_snr avg_snr; 4629 struct ewma_evm evm_1ss; 4630 struct ewma_evm evm_min[RF_PATH_MAX]; 4631 struct ewma_evm evm_max[RF_PATH_MAX]; 4632 struct ieee80211_rx_status rx_status; 4633 u16 rx_hw_rate; 4634 __le32 htc_template; 4635 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 4636 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 4637 struct list_head ba_cam_list; 4638 4639 bool use_cfg_mask; 4640 struct cfg80211_bitrate_mask mask; 4641 4642 bool cctl_tx_time; 4643 u32 ampdu_max_time:4; 4644 bool cctl_tx_retry_limit; 4645 u32 data_tx_cnt_lmt:6; 4646 }; 4647 4648 #define RTW89_EFUSE_SN_LEN 5 4649 #define RTW89_EFUSE_UUID_LEN 16 4650 4651 struct rtw89_efuse { 4652 bool valid; 4653 bool power_k_valid; 4654 bool vcore_valid; 4655 bool dswr_valid; 4656 u8 xtal_cap; 4657 u8 addr[ETH_ALEN]; 4658 u8 rfe_type; 4659 char country_code[2]; 4660 u8 adc_td; 4661 u8 bt_setting_2; 4662 u8 bt_setting_3; 4663 u8 sn[RTW89_EFUSE_SN_LEN]; 4664 u8 uuid[RTW89_EFUSE_UUID_LEN]; 4665 u8 vcore_vmax_reduce; 4666 u8 dswr_vmin; 4667 }; 4668 4669 struct rtw89_phy_rate_pattern { 4670 u64 ra_mask; 4671 u16 rate; 4672 u8 ra_mode; 4673 bool enable; 4674 }; 4675 4676 #define RTW89_TX_DONE 0x0 4677 #define RTW89_TX_RETRY_LIMIT 0x1 4678 #define RTW89_TX_LIFE_TIME 0x2 4679 #define RTW89_TX_MACID_DROP 0x3 4680 4681 #define RTW89_MAX_TX_RPTS 16 4682 #define RTW89_MAX_TX_RPTS_MASK (RTW89_MAX_TX_RPTS - 1) 4683 struct rtw89_tx_rpt { 4684 struct sk_buff *skbs[RTW89_MAX_TX_RPTS]; 4685 /* protect skbs array access/modification */ 4686 spinlock_t skb_lock; 4687 atomic_t sn; 4688 }; 4689 4690 #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500) 4691 struct rtw89_tx_wait_info { 4692 struct rcu_head rcu_head; 4693 struct list_head list; 4694 struct completion completion; 4695 struct sk_buff *skb; 4696 bool tx_done; 4697 }; 4698 4699 struct rtw89_tx_skb_data { 4700 struct rtw89_tx_wait_info __rcu *wait; 4701 u8 tx_rpt_sn; 4702 u8 tx_pkt_cnt_lmt; 4703 u8 hci_priv[]; 4704 }; 4705 4706 #define RTW89_SCAN_NULL_TIMEOUT 30 4707 4708 #define RTW89_ROC_IDLE_TIMEOUT 500 4709 #define RTW89_ROC_TX_TIMEOUT 30 4710 enum rtw89_roc_state { 4711 RTW89_ROC_IDLE, 4712 RTW89_ROC_NORMAL, 4713 RTW89_ROC_MGMT, 4714 }; 4715 4716 struct rtw89_roc { 4717 struct ieee80211_channel chan; 4718 struct wiphy_delayed_work roc_work; 4719 enum ieee80211_roc_type type; 4720 enum rtw89_roc_state state; 4721 int duration; 4722 unsigned int link_id; 4723 }; 4724 4725 #define RTW89_P2P_MAX_NOA_NUM 2 4726 4727 struct rtw89_p2p_ie_head { 4728 u8 eid; 4729 u8 ie_len; 4730 u8 oui[3]; 4731 u8 oui_type; 4732 } __packed; 4733 4734 struct rtw89_noa_attr_head { 4735 u8 attr_type; 4736 __le16 attr_len; 4737 u8 index; 4738 u8 oppps_ctwindow; 4739 } __packed; 4740 4741 struct rtw89_p2p_noa_ie { 4742 struct rtw89_p2p_ie_head p2p_head; 4743 struct rtw89_noa_attr_head noa_head; 4744 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 4745 } __packed; 4746 4747 struct rtw89_p2p_noa_setter { 4748 struct rtw89_p2p_noa_ie ie; 4749 u8 noa_count; 4750 u8 noa_index; 4751 }; 4752 4753 struct rtw89_ps_noa_once_handler { 4754 bool in_duration; 4755 u64 tsf_begin; 4756 u64 tsf_end; 4757 struct wiphy_delayed_work set_work; 4758 struct wiphy_delayed_work clr_work; 4759 }; 4760 4761 struct rtw89_vif_link { 4762 struct rtw89_vif *rtwvif; 4763 struct list_head dlink_schd; 4764 unsigned int link_id; 4765 4766 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 4767 enum rtw89_chanctx_idx chanctx_idx; 4768 enum rtw89_reg_6ghz_power reg_6ghz_power; 4769 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 4770 4771 u8 mac_id; 4772 u8 port; 4773 u8 mac_addr[ETH_ALEN]; 4774 u8 bssid[ETH_ALEN]; 4775 u8 phy_idx; 4776 u8 mac_idx; 4777 u8 net_type; 4778 u8 wifi_role; 4779 u8 self_role; 4780 u8 wmm; 4781 u8 bcn_hit_cond; 4782 u8 bcn_bw_idx; 4783 u8 hit_rule; 4784 u8 last_noa_nr; 4785 u64 sync_bcn_tsf; 4786 u64 last_sync_bcn_tsf; 4787 bool rand_tsf_done; 4788 bool trigger; 4789 bool lsig_txop; 4790 u8 tgt_ind; 4791 u8 frm_tgt_ind; 4792 bool wowlan_pattern; 4793 bool wowlan_uc; 4794 bool wowlan_magic; 4795 bool is_hesta; 4796 bool last_a_ctrl; 4797 bool dyn_tb_bedge_en; 4798 bool pre_pwr_diff_en; 4799 bool pwr_diff_en; 4800 u8 def_tri_idx; 4801 struct wiphy_work update_beacon_work; 4802 struct wiphy_delayed_work csa_beacon_work; 4803 struct rtw89_addr_cam_entry addr_cam; 4804 struct rtw89_bssid_cam_entry bssid_cam; 4805 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 4806 struct rtw89_phy_rate_pattern rate_pattern; 4807 struct list_head general_pkt_list; 4808 struct rtw89_p2p_noa_setter p2p_noa; 4809 struct rtw89_ps_noa_once_handler noa_once; 4810 struct wiphy_delayed_work mcc_gc_detect_beacon_work; 4811 u8 detect_bcn_count; 4812 }; 4813 4814 enum rtw89_lv1_rcvy_step { 4815 RTW89_LV1_RCVY_STEP_1, 4816 RTW89_LV1_RCVY_STEP_2, 4817 }; 4818 4819 struct rtw89_hci_ops { 4820 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 4821 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 4822 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 4823 void (*reset)(struct rtw89_dev *rtwdev); 4824 int (*start)(struct rtw89_dev *rtwdev); 4825 void (*stop)(struct rtw89_dev *rtwdev); 4826 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 4827 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 4828 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 4829 4830 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 4831 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 4832 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 4833 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 4834 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 4835 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 4836 4837 u32 (*read32_pci_cfg)(struct rtw89_dev *rtwdev, u32 addr); 4838 4839 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 4840 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 4841 int (*mac_post_init)(struct rtw89_dev *rtwdev); 4842 int (*deinit)(struct rtw89_dev *rtwdev); 4843 4844 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 4845 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 4846 void (*dump_err_status)(struct rtw89_dev *rtwdev); 4847 int (*napi_poll)(struct napi_struct *napi, int budget); 4848 4849 /* Deal with locks inside recovery_start and recovery_complete callbacks 4850 * by hci instance, and handle things which need to consider under SER. 4851 * e.g. turn on/off interrupts except for the one for halt notification. 4852 */ 4853 void (*recovery_start)(struct rtw89_dev *rtwdev); 4854 void (*recovery_complete)(struct rtw89_dev *rtwdev); 4855 4856 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 4857 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 4858 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 4859 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 4860 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 4861 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 4862 void (*disable_intr)(struct rtw89_dev *rtwdev); 4863 void (*enable_intr)(struct rtw89_dev *rtwdev); 4864 int (*rst_bdram)(struct rtw89_dev *rtwdev); 4865 }; 4866 4867 struct rtw89_hci_info { 4868 const struct rtw89_hci_ops *ops; 4869 enum rtw89_hci_type type; 4870 enum rtw89_hci_dle_type dle_type; 4871 u32 rpwm_addr; 4872 u32 cpwm_addr; 4873 bool paused; 4874 bool tx_rpt_enabled; 4875 }; 4876 4877 struct rtw89_chip_ops { 4878 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 4879 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 4880 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4881 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4882 void (*bb_reset)(struct rtw89_dev *rtwdev, 4883 enum rtw89_phy_idx phy_idx); 4884 void (*bb_sethw)(struct rtw89_dev *rtwdev); 4885 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4886 u32 addr, u32 mask); 4887 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 4888 u32 addr, u32 mask, u32 data); 4889 void (*set_channel)(struct rtw89_dev *rtwdev, 4890 const struct rtw89_chan *chan, 4891 enum rtw89_mac_idx mac_idx, 4892 enum rtw89_phy_idx phy_idx); 4893 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 4894 struct rtw89_channel_help_params *p, 4895 const struct rtw89_chan *chan, 4896 enum rtw89_mac_idx mac_idx, 4897 enum rtw89_phy_idx phy_idx); 4898 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 4899 enum rtw89_efuse_block block); 4900 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 4901 void (*fem_setup)(struct rtw89_dev *rtwdev); 4902 int (*data_setup)(struct rtw89_dev *rtwdev); 4903 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 4904 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 4905 void (*rfk_init)(struct rtw89_dev *rtwdev); 4906 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 4907 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 4908 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 4909 enum rtw89_phy_idx phy_idx, 4910 const struct rtw89_chan *chan); 4911 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4912 bool start); 4913 void (*rfk_track)(struct rtw89_dev *rtwdev); 4914 void (*power_trim)(struct rtw89_dev *rtwdev); 4915 void (*set_txpwr)(struct rtw89_dev *rtwdev, 4916 const struct rtw89_chan *chan, 4917 enum rtw89_phy_idx phy_idx); 4918 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 4919 enum rtw89_phy_idx phy_idx); 4920 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 4921 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 4922 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev, 4923 const struct rtw89_chan *chan); 4924 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 4925 enum rtw89_phy_idx phy_idx); 4926 void (*query_ppdu)(struct rtw89_dev *rtwdev, 4927 struct rtw89_rx_phy_ppdu *phy_ppdu, 4928 struct ieee80211_rx_status *status); 4929 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 4930 struct rtw89_rx_phy_ppdu *phy_ppdu); 4931 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 4932 struct rtw89_rx_desc_info *desc_info, 4933 struct ieee80211_rx_status *rx_status); 4934 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 4935 enum rtw89_phy_idx phy_idx); 4936 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 4937 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 4938 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 4939 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 4940 enum rtw89_phy_idx phy_idx); 4941 void (*calc_rx_gain_normal)(struct rtw89_dev *rtwdev, 4942 const struct rtw89_chan *chan, 4943 enum rtw89_rf_path path, 4944 enum rtw89_phy_idx phy_idx, 4945 struct rtw89_phy_calc_efuse_gain *calc); 4946 void (*path_diff_update)(struct rtw89_dev *rtwdev, 4947 struct rtw89_bb_ctx *bb); 4948 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 4949 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 4950 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 4951 struct rtw89_rx_desc_info *desc_info, 4952 u8 *data, u32 data_offset); 4953 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 4954 struct rtw89_tx_desc_info *desc_info, 4955 void *txdesc); 4956 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 4957 struct rtw89_tx_desc_info *desc_info, 4958 void *txdesc); 4959 u8 (*get_ch_dma[RTW89_HCI_TYPE_NUM])(struct rtw89_dev *rtwdev, u8 qsel); 4960 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 4961 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 4962 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 4963 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 4964 u32 *tx_en, enum rtw89_sch_tx_sel sel); 4965 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 4966 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 4967 struct rtw89_vif_link *rtwvif_link, 4968 struct rtw89_sta_link *rtwsta_link); 4969 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 4970 struct rtw89_vif_link *rtwvif_link, 4971 struct rtw89_sta_link *rtwsta_link); 4972 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 4973 struct rtw89_vif_link *rtwvif_link, 4974 struct rtw89_sta_link *rtwsta_link); 4975 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 4976 struct rtw89_vif_link *rtwvif_link, 4977 struct rtw89_sta_link *rtwsta_link); 4978 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 4979 struct rtw89_sta_link *rtwsta_link); 4980 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev, 4981 struct rtw89_vif_link *rtwvif_link, 4982 u16 punctured); 4983 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 4984 struct rtw89_vif_link *rtwvif_link, 4985 struct rtw89_sta_link *rtwsta_link); 4986 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 4987 struct rtw89_vif_link *rtwvif_link); 4988 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 4989 struct rtw89_vif_link *rtwvif_link, 4990 struct rtw89_sta_link *rtwsta_link, 4991 bool valid, struct ieee80211_ampdu_params *params); 4992 int (*h2c_wow_cam_update)(struct rtw89_dev *rtwdev, 4993 struct rtw89_wow_cam_info *cam_info); 4994 4995 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 4996 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 4997 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 4998 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 4999 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 5000 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 5001 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 5002 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 5003 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 5004 }; 5005 5006 enum rtw89_dma_ch { 5007 RTW89_DMA_ACH0 = 0, 5008 RTW89_DMA_ACH1 = 1, 5009 RTW89_DMA_ACH2 = 2, 5010 RTW89_DMA_ACH3 = 3, 5011 RTW89_DMA_ACH4 = 4, 5012 RTW89_DMA_ACH5 = 5, 5013 RTW89_DMA_ACH6 = 6, 5014 RTW89_DMA_ACH7 = 7, 5015 RTW89_DMA_B0MG = 8, 5016 RTW89_DMA_B0HI = 9, 5017 RTW89_DMA_B1MG = 10, 5018 RTW89_DMA_B1HI = 11, 5019 RTW89_DMA_H2C = 12, 5020 RTW89_DMA_CH_NUM = 13 5021 }; 5022 5023 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 5024 5025 enum rtw89_mlo_dbcc_mode { 5026 MLO_DBCC_NOT_SUPPORT = 1, 5027 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 5028 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 5029 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 5030 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 5031 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 5032 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 5033 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 5034 DBCC_LEGACY = 0xffffffff, 5035 }; 5036 5037 enum rtw89_scan_be_operation { 5038 RTW89_SCAN_OP_STOP, 5039 RTW89_SCAN_OP_START, 5040 RTW89_SCAN_OP_SETPARM, 5041 RTW89_SCAN_OP_GETRPT, 5042 RTW89_SCAN_OP_NUM 5043 }; 5044 5045 enum rtw89_scan_be_mode { 5046 RTW89_SCAN_MODE_SA, 5047 RTW89_SCAN_MODE_MACC, 5048 RTW89_SCAN_MODE_NUM 5049 }; 5050 5051 enum rtw89_scan_be_opmode { 5052 RTW89_SCAN_OPMODE_NONE, 5053 RTW89_SCAN_OPMODE_TBTT, 5054 RTW89_SCAN_OPMODE_INTV, 5055 RTW89_SCAN_OPMODE_CNT, 5056 RTW89_SCAN_OPMODE_NUM, 5057 }; 5058 5059 struct rtw89_scan_option { 5060 bool enable; 5061 bool target_ch_mode; 5062 u8 num_macc_role; 5063 u8 num_opch; 5064 u8 repeat; 5065 u16 norm_pd; 5066 u16 slow_pd; 5067 u16 norm_cy; 5068 u8 opch_end; 5069 u16 delay; /* in unit of ms */ 5070 u64 prohib_chan; 5071 enum rtw89_phy_idx band; 5072 enum rtw89_scan_be_operation operation; 5073 enum rtw89_scan_be_mode scan_mode; 5074 enum rtw89_mlo_dbcc_mode mlo_mode; 5075 }; 5076 5077 enum rtw89_qta_mode { 5078 RTW89_QTA_SCC, 5079 RTW89_QTA_DBCC, 5080 RTW89_QTA_DLFW, 5081 RTW89_QTA_WOW, 5082 5083 /* keep last */ 5084 RTW89_QTA_INVALID, 5085 }; 5086 5087 struct rtw89_hfc_ch_cfg { 5088 u16 min; 5089 u16 max; 5090 #define grp_0 0 5091 #define grp_1 1 5092 #define grp_num 2 5093 u8 grp; 5094 }; 5095 5096 struct rtw89_hfc_ch_info { 5097 u16 aval; 5098 u16 used; 5099 }; 5100 5101 struct rtw89_hfc_pub_cfg { 5102 u16 grp0; 5103 u16 grp1; 5104 u16 pub_max; 5105 u16 wp_thrd; 5106 }; 5107 5108 struct rtw89_hfc_pub_info { 5109 u16 g0_used; 5110 u16 g1_used; 5111 u16 g0_aval; 5112 u16 g1_aval; 5113 u16 pub_aval; 5114 u16 wp_aval; 5115 }; 5116 5117 struct rtw89_hfc_prec_cfg { 5118 u16 ch011_prec; 5119 u16 h2c_prec; 5120 u16 wp_ch07_prec; 5121 u16 wp_ch811_prec; 5122 u8 ch011_full_cond; 5123 u8 h2c_full_cond; 5124 u8 wp_ch07_full_cond; 5125 u8 wp_ch811_full_cond; 5126 /* for WiFi 7 chips after 8922D */ 5127 u16 ch011_full_page; 5128 u16 h2c_full_page; 5129 u16 wp_ch07_full_page; 5130 u16 wp_ch811_full_page; 5131 }; 5132 5133 struct rtw89_hfc_param { 5134 bool en; 5135 bool h2c_en; 5136 u8 mode; 5137 const struct rtw89_hfc_ch_cfg *ch_cfg; 5138 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 5139 struct rtw89_hfc_pub_cfg pub_cfg; 5140 struct rtw89_hfc_pub_info pub_info; 5141 struct rtw89_hfc_prec_cfg prec_cfg; 5142 }; 5143 5144 struct rtw89_hfc_param_ini { 5145 const struct rtw89_hfc_ch_cfg *ch_cfg; 5146 const struct rtw89_hfc_pub_cfg *pub_cfg; 5147 const struct rtw89_hfc_prec_cfg *prec_cfg; 5148 u8 mode; 5149 }; 5150 5151 struct rtw89_dle_size { 5152 u16 pge_size; 5153 u16 lnk_pge_num; 5154 u16 unlnk_pge_num; 5155 /* for WiFi 7 chips below (suffix v1) */ 5156 u32 srt_ofst; 5157 }; 5158 5159 struct rtw89_wde_quota { 5160 u16 hif; 5161 u16 wcpu; 5162 /* unused dcpu isn't listed */ 5163 u16 pkt_in; 5164 u16 cpu_io; 5165 }; 5166 5167 struct rtw89_ple_quota { 5168 u16 cma0_tx; 5169 u16 cma1_tx; 5170 u16 c2h; 5171 u16 h2c; 5172 u16 wcpu; 5173 u16 mpdu_proc; 5174 u16 cma0_dma; 5175 u16 cma1_dma; 5176 u16 bb_rpt; 5177 u16 wd_rel; 5178 u16 cpu_io; 5179 u16 tx_rpt; 5180 /* for WiFi 7 chips below (suffix v1) */ 5181 u16 h2d; 5182 /* for WiFi 7 chips after 8922D (suffix v2) */ 5183 u16 snrpt; 5184 }; 5185 5186 struct rtw89_rsvd_quota { 5187 u16 mpdu_info_tbl; 5188 u16 b0_csi; 5189 u16 b1_csi; 5190 u16 b0_lmr; 5191 u16 b1_lmr; 5192 u16 b0_ftm; 5193 u16 b1_ftm; 5194 u16 b0_smr; 5195 u16 b1_smr; 5196 u16 others; 5197 }; 5198 5199 struct rtw89_dle_rsvd_size { 5200 u32 srt_ofst; 5201 u32 size; 5202 }; 5203 5204 struct rtw89_dle_input { 5205 u32 tx_ampdu_num_b0; 5206 u32 tx_ampdu_num_b1; 5207 u32 tx_amsdu_size; /* unit: KB */ 5208 u32 h2c_max_size; 5209 u32 rx_amsdu_size; /* unit: KB */ 5210 u32 c2h_max_size; 5211 u32 rls_rpt_max_size; 5212 u32 mpdu_info_tbl_b0; 5213 u32 mpdu_info_tbl_b1; 5214 }; 5215 5216 struct rtw89_dle_mem { 5217 enum rtw89_qta_mode mode; 5218 const struct rtw89_dle_size *wde_size; 5219 const struct rtw89_dle_size *ple_size; 5220 const struct rtw89_wde_quota *wde_min_qt; 5221 const struct rtw89_wde_quota *wde_max_qt; 5222 const struct rtw89_ple_quota *ple_min_qt; 5223 const struct rtw89_ple_quota *ple_max_qt; 5224 /* for WiFi 7 chips below */ 5225 const struct rtw89_rsvd_quota *rsvd_qt; 5226 const struct rtw89_dle_rsvd_size *rsvd0_size; 5227 const struct rtw89_dle_rsvd_size *rsvd1_size; 5228 /* for WiFi 7 chips after 8922D */ 5229 const struct rtw89_dle_input *dle_input; 5230 }; 5231 5232 struct rtw89_reg_def { 5233 u32 addr; 5234 u32 mask; 5235 }; 5236 5237 struct rtw89_reg2_def { 5238 u32 addr; 5239 u32 data; 5240 }; 5241 5242 struct rtw89_reg3_def { 5243 u32 addr; 5244 u32 mask; 5245 u32 data; 5246 }; 5247 5248 struct rtw89_reg5_def { 5249 u8 flag; /* recognized by parsers */ 5250 u8 path; 5251 u32 addr; 5252 u32 mask; 5253 u32 data; 5254 }; 5255 5256 #define RTW89_REGS_DEF(x) {x, ARRAY_SIZE(x)} 5257 struct rtw89_regs_def { 5258 const u32 *regs; 5259 u32 reg_nr; 5260 }; 5261 5262 struct rtw89_reg_imr { 5263 u32 addr; 5264 u32 clr; 5265 u32 set; 5266 }; 5267 5268 #define RTW89_MODULE_FWNAME_PLACEHOLDER_0 0, 5269 #define __RTW89_GEN_MODULE_FWNAME_FMT(placeholder_or_ignored, strfmt) \ 5270 __take_second_arg(placeholder_or_ignored, strfmt) 5271 #define RTW89_GEN_MODULE_FWNAME_FMT(maxfmt) \ 5272 __RTW89_GEN_MODULE_FWNAME_FMT(RTW89_MODULE_FWNAME_PLACEHOLDER_ ## maxfmt, \ 5273 "-" __stringify(maxfmt)) 5274 #define RTW89_GEN_MODULE_FWNAME(basename, maxformat) \ 5275 basename RTW89_GEN_MODULE_FWNAME_FMT(maxformat) ".bin" 5276 5277 struct rtw89_fw_def { 5278 const char *fw_basename; 5279 u8 fw_format_max; 5280 u16 fw_b_aid; 5281 }; 5282 5283 struct rtw89_qta_def { 5284 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_DLE_TYPE_NUM]; 5285 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM]; 5286 }; 5287 5288 struct rtw89_phy_table { 5289 const struct rtw89_reg2_def *regs; 5290 u32 n_regs; 5291 enum rtw89_rf_path rf_path; 5292 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 5293 enum rtw89_rf_path rf_path, void *data); 5294 }; 5295 5296 struct rtw89_txpwr_table { 5297 const void *data; 5298 u32 size; 5299 void (*load)(struct rtw89_dev *rtwdev, 5300 const struct rtw89_txpwr_table *tbl); 5301 }; 5302 5303 struct rtw89_txpwr_rule_2ghz { 5304 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 5305 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5306 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 5307 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 5308 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 5309 }; 5310 5311 struct rtw89_txpwr_rule_5ghz { 5312 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 5313 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5314 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 5315 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 5316 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 5317 }; 5318 5319 struct rtw89_txpwr_rule_6ghz { 5320 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 5321 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5322 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 5323 [RTW89_6G_CH_NUM]; 5324 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 5325 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 5326 [RTW89_6G_CH_NUM]; 5327 }; 5328 5329 struct rtw89_tx_shape { 5330 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM] 5331 [NUM_OF_RTW89_REG_6GHZ_POWER]; 5332 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]; 5333 5334 const u8 (*lmt_v0)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 5335 const u8 (*lmt_ru_v0)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 5336 }; 5337 5338 struct rtw89_rfe_parms { 5339 const struct rtw89_txpwr_table *byr_tbl; 5340 struct rtw89_txpwr_rule_2ghz rule_2ghz; 5341 struct rtw89_txpwr_rule_5ghz rule_5ghz; 5342 struct rtw89_txpwr_rule_6ghz rule_6ghz; 5343 struct rtw89_txpwr_rule_2ghz rule_da_2ghz; 5344 struct rtw89_txpwr_rule_5ghz rule_da_5ghz; 5345 struct rtw89_txpwr_rule_6ghz rule_da_6ghz; 5346 struct rtw89_tx_shape tx_shape; 5347 bool has_da; 5348 }; 5349 5350 struct rtw89_rfe_parms_conf { 5351 const struct rtw89_rfe_parms *rfe_parms; 5352 u8 rfe_type; 5353 }; 5354 5355 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 5356 5357 struct rtw89_txpwr_conf { 5358 u8 rfe_type; 5359 u8 ent_sz; 5360 u32 num_ents; 5361 const void *data; 5362 }; 5363 5364 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 5365 const struct rtw89_txpwr_conf *conf) 5366 { 5367 u8 valid_size = min(size, conf->ent_sz); 5368 5369 memcpy(entry, cursor, valid_size); 5370 return true; 5371 } 5372 5373 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 5374 5375 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 5376 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 5377 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 5378 (cursor) += (conf)->ent_sz) \ 5379 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 5380 5381 struct rtw89_txpwr_byrate_data { 5382 struct rtw89_txpwr_conf conf; 5383 struct rtw89_txpwr_table tbl; 5384 }; 5385 5386 struct rtw89_txpwr_lmt_2ghz_data { 5387 struct rtw89_txpwr_conf conf; 5388 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 5389 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5390 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 5391 }; 5392 5393 struct rtw89_txpwr_lmt_5ghz_data { 5394 struct rtw89_txpwr_conf conf; 5395 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 5396 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5397 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 5398 }; 5399 5400 struct rtw89_txpwr_lmt_6ghz_data { 5401 struct rtw89_txpwr_conf conf; 5402 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 5403 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 5404 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 5405 [RTW89_6G_CH_NUM]; 5406 }; 5407 5408 struct rtw89_txpwr_lmt_ru_2ghz_data { 5409 struct rtw89_txpwr_conf conf; 5410 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 5411 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 5412 }; 5413 5414 struct rtw89_txpwr_lmt_ru_5ghz_data { 5415 struct rtw89_txpwr_conf conf; 5416 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 5417 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 5418 }; 5419 5420 struct rtw89_txpwr_lmt_ru_6ghz_data { 5421 struct rtw89_txpwr_conf conf; 5422 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 5423 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 5424 [RTW89_6G_CH_NUM]; 5425 }; 5426 5427 struct rtw89_tx_shape_lmt_data { 5428 struct rtw89_txpwr_conf conf; 5429 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM] 5430 [NUM_OF_RTW89_REG_6GHZ_POWER]; 5431 }; 5432 5433 struct rtw89_tx_shape_lmt_ru_data { 5434 struct rtw89_txpwr_conf conf; 5435 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER]; 5436 }; 5437 5438 struct rtw89_rfe_data { 5439 struct rtw89_txpwr_byrate_data byrate; 5440 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 5441 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 5442 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 5443 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz; 5444 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz; 5445 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz; 5446 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 5447 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 5448 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 5449 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz; 5450 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz; 5451 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz; 5452 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 5453 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 5454 struct rtw89_rfe_parms rfe_parms; 5455 }; 5456 5457 struct rtw89_page_regs { 5458 u32 hci_fc_ctrl; 5459 u32 ch_page_ctrl; 5460 u32 ach_page_ctrl; 5461 u32 ach_page_info; 5462 u32 pub_page_info3; 5463 u32 pub_page_ctrl1; 5464 u32 pub_page_ctrl2; 5465 u32 pub_page_info1; 5466 u32 pub_page_info2; 5467 u32 wp_page_ctrl1; 5468 u32 wp_page_ctrl2; 5469 u32 wp_page_info1; 5470 }; 5471 5472 struct rtw89_imr_info { 5473 u32 wdrls_imr_set; 5474 u32 wsec_imr_reg; 5475 u32 wsec_imr_set; 5476 u32 mpdu_tx_imr_set; 5477 u32 mpdu_rx_imr_set; 5478 u32 sta_sch_imr_set; 5479 u32 txpktctl_imr_b0_reg; 5480 u32 txpktctl_imr_b0_clr; 5481 u32 txpktctl_imr_b0_set; 5482 u32 txpktctl_imr_b1_reg; 5483 u32 txpktctl_imr_b1_clr; 5484 u32 txpktctl_imr_b1_set; 5485 u32 wde_imr_clr; 5486 u32 wde_imr_set; 5487 u32 ple_imr_clr; 5488 u32 ple_imr_set; 5489 u32 host_disp_imr_clr; 5490 u32 host_disp_imr_set; 5491 u32 cpu_disp_imr_clr; 5492 u32 cpu_disp_imr_set; 5493 u32 other_disp_imr_clr; 5494 u32 other_disp_imr_set; 5495 u32 bbrpt_com_err_imr_reg; 5496 u32 bbrpt_chinfo_err_imr_reg; 5497 u32 bbrpt_err_imr_set; 5498 u32 bbrpt_dfs_err_imr_reg; 5499 u32 ptcl_imr_clr; 5500 u32 ptcl_imr_set; 5501 u32 cdma_imr_0_reg; 5502 u32 cdma_imr_0_clr; 5503 u32 cdma_imr_0_set; 5504 u32 cdma_imr_1_reg; 5505 u32 cdma_imr_1_clr; 5506 u32 cdma_imr_1_set; 5507 u32 phy_intf_imr_reg; 5508 u32 phy_intf_imr_clr; 5509 u32 phy_intf_imr_set; 5510 u32 rmac_imr_reg; 5511 u32 rmac_imr_clr; 5512 u32 rmac_imr_set; 5513 u32 tmac_imr_reg; 5514 u32 tmac_imr_clr; 5515 u32 tmac_imr_set; 5516 }; 5517 5518 struct rtw89_imr_table { 5519 const struct rtw89_reg_imr *regs; 5520 u32 n_regs; 5521 }; 5522 5523 struct rtw89_xtal_info { 5524 u32 xcap_reg; 5525 u32 sc_xo_mask; 5526 u32 sc_xi_mask; 5527 }; 5528 5529 struct rtw89_rrsr_cfgs { 5530 struct rtw89_reg3_def ref_rate; 5531 struct rtw89_reg3_def rsc; 5532 }; 5533 5534 struct rtw89_rfkill_regs { 5535 struct rtw89_reg3_def pinmux; 5536 struct rtw89_reg3_def mode; 5537 }; 5538 5539 struct rtw89_sb_regs { 5540 struct { 5541 u32 cfg; 5542 u32 get; 5543 } n[2]; 5544 }; 5545 5546 struct rtw89_dig_regs { 5547 u32 seg0_pd_reg; 5548 u32 pd_lower_bound_mask; 5549 u32 pd_spatial_reuse_en; 5550 u32 bmode_pd_reg; 5551 u32 bmode_cca_rssi_limit_en; 5552 u32 bmode_pd_lower_bound_reg; 5553 u32 bmode_rssi_nocca_low_th_mask; 5554 struct rtw89_reg_def p0_lna_init; 5555 struct rtw89_reg_def p1_lna_init; 5556 struct rtw89_reg_def p0_tia_init; 5557 struct rtw89_reg_def p1_tia_init; 5558 struct rtw89_reg_def p0_rxb_init; 5559 struct rtw89_reg_def p1_rxb_init; 5560 struct rtw89_reg_def p0_p20_pagcugc_en; 5561 struct rtw89_reg_def p0_s20_pagcugc_en; 5562 struct rtw89_reg_def p1_p20_pagcugc_en; 5563 struct rtw89_reg_def p1_s20_pagcugc_en; 5564 }; 5565 5566 struct rtw89_edcca_regs { 5567 u32 edcca_level; 5568 u32 edcca_mask; 5569 u32 edcca_p_mask; 5570 u32 ppdu_level; 5571 u32 ppdu_mask; 5572 struct rtw89_edcca_p_regs { 5573 u32 rpt_a; 5574 u32 rpt_b; 5575 u32 rpt_sel; 5576 u32 rpt_sel_mask; 5577 } p[RTW89_PHY_NUM]; 5578 u32 rpt_sel_be; 5579 u32 rpt_sel_be_mask; 5580 u32 tx_collision_t2r_st; 5581 u32 tx_collision_t2r_st_mask; 5582 }; 5583 5584 struct rtw89_pmac_regs { 5585 struct rtw89_reg_def cck_txon; 5586 struct rtw89_reg_def cck_txen; 5587 struct rtw89_reg_def cck_cca; 5588 struct rtw89_reg_def cck_sfd_gg; 5589 struct rtw89_reg_def cck_sig_gg; 5590 struct rtw89_reg_def cck_spoofing; 5591 struct rtw89_reg_def cck_brk; 5592 struct rtw89_reg_def brk; 5593 struct rtw89_reg_def brk_option; 5594 struct rtw89_reg_def search_fail; 5595 struct rtw89_reg_def lsig_brk_s_th; 5596 struct rtw89_reg_def lsig_brk_l_th; 5597 struct rtw89_reg_def rxl_err_parity; 5598 struct rtw89_reg_def rxl_err_rate; 5599 struct rtw89_reg_def ofdm_cca; 5600 struct rtw89_reg_def cca_spoofing; 5601 struct rtw89_reg_def ampdu_miss; 5602 struct rtw89_reg_def r1b_rx_rpt_rst; 5603 struct rtw89_reg_def r1b_rr_sel; 5604 struct rtw89_reg_def enable_all_cnt; 5605 struct rtw89_reg_def rst_all_cnt; 5606 u32 cck_crc32; 5607 u32 cck_crc32_ok_mask; 5608 u32 cck_crc32_fail_mask; 5609 u32 ofdm_txon; 5610 u32 ofdm_txon_mask; 5611 u32 ofdm_txen_mask; 5612 u32 l_crc; 5613 u32 l_crc_ok_mask; 5614 u32 l_crc_err_mask; 5615 u32 ht_crc; 5616 u32 ht_crc_ok_mask; 5617 u32 ht_crc_err_mask; 5618 u32 vht_crc; 5619 u32 vht_crc_ok_mask; 5620 u32 vht_crc_err_mask; 5621 u32 he_crc; 5622 u32 he_crc_ok_mask; 5623 u32 he_crc_err_mask; 5624 u32 eht_crc; 5625 u32 eht_crc_ok_mask; 5626 u32 eht_crc_err_mask; 5627 u32 ampdu_crc; 5628 u32 ampdu_crc_ok_mask; 5629 u32 ampdu_crc_err_mask; 5630 }; 5631 5632 struct rtw89_phy_ul_tb_info { 5633 bool dyn_tb_tri_en; 5634 u8 def_if_bandedge; 5635 }; 5636 5637 struct rtw89_antdiv_stats { 5638 struct ewma_rssi cck_rssi_avg; 5639 struct ewma_rssi ofdm_rssi_avg; 5640 struct ewma_rssi non_legacy_rssi_avg; 5641 u16 pkt_cnt_cck; 5642 u16 pkt_cnt_ofdm; 5643 u16 pkt_cnt_non_legacy; 5644 u32 evm; 5645 }; 5646 5647 struct rtw89_antdiv_info { 5648 struct rtw89_antdiv_stats target_stats; 5649 struct rtw89_antdiv_stats main_stats; 5650 struct rtw89_antdiv_stats aux_stats; 5651 u8 training_count; 5652 u8 rssi_pre; 5653 bool get_stats; 5654 }; 5655 5656 struct rtw89_bb_stat_cfg { 5657 bool enable; 5658 u16 mac_id; 5659 }; 5660 5661 struct rtw89_phy_info { 5662 const struct rtw89_bb_wrap_data *bb_wrap_data; 5663 struct rtw89_bb_stat_cfg bb_stat_cfg; 5664 }; 5665 5666 enum rtw89_chanctx_state { 5667 RTW89_CHANCTX_STATE_MCC_START, 5668 RTW89_CHANCTX_STATE_MCC_STOP, 5669 }; 5670 5671 enum rtw89_chanctx_callbacks { 5672 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 5673 RTW89_CHANCTX_CALLBACK_RFK, 5674 RTW89_CHANCTX_CALLBACK_TAS, 5675 5676 NUM_OF_RTW89_CHANCTX_CALLBACKS, 5677 }; 5678 5679 struct rtw89_chanctx_listener { 5680 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 5681 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 5682 }; 5683 5684 #define RTW89_NHM_TH_NUM 11 5685 #define RTW89_NHM_RPT_NUM 12 5686 5687 #define RTW89_LED_MAX_NUM 4 5688 5689 struct rtw89_led_gpio_entry { 5690 u8 pin; 5691 unsigned int color; 5692 u8 intensity; 5693 struct rtw89_reg3_def pinmux; 5694 struct rtw89_reg2_def mode; 5695 struct rtw89_reg2_def out; 5696 }; 5697 5698 struct rtw89_led_desc { 5699 const struct rtw89_led_gpio_entry *gpios; 5700 u8 n_gpio; 5701 }; 5702 5703 struct rtw89_led { 5704 bool registered; 5705 const struct rtw89_led_desc *desc; 5706 struct led_classdev led; 5707 struct led_classdev_mc led_mc; 5708 struct mc_subled subled[RTW89_LED_MAX_NUM]; 5709 enum led_brightness brightness_cache[RTW89_LED_MAX_NUM]; 5710 char name[32]; 5711 }; 5712 5713 struct rtw89_chip_info { 5714 enum rtw89_core_chip_id chip_id; 5715 enum rtw89_chip_gen chip_gen; 5716 const struct rtw89_chip_ops *ops; 5717 const struct rtw89_mac_gen_def *mac_def; 5718 const struct rtw89_phy_gen_def *phy_def; 5719 struct rtw89_fw_def fw_def; 5720 bool try_ce_fw; 5721 u8 bbmcu_nr; 5722 u32 needed_fw_elms; 5723 const struct rtw89_fw_blacklist *fw_blacklist; 5724 u32 fifo_size; 5725 bool small_fifo_size; 5726 u32 dle_scc_rsvd_size; 5727 u16 max_amsdu_limit; 5728 u16 max_vht_mpdu_cap; 5729 u16 max_eht_mpdu_cap; 5730 u16 max_tx_agg_num; 5731 u16 max_rx_agg_num; 5732 bool dis_2g_40m_ul_ofdma; 5733 u32 rsvd_ple_ofst; 5734 struct rtw89_qta_def qta_def; 5735 u8 wde_qempty_acq_grpnum; 5736 u8 wde_qempty_mgq_grpsel; 5737 u32 rf_base_addr[2]; 5738 u8 thermal_th[2]; 5739 u8 support_macid_num; 5740 u8 support_link_num; 5741 u8 support_chanctx_num; 5742 u8 support_bands; 5743 u16 support_bandwidths; 5744 bool support_unii4; 5745 bool support_rnr; 5746 bool support_ant_gain; 5747 bool support_tas; 5748 bool support_sar_by_ant; 5749 bool support_noise; 5750 bool support_fw_cmd_ofld; 5751 bool ul_tb_waveform_ctrl; 5752 bool ul_tb_pwr_diff; 5753 bool rx_freq_from_ie; 5754 bool hw_sec_hdr; 5755 bool hw_mgmt_tx_encrypt; 5756 bool hw_tkip_crypto; 5757 bool hw_mlo_bmc_crypto; 5758 u8 rf_path_num; 5759 u8 tx_nss; 5760 u8 rx_nss; 5761 u8 acam_num; 5762 u8 bcam_num; 5763 u8 scam_num; 5764 u8 bacam_num; 5765 u8 bacam_dynamic_num; 5766 enum rtw89_bacam_ver bacam_ver; 5767 u8 addrcam_ver; 5768 u8 ppdu_max_usr; 5769 5770 u8 sec_ctrl_efuse_size; 5771 u32 physical_efuse_size; 5772 u32 logical_efuse_size; 5773 u32 limit_efuse_size; 5774 u32 dav_phy_efuse_size; 5775 u32 dav_log_efuse_size; 5776 u32 phycap_addr; 5777 u32 phycap_size; 5778 const struct rtw89_efuse_block_cfg *efuse_blocks; 5779 5780 const struct rtw89_pwr_cfg * const *pwr_on_seq; 5781 const struct rtw89_pwr_cfg * const *pwr_off_seq; 5782 const struct rtw89_phy_table *bb_table; 5783 const struct rtw89_phy_table *bb_gain_table; 5784 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 5785 const struct rtw89_phy_table *nctl_table; 5786 const struct rtw89_rfk_tbl *nctl_post_table; 5787 const struct rtw89_phy_dig_gain_table *dig_table; 5788 const struct rtw89_dig_regs *dig_regs; 5789 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 5790 5791 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 5792 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 5793 const struct rtw89_rfe_parms *dflt_parms; 5794 const struct rtw89_chanctx_listener *chanctx_listener; 5795 5796 u8 txpwr_factor_bb; 5797 u8 txpwr_factor_rf; 5798 u8 txpwr_factor_mac; 5799 5800 u32 para_ver; 5801 u32 wlcx_desired; 5802 u8 scbd; 5803 u8 mailbox; 5804 5805 u8 afh_guard_ch; 5806 u16 fdd_iso_freq; 5807 const u8 *wl_rssi_thres; 5808 const u8 *bt_rssi_thres; 5809 u8 rssi_tol; 5810 5811 u8 mon_reg_num; 5812 const struct rtw89_btc_fbtc_mreg *mon_reg; 5813 const struct rtw89_btc_rf_trx_para_v0 *rf_para_ulink_v0; 5814 const struct rtw89_btc_rf_trx_para_v0 *rf_para_dlink_v0; 5815 u8 rf_para_ulink_num_v0; 5816 u8 rf_para_dlink_num_v0; 5817 const struct rtw89_btc_rf_trx_para_v9 *rf_para_ulink_v9; 5818 const struct rtw89_btc_rf_trx_para_v9 *rf_para_dlink_v9; 5819 u8 rf_para_ulink_num_v9; 5820 u8 rf_para_dlink_num_v9; 5821 u8 ps_mode_supported; 5822 u8 low_power_hci_modes; 5823 5824 u32 h2c_cctl_func_id; 5825 u32 hci_func_en_addr; 5826 u32 h2c_desc_size; 5827 u32 txwd_body_size; 5828 u32 txwd_info_size; 5829 u32 h2c_ctrl_reg; 5830 const u32 *h2c_regs; 5831 struct rtw89_reg_def h2c_counter_reg; 5832 u32 c2h_ctrl_reg; 5833 const u32 *c2h_regs; 5834 struct rtw89_reg_def c2h_counter_reg; 5835 const struct rtw89_page_regs *page_regs; 5836 const u32 *wow_reason_reg; 5837 bool cfo_src_fd; 5838 bool cfo_hw_comp; 5839 const struct rtw89_reg_def *dcfo_comp; 5840 u8 dcfo_comp_sft; 5841 const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM]; 5842 const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM]; 5843 const struct rtw89_imr_info *imr_info; 5844 const struct rtw89_imr_table *imr_dmac_table; 5845 const struct rtw89_imr_table *imr_cmac_table; 5846 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 5847 struct rtw89_reg_def bss_clr_vld; 5848 u32 bss_clr_map_reg; 5849 const struct rtw89_rfkill_regs *rfkill_init; 5850 struct rtw89_reg_def rfkill_get; 5851 struct rtw89_sb_regs btc_sb; 5852 u32 dma_ch_mask; 5853 const struct rtw89_edcca_regs *edcca_regs; 5854 const struct rtw89_pmac_regs *pmac_regs; 5855 const struct wiphy_wowlan_support *wowlan_stub; 5856 const struct rtw89_xtal_info *xtal_info; 5857 unsigned long default_quirks; /* bitmap of rtw89_quirks */ 5858 u16 txtime_limit_2ghz; 5859 }; 5860 5861 struct rtw89_chip_variant { 5862 bool no_mcs_12_13: 1; 5863 u32 fw_min_ver_code; 5864 const struct rtw89_fw_def *fw_def_override; 5865 const struct rtw89_qta_def *qta_def_override; 5866 }; 5867 5868 struct rtw89_board_variant { 5869 const struct rtw89_led_desc *led_desc; 5870 }; 5871 5872 union rtw89_bus_info { 5873 const struct rtw89_pci_info *pci; 5874 const struct rtw89_usb_info *usb; 5875 }; 5876 5877 struct rtw89_driver_info { 5878 const struct rtw89_chip_info *chip; 5879 const struct rtw89_chip_variant *variant; 5880 const struct rtw89_board_variant *board; 5881 const struct dmi_system_id *quirks; 5882 unsigned long dev_id_quirks; /* bitmap of rtw89_quirks */ 5883 union rtw89_bus_info bus; 5884 }; 5885 5886 enum rtw89_hcifc_mode { 5887 RTW89_HCIFC_POH = 0, 5888 RTW89_HCIFC_STF = 1, 5889 RTW89_HCIFC_SDIO = 2, 5890 5891 /* keep last */ 5892 RTW89_HCIFC_MODE_INVALID, 5893 }; 5894 5895 struct rtw89_dle_info { 5896 const struct rtw89_rsvd_quota *rsvd_qt; 5897 const struct rtw89_dle_input *dle_input; 5898 enum rtw89_qta_mode qta_mode; 5899 u16 ple_pg_size; 5900 u16 ple_free_pg; 5901 u16 c0_rx_qta; 5902 u16 c1_rx_qta; 5903 }; 5904 5905 enum rtw89_host_rpr_mode { 5906 RTW89_RPR_MODE_POH = 0, 5907 RTW89_RPR_MODE_STF 5908 }; 5909 5910 #define RTW89_COMPLETION_BUF_SIZE 40 5911 #define RTW89_WAIT_COND_IDLE UINT_MAX 5912 5913 struct rtw89_completion_data { 5914 bool err; 5915 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 5916 }; 5917 5918 struct rtw89_wait_response { 5919 struct rcu_head rcu_head; 5920 struct completion completion; 5921 struct rtw89_completion_data data; 5922 }; 5923 5924 struct rtw89_wait_info { 5925 atomic_t cond; 5926 struct rtw89_completion_data data; 5927 struct rtw89_wait_response __rcu *resp; 5928 }; 5929 5930 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 5931 5932 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 5933 { 5934 rcu_assign_pointer(wait->resp, NULL); 5935 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 5936 } 5937 5938 struct rtw89_mac_info { 5939 struct rtw89_dle_info dle_info; 5940 struct rtw89_hfc_param hfc_param; 5941 enum rtw89_qta_mode qta_mode; 5942 u8 rpwm_seq_num; 5943 u8 cpwm_seq_num; 5944 5945 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 5946 struct rtw89_wait_info fw_ofld_wait; 5947 /* see RTW89_PS_WAIT_COND series for wait condition */ 5948 struct rtw89_wait_info ps_wait; 5949 }; 5950 5951 enum rtw89_fwdl_check_type { 5952 RTW89_FWDL_CHECK_FREERTOS_DONE, 5953 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 5954 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 5955 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 5956 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 5957 }; 5958 5959 enum rtw89_fw_type { 5960 RTW89_FW_NORMAL = 1, 5961 RTW89_FW_WOWLAN = 3, 5962 RTW89_FW_NORMAL_CE = 5, 5963 RTW89_FW_NORMAL_B = 14, 5964 RTW89_FW_WOWLAN_B = 15, 5965 RTW89_FW_BBMCU0 = 64, 5966 RTW89_FW_BBMCU1 = 65, 5967 RTW89_FW_LOGFMT = 255, 5968 }; 5969 5970 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \ 5971 RTW89_FW_FEATURE_##_grp##_MIN, \ 5972 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \ 5973 _features \ 5974 __RTW89_FW_FEATURE_##_grp##_E, \ 5975 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1 5976 5977 enum rtw89_fw_feature { 5978 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 5979 RTW89_FW_FEATURE_SCAN_OFFLOAD, 5980 RTW89_FW_FEATURE_TX_WAKE, 5981 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER, 5982 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0, 5983 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1, 5984 ), 5985 RTW89_FW_FEATURE_NO_PACKET_DROP, 5986 RTW89_FW_FEATURE_NO_DEEP_PS, 5987 RTW89_FW_FEATURE_NO_LPS_PG, 5988 RTW89_FW_FEATURE_BEACON_FILTER, 5989 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 5990 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 5991 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V1, 5992 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V2, 5993 RTW89_FW_FEATURE_WOW_REASON_V1, 5994 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, 5995 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 5996 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 5997 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V2, 5998 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V3, 5999 ), 6000 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY_MCC, 6001 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V0, 6002 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V1, 6003 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V2, 6004 ), 6005 RTW89_FW_FEATURE_RFK_RXDCK_V0, 6006 RTW89_FW_FEATURE_RFK_IQK_V0, 6007 RTW89_FW_FEATURE_RFK_TXIQK_V0, 6008 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 6009 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 6010 RTW89_FW_FEATURE_CH_INFO_BE_V0, 6011 RTW89_FW_FEATURE_LPS_CH_INFO, 6012 RTW89_FW_FEATURE_NO_PHYCAP_P1, 6013 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 6014 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1, 6015 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP, 6016 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0, 6017 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG, 6018 RTW89_FW_FEATURE_BEACON_TRACKING, 6019 RTW89_FW_FEATURE_ADDR_CAM_V0, 6020 RTW89_FW_FEATURE_SER_L1_BY_EVENT, 6021 RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C, 6022 RTW89_FW_FEATURE_LPS_ML_INFO_V1, 6023 RTW89_FW_FEATURE_SER_POST_RECOVER_DMAC, 6024 RTW89_FW_FEATURE_TX_HISTORY_V1, 6025 6026 NUM_OF_RTW89_FW_FEATURES, 6027 }; 6028 6029 struct rtw89_fw_suit { 6030 enum rtw89_fw_type type; 6031 const u8 *data; 6032 u32 size; 6033 u8 major_ver; 6034 u8 minor_ver; 6035 u8 sub_ver; 6036 u8 sub_idex; 6037 u16 build_year; 6038 u16 build_mon; 6039 u16 build_date; 6040 u16 build_hour; 6041 u16 build_min; 6042 u8 cmd_ver; 6043 u8 hdr_ver; 6044 u32 commitid; 6045 }; 6046 6047 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 6048 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 6049 #define RTW89_FW_SUIT_VER_CODE(s) \ 6050 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 6051 6052 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 6053 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 6054 (mfw_hdr)->ver.minor, \ 6055 (mfw_hdr)->ver.sub, \ 6056 (mfw_hdr)->ver.idx) 6057 6058 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 6059 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 6060 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 6061 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 6062 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 6063 6064 struct rtw89_fw_req_info { 6065 const struct firmware *firmware; 6066 struct completion completion; 6067 }; 6068 6069 struct rtw89_fw_log { 6070 struct rtw89_fw_suit suit; 6071 bool enable; 6072 u32 last_fmt_id; 6073 u32 fmt_count; 6074 const __le32 *fmt_ids; 6075 const char *(*fmts)[]; 6076 }; 6077 6078 struct rtw89_fw_elm_info { 6079 struct rtw89_phy_table *bb_tbl; 6080 struct rtw89_phy_table *bb_gain; 6081 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 6082 struct rtw89_phy_table *rf_nctl; 6083 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 6084 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 6085 const struct rtw89_regd_data *regd; 6086 const struct rtw89_fw_element_hdr *afe; 6087 const struct rtw89_fw_element_hdr *diag_mac; 6088 const struct rtw89_fw_element_hdr *tx_comp; 6089 }; 6090 6091 enum rtw89_fw_mss_dev_type { 6092 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 6093 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 6094 }; 6095 6096 struct rtw89_fw_secure { 6097 bool secure_boot: 1; 6098 bool can_mss_v1: 1; 6099 bool can_mss_v0: 1; 6100 u32 sb_sel_mgn; 6101 u8 mss_dev_type; 6102 u8 mss_cust_idx; 6103 u8 mss_key_num; 6104 u8 mss_idx; /* v0 */ 6105 }; 6106 6107 struct rtw89_fw_info { 6108 struct rtw89_fw_req_info req; 6109 int fw_format; 6110 u8 h2c_seq; 6111 u8 rec_seq; 6112 u8 h2c_counter; 6113 u8 c2h_counter; 6114 struct rtw89_fw_suit normal; 6115 struct rtw89_fw_suit wowlan; 6116 struct rtw89_fw_suit bbmcu0; 6117 struct rtw89_fw_suit bbmcu1; 6118 struct rtw89_fw_log log; 6119 struct rtw89_fw_elm_info elm_info; 6120 struct rtw89_fw_secure sec; 6121 6122 DECLARE_BITMAP(feature_map, NUM_OF_RTW89_FW_FEATURES); 6123 }; 6124 6125 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 6126 test_bit(RTW89_FW_FEATURE_ ## _feat, (_fw)->feature_map) 6127 6128 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \ 6129 ({ \ 6130 unsigned int bit = find_next_bit((_fw)->feature_map, \ 6131 NUM_OF_RTW89_FW_FEATURES, \ 6132 RTW89_FW_FEATURE_ ## _grp ## _MIN); \ 6133 bit <= RTW89_FW_FEATURE_ ## _grp ## _MAX; \ 6134 }) 6135 6136 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 6137 set_bit(_fw_feature, (_fw)->feature_map) 6138 6139 #define RTW89_CLR_FW_FEATURE(_fw_feature, _fw) \ 6140 clear_bit(_fw_feature, (_fw)->feature_map) 6141 6142 struct rtw89_cam_info { 6143 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 6144 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 6145 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 6146 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 6147 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 6148 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 6149 }; 6150 6151 enum rtw89_sar_sources { 6152 RTW89_SAR_SOURCE_NONE, 6153 RTW89_SAR_SOURCE_COMMON, 6154 RTW89_SAR_SOURCE_ACPI, 6155 6156 RTW89_SAR_SOURCE_NR, 6157 }; 6158 6159 enum rtw89_sar_subband { 6160 RTW89_SAR_2GHZ_SUBBAND, 6161 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 6162 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 6163 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 6164 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 6165 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 6166 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 6167 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 6168 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 6169 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 6170 6171 RTW89_SAR_SUBBAND_NR, 6172 }; 6173 6174 struct rtw89_sar_cfg_common { 6175 bool set[RTW89_SAR_SUBBAND_NR]; 6176 s32 cfg[RTW89_SAR_SUBBAND_NR]; 6177 }; 6178 6179 enum rtw89_acpi_sar_subband { 6180 RTW89_ACPI_SAR_2GHZ_SUBBAND, 6181 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */ 6182 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */ 6183 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 6184 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 6185 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 6186 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 6187 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 6188 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 6189 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 6190 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 6191 6192 NUM_OF_RTW89_ACPI_SAR_SUBBAND, 6193 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1, 6194 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1, 6195 }; 6196 6197 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */ 6198 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX 6199 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN 6200 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6 6201 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1) 6202 6203 struct rtw89_sar_entry_from_acpi { 6204 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 6205 }; 6206 6207 struct rtw89_sar_table_from_acpi { 6208 /* If this table is active, must fill all fields according to either 6209 * configuration in BIOS or some default values for SAR to work well. 6210 */ 6211 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM]; 6212 }; 6213 6214 struct rtw89_sar_indicator_from_acpi { 6215 bool enable_sync; 6216 unsigned int fields; 6217 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath); 6218 6219 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path. 6220 * Not design with pointers since addresses will be invalid after 6221 * sync content with local container instance. 6222 */ 6223 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 6224 }; 6225 6226 struct rtw89_sar_cfg_acpi { 6227 u8 downgrade_2tx; 6228 unsigned int valid_num; 6229 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL]; 6230 struct rtw89_sar_indicator_from_acpi indicator; 6231 }; 6232 6233 struct rtw89_sar_info { 6234 /* used to decide how to access SAR cfg union */ 6235 enum rtw89_sar_sources src; 6236 6237 /* reserved for different knids of SAR cfg struct. 6238 * supposed that a single cfg struct cannot handle various SAR sources. 6239 */ 6240 union { 6241 struct rtw89_sar_cfg_common cfg_common; 6242 struct rtw89_sar_cfg_acpi cfg_acpi; 6243 }; 6244 }; 6245 6246 enum rtw89_ant_gain_subband { 6247 RTW89_ANT_GAIN_2GHZ_SUBBAND, 6248 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 6249 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 6250 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 6251 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 6252 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 6253 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 6254 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 6255 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 6256 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 6257 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 6258 6259 RTW89_ANT_GAIN_SUBBAND_NR, 6260 }; 6261 6262 enum rtw89_ant_gain_domain_type { 6263 RTW89_ANT_GAIN_ETSI = 0, 6264 6265 RTW89_ANT_GAIN_DOMAIN_NUM, 6266 }; 6267 6268 #define RTW89_ANT_GAIN_CHAIN_NUM 2 6269 struct rtw89_ant_gain_info { 6270 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 6271 u32 regd_enabled; 6272 bool block_country; 6273 }; 6274 6275 struct rtw89_6ghz_span { 6276 enum rtw89_sar_subband sar_subband_low; 6277 enum rtw89_sar_subband sar_subband_high; 6278 enum rtw89_acpi_sar_subband acpi_sar_subband_low; 6279 enum rtw89_acpi_sar_subband acpi_sar_subband_high; 6280 enum rtw89_ant_gain_subband ant_gain_subband_low; 6281 enum rtw89_ant_gain_subband ant_gain_subband_high; 6282 }; 6283 6284 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 6285 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high) 6286 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 6287 6288 enum rtw89_tas_state { 6289 RTW89_TAS_STATE_DPR_OFF, 6290 RTW89_TAS_STATE_DPR_ON, 6291 RTW89_TAS_STATE_STATIC_SAR, 6292 }; 6293 6294 #define RTW89_TAS_TX_RATIO_WINDOW 6 6295 #define RTW89_TAS_TXPWR_WINDOW 180 6296 struct rtw89_tas_info { 6297 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 6298 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 6299 u8 enabled_countries; 6300 u8 txpwr_head_idx; 6301 u8 txpwr_tail_idx; 6302 u8 tx_ratio_idx; 6303 u16 total_tx_ratio; 6304 u64 total_txpwr; 6305 u64 instant_txpwr; 6306 u32 window_size; 6307 s8 dpr_on_threshold; 6308 s8 dpr_off_threshold; 6309 enum rtw89_tas_state backup_state; 6310 enum rtw89_tas_state state; 6311 bool keep_history; 6312 bool block_regd; 6313 bool enable; 6314 bool pause; 6315 }; 6316 6317 struct rtw89_chanctx_cfg { 6318 enum rtw89_chanctx_idx idx; 6319 int ref_count; 6320 }; 6321 6322 enum rtw89_chanctx_changes { 6323 RTW89_CHANCTX_REMOTE_STA_CHANGE, 6324 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 6325 RTW89_CHANCTX_P2P_PS_CHANGE, 6326 RTW89_CHANCTX_BT_SLOT_CHANGE, 6327 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 6328 6329 NUM_OF_RTW89_CHANCTX_CHANGES, 6330 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 6331 }; 6332 6333 enum rtw89_entity_mode { 6334 RTW89_ENTITY_MODE_SCC_OR_SMLD, 6335 RTW89_ENTITY_MODE_MCC_PREPARE, 6336 RTW89_ENTITY_MODE_MCC, 6337 6338 NUM_OF_RTW89_ENTITY_MODE, 6339 RTW89_ENTITY_MODE_INVALID = -EINVAL, 6340 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 6341 }; 6342 6343 #define RTW89_MAX_INTERFACE_NUM 2 6344 6345 /* only valid when running with chanctx_ops */ 6346 struct rtw89_entity_mgnt { 6347 struct list_head active_list; 6348 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 6349 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 6350 [__RTW89_MLD_MAX_LINK_NUM]; 6351 }; 6352 6353 struct rtw89_chanctx { 6354 struct cfg80211_chan_def chandef; 6355 struct rtw89_chan chan; 6356 struct rtw89_chan_rcd rcd; 6357 6358 /* only assigned when running with chanctx_ops */ 6359 struct rtw89_chanctx_cfg *cfg; 6360 }; 6361 6362 struct rtw89_edcca_bak { 6363 u8 a; 6364 u8 p; 6365 u8 ppdu; 6366 u8 th_old; 6367 }; 6368 6369 enum rtw89_dm_type { 6370 RTW89_DM_DYNAMIC_EDCCA, 6371 RTW89_DM_THERMAL_PROTECT, 6372 RTW89_DM_TAS, 6373 RTW89_DM_MLO, 6374 RTW89_DM_HW_SCAN, 6375 RTW89_DM_INACTIVE_PS, 6376 RTW89_DM_DIG_PD, 6377 RTW89_DM_VCORE, 6378 }; 6379 6380 #define RTW89_THERMAL_PROT_LV_MAX 5 6381 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 6382 #define RTW89_THERMAL_PROT_VLV_MAX 6 6383 #define RTW89_THERMAL_PROT_VLV_TH_OFFSET 20 6384 6385 struct rtw89_hal { 6386 u32 rx_fltr; 6387 u8 cv; 6388 u8 cid; /* enum rtw89_core_chip_cid */ 6389 u8 acv; 6390 u16 aid; /* enum rtw89_core_chip_aid */ 6391 u32 antenna_tx; 6392 u32 antenna_rx; 6393 u8 tx_nss; 6394 u8 rx_nss; 6395 bool tx_path_diversity; 6396 bool ant_diversity; 6397 bool ant_diversity_fixed; 6398 bool support_cckpd; 6399 bool support_igi; 6400 bool no_mcs_12_13; 6401 bool no_eht; 6402 6403 atomic_t roc_chanctx_idx; 6404 6405 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 6406 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 6407 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 6408 struct cfg80211_chan_def roc_chandef; 6409 6410 bool entity_active[RTW89_PHY_NUM]; 6411 bool entity_pause; 6412 enum rtw89_entity_mode entity_mode; 6413 struct rtw89_entity_mgnt entity_mgnt; 6414 6415 enum rtw89_phy_idx entity_force_hw; 6416 6417 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 6418 6419 u8 thermal_prot_th; 6420 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 6421 6422 u8 thermal_prot_vmax; 6423 u8 thermal_prot_vmin; 6424 u8 thermal_prot_vlv; /* 0 ~ RTW89_THERMAL_PROT_VLV_MAX (6) */ 6425 6426 u8 fixed_dig_pd_th; /* v = (X(dBm) + 102)/2 */ 6427 s8 fixed_dig_cck_pd_th; /* dBm */ 6428 }; 6429 6430 #define RTW89_MAX_MAC_ID_NUM 128 6431 #define RTW89_MAX_PKT_OFLD_NUM 255 6432 6433 enum rtw89_flags { 6434 RTW89_FLAG_POWERON, 6435 RTW89_FLAG_DMAC_FUNC, 6436 RTW89_FLAG_CMAC0_FUNC, 6437 RTW89_FLAG_CMAC1_FUNC, 6438 RTW89_FLAG_CMAC0_PWR, 6439 RTW89_FLAG_CMAC1_PWR, 6440 RTW89_FLAG_FW_RDY, 6441 RTW89_FLAG_RUNNING, 6442 RTW89_FLAG_PROBE_DONE, 6443 RTW89_FLAG_BFEE_MON, 6444 RTW89_FLAG_BFEE_EN, 6445 RTW89_FLAG_BFEE_TIMER_KEEP, 6446 RTW89_FLAG_NAPI_RUNNING, 6447 RTW89_FLAG_LEISURE_PS, 6448 RTW89_FLAG_LOW_POWER_MODE, 6449 RTW89_FLAG_INACTIVE_PS, 6450 RTW89_FLAG_CRASH_SIMULATING, 6451 RTW89_FLAG_SER_HANDLING, 6452 RTW89_FLAG_WOWLAN, 6453 RTW89_FLAG_FORBIDDEN_TRACK_WORK, 6454 RTW89_FLAG_CHANGING_INTERFACE, 6455 RTW89_FLAG_HW_RFKILL_STATE, 6456 RTW89_FLAG_UNPLUGGED, 6457 RTW89_FLAG_SHUTDOWN, 6458 6459 NUM_OF_RTW89_FLAGS, 6460 }; 6461 6462 enum rtw89_quirks { 6463 RTW89_QUIRK_PCI_BER, 6464 RTW89_QUIRK_THERMAL_PROT_120C, 6465 RTW89_QUIRK_THERMAL_PROT_110C, 6466 RTW89_QUIRK_HW_INFO_SYSFS, 6467 RTW89_QUIRK_DISABLE_2GHZ, 6468 6469 NUM_OF_RTW89_QUIRKS, 6470 }; 6471 6472 enum rtw89_custid { 6473 RTW89_CUSTID_NONE = 0, 6474 RTW89_CUSTID_HP = 1, 6475 RTW89_CUSTID_ASUS = 2, 6476 RTW89_CUSTID_ACER = 3, 6477 RTW89_CUSTID_LENOVO = 4, 6478 RTW89_CUSTID_NEC = 5, 6479 RTW89_CUSTID_AMD = 6, 6480 RTW89_CUSTID_FUJITSU = 7, 6481 RTW89_CUSTID_DELL = 8, 6482 }; 6483 6484 enum rtw89_pkt_drop_sel { 6485 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6486 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6487 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6488 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6489 RTW89_PKT_DROP_SEL_MACID_ALL, 6490 RTW89_PKT_DROP_SEL_MG0_ONCE, 6491 RTW89_PKT_DROP_SEL_HIQ_ONCE, 6492 RTW89_PKT_DROP_SEL_HIQ_PORT, 6493 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 6494 RTW89_PKT_DROP_SEL_BAND, 6495 RTW89_PKT_DROP_SEL_BAND_ONCE, 6496 RTW89_PKT_DROP_SEL_REL_MACID, 6497 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 6498 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 6499 }; 6500 6501 struct rtw89_pkt_drop_params { 6502 enum rtw89_pkt_drop_sel sel; 6503 enum rtw89_mac_idx mac_band; 6504 u8 macid; 6505 u8 port; 6506 u8 mbssid; 6507 bool tf_trs; 6508 u32 macid_band_sel[4]; 6509 }; 6510 6511 struct rtw89_pkt_stat { 6512 u16 beacon_nr; 6513 u8 beacon_rate; 6514 u32 beacon_len; 6515 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 6516 struct { 6517 u32 ldpc; 6518 u32 bcc; 6519 u32 stbc; 6520 u32 su_bf; 6521 u32 su_non_bf; 6522 u32 mu; 6523 } rx; 6524 }; 6525 6526 #define RTW89_BCN_TRACK_STAT_NR 32 6527 #define RTW89_BCN_TRACK_SCALE_FACTOR 10 6528 #define RTW89_BCN_TRACK_MAX_BIN_NUM 6 6529 #define RTW89_BCN_TRACK_BIN_WIDTH 5 6530 #define RTW89_BCN_TRACK_TARGET_BCN 80 6531 6532 struct rtw89_beacon_dist { 6533 u16 min; 6534 u16 max; 6535 u16 outlier_count; 6536 u16 lower_bound; 6537 u16 upper_bound; 6538 u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM]; 6539 }; 6540 6541 struct rtw89_beacon_stat { 6542 u8 num; 6543 u8 wp; 6544 u16 tbtt_tu_min; 6545 u16 tbtt_tu_max; 6546 u16 drift[RTW89_BCN_TRACK_STAT_NR]; 6547 u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR]; 6548 u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR]; 6549 struct rtw89_beacon_dist bcn_dist; 6550 }; 6551 6552 DECLARE_EWMA(thermal, 4, 4); 6553 DECLARE_EWMA(path_diff, 4, 2); 6554 6555 struct rtw89_phy_path_diff { 6556 struct ewma_path_diff avg; 6557 u8 raw; 6558 bool bf_smo_en; 6559 u8 link_mode; 6560 }; 6561 6562 #define RTW89_TX_RATE_NR 40 6563 struct rtw89_phy_stat { 6564 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 6565 u8 last_thermal_max; 6566 u32 tx_rate_cnt[RTW89_TX_RATE_NR]; 6567 struct rtw89_beacon_stat bcn_stat; 6568 }; 6569 6570 enum rtw89_rfk_report_state { 6571 RTW89_RFK_STATE_START = 0x0, 6572 RTW89_RFK_STATE_OK = 0x1, 6573 RTW89_RFK_STATE_FAIL = 0x2, 6574 RTW89_RFK_STATE_TIMEOUT = 0x3, 6575 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 6576 }; 6577 6578 enum rtw89_rfk_report_types { 6579 RTW89_RFK_REPORT_PRE_NTFY, 6580 RTW89_RFK_REPORT_TSSI, 6581 RTW89_RFK_REPORT_IQK, 6582 RTW89_RFK_REPORT_DPK, 6583 RTW89_RFK_REPORT_TXGAPK, 6584 RTW89_RFK_REPORT_DACK, 6585 RTW89_RFK_REPORT_RX_DCK, 6586 RTW89_RFK_REPORT_TX_IQK, 6587 RTW89_RFK_REPORT_CIM3k, 6588 6589 NUM_OF_RTW89_RFK_REPORT_TYPES, 6590 }; 6591 6592 #define RTW89_RFK_RECORD_PATH_NR 2 6593 #define RTW89_RFK_RECORD_HISTORY_NR 10 6594 6595 struct rtw89_rfk_record { 6596 u32 ch[RTW89_RFK_RECORD_PATH_NR]; 6597 u32 cv[RTW89_RFK_RECORD_PATH_NR]; 6598 u32 c5[RTW89_RFK_RECORD_PATH_NR]; 6599 enum rtw89_phy_idx phy_idx; 6600 enum rtw89_rfk_report_state states[NUM_OF_RTW89_RFK_REPORT_TYPES]; 6601 }; 6602 6603 struct rtw89_rfk_wait_info { 6604 struct completion completion; 6605 ktime_t start_time; 6606 enum rtw89_rfk_report_state state; 6607 u8 version; 6608 6609 int record_idx; 6610 struct rtw89_rfk_record *record_ptr; 6611 struct rtw89_rfk_record records[RTW89_RFK_RECORD_HISTORY_NR]; 6612 6613 int record_tssi_idx; 6614 u32 tssi_code[RTW89_RFK_RECORD_HISTORY_NR][RTW89_RFK_RECORD_PATH_NR]; 6615 }; 6616 6617 #define RTW89_DACK_PATH_NR 2 6618 #define RTW89_DACK_IDX_NR 2 6619 #define RTW89_DACK_MSBK_NR 16 6620 struct rtw89_dack_info { 6621 bool dack_done; 6622 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 6623 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 6624 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 6625 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 6626 u32 dack_cnt; 6627 bool addck_timeout[RTW89_DACK_PATH_NR]; 6628 bool dadck_timeout[RTW89_DACK_PATH_NR]; 6629 bool msbk_timeout[RTW89_DACK_PATH_NR]; 6630 }; 6631 6632 enum rtw89_rfk_chs_nrs { 6633 __RTW89_RFK_CHS_NR_V0 = 2, 6634 __RTW89_RFK_CHS_NR_V1 = 3, 6635 6636 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 6637 }; 6638 6639 struct rtw89_rfk_mcc_info_data { 6640 u8 ch[RTW89_RFK_CHS_NR]; 6641 u8 band[RTW89_RFK_CHS_NR]; 6642 u8 bw[RTW89_RFK_CHS_NR]; 6643 u32 rf18[RTW89_RFK_CHS_NR]; 6644 u8 table_idx; 6645 }; 6646 6647 struct rtw89_rfk_mcc_info { 6648 struct rtw89_rfk_mcc_info_data data[2]; 6649 }; 6650 6651 #define RTW89_IQK_CHS_NR 2 6652 #define RTW89_IQK_PATH_NR 4 6653 6654 struct rtw89_lck_info { 6655 u8 thermal[RF_PATH_MAX]; 6656 }; 6657 6658 struct rtw89_rx_dck_info { 6659 u8 thermal[RF_PATH_MAX]; 6660 }; 6661 6662 struct rtw89_iqk_info { 6663 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6664 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6665 bool lok_fail[RTW89_IQK_PATH_NR]; 6666 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6667 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6668 u32 iqk_fail_cnt; 6669 bool is_iqk_init; 6670 u32 iqk_channel[RTW89_IQK_CHS_NR]; 6671 u8 iqk_band[RTW89_IQK_PATH_NR]; 6672 u8 iqk_ch[RTW89_IQK_PATH_NR]; 6673 u8 iqk_bw[RTW89_IQK_PATH_NR]; 6674 u8 iqk_times; 6675 u8 version; 6676 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 6677 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 6678 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 6679 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 6680 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 6681 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 6682 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 6683 bool is_nbiqk; 6684 bool iqk_fft_en; 6685 bool iqk_xym_en; 6686 bool iqk_sram_en; 6687 bool iqk_cfir_en; 6688 u32 syn1to2; 6689 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6690 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 6691 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6692 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 6693 u32 iqc_bak[2]; 6694 }; 6695 6696 #define RTW89_DPK_RF_PATH 2 6697 #define RTW89_DPK_AVG_THERMAL_NUM 8 6698 #define RTW89_DPK_BKUP_NUM 2 6699 struct rtw89_dpk_bkup_para { 6700 enum rtw89_band band; 6701 enum rtw89_bandwidth bw; 6702 u8 ch; 6703 u8 path_ok; 6704 u8 mdpd_en; 6705 u8 txagc_dpk; 6706 u8 ther_dpk; 6707 u8 gs; 6708 u16 pwsf; 6709 }; 6710 6711 struct rtw89_dpk_info { 6712 bool is_dpk_enable; 6713 bool is_dpk_reload_en; 6714 u8 dpk_gs[RTW89_PHY_NUM]; 6715 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6716 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6717 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6718 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6719 u8 cur_idx[RTW89_DPK_RF_PATH]; 6720 u8 cur_k_set; 6721 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 6722 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 6723 u32 dpk_order[RTW89_DPK_RF_PATH]; 6724 }; 6725 6726 struct rtw89_fem_info { 6727 bool elna_2g; 6728 bool elna_5g; 6729 bool epa_2g; 6730 bool epa_5g; 6731 bool epa_6g; 6732 }; 6733 6734 struct rtw89_phy_ch_info { 6735 u8 rssi_min; 6736 u16 rssi_min_macid; 6737 u8 pre_rssi_min; 6738 u8 rssi_max; 6739 u16 rssi_max_macid; 6740 u8 rxsc_160; 6741 u8 rxsc_80; 6742 u8 rxsc_40; 6743 u8 rxsc_20; 6744 u8 rxsc_l; 6745 u8 is_noisy; 6746 }; 6747 6748 struct rtw89_pmac_stat_info { 6749 u32 cck_phy_txon; 6750 u32 cck_mac_txen; 6751 u32 ofdm_mac_txen; 6752 u32 ofdm_phy_txon; 6753 u32 cnt_ofdm_cca; 6754 u32 cnt_cck_cca; 6755 u32 cnt_cca_all; 6756 u32 cnt_cck_spoofing; 6757 u32 cnt_ofdm_spoofing; 6758 u32 cnt_ampdu_miss; 6759 u32 cnt_ampdu_crc_error; 6760 u32 cnt_ampdu_crc_ok; 6761 u32 cnt_cck_crc32_error; 6762 u32 cnt_cck_crc32_ok; 6763 u32 cnt_ofdm_crc32_error; 6764 u32 cnt_ofdm_crc32_ok; 6765 u32 cnt_ht_crc32_error; 6766 u32 cnt_ht_crc32_ok; 6767 u32 cnt_vht_crc32_error; 6768 u32 cnt_vht_crc32_ok; 6769 u32 cnt_he_crc32_ok; 6770 u32 cnt_he_crc32_error; 6771 u32 cnt_eht_crc32_ok; 6772 u32 cnt_eht_crc32_error; 6773 u32 cnt_crc32_error_all; 6774 u32 cnt_crc32_ok_all; 6775 u32 cnt_sfd_gg; 6776 u32 cnt_sig_gg; 6777 u32 cnt_cck_fail; 6778 u32 cnt_ofdm_fail; 6779 u32 cnt_fail_all; 6780 u32 cnt_lsig_brk_s_th; 6781 u32 cnt_lsig_brk_l_th; 6782 u32 cnt_parity_fail; 6783 u32 cnt_rate_illegal; 6784 u32 cnt_sb_search_fail; 6785 }; 6786 6787 struct rtw89_tx_stat_info { 6788 u32 info[6]; 6789 u32 common_ctrl[2]; 6790 u32 txpwr[2]; 6791 u8 type; 6792 u8 subtype; 6793 u8 txcmd; 6794 u8 txsc; 6795 u8 bw; 6796 u16 tmac_txpwr; 6797 u8 tx_path_en; 6798 u8 path_map; 6799 u8 max_mcs; 6800 bool stbc; 6801 }; 6802 6803 enum rtw89_diag_bb_type { 6804 RTW89_DIAG_BB_HANG, 6805 RTW89_DIAG_BB_PD, 6806 RTW89_DIAG_BB_NO_RX, 6807 RTW89_DIAG_BB_FA, 6808 RTW89_DIAG_BB_EDCCA, 6809 6810 RTW89_DIAG_BB_NR, 6811 }; 6812 6813 struct rtw89_diag_bb { 6814 u32 diag_bb_bitmap; /* bitmap of enum rtw89_diag_bb_type */ 6815 u32 diag_bb_cnt[RTW89_DIAG_BB_NR]; 6816 u16 consecutive_no_tx_cnt; 6817 u16 consecutive_no_rx_cnt; 6818 }; 6819 6820 struct rtw89_agc_gaincode_set { 6821 u8 lna_idx; 6822 u8 tia_idx; 6823 u8 rxb_idx; 6824 }; 6825 6826 #define IGI_RSSI_TH_NUM 5 6827 #define FA_TH_NUM 4 6828 #define TIA_LNA_OP1DB_NUM 8 6829 #define LNA_GAIN_NUM 7 6830 #define TIA_GAIN_NUM 2 6831 struct rtw89_dig_info { 6832 struct rtw89_agc_gaincode_set cur_gaincode; 6833 bool force_gaincode_idx_en; 6834 struct rtw89_agc_gaincode_set force_gaincode; 6835 enum rtw89_dig_noisy_level noisy_lv; 6836 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 6837 u16 fa_th[FA_TH_NUM]; 6838 u8 igi_rssi; 6839 u8 igi_fa_rssi; 6840 u8 fa_rssi_ofst; 6841 u8 dyn_igi_max; 6842 u8 dyn_igi_min; 6843 bool dyn_pd_th_en; 6844 u8 dyn_pd_th_max; 6845 u8 dyn_pd_max_cnt; 6846 u8 pd_low_th_ofst; 6847 u8 ib_pbk; 6848 s8 ib_pkpwr; 6849 s8 lna_gain_a[LNA_GAIN_NUM]; 6850 s8 lna_gain_g[LNA_GAIN_NUM]; 6851 s8 *lna_gain; 6852 s8 tia_gain_a[TIA_GAIN_NUM]; 6853 s8 tia_gain_g[TIA_GAIN_NUM]; 6854 s8 *tia_gain; 6855 u32 bak_dig; 6856 bool is_linked_pre; 6857 bool bypass_dig; 6858 bool pause_dig; 6859 }; 6860 6861 enum rtw89_multi_cfo_mode { 6862 RTW89_PKT_BASED_AVG_MODE = 0, 6863 RTW89_ENTRY_BASED_AVG_MODE = 1, 6864 RTW89_TP_BASED_AVG_MODE = 2, 6865 }; 6866 6867 enum rtw89_phy_cfo_status { 6868 RTW89_PHY_DCFO_STATE_NORMAL = 0, 6869 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 6870 RTW89_PHY_DCFO_STATE_HOLD = 2, 6871 RTW89_PHY_DCFO_STATE_MAX 6872 }; 6873 6874 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 6875 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 6876 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 6877 }; 6878 6879 struct rtw89_cfo_tracking_info { 6880 u16 cfo_timer_ms; 6881 bool cfo_trig_by_timer_en; 6882 enum rtw89_phy_cfo_status phy_cfo_status; 6883 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 6884 u8 phy_cfo_trk_cnt; 6885 bool is_adjust; 6886 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 6887 bool apply_compensation; 6888 u8 crystal_cap; 6889 u8 crystal_cap_default; 6890 u8 def_x_cap; 6891 s8 x_cap_ofst; 6892 u32 sta_cfo_tolerance; 6893 s32 cfo_tail[CFO_TRACK_MAX_USER]; 6894 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 6895 s32 cfo_avg_pre; 6896 s32 cfo_avg[CFO_TRACK_MAX_USER]; 6897 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 6898 s32 dcfo_avg; 6899 s32 dcfo_avg_pre; 6900 u32 packet_count; 6901 u32 packet_count_pre; 6902 s32 residual_cfo_acc; 6903 u8 phy_cfotrk_state; 6904 u8 phy_cfotrk_cnt; 6905 bool divergence_lock_en; 6906 u8 x_cap_lb; 6907 u8 x_cap_ub; 6908 u8 lock_cnt; 6909 }; 6910 6911 enum rtw89_tssi_mode { 6912 RTW89_TSSI_NORMAL = 0, 6913 RTW89_TSSI_SCAN = 1, 6914 }; 6915 6916 enum rtw89_tssi_alimk_band { 6917 TSSI_ALIMK_2G = 0, 6918 TSSI_ALIMK_5GL, 6919 TSSI_ALIMK_5GM, 6920 TSSI_ALIMK_5GH, 6921 TSSI_ALIMK_MAX 6922 }; 6923 6924 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 6925 #define TSSI_TRIM_CH_GROUP_NUM 8 6926 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 6927 6928 #define TSSI_CCK_CH_GROUP_NUM 6 6929 #define TSSI_MCS_2G_CH_GROUP_NUM 5 6930 #define TSSI_MCS_5G_CH_GROUP_NUM 14 6931 #define TSSI_MCS_6G_CH_GROUP_NUM 32 6932 #define TSSI_MCS_CH_GROUP_NUM \ 6933 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 6934 #define TSSI_MAX_CH_NUM 67 6935 #define TSSI_ALIMK_VALUE_NUM 8 6936 6937 struct rtw89_tssi_info { 6938 u8 thermal[RF_PATH_MAX]; 6939 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 6940 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 6941 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 6942 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 6943 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 6944 s8 extra_ofst[RF_PATH_MAX]; 6945 bool tssi_tracking_check[RF_PATH_MAX]; 6946 u8 default_txagc_offset[RF_PATH_MAX]; 6947 u32 base_thermal[RF_PATH_MAX]; 6948 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 6949 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 6950 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 6951 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 6952 u64 tssi_alimk_time; 6953 }; 6954 6955 struct rtw89_power_trim_info { 6956 bool pg_thermal_trim; 6957 bool pg_pa_bias_trim; 6958 bool pg_vco_trim; 6959 u8 thermal_trim[RF_PATH_MAX]; 6960 u8 pa_bias_trim[RF_PATH_MAX]; 6961 u8 pad_bias_trim[RF_PATH_MAX]; 6962 u8 vco_trim[RF_PATH_MAX]; 6963 6964 s16 thermal_k; 6965 }; 6966 6967 enum rtw89_regd_func { 6968 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 6969 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 6970 6971 NUM_OF_RTW89_REGD_FUNC, 6972 }; 6973 6974 struct rtw89_regd { 6975 char alpha2[3]; 6976 u8 txpwr_regd[RTW89_BAND_NUM]; 6977 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 6978 }; 6979 6980 struct rtw89_regd_data { 6981 unsigned int nr; 6982 struct rtw89_regd map[] __counted_by(nr); 6983 }; 6984 6985 struct rtw89_regd_ctrl { 6986 unsigned int nr; 6987 const struct rtw89_regd *map; 6988 }; 6989 6990 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 6991 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 6992 #define RTW89_5GHZ_UNII4_START_INDEX 25 6993 6994 struct rtw89_regulatory_info { 6995 struct rtw89_regd_ctrl ctrl; 6996 const struct rtw89_regd *regd; 6997 bool programmed; 6998 6999 enum rtw89_reg_6ghz_power reg_6ghz_power; 7000 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 7001 bool txpwr_uk_follow_etsi; 7002 7003 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 7004 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 7005 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 7006 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM); 7007 }; 7008 7009 enum rtw89_ifs_clm_application { 7010 RTW89_IFS_CLM_INIT = 0, 7011 RTW89_IFS_CLM_BACKGROUND = 1, 7012 RTW89_IFS_CLM_ACS = 2, 7013 RTW89_IFS_CLM_DIG = 3, 7014 RTW89_IFS_CLM_TDMA_DIG = 4, 7015 RTW89_IFS_CLM_DBG = 5, 7016 RTW89_IFS_CLM_DBG_MANUAL = 6 7017 }; 7018 7019 enum rtw89_env_racing_lv { 7020 RTW89_RAC_RELEASE = 0, 7021 RTW89_RAC_LV_1 = 1, 7022 RTW89_RAC_LV_2 = 2, 7023 RTW89_RAC_LV_3 = 3, 7024 RTW89_RAC_LV_4 = 4, 7025 RTW89_RAC_MAX_NUM = 5 7026 }; 7027 7028 struct rtw89_ccx_para_info { 7029 enum rtw89_env_racing_lv rac_lv; 7030 u16 mntr_time; 7031 bool nhm_incld_cca; 7032 u8 nhm_manual_th_ofst; 7033 u8 nhm_manual_th0; 7034 enum rtw89_ifs_clm_application ifs_clm_app; 7035 u32 ifs_clm_manual_th_times; 7036 u32 ifs_clm_manual_th0; 7037 u8 fahm_manual_th_ofst; 7038 u8 fahm_manual_th0; 7039 u8 fahm_numer_opt; 7040 u8 fahm_denom_opt; 7041 }; 7042 7043 enum rtw89_ccx_edcca_opt_sc_idx { 7044 RTW89_CCX_EDCCA_SEG0_P0 = 0, 7045 RTW89_CCX_EDCCA_SEG0_S1 = 1, 7046 RTW89_CCX_EDCCA_SEG0_S2 = 2, 7047 RTW89_CCX_EDCCA_SEG0_S3 = 3, 7048 RTW89_CCX_EDCCA_SEG1_P0 = 4, 7049 RTW89_CCX_EDCCA_SEG1_S1 = 5, 7050 RTW89_CCX_EDCCA_SEG1_S2 = 6, 7051 RTW89_CCX_EDCCA_SEG1_S3 = 7 7052 }; 7053 7054 enum rtw89_ccx_edcca_opt_bw_idx { 7055 RTW89_CCX_EDCCA_BW20_0 = 0, 7056 RTW89_CCX_EDCCA_BW20_1 = 1, 7057 RTW89_CCX_EDCCA_BW20_2 = 2, 7058 RTW89_CCX_EDCCA_BW20_3 = 3, 7059 RTW89_CCX_EDCCA_BW20_4 = 4, 7060 RTW89_CCX_EDCCA_BW20_5 = 5, 7061 RTW89_CCX_EDCCA_BW20_6 = 6, 7062 RTW89_CCX_EDCCA_BW20_7 = 7 7063 }; 7064 7065 struct rtw89_nhm_report { 7066 struct list_head list; 7067 struct ieee80211_channel *channel; 7068 u8 noise; 7069 }; 7070 7071 #define RTW89_FAHM_TH_NUM 11 7072 #define RTW89_FAHM_RPT_NUM 12 7073 #define RTW89_IFS_CLM_NUM 4 7074 struct rtw89_env_monitor_info { 7075 u8 ccx_watchdog_result; 7076 bool ccx_ongoing; 7077 u8 ccx_rac_lv; 7078 bool ccx_manual_ctrl; 7079 u16 ifs_clm_mntr_time; 7080 enum rtw89_ifs_clm_application ifs_clm_app; 7081 u16 ccx_period; 7082 u8 ccx_unit_idx; 7083 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 7084 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 7085 u16 ifs_clm_tx; 7086 u16 ifs_clm_edcca_excl_cca; 7087 u16 ifs_clm_ofdmfa; 7088 u16 ifs_clm_ofdmcca_excl_fa; 7089 u16 ifs_clm_cckfa; 7090 u16 ifs_clm_cckcca_excl_fa; 7091 u16 ifs_clm_total_ifs; 7092 u16 ifs_clm_his[RTW89_IFS_CLM_NUM]; 7093 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 7094 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 7095 u8 ifs_clm_tx_ratio; 7096 u8 ifs_clm_edcca_excl_cca_ratio; 7097 u8 ifs_clm_cck_fa_ratio; 7098 u8 ifs_clm_ofdm_fa_ratio; 7099 u8 ifs_clm_cck_cca_excl_fa_ratio; 7100 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 7101 u16 ifs_clm_cck_fa_permil; 7102 u16 ifs_clm_ofdm_fa_permil; 7103 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 7104 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 7105 bool nhm_include_cca; 7106 u32 nhm_sum; 7107 u32 nhm_mntr_time; 7108 u16 nhm_result[RTW89_NHM_RPT_NUM]; 7109 u8 nhm_th[RTW89_NHM_RPT_NUM]; 7110 struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM]; 7111 struct list_head nhm_rpt_list; 7112 u8 edcca_clm_ratio; 7113 }; 7114 7115 enum rtw89_ser_rcvy_step { 7116 RTW89_SER_DRV_STOP_TX, 7117 RTW89_SER_DRV_STOP_RX, 7118 RTW89_SER_DRV_STOP_RUN, 7119 RTW89_SER_HAL_STOP_DMA, 7120 RTW89_SER_SUPPRESS_LOG, 7121 RTW89_NUM_OF_SER_FLAGS 7122 }; 7123 7124 struct rtw89_ser_count { 7125 unsigned int l1; 7126 unsigned int l2; 7127 }; 7128 7129 struct rtw89_ser { 7130 u8 state; 7131 u8 alarm_event; 7132 bool prehandle_l1; 7133 7134 struct rtw89_ser_count sw_cnt; 7135 7136 struct work_struct ser_hdl_work; 7137 struct delayed_work ser_alarm_work; 7138 const struct state_ent *st_tbl; 7139 const struct event_ent *ev_tbl; 7140 struct list_head msg_q; 7141 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 7142 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 7143 }; 7144 7145 enum rtw89_mac_ax_ps_mode { 7146 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 7147 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 7148 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 7149 RTW89_MAC_AX_PS_MODE_MAX = 3, 7150 }; 7151 7152 enum rtw89_last_rpwm_mode { 7153 RTW89_LAST_RPWM_PS = 0x0, 7154 RTW89_LAST_RPWM_ACTIVE = 0x6, 7155 }; 7156 7157 struct rtw89_lps_parm { 7158 u8 macid; 7159 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 7160 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 7161 }; 7162 7163 struct rtw89_ppdu_sts_info { 7164 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 7165 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 7166 }; 7167 7168 struct rtw89_early_h2c { 7169 struct list_head list; 7170 u8 *h2c; 7171 u16 h2c_len; 7172 }; 7173 7174 struct rtw89_hw_scan_extra_op { 7175 bool set; 7176 u8 macid; 7177 u8 port; 7178 struct rtw89_chan chan; 7179 struct rtw89_vif_link *rtwvif_link; 7180 }; 7181 7182 struct rtw89_hw_scan_info { 7183 struct rtw89_vif_link *scanning_vif; 7184 struct list_head pkt_list[NUM_NL80211_BANDS]; 7185 struct list_head chan_list; 7186 struct rtw89_chan op_chan; 7187 struct rtw89_hw_scan_extra_op extra_op; 7188 u8 wildcard_pkt_id[NUM_NL80211_BANDS]; 7189 u16 ssid_total_len; 7190 int n_ssids; 7191 bool connected; 7192 bool abort; 7193 u16 delay; /* in unit of ms */ 7194 u8 seq: 2; 7195 }; 7196 7197 enum rtw89_phy_bb_gain_band { 7198 RTW89_BB_GAIN_BAND_2G = 0, 7199 RTW89_BB_GAIN_BAND_5G_L = 1, 7200 RTW89_BB_GAIN_BAND_5G_M = 2, 7201 RTW89_BB_GAIN_BAND_5G_H = 3, 7202 RTW89_BB_GAIN_BAND_6G_L = 4, 7203 RTW89_BB_GAIN_BAND_6G_M = 5, 7204 RTW89_BB_GAIN_BAND_6G_H = 6, 7205 RTW89_BB_GAIN_BAND_6G_UH = 7, 7206 7207 RTW89_BB_GAIN_BAND_NR, 7208 }; 7209 7210 enum rtw89_phy_gain_band_be { 7211 RTW89_BB_GAIN_BAND_2G_BE = 0, 7212 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 7213 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 7214 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 7215 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 7216 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 7217 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 7218 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 7219 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 7220 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 7221 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 7222 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 7223 7224 RTW89_BB_GAIN_BAND_NR_BE, 7225 }; 7226 7227 enum rtw89_phy_bb_bw_be { 7228 RTW89_BB_BW_20_40 = 0, 7229 RTW89_BB_BW_80_160_320 = 1, 7230 7231 RTW89_BB_BW_NR_BE, 7232 }; 7233 7234 enum rtw89_bw20_sc { 7235 RTW89_BW20_SC_20M = 1, 7236 RTW89_BW20_SC_40M = 2, 7237 RTW89_BW20_SC_80M = 4, 7238 RTW89_BW20_SC_160M = 8, 7239 RTW89_BW20_SC_320M = 16, 7240 }; 7241 7242 enum rtw89_cmac_table_bw { 7243 RTW89_CMAC_BW_20M = 0, 7244 RTW89_CMAC_BW_40M = 1, 7245 RTW89_CMAC_BW_80M = 2, 7246 RTW89_CMAC_BW_160M = 3, 7247 RTW89_CMAC_BW_320M = 4, 7248 7249 RTW89_CMAC_BW_NR, 7250 }; 7251 7252 enum rtw89_phy_bb_rxsc_num { 7253 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 7254 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 7255 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 7256 }; 7257 7258 struct rtw89_phy_bb_gain_info { 7259 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 7260 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 7261 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 7262 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 7263 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 7264 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 7265 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 7266 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 7267 [RTW89_BB_RXSC_NUM_40]; 7268 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 7269 [RTW89_BB_RXSC_NUM_80]; 7270 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 7271 [RTW89_BB_RXSC_NUM_160]; 7272 }; 7273 7274 struct rtw89_phy_bb_gain_info_be { 7275 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 7276 [LNA_GAIN_NUM]; 7277 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 7278 [TIA_GAIN_NUM]; 7279 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 7280 [RF_PATH_MAX][LNA_GAIN_NUM]; 7281 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 7282 [RF_PATH_MAX][LNA_GAIN_NUM]; 7283 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 7284 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 7285 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 7286 [RTW89_BW20_SC_20M]; 7287 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 7288 [RTW89_BW20_SC_40M]; 7289 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 7290 [RTW89_BW20_SC_80M]; 7291 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 7292 [RTW89_BW20_SC_160M]; 7293 }; 7294 7295 struct rtw89_phy_efuse_gain { 7296 bool offset_valid; 7297 bool comp_valid; 7298 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 7299 s8 offset2[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 7300 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 7301 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 7302 s8 ref_gain_base[RTW89_PHY_NUM]; /* S(8, 2) */ 7303 s8 cck_rpl_base[RTW89_PHY_NUM]; /* S(8, 0) */ 7304 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 7305 }; 7306 7307 struct rtw89_phy_calc_efuse_gain { 7308 s8 cck_mean_gain_bias; 7309 s8 cck_rpl_ofst; 7310 s8 rssi_ofst; 7311 }; 7312 7313 #define RTW89_MAX_PATTERN_NUM 18 7314 #define RTW89_MAX_PATTERN_MASK_SIZE 4 7315 #define RTW89_MAX_PATTERN_SIZE 128 7316 7317 struct rtw89_wow_cam_info { 7318 bool r_w; 7319 u8 idx; 7320 __le32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 7321 u16 crc; 7322 bool negative_pattern_match; 7323 bool skip_mac_hdr; 7324 bool uc; 7325 bool mc; 7326 bool bc; 7327 bool valid; 7328 }; 7329 7330 struct rtw89_wow_key_info { 7331 u8 ptk_tx_iv[8]; 7332 u8 valid_check; 7333 u8 symbol_check_en; 7334 u8 gtk_keyidx; 7335 u8 rsvd[5]; 7336 u8 ptk_rx_iv[8]; 7337 u8 gtk_rx_iv[4][8]; 7338 } __packed; 7339 7340 struct rtw89_wow_gtk_info { 7341 u8 kck[32]; 7342 u8 kek[32]; 7343 u8 tk1[16]; 7344 u8 rxmickey[8]; 7345 u8 txmickey[8]; 7346 __le32 igtk_keyid; 7347 __le64 ipn; 7348 u8 igtk[2][32]; 7349 u8 psk[32]; 7350 } __packed; 7351 7352 struct rtw89_wow_aoac_report { 7353 u8 rpt_ver; 7354 u8 sec_type; 7355 u8 key_idx; 7356 u8 pattern_idx; 7357 u8 rekey_ok; 7358 u8 ptk_tx_iv[8]; 7359 u8 eapol_key_replay_count[8]; 7360 u8 gtk[32]; 7361 u8 ptk_rx_iv[8]; 7362 u8 gtk_rx_iv[4][8]; 7363 u64 igtk_key_id; 7364 u64 igtk_ipn; 7365 u8 igtk[32]; 7366 u8 csa_pri_ch; 7367 u8 csa_bw; 7368 u8 csa_ch_offset; 7369 u8 csa_chsw_failed; 7370 u8 csa_ch_band; 7371 }; 7372 7373 struct rtw89_wow_param { 7374 struct rtw89_vif_link *rtwvif_link; 7375 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 7376 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 7377 struct rtw89_wow_key_info key_info; 7378 struct rtw89_wow_gtk_info gtk_info; 7379 struct rtw89_wow_aoac_report aoac_rpt; 7380 u8 pattern_cnt; 7381 u8 ptk_alg; 7382 u8 gtk_alg; 7383 u8 ptk_keyidx; 7384 u8 akm; 7385 7386 /* see RTW89_WOW_WAIT_COND series for wait condition */ 7387 struct rtw89_wait_info wait; 7388 7389 bool pno_inited; 7390 struct list_head pno_pkt_list; 7391 struct cfg80211_sched_scan_request *nd_config; 7392 }; 7393 7394 struct rtw89_mcc_limit { 7395 bool enable; 7396 u16 max_tob; /* TU; max time offset behind */ 7397 u16 max_toa; /* TU; max time offset ahead */ 7398 u16 max_dur; /* TU */ 7399 }; 7400 7401 struct rtw89_mcc_policy { 7402 u8 c2h_rpt; 7403 u8 tx_null_early; 7404 u8 dis_tx_null; 7405 u8 in_curr_ch; 7406 u8 dis_sw_retry; 7407 u8 sw_retry_count; 7408 }; 7409 7410 struct rtw89_mcc_role { 7411 struct rtw89_vif_link *rtwvif_link; 7412 struct rtw89_mcc_policy policy; 7413 struct rtw89_mcc_limit limit; 7414 7415 const struct rtw89_mcc_courtesy_cfg *crtz; 7416 7417 /* only valid when running with FW MRC mechanism */ 7418 u8 slot_idx; 7419 7420 /* byte-array in LE order for FW */ 7421 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 7422 u8 probe_count; 7423 7424 u16 duration; /* TU */ 7425 u16 beacon_interval; /* TU */ 7426 bool is_2ghz; 7427 bool is_go; 7428 bool is_gc; 7429 bool ignore_bcn; 7430 }; 7431 7432 struct rtw89_mcc_bt_role { 7433 u16 duration; /* TU */ 7434 }; 7435 7436 struct rtw89_mcc_courtesy_cfg { 7437 u8 slot_num; 7438 u8 macid_tgt; 7439 }; 7440 7441 struct rtw89_mcc_courtesy { 7442 struct rtw89_mcc_courtesy_cfg ref; 7443 struct rtw89_mcc_courtesy_cfg aux; 7444 }; 7445 7446 enum rtw89_mcc_plan { 7447 RTW89_MCC_PLAN_TAIL_BT, 7448 RTW89_MCC_PLAN_MID_BT, 7449 RTW89_MCC_PLAN_NO_BT, 7450 7451 NUM_OF_RTW89_MCC_PLAN, 7452 }; 7453 7454 struct rtw89_mcc_pattern { 7455 s16 tob_ref; /* TU; time offset behind of reference role */ 7456 s16 toa_ref; /* TU; time offset ahead of reference role */ 7457 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 7458 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 7459 7460 enum rtw89_mcc_plan plan; 7461 struct rtw89_mcc_courtesy courtesy; 7462 }; 7463 7464 struct rtw89_mcc_sync { 7465 bool enable; 7466 u16 offset; /* TU */ 7467 u8 macid_src; 7468 u8 band_src; 7469 u8 port_src; 7470 u8 macid_tgt; 7471 u8 band_tgt; 7472 u8 port_tgt; 7473 }; 7474 7475 struct rtw89_mcc_config { 7476 struct rtw89_mcc_pattern pattern; 7477 struct rtw89_mcc_sync sync; 7478 u64 start_tsf; 7479 u64 start_tsf_in_aux_domain; 7480 u64 prepare_delay; 7481 u16 mcc_interval; /* TU */ 7482 u16 beacon_offset; /* TU */ 7483 }; 7484 7485 enum rtw89_mcc_mode { 7486 RTW89_MCC_MODE_GO_STA, 7487 RTW89_MCC_MODE_GC_STA, 7488 }; 7489 7490 struct rtw89_mcc_info { 7491 struct rtw89_wait_info wait; 7492 7493 u8 group; 7494 enum rtw89_mcc_mode mode; 7495 struct rtw89_mcc_role role_ref; /* reference role */ 7496 struct rtw89_mcc_role role_aux; /* auxiliary role */ 7497 struct rtw89_mcc_bt_role bt_role; 7498 struct rtw89_mcc_config config; 7499 }; 7500 7501 enum rtw89_mlo_mode { 7502 RTW89_MLO_MODE_MLSR = 0, 7503 RTW89_MLO_MODE_EMLSR = 1, 7504 7505 NUM_OF_RTW89_MLO_MODE, 7506 }; 7507 7508 struct rtw89_mlo_info { 7509 struct rtw89_wait_info wait; 7510 }; 7511 7512 struct rtw89_beacon_track_info { 7513 bool is_data_ready; 7514 u32 tbtt_offset; /* in unit of microsecond */ 7515 u16 bcn_timeout; /* in unit of millisecond */ 7516 7517 /* The following are constant and set at association. */ 7518 u8 dtim; 7519 u16 beacon_int; 7520 u16 low_bcn_th; 7521 u16 med_bcn_th; 7522 u16 high_bcn_th; 7523 u16 target_bcn_th; 7524 u16 outlier_low_bcn_th; 7525 u16 outlier_high_bcn_th; 7526 u32 close_bcn_intvl_th; 7527 u32 tbtt_diff_th; 7528 }; 7529 7530 struct rtw89_tid_stats { 7531 s64 last_pn; 7532 u16 last_sn; 7533 bool started; 7534 }; 7535 7536 struct rtw89_io_ops { 7537 int (*pack)(struct rtw89_dev *rtwdev); 7538 int (*unpack)(struct rtw89_dev *rtwdev); 7539 void (*do_udelay)(struct rtw89_dev *rtwdev, u32 us); 7540 void (*do_mdelay)(struct rtw89_dev *rtwdev, u32 ms); 7541 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 7542 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 7543 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 7544 void (*phy_write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 7545 void (*phy_write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 7546 void (*phy_write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 7547 void (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 7548 u32 addr, u32 mask, u32 data); 7549 }; 7550 7551 struct rtw89_dev { 7552 struct ieee80211_hw *hw; 7553 struct device *dev; 7554 const struct ieee80211_ops *ops; 7555 const struct rtw89_io_ops *io; 7556 7557 bool dbcc_en; 7558 bool support_mlo; 7559 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 7560 struct rtw89_hw_scan_info scan_info; 7561 const struct rtw89_chip_info *chip; 7562 const struct rtw89_chip_variant *variant; 7563 const struct rtw89_board_variant *board; 7564 const struct rtw89_pci_info *pci_info; 7565 const struct rtw89_rfe_parms *rfe_parms; 7566 struct rtw89_hal hal; 7567 struct rtw89_beacon_track_info bcn_track; 7568 struct rtw89_mcc_info mcc; 7569 struct rtw89_mlo_info mlo; 7570 struct rtw89_mac_info mac; 7571 struct rtw89_fw_info fw; 7572 struct rtw89_hci_info hci; 7573 struct rtw89_efuse efuse; 7574 struct rtw89_traffic_stats stats; 7575 struct rtw89_rfe_data *rfe_data; 7576 enum rtw89_custid custid; 7577 7578 struct rtw89_fw_cmd_ofld_info *fw_cmd_ofld_info; 7579 7580 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 7581 refcount_t refcount_ap_info; 7582 7583 struct list_head rtwvifs_list; 7584 struct workqueue_struct *txq_wq; 7585 struct work_struct txq_work; 7586 struct delayed_work txq_reinvoke_work; 7587 /* used to protect ba_list and forbid_ba_list */ 7588 spinlock_t ba_lock; 7589 /* txqs to setup ba session */ 7590 struct list_head ba_list; 7591 /* txqs to forbid ba session */ 7592 struct list_head forbid_ba_list; 7593 struct work_struct ba_work; 7594 /* used to protect rpwm */ 7595 spinlock_t rpwm_lock; 7596 7597 struct list_head tx_waits; 7598 struct wiphy_delayed_work tx_wait_work; 7599 7600 struct rtw89_tx_rpt tx_rpt; 7601 7602 struct rtw89_cam_info cam_info; 7603 7604 struct sk_buff_head c2h_queue; 7605 struct wiphy_work c2h_work; 7606 struct wiphy_work ips_work; 7607 struct wiphy_work cancel_6ghz_probe_work; 7608 struct work_struct load_firmware_work; 7609 7610 struct list_head early_h2c_list; 7611 7612 struct rtw89_ser ser; 7613 7614 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 7615 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 7616 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 7617 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 7618 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 7619 7620 struct rtw89_phy_stat phystat; 7621 struct rtw89_rfk_wait_info rfk_wait; 7622 struct rtw89_dack_info dack; 7623 struct rtw89_iqk_info iqk; 7624 struct rtw89_dpk_info dpk; 7625 struct rtw89_rfk_mcc_info rfk_mcc; 7626 struct rtw89_lck_info lck; 7627 struct rtw89_rx_dck_info rx_dck; 7628 bool is_tssi_mode[RF_PATH_MAX]; 7629 bool is_bt_iqk_timeout; 7630 7631 struct rtw89_fem_info fem; 7632 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 7633 struct rtw89_tssi_info tssi; 7634 struct rtw89_power_trim_info pwr_trim; 7635 7636 struct rtw89_cfo_tracking_info cfo_tracking; 7637 union { 7638 struct rtw89_phy_bb_gain_info ax; 7639 struct rtw89_phy_bb_gain_info_be be; 7640 } bb_gain; 7641 struct rtw89_phy_efuse_gain efuse_gain; 7642 struct rtw89_phy_ul_tb_info ul_tb_info; 7643 struct rtw89_antdiv_info antdiv; 7644 struct rtw89_phy_info phy_info; 7645 7646 struct rtw89_bb_ctx { 7647 enum rtw89_phy_idx phy_idx; 7648 struct rtw89_env_monitor_info env_monitor; 7649 struct rtw89_dig_info dig; 7650 struct rtw89_phy_ch_info ch_info; 7651 struct rtw89_edcca_bak edcca_bak; 7652 struct ewma_rssi bcn_rssi; 7653 struct rtw89_pkt_stat cur_pkt_stat; 7654 struct rtw89_pkt_stat last_pkt_stat; 7655 struct rtw89_pmac_stat_info pmac_stat; 7656 struct rtw89_tx_stat_info tx_stat; 7657 struct rtw89_diag_bb diag; 7658 struct rtw89_phy_path_diff path_diff; 7659 } bbs[RTW89_PHY_NUM]; 7660 7661 struct wiphy_delayed_work track_work; 7662 struct wiphy_delayed_work track_ps_work; 7663 struct wiphy_delayed_work chanctx_work; 7664 struct wiphy_delayed_work coex_act1_work; 7665 struct wiphy_delayed_work coex_bt_devinfo_work; 7666 struct wiphy_delayed_work coex_rfk_chk_work; 7667 struct wiphy_delayed_work cfo_track_work; 7668 struct wiphy_delayed_work mcc_prepare_done_work; 7669 struct delayed_work forbid_ba_work; 7670 struct wiphy_delayed_work antdiv_work; 7671 struct rtw89_ppdu_sts_info ppdu_sts; 7672 u8 total_sta_assoc; 7673 bool scanning; 7674 7675 struct rtw89_regulatory_info regulatory; 7676 struct rtw89_sar_info sar; 7677 struct rtw89_tas_info tas; 7678 struct rtw89_ant_gain_info ant_gain; 7679 7680 struct rtw89_btc btc; 7681 enum rtw89_ps_mode ps_mode; 7682 bool lps_enabled; 7683 u8 ps_hang_cnt; 7684 7685 struct rtw89_wow_param wow; 7686 7687 /* napi structure */ 7688 struct net_device *netdev; 7689 struct napi_struct napi; 7690 int napi_budget_countdown; 7691 7692 struct rtw89_debugfs *debugfs; 7693 struct rtw89_vif *pure_monitor_mode_vif; 7694 struct rtw89_led led; 7695 7696 /* HCI related data, keep last */ 7697 u8 priv[] __aligned(sizeof(void *)); 7698 }; 7699 7700 struct rtw89_link_conf_container { 7701 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 7702 }; 7703 7704 struct rtw89_vif_ml_trans { 7705 u16 mediate_links; 7706 u16 links_to_del; 7707 u16 links_to_add; 7708 }; 7709 7710 #define RTW89_VIF_IDLE_LINK_ID 0 7711 7712 struct rtw89_vif { 7713 struct rtw89_dev *rtwdev; 7714 struct list_head list; 7715 struct list_head mgnt_entry; 7716 struct rtw89_link_conf_container __rcu *snap_link_confs; 7717 7718 u8 mac_addr[ETH_ALEN]; 7719 __be32 ip_addr; 7720 7721 struct rtw89_traffic_stats stats; 7722 struct rtw89_traffic_stats stats_ps; 7723 u32 tdls_peer; 7724 7725 struct ieee80211_scan_ies *scan_ies; 7726 struct cfg80211_scan_request *scan_req; 7727 7728 struct rtw89_roc roc; 7729 bool offchan; 7730 bool burst_active; 7731 7732 enum rtw89_mlo_mode mlo_mode; 7733 struct rtw89_vif_ml_trans ml_trans; 7734 7735 struct list_head dlink_pool; 7736 u8 links_inst_valid_num; 7737 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 7738 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 7739 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 7740 }; 7741 7742 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 7743 const struct rtw89_vif *rtwvif, 7744 unsigned int link_id) 7745 { 7746 *rtwvif_link = rtwvif->links[link_id]; 7747 return !!*rtwvif_link; 7748 } 7749 7750 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 7751 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 7752 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 7753 7754 enum rtw89_sta_flags { 7755 RTW89_REMOTE_STA_IN_PS, 7756 7757 NUM_OF_RTW89_STA_FLAGS, 7758 }; 7759 7760 struct rtw89_sta { 7761 struct rtw89_dev *rtwdev; 7762 struct rtw89_vif *rtwvif; 7763 7764 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 7765 7766 bool disassoc; 7767 7768 struct sk_buff_head roc_queue; 7769 7770 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 7771 struct rtw89_tid_stats tid_rx_stats[IEEE80211_NUM_TIDS]; 7772 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 7773 7774 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 7775 7776 struct list_head dlink_pool; 7777 u8 links_inst_valid_num; 7778 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 7779 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 7780 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 7781 }; 7782 7783 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 7784 const struct rtw89_sta *rtwsta, 7785 unsigned int link_id) 7786 { 7787 *rtwsta_link = rtwsta->links[link_id]; 7788 return !!*rtwsta_link; 7789 } 7790 7791 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 7792 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 7793 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 7794 7795 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 7796 { 7797 /* const after init, so no need to check if active first */ 7798 return rtwvif->links_inst[0].mac_id; 7799 } 7800 7801 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 7802 { 7803 /* const after init, so no need to check if active first */ 7804 return rtwvif->links_inst[0].port; 7805 } 7806 7807 static inline struct rtw89_vif_link * 7808 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 7809 { 7810 if (index >= rtwvif->links_inst_valid_num || 7811 !test_bit(index, rtwvif->links_inst_map)) 7812 return NULL; 7813 return &rtwvif->links_inst[index]; 7814 } 7815 7816 static inline 7817 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 7818 { 7819 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 7820 7821 return rtwvif_link - rtwvif->links_inst; 7822 } 7823 7824 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 7825 { 7826 /* const after init, so no need to check if active first */ 7827 return rtwsta->links_inst[0].mac_id; 7828 } 7829 7830 static inline struct rtw89_sta_link * 7831 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 7832 { 7833 if (index >= rtwsta->links_inst_valid_num || 7834 !test_bit(index, rtwsta->links_inst_map)) 7835 return NULL; 7836 return &rtwsta->links_inst[index]; 7837 } 7838 7839 static inline 7840 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 7841 { 7842 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 7843 7844 return rtwsta_link - rtwsta->links_inst; 7845 } 7846 7847 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 7848 { 7849 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 7850 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 7851 7852 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 7853 rtwsta_link); 7854 } 7855 7856 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 7857 { 7858 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 7859 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 7860 7861 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 7862 NULL); 7863 synchronize_rcu(); 7864 } 7865 7866 static inline struct rtw89_sta_link * 7867 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 7868 { 7869 if (unlikely(macid >= RTW89_MAX_MAC_ID_NUM)) 7870 return NULL; 7871 7872 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 7873 } 7874 7875 #define rtw89_get_designated_link(links_holder) \ 7876 ({ \ 7877 typeof(links_holder) p = links_holder; \ 7878 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 7879 }) 7880 7881 static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait) 7882 { 7883 dev_kfree_skb_any(wait->skb); 7884 kfree_rcu(wait, rcu_head); 7885 } 7886 7887 static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev) 7888 { 7889 struct rtw89_tx_wait_info *wait, *tmp; 7890 7891 lockdep_assert_wiphy(rtwdev->hw->wiphy); 7892 7893 list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) { 7894 if (!completion_done(&wait->completion)) 7895 continue; 7896 list_del(&wait->list); 7897 rtw89_tx_wait_release(wait); 7898 } 7899 } 7900 7901 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 7902 struct rtw89_core_tx_request *tx_req) 7903 { 7904 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 7905 } 7906 7907 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 7908 { 7909 rtwdev->hci.ops->reset(rtwdev); 7910 /* hci.ops->reset must complete all pending TX wait SKBs */ 7911 rtw89_tx_wait_list_clear(rtwdev); 7912 } 7913 7914 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 7915 { 7916 return rtwdev->hci.ops->start(rtwdev); 7917 } 7918 7919 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 7920 { 7921 rtwdev->hci.ops->stop(rtwdev); 7922 } 7923 7924 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 7925 { 7926 return rtwdev->hci.ops->deinit(rtwdev); 7927 } 7928 7929 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 7930 { 7931 rtwdev->hci.ops->pause(rtwdev, pause); 7932 } 7933 7934 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 7935 { 7936 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 7937 } 7938 7939 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 7940 { 7941 rtwdev->hci.ops->recalc_int_mit(rtwdev); 7942 } 7943 7944 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 7945 { 7946 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 7947 } 7948 7949 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 7950 { 7951 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 7952 } 7953 7954 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 7955 { 7956 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 7957 } 7958 7959 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 7960 bool drop) 7961 { 7962 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 7963 return; 7964 7965 if (rtwdev->hci.ops->flush_queues) 7966 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 7967 } 7968 7969 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 7970 { 7971 if (rtwdev->hci.ops->recovery_start) 7972 rtwdev->hci.ops->recovery_start(rtwdev); 7973 } 7974 7975 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 7976 { 7977 if (rtwdev->hci.ops->recovery_complete) 7978 rtwdev->hci.ops->recovery_complete(rtwdev); 7979 } 7980 7981 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 7982 { 7983 if (rtwdev->hci.ops->enable_intr) 7984 rtwdev->hci.ops->enable_intr(rtwdev); 7985 } 7986 7987 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 7988 { 7989 if (rtwdev->hci.ops->disable_intr) 7990 rtwdev->hci.ops->disable_intr(rtwdev); 7991 } 7992 7993 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 7994 { 7995 if (rtwdev->hci.ops->ctrl_txdma_ch) 7996 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 7997 } 7998 7999 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 8000 { 8001 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 8002 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 8003 } 8004 8005 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 8006 { 8007 if (rtwdev->hci.ops->ctrl_trxhci) 8008 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 8009 } 8010 8011 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 8012 { 8013 int ret = 0; 8014 8015 if (rtwdev->hci.ops->poll_txdma_ch_idle) 8016 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 8017 return ret; 8018 } 8019 8020 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 8021 { 8022 if (rtwdev->hci.ops->clr_idx_all) 8023 rtwdev->hci.ops->clr_idx_all(rtwdev); 8024 } 8025 8026 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 8027 { 8028 int ret = 0; 8029 8030 if (rtwdev->hci.ops->rst_bdram) 8031 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 8032 return ret; 8033 } 8034 8035 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 8036 { 8037 if (rtwdev->hci.ops->clear) 8038 rtwdev->hci.ops->clear(rtwdev, pdev); 8039 } 8040 8041 static inline 8042 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 8043 { 8044 /* 8045 * This should be used by/after rtw89_hci_tx_write() and before doing 8046 * ieee80211_tx_info_clear_status(). 8047 */ 8048 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 8049 8050 return (struct rtw89_tx_skb_data *)info->driver_data; 8051 } 8052 8053 static inline int rtw89_io_pack(struct rtw89_dev *rtwdev) 8054 { 8055 if (rtwdev->io->pack) 8056 return rtwdev->io->pack(rtwdev); 8057 8058 return 0; 8059 } 8060 8061 static inline int rtw89_io_unpack(struct rtw89_dev *rtwdev) 8062 { 8063 if (rtwdev->io->unpack) 8064 return rtwdev->io->unpack(rtwdev); 8065 8066 return 0; 8067 } 8068 8069 static inline void rtw89_io_udelay(struct rtw89_dev *rtwdev, u32 us) 8070 { 8071 if (rtwdev->io->do_udelay) 8072 rtwdev->io->do_udelay(rtwdev, us); 8073 else 8074 udelay(us); 8075 } 8076 8077 static inline void rtw89_io_mdelay(struct rtw89_dev *rtwdev, u32 ms) 8078 { 8079 if (rtwdev->io->do_mdelay) 8080 rtwdev->io->do_mdelay(rtwdev, ms); 8081 else 8082 mdelay(ms); 8083 } 8084 8085 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 8086 { 8087 return rtwdev->hci.ops->read8(rtwdev, addr); 8088 } 8089 8090 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 8091 { 8092 return rtwdev->hci.ops->read16(rtwdev, addr); 8093 } 8094 8095 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 8096 { 8097 return rtwdev->hci.ops->read32(rtwdev, addr); 8098 } 8099 8100 static inline void rtw89_raw_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 8101 { 8102 rtwdev->hci.ops->write8(rtwdev, addr, data); 8103 } 8104 8105 static inline void rtw89_raw_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 8106 { 8107 rtwdev->hci.ops->write16(rtwdev, addr, data); 8108 } 8109 8110 static inline void rtw89_raw_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 8111 { 8112 rtwdev->hci.ops->write32(rtwdev, addr, data); 8113 } 8114 8115 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 8116 { 8117 rtwdev->io->write8(rtwdev, addr, data); 8118 } 8119 8120 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 8121 { 8122 rtwdev->io->write16(rtwdev, addr, data); 8123 } 8124 8125 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 8126 { 8127 rtwdev->io->write32(rtwdev, addr, data); 8128 } 8129 8130 static inline void 8131 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 8132 { 8133 u8 val; 8134 8135 val = rtw89_read8(rtwdev, addr); 8136 rtw89_write8(rtwdev, addr, val | bit); 8137 } 8138 8139 static inline void 8140 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 8141 { 8142 u16 val; 8143 8144 val = rtw89_read16(rtwdev, addr); 8145 rtw89_write16(rtwdev, addr, val | bit); 8146 } 8147 8148 static inline void 8149 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 8150 { 8151 u32 val; 8152 8153 val = rtw89_read32(rtwdev, addr); 8154 rtw89_write32(rtwdev, addr, val | bit); 8155 } 8156 8157 static inline void 8158 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 8159 { 8160 u8 val; 8161 8162 val = rtw89_read8(rtwdev, addr); 8163 rtw89_write8(rtwdev, addr, val & ~bit); 8164 } 8165 8166 static inline void 8167 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 8168 { 8169 u16 val; 8170 8171 val = rtw89_read16(rtwdev, addr); 8172 rtw89_write16(rtwdev, addr, val & ~bit); 8173 } 8174 8175 static inline void 8176 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 8177 { 8178 u32 val; 8179 8180 val = rtw89_read32(rtwdev, addr); 8181 rtw89_write32(rtwdev, addr, val & ~bit); 8182 } 8183 8184 static inline u32 8185 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 8186 { 8187 u32 shift = __ffs(mask); 8188 u32 orig; 8189 u32 ret; 8190 8191 orig = rtw89_read32(rtwdev, addr); 8192 ret = (orig & mask) >> shift; 8193 8194 return ret; 8195 } 8196 8197 static inline u16 8198 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 8199 { 8200 u32 shift = __ffs(mask); 8201 u32 orig; 8202 u32 ret; 8203 8204 orig = rtw89_read16(rtwdev, addr); 8205 ret = (orig & mask) >> shift; 8206 8207 return ret; 8208 } 8209 8210 static inline u8 8211 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 8212 { 8213 u32 shift = __ffs(mask); 8214 u32 orig; 8215 u32 ret; 8216 8217 orig = rtw89_read8(rtwdev, addr); 8218 ret = (orig & mask) >> shift; 8219 8220 return ret; 8221 } 8222 8223 static inline void 8224 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 8225 { 8226 u32 shift = __ffs(mask); 8227 u32 orig; 8228 u32 set; 8229 8230 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 8231 8232 orig = rtw89_read32(rtwdev, addr); 8233 set = (orig & ~mask) | ((data << shift) & mask); 8234 rtw89_write32(rtwdev, addr, set); 8235 } 8236 8237 static inline void 8238 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 8239 { 8240 u32 shift; 8241 u16 orig, set; 8242 8243 mask &= 0xffff; 8244 shift = __ffs(mask); 8245 8246 orig = rtw89_read16(rtwdev, addr); 8247 set = (orig & ~mask) | ((data << shift) & mask); 8248 rtw89_write16(rtwdev, addr, set); 8249 } 8250 8251 static inline void 8252 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 8253 { 8254 u32 shift; 8255 u8 orig, set; 8256 8257 mask &= 0xff; 8258 shift = __ffs(mask); 8259 8260 orig = rtw89_read8(rtwdev, addr); 8261 set = (orig & ~mask) | ((data << shift) & mask); 8262 rtw89_write8(rtwdev, addr, set); 8263 } 8264 8265 static inline u32 8266 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 8267 u32 addr, u32 mask) 8268 { 8269 lockdep_assert_wiphy(rtwdev->hw->wiphy); 8270 8271 return rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 8272 } 8273 8274 static inline void 8275 rtw89_raw_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 8276 u32 addr, u32 mask, u32 data) 8277 { 8278 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 8279 } 8280 8281 static inline void 8282 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 8283 u32 addr, u32 mask, u32 data) 8284 { 8285 lockdep_assert_wiphy(rtwdev->hw->wiphy); 8286 8287 rtwdev->io->write_rf(rtwdev, rf_path, addr, mask, data); 8288 } 8289 8290 static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr) 8291 { 8292 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE || 8293 !rtwdev->hci.ops->read32_pci_cfg) 8294 return RTW89_R32_EA; 8295 8296 return rtwdev->hci.ops->read32_pci_cfg(rtwdev, addr); 8297 } 8298 8299 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 8300 { 8301 void *p = rtwtxq; 8302 8303 return container_of(p, struct ieee80211_txq, drv_priv); 8304 } 8305 8306 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 8307 struct ieee80211_txq *txq) 8308 { 8309 struct rtw89_txq *rtwtxq; 8310 8311 if (!txq) 8312 return; 8313 8314 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 8315 INIT_LIST_HEAD(&rtwtxq->list); 8316 } 8317 8318 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 8319 { 8320 void *p = rtwvif; 8321 8322 return container_of(p, struct ieee80211_vif, drv_priv); 8323 } 8324 8325 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 8326 { 8327 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 8328 } 8329 8330 static inline 8331 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 8332 { 8333 return rtwvif_to_vif(rtwvif_link->rtwvif); 8334 } 8335 8336 static inline 8337 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 8338 { 8339 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 8340 } 8341 8342 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 8343 { 8344 return (struct rtw89_vif *)vif->drv_priv; 8345 } 8346 8347 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 8348 { 8349 return vif ? vif_to_rtwvif(vif) : NULL; 8350 } 8351 8352 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 8353 { 8354 void *p = rtwsta; 8355 8356 return container_of(p, struct ieee80211_sta, drv_priv); 8357 } 8358 8359 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 8360 { 8361 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 8362 } 8363 8364 static inline 8365 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 8366 { 8367 return rtwsta_to_sta(rtwsta_link->rtwsta); 8368 } 8369 8370 static inline 8371 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 8372 { 8373 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 8374 } 8375 8376 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 8377 { 8378 return (struct rtw89_sta *)sta->drv_priv; 8379 } 8380 8381 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 8382 { 8383 return sta ? sta_to_rtwsta(sta) : NULL; 8384 } 8385 8386 static inline struct ieee80211_bss_conf * 8387 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 8388 { 8389 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 8390 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 8391 struct rtw89_link_conf_container *snap; 8392 struct ieee80211_bss_conf *bss_conf; 8393 8394 snap = rcu_dereference(rtwvif->snap_link_confs); 8395 if (snap) { 8396 bss_conf = snap->link_conf[rtwvif_link->link_id]; 8397 goto out; 8398 } 8399 8400 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 8401 8402 out: 8403 if (unlikely(!bss_conf)) { 8404 *nolink = true; 8405 return &vif->bss_conf; 8406 } 8407 8408 *nolink = false; 8409 return bss_conf; 8410 } 8411 8412 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 8413 ({ \ 8414 typeof(rtwvif_link) p = rtwvif_link; \ 8415 struct ieee80211_bss_conf *bss_conf; \ 8416 bool nolink; \ 8417 \ 8418 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 8419 if (unlikely(nolink) && (assert)) \ 8420 rtw89_err(p->rtwvif->rtwdev, \ 8421 "%s: cannot find exact bss_conf for link_id %u\n",\ 8422 __func__, p->link_id); \ 8423 bss_conf; \ 8424 }) 8425 8426 static inline struct ieee80211_link_sta * 8427 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 8428 { 8429 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 8430 struct ieee80211_link_sta *link_sta; 8431 8432 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 8433 if (unlikely(!link_sta)) { 8434 *nolink = true; 8435 return &sta->deflink; 8436 } 8437 8438 *nolink = false; 8439 return link_sta; 8440 } 8441 8442 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 8443 ({ \ 8444 typeof(rtwsta_link) p = rtwsta_link; \ 8445 struct ieee80211_link_sta *link_sta; \ 8446 bool nolink; \ 8447 \ 8448 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 8449 if (unlikely(nolink) && (assert)) \ 8450 rtw89_err(p->rtwsta->rtwdev, \ 8451 "%s: cannot find exact link_sta for link_id %u\n",\ 8452 __func__, p->link_id); \ 8453 link_sta; \ 8454 }) 8455 8456 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 8457 { 8458 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 8459 return RATE_INFO_BW_160; 8460 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 8461 return RATE_INFO_BW_80; 8462 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 8463 return RATE_INFO_BW_40; 8464 else 8465 return RATE_INFO_BW_20; 8466 } 8467 8468 static inline 8469 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 8470 { 8471 switch (hw_band) { 8472 default: 8473 case RTW89_BAND_2G: 8474 return NL80211_BAND_2GHZ; 8475 case RTW89_BAND_5G: 8476 return NL80211_BAND_5GHZ; 8477 case RTW89_BAND_6G: 8478 return NL80211_BAND_6GHZ; 8479 } 8480 } 8481 8482 static inline 8483 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 8484 { 8485 switch (nl_band) { 8486 default: 8487 case NL80211_BAND_2GHZ: 8488 return RTW89_BAND_2G; 8489 case NL80211_BAND_5GHZ: 8490 return RTW89_BAND_5G; 8491 case NL80211_BAND_6GHZ: 8492 return RTW89_BAND_6G; 8493 } 8494 } 8495 8496 static inline 8497 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 8498 { 8499 switch (width) { 8500 default: 8501 WARN(1, "Not support bandwidth %d\n", width); 8502 fallthrough; 8503 case NL80211_CHAN_WIDTH_20_NOHT: 8504 case NL80211_CHAN_WIDTH_20: 8505 return RTW89_CHANNEL_WIDTH_20; 8506 case NL80211_CHAN_WIDTH_40: 8507 return RTW89_CHANNEL_WIDTH_40; 8508 case NL80211_CHAN_WIDTH_80: 8509 return RTW89_CHANNEL_WIDTH_80; 8510 case NL80211_CHAN_WIDTH_160: 8511 return RTW89_CHANNEL_WIDTH_160; 8512 } 8513 } 8514 8515 static inline 8516 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 8517 { 8518 switch (rua) { 8519 default: 8520 WARN(1, "Invalid RU allocation: %d\n", rua); 8521 fallthrough; 8522 case 0 ... 36: 8523 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 8524 case 37 ... 52: 8525 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 8526 case 53 ... 60: 8527 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 8528 case 61 ... 64: 8529 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 8530 case 65 ... 66: 8531 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 8532 case 67: 8533 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 8534 case 68: 8535 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 8536 } 8537 } 8538 8539 static inline 8540 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 8541 struct rtw89_sta_link *rtwsta_link) 8542 { 8543 if (rtwsta_link) { 8544 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 8545 8546 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 8547 return &rtwsta_link->addr_cam; 8548 } 8549 return &rtwvif_link->addr_cam; 8550 } 8551 8552 static inline 8553 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 8554 struct rtw89_sta_link *rtwsta_link) 8555 { 8556 if (rtwsta_link) { 8557 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 8558 8559 if (sta->tdls) 8560 return &rtwsta_link->bssid_cam; 8561 } 8562 return &rtwvif_link->bssid_cam; 8563 } 8564 8565 static inline 8566 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 8567 struct rtw89_channel_help_params *p, 8568 const struct rtw89_chan *chan, 8569 enum rtw89_mac_idx mac_idx, 8570 enum rtw89_phy_idx phy_idx) 8571 { 8572 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 8573 mac_idx, phy_idx); 8574 } 8575 8576 static inline 8577 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 8578 struct rtw89_channel_help_params *p, 8579 const struct rtw89_chan *chan, 8580 enum rtw89_mac_idx mac_idx, 8581 enum rtw89_phy_idx phy_idx) 8582 { 8583 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 8584 mac_idx, phy_idx); 8585 } 8586 8587 static inline 8588 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 8589 enum rtw89_chanctx_idx idx) 8590 { 8591 struct rtw89_hal *hal = &rtwdev->hal; 8592 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 8593 8594 if (roc_idx == idx) 8595 return &hal->roc_chandef; 8596 8597 return &hal->chanctx[idx].chandef; 8598 } 8599 8600 static inline 8601 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 8602 enum rtw89_chanctx_idx idx) 8603 { 8604 struct rtw89_hal *hal = &rtwdev->hal; 8605 8606 return &hal->chanctx[idx].chan; 8607 } 8608 8609 static inline 8610 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 8611 enum rtw89_chanctx_idx idx) 8612 { 8613 struct rtw89_hal *hal = &rtwdev->hal; 8614 8615 return &hal->chanctx[idx].rcd; 8616 } 8617 8618 static inline 8619 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 8620 { 8621 const struct rtw89_chanctx *chanctx = 8622 container_of_const(chan, struct rtw89_chanctx, chan); 8623 8624 return &chanctx->rcd; 8625 } 8626 8627 static inline 8628 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 8629 { 8630 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 8631 8632 if (rtwvif_link) 8633 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 8634 else 8635 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 8636 } 8637 8638 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 8639 { 8640 const struct rtw89_chip_info *chip = rtwdev->chip; 8641 8642 if (chip->ops->fem_setup) 8643 chip->ops->fem_setup(rtwdev); 8644 } 8645 8646 static inline int rtw89_chip_data_setup(struct rtw89_dev *rtwdev) 8647 { 8648 const struct rtw89_chip_info *chip = rtwdev->chip; 8649 8650 if (!chip->ops->data_setup) 8651 return 0; 8652 8653 return chip->ops->data_setup(rtwdev); 8654 } 8655 8656 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 8657 { 8658 const struct rtw89_chip_info *chip = rtwdev->chip; 8659 8660 if (chip->ops->rfe_gpio) 8661 chip->ops->rfe_gpio(rtwdev); 8662 } 8663 8664 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 8665 { 8666 const struct rtw89_chip_info *chip = rtwdev->chip; 8667 8668 if (chip->ops->rfk_hw_init) 8669 chip->ops->rfk_hw_init(rtwdev); 8670 } 8671 8672 static inline 8673 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev) 8674 { 8675 const struct rtw89_chip_info *chip = rtwdev->chip; 8676 8677 if (!chip->ops->bb_preinit) 8678 return; 8679 8680 chip->ops->bb_preinit(rtwdev, RTW89_PHY_0); 8681 8682 if (rtwdev->dbcc_en) 8683 chip->ops->bb_preinit(rtwdev, RTW89_PHY_1); 8684 } 8685 8686 static inline 8687 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 8688 { 8689 const struct rtw89_chip_info *chip = rtwdev->chip; 8690 8691 if (!chip->ops->bb_postinit) 8692 return; 8693 8694 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 8695 8696 if (rtwdev->dbcc_en) 8697 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 8698 } 8699 8700 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 8701 { 8702 const struct rtw89_chip_info *chip = rtwdev->chip; 8703 8704 rtw89_io_pack(rtwdev); 8705 8706 if (chip->ops->bb_sethw) 8707 chip->ops->bb_sethw(rtwdev); 8708 8709 rtw89_io_unpack(rtwdev); 8710 } 8711 8712 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 8713 { 8714 const struct rtw89_chip_info *chip = rtwdev->chip; 8715 8716 if (chip->ops->rfk_init) 8717 chip->ops->rfk_init(rtwdev); 8718 } 8719 8720 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 8721 { 8722 const struct rtw89_chip_info *chip = rtwdev->chip; 8723 8724 if (chip->ops->rfk_init_late) 8725 chip->ops->rfk_init_late(rtwdev); 8726 } 8727 8728 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 8729 enum rtw89_phy_idx phy_idx, 8730 const struct rtw89_chan *chan) 8731 { 8732 const struct rtw89_chip_info *chip = rtwdev->chip; 8733 8734 if (chip->ops->rfk_band_changed) 8735 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 8736 } 8737 8738 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 8739 struct rtw89_vif_link *rtwvif_link, bool start) 8740 { 8741 const struct rtw89_chip_info *chip = rtwdev->chip; 8742 8743 if (chip->ops->rfk_scan) 8744 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 8745 } 8746 8747 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 8748 { 8749 const struct rtw89_chip_info *chip = rtwdev->chip; 8750 8751 if (chip->ops->rfk_track) 8752 chip->ops->rfk_track(rtwdev); 8753 } 8754 8755 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 8756 { 8757 const struct rtw89_chip_info *chip = rtwdev->chip; 8758 8759 if (!chip->ops->set_txpwr_ctrl) 8760 return; 8761 8762 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 8763 if (rtwdev->dbcc_en) 8764 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 8765 } 8766 8767 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 8768 { 8769 const struct rtw89_chip_info *chip = rtwdev->chip; 8770 8771 if (chip->ops->power_trim) 8772 chip->ops->power_trim(rtwdev); 8773 } 8774 8775 static inline void rtw89_chip_path_diff_update(struct rtw89_dev *rtwdev, 8776 struct rtw89_bb_ctx *bb) 8777 { 8778 const struct rtw89_chip_info *chip = rtwdev->chip; 8779 8780 if (chip->ops->path_diff_update) 8781 chip->ops->path_diff_update(rtwdev, bb); 8782 } 8783 8784 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 8785 enum rtw89_phy_idx phy_idx) 8786 { 8787 const struct rtw89_chip_info *chip = rtwdev->chip; 8788 8789 if (chip->ops->init_txpwr_unit) 8790 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 8791 } 8792 8793 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 8794 { 8795 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 8796 if (rtwdev->dbcc_en) 8797 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 8798 } 8799 8800 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 8801 enum rtw89_rf_path rf_path) 8802 { 8803 const struct rtw89_chip_info *chip = rtwdev->chip; 8804 8805 if (!chip->ops->get_thermal) 8806 return 0x10; 8807 8808 return chip->ops->get_thermal(rtwdev, rf_path); 8809 } 8810 8811 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev, 8812 const struct rtw89_chan *chan) 8813 { 8814 const struct rtw89_chip_info *chip = rtwdev->chip; 8815 8816 if (!chip->ops->chan_to_rf18_val) 8817 return 0; 8818 8819 return chip->ops->chan_to_rf18_val(rtwdev, chan); 8820 } 8821 8822 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 8823 struct rtw89_rx_phy_ppdu *phy_ppdu, 8824 struct ieee80211_rx_status *status) 8825 { 8826 const struct rtw89_chip_info *chip = rtwdev->chip; 8827 8828 if (chip->ops->query_ppdu) 8829 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 8830 } 8831 8832 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 8833 struct rtw89_rx_phy_ppdu *phy_ppdu) 8834 { 8835 const struct rtw89_chip_info *chip = rtwdev->chip; 8836 8837 if (chip->ops->convert_rpl_to_rssi) 8838 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 8839 } 8840 8841 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 8842 struct rtw89_rx_desc_info *desc_info, 8843 struct ieee80211_rx_status *rx_status) 8844 { 8845 const struct rtw89_chip_info *chip = rtwdev->chip; 8846 8847 if (chip->ops->phy_rpt_to_rssi) 8848 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 8849 } 8850 8851 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 8852 enum rtw89_phy_idx phy_idx) 8853 { 8854 const struct rtw89_chip_info *chip = rtwdev->chip; 8855 8856 if (chip->ops->ctrl_nbtg_bt_tx) 8857 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 8858 } 8859 8860 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 8861 { 8862 const struct rtw89_chip_info *chip = rtwdev->chip; 8863 8864 if (chip->ops->cfg_txrx_path) 8865 chip->ops->cfg_txrx_path(rtwdev); 8866 } 8867 8868 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 8869 enum rtw89_phy_idx phy_idx) 8870 { 8871 const struct rtw89_chip_info *chip = rtwdev->chip; 8872 8873 if (chip->ops->digital_pwr_comp) 8874 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 8875 } 8876 8877 static inline 8878 void rtw89_chip_calc_rx_gain_normal(struct rtw89_dev *rtwdev, 8879 const struct rtw89_chan *chan, 8880 enum rtw89_rf_path path, 8881 enum rtw89_phy_idx phy_idx, 8882 struct rtw89_phy_calc_efuse_gain *calc) 8883 { 8884 const struct rtw89_chip_info *chip = rtwdev->chip; 8885 8886 if (chip->ops->calc_rx_gain_normal) 8887 chip->ops->calc_rx_gain_normal(rtwdev, chan, path, phy_idx, calc); 8888 } 8889 8890 static inline const struct rtw89_fw_def * 8891 __rtw89_chip_get_fw_def(const struct rtw89_chip_info *chip, 8892 const struct rtw89_chip_variant *variant) 8893 { 8894 if (variant && variant->fw_def_override) 8895 return variant->fw_def_override; 8896 8897 return &chip->fw_def; 8898 } 8899 8900 static inline 8901 const struct rtw89_fw_def *rtw89_chip_get_fw_def(struct rtw89_dev *rtwdev) 8902 { 8903 return __rtw89_chip_get_fw_def(rtwdev->chip, rtwdev->variant); 8904 } 8905 8906 static inline 8907 const struct rtw89_qta_def *rtw89_chip_get_qta_def(struct rtw89_dev *rtwdev) 8908 { 8909 const struct rtw89_chip_variant *variant = rtwdev->variant; 8910 8911 if (variant && variant->qta_def_override) 8912 return variant->qta_def_override; 8913 8914 return &rtwdev->chip->qta_def; 8915 } 8916 8917 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 8918 const struct rtw89_txpwr_table *tbl) 8919 { 8920 tbl->load(rtwdev, tbl); 8921 } 8922 8923 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 8924 { 8925 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 8926 const struct rtw89_regd *regd = regulatory->regd; 8927 u8 txpwr_regd = regd->txpwr_regd[band]; 8928 8929 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK) 8930 return RTW89_ETSI; 8931 8932 return txpwr_regd; 8933 } 8934 8935 static inline u8 rtw89_get_tx_shape_idx(struct rtw89_dev *rtwdev, u8 band, 8936 enum rtw89_rate_section rs) 8937 { 8938 struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 8939 const struct rtw89_rfe_parms *rfe_parms = rtwdev->rfe_parms; 8940 const struct rtw89_tx_shape *tx_shape = &rfe_parms->tx_shape; 8941 u8 reg6_pwr = regulatory->reg_6ghz_power; 8942 u8 regd = rtw89_regd_get(rtwdev, band); 8943 8944 if (unlikely(rs >= RTW89_RS_TX_SHAPE_NUM)) 8945 rs = RTW89_RS_OFDM; 8946 8947 if (!tx_shape->lmt) 8948 goto v0; 8949 8950 if (band != RTW89_BAND_6G) 8951 reg6_pwr = RTW89_REG_6GHZ_POWER_DFLT; 8952 8953 return (*tx_shape->lmt)[band][rs][regd][reg6_pwr]; 8954 8955 v0: 8956 return (*tx_shape->lmt_v0)[band][rs][regd]; 8957 } 8958 8959 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 8960 enum rtw89_phy_idx phy_idx) 8961 { 8962 const struct rtw89_chip_info *chip = rtwdev->chip; 8963 8964 if (chip->ops->ctrl_btg_bt_rx) 8965 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 8966 } 8967 8968 static inline 8969 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 8970 struct rtw89_rx_desc_info *desc_info, 8971 u8 *data, u32 data_offset) 8972 { 8973 const struct rtw89_chip_info *chip = rtwdev->chip; 8974 8975 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 8976 } 8977 8978 static inline 8979 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 8980 struct rtw89_tx_desc_info *desc_info, 8981 void *txdesc) 8982 { 8983 const struct rtw89_chip_info *chip = rtwdev->chip; 8984 8985 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 8986 } 8987 8988 static inline 8989 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 8990 struct rtw89_tx_desc_info *desc_info, 8991 void *txdesc) 8992 { 8993 const struct rtw89_chip_info *chip = rtwdev->chip; 8994 8995 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 8996 } 8997 8998 static inline 8999 u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 9000 { 9001 const struct rtw89_chip_info *chip = rtwdev->chip; 9002 9003 return chip->ops->get_ch_dma[rtwdev->hci.type](rtwdev, qsel); 9004 } 9005 9006 static inline 9007 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 9008 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 9009 { 9010 const struct rtw89_chip_info *chip = rtwdev->chip; 9011 9012 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 9013 } 9014 9015 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 9016 { 9017 const struct rtw89_chip_info *chip = rtwdev->chip; 9018 9019 chip->ops->cfg_ctrl_path(rtwdev, wl); 9020 } 9021 9022 static inline 9023 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 9024 u32 *tx_en, enum rtw89_sch_tx_sel sel) 9025 { 9026 const struct rtw89_chip_info *chip = rtwdev->chip; 9027 9028 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 9029 } 9030 9031 static inline 9032 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 9033 { 9034 const struct rtw89_chip_info *chip = rtwdev->chip; 9035 9036 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 9037 } 9038 9039 static inline 9040 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 9041 struct rtw89_vif_link *rtwvif_link, 9042 struct rtw89_sta_link *rtwsta_link) 9043 { 9044 const struct rtw89_chip_info *chip = rtwdev->chip; 9045 9046 if (!chip->ops->h2c_dctl_sec_cam) 9047 return 0; 9048 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 9049 } 9050 9051 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 9052 { 9053 __le16 fc = hdr->frame_control; 9054 9055 if (ieee80211_has_tods(fc)) 9056 return hdr->addr1; 9057 else if (ieee80211_has_fromds(fc)) 9058 return hdr->addr2; 9059 else 9060 return hdr->addr3; 9061 } 9062 9063 static inline 9064 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 9065 { 9066 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 9067 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 9068 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 9069 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 9070 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 9071 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 9072 return true; 9073 return false; 9074 } 9075 9076 static inline 9077 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 9078 { 9079 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 9080 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 9081 return true; 9082 9083 return false; 9084 } 9085 9086 static inline 9087 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 9088 { 9089 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 9090 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 9091 return true; 9092 9093 return false; 9094 } 9095 9096 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 9097 enum rtw89_fw_type type) 9098 { 9099 struct rtw89_fw_info *fw_info = &rtwdev->fw; 9100 9101 switch (type) { 9102 case RTW89_FW_WOWLAN: 9103 case RTW89_FW_WOWLAN_B: 9104 return &fw_info->wowlan; 9105 case RTW89_FW_LOGFMT: 9106 return &fw_info->log.suit; 9107 case RTW89_FW_BBMCU0: 9108 return &fw_info->bbmcu0; 9109 case RTW89_FW_BBMCU1: 9110 return &fw_info->bbmcu1; 9111 default: 9112 break; 9113 } 9114 9115 return &fw_info->normal; 9116 } 9117 9118 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 9119 unsigned int length) 9120 { 9121 struct sk_buff *skb; 9122 9123 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 9124 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 9125 if (!skb) 9126 return NULL; 9127 9128 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 9129 return skb; 9130 } 9131 9132 return dev_alloc_skb(length); 9133 } 9134 9135 static inline bool rtw89_core_is_tx_wait(struct rtw89_dev *rtwdev, 9136 struct rtw89_tx_skb_data *skb_data) 9137 { 9138 return rcu_access_pointer(skb_data->wait); 9139 } 9140 9141 static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 9142 struct rtw89_tx_skb_data *skb_data, 9143 u8 tx_status) 9144 { 9145 struct rtw89_tx_wait_info *wait; 9146 9147 guard(rcu)(); 9148 9149 wait = rcu_dereference(skb_data->wait); 9150 if (!wait) 9151 return false; 9152 9153 wait->tx_done = tx_status == RTW89_TX_DONE; 9154 /* Don't access skb anymore after completion */ 9155 complete_all(&wait->completion); 9156 return true; 9157 } 9158 9159 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 9160 { 9161 switch (rtwdev->mlo_dbcc_mode) { 9162 case MLO_1_PLUS_1_1RF: 9163 case MLO_1_PLUS_1_2RF: 9164 case DBCC_LEGACY: 9165 return true; 9166 default: 9167 return false; 9168 } 9169 } 9170 9171 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 9172 { 9173 if (!rtwdev->dbcc_en) 9174 return BIT(RTW89_PHY_0); 9175 9176 switch (rtwdev->mlo_dbcc_mode) { 9177 case MLO_0_PLUS_2_1RF: 9178 case MLO_0_PLUS_2_2RF: 9179 return BIT(RTW89_PHY_1); 9180 case MLO_1_PLUS_1_1RF: 9181 case MLO_1_PLUS_1_2RF: 9182 case MLO_2_PLUS_2_2RF: 9183 case DBCC_LEGACY: 9184 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 9185 case MLO_2_PLUS_0_1RF: 9186 case MLO_2_PLUS_0_2RF: 9187 default: 9188 return BIT(RTW89_PHY_0); 9189 } 9190 } 9191 9192 #define rtw89_for_each_active_bb(rtwdev, bb) \ 9193 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 9194 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 9195 if (__active_bb_bitmap & BIT(__phy_idx) && \ 9196 (bb = &rtwdev->bbs[__phy_idx])) 9197 9198 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 9199 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 9200 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 9201 if ((bb = &rtwdev->bbs[__phy_idx])) 9202 9203 static inline 9204 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 9205 enum rtw89_phy_idx phy_idx) 9206 { 9207 if (phy_idx >= RTW89_PHY_NUM) 9208 return &rtwdev->bbs[RTW89_PHY_0]; 9209 9210 return &rtwdev->bbs[phy_idx]; 9211 } 9212 9213 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 9214 { 9215 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 9216 9217 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 9218 return true; 9219 9220 return false; 9221 } 9222 9223 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval) 9224 { 9225 switch (interval) { 9226 default: 9227 case RTW89_TFC_INTERVAL_2SEC: 9228 return bytes >> 18; /* bytes/2s --> Mbps */; 9229 case RTW89_TFC_INTERVAL_100MS: 9230 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */ 9231 } 9232 } 9233 9234 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 9235 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 9236 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 9237 struct sk_buff *skb, bool fwdl); 9238 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 9239 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 9240 struct rtw89_tx_wait_info *wait, int qsel, 9241 unsigned int timeout); 9242 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 9243 struct rtw89_tx_desc_info *desc_info, 9244 void *txdesc); 9245 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 9246 struct rtw89_tx_desc_info *desc_info, 9247 void *txdesc); 9248 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 9249 struct rtw89_tx_desc_info *desc_info, 9250 void *txdesc); 9251 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev, 9252 struct rtw89_tx_desc_info *desc_info, 9253 void *txdesc); 9254 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 9255 struct rtw89_tx_desc_info *desc_info, 9256 void *txdesc); 9257 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 9258 struct rtw89_tx_desc_info *desc_info, 9259 void *txdesc); 9260 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel); 9261 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel); 9262 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel); 9263 void rtw89_core_rx(struct rtw89_dev *rtwdev, 9264 struct rtw89_rx_desc_info *desc_info, 9265 struct sk_buff *skb); 9266 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 9267 struct rtw89_rx_desc_info *desc_info, 9268 u8 *data, u32 data_offset); 9269 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 9270 struct rtw89_rx_desc_info *desc_info, 9271 u8 *data, u32 data_offset); 9272 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev, 9273 struct rtw89_rx_desc_info *desc_info, 9274 u8 *data, u32 data_offset); 9275 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 9276 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 9277 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 9278 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 9279 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 9280 struct rtw89_vif_link *rtwvif_link, 9281 struct rtw89_sta_link *rtwsta_link); 9282 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 9283 struct rtw89_vif_link *rtwvif_link, 9284 struct rtw89_sta_link *rtwsta_link); 9285 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 9286 struct rtw89_vif_link *rtwvif_link, 9287 struct rtw89_sta_link *rtwsta_link); 9288 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 9289 struct rtw89_vif_link *rtwvif_link, 9290 struct rtw89_sta_link *rtwsta_link); 9291 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 9292 struct rtw89_vif_link *rtwvif_link, 9293 struct rtw89_sta_link *rtwsta_link); 9294 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 9295 struct ieee80211_sta *sta, 9296 struct cfg80211_tid_config *tid_config); 9297 void rtw89_core_tid_rx_stats_ctrl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 9298 struct ieee80211_ampdu_params *params, bool enable); 9299 void rtw89_core_tid_rx_stats_reset(struct rtw89_dev *rtwdev); 9300 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 9301 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 9302 int rtw89_core_init(struct rtw89_dev *rtwdev); 9303 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 9304 int rtw89_core_register(struct rtw89_dev *rtwdev); 9305 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 9306 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 9307 u32 bus_data_size, 9308 const struct rtw89_driver_info *info); 9309 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 9310 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 9311 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 9312 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 9313 u8 mac_id, u8 port); 9314 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 9315 struct rtw89_sta *rtwsta, u8 mac_id); 9316 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 9317 unsigned int link_id); 9318 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 9319 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 9320 unsigned int link_id); 9321 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 9322 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 9323 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 9324 struct rtw89_vif_link *rtwvif_link); 9325 const struct rtw89_6ghz_span * 9326 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 9327 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 9328 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 9329 struct rtw89_chan *chan); 9330 int rtw89_set_channel(struct rtw89_dev *rtwdev); 9331 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 9332 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 9333 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 9334 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 9335 struct rtw89_sta_link *rtwsta_link, u8 tid, 9336 u8 *cam_idx); 9337 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 9338 struct rtw89_sta_link *rtwsta_link, u8 tid, 9339 u8 *cam_idx); 9340 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 9341 struct ieee80211_sta *sta); 9342 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 9343 struct ieee80211_sta *sta); 9344 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 9345 struct ieee80211_sta *sta); 9346 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 9347 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 9348 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 9349 struct rtw89_vif_link *rtwvif_link); 9350 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate); 9351 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 9352 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 9353 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 9354 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 9355 struct rtw89_traffic_stats *stats); 9356 struct rtw89_wait_response * 9357 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 9358 __acquires(rtw89_wait); 9359 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 9360 struct rtw89_wait_response *prep, int err) 9361 __releases(rtw89_wait); 9362 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 9363 const struct rtw89_completion_data *data); 9364 int rtw89_core_start(struct rtw89_dev *rtwdev); 9365 void rtw89_core_stop(struct rtw89_dev *rtwdev); 9366 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 9367 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 9368 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 9369 bool qos, bool ps, int timeout); 9370 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 9371 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 9372 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 9373 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 9374 const u8 *mac_addr, bool hw_scan); 9375 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 9376 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 9377 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 9378 bool active); 9379 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 9380 struct rtw89_vif_link *rtwvif_link, 9381 struct ieee80211_bss_conf *bss_conf); 9382 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, 9383 enum rtw89_btc_hmsg event, 9384 enum rtw89_phy_idx phy_idx); 9385 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 9386 unsigned int link_id); 9387 void rtw89_core_dm_disable_cfg(struct rtw89_dev *rtwdev, u32 new); 9388 void rtw89_core_dm_disable_set(struct rtw89_dev *rtwdev, enum rtw89_dm_type type); 9389 void rtw89_core_dm_disable_clr(struct rtw89_dev *rtwdev, enum rtw89_dm_type type); 9390 9391 #endif 9392