1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_usb_info; 19 struct rtw89_mac_gen_def; 20 struct rtw89_phy_gen_def; 21 struct rtw89_fw_blacklist; 22 struct rtw89_efuse_block_cfg; 23 struct rtw89_h2c_rf_tssi; 24 struct rtw89_fw_txpwr_track_cfg; 25 struct rtw89_phy_rfk_log_fmt; 26 struct rtw89_phy_calc_efuse_gain; 27 struct rtw89_debugfs; 28 struct rtw89_regd_data; 29 struct rtw89_wow_cam_info; 30 31 extern const struct ieee80211_ops rtw89_ops; 32 33 #define MASKBYTE0 0xff 34 #define MASKBYTE1 0xff00 35 #define MASKBYTE2 0xff0000 36 #define MASKBYTE3 0xff000000 37 #define MASKBYTE4 0xff00000000ULL 38 #define MASKHWORD 0xffff0000 39 #define MASKLWORD 0x0000ffff 40 #define MASKDWORD 0xffffffff 41 #define RFREG_MASK 0xfffff 42 #define INV_RF_DATA 0xffffffff 43 #define BYPASS_CR_DATA 0xbabecafe 44 #define RTW89_R32_EA 0xEAEAEAEA 45 #define RTW89_R32_DEAD 0xDEADBEEF 46 47 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 48 #define RTW89_TRACK_PS_WORK_PERIOD msecs_to_jiffies(100) 49 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 50 #define RTW89_PS_HANG_MAX_CNT 3 51 #define CFO_TRACK_MAX_USER 64 52 #define MAX_RSSI 110 53 #define RSSI_FACTOR 1 54 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 55 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 56 #define DELTA_SWINGIDX_SIZE 30 57 58 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 59 #define RTW89_RADIOTAP_ROOM_EHT \ 60 (sizeof(struct ieee80211_radiotap_tlv) + \ 61 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 62 sizeof(struct ieee80211_radiotap_tlv) + \ 63 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 64 #define RTW89_RADIOTAP_ROOM \ 65 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 66 67 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 68 #define RTW89_HTC_VARIANT_HE 3 69 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 70 #define RTW89_HTC_VARIANT_HE_CID_OM 1 71 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 72 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 73 74 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 75 enum htc_om_channel_width { 76 HTC_OM_CHANNEL_WIDTH_20 = 0, 77 HTC_OM_CHANNEL_WIDTH_40 = 1, 78 HTC_OM_CHANNEL_WIDTH_80 = 2, 79 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 80 }; 81 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 82 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 83 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 84 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 85 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 86 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 87 88 #define RTW89_TF_PAD GENMASK(11, 0) 89 #define RTW89_TF_BASIC_USER_INFO_SZ 6 90 91 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 92 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 93 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 94 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 95 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 96 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 97 98 enum rtw89_subband { 99 RTW89_CH_2G = 0, 100 RTW89_CH_5G_BAND_1 = 1, 101 /* RTW89_CH_5G_BAND_2 = 2, unused */ 102 RTW89_CH_5G_BAND_3 = 3, 103 RTW89_CH_5G_BAND_4 = 4, 104 105 RTW89_CH_6G_BAND_IDX0, /* Low */ 106 RTW89_CH_6G_BAND_IDX1, /* Low */ 107 RTW89_CH_6G_BAND_IDX2, /* Mid */ 108 RTW89_CH_6G_BAND_IDX3, /* Mid */ 109 RTW89_CH_6G_BAND_IDX4, /* High */ 110 RTW89_CH_6G_BAND_IDX5, /* High */ 111 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 112 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 113 114 RTW89_SUBBAND_NR, 115 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 116 }; 117 118 enum rtw89_tx_comp_band { 119 RTW89_TX_COMP_BAND_2GHZ, 120 RTW89_TX_COMP_BAND_5GHZ_L, 121 RTW89_TX_COMP_BAND_5GHZ_H, 122 RTW89_TX_COMP_BAND_6GHZ_M, 123 RTW89_TX_COMP_BAND_6GHZ_UH, 124 125 RTW89_TX_COMP_BAND_NR, 126 }; 127 128 enum rtw89_gain_offset { 129 RTW89_GAIN_OFFSET_2G_CCK, 130 RTW89_GAIN_OFFSET_2G_OFDM, 131 RTW89_GAIN_OFFSET_5G_LOW, 132 RTW89_GAIN_OFFSET_5G_MID, 133 RTW89_GAIN_OFFSET_5G_HIGH, 134 RTW89_GAIN_OFFSET_6G_L0, 135 RTW89_GAIN_OFFSET_6G_L1, 136 RTW89_GAIN_OFFSET_6G_M0, 137 RTW89_GAIN_OFFSET_6G_M1, 138 RTW89_GAIN_OFFSET_6G_H0, 139 RTW89_GAIN_OFFSET_6G_H1, 140 RTW89_GAIN_OFFSET_6G_UH0, 141 RTW89_GAIN_OFFSET_6G_UH1, 142 143 RTW89_GAIN_OFFSET_NR, 144 }; 145 146 enum rtw89_hci_type { 147 RTW89_HCI_TYPE_PCIE, 148 RTW89_HCI_TYPE_USB, 149 RTW89_HCI_TYPE_SDIO, 150 151 RTW89_HCI_TYPE_NUM, 152 }; 153 154 enum rtw89_hci_dle_type { 155 RTW89_HCI_DLE_TYPE_PCIE, 156 RTW89_HCI_DLE_TYPE_USB2, 157 RTW89_HCI_DLE_TYPE_USB3, 158 RTW89_HCI_DLE_TYPE_SDIO, 159 160 RTW89_HCI_DLE_TYPE_NUM, 161 }; 162 163 enum rtw89_core_chip_id { 164 RTL8852A, 165 RTL8852B, 166 RTL8852BT, 167 RTL8852C, 168 RTL8851B, 169 RTL8922A, 170 RTL8922D, 171 }; 172 173 enum rtw89_core_chip_cid { 174 RTL8922D_CID7025 = 0x74, 175 RTL8922D_CID7090 = 0x79, 176 }; 177 178 enum rtw89_core_chip_aid { 179 RTL8922D_AID1348 = 0x1348, 180 RTL8922D_AID7060 = 0x7060, 181 RTL8922D_AID7102 = 0x7102, 182 }; 183 184 enum rtw89_chip_gen { 185 RTW89_CHIP_AX, 186 RTW89_CHIP_BE, 187 188 RTW89_CHIP_GEN_NUM, 189 }; 190 191 enum rtw89_cv { 192 CHIP_CAV, 193 CHIP_CBV, 194 CHIP_CCV, 195 CHIP_CDV, 196 CHIP_CEV, 197 CHIP_CFV, 198 CHIP_CV_MAX, 199 CHIP_CV_INVALID = CHIP_CV_MAX, 200 }; 201 202 enum rtw89_bacam_ver { 203 RTW89_BACAM_V0, 204 RTW89_BACAM_V1, 205 206 RTW89_BACAM_V0_EXT = 99, 207 }; 208 209 enum rtw89_core_tx_type { 210 RTW89_CORE_TX_TYPE_DATA, 211 RTW89_CORE_TX_TYPE_MGMT, 212 RTW89_CORE_TX_TYPE_FWCMD, 213 }; 214 215 enum rtw89_core_rx_type { 216 RTW89_CORE_RX_TYPE_WIFI = 0, 217 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 218 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 219 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 220 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 221 RTW89_CORE_RX_TYPE_SS2FW = 5, 222 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 223 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 224 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 225 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 226 RTW89_CORE_RX_TYPE_C2H = 10, 227 RTW89_CORE_RX_TYPE_CSI = 11, 228 RTW89_CORE_RX_TYPE_CQI = 12, 229 RTW89_CORE_RX_TYPE_H2C = 13, 230 RTW89_CORE_RX_TYPE_FWDL = 14, 231 }; 232 233 enum rtw89_txq_flags { 234 RTW89_TXQ_F_AMPDU = 0, 235 RTW89_TXQ_F_BLOCK_BA = 1, 236 RTW89_TXQ_F_FORBID_BA = 2, 237 }; 238 239 enum rtw89_net_type { 240 RTW89_NET_TYPE_NO_LINK = 0, 241 RTW89_NET_TYPE_AD_HOC = 1, 242 RTW89_NET_TYPE_INFRA = 2, 243 RTW89_NET_TYPE_AP_MODE = 3, 244 }; 245 246 enum rtw89_wifi_role { 247 RTW89_WIFI_ROLE_NONE, 248 RTW89_WIFI_ROLE_STATION, 249 RTW89_WIFI_ROLE_AP, 250 RTW89_WIFI_ROLE_AP_VLAN, 251 RTW89_WIFI_ROLE_ADHOC, 252 RTW89_WIFI_ROLE_ADHOC_MASTER, 253 RTW89_WIFI_ROLE_MESH_POINT, 254 RTW89_WIFI_ROLE_MONITOR, 255 RTW89_WIFI_ROLE_P2P_DEVICE, 256 RTW89_WIFI_ROLE_P2P_CLIENT, 257 RTW89_WIFI_ROLE_P2P_GO, 258 RTW89_WIFI_ROLE_NAN, 259 RTW89_WIFI_ROLE_MLME_MAX 260 }; 261 262 enum rtw89_upd_mode { 263 RTW89_ROLE_CREATE, 264 RTW89_ROLE_REMOVE, 265 RTW89_ROLE_TYPE_CHANGE, 266 RTW89_ROLE_INFO_CHANGE, 267 RTW89_ROLE_CON_DISCONN, 268 RTW89_ROLE_BAND_SW, 269 RTW89_ROLE_FW_RESTORE, 270 }; 271 272 enum rtw89_self_role { 273 RTW89_SELF_ROLE_CLIENT, 274 RTW89_SELF_ROLE_AP, 275 RTW89_SELF_ROLE_AP_CLIENT 276 }; 277 278 enum rtw89_msk_sO_el { 279 RTW89_NO_MSK, 280 RTW89_SMA, 281 RTW89_TMA, 282 RTW89_BSSID 283 }; 284 285 enum rtw89_sch_tx_sel { 286 RTW89_SCH_TX_SEL_ALL, 287 RTW89_SCH_TX_SEL_HIQ, 288 RTW89_SCH_TX_SEL_MG0, 289 RTW89_SCH_TX_SEL_MACID, 290 }; 291 292 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 293 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 294 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 295 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 296 */ 297 enum rtw89_add_cam_sec_mode { 298 RTW89_ADDR_CAM_SEC_NONE = 0, 299 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 300 RTW89_ADDR_CAM_SEC_NORMAL = 2, 301 RTW89_ADDR_CAM_SEC_4GROUP = 3, 302 }; 303 304 enum rtw89_sec_key_type { 305 RTW89_SEC_KEY_TYPE_NONE = 0, 306 RTW89_SEC_KEY_TYPE_WEP40 = 1, 307 RTW89_SEC_KEY_TYPE_WEP104 = 2, 308 RTW89_SEC_KEY_TYPE_TKIP = 3, 309 RTW89_SEC_KEY_TYPE_WAPI = 4, 310 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 311 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 312 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 313 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 314 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 315 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 316 }; 317 318 enum rtw89_port { 319 RTW89_PORT_0 = 0, 320 RTW89_PORT_1 = 1, 321 RTW89_PORT_2 = 2, 322 RTW89_PORT_3 = 3, 323 RTW89_PORT_4 = 4, 324 RTW89_PORT_NUM 325 }; 326 327 enum rtw89_band { 328 RTW89_BAND_2G = 0, 329 RTW89_BAND_5G = 1, 330 RTW89_BAND_6G = 2, 331 RTW89_BAND_NUM, 332 }; 333 334 enum rtw89_hw_rate { 335 RTW89_HW_RATE_CCK1 = 0x0, 336 RTW89_HW_RATE_CCK2 = 0x1, 337 RTW89_HW_RATE_CCK5_5 = 0x2, 338 RTW89_HW_RATE_CCK11 = 0x3, 339 RTW89_HW_RATE_OFDM6 = 0x4, 340 RTW89_HW_RATE_OFDM9 = 0x5, 341 RTW89_HW_RATE_OFDM12 = 0x6, 342 RTW89_HW_RATE_OFDM18 = 0x7, 343 RTW89_HW_RATE_OFDM24 = 0x8, 344 RTW89_HW_RATE_OFDM36 = 0x9, 345 RTW89_HW_RATE_OFDM48 = 0xA, 346 RTW89_HW_RATE_OFDM54 = 0xB, 347 RTW89_HW_RATE_MCS0 = 0x80, 348 RTW89_HW_RATE_MCS1 = 0x81, 349 RTW89_HW_RATE_MCS2 = 0x82, 350 RTW89_HW_RATE_MCS3 = 0x83, 351 RTW89_HW_RATE_MCS4 = 0x84, 352 RTW89_HW_RATE_MCS5 = 0x85, 353 RTW89_HW_RATE_MCS6 = 0x86, 354 RTW89_HW_RATE_MCS7 = 0x87, 355 RTW89_HW_RATE_MCS8 = 0x88, 356 RTW89_HW_RATE_MCS9 = 0x89, 357 RTW89_HW_RATE_MCS10 = 0x8A, 358 RTW89_HW_RATE_MCS11 = 0x8B, 359 RTW89_HW_RATE_MCS12 = 0x8C, 360 RTW89_HW_RATE_MCS13 = 0x8D, 361 RTW89_HW_RATE_MCS14 = 0x8E, 362 RTW89_HW_RATE_MCS15 = 0x8F, 363 RTW89_HW_RATE_MCS16 = 0x90, 364 RTW89_HW_RATE_MCS17 = 0x91, 365 RTW89_HW_RATE_MCS18 = 0x92, 366 RTW89_HW_RATE_MCS19 = 0x93, 367 RTW89_HW_RATE_MCS20 = 0x94, 368 RTW89_HW_RATE_MCS21 = 0x95, 369 RTW89_HW_RATE_MCS22 = 0x96, 370 RTW89_HW_RATE_MCS23 = 0x97, 371 RTW89_HW_RATE_MCS24 = 0x98, 372 RTW89_HW_RATE_MCS25 = 0x99, 373 RTW89_HW_RATE_MCS26 = 0x9A, 374 RTW89_HW_RATE_MCS27 = 0x9B, 375 RTW89_HW_RATE_MCS28 = 0x9C, 376 RTW89_HW_RATE_MCS29 = 0x9D, 377 RTW89_HW_RATE_MCS30 = 0x9E, 378 RTW89_HW_RATE_MCS31 = 0x9F, 379 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 380 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 381 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 382 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 383 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 384 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 385 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 386 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 387 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 388 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 389 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 390 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 391 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 392 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 393 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 394 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 395 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 396 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 397 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 398 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 399 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 400 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 401 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 402 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 403 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 404 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 405 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 406 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 407 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 408 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 409 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 410 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 411 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 412 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 413 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 414 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 415 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 416 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 417 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 418 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 419 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 420 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 421 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 422 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 423 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 424 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 425 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 426 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 427 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 428 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 429 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 430 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 431 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 432 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 433 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 434 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 435 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 436 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 437 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 438 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 439 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 440 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 441 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 442 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 443 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 444 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 445 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 446 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 447 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 448 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 449 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 450 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 451 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 452 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 453 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 454 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 455 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 456 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 457 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 458 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 459 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 460 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 461 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 462 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 463 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 464 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 465 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 466 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 467 468 RTW89_HW_RATE_V1_MCS0 = 0x100, 469 RTW89_HW_RATE_V1_MCS1 = 0x101, 470 RTW89_HW_RATE_V1_MCS2 = 0x102, 471 RTW89_HW_RATE_V1_MCS3 = 0x103, 472 RTW89_HW_RATE_V1_MCS4 = 0x104, 473 RTW89_HW_RATE_V1_MCS5 = 0x105, 474 RTW89_HW_RATE_V1_MCS6 = 0x106, 475 RTW89_HW_RATE_V1_MCS7 = 0x107, 476 RTW89_HW_RATE_V1_MCS8 = 0x108, 477 RTW89_HW_RATE_V1_MCS9 = 0x109, 478 RTW89_HW_RATE_V1_MCS10 = 0x10A, 479 RTW89_HW_RATE_V1_MCS11 = 0x10B, 480 RTW89_HW_RATE_V1_MCS12 = 0x10C, 481 RTW89_HW_RATE_V1_MCS13 = 0x10D, 482 RTW89_HW_RATE_V1_MCS14 = 0x10E, 483 RTW89_HW_RATE_V1_MCS15 = 0x10F, 484 RTW89_HW_RATE_V1_MCS16 = 0x110, 485 RTW89_HW_RATE_V1_MCS17 = 0x111, 486 RTW89_HW_RATE_V1_MCS18 = 0x112, 487 RTW89_HW_RATE_V1_MCS19 = 0x113, 488 RTW89_HW_RATE_V1_MCS20 = 0x114, 489 RTW89_HW_RATE_V1_MCS21 = 0x115, 490 RTW89_HW_RATE_V1_MCS22 = 0x116, 491 RTW89_HW_RATE_V1_MCS23 = 0x117, 492 RTW89_HW_RATE_V1_MCS24 = 0x118, 493 RTW89_HW_RATE_V1_MCS25 = 0x119, 494 RTW89_HW_RATE_V1_MCS26 = 0x11A, 495 RTW89_HW_RATE_V1_MCS27 = 0x11B, 496 RTW89_HW_RATE_V1_MCS28 = 0x11C, 497 RTW89_HW_RATE_V1_MCS29 = 0x11D, 498 RTW89_HW_RATE_V1_MCS30 = 0x11E, 499 RTW89_HW_RATE_V1_MCS31 = 0x11F, 500 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 501 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 502 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 503 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 504 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 505 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 506 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 507 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 508 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 509 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 510 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 511 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 512 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 513 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 514 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 515 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 516 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 517 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 518 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 519 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 520 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 521 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 522 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 523 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 524 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 525 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 526 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 527 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 528 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 529 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 530 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 531 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 532 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 533 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 534 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 535 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 536 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 537 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 538 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 539 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 540 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 541 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 542 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 543 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 544 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 545 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 546 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 547 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 548 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 549 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 550 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 551 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 552 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 553 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 554 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 555 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 556 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 557 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 558 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 559 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 560 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 561 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 562 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 563 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 564 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 565 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 566 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 567 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 568 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 569 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 570 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 571 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 572 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 573 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 574 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 575 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 576 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 577 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 578 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 579 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 580 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 581 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 582 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 583 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 584 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 585 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 586 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 587 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 588 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 589 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 590 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 591 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 592 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 593 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 594 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 595 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 596 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 597 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 598 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 599 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 600 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 601 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 602 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 603 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 604 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 605 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 606 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 607 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 608 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 609 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 610 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 611 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 612 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 613 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 614 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 615 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 616 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 617 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 618 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 619 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 620 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 621 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 622 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 623 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 624 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 625 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 626 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 627 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 628 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 629 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 630 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 631 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 632 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 633 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 634 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 635 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 636 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 637 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 638 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 639 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 640 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 641 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 642 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 643 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 644 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 645 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 646 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 647 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 648 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 649 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 650 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 651 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 652 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 653 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 654 655 RTW89_HW_RATE_NR, 656 RTW89_HW_RATE_INVAL, 657 658 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 659 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 660 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 661 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 662 }; 663 664 /* 2G channels, 665 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 666 */ 667 #define RTW89_2G_CH_NUM 14 668 669 /* 5G channels, 670 * 36, 38, 40, 42, 44, 46, 48, 50, 671 * 52, 54, 56, 58, 60, 62, 64, 672 * 100, 102, 104, 106, 108, 110, 112, 114, 673 * 116, 118, 120, 122, 124, 126, 128, 130, 674 * 132, 134, 136, 138, 140, 142, 144, 675 * 149, 151, 153, 155, 157, 159, 161, 163, 676 * 165, 167, 169, 171, 173, 175, 177 677 */ 678 #define RTW89_5G_CH_NUM 53 679 680 /* 6G channels, 681 * 1, 3, 5, 7, 9, 11, 13, 15, 682 * 17, 19, 21, 23, 25, 27, 29, 33, 683 * 35, 37, 39, 41, 43, 45, 47, 49, 684 * 51, 53, 55, 57, 59, 61, 65, 67, 685 * 69, 71, 73, 75, 77, 79, 81, 83, 686 * 85, 87, 89, 91, 93, 97, 99, 101, 687 * 103, 105, 107, 109, 111, 113, 115, 117, 688 * 119, 121, 123, 125, 129, 131, 133, 135, 689 * 137, 139, 141, 143, 145, 147, 149, 151, 690 * 153, 155, 157, 161, 163, 165, 167, 169, 691 * 171, 173, 175, 177, 179, 181, 183, 185, 692 * 187, 189, 193, 195, 197, 199, 201, 203, 693 * 205, 207, 209, 211, 213, 215, 217, 219, 694 * 221, 225, 227, 229, 231, 233, 235, 237, 695 * 239, 241, 243, 245, 247, 249, 251, 253, 696 */ 697 #define RTW89_6G_CH_NUM 120 698 699 enum rtw89_rate_section { 700 RTW89_RS_CCK, 701 RTW89_RS_OFDM, 702 RTW89_RS_MCS, /* for HT/VHT/HE */ 703 RTW89_RS_HEDCM, 704 RTW89_RS_OFFSET, 705 RTW89_RS_NUM, 706 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 707 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 708 }; 709 710 enum rtw89_rate_offset_indexes { 711 RTW89_RATE_OFFSET_HE, 712 RTW89_RATE_OFFSET_VHT, 713 RTW89_RATE_OFFSET_HT, 714 RTW89_RATE_OFFSET_OFDM, 715 RTW89_RATE_OFFSET_CCK, 716 RTW89_RATE_OFFSET_DLRU_EHT, 717 RTW89_RATE_OFFSET_DLRU_HE, 718 RTW89_RATE_OFFSET_EHT, 719 __RTW89_RATE_OFFSET_NUM, 720 721 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 722 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 723 }; 724 725 enum rtw89_rate_num { 726 RTW89_RATE_CCK_NUM = 4, 727 RTW89_RATE_OFDM_NUM = 8, 728 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 729 730 RTW89_RATE_MCS_NUM_AX = 12, 731 RTW89_RATE_MCS_NUM_BE = 16, 732 __RTW89_RATE_MCS_NUM = 16, 733 }; 734 735 enum rtw89_nss { 736 RTW89_NSS_1 = 0, 737 RTW89_NSS_2 = 1, 738 /* HE DCM only support 1ss and 2ss */ 739 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 740 RTW89_NSS_3 = 2, 741 RTW89_NSS_4 = 3, 742 RTW89_NSS_NUM, 743 }; 744 745 enum rtw89_ntx { 746 RTW89_1TX = 0, 747 RTW89_2TX = 1, 748 RTW89_NTX_NUM, 749 }; 750 751 enum rtw89_beamforming_type { 752 RTW89_NONBF = 0, 753 RTW89_BF = 1, 754 RTW89_BF_NUM, 755 }; 756 757 enum rtw89_ofdma_type { 758 RTW89_NON_OFDMA = 0, 759 RTW89_OFDMA = 1, 760 RTW89_OFDMA_NUM, 761 }; 762 763 /* neither insert new in the middle, nor change any given definition */ 764 enum rtw89_regulation_type { 765 RTW89_WW = 0, 766 RTW89_ETSI = 1, 767 RTW89_FCC = 2, 768 RTW89_MKK = 3, 769 RTW89_NA = 4, 770 RTW89_IC = 5, 771 RTW89_KCC = 6, 772 RTW89_ACMA = 7, 773 RTW89_NCC = 8, 774 RTW89_MEXICO = 9, 775 RTW89_CHILE = 10, 776 RTW89_UKRAINE = 11, 777 RTW89_CN = 12, 778 RTW89_QATAR = 13, 779 RTW89_UK = 14, 780 RTW89_THAILAND = 15, 781 RTW89_REGD_NUM, 782 }; 783 784 enum rtw89_reg_6ghz_power { 785 RTW89_REG_6GHZ_POWER_VLP = 0, 786 RTW89_REG_6GHZ_POWER_LPI = 1, 787 RTW89_REG_6GHZ_POWER_STD = 2, 788 789 NUM_OF_RTW89_REG_6GHZ_POWER, 790 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 791 }; 792 793 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 794 795 /* calculate based on ieee80211 Transmit Power Envelope */ 796 struct rtw89_reg_6ghz_tpe { 797 bool valid; 798 s8 constraint; /* unit: dBm */ 799 }; 800 801 enum rtw89_fw_pkt_ofld_type { 802 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 803 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 804 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 805 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 806 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 807 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 808 RTW89_PKT_OFLD_TYPE_NDP = 6, 809 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 810 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 811 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 812 RTW89_PKT_OFLD_TYPE_NUM, 813 }; 814 815 struct rtw89_txpwr_byrate { 816 s8 cck[RTW89_RATE_CCK_NUM]; 817 s8 ofdm[RTW89_RATE_OFDM_NUM]; 818 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 819 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 820 s8 offset[__RTW89_RATE_OFFSET_NUM]; 821 s8 trap; 822 }; 823 824 struct rtw89_rate_desc { 825 enum rtw89_nss nss; 826 enum rtw89_rate_section rs; 827 enum rtw89_ofdma_type ofdma; 828 u8 idx; 829 }; 830 831 #define PHY_STS_HDR_LEN 8 832 #define RF_PATH_MAX 4 833 #define RTW89_MAX_PPDU_CNT 8 834 struct rtw89_rx_phy_ppdu { 835 void *buf; 836 u32 len; 837 u8 rssi_avg; 838 u8 rssi[RF_PATH_MAX]; 839 u8 mac_id; 840 u8 chan_idx; 841 u8 phy_idx; 842 u8 ie; 843 u16 rate; 844 u8 rpl_avg; 845 u8 rpl_path[RF_PATH_MAX]; 846 u8 rpl_fd[RF_PATH_MAX]; 847 u8 bw_idx; 848 u8 rx_path_en; 849 struct { 850 bool has; 851 u8 avg_snr; 852 u8 evm_max; 853 u8 evm_min; 854 } ofdm; 855 bool has_data; 856 bool has_bcn; 857 bool ldpc; 858 bool stbc; 859 bool to_self; 860 bool valid; 861 bool hdr_2_en; 862 }; 863 864 enum rtw89_mac_idx { 865 RTW89_MAC_0 = 0, 866 RTW89_MAC_1 = 1, 867 RTW89_MAC_NUM, 868 }; 869 870 enum rtw89_phy_idx { 871 RTW89_PHY_0 = 0, 872 RTW89_PHY_1 = 1, 873 RTW89_PHY_NUM, 874 }; 875 876 #define __RTW89_MLD_MAX_LINK_NUM 2 877 #define RTW89_MLD_NON_STA_LINK_NUM 1 878 879 enum rtw89_chanctx_idx { 880 RTW89_CHANCTX_0 = 0, 881 RTW89_CHANCTX_1 = 1, 882 883 NUM_OF_RTW89_CHANCTX, 884 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 885 }; 886 887 enum rtw89_rf_path { 888 RF_PATH_A = 0, 889 RF_PATH_B = 1, 890 RF_PATH_C = 2, 891 RF_PATH_D = 3, 892 RF_PATH_AB, 893 RF_PATH_AC, 894 RF_PATH_AD, 895 RF_PATH_BC, 896 RF_PATH_BD, 897 RF_PATH_CD, 898 RF_PATH_ABC, 899 RF_PATH_ABD, 900 RF_PATH_ACD, 901 RF_PATH_BCD, 902 RF_PATH_ABCD, 903 }; 904 905 enum rtw89_rf_path_bit { 906 RF_A = BIT(0), 907 RF_B = BIT(1), 908 RF_C = BIT(2), 909 RF_D = BIT(3), 910 911 RF_AB = (RF_A | RF_B), 912 RF_AC = (RF_A | RF_C), 913 RF_AD = (RF_A | RF_D), 914 RF_BC = (RF_B | RF_C), 915 RF_BD = (RF_B | RF_D), 916 RF_CD = (RF_C | RF_D), 917 918 RF_ABC = (RF_A | RF_B | RF_C), 919 RF_ABD = (RF_A | RF_B | RF_D), 920 RF_ACD = (RF_A | RF_C | RF_D), 921 RF_BCD = (RF_B | RF_C | RF_D), 922 923 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 924 }; 925 926 enum rtw89_bandwidth { 927 RTW89_CHANNEL_WIDTH_20 = 0, 928 RTW89_CHANNEL_WIDTH_40 = 1, 929 RTW89_CHANNEL_WIDTH_80 = 2, 930 RTW89_CHANNEL_WIDTH_160 = 3, 931 RTW89_CHANNEL_WIDTH_320 = 4, 932 933 /* keep index order above */ 934 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 935 936 RTW89_CHANNEL_WIDTH_80_80 = 5, 937 RTW89_CHANNEL_WIDTH_5 = 6, 938 RTW89_CHANNEL_WIDTH_10 = 7, 939 }; 940 941 enum rtw89_ps_mode { 942 RTW89_PS_MODE_NONE = 0, 943 RTW89_PS_MODE_RFOFF = 1, 944 RTW89_PS_MODE_CLK_GATED = 2, 945 RTW89_PS_MODE_PWR_GATED = 3, 946 }; 947 948 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 949 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 950 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 951 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 952 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 953 954 enum rtw89_pe_duration { 955 RTW89_PE_DURATION_0 = 0, 956 RTW89_PE_DURATION_8 = 1, 957 RTW89_PE_DURATION_16 = 2, 958 RTW89_PE_DURATION_16_20 = 3, 959 }; 960 961 enum rtw89_ru_bandwidth { 962 RTW89_RU26 = 0, 963 RTW89_RU52 = 1, 964 RTW89_RU106 = 2, 965 RTW89_RU52_26 = 3, 966 RTW89_RU106_26 = 4, 967 RTW89_RU_NUM, 968 }; 969 970 enum rtw89_sc_offset { 971 RTW89_SC_DONT_CARE = 0, 972 RTW89_SC_20_UPPER = 1, 973 RTW89_SC_20_LOWER = 2, 974 RTW89_SC_20_UPMOST = 3, 975 RTW89_SC_20_LOWEST = 4, 976 RTW89_SC_20_UP2X = 5, 977 RTW89_SC_20_LOW2X = 6, 978 RTW89_SC_20_UP3X = 7, 979 RTW89_SC_20_LOW3X = 8, 980 RTW89_SC_40_UPPER = 9, 981 RTW89_SC_40_LOWER = 10, 982 }; 983 984 /* only mgd features can be added to the enum */ 985 enum rtw89_wow_flags { 986 RTW89_WOW_FLAG_EN_MAGIC_PKT, 987 RTW89_WOW_FLAG_EN_REKEY_PKT, 988 RTW89_WOW_FLAG_EN_DISCONNECT, 989 RTW89_WOW_FLAG_EN_PATTERN, 990 RTW89_WOW_FLAG_NUM, 991 }; 992 993 struct rtw89_chan { 994 u8 channel; 995 u8 primary_channel; 996 enum rtw89_band band_type; 997 enum rtw89_bandwidth band_width; 998 999 /* The follow-up are derived from the above. We must ensure that it 1000 * is assigned correctly in rtw89_chan_create() if new one is added. 1001 */ 1002 u32 freq; 1003 enum rtw89_subband subband_type; 1004 enum rtw89_tx_comp_band tx_comp_band; 1005 enum rtw89_sc_offset pri_ch_idx; 1006 u8 pri_sb_idx; 1007 }; 1008 1009 struct rtw89_chan_rcd { 1010 u8 prev_primary_channel; 1011 enum rtw89_band prev_band_type; 1012 bool band_changed; 1013 }; 1014 1015 struct rtw89_channel_help_params { 1016 u32 tx_en; 1017 }; 1018 1019 struct rtw89_port_reg { 1020 u32 port_cfg; 1021 u32 tbtt_prohib; 1022 u32 bcn_area; 1023 u32 bcn_early; 1024 u32 tbtt_early; 1025 u32 tbtt_agg; 1026 u32 bcn_space; 1027 u32 bcn_forcetx; 1028 u32 bcn_err_cnt; 1029 u32 bcn_err_flag; 1030 u32 dtim_ctrl; 1031 u32 tbtt_shift; 1032 u32 bcn_cnt_tmr; 1033 u32 tsftr_l; 1034 u32 tsftr_h; 1035 u32 md_tsft; 1036 u32 bss_color; 1037 u32 mbssid; 1038 u32 mbssid_drop; 1039 u32 tsf_sync; 1040 u32 ptcl_dbg; 1041 u32 ptcl_dbg_info; 1042 u32 bcn_drop_all; 1043 u32 bcn_psr_rpt; 1044 u32 hiq_win[RTW89_PORT_NUM]; 1045 }; 1046 1047 struct rtw89_txwd_body { 1048 __le32 dword0; 1049 __le32 dword1; 1050 __le32 dword2; 1051 __le32 dword3; 1052 __le32 dword4; 1053 __le32 dword5; 1054 } __packed; 1055 1056 struct rtw89_txwd_body_v1 { 1057 __le32 dword0; 1058 __le32 dword1; 1059 __le32 dword2; 1060 __le32 dword3; 1061 __le32 dword4; 1062 __le32 dword5; 1063 __le32 dword6; 1064 __le32 dword7; 1065 } __packed; 1066 1067 struct rtw89_txwd_body_v2 { 1068 __le32 dword0; 1069 __le32 dword1; 1070 __le32 dword2; 1071 __le32 dword3; 1072 __le32 dword4; 1073 __le32 dword5; 1074 __le32 dword6; 1075 __le32 dword7; 1076 } __packed; 1077 1078 struct rtw89_txwd_info { 1079 __le32 dword0; 1080 __le32 dword1; 1081 __le32 dword2; 1082 __le32 dword3; 1083 __le32 dword4; 1084 __le32 dword5; 1085 } __packed; 1086 1087 struct rtw89_txwd_info_v2 { 1088 __le32 dword0; 1089 __le32 dword1; 1090 __le32 dword2; 1091 __le32 dword3; 1092 __le32 dword4; 1093 __le32 dword5; 1094 __le32 dword6; 1095 __le32 dword7; 1096 } __packed; 1097 1098 struct rtw89_rx_desc_info { 1099 u16 pkt_size; 1100 u8 pkt_type; 1101 u8 drv_info_size; 1102 u8 phy_rpt_size; 1103 u8 hdr_cnv_size; 1104 u8 shift; 1105 u8 wl_hd_iv_len; 1106 bool long_rxdesc; 1107 bool bb_sel; 1108 bool mac_info_valid; 1109 u16 data_rate; 1110 u8 gi_ltf; 1111 u8 bw; 1112 u32 free_run_cnt; 1113 u8 user_id; 1114 bool sr_en; 1115 u8 ppdu_cnt; 1116 u8 ppdu_type; 1117 bool icv_err; 1118 bool crc32_err; 1119 bool hw_dec; 1120 bool sw_dec; 1121 bool addr1_match; 1122 u8 frag; 1123 u16 seq; 1124 u8 frame_type; 1125 u8 rx_pl_id; 1126 bool addr_cam_valid; 1127 u8 addr_cam_id; 1128 u8 sec_cam_id; 1129 u8 mac_id; 1130 u16 offset; 1131 u16 rxd_len; 1132 bool ready; 1133 u16 rssi; 1134 }; 1135 1136 struct rtw89_rxdesc_short { 1137 __le32 dword0; 1138 __le32 dword1; 1139 __le32 dword2; 1140 __le32 dword3; 1141 } __packed; 1142 1143 struct rtw89_rxdesc_short_v2 { 1144 __le32 dword0; 1145 __le32 dword1; 1146 __le32 dword2; 1147 __le32 dword3; 1148 __le32 dword4; 1149 __le32 dword5; 1150 } __packed; 1151 1152 struct rtw89_rxdesc_short_v3 { 1153 __le32 dword0; 1154 __le32 dword1; 1155 __le32 dword2; 1156 __le32 dword3; 1157 __le32 dword4; 1158 __le32 dword5; 1159 } __packed; 1160 1161 struct rtw89_rxdesc_long { 1162 __le32 dword0; 1163 __le32 dword1; 1164 __le32 dword2; 1165 __le32 dword3; 1166 __le32 dword4; 1167 __le32 dword5; 1168 __le32 dword6; 1169 __le32 dword7; 1170 } __packed; 1171 1172 struct rtw89_rxdesc_long_v2 { 1173 __le32 dword0; 1174 __le32 dword1; 1175 __le32 dword2; 1176 __le32 dword3; 1177 __le32 dword4; 1178 __le32 dword5; 1179 __le32 dword6; 1180 __le32 dword7; 1181 __le32 dword8; 1182 __le32 dword9; 1183 } __packed; 1184 1185 struct rtw89_rxdesc_long_v3 { 1186 __le32 dword0; 1187 __le32 dword1; 1188 __le32 dword2; 1189 __le32 dword3; 1190 __le32 dword4; 1191 __le32 dword5; 1192 __le32 dword6; 1193 __le32 dword7; 1194 __le32 dword8; 1195 __le32 dword9; 1196 } __packed; 1197 1198 struct rtw89_rxdesc_phy_rpt_v2 { 1199 __le32 dword0; 1200 __le32 dword1; 1201 } __packed; 1202 1203 struct rtw89_tx_desc_info { 1204 u16 pkt_size; 1205 u8 wp_offset; 1206 u8 mac_id; 1207 u8 qsel; 1208 u8 ch_dma; 1209 u8 hdr_llc_len; 1210 bool is_bmc; 1211 bool en_wd_info; 1212 bool wd_page; 1213 bool use_rate; 1214 bool dis_data_fb; 1215 bool tid_indicate; 1216 bool agg_en; 1217 bool bk; 1218 u8 ampdu_density; 1219 u8 ampdu_num; 1220 bool sec_en; 1221 bool report; 1222 bool tx_cnt_lmt_en; 1223 u8 sn: 4; 1224 u8 tx_cnt_lmt: 6; 1225 u8 addr_info_nr; 1226 u8 sec_keyid; 1227 u8 sec_type; 1228 u8 sec_cam_idx; 1229 u8 sec_seq[6]; 1230 u16 data_rate; 1231 u16 data_retry_lowest_rate; 1232 u8 data_bw; 1233 u8 gi_ltf; 1234 bool fw_dl; 1235 u16 seq; 1236 bool a_ctrl_bsr; 1237 u8 hw_ssn_sel; 1238 #define RTW89_MGMT_HW_SSN_SEL 1 1239 u8 hw_seq_mode; 1240 #define RTW89_MGMT_HW_SEQ_MODE 1 1241 bool hiq; 1242 u8 port; 1243 bool er_cap; 1244 bool stbc; 1245 bool ldpc; 1246 bool upd_wlan_hdr; 1247 bool mlo; 1248 bool sw_mld; 1249 }; 1250 1251 struct rtw89_core_tx_request { 1252 enum rtw89_core_tx_type tx_type; 1253 1254 struct sk_buff *skb; 1255 struct ieee80211_vif *vif; 1256 struct ieee80211_sta *sta; 1257 struct rtw89_vif_link *rtwvif_link; 1258 struct rtw89_sta_link *rtwsta_link; 1259 struct rtw89_tx_desc_info desc_info; 1260 1261 bool with_wait; 1262 }; 1263 1264 struct rtw89_txq { 1265 struct list_head list; 1266 unsigned long flags; 1267 int wait_cnt; 1268 }; 1269 1270 struct rtw89_mac_ax_gnt { 1271 u8 gnt_bt_sw_en; 1272 u8 gnt_bt; 1273 u8 gnt_wl_sw_en; 1274 u8 gnt_wl; 1275 } __packed; 1276 1277 struct rtw89_mac_ax_wl_act { 1278 u8 wlan_act_en; 1279 u8 wlan_act; 1280 } __packed; 1281 1282 #define RTW89_MAC_AX_COEX_GNT_NR 2 1283 struct rtw89_mac_ax_coex_gnt { 1284 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1285 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1286 }; 1287 1288 enum rtw89_btc_ncnt { 1289 BTC_NCNT_POWER_ON = 0x0, 1290 BTC_NCNT_POWER_OFF, 1291 BTC_NCNT_INIT_COEX, 1292 BTC_NCNT_SCAN_START, 1293 BTC_NCNT_SCAN_FINISH, 1294 BTC_NCNT_SPECIAL_PACKET, 1295 BTC_NCNT_SWITCH_BAND, 1296 BTC_NCNT_RFK_TIMEOUT, 1297 BTC_NCNT_SHOW_COEX_INFO, 1298 BTC_NCNT_ROLE_INFO, 1299 BTC_NCNT_CONTROL, 1300 BTC_NCNT_RADIO_STATE, 1301 BTC_NCNT_CUSTOMERIZE, 1302 BTC_NCNT_WL_RFK, 1303 BTC_NCNT_WL_STA, 1304 BTC_NCNT_WL_STA_LAST, 1305 BTC_NCNT_FWINFO, 1306 BTC_NCNT_TIMER, 1307 BTC_NCNT_SWITCH_CHBW, 1308 BTC_NCNT_RESUME_DL_FW, 1309 BTC_NCNT_COUNTRYCODE, 1310 BTC_NCNT_NUM, 1311 }; 1312 1313 enum rtw89_btc_btinfo { 1314 BTC_BTINFO_L0 = 0, 1315 BTC_BTINFO_L1, 1316 BTC_BTINFO_L2, 1317 BTC_BTINFO_L3, 1318 BTC_BTINFO_H0, 1319 BTC_BTINFO_H1, 1320 BTC_BTINFO_H2, 1321 BTC_BTINFO_H3, 1322 BTC_BTINFO_MAX 1323 }; 1324 1325 enum rtw89_btc_dcnt { 1326 BTC_DCNT_RUN = 0x0, 1327 BTC_DCNT_CX_RUNINFO, 1328 BTC_DCNT_RPT, 1329 BTC_DCNT_RPT_HANG, 1330 BTC_DCNT_CYCLE, 1331 BTC_DCNT_CYCLE_HANG, 1332 BTC_DCNT_W1, 1333 BTC_DCNT_W1_HANG, 1334 BTC_DCNT_B1, 1335 BTC_DCNT_B1_HANG, 1336 BTC_DCNT_TDMA_NONSYNC, 1337 BTC_DCNT_SLOT_NONSYNC, 1338 BTC_DCNT_BTCNT_HANG, 1339 BTC_DCNT_BTTX_HANG, 1340 BTC_DCNT_WL_SLOT_DRIFT, 1341 BTC_DCNT_WL_STA_LAST, 1342 BTC_DCNT_BT_SLOT_DRIFT, 1343 BTC_DCNT_BT_SLOT_FLOOD, 1344 BTC_DCNT_FDDT_TRIG, 1345 BTC_DCNT_E2G, 1346 BTC_DCNT_E2G_HANG, 1347 BTC_DCNT_WL_FW_VER_MATCH, 1348 BTC_DCNT_NULL_TX_FAIL, 1349 BTC_DCNT_WL_STA_NTFY, 1350 BTC_DCNT_NUM, 1351 }; 1352 1353 enum rtw89_btc_wl_state_cnt { 1354 BTC_WCNT_SCANAP = 0x0, 1355 BTC_WCNT_DHCP, 1356 BTC_WCNT_EAPOL, 1357 BTC_WCNT_ARP, 1358 BTC_WCNT_SCBDUPDATE, 1359 BTC_WCNT_RFK_REQ, 1360 BTC_WCNT_RFK_GO, 1361 BTC_WCNT_RFK_REJECT, 1362 BTC_WCNT_RFK_TIMEOUT, 1363 BTC_WCNT_CH_UPDATE, 1364 BTC_WCNT_DBCC_ALL_2G, 1365 BTC_WCNT_DBCC_CHG, 1366 BTC_WCNT_RX_OK_LAST, 1367 BTC_WCNT_RX_OK_LAST2S, 1368 BTC_WCNT_RX_ERR_LAST, 1369 BTC_WCNT_RX_ERR_LAST2S, 1370 BTC_WCNT_RX_LAST, 1371 BTC_WCNT_NUM 1372 }; 1373 1374 enum rtw89_btc_bt_state_cnt { 1375 BTC_BCNT_RETRY = 0x0, 1376 BTC_BCNT_REINIT, 1377 BTC_BCNT_REENABLE, 1378 BTC_BCNT_SCBDREAD, 1379 BTC_BCNT_RELINK, 1380 BTC_BCNT_IGNOWL, 1381 BTC_BCNT_INQPAG, 1382 BTC_BCNT_INQ, 1383 BTC_BCNT_PAGE, 1384 BTC_BCNT_ROLESW, 1385 BTC_BCNT_AFH, 1386 BTC_BCNT_INFOUPDATE, 1387 BTC_BCNT_INFOSAME, 1388 BTC_BCNT_SCBDUPDATE, 1389 BTC_BCNT_HIPRI_TX, 1390 BTC_BCNT_HIPRI_RX, 1391 BTC_BCNT_LOPRI_TX, 1392 BTC_BCNT_LOPRI_RX, 1393 BTC_BCNT_POLUT, 1394 BTC_BCNT_POLUT_NOW, 1395 BTC_BCNT_POLUT_DIFF, 1396 BTC_BCNT_RATECHG, 1397 BTC_BCNT_BTTXPWR_UPDATE, 1398 BTC_BCNT_NUM, 1399 }; 1400 1401 enum rtw89_btc_bt_profile { 1402 BTC_BT_NOPROFILE = 0, 1403 BTC_BT_HFP = BIT(0), 1404 BTC_BT_HID = BIT(1), 1405 BTC_BT_A2DP = BIT(2), 1406 BTC_BT_PAN = BIT(3), 1407 BTC_PROFILE_MAX = 4, 1408 }; 1409 1410 struct rtw89_btc_ant_info { 1411 u8 type; /* shared, dedicated */ 1412 u8 num; 1413 u8 isolation; 1414 1415 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1416 u8 diversity: 1; 1417 u8 btg_pos: 2; 1418 u8 stream_cnt: 4; 1419 }; 1420 1421 struct rtw89_btc_ant_info_v7 { 1422 u8 type; /* shared, dedicated(non-shared) */ 1423 u8 num; /* antenna count */ 1424 u8 isolation; 1425 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1426 1427 u8 diversity; /* only for wifi use 1-antenna */ 1428 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1429 u8 stream_cnt; /* spatial_stream count */ 1430 u8 rsvd; 1431 } __packed; 1432 1433 enum rtw89_tfc_dir { 1434 RTW89_TFC_UL, 1435 RTW89_TFC_DL, 1436 }; 1437 1438 struct rtw89_btc_wl_smap { 1439 u32 busy: 1; 1440 u32 scan: 1; 1441 u32 connecting: 1; 1442 u32 roaming: 1; 1443 u32 dbccing: 1; 1444 u32 _4way: 1; 1445 u32 rf_off: 1; 1446 u32 lps: 2; 1447 u32 ips: 1; 1448 u32 init_ok: 1; 1449 u32 traffic_dir : 2; 1450 u32 rf_off_pre: 1; 1451 u32 lps_pre: 2; 1452 u32 lps_exiting: 1; 1453 u32 emlsr: 1; 1454 }; 1455 1456 enum rtw89_tfc_interval { 1457 RTW89_TFC_INTERVAL_100MS, 1458 RTW89_TFC_INTERVAL_2SEC, 1459 }; 1460 1461 enum rtw89_tfc_lv { 1462 RTW89_TFC_IDLE, 1463 RTW89_TFC_ULTRA_LOW, 1464 RTW89_TFC_LOW, 1465 RTW89_TFC_MID, 1466 RTW89_TFC_HIGH, 1467 }; 1468 1469 DECLARE_EWMA(tp, 10, 2); 1470 1471 struct rtw89_traffic_stats { 1472 /* units in bytes */ 1473 u64 tx_unicast; 1474 u64 rx_unicast; 1475 u32 tx_avg_len; 1476 u32 rx_avg_len; 1477 1478 /* count for packets */ 1479 u64 tx_cnt; 1480 u64 rx_cnt; 1481 1482 /* units in Mbps */ 1483 u32 tx_throughput; 1484 u32 rx_throughput; 1485 u32 tx_throughput_raw; 1486 u32 rx_throughput_raw; 1487 1488 u32 rx_tf_acc; 1489 u32 rx_tf_periodic; 1490 1491 enum rtw89_tfc_lv tx_tfc_lv; 1492 enum rtw89_tfc_lv rx_tfc_lv; 1493 struct ewma_tp tx_ewma_tp; 1494 struct ewma_tp rx_ewma_tp; 1495 1496 u16 tx_rate; 1497 u16 rx_rate; 1498 }; 1499 1500 struct rtw89_btc_chdef { 1501 u8 center_ch; 1502 u8 band; 1503 u8 chan; 1504 enum rtw89_sc_offset offset; 1505 enum rtw89_bandwidth bw; 1506 }; 1507 1508 struct rtw89_btc_statistic { 1509 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1510 struct rtw89_traffic_stats traffic; 1511 }; 1512 1513 #define BTC_WL_RSSI_THMAX 4 1514 1515 struct rtw89_btc_wl_link_info { 1516 struct rtw89_btc_chdef chdef; 1517 struct rtw89_btc_statistic stat; 1518 enum rtw89_tfc_dir dir; 1519 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1520 u8 mac_addr[ETH_ALEN]; 1521 u8 busy; 1522 u8 ch; 1523 u8 bw; 1524 u8 band; 1525 u8 role; 1526 u8 pid; 1527 u8 phy; 1528 u8 dtim_period; 1529 u8 mode; 1530 u8 tx_1ss_limit; 1531 1532 u8 mac_id; 1533 u8 tx_retry; 1534 1535 u32 bcn_period; 1536 u32 busy_t; 1537 u32 tx_time; 1538 u32 client_cnt; 1539 u32 rx_rate_drop_cnt; 1540 u32 noa_duration; 1541 1542 u32 active: 1; 1543 u32 noa: 1; 1544 u32 client_ps: 1; 1545 u32 connected: 2; 1546 }; 1547 1548 union rtw89_btc_wl_state_map { 1549 u32 val; 1550 struct rtw89_btc_wl_smap map; 1551 }; 1552 1553 struct rtw89_btc_bt_hfp_desc { 1554 u32 exist: 1; 1555 u32 type: 2; 1556 u32 rsvd: 29; 1557 }; 1558 1559 struct rtw89_btc_bt_hid_desc { 1560 u32 exist: 1; 1561 u32 slot_info: 2; 1562 u32 pair_cnt: 2; 1563 u32 type: 8; 1564 u32 rsvd: 19; 1565 }; 1566 1567 struct rtw89_btc_bt_a2dp_desc { 1568 u8 exist: 1; 1569 u8 exist_last: 1; 1570 u8 play_latency: 1; 1571 u8 type: 3; 1572 u8 active: 1; 1573 u8 sink: 1; 1574 u32 handle_update: 1; 1575 u32 devinfo_query: 1; 1576 u32 no_empty_streak_2s: 8; 1577 u32 no_empty_streak_max: 8; 1578 u32 rsvd: 6; 1579 1580 u8 bitpool; 1581 u16 vendor_id; 1582 u32 device_name; 1583 u32 flush_time; 1584 }; 1585 1586 struct rtw89_btc_bt_pan_desc { 1587 u32 exist: 1; 1588 u32 type: 1; 1589 u32 active: 1; 1590 u32 rsvd: 29; 1591 }; 1592 1593 struct rtw89_btc_bt_rfk_info { 1594 u32 run: 1; 1595 u32 req: 1; 1596 u32 timeout: 1; 1597 u32 rsvd: 29; 1598 }; 1599 1600 union rtw89_btc_bt_rfk_info_map { 1601 u32 val; 1602 struct rtw89_btc_bt_rfk_info map; 1603 }; 1604 1605 struct rtw89_btc_bt_ver_info { 1606 u32 fw_coex; /* match with which coex_ver */ 1607 u32 fw; 1608 }; 1609 1610 struct rtw89_btc_bool_sta_chg { 1611 u32 now: 1; 1612 u32 last: 1; 1613 u32 remain: 1; 1614 u32 srvd: 29; 1615 }; 1616 1617 struct rtw89_btc_u8_sta_chg { 1618 u8 now; 1619 u8 last; 1620 u8 remain; 1621 u8 rsvd; 1622 }; 1623 1624 struct rtw89_btc_wl_scan_info { 1625 u8 band[RTW89_PHY_NUM]; 1626 u8 phy_map; 1627 u8 rsvd; 1628 }; 1629 1630 struct rtw89_btc_wl_dbcc_info { 1631 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1632 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1633 u8 real_band[RTW89_PHY_NUM]; 1634 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1635 }; 1636 1637 struct rtw89_btc_wl_mlo_info { 1638 u8 wmode[RTW89_PHY_NUM]; /* enum phl_mr_wmode */ 1639 u8 ch_type[RTW89_PHY_NUM]; /* enum phl_mr_ch_type */ 1640 u8 hwb_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for HW-band */ 1641 u8 path_rf_band[RTW89_PHY_NUM]; /* enum band_type, RF-band for PHY0/1 */ 1642 1643 u8 wtype; /* enum phl_mr_wtype */ 1644 u8 mrcx_mode; 1645 u8 mrcx_act_hwb_map; 1646 u8 mrcx_bt_slot_rsp; 1647 1648 u8 rf_combination; /* enum btc_mlo_rf_combin 0:2+0, 1:0+2, 2:1+1,3:2+2 */ 1649 u8 mlo_en; /* MLO enable */ 1650 u8 mlo_adie; /* a-die count */ 1651 u8 dual_hw_band_en; /* both 2 HW-band link exist */ 1652 1653 u32 link_status; /* enum mlo_dbcc_mode_type */ 1654 }; 1655 1656 struct rtw89_btc_wl_active_role { 1657 u8 connected: 1; 1658 u8 pid: 3; 1659 u8 phy: 1; 1660 u8 noa: 1; 1661 u8 band: 2; 1662 1663 u8 client_ps: 1; 1664 u8 bw: 7; 1665 1666 u8 role; 1667 u8 ch; 1668 1669 u16 tx_lvl; 1670 u16 rx_lvl; 1671 u16 tx_rate; 1672 u16 rx_rate; 1673 }; 1674 1675 struct rtw89_btc_wl_active_role_v1 { 1676 u8 connected: 1; 1677 u8 pid: 3; 1678 u8 phy: 1; 1679 u8 noa: 1; 1680 u8 band: 2; 1681 1682 u8 client_ps: 1; 1683 u8 bw: 7; 1684 1685 u8 role; 1686 u8 ch; 1687 1688 u16 tx_lvl; 1689 u16 rx_lvl; 1690 u16 tx_rate; 1691 u16 rx_rate; 1692 1693 u32 noa_duration; /* ms */ 1694 }; 1695 1696 struct rtw89_btc_wl_active_role_v2 { 1697 u8 connected: 1; 1698 u8 pid: 3; 1699 u8 phy: 1; 1700 u8 noa: 1; 1701 u8 band: 2; 1702 1703 u8 client_ps: 1; 1704 u8 bw: 7; 1705 1706 u8 role; 1707 u8 ch; 1708 1709 u32 noa_duration; /* ms */ 1710 }; 1711 1712 struct rtw89_btc_wl_active_role_v7 { 1713 u8 connected; 1714 u8 pid; 1715 u8 phy; 1716 u8 noa; 1717 1718 u8 band; 1719 u8 client_ps; 1720 u8 bw; 1721 u8 role; 1722 1723 u8 ch; 1724 u8 noa_dur; 1725 u8 client_cnt; 1726 u8 rsvd2; 1727 } __packed; 1728 1729 struct rtw89_btc_wl_role_info_bpos { 1730 u16 none: 1; 1731 u16 station: 1; 1732 u16 ap: 1; 1733 u16 vap: 1; 1734 u16 adhoc: 1; 1735 u16 adhoc_master: 1; 1736 u16 mesh: 1; 1737 u16 moniter: 1; 1738 u16 p2p_device: 1; 1739 u16 p2p_gc: 1; 1740 u16 p2p_go: 1; 1741 u16 nan: 1; 1742 }; 1743 1744 struct rtw89_btc_wl_scc_ctrl { 1745 u8 null_role1; 1746 u8 null_role2; 1747 u8 ebt_null; /* if tx null at EBT slot */ 1748 }; 1749 1750 union rtw89_btc_wl_role_info_map { 1751 u16 val; 1752 struct rtw89_btc_wl_role_info_bpos role; 1753 }; 1754 1755 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1756 u8 connect_cnt; 1757 u8 link_mode; 1758 union rtw89_btc_wl_role_info_map role_map; 1759 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1760 }; 1761 1762 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1763 u8 connect_cnt; 1764 u8 link_mode; 1765 union rtw89_btc_wl_role_info_map role_map; 1766 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1767 u32 mrole_type; /* btc_wl_mrole_type */ 1768 u32 mrole_noa_duration; /* ms */ 1769 1770 u32 dbcc_en: 1; 1771 u32 dbcc_chg: 1; 1772 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1773 u32 link_mode_chg: 1; 1774 u32 rsvd: 27; 1775 }; 1776 1777 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1778 u8 connect_cnt; 1779 u8 link_mode; 1780 union rtw89_btc_wl_role_info_map role_map; 1781 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1782 u32 mrole_type; /* btc_wl_mrole_type */ 1783 u32 mrole_noa_duration; /* ms */ 1784 1785 u32 dbcc_en: 1; 1786 u32 dbcc_chg: 1; 1787 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1788 u32 link_mode_chg: 1; 1789 u32 rsvd: 27; 1790 }; 1791 1792 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1793 u8 connected; 1794 u8 pid; 1795 u8 phy; 1796 u8 noa; 1797 1798 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1799 u8 active; /* 0:rlink is under doze */ 1800 u8 bw; /* enum channel_width */ 1801 u8 role; /*enum role_type */ 1802 1803 u8 ch; 1804 u8 noa_dur; /* ms */ 1805 u8 client_cnt; /* for Role = P2P-Go/AP */ 1806 u8 mode; /* wifi protocol */ 1807 } __packed; 1808 1809 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1810 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1811 u8 connect_cnt; 1812 u8 link_mode; 1813 u8 link_mode_chg; 1814 u8 p2p_2g; 1815 1816 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1817 1818 u32 role_map; 1819 u32 mrole_type; /* btc_wl_mrole_type */ 1820 u32 mrole_noa_duration; /* ms */ 1821 u32 dbcc_en; 1822 u32 dbcc_chg; 1823 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1824 } __packed; 1825 1826 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1827 u8 connect_cnt; 1828 u8 link_mode; 1829 u8 link_mode_chg; 1830 u8 p2p_2g; 1831 1832 u8 pta_req_band; 1833 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1834 u8 dbcc_chg; 1835 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1836 1837 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1838 1839 u32 role_map; 1840 u32 mrole_type; /* btc_wl_mrole_type */ 1841 u32 mrole_noa_duration; /* ms */ 1842 } __packed; 1843 1844 struct rtw89_btc_wl_ver_info { 1845 u32 fw_coex; /* match with which coex_ver */ 1846 u32 fw; 1847 u32 mac; 1848 u32 bb; 1849 u32 rf; 1850 }; 1851 1852 struct rtw89_btc_wl_afh_info { 1853 u8 en; 1854 u8 ch; 1855 u8 bw; 1856 u8 rsvd; 1857 } __packed; 1858 1859 struct rtw89_btc_wl_rfk_info { 1860 u32 state: 2; 1861 u32 path_map: 4; 1862 u32 phy_map: 2; 1863 u32 band: 2; 1864 u32 type: 8; 1865 u32 con_rfk: 1; 1866 u32 rsvd: 13; 1867 1868 u32 start_time; 1869 u32 proc_time; 1870 }; 1871 1872 struct rtw89_btc_bt_smap { 1873 u32 connect: 1; 1874 u32 ble_connect: 1; 1875 u32 acl_busy: 1; 1876 u32 sco_busy: 1; 1877 u32 mesh_busy: 1; 1878 u32 inq_pag: 1; 1879 }; 1880 1881 union rtw89_btc_bt_state_map { 1882 u32 val; 1883 struct rtw89_btc_bt_smap map; 1884 }; 1885 1886 #define BTC_BT_RSSI_THMAX 4 1887 #define BTC_BT_AFH_GROUP 12 1888 #define BTC_BT_AFH_LE_GROUP 5 1889 1890 struct rtw89_btc_bt_txpwr_desc { 1891 s8 br_dbm; 1892 s8 le_dbm; 1893 u8 br_gain_index; 1894 u8 le_gain_index; 1895 }; 1896 1897 struct rtw89_btc_bt_link_info { 1898 struct rtw89_btc_u8_sta_chg profile_cnt; 1899 struct rtw89_btc_bool_sta_chg multi_link; 1900 struct rtw89_btc_bool_sta_chg relink; 1901 struct rtw89_btc_bt_hfp_desc hfp_desc; 1902 struct rtw89_btc_bt_hid_desc hid_desc; 1903 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1904 struct rtw89_btc_bt_pan_desc pan_desc; 1905 union rtw89_btc_bt_state_map status; 1906 struct rtw89_btc_bt_txpwr_desc bt_txpwr_desc; 1907 1908 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1909 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1910 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1911 u8 afh_map[BTC_BT_AFH_GROUP]; 1912 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1913 1914 u32 role_sw: 1; 1915 u32 slave_role: 1; 1916 u32 afh_update: 1; 1917 u32 cqddr: 1; 1918 u32 rssi: 8; 1919 u32 tx_3m: 1; 1920 u32 rsvd: 19; 1921 }; 1922 1923 struct rtw89_btc_3rdcx_info { 1924 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1925 u8 hw_coex; 1926 u16 rsvd; 1927 }; 1928 1929 struct rtw89_btc_dm_emap { 1930 u32 init: 1; 1931 u32 pta_owner: 1; 1932 u32 wl_rfk_timeout: 1; 1933 u32 bt_rfk_timeout: 1; 1934 u32 wl_fw_hang: 1; 1935 u32 cycle_hang: 1; 1936 u32 w1_hang: 1; 1937 u32 b1_hang: 1; 1938 u32 tdma_no_sync: 1; 1939 u32 slot_no_sync: 1; 1940 u32 wl_slot_drift: 1; 1941 u32 bt_slot_drift: 1; 1942 u32 role_num_mismatch: 1; 1943 u32 null1_tx_late: 1; 1944 u32 bt_afh_conflict: 1; 1945 u32 bt_leafh_conflict: 1; 1946 u32 bt_slot_flood: 1; 1947 u32 wl_e2g_hang: 1; 1948 u32 wl_ver_mismatch: 1; 1949 u32 bt_ver_mismatch: 1; 1950 u32 rfe_type0: 1; 1951 u32 h2c_buffer_over: 1; 1952 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1953 u32 wl_no_sta_ntfy: 1; 1954 1955 u32 h2c_bmap_mismatch: 1; 1956 u32 c2h_bmap_mismatch: 1; 1957 u32 h2c_struct_invalid: 1; 1958 u32 c2h_struct_invalid: 1; 1959 u32 h2c_c2h_buffer_mismatch: 1; 1960 }; 1961 1962 union rtw89_btc_dm_error_map { 1963 u32 val; 1964 struct rtw89_btc_dm_emap map; 1965 }; 1966 1967 struct rtw89_btc_rf_para { 1968 u32 tx_pwr_freerun; 1969 u32 rx_gain_freerun; 1970 u32 tx_pwr_perpkt; 1971 u32 rx_gain_perpkt; 1972 }; 1973 1974 struct rtw89_btc_wl_nhm { 1975 u8 instant_wl_nhm_dbm; 1976 u8 instant_wl_nhm_per_mhz; 1977 u16 valid_record_times; 1978 s8 record_pwr[16]; 1979 u8 record_ratio[16]; 1980 s8 pwr; /* dbm_per_MHz */ 1981 u8 ratio; 1982 u8 current_status; 1983 u8 refresh; 1984 bool start_flag; 1985 s8 pwr_max; 1986 s8 pwr_min; 1987 }; 1988 1989 struct rtw89_btc_wl_info { 1990 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1991 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1992 struct rtw89_btc_wl_rfk_info rfk_info; 1993 struct rtw89_btc_wl_ver_info ver_info; 1994 struct rtw89_btc_wl_afh_info afh_info; 1995 struct rtw89_btc_wl_role_info role_info; 1996 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1997 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1998 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1999 struct rtw89_btc_wl_role_info_v8 role_info_v8; 2000 struct rtw89_btc_wl_scan_info scan_info; 2001 struct rtw89_btc_wl_dbcc_info dbcc_info; 2002 struct rtw89_btc_wl_mlo_info mlo_info; 2003 struct rtw89_btc_rf_para rf_para; 2004 struct rtw89_btc_wl_nhm nhm; 2005 union rtw89_btc_wl_state_map status; 2006 2007 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 2008 u8 rssi_level; 2009 u8 cn_report; 2010 u8 coex_mode; 2011 u8 pta_req_mac; 2012 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 2013 2014 bool is_5g_hi_channel; 2015 bool go_client_exist; 2016 bool noa_exist; 2017 bool pta_reg_mac_chg; 2018 bool bg_mode; 2019 bool he_mode; 2020 bool scbd_change; 2021 bool fw_ver_mismatch; 2022 bool client_cnt_inc_2g; 2023 bool link_mode_chg; 2024 bool dbcc_chg; 2025 u32 scbd; 2026 }; 2027 2028 struct rtw89_btc_module { 2029 struct rtw89_btc_ant_info ant; 2030 u8 rfe_type; 2031 u8 cv; 2032 2033 u8 bt_solo: 1; 2034 u8 bt_pos: 1; 2035 u8 switch_type: 1; 2036 u8 wa_type: 3; 2037 2038 u8 kt_ver_adie; 2039 }; 2040 2041 struct rtw89_btc_module_v7 { 2042 u8 rfe_type; 2043 u8 kt_ver; 2044 u8 bt_solo; 2045 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 2046 2047 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 2048 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 2049 u8 kt_ver_adie; 2050 u8 rsvd; 2051 2052 struct rtw89_btc_ant_info_v7 ant; 2053 } __packed; 2054 2055 union rtw89_btc_module_info { 2056 struct rtw89_btc_module md; 2057 struct rtw89_btc_module_v7 md_v7; 2058 }; 2059 2060 #define RTW89_BTC_DM_MAXSTEP 30 2061 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 2062 2063 struct rtw89_btc_dm_step { 2064 u16 step[RTW89_BTC_DM_MAXSTEP]; 2065 u8 step_pos; 2066 bool step_ov; 2067 }; 2068 2069 struct rtw89_btc_init_info { 2070 struct rtw89_btc_module module; 2071 u8 wl_guard_ch; 2072 2073 u8 wl_only: 1; 2074 u8 wl_init_ok: 1; 2075 u8 dbcc_en: 1; 2076 u8 cx_other: 1; 2077 u8 bt_only: 1; 2078 2079 u16 rsvd; 2080 }; 2081 2082 struct rtw89_btc_init_info_v7 { 2083 u8 wl_guard_ch; 2084 u8 wl_only; 2085 u8 wl_init_ok; 2086 u8 rsvd3; 2087 2088 u8 cx_other; 2089 u8 bt_only; 2090 u8 pta_mode; 2091 u8 pta_direction; 2092 2093 struct rtw89_btc_module_v7 module; 2094 } __packed; 2095 2096 union rtw89_btc_init_info_u { 2097 struct rtw89_btc_init_info init; 2098 struct rtw89_btc_init_info_v7 init_v7; 2099 }; 2100 2101 struct rtw89_btc_wl_tx_limit_para { 2102 u16 enable; 2103 u32 tx_time; /* unit: us */ 2104 u16 tx_retry; 2105 }; 2106 2107 enum rtw89_btc_bt_scan_type { 2108 BTC_SCAN_INQ = 0, 2109 BTC_SCAN_PAGE, 2110 BTC_SCAN_BLE, 2111 BTC_SCAN_INIT, 2112 BTC_SCAN_TV, 2113 BTC_SCAN_ADV, 2114 BTC_SCAN_MAX1, 2115 }; 2116 2117 enum rtw89_btc_ble_scan_type { 2118 CXSCAN_BG = 0, 2119 CXSCAN_INIT, 2120 CXSCAN_LE, 2121 CXSCAN_MAX 2122 }; 2123 2124 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2125 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2126 2127 struct rtw89_btc_bt_scan_info_v1 { 2128 __le16 win; 2129 __le16 intvl; 2130 __le32 flags; 2131 } __packed; 2132 2133 struct rtw89_btc_bt_scan_info_v2 { 2134 __le16 win; 2135 __le16 intvl; 2136 } __packed; 2137 2138 struct rtw89_btc_fbtc_btscan_v1 { 2139 u8 fver; /* btc_ver::fcxbtscan */ 2140 u8 rsvd; 2141 __le16 rsvd2; 2142 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2143 } __packed; 2144 2145 struct rtw89_btc_fbtc_btscan_v2 { 2146 u8 fver; /* btc_ver::fcxbtscan */ 2147 u8 type; 2148 __le16 rsvd2; 2149 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2150 } __packed; 2151 2152 struct rtw89_btc_fbtc_btscan_v7 { 2153 u8 fver; /* btc_ver::fcxbtscan */ 2154 u8 type; 2155 u8 rsvd0; 2156 u8 rsvd1; 2157 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2158 } __packed; 2159 2160 union rtw89_btc_fbtc_btscan { 2161 struct rtw89_btc_fbtc_btscan_v1 v1; 2162 struct rtw89_btc_fbtc_btscan_v2 v2; 2163 struct rtw89_btc_fbtc_btscan_v7 v7; 2164 }; 2165 2166 struct rtw89_btc_bt_info { 2167 struct rtw89_btc_bt_link_info link_info; 2168 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2169 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2170 struct rtw89_btc_bt_ver_info ver_info; 2171 struct rtw89_btc_bool_sta_chg enable; 2172 struct rtw89_btc_bool_sta_chg inq_pag; 2173 struct rtw89_btc_rf_para rf_para; 2174 union rtw89_btc_bt_rfk_info_map rfk_info; 2175 2176 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2177 u8 txpwr_info[BTC_BTINFO_MAX]; 2178 u8 rssi_level; 2179 2180 u32 scbd; 2181 u32 feature; 2182 2183 u32 mbx_avl: 1; 2184 u32 whql_test: 1; 2185 u32 igno_wl: 1; 2186 u32 reinit: 1; 2187 u32 ble_scan_en: 1; 2188 u32 btg_type: 1; 2189 u32 inq: 1; 2190 u32 pag: 1; 2191 u32 run_patch_code: 1; 2192 u32 hi_lna_rx: 1; 2193 u32 scan_rx_low_pri: 1; 2194 u32 scan_info_update: 1; 2195 u32 lna_constrain: 3; 2196 u32 rsvd: 17; 2197 }; 2198 2199 struct rtw89_btc_cx { 2200 struct rtw89_btc_wl_info wl; 2201 struct rtw89_btc_bt_info bt; 2202 struct rtw89_btc_3rdcx_info other; 2203 u32 state_map; 2204 u32 cnt_bt[BTC_BCNT_NUM]; 2205 u32 cnt_wl[BTC_WCNT_NUM]; 2206 }; 2207 2208 struct rtw89_btc_fbtc_tdma { 2209 u8 type; /* btc_ver::fcxtdma */ 2210 u8 rxflctrl; 2211 u8 txpause; 2212 u8 wtgle_n; 2213 u8 leak_n; 2214 u8 ext_ctrl; 2215 u8 rxflctrl_role; 2216 u8 option_ctrl; 2217 } __packed; 2218 2219 struct rtw89_btc_fbtc_tdma_v3 { 2220 u8 fver; /* btc_ver::fcxtdma */ 2221 u8 rsvd; 2222 __le16 rsvd1; 2223 struct rtw89_btc_fbtc_tdma tdma; 2224 } __packed; 2225 2226 union rtw89_btc_fbtc_tdma_le32 { 2227 struct rtw89_btc_fbtc_tdma v1; 2228 struct rtw89_btc_fbtc_tdma_v3 v3; 2229 }; 2230 2231 #define CXMREG_MAX 30 2232 #define CXMREG_MAX_V2 20 2233 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2234 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2235 2236 enum rtw89_btc_bt_sta_counter { 2237 BTC_BCNT_RFK_REQ = 0, 2238 BTC_BCNT_RFK_GO = 1, 2239 BTC_BCNT_RFK_REJECT = 2, 2240 BTC_BCNT_RFK_FAIL = 3, 2241 BTC_BCNT_RFK_TIMEOUT = 4, 2242 BTC_BCNT_HI_TX = 5, 2243 BTC_BCNT_HI_RX = 6, 2244 BTC_BCNT_LO_TX = 7, 2245 BTC_BCNT_LO_RX = 8, 2246 BTC_BCNT_POLLUTED = 9, 2247 BTC_BCNT_STA_MAX 2248 }; 2249 2250 enum rtw89_btc_bt_sta_counter_v105 { 2251 BTC_BCNT_RFK_REQ_V105 = 0, 2252 BTC_BCNT_HI_TX_V105 = 1, 2253 BTC_BCNT_HI_RX_V105 = 2, 2254 BTC_BCNT_LO_TX_V105 = 3, 2255 BTC_BCNT_LO_RX_V105 = 4, 2256 BTC_BCNT_POLLUTED_V105 = 5, 2257 BTC_BCNT_STA_MAX_V105 2258 }; 2259 2260 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2261 u16 fver; /* btc_ver::fcxbtcrpt */ 2262 u16 rpt_cnt; /* tmr counters */ 2263 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2264 u32 wl_fw_cx_offload; 2265 u32 wl_fw_ver; 2266 u32 rpt_enable; 2267 u32 rpt_para; /* ms */ 2268 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2269 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2270 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2271 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2272 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2273 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2274 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2275 u32 c2h_cnt; /* fw send c2h counter */ 2276 u32 h2c_cnt; /* fw recv h2c counter */ 2277 } __packed; 2278 2279 struct rtw89_btc_fbtc_rpt_ctrl_info { 2280 __le32 cnt; /* fw report counter */ 2281 __le32 en; /* report map */ 2282 __le32 para; /* not used */ 2283 2284 __le32 cnt_c2h; /* fw send c2h counter */ 2285 __le32 cnt_h2c; /* fw recv h2c counter */ 2286 __le32 len_c2h; /* The total length of the last C2H */ 2287 2288 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2289 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2290 } __packed; 2291 2292 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2293 __le32 cx_ver; /* match which driver's coex version */ 2294 __le32 fw_ver; 2295 __le32 en; /* report map */ 2296 2297 __le16 cnt; /* fw report counter */ 2298 __le16 cnt_c2h; /* fw send c2h counter */ 2299 __le16 cnt_h2c; /* fw recv h2c counter */ 2300 __le16 len_c2h; /* The total length of the last C2H */ 2301 2302 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2303 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2304 } __packed; 2305 2306 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2307 __le16 cnt; /* fw report counter */ 2308 __le16 cnt_c2h; /* fw send c2h counter */ 2309 __le16 cnt_h2c; /* fw recv h2c counter */ 2310 __le16 len_c2h; /* The total length of the last C2H */ 2311 2312 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2313 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2314 2315 __le32 cx_ver; /* match which driver's coex version */ 2316 __le32 fw_ver; 2317 __le32 en; /* report map */ 2318 } __packed; 2319 2320 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2321 __le32 cx_ver; /* match which driver's coex version */ 2322 __le32 cx_offload; 2323 __le32 fw_ver; 2324 } __packed; 2325 2326 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2327 __le32 cnt_empty; /* a2dp empty count */ 2328 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2329 __le32 cnt_tx; 2330 __le32 cnt_ack; 2331 __le32 cnt_nack; 2332 } __packed; 2333 2334 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2335 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2336 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2337 __le32 cnt_recv; /* fw recv mailbox counter */ 2338 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2339 } __packed; 2340 2341 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2342 u8 fver; 2343 u8 rsvd; 2344 __le16 rsvd1; 2345 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2346 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2347 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2348 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2349 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2350 } __packed; 2351 2352 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2353 u8 fver; 2354 u8 rsvd; 2355 __le16 rsvd1; 2356 2357 u8 gnt_val[RTW89_PHY_NUM][4]; 2358 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2359 2360 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2361 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2362 } __packed; 2363 2364 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2365 u8 fver; 2366 u8 rsvd; 2367 __le16 rsvd1; 2368 2369 u8 gnt_val[RTW89_PHY_NUM][4]; 2370 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2371 2372 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2373 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2374 } __packed; 2375 2376 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2377 u8 fver; 2378 u8 rsvd0; 2379 u8 rsvd1; 2380 u8 rsvd2; 2381 2382 u8 gnt_val[RTW89_PHY_NUM][4]; 2383 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2384 2385 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2386 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2387 } __packed; 2388 2389 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2390 u8 fver; 2391 u8 rsvd0; 2392 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2393 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2394 2395 u8 gnt_val[RTW89_PHY_NUM][4]; 2396 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2397 2398 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2399 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2400 } __packed; 2401 2402 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2403 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2404 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2405 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2406 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2407 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2408 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2409 }; 2410 2411 enum rtw89_fbtc_ext_ctrl_type { 2412 CXECTL_OFF = 0x0, /* tdma off */ 2413 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2414 CXECTL_EXT = 0x2, 2415 CXECTL_MAX 2416 }; 2417 2418 union rtw89_btc_fbtc_rxflct { 2419 u8 val; 2420 u8 type: 3; 2421 u8 tgln_n: 5; 2422 }; 2423 2424 enum rtw89_btc_cxst_state { 2425 CXST_OFF = 0x0, 2426 CXST_B2W = 0x1, 2427 CXST_W1 = 0x2, 2428 CXST_W2 = 0x3, 2429 CXST_W2B = 0x4, 2430 CXST_B1 = 0x5, 2431 CXST_B2 = 0x6, 2432 CXST_B3 = 0x7, 2433 CXST_B4 = 0x8, 2434 CXST_LK = 0x9, 2435 CXST_BLK = 0xa, 2436 CXST_E2G = 0xb, 2437 CXST_E5G = 0xc, 2438 CXST_EBT = 0xd, 2439 CXST_ENULL = 0xe, 2440 CXST_WLK = 0xf, 2441 CXST_W1FDD = 0x10, 2442 CXST_B1FDD = 0x11, 2443 CXST_MAX = 0x12, 2444 }; 2445 2446 enum rtw89_btc_cxevnt { 2447 CXEVNT_TDMA_ENTRY = 0x0, 2448 CXEVNT_WL_TMR, 2449 CXEVNT_B1_TMR, 2450 CXEVNT_B2_TMR, 2451 CXEVNT_B3_TMR, 2452 CXEVNT_B4_TMR, 2453 CXEVNT_W2B_TMR, 2454 CXEVNT_B2W_TMR, 2455 CXEVNT_BCN_EARLY, 2456 CXEVNT_A2DP_EMPTY, 2457 CXEVNT_LK_END, 2458 CXEVNT_RX_ISR, 2459 CXEVNT_RX_FC0, 2460 CXEVNT_RX_FC1, 2461 CXEVNT_BT_RELINK, 2462 CXEVNT_BT_RETRY, 2463 CXEVNT_E2G, 2464 CXEVNT_E5G, 2465 CXEVNT_EBT, 2466 CXEVNT_ENULL, 2467 CXEVNT_DRV_WLK, 2468 CXEVNT_BCN_OK, 2469 CXEVNT_BT_CHANGE, 2470 CXEVNT_EBT_EXTEND, 2471 CXEVNT_E2G_NULL1, 2472 CXEVNT_B1FDD_TMR, 2473 CXEVNT_MAX 2474 }; 2475 2476 enum { 2477 CXBCN_ALL = 0x0, 2478 CXBCN_ALL_OK, 2479 CXBCN_BT_SLOT, 2480 CXBCN_BT_OK, 2481 CXBCN_MAX 2482 }; 2483 2484 enum btc_slot_type { 2485 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2486 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2487 CXSTYPE_NUM, 2488 }; 2489 2490 enum { /* TIME */ 2491 CXT_BT = 0x0, 2492 CXT_WL = 0x1, 2493 CXT_MAX 2494 }; 2495 2496 enum { /* TIME-A2DP */ 2497 CXT_FLCTRL_OFF = 0x0, 2498 CXT_FLCTRL_ON = 0x1, 2499 CXT_FLCTRL_MAX 2500 }; 2501 2502 enum { /* STEP TYPE */ 2503 CXSTEP_NONE = 0x0, 2504 CXSTEP_EVNT = 0x1, 2505 CXSTEP_SLOT = 0x2, 2506 CXSTEP_MAX, 2507 }; 2508 2509 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2510 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2511 RPT_BT_AFH_SEQ_LE = 0x20 2512 }; 2513 2514 #define BTC_DBG_MAX1 32 2515 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2516 u8 fver; /* btc_ver::fcxgpiodbg */ 2517 u8 rsvd; 2518 __le16 rsvd2; 2519 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2520 __le32 pre_state; /* the debug signal is 1 or 0 */ 2521 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2522 } __packed; 2523 2524 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2525 u8 fver; 2526 u8 rsvd0; 2527 u8 rsvd1; 2528 u8 rsvd2; 2529 2530 u8 gpio_map[BTC_DBG_MAX1]; 2531 2532 __le32 en_map; 2533 __le32 pre_state; 2534 } __packed; 2535 2536 union rtw89_btc_fbtc_gpio_dbg { 2537 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2538 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2539 }; 2540 2541 struct rtw89_btc_fbtc_mreg_val_v1 { 2542 u8 fver; /* btc_ver::fcxmreg */ 2543 u8 reg_num; 2544 __le16 rsvd; 2545 __le32 mreg_val[CXMREG_MAX]; 2546 } __packed; 2547 2548 struct rtw89_btc_fbtc_mreg_val_v2 { 2549 u8 fver; /* btc_ver::fcxmreg */ 2550 u8 reg_num; 2551 __le16 rsvd; 2552 __le32 mreg_val[CXMREG_MAX_V2]; 2553 } __packed; 2554 2555 struct rtw89_btc_fbtc_mreg_val_v7 { 2556 u8 fver; 2557 u8 reg_num; 2558 u8 rsvd0; 2559 u8 rsvd1; 2560 __le32 mreg_val[CXMREG_MAX_V2]; 2561 } __packed; 2562 2563 union rtw89_btc_fbtc_mreg_val { 2564 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2565 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2566 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2567 }; 2568 2569 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2570 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2571 .offset = cpu_to_le32(__offset), } 2572 2573 struct rtw89_btc_fbtc_mreg { 2574 __le16 type; 2575 __le16 bytes; 2576 __le32 offset; 2577 } __packed; 2578 2579 struct rtw89_btc_fbtc_slot { 2580 __le16 dur; 2581 __le32 cxtbl; 2582 __le16 cxtype; 2583 } __packed; 2584 2585 struct rtw89_btc_fbtc_slots { 2586 u8 fver; /* btc_ver::fcxslots */ 2587 u8 tbl_num; 2588 __le16 rsvd; 2589 __le32 update_map; 2590 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2591 } __packed; 2592 2593 struct rtw89_btc_fbtc_slot_v7 { 2594 __le16 dur; /* slot duration */ 2595 __le16 cxtype; 2596 __le32 cxtbl; 2597 } __packed; 2598 2599 struct rtw89_btc_fbtc_slot_u16 { 2600 __le16 dur; /* slot duration */ 2601 __le16 cxtype; 2602 __le16 cxtbl_l16; /* coex table [15:0] */ 2603 __le16 cxtbl_h16; /* coex table [31:16] */ 2604 } __packed; 2605 2606 struct rtw89_btc_fbtc_1slot_v7 { 2607 u8 fver; 2608 u8 sid; /* slot id */ 2609 __le16 rsvd; 2610 struct rtw89_btc_fbtc_slot_v7 slot; 2611 } __packed; 2612 2613 struct rtw89_btc_fbtc_slots_v7 { 2614 u8 fver; 2615 u8 slot_cnt; 2616 u8 rsvd0; 2617 u8 rsvd1; 2618 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2619 __le32 update_map; 2620 } __packed; 2621 2622 union rtw89_btc_fbtc_slots_info { 2623 struct rtw89_btc_fbtc_slots v1; 2624 struct rtw89_btc_fbtc_slots_v7 v7; 2625 } __packed; 2626 2627 struct rtw89_btc_fbtc_step { 2628 u8 type; 2629 u8 val; 2630 __le16 difft; 2631 } __packed; 2632 2633 struct rtw89_btc_fbtc_steps_v2 { 2634 u8 fver; /* btc_ver::fcxstep */ 2635 u8 rsvd; 2636 __le16 cnt; 2637 __le16 pos_old; 2638 __le16 pos_new; 2639 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2640 } __packed; 2641 2642 struct rtw89_btc_fbtc_steps_v3 { 2643 u8 fver; 2644 u8 en; 2645 __le16 rsvd; 2646 __le32 cnt; 2647 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2648 } __packed; 2649 2650 union rtw89_btc_fbtc_steps_info { 2651 struct rtw89_btc_fbtc_steps_v2 v2; 2652 struct rtw89_btc_fbtc_steps_v3 v3; 2653 }; 2654 2655 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2656 u8 fver; /* btc_ver::fcxcysta */ 2657 u8 rsvd; 2658 __le16 cycles; /* total cycle number */ 2659 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2660 __le16 a2dpept; /* a2dp empty cnt */ 2661 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2662 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2663 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2664 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2665 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2666 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2667 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2668 __le16 tmax_a2dpept; /* max a2dp empty time */ 2669 __le16 tavg_lk; /* avg leak-slot time */ 2670 __le16 tmax_lk; /* max leak-slot time */ 2671 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2672 __le32 bcn_cnt[CXBCN_MAX]; 2673 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2674 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2675 __le32 skip_cnt; 2676 __le32 exception; 2677 __le32 except_cnt; 2678 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2679 } __packed; 2680 2681 struct rtw89_btc_fbtc_fdd_try_info { 2682 __le16 cycles[CXT_FLCTRL_MAX]; 2683 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2684 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2685 } __packed; 2686 2687 struct rtw89_btc_fbtc_cycle_time_info { 2688 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2689 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2690 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2691 } __packed; 2692 2693 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2694 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2695 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2696 } __packed; 2697 2698 struct rtw89_btc_fbtc_a2dp_trx_stat { 2699 u8 empty_cnt; 2700 u8 retry_cnt; 2701 u8 tx_rate; 2702 u8 tx_cnt; 2703 u8 ack_cnt; 2704 u8 nack_cnt; 2705 u8 rsvd1; 2706 u8 rsvd2; 2707 } __packed; 2708 2709 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2710 u8 empty_cnt; 2711 u8 retry_cnt; 2712 u8 tx_rate; 2713 u8 tx_cnt; 2714 u8 ack_cnt; 2715 u8 nack_cnt; 2716 u8 no_empty_cnt; 2717 u8 rsvd; 2718 } __packed; 2719 2720 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2721 __le16 cnt; /* a2dp empty cnt */ 2722 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2723 __le16 tavg; /* avg a2dp empty time */ 2724 __le16 tmax; /* max a2dp empty time */ 2725 } __packed; 2726 2727 struct rtw89_btc_fbtc_cycle_leak_info { 2728 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2729 __le16 tavg; /* avg leak-slot time */ 2730 __le16 tmax; /* max leak-slot time */ 2731 } __packed; 2732 2733 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2734 __le16 tavg; 2735 __le16 tamx; 2736 __le32 cnt_rximr; 2737 } __packed; 2738 2739 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2740 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2741 2742 struct rtw89_btc_fbtc_cycle_fddt_info { 2743 __le16 train_cycle; 2744 __le16 tp; 2745 2746 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2747 s8 bt_tx_power; /* decrease Tx power (dB) */ 2748 s8 bt_rx_gain; /* LNA constrain level */ 2749 u8 no_empty_cnt; 2750 2751 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2752 u8 cn; /* condition_num */ 2753 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2754 u8 train_result; /* refer to enum btc_fddt_check_map */ 2755 } __packed; 2756 2757 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2758 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2759 2760 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2761 __le16 train_cycle; 2762 __le16 tp; 2763 2764 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2765 s8 bt_tx_power; /* decrease Tx power (dB) */ 2766 s8 bt_rx_gain; /* LNA constrain level */ 2767 u8 no_empty_cnt; 2768 2769 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2770 u8 cn; /* condition_num */ 2771 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2772 u8 train_result; /* refer to enum btc_fddt_check_map */ 2773 } __packed; 2774 2775 struct rtw89_btc_fbtc_fddt_cell_status { 2776 s8 wl_tx_pwr; 2777 s8 bt_tx_pwr; 2778 s8 bt_rx_gain; 2779 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2780 } __packed; 2781 2782 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2783 u8 fver; 2784 u8 rsvd; 2785 __le16 cycles; /* total cycle number */ 2786 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2787 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2788 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2789 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2790 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2791 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2792 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2793 __le32 bcn_cnt[CXBCN_MAX]; 2794 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2795 __le32 skip_cnt; 2796 __le32 except_cnt; 2797 __le32 except_map; 2798 } __packed; 2799 2800 #define FDD_TRAIN_WL_DIRECTION 2 2801 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2802 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2803 2804 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2805 u8 fver; 2806 u8 rsvd; 2807 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2808 u8 except_cnt; 2809 2810 __le16 skip_cnt; 2811 __le16 cycles; /* total cycle number */ 2812 2813 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2814 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2815 __le16 bcn_cnt[CXBCN_MAX]; 2816 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2817 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2818 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2819 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2820 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2821 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2822 [FDD_TRAIN_WL_RSSI_LEVEL] 2823 [FDD_TRAIN_BT_RSSI_LEVEL]; 2824 __le32 except_map; 2825 } __packed; 2826 2827 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2828 u8 fver; 2829 u8 rsvd; 2830 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2831 u8 except_cnt; 2832 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2833 2834 __le16 skip_cnt; 2835 __le16 cycles; /* total cycle number */ 2836 2837 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2838 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2839 __le16 bcn_cnt[CXBCN_MAX]; 2840 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2841 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2842 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2843 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2844 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2845 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2846 [FDD_TRAIN_WL_RSSI_LEVEL] 2847 [FDD_TRAIN_BT_RSSI_LEVEL]; 2848 __le32 except_map; 2849 } __packed; 2850 2851 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2852 u8 fver; 2853 u8 rsvd; 2854 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2855 u8 except_cnt; 2856 2857 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2858 2859 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2860 2861 __le16 skip_cnt; 2862 __le16 cycles; /* total cycle number */ 2863 2864 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2865 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2866 __le16 bcn_cnt[CXBCN_MAX]; 2867 2868 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2869 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2870 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2871 2872 __le32 except_map; 2873 } __packed; 2874 2875 union rtw89_btc_fbtc_cysta_info { 2876 struct rtw89_btc_fbtc_cysta_v2 v2; 2877 struct rtw89_btc_fbtc_cysta_v3 v3; 2878 struct rtw89_btc_fbtc_cysta_v4 v4; 2879 struct rtw89_btc_fbtc_cysta_v5 v5; 2880 struct rtw89_btc_fbtc_cysta_v7 v7; 2881 }; 2882 2883 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2884 u8 fver; /* btc_ver::fcxnullsta */ 2885 u8 rsvd; 2886 __le16 rsvd2; 2887 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2888 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2889 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2890 } __packed; 2891 2892 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2893 u8 fver; /* btc_ver::fcxnullsta */ 2894 u8 rsvd; 2895 __le16 rsvd2; 2896 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2897 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2898 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2899 } __packed; 2900 2901 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2902 u8 fver; 2903 u8 rsvd0; 2904 u8 rsvd1; 2905 u8 rsvd2; 2906 2907 __le32 tmax[2]; 2908 __le32 tavg[2]; 2909 __le32 result[2][5]; 2910 } __packed; 2911 2912 union rtw89_btc_fbtc_cynullsta_info { 2913 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2914 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2915 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2916 }; 2917 2918 struct rtw89_btc_fbtc_btver_v1 { 2919 u8 fver; /* btc_ver::fcxbtver */ 2920 u8 rsvd; 2921 __le16 rsvd2; 2922 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2923 __le32 fw_ver; 2924 __le32 feature; 2925 } __packed; 2926 2927 struct rtw89_btc_fbtc_btver_v7 { 2928 u8 fver; 2929 u8 rsvd0; 2930 u8 rsvd1; 2931 u8 rsvd2; 2932 2933 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2934 __le32 fw_ver; 2935 __le32 feature; 2936 } __packed; 2937 2938 union rtw89_btc_fbtc_btver { 2939 struct rtw89_btc_fbtc_btver_v1 v1; 2940 struct rtw89_btc_fbtc_btver_v7 v7; 2941 } __packed; 2942 2943 struct rtw89_btc_fbtc_btafh { 2944 u8 fver; /* btc_ver::fcxbtafh */ 2945 u8 rsvd; 2946 __le16 rsvd2; 2947 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2948 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2949 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2950 } __packed; 2951 2952 struct rtw89_btc_fbtc_btafh_v2 { 2953 u8 fver; /* btc_ver::fcxbtafh */ 2954 u8 rsvd; 2955 u8 rsvd2; 2956 u8 map_type; 2957 u8 afh_l[4]; 2958 u8 afh_m[4]; 2959 u8 afh_h[4]; 2960 u8 afh_le_a[4]; 2961 u8 afh_le_b[4]; 2962 } __packed; 2963 2964 struct rtw89_btc_fbtc_btafh_v7 { 2965 u8 fver; 2966 u8 map_type; 2967 u8 rsvd0; 2968 u8 rsvd1; 2969 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2970 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2971 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2972 u8 afh_le_a[4]; 2973 u8 afh_le_b[4]; 2974 } __packed; 2975 2976 struct rtw89_btc_fbtc_btdevinfo { 2977 u8 fver; /* btc_ver::fcxbtdevinfo */ 2978 u8 rsvd; 2979 __le16 vendor_id; 2980 __le32 dev_name; /* only 24 bits valid */ 2981 __le32 flush_time; 2982 } __packed; 2983 2984 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2985 struct rtw89_btc_rf_trx_para { 2986 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2987 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2988 u8 bt_tx_power; /* decrease Tx power (dB) */ 2989 u8 bt_rx_gain; /* LNA constrain level */ 2990 }; 2991 2992 struct rtw89_btc_trx_info { 2993 u8 tx_lvl; 2994 u8 rx_lvl; 2995 u8 wl_rssi; 2996 u8 bt_rssi; 2997 2998 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2999 s8 rx_gain; /* rx gain table index (TBD.) */ 3000 s8 bt_tx_power; /* decrease Tx power (dB) */ 3001 s8 bt_rx_gain; /* LNA constrain level */ 3002 3003 u8 cn; /* condition_num */ 3004 s8 nhm; 3005 u8 bt_profile; 3006 u8 rsvd2; 3007 3008 u16 tx_rate; 3009 u16 rx_rate; 3010 3011 u32 tx_tp; 3012 u32 rx_tp; 3013 u32 rx_err_ratio; 3014 }; 3015 3016 enum btc_rf_path { 3017 BTC_RF_S0 = 0, 3018 BTC_RF_S1 = 1, 3019 BTC_RF_NUM, 3020 }; 3021 3022 struct rtw89_btc_fbtc_outsrc_set_info { 3023 u8 rf_band[BTC_RF_NUM]; /* 0:2G, 1:non-2G */ 3024 u8 btg_rx[BTC_RF_NUM]; 3025 u8 nbtg_tx[BTC_RF_NUM]; 3026 3027 struct rtw89_mac_ax_gnt gnt_set[BTC_RF_NUM]; /* refer to btc_gnt_ctrl */ 3028 struct rtw89_mac_ax_wl_act wlact_set[BTC_RF_NUM]; /* BT0/BT1 */ 3029 3030 u8 pta_req_hw_band; 3031 u8 rf_gbt_source; 3032 } __packed; 3033 3034 union rtw89_btc_fbtc_slot_u { 3035 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 3036 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 3037 }; 3038 3039 struct rtw89_btc_dm { 3040 struct rtw89_btc_fbtc_outsrc_set_info ost_info_last; /* outsrc API setup info */ 3041 struct rtw89_btc_fbtc_outsrc_set_info ost_info; /* outsrc API setup info */ 3042 union rtw89_btc_fbtc_slot_u slot; 3043 union rtw89_btc_fbtc_slot_u slot_now; 3044 struct rtw89_btc_fbtc_tdma tdma; 3045 struct rtw89_btc_fbtc_tdma tdma_now; 3046 struct rtw89_mac_ax_coex_gnt gnt; 3047 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 3048 struct rtw89_btc_rf_trx_para rf_trx_para; 3049 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 3050 struct rtw89_btc_dm_step dm_step; 3051 struct rtw89_btc_wl_scc_ctrl wl_scc; 3052 struct rtw89_btc_trx_info trx_info; 3053 union rtw89_btc_dm_error_map error; 3054 u32 cnt_dm[BTC_DCNT_NUM]; 3055 u32 cnt_notify[BTC_NCNT_NUM]; 3056 3057 u32 update_slot_map; 3058 u32 set_ant_path; 3059 u32 e2g_slot_limit; 3060 u32 e2g_slot_nulltx_time; 3061 3062 u32 wl_only: 1; 3063 u32 wl_fw_cx_offload: 1; 3064 u32 freerun: 1; 3065 u32 fddt_train: 1; 3066 u32 wl_ps_ctrl: 2; 3067 u32 wl_mimo_ps: 1; 3068 u32 leak_ap: 1; 3069 u32 noisy_level: 3; 3070 u32 coex_info_map: 8; 3071 u32 bt_only: 1; 3072 u32 wl_btg_rx: 2; 3073 u32 trx_para_level: 8; 3074 u32 wl_stb_chg: 1; 3075 u32 pta_owner: 1; 3076 3077 u32 tdma_instant_excute: 1; 3078 u32 wl_btg_rx_rb: 2; 3079 3080 u16 slot_dur[CXST_MAX]; 3081 u16 bt_slot_flood; 3082 3083 u8 run_reason; 3084 u8 run_action; 3085 3086 u8 wl_pre_agc: 2; 3087 u8 wl_lna2: 1; 3088 u8 freerun_chk: 1; 3089 u8 wl_pre_agc_rb: 2; 3090 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 3091 u8 slot_req_more: 1; 3092 }; 3093 3094 struct rtw89_btc_ctrl { 3095 u32 manual: 1; 3096 u32 igno_bt: 1; 3097 u32 always_freerun: 1; 3098 u32 trace_step: 16; 3099 u32 rsvd: 12; 3100 }; 3101 3102 struct rtw89_btc_ctrl_v7 { 3103 u8 manual; 3104 u8 igno_bt; 3105 u8 always_freerun; 3106 u8 rsvd; 3107 } __packed; 3108 3109 union rtw89_btc_ctrl_list { 3110 struct rtw89_btc_ctrl ctrl; 3111 struct rtw89_btc_ctrl_v7 ctrl_v7; 3112 }; 3113 3114 struct rtw89_btc_dbg { 3115 /* cmd "rb" */ 3116 bool rb_done; 3117 u32 rb_val; 3118 }; 3119 3120 enum rtw89_btc_btf_fw_event { 3121 BTF_EVNT_RPT = 0, 3122 BTF_EVNT_BT_INFO = 1, 3123 BTF_EVNT_BT_SCBD = 2, 3124 BTF_EVNT_BT_REG = 3, 3125 BTF_EVNT_CX_RUNINFO = 4, 3126 BTF_EVNT_BT_PSD = 5, 3127 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 3128 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 3129 BTF_EVNT_BUF_OVERFLOW, 3130 BTF_EVNT_C2H_LOOPBACK, 3131 BTF_EVNT_BT_QUERY_TXPWR, /* fwc2hfunc > 3 */ 3132 BTF_EVNT_MAX, 3133 }; 3134 3135 enum btf_fw_event_report { 3136 BTC_RPT_TYPE_CTRL = 0x0, 3137 BTC_RPT_TYPE_TDMA, 3138 BTC_RPT_TYPE_SLOT, 3139 BTC_RPT_TYPE_CYSTA, 3140 BTC_RPT_TYPE_STEP, 3141 BTC_RPT_TYPE_NULLSTA, 3142 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3143 BTC_RPT_TYPE_MREG, 3144 BTC_RPT_TYPE_GPIO_DBG, 3145 BTC_RPT_TYPE_BT_VER, 3146 BTC_RPT_TYPE_BT_SCAN, 3147 BTC_RPT_TYPE_BT_AFH, 3148 BTC_RPT_TYPE_BT_DEVICE, 3149 BTC_RPT_TYPE_TEST, 3150 BTC_RPT_TYPE_MAX = 31, 3151 3152 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3153 __BTC_RPT_TYPE_V0_MAX = 12, 3154 }; 3155 3156 enum rtw_btc_btf_reg_type { 3157 REG_MAC = 0x0, 3158 REG_BB = 0x1, 3159 REG_RF = 0x2, 3160 REG_BT_RF = 0x3, 3161 REG_BT_MODEM = 0x4, 3162 REG_BT_BLUEWIZE = 0x5, 3163 REG_BT_VENDOR = 0x6, 3164 REG_BT_LE = 0x7, 3165 REG_MAX_TYPE, 3166 }; 3167 3168 struct rtw89_btc_rpt_cmn_info { 3169 u32 rx_cnt; 3170 u32 rx_len; 3171 u32 req_len; /* expected rsp len */ 3172 u8 req_fver; /* expected rsp fver */ 3173 u8 rsp_fver; /* fver from fw */ 3174 u8 valid; 3175 } __packed; 3176 3177 union rtw89_btc_fbtc_btafh_info { 3178 struct rtw89_btc_fbtc_btafh v1; 3179 struct rtw89_btc_fbtc_btafh_v2 v2; 3180 struct rtw89_btc_fbtc_btafh_v7 v7; 3181 }; 3182 3183 struct rtw89_btc_report_ctrl_state { 3184 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3185 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3186 }; 3187 3188 struct rtw89_btc_rpt_fbtc_tdma { 3189 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3190 union rtw89_btc_fbtc_tdma_le32 finfo; 3191 }; 3192 3193 struct rtw89_btc_rpt_fbtc_slots { 3194 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3195 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3196 }; 3197 3198 struct rtw89_btc_rpt_fbtc_cysta { 3199 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3200 union rtw89_btc_fbtc_cysta_info finfo; 3201 }; 3202 3203 struct rtw89_btc_rpt_fbtc_step { 3204 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3205 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3206 }; 3207 3208 struct rtw89_btc_rpt_fbtc_nullsta { 3209 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3210 union rtw89_btc_fbtc_cynullsta_info finfo; 3211 }; 3212 3213 struct rtw89_btc_rpt_fbtc_mreg { 3214 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3215 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3216 }; 3217 3218 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3219 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3220 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3221 }; 3222 3223 struct rtw89_btc_rpt_fbtc_btver { 3224 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3225 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3226 }; 3227 3228 struct rtw89_btc_rpt_fbtc_btscan { 3229 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3230 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3231 }; 3232 3233 struct rtw89_btc_rpt_fbtc_btafh { 3234 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3235 union rtw89_btc_fbtc_btafh_info finfo; 3236 }; 3237 3238 struct rtw89_btc_rpt_fbtc_btdev { 3239 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3240 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3241 }; 3242 3243 enum rtw89_btc_btfre_type { 3244 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3245 BTFRE_UNDEF_TYPE, 3246 BTFRE_EXCEPTION, 3247 BTFRE_MAX, 3248 }; 3249 3250 struct rtw89_btc_ver { 3251 enum rtw89_core_chip_id chip_id; 3252 u32 fw_ver_code; 3253 3254 u8 fcxbtcrpt; 3255 u8 fcxtdma; 3256 u8 fcxslots; 3257 u8 fcxcysta; 3258 u8 fcxstep; 3259 u8 fcxnullsta; 3260 u8 fcxmreg; 3261 u8 fcxgpiodbg; 3262 u8 fcxbtver; 3263 u8 fcxbtscan; 3264 u8 fcxbtafh; 3265 u8 fcxbtdevinfo; 3266 u8 fwlrole; 3267 u8 frptmap; 3268 u8 fcxctrl; 3269 u8 fcxinit; 3270 3271 u8 fwevntrptl; 3272 u8 fwc2hfunc; 3273 u8 drvinfo_type; 3274 u16 info_buf; 3275 u8 max_role_num; 3276 u8 fcxosi; 3277 u8 fcxmlo; 3278 u8 bt_desired; 3279 }; 3280 3281 struct rtw89_btc_btf_fwinfo { 3282 u32 cnt_c2h; 3283 u32 cnt_h2c; 3284 u32 cnt_h2c_fail; 3285 u32 event[BTF_EVNT_MAX]; 3286 3287 u32 err[BTFRE_MAX]; 3288 u32 len_mismch; 3289 u32 fver_mismch; 3290 u32 rpt_en_map; 3291 3292 struct rtw89_btc_ver fw_subver; 3293 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3294 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3295 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3296 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3297 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3298 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3299 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3300 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3301 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3302 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3303 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3304 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3305 }; 3306 3307 #define RTW89_BTC_POLICY_MAXLEN 512 3308 3309 struct rtw89_btc { 3310 const struct rtw89_btc_ver *ver; 3311 3312 struct rtw89_btc_cx cx; 3313 struct rtw89_btc_dm dm; 3314 union rtw89_btc_ctrl_list ctrl; 3315 union rtw89_btc_module_info mdinfo; 3316 struct rtw89_btc_btf_fwinfo fwinfo; 3317 struct rtw89_btc_dbg dbg; 3318 3319 struct wiphy_work eapol_notify_work; 3320 struct wiphy_work arp_notify_work; 3321 struct wiphy_work dhcp_notify_work; 3322 struct wiphy_work icmp_notify_work; 3323 3324 u32 bt_req_len; 3325 3326 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3327 u8 ant_type; 3328 u8 btg_pos; 3329 u16 policy_len; 3330 u16 policy_type; 3331 u32 hubmsg_cnt; 3332 bool bt_req_en; 3333 bool update_policy_force; 3334 bool lps; 3335 bool manual_ctrl; 3336 }; 3337 3338 enum rtw89_btc_hmsg { 3339 RTW89_BTC_HMSG_TMR_EN = 0x0, 3340 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3341 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3342 RTW89_BTC_HMSG_FW_EV = 0x3, 3343 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3344 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3345 3346 NUM_OF_RTW89_BTC_HMSG, 3347 }; 3348 3349 enum rtw89_ra_mode { 3350 RTW89_RA_MODE_CCK = BIT(0), 3351 RTW89_RA_MODE_OFDM = BIT(1), 3352 RTW89_RA_MODE_HT = BIT(2), 3353 RTW89_RA_MODE_VHT = BIT(3), 3354 RTW89_RA_MODE_HE = BIT(4), 3355 RTW89_RA_MODE_EHT = BIT(5), 3356 }; 3357 3358 enum rtw89_ra_report_mode { 3359 RTW89_RA_RPT_MODE_LEGACY, 3360 RTW89_RA_RPT_MODE_HT, 3361 RTW89_RA_RPT_MODE_VHT, 3362 RTW89_RA_RPT_MODE_HE, 3363 RTW89_RA_RPT_MODE_EHT, 3364 }; 3365 3366 enum rtw89_dig_noisy_level { 3367 RTW89_DIG_NOISY_LEVEL0 = -1, 3368 RTW89_DIG_NOISY_LEVEL1 = 0, 3369 RTW89_DIG_NOISY_LEVEL2 = 1, 3370 RTW89_DIG_NOISY_LEVEL3 = 2, 3371 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3372 }; 3373 3374 enum rtw89_gi_ltf { 3375 RTW89_GILTF_LGI_4XHE32 = 0, 3376 RTW89_GILTF_SGI_4XHE08 = 1, 3377 RTW89_GILTF_2XHE16 = 2, 3378 RTW89_GILTF_2XHE08 = 3, 3379 RTW89_GILTF_1XHE16 = 4, 3380 RTW89_GILTF_1XHE08 = 5, 3381 RTW89_GILTF_MAX 3382 }; 3383 3384 enum rtw89_rx_frame_type { 3385 RTW89_RX_TYPE_MGNT = 0, 3386 RTW89_RX_TYPE_CTRL = 1, 3387 RTW89_RX_TYPE_DATA = 2, 3388 RTW89_RX_TYPE_RSVD = 3, 3389 }; 3390 3391 enum rtw89_efuse_block { 3392 RTW89_EFUSE_BLOCK_SYS = 0, 3393 RTW89_EFUSE_BLOCK_RF = 1, 3394 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3395 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3396 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3397 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3398 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3399 RTW89_EFUSE_BLOCK_ADIE = 7, 3400 3401 RTW89_EFUSE_BLOCK_NUM, 3402 RTW89_EFUSE_BLOCK_IGNORE, 3403 }; 3404 3405 struct rtw89_ra_info { 3406 u8 is_dis_ra:1; 3407 /* Bit0 : CCK 3408 * Bit1 : OFDM 3409 * Bit2 : HT 3410 * Bit3 : VHT 3411 * Bit4 : HE 3412 * Bit5 : EHT 3413 */ 3414 u8 mode_ctrl:6; 3415 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3416 u8 macid; 3417 u8 dcm_cap:1; 3418 u8 er_cap:1; 3419 u8 init_rate_lv:2; 3420 u8 upd_all:1; 3421 u8 en_sgi:1; 3422 u8 ldpc_cap:1; 3423 u8 stbc_cap:1; 3424 u8 ss_num:3; 3425 u8 giltf:3; 3426 u8 upd_bw_nss_mask:1; 3427 u8 upd_mask:1; 3428 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3429 /* BFee CSI */ 3430 u8 band_num; 3431 u8 ra_csi_rate_en:1; 3432 u8 fixed_csi_rate_en:1; 3433 u8 cr_tbl_sel:1; 3434 u8 fix_giltf_en:1; 3435 u8 fix_giltf:3; 3436 u8 partial_bw_er:1; 3437 u8 csi_mcs_ss_idx; 3438 u8 csi_mode:2; 3439 u8 csi_gi_ltf:3; 3440 u8 csi_bw:3; 3441 /* after v1 */ 3442 u8 is_noisy:1; 3443 u8 psra_en:1; 3444 u8 rsvd0:1; 3445 u8 macid_msb:2; 3446 u8 band:2; /* enum rtw89_band */ 3447 u8 is_new_dbgreg:1; 3448 }; 3449 3450 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3451 #define RTW89_PPDU_MAC_INFO_SIZE 8 3452 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3453 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3454 3455 struct rtw89_ampdu_params { 3456 u16 agg_num; 3457 bool amsdu; 3458 }; 3459 3460 struct rtw89_ra_report { 3461 struct rate_info txrate; 3462 u32 bit_rate; 3463 u16 hw_rate; 3464 bool might_fallback_legacy; 3465 }; 3466 3467 DECLARE_EWMA(rssi, 10, 16); 3468 DECLARE_EWMA(evm, 10, 16); 3469 DECLARE_EWMA(snr, 10, 16); 3470 3471 struct rtw89_ba_cam_entry { 3472 struct list_head list; 3473 u8 tid; 3474 }; 3475 3476 #define RTW89_MAX_ADDR_CAM_NUM 128 3477 #define RTW89_MAX_BSSID_CAM_NUM 20 3478 #define RTW89_MAX_SEC_CAM_NUM 128 3479 #define RTW89_MAX_BA_CAM_NUM 24 3480 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3481 3482 struct rtw89_addr_cam_entry { 3483 u8 addr_cam_idx; 3484 u8 offset; 3485 u8 len; 3486 u8 valid : 1; 3487 u8 addr_mask : 6; 3488 u8 wapi : 1; 3489 u8 mask_sel : 2; 3490 u8 bssid_cam_idx: 6; 3491 3492 u8 sec_ent_mode; 3493 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3494 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3495 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3496 }; 3497 3498 struct rtw89_bssid_cam_entry { 3499 u8 bssid[ETH_ALEN]; 3500 u8 phy_idx; 3501 u8 bssid_cam_idx; 3502 u8 offset; 3503 u8 len; 3504 u8 valid : 1; 3505 u8 num; 3506 }; 3507 3508 struct rtw89_sec_cam_entry { 3509 u8 sec_cam_idx; 3510 u8 offset; 3511 u8 len; 3512 u8 type : 4; 3513 u8 ext_key : 1; 3514 u8 spp_mode : 1; 3515 /* 256 bits */ 3516 u8 key[32]; 3517 3518 struct ieee80211_key_conf *key_conf; 3519 }; 3520 3521 struct rtw89_sta_link { 3522 struct rtw89_sta *rtwsta; 3523 struct list_head dlink_schd; 3524 unsigned int link_id; 3525 3526 u8 mac_id; 3527 u8 tx_retry; 3528 bool er_cap; 3529 struct rtw89_vif_link *rtwvif_link; 3530 struct rtw89_ra_info ra; 3531 struct rtw89_ra_report ra_report; 3532 int max_agg_wait; 3533 u8 prev_rssi; 3534 struct ewma_rssi avg_rssi; 3535 struct ewma_rssi rssi[RF_PATH_MAX]; 3536 struct ewma_snr avg_snr; 3537 struct ewma_evm evm_1ss; 3538 struct ewma_evm evm_min[RF_PATH_MAX]; 3539 struct ewma_evm evm_max[RF_PATH_MAX]; 3540 struct ieee80211_rx_status rx_status; 3541 u16 rx_hw_rate; 3542 __le32 htc_template; 3543 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3544 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3545 struct list_head ba_cam_list; 3546 3547 bool use_cfg_mask; 3548 struct cfg80211_bitrate_mask mask; 3549 3550 bool cctl_tx_time; 3551 u32 ampdu_max_time:4; 3552 bool cctl_tx_retry_limit; 3553 u32 data_tx_cnt_lmt:6; 3554 }; 3555 3556 struct rtw89_efuse { 3557 bool valid; 3558 bool power_k_valid; 3559 u8 xtal_cap; 3560 u8 addr[ETH_ALEN]; 3561 u8 rfe_type; 3562 char country_code[2]; 3563 u8 adc_td; 3564 }; 3565 3566 struct rtw89_phy_rate_pattern { 3567 u64 ra_mask; 3568 u16 rate; 3569 u8 ra_mode; 3570 bool enable; 3571 }; 3572 3573 #define RTW89_TX_DONE 0x0 3574 #define RTW89_TX_RETRY_LIMIT 0x1 3575 #define RTW89_TX_LIFE_TIME 0x2 3576 #define RTW89_TX_MACID_DROP 0x3 3577 3578 #define RTW89_MAX_TX_RPTS 16 3579 #define RTW89_MAX_TX_RPTS_MASK (RTW89_MAX_TX_RPTS - 1) 3580 struct rtw89_tx_rpt { 3581 struct sk_buff *skbs[RTW89_MAX_TX_RPTS]; 3582 /* protect skbs array access/modification */ 3583 spinlock_t skb_lock; 3584 atomic_t sn; 3585 }; 3586 3587 #define RTW89_TX_WAIT_WORK_TIMEOUT msecs_to_jiffies(500) 3588 struct rtw89_tx_wait_info { 3589 struct rcu_head rcu_head; 3590 struct list_head list; 3591 struct completion completion; 3592 struct sk_buff *skb; 3593 bool tx_done; 3594 }; 3595 3596 struct rtw89_tx_skb_data { 3597 struct rtw89_tx_wait_info __rcu *wait; 3598 u8 tx_rpt_sn; 3599 u8 tx_pkt_cnt_lmt; 3600 u8 hci_priv[]; 3601 }; 3602 3603 #define RTW89_SCAN_NULL_TIMEOUT 30 3604 3605 #define RTW89_ROC_IDLE_TIMEOUT 500 3606 #define RTW89_ROC_TX_TIMEOUT 30 3607 enum rtw89_roc_state { 3608 RTW89_ROC_IDLE, 3609 RTW89_ROC_NORMAL, 3610 RTW89_ROC_MGMT, 3611 }; 3612 3613 struct rtw89_roc { 3614 struct ieee80211_channel chan; 3615 struct wiphy_delayed_work roc_work; 3616 enum ieee80211_roc_type type; 3617 enum rtw89_roc_state state; 3618 int duration; 3619 unsigned int link_id; 3620 }; 3621 3622 #define RTW89_P2P_MAX_NOA_NUM 2 3623 3624 struct rtw89_p2p_ie_head { 3625 u8 eid; 3626 u8 ie_len; 3627 u8 oui[3]; 3628 u8 oui_type; 3629 } __packed; 3630 3631 struct rtw89_noa_attr_head { 3632 u8 attr_type; 3633 __le16 attr_len; 3634 u8 index; 3635 u8 oppps_ctwindow; 3636 } __packed; 3637 3638 struct rtw89_p2p_noa_ie { 3639 struct rtw89_p2p_ie_head p2p_head; 3640 struct rtw89_noa_attr_head noa_head; 3641 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3642 } __packed; 3643 3644 struct rtw89_p2p_noa_setter { 3645 struct rtw89_p2p_noa_ie ie; 3646 u8 noa_count; 3647 u8 noa_index; 3648 }; 3649 3650 struct rtw89_ps_noa_once_handler { 3651 bool in_duration; 3652 u64 tsf_begin; 3653 u64 tsf_end; 3654 struct wiphy_delayed_work set_work; 3655 struct wiphy_delayed_work clr_work; 3656 }; 3657 3658 struct rtw89_vif_link { 3659 struct rtw89_vif *rtwvif; 3660 struct list_head dlink_schd; 3661 unsigned int link_id; 3662 3663 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3664 enum rtw89_chanctx_idx chanctx_idx; 3665 enum rtw89_reg_6ghz_power reg_6ghz_power; 3666 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3667 3668 u8 mac_id; 3669 u8 port; 3670 u8 mac_addr[ETH_ALEN]; 3671 u8 bssid[ETH_ALEN]; 3672 u8 phy_idx; 3673 u8 mac_idx; 3674 u8 net_type; 3675 u8 wifi_role; 3676 u8 self_role; 3677 u8 wmm; 3678 u8 bcn_hit_cond; 3679 u8 bcn_bw_idx; 3680 u8 hit_rule; 3681 u8 last_noa_nr; 3682 u64 sync_bcn_tsf; 3683 u64 last_sync_bcn_tsf; 3684 bool rand_tsf_done; 3685 bool trigger; 3686 bool lsig_txop; 3687 u8 tgt_ind; 3688 u8 frm_tgt_ind; 3689 bool wowlan_pattern; 3690 bool wowlan_uc; 3691 bool wowlan_magic; 3692 bool is_hesta; 3693 bool last_a_ctrl; 3694 bool dyn_tb_bedge_en; 3695 bool pre_pwr_diff_en; 3696 bool pwr_diff_en; 3697 u8 def_tri_idx; 3698 struct wiphy_work update_beacon_work; 3699 struct wiphy_delayed_work csa_beacon_work; 3700 struct rtw89_addr_cam_entry addr_cam; 3701 struct rtw89_bssid_cam_entry bssid_cam; 3702 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3703 struct rtw89_phy_rate_pattern rate_pattern; 3704 struct list_head general_pkt_list; 3705 struct rtw89_p2p_noa_setter p2p_noa; 3706 struct rtw89_ps_noa_once_handler noa_once; 3707 struct wiphy_delayed_work mcc_gc_detect_beacon_work; 3708 u8 detect_bcn_count; 3709 }; 3710 3711 enum rtw89_lv1_rcvy_step { 3712 RTW89_LV1_RCVY_STEP_1, 3713 RTW89_LV1_RCVY_STEP_2, 3714 }; 3715 3716 struct rtw89_hci_ops { 3717 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3718 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3719 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3720 void (*reset)(struct rtw89_dev *rtwdev); 3721 int (*start)(struct rtw89_dev *rtwdev); 3722 void (*stop)(struct rtw89_dev *rtwdev); 3723 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3724 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3725 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3726 3727 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3728 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3729 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3730 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3731 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3732 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3733 3734 u32 (*read32_pci_cfg)(struct rtw89_dev *rtwdev, u32 addr); 3735 3736 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3737 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3738 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3739 int (*deinit)(struct rtw89_dev *rtwdev); 3740 3741 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3742 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3743 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3744 int (*napi_poll)(struct napi_struct *napi, int budget); 3745 3746 /* Deal with locks inside recovery_start and recovery_complete callbacks 3747 * by hci instance, and handle things which need to consider under SER. 3748 * e.g. turn on/off interrupts except for the one for halt notification. 3749 */ 3750 void (*recovery_start)(struct rtw89_dev *rtwdev); 3751 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3752 3753 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3754 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3755 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3756 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3757 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3758 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3759 void (*disable_intr)(struct rtw89_dev *rtwdev); 3760 void (*enable_intr)(struct rtw89_dev *rtwdev); 3761 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3762 }; 3763 3764 struct rtw89_hci_info { 3765 const struct rtw89_hci_ops *ops; 3766 enum rtw89_hci_type type; 3767 enum rtw89_hci_dle_type dle_type; 3768 u32 rpwm_addr; 3769 u32 cpwm_addr; 3770 bool paused; 3771 bool tx_rpt_enabled; 3772 }; 3773 3774 struct rtw89_chip_ops { 3775 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3776 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3777 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3778 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3779 void (*bb_reset)(struct rtw89_dev *rtwdev, 3780 enum rtw89_phy_idx phy_idx); 3781 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3782 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3783 u32 addr, u32 mask); 3784 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3785 u32 addr, u32 mask, u32 data); 3786 void (*set_channel)(struct rtw89_dev *rtwdev, 3787 const struct rtw89_chan *chan, 3788 enum rtw89_mac_idx mac_idx, 3789 enum rtw89_phy_idx phy_idx); 3790 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3791 struct rtw89_channel_help_params *p, 3792 const struct rtw89_chan *chan, 3793 enum rtw89_mac_idx mac_idx, 3794 enum rtw89_phy_idx phy_idx); 3795 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3796 enum rtw89_efuse_block block); 3797 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3798 void (*fem_setup)(struct rtw89_dev *rtwdev); 3799 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3800 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3801 void (*rfk_init)(struct rtw89_dev *rtwdev); 3802 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3803 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3804 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3805 enum rtw89_phy_idx phy_idx, 3806 const struct rtw89_chan *chan); 3807 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3808 bool start); 3809 void (*rfk_track)(struct rtw89_dev *rtwdev); 3810 void (*power_trim)(struct rtw89_dev *rtwdev); 3811 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3812 const struct rtw89_chan *chan, 3813 enum rtw89_phy_idx phy_idx); 3814 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3815 enum rtw89_phy_idx phy_idx); 3816 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3817 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3818 u32 (*chan_to_rf18_val)(struct rtw89_dev *rtwdev, 3819 const struct rtw89_chan *chan); 3820 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3821 enum rtw89_phy_idx phy_idx); 3822 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3823 struct rtw89_rx_phy_ppdu *phy_ppdu, 3824 struct ieee80211_rx_status *status); 3825 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3826 struct rtw89_rx_phy_ppdu *phy_ppdu); 3827 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3828 struct rtw89_rx_desc_info *desc_info, 3829 struct ieee80211_rx_status *rx_status); 3830 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3831 enum rtw89_phy_idx phy_idx); 3832 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3833 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3834 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3835 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3836 enum rtw89_phy_idx phy_idx); 3837 void (*calc_rx_gain_normal)(struct rtw89_dev *rtwdev, 3838 const struct rtw89_chan *chan, 3839 enum rtw89_rf_path path, 3840 enum rtw89_phy_idx phy_idx, 3841 struct rtw89_phy_calc_efuse_gain *calc); 3842 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3843 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3844 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3845 struct rtw89_rx_desc_info *desc_info, 3846 u8 *data, u32 data_offset); 3847 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3848 struct rtw89_tx_desc_info *desc_info, 3849 void *txdesc); 3850 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3851 struct rtw89_tx_desc_info *desc_info, 3852 void *txdesc); 3853 u8 (*get_ch_dma[RTW89_HCI_TYPE_NUM])(struct rtw89_dev *rtwdev, u8 qsel); 3854 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3855 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3856 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3857 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3858 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3859 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3860 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3861 struct rtw89_vif_link *rtwvif_link, 3862 struct rtw89_sta_link *rtwsta_link); 3863 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3864 struct rtw89_vif_link *rtwvif_link, 3865 struct rtw89_sta_link *rtwsta_link); 3866 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3867 struct rtw89_vif_link *rtwvif_link, 3868 struct rtw89_sta_link *rtwsta_link); 3869 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3870 struct rtw89_vif_link *rtwvif_link, 3871 struct rtw89_sta_link *rtwsta_link); 3872 int (*h2c_txtime_cmac_tbl)(struct rtw89_dev *rtwdev, 3873 struct rtw89_sta_link *rtwsta_link); 3874 int (*h2c_punctured_cmac_tbl)(struct rtw89_dev *rtwdev, 3875 struct rtw89_vif_link *rtwvif_link, 3876 u16 punctured); 3877 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3878 struct rtw89_vif_link *rtwvif_link, 3879 struct rtw89_sta_link *rtwsta_link); 3880 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3881 struct rtw89_vif_link *rtwvif_link); 3882 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3883 struct rtw89_vif_link *rtwvif_link, 3884 struct rtw89_sta_link *rtwsta_link, 3885 bool valid, struct ieee80211_ampdu_params *params); 3886 int (*h2c_wow_cam_update)(struct rtw89_dev *rtwdev, 3887 struct rtw89_wow_cam_info *cam_info); 3888 3889 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3890 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3891 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3892 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3893 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3894 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3895 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3896 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3897 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3898 }; 3899 3900 enum rtw89_dma_ch { 3901 RTW89_DMA_ACH0 = 0, 3902 RTW89_DMA_ACH1 = 1, 3903 RTW89_DMA_ACH2 = 2, 3904 RTW89_DMA_ACH3 = 3, 3905 RTW89_DMA_ACH4 = 4, 3906 RTW89_DMA_ACH5 = 5, 3907 RTW89_DMA_ACH6 = 6, 3908 RTW89_DMA_ACH7 = 7, 3909 RTW89_DMA_B0MG = 8, 3910 RTW89_DMA_B0HI = 9, 3911 RTW89_DMA_B1MG = 10, 3912 RTW89_DMA_B1HI = 11, 3913 RTW89_DMA_H2C = 12, 3914 RTW89_DMA_CH_NUM = 13 3915 }; 3916 3917 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3918 3919 enum rtw89_mlo_dbcc_mode { 3920 MLO_DBCC_NOT_SUPPORT = 1, 3921 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3922 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3923 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3924 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3925 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3926 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3927 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3928 DBCC_LEGACY = 0xffffffff, 3929 }; 3930 3931 enum rtw89_scan_be_operation { 3932 RTW89_SCAN_OP_STOP, 3933 RTW89_SCAN_OP_START, 3934 RTW89_SCAN_OP_SETPARM, 3935 RTW89_SCAN_OP_GETRPT, 3936 RTW89_SCAN_OP_NUM 3937 }; 3938 3939 enum rtw89_scan_be_mode { 3940 RTW89_SCAN_MODE_SA, 3941 RTW89_SCAN_MODE_MACC, 3942 RTW89_SCAN_MODE_NUM 3943 }; 3944 3945 enum rtw89_scan_be_opmode { 3946 RTW89_SCAN_OPMODE_NONE, 3947 RTW89_SCAN_OPMODE_TBTT, 3948 RTW89_SCAN_OPMODE_INTV, 3949 RTW89_SCAN_OPMODE_CNT, 3950 RTW89_SCAN_OPMODE_NUM, 3951 }; 3952 3953 struct rtw89_scan_option { 3954 bool enable; 3955 bool target_ch_mode; 3956 u8 num_macc_role; 3957 u8 num_opch; 3958 u8 repeat; 3959 u16 norm_pd; 3960 u16 slow_pd; 3961 u16 norm_cy; 3962 u8 opch_end; 3963 u16 delay; /* in unit of ms */ 3964 u64 prohib_chan; 3965 enum rtw89_phy_idx band; 3966 enum rtw89_scan_be_operation operation; 3967 enum rtw89_scan_be_mode scan_mode; 3968 enum rtw89_mlo_dbcc_mode mlo_mode; 3969 }; 3970 3971 enum rtw89_qta_mode { 3972 RTW89_QTA_SCC, 3973 RTW89_QTA_DBCC, 3974 RTW89_QTA_DLFW, 3975 RTW89_QTA_WOW, 3976 3977 /* keep last */ 3978 RTW89_QTA_INVALID, 3979 }; 3980 3981 struct rtw89_hfc_ch_cfg { 3982 u16 min; 3983 u16 max; 3984 #define grp_0 0 3985 #define grp_1 1 3986 #define grp_num 2 3987 u8 grp; 3988 }; 3989 3990 struct rtw89_hfc_ch_info { 3991 u16 aval; 3992 u16 used; 3993 }; 3994 3995 struct rtw89_hfc_pub_cfg { 3996 u16 grp0; 3997 u16 grp1; 3998 u16 pub_max; 3999 u16 wp_thrd; 4000 }; 4001 4002 struct rtw89_hfc_pub_info { 4003 u16 g0_used; 4004 u16 g1_used; 4005 u16 g0_aval; 4006 u16 g1_aval; 4007 u16 pub_aval; 4008 u16 wp_aval; 4009 }; 4010 4011 struct rtw89_hfc_prec_cfg { 4012 u16 ch011_prec; 4013 u16 h2c_prec; 4014 u16 wp_ch07_prec; 4015 u16 wp_ch811_prec; 4016 u8 ch011_full_cond; 4017 u8 h2c_full_cond; 4018 u8 wp_ch07_full_cond; 4019 u8 wp_ch811_full_cond; 4020 /* for WiFi 7 chips after 8922D */ 4021 u16 ch011_full_page; 4022 u16 h2c_full_page; 4023 u16 wp_ch07_full_page; 4024 u16 wp_ch811_full_page; 4025 }; 4026 4027 struct rtw89_hfc_param { 4028 bool en; 4029 bool h2c_en; 4030 u8 mode; 4031 const struct rtw89_hfc_ch_cfg *ch_cfg; 4032 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 4033 struct rtw89_hfc_pub_cfg pub_cfg; 4034 struct rtw89_hfc_pub_info pub_info; 4035 struct rtw89_hfc_prec_cfg prec_cfg; 4036 }; 4037 4038 struct rtw89_hfc_param_ini { 4039 const struct rtw89_hfc_ch_cfg *ch_cfg; 4040 const struct rtw89_hfc_pub_cfg *pub_cfg; 4041 const struct rtw89_hfc_prec_cfg *prec_cfg; 4042 u8 mode; 4043 }; 4044 4045 struct rtw89_dle_size { 4046 u16 pge_size; 4047 u16 lnk_pge_num; 4048 u16 unlnk_pge_num; 4049 /* for WiFi 7 chips below (suffix v1) */ 4050 u32 srt_ofst; 4051 }; 4052 4053 struct rtw89_wde_quota { 4054 u16 hif; 4055 u16 wcpu; 4056 /* unused dcpu isn't listed */ 4057 u16 pkt_in; 4058 u16 cpu_io; 4059 }; 4060 4061 struct rtw89_ple_quota { 4062 u16 cma0_tx; 4063 u16 cma1_tx; 4064 u16 c2h; 4065 u16 h2c; 4066 u16 wcpu; 4067 u16 mpdu_proc; 4068 u16 cma0_dma; 4069 u16 cma1_dma; 4070 u16 bb_rpt; 4071 u16 wd_rel; 4072 u16 cpu_io; 4073 u16 tx_rpt; 4074 /* for WiFi 7 chips below (suffix v1) */ 4075 u16 h2d; 4076 /* for WiFi 7 chips after 8922D (suffix v2) */ 4077 u16 snrpt; 4078 }; 4079 4080 struct rtw89_rsvd_quota { 4081 u16 mpdu_info_tbl; 4082 u16 b0_csi; 4083 u16 b1_csi; 4084 u16 b0_lmr; 4085 u16 b1_lmr; 4086 u16 b0_ftm; 4087 u16 b1_ftm; 4088 u16 b0_smr; 4089 u16 b1_smr; 4090 u16 others; 4091 }; 4092 4093 struct rtw89_dle_rsvd_size { 4094 u32 srt_ofst; 4095 u32 size; 4096 }; 4097 4098 struct rtw89_dle_input { 4099 u32 tx_ampdu_num_b0; 4100 u32 tx_ampdu_num_b1; 4101 u32 tx_amsdu_size; /* unit: KB */ 4102 u32 h2c_max_size; 4103 u32 rx_amsdu_size; /* unit: KB */ 4104 u32 c2h_max_size; 4105 u32 mpdu_info_tbl_b0; 4106 u32 mpdu_info_tbl_b1; 4107 }; 4108 4109 struct rtw89_dle_mem { 4110 enum rtw89_qta_mode mode; 4111 const struct rtw89_dle_size *wde_size; 4112 const struct rtw89_dle_size *ple_size; 4113 const struct rtw89_wde_quota *wde_min_qt; 4114 const struct rtw89_wde_quota *wde_max_qt; 4115 const struct rtw89_ple_quota *ple_min_qt; 4116 const struct rtw89_ple_quota *ple_max_qt; 4117 /* for WiFi 7 chips below */ 4118 const struct rtw89_rsvd_quota *rsvd_qt; 4119 const struct rtw89_dle_rsvd_size *rsvd0_size; 4120 const struct rtw89_dle_rsvd_size *rsvd1_size; 4121 /* for WiFi 7 chips after 8922D */ 4122 const struct rtw89_dle_input *dle_input; 4123 }; 4124 4125 struct rtw89_reg_def { 4126 u32 addr; 4127 u32 mask; 4128 }; 4129 4130 struct rtw89_reg2_def { 4131 u32 addr; 4132 u32 data; 4133 }; 4134 4135 struct rtw89_reg3_def { 4136 u32 addr; 4137 u32 mask; 4138 u32 data; 4139 }; 4140 4141 struct rtw89_reg5_def { 4142 u8 flag; /* recognized by parsers */ 4143 u8 path; 4144 u32 addr; 4145 u32 mask; 4146 u32 data; 4147 }; 4148 4149 struct rtw89_reg_imr { 4150 u32 addr; 4151 u32 clr; 4152 u32 set; 4153 }; 4154 4155 struct rtw89_phy_table { 4156 const struct rtw89_reg2_def *regs; 4157 u32 n_regs; 4158 enum rtw89_rf_path rf_path; 4159 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 4160 enum rtw89_rf_path rf_path, void *data); 4161 }; 4162 4163 struct rtw89_txpwr_table { 4164 const void *data; 4165 u32 size; 4166 void (*load)(struct rtw89_dev *rtwdev, 4167 const struct rtw89_txpwr_table *tbl); 4168 }; 4169 4170 struct rtw89_txpwr_rule_2ghz { 4171 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4172 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4173 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4174 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4175 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4176 }; 4177 4178 struct rtw89_txpwr_rule_5ghz { 4179 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4180 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4181 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4182 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4183 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4184 }; 4185 4186 struct rtw89_txpwr_rule_6ghz { 4187 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4188 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4189 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4190 [RTW89_6G_CH_NUM]; 4191 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 4192 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4193 [RTW89_6G_CH_NUM]; 4194 }; 4195 4196 struct rtw89_tx_shape { 4197 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4198 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4199 }; 4200 4201 struct rtw89_rfe_parms { 4202 const struct rtw89_txpwr_table *byr_tbl; 4203 struct rtw89_txpwr_rule_2ghz rule_2ghz; 4204 struct rtw89_txpwr_rule_5ghz rule_5ghz; 4205 struct rtw89_txpwr_rule_6ghz rule_6ghz; 4206 struct rtw89_txpwr_rule_2ghz rule_da_2ghz; 4207 struct rtw89_txpwr_rule_5ghz rule_da_5ghz; 4208 struct rtw89_txpwr_rule_6ghz rule_da_6ghz; 4209 struct rtw89_tx_shape tx_shape; 4210 bool has_da; 4211 }; 4212 4213 struct rtw89_rfe_parms_conf { 4214 const struct rtw89_rfe_parms *rfe_parms; 4215 u8 rfe_type; 4216 }; 4217 4218 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 4219 4220 struct rtw89_txpwr_conf { 4221 u8 rfe_type; 4222 u8 ent_sz; 4223 u32 num_ents; 4224 const void *data; 4225 }; 4226 4227 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4228 const struct rtw89_txpwr_conf *conf) 4229 { 4230 u8 valid_size = min(size, conf->ent_sz); 4231 4232 memcpy(entry, cursor, valid_size); 4233 return true; 4234 } 4235 4236 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4237 4238 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4239 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4240 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4241 (cursor) += (conf)->ent_sz) \ 4242 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4243 4244 struct rtw89_txpwr_byrate_data { 4245 struct rtw89_txpwr_conf conf; 4246 struct rtw89_txpwr_table tbl; 4247 }; 4248 4249 struct rtw89_txpwr_lmt_2ghz_data { 4250 struct rtw89_txpwr_conf conf; 4251 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4252 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4253 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4254 }; 4255 4256 struct rtw89_txpwr_lmt_5ghz_data { 4257 struct rtw89_txpwr_conf conf; 4258 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4259 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4260 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4261 }; 4262 4263 struct rtw89_txpwr_lmt_6ghz_data { 4264 struct rtw89_txpwr_conf conf; 4265 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4266 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4267 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4268 [RTW89_6G_CH_NUM]; 4269 }; 4270 4271 struct rtw89_txpwr_lmt_ru_2ghz_data { 4272 struct rtw89_txpwr_conf conf; 4273 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4274 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4275 }; 4276 4277 struct rtw89_txpwr_lmt_ru_5ghz_data { 4278 struct rtw89_txpwr_conf conf; 4279 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4280 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4281 }; 4282 4283 struct rtw89_txpwr_lmt_ru_6ghz_data { 4284 struct rtw89_txpwr_conf conf; 4285 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4286 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4287 [RTW89_6G_CH_NUM]; 4288 }; 4289 4290 struct rtw89_tx_shape_lmt_data { 4291 struct rtw89_txpwr_conf conf; 4292 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4293 }; 4294 4295 struct rtw89_tx_shape_lmt_ru_data { 4296 struct rtw89_txpwr_conf conf; 4297 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4298 }; 4299 4300 struct rtw89_rfe_data { 4301 struct rtw89_txpwr_byrate_data byrate; 4302 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4303 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4304 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4305 struct rtw89_txpwr_lmt_2ghz_data da_lmt_2ghz; 4306 struct rtw89_txpwr_lmt_5ghz_data da_lmt_5ghz; 4307 struct rtw89_txpwr_lmt_6ghz_data da_lmt_6ghz; 4308 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4309 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4310 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4311 struct rtw89_txpwr_lmt_ru_2ghz_data da_lmt_ru_2ghz; 4312 struct rtw89_txpwr_lmt_ru_5ghz_data da_lmt_ru_5ghz; 4313 struct rtw89_txpwr_lmt_ru_6ghz_data da_lmt_ru_6ghz; 4314 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4315 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4316 struct rtw89_rfe_parms rfe_parms; 4317 }; 4318 4319 struct rtw89_page_regs { 4320 u32 hci_fc_ctrl; 4321 u32 ch_page_ctrl; 4322 u32 ach_page_ctrl; 4323 u32 ach_page_info; 4324 u32 pub_page_info3; 4325 u32 pub_page_ctrl1; 4326 u32 pub_page_ctrl2; 4327 u32 pub_page_info1; 4328 u32 pub_page_info2; 4329 u32 wp_page_ctrl1; 4330 u32 wp_page_ctrl2; 4331 u32 wp_page_info1; 4332 }; 4333 4334 struct rtw89_imr_info { 4335 u32 wdrls_imr_set; 4336 u32 wsec_imr_reg; 4337 u32 wsec_imr_set; 4338 u32 mpdu_tx_imr_set; 4339 u32 mpdu_rx_imr_set; 4340 u32 sta_sch_imr_set; 4341 u32 txpktctl_imr_b0_reg; 4342 u32 txpktctl_imr_b0_clr; 4343 u32 txpktctl_imr_b0_set; 4344 u32 txpktctl_imr_b1_reg; 4345 u32 txpktctl_imr_b1_clr; 4346 u32 txpktctl_imr_b1_set; 4347 u32 wde_imr_clr; 4348 u32 wde_imr_set; 4349 u32 ple_imr_clr; 4350 u32 ple_imr_set; 4351 u32 host_disp_imr_clr; 4352 u32 host_disp_imr_set; 4353 u32 cpu_disp_imr_clr; 4354 u32 cpu_disp_imr_set; 4355 u32 other_disp_imr_clr; 4356 u32 other_disp_imr_set; 4357 u32 bbrpt_com_err_imr_reg; 4358 u32 bbrpt_chinfo_err_imr_reg; 4359 u32 bbrpt_err_imr_set; 4360 u32 bbrpt_dfs_err_imr_reg; 4361 u32 ptcl_imr_clr; 4362 u32 ptcl_imr_set; 4363 u32 cdma_imr_0_reg; 4364 u32 cdma_imr_0_clr; 4365 u32 cdma_imr_0_set; 4366 u32 cdma_imr_1_reg; 4367 u32 cdma_imr_1_clr; 4368 u32 cdma_imr_1_set; 4369 u32 phy_intf_imr_reg; 4370 u32 phy_intf_imr_clr; 4371 u32 phy_intf_imr_set; 4372 u32 rmac_imr_reg; 4373 u32 rmac_imr_clr; 4374 u32 rmac_imr_set; 4375 u32 tmac_imr_reg; 4376 u32 tmac_imr_clr; 4377 u32 tmac_imr_set; 4378 }; 4379 4380 struct rtw89_imr_table { 4381 const struct rtw89_reg_imr *regs; 4382 u32 n_regs; 4383 }; 4384 4385 struct rtw89_xtal_info { 4386 u32 xcap_reg; 4387 u32 sc_xo_mask; 4388 u32 sc_xi_mask; 4389 }; 4390 4391 struct rtw89_rrsr_cfgs { 4392 struct rtw89_reg3_def ref_rate; 4393 struct rtw89_reg3_def rsc; 4394 }; 4395 4396 struct rtw89_rfkill_regs { 4397 struct rtw89_reg3_def pinmux; 4398 struct rtw89_reg3_def mode; 4399 }; 4400 4401 struct rtw89_sb_regs { 4402 struct { 4403 u32 cfg; 4404 u32 get; 4405 } n[2]; 4406 }; 4407 4408 struct rtw89_dig_regs { 4409 u32 seg0_pd_reg; 4410 u32 pd_lower_bound_mask; 4411 u32 pd_spatial_reuse_en; 4412 u32 bmode_pd_reg; 4413 u32 bmode_cca_rssi_limit_en; 4414 u32 bmode_pd_lower_bound_reg; 4415 u32 bmode_rssi_nocca_low_th_mask; 4416 struct rtw89_reg_def p0_lna_init; 4417 struct rtw89_reg_def p1_lna_init; 4418 struct rtw89_reg_def p0_tia_init; 4419 struct rtw89_reg_def p1_tia_init; 4420 struct rtw89_reg_def p0_rxb_init; 4421 struct rtw89_reg_def p1_rxb_init; 4422 struct rtw89_reg_def p0_p20_pagcugc_en; 4423 struct rtw89_reg_def p0_s20_pagcugc_en; 4424 struct rtw89_reg_def p1_p20_pagcugc_en; 4425 struct rtw89_reg_def p1_s20_pagcugc_en; 4426 }; 4427 4428 struct rtw89_edcca_regs { 4429 u32 edcca_level; 4430 u32 edcca_mask; 4431 u32 edcca_p_mask; 4432 u32 ppdu_level; 4433 u32 ppdu_mask; 4434 struct rtw89_edcca_p_regs { 4435 u32 rpt_a; 4436 u32 rpt_b; 4437 u32 rpt_sel; 4438 u32 rpt_sel_mask; 4439 } p[RTW89_PHY_NUM]; 4440 u32 rpt_sel_be; 4441 u32 rpt_sel_be_mask; 4442 u32 tx_collision_t2r_st; 4443 u32 tx_collision_t2r_st_mask; 4444 }; 4445 4446 struct rtw89_phy_ul_tb_info { 4447 bool dyn_tb_tri_en; 4448 u8 def_if_bandedge; 4449 }; 4450 4451 struct rtw89_antdiv_stats { 4452 struct ewma_rssi cck_rssi_avg; 4453 struct ewma_rssi ofdm_rssi_avg; 4454 struct ewma_rssi non_legacy_rssi_avg; 4455 u16 pkt_cnt_cck; 4456 u16 pkt_cnt_ofdm; 4457 u16 pkt_cnt_non_legacy; 4458 u32 evm; 4459 }; 4460 4461 struct rtw89_antdiv_info { 4462 struct rtw89_antdiv_stats target_stats; 4463 struct rtw89_antdiv_stats main_stats; 4464 struct rtw89_antdiv_stats aux_stats; 4465 u8 training_count; 4466 u8 rssi_pre; 4467 bool get_stats; 4468 }; 4469 4470 enum rtw89_chanctx_state { 4471 RTW89_CHANCTX_STATE_MCC_START, 4472 RTW89_CHANCTX_STATE_MCC_STOP, 4473 }; 4474 4475 enum rtw89_chanctx_callbacks { 4476 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4477 RTW89_CHANCTX_CALLBACK_RFK, 4478 RTW89_CHANCTX_CALLBACK_TAS, 4479 4480 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4481 }; 4482 4483 struct rtw89_chanctx_listener { 4484 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4485 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4486 }; 4487 4488 #define RTW89_NHM_TH_NUM 11 4489 #define RTW89_NHM_RPT_NUM 12 4490 4491 struct rtw89_chip_info { 4492 enum rtw89_core_chip_id chip_id; 4493 enum rtw89_chip_gen chip_gen; 4494 const struct rtw89_chip_ops *ops; 4495 const struct rtw89_mac_gen_def *mac_def; 4496 const struct rtw89_phy_gen_def *phy_def; 4497 const char *fw_basename; 4498 u8 fw_format_max; 4499 bool try_ce_fw; 4500 u8 bbmcu_nr; 4501 u32 needed_fw_elms; 4502 const struct rtw89_fw_blacklist *fw_blacklist; 4503 u32 fifo_size; 4504 bool small_fifo_size; 4505 u32 dle_scc_rsvd_size; 4506 u16 max_amsdu_limit; 4507 u16 max_vht_mpdu_cap; 4508 u16 max_eht_mpdu_cap; 4509 u16 max_tx_agg_num; 4510 u16 max_rx_agg_num; 4511 bool dis_2g_40m_ul_ofdma; 4512 u32 rsvd_ple_ofst; 4513 const struct rtw89_hfc_param_ini *hfc_param_ini[RTW89_HCI_TYPE_NUM]; 4514 const struct rtw89_dle_mem *dle_mem[RTW89_HCI_DLE_TYPE_NUM]; 4515 u8 wde_qempty_acq_grpnum; 4516 u8 wde_qempty_mgq_grpsel; 4517 u32 rf_base_addr[2]; 4518 u8 thermal_th[2]; 4519 u8 support_macid_num; 4520 u8 support_link_num; 4521 u8 support_chanctx_num; 4522 u8 support_bands; 4523 u16 support_bandwidths; 4524 bool support_unii4; 4525 bool support_rnr; 4526 bool support_ant_gain; 4527 bool support_tas; 4528 bool support_sar_by_ant; 4529 bool support_noise; 4530 bool ul_tb_waveform_ctrl; 4531 bool ul_tb_pwr_diff; 4532 bool rx_freq_frome_ie; 4533 bool hw_sec_hdr; 4534 bool hw_mgmt_tx_encrypt; 4535 bool hw_tkip_crypto; 4536 bool hw_mlo_bmc_crypto; 4537 u8 rf_path_num; 4538 u8 tx_nss; 4539 u8 rx_nss; 4540 u8 acam_num; 4541 u8 bcam_num; 4542 u8 scam_num; 4543 u8 bacam_num; 4544 u8 bacam_dynamic_num; 4545 enum rtw89_bacam_ver bacam_ver; 4546 u8 addrcam_ver; 4547 u8 ppdu_max_usr; 4548 4549 u8 sec_ctrl_efuse_size; 4550 u32 physical_efuse_size; 4551 u32 logical_efuse_size; 4552 u32 limit_efuse_size; 4553 u32 dav_phy_efuse_size; 4554 u32 dav_log_efuse_size; 4555 u32 phycap_addr; 4556 u32 phycap_size; 4557 const struct rtw89_efuse_block_cfg *efuse_blocks; 4558 4559 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4560 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4561 const struct rtw89_phy_table *bb_table; 4562 const struct rtw89_phy_table *bb_gain_table; 4563 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4564 const struct rtw89_phy_table *nctl_table; 4565 const struct rtw89_rfk_tbl *nctl_post_table; 4566 const struct rtw89_phy_dig_gain_table *dig_table; 4567 const struct rtw89_dig_regs *dig_regs; 4568 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4569 4570 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4571 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4572 const struct rtw89_rfe_parms *dflt_parms; 4573 const struct rtw89_chanctx_listener *chanctx_listener; 4574 4575 u8 txpwr_factor_bb; 4576 u8 txpwr_factor_rf; 4577 u8 txpwr_factor_mac; 4578 4579 u32 para_ver; 4580 u32 wlcx_desired; 4581 u8 scbd; 4582 u8 mailbox; 4583 4584 u8 afh_guard_ch; 4585 const u8 *wl_rssi_thres; 4586 const u8 *bt_rssi_thres; 4587 u8 rssi_tol; 4588 4589 u8 mon_reg_num; 4590 const struct rtw89_btc_fbtc_mreg *mon_reg; 4591 u8 rf_para_ulink_num; 4592 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4593 u8 rf_para_dlink_num; 4594 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4595 u8 ps_mode_supported; 4596 u8 low_power_hci_modes; 4597 4598 u32 h2c_cctl_func_id; 4599 u32 hci_func_en_addr; 4600 u32 h2c_desc_size; 4601 u32 txwd_body_size; 4602 u32 txwd_info_size; 4603 u32 h2c_ctrl_reg; 4604 const u32 *h2c_regs; 4605 struct rtw89_reg_def h2c_counter_reg; 4606 u32 c2h_ctrl_reg; 4607 const u32 *c2h_regs; 4608 struct rtw89_reg_def c2h_counter_reg; 4609 const struct rtw89_page_regs *page_regs; 4610 const u32 *wow_reason_reg; 4611 bool cfo_src_fd; 4612 bool cfo_hw_comp; 4613 const struct rtw89_reg_def *dcfo_comp; 4614 u8 dcfo_comp_sft; 4615 const struct rtw89_reg_def (*nhm_report)[RTW89_NHM_RPT_NUM]; 4616 const struct rtw89_reg_def (*nhm_th)[RTW89_NHM_TH_NUM]; 4617 const struct rtw89_imr_info *imr_info; 4618 const struct rtw89_imr_table *imr_dmac_table; 4619 const struct rtw89_imr_table *imr_cmac_table; 4620 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4621 struct rtw89_reg_def bss_clr_vld; 4622 u32 bss_clr_map_reg; 4623 const struct rtw89_rfkill_regs *rfkill_init; 4624 struct rtw89_reg_def rfkill_get; 4625 struct rtw89_sb_regs btc_sb; 4626 u32 dma_ch_mask; 4627 const struct rtw89_edcca_regs *edcca_regs; 4628 const struct wiphy_wowlan_support *wowlan_stub; 4629 const struct rtw89_xtal_info *xtal_info; 4630 unsigned long default_quirks; /* bitmap of rtw89_quirks */ 4631 }; 4632 4633 struct rtw89_chip_variant { 4634 bool no_mcs_12_13: 1; 4635 u32 fw_min_ver_code; 4636 }; 4637 4638 union rtw89_bus_info { 4639 const struct rtw89_pci_info *pci; 4640 const struct rtw89_usb_info *usb; 4641 }; 4642 4643 struct rtw89_driver_info { 4644 const struct rtw89_chip_info *chip; 4645 const struct rtw89_chip_variant *variant; 4646 const struct dmi_system_id *quirks; 4647 union rtw89_bus_info bus; 4648 }; 4649 4650 enum rtw89_hcifc_mode { 4651 RTW89_HCIFC_POH = 0, 4652 RTW89_HCIFC_STF = 1, 4653 RTW89_HCIFC_SDIO = 2, 4654 4655 /* keep last */ 4656 RTW89_HCIFC_MODE_INVALID, 4657 }; 4658 4659 struct rtw89_dle_info { 4660 const struct rtw89_rsvd_quota *rsvd_qt; 4661 const struct rtw89_dle_input *dle_input; 4662 enum rtw89_qta_mode qta_mode; 4663 u16 ple_pg_size; 4664 u16 ple_free_pg; 4665 u16 c0_rx_qta; 4666 u16 c1_rx_qta; 4667 }; 4668 4669 enum rtw89_host_rpr_mode { 4670 RTW89_RPR_MODE_POH = 0, 4671 RTW89_RPR_MODE_STF 4672 }; 4673 4674 #define RTW89_COMPLETION_BUF_SIZE 40 4675 #define RTW89_WAIT_COND_IDLE UINT_MAX 4676 4677 struct rtw89_completion_data { 4678 bool err; 4679 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4680 }; 4681 4682 struct rtw89_wait_response { 4683 struct rcu_head rcu_head; 4684 struct completion completion; 4685 struct rtw89_completion_data data; 4686 }; 4687 4688 struct rtw89_wait_info { 4689 atomic_t cond; 4690 struct rtw89_completion_data data; 4691 struct rtw89_wait_response __rcu *resp; 4692 }; 4693 4694 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4695 4696 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4697 { 4698 rcu_assign_pointer(wait->resp, NULL); 4699 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4700 } 4701 4702 struct rtw89_mac_info { 4703 struct rtw89_dle_info dle_info; 4704 struct rtw89_hfc_param hfc_param; 4705 enum rtw89_qta_mode qta_mode; 4706 u8 rpwm_seq_num; 4707 u8 cpwm_seq_num; 4708 4709 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4710 struct rtw89_wait_info fw_ofld_wait; 4711 /* see RTW89_PS_WAIT_COND series for wait condition */ 4712 struct rtw89_wait_info ps_wait; 4713 }; 4714 4715 enum rtw89_fwdl_check_type { 4716 RTW89_FWDL_CHECK_FREERTOS_DONE, 4717 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4718 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4719 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4720 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4721 }; 4722 4723 enum rtw89_fw_type { 4724 RTW89_FW_NORMAL = 1, 4725 RTW89_FW_WOWLAN = 3, 4726 RTW89_FW_NORMAL_CE = 5, 4727 RTW89_FW_BBMCU0 = 64, 4728 RTW89_FW_BBMCU1 = 65, 4729 RTW89_FW_LOGFMT = 255, 4730 }; 4731 4732 #define RTW89_FW_FEATURE_GROUP(_grp, _features...) \ 4733 RTW89_FW_FEATURE_##_grp##_MIN, \ 4734 __RTW89_FW_FEATURE_##_grp##_S = RTW89_FW_FEATURE_##_grp##_MIN - 1, \ 4735 _features \ 4736 __RTW89_FW_FEATURE_##_grp##_E, \ 4737 RTW89_FW_FEATURE_##_grp##_MAX = __RTW89_FW_FEATURE_##_grp##_E - 1 4738 4739 enum rtw89_fw_feature { 4740 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4741 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4742 RTW89_FW_FEATURE_TX_WAKE, 4743 RTW89_FW_FEATURE_GROUP(CRASH_TRIGGER, 4744 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_0, 4745 RTW89_FW_FEATURE_CRASH_TRIGGER_TYPE_1, 4746 ), 4747 RTW89_FW_FEATURE_NO_PACKET_DROP, 4748 RTW89_FW_FEATURE_NO_DEEP_PS, 4749 RTW89_FW_FEATURE_NO_LPS_PG, 4750 RTW89_FW_FEATURE_BEACON_FILTER, 4751 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4752 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4753 RTW89_FW_FEATURE_WOW_REASON_V1, 4754 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, 4755 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4756 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4757 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V2, 4758 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V3, 4759 ), 4760 RTW89_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY_MCC, 4761 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V0, 4762 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V1, 4763 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_MCC_V2, 4764 ), 4765 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4766 RTW89_FW_FEATURE_RFK_IQK_V0, 4767 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4768 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4769 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4770 RTW89_FW_FEATURE_LPS_CH_INFO, 4771 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4772 RTW89_FW_FEATURE_NO_POWER_DIFFERENCE, 4773 RTW89_FW_FEATURE_BEACON_LOSS_COUNT_V1, 4774 RTW89_FW_FEATURE_SCAN_OFFLOAD_EXTRA_OP, 4775 RTW89_FW_FEATURE_RFK_NTFY_MCC_V0, 4776 RTW89_FW_FEATURE_LPS_DACK_BY_C2H_REG, 4777 RTW89_FW_FEATURE_BEACON_TRACKING, 4778 RTW89_FW_FEATURE_ADDR_CAM_V0, 4779 RTW89_FW_FEATURE_SER_L1_BY_EVENT, 4780 RTW89_FW_FEATURE_SIM_SER_L0L1_BY_HALT_H2C, 4781 RTW89_FW_FEATURE_LPS_ML_INFO_V1, 4782 4783 NUM_OF_RTW89_FW_FEATURES, 4784 }; 4785 4786 struct rtw89_fw_suit { 4787 enum rtw89_fw_type type; 4788 const u8 *data; 4789 u32 size; 4790 u8 major_ver; 4791 u8 minor_ver; 4792 u8 sub_ver; 4793 u8 sub_idex; 4794 u16 build_year; 4795 u16 build_mon; 4796 u16 build_date; 4797 u16 build_hour; 4798 u16 build_min; 4799 u8 cmd_ver; 4800 u8 hdr_ver; 4801 u32 commitid; 4802 }; 4803 4804 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4805 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4806 #define RTW89_FW_SUIT_VER_CODE(s) \ 4807 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4808 4809 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4810 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4811 (mfw_hdr)->ver.minor, \ 4812 (mfw_hdr)->ver.sub, \ 4813 (mfw_hdr)->ver.idx) 4814 4815 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4816 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4817 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4818 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4819 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4820 4821 struct rtw89_fw_req_info { 4822 const struct firmware *firmware; 4823 struct completion completion; 4824 }; 4825 4826 struct rtw89_fw_log { 4827 struct rtw89_fw_suit suit; 4828 bool enable; 4829 u32 last_fmt_id; 4830 u32 fmt_count; 4831 const __le32 *fmt_ids; 4832 const char *(*fmts)[]; 4833 }; 4834 4835 struct rtw89_fw_elm_info { 4836 struct rtw89_phy_table *bb_tbl; 4837 struct rtw89_phy_table *bb_gain; 4838 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4839 struct rtw89_phy_table *rf_nctl; 4840 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4841 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4842 const struct rtw89_regd_data *regd; 4843 const struct rtw89_fw_element_hdr *afe; 4844 const struct rtw89_fw_element_hdr *diag_mac; 4845 const struct rtw89_fw_element_hdr *tx_comp; 4846 }; 4847 4848 enum rtw89_fw_mss_dev_type { 4849 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4850 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4851 }; 4852 4853 struct rtw89_fw_secure { 4854 bool secure_boot: 1; 4855 bool can_mss_v1: 1; 4856 bool can_mss_v0: 1; 4857 u32 sb_sel_mgn; 4858 u8 mss_dev_type; 4859 u8 mss_cust_idx; 4860 u8 mss_key_num; 4861 u8 mss_idx; /* v0 */ 4862 }; 4863 4864 struct rtw89_fw_info { 4865 struct rtw89_fw_req_info req; 4866 int fw_format; 4867 u8 h2c_seq; 4868 u8 rec_seq; 4869 u8 h2c_counter; 4870 u8 c2h_counter; 4871 struct rtw89_fw_suit normal; 4872 struct rtw89_fw_suit wowlan; 4873 struct rtw89_fw_suit bbmcu0; 4874 struct rtw89_fw_suit bbmcu1; 4875 struct rtw89_fw_log log; 4876 struct rtw89_fw_elm_info elm_info; 4877 struct rtw89_fw_secure sec; 4878 4879 DECLARE_BITMAP(feature_map, NUM_OF_RTW89_FW_FEATURES); 4880 }; 4881 4882 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4883 test_bit(RTW89_FW_FEATURE_ ## _feat, (_fw)->feature_map) 4884 4885 #define RTW89_CHK_FW_FEATURE_GROUP(_grp, _fw) \ 4886 ({ \ 4887 unsigned int bit = find_next_bit((_fw)->feature_map, \ 4888 NUM_OF_RTW89_FW_FEATURES, \ 4889 RTW89_FW_FEATURE_ ## _grp ## _MIN); \ 4890 bit <= RTW89_FW_FEATURE_ ## _grp ## _MAX; \ 4891 }) 4892 4893 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4894 set_bit(_fw_feature, (_fw)->feature_map) 4895 4896 #define RTW89_CLR_FW_FEATURE(_fw_feature, _fw) \ 4897 clear_bit(_fw_feature, (_fw)->feature_map) 4898 4899 struct rtw89_cam_info { 4900 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4901 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4902 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4903 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4904 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4905 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4906 }; 4907 4908 enum rtw89_sar_sources { 4909 RTW89_SAR_SOURCE_NONE, 4910 RTW89_SAR_SOURCE_COMMON, 4911 RTW89_SAR_SOURCE_ACPI, 4912 4913 RTW89_SAR_SOURCE_NR, 4914 }; 4915 4916 enum rtw89_sar_subband { 4917 RTW89_SAR_2GHZ_SUBBAND, 4918 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4919 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4920 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4921 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4922 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4923 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4924 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4925 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4926 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4927 4928 RTW89_SAR_SUBBAND_NR, 4929 }; 4930 4931 struct rtw89_sar_cfg_common { 4932 bool set[RTW89_SAR_SUBBAND_NR]; 4933 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4934 }; 4935 4936 enum rtw89_acpi_sar_subband { 4937 RTW89_ACPI_SAR_2GHZ_SUBBAND, 4938 RTW89_ACPI_SAR_5GHZ_SUBBAND_1, /* U-NII-1 */ 4939 RTW89_ACPI_SAR_5GHZ_SUBBAND_2, /* U-NII-2 */ 4940 RTW89_ACPI_SAR_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4941 RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4942 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4943 RTW89_ACPI_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4944 RTW89_ACPI_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4945 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4946 RTW89_ACPI_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4947 RTW89_ACPI_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4948 4949 NUM_OF_RTW89_ACPI_SAR_SUBBAND, 4950 RTW89_ACPI_SAR_SUBBAND_NR_LEGACY = RTW89_ACPI_SAR_5GHZ_SUBBAND_3_4 + 1, 4951 RTW89_ACPI_SAR_SUBBAND_NR_HAS_6GHZ = RTW89_ACPI_SAR_6GHZ_SUBBAND_8 + 1, 4952 }; 4953 4954 #define TXPWR_FACTOR_OF_RTW89_ACPI_SAR 3 /* unit: 0.125 dBm */ 4955 #define MAX_VAL_OF_RTW89_ACPI_SAR S16_MAX 4956 #define MIN_VAL_OF_RTW89_ACPI_SAR S16_MIN 4957 #define MAX_NUM_OF_RTW89_ACPI_SAR_TBL 6 4958 #define NUM_OF_RTW89_ACPI_SAR_RF_PATH (RF_PATH_B + 1) 4959 4960 struct rtw89_sar_entry_from_acpi { 4961 s16 v[NUM_OF_RTW89_ACPI_SAR_SUBBAND][NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4962 }; 4963 4964 struct rtw89_sar_table_from_acpi { 4965 /* If this table is active, must fill all fields according to either 4966 * configuration in BIOS or some default values for SAR to work well. 4967 */ 4968 struct rtw89_sar_entry_from_acpi entries[RTW89_REGD_NUM]; 4969 }; 4970 4971 struct rtw89_sar_indicator_from_acpi { 4972 bool enable_sync; 4973 unsigned int fields; 4974 u8 (*rfpath_to_antidx)(enum rtw89_rf_path rfpath); 4975 4976 /* Select among @tables of container, rtw89_sar_cfg_acpi, by path. 4977 * Not design with pointers since addresses will be invalid after 4978 * sync content with local container instance. 4979 */ 4980 u8 tblsel[NUM_OF_RTW89_ACPI_SAR_RF_PATH]; 4981 }; 4982 4983 struct rtw89_sar_cfg_acpi { 4984 u8 downgrade_2tx; 4985 unsigned int valid_num; 4986 struct rtw89_sar_table_from_acpi tables[MAX_NUM_OF_RTW89_ACPI_SAR_TBL]; 4987 struct rtw89_sar_indicator_from_acpi indicator; 4988 }; 4989 4990 struct rtw89_sar_info { 4991 /* used to decide how to access SAR cfg union */ 4992 enum rtw89_sar_sources src; 4993 4994 /* reserved for different knids of SAR cfg struct. 4995 * supposed that a single cfg struct cannot handle various SAR sources. 4996 */ 4997 union { 4998 struct rtw89_sar_cfg_common cfg_common; 4999 struct rtw89_sar_cfg_acpi cfg_acpi; 5000 }; 5001 }; 5002 5003 enum rtw89_ant_gain_subband { 5004 RTW89_ANT_GAIN_2GHZ_SUBBAND, 5005 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 5006 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 5007 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 5008 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 5009 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 5010 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 5011 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 5012 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 5013 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 5014 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 5015 5016 RTW89_ANT_GAIN_SUBBAND_NR, 5017 }; 5018 5019 enum rtw89_ant_gain_domain_type { 5020 RTW89_ANT_GAIN_ETSI = 0, 5021 5022 RTW89_ANT_GAIN_DOMAIN_NUM, 5023 }; 5024 5025 #define RTW89_ANT_GAIN_CHAIN_NUM 2 5026 struct rtw89_ant_gain_info { 5027 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 5028 u32 regd_enabled; 5029 bool block_country; 5030 }; 5031 5032 struct rtw89_6ghz_span { 5033 enum rtw89_sar_subband sar_subband_low; 5034 enum rtw89_sar_subband sar_subband_high; 5035 enum rtw89_acpi_sar_subband acpi_sar_subband_low; 5036 enum rtw89_acpi_sar_subband acpi_sar_subband_high; 5037 enum rtw89_ant_gain_subband ant_gain_subband_low; 5038 enum rtw89_ant_gain_subband ant_gain_subband_high; 5039 }; 5040 5041 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 5042 #define RTW89_ACPI_SAR_SPAN_VALID(span) ((span)->acpi_sar_subband_high) 5043 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 5044 5045 enum rtw89_tas_state { 5046 RTW89_TAS_STATE_DPR_OFF, 5047 RTW89_TAS_STATE_DPR_ON, 5048 RTW89_TAS_STATE_STATIC_SAR, 5049 }; 5050 5051 #define RTW89_TAS_TX_RATIO_WINDOW 6 5052 #define RTW89_TAS_TXPWR_WINDOW 180 5053 struct rtw89_tas_info { 5054 u16 tx_ratio_history[RTW89_TAS_TX_RATIO_WINDOW]; 5055 u64 txpwr_history[RTW89_TAS_TXPWR_WINDOW]; 5056 u8 enabled_countries; 5057 u8 txpwr_head_idx; 5058 u8 txpwr_tail_idx; 5059 u8 tx_ratio_idx; 5060 u16 total_tx_ratio; 5061 u64 total_txpwr; 5062 u64 instant_txpwr; 5063 u32 window_size; 5064 s8 dpr_on_threshold; 5065 s8 dpr_off_threshold; 5066 enum rtw89_tas_state backup_state; 5067 enum rtw89_tas_state state; 5068 bool keep_history; 5069 bool block_regd; 5070 bool enable; 5071 bool pause; 5072 }; 5073 5074 struct rtw89_chanctx_cfg { 5075 enum rtw89_chanctx_idx idx; 5076 int ref_count; 5077 }; 5078 5079 enum rtw89_chanctx_changes { 5080 RTW89_CHANCTX_REMOTE_STA_CHANGE, 5081 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 5082 RTW89_CHANCTX_P2P_PS_CHANGE, 5083 RTW89_CHANCTX_BT_SLOT_CHANGE, 5084 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 5085 5086 NUM_OF_RTW89_CHANCTX_CHANGES, 5087 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 5088 }; 5089 5090 enum rtw89_entity_mode { 5091 RTW89_ENTITY_MODE_SCC_OR_SMLD, 5092 RTW89_ENTITY_MODE_MCC_PREPARE, 5093 RTW89_ENTITY_MODE_MCC, 5094 5095 NUM_OF_RTW89_ENTITY_MODE, 5096 RTW89_ENTITY_MODE_INVALID = -EINVAL, 5097 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 5098 }; 5099 5100 #define RTW89_MAX_INTERFACE_NUM 2 5101 5102 /* only valid when running with chanctx_ops */ 5103 struct rtw89_entity_mgnt { 5104 struct list_head active_list; 5105 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 5106 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 5107 [__RTW89_MLD_MAX_LINK_NUM]; 5108 }; 5109 5110 struct rtw89_chanctx { 5111 struct cfg80211_chan_def chandef; 5112 struct rtw89_chan chan; 5113 struct rtw89_chan_rcd rcd; 5114 5115 /* only assigned when running with chanctx_ops */ 5116 struct rtw89_chanctx_cfg *cfg; 5117 }; 5118 5119 struct rtw89_edcca_bak { 5120 u8 a; 5121 u8 p; 5122 u8 ppdu; 5123 u8 th_old; 5124 }; 5125 5126 enum rtw89_dm_type { 5127 RTW89_DM_DYNAMIC_EDCCA, 5128 RTW89_DM_THERMAL_PROTECT, 5129 RTW89_DM_TAS, 5130 RTW89_DM_MLO, 5131 }; 5132 5133 #define RTW89_THERMAL_PROT_LV_MAX 5 5134 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 5135 5136 struct rtw89_hal { 5137 u32 rx_fltr; 5138 u8 cv; 5139 u8 cid; /* enum rtw89_core_chip_cid */ 5140 u8 acv; 5141 u16 aid; /* enum rtw89_core_chip_aid */ 5142 u32 antenna_tx; 5143 u32 antenna_rx; 5144 u8 tx_nss; 5145 u8 rx_nss; 5146 bool tx_path_diversity; 5147 bool ant_diversity; 5148 bool ant_diversity_fixed; 5149 bool support_cckpd; 5150 bool support_igi; 5151 bool no_mcs_12_13; 5152 bool no_eht; 5153 5154 atomic_t roc_chanctx_idx; 5155 u8 roc_link_index; 5156 5157 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 5158 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 5159 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 5160 struct cfg80211_chan_def roc_chandef; 5161 5162 bool entity_active[RTW89_PHY_NUM]; 5163 bool entity_pause; 5164 enum rtw89_entity_mode entity_mode; 5165 struct rtw89_entity_mgnt entity_mgnt; 5166 5167 enum rtw89_phy_idx entity_force_hw; 5168 5169 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 5170 5171 u8 thermal_prot_th; 5172 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 5173 }; 5174 5175 #define RTW89_MAX_MAC_ID_NUM 128 5176 #define RTW89_MAX_PKT_OFLD_NUM 255 5177 5178 enum rtw89_flags { 5179 RTW89_FLAG_POWERON, 5180 RTW89_FLAG_DMAC_FUNC, 5181 RTW89_FLAG_CMAC0_FUNC, 5182 RTW89_FLAG_CMAC1_FUNC, 5183 RTW89_FLAG_CMAC0_PWR, 5184 RTW89_FLAG_CMAC1_PWR, 5185 RTW89_FLAG_FW_RDY, 5186 RTW89_FLAG_RUNNING, 5187 RTW89_FLAG_PROBE_DONE, 5188 RTW89_FLAG_BFEE_MON, 5189 RTW89_FLAG_BFEE_EN, 5190 RTW89_FLAG_BFEE_TIMER_KEEP, 5191 RTW89_FLAG_NAPI_RUNNING, 5192 RTW89_FLAG_LEISURE_PS, 5193 RTW89_FLAG_LOW_POWER_MODE, 5194 RTW89_FLAG_INACTIVE_PS, 5195 RTW89_FLAG_CRASH_SIMULATING, 5196 RTW89_FLAG_SER_HANDLING, 5197 RTW89_FLAG_WOWLAN, 5198 RTW89_FLAG_FORBIDDEN_TRACK_WORK, 5199 RTW89_FLAG_CHANGING_INTERFACE, 5200 RTW89_FLAG_HW_RFKILL_STATE, 5201 RTW89_FLAG_UNPLUGGED, 5202 5203 NUM_OF_RTW89_FLAGS, 5204 }; 5205 5206 enum rtw89_quirks { 5207 RTW89_QUIRK_PCI_BER, 5208 RTW89_QUIRK_THERMAL_PROT_120C, 5209 RTW89_QUIRK_THERMAL_PROT_110C, 5210 5211 NUM_OF_RTW89_QUIRKS, 5212 }; 5213 5214 enum rtw89_custid { 5215 RTW89_CUSTID_NONE = 0, 5216 RTW89_CUSTID_HP = 1, 5217 RTW89_CUSTID_ASUS = 2, 5218 RTW89_CUSTID_ACER = 3, 5219 RTW89_CUSTID_LENOVO = 4, 5220 RTW89_CUSTID_NEC = 5, 5221 RTW89_CUSTID_AMD = 6, 5222 RTW89_CUSTID_FUJITSU = 7, 5223 RTW89_CUSTID_DELL = 8, 5224 }; 5225 5226 enum rtw89_pkt_drop_sel { 5227 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 5228 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 5229 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 5230 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 5231 RTW89_PKT_DROP_SEL_MACID_ALL, 5232 RTW89_PKT_DROP_SEL_MG0_ONCE, 5233 RTW89_PKT_DROP_SEL_HIQ_ONCE, 5234 RTW89_PKT_DROP_SEL_HIQ_PORT, 5235 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 5236 RTW89_PKT_DROP_SEL_BAND, 5237 RTW89_PKT_DROP_SEL_BAND_ONCE, 5238 RTW89_PKT_DROP_SEL_REL_MACID, 5239 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 5240 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 5241 }; 5242 5243 struct rtw89_pkt_drop_params { 5244 enum rtw89_pkt_drop_sel sel; 5245 enum rtw89_mac_idx mac_band; 5246 u8 macid; 5247 u8 port; 5248 u8 mbssid; 5249 bool tf_trs; 5250 u32 macid_band_sel[4]; 5251 }; 5252 5253 struct rtw89_pkt_stat { 5254 u16 beacon_nr; 5255 u8 beacon_rate; 5256 u32 beacon_len; 5257 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 5258 }; 5259 5260 #define RTW89_BCN_TRACK_STAT_NR 32 5261 #define RTW89_BCN_TRACK_SCALE_FACTOR 10 5262 #define RTW89_BCN_TRACK_MAX_BIN_NUM 6 5263 #define RTW89_BCN_TRACK_BIN_WIDTH 5 5264 #define RTW89_BCN_TRACK_TARGET_BCN 80 5265 5266 struct rtw89_beacon_dist { 5267 u16 min; 5268 u16 max; 5269 u16 outlier_count; 5270 u16 lower_bound; 5271 u16 upper_bound; 5272 u16 bins[RTW89_BCN_TRACK_MAX_BIN_NUM]; 5273 }; 5274 5275 struct rtw89_beacon_stat { 5276 u8 num; 5277 u8 wp; 5278 u16 tbtt_tu_min; 5279 u16 tbtt_tu_max; 5280 u16 drift[RTW89_BCN_TRACK_STAT_NR]; 5281 u32 tbtt_us[RTW89_BCN_TRACK_STAT_NR]; 5282 u16 tbtt_tu[RTW89_BCN_TRACK_STAT_NR]; 5283 struct rtw89_beacon_dist bcn_dist; 5284 }; 5285 5286 DECLARE_EWMA(thermal, 4, 4); 5287 5288 struct rtw89_phy_stat { 5289 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 5290 u8 last_thermal_max; 5291 struct ewma_rssi bcn_rssi; 5292 struct rtw89_pkt_stat cur_pkt_stat; 5293 struct rtw89_pkt_stat last_pkt_stat; 5294 struct rtw89_beacon_stat bcn_stat; 5295 }; 5296 5297 enum rtw89_rfk_report_state { 5298 RTW89_RFK_STATE_START = 0x0, 5299 RTW89_RFK_STATE_OK = 0x1, 5300 RTW89_RFK_STATE_FAIL = 0x2, 5301 RTW89_RFK_STATE_TIMEOUT = 0x3, 5302 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 5303 }; 5304 5305 struct rtw89_rfk_wait_info { 5306 struct completion completion; 5307 ktime_t start_time; 5308 enum rtw89_rfk_report_state state; 5309 u8 version; 5310 }; 5311 5312 #define RTW89_DACK_PATH_NR 2 5313 #define RTW89_DACK_IDX_NR 2 5314 #define RTW89_DACK_MSBK_NR 16 5315 struct rtw89_dack_info { 5316 bool dack_done; 5317 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 5318 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5319 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5320 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 5321 u32 dack_cnt; 5322 bool addck_timeout[RTW89_DACK_PATH_NR]; 5323 bool dadck_timeout[RTW89_DACK_PATH_NR]; 5324 bool msbk_timeout[RTW89_DACK_PATH_NR]; 5325 }; 5326 5327 enum rtw89_rfk_chs_nrs { 5328 __RTW89_RFK_CHS_NR_V0 = 2, 5329 __RTW89_RFK_CHS_NR_V1 = 3, 5330 5331 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 5332 }; 5333 5334 struct rtw89_rfk_mcc_info_data { 5335 u8 ch[RTW89_RFK_CHS_NR]; 5336 u8 band[RTW89_RFK_CHS_NR]; 5337 u8 bw[RTW89_RFK_CHS_NR]; 5338 u32 rf18[RTW89_RFK_CHS_NR]; 5339 u8 table_idx; 5340 }; 5341 5342 struct rtw89_rfk_mcc_info { 5343 struct rtw89_rfk_mcc_info_data data[2]; 5344 }; 5345 5346 #define RTW89_IQK_CHS_NR 2 5347 #define RTW89_IQK_PATH_NR 4 5348 5349 struct rtw89_lck_info { 5350 u8 thermal[RF_PATH_MAX]; 5351 }; 5352 5353 struct rtw89_rx_dck_info { 5354 u8 thermal[RF_PATH_MAX]; 5355 }; 5356 5357 struct rtw89_iqk_info { 5358 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5359 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5360 bool lok_fail[RTW89_IQK_PATH_NR]; 5361 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5362 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5363 u32 iqk_fail_cnt; 5364 bool is_iqk_init; 5365 u32 iqk_channel[RTW89_IQK_CHS_NR]; 5366 u8 iqk_band[RTW89_IQK_PATH_NR]; 5367 u8 iqk_ch[RTW89_IQK_PATH_NR]; 5368 u8 iqk_bw[RTW89_IQK_PATH_NR]; 5369 u8 iqk_times; 5370 u8 version; 5371 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 5372 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 5373 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 5374 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 5375 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 5376 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 5377 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 5378 bool is_nbiqk; 5379 bool iqk_fft_en; 5380 bool iqk_xym_en; 5381 bool iqk_sram_en; 5382 bool iqk_cfir_en; 5383 u32 syn1to2; 5384 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5385 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 5386 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5387 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 5388 }; 5389 5390 #define RTW89_DPK_RF_PATH 2 5391 #define RTW89_DPK_AVG_THERMAL_NUM 8 5392 #define RTW89_DPK_BKUP_NUM 2 5393 struct rtw89_dpk_bkup_para { 5394 enum rtw89_band band; 5395 enum rtw89_bandwidth bw; 5396 u8 ch; 5397 u8 path_ok; 5398 u8 mdpd_en; 5399 u8 txagc_dpk; 5400 u8 ther_dpk; 5401 u8 gs; 5402 u16 pwsf; 5403 }; 5404 5405 struct rtw89_dpk_info { 5406 bool is_dpk_enable; 5407 bool is_dpk_reload_en; 5408 u8 dpk_gs[RTW89_PHY_NUM]; 5409 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5410 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5411 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5412 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5413 u8 cur_idx[RTW89_DPK_RF_PATH]; 5414 u8 cur_k_set; 5415 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 5416 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 5417 u32 dpk_order[RTW89_DPK_RF_PATH]; 5418 }; 5419 5420 struct rtw89_fem_info { 5421 bool elna_2g; 5422 bool elna_5g; 5423 bool epa_2g; 5424 bool epa_5g; 5425 bool epa_6g; 5426 }; 5427 5428 struct rtw89_phy_ch_info { 5429 u8 rssi_min; 5430 u16 rssi_min_macid; 5431 u8 pre_rssi_min; 5432 u8 rssi_max; 5433 u16 rssi_max_macid; 5434 u8 rxsc_160; 5435 u8 rxsc_80; 5436 u8 rxsc_40; 5437 u8 rxsc_20; 5438 u8 rxsc_l; 5439 u8 is_noisy; 5440 }; 5441 5442 struct rtw89_agc_gaincode_set { 5443 u8 lna_idx; 5444 u8 tia_idx; 5445 u8 rxb_idx; 5446 }; 5447 5448 #define IGI_RSSI_TH_NUM 5 5449 #define FA_TH_NUM 4 5450 #define TIA_LNA_OP1DB_NUM 8 5451 #define LNA_GAIN_NUM 7 5452 #define TIA_GAIN_NUM 2 5453 struct rtw89_dig_info { 5454 struct rtw89_agc_gaincode_set cur_gaincode; 5455 bool force_gaincode_idx_en; 5456 struct rtw89_agc_gaincode_set force_gaincode; 5457 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5458 u16 fa_th[FA_TH_NUM]; 5459 u8 igi_rssi; 5460 u8 igi_fa_rssi; 5461 u8 fa_rssi_ofst; 5462 u8 dyn_igi_max; 5463 u8 dyn_igi_min; 5464 bool dyn_pd_th_en; 5465 u8 dyn_pd_th_max; 5466 u8 pd_low_th_ofst; 5467 u8 ib_pbk; 5468 s8 ib_pkpwr; 5469 s8 lna_gain_a[LNA_GAIN_NUM]; 5470 s8 lna_gain_g[LNA_GAIN_NUM]; 5471 s8 *lna_gain; 5472 s8 tia_gain_a[TIA_GAIN_NUM]; 5473 s8 tia_gain_g[TIA_GAIN_NUM]; 5474 s8 *tia_gain; 5475 u32 bak_dig; 5476 bool is_linked_pre; 5477 bool bypass_dig; 5478 bool pause_dig; 5479 }; 5480 5481 enum rtw89_multi_cfo_mode { 5482 RTW89_PKT_BASED_AVG_MODE = 0, 5483 RTW89_ENTRY_BASED_AVG_MODE = 1, 5484 RTW89_TP_BASED_AVG_MODE = 2, 5485 }; 5486 5487 enum rtw89_phy_cfo_status { 5488 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5489 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5490 RTW89_PHY_DCFO_STATE_HOLD = 2, 5491 RTW89_PHY_DCFO_STATE_MAX 5492 }; 5493 5494 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5495 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5496 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5497 }; 5498 5499 struct rtw89_cfo_tracking_info { 5500 u16 cfo_timer_ms; 5501 bool cfo_trig_by_timer_en; 5502 enum rtw89_phy_cfo_status phy_cfo_status; 5503 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5504 u8 phy_cfo_trk_cnt; 5505 bool is_adjust; 5506 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5507 bool apply_compensation; 5508 u8 crystal_cap; 5509 u8 crystal_cap_default; 5510 u8 def_x_cap; 5511 s8 x_cap_ofst; 5512 u32 sta_cfo_tolerance; 5513 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5514 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5515 s32 cfo_avg_pre; 5516 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5517 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5518 s32 dcfo_avg; 5519 s32 dcfo_avg_pre; 5520 u32 packet_count; 5521 u32 packet_count_pre; 5522 s32 residual_cfo_acc; 5523 u8 phy_cfotrk_state; 5524 u8 phy_cfotrk_cnt; 5525 bool divergence_lock_en; 5526 u8 x_cap_lb; 5527 u8 x_cap_ub; 5528 u8 lock_cnt; 5529 }; 5530 5531 enum rtw89_tssi_mode { 5532 RTW89_TSSI_NORMAL = 0, 5533 RTW89_TSSI_SCAN = 1, 5534 }; 5535 5536 enum rtw89_tssi_alimk_band { 5537 TSSI_ALIMK_2G = 0, 5538 TSSI_ALIMK_5GL, 5539 TSSI_ALIMK_5GM, 5540 TSSI_ALIMK_5GH, 5541 TSSI_ALIMK_MAX 5542 }; 5543 5544 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5545 #define TSSI_TRIM_CH_GROUP_NUM 8 5546 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5547 5548 #define TSSI_CCK_CH_GROUP_NUM 6 5549 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5550 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5551 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5552 #define TSSI_MCS_CH_GROUP_NUM \ 5553 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5554 #define TSSI_MAX_CH_NUM 67 5555 #define TSSI_ALIMK_VALUE_NUM 8 5556 5557 struct rtw89_tssi_info { 5558 u8 thermal[RF_PATH_MAX]; 5559 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5560 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5561 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5562 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5563 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5564 s8 extra_ofst[RF_PATH_MAX]; 5565 bool tssi_tracking_check[RF_PATH_MAX]; 5566 u8 default_txagc_offset[RF_PATH_MAX]; 5567 u32 base_thermal[RF_PATH_MAX]; 5568 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5569 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5570 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5571 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5572 u64 tssi_alimk_time; 5573 }; 5574 5575 struct rtw89_power_trim_info { 5576 bool pg_thermal_trim; 5577 bool pg_pa_bias_trim; 5578 u8 thermal_trim[RF_PATH_MAX]; 5579 u8 pa_bias_trim[RF_PATH_MAX]; 5580 u8 pad_bias_trim[RF_PATH_MAX]; 5581 }; 5582 5583 enum rtw89_regd_func { 5584 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 5585 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 5586 5587 NUM_OF_RTW89_REGD_FUNC, 5588 }; 5589 5590 struct rtw89_regd { 5591 char alpha2[3]; 5592 u8 txpwr_regd[RTW89_BAND_NUM]; 5593 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 5594 }; 5595 5596 struct rtw89_regd_data { 5597 unsigned int nr; 5598 struct rtw89_regd map[] __counted_by(nr); 5599 }; 5600 5601 struct rtw89_regd_ctrl { 5602 unsigned int nr; 5603 const struct rtw89_regd *map; 5604 }; 5605 5606 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5607 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5608 #define RTW89_5GHZ_UNII4_START_INDEX 25 5609 5610 struct rtw89_regulatory_info { 5611 struct rtw89_regd_ctrl ctrl; 5612 const struct rtw89_regd *regd; 5613 bool programmed; 5614 5615 enum rtw89_reg_6ghz_power reg_6ghz_power; 5616 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5617 bool txpwr_uk_follow_etsi; 5618 5619 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5620 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5621 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5622 DECLARE_BITMAP(block_6ghz_vlp, RTW89_REGD_MAX_COUNTRY_NUM); 5623 }; 5624 5625 enum rtw89_ifs_clm_application { 5626 RTW89_IFS_CLM_INIT = 0, 5627 RTW89_IFS_CLM_BACKGROUND = 1, 5628 RTW89_IFS_CLM_ACS = 2, 5629 RTW89_IFS_CLM_DIG = 3, 5630 RTW89_IFS_CLM_TDMA_DIG = 4, 5631 RTW89_IFS_CLM_DBG = 5, 5632 RTW89_IFS_CLM_DBG_MANUAL = 6 5633 }; 5634 5635 enum rtw89_env_racing_lv { 5636 RTW89_RAC_RELEASE = 0, 5637 RTW89_RAC_LV_1 = 1, 5638 RTW89_RAC_LV_2 = 2, 5639 RTW89_RAC_LV_3 = 3, 5640 RTW89_RAC_LV_4 = 4, 5641 RTW89_RAC_MAX_NUM = 5 5642 }; 5643 5644 struct rtw89_ccx_para_info { 5645 enum rtw89_env_racing_lv rac_lv; 5646 u16 mntr_time; 5647 bool nhm_incld_cca; 5648 u8 nhm_manual_th_ofst; 5649 u8 nhm_manual_th0; 5650 enum rtw89_ifs_clm_application ifs_clm_app; 5651 u32 ifs_clm_manual_th_times; 5652 u32 ifs_clm_manual_th0; 5653 u8 fahm_manual_th_ofst; 5654 u8 fahm_manual_th0; 5655 u8 fahm_numer_opt; 5656 u8 fahm_denom_opt; 5657 }; 5658 5659 enum rtw89_ccx_edcca_opt_sc_idx { 5660 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5661 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5662 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5663 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5664 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5665 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5666 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5667 RTW89_CCX_EDCCA_SEG1_S3 = 7 5668 }; 5669 5670 enum rtw89_ccx_edcca_opt_bw_idx { 5671 RTW89_CCX_EDCCA_BW20_0 = 0, 5672 RTW89_CCX_EDCCA_BW20_1 = 1, 5673 RTW89_CCX_EDCCA_BW20_2 = 2, 5674 RTW89_CCX_EDCCA_BW20_3 = 3, 5675 RTW89_CCX_EDCCA_BW20_4 = 4, 5676 RTW89_CCX_EDCCA_BW20_5 = 5, 5677 RTW89_CCX_EDCCA_BW20_6 = 6, 5678 RTW89_CCX_EDCCA_BW20_7 = 7 5679 }; 5680 5681 struct rtw89_nhm_report { 5682 struct list_head list; 5683 struct ieee80211_channel *channel; 5684 u8 noise; 5685 }; 5686 5687 #define RTW89_FAHM_TH_NUM 11 5688 #define RTW89_FAHM_RPT_NUM 12 5689 #define RTW89_IFS_CLM_NUM 4 5690 struct rtw89_env_monitor_info { 5691 u8 ccx_watchdog_result; 5692 bool ccx_ongoing; 5693 u8 ccx_rac_lv; 5694 bool ccx_manual_ctrl; 5695 u16 ifs_clm_mntr_time; 5696 enum rtw89_ifs_clm_application ifs_clm_app; 5697 u16 ccx_period; 5698 u8 ccx_unit_idx; 5699 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5700 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5701 u16 ifs_clm_tx; 5702 u16 ifs_clm_edcca_excl_cca; 5703 u16 ifs_clm_ofdmfa; 5704 u16 ifs_clm_ofdmcca_excl_fa; 5705 u16 ifs_clm_cckfa; 5706 u16 ifs_clm_cckcca_excl_fa; 5707 u16 ifs_clm_total_ifs; 5708 u16 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5709 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5710 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5711 u8 ifs_clm_tx_ratio; 5712 u8 ifs_clm_edcca_excl_cca_ratio; 5713 u8 ifs_clm_cck_fa_ratio; 5714 u8 ifs_clm_ofdm_fa_ratio; 5715 u8 ifs_clm_cck_cca_excl_fa_ratio; 5716 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5717 u16 ifs_clm_cck_fa_permil; 5718 u16 ifs_clm_ofdm_fa_permil; 5719 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5720 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5721 bool nhm_include_cca; 5722 u32 nhm_sum; 5723 u32 nhm_mntr_time; 5724 u16 nhm_result[RTW89_NHM_RPT_NUM]; 5725 u8 nhm_th[RTW89_NHM_RPT_NUM]; 5726 struct rtw89_nhm_report *nhm_his[RTW89_BAND_NUM]; 5727 struct list_head nhm_rpt_list; 5728 }; 5729 5730 enum rtw89_ser_rcvy_step { 5731 RTW89_SER_DRV_STOP_TX, 5732 RTW89_SER_DRV_STOP_RX, 5733 RTW89_SER_DRV_STOP_RUN, 5734 RTW89_SER_HAL_STOP_DMA, 5735 RTW89_SER_SUPPRESS_LOG, 5736 RTW89_NUM_OF_SER_FLAGS 5737 }; 5738 5739 struct rtw89_ser { 5740 u8 state; 5741 u8 alarm_event; 5742 bool prehandle_l1; 5743 5744 struct work_struct ser_hdl_work; 5745 struct delayed_work ser_alarm_work; 5746 const struct state_ent *st_tbl; 5747 const struct event_ent *ev_tbl; 5748 struct list_head msg_q; 5749 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5750 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5751 }; 5752 5753 enum rtw89_mac_ax_ps_mode { 5754 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5755 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5756 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5757 RTW89_MAC_AX_PS_MODE_MAX = 3, 5758 }; 5759 5760 enum rtw89_last_rpwm_mode { 5761 RTW89_LAST_RPWM_PS = 0x0, 5762 RTW89_LAST_RPWM_ACTIVE = 0x6, 5763 }; 5764 5765 struct rtw89_lps_parm { 5766 u8 macid; 5767 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5768 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5769 }; 5770 5771 struct rtw89_ppdu_sts_info { 5772 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 5773 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 5774 }; 5775 5776 struct rtw89_early_h2c { 5777 struct list_head list; 5778 u8 *h2c; 5779 u16 h2c_len; 5780 }; 5781 5782 struct rtw89_hw_scan_extra_op { 5783 bool set; 5784 u8 macid; 5785 u8 port; 5786 struct rtw89_chan chan; 5787 struct rtw89_vif_link *rtwvif_link; 5788 }; 5789 5790 struct rtw89_hw_scan_info { 5791 struct rtw89_vif_link *scanning_vif; 5792 struct list_head pkt_list[NUM_NL80211_BANDS]; 5793 struct list_head chan_list; 5794 struct rtw89_chan op_chan; 5795 struct rtw89_hw_scan_extra_op extra_op; 5796 bool connected; 5797 bool abort; 5798 u16 delay; /* in unit of ms */ 5799 u8 seq: 2; 5800 }; 5801 5802 enum rtw89_phy_bb_gain_band { 5803 RTW89_BB_GAIN_BAND_2G = 0, 5804 RTW89_BB_GAIN_BAND_5G_L = 1, 5805 RTW89_BB_GAIN_BAND_5G_M = 2, 5806 RTW89_BB_GAIN_BAND_5G_H = 3, 5807 RTW89_BB_GAIN_BAND_6G_L = 4, 5808 RTW89_BB_GAIN_BAND_6G_M = 5, 5809 RTW89_BB_GAIN_BAND_6G_H = 6, 5810 RTW89_BB_GAIN_BAND_6G_UH = 7, 5811 5812 RTW89_BB_GAIN_BAND_NR, 5813 }; 5814 5815 enum rtw89_phy_gain_band_be { 5816 RTW89_BB_GAIN_BAND_2G_BE = 0, 5817 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5818 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5819 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5820 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5821 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5822 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5823 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5824 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5825 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5826 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5827 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5828 5829 RTW89_BB_GAIN_BAND_NR_BE, 5830 }; 5831 5832 enum rtw89_phy_bb_bw_be { 5833 RTW89_BB_BW_20_40 = 0, 5834 RTW89_BB_BW_80_160_320 = 1, 5835 5836 RTW89_BB_BW_NR_BE, 5837 }; 5838 5839 enum rtw89_bw20_sc { 5840 RTW89_BW20_SC_20M = 1, 5841 RTW89_BW20_SC_40M = 2, 5842 RTW89_BW20_SC_80M = 4, 5843 RTW89_BW20_SC_160M = 8, 5844 RTW89_BW20_SC_320M = 16, 5845 }; 5846 5847 enum rtw89_cmac_table_bw { 5848 RTW89_CMAC_BW_20M = 0, 5849 RTW89_CMAC_BW_40M = 1, 5850 RTW89_CMAC_BW_80M = 2, 5851 RTW89_CMAC_BW_160M = 3, 5852 RTW89_CMAC_BW_320M = 4, 5853 5854 RTW89_CMAC_BW_NR, 5855 }; 5856 5857 enum rtw89_phy_bb_rxsc_num { 5858 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5859 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5860 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5861 }; 5862 5863 struct rtw89_phy_bb_gain_info { 5864 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5865 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5866 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5867 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5868 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5869 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5870 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5871 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5872 [RTW89_BB_RXSC_NUM_40]; 5873 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5874 [RTW89_BB_RXSC_NUM_80]; 5875 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5876 [RTW89_BB_RXSC_NUM_160]; 5877 }; 5878 5879 struct rtw89_phy_bb_gain_info_be { 5880 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5881 [LNA_GAIN_NUM]; 5882 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5883 [TIA_GAIN_NUM]; 5884 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5885 [RF_PATH_MAX][LNA_GAIN_NUM]; 5886 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5887 [RF_PATH_MAX][LNA_GAIN_NUM]; 5888 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5889 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5890 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5891 [RTW89_BW20_SC_20M]; 5892 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5893 [RTW89_BW20_SC_40M]; 5894 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5895 [RTW89_BW20_SC_80M]; 5896 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5897 [RTW89_BW20_SC_160M]; 5898 }; 5899 5900 struct rtw89_phy_efuse_gain { 5901 bool offset_valid; 5902 bool comp_valid; 5903 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5904 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5905 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5906 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5907 }; 5908 5909 struct rtw89_phy_calc_efuse_gain { 5910 s8 cck_mean_gain_bias; 5911 s8 cck_rpl_ofst; 5912 s8 rssi_ofst; 5913 }; 5914 5915 #define RTW89_MAX_PATTERN_NUM 18 5916 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5917 #define RTW89_MAX_PATTERN_SIZE 128 5918 5919 struct rtw89_wow_cam_info { 5920 bool r_w; 5921 u8 idx; 5922 __le32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5923 u16 crc; 5924 bool negative_pattern_match; 5925 bool skip_mac_hdr; 5926 bool uc; 5927 bool mc; 5928 bool bc; 5929 bool valid; 5930 }; 5931 5932 struct rtw89_wow_key_info { 5933 u8 ptk_tx_iv[8]; 5934 u8 valid_check; 5935 u8 symbol_check_en; 5936 u8 gtk_keyidx; 5937 u8 rsvd[5]; 5938 u8 ptk_rx_iv[8]; 5939 u8 gtk_rx_iv[4][8]; 5940 } __packed; 5941 5942 struct rtw89_wow_gtk_info { 5943 u8 kck[32]; 5944 u8 kek[32]; 5945 u8 tk1[16]; 5946 u8 rxmickey[8]; 5947 u8 txmickey[8]; 5948 __le32 igtk_keyid; 5949 __le64 ipn; 5950 u8 igtk[2][32]; 5951 u8 psk[32]; 5952 } __packed; 5953 5954 struct rtw89_wow_aoac_report { 5955 u8 rpt_ver; 5956 u8 sec_type; 5957 u8 key_idx; 5958 u8 pattern_idx; 5959 u8 rekey_ok; 5960 u8 ptk_tx_iv[8]; 5961 u8 eapol_key_replay_count[8]; 5962 u8 gtk[32]; 5963 u8 ptk_rx_iv[8]; 5964 u8 gtk_rx_iv[4][8]; 5965 u64 igtk_key_id; 5966 u64 igtk_ipn; 5967 u8 igtk[32]; 5968 u8 csa_pri_ch; 5969 u8 csa_bw; 5970 u8 csa_ch_offset; 5971 u8 csa_chsw_failed; 5972 u8 csa_ch_band; 5973 }; 5974 5975 struct rtw89_wow_param { 5976 struct rtw89_vif_link *rtwvif_link; 5977 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5978 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5979 struct rtw89_wow_key_info key_info; 5980 struct rtw89_wow_gtk_info gtk_info; 5981 struct rtw89_wow_aoac_report aoac_rpt; 5982 u8 pattern_cnt; 5983 u8 ptk_alg; 5984 u8 gtk_alg; 5985 u8 ptk_keyidx; 5986 u8 akm; 5987 5988 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5989 struct rtw89_wait_info wait; 5990 5991 bool pno_inited; 5992 struct list_head pno_pkt_list; 5993 struct cfg80211_sched_scan_request *nd_config; 5994 }; 5995 5996 struct rtw89_mcc_limit { 5997 bool enable; 5998 u16 max_tob; /* TU; max time offset behind */ 5999 u16 max_toa; /* TU; max time offset ahead */ 6000 u16 max_dur; /* TU */ 6001 }; 6002 6003 struct rtw89_mcc_policy { 6004 u8 c2h_rpt; 6005 u8 tx_null_early; 6006 u8 dis_tx_null; 6007 u8 in_curr_ch; 6008 u8 dis_sw_retry; 6009 u8 sw_retry_count; 6010 }; 6011 6012 struct rtw89_mcc_role { 6013 struct rtw89_vif_link *rtwvif_link; 6014 struct rtw89_mcc_policy policy; 6015 struct rtw89_mcc_limit limit; 6016 6017 const struct rtw89_mcc_courtesy_cfg *crtz; 6018 6019 /* only valid when running with FW MRC mechanism */ 6020 u8 slot_idx; 6021 6022 /* byte-array in LE order for FW */ 6023 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 6024 u8 probe_count; 6025 6026 u16 duration; /* TU */ 6027 u16 beacon_interval; /* TU */ 6028 bool is_2ghz; 6029 bool is_go; 6030 bool is_gc; 6031 bool ignore_bcn; 6032 }; 6033 6034 struct rtw89_mcc_bt_role { 6035 u16 duration; /* TU */ 6036 }; 6037 6038 struct rtw89_mcc_courtesy_cfg { 6039 u8 slot_num; 6040 u8 macid_tgt; 6041 }; 6042 6043 struct rtw89_mcc_courtesy { 6044 struct rtw89_mcc_courtesy_cfg ref; 6045 struct rtw89_mcc_courtesy_cfg aux; 6046 }; 6047 6048 enum rtw89_mcc_plan { 6049 RTW89_MCC_PLAN_TAIL_BT, 6050 RTW89_MCC_PLAN_MID_BT, 6051 RTW89_MCC_PLAN_NO_BT, 6052 6053 NUM_OF_RTW89_MCC_PLAN, 6054 }; 6055 6056 struct rtw89_mcc_pattern { 6057 s16 tob_ref; /* TU; time offset behind of reference role */ 6058 s16 toa_ref; /* TU; time offset ahead of reference role */ 6059 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 6060 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 6061 6062 enum rtw89_mcc_plan plan; 6063 struct rtw89_mcc_courtesy courtesy; 6064 }; 6065 6066 struct rtw89_mcc_sync { 6067 bool enable; 6068 u16 offset; /* TU */ 6069 u8 macid_src; 6070 u8 band_src; 6071 u8 port_src; 6072 u8 macid_tgt; 6073 u8 band_tgt; 6074 u8 port_tgt; 6075 }; 6076 6077 struct rtw89_mcc_config { 6078 struct rtw89_mcc_pattern pattern; 6079 struct rtw89_mcc_sync sync; 6080 u64 start_tsf; 6081 u64 start_tsf_in_aux_domain; 6082 u64 prepare_delay; 6083 u16 mcc_interval; /* TU */ 6084 u16 beacon_offset; /* TU */ 6085 }; 6086 6087 enum rtw89_mcc_mode { 6088 RTW89_MCC_MODE_GO_STA, 6089 RTW89_MCC_MODE_GC_STA, 6090 }; 6091 6092 struct rtw89_mcc_info { 6093 struct rtw89_wait_info wait; 6094 6095 u8 group; 6096 enum rtw89_mcc_mode mode; 6097 struct rtw89_mcc_role role_ref; /* reference role */ 6098 struct rtw89_mcc_role role_aux; /* auxiliary role */ 6099 struct rtw89_mcc_bt_role bt_role; 6100 struct rtw89_mcc_config config; 6101 }; 6102 6103 enum rtw89_mlo_mode { 6104 RTW89_MLO_MODE_MLSR = 0, 6105 RTW89_MLO_MODE_EMLSR = 1, 6106 6107 NUM_OF_RTW89_MLO_MODE, 6108 }; 6109 6110 struct rtw89_mlo_info { 6111 struct rtw89_wait_info wait; 6112 }; 6113 6114 struct rtw89_beacon_track_info { 6115 bool is_data_ready; 6116 u32 tbtt_offset; /* in unit of microsecond */ 6117 u16 bcn_timeout; /* in unit of millisecond */ 6118 6119 /* The following are constant and set at association. */ 6120 u8 dtim; 6121 u16 beacon_int; 6122 u16 low_bcn_th; 6123 u16 med_bcn_th; 6124 u16 high_bcn_th; 6125 u16 target_bcn_th; 6126 u16 outlier_low_bcn_th; 6127 u16 outlier_high_bcn_th; 6128 u32 close_bcn_intvl_th; 6129 u32 tbtt_diff_th; 6130 }; 6131 6132 struct rtw89_dev { 6133 struct ieee80211_hw *hw; 6134 struct device *dev; 6135 const struct ieee80211_ops *ops; 6136 6137 bool dbcc_en; 6138 bool support_mlo; 6139 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 6140 struct rtw89_hw_scan_info scan_info; 6141 const struct rtw89_chip_info *chip; 6142 const struct rtw89_chip_variant *variant; 6143 const struct rtw89_pci_info *pci_info; 6144 const struct rtw89_rfe_parms *rfe_parms; 6145 struct rtw89_hal hal; 6146 struct rtw89_beacon_track_info bcn_track; 6147 struct rtw89_mcc_info mcc; 6148 struct rtw89_mlo_info mlo; 6149 struct rtw89_mac_info mac; 6150 struct rtw89_fw_info fw; 6151 struct rtw89_hci_info hci; 6152 struct rtw89_efuse efuse; 6153 struct rtw89_traffic_stats stats; 6154 struct rtw89_rfe_data *rfe_data; 6155 enum rtw89_custid custid; 6156 6157 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 6158 refcount_t refcount_ap_info; 6159 6160 struct list_head rtwvifs_list; 6161 /* used to protect rf read write */ 6162 struct mutex rf_mutex; 6163 struct workqueue_struct *txq_wq; 6164 struct work_struct txq_work; 6165 struct delayed_work txq_reinvoke_work; 6166 /* used to protect ba_list and forbid_ba_list */ 6167 spinlock_t ba_lock; 6168 /* txqs to setup ba session */ 6169 struct list_head ba_list; 6170 /* txqs to forbid ba session */ 6171 struct list_head forbid_ba_list; 6172 struct work_struct ba_work; 6173 /* used to protect rpwm */ 6174 spinlock_t rpwm_lock; 6175 6176 struct list_head tx_waits; 6177 struct wiphy_delayed_work tx_wait_work; 6178 6179 struct rtw89_tx_rpt tx_rpt; 6180 6181 struct rtw89_cam_info cam_info; 6182 6183 struct sk_buff_head c2h_queue; 6184 struct wiphy_work c2h_work; 6185 struct wiphy_work ips_work; 6186 struct wiphy_work cancel_6ghz_probe_work; 6187 struct work_struct load_firmware_work; 6188 6189 struct list_head early_h2c_list; 6190 6191 struct rtw89_ser ser; 6192 6193 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 6194 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 6195 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 6196 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 6197 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 6198 6199 struct rtw89_phy_stat phystat; 6200 struct rtw89_rfk_wait_info rfk_wait; 6201 struct rtw89_dack_info dack; 6202 struct rtw89_iqk_info iqk; 6203 struct rtw89_dpk_info dpk; 6204 struct rtw89_rfk_mcc_info rfk_mcc; 6205 struct rtw89_lck_info lck; 6206 struct rtw89_rx_dck_info rx_dck; 6207 bool is_tssi_mode[RF_PATH_MAX]; 6208 bool is_bt_iqk_timeout; 6209 6210 struct rtw89_fem_info fem; 6211 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 6212 struct rtw89_tssi_info tssi; 6213 struct rtw89_power_trim_info pwr_trim; 6214 6215 struct rtw89_cfo_tracking_info cfo_tracking; 6216 union { 6217 struct rtw89_phy_bb_gain_info ax; 6218 struct rtw89_phy_bb_gain_info_be be; 6219 } bb_gain; 6220 struct rtw89_phy_efuse_gain efuse_gain; 6221 struct rtw89_phy_ul_tb_info ul_tb_info; 6222 struct rtw89_antdiv_info antdiv; 6223 6224 struct rtw89_bb_ctx { 6225 enum rtw89_phy_idx phy_idx; 6226 struct rtw89_env_monitor_info env_monitor; 6227 struct rtw89_dig_info dig; 6228 struct rtw89_phy_ch_info ch_info; 6229 struct rtw89_edcca_bak edcca_bak; 6230 } bbs[RTW89_PHY_NUM]; 6231 6232 struct wiphy_delayed_work track_work; 6233 struct wiphy_delayed_work track_ps_work; 6234 struct wiphy_delayed_work chanctx_work; 6235 struct wiphy_delayed_work coex_act1_work; 6236 struct wiphy_delayed_work coex_bt_devinfo_work; 6237 struct wiphy_delayed_work coex_rfk_chk_work; 6238 struct wiphy_delayed_work cfo_track_work; 6239 struct wiphy_delayed_work mcc_prepare_done_work; 6240 struct delayed_work forbid_ba_work; 6241 struct wiphy_delayed_work antdiv_work; 6242 struct rtw89_ppdu_sts_info ppdu_sts; 6243 u8 total_sta_assoc; 6244 bool scanning; 6245 6246 struct rtw89_regulatory_info regulatory; 6247 struct rtw89_sar_info sar; 6248 struct rtw89_tas_info tas; 6249 struct rtw89_ant_gain_info ant_gain; 6250 6251 struct rtw89_btc btc; 6252 enum rtw89_ps_mode ps_mode; 6253 bool lps_enabled; 6254 u8 ps_hang_cnt; 6255 6256 struct rtw89_wow_param wow; 6257 6258 /* napi structure */ 6259 struct net_device *netdev; 6260 struct napi_struct napi; 6261 int napi_budget_countdown; 6262 6263 struct rtw89_debugfs *debugfs; 6264 struct rtw89_vif *pure_monitor_mode_vif; 6265 6266 /* HCI related data, keep last */ 6267 u8 priv[] __aligned(sizeof(void *)); 6268 }; 6269 6270 struct rtw89_link_conf_container { 6271 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 6272 }; 6273 6274 struct rtw89_vif_ml_trans { 6275 u16 mediate_links; 6276 u16 links_to_del; 6277 u16 links_to_add; 6278 }; 6279 6280 #define RTW89_VIF_IDLE_LINK_ID 0 6281 6282 struct rtw89_vif { 6283 struct rtw89_dev *rtwdev; 6284 struct list_head list; 6285 struct list_head mgnt_entry; 6286 struct rtw89_link_conf_container __rcu *snap_link_confs; 6287 6288 u8 mac_addr[ETH_ALEN]; 6289 __be32 ip_addr; 6290 6291 struct rtw89_traffic_stats stats; 6292 struct rtw89_traffic_stats stats_ps; 6293 u32 tdls_peer; 6294 6295 struct ieee80211_scan_ies *scan_ies; 6296 struct cfg80211_scan_request *scan_req; 6297 6298 struct rtw89_roc roc; 6299 bool offchan; 6300 6301 enum rtw89_mlo_mode mlo_mode; 6302 struct rtw89_vif_ml_trans ml_trans; 6303 6304 struct list_head dlink_pool; 6305 u8 links_inst_valid_num; 6306 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6307 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6308 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 6309 }; 6310 6311 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 6312 const struct rtw89_vif *rtwvif, 6313 unsigned int link_id) 6314 { 6315 *rtwvif_link = rtwvif->links[link_id]; 6316 return !!*rtwvif_link; 6317 } 6318 6319 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 6320 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6321 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 6322 6323 enum rtw89_sta_flags { 6324 RTW89_REMOTE_STA_IN_PS, 6325 6326 NUM_OF_RTW89_STA_FLAGS, 6327 }; 6328 6329 struct rtw89_sta { 6330 struct rtw89_dev *rtwdev; 6331 struct rtw89_vif *rtwvif; 6332 6333 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 6334 6335 bool disassoc; 6336 6337 struct sk_buff_head roc_queue; 6338 6339 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 6340 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 6341 6342 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 6343 6344 struct list_head dlink_pool; 6345 u8 links_inst_valid_num; 6346 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 6347 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 6348 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 6349 }; 6350 6351 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 6352 const struct rtw89_sta *rtwsta, 6353 unsigned int link_id) 6354 { 6355 *rtwsta_link = rtwsta->links[link_id]; 6356 return !!*rtwsta_link; 6357 } 6358 6359 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 6360 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 6361 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 6362 6363 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 6364 { 6365 /* const after init, so no need to check if active first */ 6366 return rtwvif->links_inst[0].mac_id; 6367 } 6368 6369 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 6370 { 6371 /* const after init, so no need to check if active first */ 6372 return rtwvif->links_inst[0].port; 6373 } 6374 6375 static inline struct rtw89_vif_link * 6376 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 6377 { 6378 if (index >= rtwvif->links_inst_valid_num || 6379 !test_bit(index, rtwvif->links_inst_map)) 6380 return NULL; 6381 return &rtwvif->links_inst[index]; 6382 } 6383 6384 static inline 6385 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 6386 { 6387 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6388 6389 return rtwvif_link - rtwvif->links_inst; 6390 } 6391 6392 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 6393 { 6394 /* const after init, so no need to check if active first */ 6395 return rtwsta->links_inst[0].mac_id; 6396 } 6397 6398 static inline struct rtw89_sta_link * 6399 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 6400 { 6401 if (index >= rtwsta->links_inst_valid_num || 6402 !test_bit(index, rtwsta->links_inst_map)) 6403 return NULL; 6404 return &rtwsta->links_inst[index]; 6405 } 6406 6407 static inline 6408 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 6409 { 6410 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6411 6412 return rtwsta_link - rtwsta->links_inst; 6413 } 6414 6415 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 6416 { 6417 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6418 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6419 6420 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6421 rtwsta_link); 6422 } 6423 6424 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 6425 { 6426 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 6427 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 6428 6429 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 6430 NULL); 6431 synchronize_rcu(); 6432 } 6433 6434 static inline struct rtw89_sta_link * 6435 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 6436 { 6437 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 6438 } 6439 6440 #define rtw89_get_designated_link(links_holder) \ 6441 ({ \ 6442 typeof(links_holder) p = links_holder; \ 6443 list_first_entry_or_null(&p->dlink_pool, typeof(*p->links_inst), dlink_schd); \ 6444 }) 6445 6446 static inline void rtw89_tx_wait_release(struct rtw89_tx_wait_info *wait) 6447 { 6448 dev_kfree_skb_any(wait->skb); 6449 kfree_rcu(wait, rcu_head); 6450 } 6451 6452 static inline void rtw89_tx_wait_list_clear(struct rtw89_dev *rtwdev) 6453 { 6454 struct rtw89_tx_wait_info *wait, *tmp; 6455 6456 lockdep_assert_wiphy(rtwdev->hw->wiphy); 6457 6458 list_for_each_entry_safe(wait, tmp, &rtwdev->tx_waits, list) { 6459 if (!completion_done(&wait->completion)) 6460 continue; 6461 list_del(&wait->list); 6462 rtw89_tx_wait_release(wait); 6463 } 6464 } 6465 6466 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 6467 struct rtw89_core_tx_request *tx_req) 6468 { 6469 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 6470 } 6471 6472 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 6473 { 6474 rtwdev->hci.ops->reset(rtwdev); 6475 /* hci.ops->reset must complete all pending TX wait SKBs */ 6476 rtw89_tx_wait_list_clear(rtwdev); 6477 } 6478 6479 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 6480 { 6481 return rtwdev->hci.ops->start(rtwdev); 6482 } 6483 6484 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 6485 { 6486 rtwdev->hci.ops->stop(rtwdev); 6487 } 6488 6489 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 6490 { 6491 return rtwdev->hci.ops->deinit(rtwdev); 6492 } 6493 6494 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 6495 { 6496 rtwdev->hci.ops->pause(rtwdev, pause); 6497 } 6498 6499 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 6500 { 6501 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 6502 } 6503 6504 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 6505 { 6506 rtwdev->hci.ops->recalc_int_mit(rtwdev); 6507 } 6508 6509 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 6510 { 6511 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 6512 } 6513 6514 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 6515 { 6516 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 6517 } 6518 6519 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 6520 { 6521 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 6522 } 6523 6524 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 6525 bool drop) 6526 { 6527 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 6528 return; 6529 6530 if (rtwdev->hci.ops->flush_queues) 6531 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 6532 } 6533 6534 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 6535 { 6536 if (rtwdev->hci.ops->recovery_start) 6537 rtwdev->hci.ops->recovery_start(rtwdev); 6538 } 6539 6540 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 6541 { 6542 if (rtwdev->hci.ops->recovery_complete) 6543 rtwdev->hci.ops->recovery_complete(rtwdev); 6544 } 6545 6546 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 6547 { 6548 if (rtwdev->hci.ops->enable_intr) 6549 rtwdev->hci.ops->enable_intr(rtwdev); 6550 } 6551 6552 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 6553 { 6554 if (rtwdev->hci.ops->disable_intr) 6555 rtwdev->hci.ops->disable_intr(rtwdev); 6556 } 6557 6558 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 6559 { 6560 if (rtwdev->hci.ops->ctrl_txdma_ch) 6561 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 6562 } 6563 6564 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6565 { 6566 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6567 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6568 } 6569 6570 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6571 { 6572 if (rtwdev->hci.ops->ctrl_trxhci) 6573 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6574 } 6575 6576 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6577 { 6578 int ret = 0; 6579 6580 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6581 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6582 return ret; 6583 } 6584 6585 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6586 { 6587 if (rtwdev->hci.ops->clr_idx_all) 6588 rtwdev->hci.ops->clr_idx_all(rtwdev); 6589 } 6590 6591 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6592 { 6593 int ret = 0; 6594 6595 if (rtwdev->hci.ops->rst_bdram) 6596 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6597 return ret; 6598 } 6599 6600 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6601 { 6602 if (rtwdev->hci.ops->clear) 6603 rtwdev->hci.ops->clear(rtwdev, pdev); 6604 } 6605 6606 static inline 6607 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6608 { 6609 /* 6610 * This should be used by/after rtw89_hci_tx_write() and before doing 6611 * ieee80211_tx_info_clear_status(). 6612 */ 6613 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6614 6615 return (struct rtw89_tx_skb_data *)info->driver_data; 6616 } 6617 6618 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6619 { 6620 return rtwdev->hci.ops->read8(rtwdev, addr); 6621 } 6622 6623 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6624 { 6625 return rtwdev->hci.ops->read16(rtwdev, addr); 6626 } 6627 6628 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6629 { 6630 return rtwdev->hci.ops->read32(rtwdev, addr); 6631 } 6632 6633 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6634 { 6635 rtwdev->hci.ops->write8(rtwdev, addr, data); 6636 } 6637 6638 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6639 { 6640 rtwdev->hci.ops->write16(rtwdev, addr, data); 6641 } 6642 6643 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6644 { 6645 rtwdev->hci.ops->write32(rtwdev, addr, data); 6646 } 6647 6648 static inline void 6649 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6650 { 6651 u8 val; 6652 6653 val = rtw89_read8(rtwdev, addr); 6654 rtw89_write8(rtwdev, addr, val | bit); 6655 } 6656 6657 static inline void 6658 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6659 { 6660 u16 val; 6661 6662 val = rtw89_read16(rtwdev, addr); 6663 rtw89_write16(rtwdev, addr, val | bit); 6664 } 6665 6666 static inline void 6667 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6668 { 6669 u32 val; 6670 6671 val = rtw89_read32(rtwdev, addr); 6672 rtw89_write32(rtwdev, addr, val | bit); 6673 } 6674 6675 static inline void 6676 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6677 { 6678 u8 val; 6679 6680 val = rtw89_read8(rtwdev, addr); 6681 rtw89_write8(rtwdev, addr, val & ~bit); 6682 } 6683 6684 static inline void 6685 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6686 { 6687 u16 val; 6688 6689 val = rtw89_read16(rtwdev, addr); 6690 rtw89_write16(rtwdev, addr, val & ~bit); 6691 } 6692 6693 static inline void 6694 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6695 { 6696 u32 val; 6697 6698 val = rtw89_read32(rtwdev, addr); 6699 rtw89_write32(rtwdev, addr, val & ~bit); 6700 } 6701 6702 static inline u32 6703 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6704 { 6705 u32 shift = __ffs(mask); 6706 u32 orig; 6707 u32 ret; 6708 6709 orig = rtw89_read32(rtwdev, addr); 6710 ret = (orig & mask) >> shift; 6711 6712 return ret; 6713 } 6714 6715 static inline u16 6716 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6717 { 6718 u32 shift = __ffs(mask); 6719 u32 orig; 6720 u32 ret; 6721 6722 orig = rtw89_read16(rtwdev, addr); 6723 ret = (orig & mask) >> shift; 6724 6725 return ret; 6726 } 6727 6728 static inline u8 6729 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6730 { 6731 u32 shift = __ffs(mask); 6732 u32 orig; 6733 u32 ret; 6734 6735 orig = rtw89_read8(rtwdev, addr); 6736 ret = (orig & mask) >> shift; 6737 6738 return ret; 6739 } 6740 6741 static inline void 6742 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6743 { 6744 u32 shift = __ffs(mask); 6745 u32 orig; 6746 u32 set; 6747 6748 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6749 6750 orig = rtw89_read32(rtwdev, addr); 6751 set = (orig & ~mask) | ((data << shift) & mask); 6752 rtw89_write32(rtwdev, addr, set); 6753 } 6754 6755 static inline void 6756 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6757 { 6758 u32 shift; 6759 u16 orig, set; 6760 6761 mask &= 0xffff; 6762 shift = __ffs(mask); 6763 6764 orig = rtw89_read16(rtwdev, addr); 6765 set = (orig & ~mask) | ((data << shift) & mask); 6766 rtw89_write16(rtwdev, addr, set); 6767 } 6768 6769 static inline void 6770 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6771 { 6772 u32 shift; 6773 u8 orig, set; 6774 6775 mask &= 0xff; 6776 shift = __ffs(mask); 6777 6778 orig = rtw89_read8(rtwdev, addr); 6779 set = (orig & ~mask) | ((data << shift) & mask); 6780 rtw89_write8(rtwdev, addr, set); 6781 } 6782 6783 static inline u32 6784 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6785 u32 addr, u32 mask) 6786 { 6787 u32 val; 6788 6789 mutex_lock(&rtwdev->rf_mutex); 6790 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6791 mutex_unlock(&rtwdev->rf_mutex); 6792 6793 return val; 6794 } 6795 6796 static inline void 6797 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6798 u32 addr, u32 mask, u32 data) 6799 { 6800 mutex_lock(&rtwdev->rf_mutex); 6801 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6802 mutex_unlock(&rtwdev->rf_mutex); 6803 } 6804 6805 static inline u32 rtw89_read32_pci_cfg(struct rtw89_dev *rtwdev, u32 addr) 6806 { 6807 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE || 6808 !rtwdev->hci.ops->read32_pci_cfg) 6809 return RTW89_R32_EA; 6810 6811 return rtwdev->hci.ops->read32_pci_cfg(rtwdev, addr); 6812 } 6813 6814 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6815 { 6816 void *p = rtwtxq; 6817 6818 return container_of(p, struct ieee80211_txq, drv_priv); 6819 } 6820 6821 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6822 struct ieee80211_txq *txq) 6823 { 6824 struct rtw89_txq *rtwtxq; 6825 6826 if (!txq) 6827 return; 6828 6829 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6830 INIT_LIST_HEAD(&rtwtxq->list); 6831 } 6832 6833 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6834 { 6835 void *p = rtwvif; 6836 6837 return container_of(p, struct ieee80211_vif, drv_priv); 6838 } 6839 6840 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6841 { 6842 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6843 } 6844 6845 static inline 6846 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6847 { 6848 return rtwvif_to_vif(rtwvif_link->rtwvif); 6849 } 6850 6851 static inline 6852 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6853 { 6854 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6855 } 6856 6857 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6858 { 6859 return (struct rtw89_vif *)vif->drv_priv; 6860 } 6861 6862 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6863 { 6864 return vif ? vif_to_rtwvif(vif) : NULL; 6865 } 6866 6867 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6868 { 6869 void *p = rtwsta; 6870 6871 return container_of(p, struct ieee80211_sta, drv_priv); 6872 } 6873 6874 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6875 { 6876 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6877 } 6878 6879 static inline 6880 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6881 { 6882 return rtwsta_to_sta(rtwsta_link->rtwsta); 6883 } 6884 6885 static inline 6886 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6887 { 6888 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6889 } 6890 6891 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6892 { 6893 return (struct rtw89_sta *)sta->drv_priv; 6894 } 6895 6896 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6897 { 6898 return sta ? sta_to_rtwsta(sta) : NULL; 6899 } 6900 6901 static inline struct ieee80211_bss_conf * 6902 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6903 { 6904 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6905 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6906 struct rtw89_link_conf_container *snap; 6907 struct ieee80211_bss_conf *bss_conf; 6908 6909 snap = rcu_dereference(rtwvif->snap_link_confs); 6910 if (snap) { 6911 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6912 goto out; 6913 } 6914 6915 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6916 6917 out: 6918 if (unlikely(!bss_conf)) { 6919 *nolink = true; 6920 return &vif->bss_conf; 6921 } 6922 6923 *nolink = false; 6924 return bss_conf; 6925 } 6926 6927 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6928 ({ \ 6929 typeof(rtwvif_link) p = rtwvif_link; \ 6930 struct ieee80211_bss_conf *bss_conf; \ 6931 bool nolink; \ 6932 \ 6933 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6934 if (unlikely(nolink) && (assert)) \ 6935 rtw89_err(p->rtwvif->rtwdev, \ 6936 "%s: cannot find exact bss_conf for link_id %u\n",\ 6937 __func__, p->link_id); \ 6938 bss_conf; \ 6939 }) 6940 6941 static inline struct ieee80211_link_sta * 6942 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6943 { 6944 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6945 struct ieee80211_link_sta *link_sta; 6946 6947 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6948 if (unlikely(!link_sta)) { 6949 *nolink = true; 6950 return &sta->deflink; 6951 } 6952 6953 *nolink = false; 6954 return link_sta; 6955 } 6956 6957 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6958 ({ \ 6959 typeof(rtwsta_link) p = rtwsta_link; \ 6960 struct ieee80211_link_sta *link_sta; \ 6961 bool nolink; \ 6962 \ 6963 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6964 if (unlikely(nolink) && (assert)) \ 6965 rtw89_err(p->rtwsta->rtwdev, \ 6966 "%s: cannot find exact link_sta for link_id %u\n",\ 6967 __func__, p->link_id); \ 6968 link_sta; \ 6969 }) 6970 6971 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6972 { 6973 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6974 return RATE_INFO_BW_160; 6975 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6976 return RATE_INFO_BW_80; 6977 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6978 return RATE_INFO_BW_40; 6979 else 6980 return RATE_INFO_BW_20; 6981 } 6982 6983 static inline 6984 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6985 { 6986 switch (hw_band) { 6987 default: 6988 case RTW89_BAND_2G: 6989 return NL80211_BAND_2GHZ; 6990 case RTW89_BAND_5G: 6991 return NL80211_BAND_5GHZ; 6992 case RTW89_BAND_6G: 6993 return NL80211_BAND_6GHZ; 6994 } 6995 } 6996 6997 static inline 6998 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6999 { 7000 switch (nl_band) { 7001 default: 7002 case NL80211_BAND_2GHZ: 7003 return RTW89_BAND_2G; 7004 case NL80211_BAND_5GHZ: 7005 return RTW89_BAND_5G; 7006 case NL80211_BAND_6GHZ: 7007 return RTW89_BAND_6G; 7008 } 7009 } 7010 7011 static inline 7012 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 7013 { 7014 switch (width) { 7015 default: 7016 WARN(1, "Not support bandwidth %d\n", width); 7017 fallthrough; 7018 case NL80211_CHAN_WIDTH_20_NOHT: 7019 case NL80211_CHAN_WIDTH_20: 7020 return RTW89_CHANNEL_WIDTH_20; 7021 case NL80211_CHAN_WIDTH_40: 7022 return RTW89_CHANNEL_WIDTH_40; 7023 case NL80211_CHAN_WIDTH_80: 7024 return RTW89_CHANNEL_WIDTH_80; 7025 case NL80211_CHAN_WIDTH_160: 7026 return RTW89_CHANNEL_WIDTH_160; 7027 } 7028 } 7029 7030 static inline 7031 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 7032 { 7033 switch (rua) { 7034 default: 7035 WARN(1, "Invalid RU allocation: %d\n", rua); 7036 fallthrough; 7037 case 0 ... 36: 7038 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 7039 case 37 ... 52: 7040 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 7041 case 53 ... 60: 7042 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 7043 case 61 ... 64: 7044 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 7045 case 65 ... 66: 7046 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 7047 case 67: 7048 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 7049 case 68: 7050 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 7051 } 7052 } 7053 7054 static inline 7055 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 7056 struct rtw89_sta_link *rtwsta_link) 7057 { 7058 if (rtwsta_link) { 7059 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 7060 7061 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 7062 return &rtwsta_link->addr_cam; 7063 } 7064 return &rtwvif_link->addr_cam; 7065 } 7066 7067 static inline 7068 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 7069 struct rtw89_sta_link *rtwsta_link) 7070 { 7071 if (rtwsta_link) { 7072 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 7073 7074 if (sta->tdls) 7075 return &rtwsta_link->bssid_cam; 7076 } 7077 return &rtwvif_link->bssid_cam; 7078 } 7079 7080 static inline 7081 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 7082 struct rtw89_channel_help_params *p, 7083 const struct rtw89_chan *chan, 7084 enum rtw89_mac_idx mac_idx, 7085 enum rtw89_phy_idx phy_idx) 7086 { 7087 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 7088 mac_idx, phy_idx); 7089 } 7090 7091 static inline 7092 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 7093 struct rtw89_channel_help_params *p, 7094 const struct rtw89_chan *chan, 7095 enum rtw89_mac_idx mac_idx, 7096 enum rtw89_phy_idx phy_idx) 7097 { 7098 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 7099 mac_idx, phy_idx); 7100 } 7101 7102 static inline 7103 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 7104 enum rtw89_chanctx_idx idx) 7105 { 7106 struct rtw89_hal *hal = &rtwdev->hal; 7107 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 7108 7109 if (roc_idx == idx) 7110 return &hal->roc_chandef; 7111 7112 return &hal->chanctx[idx].chandef; 7113 } 7114 7115 static inline 7116 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 7117 enum rtw89_chanctx_idx idx) 7118 { 7119 struct rtw89_hal *hal = &rtwdev->hal; 7120 7121 return &hal->chanctx[idx].chan; 7122 } 7123 7124 static inline 7125 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 7126 enum rtw89_chanctx_idx idx) 7127 { 7128 struct rtw89_hal *hal = &rtwdev->hal; 7129 7130 return &hal->chanctx[idx].rcd; 7131 } 7132 7133 static inline 7134 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 7135 { 7136 const struct rtw89_chanctx *chanctx = 7137 container_of_const(chan, struct rtw89_chanctx, chan); 7138 7139 return &chanctx->rcd; 7140 } 7141 7142 static inline 7143 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 7144 { 7145 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 7146 7147 if (rtwvif_link) 7148 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 7149 else 7150 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 7151 } 7152 7153 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 7154 { 7155 const struct rtw89_chip_info *chip = rtwdev->chip; 7156 7157 if (chip->ops->fem_setup) 7158 chip->ops->fem_setup(rtwdev); 7159 } 7160 7161 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 7162 { 7163 const struct rtw89_chip_info *chip = rtwdev->chip; 7164 7165 if (chip->ops->rfe_gpio) 7166 chip->ops->rfe_gpio(rtwdev); 7167 } 7168 7169 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 7170 { 7171 const struct rtw89_chip_info *chip = rtwdev->chip; 7172 7173 if (chip->ops->rfk_hw_init) 7174 chip->ops->rfk_hw_init(rtwdev); 7175 } 7176 7177 static inline 7178 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev) 7179 { 7180 const struct rtw89_chip_info *chip = rtwdev->chip; 7181 7182 if (!chip->ops->bb_preinit) 7183 return; 7184 7185 chip->ops->bb_preinit(rtwdev, RTW89_PHY_0); 7186 7187 if (rtwdev->dbcc_en) 7188 chip->ops->bb_preinit(rtwdev, RTW89_PHY_1); 7189 } 7190 7191 static inline 7192 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 7193 { 7194 const struct rtw89_chip_info *chip = rtwdev->chip; 7195 7196 if (!chip->ops->bb_postinit) 7197 return; 7198 7199 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 7200 7201 if (rtwdev->dbcc_en) 7202 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 7203 } 7204 7205 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 7206 { 7207 const struct rtw89_chip_info *chip = rtwdev->chip; 7208 7209 if (chip->ops->bb_sethw) 7210 chip->ops->bb_sethw(rtwdev); 7211 } 7212 7213 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 7214 { 7215 const struct rtw89_chip_info *chip = rtwdev->chip; 7216 7217 if (chip->ops->rfk_init) 7218 chip->ops->rfk_init(rtwdev); 7219 } 7220 7221 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 7222 { 7223 const struct rtw89_chip_info *chip = rtwdev->chip; 7224 7225 if (chip->ops->rfk_init_late) 7226 chip->ops->rfk_init_late(rtwdev); 7227 } 7228 7229 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 7230 enum rtw89_phy_idx phy_idx, 7231 const struct rtw89_chan *chan) 7232 { 7233 const struct rtw89_chip_info *chip = rtwdev->chip; 7234 7235 if (chip->ops->rfk_band_changed) 7236 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 7237 } 7238 7239 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 7240 struct rtw89_vif_link *rtwvif_link, bool start) 7241 { 7242 const struct rtw89_chip_info *chip = rtwdev->chip; 7243 7244 if (chip->ops->rfk_scan) 7245 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 7246 } 7247 7248 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 7249 { 7250 const struct rtw89_chip_info *chip = rtwdev->chip; 7251 7252 if (chip->ops->rfk_track) 7253 chip->ops->rfk_track(rtwdev); 7254 } 7255 7256 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 7257 { 7258 const struct rtw89_chip_info *chip = rtwdev->chip; 7259 7260 if (!chip->ops->set_txpwr_ctrl) 7261 return; 7262 7263 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 7264 if (rtwdev->dbcc_en) 7265 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 7266 } 7267 7268 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 7269 { 7270 const struct rtw89_chip_info *chip = rtwdev->chip; 7271 7272 if (chip->ops->power_trim) 7273 chip->ops->power_trim(rtwdev); 7274 } 7275 7276 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 7277 enum rtw89_phy_idx phy_idx) 7278 { 7279 const struct rtw89_chip_info *chip = rtwdev->chip; 7280 7281 if (chip->ops->init_txpwr_unit) 7282 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 7283 } 7284 7285 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 7286 { 7287 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 7288 if (rtwdev->dbcc_en) 7289 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 7290 } 7291 7292 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 7293 enum rtw89_rf_path rf_path) 7294 { 7295 const struct rtw89_chip_info *chip = rtwdev->chip; 7296 7297 if (!chip->ops->get_thermal) 7298 return 0x10; 7299 7300 return chip->ops->get_thermal(rtwdev, rf_path); 7301 } 7302 7303 static inline u32 rtw89_chip_chan_to_rf18_val(struct rtw89_dev *rtwdev, 7304 const struct rtw89_chan *chan) 7305 { 7306 const struct rtw89_chip_info *chip = rtwdev->chip; 7307 7308 if (!chip->ops->chan_to_rf18_val) 7309 return 0; 7310 7311 return chip->ops->chan_to_rf18_val(rtwdev, chan); 7312 } 7313 7314 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 7315 struct rtw89_rx_phy_ppdu *phy_ppdu, 7316 struct ieee80211_rx_status *status) 7317 { 7318 const struct rtw89_chip_info *chip = rtwdev->chip; 7319 7320 if (chip->ops->query_ppdu) 7321 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 7322 } 7323 7324 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 7325 struct rtw89_rx_phy_ppdu *phy_ppdu) 7326 { 7327 const struct rtw89_chip_info *chip = rtwdev->chip; 7328 7329 if (chip->ops->convert_rpl_to_rssi) 7330 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 7331 } 7332 7333 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 7334 struct rtw89_rx_desc_info *desc_info, 7335 struct ieee80211_rx_status *rx_status) 7336 { 7337 const struct rtw89_chip_info *chip = rtwdev->chip; 7338 7339 if (chip->ops->phy_rpt_to_rssi) 7340 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 7341 } 7342 7343 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 7344 enum rtw89_phy_idx phy_idx) 7345 { 7346 const struct rtw89_chip_info *chip = rtwdev->chip; 7347 7348 if (chip->ops->ctrl_nbtg_bt_tx) 7349 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 7350 } 7351 7352 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 7353 { 7354 const struct rtw89_chip_info *chip = rtwdev->chip; 7355 7356 if (chip->ops->cfg_txrx_path) 7357 chip->ops->cfg_txrx_path(rtwdev); 7358 } 7359 7360 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 7361 enum rtw89_phy_idx phy_idx) 7362 { 7363 const struct rtw89_chip_info *chip = rtwdev->chip; 7364 7365 if (chip->ops->digital_pwr_comp) 7366 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 7367 } 7368 7369 static inline 7370 void rtw89_chip_calc_rx_gain_normal(struct rtw89_dev *rtwdev, 7371 const struct rtw89_chan *chan, 7372 enum rtw89_rf_path path, 7373 enum rtw89_phy_idx phy_idx, 7374 struct rtw89_phy_calc_efuse_gain *calc) 7375 { 7376 const struct rtw89_chip_info *chip = rtwdev->chip; 7377 7378 if (chip->ops->calc_rx_gain_normal) 7379 chip->ops->calc_rx_gain_normal(rtwdev, chan, path, phy_idx, calc); 7380 } 7381 7382 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 7383 const struct rtw89_txpwr_table *tbl) 7384 { 7385 tbl->load(rtwdev, tbl); 7386 } 7387 7388 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 7389 { 7390 const struct rtw89_regulatory_info *regulatory = &rtwdev->regulatory; 7391 const struct rtw89_regd *regd = regulatory->regd; 7392 u8 txpwr_regd = regd->txpwr_regd[band]; 7393 7394 if (regulatory->txpwr_uk_follow_etsi && txpwr_regd == RTW89_UK) 7395 return RTW89_ETSI; 7396 7397 return txpwr_regd; 7398 } 7399 7400 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 7401 enum rtw89_phy_idx phy_idx) 7402 { 7403 const struct rtw89_chip_info *chip = rtwdev->chip; 7404 7405 if (chip->ops->ctrl_btg_bt_rx) 7406 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 7407 } 7408 7409 static inline 7410 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 7411 struct rtw89_rx_desc_info *desc_info, 7412 u8 *data, u32 data_offset) 7413 { 7414 const struct rtw89_chip_info *chip = rtwdev->chip; 7415 7416 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 7417 } 7418 7419 static inline 7420 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 7421 struct rtw89_tx_desc_info *desc_info, 7422 void *txdesc) 7423 { 7424 const struct rtw89_chip_info *chip = rtwdev->chip; 7425 7426 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 7427 } 7428 7429 static inline 7430 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 7431 struct rtw89_tx_desc_info *desc_info, 7432 void *txdesc) 7433 { 7434 const struct rtw89_chip_info *chip = rtwdev->chip; 7435 7436 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 7437 } 7438 7439 static inline 7440 u8 rtw89_chip_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel) 7441 { 7442 const struct rtw89_chip_info *chip = rtwdev->chip; 7443 7444 return chip->ops->get_ch_dma[rtwdev->hci.type](rtwdev, qsel); 7445 } 7446 7447 static inline 7448 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 7449 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 7450 { 7451 const struct rtw89_chip_info *chip = rtwdev->chip; 7452 7453 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 7454 } 7455 7456 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 7457 { 7458 const struct rtw89_chip_info *chip = rtwdev->chip; 7459 7460 chip->ops->cfg_ctrl_path(rtwdev, wl); 7461 } 7462 7463 static inline 7464 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 7465 u32 *tx_en, enum rtw89_sch_tx_sel sel) 7466 { 7467 const struct rtw89_chip_info *chip = rtwdev->chip; 7468 7469 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 7470 } 7471 7472 static inline 7473 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 7474 { 7475 const struct rtw89_chip_info *chip = rtwdev->chip; 7476 7477 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 7478 } 7479 7480 static inline 7481 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 7482 struct rtw89_vif_link *rtwvif_link, 7483 struct rtw89_sta_link *rtwsta_link) 7484 { 7485 const struct rtw89_chip_info *chip = rtwdev->chip; 7486 7487 if (!chip->ops->h2c_dctl_sec_cam) 7488 return 0; 7489 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 7490 } 7491 7492 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 7493 { 7494 __le16 fc = hdr->frame_control; 7495 7496 if (ieee80211_has_tods(fc)) 7497 return hdr->addr1; 7498 else if (ieee80211_has_fromds(fc)) 7499 return hdr->addr2; 7500 else 7501 return hdr->addr3; 7502 } 7503 7504 static inline 7505 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 7506 { 7507 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 7508 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 7509 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 7510 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 7511 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 7512 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 7513 return true; 7514 return false; 7515 } 7516 7517 static inline 7518 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 7519 { 7520 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 7521 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 7522 return true; 7523 7524 return false; 7525 } 7526 7527 static inline 7528 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 7529 { 7530 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 7531 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 7532 return true; 7533 7534 return false; 7535 } 7536 7537 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 7538 enum rtw89_fw_type type) 7539 { 7540 struct rtw89_fw_info *fw_info = &rtwdev->fw; 7541 7542 switch (type) { 7543 case RTW89_FW_WOWLAN: 7544 return &fw_info->wowlan; 7545 case RTW89_FW_LOGFMT: 7546 return &fw_info->log.suit; 7547 case RTW89_FW_BBMCU0: 7548 return &fw_info->bbmcu0; 7549 case RTW89_FW_BBMCU1: 7550 return &fw_info->bbmcu1; 7551 default: 7552 break; 7553 } 7554 7555 return &fw_info->normal; 7556 } 7557 7558 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 7559 unsigned int length) 7560 { 7561 struct sk_buff *skb; 7562 7563 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 7564 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 7565 if (!skb) 7566 return NULL; 7567 7568 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 7569 return skb; 7570 } 7571 7572 return dev_alloc_skb(length); 7573 } 7574 7575 static inline bool rtw89_core_is_tx_wait(struct rtw89_dev *rtwdev, 7576 struct rtw89_tx_skb_data *skb_data) 7577 { 7578 return rcu_access_pointer(skb_data->wait); 7579 } 7580 7581 static inline bool rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 7582 struct rtw89_tx_skb_data *skb_data, 7583 u8 tx_status) 7584 { 7585 struct rtw89_tx_wait_info *wait; 7586 7587 guard(rcu)(); 7588 7589 wait = rcu_dereference(skb_data->wait); 7590 if (!wait) 7591 return false; 7592 7593 wait->tx_done = tx_status == RTW89_TX_DONE; 7594 /* Don't access skb anymore after completion */ 7595 complete_all(&wait->completion); 7596 return true; 7597 } 7598 7599 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 7600 { 7601 switch (rtwdev->mlo_dbcc_mode) { 7602 case MLO_1_PLUS_1_1RF: 7603 case MLO_1_PLUS_1_2RF: 7604 case DBCC_LEGACY: 7605 return true; 7606 default: 7607 return false; 7608 } 7609 } 7610 7611 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 7612 { 7613 if (!rtwdev->dbcc_en) 7614 return BIT(RTW89_PHY_0); 7615 7616 switch (rtwdev->mlo_dbcc_mode) { 7617 case MLO_0_PLUS_2_1RF: 7618 case MLO_0_PLUS_2_2RF: 7619 return BIT(RTW89_PHY_1); 7620 case MLO_1_PLUS_1_1RF: 7621 case MLO_1_PLUS_1_2RF: 7622 case MLO_2_PLUS_2_2RF: 7623 case DBCC_LEGACY: 7624 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 7625 case MLO_2_PLUS_0_1RF: 7626 case MLO_2_PLUS_0_2RF: 7627 default: 7628 return BIT(RTW89_PHY_0); 7629 } 7630 } 7631 7632 #define rtw89_for_each_active_bb(rtwdev, bb) \ 7633 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 7634 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 7635 if (__active_bb_bitmap & BIT(__phy_idx) && \ 7636 (bb = &rtwdev->bbs[__phy_idx])) 7637 7638 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 7639 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 7640 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 7641 if ((bb = &rtwdev->bbs[__phy_idx])) 7642 7643 static inline 7644 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 7645 enum rtw89_phy_idx phy_idx) 7646 { 7647 if (phy_idx >= RTW89_PHY_NUM) 7648 return &rtwdev->bbs[RTW89_PHY_0]; 7649 7650 return &rtwdev->bbs[phy_idx]; 7651 } 7652 7653 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7654 { 7655 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7656 7657 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7658 return true; 7659 7660 return false; 7661 } 7662 7663 static inline u32 rtw89_bytes_to_mbps(u64 bytes, enum rtw89_tfc_interval interval) 7664 { 7665 switch (interval) { 7666 default: 7667 case RTW89_TFC_INTERVAL_2SEC: 7668 return bytes >> 18; /* bytes/2s --> Mbps */; 7669 case RTW89_TFC_INTERVAL_100MS: 7670 return (bytes * 10) >> 17; /* bytes/100ms --> Mbps */ 7671 } 7672 } 7673 7674 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7675 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7676 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7677 struct sk_buff *skb, bool fwdl); 7678 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7679 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7680 struct rtw89_tx_wait_info *wait, int qsel, 7681 unsigned int timeout); 7682 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7683 struct rtw89_tx_desc_info *desc_info, 7684 void *txdesc); 7685 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7686 struct rtw89_tx_desc_info *desc_info, 7687 void *txdesc); 7688 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7689 struct rtw89_tx_desc_info *desc_info, 7690 void *txdesc); 7691 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev, 7692 struct rtw89_tx_desc_info *desc_info, 7693 void *txdesc); 7694 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7695 struct rtw89_tx_desc_info *desc_info, 7696 void *txdesc); 7697 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7698 struct rtw89_tx_desc_info *desc_info, 7699 void *txdesc); 7700 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel); 7701 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel); 7702 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel); 7703 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7704 struct rtw89_rx_desc_info *desc_info, 7705 struct sk_buff *skb); 7706 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7707 struct rtw89_rx_desc_info *desc_info, 7708 u8 *data, u32 data_offset); 7709 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7710 struct rtw89_rx_desc_info *desc_info, 7711 u8 *data, u32 data_offset); 7712 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev, 7713 struct rtw89_rx_desc_info *desc_info, 7714 u8 *data, u32 data_offset); 7715 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7716 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7717 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7718 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7719 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7720 struct rtw89_vif_link *rtwvif_link, 7721 struct rtw89_sta_link *rtwsta_link); 7722 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7723 struct rtw89_vif_link *rtwvif_link, 7724 struct rtw89_sta_link *rtwsta_link); 7725 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7726 struct rtw89_vif_link *rtwvif_link, 7727 struct rtw89_sta_link *rtwsta_link); 7728 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7729 struct rtw89_vif_link *rtwvif_link, 7730 struct rtw89_sta_link *rtwsta_link); 7731 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7732 struct rtw89_vif_link *rtwvif_link, 7733 struct rtw89_sta_link *rtwsta_link); 7734 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7735 struct ieee80211_sta *sta, 7736 struct cfg80211_tid_config *tid_config); 7737 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7738 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7739 int rtw89_core_init(struct rtw89_dev *rtwdev); 7740 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7741 int rtw89_core_register(struct rtw89_dev *rtwdev); 7742 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7743 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7744 u32 bus_data_size, 7745 const struct rtw89_chip_info *chip, 7746 const struct rtw89_chip_variant *variant); 7747 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7748 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7749 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7750 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7751 u8 mac_id, u8 port); 7752 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7753 struct rtw89_sta *rtwsta, u8 mac_id); 7754 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7755 unsigned int link_id); 7756 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7757 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7758 unsigned int link_id); 7759 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7760 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7761 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 7762 struct rtw89_vif_link *rtwvif_link); 7763 const struct rtw89_6ghz_span * 7764 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7765 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7766 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7767 struct rtw89_chan *chan); 7768 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7769 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7770 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7771 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7772 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7773 struct rtw89_sta_link *rtwsta_link, u8 tid, 7774 u8 *cam_idx); 7775 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7776 struct rtw89_sta_link *rtwsta_link, u8 tid, 7777 u8 *cam_idx); 7778 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7779 struct ieee80211_sta *sta); 7780 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7781 struct ieee80211_sta *sta); 7782 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7783 struct ieee80211_sta *sta); 7784 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7785 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7786 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7787 struct rtw89_vif_link *rtwvif_link); 7788 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate); 7789 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7790 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7791 const char *rtw89_regd_get_string(enum rtw89_regulation_type regd); 7792 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7793 struct rtw89_traffic_stats *stats); 7794 struct rtw89_wait_response * 7795 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond) 7796 __acquires(rtw89_wait); 7797 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait, 7798 struct rtw89_wait_response *prep, int err) 7799 __releases(rtw89_wait); 7800 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7801 const struct rtw89_completion_data *data); 7802 int rtw89_core_start(struct rtw89_dev *rtwdev); 7803 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7804 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7805 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7806 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7807 bool qos, bool ps, int timeout); 7808 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 7809 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7810 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7811 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7812 const u8 *mac_addr, bool hw_scan); 7813 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7814 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7815 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7816 bool active); 7817 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7818 struct rtw89_vif_link *rtwvif_link, 7819 struct ieee80211_bss_conf *bss_conf); 7820 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7821 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7822 unsigned int link_id); 7823 7824 #endif 7825