1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_efuse_block_cfg; 21 struct rtw89_h2c_rf_tssi; 22 struct rtw89_fw_txpwr_track_cfg; 23 struct rtw89_phy_rfk_log_fmt; 24 struct rtw89_debugfs; 25 struct rtw89_regd_data; 26 27 extern const struct ieee80211_ops rtw89_ops; 28 29 #define MASKBYTE0 0xff 30 #define MASKBYTE1 0xff00 31 #define MASKBYTE2 0xff0000 32 #define MASKBYTE3 0xff000000 33 #define MASKBYTE4 0xff00000000ULL 34 #define MASKHWORD 0xffff0000 35 #define MASKLWORD 0x0000ffff 36 #define MASKDWORD 0xffffffff 37 #define RFREG_MASK 0xfffff 38 #define INV_RF_DATA 0xffffffff 39 #define BYPASS_CR_DATA 0xbabecafe 40 41 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 42 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 43 #define CFO_TRACK_MAX_USER 64 44 #define MAX_RSSI 110 45 #define RSSI_FACTOR 1 46 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 47 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 48 #define DELTA_SWINGIDX_SIZE 30 49 50 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 51 #define RTW89_RADIOTAP_ROOM_EHT \ 52 (sizeof(struct ieee80211_radiotap_tlv) + \ 53 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 54 sizeof(struct ieee80211_radiotap_tlv) + \ 55 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 56 #define RTW89_RADIOTAP_ROOM \ 57 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 58 59 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 60 #define RTW89_HTC_VARIANT_HE 3 61 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 62 #define RTW89_HTC_VARIANT_HE_CID_OM 1 63 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 64 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 65 66 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 67 enum htc_om_channel_width { 68 HTC_OM_CHANNEL_WIDTH_20 = 0, 69 HTC_OM_CHANNEL_WIDTH_40 = 1, 70 HTC_OM_CHANNEL_WIDTH_80 = 2, 71 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 72 }; 73 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 74 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 75 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 76 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 77 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 78 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 79 80 #define RTW89_TF_PAD GENMASK(11, 0) 81 #define RTW89_TF_BASIC_USER_INFO_SZ 6 82 83 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 84 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 85 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 86 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 87 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 88 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 89 90 enum rtw89_subband { 91 RTW89_CH_2G = 0, 92 RTW89_CH_5G_BAND_1 = 1, 93 /* RTW89_CH_5G_BAND_2 = 2, unused */ 94 RTW89_CH_5G_BAND_3 = 3, 95 RTW89_CH_5G_BAND_4 = 4, 96 97 RTW89_CH_6G_BAND_IDX0, /* Low */ 98 RTW89_CH_6G_BAND_IDX1, /* Low */ 99 RTW89_CH_6G_BAND_IDX2, /* Mid */ 100 RTW89_CH_6G_BAND_IDX3, /* Mid */ 101 RTW89_CH_6G_BAND_IDX4, /* High */ 102 RTW89_CH_6G_BAND_IDX5, /* High */ 103 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 104 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 105 106 RTW89_SUBBAND_NR, 107 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 108 }; 109 110 enum rtw89_gain_offset { 111 RTW89_GAIN_OFFSET_2G_CCK, 112 RTW89_GAIN_OFFSET_2G_OFDM, 113 RTW89_GAIN_OFFSET_5G_LOW, 114 RTW89_GAIN_OFFSET_5G_MID, 115 RTW89_GAIN_OFFSET_5G_HIGH, 116 RTW89_GAIN_OFFSET_6G_L0, 117 RTW89_GAIN_OFFSET_6G_L1, 118 RTW89_GAIN_OFFSET_6G_M0, 119 RTW89_GAIN_OFFSET_6G_M1, 120 RTW89_GAIN_OFFSET_6G_H0, 121 RTW89_GAIN_OFFSET_6G_H1, 122 RTW89_GAIN_OFFSET_6G_UH0, 123 RTW89_GAIN_OFFSET_6G_UH1, 124 125 RTW89_GAIN_OFFSET_NR, 126 }; 127 128 enum rtw89_hci_type { 129 RTW89_HCI_TYPE_PCIE, 130 RTW89_HCI_TYPE_USB, 131 RTW89_HCI_TYPE_SDIO, 132 }; 133 134 enum rtw89_core_chip_id { 135 RTL8852A, 136 RTL8852B, 137 RTL8852BT, 138 RTL8852C, 139 RTL8851B, 140 RTL8922A, 141 }; 142 143 enum rtw89_chip_gen { 144 RTW89_CHIP_AX, 145 RTW89_CHIP_BE, 146 147 RTW89_CHIP_GEN_NUM, 148 }; 149 150 enum rtw89_cv { 151 CHIP_CAV, 152 CHIP_CBV, 153 CHIP_CCV, 154 CHIP_CDV, 155 CHIP_CEV, 156 CHIP_CFV, 157 CHIP_CV_MAX, 158 CHIP_CV_INVALID = CHIP_CV_MAX, 159 }; 160 161 enum rtw89_bacam_ver { 162 RTW89_BACAM_V0, 163 RTW89_BACAM_V1, 164 165 RTW89_BACAM_V0_EXT = 99, 166 }; 167 168 enum rtw89_core_tx_type { 169 RTW89_CORE_TX_TYPE_DATA, 170 RTW89_CORE_TX_TYPE_MGMT, 171 RTW89_CORE_TX_TYPE_FWCMD, 172 }; 173 174 enum rtw89_core_rx_type { 175 RTW89_CORE_RX_TYPE_WIFI = 0, 176 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 177 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 178 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 179 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 180 RTW89_CORE_RX_TYPE_SS2FW = 5, 181 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 182 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 183 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 184 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 185 RTW89_CORE_RX_TYPE_C2H = 10, 186 RTW89_CORE_RX_TYPE_CSI = 11, 187 RTW89_CORE_RX_TYPE_CQI = 12, 188 RTW89_CORE_RX_TYPE_H2C = 13, 189 RTW89_CORE_RX_TYPE_FWDL = 14, 190 }; 191 192 enum rtw89_txq_flags { 193 RTW89_TXQ_F_AMPDU = 0, 194 RTW89_TXQ_F_BLOCK_BA = 1, 195 RTW89_TXQ_F_FORBID_BA = 2, 196 }; 197 198 enum rtw89_net_type { 199 RTW89_NET_TYPE_NO_LINK = 0, 200 RTW89_NET_TYPE_AD_HOC = 1, 201 RTW89_NET_TYPE_INFRA = 2, 202 RTW89_NET_TYPE_AP_MODE = 3, 203 }; 204 205 enum rtw89_wifi_role { 206 RTW89_WIFI_ROLE_NONE, 207 RTW89_WIFI_ROLE_STATION, 208 RTW89_WIFI_ROLE_AP, 209 RTW89_WIFI_ROLE_AP_VLAN, 210 RTW89_WIFI_ROLE_ADHOC, 211 RTW89_WIFI_ROLE_ADHOC_MASTER, 212 RTW89_WIFI_ROLE_MESH_POINT, 213 RTW89_WIFI_ROLE_MONITOR, 214 RTW89_WIFI_ROLE_P2P_DEVICE, 215 RTW89_WIFI_ROLE_P2P_CLIENT, 216 RTW89_WIFI_ROLE_P2P_GO, 217 RTW89_WIFI_ROLE_NAN, 218 RTW89_WIFI_ROLE_MLME_MAX 219 }; 220 221 enum rtw89_upd_mode { 222 RTW89_ROLE_CREATE, 223 RTW89_ROLE_REMOVE, 224 RTW89_ROLE_TYPE_CHANGE, 225 RTW89_ROLE_INFO_CHANGE, 226 RTW89_ROLE_CON_DISCONN, 227 RTW89_ROLE_BAND_SW, 228 RTW89_ROLE_FW_RESTORE, 229 }; 230 231 enum rtw89_self_role { 232 RTW89_SELF_ROLE_CLIENT, 233 RTW89_SELF_ROLE_AP, 234 RTW89_SELF_ROLE_AP_CLIENT 235 }; 236 237 enum rtw89_msk_sO_el { 238 RTW89_NO_MSK, 239 RTW89_SMA, 240 RTW89_TMA, 241 RTW89_BSSID 242 }; 243 244 enum rtw89_sch_tx_sel { 245 RTW89_SCH_TX_SEL_ALL, 246 RTW89_SCH_TX_SEL_HIQ, 247 RTW89_SCH_TX_SEL_MG0, 248 RTW89_SCH_TX_SEL_MACID, 249 }; 250 251 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 252 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 253 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 254 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 255 */ 256 enum rtw89_add_cam_sec_mode { 257 RTW89_ADDR_CAM_SEC_NONE = 0, 258 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 259 RTW89_ADDR_CAM_SEC_NORMAL = 2, 260 RTW89_ADDR_CAM_SEC_4GROUP = 3, 261 }; 262 263 enum rtw89_sec_key_type { 264 RTW89_SEC_KEY_TYPE_NONE = 0, 265 RTW89_SEC_KEY_TYPE_WEP40 = 1, 266 RTW89_SEC_KEY_TYPE_WEP104 = 2, 267 RTW89_SEC_KEY_TYPE_TKIP = 3, 268 RTW89_SEC_KEY_TYPE_WAPI = 4, 269 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 270 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 271 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 272 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 273 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 274 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 275 }; 276 277 enum rtw89_port { 278 RTW89_PORT_0 = 0, 279 RTW89_PORT_1 = 1, 280 RTW89_PORT_2 = 2, 281 RTW89_PORT_3 = 3, 282 RTW89_PORT_4 = 4, 283 RTW89_PORT_NUM 284 }; 285 286 enum rtw89_band { 287 RTW89_BAND_2G = 0, 288 RTW89_BAND_5G = 1, 289 RTW89_BAND_6G = 2, 290 RTW89_BAND_NUM, 291 }; 292 293 enum rtw89_hw_rate { 294 RTW89_HW_RATE_CCK1 = 0x0, 295 RTW89_HW_RATE_CCK2 = 0x1, 296 RTW89_HW_RATE_CCK5_5 = 0x2, 297 RTW89_HW_RATE_CCK11 = 0x3, 298 RTW89_HW_RATE_OFDM6 = 0x4, 299 RTW89_HW_RATE_OFDM9 = 0x5, 300 RTW89_HW_RATE_OFDM12 = 0x6, 301 RTW89_HW_RATE_OFDM18 = 0x7, 302 RTW89_HW_RATE_OFDM24 = 0x8, 303 RTW89_HW_RATE_OFDM36 = 0x9, 304 RTW89_HW_RATE_OFDM48 = 0xA, 305 RTW89_HW_RATE_OFDM54 = 0xB, 306 RTW89_HW_RATE_MCS0 = 0x80, 307 RTW89_HW_RATE_MCS1 = 0x81, 308 RTW89_HW_RATE_MCS2 = 0x82, 309 RTW89_HW_RATE_MCS3 = 0x83, 310 RTW89_HW_RATE_MCS4 = 0x84, 311 RTW89_HW_RATE_MCS5 = 0x85, 312 RTW89_HW_RATE_MCS6 = 0x86, 313 RTW89_HW_RATE_MCS7 = 0x87, 314 RTW89_HW_RATE_MCS8 = 0x88, 315 RTW89_HW_RATE_MCS9 = 0x89, 316 RTW89_HW_RATE_MCS10 = 0x8A, 317 RTW89_HW_RATE_MCS11 = 0x8B, 318 RTW89_HW_RATE_MCS12 = 0x8C, 319 RTW89_HW_RATE_MCS13 = 0x8D, 320 RTW89_HW_RATE_MCS14 = 0x8E, 321 RTW89_HW_RATE_MCS15 = 0x8F, 322 RTW89_HW_RATE_MCS16 = 0x90, 323 RTW89_HW_RATE_MCS17 = 0x91, 324 RTW89_HW_RATE_MCS18 = 0x92, 325 RTW89_HW_RATE_MCS19 = 0x93, 326 RTW89_HW_RATE_MCS20 = 0x94, 327 RTW89_HW_RATE_MCS21 = 0x95, 328 RTW89_HW_RATE_MCS22 = 0x96, 329 RTW89_HW_RATE_MCS23 = 0x97, 330 RTW89_HW_RATE_MCS24 = 0x98, 331 RTW89_HW_RATE_MCS25 = 0x99, 332 RTW89_HW_RATE_MCS26 = 0x9A, 333 RTW89_HW_RATE_MCS27 = 0x9B, 334 RTW89_HW_RATE_MCS28 = 0x9C, 335 RTW89_HW_RATE_MCS29 = 0x9D, 336 RTW89_HW_RATE_MCS30 = 0x9E, 337 RTW89_HW_RATE_MCS31 = 0x9F, 338 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 339 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 340 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 341 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 342 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 343 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 344 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 345 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 346 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 347 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 348 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 349 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 350 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 351 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 352 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 353 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 354 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 355 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 356 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 357 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 358 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 359 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 360 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 361 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 362 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 363 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 364 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 365 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 366 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 367 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 368 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 369 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 370 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 371 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 372 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 373 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 374 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 375 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 376 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 377 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 378 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 379 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 380 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 381 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 382 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 383 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 384 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 385 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 386 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 387 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 388 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 389 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 390 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 391 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 392 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 393 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 394 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 395 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 396 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 397 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 398 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 399 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 400 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 401 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 402 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 403 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 404 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 405 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 406 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 407 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 408 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 409 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 410 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 411 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 412 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 413 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 414 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 415 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 416 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 417 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 418 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 419 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 420 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 421 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 422 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 423 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 424 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 425 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 426 427 RTW89_HW_RATE_V1_MCS0 = 0x100, 428 RTW89_HW_RATE_V1_MCS1 = 0x101, 429 RTW89_HW_RATE_V1_MCS2 = 0x102, 430 RTW89_HW_RATE_V1_MCS3 = 0x103, 431 RTW89_HW_RATE_V1_MCS4 = 0x104, 432 RTW89_HW_RATE_V1_MCS5 = 0x105, 433 RTW89_HW_RATE_V1_MCS6 = 0x106, 434 RTW89_HW_RATE_V1_MCS7 = 0x107, 435 RTW89_HW_RATE_V1_MCS8 = 0x108, 436 RTW89_HW_RATE_V1_MCS9 = 0x109, 437 RTW89_HW_RATE_V1_MCS10 = 0x10A, 438 RTW89_HW_RATE_V1_MCS11 = 0x10B, 439 RTW89_HW_RATE_V1_MCS12 = 0x10C, 440 RTW89_HW_RATE_V1_MCS13 = 0x10D, 441 RTW89_HW_RATE_V1_MCS14 = 0x10E, 442 RTW89_HW_RATE_V1_MCS15 = 0x10F, 443 RTW89_HW_RATE_V1_MCS16 = 0x110, 444 RTW89_HW_RATE_V1_MCS17 = 0x111, 445 RTW89_HW_RATE_V1_MCS18 = 0x112, 446 RTW89_HW_RATE_V1_MCS19 = 0x113, 447 RTW89_HW_RATE_V1_MCS20 = 0x114, 448 RTW89_HW_RATE_V1_MCS21 = 0x115, 449 RTW89_HW_RATE_V1_MCS22 = 0x116, 450 RTW89_HW_RATE_V1_MCS23 = 0x117, 451 RTW89_HW_RATE_V1_MCS24 = 0x118, 452 RTW89_HW_RATE_V1_MCS25 = 0x119, 453 RTW89_HW_RATE_V1_MCS26 = 0x11A, 454 RTW89_HW_RATE_V1_MCS27 = 0x11B, 455 RTW89_HW_RATE_V1_MCS28 = 0x11C, 456 RTW89_HW_RATE_V1_MCS29 = 0x11D, 457 RTW89_HW_RATE_V1_MCS30 = 0x11E, 458 RTW89_HW_RATE_V1_MCS31 = 0x11F, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 469 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 470 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 481 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 482 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 493 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 494 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 505 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 506 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 517 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 518 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 529 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 530 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 541 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 542 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 553 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 554 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 570 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 583 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 584 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 597 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 598 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 611 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 612 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 613 614 RTW89_HW_RATE_NR, 615 RTW89_HW_RATE_INVAL, 616 617 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 618 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 619 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 620 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 621 }; 622 623 /* 2G channels, 624 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 625 */ 626 #define RTW89_2G_CH_NUM 14 627 628 /* 5G channels, 629 * 36, 38, 40, 42, 44, 46, 48, 50, 630 * 52, 54, 56, 58, 60, 62, 64, 631 * 100, 102, 104, 106, 108, 110, 112, 114, 632 * 116, 118, 120, 122, 124, 126, 128, 130, 633 * 132, 134, 136, 138, 140, 142, 144, 634 * 149, 151, 153, 155, 157, 159, 161, 163, 635 * 165, 167, 169, 171, 173, 175, 177 636 */ 637 #define RTW89_5G_CH_NUM 53 638 639 /* 6G channels, 640 * 1, 3, 5, 7, 9, 11, 13, 15, 641 * 17, 19, 21, 23, 25, 27, 29, 33, 642 * 35, 37, 39, 41, 43, 45, 47, 49, 643 * 51, 53, 55, 57, 59, 61, 65, 67, 644 * 69, 71, 73, 75, 77, 79, 81, 83, 645 * 85, 87, 89, 91, 93, 97, 99, 101, 646 * 103, 105, 107, 109, 111, 113, 115, 117, 647 * 119, 121, 123, 125, 129, 131, 133, 135, 648 * 137, 139, 141, 143, 145, 147, 149, 151, 649 * 153, 155, 157, 161, 163, 165, 167, 169, 650 * 171, 173, 175, 177, 179, 181, 183, 185, 651 * 187, 189, 193, 195, 197, 199, 201, 203, 652 * 205, 207, 209, 211, 213, 215, 217, 219, 653 * 221, 225, 227, 229, 231, 233, 235, 237, 654 * 239, 241, 243, 245, 247, 249, 251, 253, 655 */ 656 #define RTW89_6G_CH_NUM 120 657 658 enum rtw89_rate_section { 659 RTW89_RS_CCK, 660 RTW89_RS_OFDM, 661 RTW89_RS_MCS, /* for HT/VHT/HE */ 662 RTW89_RS_HEDCM, 663 RTW89_RS_OFFSET, 664 RTW89_RS_NUM, 665 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 666 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 667 }; 668 669 enum rtw89_rate_offset_indexes { 670 RTW89_RATE_OFFSET_HE, 671 RTW89_RATE_OFFSET_VHT, 672 RTW89_RATE_OFFSET_HT, 673 RTW89_RATE_OFFSET_OFDM, 674 RTW89_RATE_OFFSET_CCK, 675 RTW89_RATE_OFFSET_DLRU_EHT, 676 RTW89_RATE_OFFSET_DLRU_HE, 677 RTW89_RATE_OFFSET_EHT, 678 __RTW89_RATE_OFFSET_NUM, 679 680 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 681 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 682 }; 683 684 enum rtw89_rate_num { 685 RTW89_RATE_CCK_NUM = 4, 686 RTW89_RATE_OFDM_NUM = 8, 687 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 688 689 RTW89_RATE_MCS_NUM_AX = 12, 690 RTW89_RATE_MCS_NUM_BE = 16, 691 __RTW89_RATE_MCS_NUM = 16, 692 }; 693 694 enum rtw89_nss { 695 RTW89_NSS_1 = 0, 696 RTW89_NSS_2 = 1, 697 /* HE DCM only support 1ss and 2ss */ 698 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 699 RTW89_NSS_3 = 2, 700 RTW89_NSS_4 = 3, 701 RTW89_NSS_NUM, 702 }; 703 704 enum rtw89_ntx { 705 RTW89_1TX = 0, 706 RTW89_2TX = 1, 707 RTW89_NTX_NUM, 708 }; 709 710 enum rtw89_beamforming_type { 711 RTW89_NONBF = 0, 712 RTW89_BF = 1, 713 RTW89_BF_NUM, 714 }; 715 716 enum rtw89_ofdma_type { 717 RTW89_NON_OFDMA = 0, 718 RTW89_OFDMA = 1, 719 RTW89_OFDMA_NUM, 720 }; 721 722 /* neither insert new in the middle, nor change any given definition */ 723 enum rtw89_regulation_type { 724 RTW89_WW = 0, 725 RTW89_ETSI = 1, 726 RTW89_FCC = 2, 727 RTW89_MKK = 3, 728 RTW89_NA = 4, 729 RTW89_IC = 5, 730 RTW89_KCC = 6, 731 RTW89_ACMA = 7, 732 RTW89_NCC = 8, 733 RTW89_MEXICO = 9, 734 RTW89_CHILE = 10, 735 RTW89_UKRAINE = 11, 736 RTW89_CN = 12, 737 RTW89_QATAR = 13, 738 RTW89_UK = 14, 739 RTW89_THAILAND = 15, 740 RTW89_REGD_NUM, 741 }; 742 743 enum rtw89_reg_6ghz_power { 744 RTW89_REG_6GHZ_POWER_VLP = 0, 745 RTW89_REG_6GHZ_POWER_LPI = 1, 746 RTW89_REG_6GHZ_POWER_STD = 2, 747 748 NUM_OF_RTW89_REG_6GHZ_POWER, 749 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 750 }; 751 752 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 753 754 /* calculate based on ieee80211 Transmit Power Envelope */ 755 struct rtw89_reg_6ghz_tpe { 756 bool valid; 757 s8 constraint; /* unit: dBm */ 758 }; 759 760 enum rtw89_fw_pkt_ofld_type { 761 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 762 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 763 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 764 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 765 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 766 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 767 RTW89_PKT_OFLD_TYPE_NDP = 6, 768 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 769 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 770 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 771 RTW89_PKT_OFLD_TYPE_NUM, 772 }; 773 774 struct rtw89_txpwr_byrate { 775 s8 cck[RTW89_RATE_CCK_NUM]; 776 s8 ofdm[RTW89_RATE_OFDM_NUM]; 777 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 778 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 779 s8 offset[__RTW89_RATE_OFFSET_NUM]; 780 s8 trap; 781 }; 782 783 struct rtw89_rate_desc { 784 enum rtw89_nss nss; 785 enum rtw89_rate_section rs; 786 enum rtw89_ofdma_type ofdma; 787 u8 idx; 788 }; 789 790 #define PHY_STS_HDR_LEN 8 791 #define RF_PATH_MAX 4 792 #define RTW89_MAX_PPDU_CNT 8 793 struct rtw89_rx_phy_ppdu { 794 void *buf; 795 u32 len; 796 u8 rssi_avg; 797 u8 rssi[RF_PATH_MAX]; 798 u8 mac_id; 799 u8 chan_idx; 800 u8 ie; 801 u16 rate; 802 u8 rpl_avg; 803 u8 rpl_path[RF_PATH_MAX]; 804 u8 rpl_fd[RF_PATH_MAX]; 805 u8 bw_idx; 806 u8 rx_path_en; 807 struct { 808 bool has; 809 u8 avg_snr; 810 u8 evm_max; 811 u8 evm_min; 812 } ofdm; 813 bool has_data; 814 bool has_bcn; 815 bool ldpc; 816 bool stbc; 817 bool to_self; 818 bool valid; 819 bool hdr_2_en; 820 }; 821 822 enum rtw89_mac_idx { 823 RTW89_MAC_0 = 0, 824 RTW89_MAC_1 = 1, 825 RTW89_MAC_NUM, 826 }; 827 828 enum rtw89_phy_idx { 829 RTW89_PHY_0 = 0, 830 RTW89_PHY_1 = 1, 831 RTW89_PHY_NUM, 832 }; 833 834 #define __RTW89_MLD_MAX_LINK_NUM 2 835 #define RTW89_MLD_NON_STA_LINK_NUM 1 836 837 enum rtw89_chanctx_idx { 838 RTW89_CHANCTX_0 = 0, 839 RTW89_CHANCTX_1 = 1, 840 841 NUM_OF_RTW89_CHANCTX, 842 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 843 }; 844 845 enum rtw89_rf_path { 846 RF_PATH_A = 0, 847 RF_PATH_B = 1, 848 RF_PATH_C = 2, 849 RF_PATH_D = 3, 850 RF_PATH_AB, 851 RF_PATH_AC, 852 RF_PATH_AD, 853 RF_PATH_BC, 854 RF_PATH_BD, 855 RF_PATH_CD, 856 RF_PATH_ABC, 857 RF_PATH_ABD, 858 RF_PATH_ACD, 859 RF_PATH_BCD, 860 RF_PATH_ABCD, 861 }; 862 863 enum rtw89_rf_path_bit { 864 RF_A = BIT(0), 865 RF_B = BIT(1), 866 RF_C = BIT(2), 867 RF_D = BIT(3), 868 869 RF_AB = (RF_A | RF_B), 870 RF_AC = (RF_A | RF_C), 871 RF_AD = (RF_A | RF_D), 872 RF_BC = (RF_B | RF_C), 873 RF_BD = (RF_B | RF_D), 874 RF_CD = (RF_C | RF_D), 875 876 RF_ABC = (RF_A | RF_B | RF_C), 877 RF_ABD = (RF_A | RF_B | RF_D), 878 RF_ACD = (RF_A | RF_C | RF_D), 879 RF_BCD = (RF_B | RF_C | RF_D), 880 881 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 882 }; 883 884 enum rtw89_bandwidth { 885 RTW89_CHANNEL_WIDTH_20 = 0, 886 RTW89_CHANNEL_WIDTH_40 = 1, 887 RTW89_CHANNEL_WIDTH_80 = 2, 888 RTW89_CHANNEL_WIDTH_160 = 3, 889 RTW89_CHANNEL_WIDTH_320 = 4, 890 891 /* keep index order above */ 892 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 893 894 RTW89_CHANNEL_WIDTH_80_80 = 5, 895 RTW89_CHANNEL_WIDTH_5 = 6, 896 RTW89_CHANNEL_WIDTH_10 = 7, 897 }; 898 899 enum rtw89_ps_mode { 900 RTW89_PS_MODE_NONE = 0, 901 RTW89_PS_MODE_RFOFF = 1, 902 RTW89_PS_MODE_CLK_GATED = 2, 903 RTW89_PS_MODE_PWR_GATED = 3, 904 }; 905 906 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 907 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 908 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 909 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 910 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 911 912 enum rtw89_pe_duration { 913 RTW89_PE_DURATION_0 = 0, 914 RTW89_PE_DURATION_8 = 1, 915 RTW89_PE_DURATION_16 = 2, 916 RTW89_PE_DURATION_16_20 = 3, 917 }; 918 919 enum rtw89_ru_bandwidth { 920 RTW89_RU26 = 0, 921 RTW89_RU52 = 1, 922 RTW89_RU106 = 2, 923 RTW89_RU52_26 = 3, 924 RTW89_RU106_26 = 4, 925 RTW89_RU_NUM, 926 }; 927 928 enum rtw89_sc_offset { 929 RTW89_SC_DONT_CARE = 0, 930 RTW89_SC_20_UPPER = 1, 931 RTW89_SC_20_LOWER = 2, 932 RTW89_SC_20_UPMOST = 3, 933 RTW89_SC_20_LOWEST = 4, 934 RTW89_SC_20_UP2X = 5, 935 RTW89_SC_20_LOW2X = 6, 936 RTW89_SC_20_UP3X = 7, 937 RTW89_SC_20_LOW3X = 8, 938 RTW89_SC_40_UPPER = 9, 939 RTW89_SC_40_LOWER = 10, 940 }; 941 942 /* only mgd features can be added to the enum */ 943 enum rtw89_wow_flags { 944 RTW89_WOW_FLAG_EN_MAGIC_PKT, 945 RTW89_WOW_FLAG_EN_REKEY_PKT, 946 RTW89_WOW_FLAG_EN_DISCONNECT, 947 RTW89_WOW_FLAG_EN_PATTERN, 948 RTW89_WOW_FLAG_NUM, 949 }; 950 951 struct rtw89_chan { 952 u8 channel; 953 u8 primary_channel; 954 enum rtw89_band band_type; 955 enum rtw89_bandwidth band_width; 956 957 /* The follow-up are derived from the above. We must ensure that it 958 * is assigned correctly in rtw89_chan_create() if new one is added. 959 */ 960 u32 freq; 961 enum rtw89_subband subband_type; 962 enum rtw89_sc_offset pri_ch_idx; 963 u8 pri_sb_idx; 964 }; 965 966 struct rtw89_chan_rcd { 967 u8 prev_primary_channel; 968 enum rtw89_band prev_band_type; 969 bool band_changed; 970 }; 971 972 struct rtw89_channel_help_params { 973 u32 tx_en; 974 }; 975 976 struct rtw89_port_reg { 977 u32 port_cfg; 978 u32 tbtt_prohib; 979 u32 bcn_area; 980 u32 bcn_early; 981 u32 tbtt_early; 982 u32 tbtt_agg; 983 u32 bcn_space; 984 u32 bcn_forcetx; 985 u32 bcn_err_cnt; 986 u32 bcn_err_flag; 987 u32 dtim_ctrl; 988 u32 tbtt_shift; 989 u32 bcn_cnt_tmr; 990 u32 tsftr_l; 991 u32 tsftr_h; 992 u32 md_tsft; 993 u32 bss_color; 994 u32 mbssid; 995 u32 mbssid_drop; 996 u32 tsf_sync; 997 u32 ptcl_dbg; 998 u32 ptcl_dbg_info; 999 u32 bcn_drop_all; 1000 u32 hiq_win[RTW89_PORT_NUM]; 1001 }; 1002 1003 struct rtw89_txwd_body { 1004 __le32 dword0; 1005 __le32 dword1; 1006 __le32 dword2; 1007 __le32 dword3; 1008 __le32 dword4; 1009 __le32 dword5; 1010 } __packed; 1011 1012 struct rtw89_txwd_body_v1 { 1013 __le32 dword0; 1014 __le32 dword1; 1015 __le32 dword2; 1016 __le32 dword3; 1017 __le32 dword4; 1018 __le32 dword5; 1019 __le32 dword6; 1020 __le32 dword7; 1021 } __packed; 1022 1023 struct rtw89_txwd_body_v2 { 1024 __le32 dword0; 1025 __le32 dword1; 1026 __le32 dword2; 1027 __le32 dword3; 1028 __le32 dword4; 1029 __le32 dword5; 1030 __le32 dword6; 1031 __le32 dword7; 1032 } __packed; 1033 1034 struct rtw89_txwd_info { 1035 __le32 dword0; 1036 __le32 dword1; 1037 __le32 dword2; 1038 __le32 dword3; 1039 __le32 dword4; 1040 __le32 dword5; 1041 } __packed; 1042 1043 struct rtw89_txwd_info_v2 { 1044 __le32 dword0; 1045 __le32 dword1; 1046 __le32 dword2; 1047 __le32 dword3; 1048 __le32 dword4; 1049 __le32 dword5; 1050 __le32 dword6; 1051 __le32 dword7; 1052 } __packed; 1053 1054 struct rtw89_rx_desc_info { 1055 u16 pkt_size; 1056 u8 pkt_type; 1057 u8 drv_info_size; 1058 u8 phy_rpt_size; 1059 u8 hdr_cnv_size; 1060 u8 shift; 1061 u8 wl_hd_iv_len; 1062 bool long_rxdesc; 1063 bool bb_sel; 1064 bool mac_info_valid; 1065 u16 data_rate; 1066 u8 gi_ltf; 1067 u8 bw; 1068 u32 free_run_cnt; 1069 u8 user_id; 1070 bool sr_en; 1071 u8 ppdu_cnt; 1072 u8 ppdu_type; 1073 bool icv_err; 1074 bool crc32_err; 1075 bool hw_dec; 1076 bool sw_dec; 1077 bool addr1_match; 1078 u8 frag; 1079 u16 seq; 1080 u8 frame_type; 1081 u8 rx_pl_id; 1082 bool addr_cam_valid; 1083 u8 addr_cam_id; 1084 u8 sec_cam_id; 1085 u8 mac_id; 1086 u16 offset; 1087 u16 rxd_len; 1088 bool ready; 1089 u16 rssi; 1090 }; 1091 1092 struct rtw89_rxdesc_short { 1093 __le32 dword0; 1094 __le32 dword1; 1095 __le32 dword2; 1096 __le32 dword3; 1097 } __packed; 1098 1099 struct rtw89_rxdesc_short_v2 { 1100 __le32 dword0; 1101 __le32 dword1; 1102 __le32 dword2; 1103 __le32 dword3; 1104 __le32 dword4; 1105 __le32 dword5; 1106 } __packed; 1107 1108 struct rtw89_rxdesc_long { 1109 __le32 dword0; 1110 __le32 dword1; 1111 __le32 dword2; 1112 __le32 dword3; 1113 __le32 dword4; 1114 __le32 dword5; 1115 __le32 dword6; 1116 __le32 dword7; 1117 } __packed; 1118 1119 struct rtw89_rxdesc_long_v2 { 1120 __le32 dword0; 1121 __le32 dword1; 1122 __le32 dword2; 1123 __le32 dword3; 1124 __le32 dword4; 1125 __le32 dword5; 1126 __le32 dword6; 1127 __le32 dword7; 1128 __le32 dword8; 1129 __le32 dword9; 1130 } __packed; 1131 1132 struct rtw89_rxdesc_phy_rpt_v2 { 1133 __le32 dword0; 1134 __le32 dword1; 1135 } __packed; 1136 1137 struct rtw89_tx_desc_info { 1138 u16 pkt_size; 1139 u8 wp_offset; 1140 u8 mac_id; 1141 u8 qsel; 1142 u8 ch_dma; 1143 u8 hdr_llc_len; 1144 bool is_bmc; 1145 bool en_wd_info; 1146 bool wd_page; 1147 bool use_rate; 1148 bool dis_data_fb; 1149 bool tid_indicate; 1150 bool agg_en; 1151 bool bk; 1152 u8 ampdu_density; 1153 u8 ampdu_num; 1154 bool sec_en; 1155 u8 addr_info_nr; 1156 u8 sec_keyid; 1157 u8 sec_type; 1158 u8 sec_cam_idx; 1159 u8 sec_seq[6]; 1160 u16 data_rate; 1161 u16 data_retry_lowest_rate; 1162 bool fw_dl; 1163 u16 seq; 1164 bool a_ctrl_bsr; 1165 u8 hw_ssn_sel; 1166 #define RTW89_MGMT_HW_SSN_SEL 1 1167 u8 hw_seq_mode; 1168 #define RTW89_MGMT_HW_SEQ_MODE 1 1169 bool hiq; 1170 u8 port; 1171 bool er_cap; 1172 bool stbc; 1173 bool ldpc; 1174 bool upd_wlan_hdr; 1175 bool mlo; 1176 }; 1177 1178 struct rtw89_core_tx_request { 1179 enum rtw89_core_tx_type tx_type; 1180 1181 struct sk_buff *skb; 1182 struct ieee80211_vif *vif; 1183 struct ieee80211_sta *sta; 1184 struct rtw89_vif_link *rtwvif_link; 1185 struct rtw89_sta_link *rtwsta_link; 1186 struct rtw89_tx_desc_info desc_info; 1187 }; 1188 1189 struct rtw89_txq { 1190 struct list_head list; 1191 unsigned long flags; 1192 int wait_cnt; 1193 }; 1194 1195 struct rtw89_mac_ax_gnt { 1196 u8 gnt_bt_sw_en; 1197 u8 gnt_bt; 1198 u8 gnt_wl_sw_en; 1199 u8 gnt_wl; 1200 } __packed; 1201 1202 struct rtw89_mac_ax_wl_act { 1203 u8 wlan_act_en; 1204 u8 wlan_act; 1205 }; 1206 1207 #define RTW89_MAC_AX_COEX_GNT_NR 2 1208 struct rtw89_mac_ax_coex_gnt { 1209 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1210 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1211 }; 1212 1213 enum rtw89_btc_ncnt { 1214 BTC_NCNT_POWER_ON = 0x0, 1215 BTC_NCNT_POWER_OFF, 1216 BTC_NCNT_INIT_COEX, 1217 BTC_NCNT_SCAN_START, 1218 BTC_NCNT_SCAN_FINISH, 1219 BTC_NCNT_SPECIAL_PACKET, 1220 BTC_NCNT_SWITCH_BAND, 1221 BTC_NCNT_RFK_TIMEOUT, 1222 BTC_NCNT_SHOW_COEX_INFO, 1223 BTC_NCNT_ROLE_INFO, 1224 BTC_NCNT_CONTROL, 1225 BTC_NCNT_RADIO_STATE, 1226 BTC_NCNT_CUSTOMERIZE, 1227 BTC_NCNT_WL_RFK, 1228 BTC_NCNT_WL_STA, 1229 BTC_NCNT_WL_STA_LAST, 1230 BTC_NCNT_FWINFO, 1231 BTC_NCNT_TIMER, 1232 BTC_NCNT_SWITCH_CHBW, 1233 BTC_NCNT_RESUME_DL_FW, 1234 BTC_NCNT_COUNTRYCODE, 1235 BTC_NCNT_NUM, 1236 }; 1237 1238 enum rtw89_btc_btinfo { 1239 BTC_BTINFO_L0 = 0, 1240 BTC_BTINFO_L1, 1241 BTC_BTINFO_L2, 1242 BTC_BTINFO_L3, 1243 BTC_BTINFO_H0, 1244 BTC_BTINFO_H1, 1245 BTC_BTINFO_H2, 1246 BTC_BTINFO_H3, 1247 BTC_BTINFO_MAX 1248 }; 1249 1250 enum rtw89_btc_dcnt { 1251 BTC_DCNT_RUN = 0x0, 1252 BTC_DCNT_CX_RUNINFO, 1253 BTC_DCNT_RPT, 1254 BTC_DCNT_RPT_HANG, 1255 BTC_DCNT_CYCLE, 1256 BTC_DCNT_CYCLE_HANG, 1257 BTC_DCNT_W1, 1258 BTC_DCNT_W1_HANG, 1259 BTC_DCNT_B1, 1260 BTC_DCNT_B1_HANG, 1261 BTC_DCNT_TDMA_NONSYNC, 1262 BTC_DCNT_SLOT_NONSYNC, 1263 BTC_DCNT_BTCNT_HANG, 1264 BTC_DCNT_BTTX_HANG, 1265 BTC_DCNT_WL_SLOT_DRIFT, 1266 BTC_DCNT_WL_STA_LAST, 1267 BTC_DCNT_BT_SLOT_DRIFT, 1268 BTC_DCNT_BT_SLOT_FLOOD, 1269 BTC_DCNT_FDDT_TRIG, 1270 BTC_DCNT_E2G, 1271 BTC_DCNT_E2G_HANG, 1272 BTC_DCNT_WL_FW_VER_MATCH, 1273 BTC_DCNT_NULL_TX_FAIL, 1274 BTC_DCNT_WL_STA_NTFY, 1275 BTC_DCNT_NUM, 1276 }; 1277 1278 enum rtw89_btc_wl_state_cnt { 1279 BTC_WCNT_SCANAP = 0x0, 1280 BTC_WCNT_DHCP, 1281 BTC_WCNT_EAPOL, 1282 BTC_WCNT_ARP, 1283 BTC_WCNT_SCBDUPDATE, 1284 BTC_WCNT_RFK_REQ, 1285 BTC_WCNT_RFK_GO, 1286 BTC_WCNT_RFK_REJECT, 1287 BTC_WCNT_RFK_TIMEOUT, 1288 BTC_WCNT_CH_UPDATE, 1289 BTC_WCNT_DBCC_ALL_2G, 1290 BTC_WCNT_DBCC_CHG, 1291 BTC_WCNT_RX_OK_LAST, 1292 BTC_WCNT_RX_OK_LAST2S, 1293 BTC_WCNT_RX_ERR_LAST, 1294 BTC_WCNT_RX_ERR_LAST2S, 1295 BTC_WCNT_RX_LAST, 1296 BTC_WCNT_NUM 1297 }; 1298 1299 enum rtw89_btc_bt_state_cnt { 1300 BTC_BCNT_RETRY = 0x0, 1301 BTC_BCNT_REINIT, 1302 BTC_BCNT_REENABLE, 1303 BTC_BCNT_SCBDREAD, 1304 BTC_BCNT_RELINK, 1305 BTC_BCNT_IGNOWL, 1306 BTC_BCNT_INQPAG, 1307 BTC_BCNT_INQ, 1308 BTC_BCNT_PAGE, 1309 BTC_BCNT_ROLESW, 1310 BTC_BCNT_AFH, 1311 BTC_BCNT_INFOUPDATE, 1312 BTC_BCNT_INFOSAME, 1313 BTC_BCNT_SCBDUPDATE, 1314 BTC_BCNT_HIPRI_TX, 1315 BTC_BCNT_HIPRI_RX, 1316 BTC_BCNT_LOPRI_TX, 1317 BTC_BCNT_LOPRI_RX, 1318 BTC_BCNT_POLUT, 1319 BTC_BCNT_POLUT_NOW, 1320 BTC_BCNT_POLUT_DIFF, 1321 BTC_BCNT_RATECHG, 1322 BTC_BCNT_NUM, 1323 }; 1324 1325 enum rtw89_btc_bt_profile { 1326 BTC_BT_NOPROFILE = 0, 1327 BTC_BT_HFP = BIT(0), 1328 BTC_BT_HID = BIT(1), 1329 BTC_BT_A2DP = BIT(2), 1330 BTC_BT_PAN = BIT(3), 1331 BTC_PROFILE_MAX = 4, 1332 }; 1333 1334 struct rtw89_btc_ant_info { 1335 u8 type; /* shared, dedicated */ 1336 u8 num; 1337 u8 isolation; 1338 1339 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1340 u8 diversity: 1; 1341 u8 btg_pos: 2; 1342 u8 stream_cnt: 4; 1343 }; 1344 1345 struct rtw89_btc_ant_info_v7 { 1346 u8 type; /* shared, dedicated(non-shared) */ 1347 u8 num; /* antenna count */ 1348 u8 isolation; 1349 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1350 1351 u8 diversity; /* only for wifi use 1-antenna */ 1352 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1353 u8 stream_cnt; /* spatial_stream count */ 1354 u8 rsvd; 1355 } __packed; 1356 1357 enum rtw89_tfc_dir { 1358 RTW89_TFC_UL, 1359 RTW89_TFC_DL, 1360 }; 1361 1362 struct rtw89_btc_wl_smap { 1363 u32 busy: 1; 1364 u32 scan: 1; 1365 u32 connecting: 1; 1366 u32 roaming: 1; 1367 u32 dbccing: 1; 1368 u32 _4way: 1; 1369 u32 rf_off: 1; 1370 u32 lps: 2; 1371 u32 ips: 1; 1372 u32 init_ok: 1; 1373 u32 traffic_dir : 2; 1374 u32 rf_off_pre: 1; 1375 u32 lps_pre: 2; 1376 u32 lps_exiting: 1; 1377 u32 emlsr: 1; 1378 }; 1379 1380 enum rtw89_tfc_lv { 1381 RTW89_TFC_IDLE, 1382 RTW89_TFC_ULTRA_LOW, 1383 RTW89_TFC_LOW, 1384 RTW89_TFC_MID, 1385 RTW89_TFC_HIGH, 1386 }; 1387 1388 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1389 DECLARE_EWMA(tp, 10, 2); 1390 1391 struct rtw89_traffic_stats { 1392 /* units in bytes */ 1393 u64 tx_unicast; 1394 u64 rx_unicast; 1395 u32 tx_avg_len; 1396 u32 rx_avg_len; 1397 1398 /* count for packets */ 1399 u64 tx_cnt; 1400 u64 rx_cnt; 1401 1402 /* units in Mbps */ 1403 u32 tx_throughput; 1404 u32 rx_throughput; 1405 u32 tx_throughput_raw; 1406 u32 rx_throughput_raw; 1407 1408 u32 rx_tf_acc; 1409 u32 rx_tf_periodic; 1410 1411 enum rtw89_tfc_lv tx_tfc_lv; 1412 enum rtw89_tfc_lv rx_tfc_lv; 1413 struct ewma_tp tx_ewma_tp; 1414 struct ewma_tp rx_ewma_tp; 1415 1416 u16 tx_rate; 1417 u16 rx_rate; 1418 }; 1419 1420 struct rtw89_btc_chdef { 1421 u8 center_ch; 1422 u8 band; 1423 u8 chan; 1424 enum rtw89_sc_offset offset; 1425 enum rtw89_bandwidth bw; 1426 }; 1427 1428 struct rtw89_btc_statistic { 1429 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1430 struct rtw89_traffic_stats traffic; 1431 }; 1432 1433 #define BTC_WL_RSSI_THMAX 4 1434 1435 struct rtw89_btc_wl_link_info { 1436 struct rtw89_btc_chdef chdef; 1437 struct rtw89_btc_statistic stat; 1438 enum rtw89_tfc_dir dir; 1439 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1440 u8 mac_addr[ETH_ALEN]; 1441 u8 busy; 1442 u8 ch; 1443 u8 bw; 1444 u8 band; 1445 u8 role; 1446 u8 pid; 1447 u8 phy; 1448 u8 dtim_period; 1449 u8 mode; 1450 u8 tx_1ss_limit; 1451 1452 u8 mac_id; 1453 u8 tx_retry; 1454 1455 u32 bcn_period; 1456 u32 busy_t; 1457 u32 tx_time; 1458 u32 client_cnt; 1459 u32 rx_rate_drop_cnt; 1460 u32 noa_duration; 1461 1462 u32 active: 1; 1463 u32 noa: 1; 1464 u32 client_ps: 1; 1465 u32 connected: 2; 1466 }; 1467 1468 union rtw89_btc_wl_state_map { 1469 u32 val; 1470 struct rtw89_btc_wl_smap map; 1471 }; 1472 1473 struct rtw89_btc_bt_hfp_desc { 1474 u32 exist: 1; 1475 u32 type: 2; 1476 u32 rsvd: 29; 1477 }; 1478 1479 struct rtw89_btc_bt_hid_desc { 1480 u32 exist: 1; 1481 u32 slot_info: 2; 1482 u32 pair_cnt: 2; 1483 u32 type: 8; 1484 u32 rsvd: 19; 1485 }; 1486 1487 struct rtw89_btc_bt_a2dp_desc { 1488 u8 exist: 1; 1489 u8 exist_last: 1; 1490 u8 play_latency: 1; 1491 u8 type: 3; 1492 u8 active: 1; 1493 u8 sink: 1; 1494 u32 handle_update: 1; 1495 u32 devinfo_query: 1; 1496 u32 no_empty_streak_2s: 8; 1497 u32 no_empty_streak_max: 8; 1498 u32 rsvd: 6; 1499 1500 u8 bitpool; 1501 u16 vendor_id; 1502 u32 device_name; 1503 u32 flush_time; 1504 }; 1505 1506 struct rtw89_btc_bt_pan_desc { 1507 u32 exist: 1; 1508 u32 type: 1; 1509 u32 active: 1; 1510 u32 rsvd: 29; 1511 }; 1512 1513 struct rtw89_btc_bt_rfk_info { 1514 u32 run: 1; 1515 u32 req: 1; 1516 u32 timeout: 1; 1517 u32 rsvd: 29; 1518 }; 1519 1520 union rtw89_btc_bt_rfk_info_map { 1521 u32 val; 1522 struct rtw89_btc_bt_rfk_info map; 1523 }; 1524 1525 struct rtw89_btc_bt_ver_info { 1526 u32 fw_coex; /* match with which coex_ver */ 1527 u32 fw; 1528 }; 1529 1530 struct rtw89_btc_bool_sta_chg { 1531 u32 now: 1; 1532 u32 last: 1; 1533 u32 remain: 1; 1534 u32 srvd: 29; 1535 }; 1536 1537 struct rtw89_btc_u8_sta_chg { 1538 u8 now; 1539 u8 last; 1540 u8 remain; 1541 u8 rsvd; 1542 }; 1543 1544 struct rtw89_btc_wl_scan_info { 1545 u8 band[RTW89_PHY_NUM]; 1546 u8 phy_map; 1547 u8 rsvd; 1548 }; 1549 1550 struct rtw89_btc_wl_dbcc_info { 1551 u8 op_band[RTW89_PHY_NUM]; /* op band in each phy */ 1552 u8 scan_band[RTW89_PHY_NUM]; /* scan band in each phy */ 1553 u8 real_band[RTW89_PHY_NUM]; 1554 u8 role[RTW89_PHY_NUM]; /* role in each phy */ 1555 }; 1556 1557 struct rtw89_btc_wl_active_role { 1558 u8 connected: 1; 1559 u8 pid: 3; 1560 u8 phy: 1; 1561 u8 noa: 1; 1562 u8 band: 2; 1563 1564 u8 client_ps: 1; 1565 u8 bw: 7; 1566 1567 u8 role; 1568 u8 ch; 1569 1570 u16 tx_lvl; 1571 u16 rx_lvl; 1572 u16 tx_rate; 1573 u16 rx_rate; 1574 }; 1575 1576 struct rtw89_btc_wl_active_role_v1 { 1577 u8 connected: 1; 1578 u8 pid: 3; 1579 u8 phy: 1; 1580 u8 noa: 1; 1581 u8 band: 2; 1582 1583 u8 client_ps: 1; 1584 u8 bw: 7; 1585 1586 u8 role; 1587 u8 ch; 1588 1589 u16 tx_lvl; 1590 u16 rx_lvl; 1591 u16 tx_rate; 1592 u16 rx_rate; 1593 1594 u32 noa_duration; /* ms */ 1595 }; 1596 1597 struct rtw89_btc_wl_active_role_v2 { 1598 u8 connected: 1; 1599 u8 pid: 3; 1600 u8 phy: 1; 1601 u8 noa: 1; 1602 u8 band: 2; 1603 1604 u8 client_ps: 1; 1605 u8 bw: 7; 1606 1607 u8 role; 1608 u8 ch; 1609 1610 u32 noa_duration; /* ms */ 1611 }; 1612 1613 struct rtw89_btc_wl_active_role_v7 { 1614 u8 connected; 1615 u8 pid; 1616 u8 phy; 1617 u8 noa; 1618 1619 u8 band; 1620 u8 client_ps; 1621 u8 bw; 1622 u8 role; 1623 1624 u8 ch; 1625 u8 noa_dur; 1626 u8 client_cnt; 1627 u8 rsvd2; 1628 } __packed; 1629 1630 struct rtw89_btc_wl_role_info_bpos { 1631 u16 none: 1; 1632 u16 station: 1; 1633 u16 ap: 1; 1634 u16 vap: 1; 1635 u16 adhoc: 1; 1636 u16 adhoc_master: 1; 1637 u16 mesh: 1; 1638 u16 moniter: 1; 1639 u16 p2p_device: 1; 1640 u16 p2p_gc: 1; 1641 u16 p2p_go: 1; 1642 u16 nan: 1; 1643 }; 1644 1645 struct rtw89_btc_wl_scc_ctrl { 1646 u8 null_role1; 1647 u8 null_role2; 1648 u8 ebt_null; /* if tx null at EBT slot */ 1649 }; 1650 1651 union rtw89_btc_wl_role_info_map { 1652 u16 val; 1653 struct rtw89_btc_wl_role_info_bpos role; 1654 }; 1655 1656 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1657 u8 connect_cnt; 1658 u8 link_mode; 1659 union rtw89_btc_wl_role_info_map role_map; 1660 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1661 }; 1662 1663 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1664 u8 connect_cnt; 1665 u8 link_mode; 1666 union rtw89_btc_wl_role_info_map role_map; 1667 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1668 u32 mrole_type; /* btc_wl_mrole_type */ 1669 u32 mrole_noa_duration; /* ms */ 1670 1671 u32 dbcc_en: 1; 1672 u32 dbcc_chg: 1; 1673 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1674 u32 link_mode_chg: 1; 1675 u32 rsvd: 27; 1676 }; 1677 1678 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1679 u8 connect_cnt; 1680 u8 link_mode; 1681 union rtw89_btc_wl_role_info_map role_map; 1682 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1683 u32 mrole_type; /* btc_wl_mrole_type */ 1684 u32 mrole_noa_duration; /* ms */ 1685 1686 u32 dbcc_en: 1; 1687 u32 dbcc_chg: 1; 1688 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1689 u32 link_mode_chg: 1; 1690 u32 rsvd: 27; 1691 }; 1692 1693 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1694 u8 connected; 1695 u8 pid; 1696 u8 phy; 1697 u8 noa; 1698 1699 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1700 u8 active; /* 0:rlink is under doze */ 1701 u8 bw; /* enum channel_width */ 1702 u8 role; /*enum role_type */ 1703 1704 u8 ch; 1705 u8 noa_dur; /* ms */ 1706 u8 client_cnt; /* for Role = P2P-Go/AP */ 1707 u8 mode; /* wifi protocol */ 1708 } __packed; 1709 1710 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1711 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1712 u8 connect_cnt; 1713 u8 link_mode; 1714 u8 link_mode_chg; 1715 u8 p2p_2g; 1716 1717 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1718 1719 u32 role_map; 1720 u32 mrole_type; /* btc_wl_mrole_type */ 1721 u32 mrole_noa_duration; /* ms */ 1722 u32 dbcc_en; 1723 u32 dbcc_chg; 1724 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1725 } __packed; 1726 1727 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1728 u8 connect_cnt; 1729 u8 link_mode; 1730 u8 link_mode_chg; 1731 u8 p2p_2g; 1732 1733 u8 pta_req_band; 1734 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1735 u8 dbcc_chg; 1736 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1737 1738 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1739 1740 u32 role_map; 1741 u32 mrole_type; /* btc_wl_mrole_type */ 1742 u32 mrole_noa_duration; /* ms */ 1743 } __packed; 1744 1745 struct rtw89_btc_wl_ver_info { 1746 u32 fw_coex; /* match with which coex_ver */ 1747 u32 fw; 1748 u32 mac; 1749 u32 bb; 1750 u32 rf; 1751 }; 1752 1753 struct rtw89_btc_wl_afh_info { 1754 u8 en; 1755 u8 ch; 1756 u8 bw; 1757 u8 rsvd; 1758 } __packed; 1759 1760 struct rtw89_btc_wl_rfk_info { 1761 u32 state: 2; 1762 u32 path_map: 4; 1763 u32 phy_map: 2; 1764 u32 band: 2; 1765 u32 type: 8; 1766 u32 con_rfk: 1; 1767 u32 rsvd: 13; 1768 1769 u32 start_time; 1770 u32 proc_time; 1771 }; 1772 1773 struct rtw89_btc_bt_smap { 1774 u32 connect: 1; 1775 u32 ble_connect: 1; 1776 u32 acl_busy: 1; 1777 u32 sco_busy: 1; 1778 u32 mesh_busy: 1; 1779 u32 inq_pag: 1; 1780 }; 1781 1782 union rtw89_btc_bt_state_map { 1783 u32 val; 1784 struct rtw89_btc_bt_smap map; 1785 }; 1786 1787 #define BTC_BT_RSSI_THMAX 4 1788 #define BTC_BT_AFH_GROUP 12 1789 #define BTC_BT_AFH_LE_GROUP 5 1790 1791 struct rtw89_btc_bt_link_info { 1792 struct rtw89_btc_u8_sta_chg profile_cnt; 1793 struct rtw89_btc_bool_sta_chg multi_link; 1794 struct rtw89_btc_bool_sta_chg relink; 1795 struct rtw89_btc_bt_hfp_desc hfp_desc; 1796 struct rtw89_btc_bt_hid_desc hid_desc; 1797 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1798 struct rtw89_btc_bt_pan_desc pan_desc; 1799 union rtw89_btc_bt_state_map status; 1800 1801 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1802 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1803 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1804 u8 afh_map[BTC_BT_AFH_GROUP]; 1805 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1806 1807 u32 role_sw: 1; 1808 u32 slave_role: 1; 1809 u32 afh_update: 1; 1810 u32 cqddr: 1; 1811 u32 rssi: 8; 1812 u32 tx_3m: 1; 1813 u32 rsvd: 19; 1814 }; 1815 1816 struct rtw89_btc_3rdcx_info { 1817 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1818 u8 hw_coex; 1819 u16 rsvd; 1820 }; 1821 1822 struct rtw89_btc_dm_emap { 1823 u32 init: 1; 1824 u32 pta_owner: 1; 1825 u32 wl_rfk_timeout: 1; 1826 u32 bt_rfk_timeout: 1; 1827 u32 wl_fw_hang: 1; 1828 u32 cycle_hang: 1; 1829 u32 w1_hang: 1; 1830 u32 b1_hang: 1; 1831 u32 tdma_no_sync: 1; 1832 u32 slot_no_sync: 1; 1833 u32 wl_slot_drift: 1; 1834 u32 bt_slot_drift: 1; 1835 u32 role_num_mismatch: 1; 1836 u32 null1_tx_late: 1; 1837 u32 bt_afh_conflict: 1; 1838 u32 bt_leafh_conflict: 1; 1839 u32 bt_slot_flood: 1; 1840 u32 wl_e2g_hang: 1; 1841 u32 wl_ver_mismatch: 1; 1842 u32 bt_ver_mismatch: 1; 1843 u32 rfe_type0: 1; 1844 u32 h2c_buffer_over: 1; 1845 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1846 u32 wl_no_sta_ntfy: 1; 1847 1848 u32 h2c_bmap_mismatch: 1; 1849 u32 c2h_bmap_mismatch: 1; 1850 u32 h2c_struct_invalid: 1; 1851 u32 c2h_struct_invalid: 1; 1852 u32 h2c_c2h_buffer_mismatch: 1; 1853 }; 1854 1855 union rtw89_btc_dm_error_map { 1856 u32 val; 1857 struct rtw89_btc_dm_emap map; 1858 }; 1859 1860 struct rtw89_btc_rf_para { 1861 u32 tx_pwr_freerun; 1862 u32 rx_gain_freerun; 1863 u32 tx_pwr_perpkt; 1864 u32 rx_gain_perpkt; 1865 }; 1866 1867 struct rtw89_btc_wl_nhm { 1868 u8 instant_wl_nhm_dbm; 1869 u8 instant_wl_nhm_per_mhz; 1870 u16 valid_record_times; 1871 s8 record_pwr[16]; 1872 u8 record_ratio[16]; 1873 s8 pwr; /* dbm_per_MHz */ 1874 u8 ratio; 1875 u8 current_status; 1876 u8 refresh; 1877 bool start_flag; 1878 s8 pwr_max; 1879 s8 pwr_min; 1880 }; 1881 1882 struct rtw89_btc_wl_info { 1883 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1884 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1885 struct rtw89_btc_wl_rfk_info rfk_info; 1886 struct rtw89_btc_wl_ver_info ver_info; 1887 struct rtw89_btc_wl_afh_info afh_info; 1888 struct rtw89_btc_wl_role_info role_info; 1889 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1890 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1891 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1892 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1893 struct rtw89_btc_wl_scan_info scan_info; 1894 struct rtw89_btc_wl_dbcc_info dbcc_info; 1895 struct rtw89_btc_rf_para rf_para; 1896 struct rtw89_btc_wl_nhm nhm; 1897 union rtw89_btc_wl_state_map status; 1898 1899 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1900 u8 rssi_level; 1901 u8 cn_report; 1902 u8 coex_mode; 1903 u8 pta_req_mac; 1904 u8 bt_polut_type[RTW89_PHY_NUM]; /* BT polluted WL-Tx type for phy0/1 */ 1905 1906 bool is_5g_hi_channel; 1907 bool pta_reg_mac_chg; 1908 bool bg_mode; 1909 bool he_mode; 1910 bool scbd_change; 1911 bool fw_ver_mismatch; 1912 bool client_cnt_inc_2g; 1913 u32 scbd; 1914 }; 1915 1916 struct rtw89_btc_module { 1917 struct rtw89_btc_ant_info ant; 1918 u8 rfe_type; 1919 u8 cv; 1920 1921 u8 bt_solo: 1; 1922 u8 bt_pos: 1; 1923 u8 switch_type: 1; 1924 u8 wa_type: 3; 1925 1926 u8 kt_ver_adie; 1927 }; 1928 1929 struct rtw89_btc_module_v7 { 1930 u8 rfe_type; 1931 u8 kt_ver; 1932 u8 bt_solo; 1933 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1934 1935 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1936 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1937 u8 kt_ver_adie; 1938 u8 rsvd; 1939 1940 struct rtw89_btc_ant_info_v7 ant; 1941 } __packed; 1942 1943 union rtw89_btc_module_info { 1944 struct rtw89_btc_module md; 1945 struct rtw89_btc_module_v7 md_v7; 1946 }; 1947 1948 #define RTW89_BTC_DM_MAXSTEP 30 1949 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1950 1951 struct rtw89_btc_dm_step { 1952 u16 step[RTW89_BTC_DM_MAXSTEP]; 1953 u8 step_pos; 1954 bool step_ov; 1955 }; 1956 1957 struct rtw89_btc_init_info { 1958 struct rtw89_btc_module module; 1959 u8 wl_guard_ch; 1960 1961 u8 wl_only: 1; 1962 u8 wl_init_ok: 1; 1963 u8 dbcc_en: 1; 1964 u8 cx_other: 1; 1965 u8 bt_only: 1; 1966 1967 u16 rsvd; 1968 }; 1969 1970 struct rtw89_btc_init_info_v7 { 1971 u8 wl_guard_ch; 1972 u8 wl_only; 1973 u8 wl_init_ok; 1974 u8 rsvd3; 1975 1976 u8 cx_other; 1977 u8 bt_only; 1978 u8 pta_mode; 1979 u8 pta_direction; 1980 1981 struct rtw89_btc_module_v7 module; 1982 } __packed; 1983 1984 union rtw89_btc_init_info_u { 1985 struct rtw89_btc_init_info init; 1986 struct rtw89_btc_init_info_v7 init_v7; 1987 }; 1988 1989 struct rtw89_btc_wl_tx_limit_para { 1990 u16 enable; 1991 u32 tx_time; /* unit: us */ 1992 u16 tx_retry; 1993 }; 1994 1995 enum rtw89_btc_bt_scan_type { 1996 BTC_SCAN_INQ = 0, 1997 BTC_SCAN_PAGE, 1998 BTC_SCAN_BLE, 1999 BTC_SCAN_INIT, 2000 BTC_SCAN_TV, 2001 BTC_SCAN_ADV, 2002 BTC_SCAN_MAX1, 2003 }; 2004 2005 enum rtw89_btc_ble_scan_type { 2006 CXSCAN_BG = 0, 2007 CXSCAN_INIT, 2008 CXSCAN_LE, 2009 CXSCAN_MAX 2010 }; 2011 2012 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2013 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2014 2015 struct rtw89_btc_bt_scan_info_v1 { 2016 __le16 win; 2017 __le16 intvl; 2018 __le32 flags; 2019 } __packed; 2020 2021 struct rtw89_btc_bt_scan_info_v2 { 2022 __le16 win; 2023 __le16 intvl; 2024 } __packed; 2025 2026 struct rtw89_btc_fbtc_btscan_v1 { 2027 u8 fver; /* btc_ver::fcxbtscan */ 2028 u8 rsvd; 2029 __le16 rsvd2; 2030 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2031 } __packed; 2032 2033 struct rtw89_btc_fbtc_btscan_v2 { 2034 u8 fver; /* btc_ver::fcxbtscan */ 2035 u8 type; 2036 __le16 rsvd2; 2037 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2038 } __packed; 2039 2040 struct rtw89_btc_fbtc_btscan_v7 { 2041 u8 fver; /* btc_ver::fcxbtscan */ 2042 u8 type; 2043 u8 rsvd0; 2044 u8 rsvd1; 2045 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2046 } __packed; 2047 2048 union rtw89_btc_fbtc_btscan { 2049 struct rtw89_btc_fbtc_btscan_v1 v1; 2050 struct rtw89_btc_fbtc_btscan_v2 v2; 2051 struct rtw89_btc_fbtc_btscan_v7 v7; 2052 }; 2053 2054 struct rtw89_btc_bt_info { 2055 struct rtw89_btc_bt_link_info link_info; 2056 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2057 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2058 struct rtw89_btc_bt_ver_info ver_info; 2059 struct rtw89_btc_bool_sta_chg enable; 2060 struct rtw89_btc_bool_sta_chg inq_pag; 2061 struct rtw89_btc_rf_para rf_para; 2062 union rtw89_btc_bt_rfk_info_map rfk_info; 2063 2064 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2065 u8 rssi_level; 2066 2067 u32 scbd; 2068 u32 feature; 2069 2070 u32 mbx_avl: 1; 2071 u32 whql_test: 1; 2072 u32 igno_wl: 1; 2073 u32 reinit: 1; 2074 u32 ble_scan_en: 1; 2075 u32 btg_type: 1; 2076 u32 inq: 1; 2077 u32 pag: 1; 2078 u32 run_patch_code: 1; 2079 u32 hi_lna_rx: 1; 2080 u32 scan_rx_low_pri: 1; 2081 u32 scan_info_update: 1; 2082 u32 lna_constrain: 3; 2083 u32 rsvd: 17; 2084 }; 2085 2086 struct rtw89_btc_cx { 2087 struct rtw89_btc_wl_info wl; 2088 struct rtw89_btc_bt_info bt; 2089 struct rtw89_btc_3rdcx_info other; 2090 u32 state_map; 2091 u32 cnt_bt[BTC_BCNT_NUM]; 2092 u32 cnt_wl[BTC_WCNT_NUM]; 2093 }; 2094 2095 struct rtw89_btc_fbtc_tdma { 2096 u8 type; /* btc_ver::fcxtdma */ 2097 u8 rxflctrl; 2098 u8 txpause; 2099 u8 wtgle_n; 2100 u8 leak_n; 2101 u8 ext_ctrl; 2102 u8 rxflctrl_role; 2103 u8 option_ctrl; 2104 } __packed; 2105 2106 struct rtw89_btc_fbtc_tdma_v3 { 2107 u8 fver; /* btc_ver::fcxtdma */ 2108 u8 rsvd; 2109 __le16 rsvd1; 2110 struct rtw89_btc_fbtc_tdma tdma; 2111 } __packed; 2112 2113 union rtw89_btc_fbtc_tdma_le32 { 2114 struct rtw89_btc_fbtc_tdma v1; 2115 struct rtw89_btc_fbtc_tdma_v3 v3; 2116 }; 2117 2118 #define CXMREG_MAX 30 2119 #define CXMREG_MAX_V2 20 2120 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2121 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2122 2123 enum rtw89_btc_bt_sta_counter { 2124 BTC_BCNT_RFK_REQ = 0, 2125 BTC_BCNT_RFK_GO = 1, 2126 BTC_BCNT_RFK_REJECT = 2, 2127 BTC_BCNT_RFK_FAIL = 3, 2128 BTC_BCNT_RFK_TIMEOUT = 4, 2129 BTC_BCNT_HI_TX = 5, 2130 BTC_BCNT_HI_RX = 6, 2131 BTC_BCNT_LO_TX = 7, 2132 BTC_BCNT_LO_RX = 8, 2133 BTC_BCNT_POLLUTED = 9, 2134 BTC_BCNT_STA_MAX 2135 }; 2136 2137 enum rtw89_btc_bt_sta_counter_v105 { 2138 BTC_BCNT_RFK_REQ_V105 = 0, 2139 BTC_BCNT_HI_TX_V105 = 1, 2140 BTC_BCNT_HI_RX_V105 = 2, 2141 BTC_BCNT_LO_TX_V105 = 3, 2142 BTC_BCNT_LO_RX_V105 = 4, 2143 BTC_BCNT_POLLUTED_V105 = 5, 2144 BTC_BCNT_STA_MAX_V105 2145 }; 2146 2147 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2148 u16 fver; /* btc_ver::fcxbtcrpt */ 2149 u16 rpt_cnt; /* tmr counters */ 2150 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2151 u32 wl_fw_cx_offload; 2152 u32 wl_fw_ver; 2153 u32 rpt_enable; 2154 u32 rpt_para; /* ms */ 2155 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2156 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2157 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2158 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2159 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2160 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2161 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2162 u32 c2h_cnt; /* fw send c2h counter */ 2163 u32 h2c_cnt; /* fw recv h2c counter */ 2164 } __packed; 2165 2166 struct rtw89_btc_fbtc_rpt_ctrl_info { 2167 __le32 cnt; /* fw report counter */ 2168 __le32 en; /* report map */ 2169 __le32 para; /* not used */ 2170 2171 __le32 cnt_c2h; /* fw send c2h counter */ 2172 __le32 cnt_h2c; /* fw recv h2c counter */ 2173 __le32 len_c2h; /* The total length of the last C2H */ 2174 2175 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2176 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2177 } __packed; 2178 2179 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2180 __le32 cx_ver; /* match which driver's coex version */ 2181 __le32 fw_ver; 2182 __le32 en; /* report map */ 2183 2184 __le16 cnt; /* fw report counter */ 2185 __le16 cnt_c2h; /* fw send c2h counter */ 2186 __le16 cnt_h2c; /* fw recv h2c counter */ 2187 __le16 len_c2h; /* The total length of the last C2H */ 2188 2189 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2190 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2191 } __packed; 2192 2193 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2194 __le16 cnt; /* fw report counter */ 2195 __le16 cnt_c2h; /* fw send c2h counter */ 2196 __le16 cnt_h2c; /* fw recv h2c counter */ 2197 __le16 len_c2h; /* The total length of the last C2H */ 2198 2199 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2200 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2201 2202 __le32 cx_ver; /* match which driver's coex version */ 2203 __le32 fw_ver; 2204 __le32 en; /* report map */ 2205 } __packed; 2206 2207 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2208 __le32 cx_ver; /* match which driver's coex version */ 2209 __le32 cx_offload; 2210 __le32 fw_ver; 2211 } __packed; 2212 2213 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2214 __le32 cnt_empty; /* a2dp empty count */ 2215 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2216 __le32 cnt_tx; 2217 __le32 cnt_ack; 2218 __le32 cnt_nack; 2219 } __packed; 2220 2221 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2222 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2223 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2224 __le32 cnt_recv; /* fw recv mailbox counter */ 2225 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2226 } __packed; 2227 2228 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2229 u8 fver; 2230 u8 rsvd; 2231 __le16 rsvd1; 2232 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2233 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2234 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2235 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2236 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_NUM]; 2237 } __packed; 2238 2239 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2240 u8 fver; 2241 u8 rsvd; 2242 __le16 rsvd1; 2243 2244 u8 gnt_val[RTW89_PHY_NUM][4]; 2245 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2246 2247 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2248 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2249 } __packed; 2250 2251 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2252 u8 fver; 2253 u8 rsvd; 2254 __le16 rsvd1; 2255 2256 u8 gnt_val[RTW89_PHY_NUM][4]; 2257 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2258 2259 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2260 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2261 } __packed; 2262 2263 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2264 u8 fver; 2265 u8 rsvd0; 2266 u8 rsvd1; 2267 u8 rsvd2; 2268 2269 u8 gnt_val[RTW89_PHY_NUM][4]; 2270 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2271 2272 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2273 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2274 } __packed; 2275 2276 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2277 u8 fver; 2278 u8 rsvd0; 2279 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2280 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2281 2282 u8 gnt_val[RTW89_PHY_NUM][4]; 2283 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2284 2285 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2286 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2287 } __packed; 2288 2289 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2290 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2291 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2292 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2293 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2294 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2295 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2296 }; 2297 2298 enum rtw89_fbtc_ext_ctrl_type { 2299 CXECTL_OFF = 0x0, /* tdma off */ 2300 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2301 CXECTL_EXT = 0x2, 2302 CXECTL_MAX 2303 }; 2304 2305 union rtw89_btc_fbtc_rxflct { 2306 u8 val; 2307 u8 type: 3; 2308 u8 tgln_n: 5; 2309 }; 2310 2311 enum rtw89_btc_cxst_state { 2312 CXST_OFF = 0x0, 2313 CXST_B2W = 0x1, 2314 CXST_W1 = 0x2, 2315 CXST_W2 = 0x3, 2316 CXST_W2B = 0x4, 2317 CXST_B1 = 0x5, 2318 CXST_B2 = 0x6, 2319 CXST_B3 = 0x7, 2320 CXST_B4 = 0x8, 2321 CXST_LK = 0x9, 2322 CXST_BLK = 0xa, 2323 CXST_E2G = 0xb, 2324 CXST_E5G = 0xc, 2325 CXST_EBT = 0xd, 2326 CXST_ENULL = 0xe, 2327 CXST_WLK = 0xf, 2328 CXST_W1FDD = 0x10, 2329 CXST_B1FDD = 0x11, 2330 CXST_MAX = 0x12, 2331 }; 2332 2333 enum rtw89_btc_cxevnt { 2334 CXEVNT_TDMA_ENTRY = 0x0, 2335 CXEVNT_WL_TMR, 2336 CXEVNT_B1_TMR, 2337 CXEVNT_B2_TMR, 2338 CXEVNT_B3_TMR, 2339 CXEVNT_B4_TMR, 2340 CXEVNT_W2B_TMR, 2341 CXEVNT_B2W_TMR, 2342 CXEVNT_BCN_EARLY, 2343 CXEVNT_A2DP_EMPTY, 2344 CXEVNT_LK_END, 2345 CXEVNT_RX_ISR, 2346 CXEVNT_RX_FC0, 2347 CXEVNT_RX_FC1, 2348 CXEVNT_BT_RELINK, 2349 CXEVNT_BT_RETRY, 2350 CXEVNT_E2G, 2351 CXEVNT_E5G, 2352 CXEVNT_EBT, 2353 CXEVNT_ENULL, 2354 CXEVNT_DRV_WLK, 2355 CXEVNT_BCN_OK, 2356 CXEVNT_BT_CHANGE, 2357 CXEVNT_EBT_EXTEND, 2358 CXEVNT_E2G_NULL1, 2359 CXEVNT_B1FDD_TMR, 2360 CXEVNT_MAX 2361 }; 2362 2363 enum { 2364 CXBCN_ALL = 0x0, 2365 CXBCN_ALL_OK, 2366 CXBCN_BT_SLOT, 2367 CXBCN_BT_OK, 2368 CXBCN_MAX 2369 }; 2370 2371 enum btc_slot_type { 2372 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2373 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2374 CXSTYPE_NUM, 2375 }; 2376 2377 enum { /* TIME */ 2378 CXT_BT = 0x0, 2379 CXT_WL = 0x1, 2380 CXT_MAX 2381 }; 2382 2383 enum { /* TIME-A2DP */ 2384 CXT_FLCTRL_OFF = 0x0, 2385 CXT_FLCTRL_ON = 0x1, 2386 CXT_FLCTRL_MAX 2387 }; 2388 2389 enum { /* STEP TYPE */ 2390 CXSTEP_NONE = 0x0, 2391 CXSTEP_EVNT = 0x1, 2392 CXSTEP_SLOT = 0x2, 2393 CXSTEP_MAX, 2394 }; 2395 2396 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2397 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2398 RPT_BT_AFH_SEQ_LE = 0x20 2399 }; 2400 2401 #define BTC_DBG_MAX1 32 2402 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2403 u8 fver; /* btc_ver::fcxgpiodbg */ 2404 u8 rsvd; 2405 __le16 rsvd2; 2406 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2407 __le32 pre_state; /* the debug signal is 1 or 0 */ 2408 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2409 } __packed; 2410 2411 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2412 u8 fver; 2413 u8 rsvd0; 2414 u8 rsvd1; 2415 u8 rsvd2; 2416 2417 u8 gpio_map[BTC_DBG_MAX1]; 2418 2419 __le32 en_map; 2420 __le32 pre_state; 2421 } __packed; 2422 2423 union rtw89_btc_fbtc_gpio_dbg { 2424 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2425 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2426 }; 2427 2428 struct rtw89_btc_fbtc_mreg_val_v1 { 2429 u8 fver; /* btc_ver::fcxmreg */ 2430 u8 reg_num; 2431 __le16 rsvd; 2432 __le32 mreg_val[CXMREG_MAX]; 2433 } __packed; 2434 2435 struct rtw89_btc_fbtc_mreg_val_v2 { 2436 u8 fver; /* btc_ver::fcxmreg */ 2437 u8 reg_num; 2438 __le16 rsvd; 2439 __le32 mreg_val[CXMREG_MAX_V2]; 2440 } __packed; 2441 2442 struct rtw89_btc_fbtc_mreg_val_v7 { 2443 u8 fver; 2444 u8 reg_num; 2445 u8 rsvd0; 2446 u8 rsvd1; 2447 __le32 mreg_val[CXMREG_MAX_V2]; 2448 } __packed; 2449 2450 union rtw89_btc_fbtc_mreg_val { 2451 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2452 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2453 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2454 }; 2455 2456 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2457 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2458 .offset = cpu_to_le32(__offset), } 2459 2460 struct rtw89_btc_fbtc_mreg { 2461 __le16 type; 2462 __le16 bytes; 2463 __le32 offset; 2464 } __packed; 2465 2466 struct rtw89_btc_fbtc_slot { 2467 __le16 dur; 2468 __le32 cxtbl; 2469 __le16 cxtype; 2470 } __packed; 2471 2472 struct rtw89_btc_fbtc_slots { 2473 u8 fver; /* btc_ver::fcxslots */ 2474 u8 tbl_num; 2475 __le16 rsvd; 2476 __le32 update_map; 2477 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2478 } __packed; 2479 2480 struct rtw89_btc_fbtc_slot_v7 { 2481 __le16 dur; /* slot duration */ 2482 __le16 cxtype; 2483 __le32 cxtbl; 2484 } __packed; 2485 2486 struct rtw89_btc_fbtc_slot_u16 { 2487 __le16 dur; /* slot duration */ 2488 __le16 cxtype; 2489 __le16 cxtbl_l16; /* coex table [15:0] */ 2490 __le16 cxtbl_h16; /* coex table [31:16] */ 2491 } __packed; 2492 2493 struct rtw89_btc_fbtc_1slot_v7 { 2494 u8 fver; 2495 u8 sid; /* slot id */ 2496 __le16 rsvd; 2497 struct rtw89_btc_fbtc_slot_v7 slot; 2498 } __packed; 2499 2500 struct rtw89_btc_fbtc_slots_v7 { 2501 u8 fver; 2502 u8 slot_cnt; 2503 u8 rsvd0; 2504 u8 rsvd1; 2505 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2506 __le32 update_map; 2507 } __packed; 2508 2509 union rtw89_btc_fbtc_slots_info { 2510 struct rtw89_btc_fbtc_slots v1; 2511 struct rtw89_btc_fbtc_slots_v7 v7; 2512 } __packed; 2513 2514 struct rtw89_btc_fbtc_step { 2515 u8 type; 2516 u8 val; 2517 __le16 difft; 2518 } __packed; 2519 2520 struct rtw89_btc_fbtc_steps_v2 { 2521 u8 fver; /* btc_ver::fcxstep */ 2522 u8 rsvd; 2523 __le16 cnt; 2524 __le16 pos_old; 2525 __le16 pos_new; 2526 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2527 } __packed; 2528 2529 struct rtw89_btc_fbtc_steps_v3 { 2530 u8 fver; 2531 u8 en; 2532 __le16 rsvd; 2533 __le32 cnt; 2534 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2535 } __packed; 2536 2537 union rtw89_btc_fbtc_steps_info { 2538 struct rtw89_btc_fbtc_steps_v2 v2; 2539 struct rtw89_btc_fbtc_steps_v3 v3; 2540 }; 2541 2542 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2543 u8 fver; /* btc_ver::fcxcysta */ 2544 u8 rsvd; 2545 __le16 cycles; /* total cycle number */ 2546 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2547 __le16 a2dpept; /* a2dp empty cnt */ 2548 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2549 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2550 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2551 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2552 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2553 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2554 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2555 __le16 tmax_a2dpept; /* max a2dp empty time */ 2556 __le16 tavg_lk; /* avg leak-slot time */ 2557 __le16 tmax_lk; /* max leak-slot time */ 2558 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2559 __le32 bcn_cnt[CXBCN_MAX]; 2560 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2561 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2562 __le32 skip_cnt; 2563 __le32 exception; 2564 __le32 except_cnt; 2565 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2566 } __packed; 2567 2568 struct rtw89_btc_fbtc_fdd_try_info { 2569 __le16 cycles[CXT_FLCTRL_MAX]; 2570 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2571 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2572 } __packed; 2573 2574 struct rtw89_btc_fbtc_cycle_time_info { 2575 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2576 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2577 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2578 } __packed; 2579 2580 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2581 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2582 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2583 } __packed; 2584 2585 struct rtw89_btc_fbtc_a2dp_trx_stat { 2586 u8 empty_cnt; 2587 u8 retry_cnt; 2588 u8 tx_rate; 2589 u8 tx_cnt; 2590 u8 ack_cnt; 2591 u8 nack_cnt; 2592 u8 rsvd1; 2593 u8 rsvd2; 2594 } __packed; 2595 2596 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2597 u8 empty_cnt; 2598 u8 retry_cnt; 2599 u8 tx_rate; 2600 u8 tx_cnt; 2601 u8 ack_cnt; 2602 u8 nack_cnt; 2603 u8 no_empty_cnt; 2604 u8 rsvd; 2605 } __packed; 2606 2607 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2608 __le16 cnt; /* a2dp empty cnt */ 2609 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2610 __le16 tavg; /* avg a2dp empty time */ 2611 __le16 tmax; /* max a2dp empty time */ 2612 } __packed; 2613 2614 struct rtw89_btc_fbtc_cycle_leak_info { 2615 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2616 __le16 tavg; /* avg leak-slot time */ 2617 __le16 tmax; /* max leak-slot time */ 2618 } __packed; 2619 2620 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2621 __le16 tavg; 2622 __le16 tamx; 2623 __le32 cnt_rximr; 2624 } __packed; 2625 2626 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2627 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2628 2629 struct rtw89_btc_fbtc_cycle_fddt_info { 2630 __le16 train_cycle; 2631 __le16 tp; 2632 2633 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2634 s8 bt_tx_power; /* decrease Tx power (dB) */ 2635 s8 bt_rx_gain; /* LNA constrain level */ 2636 u8 no_empty_cnt; 2637 2638 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2639 u8 cn; /* condition_num */ 2640 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2641 u8 train_result; /* refer to enum btc_fddt_check_map */ 2642 } __packed; 2643 2644 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2645 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2646 2647 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2648 __le16 train_cycle; 2649 __le16 tp; 2650 2651 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2652 s8 bt_tx_power; /* decrease Tx power (dB) */ 2653 s8 bt_rx_gain; /* LNA constrain level */ 2654 u8 no_empty_cnt; 2655 2656 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2657 u8 cn; /* condition_num */ 2658 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2659 u8 train_result; /* refer to enum btc_fddt_check_map */ 2660 } __packed; 2661 2662 struct rtw89_btc_fbtc_fddt_cell_status { 2663 s8 wl_tx_pwr; 2664 s8 bt_tx_pwr; 2665 s8 bt_rx_gain; 2666 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2667 } __packed; 2668 2669 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2670 u8 fver; 2671 u8 rsvd; 2672 __le16 cycles; /* total cycle number */ 2673 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2674 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2675 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2676 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2677 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2678 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2679 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2680 __le32 bcn_cnt[CXBCN_MAX]; 2681 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2682 __le32 skip_cnt; 2683 __le32 except_cnt; 2684 __le32 except_map; 2685 } __packed; 2686 2687 #define FDD_TRAIN_WL_DIRECTION 2 2688 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2689 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2690 2691 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2692 u8 fver; 2693 u8 rsvd; 2694 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2695 u8 except_cnt; 2696 2697 __le16 skip_cnt; 2698 __le16 cycles; /* total cycle number */ 2699 2700 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2701 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2702 __le16 bcn_cnt[CXBCN_MAX]; 2703 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2704 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2705 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2706 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2707 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2708 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2709 [FDD_TRAIN_WL_RSSI_LEVEL] 2710 [FDD_TRAIN_BT_RSSI_LEVEL]; 2711 __le32 except_map; 2712 } __packed; 2713 2714 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2715 u8 fver; 2716 u8 rsvd; 2717 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2718 u8 except_cnt; 2719 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2720 2721 __le16 skip_cnt; 2722 __le16 cycles; /* total cycle number */ 2723 2724 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2725 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2726 __le16 bcn_cnt[CXBCN_MAX]; 2727 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2728 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2729 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2730 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2731 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2732 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2733 [FDD_TRAIN_WL_RSSI_LEVEL] 2734 [FDD_TRAIN_BT_RSSI_LEVEL]; 2735 __le32 except_map; 2736 } __packed; 2737 2738 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2739 u8 fver; 2740 u8 rsvd; 2741 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2742 u8 except_cnt; 2743 2744 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2745 2746 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2747 2748 __le16 skip_cnt; 2749 __le16 cycles; /* total cycle number */ 2750 2751 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2752 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2753 __le16 bcn_cnt[CXBCN_MAX]; 2754 2755 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2756 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2757 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2758 2759 __le32 except_map; 2760 } __packed; 2761 2762 union rtw89_btc_fbtc_cysta_info { 2763 struct rtw89_btc_fbtc_cysta_v2 v2; 2764 struct rtw89_btc_fbtc_cysta_v3 v3; 2765 struct rtw89_btc_fbtc_cysta_v4 v4; 2766 struct rtw89_btc_fbtc_cysta_v5 v5; 2767 struct rtw89_btc_fbtc_cysta_v7 v7; 2768 }; 2769 2770 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2771 u8 fver; /* btc_ver::fcxnullsta */ 2772 u8 rsvd; 2773 __le16 rsvd2; 2774 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2775 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2776 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2777 } __packed; 2778 2779 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2780 u8 fver; /* btc_ver::fcxnullsta */ 2781 u8 rsvd; 2782 __le16 rsvd2; 2783 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2784 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2785 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2786 } __packed; 2787 2788 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2789 u8 fver; 2790 u8 rsvd0; 2791 u8 rsvd1; 2792 u8 rsvd2; 2793 2794 __le32 tmax[2]; 2795 __le32 tavg[2]; 2796 __le32 result[2][5]; 2797 } __packed; 2798 2799 union rtw89_btc_fbtc_cynullsta_info { 2800 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2801 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2802 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2803 }; 2804 2805 struct rtw89_btc_fbtc_btver_v1 { 2806 u8 fver; /* btc_ver::fcxbtver */ 2807 u8 rsvd; 2808 __le16 rsvd2; 2809 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2810 __le32 fw_ver; 2811 __le32 feature; 2812 } __packed; 2813 2814 struct rtw89_btc_fbtc_btver_v7 { 2815 u8 fver; 2816 u8 rsvd0; 2817 u8 rsvd1; 2818 u8 rsvd2; 2819 2820 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2821 __le32 fw_ver; 2822 __le32 feature; 2823 } __packed; 2824 2825 union rtw89_btc_fbtc_btver { 2826 struct rtw89_btc_fbtc_btver_v1 v1; 2827 struct rtw89_btc_fbtc_btver_v7 v7; 2828 } __packed; 2829 2830 struct rtw89_btc_fbtc_btafh { 2831 u8 fver; /* btc_ver::fcxbtafh */ 2832 u8 rsvd; 2833 __le16 rsvd2; 2834 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2835 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2836 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2837 } __packed; 2838 2839 struct rtw89_btc_fbtc_btafh_v2 { 2840 u8 fver; /* btc_ver::fcxbtafh */ 2841 u8 rsvd; 2842 u8 rsvd2; 2843 u8 map_type; 2844 u8 afh_l[4]; 2845 u8 afh_m[4]; 2846 u8 afh_h[4]; 2847 u8 afh_le_a[4]; 2848 u8 afh_le_b[4]; 2849 } __packed; 2850 2851 struct rtw89_btc_fbtc_btafh_v7 { 2852 u8 fver; 2853 u8 map_type; 2854 u8 rsvd0; 2855 u8 rsvd1; 2856 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2857 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2858 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2859 u8 afh_le_a[4]; 2860 u8 afh_le_b[4]; 2861 } __packed; 2862 2863 struct rtw89_btc_fbtc_btdevinfo { 2864 u8 fver; /* btc_ver::fcxbtdevinfo */ 2865 u8 rsvd; 2866 __le16 vendor_id; 2867 __le32 dev_name; /* only 24 bits valid */ 2868 __le32 flush_time; 2869 } __packed; 2870 2871 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2872 struct rtw89_btc_rf_trx_para { 2873 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2874 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2875 u8 bt_tx_power; /* decrease Tx power (dB) */ 2876 u8 bt_rx_gain; /* LNA constrain level */ 2877 }; 2878 2879 struct rtw89_btc_trx_info { 2880 u8 tx_lvl; 2881 u8 rx_lvl; 2882 u8 wl_rssi; 2883 u8 bt_rssi; 2884 2885 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2886 s8 rx_gain; /* rx gain table index (TBD.) */ 2887 s8 bt_tx_power; /* decrease Tx power (dB) */ 2888 s8 bt_rx_gain; /* LNA constrain level */ 2889 2890 u8 cn; /* condition_num */ 2891 s8 nhm; 2892 u8 bt_profile; 2893 u8 rsvd2; 2894 2895 u16 tx_rate; 2896 u16 rx_rate; 2897 2898 u32 tx_tp; 2899 u32 rx_tp; 2900 u32 rx_err_ratio; 2901 }; 2902 2903 union rtw89_btc_fbtc_slot_u { 2904 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2905 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2906 }; 2907 2908 struct rtw89_btc_dm { 2909 union rtw89_btc_fbtc_slot_u slot; 2910 union rtw89_btc_fbtc_slot_u slot_now; 2911 struct rtw89_btc_fbtc_tdma tdma; 2912 struct rtw89_btc_fbtc_tdma tdma_now; 2913 struct rtw89_mac_ax_coex_gnt gnt; 2914 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2915 struct rtw89_btc_rf_trx_para rf_trx_para; 2916 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2917 struct rtw89_btc_dm_step dm_step; 2918 struct rtw89_btc_wl_scc_ctrl wl_scc; 2919 struct rtw89_btc_trx_info trx_info; 2920 union rtw89_btc_dm_error_map error; 2921 u32 cnt_dm[BTC_DCNT_NUM]; 2922 u32 cnt_notify[BTC_NCNT_NUM]; 2923 2924 u32 update_slot_map; 2925 u32 set_ant_path; 2926 u32 e2g_slot_limit; 2927 u32 e2g_slot_nulltx_time; 2928 2929 u32 wl_only: 1; 2930 u32 wl_fw_cx_offload: 1; 2931 u32 freerun: 1; 2932 u32 fddt_train: 1; 2933 u32 wl_ps_ctrl: 2; 2934 u32 wl_mimo_ps: 1; 2935 u32 leak_ap: 1; 2936 u32 noisy_level: 3; 2937 u32 coex_info_map: 8; 2938 u32 bt_only: 1; 2939 u32 wl_btg_rx: 2; 2940 u32 trx_para_level: 8; 2941 u32 wl_stb_chg: 1; 2942 u32 pta_owner: 1; 2943 2944 u32 tdma_instant_excute: 1; 2945 u32 wl_btg_rx_rb: 2; 2946 2947 u16 slot_dur[CXST_MAX]; 2948 u16 bt_slot_flood; 2949 2950 u8 run_reason; 2951 u8 run_action; 2952 2953 u8 wl_pre_agc: 2; 2954 u8 wl_lna2: 1; 2955 u8 freerun_chk: 1; 2956 u8 wl_pre_agc_rb: 2; 2957 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2958 u8 slot_req_more: 1; 2959 }; 2960 2961 struct rtw89_btc_ctrl { 2962 u32 manual: 1; 2963 u32 igno_bt: 1; 2964 u32 always_freerun: 1; 2965 u32 trace_step: 16; 2966 u32 rsvd: 12; 2967 }; 2968 2969 struct rtw89_btc_ctrl_v7 { 2970 u8 manual; 2971 u8 igno_bt; 2972 u8 always_freerun; 2973 u8 rsvd; 2974 } __packed; 2975 2976 union rtw89_btc_ctrl_list { 2977 struct rtw89_btc_ctrl ctrl; 2978 struct rtw89_btc_ctrl_v7 ctrl_v7; 2979 }; 2980 2981 struct rtw89_btc_dbg { 2982 /* cmd "rb" */ 2983 bool rb_done; 2984 u32 rb_val; 2985 }; 2986 2987 enum rtw89_btc_btf_fw_event { 2988 BTF_EVNT_RPT = 0, 2989 BTF_EVNT_BT_INFO = 1, 2990 BTF_EVNT_BT_SCBD = 2, 2991 BTF_EVNT_BT_REG = 3, 2992 BTF_EVNT_CX_RUNINFO = 4, 2993 BTF_EVNT_BT_PSD = 5, 2994 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 2995 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 2996 BTF_EVNT_BUF_OVERFLOW, 2997 BTF_EVNT_C2H_LOOPBACK, 2998 BTF_EVNT_MAX, 2999 }; 3000 3001 enum btf_fw_event_report { 3002 BTC_RPT_TYPE_CTRL = 0x0, 3003 BTC_RPT_TYPE_TDMA, 3004 BTC_RPT_TYPE_SLOT, 3005 BTC_RPT_TYPE_CYSTA, 3006 BTC_RPT_TYPE_STEP, 3007 BTC_RPT_TYPE_NULLSTA, 3008 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3009 BTC_RPT_TYPE_MREG, 3010 BTC_RPT_TYPE_GPIO_DBG, 3011 BTC_RPT_TYPE_BT_VER, 3012 BTC_RPT_TYPE_BT_SCAN, 3013 BTC_RPT_TYPE_BT_AFH, 3014 BTC_RPT_TYPE_BT_DEVICE, 3015 BTC_RPT_TYPE_TEST, 3016 BTC_RPT_TYPE_MAX = 31, 3017 3018 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3019 __BTC_RPT_TYPE_V0_MAX = 12, 3020 }; 3021 3022 enum rtw_btc_btf_reg_type { 3023 REG_MAC = 0x0, 3024 REG_BB = 0x1, 3025 REG_RF = 0x2, 3026 REG_BT_RF = 0x3, 3027 REG_BT_MODEM = 0x4, 3028 REG_BT_BLUEWIZE = 0x5, 3029 REG_BT_VENDOR = 0x6, 3030 REG_BT_LE = 0x7, 3031 REG_MAX_TYPE, 3032 }; 3033 3034 struct rtw89_btc_rpt_cmn_info { 3035 u32 rx_cnt; 3036 u32 rx_len; 3037 u32 req_len; /* expected rsp len */ 3038 u8 req_fver; /* expected rsp fver */ 3039 u8 rsp_fver; /* fver from fw */ 3040 u8 valid; 3041 } __packed; 3042 3043 union rtw89_btc_fbtc_btafh_info { 3044 struct rtw89_btc_fbtc_btafh v1; 3045 struct rtw89_btc_fbtc_btafh_v2 v2; 3046 }; 3047 3048 struct rtw89_btc_report_ctrl_state { 3049 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3050 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3051 }; 3052 3053 struct rtw89_btc_rpt_fbtc_tdma { 3054 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3055 union rtw89_btc_fbtc_tdma_le32 finfo; 3056 }; 3057 3058 struct rtw89_btc_rpt_fbtc_slots { 3059 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3060 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3061 }; 3062 3063 struct rtw89_btc_rpt_fbtc_cysta { 3064 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3065 union rtw89_btc_fbtc_cysta_info finfo; 3066 }; 3067 3068 struct rtw89_btc_rpt_fbtc_step { 3069 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3070 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3071 }; 3072 3073 struct rtw89_btc_rpt_fbtc_nullsta { 3074 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3075 union rtw89_btc_fbtc_cynullsta_info finfo; 3076 }; 3077 3078 struct rtw89_btc_rpt_fbtc_mreg { 3079 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3080 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3081 }; 3082 3083 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3084 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3085 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3086 }; 3087 3088 struct rtw89_btc_rpt_fbtc_btver { 3089 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3090 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3091 }; 3092 3093 struct rtw89_btc_rpt_fbtc_btscan { 3094 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3095 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3096 }; 3097 3098 struct rtw89_btc_rpt_fbtc_btafh { 3099 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3100 union rtw89_btc_fbtc_btafh_info finfo; 3101 }; 3102 3103 struct rtw89_btc_rpt_fbtc_btdev { 3104 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3105 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3106 }; 3107 3108 enum rtw89_btc_btfre_type { 3109 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3110 BTFRE_UNDEF_TYPE, 3111 BTFRE_EXCEPTION, 3112 BTFRE_MAX, 3113 }; 3114 3115 struct rtw89_btc_btf_fwinfo { 3116 u32 cnt_c2h; 3117 u32 cnt_h2c; 3118 u32 cnt_h2c_fail; 3119 u32 event[BTF_EVNT_MAX]; 3120 3121 u32 err[BTFRE_MAX]; 3122 u32 len_mismch; 3123 u32 fver_mismch; 3124 u32 rpt_en_map; 3125 3126 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3127 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3128 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3129 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3130 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3131 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3132 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3133 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3134 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3135 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3136 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3137 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3138 }; 3139 3140 struct rtw89_btc_ver { 3141 enum rtw89_core_chip_id chip_id; 3142 u32 fw_ver_code; 3143 3144 u8 fcxbtcrpt; 3145 u8 fcxtdma; 3146 u8 fcxslots; 3147 u8 fcxcysta; 3148 u8 fcxstep; 3149 u8 fcxnullsta; 3150 u8 fcxmreg; 3151 u8 fcxgpiodbg; 3152 u8 fcxbtver; 3153 u8 fcxbtscan; 3154 u8 fcxbtafh; 3155 u8 fcxbtdevinfo; 3156 u8 fwlrole; 3157 u8 frptmap; 3158 u8 fcxctrl; 3159 u8 fcxinit; 3160 3161 u8 fwevntrptl; 3162 u8 fwc2hfunc; 3163 u8 drvinfo_type; 3164 u16 info_buf; 3165 u8 max_role_num; 3166 }; 3167 3168 #define RTW89_BTC_POLICY_MAXLEN 512 3169 3170 struct rtw89_btc { 3171 const struct rtw89_btc_ver *ver; 3172 3173 struct rtw89_btc_cx cx; 3174 struct rtw89_btc_dm dm; 3175 union rtw89_btc_ctrl_list ctrl; 3176 union rtw89_btc_module_info mdinfo; 3177 struct rtw89_btc_btf_fwinfo fwinfo; 3178 struct rtw89_btc_dbg dbg; 3179 3180 struct wiphy_work eapol_notify_work; 3181 struct wiphy_work arp_notify_work; 3182 struct wiphy_work dhcp_notify_work; 3183 struct wiphy_work icmp_notify_work; 3184 3185 u32 bt_req_len; 3186 3187 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3188 u8 ant_type; 3189 u8 btg_pos; 3190 u16 policy_len; 3191 u16 policy_type; 3192 u32 hubmsg_cnt; 3193 bool bt_req_en; 3194 bool update_policy_force; 3195 bool lps; 3196 bool manual_ctrl; 3197 }; 3198 3199 enum rtw89_btc_hmsg { 3200 RTW89_BTC_HMSG_TMR_EN = 0x0, 3201 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3202 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3203 RTW89_BTC_HMSG_FW_EV = 0x3, 3204 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3205 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3206 3207 NUM_OF_RTW89_BTC_HMSG, 3208 }; 3209 3210 enum rtw89_ra_mode { 3211 RTW89_RA_MODE_CCK = BIT(0), 3212 RTW89_RA_MODE_OFDM = BIT(1), 3213 RTW89_RA_MODE_HT = BIT(2), 3214 RTW89_RA_MODE_VHT = BIT(3), 3215 RTW89_RA_MODE_HE = BIT(4), 3216 RTW89_RA_MODE_EHT = BIT(5), 3217 }; 3218 3219 enum rtw89_ra_report_mode { 3220 RTW89_RA_RPT_MODE_LEGACY, 3221 RTW89_RA_RPT_MODE_HT, 3222 RTW89_RA_RPT_MODE_VHT, 3223 RTW89_RA_RPT_MODE_HE, 3224 RTW89_RA_RPT_MODE_EHT, 3225 }; 3226 3227 enum rtw89_dig_noisy_level { 3228 RTW89_DIG_NOISY_LEVEL0 = -1, 3229 RTW89_DIG_NOISY_LEVEL1 = 0, 3230 RTW89_DIG_NOISY_LEVEL2 = 1, 3231 RTW89_DIG_NOISY_LEVEL3 = 2, 3232 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3233 }; 3234 3235 enum rtw89_gi_ltf { 3236 RTW89_GILTF_LGI_4XHE32 = 0, 3237 RTW89_GILTF_SGI_4XHE08 = 1, 3238 RTW89_GILTF_2XHE16 = 2, 3239 RTW89_GILTF_2XHE08 = 3, 3240 RTW89_GILTF_1XHE16 = 4, 3241 RTW89_GILTF_1XHE08 = 5, 3242 RTW89_GILTF_MAX 3243 }; 3244 3245 enum rtw89_rx_frame_type { 3246 RTW89_RX_TYPE_MGNT = 0, 3247 RTW89_RX_TYPE_CTRL = 1, 3248 RTW89_RX_TYPE_DATA = 2, 3249 RTW89_RX_TYPE_RSVD = 3, 3250 }; 3251 3252 enum rtw89_efuse_block { 3253 RTW89_EFUSE_BLOCK_SYS = 0, 3254 RTW89_EFUSE_BLOCK_RF = 1, 3255 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3256 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3257 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3258 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3259 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3260 RTW89_EFUSE_BLOCK_ADIE = 7, 3261 3262 RTW89_EFUSE_BLOCK_NUM, 3263 RTW89_EFUSE_BLOCK_IGNORE, 3264 }; 3265 3266 struct rtw89_ra_info { 3267 u8 is_dis_ra:1; 3268 /* Bit0 : CCK 3269 * Bit1 : OFDM 3270 * Bit2 : HT 3271 * Bit3 : VHT 3272 * Bit4 : HE 3273 * Bit5 : EHT 3274 */ 3275 u8 mode_ctrl:6; 3276 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3277 u8 macid; 3278 u8 dcm_cap:1; 3279 u8 er_cap:1; 3280 u8 init_rate_lv:2; 3281 u8 upd_all:1; 3282 u8 en_sgi:1; 3283 u8 ldpc_cap:1; 3284 u8 stbc_cap:1; 3285 u8 ss_num:3; 3286 u8 giltf:3; 3287 u8 upd_bw_nss_mask:1; 3288 u8 upd_mask:1; 3289 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3290 /* BFee CSI */ 3291 u8 band_num; 3292 u8 ra_csi_rate_en:1; 3293 u8 fixed_csi_rate_en:1; 3294 u8 cr_tbl_sel:1; 3295 u8 fix_giltf_en:1; 3296 u8 fix_giltf:3; 3297 u8 rsvd2:1; 3298 u8 csi_mcs_ss_idx; 3299 u8 csi_mode:2; 3300 u8 csi_gi_ltf:3; 3301 u8 csi_bw:3; 3302 }; 3303 3304 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3305 #define RTW89_PPDU_MAC_INFO_SIZE 8 3306 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3307 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3308 3309 #define RTW89_MAX_RX_AGG_NUM 64 3310 #define RTW89_MAX_TX_AGG_NUM 128 3311 3312 struct rtw89_ampdu_params { 3313 u16 agg_num; 3314 bool amsdu; 3315 }; 3316 3317 struct rtw89_ra_report { 3318 struct rate_info txrate; 3319 u32 bit_rate; 3320 u16 hw_rate; 3321 bool might_fallback_legacy; 3322 }; 3323 3324 DECLARE_EWMA(rssi, 10, 16); 3325 DECLARE_EWMA(evm, 10, 16); 3326 DECLARE_EWMA(snr, 10, 16); 3327 3328 struct rtw89_ba_cam_entry { 3329 struct list_head list; 3330 u8 tid; 3331 }; 3332 3333 #define RTW89_MAX_ADDR_CAM_NUM 128 3334 #define RTW89_MAX_BSSID_CAM_NUM 20 3335 #define RTW89_MAX_SEC_CAM_NUM 128 3336 #define RTW89_MAX_BA_CAM_NUM 24 3337 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3338 3339 struct rtw89_addr_cam_entry { 3340 u8 addr_cam_idx; 3341 u8 offset; 3342 u8 len; 3343 u8 valid : 1; 3344 u8 addr_mask : 6; 3345 u8 wapi : 1; 3346 u8 mask_sel : 2; 3347 u8 bssid_cam_idx: 6; 3348 3349 u8 sec_ent_mode; 3350 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3351 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3352 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3353 }; 3354 3355 struct rtw89_bssid_cam_entry { 3356 u8 bssid[ETH_ALEN]; 3357 u8 phy_idx; 3358 u8 bssid_cam_idx; 3359 u8 offset; 3360 u8 len; 3361 u8 valid : 1; 3362 u8 num; 3363 }; 3364 3365 struct rtw89_sec_cam_entry { 3366 u8 sec_cam_idx; 3367 u8 offset; 3368 u8 len; 3369 u8 type : 4; 3370 u8 ext_key : 1; 3371 u8 spp_mode : 1; 3372 /* 256 bits */ 3373 u8 key[32]; 3374 3375 struct ieee80211_key_conf *key_conf; 3376 }; 3377 3378 struct rtw89_sta_link { 3379 struct rtw89_sta *rtwsta; 3380 unsigned int link_id; 3381 3382 u8 mac_id; 3383 bool er_cap; 3384 struct rtw89_vif_link *rtwvif_link; 3385 struct rtw89_ra_info ra; 3386 struct rtw89_ra_report ra_report; 3387 int max_agg_wait; 3388 u8 prev_rssi; 3389 struct ewma_rssi avg_rssi; 3390 struct ewma_rssi rssi[RF_PATH_MAX]; 3391 struct ewma_snr avg_snr; 3392 struct ewma_evm evm_1ss; 3393 struct ewma_evm evm_min[RF_PATH_MAX]; 3394 struct ewma_evm evm_max[RF_PATH_MAX]; 3395 struct ieee80211_rx_status rx_status; 3396 u16 rx_hw_rate; 3397 __le32 htc_template; 3398 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3399 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3400 struct list_head ba_cam_list; 3401 3402 bool use_cfg_mask; 3403 struct cfg80211_bitrate_mask mask; 3404 3405 bool cctl_tx_time; 3406 u32 ampdu_max_time:4; 3407 bool cctl_tx_retry_limit; 3408 u32 data_tx_cnt_lmt:6; 3409 }; 3410 3411 struct rtw89_efuse { 3412 bool valid; 3413 bool power_k_valid; 3414 u8 xtal_cap; 3415 u8 addr[ETH_ALEN]; 3416 u8 rfe_type; 3417 char country_code[2]; 3418 }; 3419 3420 struct rtw89_phy_rate_pattern { 3421 u64 ra_mask; 3422 u16 rate; 3423 u8 ra_mode; 3424 bool enable; 3425 }; 3426 3427 struct rtw89_tx_wait_info { 3428 struct rcu_head rcu_head; 3429 struct completion completion; 3430 bool tx_done; 3431 }; 3432 3433 struct rtw89_tx_skb_data { 3434 struct rtw89_tx_wait_info __rcu *wait; 3435 u8 hci_priv[]; 3436 }; 3437 3438 #define RTW89_ROC_IDLE_TIMEOUT 500 3439 #define RTW89_ROC_TX_TIMEOUT 30 3440 enum rtw89_roc_state { 3441 RTW89_ROC_IDLE, 3442 RTW89_ROC_NORMAL, 3443 RTW89_ROC_MGMT, 3444 }; 3445 3446 #define RTW89_ROC_BY_LINK_INDEX 0 3447 3448 struct rtw89_roc { 3449 struct ieee80211_channel chan; 3450 struct wiphy_delayed_work roc_work; 3451 enum ieee80211_roc_type type; 3452 enum rtw89_roc_state state; 3453 int duration; 3454 }; 3455 3456 #define RTW89_P2P_MAX_NOA_NUM 2 3457 3458 struct rtw89_p2p_ie_head { 3459 u8 eid; 3460 u8 ie_len; 3461 u8 oui[3]; 3462 u8 oui_type; 3463 } __packed; 3464 3465 struct rtw89_noa_attr_head { 3466 u8 attr_type; 3467 __le16 attr_len; 3468 u8 index; 3469 u8 oppps_ctwindow; 3470 } __packed; 3471 3472 struct rtw89_p2p_noa_ie { 3473 struct rtw89_p2p_ie_head p2p_head; 3474 struct rtw89_noa_attr_head noa_head; 3475 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3476 } __packed; 3477 3478 struct rtw89_p2p_noa_setter { 3479 struct rtw89_p2p_noa_ie ie; 3480 u8 noa_count; 3481 u8 noa_index; 3482 }; 3483 3484 struct rtw89_vif_link { 3485 struct rtw89_vif *rtwvif; 3486 unsigned int link_id; 3487 3488 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3489 enum rtw89_chanctx_idx chanctx_idx; 3490 enum rtw89_reg_6ghz_power reg_6ghz_power; 3491 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3492 3493 u8 mac_id; 3494 u8 port; 3495 u8 mac_addr[ETH_ALEN]; 3496 u8 bssid[ETH_ALEN]; 3497 u8 phy_idx; 3498 u8 mac_idx; 3499 u8 net_type; 3500 u8 wifi_role; 3501 u8 self_role; 3502 u8 wmm; 3503 u8 bcn_hit_cond; 3504 u8 bcn_bw_idx; 3505 u8 hit_rule; 3506 u8 last_noa_nr; 3507 u64 sync_bcn_tsf; 3508 bool trigger; 3509 bool lsig_txop; 3510 u8 tgt_ind; 3511 u8 frm_tgt_ind; 3512 bool wowlan_pattern; 3513 bool wowlan_uc; 3514 bool wowlan_magic; 3515 bool is_hesta; 3516 bool last_a_ctrl; 3517 bool dyn_tb_bedge_en; 3518 bool pre_pwr_diff_en; 3519 bool pwr_diff_en; 3520 u8 def_tri_idx; 3521 struct wiphy_work update_beacon_work; 3522 struct rtw89_addr_cam_entry addr_cam; 3523 struct rtw89_bssid_cam_entry bssid_cam; 3524 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3525 struct rtw89_phy_rate_pattern rate_pattern; 3526 struct list_head general_pkt_list; 3527 struct rtw89_p2p_noa_setter p2p_noa; 3528 }; 3529 3530 enum rtw89_lv1_rcvy_step { 3531 RTW89_LV1_RCVY_STEP_1, 3532 RTW89_LV1_RCVY_STEP_2, 3533 }; 3534 3535 struct rtw89_hci_ops { 3536 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3537 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3538 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3539 void (*reset)(struct rtw89_dev *rtwdev); 3540 int (*start)(struct rtw89_dev *rtwdev); 3541 void (*stop)(struct rtw89_dev *rtwdev); 3542 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3543 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3544 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3545 3546 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3547 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3548 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3549 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3550 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3551 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3552 3553 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3554 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3555 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3556 int (*deinit)(struct rtw89_dev *rtwdev); 3557 3558 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3559 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3560 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3561 int (*napi_poll)(struct napi_struct *napi, int budget); 3562 3563 /* Deal with locks inside recovery_start and recovery_complete callbacks 3564 * by hci instance, and handle things which need to consider under SER. 3565 * e.g. turn on/off interrupts except for the one for halt notification. 3566 */ 3567 void (*recovery_start)(struct rtw89_dev *rtwdev); 3568 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3569 3570 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3571 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3572 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3573 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3574 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3575 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3576 void (*disable_intr)(struct rtw89_dev *rtwdev); 3577 void (*enable_intr)(struct rtw89_dev *rtwdev); 3578 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3579 }; 3580 3581 struct rtw89_hci_info { 3582 const struct rtw89_hci_ops *ops; 3583 enum rtw89_hci_type type; 3584 u32 rpwm_addr; 3585 u32 cpwm_addr; 3586 bool paused; 3587 }; 3588 3589 struct rtw89_chip_ops { 3590 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3591 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3592 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3593 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3594 void (*bb_reset)(struct rtw89_dev *rtwdev, 3595 enum rtw89_phy_idx phy_idx); 3596 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3597 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3598 u32 addr, u32 mask); 3599 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3600 u32 addr, u32 mask, u32 data); 3601 void (*set_channel)(struct rtw89_dev *rtwdev, 3602 const struct rtw89_chan *chan, 3603 enum rtw89_mac_idx mac_idx, 3604 enum rtw89_phy_idx phy_idx); 3605 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3606 struct rtw89_channel_help_params *p, 3607 const struct rtw89_chan *chan, 3608 enum rtw89_mac_idx mac_idx, 3609 enum rtw89_phy_idx phy_idx); 3610 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3611 enum rtw89_efuse_block block); 3612 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3613 void (*fem_setup)(struct rtw89_dev *rtwdev); 3614 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3615 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3616 void (*rfk_init)(struct rtw89_dev *rtwdev); 3617 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3618 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3619 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3620 enum rtw89_phy_idx phy_idx, 3621 const struct rtw89_chan *chan); 3622 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3623 bool start); 3624 void (*rfk_track)(struct rtw89_dev *rtwdev); 3625 void (*power_trim)(struct rtw89_dev *rtwdev); 3626 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3627 const struct rtw89_chan *chan, 3628 enum rtw89_phy_idx phy_idx); 3629 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3630 enum rtw89_phy_idx phy_idx); 3631 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3632 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3633 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3634 enum rtw89_phy_idx phy_idx); 3635 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3636 struct rtw89_rx_phy_ppdu *phy_ppdu, 3637 struct ieee80211_rx_status *status); 3638 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3639 struct rtw89_rx_phy_ppdu *phy_ppdu); 3640 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3641 struct rtw89_rx_desc_info *desc_info, 3642 struct ieee80211_rx_status *rx_status); 3643 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3644 enum rtw89_phy_idx phy_idx); 3645 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3646 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3647 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3648 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3649 enum rtw89_phy_idx phy_idx); 3650 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3651 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3652 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3653 struct rtw89_rx_desc_info *desc_info, 3654 u8 *data, u32 data_offset); 3655 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3656 struct rtw89_tx_desc_info *desc_info, 3657 void *txdesc); 3658 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3659 struct rtw89_tx_desc_info *desc_info, 3660 void *txdesc); 3661 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3662 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3663 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3664 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3665 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3666 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3667 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3668 struct rtw89_vif_link *rtwvif_link, 3669 struct rtw89_sta_link *rtwsta_link); 3670 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3671 struct rtw89_vif_link *rtwvif_link, 3672 struct rtw89_sta_link *rtwsta_link); 3673 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3674 struct rtw89_vif_link *rtwvif_link, 3675 struct rtw89_sta_link *rtwsta_link); 3676 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3677 struct rtw89_vif_link *rtwvif_link, 3678 struct rtw89_sta_link *rtwsta_link); 3679 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3680 struct rtw89_vif_link *rtwvif_link, 3681 struct rtw89_sta_link *rtwsta_link); 3682 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3683 struct rtw89_vif_link *rtwvif_link); 3684 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3685 struct rtw89_vif_link *rtwvif_link, 3686 struct rtw89_sta_link *rtwsta_link, 3687 bool valid, struct ieee80211_ampdu_params *params); 3688 3689 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3690 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3691 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3692 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3693 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3694 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3695 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3696 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3697 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3698 }; 3699 3700 enum rtw89_dma_ch { 3701 RTW89_DMA_ACH0 = 0, 3702 RTW89_DMA_ACH1 = 1, 3703 RTW89_DMA_ACH2 = 2, 3704 RTW89_DMA_ACH3 = 3, 3705 RTW89_DMA_ACH4 = 4, 3706 RTW89_DMA_ACH5 = 5, 3707 RTW89_DMA_ACH6 = 6, 3708 RTW89_DMA_ACH7 = 7, 3709 RTW89_DMA_B0MG = 8, 3710 RTW89_DMA_B0HI = 9, 3711 RTW89_DMA_B1MG = 10, 3712 RTW89_DMA_B1HI = 11, 3713 RTW89_DMA_H2C = 12, 3714 RTW89_DMA_CH_NUM = 13 3715 }; 3716 3717 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3718 3719 enum rtw89_mlo_dbcc_mode { 3720 MLO_DBCC_NOT_SUPPORT = 1, 3721 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3722 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3723 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3724 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3725 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3726 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3727 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3728 DBCC_LEGACY = 0xffffffff, 3729 }; 3730 3731 enum rtw89_scan_be_operation { 3732 RTW89_SCAN_OP_STOP, 3733 RTW89_SCAN_OP_START, 3734 RTW89_SCAN_OP_SETPARM, 3735 RTW89_SCAN_OP_GETRPT, 3736 RTW89_SCAN_OP_NUM 3737 }; 3738 3739 enum rtw89_scan_be_mode { 3740 RTW89_SCAN_MODE_SA, 3741 RTW89_SCAN_MODE_MACC, 3742 RTW89_SCAN_MODE_NUM 3743 }; 3744 3745 enum rtw89_scan_be_opmode { 3746 RTW89_SCAN_OPMODE_NONE, 3747 RTW89_SCAN_OPMODE_TBTT, 3748 RTW89_SCAN_OPMODE_INTV, 3749 RTW89_SCAN_OPMODE_CNT, 3750 RTW89_SCAN_OPMODE_NUM, 3751 }; 3752 3753 struct rtw89_scan_option { 3754 bool enable; 3755 bool target_ch_mode; 3756 u8 num_macc_role; 3757 u8 num_opch; 3758 u8 repeat; 3759 u16 norm_pd; 3760 u16 slow_pd; 3761 u16 norm_cy; 3762 u8 opch_end; 3763 u16 delay; 3764 u64 prohib_chan; 3765 enum rtw89_phy_idx band; 3766 enum rtw89_scan_be_operation operation; 3767 enum rtw89_scan_be_mode scan_mode; 3768 enum rtw89_mlo_dbcc_mode mlo_mode; 3769 }; 3770 3771 enum rtw89_qta_mode { 3772 RTW89_QTA_SCC, 3773 RTW89_QTA_DBCC, 3774 RTW89_QTA_DLFW, 3775 RTW89_QTA_WOW, 3776 3777 /* keep last */ 3778 RTW89_QTA_INVALID, 3779 }; 3780 3781 struct rtw89_hfc_ch_cfg { 3782 u16 min; 3783 u16 max; 3784 #define grp_0 0 3785 #define grp_1 1 3786 #define grp_num 2 3787 u8 grp; 3788 }; 3789 3790 struct rtw89_hfc_ch_info { 3791 u16 aval; 3792 u16 used; 3793 }; 3794 3795 struct rtw89_hfc_pub_cfg { 3796 u16 grp0; 3797 u16 grp1; 3798 u16 pub_max; 3799 u16 wp_thrd; 3800 }; 3801 3802 struct rtw89_hfc_pub_info { 3803 u16 g0_used; 3804 u16 g1_used; 3805 u16 g0_aval; 3806 u16 g1_aval; 3807 u16 pub_aval; 3808 u16 wp_aval; 3809 }; 3810 3811 struct rtw89_hfc_prec_cfg { 3812 u16 ch011_prec; 3813 u16 h2c_prec; 3814 u16 wp_ch07_prec; 3815 u16 wp_ch811_prec; 3816 u8 ch011_full_cond; 3817 u8 h2c_full_cond; 3818 u8 wp_ch07_full_cond; 3819 u8 wp_ch811_full_cond; 3820 }; 3821 3822 struct rtw89_hfc_param { 3823 bool en; 3824 bool h2c_en; 3825 u8 mode; 3826 const struct rtw89_hfc_ch_cfg *ch_cfg; 3827 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3828 struct rtw89_hfc_pub_cfg pub_cfg; 3829 struct rtw89_hfc_pub_info pub_info; 3830 struct rtw89_hfc_prec_cfg prec_cfg; 3831 }; 3832 3833 struct rtw89_hfc_param_ini { 3834 const struct rtw89_hfc_ch_cfg *ch_cfg; 3835 const struct rtw89_hfc_pub_cfg *pub_cfg; 3836 const struct rtw89_hfc_prec_cfg *prec_cfg; 3837 u8 mode; 3838 }; 3839 3840 struct rtw89_dle_size { 3841 u16 pge_size; 3842 u16 lnk_pge_num; 3843 u16 unlnk_pge_num; 3844 /* for WiFi 7 chips below */ 3845 u32 srt_ofst; 3846 }; 3847 3848 struct rtw89_wde_quota { 3849 u16 hif; 3850 u16 wcpu; 3851 u16 pkt_in; 3852 u16 cpu_io; 3853 }; 3854 3855 struct rtw89_ple_quota { 3856 u16 cma0_tx; 3857 u16 cma1_tx; 3858 u16 c2h; 3859 u16 h2c; 3860 u16 wcpu; 3861 u16 mpdu_proc; 3862 u16 cma0_dma; 3863 u16 cma1_dma; 3864 u16 bb_rpt; 3865 u16 wd_rel; 3866 u16 cpu_io; 3867 u16 tx_rpt; 3868 /* for WiFi 7 chips below */ 3869 u16 h2d; 3870 }; 3871 3872 struct rtw89_rsvd_quota { 3873 u16 mpdu_info_tbl; 3874 u16 b0_csi; 3875 u16 b1_csi; 3876 u16 b0_lmr; 3877 u16 b1_lmr; 3878 u16 b0_ftm; 3879 u16 b1_ftm; 3880 u16 b0_smr; 3881 u16 b1_smr; 3882 u16 others; 3883 }; 3884 3885 struct rtw89_dle_rsvd_size { 3886 u32 srt_ofst; 3887 u32 size; 3888 }; 3889 3890 struct rtw89_dle_mem { 3891 enum rtw89_qta_mode mode; 3892 const struct rtw89_dle_size *wde_size; 3893 const struct rtw89_dle_size *ple_size; 3894 const struct rtw89_wde_quota *wde_min_qt; 3895 const struct rtw89_wde_quota *wde_max_qt; 3896 const struct rtw89_ple_quota *ple_min_qt; 3897 const struct rtw89_ple_quota *ple_max_qt; 3898 /* for WiFi 7 chips below */ 3899 const struct rtw89_rsvd_quota *rsvd_qt; 3900 const struct rtw89_dle_rsvd_size *rsvd0_size; 3901 const struct rtw89_dle_rsvd_size *rsvd1_size; 3902 }; 3903 3904 struct rtw89_reg_def { 3905 u32 addr; 3906 u32 mask; 3907 }; 3908 3909 struct rtw89_reg2_def { 3910 u32 addr; 3911 u32 data; 3912 }; 3913 3914 struct rtw89_reg3_def { 3915 u32 addr; 3916 u32 mask; 3917 u32 data; 3918 }; 3919 3920 struct rtw89_reg5_def { 3921 u8 flag; /* recognized by parsers */ 3922 u8 path; 3923 u32 addr; 3924 u32 mask; 3925 u32 data; 3926 }; 3927 3928 struct rtw89_reg_imr { 3929 u32 addr; 3930 u32 clr; 3931 u32 set; 3932 }; 3933 3934 struct rtw89_phy_table { 3935 const struct rtw89_reg2_def *regs; 3936 u32 n_regs; 3937 enum rtw89_rf_path rf_path; 3938 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3939 enum rtw89_rf_path rf_path, void *data); 3940 }; 3941 3942 struct rtw89_txpwr_table { 3943 const void *data; 3944 u32 size; 3945 void (*load)(struct rtw89_dev *rtwdev, 3946 const struct rtw89_txpwr_table *tbl); 3947 }; 3948 3949 struct rtw89_txpwr_rule_2ghz { 3950 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3951 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3952 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3953 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3954 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3955 }; 3956 3957 struct rtw89_txpwr_rule_5ghz { 3958 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3959 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3960 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3961 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3962 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3963 }; 3964 3965 struct rtw89_txpwr_rule_6ghz { 3966 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3967 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3968 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3969 [RTW89_6G_CH_NUM]; 3970 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3971 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3972 [RTW89_6G_CH_NUM]; 3973 }; 3974 3975 struct rtw89_tx_shape { 3976 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3977 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3978 }; 3979 3980 struct rtw89_rfe_parms { 3981 const struct rtw89_txpwr_table *byr_tbl; 3982 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3983 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3984 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3985 struct rtw89_tx_shape tx_shape; 3986 }; 3987 3988 struct rtw89_rfe_parms_conf { 3989 const struct rtw89_rfe_parms *rfe_parms; 3990 u8 rfe_type; 3991 }; 3992 3993 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3994 3995 struct rtw89_txpwr_conf { 3996 u8 rfe_type; 3997 u8 ent_sz; 3998 u32 num_ents; 3999 const void *data; 4000 }; 4001 4002 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 4003 const struct rtw89_txpwr_conf *conf) 4004 { 4005 u8 valid_size = min(size, conf->ent_sz); 4006 4007 memcpy(entry, cursor, valid_size); 4008 return true; 4009 } 4010 4011 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4012 4013 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4014 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4015 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4016 (cursor) += (conf)->ent_sz) \ 4017 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4018 4019 struct rtw89_txpwr_byrate_data { 4020 struct rtw89_txpwr_conf conf; 4021 struct rtw89_txpwr_table tbl; 4022 }; 4023 4024 struct rtw89_txpwr_lmt_2ghz_data { 4025 struct rtw89_txpwr_conf conf; 4026 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4027 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4028 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4029 }; 4030 4031 struct rtw89_txpwr_lmt_5ghz_data { 4032 struct rtw89_txpwr_conf conf; 4033 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4034 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4035 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4036 }; 4037 4038 struct rtw89_txpwr_lmt_6ghz_data { 4039 struct rtw89_txpwr_conf conf; 4040 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4041 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4042 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4043 [RTW89_6G_CH_NUM]; 4044 }; 4045 4046 struct rtw89_txpwr_lmt_ru_2ghz_data { 4047 struct rtw89_txpwr_conf conf; 4048 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4049 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4050 }; 4051 4052 struct rtw89_txpwr_lmt_ru_5ghz_data { 4053 struct rtw89_txpwr_conf conf; 4054 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4055 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4056 }; 4057 4058 struct rtw89_txpwr_lmt_ru_6ghz_data { 4059 struct rtw89_txpwr_conf conf; 4060 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4061 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4062 [RTW89_6G_CH_NUM]; 4063 }; 4064 4065 struct rtw89_tx_shape_lmt_data { 4066 struct rtw89_txpwr_conf conf; 4067 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4068 }; 4069 4070 struct rtw89_tx_shape_lmt_ru_data { 4071 struct rtw89_txpwr_conf conf; 4072 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4073 }; 4074 4075 struct rtw89_rfe_data { 4076 struct rtw89_txpwr_byrate_data byrate; 4077 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4078 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4079 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4080 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4081 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4082 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4083 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4084 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4085 struct rtw89_rfe_parms rfe_parms; 4086 }; 4087 4088 struct rtw89_page_regs { 4089 u32 hci_fc_ctrl; 4090 u32 ch_page_ctrl; 4091 u32 ach_page_ctrl; 4092 u32 ach_page_info; 4093 u32 pub_page_info3; 4094 u32 pub_page_ctrl1; 4095 u32 pub_page_ctrl2; 4096 u32 pub_page_info1; 4097 u32 pub_page_info2; 4098 u32 wp_page_ctrl1; 4099 u32 wp_page_ctrl2; 4100 u32 wp_page_info1; 4101 }; 4102 4103 struct rtw89_imr_info { 4104 u32 wdrls_imr_set; 4105 u32 wsec_imr_reg; 4106 u32 wsec_imr_set; 4107 u32 mpdu_tx_imr_set; 4108 u32 mpdu_rx_imr_set; 4109 u32 sta_sch_imr_set; 4110 u32 txpktctl_imr_b0_reg; 4111 u32 txpktctl_imr_b0_clr; 4112 u32 txpktctl_imr_b0_set; 4113 u32 txpktctl_imr_b1_reg; 4114 u32 txpktctl_imr_b1_clr; 4115 u32 txpktctl_imr_b1_set; 4116 u32 wde_imr_clr; 4117 u32 wde_imr_set; 4118 u32 ple_imr_clr; 4119 u32 ple_imr_set; 4120 u32 host_disp_imr_clr; 4121 u32 host_disp_imr_set; 4122 u32 cpu_disp_imr_clr; 4123 u32 cpu_disp_imr_set; 4124 u32 other_disp_imr_clr; 4125 u32 other_disp_imr_set; 4126 u32 bbrpt_com_err_imr_reg; 4127 u32 bbrpt_chinfo_err_imr_reg; 4128 u32 bbrpt_err_imr_set; 4129 u32 bbrpt_dfs_err_imr_reg; 4130 u32 ptcl_imr_clr; 4131 u32 ptcl_imr_set; 4132 u32 cdma_imr_0_reg; 4133 u32 cdma_imr_0_clr; 4134 u32 cdma_imr_0_set; 4135 u32 cdma_imr_1_reg; 4136 u32 cdma_imr_1_clr; 4137 u32 cdma_imr_1_set; 4138 u32 phy_intf_imr_reg; 4139 u32 phy_intf_imr_clr; 4140 u32 phy_intf_imr_set; 4141 u32 rmac_imr_reg; 4142 u32 rmac_imr_clr; 4143 u32 rmac_imr_set; 4144 u32 tmac_imr_reg; 4145 u32 tmac_imr_clr; 4146 u32 tmac_imr_set; 4147 }; 4148 4149 struct rtw89_imr_table { 4150 const struct rtw89_reg_imr *regs; 4151 u32 n_regs; 4152 }; 4153 4154 struct rtw89_xtal_info { 4155 u32 xcap_reg; 4156 u32 sc_xo_mask; 4157 u32 sc_xi_mask; 4158 }; 4159 4160 struct rtw89_rrsr_cfgs { 4161 struct rtw89_reg3_def ref_rate; 4162 struct rtw89_reg3_def rsc; 4163 }; 4164 4165 struct rtw89_rfkill_regs { 4166 struct rtw89_reg3_def pinmux; 4167 struct rtw89_reg3_def mode; 4168 }; 4169 4170 struct rtw89_dig_regs { 4171 u32 seg0_pd_reg; 4172 u32 pd_lower_bound_mask; 4173 u32 pd_spatial_reuse_en; 4174 u32 bmode_pd_reg; 4175 u32 bmode_cca_rssi_limit_en; 4176 u32 bmode_pd_lower_bound_reg; 4177 u32 bmode_rssi_nocca_low_th_mask; 4178 struct rtw89_reg_def p0_lna_init; 4179 struct rtw89_reg_def p1_lna_init; 4180 struct rtw89_reg_def p0_tia_init; 4181 struct rtw89_reg_def p1_tia_init; 4182 struct rtw89_reg_def p0_rxb_init; 4183 struct rtw89_reg_def p1_rxb_init; 4184 struct rtw89_reg_def p0_p20_pagcugc_en; 4185 struct rtw89_reg_def p0_s20_pagcugc_en; 4186 struct rtw89_reg_def p1_p20_pagcugc_en; 4187 struct rtw89_reg_def p1_s20_pagcugc_en; 4188 }; 4189 4190 struct rtw89_edcca_regs { 4191 u32 edcca_level; 4192 u32 edcca_mask; 4193 u32 edcca_p_mask; 4194 u32 ppdu_level; 4195 u32 ppdu_mask; 4196 struct rtw89_edcca_p_regs { 4197 u32 rpt_a; 4198 u32 rpt_b; 4199 u32 rpt_sel; 4200 u32 rpt_sel_mask; 4201 } p[RTW89_PHY_NUM]; 4202 u32 rpt_sel_be; 4203 u32 rpt_sel_be_mask; 4204 u32 tx_collision_t2r_st; 4205 u32 tx_collision_t2r_st_mask; 4206 }; 4207 4208 struct rtw89_phy_ul_tb_info { 4209 bool dyn_tb_tri_en; 4210 u8 def_if_bandedge; 4211 }; 4212 4213 struct rtw89_antdiv_stats { 4214 struct ewma_rssi cck_rssi_avg; 4215 struct ewma_rssi ofdm_rssi_avg; 4216 struct ewma_rssi non_legacy_rssi_avg; 4217 u16 pkt_cnt_cck; 4218 u16 pkt_cnt_ofdm; 4219 u16 pkt_cnt_non_legacy; 4220 u32 evm; 4221 }; 4222 4223 struct rtw89_antdiv_info { 4224 struct rtw89_antdiv_stats target_stats; 4225 struct rtw89_antdiv_stats main_stats; 4226 struct rtw89_antdiv_stats aux_stats; 4227 u8 training_count; 4228 u8 rssi_pre; 4229 bool get_stats; 4230 }; 4231 4232 enum rtw89_chanctx_state { 4233 RTW89_CHANCTX_STATE_MCC_START, 4234 RTW89_CHANCTX_STATE_MCC_STOP, 4235 }; 4236 4237 enum rtw89_chanctx_callbacks { 4238 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4239 RTW89_CHANCTX_CALLBACK_RFK, 4240 4241 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4242 }; 4243 4244 struct rtw89_chanctx_listener { 4245 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4246 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4247 }; 4248 4249 struct rtw89_chip_info { 4250 enum rtw89_core_chip_id chip_id; 4251 enum rtw89_chip_gen chip_gen; 4252 const struct rtw89_chip_ops *ops; 4253 const struct rtw89_mac_gen_def *mac_def; 4254 const struct rtw89_phy_gen_def *phy_def; 4255 const char *fw_basename; 4256 u8 fw_format_max; 4257 bool try_ce_fw; 4258 u8 bbmcu_nr; 4259 u32 needed_fw_elms; 4260 u32 fifo_size; 4261 bool small_fifo_size; 4262 u32 dle_scc_rsvd_size; 4263 u16 max_amsdu_limit; 4264 bool dis_2g_40m_ul_ofdma; 4265 u32 rsvd_ple_ofst; 4266 const struct rtw89_hfc_param_ini *hfc_param_ini; 4267 const struct rtw89_dle_mem *dle_mem; 4268 u8 wde_qempty_acq_grpnum; 4269 u8 wde_qempty_mgq_grpsel; 4270 u32 rf_base_addr[2]; 4271 u8 thermal_th[2]; 4272 u8 support_macid_num; 4273 u8 support_link_num; 4274 u8 support_chanctx_num; 4275 u8 support_bands; 4276 u16 support_bandwidths; 4277 bool support_unii4; 4278 bool support_rnr; 4279 bool support_ant_gain; 4280 bool ul_tb_waveform_ctrl; 4281 bool ul_tb_pwr_diff; 4282 bool hw_sec_hdr; 4283 bool hw_mgmt_tx_encrypt; 4284 u8 rf_path_num; 4285 u8 tx_nss; 4286 u8 rx_nss; 4287 u8 acam_num; 4288 u8 bcam_num; 4289 u8 scam_num; 4290 u8 bacam_num; 4291 u8 bacam_dynamic_num; 4292 enum rtw89_bacam_ver bacam_ver; 4293 u8 ppdu_max_usr; 4294 4295 u8 sec_ctrl_efuse_size; 4296 u32 physical_efuse_size; 4297 u32 logical_efuse_size; 4298 u32 limit_efuse_size; 4299 u32 dav_phy_efuse_size; 4300 u32 dav_log_efuse_size; 4301 u32 phycap_addr; 4302 u32 phycap_size; 4303 const struct rtw89_efuse_block_cfg *efuse_blocks; 4304 4305 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4306 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4307 const struct rtw89_phy_table *bb_table; 4308 const struct rtw89_phy_table *bb_gain_table; 4309 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4310 const struct rtw89_phy_table *nctl_table; 4311 const struct rtw89_rfk_tbl *nctl_post_table; 4312 const struct rtw89_phy_dig_gain_table *dig_table; 4313 const struct rtw89_dig_regs *dig_regs; 4314 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4315 4316 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4317 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4318 const struct rtw89_rfe_parms *dflt_parms; 4319 const struct rtw89_chanctx_listener *chanctx_listener; 4320 4321 u8 txpwr_factor_bb; 4322 u8 txpwr_factor_rf; 4323 u8 txpwr_factor_mac; 4324 4325 u32 para_ver; 4326 u32 wlcx_desired; 4327 u8 btcx_desired; 4328 u8 scbd; 4329 u8 mailbox; 4330 4331 u8 afh_guard_ch; 4332 const u8 *wl_rssi_thres; 4333 const u8 *bt_rssi_thres; 4334 u8 rssi_tol; 4335 4336 u8 mon_reg_num; 4337 const struct rtw89_btc_fbtc_mreg *mon_reg; 4338 u8 rf_para_ulink_num; 4339 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4340 u8 rf_para_dlink_num; 4341 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4342 u8 ps_mode_supported; 4343 u8 low_power_hci_modes; 4344 4345 u32 h2c_cctl_func_id; 4346 u32 hci_func_en_addr; 4347 u32 h2c_desc_size; 4348 u32 txwd_body_size; 4349 u32 txwd_info_size; 4350 u32 h2c_ctrl_reg; 4351 const u32 *h2c_regs; 4352 struct rtw89_reg_def h2c_counter_reg; 4353 u32 c2h_ctrl_reg; 4354 const u32 *c2h_regs; 4355 struct rtw89_reg_def c2h_counter_reg; 4356 const struct rtw89_page_regs *page_regs; 4357 const u32 *wow_reason_reg; 4358 bool cfo_src_fd; 4359 bool cfo_hw_comp; 4360 const struct rtw89_reg_def *dcfo_comp; 4361 u8 dcfo_comp_sft; 4362 const struct rtw89_imr_info *imr_info; 4363 const struct rtw89_imr_table *imr_dmac_table; 4364 const struct rtw89_imr_table *imr_cmac_table; 4365 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4366 struct rtw89_reg_def bss_clr_vld; 4367 u32 bss_clr_map_reg; 4368 const struct rtw89_rfkill_regs *rfkill_init; 4369 struct rtw89_reg_def rfkill_get; 4370 u32 dma_ch_mask; 4371 const struct rtw89_edcca_regs *edcca_regs; 4372 const struct wiphy_wowlan_support *wowlan_stub; 4373 const struct rtw89_xtal_info *xtal_info; 4374 }; 4375 4376 struct rtw89_chip_variant { 4377 bool no_mcs_12_13: 1; 4378 u32 fw_min_ver_code; 4379 }; 4380 4381 union rtw89_bus_info { 4382 const struct rtw89_pci_info *pci; 4383 }; 4384 4385 struct rtw89_driver_info { 4386 const struct rtw89_chip_info *chip; 4387 const struct rtw89_chip_variant *variant; 4388 const struct dmi_system_id *quirks; 4389 union rtw89_bus_info bus; 4390 }; 4391 4392 enum rtw89_hcifc_mode { 4393 RTW89_HCIFC_POH = 0, 4394 RTW89_HCIFC_STF = 1, 4395 RTW89_HCIFC_SDIO = 2, 4396 4397 /* keep last */ 4398 RTW89_HCIFC_MODE_INVALID, 4399 }; 4400 4401 struct rtw89_dle_info { 4402 const struct rtw89_rsvd_quota *rsvd_qt; 4403 enum rtw89_qta_mode qta_mode; 4404 u16 ple_pg_size; 4405 u16 ple_free_pg; 4406 u16 c0_rx_qta; 4407 u16 c1_rx_qta; 4408 }; 4409 4410 enum rtw89_host_rpr_mode { 4411 RTW89_RPR_MODE_POH = 0, 4412 RTW89_RPR_MODE_STF 4413 }; 4414 4415 #define RTW89_COMPLETION_BUF_SIZE 40 4416 #define RTW89_WAIT_COND_IDLE UINT_MAX 4417 4418 struct rtw89_completion_data { 4419 bool err; 4420 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4421 }; 4422 4423 struct rtw89_wait_info { 4424 atomic_t cond; 4425 struct completion completion; 4426 struct rtw89_completion_data data; 4427 }; 4428 4429 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4430 4431 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4432 { 4433 init_completion(&wait->completion); 4434 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4435 } 4436 4437 struct rtw89_mac_info { 4438 struct rtw89_dle_info dle_info; 4439 struct rtw89_hfc_param hfc_param; 4440 enum rtw89_qta_mode qta_mode; 4441 u8 rpwm_seq_num; 4442 u8 cpwm_seq_num; 4443 4444 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4445 struct rtw89_wait_info fw_ofld_wait; 4446 /* see RTW89_PS_WAIT_COND series for wait condition */ 4447 struct rtw89_wait_info ps_wait; 4448 }; 4449 4450 enum rtw89_fwdl_check_type { 4451 RTW89_FWDL_CHECK_FREERTOS_DONE, 4452 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4453 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4454 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4455 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4456 }; 4457 4458 enum rtw89_fw_type { 4459 RTW89_FW_NORMAL = 1, 4460 RTW89_FW_WOWLAN = 3, 4461 RTW89_FW_NORMAL_CE = 5, 4462 RTW89_FW_BBMCU0 = 64, 4463 RTW89_FW_BBMCU1 = 65, 4464 RTW89_FW_LOGFMT = 255, 4465 }; 4466 4467 enum rtw89_fw_feature { 4468 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4469 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4470 RTW89_FW_FEATURE_TX_WAKE, 4471 RTW89_FW_FEATURE_CRASH_TRIGGER, 4472 RTW89_FW_FEATURE_NO_PACKET_DROP, 4473 RTW89_FW_FEATURE_NO_DEEP_PS, 4474 RTW89_FW_FEATURE_NO_LPS_PG, 4475 RTW89_FW_FEATURE_BEACON_FILTER, 4476 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4477 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4478 RTW89_FW_FEATURE_WOW_REASON_V1, 4479 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4480 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4481 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4482 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4483 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4484 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4485 RTW89_FW_FEATURE_LPS_CH_INFO, 4486 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4487 }; 4488 4489 struct rtw89_fw_suit { 4490 enum rtw89_fw_type type; 4491 const u8 *data; 4492 u32 size; 4493 u8 major_ver; 4494 u8 minor_ver; 4495 u8 sub_ver; 4496 u8 sub_idex; 4497 u16 build_year; 4498 u16 build_mon; 4499 u16 build_date; 4500 u16 build_hour; 4501 u16 build_min; 4502 u8 cmd_ver; 4503 u8 hdr_ver; 4504 u32 commitid; 4505 }; 4506 4507 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4508 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4509 #define RTW89_FW_SUIT_VER_CODE(s) \ 4510 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4511 4512 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4513 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4514 (mfw_hdr)->ver.minor, \ 4515 (mfw_hdr)->ver.sub, \ 4516 (mfw_hdr)->ver.idx) 4517 4518 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4519 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4520 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4521 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4522 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4523 4524 struct rtw89_fw_req_info { 4525 const struct firmware *firmware; 4526 struct completion completion; 4527 }; 4528 4529 struct rtw89_fw_log { 4530 struct rtw89_fw_suit suit; 4531 bool enable; 4532 u32 last_fmt_id; 4533 u32 fmt_count; 4534 const __le32 *fmt_ids; 4535 const char *(*fmts)[]; 4536 }; 4537 4538 struct rtw89_fw_elm_info { 4539 struct rtw89_phy_table *bb_tbl; 4540 struct rtw89_phy_table *bb_gain; 4541 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4542 struct rtw89_phy_table *rf_nctl; 4543 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4544 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4545 const struct rtw89_regd_data *regd; 4546 }; 4547 4548 enum rtw89_fw_mss_dev_type { 4549 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4550 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4551 }; 4552 4553 struct rtw89_fw_secure { 4554 bool secure_boot: 1; 4555 bool can_mss_v1: 1; 4556 bool can_mss_v0: 1; 4557 u32 sb_sel_mgn; 4558 u8 mss_dev_type; 4559 u8 mss_cust_idx; 4560 u8 mss_key_num; 4561 u8 mss_idx; /* v0 */ 4562 }; 4563 4564 struct rtw89_fw_info { 4565 struct rtw89_fw_req_info req; 4566 int fw_format; 4567 u8 h2c_seq; 4568 u8 rec_seq; 4569 u8 h2c_counter; 4570 u8 c2h_counter; 4571 struct rtw89_fw_suit normal; 4572 struct rtw89_fw_suit wowlan; 4573 struct rtw89_fw_suit bbmcu0; 4574 struct rtw89_fw_suit bbmcu1; 4575 struct rtw89_fw_log log; 4576 u32 feature_map; 4577 struct rtw89_fw_elm_info elm_info; 4578 struct rtw89_fw_secure sec; 4579 }; 4580 4581 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4582 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4583 4584 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4585 ((_fw)->feature_map |= BIT(_fw_feature)) 4586 4587 struct rtw89_cam_info { 4588 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4589 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4590 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4591 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4592 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4593 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4594 }; 4595 4596 enum rtw89_sar_sources { 4597 RTW89_SAR_SOURCE_NONE, 4598 RTW89_SAR_SOURCE_COMMON, 4599 4600 RTW89_SAR_SOURCE_NR, 4601 }; 4602 4603 enum rtw89_sar_subband { 4604 RTW89_SAR_2GHZ_SUBBAND, 4605 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4606 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4607 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4608 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4609 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4610 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4611 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4612 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4613 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4614 4615 RTW89_SAR_SUBBAND_NR, 4616 }; 4617 4618 struct rtw89_sar_cfg_common { 4619 bool set[RTW89_SAR_SUBBAND_NR]; 4620 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4621 }; 4622 4623 struct rtw89_sar_info { 4624 /* used to decide how to acces SAR cfg union */ 4625 enum rtw89_sar_sources src; 4626 4627 /* reserved for different knids of SAR cfg struct. 4628 * supposed that a single cfg struct cannot handle various SAR sources. 4629 */ 4630 union { 4631 struct rtw89_sar_cfg_common cfg_common; 4632 }; 4633 }; 4634 4635 enum rtw89_ant_gain_subband { 4636 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4637 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4638 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4639 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4640 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4641 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4642 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4643 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4644 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4645 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4646 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4647 4648 RTW89_ANT_GAIN_SUBBAND_NR, 4649 }; 4650 4651 enum rtw89_ant_gain_domain_type { 4652 RTW89_ANT_GAIN_ETSI = 0, 4653 4654 RTW89_ANT_GAIN_DOMAIN_NUM, 4655 }; 4656 4657 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4658 struct rtw89_ant_gain_info { 4659 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4660 u32 regd_enabled; 4661 }; 4662 4663 struct rtw89_6ghz_span { 4664 enum rtw89_sar_subband sar_subband_low; 4665 enum rtw89_sar_subband sar_subband_high; 4666 enum rtw89_ant_gain_subband ant_gain_subband_low; 4667 enum rtw89_ant_gain_subband ant_gain_subband_high; 4668 }; 4669 4670 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4671 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4672 4673 enum rtw89_tas_state { 4674 RTW89_TAS_STATE_DPR_OFF, 4675 RTW89_TAS_STATE_DPR_ON, 4676 RTW89_TAS_STATE_DPR_FORBID, 4677 }; 4678 4679 #define RTW89_TAS_MAX_WINDOW 50 4680 struct rtw89_tas_info { 4681 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4682 s32 total_txpwr; 4683 u8 cur_idx; 4684 s8 dpr_gap; 4685 s8 delta; 4686 enum rtw89_tas_state state; 4687 bool enable; 4688 }; 4689 4690 struct rtw89_chanctx_cfg { 4691 enum rtw89_chanctx_idx idx; 4692 int ref_count; 4693 }; 4694 4695 enum rtw89_chanctx_changes { 4696 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4697 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4698 RTW89_CHANCTX_P2P_PS_CHANGE, 4699 RTW89_CHANCTX_BT_SLOT_CHANGE, 4700 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4701 4702 NUM_OF_RTW89_CHANCTX_CHANGES, 4703 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4704 }; 4705 4706 enum rtw89_entity_mode { 4707 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4708 RTW89_ENTITY_MODE_MCC_PREPARE, 4709 RTW89_ENTITY_MODE_MCC, 4710 4711 NUM_OF_RTW89_ENTITY_MODE, 4712 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4713 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4714 }; 4715 4716 #define RTW89_MAX_INTERFACE_NUM 2 4717 4718 /* only valid when running with chanctx_ops */ 4719 struct rtw89_entity_mgnt { 4720 struct list_head active_list; 4721 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4722 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4723 [__RTW89_MLD_MAX_LINK_NUM]; 4724 }; 4725 4726 struct rtw89_chanctx { 4727 struct cfg80211_chan_def chandef; 4728 struct rtw89_chan chan; 4729 struct rtw89_chan_rcd rcd; 4730 4731 /* only assigned when running with chanctx_ops */ 4732 struct rtw89_chanctx_cfg *cfg; 4733 }; 4734 4735 struct rtw89_edcca_bak { 4736 u8 a; 4737 u8 p; 4738 u8 ppdu; 4739 u8 th_old; 4740 }; 4741 4742 enum rtw89_dm_type { 4743 RTW89_DM_DYNAMIC_EDCCA, 4744 RTW89_DM_THERMAL_PROTECT, 4745 }; 4746 4747 #define RTW89_THERMAL_PROT_LV_MAX 5 4748 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 4749 4750 struct rtw89_hal { 4751 u32 rx_fltr; 4752 u8 cv; 4753 u8 acv; 4754 u32 antenna_tx; 4755 u32 antenna_rx; 4756 u8 tx_nss; 4757 u8 rx_nss; 4758 bool tx_path_diversity; 4759 bool ant_diversity; 4760 bool ant_diversity_fixed; 4761 bool support_cckpd; 4762 bool support_igi; 4763 bool no_mcs_12_13; 4764 4765 atomic_t roc_chanctx_idx; 4766 4767 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4768 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4769 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4770 struct cfg80211_chan_def roc_chandef; 4771 4772 bool entity_active[RTW89_PHY_NUM]; 4773 bool entity_pause; 4774 enum rtw89_entity_mode entity_mode; 4775 struct rtw89_entity_mgnt entity_mgnt; 4776 4777 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4778 4779 u8 thermal_prot_th; 4780 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 4781 }; 4782 4783 #define RTW89_MAX_MAC_ID_NUM 128 4784 #define RTW89_MAX_PKT_OFLD_NUM 255 4785 4786 enum rtw89_flags { 4787 RTW89_FLAG_POWERON, 4788 RTW89_FLAG_DMAC_FUNC, 4789 RTW89_FLAG_CMAC0_FUNC, 4790 RTW89_FLAG_CMAC1_FUNC, 4791 RTW89_FLAG_FW_RDY, 4792 RTW89_FLAG_RUNNING, 4793 RTW89_FLAG_PROBE_DONE, 4794 RTW89_FLAG_BFEE_MON, 4795 RTW89_FLAG_BFEE_EN, 4796 RTW89_FLAG_BFEE_TIMER_KEEP, 4797 RTW89_FLAG_NAPI_RUNNING, 4798 RTW89_FLAG_LEISURE_PS, 4799 RTW89_FLAG_LOW_POWER_MODE, 4800 RTW89_FLAG_INACTIVE_PS, 4801 RTW89_FLAG_CRASH_SIMULATING, 4802 RTW89_FLAG_SER_HANDLING, 4803 RTW89_FLAG_WOWLAN, 4804 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4805 RTW89_FLAG_CHANGING_INTERFACE, 4806 RTW89_FLAG_HW_RFKILL_STATE, 4807 4808 NUM_OF_RTW89_FLAGS, 4809 }; 4810 4811 enum rtw89_quirks { 4812 RTW89_QUIRK_PCI_BER, 4813 RTW89_QUIRK_THERMAL_PROT_120C, 4814 RTW89_QUIRK_THERMAL_PROT_110C, 4815 4816 NUM_OF_RTW89_QUIRKS, 4817 }; 4818 4819 enum rtw89_custid { 4820 RTW89_CUSTID_NONE, 4821 RTW89_CUSTID_ACER, 4822 RTW89_CUSTID_AMD, 4823 RTW89_CUSTID_ASUS, 4824 RTW89_CUSTID_DELL, 4825 RTW89_CUSTID_HP, 4826 RTW89_CUSTID_LENOVO, 4827 }; 4828 4829 enum rtw89_pkt_drop_sel { 4830 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4831 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4832 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4833 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4834 RTW89_PKT_DROP_SEL_MACID_ALL, 4835 RTW89_PKT_DROP_SEL_MG0_ONCE, 4836 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4837 RTW89_PKT_DROP_SEL_HIQ_PORT, 4838 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4839 RTW89_PKT_DROP_SEL_BAND, 4840 RTW89_PKT_DROP_SEL_BAND_ONCE, 4841 RTW89_PKT_DROP_SEL_REL_MACID, 4842 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4843 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4844 }; 4845 4846 struct rtw89_pkt_drop_params { 4847 enum rtw89_pkt_drop_sel sel; 4848 enum rtw89_mac_idx mac_band; 4849 u8 macid; 4850 u8 port; 4851 u8 mbssid; 4852 bool tf_trs; 4853 u32 macid_band_sel[4]; 4854 }; 4855 4856 struct rtw89_pkt_stat { 4857 u16 beacon_nr; 4858 u8 beacon_rate; 4859 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4860 }; 4861 4862 DECLARE_EWMA(thermal, 4, 4); 4863 4864 struct rtw89_phy_stat { 4865 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4866 u8 last_thermal_max; 4867 struct ewma_rssi bcn_rssi; 4868 struct rtw89_pkt_stat cur_pkt_stat; 4869 struct rtw89_pkt_stat last_pkt_stat; 4870 }; 4871 4872 enum rtw89_rfk_report_state { 4873 RTW89_RFK_STATE_START = 0x0, 4874 RTW89_RFK_STATE_OK = 0x1, 4875 RTW89_RFK_STATE_FAIL = 0x2, 4876 RTW89_RFK_STATE_TIMEOUT = 0x3, 4877 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4878 }; 4879 4880 struct rtw89_rfk_wait_info { 4881 struct completion completion; 4882 ktime_t start_time; 4883 enum rtw89_rfk_report_state state; 4884 u8 version; 4885 }; 4886 4887 #define RTW89_DACK_PATH_NR 2 4888 #define RTW89_DACK_IDX_NR 2 4889 #define RTW89_DACK_MSBK_NR 16 4890 struct rtw89_dack_info { 4891 bool dack_done; 4892 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4893 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4894 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4895 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4896 u32 dack_cnt; 4897 bool addck_timeout[RTW89_DACK_PATH_NR]; 4898 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4899 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4900 }; 4901 4902 enum rtw89_rfk_chs_nrs { 4903 __RTW89_RFK_CHS_NR_V0 = 2, 4904 __RTW89_RFK_CHS_NR_V1 = 3, 4905 4906 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 4907 }; 4908 4909 struct rtw89_rfk_mcc_info_data { 4910 u8 ch[RTW89_RFK_CHS_NR]; 4911 u8 band[RTW89_RFK_CHS_NR]; 4912 u8 bw[RTW89_RFK_CHS_NR]; 4913 u8 table_idx; 4914 }; 4915 4916 struct rtw89_rfk_mcc_info { 4917 struct rtw89_rfk_mcc_info_data data[2]; 4918 }; 4919 4920 #define RTW89_IQK_CHS_NR 2 4921 #define RTW89_IQK_PATH_NR 4 4922 4923 struct rtw89_lck_info { 4924 u8 thermal[RF_PATH_MAX]; 4925 }; 4926 4927 struct rtw89_rx_dck_info { 4928 u8 thermal[RF_PATH_MAX]; 4929 }; 4930 4931 struct rtw89_iqk_info { 4932 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4933 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4934 bool lok_fail[RTW89_IQK_PATH_NR]; 4935 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4936 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4937 u32 iqk_fail_cnt; 4938 bool is_iqk_init; 4939 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4940 u8 iqk_band[RTW89_IQK_PATH_NR]; 4941 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4942 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4943 u8 iqk_times; 4944 u8 version; 4945 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4946 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4947 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4948 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4949 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4950 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4951 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4952 bool is_nbiqk; 4953 bool iqk_fft_en; 4954 bool iqk_xym_en; 4955 bool iqk_sram_en; 4956 bool iqk_cfir_en; 4957 u32 syn1to2; 4958 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4959 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4960 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4961 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4962 }; 4963 4964 #define RTW89_DPK_RF_PATH 2 4965 #define RTW89_DPK_AVG_THERMAL_NUM 8 4966 #define RTW89_DPK_BKUP_NUM 2 4967 struct rtw89_dpk_bkup_para { 4968 enum rtw89_band band; 4969 enum rtw89_bandwidth bw; 4970 u8 ch; 4971 bool path_ok; 4972 u8 mdpd_en; 4973 u8 txagc_dpk; 4974 u8 ther_dpk; 4975 u8 gs; 4976 u16 pwsf; 4977 }; 4978 4979 struct rtw89_dpk_info { 4980 bool is_dpk_enable; 4981 bool is_dpk_reload_en; 4982 u8 dpk_gs[RTW89_PHY_NUM]; 4983 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4984 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4985 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4986 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4987 u8 cur_idx[RTW89_DPK_RF_PATH]; 4988 u8 cur_k_set; 4989 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4990 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 4991 u32 dpk_order[RTW89_DPK_RF_PATH]; 4992 }; 4993 4994 struct rtw89_fem_info { 4995 bool elna_2g; 4996 bool elna_5g; 4997 bool epa_2g; 4998 bool epa_5g; 4999 bool epa_6g; 5000 }; 5001 5002 struct rtw89_phy_ch_info { 5003 u8 rssi_min; 5004 u16 rssi_min_macid; 5005 u8 pre_rssi_min; 5006 u8 rssi_max; 5007 u16 rssi_max_macid; 5008 u8 rxsc_160; 5009 u8 rxsc_80; 5010 u8 rxsc_40; 5011 u8 rxsc_20; 5012 u8 rxsc_l; 5013 u8 is_noisy; 5014 }; 5015 5016 struct rtw89_agc_gaincode_set { 5017 u8 lna_idx; 5018 u8 tia_idx; 5019 u8 rxb_idx; 5020 }; 5021 5022 #define IGI_RSSI_TH_NUM 5 5023 #define FA_TH_NUM 4 5024 #define TIA_LNA_OP1DB_NUM 8 5025 #define LNA_GAIN_NUM 7 5026 #define TIA_GAIN_NUM 2 5027 struct rtw89_dig_info { 5028 struct rtw89_agc_gaincode_set cur_gaincode; 5029 bool force_gaincode_idx_en; 5030 struct rtw89_agc_gaincode_set force_gaincode; 5031 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5032 u16 fa_th[FA_TH_NUM]; 5033 u8 igi_rssi; 5034 u8 igi_fa_rssi; 5035 u8 fa_rssi_ofst; 5036 u8 dyn_igi_max; 5037 u8 dyn_igi_min; 5038 bool dyn_pd_th_en; 5039 u8 dyn_pd_th_max; 5040 u8 pd_low_th_ofst; 5041 u8 ib_pbk; 5042 s8 ib_pkpwr; 5043 s8 lna_gain_a[LNA_GAIN_NUM]; 5044 s8 lna_gain_g[LNA_GAIN_NUM]; 5045 s8 *lna_gain; 5046 s8 tia_gain_a[TIA_GAIN_NUM]; 5047 s8 tia_gain_g[TIA_GAIN_NUM]; 5048 s8 *tia_gain; 5049 bool is_linked_pre; 5050 bool bypass_dig; 5051 }; 5052 5053 enum rtw89_multi_cfo_mode { 5054 RTW89_PKT_BASED_AVG_MODE = 0, 5055 RTW89_ENTRY_BASED_AVG_MODE = 1, 5056 RTW89_TP_BASED_AVG_MODE = 2, 5057 }; 5058 5059 enum rtw89_phy_cfo_status { 5060 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5061 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5062 RTW89_PHY_DCFO_STATE_HOLD = 2, 5063 RTW89_PHY_DCFO_STATE_MAX 5064 }; 5065 5066 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5067 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5068 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5069 }; 5070 5071 struct rtw89_cfo_tracking_info { 5072 u16 cfo_timer_ms; 5073 bool cfo_trig_by_timer_en; 5074 enum rtw89_phy_cfo_status phy_cfo_status; 5075 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5076 u8 phy_cfo_trk_cnt; 5077 bool is_adjust; 5078 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5079 bool apply_compensation; 5080 u8 crystal_cap; 5081 u8 crystal_cap_default; 5082 u8 def_x_cap; 5083 s8 x_cap_ofst; 5084 u32 sta_cfo_tolerance; 5085 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5086 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5087 s32 cfo_avg_pre; 5088 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5089 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5090 s32 dcfo_avg; 5091 s32 dcfo_avg_pre; 5092 u32 packet_count; 5093 u32 packet_count_pre; 5094 s32 residual_cfo_acc; 5095 u8 phy_cfotrk_state; 5096 u8 phy_cfotrk_cnt; 5097 bool divergence_lock_en; 5098 u8 x_cap_lb; 5099 u8 x_cap_ub; 5100 u8 lock_cnt; 5101 }; 5102 5103 enum rtw89_tssi_mode { 5104 RTW89_TSSI_NORMAL = 0, 5105 RTW89_TSSI_SCAN = 1, 5106 }; 5107 5108 enum rtw89_tssi_alimk_band { 5109 TSSI_ALIMK_2G = 0, 5110 TSSI_ALIMK_5GL, 5111 TSSI_ALIMK_5GM, 5112 TSSI_ALIMK_5GH, 5113 TSSI_ALIMK_MAX 5114 }; 5115 5116 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5117 #define TSSI_TRIM_CH_GROUP_NUM 8 5118 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5119 5120 #define TSSI_CCK_CH_GROUP_NUM 6 5121 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5122 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5123 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5124 #define TSSI_MCS_CH_GROUP_NUM \ 5125 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5126 #define TSSI_MAX_CH_NUM 67 5127 #define TSSI_ALIMK_VALUE_NUM 8 5128 5129 struct rtw89_tssi_info { 5130 u8 thermal[RF_PATH_MAX]; 5131 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5132 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5133 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5134 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5135 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5136 s8 extra_ofst[RF_PATH_MAX]; 5137 bool tssi_tracking_check[RF_PATH_MAX]; 5138 u8 default_txagc_offset[RF_PATH_MAX]; 5139 u32 base_thermal[RF_PATH_MAX]; 5140 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5141 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5142 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5143 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5144 u32 tssi_alimk_time; 5145 }; 5146 5147 struct rtw89_power_trim_info { 5148 bool pg_thermal_trim; 5149 bool pg_pa_bias_trim; 5150 u8 thermal_trim[RF_PATH_MAX]; 5151 u8 pa_bias_trim[RF_PATH_MAX]; 5152 u8 pad_bias_trim[RF_PATH_MAX]; 5153 }; 5154 5155 enum rtw89_regd_func { 5156 RTW89_REGD_FUNC_TAS = 0, /* TAS (Time Average SAR) */ 5157 RTW89_REGD_FUNC_DAG = 1, /* DAG (Dynamic Antenna Gain) */ 5158 5159 NUM_OF_RTW89_REGD_FUNC, 5160 }; 5161 5162 struct rtw89_regd { 5163 char alpha2[3]; 5164 u8 txpwr_regd[RTW89_BAND_NUM]; 5165 DECLARE_BITMAP(func_bitmap, NUM_OF_RTW89_REGD_FUNC); 5166 }; 5167 5168 struct rtw89_regd_data { 5169 unsigned int nr; 5170 struct rtw89_regd map[] __counted_by(nr); 5171 }; 5172 5173 struct rtw89_regd_ctrl { 5174 unsigned int nr; 5175 const struct rtw89_regd *map; 5176 }; 5177 5178 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5179 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5180 #define RTW89_5GHZ_UNII4_START_INDEX 25 5181 5182 struct rtw89_regulatory_info { 5183 struct rtw89_regd_ctrl ctrl; 5184 const struct rtw89_regd *regd; 5185 enum rtw89_reg_6ghz_power reg_6ghz_power; 5186 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5187 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5188 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5189 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5190 }; 5191 5192 enum rtw89_ifs_clm_application { 5193 RTW89_IFS_CLM_INIT = 0, 5194 RTW89_IFS_CLM_BACKGROUND = 1, 5195 RTW89_IFS_CLM_ACS = 2, 5196 RTW89_IFS_CLM_DIG = 3, 5197 RTW89_IFS_CLM_TDMA_DIG = 4, 5198 RTW89_IFS_CLM_DBG = 5, 5199 RTW89_IFS_CLM_DBG_MANUAL = 6 5200 }; 5201 5202 enum rtw89_env_racing_lv { 5203 RTW89_RAC_RELEASE = 0, 5204 RTW89_RAC_LV_1 = 1, 5205 RTW89_RAC_LV_2 = 2, 5206 RTW89_RAC_LV_3 = 3, 5207 RTW89_RAC_LV_4 = 4, 5208 RTW89_RAC_MAX_NUM = 5 5209 }; 5210 5211 struct rtw89_ccx_para_info { 5212 enum rtw89_env_racing_lv rac_lv; 5213 u16 mntr_time; 5214 u8 nhm_manual_th_ofst; 5215 u8 nhm_manual_th0; 5216 enum rtw89_ifs_clm_application ifs_clm_app; 5217 u32 ifs_clm_manual_th_times; 5218 u32 ifs_clm_manual_th0; 5219 u8 fahm_manual_th_ofst; 5220 u8 fahm_manual_th0; 5221 u8 fahm_numer_opt; 5222 u8 fahm_denom_opt; 5223 }; 5224 5225 enum rtw89_ccx_edcca_opt_sc_idx { 5226 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5227 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5228 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5229 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5230 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5231 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5232 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5233 RTW89_CCX_EDCCA_SEG1_S3 = 7 5234 }; 5235 5236 enum rtw89_ccx_edcca_opt_bw_idx { 5237 RTW89_CCX_EDCCA_BW20_0 = 0, 5238 RTW89_CCX_EDCCA_BW20_1 = 1, 5239 RTW89_CCX_EDCCA_BW20_2 = 2, 5240 RTW89_CCX_EDCCA_BW20_3 = 3, 5241 RTW89_CCX_EDCCA_BW20_4 = 4, 5242 RTW89_CCX_EDCCA_BW20_5 = 5, 5243 RTW89_CCX_EDCCA_BW20_6 = 6, 5244 RTW89_CCX_EDCCA_BW20_7 = 7 5245 }; 5246 5247 #define RTW89_NHM_TH_NUM 11 5248 #define RTW89_FAHM_TH_NUM 11 5249 #define RTW89_NHM_RPT_NUM 12 5250 #define RTW89_FAHM_RPT_NUM 12 5251 #define RTW89_IFS_CLM_NUM 4 5252 struct rtw89_env_monitor_info { 5253 u8 ccx_watchdog_result; 5254 bool ccx_ongoing; 5255 u8 ccx_rac_lv; 5256 bool ccx_manual_ctrl; 5257 u16 ifs_clm_mntr_time; 5258 enum rtw89_ifs_clm_application ifs_clm_app; 5259 u16 ccx_period; 5260 u8 ccx_unit_idx; 5261 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5262 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5263 u16 ifs_clm_tx; 5264 u16 ifs_clm_edcca_excl_cca; 5265 u16 ifs_clm_ofdmfa; 5266 u16 ifs_clm_ofdmcca_excl_fa; 5267 u16 ifs_clm_cckfa; 5268 u16 ifs_clm_cckcca_excl_fa; 5269 u16 ifs_clm_total_ifs; 5270 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5271 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5272 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5273 u8 ifs_clm_tx_ratio; 5274 u8 ifs_clm_edcca_excl_cca_ratio; 5275 u8 ifs_clm_cck_fa_ratio; 5276 u8 ifs_clm_ofdm_fa_ratio; 5277 u8 ifs_clm_cck_cca_excl_fa_ratio; 5278 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5279 u16 ifs_clm_cck_fa_permil; 5280 u16 ifs_clm_ofdm_fa_permil; 5281 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5282 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5283 }; 5284 5285 enum rtw89_ser_rcvy_step { 5286 RTW89_SER_DRV_STOP_TX, 5287 RTW89_SER_DRV_STOP_RX, 5288 RTW89_SER_DRV_STOP_RUN, 5289 RTW89_SER_HAL_STOP_DMA, 5290 RTW89_SER_SUPPRESS_LOG, 5291 RTW89_NUM_OF_SER_FLAGS 5292 }; 5293 5294 struct rtw89_ser { 5295 u8 state; 5296 u8 alarm_event; 5297 bool prehandle_l1; 5298 5299 struct work_struct ser_hdl_work; 5300 struct delayed_work ser_alarm_work; 5301 const struct state_ent *st_tbl; 5302 const struct event_ent *ev_tbl; 5303 struct list_head msg_q; 5304 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5305 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5306 }; 5307 5308 enum rtw89_mac_ax_ps_mode { 5309 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5310 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5311 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5312 RTW89_MAC_AX_PS_MODE_MAX = 3, 5313 }; 5314 5315 enum rtw89_last_rpwm_mode { 5316 RTW89_LAST_RPWM_PS = 0x0, 5317 RTW89_LAST_RPWM_ACTIVE = 0x6, 5318 }; 5319 5320 struct rtw89_lps_parm { 5321 u8 macid; 5322 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5323 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5324 }; 5325 5326 struct rtw89_ppdu_sts_info { 5327 struct sk_buff_head rx_queue[RTW89_PHY_NUM]; 5328 u8 curr_rx_ppdu_cnt[RTW89_PHY_NUM]; 5329 }; 5330 5331 struct rtw89_early_h2c { 5332 struct list_head list; 5333 u8 *h2c; 5334 u16 h2c_len; 5335 }; 5336 5337 struct rtw89_hw_scan_info { 5338 struct rtw89_vif_link *scanning_vif; 5339 struct list_head pkt_list[NUM_NL80211_BANDS]; 5340 struct rtw89_chan op_chan; 5341 bool abort; 5342 u32 last_chan_idx; 5343 }; 5344 5345 enum rtw89_phy_bb_gain_band { 5346 RTW89_BB_GAIN_BAND_2G = 0, 5347 RTW89_BB_GAIN_BAND_5G_L = 1, 5348 RTW89_BB_GAIN_BAND_5G_M = 2, 5349 RTW89_BB_GAIN_BAND_5G_H = 3, 5350 RTW89_BB_GAIN_BAND_6G_L = 4, 5351 RTW89_BB_GAIN_BAND_6G_M = 5, 5352 RTW89_BB_GAIN_BAND_6G_H = 6, 5353 RTW89_BB_GAIN_BAND_6G_UH = 7, 5354 5355 RTW89_BB_GAIN_BAND_NR, 5356 }; 5357 5358 enum rtw89_phy_gain_band_be { 5359 RTW89_BB_GAIN_BAND_2G_BE = 0, 5360 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5361 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5362 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5363 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5364 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5365 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5366 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5367 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5368 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5369 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5370 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5371 5372 RTW89_BB_GAIN_BAND_NR_BE, 5373 }; 5374 5375 enum rtw89_phy_bb_bw_be { 5376 RTW89_BB_BW_20_40 = 0, 5377 RTW89_BB_BW_80_160_320 = 1, 5378 5379 RTW89_BB_BW_NR_BE, 5380 }; 5381 5382 enum rtw89_bw20_sc { 5383 RTW89_BW20_SC_20M = 1, 5384 RTW89_BW20_SC_40M = 2, 5385 RTW89_BW20_SC_80M = 4, 5386 RTW89_BW20_SC_160M = 8, 5387 RTW89_BW20_SC_320M = 16, 5388 }; 5389 5390 enum rtw89_cmac_table_bw { 5391 RTW89_CMAC_BW_20M = 0, 5392 RTW89_CMAC_BW_40M = 1, 5393 RTW89_CMAC_BW_80M = 2, 5394 RTW89_CMAC_BW_160M = 3, 5395 RTW89_CMAC_BW_320M = 4, 5396 5397 RTW89_CMAC_BW_NR, 5398 }; 5399 5400 enum rtw89_phy_bb_rxsc_num { 5401 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5402 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5403 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5404 }; 5405 5406 struct rtw89_phy_bb_gain_info { 5407 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5408 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5409 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5410 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5411 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5412 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5413 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5414 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5415 [RTW89_BB_RXSC_NUM_40]; 5416 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5417 [RTW89_BB_RXSC_NUM_80]; 5418 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5419 [RTW89_BB_RXSC_NUM_160]; 5420 }; 5421 5422 struct rtw89_phy_bb_gain_info_be { 5423 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5424 [LNA_GAIN_NUM]; 5425 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5426 [TIA_GAIN_NUM]; 5427 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5428 [RF_PATH_MAX][LNA_GAIN_NUM]; 5429 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5430 [RF_PATH_MAX][LNA_GAIN_NUM]; 5431 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5432 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5433 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5434 [RTW89_BW20_SC_20M]; 5435 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5436 [RTW89_BW20_SC_40M]; 5437 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5438 [RTW89_BW20_SC_80M]; 5439 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5440 [RTW89_BW20_SC_160M]; 5441 }; 5442 5443 struct rtw89_phy_efuse_gain { 5444 bool offset_valid; 5445 bool comp_valid; 5446 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5447 s8 offset_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5448 s8 rssi_base[RTW89_PHY_NUM]; /* S(8, 4) */ 5449 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5450 }; 5451 5452 #define RTW89_MAX_PATTERN_NUM 18 5453 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5454 #define RTW89_MAX_PATTERN_SIZE 128 5455 5456 struct rtw89_wow_cam_info { 5457 bool r_w; 5458 u8 idx; 5459 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5460 u16 crc; 5461 bool negative_pattern_match; 5462 bool skip_mac_hdr; 5463 bool uc; 5464 bool mc; 5465 bool bc; 5466 bool valid; 5467 }; 5468 5469 struct rtw89_wow_key_info { 5470 u8 ptk_tx_iv[8]; 5471 u8 valid_check; 5472 u8 symbol_check_en; 5473 u8 gtk_keyidx; 5474 u8 rsvd[5]; 5475 u8 ptk_rx_iv[8]; 5476 u8 gtk_rx_iv[4][8]; 5477 } __packed; 5478 5479 struct rtw89_wow_gtk_info { 5480 u8 kck[32]; 5481 u8 kek[32]; 5482 u8 tk1[16]; 5483 u8 txmickey[8]; 5484 u8 rxmickey[8]; 5485 __le32 igtk_keyid; 5486 __le64 ipn; 5487 u8 igtk[2][32]; 5488 u8 psk[32]; 5489 } __packed; 5490 5491 struct rtw89_wow_aoac_report { 5492 u8 rpt_ver; 5493 u8 sec_type; 5494 u8 key_idx; 5495 u8 pattern_idx; 5496 u8 rekey_ok; 5497 u8 ptk_tx_iv[8]; 5498 u8 eapol_key_replay_count[8]; 5499 u8 gtk[32]; 5500 u8 ptk_rx_iv[8]; 5501 u8 gtk_rx_iv[4][8]; 5502 u64 igtk_key_id; 5503 u64 igtk_ipn; 5504 u8 igtk[32]; 5505 u8 csa_pri_ch; 5506 u8 csa_bw; 5507 u8 csa_ch_offset; 5508 u8 csa_chsw_failed; 5509 u8 csa_ch_band; 5510 }; 5511 5512 struct rtw89_wow_param { 5513 struct rtw89_vif_link *rtwvif_link; 5514 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5515 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5516 struct rtw89_wow_key_info key_info; 5517 struct rtw89_wow_gtk_info gtk_info; 5518 struct rtw89_wow_aoac_report aoac_rpt; 5519 u8 pattern_cnt; 5520 u8 ptk_alg; 5521 u8 gtk_alg; 5522 u8 ptk_keyidx; 5523 u8 akm; 5524 5525 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5526 struct rtw89_wait_info wait; 5527 5528 bool pno_inited; 5529 struct list_head pno_pkt_list; 5530 struct cfg80211_sched_scan_request *nd_config; 5531 }; 5532 5533 struct rtw89_mcc_limit { 5534 bool enable; 5535 u16 max_tob; /* TU; max time offset behind */ 5536 u16 max_toa; /* TU; max time offset ahead */ 5537 u16 max_dur; /* TU */ 5538 }; 5539 5540 struct rtw89_mcc_policy { 5541 u8 c2h_rpt; 5542 u8 tx_null_early; 5543 u8 dis_tx_null; 5544 u8 in_curr_ch; 5545 u8 dis_sw_retry; 5546 u8 sw_retry_count; 5547 }; 5548 5549 struct rtw89_mcc_role { 5550 struct rtw89_vif_link *rtwvif_link; 5551 struct rtw89_mcc_policy policy; 5552 struct rtw89_mcc_limit limit; 5553 5554 /* only valid when running with FW MRC mechanism */ 5555 u8 slot_idx; 5556 5557 /* byte-array in LE order for FW */ 5558 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5559 5560 u16 duration; /* TU */ 5561 u16 beacon_interval; /* TU */ 5562 bool is_2ghz; 5563 bool is_go; 5564 bool is_gc; 5565 }; 5566 5567 struct rtw89_mcc_bt_role { 5568 u16 duration; /* TU */ 5569 }; 5570 5571 struct rtw89_mcc_courtesy { 5572 bool enable; 5573 u8 slot_num; 5574 u8 macid_src; 5575 u8 macid_tgt; 5576 }; 5577 5578 enum rtw89_mcc_plan { 5579 RTW89_MCC_PLAN_TAIL_BT, 5580 RTW89_MCC_PLAN_MID_BT, 5581 RTW89_MCC_PLAN_NO_BT, 5582 5583 NUM_OF_RTW89_MCC_PLAN, 5584 }; 5585 5586 struct rtw89_mcc_pattern { 5587 s16 tob_ref; /* TU; time offset behind of reference role */ 5588 s16 toa_ref; /* TU; time offset ahead of reference role */ 5589 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5590 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5591 5592 enum rtw89_mcc_plan plan; 5593 struct rtw89_mcc_courtesy courtesy; 5594 }; 5595 5596 struct rtw89_mcc_sync { 5597 bool enable; 5598 u16 offset; /* TU */ 5599 u8 macid_src; 5600 u8 band_src; 5601 u8 port_src; 5602 u8 macid_tgt; 5603 u8 band_tgt; 5604 u8 port_tgt; 5605 }; 5606 5607 struct rtw89_mcc_config { 5608 struct rtw89_mcc_pattern pattern; 5609 struct rtw89_mcc_sync sync; 5610 u64 start_tsf; 5611 u16 mcc_interval; /* TU */ 5612 u16 beacon_offset; /* TU */ 5613 }; 5614 5615 enum rtw89_mcc_mode { 5616 RTW89_MCC_MODE_GO_STA, 5617 RTW89_MCC_MODE_GC_STA, 5618 }; 5619 5620 struct rtw89_mcc_info { 5621 struct rtw89_wait_info wait; 5622 5623 u8 group; 5624 enum rtw89_mcc_mode mode; 5625 struct rtw89_mcc_role role_ref; /* reference role */ 5626 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5627 struct rtw89_mcc_bt_role bt_role; 5628 struct rtw89_mcc_config config; 5629 }; 5630 5631 struct rtw89_dev { 5632 struct ieee80211_hw *hw; 5633 struct device *dev; 5634 const struct ieee80211_ops *ops; 5635 5636 bool dbcc_en; 5637 bool support_mlo; 5638 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5639 struct rtw89_hw_scan_info scan_info; 5640 const struct rtw89_chip_info *chip; 5641 const struct rtw89_chip_variant *variant; 5642 const struct rtw89_pci_info *pci_info; 5643 const struct rtw89_rfe_parms *rfe_parms; 5644 struct rtw89_hal hal; 5645 struct rtw89_mcc_info mcc; 5646 struct rtw89_mac_info mac; 5647 struct rtw89_fw_info fw; 5648 struct rtw89_hci_info hci; 5649 struct rtw89_efuse efuse; 5650 struct rtw89_traffic_stats stats; 5651 struct rtw89_rfe_data *rfe_data; 5652 enum rtw89_custid custid; 5653 5654 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 5655 refcount_t refcount_ap_info; 5656 5657 struct list_head rtwvifs_list; 5658 /* used to protect rf read write */ 5659 struct mutex rf_mutex; 5660 struct workqueue_struct *txq_wq; 5661 struct work_struct txq_work; 5662 struct delayed_work txq_reinvoke_work; 5663 /* used to protect ba_list and forbid_ba_list */ 5664 spinlock_t ba_lock; 5665 /* txqs to setup ba session */ 5666 struct list_head ba_list; 5667 /* txqs to forbid ba session */ 5668 struct list_head forbid_ba_list; 5669 struct work_struct ba_work; 5670 /* used to protect rpwm */ 5671 spinlock_t rpwm_lock; 5672 5673 struct rtw89_cam_info cam_info; 5674 5675 struct sk_buff_head c2h_queue; 5676 struct wiphy_work c2h_work; 5677 struct wiphy_work ips_work; 5678 struct wiphy_work cancel_6ghz_probe_work; 5679 struct work_struct load_firmware_work; 5680 5681 struct list_head early_h2c_list; 5682 5683 struct rtw89_ser ser; 5684 5685 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5686 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5687 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5688 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5689 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5690 5691 struct rtw89_phy_stat phystat; 5692 struct rtw89_rfk_wait_info rfk_wait; 5693 struct rtw89_dack_info dack; 5694 struct rtw89_iqk_info iqk; 5695 struct rtw89_dpk_info dpk; 5696 struct rtw89_rfk_mcc_info rfk_mcc; 5697 struct rtw89_lck_info lck; 5698 struct rtw89_rx_dck_info rx_dck; 5699 bool is_tssi_mode[RF_PATH_MAX]; 5700 bool is_bt_iqk_timeout; 5701 5702 struct rtw89_fem_info fem; 5703 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5704 struct rtw89_tssi_info tssi; 5705 struct rtw89_power_trim_info pwr_trim; 5706 5707 struct rtw89_cfo_tracking_info cfo_tracking; 5708 union { 5709 struct rtw89_phy_bb_gain_info ax; 5710 struct rtw89_phy_bb_gain_info_be be; 5711 } bb_gain; 5712 struct rtw89_phy_efuse_gain efuse_gain; 5713 struct rtw89_phy_ul_tb_info ul_tb_info; 5714 struct rtw89_antdiv_info antdiv; 5715 5716 struct rtw89_bb_ctx { 5717 enum rtw89_phy_idx phy_idx; 5718 struct rtw89_env_monitor_info env_monitor; 5719 struct rtw89_dig_info dig; 5720 struct rtw89_phy_ch_info ch_info; 5721 struct rtw89_edcca_bak edcca_bak; 5722 } bbs[RTW89_PHY_NUM]; 5723 5724 struct wiphy_delayed_work track_work; 5725 struct wiphy_delayed_work chanctx_work; 5726 struct wiphy_delayed_work coex_act1_work; 5727 struct wiphy_delayed_work coex_bt_devinfo_work; 5728 struct wiphy_delayed_work coex_rfk_chk_work; 5729 struct wiphy_delayed_work cfo_track_work; 5730 struct delayed_work forbid_ba_work; 5731 struct wiphy_delayed_work antdiv_work; 5732 struct rtw89_ppdu_sts_info ppdu_sts; 5733 u8 total_sta_assoc; 5734 bool scanning; 5735 5736 struct rtw89_regulatory_info regulatory; 5737 struct rtw89_sar_info sar; 5738 struct rtw89_tas_info tas; 5739 struct rtw89_ant_gain_info ant_gain; 5740 5741 struct rtw89_btc btc; 5742 enum rtw89_ps_mode ps_mode; 5743 bool lps_enabled; 5744 5745 struct rtw89_wow_param wow; 5746 5747 /* napi structure */ 5748 struct net_device *netdev; 5749 struct napi_struct napi; 5750 int napi_budget_countdown; 5751 5752 struct rtw89_debugfs *debugfs; 5753 5754 /* HCI related data, keep last */ 5755 u8 priv[] __aligned(sizeof(void *)); 5756 }; 5757 5758 struct rtw89_link_conf_container { 5759 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 5760 }; 5761 5762 #define RTW89_VIF_IDLE_LINK_ID 0 5763 5764 struct rtw89_vif { 5765 struct rtw89_dev *rtwdev; 5766 struct list_head list; 5767 struct list_head mgnt_entry; 5768 struct rtw89_link_conf_container __rcu *snap_link_confs; 5769 5770 u8 mac_addr[ETH_ALEN]; 5771 __be32 ip_addr; 5772 5773 struct rtw89_traffic_stats stats; 5774 u32 tdls_peer; 5775 5776 struct ieee80211_scan_ies *scan_ies; 5777 struct cfg80211_scan_request *scan_req; 5778 5779 struct rtw89_roc roc; 5780 bool offchan; 5781 5782 u8 links_inst_valid_num; 5783 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5784 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5785 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 5786 }; 5787 5788 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 5789 const struct rtw89_vif *rtwvif, 5790 unsigned int link_id) 5791 { 5792 *rtwvif_link = rtwvif->links[link_id]; 5793 return !!*rtwvif_link; 5794 } 5795 5796 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 5797 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5798 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 5799 5800 enum rtw89_sta_flags { 5801 RTW89_REMOTE_STA_IN_PS, 5802 5803 NUM_OF_RTW89_STA_FLAGS, 5804 }; 5805 5806 struct rtw89_sta { 5807 struct rtw89_dev *rtwdev; 5808 struct rtw89_vif *rtwvif; 5809 5810 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 5811 5812 bool disassoc; 5813 5814 struct sk_buff_head roc_queue; 5815 5816 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 5817 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 5818 5819 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 5820 5821 u8 links_inst_valid_num; 5822 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5823 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5824 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 5825 }; 5826 5827 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 5828 const struct rtw89_sta *rtwsta, 5829 unsigned int link_id) 5830 { 5831 *rtwsta_link = rtwsta->links[link_id]; 5832 return !!*rtwsta_link; 5833 } 5834 5835 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 5836 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5837 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 5838 5839 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 5840 { 5841 /* const after init, so no need to check if active first */ 5842 return rtwvif->links_inst[0].mac_id; 5843 } 5844 5845 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 5846 { 5847 /* const after init, so no need to check if active first */ 5848 return rtwvif->links_inst[0].port; 5849 } 5850 5851 static inline struct rtw89_vif_link * 5852 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 5853 { 5854 if (index >= rtwvif->links_inst_valid_num || 5855 !test_bit(index, rtwvif->links_inst_map)) 5856 return NULL; 5857 return &rtwvif->links_inst[index]; 5858 } 5859 5860 static inline 5861 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 5862 { 5863 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5864 5865 return rtwvif_link - rtwvif->links_inst; 5866 } 5867 5868 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 5869 { 5870 /* const after init, so no need to check if active first */ 5871 return rtwsta->links_inst[0].mac_id; 5872 } 5873 5874 static inline struct rtw89_sta_link * 5875 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 5876 { 5877 if (index >= rtwsta->links_inst_valid_num || 5878 !test_bit(index, rtwsta->links_inst_map)) 5879 return NULL; 5880 return &rtwsta->links_inst[index]; 5881 } 5882 5883 static inline 5884 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 5885 { 5886 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5887 5888 return rtwsta_link - rtwsta->links_inst; 5889 } 5890 5891 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 5892 { 5893 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5894 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5895 5896 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5897 rtwsta_link); 5898 } 5899 5900 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 5901 { 5902 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5903 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5904 5905 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5906 NULL); 5907 synchronize_rcu(); 5908 } 5909 5910 static inline struct rtw89_sta_link * 5911 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 5912 { 5913 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 5914 } 5915 5916 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5917 struct rtw89_core_tx_request *tx_req) 5918 { 5919 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5920 } 5921 5922 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5923 { 5924 rtwdev->hci.ops->reset(rtwdev); 5925 } 5926 5927 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5928 { 5929 return rtwdev->hci.ops->start(rtwdev); 5930 } 5931 5932 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5933 { 5934 rtwdev->hci.ops->stop(rtwdev); 5935 } 5936 5937 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5938 { 5939 return rtwdev->hci.ops->deinit(rtwdev); 5940 } 5941 5942 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5943 { 5944 rtwdev->hci.ops->pause(rtwdev, pause); 5945 } 5946 5947 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5948 { 5949 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5950 } 5951 5952 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5953 { 5954 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5955 } 5956 5957 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5958 { 5959 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5960 } 5961 5962 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5963 { 5964 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5965 } 5966 5967 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5968 { 5969 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5970 } 5971 5972 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5973 bool drop) 5974 { 5975 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5976 return; 5977 5978 if (rtwdev->hci.ops->flush_queues) 5979 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5980 } 5981 5982 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5983 { 5984 if (rtwdev->hci.ops->recovery_start) 5985 rtwdev->hci.ops->recovery_start(rtwdev); 5986 } 5987 5988 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5989 { 5990 if (rtwdev->hci.ops->recovery_complete) 5991 rtwdev->hci.ops->recovery_complete(rtwdev); 5992 } 5993 5994 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5995 { 5996 if (rtwdev->hci.ops->enable_intr) 5997 rtwdev->hci.ops->enable_intr(rtwdev); 5998 } 5999 6000 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 6001 { 6002 if (rtwdev->hci.ops->disable_intr) 6003 rtwdev->hci.ops->disable_intr(rtwdev); 6004 } 6005 6006 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 6007 { 6008 if (rtwdev->hci.ops->ctrl_txdma_ch) 6009 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 6010 } 6011 6012 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 6013 { 6014 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 6015 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 6016 } 6017 6018 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 6019 { 6020 if (rtwdev->hci.ops->ctrl_trxhci) 6021 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 6022 } 6023 6024 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 6025 { 6026 int ret = 0; 6027 6028 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6029 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6030 return ret; 6031 } 6032 6033 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6034 { 6035 if (rtwdev->hci.ops->clr_idx_all) 6036 rtwdev->hci.ops->clr_idx_all(rtwdev); 6037 } 6038 6039 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6040 { 6041 int ret = 0; 6042 6043 if (rtwdev->hci.ops->rst_bdram) 6044 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6045 return ret; 6046 } 6047 6048 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6049 { 6050 if (rtwdev->hci.ops->clear) 6051 rtwdev->hci.ops->clear(rtwdev, pdev); 6052 } 6053 6054 static inline 6055 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6056 { 6057 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6058 6059 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 6060 } 6061 6062 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6063 { 6064 return rtwdev->hci.ops->read8(rtwdev, addr); 6065 } 6066 6067 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6068 { 6069 return rtwdev->hci.ops->read16(rtwdev, addr); 6070 } 6071 6072 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6073 { 6074 return rtwdev->hci.ops->read32(rtwdev, addr); 6075 } 6076 6077 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6078 { 6079 rtwdev->hci.ops->write8(rtwdev, addr, data); 6080 } 6081 6082 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6083 { 6084 rtwdev->hci.ops->write16(rtwdev, addr, data); 6085 } 6086 6087 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6088 { 6089 rtwdev->hci.ops->write32(rtwdev, addr, data); 6090 } 6091 6092 static inline void 6093 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6094 { 6095 u8 val; 6096 6097 val = rtw89_read8(rtwdev, addr); 6098 rtw89_write8(rtwdev, addr, val | bit); 6099 } 6100 6101 static inline void 6102 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6103 { 6104 u16 val; 6105 6106 val = rtw89_read16(rtwdev, addr); 6107 rtw89_write16(rtwdev, addr, val | bit); 6108 } 6109 6110 static inline void 6111 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6112 { 6113 u32 val; 6114 6115 val = rtw89_read32(rtwdev, addr); 6116 rtw89_write32(rtwdev, addr, val | bit); 6117 } 6118 6119 static inline void 6120 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6121 { 6122 u8 val; 6123 6124 val = rtw89_read8(rtwdev, addr); 6125 rtw89_write8(rtwdev, addr, val & ~bit); 6126 } 6127 6128 static inline void 6129 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6130 { 6131 u16 val; 6132 6133 val = rtw89_read16(rtwdev, addr); 6134 rtw89_write16(rtwdev, addr, val & ~bit); 6135 } 6136 6137 static inline void 6138 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6139 { 6140 u32 val; 6141 6142 val = rtw89_read32(rtwdev, addr); 6143 rtw89_write32(rtwdev, addr, val & ~bit); 6144 } 6145 6146 static inline u32 6147 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6148 { 6149 u32 shift = __ffs(mask); 6150 u32 orig; 6151 u32 ret; 6152 6153 orig = rtw89_read32(rtwdev, addr); 6154 ret = (orig & mask) >> shift; 6155 6156 return ret; 6157 } 6158 6159 static inline u16 6160 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6161 { 6162 u32 shift = __ffs(mask); 6163 u32 orig; 6164 u32 ret; 6165 6166 orig = rtw89_read16(rtwdev, addr); 6167 ret = (orig & mask) >> shift; 6168 6169 return ret; 6170 } 6171 6172 static inline u8 6173 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6174 { 6175 u32 shift = __ffs(mask); 6176 u32 orig; 6177 u32 ret; 6178 6179 orig = rtw89_read8(rtwdev, addr); 6180 ret = (orig & mask) >> shift; 6181 6182 return ret; 6183 } 6184 6185 static inline void 6186 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6187 { 6188 u32 shift = __ffs(mask); 6189 u32 orig; 6190 u32 set; 6191 6192 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6193 6194 orig = rtw89_read32(rtwdev, addr); 6195 set = (orig & ~mask) | ((data << shift) & mask); 6196 rtw89_write32(rtwdev, addr, set); 6197 } 6198 6199 static inline void 6200 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6201 { 6202 u32 shift; 6203 u16 orig, set; 6204 6205 mask &= 0xffff; 6206 shift = __ffs(mask); 6207 6208 orig = rtw89_read16(rtwdev, addr); 6209 set = (orig & ~mask) | ((data << shift) & mask); 6210 rtw89_write16(rtwdev, addr, set); 6211 } 6212 6213 static inline void 6214 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6215 { 6216 u32 shift; 6217 u8 orig, set; 6218 6219 mask &= 0xff; 6220 shift = __ffs(mask); 6221 6222 orig = rtw89_read8(rtwdev, addr); 6223 set = (orig & ~mask) | ((data << shift) & mask); 6224 rtw89_write8(rtwdev, addr, set); 6225 } 6226 6227 static inline u32 6228 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6229 u32 addr, u32 mask) 6230 { 6231 u32 val; 6232 6233 mutex_lock(&rtwdev->rf_mutex); 6234 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6235 mutex_unlock(&rtwdev->rf_mutex); 6236 6237 return val; 6238 } 6239 6240 static inline void 6241 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6242 u32 addr, u32 mask, u32 data) 6243 { 6244 mutex_lock(&rtwdev->rf_mutex); 6245 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6246 mutex_unlock(&rtwdev->rf_mutex); 6247 } 6248 6249 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6250 { 6251 void *p = rtwtxq; 6252 6253 return container_of(p, struct ieee80211_txq, drv_priv); 6254 } 6255 6256 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6257 struct ieee80211_txq *txq) 6258 { 6259 struct rtw89_txq *rtwtxq; 6260 6261 if (!txq) 6262 return; 6263 6264 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6265 INIT_LIST_HEAD(&rtwtxq->list); 6266 } 6267 6268 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6269 { 6270 void *p = rtwvif; 6271 6272 return container_of(p, struct ieee80211_vif, drv_priv); 6273 } 6274 6275 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6276 { 6277 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6278 } 6279 6280 static inline 6281 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6282 { 6283 return rtwvif_to_vif(rtwvif_link->rtwvif); 6284 } 6285 6286 static inline 6287 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6288 { 6289 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6290 } 6291 6292 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6293 { 6294 return (struct rtw89_vif *)vif->drv_priv; 6295 } 6296 6297 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6298 { 6299 return vif ? vif_to_rtwvif(vif) : NULL; 6300 } 6301 6302 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6303 { 6304 void *p = rtwsta; 6305 6306 return container_of(p, struct ieee80211_sta, drv_priv); 6307 } 6308 6309 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6310 { 6311 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6312 } 6313 6314 static inline 6315 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6316 { 6317 return rtwsta_to_sta(rtwsta_link->rtwsta); 6318 } 6319 6320 static inline 6321 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6322 { 6323 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6324 } 6325 6326 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6327 { 6328 return (struct rtw89_sta *)sta->drv_priv; 6329 } 6330 6331 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6332 { 6333 return sta ? sta_to_rtwsta(sta) : NULL; 6334 } 6335 6336 static inline struct ieee80211_bss_conf * 6337 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6338 { 6339 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6340 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6341 struct rtw89_link_conf_container *snap; 6342 struct ieee80211_bss_conf *bss_conf; 6343 6344 snap = rcu_dereference(rtwvif->snap_link_confs); 6345 if (snap) { 6346 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6347 goto out; 6348 } 6349 6350 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6351 6352 out: 6353 if (unlikely(!bss_conf)) { 6354 *nolink = true; 6355 return &vif->bss_conf; 6356 } 6357 6358 *nolink = false; 6359 return bss_conf; 6360 } 6361 6362 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6363 ({ \ 6364 typeof(rtwvif_link) p = rtwvif_link; \ 6365 struct ieee80211_bss_conf *bss_conf; \ 6366 bool nolink; \ 6367 \ 6368 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6369 if (unlikely(nolink) && (assert)) \ 6370 rtw89_err(p->rtwvif->rtwdev, \ 6371 "%s: cannot find exact bss_conf for link_id %u\n",\ 6372 __func__, p->link_id); \ 6373 bss_conf; \ 6374 }) 6375 6376 static inline struct ieee80211_link_sta * 6377 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6378 { 6379 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6380 struct ieee80211_link_sta *link_sta; 6381 6382 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6383 if (unlikely(!link_sta)) { 6384 *nolink = true; 6385 return &sta->deflink; 6386 } 6387 6388 *nolink = false; 6389 return link_sta; 6390 } 6391 6392 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6393 ({ \ 6394 typeof(rtwsta_link) p = rtwsta_link; \ 6395 struct ieee80211_link_sta *link_sta; \ 6396 bool nolink; \ 6397 \ 6398 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6399 if (unlikely(nolink) && (assert)) \ 6400 rtw89_err(p->rtwsta->rtwdev, \ 6401 "%s: cannot find exact link_sta for link_id %u\n",\ 6402 __func__, p->link_id); \ 6403 link_sta; \ 6404 }) 6405 6406 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6407 { 6408 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6409 return RATE_INFO_BW_160; 6410 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6411 return RATE_INFO_BW_80; 6412 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6413 return RATE_INFO_BW_40; 6414 else 6415 return RATE_INFO_BW_20; 6416 } 6417 6418 static inline 6419 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6420 { 6421 switch (hw_band) { 6422 default: 6423 case RTW89_BAND_2G: 6424 return NL80211_BAND_2GHZ; 6425 case RTW89_BAND_5G: 6426 return NL80211_BAND_5GHZ; 6427 case RTW89_BAND_6G: 6428 return NL80211_BAND_6GHZ; 6429 } 6430 } 6431 6432 static inline 6433 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6434 { 6435 switch (nl_band) { 6436 default: 6437 case NL80211_BAND_2GHZ: 6438 return RTW89_BAND_2G; 6439 case NL80211_BAND_5GHZ: 6440 return RTW89_BAND_5G; 6441 case NL80211_BAND_6GHZ: 6442 return RTW89_BAND_6G; 6443 } 6444 } 6445 6446 static inline 6447 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6448 { 6449 switch (width) { 6450 default: 6451 WARN(1, "Not support bandwidth %d\n", width); 6452 fallthrough; 6453 case NL80211_CHAN_WIDTH_20_NOHT: 6454 case NL80211_CHAN_WIDTH_20: 6455 return RTW89_CHANNEL_WIDTH_20; 6456 case NL80211_CHAN_WIDTH_40: 6457 return RTW89_CHANNEL_WIDTH_40; 6458 case NL80211_CHAN_WIDTH_80: 6459 return RTW89_CHANNEL_WIDTH_80; 6460 case NL80211_CHAN_WIDTH_160: 6461 return RTW89_CHANNEL_WIDTH_160; 6462 } 6463 } 6464 6465 static inline 6466 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6467 { 6468 switch (rua) { 6469 default: 6470 WARN(1, "Invalid RU allocation: %d\n", rua); 6471 fallthrough; 6472 case 0 ... 36: 6473 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6474 case 37 ... 52: 6475 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6476 case 53 ... 60: 6477 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6478 case 61 ... 64: 6479 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6480 case 65 ... 66: 6481 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6482 case 67: 6483 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6484 case 68: 6485 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6486 } 6487 } 6488 6489 static inline 6490 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6491 struct rtw89_sta_link *rtwsta_link) 6492 { 6493 if (rtwsta_link) { 6494 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6495 6496 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6497 return &rtwsta_link->addr_cam; 6498 } 6499 return &rtwvif_link->addr_cam; 6500 } 6501 6502 static inline 6503 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6504 struct rtw89_sta_link *rtwsta_link) 6505 { 6506 if (rtwsta_link) { 6507 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6508 6509 if (sta->tdls) 6510 return &rtwsta_link->bssid_cam; 6511 } 6512 return &rtwvif_link->bssid_cam; 6513 } 6514 6515 static inline 6516 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6517 struct rtw89_channel_help_params *p, 6518 const struct rtw89_chan *chan, 6519 enum rtw89_mac_idx mac_idx, 6520 enum rtw89_phy_idx phy_idx) 6521 { 6522 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6523 mac_idx, phy_idx); 6524 } 6525 6526 static inline 6527 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6528 struct rtw89_channel_help_params *p, 6529 const struct rtw89_chan *chan, 6530 enum rtw89_mac_idx mac_idx, 6531 enum rtw89_phy_idx phy_idx) 6532 { 6533 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6534 mac_idx, phy_idx); 6535 } 6536 6537 static inline 6538 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6539 enum rtw89_chanctx_idx idx) 6540 { 6541 struct rtw89_hal *hal = &rtwdev->hal; 6542 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6543 6544 if (roc_idx == idx) 6545 return &hal->roc_chandef; 6546 6547 return &hal->chanctx[idx].chandef; 6548 } 6549 6550 static inline 6551 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6552 enum rtw89_chanctx_idx idx) 6553 { 6554 struct rtw89_hal *hal = &rtwdev->hal; 6555 6556 return &hal->chanctx[idx].chan; 6557 } 6558 6559 static inline 6560 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6561 enum rtw89_chanctx_idx idx) 6562 { 6563 struct rtw89_hal *hal = &rtwdev->hal; 6564 6565 return &hal->chanctx[idx].rcd; 6566 } 6567 6568 static inline 6569 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6570 { 6571 const struct rtw89_chanctx *chanctx = 6572 container_of_const(chan, struct rtw89_chanctx, chan); 6573 6574 return &chanctx->rcd; 6575 } 6576 6577 static inline 6578 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6579 { 6580 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6581 6582 if (rtwvif_link) 6583 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6584 else 6585 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6586 } 6587 6588 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6589 { 6590 const struct rtw89_chip_info *chip = rtwdev->chip; 6591 6592 if (chip->ops->fem_setup) 6593 chip->ops->fem_setup(rtwdev); 6594 } 6595 6596 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6597 { 6598 const struct rtw89_chip_info *chip = rtwdev->chip; 6599 6600 if (chip->ops->rfe_gpio) 6601 chip->ops->rfe_gpio(rtwdev); 6602 } 6603 6604 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6605 { 6606 const struct rtw89_chip_info *chip = rtwdev->chip; 6607 6608 if (chip->ops->rfk_hw_init) 6609 chip->ops->rfk_hw_init(rtwdev); 6610 } 6611 6612 static inline 6613 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6614 { 6615 const struct rtw89_chip_info *chip = rtwdev->chip; 6616 6617 if (chip->ops->bb_preinit) 6618 chip->ops->bb_preinit(rtwdev, phy_idx); 6619 } 6620 6621 static inline 6622 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6623 { 6624 const struct rtw89_chip_info *chip = rtwdev->chip; 6625 6626 if (!chip->ops->bb_postinit) 6627 return; 6628 6629 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6630 6631 if (rtwdev->dbcc_en) 6632 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6633 } 6634 6635 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6636 { 6637 const struct rtw89_chip_info *chip = rtwdev->chip; 6638 6639 if (chip->ops->bb_sethw) 6640 chip->ops->bb_sethw(rtwdev); 6641 } 6642 6643 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6644 { 6645 const struct rtw89_chip_info *chip = rtwdev->chip; 6646 6647 if (chip->ops->rfk_init) 6648 chip->ops->rfk_init(rtwdev); 6649 } 6650 6651 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6652 { 6653 const struct rtw89_chip_info *chip = rtwdev->chip; 6654 6655 if (chip->ops->rfk_init_late) 6656 chip->ops->rfk_init_late(rtwdev); 6657 } 6658 6659 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6660 struct rtw89_vif_link *rtwvif_link) 6661 { 6662 const struct rtw89_chip_info *chip = rtwdev->chip; 6663 6664 if (chip->ops->rfk_channel) 6665 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6666 } 6667 6668 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6669 enum rtw89_phy_idx phy_idx, 6670 const struct rtw89_chan *chan) 6671 { 6672 const struct rtw89_chip_info *chip = rtwdev->chip; 6673 6674 if (chip->ops->rfk_band_changed) 6675 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6676 } 6677 6678 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6679 struct rtw89_vif_link *rtwvif_link, bool start) 6680 { 6681 const struct rtw89_chip_info *chip = rtwdev->chip; 6682 6683 if (chip->ops->rfk_scan) 6684 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6685 } 6686 6687 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6688 { 6689 const struct rtw89_chip_info *chip = rtwdev->chip; 6690 6691 if (chip->ops->rfk_track) 6692 chip->ops->rfk_track(rtwdev); 6693 } 6694 6695 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6696 { 6697 const struct rtw89_chip_info *chip = rtwdev->chip; 6698 6699 if (!chip->ops->set_txpwr_ctrl) 6700 return; 6701 6702 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6703 if (rtwdev->dbcc_en) 6704 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6705 } 6706 6707 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6708 { 6709 const struct rtw89_chip_info *chip = rtwdev->chip; 6710 6711 if (chip->ops->power_trim) 6712 chip->ops->power_trim(rtwdev); 6713 } 6714 6715 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6716 enum rtw89_phy_idx phy_idx) 6717 { 6718 const struct rtw89_chip_info *chip = rtwdev->chip; 6719 6720 if (chip->ops->init_txpwr_unit) 6721 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6722 } 6723 6724 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6725 { 6726 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6727 if (rtwdev->dbcc_en) 6728 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6729 } 6730 6731 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6732 enum rtw89_rf_path rf_path) 6733 { 6734 const struct rtw89_chip_info *chip = rtwdev->chip; 6735 6736 if (!chip->ops->get_thermal) 6737 return 0x10; 6738 6739 return chip->ops->get_thermal(rtwdev, rf_path); 6740 } 6741 6742 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6743 struct rtw89_rx_phy_ppdu *phy_ppdu, 6744 struct ieee80211_rx_status *status) 6745 { 6746 const struct rtw89_chip_info *chip = rtwdev->chip; 6747 6748 if (chip->ops->query_ppdu) 6749 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6750 } 6751 6752 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 6753 struct rtw89_rx_phy_ppdu *phy_ppdu) 6754 { 6755 const struct rtw89_chip_info *chip = rtwdev->chip; 6756 6757 if (chip->ops->convert_rpl_to_rssi) 6758 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 6759 } 6760 6761 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 6762 struct rtw89_rx_desc_info *desc_info, 6763 struct ieee80211_rx_status *rx_status) 6764 { 6765 const struct rtw89_chip_info *chip = rtwdev->chip; 6766 6767 if (chip->ops->phy_rpt_to_rssi) 6768 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 6769 } 6770 6771 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6772 enum rtw89_phy_idx phy_idx) 6773 { 6774 const struct rtw89_chip_info *chip = rtwdev->chip; 6775 6776 if (chip->ops->ctrl_nbtg_bt_tx) 6777 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6778 } 6779 6780 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6781 { 6782 const struct rtw89_chip_info *chip = rtwdev->chip; 6783 6784 if (chip->ops->cfg_txrx_path) 6785 chip->ops->cfg_txrx_path(rtwdev); 6786 } 6787 6788 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 6789 enum rtw89_phy_idx phy_idx) 6790 { 6791 const struct rtw89_chip_info *chip = rtwdev->chip; 6792 6793 if (chip->ops->digital_pwr_comp) 6794 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 6795 } 6796 6797 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6798 const struct rtw89_txpwr_table *tbl) 6799 { 6800 tbl->load(rtwdev, tbl); 6801 } 6802 6803 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6804 { 6805 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6806 6807 return regd->txpwr_regd[band]; 6808 } 6809 6810 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6811 enum rtw89_phy_idx phy_idx) 6812 { 6813 const struct rtw89_chip_info *chip = rtwdev->chip; 6814 6815 if (chip->ops->ctrl_btg_bt_rx) 6816 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6817 } 6818 6819 static inline 6820 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6821 struct rtw89_rx_desc_info *desc_info, 6822 u8 *data, u32 data_offset) 6823 { 6824 const struct rtw89_chip_info *chip = rtwdev->chip; 6825 6826 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6827 } 6828 6829 static inline 6830 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6831 struct rtw89_tx_desc_info *desc_info, 6832 void *txdesc) 6833 { 6834 const struct rtw89_chip_info *chip = rtwdev->chip; 6835 6836 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6837 } 6838 6839 static inline 6840 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6841 struct rtw89_tx_desc_info *desc_info, 6842 void *txdesc) 6843 { 6844 const struct rtw89_chip_info *chip = rtwdev->chip; 6845 6846 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6847 } 6848 6849 static inline 6850 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6851 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6852 { 6853 const struct rtw89_chip_info *chip = rtwdev->chip; 6854 6855 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6856 } 6857 6858 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6859 { 6860 const struct rtw89_chip_info *chip = rtwdev->chip; 6861 6862 chip->ops->cfg_ctrl_path(rtwdev, wl); 6863 } 6864 6865 static inline 6866 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6867 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6868 { 6869 const struct rtw89_chip_info *chip = rtwdev->chip; 6870 6871 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6872 } 6873 6874 static inline 6875 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6876 { 6877 const struct rtw89_chip_info *chip = rtwdev->chip; 6878 6879 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6880 } 6881 6882 static inline 6883 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6884 struct rtw89_vif_link *rtwvif_link, 6885 struct rtw89_sta_link *rtwsta_link) 6886 { 6887 const struct rtw89_chip_info *chip = rtwdev->chip; 6888 6889 if (!chip->ops->h2c_dctl_sec_cam) 6890 return 0; 6891 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 6892 } 6893 6894 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6895 { 6896 __le16 fc = hdr->frame_control; 6897 6898 if (ieee80211_has_tods(fc)) 6899 return hdr->addr1; 6900 else if (ieee80211_has_fromds(fc)) 6901 return hdr->addr2; 6902 else 6903 return hdr->addr3; 6904 } 6905 6906 static inline 6907 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 6908 { 6909 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6910 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6911 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 6912 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6913 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 6914 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6915 return true; 6916 return false; 6917 } 6918 6919 static inline 6920 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 6921 { 6922 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 6923 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 6924 return true; 6925 6926 return false; 6927 } 6928 6929 static inline 6930 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 6931 { 6932 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 6933 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 6934 return true; 6935 6936 return false; 6937 } 6938 6939 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6940 enum rtw89_fw_type type) 6941 { 6942 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6943 6944 switch (type) { 6945 case RTW89_FW_WOWLAN: 6946 return &fw_info->wowlan; 6947 case RTW89_FW_LOGFMT: 6948 return &fw_info->log.suit; 6949 case RTW89_FW_BBMCU0: 6950 return &fw_info->bbmcu0; 6951 case RTW89_FW_BBMCU1: 6952 return &fw_info->bbmcu1; 6953 default: 6954 break; 6955 } 6956 6957 return &fw_info->normal; 6958 } 6959 6960 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6961 unsigned int length) 6962 { 6963 struct sk_buff *skb; 6964 6965 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6966 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6967 if (!skb) 6968 return NULL; 6969 6970 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6971 return skb; 6972 } 6973 6974 return dev_alloc_skb(length); 6975 } 6976 6977 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6978 struct rtw89_tx_skb_data *skb_data, 6979 bool tx_done) 6980 { 6981 struct rtw89_tx_wait_info *wait; 6982 6983 rcu_read_lock(); 6984 6985 wait = rcu_dereference(skb_data->wait); 6986 if (!wait) 6987 goto out; 6988 6989 wait->tx_done = tx_done; 6990 complete(&wait->completion); 6991 6992 out: 6993 rcu_read_unlock(); 6994 } 6995 6996 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6997 { 6998 switch (rtwdev->mlo_dbcc_mode) { 6999 case MLO_1_PLUS_1_1RF: 7000 case MLO_1_PLUS_1_2RF: 7001 case DBCC_LEGACY: 7002 return true; 7003 default: 7004 return false; 7005 } 7006 } 7007 7008 static inline u8 rtw89_get_active_phy_bitmap(struct rtw89_dev *rtwdev) 7009 { 7010 if (!rtwdev->dbcc_en) 7011 return BIT(RTW89_PHY_0); 7012 7013 switch (rtwdev->mlo_dbcc_mode) { 7014 case MLO_0_PLUS_2_1RF: 7015 case MLO_0_PLUS_2_2RF: 7016 return BIT(RTW89_PHY_1); 7017 case MLO_1_PLUS_1_1RF: 7018 case MLO_1_PLUS_1_2RF: 7019 case MLO_2_PLUS_2_2RF: 7020 case DBCC_LEGACY: 7021 return BIT(RTW89_PHY_0) | BIT(RTW89_PHY_1); 7022 case MLO_2_PLUS_0_1RF: 7023 case MLO_2_PLUS_0_2RF: 7024 default: 7025 return BIT(RTW89_PHY_0); 7026 } 7027 } 7028 7029 #define rtw89_for_each_active_bb(rtwdev, bb) \ 7030 for (u8 __active_bb_bitmap = rtw89_get_active_phy_bitmap(rtwdev), \ 7031 __phy_idx = 0; __phy_idx < RTW89_PHY_NUM; __phy_idx++) \ 7032 if (__active_bb_bitmap & BIT(__phy_idx) && \ 7033 (bb = &rtwdev->bbs[__phy_idx])) 7034 7035 #define rtw89_for_each_capab_bb(rtwdev, bb) \ 7036 for (u8 __phy_idx_max = rtwdev->dbcc_en ? RTW89_PHY_1 : RTW89_PHY_0, \ 7037 __phy_idx = 0; __phy_idx <= __phy_idx_max; __phy_idx++) \ 7038 if ((bb = &rtwdev->bbs[__phy_idx])) 7039 7040 static inline 7041 struct rtw89_bb_ctx *rtw89_get_bb_ctx(struct rtw89_dev *rtwdev, 7042 enum rtw89_phy_idx phy_idx) 7043 { 7044 if (phy_idx >= RTW89_PHY_NUM) 7045 return &rtwdev->bbs[RTW89_PHY_0]; 7046 7047 return &rtwdev->bbs[phy_idx]; 7048 } 7049 7050 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 7051 { 7052 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 7053 7054 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 7055 return true; 7056 7057 return false; 7058 } 7059 7060 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 7061 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 7062 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 7063 struct sk_buff *skb, bool fwdl); 7064 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 7065 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 7066 int qsel, unsigned int timeout); 7067 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 7068 struct rtw89_tx_desc_info *desc_info, 7069 void *txdesc); 7070 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7071 struct rtw89_tx_desc_info *desc_info, 7072 void *txdesc); 7073 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7074 struct rtw89_tx_desc_info *desc_info, 7075 void *txdesc); 7076 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7077 struct rtw89_tx_desc_info *desc_info, 7078 void *txdesc); 7079 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7080 struct rtw89_tx_desc_info *desc_info, 7081 void *txdesc); 7082 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7083 struct rtw89_rx_desc_info *desc_info, 7084 struct sk_buff *skb); 7085 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7086 struct rtw89_rx_desc_info *desc_info, 7087 u8 *data, u32 data_offset); 7088 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7089 struct rtw89_rx_desc_info *desc_info, 7090 u8 *data, u32 data_offset); 7091 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7092 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7093 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7094 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7095 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7096 struct rtw89_vif_link *rtwvif_link, 7097 struct rtw89_sta_link *rtwsta_link); 7098 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7099 struct rtw89_vif_link *rtwvif_link, 7100 struct rtw89_sta_link *rtwsta_link); 7101 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7102 struct rtw89_vif_link *rtwvif_link, 7103 struct rtw89_sta_link *rtwsta_link); 7104 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7105 struct rtw89_vif_link *rtwvif_link, 7106 struct rtw89_sta_link *rtwsta_link); 7107 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7108 struct rtw89_vif_link *rtwvif_link, 7109 struct rtw89_sta_link *rtwsta_link); 7110 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7111 struct ieee80211_sta *sta, 7112 struct cfg80211_tid_config *tid_config); 7113 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7114 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7115 int rtw89_core_init(struct rtw89_dev *rtwdev); 7116 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7117 int rtw89_core_register(struct rtw89_dev *rtwdev); 7118 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7119 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7120 u32 bus_data_size, 7121 const struct rtw89_chip_info *chip, 7122 const struct rtw89_chip_variant *variant); 7123 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7124 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7125 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7126 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7127 u8 mac_id, u8 port); 7128 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7129 struct rtw89_sta *rtwsta, u8 mac_id); 7130 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7131 unsigned int link_id); 7132 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7133 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7134 unsigned int link_id); 7135 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7136 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7137 const struct rtw89_6ghz_span * 7138 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7139 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7140 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7141 struct rtw89_chan *chan); 7142 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7143 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7144 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7145 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7146 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7147 struct rtw89_sta_link *rtwsta_link, u8 tid, 7148 u8 *cam_idx); 7149 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7150 struct rtw89_sta_link *rtwsta_link, u8 tid, 7151 u8 *cam_idx); 7152 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7153 struct ieee80211_sta *sta); 7154 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7155 struct ieee80211_sta *sta); 7156 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7157 struct ieee80211_sta *sta); 7158 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7159 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7160 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7161 struct rtw89_vif_link *rtwvif_link); 7162 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 7163 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7164 int rtw89_regd_init_hint(struct rtw89_dev *rtwdev); 7165 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7166 struct rtw89_traffic_stats *stats); 7167 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 7168 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7169 const struct rtw89_completion_data *data); 7170 int rtw89_core_start(struct rtw89_dev *rtwdev); 7171 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7172 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work); 7173 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work); 7174 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7175 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7176 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7177 const u8 *mac_addr, bool hw_scan); 7178 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7179 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7180 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7181 bool active); 7182 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7183 struct rtw89_vif_link *rtwvif_link, 7184 struct ieee80211_bss_conf *bss_conf); 7185 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7186 7187 #endif 7188