1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_efuse_block_cfg; 21 struct rtw89_h2c_rf_tssi; 22 struct rtw89_fw_txpwr_track_cfg; 23 struct rtw89_phy_rfk_log_fmt; 24 struct rtw89_debugfs; 25 26 extern const struct ieee80211_ops rtw89_ops; 27 28 #define MASKBYTE0 0xff 29 #define MASKBYTE1 0xff00 30 #define MASKBYTE2 0xff0000 31 #define MASKBYTE3 0xff000000 32 #define MASKBYTE4 0xff00000000ULL 33 #define MASKHWORD 0xffff0000 34 #define MASKLWORD 0x0000ffff 35 #define MASKDWORD 0xffffffff 36 #define RFREG_MASK 0xfffff 37 #define INV_RF_DATA 0xffffffff 38 #define BYPASS_CR_DATA 0xbabecafe 39 40 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 41 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 42 #define CFO_TRACK_MAX_USER 64 43 #define MAX_RSSI 110 44 #define RSSI_FACTOR 1 45 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 46 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 47 #define DELTA_SWINGIDX_SIZE 30 48 49 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 50 #define RTW89_RADIOTAP_ROOM_EHT \ 51 (sizeof(struct ieee80211_radiotap_tlv) + \ 52 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 53 sizeof(struct ieee80211_radiotap_tlv) + \ 54 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 55 #define RTW89_RADIOTAP_ROOM \ 56 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 57 58 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 59 #define RTW89_HTC_VARIANT_HE 3 60 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 61 #define RTW89_HTC_VARIANT_HE_CID_OM 1 62 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 63 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 64 65 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 66 enum htc_om_channel_width { 67 HTC_OM_CHANNEL_WIDTH_20 = 0, 68 HTC_OM_CHANNEL_WIDTH_40 = 1, 69 HTC_OM_CHANNEL_WIDTH_80 = 2, 70 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 71 }; 72 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 73 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 74 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 75 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 76 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 77 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 78 79 #define RTW89_TF_PAD GENMASK(11, 0) 80 #define RTW89_TF_BASIC_USER_INFO_SZ 6 81 82 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 83 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 84 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 86 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 87 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 88 89 enum rtw89_subband { 90 RTW89_CH_2G = 0, 91 RTW89_CH_5G_BAND_1 = 1, 92 /* RTW89_CH_5G_BAND_2 = 2, unused */ 93 RTW89_CH_5G_BAND_3 = 3, 94 RTW89_CH_5G_BAND_4 = 4, 95 96 RTW89_CH_6G_BAND_IDX0, /* Low */ 97 RTW89_CH_6G_BAND_IDX1, /* Low */ 98 RTW89_CH_6G_BAND_IDX2, /* Mid */ 99 RTW89_CH_6G_BAND_IDX3, /* Mid */ 100 RTW89_CH_6G_BAND_IDX4, /* High */ 101 RTW89_CH_6G_BAND_IDX5, /* High */ 102 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 103 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 104 105 RTW89_SUBBAND_NR, 106 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 107 }; 108 109 enum rtw89_gain_offset { 110 RTW89_GAIN_OFFSET_2G_CCK, 111 RTW89_GAIN_OFFSET_2G_OFDM, 112 RTW89_GAIN_OFFSET_5G_LOW, 113 RTW89_GAIN_OFFSET_5G_MID, 114 RTW89_GAIN_OFFSET_5G_HIGH, 115 RTW89_GAIN_OFFSET_6G_L0, 116 RTW89_GAIN_OFFSET_6G_L1, 117 RTW89_GAIN_OFFSET_6G_M0, 118 RTW89_GAIN_OFFSET_6G_M1, 119 RTW89_GAIN_OFFSET_6G_H0, 120 RTW89_GAIN_OFFSET_6G_H1, 121 RTW89_GAIN_OFFSET_6G_UH0, 122 RTW89_GAIN_OFFSET_6G_UH1, 123 124 RTW89_GAIN_OFFSET_NR, 125 }; 126 127 enum rtw89_hci_type { 128 RTW89_HCI_TYPE_PCIE, 129 RTW89_HCI_TYPE_USB, 130 RTW89_HCI_TYPE_SDIO, 131 }; 132 133 enum rtw89_core_chip_id { 134 RTL8852A, 135 RTL8852B, 136 RTL8852BT, 137 RTL8852C, 138 RTL8851B, 139 RTL8922A, 140 }; 141 142 enum rtw89_chip_gen { 143 RTW89_CHIP_AX, 144 RTW89_CHIP_BE, 145 146 RTW89_CHIP_GEN_NUM, 147 }; 148 149 enum rtw89_cv { 150 CHIP_CAV, 151 CHIP_CBV, 152 CHIP_CCV, 153 CHIP_CDV, 154 CHIP_CEV, 155 CHIP_CFV, 156 CHIP_CV_MAX, 157 CHIP_CV_INVALID = CHIP_CV_MAX, 158 }; 159 160 enum rtw89_bacam_ver { 161 RTW89_BACAM_V0, 162 RTW89_BACAM_V1, 163 164 RTW89_BACAM_V0_EXT = 99, 165 }; 166 167 enum rtw89_core_tx_type { 168 RTW89_CORE_TX_TYPE_DATA, 169 RTW89_CORE_TX_TYPE_MGMT, 170 RTW89_CORE_TX_TYPE_FWCMD, 171 }; 172 173 enum rtw89_core_rx_type { 174 RTW89_CORE_RX_TYPE_WIFI = 0, 175 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 176 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 177 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 178 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 179 RTW89_CORE_RX_TYPE_SS2FW = 5, 180 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 181 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 182 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 183 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 184 RTW89_CORE_RX_TYPE_C2H = 10, 185 RTW89_CORE_RX_TYPE_CSI = 11, 186 RTW89_CORE_RX_TYPE_CQI = 12, 187 RTW89_CORE_RX_TYPE_H2C = 13, 188 RTW89_CORE_RX_TYPE_FWDL = 14, 189 }; 190 191 enum rtw89_txq_flags { 192 RTW89_TXQ_F_AMPDU = 0, 193 RTW89_TXQ_F_BLOCK_BA = 1, 194 RTW89_TXQ_F_FORBID_BA = 2, 195 }; 196 197 enum rtw89_net_type { 198 RTW89_NET_TYPE_NO_LINK = 0, 199 RTW89_NET_TYPE_AD_HOC = 1, 200 RTW89_NET_TYPE_INFRA = 2, 201 RTW89_NET_TYPE_AP_MODE = 3, 202 }; 203 204 enum rtw89_wifi_role { 205 RTW89_WIFI_ROLE_NONE, 206 RTW89_WIFI_ROLE_STATION, 207 RTW89_WIFI_ROLE_AP, 208 RTW89_WIFI_ROLE_AP_VLAN, 209 RTW89_WIFI_ROLE_ADHOC, 210 RTW89_WIFI_ROLE_ADHOC_MASTER, 211 RTW89_WIFI_ROLE_MESH_POINT, 212 RTW89_WIFI_ROLE_MONITOR, 213 RTW89_WIFI_ROLE_P2P_DEVICE, 214 RTW89_WIFI_ROLE_P2P_CLIENT, 215 RTW89_WIFI_ROLE_P2P_GO, 216 RTW89_WIFI_ROLE_NAN, 217 RTW89_WIFI_ROLE_MLME_MAX 218 }; 219 220 enum rtw89_upd_mode { 221 RTW89_ROLE_CREATE, 222 RTW89_ROLE_REMOVE, 223 RTW89_ROLE_TYPE_CHANGE, 224 RTW89_ROLE_INFO_CHANGE, 225 RTW89_ROLE_CON_DISCONN, 226 RTW89_ROLE_BAND_SW, 227 RTW89_ROLE_FW_RESTORE, 228 }; 229 230 enum rtw89_self_role { 231 RTW89_SELF_ROLE_CLIENT, 232 RTW89_SELF_ROLE_AP, 233 RTW89_SELF_ROLE_AP_CLIENT 234 }; 235 236 enum rtw89_msk_sO_el { 237 RTW89_NO_MSK, 238 RTW89_SMA, 239 RTW89_TMA, 240 RTW89_BSSID 241 }; 242 243 enum rtw89_sch_tx_sel { 244 RTW89_SCH_TX_SEL_ALL, 245 RTW89_SCH_TX_SEL_HIQ, 246 RTW89_SCH_TX_SEL_MG0, 247 RTW89_SCH_TX_SEL_MACID, 248 }; 249 250 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 251 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 252 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 253 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 254 */ 255 enum rtw89_add_cam_sec_mode { 256 RTW89_ADDR_CAM_SEC_NONE = 0, 257 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 258 RTW89_ADDR_CAM_SEC_NORMAL = 2, 259 RTW89_ADDR_CAM_SEC_4GROUP = 3, 260 }; 261 262 enum rtw89_sec_key_type { 263 RTW89_SEC_KEY_TYPE_NONE = 0, 264 RTW89_SEC_KEY_TYPE_WEP40 = 1, 265 RTW89_SEC_KEY_TYPE_WEP104 = 2, 266 RTW89_SEC_KEY_TYPE_TKIP = 3, 267 RTW89_SEC_KEY_TYPE_WAPI = 4, 268 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 269 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 270 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 271 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 272 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 273 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 274 }; 275 276 enum rtw89_port { 277 RTW89_PORT_0 = 0, 278 RTW89_PORT_1 = 1, 279 RTW89_PORT_2 = 2, 280 RTW89_PORT_3 = 3, 281 RTW89_PORT_4 = 4, 282 RTW89_PORT_NUM 283 }; 284 285 enum rtw89_band { 286 RTW89_BAND_2G = 0, 287 RTW89_BAND_5G = 1, 288 RTW89_BAND_6G = 2, 289 RTW89_BAND_NUM, 290 }; 291 292 enum rtw89_hw_rate { 293 RTW89_HW_RATE_CCK1 = 0x0, 294 RTW89_HW_RATE_CCK2 = 0x1, 295 RTW89_HW_RATE_CCK5_5 = 0x2, 296 RTW89_HW_RATE_CCK11 = 0x3, 297 RTW89_HW_RATE_OFDM6 = 0x4, 298 RTW89_HW_RATE_OFDM9 = 0x5, 299 RTW89_HW_RATE_OFDM12 = 0x6, 300 RTW89_HW_RATE_OFDM18 = 0x7, 301 RTW89_HW_RATE_OFDM24 = 0x8, 302 RTW89_HW_RATE_OFDM36 = 0x9, 303 RTW89_HW_RATE_OFDM48 = 0xA, 304 RTW89_HW_RATE_OFDM54 = 0xB, 305 RTW89_HW_RATE_MCS0 = 0x80, 306 RTW89_HW_RATE_MCS1 = 0x81, 307 RTW89_HW_RATE_MCS2 = 0x82, 308 RTW89_HW_RATE_MCS3 = 0x83, 309 RTW89_HW_RATE_MCS4 = 0x84, 310 RTW89_HW_RATE_MCS5 = 0x85, 311 RTW89_HW_RATE_MCS6 = 0x86, 312 RTW89_HW_RATE_MCS7 = 0x87, 313 RTW89_HW_RATE_MCS8 = 0x88, 314 RTW89_HW_RATE_MCS9 = 0x89, 315 RTW89_HW_RATE_MCS10 = 0x8A, 316 RTW89_HW_RATE_MCS11 = 0x8B, 317 RTW89_HW_RATE_MCS12 = 0x8C, 318 RTW89_HW_RATE_MCS13 = 0x8D, 319 RTW89_HW_RATE_MCS14 = 0x8E, 320 RTW89_HW_RATE_MCS15 = 0x8F, 321 RTW89_HW_RATE_MCS16 = 0x90, 322 RTW89_HW_RATE_MCS17 = 0x91, 323 RTW89_HW_RATE_MCS18 = 0x92, 324 RTW89_HW_RATE_MCS19 = 0x93, 325 RTW89_HW_RATE_MCS20 = 0x94, 326 RTW89_HW_RATE_MCS21 = 0x95, 327 RTW89_HW_RATE_MCS22 = 0x96, 328 RTW89_HW_RATE_MCS23 = 0x97, 329 RTW89_HW_RATE_MCS24 = 0x98, 330 RTW89_HW_RATE_MCS25 = 0x99, 331 RTW89_HW_RATE_MCS26 = 0x9A, 332 RTW89_HW_RATE_MCS27 = 0x9B, 333 RTW89_HW_RATE_MCS28 = 0x9C, 334 RTW89_HW_RATE_MCS29 = 0x9D, 335 RTW89_HW_RATE_MCS30 = 0x9E, 336 RTW89_HW_RATE_MCS31 = 0x9F, 337 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 338 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 339 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 340 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 341 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 342 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 343 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 344 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 345 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 346 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 347 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 348 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 349 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 350 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 351 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 352 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 353 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 354 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 355 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 356 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 357 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 358 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 359 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 360 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 361 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 362 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 363 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 364 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 365 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 366 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 367 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 368 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 369 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 370 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 371 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 372 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 373 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 374 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 375 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 376 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 377 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 378 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 379 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 380 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 381 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 382 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 383 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 384 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 385 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 386 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 387 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 388 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 389 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 390 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 391 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 392 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 393 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 394 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 395 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 396 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 397 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 398 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 399 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 400 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 401 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 402 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 403 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 404 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 405 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 406 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 407 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 408 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 409 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 410 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 411 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 412 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 413 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 414 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 415 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 416 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 417 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 418 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 419 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 420 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 421 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 422 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 423 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 424 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 425 426 RTW89_HW_RATE_V1_MCS0 = 0x100, 427 RTW89_HW_RATE_V1_MCS1 = 0x101, 428 RTW89_HW_RATE_V1_MCS2 = 0x102, 429 RTW89_HW_RATE_V1_MCS3 = 0x103, 430 RTW89_HW_RATE_V1_MCS4 = 0x104, 431 RTW89_HW_RATE_V1_MCS5 = 0x105, 432 RTW89_HW_RATE_V1_MCS6 = 0x106, 433 RTW89_HW_RATE_V1_MCS7 = 0x107, 434 RTW89_HW_RATE_V1_MCS8 = 0x108, 435 RTW89_HW_RATE_V1_MCS9 = 0x109, 436 RTW89_HW_RATE_V1_MCS10 = 0x10A, 437 RTW89_HW_RATE_V1_MCS11 = 0x10B, 438 RTW89_HW_RATE_V1_MCS12 = 0x10C, 439 RTW89_HW_RATE_V1_MCS13 = 0x10D, 440 RTW89_HW_RATE_V1_MCS14 = 0x10E, 441 RTW89_HW_RATE_V1_MCS15 = 0x10F, 442 RTW89_HW_RATE_V1_MCS16 = 0x110, 443 RTW89_HW_RATE_V1_MCS17 = 0x111, 444 RTW89_HW_RATE_V1_MCS18 = 0x112, 445 RTW89_HW_RATE_V1_MCS19 = 0x113, 446 RTW89_HW_RATE_V1_MCS20 = 0x114, 447 RTW89_HW_RATE_V1_MCS21 = 0x115, 448 RTW89_HW_RATE_V1_MCS22 = 0x116, 449 RTW89_HW_RATE_V1_MCS23 = 0x117, 450 RTW89_HW_RATE_V1_MCS24 = 0x118, 451 RTW89_HW_RATE_V1_MCS25 = 0x119, 452 RTW89_HW_RATE_V1_MCS26 = 0x11A, 453 RTW89_HW_RATE_V1_MCS27 = 0x11B, 454 RTW89_HW_RATE_V1_MCS28 = 0x11C, 455 RTW89_HW_RATE_V1_MCS29 = 0x11D, 456 RTW89_HW_RATE_V1_MCS30 = 0x11E, 457 RTW89_HW_RATE_V1_MCS31 = 0x11F, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 469 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 481 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 493 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 505 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 517 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 529 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 541 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 553 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 583 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 597 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 611 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 612 613 RTW89_HW_RATE_NR, 614 RTW89_HW_RATE_INVAL, 615 616 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 617 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 618 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 619 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 620 }; 621 622 /* 2G channels, 623 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 624 */ 625 #define RTW89_2G_CH_NUM 14 626 627 /* 5G channels, 628 * 36, 38, 40, 42, 44, 46, 48, 50, 629 * 52, 54, 56, 58, 60, 62, 64, 630 * 100, 102, 104, 106, 108, 110, 112, 114, 631 * 116, 118, 120, 122, 124, 126, 128, 130, 632 * 132, 134, 136, 138, 140, 142, 144, 633 * 149, 151, 153, 155, 157, 159, 161, 163, 634 * 165, 167, 169, 171, 173, 175, 177 635 */ 636 #define RTW89_5G_CH_NUM 53 637 638 /* 6G channels, 639 * 1, 3, 5, 7, 9, 11, 13, 15, 640 * 17, 19, 21, 23, 25, 27, 29, 33, 641 * 35, 37, 39, 41, 43, 45, 47, 49, 642 * 51, 53, 55, 57, 59, 61, 65, 67, 643 * 69, 71, 73, 75, 77, 79, 81, 83, 644 * 85, 87, 89, 91, 93, 97, 99, 101, 645 * 103, 105, 107, 109, 111, 113, 115, 117, 646 * 119, 121, 123, 125, 129, 131, 133, 135, 647 * 137, 139, 141, 143, 145, 147, 149, 151, 648 * 153, 155, 157, 161, 163, 165, 167, 169, 649 * 171, 173, 175, 177, 179, 181, 183, 185, 650 * 187, 189, 193, 195, 197, 199, 201, 203, 651 * 205, 207, 209, 211, 213, 215, 217, 219, 652 * 221, 225, 227, 229, 231, 233, 235, 237, 653 * 239, 241, 243, 245, 247, 249, 251, 253, 654 */ 655 #define RTW89_6G_CH_NUM 120 656 657 enum rtw89_rate_section { 658 RTW89_RS_CCK, 659 RTW89_RS_OFDM, 660 RTW89_RS_MCS, /* for HT/VHT/HE */ 661 RTW89_RS_HEDCM, 662 RTW89_RS_OFFSET, 663 RTW89_RS_NUM, 664 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 665 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 666 }; 667 668 enum rtw89_rate_offset_indexes { 669 RTW89_RATE_OFFSET_HE, 670 RTW89_RATE_OFFSET_VHT, 671 RTW89_RATE_OFFSET_HT, 672 RTW89_RATE_OFFSET_OFDM, 673 RTW89_RATE_OFFSET_CCK, 674 RTW89_RATE_OFFSET_DLRU_EHT, 675 RTW89_RATE_OFFSET_DLRU_HE, 676 RTW89_RATE_OFFSET_EHT, 677 __RTW89_RATE_OFFSET_NUM, 678 679 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 680 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 681 }; 682 683 enum rtw89_rate_num { 684 RTW89_RATE_CCK_NUM = 4, 685 RTW89_RATE_OFDM_NUM = 8, 686 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 687 688 RTW89_RATE_MCS_NUM_AX = 12, 689 RTW89_RATE_MCS_NUM_BE = 16, 690 __RTW89_RATE_MCS_NUM = 16, 691 }; 692 693 enum rtw89_nss { 694 RTW89_NSS_1 = 0, 695 RTW89_NSS_2 = 1, 696 /* HE DCM only support 1ss and 2ss */ 697 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 698 RTW89_NSS_3 = 2, 699 RTW89_NSS_4 = 3, 700 RTW89_NSS_NUM, 701 }; 702 703 enum rtw89_ntx { 704 RTW89_1TX = 0, 705 RTW89_2TX = 1, 706 RTW89_NTX_NUM, 707 }; 708 709 enum rtw89_beamforming_type { 710 RTW89_NONBF = 0, 711 RTW89_BF = 1, 712 RTW89_BF_NUM, 713 }; 714 715 enum rtw89_ofdma_type { 716 RTW89_NON_OFDMA = 0, 717 RTW89_OFDMA = 1, 718 RTW89_OFDMA_NUM, 719 }; 720 721 enum rtw89_regulation_type { 722 RTW89_WW = 0, 723 RTW89_ETSI = 1, 724 RTW89_FCC = 2, 725 RTW89_MKK = 3, 726 RTW89_NA = 4, 727 RTW89_IC = 5, 728 RTW89_KCC = 6, 729 RTW89_ACMA = 7, 730 RTW89_NCC = 8, 731 RTW89_MEXICO = 9, 732 RTW89_CHILE = 10, 733 RTW89_UKRAINE = 11, 734 RTW89_CN = 12, 735 RTW89_QATAR = 13, 736 RTW89_UK = 14, 737 RTW89_THAILAND = 15, 738 RTW89_REGD_NUM, 739 }; 740 741 enum rtw89_reg_6ghz_power { 742 RTW89_REG_6GHZ_POWER_VLP = 0, 743 RTW89_REG_6GHZ_POWER_LPI = 1, 744 RTW89_REG_6GHZ_POWER_STD = 2, 745 746 NUM_OF_RTW89_REG_6GHZ_POWER, 747 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 748 }; 749 750 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 751 752 /* calculate based on ieee80211 Transmit Power Envelope */ 753 struct rtw89_reg_6ghz_tpe { 754 bool valid; 755 s8 constraint; /* unit: dBm */ 756 }; 757 758 enum rtw89_fw_pkt_ofld_type { 759 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 760 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 761 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 762 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 763 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 764 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 765 RTW89_PKT_OFLD_TYPE_NDP = 6, 766 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 767 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 768 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 769 RTW89_PKT_OFLD_TYPE_NUM, 770 }; 771 772 struct rtw89_txpwr_byrate { 773 s8 cck[RTW89_RATE_CCK_NUM]; 774 s8 ofdm[RTW89_RATE_OFDM_NUM]; 775 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 776 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 777 s8 offset[__RTW89_RATE_OFFSET_NUM]; 778 s8 trap; 779 }; 780 781 struct rtw89_rate_desc { 782 enum rtw89_nss nss; 783 enum rtw89_rate_section rs; 784 enum rtw89_ofdma_type ofdma; 785 u8 idx; 786 }; 787 788 #define PHY_STS_HDR_LEN 8 789 #define RF_PATH_MAX 4 790 #define RTW89_MAX_PPDU_CNT 8 791 struct rtw89_rx_phy_ppdu { 792 void *buf; 793 u32 len; 794 u8 rssi_avg; 795 u8 rssi[RF_PATH_MAX]; 796 u8 mac_id; 797 u8 chan_idx; 798 u8 ie; 799 u16 rate; 800 u8 rpl_avg; 801 u8 rpl_path[RF_PATH_MAX]; 802 u8 rpl_fd[RF_PATH_MAX]; 803 u8 bw_idx; 804 u8 rx_path_en; 805 struct { 806 bool has; 807 u8 avg_snr; 808 u8 evm_max; 809 u8 evm_min; 810 } ofdm; 811 bool has_data; 812 bool has_bcn; 813 bool ldpc; 814 bool stbc; 815 bool to_self; 816 bool valid; 817 bool hdr_2_en; 818 }; 819 820 enum rtw89_mac_idx { 821 RTW89_MAC_0 = 0, 822 RTW89_MAC_1 = 1, 823 RTW89_MAC_NUM, 824 }; 825 826 enum rtw89_phy_idx { 827 RTW89_PHY_0 = 0, 828 RTW89_PHY_1 = 1, 829 RTW89_PHY_MAX 830 }; 831 832 #define __RTW89_MLD_MAX_LINK_NUM 2 833 #define RTW89_MLD_NON_STA_LINK_NUM 1 834 835 enum rtw89_chanctx_idx { 836 RTW89_CHANCTX_0 = 0, 837 RTW89_CHANCTX_1 = 1, 838 839 NUM_OF_RTW89_CHANCTX, 840 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 841 }; 842 843 enum rtw89_rf_path { 844 RF_PATH_A = 0, 845 RF_PATH_B = 1, 846 RF_PATH_C = 2, 847 RF_PATH_D = 3, 848 RF_PATH_AB, 849 RF_PATH_AC, 850 RF_PATH_AD, 851 RF_PATH_BC, 852 RF_PATH_BD, 853 RF_PATH_CD, 854 RF_PATH_ABC, 855 RF_PATH_ABD, 856 RF_PATH_ACD, 857 RF_PATH_BCD, 858 RF_PATH_ABCD, 859 }; 860 861 enum rtw89_rf_path_bit { 862 RF_A = BIT(0), 863 RF_B = BIT(1), 864 RF_C = BIT(2), 865 RF_D = BIT(3), 866 867 RF_AB = (RF_A | RF_B), 868 RF_AC = (RF_A | RF_C), 869 RF_AD = (RF_A | RF_D), 870 RF_BC = (RF_B | RF_C), 871 RF_BD = (RF_B | RF_D), 872 RF_CD = (RF_C | RF_D), 873 874 RF_ABC = (RF_A | RF_B | RF_C), 875 RF_ABD = (RF_A | RF_B | RF_D), 876 RF_ACD = (RF_A | RF_C | RF_D), 877 RF_BCD = (RF_B | RF_C | RF_D), 878 879 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 880 }; 881 882 enum rtw89_bandwidth { 883 RTW89_CHANNEL_WIDTH_20 = 0, 884 RTW89_CHANNEL_WIDTH_40 = 1, 885 RTW89_CHANNEL_WIDTH_80 = 2, 886 RTW89_CHANNEL_WIDTH_160 = 3, 887 RTW89_CHANNEL_WIDTH_320 = 4, 888 889 /* keep index order above */ 890 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 891 892 RTW89_CHANNEL_WIDTH_80_80 = 5, 893 RTW89_CHANNEL_WIDTH_5 = 6, 894 RTW89_CHANNEL_WIDTH_10 = 7, 895 }; 896 897 enum rtw89_ps_mode { 898 RTW89_PS_MODE_NONE = 0, 899 RTW89_PS_MODE_RFOFF = 1, 900 RTW89_PS_MODE_CLK_GATED = 2, 901 RTW89_PS_MODE_PWR_GATED = 3, 902 }; 903 904 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 905 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 906 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 907 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 908 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 909 910 enum rtw89_pe_duration { 911 RTW89_PE_DURATION_0 = 0, 912 RTW89_PE_DURATION_8 = 1, 913 RTW89_PE_DURATION_16 = 2, 914 RTW89_PE_DURATION_16_20 = 3, 915 }; 916 917 enum rtw89_ru_bandwidth { 918 RTW89_RU26 = 0, 919 RTW89_RU52 = 1, 920 RTW89_RU106 = 2, 921 RTW89_RU52_26 = 3, 922 RTW89_RU106_26 = 4, 923 RTW89_RU_NUM, 924 }; 925 926 enum rtw89_sc_offset { 927 RTW89_SC_DONT_CARE = 0, 928 RTW89_SC_20_UPPER = 1, 929 RTW89_SC_20_LOWER = 2, 930 RTW89_SC_20_UPMOST = 3, 931 RTW89_SC_20_LOWEST = 4, 932 RTW89_SC_20_UP2X = 5, 933 RTW89_SC_20_LOW2X = 6, 934 RTW89_SC_20_UP3X = 7, 935 RTW89_SC_20_LOW3X = 8, 936 RTW89_SC_40_UPPER = 9, 937 RTW89_SC_40_LOWER = 10, 938 }; 939 940 /* only mgd features can be added to the enum */ 941 enum rtw89_wow_flags { 942 RTW89_WOW_FLAG_EN_MAGIC_PKT, 943 RTW89_WOW_FLAG_EN_REKEY_PKT, 944 RTW89_WOW_FLAG_EN_DISCONNECT, 945 RTW89_WOW_FLAG_EN_PATTERN, 946 RTW89_WOW_FLAG_NUM, 947 }; 948 949 struct rtw89_chan { 950 u8 channel; 951 u8 primary_channel; 952 enum rtw89_band band_type; 953 enum rtw89_bandwidth band_width; 954 955 /* The follow-up are derived from the above. We must ensure that it 956 * is assigned correctly in rtw89_chan_create() if new one is added. 957 */ 958 u32 freq; 959 enum rtw89_subband subband_type; 960 enum rtw89_sc_offset pri_ch_idx; 961 u8 pri_sb_idx; 962 }; 963 964 struct rtw89_chan_rcd { 965 u8 prev_primary_channel; 966 enum rtw89_band prev_band_type; 967 bool band_changed; 968 }; 969 970 struct rtw89_channel_help_params { 971 u32 tx_en; 972 }; 973 974 struct rtw89_port_reg { 975 u32 port_cfg; 976 u32 tbtt_prohib; 977 u32 bcn_area; 978 u32 bcn_early; 979 u32 tbtt_early; 980 u32 tbtt_agg; 981 u32 bcn_space; 982 u32 bcn_forcetx; 983 u32 bcn_err_cnt; 984 u32 bcn_err_flag; 985 u32 dtim_ctrl; 986 u32 tbtt_shift; 987 u32 bcn_cnt_tmr; 988 u32 tsftr_l; 989 u32 tsftr_h; 990 u32 md_tsft; 991 u32 bss_color; 992 u32 mbssid; 993 u32 mbssid_drop; 994 u32 tsf_sync; 995 u32 ptcl_dbg; 996 u32 ptcl_dbg_info; 997 u32 bcn_drop_all; 998 u32 hiq_win[RTW89_PORT_NUM]; 999 }; 1000 1001 struct rtw89_txwd_body { 1002 __le32 dword0; 1003 __le32 dword1; 1004 __le32 dword2; 1005 __le32 dword3; 1006 __le32 dword4; 1007 __le32 dword5; 1008 } __packed; 1009 1010 struct rtw89_txwd_body_v1 { 1011 __le32 dword0; 1012 __le32 dword1; 1013 __le32 dword2; 1014 __le32 dword3; 1015 __le32 dword4; 1016 __le32 dword5; 1017 __le32 dword6; 1018 __le32 dword7; 1019 } __packed; 1020 1021 struct rtw89_txwd_body_v2 { 1022 __le32 dword0; 1023 __le32 dword1; 1024 __le32 dword2; 1025 __le32 dword3; 1026 __le32 dword4; 1027 __le32 dword5; 1028 __le32 dword6; 1029 __le32 dword7; 1030 } __packed; 1031 1032 struct rtw89_txwd_info { 1033 __le32 dword0; 1034 __le32 dword1; 1035 __le32 dword2; 1036 __le32 dword3; 1037 __le32 dword4; 1038 __le32 dword5; 1039 } __packed; 1040 1041 struct rtw89_txwd_info_v2 { 1042 __le32 dword0; 1043 __le32 dword1; 1044 __le32 dword2; 1045 __le32 dword3; 1046 __le32 dword4; 1047 __le32 dword5; 1048 __le32 dword6; 1049 __le32 dword7; 1050 } __packed; 1051 1052 struct rtw89_rx_desc_info { 1053 u16 pkt_size; 1054 u8 pkt_type; 1055 u8 drv_info_size; 1056 u8 phy_rpt_size; 1057 u8 hdr_cnv_size; 1058 u8 shift; 1059 u8 wl_hd_iv_len; 1060 bool long_rxdesc; 1061 bool bb_sel; 1062 bool mac_info_valid; 1063 u16 data_rate; 1064 u8 gi_ltf; 1065 u8 bw; 1066 u32 free_run_cnt; 1067 u8 user_id; 1068 bool sr_en; 1069 u8 ppdu_cnt; 1070 u8 ppdu_type; 1071 bool icv_err; 1072 bool crc32_err; 1073 bool hw_dec; 1074 bool sw_dec; 1075 bool addr1_match; 1076 u8 frag; 1077 u16 seq; 1078 u8 frame_type; 1079 u8 rx_pl_id; 1080 bool addr_cam_valid; 1081 u8 addr_cam_id; 1082 u8 sec_cam_id; 1083 u8 mac_id; 1084 u16 offset; 1085 u16 rxd_len; 1086 bool ready; 1087 u16 rssi; 1088 }; 1089 1090 struct rtw89_rxdesc_short { 1091 __le32 dword0; 1092 __le32 dword1; 1093 __le32 dword2; 1094 __le32 dword3; 1095 } __packed; 1096 1097 struct rtw89_rxdesc_short_v2 { 1098 __le32 dword0; 1099 __le32 dword1; 1100 __le32 dword2; 1101 __le32 dword3; 1102 __le32 dword4; 1103 __le32 dword5; 1104 } __packed; 1105 1106 struct rtw89_rxdesc_long { 1107 __le32 dword0; 1108 __le32 dword1; 1109 __le32 dword2; 1110 __le32 dword3; 1111 __le32 dword4; 1112 __le32 dword5; 1113 __le32 dword6; 1114 __le32 dword7; 1115 } __packed; 1116 1117 struct rtw89_rxdesc_long_v2 { 1118 __le32 dword0; 1119 __le32 dword1; 1120 __le32 dword2; 1121 __le32 dword3; 1122 __le32 dword4; 1123 __le32 dword5; 1124 __le32 dword6; 1125 __le32 dword7; 1126 __le32 dword8; 1127 __le32 dword9; 1128 } __packed; 1129 1130 struct rtw89_rxdesc_phy_rpt_v2 { 1131 __le32 dword0; 1132 __le32 dword1; 1133 } __packed; 1134 1135 struct rtw89_tx_desc_info { 1136 u16 pkt_size; 1137 u8 wp_offset; 1138 u8 mac_id; 1139 u8 qsel; 1140 u8 ch_dma; 1141 u8 hdr_llc_len; 1142 bool is_bmc; 1143 bool en_wd_info; 1144 bool wd_page; 1145 bool use_rate; 1146 bool dis_data_fb; 1147 bool tid_indicate; 1148 bool agg_en; 1149 bool bk; 1150 u8 ampdu_density; 1151 u8 ampdu_num; 1152 bool sec_en; 1153 u8 addr_info_nr; 1154 u8 sec_keyid; 1155 u8 sec_type; 1156 u8 sec_cam_idx; 1157 u8 sec_seq[6]; 1158 u16 data_rate; 1159 u16 data_retry_lowest_rate; 1160 bool fw_dl; 1161 u16 seq; 1162 bool a_ctrl_bsr; 1163 u8 hw_ssn_sel; 1164 #define RTW89_MGMT_HW_SSN_SEL 1 1165 u8 hw_seq_mode; 1166 #define RTW89_MGMT_HW_SEQ_MODE 1 1167 bool hiq; 1168 u8 port; 1169 bool er_cap; 1170 bool stbc; 1171 bool ldpc; 1172 bool upd_wlan_hdr; 1173 }; 1174 1175 struct rtw89_core_tx_request { 1176 enum rtw89_core_tx_type tx_type; 1177 1178 struct sk_buff *skb; 1179 struct rtw89_vif_link *rtwvif_link; 1180 struct rtw89_sta_link *rtwsta_link; 1181 struct rtw89_tx_desc_info desc_info; 1182 }; 1183 1184 struct rtw89_txq { 1185 struct list_head list; 1186 unsigned long flags; 1187 int wait_cnt; 1188 }; 1189 1190 struct rtw89_mac_ax_gnt { 1191 u8 gnt_bt_sw_en; 1192 u8 gnt_bt; 1193 u8 gnt_wl_sw_en; 1194 u8 gnt_wl; 1195 } __packed; 1196 1197 struct rtw89_mac_ax_wl_act { 1198 u8 wlan_act_en; 1199 u8 wlan_act; 1200 }; 1201 1202 #define RTW89_MAC_AX_COEX_GNT_NR 2 1203 struct rtw89_mac_ax_coex_gnt { 1204 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1205 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1206 }; 1207 1208 enum rtw89_btc_ncnt { 1209 BTC_NCNT_POWER_ON = 0x0, 1210 BTC_NCNT_POWER_OFF, 1211 BTC_NCNT_INIT_COEX, 1212 BTC_NCNT_SCAN_START, 1213 BTC_NCNT_SCAN_FINISH, 1214 BTC_NCNT_SPECIAL_PACKET, 1215 BTC_NCNT_SWITCH_BAND, 1216 BTC_NCNT_RFK_TIMEOUT, 1217 BTC_NCNT_SHOW_COEX_INFO, 1218 BTC_NCNT_ROLE_INFO, 1219 BTC_NCNT_CONTROL, 1220 BTC_NCNT_RADIO_STATE, 1221 BTC_NCNT_CUSTOMERIZE, 1222 BTC_NCNT_WL_RFK, 1223 BTC_NCNT_WL_STA, 1224 BTC_NCNT_WL_STA_LAST, 1225 BTC_NCNT_FWINFO, 1226 BTC_NCNT_TIMER, 1227 BTC_NCNT_SWITCH_CHBW, 1228 BTC_NCNT_RESUME_DL_FW, 1229 BTC_NCNT_COUNTRYCODE, 1230 BTC_NCNT_NUM, 1231 }; 1232 1233 enum rtw89_btc_btinfo { 1234 BTC_BTINFO_L0 = 0, 1235 BTC_BTINFO_L1, 1236 BTC_BTINFO_L2, 1237 BTC_BTINFO_L3, 1238 BTC_BTINFO_H0, 1239 BTC_BTINFO_H1, 1240 BTC_BTINFO_H2, 1241 BTC_BTINFO_H3, 1242 BTC_BTINFO_MAX 1243 }; 1244 1245 enum rtw89_btc_dcnt { 1246 BTC_DCNT_RUN = 0x0, 1247 BTC_DCNT_CX_RUNINFO, 1248 BTC_DCNT_RPT, 1249 BTC_DCNT_RPT_HANG, 1250 BTC_DCNT_CYCLE, 1251 BTC_DCNT_CYCLE_HANG, 1252 BTC_DCNT_W1, 1253 BTC_DCNT_W1_HANG, 1254 BTC_DCNT_B1, 1255 BTC_DCNT_B1_HANG, 1256 BTC_DCNT_TDMA_NONSYNC, 1257 BTC_DCNT_SLOT_NONSYNC, 1258 BTC_DCNT_BTCNT_HANG, 1259 BTC_DCNT_BTTX_HANG, 1260 BTC_DCNT_WL_SLOT_DRIFT, 1261 BTC_DCNT_WL_STA_LAST, 1262 BTC_DCNT_BT_SLOT_DRIFT, 1263 BTC_DCNT_BT_SLOT_FLOOD, 1264 BTC_DCNT_FDDT_TRIG, 1265 BTC_DCNT_E2G, 1266 BTC_DCNT_E2G_HANG, 1267 BTC_DCNT_WL_FW_VER_MATCH, 1268 BTC_DCNT_NULL_TX_FAIL, 1269 BTC_DCNT_WL_STA_NTFY, 1270 BTC_DCNT_NUM, 1271 }; 1272 1273 enum rtw89_btc_wl_state_cnt { 1274 BTC_WCNT_SCANAP = 0x0, 1275 BTC_WCNT_DHCP, 1276 BTC_WCNT_EAPOL, 1277 BTC_WCNT_ARP, 1278 BTC_WCNT_SCBDUPDATE, 1279 BTC_WCNT_RFK_REQ, 1280 BTC_WCNT_RFK_GO, 1281 BTC_WCNT_RFK_REJECT, 1282 BTC_WCNT_RFK_TIMEOUT, 1283 BTC_WCNT_CH_UPDATE, 1284 BTC_WCNT_DBCC_ALL_2G, 1285 BTC_WCNT_DBCC_CHG, 1286 BTC_WCNT_RX_OK_LAST, 1287 BTC_WCNT_RX_OK_LAST2S, 1288 BTC_WCNT_RX_ERR_LAST, 1289 BTC_WCNT_RX_ERR_LAST2S, 1290 BTC_WCNT_RX_LAST, 1291 BTC_WCNT_NUM 1292 }; 1293 1294 enum rtw89_btc_bt_state_cnt { 1295 BTC_BCNT_RETRY = 0x0, 1296 BTC_BCNT_REINIT, 1297 BTC_BCNT_REENABLE, 1298 BTC_BCNT_SCBDREAD, 1299 BTC_BCNT_RELINK, 1300 BTC_BCNT_IGNOWL, 1301 BTC_BCNT_INQPAG, 1302 BTC_BCNT_INQ, 1303 BTC_BCNT_PAGE, 1304 BTC_BCNT_ROLESW, 1305 BTC_BCNT_AFH, 1306 BTC_BCNT_INFOUPDATE, 1307 BTC_BCNT_INFOSAME, 1308 BTC_BCNT_SCBDUPDATE, 1309 BTC_BCNT_HIPRI_TX, 1310 BTC_BCNT_HIPRI_RX, 1311 BTC_BCNT_LOPRI_TX, 1312 BTC_BCNT_LOPRI_RX, 1313 BTC_BCNT_POLUT, 1314 BTC_BCNT_POLUT_NOW, 1315 BTC_BCNT_POLUT_DIFF, 1316 BTC_BCNT_RATECHG, 1317 BTC_BCNT_NUM, 1318 }; 1319 1320 enum rtw89_btc_bt_profile { 1321 BTC_BT_NOPROFILE = 0, 1322 BTC_BT_HFP = BIT(0), 1323 BTC_BT_HID = BIT(1), 1324 BTC_BT_A2DP = BIT(2), 1325 BTC_BT_PAN = BIT(3), 1326 BTC_PROFILE_MAX = 4, 1327 }; 1328 1329 struct rtw89_btc_ant_info { 1330 u8 type; /* shared, dedicated */ 1331 u8 num; 1332 u8 isolation; 1333 1334 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1335 u8 diversity: 1; 1336 u8 btg_pos: 2; 1337 u8 stream_cnt: 4; 1338 }; 1339 1340 struct rtw89_btc_ant_info_v7 { 1341 u8 type; /* shared, dedicated(non-shared) */ 1342 u8 num; /* antenna count */ 1343 u8 isolation; 1344 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1345 1346 u8 diversity; /* only for wifi use 1-antenna */ 1347 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1348 u8 stream_cnt; /* spatial_stream count */ 1349 u8 rsvd; 1350 } __packed; 1351 1352 enum rtw89_tfc_dir { 1353 RTW89_TFC_UL, 1354 RTW89_TFC_DL, 1355 }; 1356 1357 struct rtw89_btc_wl_smap { 1358 u32 busy: 1; 1359 u32 scan: 1; 1360 u32 connecting: 1; 1361 u32 roaming: 1; 1362 u32 dbccing: 1; 1363 u32 _4way: 1; 1364 u32 rf_off: 1; 1365 u32 lps: 2; 1366 u32 ips: 1; 1367 u32 init_ok: 1; 1368 u32 traffic_dir : 2; 1369 u32 rf_off_pre: 1; 1370 u32 lps_pre: 2; 1371 u32 lps_exiting: 1; 1372 u32 emlsr: 1; 1373 }; 1374 1375 enum rtw89_tfc_lv { 1376 RTW89_TFC_IDLE, 1377 RTW89_TFC_ULTRA_LOW, 1378 RTW89_TFC_LOW, 1379 RTW89_TFC_MID, 1380 RTW89_TFC_HIGH, 1381 }; 1382 1383 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1384 DECLARE_EWMA(tp, 10, 2); 1385 1386 struct rtw89_traffic_stats { 1387 /* units in bytes */ 1388 u64 tx_unicast; 1389 u64 rx_unicast; 1390 u32 tx_avg_len; 1391 u32 rx_avg_len; 1392 1393 /* count for packets */ 1394 u64 tx_cnt; 1395 u64 rx_cnt; 1396 1397 /* units in Mbps */ 1398 u32 tx_throughput; 1399 u32 rx_throughput; 1400 u32 tx_throughput_raw; 1401 u32 rx_throughput_raw; 1402 1403 u32 rx_tf_acc; 1404 u32 rx_tf_periodic; 1405 1406 enum rtw89_tfc_lv tx_tfc_lv; 1407 enum rtw89_tfc_lv rx_tfc_lv; 1408 struct ewma_tp tx_ewma_tp; 1409 struct ewma_tp rx_ewma_tp; 1410 1411 u16 tx_rate; 1412 u16 rx_rate; 1413 }; 1414 1415 struct rtw89_btc_chdef { 1416 u8 center_ch; 1417 u8 band; 1418 u8 chan; 1419 enum rtw89_sc_offset offset; 1420 enum rtw89_bandwidth bw; 1421 }; 1422 1423 struct rtw89_btc_statistic { 1424 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1425 struct rtw89_traffic_stats traffic; 1426 }; 1427 1428 #define BTC_WL_RSSI_THMAX 4 1429 1430 struct rtw89_btc_wl_link_info { 1431 struct rtw89_btc_chdef chdef; 1432 struct rtw89_btc_statistic stat; 1433 enum rtw89_tfc_dir dir; 1434 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1435 u8 mac_addr[ETH_ALEN]; 1436 u8 busy; 1437 u8 ch; 1438 u8 bw; 1439 u8 band; 1440 u8 role; 1441 u8 pid; 1442 u8 phy; 1443 u8 dtim_period; 1444 u8 mode; 1445 u8 tx_1ss_limit; 1446 1447 u8 mac_id; 1448 u8 tx_retry; 1449 1450 u32 bcn_period; 1451 u32 busy_t; 1452 u32 tx_time; 1453 u32 client_cnt; 1454 u32 rx_rate_drop_cnt; 1455 u32 noa_duration; 1456 1457 u32 active: 1; 1458 u32 noa: 1; 1459 u32 client_ps: 1; 1460 u32 connected: 2; 1461 }; 1462 1463 union rtw89_btc_wl_state_map { 1464 u32 val; 1465 struct rtw89_btc_wl_smap map; 1466 }; 1467 1468 struct rtw89_btc_bt_hfp_desc { 1469 u32 exist: 1; 1470 u32 type: 2; 1471 u32 rsvd: 29; 1472 }; 1473 1474 struct rtw89_btc_bt_hid_desc { 1475 u32 exist: 1; 1476 u32 slot_info: 2; 1477 u32 pair_cnt: 2; 1478 u32 type: 8; 1479 u32 rsvd: 19; 1480 }; 1481 1482 struct rtw89_btc_bt_a2dp_desc { 1483 u8 exist: 1; 1484 u8 exist_last: 1; 1485 u8 play_latency: 1; 1486 u8 type: 3; 1487 u8 active: 1; 1488 u8 sink: 1; 1489 u32 handle_update: 1; 1490 u32 devinfo_query: 1; 1491 u32 no_empty_streak_2s: 8; 1492 u32 no_empty_streak_max: 8; 1493 u32 rsvd: 6; 1494 1495 u8 bitpool; 1496 u16 vendor_id; 1497 u32 device_name; 1498 u32 flush_time; 1499 }; 1500 1501 struct rtw89_btc_bt_pan_desc { 1502 u32 exist: 1; 1503 u32 type: 1; 1504 u32 active: 1; 1505 u32 rsvd: 29; 1506 }; 1507 1508 struct rtw89_btc_bt_rfk_info { 1509 u32 run: 1; 1510 u32 req: 1; 1511 u32 timeout: 1; 1512 u32 rsvd: 29; 1513 }; 1514 1515 union rtw89_btc_bt_rfk_info_map { 1516 u32 val; 1517 struct rtw89_btc_bt_rfk_info map; 1518 }; 1519 1520 struct rtw89_btc_bt_ver_info { 1521 u32 fw_coex; /* match with which coex_ver */ 1522 u32 fw; 1523 }; 1524 1525 struct rtw89_btc_bool_sta_chg { 1526 u32 now: 1; 1527 u32 last: 1; 1528 u32 remain: 1; 1529 u32 srvd: 29; 1530 }; 1531 1532 struct rtw89_btc_u8_sta_chg { 1533 u8 now; 1534 u8 last; 1535 u8 remain; 1536 u8 rsvd; 1537 }; 1538 1539 struct rtw89_btc_wl_scan_info { 1540 u8 band[RTW89_PHY_MAX]; 1541 u8 phy_map; 1542 u8 rsvd; 1543 }; 1544 1545 struct rtw89_btc_wl_dbcc_info { 1546 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1547 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1548 u8 real_band[RTW89_PHY_MAX]; 1549 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1550 }; 1551 1552 struct rtw89_btc_wl_active_role { 1553 u8 connected: 1; 1554 u8 pid: 3; 1555 u8 phy: 1; 1556 u8 noa: 1; 1557 u8 band: 2; 1558 1559 u8 client_ps: 1; 1560 u8 bw: 7; 1561 1562 u8 role; 1563 u8 ch; 1564 1565 u16 tx_lvl; 1566 u16 rx_lvl; 1567 u16 tx_rate; 1568 u16 rx_rate; 1569 }; 1570 1571 struct rtw89_btc_wl_active_role_v1 { 1572 u8 connected: 1; 1573 u8 pid: 3; 1574 u8 phy: 1; 1575 u8 noa: 1; 1576 u8 band: 2; 1577 1578 u8 client_ps: 1; 1579 u8 bw: 7; 1580 1581 u8 role; 1582 u8 ch; 1583 1584 u16 tx_lvl; 1585 u16 rx_lvl; 1586 u16 tx_rate; 1587 u16 rx_rate; 1588 1589 u32 noa_duration; /* ms */ 1590 }; 1591 1592 struct rtw89_btc_wl_active_role_v2 { 1593 u8 connected: 1; 1594 u8 pid: 3; 1595 u8 phy: 1; 1596 u8 noa: 1; 1597 u8 band: 2; 1598 1599 u8 client_ps: 1; 1600 u8 bw: 7; 1601 1602 u8 role; 1603 u8 ch; 1604 1605 u32 noa_duration; /* ms */ 1606 }; 1607 1608 struct rtw89_btc_wl_active_role_v7 { 1609 u8 connected; 1610 u8 pid; 1611 u8 phy; 1612 u8 noa; 1613 1614 u8 band; 1615 u8 client_ps; 1616 u8 bw; 1617 u8 role; 1618 1619 u8 ch; 1620 u8 noa_dur; 1621 u8 client_cnt; 1622 u8 rsvd2; 1623 } __packed; 1624 1625 struct rtw89_btc_wl_role_info_bpos { 1626 u16 none: 1; 1627 u16 station: 1; 1628 u16 ap: 1; 1629 u16 vap: 1; 1630 u16 adhoc: 1; 1631 u16 adhoc_master: 1; 1632 u16 mesh: 1; 1633 u16 moniter: 1; 1634 u16 p2p_device: 1; 1635 u16 p2p_gc: 1; 1636 u16 p2p_go: 1; 1637 u16 nan: 1; 1638 }; 1639 1640 struct rtw89_btc_wl_scc_ctrl { 1641 u8 null_role1; 1642 u8 null_role2; 1643 u8 ebt_null; /* if tx null at EBT slot */ 1644 }; 1645 1646 union rtw89_btc_wl_role_info_map { 1647 u16 val; 1648 struct rtw89_btc_wl_role_info_bpos role; 1649 }; 1650 1651 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1652 u8 connect_cnt; 1653 u8 link_mode; 1654 union rtw89_btc_wl_role_info_map role_map; 1655 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1656 }; 1657 1658 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1659 u8 connect_cnt; 1660 u8 link_mode; 1661 union rtw89_btc_wl_role_info_map role_map; 1662 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1663 u32 mrole_type; /* btc_wl_mrole_type */ 1664 u32 mrole_noa_duration; /* ms */ 1665 1666 u32 dbcc_en: 1; 1667 u32 dbcc_chg: 1; 1668 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1669 u32 link_mode_chg: 1; 1670 u32 rsvd: 27; 1671 }; 1672 1673 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1674 u8 connect_cnt; 1675 u8 link_mode; 1676 union rtw89_btc_wl_role_info_map role_map; 1677 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1678 u32 mrole_type; /* btc_wl_mrole_type */ 1679 u32 mrole_noa_duration; /* ms */ 1680 1681 u32 dbcc_en: 1; 1682 u32 dbcc_chg: 1; 1683 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1684 u32 link_mode_chg: 1; 1685 u32 rsvd: 27; 1686 }; 1687 1688 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1689 u8 connected; 1690 u8 pid; 1691 u8 phy; 1692 u8 noa; 1693 1694 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1695 u8 active; /* 0:rlink is under doze */ 1696 u8 bw; /* enum channel_width */ 1697 u8 role; /*enum role_type */ 1698 1699 u8 ch; 1700 u8 noa_dur; /* ms */ 1701 u8 client_cnt; /* for Role = P2P-Go/AP */ 1702 u8 mode; /* wifi protocol */ 1703 } __packed; 1704 1705 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1706 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1707 u8 connect_cnt; 1708 u8 link_mode; 1709 u8 link_mode_chg; 1710 u8 p2p_2g; 1711 1712 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1713 1714 u32 role_map; 1715 u32 mrole_type; /* btc_wl_mrole_type */ 1716 u32 mrole_noa_duration; /* ms */ 1717 u32 dbcc_en; 1718 u32 dbcc_chg; 1719 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1720 } __packed; 1721 1722 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1723 u8 connect_cnt; 1724 u8 link_mode; 1725 u8 link_mode_chg; 1726 u8 p2p_2g; 1727 1728 u8 pta_req_band; 1729 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1730 u8 dbcc_chg; 1731 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1732 1733 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1734 1735 u32 role_map; 1736 u32 mrole_type; /* btc_wl_mrole_type */ 1737 u32 mrole_noa_duration; /* ms */ 1738 } __packed; 1739 1740 struct rtw89_btc_wl_ver_info { 1741 u32 fw_coex; /* match with which coex_ver */ 1742 u32 fw; 1743 u32 mac; 1744 u32 bb; 1745 u32 rf; 1746 }; 1747 1748 struct rtw89_btc_wl_afh_info { 1749 u8 en; 1750 u8 ch; 1751 u8 bw; 1752 u8 rsvd; 1753 } __packed; 1754 1755 struct rtw89_btc_wl_rfk_info { 1756 u32 state: 2; 1757 u32 path_map: 4; 1758 u32 phy_map: 2; 1759 u32 band: 2; 1760 u32 type: 8; 1761 u32 rsvd: 14; 1762 1763 u32 start_time; 1764 u32 proc_time; 1765 }; 1766 1767 struct rtw89_btc_bt_smap { 1768 u32 connect: 1; 1769 u32 ble_connect: 1; 1770 u32 acl_busy: 1; 1771 u32 sco_busy: 1; 1772 u32 mesh_busy: 1; 1773 u32 inq_pag: 1; 1774 }; 1775 1776 union rtw89_btc_bt_state_map { 1777 u32 val; 1778 struct rtw89_btc_bt_smap map; 1779 }; 1780 1781 #define BTC_BT_RSSI_THMAX 4 1782 #define BTC_BT_AFH_GROUP 12 1783 #define BTC_BT_AFH_LE_GROUP 5 1784 1785 struct rtw89_btc_bt_link_info { 1786 struct rtw89_btc_u8_sta_chg profile_cnt; 1787 struct rtw89_btc_bool_sta_chg multi_link; 1788 struct rtw89_btc_bool_sta_chg relink; 1789 struct rtw89_btc_bt_hfp_desc hfp_desc; 1790 struct rtw89_btc_bt_hid_desc hid_desc; 1791 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1792 struct rtw89_btc_bt_pan_desc pan_desc; 1793 union rtw89_btc_bt_state_map status; 1794 1795 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1796 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1797 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1798 u8 afh_map[BTC_BT_AFH_GROUP]; 1799 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1800 1801 u32 role_sw: 1; 1802 u32 slave_role: 1; 1803 u32 afh_update: 1; 1804 u32 cqddr: 1; 1805 u32 rssi: 8; 1806 u32 tx_3m: 1; 1807 u32 rsvd: 19; 1808 }; 1809 1810 struct rtw89_btc_3rdcx_info { 1811 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1812 u8 hw_coex; 1813 u16 rsvd; 1814 }; 1815 1816 struct rtw89_btc_dm_emap { 1817 u32 init: 1; 1818 u32 pta_owner: 1; 1819 u32 wl_rfk_timeout: 1; 1820 u32 bt_rfk_timeout: 1; 1821 u32 wl_fw_hang: 1; 1822 u32 cycle_hang: 1; 1823 u32 w1_hang: 1; 1824 u32 b1_hang: 1; 1825 u32 tdma_no_sync: 1; 1826 u32 slot_no_sync: 1; 1827 u32 wl_slot_drift: 1; 1828 u32 bt_slot_drift: 1; 1829 u32 role_num_mismatch: 1; 1830 u32 null1_tx_late: 1; 1831 u32 bt_afh_conflict: 1; 1832 u32 bt_leafh_conflict: 1; 1833 u32 bt_slot_flood: 1; 1834 u32 wl_e2g_hang: 1; 1835 u32 wl_ver_mismatch: 1; 1836 u32 bt_ver_mismatch: 1; 1837 u32 rfe_type0: 1; 1838 u32 h2c_buffer_over: 1; 1839 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1840 u32 wl_no_sta_ntfy: 1; 1841 1842 u32 h2c_bmap_mismatch: 1; 1843 u32 c2h_bmap_mismatch: 1; 1844 u32 h2c_struct_invalid: 1; 1845 u32 c2h_struct_invalid: 1; 1846 u32 h2c_c2h_buffer_mismatch: 1; 1847 }; 1848 1849 union rtw89_btc_dm_error_map { 1850 u32 val; 1851 struct rtw89_btc_dm_emap map; 1852 }; 1853 1854 struct rtw89_btc_rf_para { 1855 u32 tx_pwr_freerun; 1856 u32 rx_gain_freerun; 1857 u32 tx_pwr_perpkt; 1858 u32 rx_gain_perpkt; 1859 }; 1860 1861 struct rtw89_btc_wl_nhm { 1862 u8 instant_wl_nhm_dbm; 1863 u8 instant_wl_nhm_per_mhz; 1864 u16 valid_record_times; 1865 s8 record_pwr[16]; 1866 u8 record_ratio[16]; 1867 s8 pwr; /* dbm_per_MHz */ 1868 u8 ratio; 1869 u8 current_status; 1870 u8 refresh; 1871 bool start_flag; 1872 s8 pwr_max; 1873 s8 pwr_min; 1874 }; 1875 1876 struct rtw89_btc_wl_info { 1877 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1878 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1879 struct rtw89_btc_wl_rfk_info rfk_info; 1880 struct rtw89_btc_wl_ver_info ver_info; 1881 struct rtw89_btc_wl_afh_info afh_info; 1882 struct rtw89_btc_wl_role_info role_info; 1883 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1884 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1885 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1886 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1887 struct rtw89_btc_wl_scan_info scan_info; 1888 struct rtw89_btc_wl_dbcc_info dbcc_info; 1889 struct rtw89_btc_rf_para rf_para; 1890 struct rtw89_btc_wl_nhm nhm; 1891 union rtw89_btc_wl_state_map status; 1892 1893 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1894 u8 rssi_level; 1895 u8 cn_report; 1896 u8 coex_mode; 1897 u8 pta_req_mac; 1898 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */ 1899 1900 bool is_5g_hi_channel; 1901 bool pta_reg_mac_chg; 1902 bool bg_mode; 1903 bool he_mode; 1904 bool scbd_change; 1905 bool fw_ver_mismatch; 1906 bool client_cnt_inc_2g; 1907 u32 scbd; 1908 }; 1909 1910 struct rtw89_btc_module { 1911 struct rtw89_btc_ant_info ant; 1912 u8 rfe_type; 1913 u8 cv; 1914 1915 u8 bt_solo: 1; 1916 u8 bt_pos: 1; 1917 u8 switch_type: 1; 1918 u8 wa_type: 3; 1919 1920 u8 kt_ver_adie; 1921 }; 1922 1923 struct rtw89_btc_module_v7 { 1924 u8 rfe_type; 1925 u8 kt_ver; 1926 u8 bt_solo; 1927 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1928 1929 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1930 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1931 u8 kt_ver_adie; 1932 u8 rsvd; 1933 1934 struct rtw89_btc_ant_info_v7 ant; 1935 } __packed; 1936 1937 union rtw89_btc_module_info { 1938 struct rtw89_btc_module md; 1939 struct rtw89_btc_module_v7 md_v7; 1940 }; 1941 1942 #define RTW89_BTC_DM_MAXSTEP 30 1943 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1944 1945 struct rtw89_btc_dm_step { 1946 u16 step[RTW89_BTC_DM_MAXSTEP]; 1947 u8 step_pos; 1948 bool step_ov; 1949 }; 1950 1951 struct rtw89_btc_init_info { 1952 struct rtw89_btc_module module; 1953 u8 wl_guard_ch; 1954 1955 u8 wl_only: 1; 1956 u8 wl_init_ok: 1; 1957 u8 dbcc_en: 1; 1958 u8 cx_other: 1; 1959 u8 bt_only: 1; 1960 1961 u16 rsvd; 1962 }; 1963 1964 struct rtw89_btc_init_info_v7 { 1965 u8 wl_guard_ch; 1966 u8 wl_only; 1967 u8 wl_init_ok; 1968 u8 rsvd3; 1969 1970 u8 cx_other; 1971 u8 bt_only; 1972 u8 pta_mode; 1973 u8 pta_direction; 1974 1975 struct rtw89_btc_module_v7 module; 1976 } __packed; 1977 1978 union rtw89_btc_init_info_u { 1979 struct rtw89_btc_init_info init; 1980 struct rtw89_btc_init_info_v7 init_v7; 1981 }; 1982 1983 struct rtw89_btc_wl_tx_limit_para { 1984 u16 enable; 1985 u32 tx_time; /* unit: us */ 1986 u16 tx_retry; 1987 }; 1988 1989 enum rtw89_btc_bt_scan_type { 1990 BTC_SCAN_INQ = 0, 1991 BTC_SCAN_PAGE, 1992 BTC_SCAN_BLE, 1993 BTC_SCAN_INIT, 1994 BTC_SCAN_TV, 1995 BTC_SCAN_ADV, 1996 BTC_SCAN_MAX1, 1997 }; 1998 1999 enum rtw89_btc_ble_scan_type { 2000 CXSCAN_BG = 0, 2001 CXSCAN_INIT, 2002 CXSCAN_LE, 2003 CXSCAN_MAX 2004 }; 2005 2006 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2007 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2008 2009 struct rtw89_btc_bt_scan_info_v1 { 2010 __le16 win; 2011 __le16 intvl; 2012 __le32 flags; 2013 } __packed; 2014 2015 struct rtw89_btc_bt_scan_info_v2 { 2016 __le16 win; 2017 __le16 intvl; 2018 } __packed; 2019 2020 struct rtw89_btc_fbtc_btscan_v1 { 2021 u8 fver; /* btc_ver::fcxbtscan */ 2022 u8 rsvd; 2023 __le16 rsvd2; 2024 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2025 } __packed; 2026 2027 struct rtw89_btc_fbtc_btscan_v2 { 2028 u8 fver; /* btc_ver::fcxbtscan */ 2029 u8 type; 2030 __le16 rsvd2; 2031 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2032 } __packed; 2033 2034 struct rtw89_btc_fbtc_btscan_v7 { 2035 u8 fver; /* btc_ver::fcxbtscan */ 2036 u8 type; 2037 u8 rsvd0; 2038 u8 rsvd1; 2039 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2040 } __packed; 2041 2042 union rtw89_btc_fbtc_btscan { 2043 struct rtw89_btc_fbtc_btscan_v1 v1; 2044 struct rtw89_btc_fbtc_btscan_v2 v2; 2045 struct rtw89_btc_fbtc_btscan_v7 v7; 2046 }; 2047 2048 struct rtw89_btc_bt_info { 2049 struct rtw89_btc_bt_link_info link_info; 2050 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2051 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2052 struct rtw89_btc_bt_ver_info ver_info; 2053 struct rtw89_btc_bool_sta_chg enable; 2054 struct rtw89_btc_bool_sta_chg inq_pag; 2055 struct rtw89_btc_rf_para rf_para; 2056 union rtw89_btc_bt_rfk_info_map rfk_info; 2057 2058 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2059 u8 rssi_level; 2060 2061 u32 scbd; 2062 u32 feature; 2063 2064 u32 mbx_avl: 1; 2065 u32 whql_test: 1; 2066 u32 igno_wl: 1; 2067 u32 reinit: 1; 2068 u32 ble_scan_en: 1; 2069 u32 btg_type: 1; 2070 u32 inq: 1; 2071 u32 pag: 1; 2072 u32 run_patch_code: 1; 2073 u32 hi_lna_rx: 1; 2074 u32 scan_rx_low_pri: 1; 2075 u32 scan_info_update: 1; 2076 u32 lna_constrain: 3; 2077 u32 rsvd: 17; 2078 }; 2079 2080 struct rtw89_btc_cx { 2081 struct rtw89_btc_wl_info wl; 2082 struct rtw89_btc_bt_info bt; 2083 struct rtw89_btc_3rdcx_info other; 2084 u32 state_map; 2085 u32 cnt_bt[BTC_BCNT_NUM]; 2086 u32 cnt_wl[BTC_WCNT_NUM]; 2087 }; 2088 2089 struct rtw89_btc_fbtc_tdma { 2090 u8 type; /* btc_ver::fcxtdma */ 2091 u8 rxflctrl; 2092 u8 txpause; 2093 u8 wtgle_n; 2094 u8 leak_n; 2095 u8 ext_ctrl; 2096 u8 rxflctrl_role; 2097 u8 option_ctrl; 2098 } __packed; 2099 2100 struct rtw89_btc_fbtc_tdma_v3 { 2101 u8 fver; /* btc_ver::fcxtdma */ 2102 u8 rsvd; 2103 __le16 rsvd1; 2104 struct rtw89_btc_fbtc_tdma tdma; 2105 } __packed; 2106 2107 union rtw89_btc_fbtc_tdma_le32 { 2108 struct rtw89_btc_fbtc_tdma v1; 2109 struct rtw89_btc_fbtc_tdma_v3 v3; 2110 }; 2111 2112 #define CXMREG_MAX 30 2113 #define CXMREG_MAX_V2 20 2114 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2115 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2116 2117 enum rtw89_btc_bt_sta_counter { 2118 BTC_BCNT_RFK_REQ = 0, 2119 BTC_BCNT_RFK_GO = 1, 2120 BTC_BCNT_RFK_REJECT = 2, 2121 BTC_BCNT_RFK_FAIL = 3, 2122 BTC_BCNT_RFK_TIMEOUT = 4, 2123 BTC_BCNT_HI_TX = 5, 2124 BTC_BCNT_HI_RX = 6, 2125 BTC_BCNT_LO_TX = 7, 2126 BTC_BCNT_LO_RX = 8, 2127 BTC_BCNT_POLLUTED = 9, 2128 BTC_BCNT_STA_MAX 2129 }; 2130 2131 enum rtw89_btc_bt_sta_counter_v105 { 2132 BTC_BCNT_RFK_REQ_V105 = 0, 2133 BTC_BCNT_HI_TX_V105 = 1, 2134 BTC_BCNT_HI_RX_V105 = 2, 2135 BTC_BCNT_LO_TX_V105 = 3, 2136 BTC_BCNT_LO_RX_V105 = 4, 2137 BTC_BCNT_POLLUTED_V105 = 5, 2138 BTC_BCNT_STA_MAX_V105 2139 }; 2140 2141 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2142 u16 fver; /* btc_ver::fcxbtcrpt */ 2143 u16 rpt_cnt; /* tmr counters */ 2144 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2145 u32 wl_fw_cx_offload; 2146 u32 wl_fw_ver; 2147 u32 rpt_enable; 2148 u32 rpt_para; /* ms */ 2149 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2150 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2151 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2152 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2153 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2154 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2155 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2156 u32 c2h_cnt; /* fw send c2h counter */ 2157 u32 h2c_cnt; /* fw recv h2c counter */ 2158 } __packed; 2159 2160 struct rtw89_btc_fbtc_rpt_ctrl_info { 2161 __le32 cnt; /* fw report counter */ 2162 __le32 en; /* report map */ 2163 __le32 para; /* not used */ 2164 2165 __le32 cnt_c2h; /* fw send c2h counter */ 2166 __le32 cnt_h2c; /* fw recv h2c counter */ 2167 __le32 len_c2h; /* The total length of the last C2H */ 2168 2169 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2170 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2171 } __packed; 2172 2173 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2174 __le32 cx_ver; /* match which driver's coex version */ 2175 __le32 fw_ver; 2176 __le32 en; /* report map */ 2177 2178 __le16 cnt; /* fw report counter */ 2179 __le16 cnt_c2h; /* fw send c2h counter */ 2180 __le16 cnt_h2c; /* fw recv h2c counter */ 2181 __le16 len_c2h; /* The total length of the last C2H */ 2182 2183 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2184 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2185 } __packed; 2186 2187 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2188 __le16 cnt; /* fw report counter */ 2189 __le16 cnt_c2h; /* fw send c2h counter */ 2190 __le16 cnt_h2c; /* fw recv h2c counter */ 2191 __le16 len_c2h; /* The total length of the last C2H */ 2192 2193 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2194 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2195 2196 __le32 cx_ver; /* match which driver's coex version */ 2197 __le32 fw_ver; 2198 __le32 en; /* report map */ 2199 } __packed; 2200 2201 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2202 __le32 cx_ver; /* match which driver's coex version */ 2203 __le32 cx_offload; 2204 __le32 fw_ver; 2205 } __packed; 2206 2207 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2208 __le32 cnt_empty; /* a2dp empty count */ 2209 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2210 __le32 cnt_tx; 2211 __le32 cnt_ack; 2212 __le32 cnt_nack; 2213 } __packed; 2214 2215 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2216 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2217 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2218 __le32 cnt_recv; /* fw recv mailbox counter */ 2219 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2220 } __packed; 2221 2222 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2223 u8 fver; 2224 u8 rsvd; 2225 __le16 rsvd1; 2226 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2227 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2228 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2229 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2230 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2231 } __packed; 2232 2233 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2234 u8 fver; 2235 u8 rsvd; 2236 __le16 rsvd1; 2237 2238 u8 gnt_val[RTW89_PHY_MAX][4]; 2239 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2240 2241 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2242 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2243 } __packed; 2244 2245 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2246 u8 fver; 2247 u8 rsvd; 2248 __le16 rsvd1; 2249 2250 u8 gnt_val[RTW89_PHY_MAX][4]; 2251 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2252 2253 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2254 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2255 } __packed; 2256 2257 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2258 u8 fver; 2259 u8 rsvd0; 2260 u8 rsvd1; 2261 u8 rsvd2; 2262 2263 u8 gnt_val[RTW89_PHY_MAX][4]; 2264 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2265 2266 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2267 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2268 } __packed; 2269 2270 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2271 u8 fver; 2272 u8 rsvd0; 2273 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2274 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2275 2276 u8 gnt_val[RTW89_PHY_MAX][4]; 2277 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2278 2279 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2280 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2281 } __packed; 2282 2283 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2284 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2285 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2286 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2287 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2288 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2289 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2290 }; 2291 2292 enum rtw89_fbtc_ext_ctrl_type { 2293 CXECTL_OFF = 0x0, /* tdma off */ 2294 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2295 CXECTL_EXT = 0x2, 2296 CXECTL_MAX 2297 }; 2298 2299 union rtw89_btc_fbtc_rxflct { 2300 u8 val; 2301 u8 type: 3; 2302 u8 tgln_n: 5; 2303 }; 2304 2305 enum rtw89_btc_cxst_state { 2306 CXST_OFF = 0x0, 2307 CXST_B2W = 0x1, 2308 CXST_W1 = 0x2, 2309 CXST_W2 = 0x3, 2310 CXST_W2B = 0x4, 2311 CXST_B1 = 0x5, 2312 CXST_B2 = 0x6, 2313 CXST_B3 = 0x7, 2314 CXST_B4 = 0x8, 2315 CXST_LK = 0x9, 2316 CXST_BLK = 0xa, 2317 CXST_E2G = 0xb, 2318 CXST_E5G = 0xc, 2319 CXST_EBT = 0xd, 2320 CXST_ENULL = 0xe, 2321 CXST_WLK = 0xf, 2322 CXST_W1FDD = 0x10, 2323 CXST_B1FDD = 0x11, 2324 CXST_MAX = 0x12, 2325 }; 2326 2327 enum rtw89_btc_cxevnt { 2328 CXEVNT_TDMA_ENTRY = 0x0, 2329 CXEVNT_WL_TMR, 2330 CXEVNT_B1_TMR, 2331 CXEVNT_B2_TMR, 2332 CXEVNT_B3_TMR, 2333 CXEVNT_B4_TMR, 2334 CXEVNT_W2B_TMR, 2335 CXEVNT_B2W_TMR, 2336 CXEVNT_BCN_EARLY, 2337 CXEVNT_A2DP_EMPTY, 2338 CXEVNT_LK_END, 2339 CXEVNT_RX_ISR, 2340 CXEVNT_RX_FC0, 2341 CXEVNT_RX_FC1, 2342 CXEVNT_BT_RELINK, 2343 CXEVNT_BT_RETRY, 2344 CXEVNT_E2G, 2345 CXEVNT_E5G, 2346 CXEVNT_EBT, 2347 CXEVNT_ENULL, 2348 CXEVNT_DRV_WLK, 2349 CXEVNT_BCN_OK, 2350 CXEVNT_BT_CHANGE, 2351 CXEVNT_EBT_EXTEND, 2352 CXEVNT_E2G_NULL1, 2353 CXEVNT_B1FDD_TMR, 2354 CXEVNT_MAX 2355 }; 2356 2357 enum { 2358 CXBCN_ALL = 0x0, 2359 CXBCN_ALL_OK, 2360 CXBCN_BT_SLOT, 2361 CXBCN_BT_OK, 2362 CXBCN_MAX 2363 }; 2364 2365 enum btc_slot_type { 2366 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2367 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2368 CXSTYPE_NUM, 2369 }; 2370 2371 enum { /* TIME */ 2372 CXT_BT = 0x0, 2373 CXT_WL = 0x1, 2374 CXT_MAX 2375 }; 2376 2377 enum { /* TIME-A2DP */ 2378 CXT_FLCTRL_OFF = 0x0, 2379 CXT_FLCTRL_ON = 0x1, 2380 CXT_FLCTRL_MAX 2381 }; 2382 2383 enum { /* STEP TYPE */ 2384 CXSTEP_NONE = 0x0, 2385 CXSTEP_EVNT = 0x1, 2386 CXSTEP_SLOT = 0x2, 2387 CXSTEP_MAX, 2388 }; 2389 2390 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2391 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2392 RPT_BT_AFH_SEQ_LE = 0x20 2393 }; 2394 2395 #define BTC_DBG_MAX1 32 2396 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2397 u8 fver; /* btc_ver::fcxgpiodbg */ 2398 u8 rsvd; 2399 __le16 rsvd2; 2400 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2401 __le32 pre_state; /* the debug signal is 1 or 0 */ 2402 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2403 } __packed; 2404 2405 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2406 u8 fver; 2407 u8 rsvd0; 2408 u8 rsvd1; 2409 u8 rsvd2; 2410 2411 u8 gpio_map[BTC_DBG_MAX1]; 2412 2413 __le32 en_map; 2414 __le32 pre_state; 2415 } __packed; 2416 2417 union rtw89_btc_fbtc_gpio_dbg { 2418 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2419 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2420 }; 2421 2422 struct rtw89_btc_fbtc_mreg_val_v1 { 2423 u8 fver; /* btc_ver::fcxmreg */ 2424 u8 reg_num; 2425 __le16 rsvd; 2426 __le32 mreg_val[CXMREG_MAX]; 2427 } __packed; 2428 2429 struct rtw89_btc_fbtc_mreg_val_v2 { 2430 u8 fver; /* btc_ver::fcxmreg */ 2431 u8 reg_num; 2432 __le16 rsvd; 2433 __le32 mreg_val[CXMREG_MAX_V2]; 2434 } __packed; 2435 2436 struct rtw89_btc_fbtc_mreg_val_v7 { 2437 u8 fver; 2438 u8 reg_num; 2439 u8 rsvd0; 2440 u8 rsvd1; 2441 __le32 mreg_val[CXMREG_MAX_V2]; 2442 } __packed; 2443 2444 union rtw89_btc_fbtc_mreg_val { 2445 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2446 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2447 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2448 }; 2449 2450 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2451 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2452 .offset = cpu_to_le32(__offset), } 2453 2454 struct rtw89_btc_fbtc_mreg { 2455 __le16 type; 2456 __le16 bytes; 2457 __le32 offset; 2458 } __packed; 2459 2460 struct rtw89_btc_fbtc_slot { 2461 __le16 dur; 2462 __le32 cxtbl; 2463 __le16 cxtype; 2464 } __packed; 2465 2466 struct rtw89_btc_fbtc_slots { 2467 u8 fver; /* btc_ver::fcxslots */ 2468 u8 tbl_num; 2469 __le16 rsvd; 2470 __le32 update_map; 2471 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2472 } __packed; 2473 2474 struct rtw89_btc_fbtc_slot_v7 { 2475 __le16 dur; /* slot duration */ 2476 __le16 cxtype; 2477 __le32 cxtbl; 2478 } __packed; 2479 2480 struct rtw89_btc_fbtc_slot_u16 { 2481 __le16 dur; /* slot duration */ 2482 __le16 cxtype; 2483 __le16 cxtbl_l16; /* coex table [15:0] */ 2484 __le16 cxtbl_h16; /* coex table [31:16] */ 2485 } __packed; 2486 2487 struct rtw89_btc_fbtc_1slot_v7 { 2488 u8 fver; 2489 u8 sid; /* slot id */ 2490 __le16 rsvd; 2491 struct rtw89_btc_fbtc_slot_v7 slot; 2492 } __packed; 2493 2494 struct rtw89_btc_fbtc_slots_v7 { 2495 u8 fver; 2496 u8 slot_cnt; 2497 u8 rsvd0; 2498 u8 rsvd1; 2499 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2500 __le32 update_map; 2501 } __packed; 2502 2503 union rtw89_btc_fbtc_slots_info { 2504 struct rtw89_btc_fbtc_slots v1; 2505 struct rtw89_btc_fbtc_slots_v7 v7; 2506 } __packed; 2507 2508 struct rtw89_btc_fbtc_step { 2509 u8 type; 2510 u8 val; 2511 __le16 difft; 2512 } __packed; 2513 2514 struct rtw89_btc_fbtc_steps_v2 { 2515 u8 fver; /* btc_ver::fcxstep */ 2516 u8 rsvd; 2517 __le16 cnt; 2518 __le16 pos_old; 2519 __le16 pos_new; 2520 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2521 } __packed; 2522 2523 struct rtw89_btc_fbtc_steps_v3 { 2524 u8 fver; 2525 u8 en; 2526 __le16 rsvd; 2527 __le32 cnt; 2528 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2529 } __packed; 2530 2531 union rtw89_btc_fbtc_steps_info { 2532 struct rtw89_btc_fbtc_steps_v2 v2; 2533 struct rtw89_btc_fbtc_steps_v3 v3; 2534 }; 2535 2536 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2537 u8 fver; /* btc_ver::fcxcysta */ 2538 u8 rsvd; 2539 __le16 cycles; /* total cycle number */ 2540 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2541 __le16 a2dpept; /* a2dp empty cnt */ 2542 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2543 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2544 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2545 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2546 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2547 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2548 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2549 __le16 tmax_a2dpept; /* max a2dp empty time */ 2550 __le16 tavg_lk; /* avg leak-slot time */ 2551 __le16 tmax_lk; /* max leak-slot time */ 2552 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2553 __le32 bcn_cnt[CXBCN_MAX]; 2554 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2555 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2556 __le32 skip_cnt; 2557 __le32 exception; 2558 __le32 except_cnt; 2559 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2560 } __packed; 2561 2562 struct rtw89_btc_fbtc_fdd_try_info { 2563 __le16 cycles[CXT_FLCTRL_MAX]; 2564 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2565 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2566 } __packed; 2567 2568 struct rtw89_btc_fbtc_cycle_time_info { 2569 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2570 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2571 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2572 } __packed; 2573 2574 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2575 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2576 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2577 } __packed; 2578 2579 struct rtw89_btc_fbtc_a2dp_trx_stat { 2580 u8 empty_cnt; 2581 u8 retry_cnt; 2582 u8 tx_rate; 2583 u8 tx_cnt; 2584 u8 ack_cnt; 2585 u8 nack_cnt; 2586 u8 rsvd1; 2587 u8 rsvd2; 2588 } __packed; 2589 2590 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2591 u8 empty_cnt; 2592 u8 retry_cnt; 2593 u8 tx_rate; 2594 u8 tx_cnt; 2595 u8 ack_cnt; 2596 u8 nack_cnt; 2597 u8 no_empty_cnt; 2598 u8 rsvd; 2599 } __packed; 2600 2601 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2602 __le16 cnt; /* a2dp empty cnt */ 2603 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2604 __le16 tavg; /* avg a2dp empty time */ 2605 __le16 tmax; /* max a2dp empty time */ 2606 } __packed; 2607 2608 struct rtw89_btc_fbtc_cycle_leak_info { 2609 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2610 __le16 tavg; /* avg leak-slot time */ 2611 __le16 tmax; /* max leak-slot time */ 2612 } __packed; 2613 2614 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2615 __le16 tavg; 2616 __le16 tamx; 2617 __le32 cnt_rximr; 2618 } __packed; 2619 2620 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2621 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2622 2623 struct rtw89_btc_fbtc_cycle_fddt_info { 2624 __le16 train_cycle; 2625 __le16 tp; 2626 2627 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2628 s8 bt_tx_power; /* decrease Tx power (dB) */ 2629 s8 bt_rx_gain; /* LNA constrain level */ 2630 u8 no_empty_cnt; 2631 2632 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2633 u8 cn; /* condition_num */ 2634 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2635 u8 train_result; /* refer to enum btc_fddt_check_map */ 2636 } __packed; 2637 2638 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2639 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2640 2641 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2642 __le16 train_cycle; 2643 __le16 tp; 2644 2645 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2646 s8 bt_tx_power; /* decrease Tx power (dB) */ 2647 s8 bt_rx_gain; /* LNA constrain level */ 2648 u8 no_empty_cnt; 2649 2650 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2651 u8 cn; /* condition_num */ 2652 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2653 u8 train_result; /* refer to enum btc_fddt_check_map */ 2654 } __packed; 2655 2656 struct rtw89_btc_fbtc_fddt_cell_status { 2657 s8 wl_tx_pwr; 2658 s8 bt_tx_pwr; 2659 s8 bt_rx_gain; 2660 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2661 } __packed; 2662 2663 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2664 u8 fver; 2665 u8 rsvd; 2666 __le16 cycles; /* total cycle number */ 2667 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2668 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2669 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2670 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2671 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2672 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2673 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2674 __le32 bcn_cnt[CXBCN_MAX]; 2675 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2676 __le32 skip_cnt; 2677 __le32 except_cnt; 2678 __le32 except_map; 2679 } __packed; 2680 2681 #define FDD_TRAIN_WL_DIRECTION 2 2682 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2683 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2684 2685 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2686 u8 fver; 2687 u8 rsvd; 2688 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2689 u8 except_cnt; 2690 2691 __le16 skip_cnt; 2692 __le16 cycles; /* total cycle number */ 2693 2694 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2695 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2696 __le16 bcn_cnt[CXBCN_MAX]; 2697 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2698 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2699 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2700 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2701 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2702 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2703 [FDD_TRAIN_WL_RSSI_LEVEL] 2704 [FDD_TRAIN_BT_RSSI_LEVEL]; 2705 __le32 except_map; 2706 } __packed; 2707 2708 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2709 u8 fver; 2710 u8 rsvd; 2711 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2712 u8 except_cnt; 2713 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2714 2715 __le16 skip_cnt; 2716 __le16 cycles; /* total cycle number */ 2717 2718 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2719 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2720 __le16 bcn_cnt[CXBCN_MAX]; 2721 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2722 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2723 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2724 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2725 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2726 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2727 [FDD_TRAIN_WL_RSSI_LEVEL] 2728 [FDD_TRAIN_BT_RSSI_LEVEL]; 2729 __le32 except_map; 2730 } __packed; 2731 2732 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2733 u8 fver; 2734 u8 rsvd; 2735 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2736 u8 except_cnt; 2737 2738 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2739 2740 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2741 2742 __le16 skip_cnt; 2743 __le16 cycles; /* total cycle number */ 2744 2745 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2746 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2747 __le16 bcn_cnt[CXBCN_MAX]; 2748 2749 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2750 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2751 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2752 2753 __le32 except_map; 2754 } __packed; 2755 2756 union rtw89_btc_fbtc_cysta_info { 2757 struct rtw89_btc_fbtc_cysta_v2 v2; 2758 struct rtw89_btc_fbtc_cysta_v3 v3; 2759 struct rtw89_btc_fbtc_cysta_v4 v4; 2760 struct rtw89_btc_fbtc_cysta_v5 v5; 2761 struct rtw89_btc_fbtc_cysta_v7 v7; 2762 }; 2763 2764 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2765 u8 fver; /* btc_ver::fcxnullsta */ 2766 u8 rsvd; 2767 __le16 rsvd2; 2768 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2769 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2770 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2771 } __packed; 2772 2773 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2774 u8 fver; /* btc_ver::fcxnullsta */ 2775 u8 rsvd; 2776 __le16 rsvd2; 2777 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2778 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2779 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2780 } __packed; 2781 2782 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2783 u8 fver; 2784 u8 rsvd0; 2785 u8 rsvd1; 2786 u8 rsvd2; 2787 2788 __le32 tmax[2]; 2789 __le32 tavg[2]; 2790 __le32 result[2][5]; 2791 } __packed; 2792 2793 union rtw89_btc_fbtc_cynullsta_info { 2794 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2795 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2796 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2797 }; 2798 2799 struct rtw89_btc_fbtc_btver_v1 { 2800 u8 fver; /* btc_ver::fcxbtver */ 2801 u8 rsvd; 2802 __le16 rsvd2; 2803 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2804 __le32 fw_ver; 2805 __le32 feature; 2806 } __packed; 2807 2808 struct rtw89_btc_fbtc_btver_v7 { 2809 u8 fver; 2810 u8 rsvd0; 2811 u8 rsvd1; 2812 u8 rsvd2; 2813 2814 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2815 __le32 fw_ver; 2816 __le32 feature; 2817 } __packed; 2818 2819 union rtw89_btc_fbtc_btver { 2820 struct rtw89_btc_fbtc_btver_v1 v1; 2821 struct rtw89_btc_fbtc_btver_v7 v7; 2822 } __packed; 2823 2824 struct rtw89_btc_fbtc_btafh { 2825 u8 fver; /* btc_ver::fcxbtafh */ 2826 u8 rsvd; 2827 __le16 rsvd2; 2828 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2829 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2830 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2831 } __packed; 2832 2833 struct rtw89_btc_fbtc_btafh_v2 { 2834 u8 fver; /* btc_ver::fcxbtafh */ 2835 u8 rsvd; 2836 u8 rsvd2; 2837 u8 map_type; 2838 u8 afh_l[4]; 2839 u8 afh_m[4]; 2840 u8 afh_h[4]; 2841 u8 afh_le_a[4]; 2842 u8 afh_le_b[4]; 2843 } __packed; 2844 2845 struct rtw89_btc_fbtc_btafh_v7 { 2846 u8 fver; 2847 u8 map_type; 2848 u8 rsvd0; 2849 u8 rsvd1; 2850 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2851 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2852 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2853 u8 afh_le_a[4]; 2854 u8 afh_le_b[4]; 2855 } __packed; 2856 2857 struct rtw89_btc_fbtc_btdevinfo { 2858 u8 fver; /* btc_ver::fcxbtdevinfo */ 2859 u8 rsvd; 2860 __le16 vendor_id; 2861 __le32 dev_name; /* only 24 bits valid */ 2862 __le32 flush_time; 2863 } __packed; 2864 2865 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2866 struct rtw89_btc_rf_trx_para { 2867 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2868 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2869 u8 bt_tx_power; /* decrease Tx power (dB) */ 2870 u8 bt_rx_gain; /* LNA constrain level */ 2871 }; 2872 2873 struct rtw89_btc_trx_info { 2874 u8 tx_lvl; 2875 u8 rx_lvl; 2876 u8 wl_rssi; 2877 u8 bt_rssi; 2878 2879 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2880 s8 rx_gain; /* rx gain table index (TBD.) */ 2881 s8 bt_tx_power; /* decrease Tx power (dB) */ 2882 s8 bt_rx_gain; /* LNA constrain level */ 2883 2884 u8 cn; /* condition_num */ 2885 s8 nhm; 2886 u8 bt_profile; 2887 u8 rsvd2; 2888 2889 u16 tx_rate; 2890 u16 rx_rate; 2891 2892 u32 tx_tp; 2893 u32 rx_tp; 2894 u32 rx_err_ratio; 2895 }; 2896 2897 union rtw89_btc_fbtc_slot_u { 2898 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2899 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2900 }; 2901 2902 struct rtw89_btc_dm { 2903 union rtw89_btc_fbtc_slot_u slot; 2904 union rtw89_btc_fbtc_slot_u slot_now; 2905 struct rtw89_btc_fbtc_tdma tdma; 2906 struct rtw89_btc_fbtc_tdma tdma_now; 2907 struct rtw89_mac_ax_coex_gnt gnt; 2908 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2909 struct rtw89_btc_rf_trx_para rf_trx_para; 2910 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2911 struct rtw89_btc_dm_step dm_step; 2912 struct rtw89_btc_wl_scc_ctrl wl_scc; 2913 struct rtw89_btc_trx_info trx_info; 2914 union rtw89_btc_dm_error_map error; 2915 u32 cnt_dm[BTC_DCNT_NUM]; 2916 u32 cnt_notify[BTC_NCNT_NUM]; 2917 2918 u32 update_slot_map; 2919 u32 set_ant_path; 2920 u32 e2g_slot_limit; 2921 u32 e2g_slot_nulltx_time; 2922 2923 u32 wl_only: 1; 2924 u32 wl_fw_cx_offload: 1; 2925 u32 freerun: 1; 2926 u32 fddt_train: 1; 2927 u32 wl_ps_ctrl: 2; 2928 u32 wl_mimo_ps: 1; 2929 u32 leak_ap: 1; 2930 u32 noisy_level: 3; 2931 u32 coex_info_map: 8; 2932 u32 bt_only: 1; 2933 u32 wl_btg_rx: 2; 2934 u32 trx_para_level: 8; 2935 u32 wl_stb_chg: 1; 2936 u32 pta_owner: 1; 2937 2938 u32 tdma_instant_excute: 1; 2939 u32 wl_btg_rx_rb: 2; 2940 2941 u16 slot_dur[CXST_MAX]; 2942 u16 bt_slot_flood; 2943 2944 u8 run_reason; 2945 u8 run_action; 2946 2947 u8 wl_pre_agc: 2; 2948 u8 wl_lna2: 1; 2949 u8 freerun_chk: 1; 2950 u8 wl_pre_agc_rb: 2; 2951 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2952 u8 slot_req_more: 1; 2953 }; 2954 2955 struct rtw89_btc_ctrl { 2956 u32 manual: 1; 2957 u32 igno_bt: 1; 2958 u32 always_freerun: 1; 2959 u32 trace_step: 16; 2960 u32 rsvd: 12; 2961 }; 2962 2963 struct rtw89_btc_ctrl_v7 { 2964 u8 manual; 2965 u8 igno_bt; 2966 u8 always_freerun; 2967 u8 rsvd; 2968 } __packed; 2969 2970 union rtw89_btc_ctrl_list { 2971 struct rtw89_btc_ctrl ctrl; 2972 struct rtw89_btc_ctrl_v7 ctrl_v7; 2973 }; 2974 2975 struct rtw89_btc_dbg { 2976 /* cmd "rb" */ 2977 bool rb_done; 2978 u32 rb_val; 2979 }; 2980 2981 enum rtw89_btc_btf_fw_event { 2982 BTF_EVNT_RPT = 0, 2983 BTF_EVNT_BT_INFO = 1, 2984 BTF_EVNT_BT_SCBD = 2, 2985 BTF_EVNT_BT_REG = 3, 2986 BTF_EVNT_CX_RUNINFO = 4, 2987 BTF_EVNT_BT_PSD = 5, 2988 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 2989 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 2990 BTF_EVNT_BUF_OVERFLOW, 2991 BTF_EVNT_C2H_LOOPBACK, 2992 BTF_EVNT_MAX, 2993 }; 2994 2995 enum btf_fw_event_report { 2996 BTC_RPT_TYPE_CTRL = 0x0, 2997 BTC_RPT_TYPE_TDMA, 2998 BTC_RPT_TYPE_SLOT, 2999 BTC_RPT_TYPE_CYSTA, 3000 BTC_RPT_TYPE_STEP, 3001 BTC_RPT_TYPE_NULLSTA, 3002 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3003 BTC_RPT_TYPE_MREG, 3004 BTC_RPT_TYPE_GPIO_DBG, 3005 BTC_RPT_TYPE_BT_VER, 3006 BTC_RPT_TYPE_BT_SCAN, 3007 BTC_RPT_TYPE_BT_AFH, 3008 BTC_RPT_TYPE_BT_DEVICE, 3009 BTC_RPT_TYPE_TEST, 3010 BTC_RPT_TYPE_MAX = 31, 3011 3012 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3013 __BTC_RPT_TYPE_V0_MAX = 12, 3014 }; 3015 3016 enum rtw_btc_btf_reg_type { 3017 REG_MAC = 0x0, 3018 REG_BB = 0x1, 3019 REG_RF = 0x2, 3020 REG_BT_RF = 0x3, 3021 REG_BT_MODEM = 0x4, 3022 REG_BT_BLUEWIZE = 0x5, 3023 REG_BT_VENDOR = 0x6, 3024 REG_BT_LE = 0x7, 3025 REG_MAX_TYPE, 3026 }; 3027 3028 struct rtw89_btc_rpt_cmn_info { 3029 u32 rx_cnt; 3030 u32 rx_len; 3031 u32 req_len; /* expected rsp len */ 3032 u8 req_fver; /* expected rsp fver */ 3033 u8 rsp_fver; /* fver from fw */ 3034 u8 valid; 3035 } __packed; 3036 3037 union rtw89_btc_fbtc_btafh_info { 3038 struct rtw89_btc_fbtc_btafh v1; 3039 struct rtw89_btc_fbtc_btafh_v2 v2; 3040 }; 3041 3042 struct rtw89_btc_report_ctrl_state { 3043 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3044 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3045 }; 3046 3047 struct rtw89_btc_rpt_fbtc_tdma { 3048 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3049 union rtw89_btc_fbtc_tdma_le32 finfo; 3050 }; 3051 3052 struct rtw89_btc_rpt_fbtc_slots { 3053 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3054 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3055 }; 3056 3057 struct rtw89_btc_rpt_fbtc_cysta { 3058 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3059 union rtw89_btc_fbtc_cysta_info finfo; 3060 }; 3061 3062 struct rtw89_btc_rpt_fbtc_step { 3063 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3064 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3065 }; 3066 3067 struct rtw89_btc_rpt_fbtc_nullsta { 3068 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3069 union rtw89_btc_fbtc_cynullsta_info finfo; 3070 }; 3071 3072 struct rtw89_btc_rpt_fbtc_mreg { 3073 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3074 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3075 }; 3076 3077 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3078 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3079 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3080 }; 3081 3082 struct rtw89_btc_rpt_fbtc_btver { 3083 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3084 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3085 }; 3086 3087 struct rtw89_btc_rpt_fbtc_btscan { 3088 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3089 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3090 }; 3091 3092 struct rtw89_btc_rpt_fbtc_btafh { 3093 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3094 union rtw89_btc_fbtc_btafh_info finfo; 3095 }; 3096 3097 struct rtw89_btc_rpt_fbtc_btdev { 3098 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3099 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3100 }; 3101 3102 enum rtw89_btc_btfre_type { 3103 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3104 BTFRE_UNDEF_TYPE, 3105 BTFRE_EXCEPTION, 3106 BTFRE_MAX, 3107 }; 3108 3109 struct rtw89_btc_btf_fwinfo { 3110 u32 cnt_c2h; 3111 u32 cnt_h2c; 3112 u32 cnt_h2c_fail; 3113 u32 event[BTF_EVNT_MAX]; 3114 3115 u32 err[BTFRE_MAX]; 3116 u32 len_mismch; 3117 u32 fver_mismch; 3118 u32 rpt_en_map; 3119 3120 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3121 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3122 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3123 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3124 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3125 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3126 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3127 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3128 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3129 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3130 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3131 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3132 }; 3133 3134 struct rtw89_btc_ver { 3135 enum rtw89_core_chip_id chip_id; 3136 u32 fw_ver_code; 3137 3138 u8 fcxbtcrpt; 3139 u8 fcxtdma; 3140 u8 fcxslots; 3141 u8 fcxcysta; 3142 u8 fcxstep; 3143 u8 fcxnullsta; 3144 u8 fcxmreg; 3145 u8 fcxgpiodbg; 3146 u8 fcxbtver; 3147 u8 fcxbtscan; 3148 u8 fcxbtafh; 3149 u8 fcxbtdevinfo; 3150 u8 fwlrole; 3151 u8 frptmap; 3152 u8 fcxctrl; 3153 u8 fcxinit; 3154 3155 u8 fwevntrptl; 3156 u8 fwc2hfunc; 3157 u8 drvinfo_type; 3158 u16 info_buf; 3159 u8 max_role_num; 3160 }; 3161 3162 #define RTW89_BTC_POLICY_MAXLEN 512 3163 3164 struct rtw89_btc { 3165 const struct rtw89_btc_ver *ver; 3166 3167 struct rtw89_btc_cx cx; 3168 struct rtw89_btc_dm dm; 3169 union rtw89_btc_ctrl_list ctrl; 3170 union rtw89_btc_module_info mdinfo; 3171 struct rtw89_btc_btf_fwinfo fwinfo; 3172 struct rtw89_btc_dbg dbg; 3173 3174 struct work_struct eapol_notify_work; 3175 struct work_struct arp_notify_work; 3176 struct work_struct dhcp_notify_work; 3177 struct work_struct icmp_notify_work; 3178 3179 u32 bt_req_len; 3180 3181 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3182 u8 ant_type; 3183 u8 btg_pos; 3184 u16 policy_len; 3185 u16 policy_type; 3186 u32 hubmsg_cnt; 3187 bool bt_req_en; 3188 bool update_policy_force; 3189 bool lps; 3190 bool manual_ctrl; 3191 }; 3192 3193 enum rtw89_btc_hmsg { 3194 RTW89_BTC_HMSG_TMR_EN = 0x0, 3195 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3196 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3197 RTW89_BTC_HMSG_FW_EV = 0x3, 3198 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3199 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3200 3201 NUM_OF_RTW89_BTC_HMSG, 3202 }; 3203 3204 enum rtw89_ra_mode { 3205 RTW89_RA_MODE_CCK = BIT(0), 3206 RTW89_RA_MODE_OFDM = BIT(1), 3207 RTW89_RA_MODE_HT = BIT(2), 3208 RTW89_RA_MODE_VHT = BIT(3), 3209 RTW89_RA_MODE_HE = BIT(4), 3210 RTW89_RA_MODE_EHT = BIT(5), 3211 }; 3212 3213 enum rtw89_ra_report_mode { 3214 RTW89_RA_RPT_MODE_LEGACY, 3215 RTW89_RA_RPT_MODE_HT, 3216 RTW89_RA_RPT_MODE_VHT, 3217 RTW89_RA_RPT_MODE_HE, 3218 RTW89_RA_RPT_MODE_EHT, 3219 }; 3220 3221 enum rtw89_dig_noisy_level { 3222 RTW89_DIG_NOISY_LEVEL0 = -1, 3223 RTW89_DIG_NOISY_LEVEL1 = 0, 3224 RTW89_DIG_NOISY_LEVEL2 = 1, 3225 RTW89_DIG_NOISY_LEVEL3 = 2, 3226 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3227 }; 3228 3229 enum rtw89_gi_ltf { 3230 RTW89_GILTF_LGI_4XHE32 = 0, 3231 RTW89_GILTF_SGI_4XHE08 = 1, 3232 RTW89_GILTF_2XHE16 = 2, 3233 RTW89_GILTF_2XHE08 = 3, 3234 RTW89_GILTF_1XHE16 = 4, 3235 RTW89_GILTF_1XHE08 = 5, 3236 RTW89_GILTF_MAX 3237 }; 3238 3239 enum rtw89_rx_frame_type { 3240 RTW89_RX_TYPE_MGNT = 0, 3241 RTW89_RX_TYPE_CTRL = 1, 3242 RTW89_RX_TYPE_DATA = 2, 3243 RTW89_RX_TYPE_RSVD = 3, 3244 }; 3245 3246 enum rtw89_efuse_block { 3247 RTW89_EFUSE_BLOCK_SYS = 0, 3248 RTW89_EFUSE_BLOCK_RF = 1, 3249 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3250 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3251 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3252 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3253 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3254 RTW89_EFUSE_BLOCK_ADIE = 7, 3255 3256 RTW89_EFUSE_BLOCK_NUM, 3257 RTW89_EFUSE_BLOCK_IGNORE, 3258 }; 3259 3260 struct rtw89_ra_info { 3261 u8 is_dis_ra:1; 3262 /* Bit0 : CCK 3263 * Bit1 : OFDM 3264 * Bit2 : HT 3265 * Bit3 : VHT 3266 * Bit4 : HE 3267 * Bit5 : EHT 3268 */ 3269 u8 mode_ctrl:6; 3270 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3271 u8 macid; 3272 u8 dcm_cap:1; 3273 u8 er_cap:1; 3274 u8 init_rate_lv:2; 3275 u8 upd_all:1; 3276 u8 en_sgi:1; 3277 u8 ldpc_cap:1; 3278 u8 stbc_cap:1; 3279 u8 ss_num:3; 3280 u8 giltf:3; 3281 u8 upd_bw_nss_mask:1; 3282 u8 upd_mask:1; 3283 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3284 /* BFee CSI */ 3285 u8 band_num; 3286 u8 ra_csi_rate_en:1; 3287 u8 fixed_csi_rate_en:1; 3288 u8 cr_tbl_sel:1; 3289 u8 fix_giltf_en:1; 3290 u8 fix_giltf:3; 3291 u8 rsvd2:1; 3292 u8 csi_mcs_ss_idx; 3293 u8 csi_mode:2; 3294 u8 csi_gi_ltf:3; 3295 u8 csi_bw:3; 3296 }; 3297 3298 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3299 #define RTW89_PPDU_MAC_INFO_SIZE 8 3300 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3301 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3302 3303 #define RTW89_MAX_RX_AGG_NUM 64 3304 #define RTW89_MAX_TX_AGG_NUM 128 3305 3306 struct rtw89_ampdu_params { 3307 u16 agg_num; 3308 bool amsdu; 3309 }; 3310 3311 struct rtw89_ra_report { 3312 struct rate_info txrate; 3313 u32 bit_rate; 3314 u16 hw_rate; 3315 bool might_fallback_legacy; 3316 }; 3317 3318 DECLARE_EWMA(rssi, 10, 16); 3319 DECLARE_EWMA(evm, 10, 16); 3320 DECLARE_EWMA(snr, 10, 16); 3321 3322 struct rtw89_ba_cam_entry { 3323 struct list_head list; 3324 u8 tid; 3325 }; 3326 3327 #define RTW89_MAX_ADDR_CAM_NUM 128 3328 #define RTW89_MAX_BSSID_CAM_NUM 20 3329 #define RTW89_MAX_SEC_CAM_NUM 128 3330 #define RTW89_MAX_BA_CAM_NUM 24 3331 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3332 3333 struct rtw89_addr_cam_entry { 3334 u8 addr_cam_idx; 3335 u8 offset; 3336 u8 len; 3337 u8 valid : 1; 3338 u8 addr_mask : 6; 3339 u8 wapi : 1; 3340 u8 mask_sel : 2; 3341 u8 bssid_cam_idx: 6; 3342 3343 u8 sec_ent_mode; 3344 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3345 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3346 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3347 }; 3348 3349 struct rtw89_bssid_cam_entry { 3350 u8 bssid[ETH_ALEN]; 3351 u8 phy_idx; 3352 u8 bssid_cam_idx; 3353 u8 offset; 3354 u8 len; 3355 u8 valid : 1; 3356 u8 num; 3357 }; 3358 3359 struct rtw89_sec_cam_entry { 3360 u8 sec_cam_idx; 3361 u8 offset; 3362 u8 len; 3363 u8 type : 4; 3364 u8 ext_key : 1; 3365 u8 spp_mode : 1; 3366 /* 256 bits */ 3367 u8 key[32]; 3368 3369 struct ieee80211_key_conf *key_conf; 3370 }; 3371 3372 struct rtw89_sta_link { 3373 struct rtw89_sta *rtwsta; 3374 unsigned int link_id; 3375 3376 u8 mac_id; 3377 bool er_cap; 3378 struct rtw89_vif_link *rtwvif_link; 3379 struct rtw89_ra_info ra; 3380 struct rtw89_ra_report ra_report; 3381 int max_agg_wait; 3382 u8 prev_rssi; 3383 struct ewma_rssi avg_rssi; 3384 struct ewma_rssi rssi[RF_PATH_MAX]; 3385 struct ewma_snr avg_snr; 3386 struct ewma_evm evm_1ss; 3387 struct ewma_evm evm_min[RF_PATH_MAX]; 3388 struct ewma_evm evm_max[RF_PATH_MAX]; 3389 struct ieee80211_rx_status rx_status; 3390 u16 rx_hw_rate; 3391 __le32 htc_template; 3392 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3393 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3394 struct list_head ba_cam_list; 3395 3396 bool use_cfg_mask; 3397 struct cfg80211_bitrate_mask mask; 3398 3399 bool cctl_tx_time; 3400 u32 ampdu_max_time:4; 3401 bool cctl_tx_retry_limit; 3402 u32 data_tx_cnt_lmt:6; 3403 }; 3404 3405 struct rtw89_efuse { 3406 bool valid; 3407 bool power_k_valid; 3408 u8 xtal_cap; 3409 u8 addr[ETH_ALEN]; 3410 u8 rfe_type; 3411 char country_code[2]; 3412 }; 3413 3414 struct rtw89_phy_rate_pattern { 3415 u64 ra_mask; 3416 u16 rate; 3417 u8 ra_mode; 3418 bool enable; 3419 }; 3420 3421 struct rtw89_tx_wait_info { 3422 struct rcu_head rcu_head; 3423 struct completion completion; 3424 bool tx_done; 3425 }; 3426 3427 struct rtw89_tx_skb_data { 3428 struct rtw89_tx_wait_info __rcu *wait; 3429 u8 hci_priv[]; 3430 }; 3431 3432 #define RTW89_ROC_IDLE_TIMEOUT 500 3433 #define RTW89_ROC_TX_TIMEOUT 30 3434 enum rtw89_roc_state { 3435 RTW89_ROC_IDLE, 3436 RTW89_ROC_NORMAL, 3437 RTW89_ROC_MGMT, 3438 }; 3439 3440 #define RTW89_ROC_BY_LINK_INDEX 0 3441 3442 struct rtw89_roc { 3443 struct ieee80211_channel chan; 3444 struct delayed_work roc_work; 3445 enum ieee80211_roc_type type; 3446 enum rtw89_roc_state state; 3447 int duration; 3448 }; 3449 3450 #define RTW89_P2P_MAX_NOA_NUM 2 3451 3452 struct rtw89_p2p_ie_head { 3453 u8 eid; 3454 u8 ie_len; 3455 u8 oui[3]; 3456 u8 oui_type; 3457 } __packed; 3458 3459 struct rtw89_noa_attr_head { 3460 u8 attr_type; 3461 __le16 attr_len; 3462 u8 index; 3463 u8 oppps_ctwindow; 3464 } __packed; 3465 3466 struct rtw89_p2p_noa_ie { 3467 struct rtw89_p2p_ie_head p2p_head; 3468 struct rtw89_noa_attr_head noa_head; 3469 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3470 } __packed; 3471 3472 struct rtw89_p2p_noa_setter { 3473 struct rtw89_p2p_noa_ie ie; 3474 u8 noa_count; 3475 u8 noa_index; 3476 }; 3477 3478 struct rtw89_vif_link { 3479 struct rtw89_vif *rtwvif; 3480 unsigned int link_id; 3481 3482 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3483 enum rtw89_chanctx_idx chanctx_idx; 3484 enum rtw89_reg_6ghz_power reg_6ghz_power; 3485 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3486 3487 u8 mac_id; 3488 u8 port; 3489 u8 mac_addr[ETH_ALEN]; 3490 u8 bssid[ETH_ALEN]; 3491 u8 phy_idx; 3492 u8 mac_idx; 3493 u8 net_type; 3494 u8 wifi_role; 3495 u8 self_role; 3496 u8 wmm; 3497 u8 bcn_hit_cond; 3498 u8 hit_rule; 3499 u8 last_noa_nr; 3500 u64 sync_bcn_tsf; 3501 bool trigger; 3502 bool lsig_txop; 3503 u8 tgt_ind; 3504 u8 frm_tgt_ind; 3505 bool wowlan_pattern; 3506 bool wowlan_uc; 3507 bool wowlan_magic; 3508 bool is_hesta; 3509 bool last_a_ctrl; 3510 bool dyn_tb_bedge_en; 3511 bool pre_pwr_diff_en; 3512 bool pwr_diff_en; 3513 u8 def_tri_idx; 3514 struct work_struct update_beacon_work; 3515 struct rtw89_addr_cam_entry addr_cam; 3516 struct rtw89_bssid_cam_entry bssid_cam; 3517 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3518 struct rtw89_phy_rate_pattern rate_pattern; 3519 struct list_head general_pkt_list; 3520 struct rtw89_p2p_noa_setter p2p_noa; 3521 }; 3522 3523 enum rtw89_lv1_rcvy_step { 3524 RTW89_LV1_RCVY_STEP_1, 3525 RTW89_LV1_RCVY_STEP_2, 3526 }; 3527 3528 struct rtw89_hci_ops { 3529 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3530 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3531 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3532 void (*reset)(struct rtw89_dev *rtwdev); 3533 int (*start)(struct rtw89_dev *rtwdev); 3534 void (*stop)(struct rtw89_dev *rtwdev); 3535 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3536 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3537 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3538 3539 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3540 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3541 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3542 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3543 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3544 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3545 3546 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3547 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3548 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3549 int (*deinit)(struct rtw89_dev *rtwdev); 3550 3551 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3552 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3553 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3554 int (*napi_poll)(struct napi_struct *napi, int budget); 3555 3556 /* Deal with locks inside recovery_start and recovery_complete callbacks 3557 * by hci instance, and handle things which need to consider under SER. 3558 * e.g. turn on/off interrupts except for the one for halt notification. 3559 */ 3560 void (*recovery_start)(struct rtw89_dev *rtwdev); 3561 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3562 3563 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3564 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3565 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3566 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3567 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3568 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3569 void (*disable_intr)(struct rtw89_dev *rtwdev); 3570 void (*enable_intr)(struct rtw89_dev *rtwdev); 3571 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3572 }; 3573 3574 struct rtw89_hci_info { 3575 const struct rtw89_hci_ops *ops; 3576 enum rtw89_hci_type type; 3577 u32 rpwm_addr; 3578 u32 cpwm_addr; 3579 bool paused; 3580 }; 3581 3582 struct rtw89_chip_ops { 3583 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3584 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3585 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3586 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3587 void (*bb_reset)(struct rtw89_dev *rtwdev, 3588 enum rtw89_phy_idx phy_idx); 3589 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3590 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3591 u32 addr, u32 mask); 3592 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3593 u32 addr, u32 mask, u32 data); 3594 void (*set_channel)(struct rtw89_dev *rtwdev, 3595 const struct rtw89_chan *chan, 3596 enum rtw89_mac_idx mac_idx, 3597 enum rtw89_phy_idx phy_idx); 3598 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3599 struct rtw89_channel_help_params *p, 3600 const struct rtw89_chan *chan, 3601 enum rtw89_mac_idx mac_idx, 3602 enum rtw89_phy_idx phy_idx); 3603 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3604 enum rtw89_efuse_block block); 3605 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3606 void (*fem_setup)(struct rtw89_dev *rtwdev); 3607 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3608 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3609 void (*rfk_init)(struct rtw89_dev *rtwdev); 3610 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3611 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3612 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3613 enum rtw89_phy_idx phy_idx, 3614 const struct rtw89_chan *chan); 3615 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3616 bool start); 3617 void (*rfk_track)(struct rtw89_dev *rtwdev); 3618 void (*power_trim)(struct rtw89_dev *rtwdev); 3619 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3620 const struct rtw89_chan *chan, 3621 enum rtw89_phy_idx phy_idx); 3622 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3623 enum rtw89_phy_idx phy_idx); 3624 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3625 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3626 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3627 enum rtw89_phy_idx phy_idx); 3628 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3629 struct rtw89_rx_phy_ppdu *phy_ppdu, 3630 struct ieee80211_rx_status *status); 3631 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3632 struct rtw89_rx_phy_ppdu *phy_ppdu); 3633 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3634 struct rtw89_rx_desc_info *desc_info, 3635 struct ieee80211_rx_status *rx_status); 3636 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3637 enum rtw89_phy_idx phy_idx); 3638 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3639 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3640 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3641 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3642 enum rtw89_phy_idx phy_idx); 3643 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3644 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3645 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3646 struct rtw89_rx_desc_info *desc_info, 3647 u8 *data, u32 data_offset); 3648 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3649 struct rtw89_tx_desc_info *desc_info, 3650 void *txdesc); 3651 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3652 struct rtw89_tx_desc_info *desc_info, 3653 void *txdesc); 3654 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3655 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3656 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3657 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3658 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3659 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3660 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3661 struct rtw89_vif_link *rtwvif_link, 3662 struct rtw89_sta_link *rtwsta_link); 3663 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3664 struct rtw89_vif_link *rtwvif_link, 3665 struct rtw89_sta_link *rtwsta_link); 3666 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3667 struct rtw89_vif_link *rtwvif_link, 3668 struct rtw89_sta_link *rtwsta_link); 3669 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3670 struct rtw89_vif_link *rtwvif_link, 3671 struct rtw89_sta_link *rtwsta_link); 3672 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3673 struct rtw89_vif_link *rtwvif_link, 3674 struct rtw89_sta_link *rtwsta_link); 3675 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3676 struct rtw89_vif_link *rtwvif_link); 3677 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3678 struct rtw89_vif_link *rtwvif_link, 3679 struct rtw89_sta_link *rtwsta_link, 3680 bool valid, struct ieee80211_ampdu_params *params); 3681 3682 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3683 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3684 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3685 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3686 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3687 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3688 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3689 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3690 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3691 }; 3692 3693 enum rtw89_dma_ch { 3694 RTW89_DMA_ACH0 = 0, 3695 RTW89_DMA_ACH1 = 1, 3696 RTW89_DMA_ACH2 = 2, 3697 RTW89_DMA_ACH3 = 3, 3698 RTW89_DMA_ACH4 = 4, 3699 RTW89_DMA_ACH5 = 5, 3700 RTW89_DMA_ACH6 = 6, 3701 RTW89_DMA_ACH7 = 7, 3702 RTW89_DMA_B0MG = 8, 3703 RTW89_DMA_B0HI = 9, 3704 RTW89_DMA_B1MG = 10, 3705 RTW89_DMA_B1HI = 11, 3706 RTW89_DMA_H2C = 12, 3707 RTW89_DMA_CH_NUM = 13 3708 }; 3709 3710 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3711 3712 enum rtw89_mlo_dbcc_mode { 3713 MLO_DBCC_NOT_SUPPORT = 1, 3714 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3715 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3716 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3717 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3718 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3719 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3720 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3721 DBCC_LEGACY = 0xffffffff, 3722 }; 3723 3724 enum rtw89_scan_be_operation { 3725 RTW89_SCAN_OP_STOP, 3726 RTW89_SCAN_OP_START, 3727 RTW89_SCAN_OP_SETPARM, 3728 RTW89_SCAN_OP_GETRPT, 3729 RTW89_SCAN_OP_NUM 3730 }; 3731 3732 enum rtw89_scan_be_mode { 3733 RTW89_SCAN_MODE_SA, 3734 RTW89_SCAN_MODE_MACC, 3735 RTW89_SCAN_MODE_NUM 3736 }; 3737 3738 enum rtw89_scan_be_opmode { 3739 RTW89_SCAN_OPMODE_NONE, 3740 RTW89_SCAN_OPMODE_TBTT, 3741 RTW89_SCAN_OPMODE_INTV, 3742 RTW89_SCAN_OPMODE_CNT, 3743 RTW89_SCAN_OPMODE_NUM, 3744 }; 3745 3746 struct rtw89_scan_option { 3747 bool enable; 3748 bool target_ch_mode; 3749 u8 num_macc_role; 3750 u8 num_opch; 3751 u8 repeat; 3752 u16 norm_pd; 3753 u16 slow_pd; 3754 u16 norm_cy; 3755 u8 opch_end; 3756 u16 delay; 3757 u64 prohib_chan; 3758 enum rtw89_phy_idx band; 3759 enum rtw89_scan_be_operation operation; 3760 enum rtw89_scan_be_mode scan_mode; 3761 enum rtw89_mlo_dbcc_mode mlo_mode; 3762 }; 3763 3764 enum rtw89_qta_mode { 3765 RTW89_QTA_SCC, 3766 RTW89_QTA_DBCC, 3767 RTW89_QTA_DLFW, 3768 RTW89_QTA_WOW, 3769 3770 /* keep last */ 3771 RTW89_QTA_INVALID, 3772 }; 3773 3774 struct rtw89_hfc_ch_cfg { 3775 u16 min; 3776 u16 max; 3777 #define grp_0 0 3778 #define grp_1 1 3779 #define grp_num 2 3780 u8 grp; 3781 }; 3782 3783 struct rtw89_hfc_ch_info { 3784 u16 aval; 3785 u16 used; 3786 }; 3787 3788 struct rtw89_hfc_pub_cfg { 3789 u16 grp0; 3790 u16 grp1; 3791 u16 pub_max; 3792 u16 wp_thrd; 3793 }; 3794 3795 struct rtw89_hfc_pub_info { 3796 u16 g0_used; 3797 u16 g1_used; 3798 u16 g0_aval; 3799 u16 g1_aval; 3800 u16 pub_aval; 3801 u16 wp_aval; 3802 }; 3803 3804 struct rtw89_hfc_prec_cfg { 3805 u16 ch011_prec; 3806 u16 h2c_prec; 3807 u16 wp_ch07_prec; 3808 u16 wp_ch811_prec; 3809 u8 ch011_full_cond; 3810 u8 h2c_full_cond; 3811 u8 wp_ch07_full_cond; 3812 u8 wp_ch811_full_cond; 3813 }; 3814 3815 struct rtw89_hfc_param { 3816 bool en; 3817 bool h2c_en; 3818 u8 mode; 3819 const struct rtw89_hfc_ch_cfg *ch_cfg; 3820 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3821 struct rtw89_hfc_pub_cfg pub_cfg; 3822 struct rtw89_hfc_pub_info pub_info; 3823 struct rtw89_hfc_prec_cfg prec_cfg; 3824 }; 3825 3826 struct rtw89_hfc_param_ini { 3827 const struct rtw89_hfc_ch_cfg *ch_cfg; 3828 const struct rtw89_hfc_pub_cfg *pub_cfg; 3829 const struct rtw89_hfc_prec_cfg *prec_cfg; 3830 u8 mode; 3831 }; 3832 3833 struct rtw89_dle_size { 3834 u16 pge_size; 3835 u16 lnk_pge_num; 3836 u16 unlnk_pge_num; 3837 /* for WiFi 7 chips below */ 3838 u32 srt_ofst; 3839 }; 3840 3841 struct rtw89_wde_quota { 3842 u16 hif; 3843 u16 wcpu; 3844 u16 pkt_in; 3845 u16 cpu_io; 3846 }; 3847 3848 struct rtw89_ple_quota { 3849 u16 cma0_tx; 3850 u16 cma1_tx; 3851 u16 c2h; 3852 u16 h2c; 3853 u16 wcpu; 3854 u16 mpdu_proc; 3855 u16 cma0_dma; 3856 u16 cma1_dma; 3857 u16 bb_rpt; 3858 u16 wd_rel; 3859 u16 cpu_io; 3860 u16 tx_rpt; 3861 /* for WiFi 7 chips below */ 3862 u16 h2d; 3863 }; 3864 3865 struct rtw89_rsvd_quota { 3866 u16 mpdu_info_tbl; 3867 u16 b0_csi; 3868 u16 b1_csi; 3869 u16 b0_lmr; 3870 u16 b1_lmr; 3871 u16 b0_ftm; 3872 u16 b1_ftm; 3873 u16 b0_smr; 3874 u16 b1_smr; 3875 u16 others; 3876 }; 3877 3878 struct rtw89_dle_rsvd_size { 3879 u32 srt_ofst; 3880 u32 size; 3881 }; 3882 3883 struct rtw89_dle_mem { 3884 enum rtw89_qta_mode mode; 3885 const struct rtw89_dle_size *wde_size; 3886 const struct rtw89_dle_size *ple_size; 3887 const struct rtw89_wde_quota *wde_min_qt; 3888 const struct rtw89_wde_quota *wde_max_qt; 3889 const struct rtw89_ple_quota *ple_min_qt; 3890 const struct rtw89_ple_quota *ple_max_qt; 3891 /* for WiFi 7 chips below */ 3892 const struct rtw89_rsvd_quota *rsvd_qt; 3893 const struct rtw89_dle_rsvd_size *rsvd0_size; 3894 const struct rtw89_dle_rsvd_size *rsvd1_size; 3895 }; 3896 3897 struct rtw89_reg_def { 3898 u32 addr; 3899 u32 mask; 3900 }; 3901 3902 struct rtw89_reg2_def { 3903 u32 addr; 3904 u32 data; 3905 }; 3906 3907 struct rtw89_reg3_def { 3908 u32 addr; 3909 u32 mask; 3910 u32 data; 3911 }; 3912 3913 struct rtw89_reg5_def { 3914 u8 flag; /* recognized by parsers */ 3915 u8 path; 3916 u32 addr; 3917 u32 mask; 3918 u32 data; 3919 }; 3920 3921 struct rtw89_reg_imr { 3922 u32 addr; 3923 u32 clr; 3924 u32 set; 3925 }; 3926 3927 struct rtw89_phy_table { 3928 const struct rtw89_reg2_def *regs; 3929 u32 n_regs; 3930 enum rtw89_rf_path rf_path; 3931 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3932 enum rtw89_rf_path rf_path, void *data); 3933 }; 3934 3935 struct rtw89_txpwr_table { 3936 const void *data; 3937 u32 size; 3938 void (*load)(struct rtw89_dev *rtwdev, 3939 const struct rtw89_txpwr_table *tbl); 3940 }; 3941 3942 struct rtw89_txpwr_rule_2ghz { 3943 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3944 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3945 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3946 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3947 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3948 }; 3949 3950 struct rtw89_txpwr_rule_5ghz { 3951 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3952 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3953 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3954 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3955 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3956 }; 3957 3958 struct rtw89_txpwr_rule_6ghz { 3959 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3960 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3961 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3962 [RTW89_6G_CH_NUM]; 3963 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3964 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3965 [RTW89_6G_CH_NUM]; 3966 }; 3967 3968 struct rtw89_tx_shape { 3969 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3970 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3971 }; 3972 3973 struct rtw89_rfe_parms { 3974 const struct rtw89_txpwr_table *byr_tbl; 3975 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3976 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3977 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3978 struct rtw89_tx_shape tx_shape; 3979 }; 3980 3981 struct rtw89_rfe_parms_conf { 3982 const struct rtw89_rfe_parms *rfe_parms; 3983 u8 rfe_type; 3984 }; 3985 3986 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3987 3988 struct rtw89_txpwr_conf { 3989 u8 rfe_type; 3990 u8 ent_sz; 3991 u32 num_ents; 3992 const void *data; 3993 }; 3994 3995 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 3996 const struct rtw89_txpwr_conf *conf) 3997 { 3998 u8 valid_size = min(size, conf->ent_sz); 3999 4000 memcpy(entry, cursor, valid_size); 4001 return true; 4002 } 4003 4004 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4005 4006 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4007 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4008 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4009 (cursor) += (conf)->ent_sz) \ 4010 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4011 4012 struct rtw89_txpwr_byrate_data { 4013 struct rtw89_txpwr_conf conf; 4014 struct rtw89_txpwr_table tbl; 4015 }; 4016 4017 struct rtw89_txpwr_lmt_2ghz_data { 4018 struct rtw89_txpwr_conf conf; 4019 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4020 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4021 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4022 }; 4023 4024 struct rtw89_txpwr_lmt_5ghz_data { 4025 struct rtw89_txpwr_conf conf; 4026 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4027 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4028 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4029 }; 4030 4031 struct rtw89_txpwr_lmt_6ghz_data { 4032 struct rtw89_txpwr_conf conf; 4033 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4034 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4035 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4036 [RTW89_6G_CH_NUM]; 4037 }; 4038 4039 struct rtw89_txpwr_lmt_ru_2ghz_data { 4040 struct rtw89_txpwr_conf conf; 4041 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4042 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4043 }; 4044 4045 struct rtw89_txpwr_lmt_ru_5ghz_data { 4046 struct rtw89_txpwr_conf conf; 4047 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4048 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4049 }; 4050 4051 struct rtw89_txpwr_lmt_ru_6ghz_data { 4052 struct rtw89_txpwr_conf conf; 4053 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4054 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4055 [RTW89_6G_CH_NUM]; 4056 }; 4057 4058 struct rtw89_tx_shape_lmt_data { 4059 struct rtw89_txpwr_conf conf; 4060 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4061 }; 4062 4063 struct rtw89_tx_shape_lmt_ru_data { 4064 struct rtw89_txpwr_conf conf; 4065 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4066 }; 4067 4068 struct rtw89_rfe_data { 4069 struct rtw89_txpwr_byrate_data byrate; 4070 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4071 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4072 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4073 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4074 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4075 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4076 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4077 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4078 struct rtw89_rfe_parms rfe_parms; 4079 }; 4080 4081 struct rtw89_page_regs { 4082 u32 hci_fc_ctrl; 4083 u32 ch_page_ctrl; 4084 u32 ach_page_ctrl; 4085 u32 ach_page_info; 4086 u32 pub_page_info3; 4087 u32 pub_page_ctrl1; 4088 u32 pub_page_ctrl2; 4089 u32 pub_page_info1; 4090 u32 pub_page_info2; 4091 u32 wp_page_ctrl1; 4092 u32 wp_page_ctrl2; 4093 u32 wp_page_info1; 4094 }; 4095 4096 struct rtw89_imr_info { 4097 u32 wdrls_imr_set; 4098 u32 wsec_imr_reg; 4099 u32 wsec_imr_set; 4100 u32 mpdu_tx_imr_set; 4101 u32 mpdu_rx_imr_set; 4102 u32 sta_sch_imr_set; 4103 u32 txpktctl_imr_b0_reg; 4104 u32 txpktctl_imr_b0_clr; 4105 u32 txpktctl_imr_b0_set; 4106 u32 txpktctl_imr_b1_reg; 4107 u32 txpktctl_imr_b1_clr; 4108 u32 txpktctl_imr_b1_set; 4109 u32 wde_imr_clr; 4110 u32 wde_imr_set; 4111 u32 ple_imr_clr; 4112 u32 ple_imr_set; 4113 u32 host_disp_imr_clr; 4114 u32 host_disp_imr_set; 4115 u32 cpu_disp_imr_clr; 4116 u32 cpu_disp_imr_set; 4117 u32 other_disp_imr_clr; 4118 u32 other_disp_imr_set; 4119 u32 bbrpt_com_err_imr_reg; 4120 u32 bbrpt_chinfo_err_imr_reg; 4121 u32 bbrpt_err_imr_set; 4122 u32 bbrpt_dfs_err_imr_reg; 4123 u32 ptcl_imr_clr; 4124 u32 ptcl_imr_set; 4125 u32 cdma_imr_0_reg; 4126 u32 cdma_imr_0_clr; 4127 u32 cdma_imr_0_set; 4128 u32 cdma_imr_1_reg; 4129 u32 cdma_imr_1_clr; 4130 u32 cdma_imr_1_set; 4131 u32 phy_intf_imr_reg; 4132 u32 phy_intf_imr_clr; 4133 u32 phy_intf_imr_set; 4134 u32 rmac_imr_reg; 4135 u32 rmac_imr_clr; 4136 u32 rmac_imr_set; 4137 u32 tmac_imr_reg; 4138 u32 tmac_imr_clr; 4139 u32 tmac_imr_set; 4140 }; 4141 4142 struct rtw89_imr_table { 4143 const struct rtw89_reg_imr *regs; 4144 u32 n_regs; 4145 }; 4146 4147 struct rtw89_xtal_info { 4148 u32 xcap_reg; 4149 u32 sc_xo_mask; 4150 u32 sc_xi_mask; 4151 }; 4152 4153 struct rtw89_rrsr_cfgs { 4154 struct rtw89_reg3_def ref_rate; 4155 struct rtw89_reg3_def rsc; 4156 }; 4157 4158 struct rtw89_rfkill_regs { 4159 struct rtw89_reg3_def pinmux; 4160 struct rtw89_reg3_def mode; 4161 }; 4162 4163 struct rtw89_dig_regs { 4164 u32 seg0_pd_reg; 4165 u32 pd_lower_bound_mask; 4166 u32 pd_spatial_reuse_en; 4167 u32 bmode_pd_reg; 4168 u32 bmode_cca_rssi_limit_en; 4169 u32 bmode_pd_lower_bound_reg; 4170 u32 bmode_rssi_nocca_low_th_mask; 4171 struct rtw89_reg_def p0_lna_init; 4172 struct rtw89_reg_def p1_lna_init; 4173 struct rtw89_reg_def p0_tia_init; 4174 struct rtw89_reg_def p1_tia_init; 4175 struct rtw89_reg_def p0_rxb_init; 4176 struct rtw89_reg_def p1_rxb_init; 4177 struct rtw89_reg_def p0_p20_pagcugc_en; 4178 struct rtw89_reg_def p0_s20_pagcugc_en; 4179 struct rtw89_reg_def p1_p20_pagcugc_en; 4180 struct rtw89_reg_def p1_s20_pagcugc_en; 4181 }; 4182 4183 struct rtw89_edcca_regs { 4184 u32 edcca_level; 4185 u32 edcca_mask; 4186 u32 edcca_p_mask; 4187 u32 ppdu_level; 4188 u32 ppdu_mask; 4189 u32 rpt_a; 4190 u32 rpt_b; 4191 u32 rpt_sel; 4192 u32 rpt_sel_mask; 4193 u32 rpt_sel_be; 4194 u32 rpt_sel_be_mask; 4195 u32 tx_collision_t2r_st; 4196 u32 tx_collision_t2r_st_mask; 4197 }; 4198 4199 struct rtw89_phy_ul_tb_info { 4200 bool dyn_tb_tri_en; 4201 u8 def_if_bandedge; 4202 }; 4203 4204 struct rtw89_antdiv_stats { 4205 struct ewma_rssi cck_rssi_avg; 4206 struct ewma_rssi ofdm_rssi_avg; 4207 struct ewma_rssi non_legacy_rssi_avg; 4208 u16 pkt_cnt_cck; 4209 u16 pkt_cnt_ofdm; 4210 u16 pkt_cnt_non_legacy; 4211 u32 evm; 4212 }; 4213 4214 struct rtw89_antdiv_info { 4215 struct rtw89_antdiv_stats target_stats; 4216 struct rtw89_antdiv_stats main_stats; 4217 struct rtw89_antdiv_stats aux_stats; 4218 u8 training_count; 4219 u8 rssi_pre; 4220 bool get_stats; 4221 }; 4222 4223 enum rtw89_chanctx_state { 4224 RTW89_CHANCTX_STATE_MCC_START, 4225 RTW89_CHANCTX_STATE_MCC_STOP, 4226 }; 4227 4228 enum rtw89_chanctx_callbacks { 4229 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4230 RTW89_CHANCTX_CALLBACK_RFK, 4231 4232 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4233 }; 4234 4235 struct rtw89_chanctx_listener { 4236 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4237 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4238 }; 4239 4240 struct rtw89_chip_info { 4241 enum rtw89_core_chip_id chip_id; 4242 enum rtw89_chip_gen chip_gen; 4243 const struct rtw89_chip_ops *ops; 4244 const struct rtw89_mac_gen_def *mac_def; 4245 const struct rtw89_phy_gen_def *phy_def; 4246 const char *fw_basename; 4247 u8 fw_format_max; 4248 bool try_ce_fw; 4249 u8 bbmcu_nr; 4250 u32 needed_fw_elms; 4251 u32 fifo_size; 4252 bool small_fifo_size; 4253 u32 dle_scc_rsvd_size; 4254 u16 max_amsdu_limit; 4255 bool dis_2g_40m_ul_ofdma; 4256 u32 rsvd_ple_ofst; 4257 const struct rtw89_hfc_param_ini *hfc_param_ini; 4258 const struct rtw89_dle_mem *dle_mem; 4259 u8 wde_qempty_acq_grpnum; 4260 u8 wde_qempty_mgq_grpsel; 4261 u32 rf_base_addr[2]; 4262 u8 thermal_th[2]; 4263 u8 support_macid_num; 4264 u8 support_link_num; 4265 u8 support_chanctx_num; 4266 u8 support_bands; 4267 u16 support_bandwidths; 4268 bool support_unii4; 4269 bool support_rnr; 4270 bool support_ant_gain; 4271 bool ul_tb_waveform_ctrl; 4272 bool ul_tb_pwr_diff; 4273 bool hw_sec_hdr; 4274 bool hw_mgmt_tx_encrypt; 4275 u8 rf_path_num; 4276 u8 tx_nss; 4277 u8 rx_nss; 4278 u8 acam_num; 4279 u8 bcam_num; 4280 u8 scam_num; 4281 u8 bacam_num; 4282 u8 bacam_dynamic_num; 4283 enum rtw89_bacam_ver bacam_ver; 4284 u8 ppdu_max_usr; 4285 4286 u8 sec_ctrl_efuse_size; 4287 u32 physical_efuse_size; 4288 u32 logical_efuse_size; 4289 u32 limit_efuse_size; 4290 u32 dav_phy_efuse_size; 4291 u32 dav_log_efuse_size; 4292 u32 phycap_addr; 4293 u32 phycap_size; 4294 const struct rtw89_efuse_block_cfg *efuse_blocks; 4295 4296 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4297 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4298 const struct rtw89_phy_table *bb_table; 4299 const struct rtw89_phy_table *bb_gain_table; 4300 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4301 const struct rtw89_phy_table *nctl_table; 4302 const struct rtw89_rfk_tbl *nctl_post_table; 4303 const struct rtw89_phy_dig_gain_table *dig_table; 4304 const struct rtw89_dig_regs *dig_regs; 4305 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4306 4307 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4308 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4309 const struct rtw89_rfe_parms *dflt_parms; 4310 const struct rtw89_chanctx_listener *chanctx_listener; 4311 4312 u8 txpwr_factor_bb; 4313 u8 txpwr_factor_rf; 4314 u8 txpwr_factor_mac; 4315 4316 u32 para_ver; 4317 u32 wlcx_desired; 4318 u8 btcx_desired; 4319 u8 scbd; 4320 u8 mailbox; 4321 4322 u8 afh_guard_ch; 4323 const u8 *wl_rssi_thres; 4324 const u8 *bt_rssi_thres; 4325 u8 rssi_tol; 4326 4327 u8 mon_reg_num; 4328 const struct rtw89_btc_fbtc_mreg *mon_reg; 4329 u8 rf_para_ulink_num; 4330 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4331 u8 rf_para_dlink_num; 4332 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4333 u8 ps_mode_supported; 4334 u8 low_power_hci_modes; 4335 4336 u32 h2c_cctl_func_id; 4337 u32 hci_func_en_addr; 4338 u32 h2c_desc_size; 4339 u32 txwd_body_size; 4340 u32 txwd_info_size; 4341 u32 h2c_ctrl_reg; 4342 const u32 *h2c_regs; 4343 struct rtw89_reg_def h2c_counter_reg; 4344 u32 c2h_ctrl_reg; 4345 const u32 *c2h_regs; 4346 struct rtw89_reg_def c2h_counter_reg; 4347 const struct rtw89_page_regs *page_regs; 4348 const u32 *wow_reason_reg; 4349 bool cfo_src_fd; 4350 bool cfo_hw_comp; 4351 const struct rtw89_reg_def *dcfo_comp; 4352 u8 dcfo_comp_sft; 4353 const struct rtw89_imr_info *imr_info; 4354 const struct rtw89_imr_table *imr_dmac_table; 4355 const struct rtw89_imr_table *imr_cmac_table; 4356 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4357 struct rtw89_reg_def bss_clr_vld; 4358 u32 bss_clr_map_reg; 4359 const struct rtw89_rfkill_regs *rfkill_init; 4360 struct rtw89_reg_def rfkill_get; 4361 u32 dma_ch_mask; 4362 const struct rtw89_edcca_regs *edcca_regs; 4363 const struct wiphy_wowlan_support *wowlan_stub; 4364 const struct rtw89_xtal_info *xtal_info; 4365 }; 4366 4367 union rtw89_bus_info { 4368 const struct rtw89_pci_info *pci; 4369 }; 4370 4371 struct rtw89_driver_info { 4372 const struct rtw89_chip_info *chip; 4373 const struct dmi_system_id *quirks; 4374 union rtw89_bus_info bus; 4375 }; 4376 4377 enum rtw89_hcifc_mode { 4378 RTW89_HCIFC_POH = 0, 4379 RTW89_HCIFC_STF = 1, 4380 RTW89_HCIFC_SDIO = 2, 4381 4382 /* keep last */ 4383 RTW89_HCIFC_MODE_INVALID, 4384 }; 4385 4386 struct rtw89_dle_info { 4387 const struct rtw89_rsvd_quota *rsvd_qt; 4388 enum rtw89_qta_mode qta_mode; 4389 u16 ple_pg_size; 4390 u16 ple_free_pg; 4391 u16 c0_rx_qta; 4392 u16 c1_rx_qta; 4393 }; 4394 4395 enum rtw89_host_rpr_mode { 4396 RTW89_RPR_MODE_POH = 0, 4397 RTW89_RPR_MODE_STF 4398 }; 4399 4400 #define RTW89_COMPLETION_BUF_SIZE 40 4401 #define RTW89_WAIT_COND_IDLE UINT_MAX 4402 4403 struct rtw89_completion_data { 4404 bool err; 4405 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4406 }; 4407 4408 struct rtw89_wait_info { 4409 atomic_t cond; 4410 struct completion completion; 4411 struct rtw89_completion_data data; 4412 }; 4413 4414 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4415 4416 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4417 { 4418 init_completion(&wait->completion); 4419 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4420 } 4421 4422 struct rtw89_mac_info { 4423 struct rtw89_dle_info dle_info; 4424 struct rtw89_hfc_param hfc_param; 4425 enum rtw89_qta_mode qta_mode; 4426 u8 rpwm_seq_num; 4427 u8 cpwm_seq_num; 4428 4429 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4430 struct rtw89_wait_info fw_ofld_wait; 4431 /* see RTW89_PS_WAIT_COND series for wait condition */ 4432 struct rtw89_wait_info ps_wait; 4433 }; 4434 4435 enum rtw89_fwdl_check_type { 4436 RTW89_FWDL_CHECK_FREERTOS_DONE, 4437 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4438 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4439 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4440 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4441 }; 4442 4443 enum rtw89_fw_type { 4444 RTW89_FW_NORMAL = 1, 4445 RTW89_FW_WOWLAN = 3, 4446 RTW89_FW_NORMAL_CE = 5, 4447 RTW89_FW_BBMCU0 = 64, 4448 RTW89_FW_BBMCU1 = 65, 4449 RTW89_FW_LOGFMT = 255, 4450 }; 4451 4452 enum rtw89_fw_feature { 4453 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4454 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4455 RTW89_FW_FEATURE_TX_WAKE, 4456 RTW89_FW_FEATURE_CRASH_TRIGGER, 4457 RTW89_FW_FEATURE_NO_PACKET_DROP, 4458 RTW89_FW_FEATURE_NO_DEEP_PS, 4459 RTW89_FW_FEATURE_NO_LPS_PG, 4460 RTW89_FW_FEATURE_BEACON_FILTER, 4461 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4462 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4463 RTW89_FW_FEATURE_WOW_REASON_V1, 4464 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4465 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4466 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4467 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4468 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4469 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4470 RTW89_FW_FEATURE_LPS_CH_INFO, 4471 }; 4472 4473 struct rtw89_fw_suit { 4474 enum rtw89_fw_type type; 4475 const u8 *data; 4476 u32 size; 4477 u8 major_ver; 4478 u8 minor_ver; 4479 u8 sub_ver; 4480 u8 sub_idex; 4481 u16 build_year; 4482 u16 build_mon; 4483 u16 build_date; 4484 u16 build_hour; 4485 u16 build_min; 4486 u8 cmd_ver; 4487 u8 hdr_ver; 4488 u32 commitid; 4489 }; 4490 4491 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4492 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4493 #define RTW89_FW_SUIT_VER_CODE(s) \ 4494 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4495 4496 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4497 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4498 (mfw_hdr)->ver.minor, \ 4499 (mfw_hdr)->ver.sub, \ 4500 (mfw_hdr)->ver.idx) 4501 4502 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4503 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4504 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4505 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4506 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4507 4508 struct rtw89_fw_req_info { 4509 const struct firmware *firmware; 4510 struct completion completion; 4511 }; 4512 4513 struct rtw89_fw_log { 4514 struct rtw89_fw_suit suit; 4515 bool enable; 4516 u32 last_fmt_id; 4517 u32 fmt_count; 4518 const __le32 *fmt_ids; 4519 const char *(*fmts)[]; 4520 }; 4521 4522 struct rtw89_fw_elm_info { 4523 struct rtw89_phy_table *bb_tbl; 4524 struct rtw89_phy_table *bb_gain; 4525 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4526 struct rtw89_phy_table *rf_nctl; 4527 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4528 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4529 }; 4530 4531 enum rtw89_fw_mss_dev_type { 4532 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4533 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4534 }; 4535 4536 struct rtw89_fw_secure { 4537 bool secure_boot: 1; 4538 bool can_mss_v1: 1; 4539 bool can_mss_v0: 1; 4540 u32 sb_sel_mgn; 4541 u8 mss_dev_type; 4542 u8 mss_cust_idx; 4543 u8 mss_key_num; 4544 u8 mss_idx; /* v0 */ 4545 }; 4546 4547 struct rtw89_fw_info { 4548 struct rtw89_fw_req_info req; 4549 int fw_format; 4550 u8 h2c_seq; 4551 u8 rec_seq; 4552 u8 h2c_counter; 4553 u8 c2h_counter; 4554 struct rtw89_fw_suit normal; 4555 struct rtw89_fw_suit wowlan; 4556 struct rtw89_fw_suit bbmcu0; 4557 struct rtw89_fw_suit bbmcu1; 4558 struct rtw89_fw_log log; 4559 u32 feature_map; 4560 struct rtw89_fw_elm_info elm_info; 4561 struct rtw89_fw_secure sec; 4562 }; 4563 4564 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4565 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4566 4567 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4568 ((_fw)->feature_map |= BIT(_fw_feature)) 4569 4570 struct rtw89_cam_info { 4571 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4572 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4573 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4574 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4575 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4576 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4577 }; 4578 4579 enum rtw89_sar_sources { 4580 RTW89_SAR_SOURCE_NONE, 4581 RTW89_SAR_SOURCE_COMMON, 4582 4583 RTW89_SAR_SOURCE_NR, 4584 }; 4585 4586 enum rtw89_sar_subband { 4587 RTW89_SAR_2GHZ_SUBBAND, 4588 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4589 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4590 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4591 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4592 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4593 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4594 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4595 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4596 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4597 4598 RTW89_SAR_SUBBAND_NR, 4599 }; 4600 4601 struct rtw89_sar_cfg_common { 4602 bool set[RTW89_SAR_SUBBAND_NR]; 4603 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4604 }; 4605 4606 struct rtw89_sar_info { 4607 /* used to decide how to acces SAR cfg union */ 4608 enum rtw89_sar_sources src; 4609 4610 /* reserved for different knids of SAR cfg struct. 4611 * supposed that a single cfg struct cannot handle various SAR sources. 4612 */ 4613 union { 4614 struct rtw89_sar_cfg_common cfg_common; 4615 }; 4616 }; 4617 4618 enum rtw89_ant_gain_subband { 4619 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4620 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4621 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4622 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4623 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4624 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4625 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4626 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4627 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4628 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4629 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4630 4631 RTW89_ANT_GAIN_SUBBAND_NR, 4632 }; 4633 4634 enum rtw89_ant_gain_domain_type { 4635 RTW89_ANT_GAIN_ETSI = 0, 4636 4637 RTW89_ANT_GAIN_DOMAIN_NUM, 4638 }; 4639 4640 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4641 struct rtw89_ant_gain_info { 4642 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4643 u32 regd_enabled; 4644 }; 4645 4646 struct rtw89_6ghz_span { 4647 enum rtw89_sar_subband sar_subband_low; 4648 enum rtw89_sar_subband sar_subband_high; 4649 enum rtw89_ant_gain_subband ant_gain_subband_low; 4650 enum rtw89_ant_gain_subband ant_gain_subband_high; 4651 }; 4652 4653 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4654 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4655 4656 enum rtw89_tas_state { 4657 RTW89_TAS_STATE_DPR_OFF, 4658 RTW89_TAS_STATE_DPR_ON, 4659 RTW89_TAS_STATE_DPR_FORBID, 4660 }; 4661 4662 #define RTW89_TAS_MAX_WINDOW 50 4663 struct rtw89_tas_info { 4664 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4665 s32 total_txpwr; 4666 u8 cur_idx; 4667 s8 dpr_gap; 4668 s8 delta; 4669 enum rtw89_tas_state state; 4670 bool enable; 4671 }; 4672 4673 struct rtw89_chanctx_cfg { 4674 enum rtw89_chanctx_idx idx; 4675 int ref_count; 4676 }; 4677 4678 enum rtw89_chanctx_changes { 4679 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4680 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4681 RTW89_CHANCTX_P2P_PS_CHANGE, 4682 RTW89_CHANCTX_BT_SLOT_CHANGE, 4683 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4684 4685 NUM_OF_RTW89_CHANCTX_CHANGES, 4686 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4687 }; 4688 4689 enum rtw89_entity_mode { 4690 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4691 RTW89_ENTITY_MODE_MCC_PREPARE, 4692 RTW89_ENTITY_MODE_MCC, 4693 4694 NUM_OF_RTW89_ENTITY_MODE, 4695 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4696 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4697 }; 4698 4699 #define RTW89_MAX_INTERFACE_NUM 2 4700 4701 /* only valid when running with chanctx_ops */ 4702 struct rtw89_entity_mgnt { 4703 struct list_head active_list; 4704 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4705 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4706 [__RTW89_MLD_MAX_LINK_NUM]; 4707 }; 4708 4709 struct rtw89_chanctx { 4710 struct cfg80211_chan_def chandef; 4711 struct rtw89_chan chan; 4712 struct rtw89_chan_rcd rcd; 4713 4714 /* only assigned when running with chanctx_ops */ 4715 struct rtw89_chanctx_cfg *cfg; 4716 }; 4717 4718 struct rtw89_edcca_bak { 4719 u8 a; 4720 u8 p; 4721 u8 ppdu; 4722 u8 th_old; 4723 }; 4724 4725 enum rtw89_dm_type { 4726 RTW89_DM_DYNAMIC_EDCCA, 4727 RTW89_DM_THERMAL_PROTECT, 4728 }; 4729 4730 #define RTW89_THERMAL_PROT_LV_MAX 5 4731 #define RTW89_THERMAL_PROT_STEP 19 /* -19% for each level */ 4732 4733 struct rtw89_hal { 4734 u32 rx_fltr; 4735 u8 cv; 4736 u8 acv; 4737 u32 antenna_tx; 4738 u32 antenna_rx; 4739 u8 tx_nss; 4740 u8 rx_nss; 4741 bool tx_path_diversity; 4742 bool ant_diversity; 4743 bool ant_diversity_fixed; 4744 bool support_cckpd; 4745 bool support_igi; 4746 atomic_t roc_chanctx_idx; 4747 4748 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4749 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4750 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4751 struct cfg80211_chan_def roc_chandef; 4752 4753 bool entity_active[RTW89_PHY_MAX]; 4754 bool entity_pause; 4755 enum rtw89_entity_mode entity_mode; 4756 struct rtw89_entity_mgnt entity_mgnt; 4757 4758 struct rtw89_edcca_bak edcca_bak; 4759 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4760 4761 u8 thermal_prot_th; 4762 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 4763 }; 4764 4765 #define RTW89_MAX_MAC_ID_NUM 128 4766 #define RTW89_MAX_PKT_OFLD_NUM 255 4767 4768 enum rtw89_flags { 4769 RTW89_FLAG_POWERON, 4770 RTW89_FLAG_DMAC_FUNC, 4771 RTW89_FLAG_CMAC0_FUNC, 4772 RTW89_FLAG_CMAC1_FUNC, 4773 RTW89_FLAG_FW_RDY, 4774 RTW89_FLAG_RUNNING, 4775 RTW89_FLAG_PROBE_DONE, 4776 RTW89_FLAG_BFEE_MON, 4777 RTW89_FLAG_BFEE_EN, 4778 RTW89_FLAG_BFEE_TIMER_KEEP, 4779 RTW89_FLAG_NAPI_RUNNING, 4780 RTW89_FLAG_LEISURE_PS, 4781 RTW89_FLAG_LOW_POWER_MODE, 4782 RTW89_FLAG_INACTIVE_PS, 4783 RTW89_FLAG_CRASH_SIMULATING, 4784 RTW89_FLAG_SER_HANDLING, 4785 RTW89_FLAG_WOWLAN, 4786 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4787 RTW89_FLAG_CHANGING_INTERFACE, 4788 RTW89_FLAG_HW_RFKILL_STATE, 4789 4790 NUM_OF_RTW89_FLAGS, 4791 }; 4792 4793 enum rtw89_quirks { 4794 RTW89_QUIRK_PCI_BER, 4795 RTW89_QUIRK_THERMAL_PROT_120C, 4796 RTW89_QUIRK_THERMAL_PROT_110C, 4797 4798 NUM_OF_RTW89_QUIRKS, 4799 }; 4800 4801 enum rtw89_custid { 4802 RTW89_CUSTID_NONE, 4803 RTW89_CUSTID_ACER, 4804 RTW89_CUSTID_AMD, 4805 RTW89_CUSTID_ASUS, 4806 RTW89_CUSTID_DELL, 4807 RTW89_CUSTID_HP, 4808 RTW89_CUSTID_LENOVO, 4809 }; 4810 4811 enum rtw89_pkt_drop_sel { 4812 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4813 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4814 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4815 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4816 RTW89_PKT_DROP_SEL_MACID_ALL, 4817 RTW89_PKT_DROP_SEL_MG0_ONCE, 4818 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4819 RTW89_PKT_DROP_SEL_HIQ_PORT, 4820 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4821 RTW89_PKT_DROP_SEL_BAND, 4822 RTW89_PKT_DROP_SEL_BAND_ONCE, 4823 RTW89_PKT_DROP_SEL_REL_MACID, 4824 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4825 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4826 }; 4827 4828 struct rtw89_pkt_drop_params { 4829 enum rtw89_pkt_drop_sel sel; 4830 enum rtw89_mac_idx mac_band; 4831 u8 macid; 4832 u8 port; 4833 u8 mbssid; 4834 bool tf_trs; 4835 u32 macid_band_sel[4]; 4836 }; 4837 4838 struct rtw89_pkt_stat { 4839 u16 beacon_nr; 4840 u8 beacon_rate; 4841 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4842 }; 4843 4844 DECLARE_EWMA(thermal, 4, 4); 4845 4846 struct rtw89_phy_stat { 4847 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4848 u8 last_thermal_max; 4849 struct ewma_rssi bcn_rssi; 4850 struct rtw89_pkt_stat cur_pkt_stat; 4851 struct rtw89_pkt_stat last_pkt_stat; 4852 }; 4853 4854 enum rtw89_rfk_report_state { 4855 RTW89_RFK_STATE_START = 0x0, 4856 RTW89_RFK_STATE_OK = 0x1, 4857 RTW89_RFK_STATE_FAIL = 0x2, 4858 RTW89_RFK_STATE_TIMEOUT = 0x3, 4859 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4860 }; 4861 4862 struct rtw89_rfk_wait_info { 4863 struct completion completion; 4864 ktime_t start_time; 4865 enum rtw89_rfk_report_state state; 4866 u8 version; 4867 }; 4868 4869 #define RTW89_DACK_PATH_NR 2 4870 #define RTW89_DACK_IDX_NR 2 4871 #define RTW89_DACK_MSBK_NR 16 4872 struct rtw89_dack_info { 4873 bool dack_done; 4874 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4875 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4876 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4877 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4878 u32 dack_cnt; 4879 bool addck_timeout[RTW89_DACK_PATH_NR]; 4880 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4881 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4882 }; 4883 4884 enum rtw89_rfk_chs_nrs { 4885 __RTW89_RFK_CHS_NR_V0 = 2, 4886 __RTW89_RFK_CHS_NR_V1 = 3, 4887 4888 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 4889 }; 4890 4891 struct rtw89_rfk_mcc_info_data { 4892 u8 ch[RTW89_RFK_CHS_NR]; 4893 u8 band[RTW89_RFK_CHS_NR]; 4894 u8 bw[RTW89_RFK_CHS_NR]; 4895 u8 table_idx; 4896 }; 4897 4898 struct rtw89_rfk_mcc_info { 4899 struct rtw89_rfk_mcc_info_data data[2]; 4900 }; 4901 4902 #define RTW89_IQK_CHS_NR 2 4903 #define RTW89_IQK_PATH_NR 4 4904 4905 struct rtw89_lck_info { 4906 u8 thermal[RF_PATH_MAX]; 4907 }; 4908 4909 struct rtw89_rx_dck_info { 4910 u8 thermal[RF_PATH_MAX]; 4911 }; 4912 4913 struct rtw89_iqk_info { 4914 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4915 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4916 bool lok_fail[RTW89_IQK_PATH_NR]; 4917 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4918 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4919 u32 iqk_fail_cnt; 4920 bool is_iqk_init; 4921 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4922 u8 iqk_band[RTW89_IQK_PATH_NR]; 4923 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4924 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4925 u8 iqk_times; 4926 u8 version; 4927 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4928 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4929 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4930 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4931 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4932 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4933 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4934 bool is_nbiqk; 4935 bool iqk_fft_en; 4936 bool iqk_xym_en; 4937 bool iqk_sram_en; 4938 bool iqk_cfir_en; 4939 u32 syn1to2; 4940 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4941 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4942 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4943 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4944 }; 4945 4946 #define RTW89_DPK_RF_PATH 2 4947 #define RTW89_DPK_AVG_THERMAL_NUM 8 4948 #define RTW89_DPK_BKUP_NUM 2 4949 struct rtw89_dpk_bkup_para { 4950 enum rtw89_band band; 4951 enum rtw89_bandwidth bw; 4952 u8 ch; 4953 bool path_ok; 4954 u8 mdpd_en; 4955 u8 txagc_dpk; 4956 u8 ther_dpk; 4957 u8 gs; 4958 u16 pwsf; 4959 }; 4960 4961 struct rtw89_dpk_info { 4962 bool is_dpk_enable; 4963 bool is_dpk_reload_en; 4964 u8 dpk_gs[RTW89_PHY_MAX]; 4965 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4966 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4967 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4968 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4969 u8 cur_idx[RTW89_DPK_RF_PATH]; 4970 u8 cur_k_set; 4971 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4972 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 4973 u32 dpk_order[RTW89_DPK_RF_PATH]; 4974 }; 4975 4976 struct rtw89_fem_info { 4977 bool elna_2g; 4978 bool elna_5g; 4979 bool epa_2g; 4980 bool epa_5g; 4981 bool epa_6g; 4982 }; 4983 4984 struct rtw89_phy_ch_info { 4985 u8 rssi_min; 4986 u16 rssi_min_macid; 4987 u8 pre_rssi_min; 4988 u8 rssi_max; 4989 u16 rssi_max_macid; 4990 u8 rxsc_160; 4991 u8 rxsc_80; 4992 u8 rxsc_40; 4993 u8 rxsc_20; 4994 u8 rxsc_l; 4995 u8 is_noisy; 4996 }; 4997 4998 struct rtw89_agc_gaincode_set { 4999 u8 lna_idx; 5000 u8 tia_idx; 5001 u8 rxb_idx; 5002 }; 5003 5004 #define IGI_RSSI_TH_NUM 5 5005 #define FA_TH_NUM 4 5006 #define TIA_LNA_OP1DB_NUM 8 5007 #define LNA_GAIN_NUM 7 5008 #define TIA_GAIN_NUM 2 5009 struct rtw89_dig_info { 5010 struct rtw89_agc_gaincode_set cur_gaincode; 5011 bool force_gaincode_idx_en; 5012 struct rtw89_agc_gaincode_set force_gaincode; 5013 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5014 u16 fa_th[FA_TH_NUM]; 5015 u8 igi_rssi; 5016 u8 igi_fa_rssi; 5017 u8 fa_rssi_ofst; 5018 u8 dyn_igi_max; 5019 u8 dyn_igi_min; 5020 bool dyn_pd_th_en; 5021 u8 dyn_pd_th_max; 5022 u8 pd_low_th_ofst; 5023 u8 ib_pbk; 5024 s8 ib_pkpwr; 5025 s8 lna_gain_a[LNA_GAIN_NUM]; 5026 s8 lna_gain_g[LNA_GAIN_NUM]; 5027 s8 *lna_gain; 5028 s8 tia_gain_a[TIA_GAIN_NUM]; 5029 s8 tia_gain_g[TIA_GAIN_NUM]; 5030 s8 *tia_gain; 5031 bool is_linked_pre; 5032 bool bypass_dig; 5033 }; 5034 5035 enum rtw89_multi_cfo_mode { 5036 RTW89_PKT_BASED_AVG_MODE = 0, 5037 RTW89_ENTRY_BASED_AVG_MODE = 1, 5038 RTW89_TP_BASED_AVG_MODE = 2, 5039 }; 5040 5041 enum rtw89_phy_cfo_status { 5042 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5043 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5044 RTW89_PHY_DCFO_STATE_HOLD = 2, 5045 RTW89_PHY_DCFO_STATE_MAX 5046 }; 5047 5048 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5049 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5050 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5051 }; 5052 5053 struct rtw89_cfo_tracking_info { 5054 u16 cfo_timer_ms; 5055 bool cfo_trig_by_timer_en; 5056 enum rtw89_phy_cfo_status phy_cfo_status; 5057 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5058 u8 phy_cfo_trk_cnt; 5059 bool is_adjust; 5060 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5061 bool apply_compensation; 5062 u8 crystal_cap; 5063 u8 crystal_cap_default; 5064 u8 def_x_cap; 5065 s8 x_cap_ofst; 5066 u32 sta_cfo_tolerance; 5067 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5068 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5069 s32 cfo_avg_pre; 5070 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5071 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5072 s32 dcfo_avg; 5073 s32 dcfo_avg_pre; 5074 u32 packet_count; 5075 u32 packet_count_pre; 5076 s32 residual_cfo_acc; 5077 u8 phy_cfotrk_state; 5078 u8 phy_cfotrk_cnt; 5079 bool divergence_lock_en; 5080 u8 x_cap_lb; 5081 u8 x_cap_ub; 5082 u8 lock_cnt; 5083 }; 5084 5085 enum rtw89_tssi_mode { 5086 RTW89_TSSI_NORMAL = 0, 5087 RTW89_TSSI_SCAN = 1, 5088 }; 5089 5090 enum rtw89_tssi_alimk_band { 5091 TSSI_ALIMK_2G = 0, 5092 TSSI_ALIMK_5GL, 5093 TSSI_ALIMK_5GM, 5094 TSSI_ALIMK_5GH, 5095 TSSI_ALIMK_MAX 5096 }; 5097 5098 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5099 #define TSSI_TRIM_CH_GROUP_NUM 8 5100 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5101 5102 #define TSSI_CCK_CH_GROUP_NUM 6 5103 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5104 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5105 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5106 #define TSSI_MCS_CH_GROUP_NUM \ 5107 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5108 #define TSSI_MAX_CH_NUM 67 5109 #define TSSI_ALIMK_VALUE_NUM 8 5110 5111 struct rtw89_tssi_info { 5112 u8 thermal[RF_PATH_MAX]; 5113 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5114 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5115 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5116 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5117 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5118 s8 extra_ofst[RF_PATH_MAX]; 5119 bool tssi_tracking_check[RF_PATH_MAX]; 5120 u8 default_txagc_offset[RF_PATH_MAX]; 5121 u32 base_thermal[RF_PATH_MAX]; 5122 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5123 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5124 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5125 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5126 u32 tssi_alimk_time; 5127 }; 5128 5129 struct rtw89_power_trim_info { 5130 bool pg_thermal_trim; 5131 bool pg_pa_bias_trim; 5132 u8 thermal_trim[RF_PATH_MAX]; 5133 u8 pa_bias_trim[RF_PATH_MAX]; 5134 u8 pad_bias_trim[RF_PATH_MAX]; 5135 }; 5136 5137 struct rtw89_regd { 5138 char alpha2[3]; 5139 u8 txpwr_regd[RTW89_BAND_NUM]; 5140 }; 5141 5142 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5143 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5144 #define RTW89_5GHZ_UNII4_START_INDEX 25 5145 5146 struct rtw89_regulatory_info { 5147 const struct rtw89_regd *regd; 5148 enum rtw89_reg_6ghz_power reg_6ghz_power; 5149 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5150 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5151 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5152 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5153 }; 5154 5155 enum rtw89_ifs_clm_application { 5156 RTW89_IFS_CLM_INIT = 0, 5157 RTW89_IFS_CLM_BACKGROUND = 1, 5158 RTW89_IFS_CLM_ACS = 2, 5159 RTW89_IFS_CLM_DIG = 3, 5160 RTW89_IFS_CLM_TDMA_DIG = 4, 5161 RTW89_IFS_CLM_DBG = 5, 5162 RTW89_IFS_CLM_DBG_MANUAL = 6 5163 }; 5164 5165 enum rtw89_env_racing_lv { 5166 RTW89_RAC_RELEASE = 0, 5167 RTW89_RAC_LV_1 = 1, 5168 RTW89_RAC_LV_2 = 2, 5169 RTW89_RAC_LV_3 = 3, 5170 RTW89_RAC_LV_4 = 4, 5171 RTW89_RAC_MAX_NUM = 5 5172 }; 5173 5174 struct rtw89_ccx_para_info { 5175 enum rtw89_env_racing_lv rac_lv; 5176 u16 mntr_time; 5177 u8 nhm_manual_th_ofst; 5178 u8 nhm_manual_th0; 5179 enum rtw89_ifs_clm_application ifs_clm_app; 5180 u32 ifs_clm_manual_th_times; 5181 u32 ifs_clm_manual_th0; 5182 u8 fahm_manual_th_ofst; 5183 u8 fahm_manual_th0; 5184 u8 fahm_numer_opt; 5185 u8 fahm_denom_opt; 5186 }; 5187 5188 enum rtw89_ccx_edcca_opt_sc_idx { 5189 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5190 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5191 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5192 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5193 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5194 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5195 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5196 RTW89_CCX_EDCCA_SEG1_S3 = 7 5197 }; 5198 5199 enum rtw89_ccx_edcca_opt_bw_idx { 5200 RTW89_CCX_EDCCA_BW20_0 = 0, 5201 RTW89_CCX_EDCCA_BW20_1 = 1, 5202 RTW89_CCX_EDCCA_BW20_2 = 2, 5203 RTW89_CCX_EDCCA_BW20_3 = 3, 5204 RTW89_CCX_EDCCA_BW20_4 = 4, 5205 RTW89_CCX_EDCCA_BW20_5 = 5, 5206 RTW89_CCX_EDCCA_BW20_6 = 6, 5207 RTW89_CCX_EDCCA_BW20_7 = 7 5208 }; 5209 5210 #define RTW89_NHM_TH_NUM 11 5211 #define RTW89_FAHM_TH_NUM 11 5212 #define RTW89_NHM_RPT_NUM 12 5213 #define RTW89_FAHM_RPT_NUM 12 5214 #define RTW89_IFS_CLM_NUM 4 5215 struct rtw89_env_monitor_info { 5216 u8 ccx_watchdog_result; 5217 bool ccx_ongoing; 5218 u8 ccx_rac_lv; 5219 bool ccx_manual_ctrl; 5220 u16 ifs_clm_mntr_time; 5221 enum rtw89_ifs_clm_application ifs_clm_app; 5222 u16 ccx_period; 5223 u8 ccx_unit_idx; 5224 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5225 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5226 u16 ifs_clm_tx; 5227 u16 ifs_clm_edcca_excl_cca; 5228 u16 ifs_clm_ofdmfa; 5229 u16 ifs_clm_ofdmcca_excl_fa; 5230 u16 ifs_clm_cckfa; 5231 u16 ifs_clm_cckcca_excl_fa; 5232 u16 ifs_clm_total_ifs; 5233 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5234 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5235 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5236 u8 ifs_clm_tx_ratio; 5237 u8 ifs_clm_edcca_excl_cca_ratio; 5238 u8 ifs_clm_cck_fa_ratio; 5239 u8 ifs_clm_ofdm_fa_ratio; 5240 u8 ifs_clm_cck_cca_excl_fa_ratio; 5241 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5242 u16 ifs_clm_cck_fa_permil; 5243 u16 ifs_clm_ofdm_fa_permil; 5244 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5245 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5246 }; 5247 5248 enum rtw89_ser_rcvy_step { 5249 RTW89_SER_DRV_STOP_TX, 5250 RTW89_SER_DRV_STOP_RX, 5251 RTW89_SER_DRV_STOP_RUN, 5252 RTW89_SER_HAL_STOP_DMA, 5253 RTW89_SER_SUPPRESS_LOG, 5254 RTW89_NUM_OF_SER_FLAGS 5255 }; 5256 5257 struct rtw89_ser { 5258 u8 state; 5259 u8 alarm_event; 5260 bool prehandle_l1; 5261 5262 struct work_struct ser_hdl_work; 5263 struct delayed_work ser_alarm_work; 5264 const struct state_ent *st_tbl; 5265 const struct event_ent *ev_tbl; 5266 struct list_head msg_q; 5267 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5268 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5269 }; 5270 5271 enum rtw89_mac_ax_ps_mode { 5272 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5273 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5274 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5275 RTW89_MAC_AX_PS_MODE_MAX = 3, 5276 }; 5277 5278 enum rtw89_last_rpwm_mode { 5279 RTW89_LAST_RPWM_PS = 0x0, 5280 RTW89_LAST_RPWM_ACTIVE = 0x6, 5281 }; 5282 5283 struct rtw89_lps_parm { 5284 u8 macid; 5285 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5286 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5287 }; 5288 5289 struct rtw89_ppdu_sts_info { 5290 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 5291 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 5292 }; 5293 5294 struct rtw89_early_h2c { 5295 struct list_head list; 5296 u8 *h2c; 5297 u16 h2c_len; 5298 }; 5299 5300 struct rtw89_hw_scan_info { 5301 struct rtw89_vif_link *scanning_vif; 5302 struct list_head pkt_list[NUM_NL80211_BANDS]; 5303 struct rtw89_chan op_chan; 5304 bool abort; 5305 u32 last_chan_idx; 5306 }; 5307 5308 enum rtw89_phy_bb_gain_band { 5309 RTW89_BB_GAIN_BAND_2G = 0, 5310 RTW89_BB_GAIN_BAND_5G_L = 1, 5311 RTW89_BB_GAIN_BAND_5G_M = 2, 5312 RTW89_BB_GAIN_BAND_5G_H = 3, 5313 RTW89_BB_GAIN_BAND_6G_L = 4, 5314 RTW89_BB_GAIN_BAND_6G_M = 5, 5315 RTW89_BB_GAIN_BAND_6G_H = 6, 5316 RTW89_BB_GAIN_BAND_6G_UH = 7, 5317 5318 RTW89_BB_GAIN_BAND_NR, 5319 }; 5320 5321 enum rtw89_phy_gain_band_be { 5322 RTW89_BB_GAIN_BAND_2G_BE = 0, 5323 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5324 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5325 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5326 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5327 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5328 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5329 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5330 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5331 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5332 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5333 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5334 5335 RTW89_BB_GAIN_BAND_NR_BE, 5336 }; 5337 5338 enum rtw89_phy_bb_bw_be { 5339 RTW89_BB_BW_20_40 = 0, 5340 RTW89_BB_BW_80_160_320 = 1, 5341 5342 RTW89_BB_BW_NR_BE, 5343 }; 5344 5345 enum rtw89_bw20_sc { 5346 RTW89_BW20_SC_20M = 1, 5347 RTW89_BW20_SC_40M = 2, 5348 RTW89_BW20_SC_80M = 4, 5349 RTW89_BW20_SC_160M = 8, 5350 RTW89_BW20_SC_320M = 16, 5351 }; 5352 5353 enum rtw89_cmac_table_bw { 5354 RTW89_CMAC_BW_20M = 0, 5355 RTW89_CMAC_BW_40M = 1, 5356 RTW89_CMAC_BW_80M = 2, 5357 RTW89_CMAC_BW_160M = 3, 5358 RTW89_CMAC_BW_320M = 4, 5359 5360 RTW89_CMAC_BW_NR, 5361 }; 5362 5363 enum rtw89_phy_bb_rxsc_num { 5364 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5365 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5366 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5367 }; 5368 5369 struct rtw89_phy_bb_gain_info { 5370 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5371 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5372 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5373 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5374 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5375 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5376 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5377 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5378 [RTW89_BB_RXSC_NUM_40]; 5379 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5380 [RTW89_BB_RXSC_NUM_80]; 5381 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5382 [RTW89_BB_RXSC_NUM_160]; 5383 }; 5384 5385 struct rtw89_phy_bb_gain_info_be { 5386 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5387 [LNA_GAIN_NUM]; 5388 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5389 [TIA_GAIN_NUM]; 5390 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5391 [RF_PATH_MAX][LNA_GAIN_NUM]; 5392 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5393 [RF_PATH_MAX][LNA_GAIN_NUM]; 5394 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5395 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5396 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5397 [RTW89_BW20_SC_20M]; 5398 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5399 [RTW89_BW20_SC_40M]; 5400 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5401 [RTW89_BW20_SC_80M]; 5402 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5403 [RTW89_BW20_SC_160M]; 5404 }; 5405 5406 struct rtw89_phy_efuse_gain { 5407 bool offset_valid; 5408 bool comp_valid; 5409 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5410 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5411 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5412 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5413 }; 5414 5415 #define RTW89_MAX_PATTERN_NUM 18 5416 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5417 #define RTW89_MAX_PATTERN_SIZE 128 5418 5419 struct rtw89_wow_cam_info { 5420 bool r_w; 5421 u8 idx; 5422 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5423 u16 crc; 5424 bool negative_pattern_match; 5425 bool skip_mac_hdr; 5426 bool uc; 5427 bool mc; 5428 bool bc; 5429 bool valid; 5430 }; 5431 5432 struct rtw89_wow_key_info { 5433 u8 ptk_tx_iv[8]; 5434 u8 valid_check; 5435 u8 symbol_check_en; 5436 u8 gtk_keyidx; 5437 u8 rsvd[5]; 5438 u8 ptk_rx_iv[8]; 5439 u8 gtk_rx_iv[4][8]; 5440 } __packed; 5441 5442 struct rtw89_wow_gtk_info { 5443 u8 kck[32]; 5444 u8 kek[32]; 5445 u8 tk1[16]; 5446 u8 txmickey[8]; 5447 u8 rxmickey[8]; 5448 __le32 igtk_keyid; 5449 __le64 ipn; 5450 u8 igtk[2][32]; 5451 u8 psk[32]; 5452 } __packed; 5453 5454 struct rtw89_wow_aoac_report { 5455 u8 rpt_ver; 5456 u8 sec_type; 5457 u8 key_idx; 5458 u8 pattern_idx; 5459 u8 rekey_ok; 5460 u8 ptk_tx_iv[8]; 5461 u8 eapol_key_replay_count[8]; 5462 u8 gtk[32]; 5463 u8 ptk_rx_iv[8]; 5464 u8 gtk_rx_iv[4][8]; 5465 u64 igtk_key_id; 5466 u64 igtk_ipn; 5467 u8 igtk[32]; 5468 u8 csa_pri_ch; 5469 u8 csa_bw; 5470 u8 csa_ch_offset; 5471 u8 csa_chsw_failed; 5472 u8 csa_ch_band; 5473 }; 5474 5475 struct rtw89_wow_param { 5476 struct rtw89_vif_link *rtwvif_link; 5477 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5478 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5479 struct rtw89_wow_key_info key_info; 5480 struct rtw89_wow_gtk_info gtk_info; 5481 struct rtw89_wow_aoac_report aoac_rpt; 5482 u8 pattern_cnt; 5483 u8 ptk_alg; 5484 u8 gtk_alg; 5485 u8 ptk_keyidx; 5486 u8 akm; 5487 5488 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5489 struct rtw89_wait_info wait; 5490 5491 bool pno_inited; 5492 struct list_head pno_pkt_list; 5493 struct cfg80211_sched_scan_request *nd_config; 5494 }; 5495 5496 struct rtw89_mcc_limit { 5497 bool enable; 5498 u16 max_tob; /* TU; max time offset behind */ 5499 u16 max_toa; /* TU; max time offset ahead */ 5500 u16 max_dur; /* TU */ 5501 }; 5502 5503 struct rtw89_mcc_policy { 5504 u8 c2h_rpt; 5505 u8 tx_null_early; 5506 u8 dis_tx_null; 5507 u8 in_curr_ch; 5508 u8 dis_sw_retry; 5509 u8 sw_retry_count; 5510 }; 5511 5512 struct rtw89_mcc_role { 5513 struct rtw89_vif_link *rtwvif_link; 5514 struct rtw89_mcc_policy policy; 5515 struct rtw89_mcc_limit limit; 5516 5517 /* only valid when running with FW MRC mechanism */ 5518 u8 slot_idx; 5519 5520 /* byte-array in LE order for FW */ 5521 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5522 5523 u16 duration; /* TU */ 5524 u16 beacon_interval; /* TU */ 5525 bool is_2ghz; 5526 bool is_go; 5527 bool is_gc; 5528 }; 5529 5530 struct rtw89_mcc_bt_role { 5531 u16 duration; /* TU */ 5532 }; 5533 5534 struct rtw89_mcc_courtesy { 5535 bool enable; 5536 u8 slot_num; 5537 u8 macid_src; 5538 u8 macid_tgt; 5539 }; 5540 5541 enum rtw89_mcc_plan { 5542 RTW89_MCC_PLAN_TAIL_BT, 5543 RTW89_MCC_PLAN_MID_BT, 5544 RTW89_MCC_PLAN_NO_BT, 5545 5546 NUM_OF_RTW89_MCC_PLAN, 5547 }; 5548 5549 struct rtw89_mcc_pattern { 5550 s16 tob_ref; /* TU; time offset behind of reference role */ 5551 s16 toa_ref; /* TU; time offset ahead of reference role */ 5552 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5553 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5554 5555 enum rtw89_mcc_plan plan; 5556 struct rtw89_mcc_courtesy courtesy; 5557 }; 5558 5559 struct rtw89_mcc_sync { 5560 bool enable; 5561 u16 offset; /* TU */ 5562 u8 macid_src; 5563 u8 band_src; 5564 u8 port_src; 5565 u8 macid_tgt; 5566 u8 band_tgt; 5567 u8 port_tgt; 5568 }; 5569 5570 struct rtw89_mcc_config { 5571 struct rtw89_mcc_pattern pattern; 5572 struct rtw89_mcc_sync sync; 5573 u64 start_tsf; 5574 u16 mcc_interval; /* TU */ 5575 u16 beacon_offset; /* TU */ 5576 }; 5577 5578 enum rtw89_mcc_mode { 5579 RTW89_MCC_MODE_GO_STA, 5580 RTW89_MCC_MODE_GC_STA, 5581 }; 5582 5583 struct rtw89_mcc_info { 5584 struct rtw89_wait_info wait; 5585 5586 u8 group; 5587 enum rtw89_mcc_mode mode; 5588 struct rtw89_mcc_role role_ref; /* reference role */ 5589 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5590 struct rtw89_mcc_bt_role bt_role; 5591 struct rtw89_mcc_config config; 5592 }; 5593 5594 struct rtw89_dev { 5595 struct ieee80211_hw *hw; 5596 struct device *dev; 5597 const struct ieee80211_ops *ops; 5598 5599 bool dbcc_en; 5600 bool support_mlo; 5601 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5602 struct rtw89_hw_scan_info scan_info; 5603 const struct rtw89_chip_info *chip; 5604 const struct rtw89_pci_info *pci_info; 5605 const struct rtw89_rfe_parms *rfe_parms; 5606 struct rtw89_hal hal; 5607 struct rtw89_mcc_info mcc; 5608 struct rtw89_mac_info mac; 5609 struct rtw89_fw_info fw; 5610 struct rtw89_hci_info hci; 5611 struct rtw89_efuse efuse; 5612 struct rtw89_traffic_stats stats; 5613 struct rtw89_rfe_data *rfe_data; 5614 enum rtw89_custid custid; 5615 5616 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 5617 refcount_t refcount_ap_info; 5618 5619 /* ensures exclusive access from mac80211 callbacks */ 5620 struct mutex mutex; 5621 struct list_head rtwvifs_list; 5622 /* used to protect rf read write */ 5623 struct mutex rf_mutex; 5624 struct workqueue_struct *txq_wq; 5625 struct work_struct txq_work; 5626 struct delayed_work txq_reinvoke_work; 5627 /* used to protect ba_list and forbid_ba_list */ 5628 spinlock_t ba_lock; 5629 /* txqs to setup ba session */ 5630 struct list_head ba_list; 5631 /* txqs to forbid ba session */ 5632 struct list_head forbid_ba_list; 5633 struct work_struct ba_work; 5634 /* used to protect rpwm */ 5635 spinlock_t rpwm_lock; 5636 5637 struct rtw89_cam_info cam_info; 5638 5639 struct sk_buff_head c2h_queue; 5640 struct work_struct c2h_work; 5641 struct work_struct ips_work; 5642 struct work_struct load_firmware_work; 5643 struct work_struct cancel_6ghz_probe_work; 5644 5645 struct list_head early_h2c_list; 5646 5647 struct rtw89_ser ser; 5648 5649 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5650 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5651 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5652 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5653 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5654 5655 struct rtw89_phy_stat phystat; 5656 struct rtw89_rfk_wait_info rfk_wait; 5657 struct rtw89_dack_info dack; 5658 struct rtw89_iqk_info iqk; 5659 struct rtw89_dpk_info dpk; 5660 struct rtw89_rfk_mcc_info rfk_mcc; 5661 struct rtw89_lck_info lck; 5662 struct rtw89_rx_dck_info rx_dck; 5663 bool is_tssi_mode[RF_PATH_MAX]; 5664 bool is_bt_iqk_timeout; 5665 5666 struct rtw89_fem_info fem; 5667 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5668 struct rtw89_tssi_info tssi; 5669 struct rtw89_power_trim_info pwr_trim; 5670 5671 struct rtw89_cfo_tracking_info cfo_tracking; 5672 struct rtw89_env_monitor_info env_monitor; 5673 struct rtw89_dig_info dig; 5674 struct rtw89_phy_ch_info ch_info; 5675 union { 5676 struct rtw89_phy_bb_gain_info ax; 5677 struct rtw89_phy_bb_gain_info_be be; 5678 } bb_gain; 5679 struct rtw89_phy_efuse_gain efuse_gain; 5680 struct rtw89_phy_ul_tb_info ul_tb_info; 5681 struct rtw89_antdiv_info antdiv; 5682 5683 struct delayed_work track_work; 5684 struct delayed_work chanctx_work; 5685 struct delayed_work coex_act1_work; 5686 struct delayed_work coex_bt_devinfo_work; 5687 struct delayed_work coex_rfk_chk_work; 5688 struct delayed_work cfo_track_work; 5689 struct delayed_work forbid_ba_work; 5690 struct delayed_work roc_work; 5691 struct delayed_work antdiv_work; 5692 struct rtw89_ppdu_sts_info ppdu_sts; 5693 u8 total_sta_assoc; 5694 bool scanning; 5695 5696 struct rtw89_regulatory_info regulatory; 5697 struct rtw89_sar_info sar; 5698 struct rtw89_tas_info tas; 5699 struct rtw89_ant_gain_info ant_gain; 5700 5701 struct rtw89_btc btc; 5702 enum rtw89_ps_mode ps_mode; 5703 bool lps_enabled; 5704 5705 struct rtw89_wow_param wow; 5706 5707 /* napi structure */ 5708 struct net_device *netdev; 5709 struct napi_struct napi; 5710 int napi_budget_countdown; 5711 5712 struct rtw89_debugfs *debugfs; 5713 5714 /* HCI related data, keep last */ 5715 u8 priv[] __aligned(sizeof(void *)); 5716 }; 5717 5718 struct rtw89_link_conf_container { 5719 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 5720 }; 5721 5722 #define RTW89_VIF_IDLE_LINK_ID 0 5723 5724 struct rtw89_vif { 5725 struct rtw89_dev *rtwdev; 5726 struct list_head list; 5727 struct list_head mgnt_entry; 5728 struct rtw89_link_conf_container __rcu *snap_link_confs; 5729 5730 u8 mac_addr[ETH_ALEN]; 5731 __be32 ip_addr; 5732 5733 struct rtw89_traffic_stats stats; 5734 u32 tdls_peer; 5735 5736 struct ieee80211_scan_ies *scan_ies; 5737 struct cfg80211_scan_request *scan_req; 5738 5739 struct rtw89_roc roc; 5740 bool offchan; 5741 5742 u8 links_inst_valid_num; 5743 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5744 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5745 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 5746 }; 5747 5748 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 5749 const struct rtw89_vif *rtwvif, 5750 unsigned int link_id) 5751 { 5752 *rtwvif_link = rtwvif->links[link_id]; 5753 return !!*rtwvif_link; 5754 } 5755 5756 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 5757 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5758 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 5759 5760 enum rtw89_sta_flags { 5761 RTW89_REMOTE_STA_IN_PS, 5762 5763 NUM_OF_RTW89_STA_FLAGS, 5764 }; 5765 5766 struct rtw89_sta { 5767 struct rtw89_dev *rtwdev; 5768 struct rtw89_vif *rtwvif; 5769 5770 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 5771 5772 bool disassoc; 5773 5774 struct sk_buff_head roc_queue; 5775 5776 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 5777 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 5778 5779 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 5780 5781 u8 links_inst_valid_num; 5782 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5783 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5784 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 5785 }; 5786 5787 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 5788 const struct rtw89_sta *rtwsta, 5789 unsigned int link_id) 5790 { 5791 *rtwsta_link = rtwsta->links[link_id]; 5792 return !!*rtwsta_link; 5793 } 5794 5795 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 5796 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5797 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 5798 5799 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 5800 { 5801 /* const after init, so no need to check if active first */ 5802 return rtwvif->links_inst[0].mac_id; 5803 } 5804 5805 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 5806 { 5807 /* const after init, so no need to check if active first */ 5808 return rtwvif->links_inst[0].port; 5809 } 5810 5811 static inline struct rtw89_vif_link * 5812 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 5813 { 5814 if (index >= rtwvif->links_inst_valid_num || 5815 !test_bit(index, rtwvif->links_inst_map)) 5816 return NULL; 5817 return &rtwvif->links_inst[index]; 5818 } 5819 5820 static inline 5821 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 5822 { 5823 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5824 5825 return rtwvif_link - rtwvif->links_inst; 5826 } 5827 5828 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 5829 { 5830 /* const after init, so no need to check if active first */ 5831 return rtwsta->links_inst[0].mac_id; 5832 } 5833 5834 static inline struct rtw89_sta_link * 5835 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 5836 { 5837 if (index >= rtwsta->links_inst_valid_num || 5838 !test_bit(index, rtwsta->links_inst_map)) 5839 return NULL; 5840 return &rtwsta->links_inst[index]; 5841 } 5842 5843 static inline 5844 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 5845 { 5846 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5847 5848 return rtwsta_link - rtwsta->links_inst; 5849 } 5850 5851 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 5852 { 5853 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5854 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5855 5856 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5857 rtwsta_link); 5858 } 5859 5860 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 5861 { 5862 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5863 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5864 5865 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5866 NULL); 5867 synchronize_rcu(); 5868 } 5869 5870 static inline struct rtw89_sta_link * 5871 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 5872 { 5873 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 5874 } 5875 5876 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5877 struct rtw89_core_tx_request *tx_req) 5878 { 5879 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5880 } 5881 5882 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5883 { 5884 rtwdev->hci.ops->reset(rtwdev); 5885 } 5886 5887 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5888 { 5889 return rtwdev->hci.ops->start(rtwdev); 5890 } 5891 5892 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5893 { 5894 rtwdev->hci.ops->stop(rtwdev); 5895 } 5896 5897 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5898 { 5899 return rtwdev->hci.ops->deinit(rtwdev); 5900 } 5901 5902 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5903 { 5904 rtwdev->hci.ops->pause(rtwdev, pause); 5905 } 5906 5907 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5908 { 5909 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5910 } 5911 5912 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5913 { 5914 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5915 } 5916 5917 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5918 { 5919 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5920 } 5921 5922 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5923 { 5924 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5925 } 5926 5927 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5928 { 5929 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5930 } 5931 5932 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5933 bool drop) 5934 { 5935 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5936 return; 5937 5938 if (rtwdev->hci.ops->flush_queues) 5939 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5940 } 5941 5942 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5943 { 5944 if (rtwdev->hci.ops->recovery_start) 5945 rtwdev->hci.ops->recovery_start(rtwdev); 5946 } 5947 5948 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5949 { 5950 if (rtwdev->hci.ops->recovery_complete) 5951 rtwdev->hci.ops->recovery_complete(rtwdev); 5952 } 5953 5954 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5955 { 5956 if (rtwdev->hci.ops->enable_intr) 5957 rtwdev->hci.ops->enable_intr(rtwdev); 5958 } 5959 5960 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5961 { 5962 if (rtwdev->hci.ops->disable_intr) 5963 rtwdev->hci.ops->disable_intr(rtwdev); 5964 } 5965 5966 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5967 { 5968 if (rtwdev->hci.ops->ctrl_txdma_ch) 5969 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5970 } 5971 5972 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5973 { 5974 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5975 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5976 } 5977 5978 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5979 { 5980 if (rtwdev->hci.ops->ctrl_trxhci) 5981 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5982 } 5983 5984 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5985 { 5986 int ret = 0; 5987 5988 if (rtwdev->hci.ops->poll_txdma_ch_idle) 5989 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 5990 return ret; 5991 } 5992 5993 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 5994 { 5995 if (rtwdev->hci.ops->clr_idx_all) 5996 rtwdev->hci.ops->clr_idx_all(rtwdev); 5997 } 5998 5999 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6000 { 6001 int ret = 0; 6002 6003 if (rtwdev->hci.ops->rst_bdram) 6004 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6005 return ret; 6006 } 6007 6008 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6009 { 6010 if (rtwdev->hci.ops->clear) 6011 rtwdev->hci.ops->clear(rtwdev, pdev); 6012 } 6013 6014 static inline 6015 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6016 { 6017 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6018 6019 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 6020 } 6021 6022 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6023 { 6024 return rtwdev->hci.ops->read8(rtwdev, addr); 6025 } 6026 6027 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6028 { 6029 return rtwdev->hci.ops->read16(rtwdev, addr); 6030 } 6031 6032 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6033 { 6034 return rtwdev->hci.ops->read32(rtwdev, addr); 6035 } 6036 6037 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6038 { 6039 rtwdev->hci.ops->write8(rtwdev, addr, data); 6040 } 6041 6042 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6043 { 6044 rtwdev->hci.ops->write16(rtwdev, addr, data); 6045 } 6046 6047 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6048 { 6049 rtwdev->hci.ops->write32(rtwdev, addr, data); 6050 } 6051 6052 static inline void 6053 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6054 { 6055 u8 val; 6056 6057 val = rtw89_read8(rtwdev, addr); 6058 rtw89_write8(rtwdev, addr, val | bit); 6059 } 6060 6061 static inline void 6062 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6063 { 6064 u16 val; 6065 6066 val = rtw89_read16(rtwdev, addr); 6067 rtw89_write16(rtwdev, addr, val | bit); 6068 } 6069 6070 static inline void 6071 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6072 { 6073 u32 val; 6074 6075 val = rtw89_read32(rtwdev, addr); 6076 rtw89_write32(rtwdev, addr, val | bit); 6077 } 6078 6079 static inline void 6080 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6081 { 6082 u8 val; 6083 6084 val = rtw89_read8(rtwdev, addr); 6085 rtw89_write8(rtwdev, addr, val & ~bit); 6086 } 6087 6088 static inline void 6089 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6090 { 6091 u16 val; 6092 6093 val = rtw89_read16(rtwdev, addr); 6094 rtw89_write16(rtwdev, addr, val & ~bit); 6095 } 6096 6097 static inline void 6098 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6099 { 6100 u32 val; 6101 6102 val = rtw89_read32(rtwdev, addr); 6103 rtw89_write32(rtwdev, addr, val & ~bit); 6104 } 6105 6106 static inline u32 6107 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6108 { 6109 u32 shift = __ffs(mask); 6110 u32 orig; 6111 u32 ret; 6112 6113 orig = rtw89_read32(rtwdev, addr); 6114 ret = (orig & mask) >> shift; 6115 6116 return ret; 6117 } 6118 6119 static inline u16 6120 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6121 { 6122 u32 shift = __ffs(mask); 6123 u32 orig; 6124 u32 ret; 6125 6126 orig = rtw89_read16(rtwdev, addr); 6127 ret = (orig & mask) >> shift; 6128 6129 return ret; 6130 } 6131 6132 static inline u8 6133 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6134 { 6135 u32 shift = __ffs(mask); 6136 u32 orig; 6137 u32 ret; 6138 6139 orig = rtw89_read8(rtwdev, addr); 6140 ret = (orig & mask) >> shift; 6141 6142 return ret; 6143 } 6144 6145 static inline void 6146 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6147 { 6148 u32 shift = __ffs(mask); 6149 u32 orig; 6150 u32 set; 6151 6152 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6153 6154 orig = rtw89_read32(rtwdev, addr); 6155 set = (orig & ~mask) | ((data << shift) & mask); 6156 rtw89_write32(rtwdev, addr, set); 6157 } 6158 6159 static inline void 6160 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6161 { 6162 u32 shift; 6163 u16 orig, set; 6164 6165 mask &= 0xffff; 6166 shift = __ffs(mask); 6167 6168 orig = rtw89_read16(rtwdev, addr); 6169 set = (orig & ~mask) | ((data << shift) & mask); 6170 rtw89_write16(rtwdev, addr, set); 6171 } 6172 6173 static inline void 6174 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6175 { 6176 u32 shift; 6177 u8 orig, set; 6178 6179 mask &= 0xff; 6180 shift = __ffs(mask); 6181 6182 orig = rtw89_read8(rtwdev, addr); 6183 set = (orig & ~mask) | ((data << shift) & mask); 6184 rtw89_write8(rtwdev, addr, set); 6185 } 6186 6187 static inline u32 6188 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6189 u32 addr, u32 mask) 6190 { 6191 u32 val; 6192 6193 mutex_lock(&rtwdev->rf_mutex); 6194 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6195 mutex_unlock(&rtwdev->rf_mutex); 6196 6197 return val; 6198 } 6199 6200 static inline void 6201 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6202 u32 addr, u32 mask, u32 data) 6203 { 6204 mutex_lock(&rtwdev->rf_mutex); 6205 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6206 mutex_unlock(&rtwdev->rf_mutex); 6207 } 6208 6209 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6210 { 6211 void *p = rtwtxq; 6212 6213 return container_of(p, struct ieee80211_txq, drv_priv); 6214 } 6215 6216 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6217 struct ieee80211_txq *txq) 6218 { 6219 struct rtw89_txq *rtwtxq; 6220 6221 if (!txq) 6222 return; 6223 6224 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6225 INIT_LIST_HEAD(&rtwtxq->list); 6226 } 6227 6228 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6229 { 6230 void *p = rtwvif; 6231 6232 return container_of(p, struct ieee80211_vif, drv_priv); 6233 } 6234 6235 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6236 { 6237 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6238 } 6239 6240 static inline 6241 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6242 { 6243 return rtwvif_to_vif(rtwvif_link->rtwvif); 6244 } 6245 6246 static inline 6247 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6248 { 6249 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6250 } 6251 6252 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6253 { 6254 return (struct rtw89_vif *)vif->drv_priv; 6255 } 6256 6257 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6258 { 6259 return vif ? vif_to_rtwvif(vif) : NULL; 6260 } 6261 6262 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6263 { 6264 void *p = rtwsta; 6265 6266 return container_of(p, struct ieee80211_sta, drv_priv); 6267 } 6268 6269 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6270 { 6271 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6272 } 6273 6274 static inline 6275 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6276 { 6277 return rtwsta_to_sta(rtwsta_link->rtwsta); 6278 } 6279 6280 static inline 6281 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6282 { 6283 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6284 } 6285 6286 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6287 { 6288 return (struct rtw89_sta *)sta->drv_priv; 6289 } 6290 6291 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6292 { 6293 return sta ? sta_to_rtwsta(sta) : NULL; 6294 } 6295 6296 static inline struct ieee80211_bss_conf * 6297 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6298 { 6299 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6300 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6301 struct rtw89_link_conf_container *snap; 6302 struct ieee80211_bss_conf *bss_conf; 6303 6304 snap = rcu_dereference(rtwvif->snap_link_confs); 6305 if (snap) { 6306 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6307 goto out; 6308 } 6309 6310 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6311 6312 out: 6313 if (unlikely(!bss_conf)) { 6314 *nolink = true; 6315 return &vif->bss_conf; 6316 } 6317 6318 *nolink = false; 6319 return bss_conf; 6320 } 6321 6322 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6323 ({ \ 6324 typeof(rtwvif_link) p = rtwvif_link; \ 6325 struct ieee80211_bss_conf *bss_conf; \ 6326 bool nolink; \ 6327 \ 6328 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6329 if (unlikely(nolink) && (assert)) \ 6330 rtw89_err(p->rtwvif->rtwdev, \ 6331 "%s: cannot find exact bss_conf for link_id %u\n",\ 6332 __func__, p->link_id); \ 6333 bss_conf; \ 6334 }) 6335 6336 static inline struct ieee80211_link_sta * 6337 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6338 { 6339 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6340 struct ieee80211_link_sta *link_sta; 6341 6342 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6343 if (unlikely(!link_sta)) { 6344 *nolink = true; 6345 return &sta->deflink; 6346 } 6347 6348 *nolink = false; 6349 return link_sta; 6350 } 6351 6352 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6353 ({ \ 6354 typeof(rtwsta_link) p = rtwsta_link; \ 6355 struct ieee80211_link_sta *link_sta; \ 6356 bool nolink; \ 6357 \ 6358 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6359 if (unlikely(nolink) && (assert)) \ 6360 rtw89_err(p->rtwsta->rtwdev, \ 6361 "%s: cannot find exact link_sta for link_id %u\n",\ 6362 __func__, p->link_id); \ 6363 link_sta; \ 6364 }) 6365 6366 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6367 { 6368 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6369 return RATE_INFO_BW_160; 6370 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6371 return RATE_INFO_BW_80; 6372 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6373 return RATE_INFO_BW_40; 6374 else 6375 return RATE_INFO_BW_20; 6376 } 6377 6378 static inline 6379 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6380 { 6381 switch (hw_band) { 6382 default: 6383 case RTW89_BAND_2G: 6384 return NL80211_BAND_2GHZ; 6385 case RTW89_BAND_5G: 6386 return NL80211_BAND_5GHZ; 6387 case RTW89_BAND_6G: 6388 return NL80211_BAND_6GHZ; 6389 } 6390 } 6391 6392 static inline 6393 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6394 { 6395 switch (nl_band) { 6396 default: 6397 case NL80211_BAND_2GHZ: 6398 return RTW89_BAND_2G; 6399 case NL80211_BAND_5GHZ: 6400 return RTW89_BAND_5G; 6401 case NL80211_BAND_6GHZ: 6402 return RTW89_BAND_6G; 6403 } 6404 } 6405 6406 static inline 6407 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6408 { 6409 switch (width) { 6410 default: 6411 WARN(1, "Not support bandwidth %d\n", width); 6412 fallthrough; 6413 case NL80211_CHAN_WIDTH_20_NOHT: 6414 case NL80211_CHAN_WIDTH_20: 6415 return RTW89_CHANNEL_WIDTH_20; 6416 case NL80211_CHAN_WIDTH_40: 6417 return RTW89_CHANNEL_WIDTH_40; 6418 case NL80211_CHAN_WIDTH_80: 6419 return RTW89_CHANNEL_WIDTH_80; 6420 case NL80211_CHAN_WIDTH_160: 6421 return RTW89_CHANNEL_WIDTH_160; 6422 } 6423 } 6424 6425 static inline 6426 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6427 { 6428 switch (rua) { 6429 default: 6430 WARN(1, "Invalid RU allocation: %d\n", rua); 6431 fallthrough; 6432 case 0 ... 36: 6433 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6434 case 37 ... 52: 6435 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6436 case 53 ... 60: 6437 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6438 case 61 ... 64: 6439 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6440 case 65 ... 66: 6441 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6442 case 67: 6443 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6444 case 68: 6445 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6446 } 6447 } 6448 6449 static inline 6450 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6451 struct rtw89_sta_link *rtwsta_link) 6452 { 6453 if (rtwsta_link) { 6454 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6455 6456 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6457 return &rtwsta_link->addr_cam; 6458 } 6459 return &rtwvif_link->addr_cam; 6460 } 6461 6462 static inline 6463 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6464 struct rtw89_sta_link *rtwsta_link) 6465 { 6466 if (rtwsta_link) { 6467 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6468 6469 if (sta->tdls) 6470 return &rtwsta_link->bssid_cam; 6471 } 6472 return &rtwvif_link->bssid_cam; 6473 } 6474 6475 static inline 6476 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6477 struct rtw89_channel_help_params *p, 6478 const struct rtw89_chan *chan, 6479 enum rtw89_mac_idx mac_idx, 6480 enum rtw89_phy_idx phy_idx) 6481 { 6482 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6483 mac_idx, phy_idx); 6484 } 6485 6486 static inline 6487 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6488 struct rtw89_channel_help_params *p, 6489 const struct rtw89_chan *chan, 6490 enum rtw89_mac_idx mac_idx, 6491 enum rtw89_phy_idx phy_idx) 6492 { 6493 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6494 mac_idx, phy_idx); 6495 } 6496 6497 static inline 6498 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6499 enum rtw89_chanctx_idx idx) 6500 { 6501 struct rtw89_hal *hal = &rtwdev->hal; 6502 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6503 6504 if (roc_idx == idx) 6505 return &hal->roc_chandef; 6506 6507 return &hal->chanctx[idx].chandef; 6508 } 6509 6510 static inline 6511 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6512 enum rtw89_chanctx_idx idx) 6513 { 6514 struct rtw89_hal *hal = &rtwdev->hal; 6515 6516 return &hal->chanctx[idx].chan; 6517 } 6518 6519 static inline 6520 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6521 enum rtw89_chanctx_idx idx) 6522 { 6523 struct rtw89_hal *hal = &rtwdev->hal; 6524 6525 return &hal->chanctx[idx].rcd; 6526 } 6527 6528 static inline 6529 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6530 { 6531 const struct rtw89_chanctx *chanctx = 6532 container_of_const(chan, struct rtw89_chanctx, chan); 6533 6534 return &chanctx->rcd; 6535 } 6536 6537 static inline 6538 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6539 { 6540 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6541 6542 if (rtwvif_link) 6543 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6544 else 6545 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6546 } 6547 6548 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6549 { 6550 const struct rtw89_chip_info *chip = rtwdev->chip; 6551 6552 if (chip->ops->fem_setup) 6553 chip->ops->fem_setup(rtwdev); 6554 } 6555 6556 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6557 { 6558 const struct rtw89_chip_info *chip = rtwdev->chip; 6559 6560 if (chip->ops->rfe_gpio) 6561 chip->ops->rfe_gpio(rtwdev); 6562 } 6563 6564 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6565 { 6566 const struct rtw89_chip_info *chip = rtwdev->chip; 6567 6568 if (chip->ops->rfk_hw_init) 6569 chip->ops->rfk_hw_init(rtwdev); 6570 } 6571 6572 static inline 6573 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6574 { 6575 const struct rtw89_chip_info *chip = rtwdev->chip; 6576 6577 if (chip->ops->bb_preinit) 6578 chip->ops->bb_preinit(rtwdev, phy_idx); 6579 } 6580 6581 static inline 6582 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6583 { 6584 const struct rtw89_chip_info *chip = rtwdev->chip; 6585 6586 if (!chip->ops->bb_postinit) 6587 return; 6588 6589 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6590 6591 if (rtwdev->dbcc_en) 6592 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6593 } 6594 6595 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6596 { 6597 const struct rtw89_chip_info *chip = rtwdev->chip; 6598 6599 if (chip->ops->bb_sethw) 6600 chip->ops->bb_sethw(rtwdev); 6601 } 6602 6603 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6604 { 6605 const struct rtw89_chip_info *chip = rtwdev->chip; 6606 6607 if (chip->ops->rfk_init) 6608 chip->ops->rfk_init(rtwdev); 6609 } 6610 6611 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6612 { 6613 const struct rtw89_chip_info *chip = rtwdev->chip; 6614 6615 if (chip->ops->rfk_init_late) 6616 chip->ops->rfk_init_late(rtwdev); 6617 } 6618 6619 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6620 struct rtw89_vif_link *rtwvif_link) 6621 { 6622 const struct rtw89_chip_info *chip = rtwdev->chip; 6623 6624 if (chip->ops->rfk_channel) 6625 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6626 } 6627 6628 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6629 enum rtw89_phy_idx phy_idx, 6630 const struct rtw89_chan *chan) 6631 { 6632 const struct rtw89_chip_info *chip = rtwdev->chip; 6633 6634 if (chip->ops->rfk_band_changed) 6635 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6636 } 6637 6638 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6639 struct rtw89_vif_link *rtwvif_link, bool start) 6640 { 6641 const struct rtw89_chip_info *chip = rtwdev->chip; 6642 6643 if (chip->ops->rfk_scan) 6644 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6645 } 6646 6647 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6648 { 6649 const struct rtw89_chip_info *chip = rtwdev->chip; 6650 6651 if (chip->ops->rfk_track) 6652 chip->ops->rfk_track(rtwdev); 6653 } 6654 6655 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6656 { 6657 const struct rtw89_chip_info *chip = rtwdev->chip; 6658 6659 if (!chip->ops->set_txpwr_ctrl) 6660 return; 6661 6662 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6663 if (rtwdev->dbcc_en) 6664 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6665 } 6666 6667 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6668 { 6669 const struct rtw89_chip_info *chip = rtwdev->chip; 6670 6671 if (chip->ops->power_trim) 6672 chip->ops->power_trim(rtwdev); 6673 } 6674 6675 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6676 enum rtw89_phy_idx phy_idx) 6677 { 6678 const struct rtw89_chip_info *chip = rtwdev->chip; 6679 6680 if (chip->ops->init_txpwr_unit) 6681 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6682 } 6683 6684 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6685 { 6686 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6687 if (rtwdev->dbcc_en) 6688 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6689 } 6690 6691 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6692 enum rtw89_rf_path rf_path) 6693 { 6694 const struct rtw89_chip_info *chip = rtwdev->chip; 6695 6696 if (!chip->ops->get_thermal) 6697 return 0x10; 6698 6699 return chip->ops->get_thermal(rtwdev, rf_path); 6700 } 6701 6702 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6703 struct rtw89_rx_phy_ppdu *phy_ppdu, 6704 struct ieee80211_rx_status *status) 6705 { 6706 const struct rtw89_chip_info *chip = rtwdev->chip; 6707 6708 if (chip->ops->query_ppdu) 6709 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6710 } 6711 6712 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 6713 struct rtw89_rx_phy_ppdu *phy_ppdu) 6714 { 6715 const struct rtw89_chip_info *chip = rtwdev->chip; 6716 6717 if (chip->ops->convert_rpl_to_rssi) 6718 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 6719 } 6720 6721 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 6722 struct rtw89_rx_desc_info *desc_info, 6723 struct ieee80211_rx_status *rx_status) 6724 { 6725 const struct rtw89_chip_info *chip = rtwdev->chip; 6726 6727 if (chip->ops->phy_rpt_to_rssi) 6728 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 6729 } 6730 6731 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6732 enum rtw89_phy_idx phy_idx) 6733 { 6734 const struct rtw89_chip_info *chip = rtwdev->chip; 6735 6736 if (chip->ops->ctrl_nbtg_bt_tx) 6737 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6738 } 6739 6740 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6741 { 6742 const struct rtw89_chip_info *chip = rtwdev->chip; 6743 6744 if (chip->ops->cfg_txrx_path) 6745 chip->ops->cfg_txrx_path(rtwdev); 6746 } 6747 6748 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 6749 enum rtw89_phy_idx phy_idx) 6750 { 6751 const struct rtw89_chip_info *chip = rtwdev->chip; 6752 6753 if (chip->ops->digital_pwr_comp) 6754 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 6755 } 6756 6757 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6758 const struct rtw89_txpwr_table *tbl) 6759 { 6760 tbl->load(rtwdev, tbl); 6761 } 6762 6763 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6764 { 6765 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6766 6767 return regd->txpwr_regd[band]; 6768 } 6769 6770 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6771 enum rtw89_phy_idx phy_idx) 6772 { 6773 const struct rtw89_chip_info *chip = rtwdev->chip; 6774 6775 if (chip->ops->ctrl_btg_bt_rx) 6776 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6777 } 6778 6779 static inline 6780 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6781 struct rtw89_rx_desc_info *desc_info, 6782 u8 *data, u32 data_offset) 6783 { 6784 const struct rtw89_chip_info *chip = rtwdev->chip; 6785 6786 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6787 } 6788 6789 static inline 6790 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6791 struct rtw89_tx_desc_info *desc_info, 6792 void *txdesc) 6793 { 6794 const struct rtw89_chip_info *chip = rtwdev->chip; 6795 6796 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6797 } 6798 6799 static inline 6800 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6801 struct rtw89_tx_desc_info *desc_info, 6802 void *txdesc) 6803 { 6804 const struct rtw89_chip_info *chip = rtwdev->chip; 6805 6806 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6807 } 6808 6809 static inline 6810 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6811 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6812 { 6813 const struct rtw89_chip_info *chip = rtwdev->chip; 6814 6815 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6816 } 6817 6818 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6819 { 6820 const struct rtw89_chip_info *chip = rtwdev->chip; 6821 6822 chip->ops->cfg_ctrl_path(rtwdev, wl); 6823 } 6824 6825 static inline 6826 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6827 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6828 { 6829 const struct rtw89_chip_info *chip = rtwdev->chip; 6830 6831 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6832 } 6833 6834 static inline 6835 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6836 { 6837 const struct rtw89_chip_info *chip = rtwdev->chip; 6838 6839 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6840 } 6841 6842 static inline 6843 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6844 struct rtw89_vif_link *rtwvif_link, 6845 struct rtw89_sta_link *rtwsta_link) 6846 { 6847 const struct rtw89_chip_info *chip = rtwdev->chip; 6848 6849 if (!chip->ops->h2c_dctl_sec_cam) 6850 return 0; 6851 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 6852 } 6853 6854 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6855 { 6856 __le16 fc = hdr->frame_control; 6857 6858 if (ieee80211_has_tods(fc)) 6859 return hdr->addr1; 6860 else if (ieee80211_has_fromds(fc)) 6861 return hdr->addr2; 6862 else 6863 return hdr->addr3; 6864 } 6865 6866 static inline 6867 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 6868 { 6869 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6870 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6871 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 6872 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6873 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 6874 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6875 return true; 6876 return false; 6877 } 6878 6879 static inline 6880 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 6881 { 6882 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 6883 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 6884 return true; 6885 6886 return false; 6887 } 6888 6889 static inline 6890 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 6891 { 6892 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 6893 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 6894 return true; 6895 6896 return false; 6897 } 6898 6899 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6900 enum rtw89_fw_type type) 6901 { 6902 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6903 6904 switch (type) { 6905 case RTW89_FW_WOWLAN: 6906 return &fw_info->wowlan; 6907 case RTW89_FW_LOGFMT: 6908 return &fw_info->log.suit; 6909 case RTW89_FW_BBMCU0: 6910 return &fw_info->bbmcu0; 6911 case RTW89_FW_BBMCU1: 6912 return &fw_info->bbmcu1; 6913 default: 6914 break; 6915 } 6916 6917 return &fw_info->normal; 6918 } 6919 6920 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6921 unsigned int length) 6922 { 6923 struct sk_buff *skb; 6924 6925 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6926 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6927 if (!skb) 6928 return NULL; 6929 6930 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6931 return skb; 6932 } 6933 6934 return dev_alloc_skb(length); 6935 } 6936 6937 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6938 struct rtw89_tx_skb_data *skb_data, 6939 bool tx_done) 6940 { 6941 struct rtw89_tx_wait_info *wait; 6942 6943 rcu_read_lock(); 6944 6945 wait = rcu_dereference(skb_data->wait); 6946 if (!wait) 6947 goto out; 6948 6949 wait->tx_done = tx_done; 6950 complete(&wait->completion); 6951 6952 out: 6953 rcu_read_unlock(); 6954 } 6955 6956 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6957 { 6958 switch (rtwdev->mlo_dbcc_mode) { 6959 case MLO_1_PLUS_1_1RF: 6960 case MLO_1_PLUS_1_2RF: 6961 case DBCC_LEGACY: 6962 return true; 6963 default: 6964 return false; 6965 } 6966 } 6967 6968 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 6969 { 6970 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6971 6972 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 6973 return true; 6974 6975 return false; 6976 } 6977 6978 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6979 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6980 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6981 struct sk_buff *skb, bool fwdl); 6982 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6983 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6984 int qsel, unsigned int timeout); 6985 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6986 struct rtw89_tx_desc_info *desc_info, 6987 void *txdesc); 6988 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 6989 struct rtw89_tx_desc_info *desc_info, 6990 void *txdesc); 6991 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 6992 struct rtw89_tx_desc_info *desc_info, 6993 void *txdesc); 6994 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 6995 struct rtw89_tx_desc_info *desc_info, 6996 void *txdesc); 6997 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 6998 struct rtw89_tx_desc_info *desc_info, 6999 void *txdesc); 7000 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7001 struct rtw89_rx_desc_info *desc_info, 7002 struct sk_buff *skb); 7003 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7004 struct rtw89_rx_desc_info *desc_info, 7005 u8 *data, u32 data_offset); 7006 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7007 struct rtw89_rx_desc_info *desc_info, 7008 u8 *data, u32 data_offset); 7009 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7010 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7011 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7012 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7013 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7014 struct rtw89_vif_link *rtwvif_link, 7015 struct rtw89_sta_link *rtwsta_link); 7016 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7017 struct rtw89_vif_link *rtwvif_link, 7018 struct rtw89_sta_link *rtwsta_link); 7019 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7020 struct rtw89_vif_link *rtwvif_link, 7021 struct rtw89_sta_link *rtwsta_link); 7022 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7023 struct rtw89_vif_link *rtwvif_link, 7024 struct rtw89_sta_link *rtwsta_link); 7025 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7026 struct rtw89_vif_link *rtwvif_link, 7027 struct rtw89_sta_link *rtwsta_link); 7028 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7029 struct ieee80211_sta *sta, 7030 struct cfg80211_tid_config *tid_config); 7031 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7032 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7033 int rtw89_core_init(struct rtw89_dev *rtwdev); 7034 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7035 int rtw89_core_register(struct rtw89_dev *rtwdev); 7036 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7037 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7038 u32 bus_data_size, 7039 const struct rtw89_chip_info *chip); 7040 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7041 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7042 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7043 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7044 u8 mac_id, u8 port); 7045 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7046 struct rtw89_sta *rtwsta, u8 mac_id); 7047 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7048 unsigned int link_id); 7049 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7050 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7051 unsigned int link_id); 7052 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7053 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7054 const struct rtw89_6ghz_span * 7055 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7056 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7057 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7058 struct rtw89_chan *chan); 7059 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7060 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7061 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7062 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7063 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7064 struct rtw89_sta_link *rtwsta_link, u8 tid, 7065 u8 *cam_idx); 7066 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7067 struct rtw89_sta_link *rtwsta_link, u8 tid, 7068 u8 *cam_idx); 7069 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7070 struct ieee80211_sta *sta); 7071 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7072 struct ieee80211_sta *sta); 7073 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7074 struct ieee80211_sta *sta); 7075 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7076 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7077 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7078 struct rtw89_vif_link *rtwvif_link); 7079 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 7080 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7081 int rtw89_regd_init(struct rtw89_dev *rtwdev, 7082 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 7083 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 7084 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7085 struct rtw89_traffic_stats *stats); 7086 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 7087 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7088 const struct rtw89_completion_data *data); 7089 int rtw89_core_start(struct rtw89_dev *rtwdev); 7090 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7091 void rtw89_core_update_beacon_work(struct work_struct *work); 7092 void rtw89_roc_work(struct work_struct *work); 7093 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7094 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7095 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7096 const u8 *mac_addr, bool hw_scan); 7097 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7098 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7099 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7100 bool active); 7101 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7102 struct rtw89_vif_link *rtwvif_link, 7103 struct ieee80211_bss_conf *bss_conf); 7104 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7105 7106 #endif 7107