1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/dmi.h> 11 #include <linux/firmware.h> 12 #include <linux/iopoll.h> 13 #include <linux/workqueue.h> 14 #include <net/mac80211.h> 15 16 struct rtw89_dev; 17 struct rtw89_pci_info; 18 struct rtw89_mac_gen_def; 19 struct rtw89_phy_gen_def; 20 struct rtw89_efuse_block_cfg; 21 struct rtw89_h2c_rf_tssi; 22 struct rtw89_fw_txpwr_track_cfg; 23 struct rtw89_phy_rfk_log_fmt; 24 struct rtw89_debugfs; 25 26 extern const struct ieee80211_ops rtw89_ops; 27 28 #define MASKBYTE0 0xff 29 #define MASKBYTE1 0xff00 30 #define MASKBYTE2 0xff0000 31 #define MASKBYTE3 0xff000000 32 #define MASKBYTE4 0xff00000000ULL 33 #define MASKHWORD 0xffff0000 34 #define MASKLWORD 0x0000ffff 35 #define MASKDWORD 0xffffffff 36 #define RFREG_MASK 0xfffff 37 #define INV_RF_DATA 0xffffffff 38 #define BYPASS_CR_DATA 0xbabecafe 39 40 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 41 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 42 #define CFO_TRACK_MAX_USER 64 43 #define MAX_RSSI 110 44 #define RSSI_FACTOR 1 45 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 46 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 47 #define DELTA_SWINGIDX_SIZE 30 48 49 #define RTW89_RADIOTAP_ROOM_HE sizeof(struct ieee80211_radiotap_he) 50 #define RTW89_RADIOTAP_ROOM_EHT \ 51 (sizeof(struct ieee80211_radiotap_tlv) + \ 52 ALIGN(struct_size((struct ieee80211_radiotap_eht *)0, user_info, 1), 4) + \ 53 sizeof(struct ieee80211_radiotap_tlv) + \ 54 ALIGN(sizeof(struct ieee80211_radiotap_eht_usig), 4)) 55 #define RTW89_RADIOTAP_ROOM \ 56 ALIGN(max(RTW89_RADIOTAP_ROOM_HE, RTW89_RADIOTAP_ROOM_EHT), 64) 57 58 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 59 #define RTW89_HTC_VARIANT_HE 3 60 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 61 #define RTW89_HTC_VARIANT_HE_CID_OM 1 62 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 63 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 64 65 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 66 enum htc_om_channel_width { 67 HTC_OM_CHANNEL_WIDTH_20 = 0, 68 HTC_OM_CHANNEL_WIDTH_40 = 1, 69 HTC_OM_CHANNEL_WIDTH_80 = 2, 70 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 71 }; 72 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 73 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 74 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 75 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 76 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 77 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 78 79 #define RTW89_TF_PAD GENMASK(11, 0) 80 #define RTW89_TF_BASIC_USER_INFO_SZ 6 81 82 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 83 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 84 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 85 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 86 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 87 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 88 89 enum rtw89_subband { 90 RTW89_CH_2G = 0, 91 RTW89_CH_5G_BAND_1 = 1, 92 /* RTW89_CH_5G_BAND_2 = 2, unused */ 93 RTW89_CH_5G_BAND_3 = 3, 94 RTW89_CH_5G_BAND_4 = 4, 95 96 RTW89_CH_6G_BAND_IDX0, /* Low */ 97 RTW89_CH_6G_BAND_IDX1, /* Low */ 98 RTW89_CH_6G_BAND_IDX2, /* Mid */ 99 RTW89_CH_6G_BAND_IDX3, /* Mid */ 100 RTW89_CH_6G_BAND_IDX4, /* High */ 101 RTW89_CH_6G_BAND_IDX5, /* High */ 102 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 103 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 104 105 RTW89_SUBBAND_NR, 106 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 107 }; 108 109 enum rtw89_gain_offset { 110 RTW89_GAIN_OFFSET_2G_CCK, 111 RTW89_GAIN_OFFSET_2G_OFDM, 112 RTW89_GAIN_OFFSET_5G_LOW, 113 RTW89_GAIN_OFFSET_5G_MID, 114 RTW89_GAIN_OFFSET_5G_HIGH, 115 RTW89_GAIN_OFFSET_6G_L0, 116 RTW89_GAIN_OFFSET_6G_L1, 117 RTW89_GAIN_OFFSET_6G_M0, 118 RTW89_GAIN_OFFSET_6G_M1, 119 RTW89_GAIN_OFFSET_6G_H0, 120 RTW89_GAIN_OFFSET_6G_H1, 121 RTW89_GAIN_OFFSET_6G_UH0, 122 RTW89_GAIN_OFFSET_6G_UH1, 123 124 RTW89_GAIN_OFFSET_NR, 125 }; 126 127 enum rtw89_hci_type { 128 RTW89_HCI_TYPE_PCIE, 129 RTW89_HCI_TYPE_USB, 130 RTW89_HCI_TYPE_SDIO, 131 }; 132 133 enum rtw89_core_chip_id { 134 RTL8852A, 135 RTL8852B, 136 RTL8852BT, 137 RTL8852C, 138 RTL8851B, 139 RTL8922A, 140 }; 141 142 enum rtw89_chip_gen { 143 RTW89_CHIP_AX, 144 RTW89_CHIP_BE, 145 146 RTW89_CHIP_GEN_NUM, 147 }; 148 149 enum rtw89_cv { 150 CHIP_CAV, 151 CHIP_CBV, 152 CHIP_CCV, 153 CHIP_CDV, 154 CHIP_CEV, 155 CHIP_CFV, 156 CHIP_CV_MAX, 157 CHIP_CV_INVALID = CHIP_CV_MAX, 158 }; 159 160 enum rtw89_bacam_ver { 161 RTW89_BACAM_V0, 162 RTW89_BACAM_V1, 163 164 RTW89_BACAM_V0_EXT = 99, 165 }; 166 167 enum rtw89_core_tx_type { 168 RTW89_CORE_TX_TYPE_DATA, 169 RTW89_CORE_TX_TYPE_MGMT, 170 RTW89_CORE_TX_TYPE_FWCMD, 171 }; 172 173 enum rtw89_core_rx_type { 174 RTW89_CORE_RX_TYPE_WIFI = 0, 175 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 176 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 177 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 178 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 179 RTW89_CORE_RX_TYPE_SS2FW = 5, 180 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 181 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 182 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 183 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 184 RTW89_CORE_RX_TYPE_C2H = 10, 185 RTW89_CORE_RX_TYPE_CSI = 11, 186 RTW89_CORE_RX_TYPE_CQI = 12, 187 RTW89_CORE_RX_TYPE_H2C = 13, 188 RTW89_CORE_RX_TYPE_FWDL = 14, 189 }; 190 191 enum rtw89_txq_flags { 192 RTW89_TXQ_F_AMPDU = 0, 193 RTW89_TXQ_F_BLOCK_BA = 1, 194 RTW89_TXQ_F_FORBID_BA = 2, 195 }; 196 197 enum rtw89_net_type { 198 RTW89_NET_TYPE_NO_LINK = 0, 199 RTW89_NET_TYPE_AD_HOC = 1, 200 RTW89_NET_TYPE_INFRA = 2, 201 RTW89_NET_TYPE_AP_MODE = 3, 202 }; 203 204 enum rtw89_wifi_role { 205 RTW89_WIFI_ROLE_NONE, 206 RTW89_WIFI_ROLE_STATION, 207 RTW89_WIFI_ROLE_AP, 208 RTW89_WIFI_ROLE_AP_VLAN, 209 RTW89_WIFI_ROLE_ADHOC, 210 RTW89_WIFI_ROLE_ADHOC_MASTER, 211 RTW89_WIFI_ROLE_MESH_POINT, 212 RTW89_WIFI_ROLE_MONITOR, 213 RTW89_WIFI_ROLE_P2P_DEVICE, 214 RTW89_WIFI_ROLE_P2P_CLIENT, 215 RTW89_WIFI_ROLE_P2P_GO, 216 RTW89_WIFI_ROLE_NAN, 217 RTW89_WIFI_ROLE_MLME_MAX 218 }; 219 220 enum rtw89_upd_mode { 221 RTW89_ROLE_CREATE, 222 RTW89_ROLE_REMOVE, 223 RTW89_ROLE_TYPE_CHANGE, 224 RTW89_ROLE_INFO_CHANGE, 225 RTW89_ROLE_CON_DISCONN, 226 RTW89_ROLE_BAND_SW, 227 RTW89_ROLE_FW_RESTORE, 228 }; 229 230 enum rtw89_self_role { 231 RTW89_SELF_ROLE_CLIENT, 232 RTW89_SELF_ROLE_AP, 233 RTW89_SELF_ROLE_AP_CLIENT 234 }; 235 236 enum rtw89_msk_sO_el { 237 RTW89_NO_MSK, 238 RTW89_SMA, 239 RTW89_TMA, 240 RTW89_BSSID 241 }; 242 243 enum rtw89_sch_tx_sel { 244 RTW89_SCH_TX_SEL_ALL, 245 RTW89_SCH_TX_SEL_HIQ, 246 RTW89_SCH_TX_SEL_MG0, 247 RTW89_SCH_TX_SEL_MACID, 248 }; 249 250 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 251 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 252 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 253 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 254 */ 255 enum rtw89_add_cam_sec_mode { 256 RTW89_ADDR_CAM_SEC_NONE = 0, 257 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 258 RTW89_ADDR_CAM_SEC_NORMAL = 2, 259 RTW89_ADDR_CAM_SEC_4GROUP = 3, 260 }; 261 262 enum rtw89_sec_key_type { 263 RTW89_SEC_KEY_TYPE_NONE = 0, 264 RTW89_SEC_KEY_TYPE_WEP40 = 1, 265 RTW89_SEC_KEY_TYPE_WEP104 = 2, 266 RTW89_SEC_KEY_TYPE_TKIP = 3, 267 RTW89_SEC_KEY_TYPE_WAPI = 4, 268 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 269 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 270 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 271 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 272 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 273 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 274 }; 275 276 enum rtw89_port { 277 RTW89_PORT_0 = 0, 278 RTW89_PORT_1 = 1, 279 RTW89_PORT_2 = 2, 280 RTW89_PORT_3 = 3, 281 RTW89_PORT_4 = 4, 282 RTW89_PORT_NUM 283 }; 284 285 enum rtw89_band { 286 RTW89_BAND_2G = 0, 287 RTW89_BAND_5G = 1, 288 RTW89_BAND_6G = 2, 289 RTW89_BAND_NUM, 290 }; 291 292 enum rtw89_hw_rate { 293 RTW89_HW_RATE_CCK1 = 0x0, 294 RTW89_HW_RATE_CCK2 = 0x1, 295 RTW89_HW_RATE_CCK5_5 = 0x2, 296 RTW89_HW_RATE_CCK11 = 0x3, 297 RTW89_HW_RATE_OFDM6 = 0x4, 298 RTW89_HW_RATE_OFDM9 = 0x5, 299 RTW89_HW_RATE_OFDM12 = 0x6, 300 RTW89_HW_RATE_OFDM18 = 0x7, 301 RTW89_HW_RATE_OFDM24 = 0x8, 302 RTW89_HW_RATE_OFDM36 = 0x9, 303 RTW89_HW_RATE_OFDM48 = 0xA, 304 RTW89_HW_RATE_OFDM54 = 0xB, 305 RTW89_HW_RATE_MCS0 = 0x80, 306 RTW89_HW_RATE_MCS1 = 0x81, 307 RTW89_HW_RATE_MCS2 = 0x82, 308 RTW89_HW_RATE_MCS3 = 0x83, 309 RTW89_HW_RATE_MCS4 = 0x84, 310 RTW89_HW_RATE_MCS5 = 0x85, 311 RTW89_HW_RATE_MCS6 = 0x86, 312 RTW89_HW_RATE_MCS7 = 0x87, 313 RTW89_HW_RATE_MCS8 = 0x88, 314 RTW89_HW_RATE_MCS9 = 0x89, 315 RTW89_HW_RATE_MCS10 = 0x8A, 316 RTW89_HW_RATE_MCS11 = 0x8B, 317 RTW89_HW_RATE_MCS12 = 0x8C, 318 RTW89_HW_RATE_MCS13 = 0x8D, 319 RTW89_HW_RATE_MCS14 = 0x8E, 320 RTW89_HW_RATE_MCS15 = 0x8F, 321 RTW89_HW_RATE_MCS16 = 0x90, 322 RTW89_HW_RATE_MCS17 = 0x91, 323 RTW89_HW_RATE_MCS18 = 0x92, 324 RTW89_HW_RATE_MCS19 = 0x93, 325 RTW89_HW_RATE_MCS20 = 0x94, 326 RTW89_HW_RATE_MCS21 = 0x95, 327 RTW89_HW_RATE_MCS22 = 0x96, 328 RTW89_HW_RATE_MCS23 = 0x97, 329 RTW89_HW_RATE_MCS24 = 0x98, 330 RTW89_HW_RATE_MCS25 = 0x99, 331 RTW89_HW_RATE_MCS26 = 0x9A, 332 RTW89_HW_RATE_MCS27 = 0x9B, 333 RTW89_HW_RATE_MCS28 = 0x9C, 334 RTW89_HW_RATE_MCS29 = 0x9D, 335 RTW89_HW_RATE_MCS30 = 0x9E, 336 RTW89_HW_RATE_MCS31 = 0x9F, 337 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 338 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 339 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 340 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 341 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 342 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 343 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 344 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 345 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 346 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 347 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 348 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 349 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 350 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 351 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 352 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 353 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 354 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 355 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 356 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 357 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 358 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 359 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 360 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 361 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 362 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 363 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 364 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 365 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 366 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 367 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 368 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 369 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 370 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 371 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 372 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 373 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 374 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 375 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 376 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 377 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 378 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 379 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 380 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 381 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 382 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 383 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 384 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 385 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 386 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 387 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 388 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 389 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 390 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 391 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 392 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 393 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 394 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 395 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 396 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 397 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 398 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 399 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 400 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 401 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 402 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 403 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 404 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 405 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 406 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 407 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 408 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 409 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 410 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 411 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 412 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 413 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 414 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 415 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 416 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 417 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 418 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 419 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 420 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 421 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 422 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 423 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 424 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 425 426 RTW89_HW_RATE_V1_MCS0 = 0x100, 427 RTW89_HW_RATE_V1_MCS1 = 0x101, 428 RTW89_HW_RATE_V1_MCS2 = 0x102, 429 RTW89_HW_RATE_V1_MCS3 = 0x103, 430 RTW89_HW_RATE_V1_MCS4 = 0x104, 431 RTW89_HW_RATE_V1_MCS5 = 0x105, 432 RTW89_HW_RATE_V1_MCS6 = 0x106, 433 RTW89_HW_RATE_V1_MCS7 = 0x107, 434 RTW89_HW_RATE_V1_MCS8 = 0x108, 435 RTW89_HW_RATE_V1_MCS9 = 0x109, 436 RTW89_HW_RATE_V1_MCS10 = 0x10A, 437 RTW89_HW_RATE_V1_MCS11 = 0x10B, 438 RTW89_HW_RATE_V1_MCS12 = 0x10C, 439 RTW89_HW_RATE_V1_MCS13 = 0x10D, 440 RTW89_HW_RATE_V1_MCS14 = 0x10E, 441 RTW89_HW_RATE_V1_MCS15 = 0x10F, 442 RTW89_HW_RATE_V1_MCS16 = 0x110, 443 RTW89_HW_RATE_V1_MCS17 = 0x111, 444 RTW89_HW_RATE_V1_MCS18 = 0x112, 445 RTW89_HW_RATE_V1_MCS19 = 0x113, 446 RTW89_HW_RATE_V1_MCS20 = 0x114, 447 RTW89_HW_RATE_V1_MCS21 = 0x115, 448 RTW89_HW_RATE_V1_MCS22 = 0x116, 449 RTW89_HW_RATE_V1_MCS23 = 0x117, 450 RTW89_HW_RATE_V1_MCS24 = 0x118, 451 RTW89_HW_RATE_V1_MCS25 = 0x119, 452 RTW89_HW_RATE_V1_MCS26 = 0x11A, 453 RTW89_HW_RATE_V1_MCS27 = 0x11B, 454 RTW89_HW_RATE_V1_MCS28 = 0x11C, 455 RTW89_HW_RATE_V1_MCS29 = 0x11D, 456 RTW89_HW_RATE_V1_MCS30 = 0x11E, 457 RTW89_HW_RATE_V1_MCS31 = 0x11F, 458 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 459 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 460 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 461 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 462 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 463 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 464 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 465 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 466 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 467 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 468 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 469 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 470 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 471 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 472 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 473 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 474 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 475 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 476 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 477 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 478 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 479 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 480 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 481 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 482 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 483 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 484 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 485 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 486 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 487 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 488 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 489 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 490 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 491 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 492 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 493 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 494 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 495 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 496 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 497 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 498 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 499 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 500 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 501 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 502 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 503 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 504 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 505 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 506 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 507 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 508 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 509 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 510 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 511 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 512 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 513 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 514 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 515 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 516 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 517 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 518 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 519 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 520 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 521 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 522 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 523 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 524 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 525 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 526 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 527 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 528 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 529 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 530 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 531 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 532 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 533 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 534 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 535 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 536 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 537 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 538 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 539 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 540 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 541 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 542 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 543 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 544 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 545 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 546 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 547 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 548 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 549 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 550 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 551 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 552 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 553 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 554 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 555 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 556 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 557 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 558 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 559 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 560 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 561 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 562 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 563 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 564 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 565 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 566 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 567 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 568 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 569 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 570 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 571 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 572 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 573 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 574 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 575 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 576 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 577 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 578 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 579 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 580 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 581 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 582 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 583 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 584 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 585 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 586 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 587 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 588 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 589 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 590 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 591 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 592 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 593 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 594 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 595 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 596 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 597 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 598 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 599 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 600 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 601 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 602 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 603 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 604 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 605 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 606 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 607 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 608 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 609 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 610 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 611 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 612 613 RTW89_HW_RATE_NR, 614 RTW89_HW_RATE_INVAL, 615 616 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 617 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 618 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 619 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 620 }; 621 622 /* 2G channels, 623 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 624 */ 625 #define RTW89_2G_CH_NUM 14 626 627 /* 5G channels, 628 * 36, 38, 40, 42, 44, 46, 48, 50, 629 * 52, 54, 56, 58, 60, 62, 64, 630 * 100, 102, 104, 106, 108, 110, 112, 114, 631 * 116, 118, 120, 122, 124, 126, 128, 130, 632 * 132, 134, 136, 138, 140, 142, 144, 633 * 149, 151, 153, 155, 157, 159, 161, 163, 634 * 165, 167, 169, 171, 173, 175, 177 635 */ 636 #define RTW89_5G_CH_NUM 53 637 638 /* 6G channels, 639 * 1, 3, 5, 7, 9, 11, 13, 15, 640 * 17, 19, 21, 23, 25, 27, 29, 33, 641 * 35, 37, 39, 41, 43, 45, 47, 49, 642 * 51, 53, 55, 57, 59, 61, 65, 67, 643 * 69, 71, 73, 75, 77, 79, 81, 83, 644 * 85, 87, 89, 91, 93, 97, 99, 101, 645 * 103, 105, 107, 109, 111, 113, 115, 117, 646 * 119, 121, 123, 125, 129, 131, 133, 135, 647 * 137, 139, 141, 143, 145, 147, 149, 151, 648 * 153, 155, 157, 161, 163, 165, 167, 169, 649 * 171, 173, 175, 177, 179, 181, 183, 185, 650 * 187, 189, 193, 195, 197, 199, 201, 203, 651 * 205, 207, 209, 211, 213, 215, 217, 219, 652 * 221, 225, 227, 229, 231, 233, 235, 237, 653 * 239, 241, 243, 245, 247, 249, 251, 253, 654 */ 655 #define RTW89_6G_CH_NUM 120 656 657 enum rtw89_rate_section { 658 RTW89_RS_CCK, 659 RTW89_RS_OFDM, 660 RTW89_RS_MCS, /* for HT/VHT/HE */ 661 RTW89_RS_HEDCM, 662 RTW89_RS_OFFSET, 663 RTW89_RS_NUM, 664 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 665 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 666 }; 667 668 enum rtw89_rate_offset_indexes { 669 RTW89_RATE_OFFSET_HE, 670 RTW89_RATE_OFFSET_VHT, 671 RTW89_RATE_OFFSET_HT, 672 RTW89_RATE_OFFSET_OFDM, 673 RTW89_RATE_OFFSET_CCK, 674 RTW89_RATE_OFFSET_DLRU_EHT, 675 RTW89_RATE_OFFSET_DLRU_HE, 676 RTW89_RATE_OFFSET_EHT, 677 __RTW89_RATE_OFFSET_NUM, 678 679 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 680 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 681 }; 682 683 enum rtw89_rate_num { 684 RTW89_RATE_CCK_NUM = 4, 685 RTW89_RATE_OFDM_NUM = 8, 686 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 687 688 RTW89_RATE_MCS_NUM_AX = 12, 689 RTW89_RATE_MCS_NUM_BE = 16, 690 __RTW89_RATE_MCS_NUM = 16, 691 }; 692 693 enum rtw89_nss { 694 RTW89_NSS_1 = 0, 695 RTW89_NSS_2 = 1, 696 /* HE DCM only support 1ss and 2ss */ 697 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 698 RTW89_NSS_3 = 2, 699 RTW89_NSS_4 = 3, 700 RTW89_NSS_NUM, 701 }; 702 703 enum rtw89_ntx { 704 RTW89_1TX = 0, 705 RTW89_2TX = 1, 706 RTW89_NTX_NUM, 707 }; 708 709 enum rtw89_beamforming_type { 710 RTW89_NONBF = 0, 711 RTW89_BF = 1, 712 RTW89_BF_NUM, 713 }; 714 715 enum rtw89_ofdma_type { 716 RTW89_NON_OFDMA = 0, 717 RTW89_OFDMA = 1, 718 RTW89_OFDMA_NUM, 719 }; 720 721 enum rtw89_regulation_type { 722 RTW89_WW = 0, 723 RTW89_ETSI = 1, 724 RTW89_FCC = 2, 725 RTW89_MKK = 3, 726 RTW89_NA = 4, 727 RTW89_IC = 5, 728 RTW89_KCC = 6, 729 RTW89_ACMA = 7, 730 RTW89_NCC = 8, 731 RTW89_MEXICO = 9, 732 RTW89_CHILE = 10, 733 RTW89_UKRAINE = 11, 734 RTW89_CN = 12, 735 RTW89_QATAR = 13, 736 RTW89_UK = 14, 737 RTW89_THAILAND = 15, 738 RTW89_REGD_NUM, 739 }; 740 741 enum rtw89_reg_6ghz_power { 742 RTW89_REG_6GHZ_POWER_VLP = 0, 743 RTW89_REG_6GHZ_POWER_LPI = 1, 744 RTW89_REG_6GHZ_POWER_STD = 2, 745 746 NUM_OF_RTW89_REG_6GHZ_POWER, 747 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 748 }; 749 750 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */ 751 752 /* calculate based on ieee80211 Transmit Power Envelope */ 753 struct rtw89_reg_6ghz_tpe { 754 bool valid; 755 s8 constraint; /* unit: dBm */ 756 }; 757 758 enum rtw89_fw_pkt_ofld_type { 759 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 760 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 761 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 762 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 763 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 764 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 765 RTW89_PKT_OFLD_TYPE_NDP = 6, 766 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 767 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 768 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 769 RTW89_PKT_OFLD_TYPE_NUM, 770 }; 771 772 struct rtw89_txpwr_byrate { 773 s8 cck[RTW89_RATE_CCK_NUM]; 774 s8 ofdm[RTW89_RATE_OFDM_NUM]; 775 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 776 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 777 s8 offset[__RTW89_RATE_OFFSET_NUM]; 778 s8 trap; 779 }; 780 781 struct rtw89_rate_desc { 782 enum rtw89_nss nss; 783 enum rtw89_rate_section rs; 784 enum rtw89_ofdma_type ofdma; 785 u8 idx; 786 }; 787 788 #define PHY_STS_HDR_LEN 8 789 #define RF_PATH_MAX 4 790 #define RTW89_MAX_PPDU_CNT 8 791 struct rtw89_rx_phy_ppdu { 792 void *buf; 793 u32 len; 794 u8 rssi_avg; 795 u8 rssi[RF_PATH_MAX]; 796 u8 mac_id; 797 u8 chan_idx; 798 u8 ie; 799 u16 rate; 800 u8 rpl_avg; 801 u8 rpl_path[RF_PATH_MAX]; 802 u8 rpl_fd[RF_PATH_MAX]; 803 u8 bw_idx; 804 u8 rx_path_en; 805 struct { 806 bool has; 807 u8 avg_snr; 808 u8 evm_max; 809 u8 evm_min; 810 } ofdm; 811 bool has_data; 812 bool has_bcn; 813 bool ldpc; 814 bool stbc; 815 bool to_self; 816 bool valid; 817 bool hdr_2_en; 818 }; 819 820 enum rtw89_mac_idx { 821 RTW89_MAC_0 = 0, 822 RTW89_MAC_1 = 1, 823 RTW89_MAC_NUM, 824 }; 825 826 enum rtw89_phy_idx { 827 RTW89_PHY_0 = 0, 828 RTW89_PHY_1 = 1, 829 RTW89_PHY_MAX 830 }; 831 832 #define __RTW89_MLD_MAX_LINK_NUM 2 833 #define RTW89_MLD_NON_STA_LINK_NUM 1 834 835 enum rtw89_chanctx_idx { 836 RTW89_CHANCTX_0 = 0, 837 RTW89_CHANCTX_1 = 1, 838 839 NUM_OF_RTW89_CHANCTX, 840 RTW89_CHANCTX_IDLE = NUM_OF_RTW89_CHANCTX, 841 }; 842 843 enum rtw89_rf_path { 844 RF_PATH_A = 0, 845 RF_PATH_B = 1, 846 RF_PATH_C = 2, 847 RF_PATH_D = 3, 848 RF_PATH_AB, 849 RF_PATH_AC, 850 RF_PATH_AD, 851 RF_PATH_BC, 852 RF_PATH_BD, 853 RF_PATH_CD, 854 RF_PATH_ABC, 855 RF_PATH_ABD, 856 RF_PATH_ACD, 857 RF_PATH_BCD, 858 RF_PATH_ABCD, 859 }; 860 861 enum rtw89_rf_path_bit { 862 RF_A = BIT(0), 863 RF_B = BIT(1), 864 RF_C = BIT(2), 865 RF_D = BIT(3), 866 867 RF_AB = (RF_A | RF_B), 868 RF_AC = (RF_A | RF_C), 869 RF_AD = (RF_A | RF_D), 870 RF_BC = (RF_B | RF_C), 871 RF_BD = (RF_B | RF_D), 872 RF_CD = (RF_C | RF_D), 873 874 RF_ABC = (RF_A | RF_B | RF_C), 875 RF_ABD = (RF_A | RF_B | RF_D), 876 RF_ACD = (RF_A | RF_C | RF_D), 877 RF_BCD = (RF_B | RF_C | RF_D), 878 879 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 880 }; 881 882 enum rtw89_bandwidth { 883 RTW89_CHANNEL_WIDTH_20 = 0, 884 RTW89_CHANNEL_WIDTH_40 = 1, 885 RTW89_CHANNEL_WIDTH_80 = 2, 886 RTW89_CHANNEL_WIDTH_160 = 3, 887 RTW89_CHANNEL_WIDTH_320 = 4, 888 889 /* keep index order above */ 890 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 891 892 RTW89_CHANNEL_WIDTH_80_80 = 5, 893 RTW89_CHANNEL_WIDTH_5 = 6, 894 RTW89_CHANNEL_WIDTH_10 = 7, 895 }; 896 897 enum rtw89_ps_mode { 898 RTW89_PS_MODE_NONE = 0, 899 RTW89_PS_MODE_RFOFF = 1, 900 RTW89_PS_MODE_CLK_GATED = 2, 901 RTW89_PS_MODE_PWR_GATED = 3, 902 }; 903 904 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 905 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 906 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 907 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 908 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 909 910 enum rtw89_pe_duration { 911 RTW89_PE_DURATION_0 = 0, 912 RTW89_PE_DURATION_8 = 1, 913 RTW89_PE_DURATION_16 = 2, 914 RTW89_PE_DURATION_16_20 = 3, 915 }; 916 917 enum rtw89_ru_bandwidth { 918 RTW89_RU26 = 0, 919 RTW89_RU52 = 1, 920 RTW89_RU106 = 2, 921 RTW89_RU52_26 = 3, 922 RTW89_RU106_26 = 4, 923 RTW89_RU_NUM, 924 }; 925 926 enum rtw89_sc_offset { 927 RTW89_SC_DONT_CARE = 0, 928 RTW89_SC_20_UPPER = 1, 929 RTW89_SC_20_LOWER = 2, 930 RTW89_SC_20_UPMOST = 3, 931 RTW89_SC_20_LOWEST = 4, 932 RTW89_SC_20_UP2X = 5, 933 RTW89_SC_20_LOW2X = 6, 934 RTW89_SC_20_UP3X = 7, 935 RTW89_SC_20_LOW3X = 8, 936 RTW89_SC_40_UPPER = 9, 937 RTW89_SC_40_LOWER = 10, 938 }; 939 940 /* only mgd features can be added to the enum */ 941 enum rtw89_wow_flags { 942 RTW89_WOW_FLAG_EN_MAGIC_PKT, 943 RTW89_WOW_FLAG_EN_REKEY_PKT, 944 RTW89_WOW_FLAG_EN_DISCONNECT, 945 RTW89_WOW_FLAG_EN_PATTERN, 946 RTW89_WOW_FLAG_NUM, 947 }; 948 949 struct rtw89_chan { 950 u8 channel; 951 u8 primary_channel; 952 enum rtw89_band band_type; 953 enum rtw89_bandwidth band_width; 954 955 /* The follow-up are derived from the above. We must ensure that it 956 * is assigned correctly in rtw89_chan_create() if new one is added. 957 */ 958 u32 freq; 959 enum rtw89_subband subband_type; 960 enum rtw89_sc_offset pri_ch_idx; 961 u8 pri_sb_idx; 962 }; 963 964 struct rtw89_chan_rcd { 965 u8 prev_primary_channel; 966 enum rtw89_band prev_band_type; 967 bool band_changed; 968 }; 969 970 struct rtw89_channel_help_params { 971 u32 tx_en; 972 }; 973 974 struct rtw89_port_reg { 975 u32 port_cfg; 976 u32 tbtt_prohib; 977 u32 bcn_area; 978 u32 bcn_early; 979 u32 tbtt_early; 980 u32 tbtt_agg; 981 u32 bcn_space; 982 u32 bcn_forcetx; 983 u32 bcn_err_cnt; 984 u32 bcn_err_flag; 985 u32 dtim_ctrl; 986 u32 tbtt_shift; 987 u32 bcn_cnt_tmr; 988 u32 tsftr_l; 989 u32 tsftr_h; 990 u32 md_tsft; 991 u32 bss_color; 992 u32 mbssid; 993 u32 mbssid_drop; 994 u32 tsf_sync; 995 u32 ptcl_dbg; 996 u32 ptcl_dbg_info; 997 u32 bcn_drop_all; 998 u32 hiq_win[RTW89_PORT_NUM]; 999 }; 1000 1001 struct rtw89_txwd_body { 1002 __le32 dword0; 1003 __le32 dword1; 1004 __le32 dword2; 1005 __le32 dword3; 1006 __le32 dword4; 1007 __le32 dword5; 1008 } __packed; 1009 1010 struct rtw89_txwd_body_v1 { 1011 __le32 dword0; 1012 __le32 dword1; 1013 __le32 dword2; 1014 __le32 dword3; 1015 __le32 dword4; 1016 __le32 dword5; 1017 __le32 dword6; 1018 __le32 dword7; 1019 } __packed; 1020 1021 struct rtw89_txwd_body_v2 { 1022 __le32 dword0; 1023 __le32 dword1; 1024 __le32 dword2; 1025 __le32 dword3; 1026 __le32 dword4; 1027 __le32 dword5; 1028 __le32 dword6; 1029 __le32 dword7; 1030 } __packed; 1031 1032 struct rtw89_txwd_info { 1033 __le32 dword0; 1034 __le32 dword1; 1035 __le32 dword2; 1036 __le32 dword3; 1037 __le32 dword4; 1038 __le32 dword5; 1039 } __packed; 1040 1041 struct rtw89_txwd_info_v2 { 1042 __le32 dword0; 1043 __le32 dword1; 1044 __le32 dword2; 1045 __le32 dword3; 1046 __le32 dword4; 1047 __le32 dword5; 1048 __le32 dword6; 1049 __le32 dword7; 1050 } __packed; 1051 1052 struct rtw89_rx_desc_info { 1053 u16 pkt_size; 1054 u8 pkt_type; 1055 u8 drv_info_size; 1056 u8 phy_rpt_size; 1057 u8 hdr_cnv_size; 1058 u8 shift; 1059 u8 wl_hd_iv_len; 1060 bool long_rxdesc; 1061 bool bb_sel; 1062 bool mac_info_valid; 1063 u16 data_rate; 1064 u8 gi_ltf; 1065 u8 bw; 1066 u32 free_run_cnt; 1067 u8 user_id; 1068 bool sr_en; 1069 u8 ppdu_cnt; 1070 u8 ppdu_type; 1071 bool icv_err; 1072 bool crc32_err; 1073 bool hw_dec; 1074 bool sw_dec; 1075 bool addr1_match; 1076 u8 frag; 1077 u16 seq; 1078 u8 frame_type; 1079 u8 rx_pl_id; 1080 bool addr_cam_valid; 1081 u8 addr_cam_id; 1082 u8 sec_cam_id; 1083 u8 mac_id; 1084 u16 offset; 1085 u16 rxd_len; 1086 bool ready; 1087 u16 rssi; 1088 }; 1089 1090 struct rtw89_rxdesc_short { 1091 __le32 dword0; 1092 __le32 dword1; 1093 __le32 dword2; 1094 __le32 dword3; 1095 } __packed; 1096 1097 struct rtw89_rxdesc_short_v2 { 1098 __le32 dword0; 1099 __le32 dword1; 1100 __le32 dword2; 1101 __le32 dword3; 1102 __le32 dword4; 1103 __le32 dword5; 1104 } __packed; 1105 1106 struct rtw89_rxdesc_long { 1107 __le32 dword0; 1108 __le32 dword1; 1109 __le32 dword2; 1110 __le32 dword3; 1111 __le32 dword4; 1112 __le32 dword5; 1113 __le32 dword6; 1114 __le32 dword7; 1115 } __packed; 1116 1117 struct rtw89_rxdesc_long_v2 { 1118 __le32 dword0; 1119 __le32 dword1; 1120 __le32 dword2; 1121 __le32 dword3; 1122 __le32 dword4; 1123 __le32 dword5; 1124 __le32 dword6; 1125 __le32 dword7; 1126 __le32 dword8; 1127 __le32 dword9; 1128 } __packed; 1129 1130 struct rtw89_rxdesc_phy_rpt_v2 { 1131 __le32 dword0; 1132 __le32 dword1; 1133 } __packed; 1134 1135 struct rtw89_tx_desc_info { 1136 u16 pkt_size; 1137 u8 wp_offset; 1138 u8 mac_id; 1139 u8 qsel; 1140 u8 ch_dma; 1141 u8 hdr_llc_len; 1142 bool is_bmc; 1143 bool en_wd_info; 1144 bool wd_page; 1145 bool use_rate; 1146 bool dis_data_fb; 1147 bool tid_indicate; 1148 bool agg_en; 1149 bool bk; 1150 u8 ampdu_density; 1151 u8 ampdu_num; 1152 bool sec_en; 1153 u8 addr_info_nr; 1154 u8 sec_keyid; 1155 u8 sec_type; 1156 u8 sec_cam_idx; 1157 u8 sec_seq[6]; 1158 u16 data_rate; 1159 u16 data_retry_lowest_rate; 1160 bool fw_dl; 1161 u16 seq; 1162 bool a_ctrl_bsr; 1163 u8 hw_ssn_sel; 1164 #define RTW89_MGMT_HW_SSN_SEL 1 1165 u8 hw_seq_mode; 1166 #define RTW89_MGMT_HW_SEQ_MODE 1 1167 bool hiq; 1168 u8 port; 1169 bool er_cap; 1170 bool stbc; 1171 bool ldpc; 1172 bool upd_wlan_hdr; 1173 bool mlo; 1174 }; 1175 1176 struct rtw89_core_tx_request { 1177 enum rtw89_core_tx_type tx_type; 1178 1179 struct sk_buff *skb; 1180 struct ieee80211_vif *vif; 1181 struct ieee80211_sta *sta; 1182 struct rtw89_vif_link *rtwvif_link; 1183 struct rtw89_sta_link *rtwsta_link; 1184 struct rtw89_tx_desc_info desc_info; 1185 }; 1186 1187 struct rtw89_txq { 1188 struct list_head list; 1189 unsigned long flags; 1190 int wait_cnt; 1191 }; 1192 1193 struct rtw89_mac_ax_gnt { 1194 u8 gnt_bt_sw_en; 1195 u8 gnt_bt; 1196 u8 gnt_wl_sw_en; 1197 u8 gnt_wl; 1198 } __packed; 1199 1200 struct rtw89_mac_ax_wl_act { 1201 u8 wlan_act_en; 1202 u8 wlan_act; 1203 }; 1204 1205 #define RTW89_MAC_AX_COEX_GNT_NR 2 1206 struct rtw89_mac_ax_coex_gnt { 1207 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1208 struct rtw89_mac_ax_wl_act bt[RTW89_MAC_AX_COEX_GNT_NR]; 1209 }; 1210 1211 enum rtw89_btc_ncnt { 1212 BTC_NCNT_POWER_ON = 0x0, 1213 BTC_NCNT_POWER_OFF, 1214 BTC_NCNT_INIT_COEX, 1215 BTC_NCNT_SCAN_START, 1216 BTC_NCNT_SCAN_FINISH, 1217 BTC_NCNT_SPECIAL_PACKET, 1218 BTC_NCNT_SWITCH_BAND, 1219 BTC_NCNT_RFK_TIMEOUT, 1220 BTC_NCNT_SHOW_COEX_INFO, 1221 BTC_NCNT_ROLE_INFO, 1222 BTC_NCNT_CONTROL, 1223 BTC_NCNT_RADIO_STATE, 1224 BTC_NCNT_CUSTOMERIZE, 1225 BTC_NCNT_WL_RFK, 1226 BTC_NCNT_WL_STA, 1227 BTC_NCNT_WL_STA_LAST, 1228 BTC_NCNT_FWINFO, 1229 BTC_NCNT_TIMER, 1230 BTC_NCNT_SWITCH_CHBW, 1231 BTC_NCNT_RESUME_DL_FW, 1232 BTC_NCNT_COUNTRYCODE, 1233 BTC_NCNT_NUM, 1234 }; 1235 1236 enum rtw89_btc_btinfo { 1237 BTC_BTINFO_L0 = 0, 1238 BTC_BTINFO_L1, 1239 BTC_BTINFO_L2, 1240 BTC_BTINFO_L3, 1241 BTC_BTINFO_H0, 1242 BTC_BTINFO_H1, 1243 BTC_BTINFO_H2, 1244 BTC_BTINFO_H3, 1245 BTC_BTINFO_MAX 1246 }; 1247 1248 enum rtw89_btc_dcnt { 1249 BTC_DCNT_RUN = 0x0, 1250 BTC_DCNT_CX_RUNINFO, 1251 BTC_DCNT_RPT, 1252 BTC_DCNT_RPT_HANG, 1253 BTC_DCNT_CYCLE, 1254 BTC_DCNT_CYCLE_HANG, 1255 BTC_DCNT_W1, 1256 BTC_DCNT_W1_HANG, 1257 BTC_DCNT_B1, 1258 BTC_DCNT_B1_HANG, 1259 BTC_DCNT_TDMA_NONSYNC, 1260 BTC_DCNT_SLOT_NONSYNC, 1261 BTC_DCNT_BTCNT_HANG, 1262 BTC_DCNT_BTTX_HANG, 1263 BTC_DCNT_WL_SLOT_DRIFT, 1264 BTC_DCNT_WL_STA_LAST, 1265 BTC_DCNT_BT_SLOT_DRIFT, 1266 BTC_DCNT_BT_SLOT_FLOOD, 1267 BTC_DCNT_FDDT_TRIG, 1268 BTC_DCNT_E2G, 1269 BTC_DCNT_E2G_HANG, 1270 BTC_DCNT_WL_FW_VER_MATCH, 1271 BTC_DCNT_NULL_TX_FAIL, 1272 BTC_DCNT_WL_STA_NTFY, 1273 BTC_DCNT_NUM, 1274 }; 1275 1276 enum rtw89_btc_wl_state_cnt { 1277 BTC_WCNT_SCANAP = 0x0, 1278 BTC_WCNT_DHCP, 1279 BTC_WCNT_EAPOL, 1280 BTC_WCNT_ARP, 1281 BTC_WCNT_SCBDUPDATE, 1282 BTC_WCNT_RFK_REQ, 1283 BTC_WCNT_RFK_GO, 1284 BTC_WCNT_RFK_REJECT, 1285 BTC_WCNT_RFK_TIMEOUT, 1286 BTC_WCNT_CH_UPDATE, 1287 BTC_WCNT_DBCC_ALL_2G, 1288 BTC_WCNT_DBCC_CHG, 1289 BTC_WCNT_RX_OK_LAST, 1290 BTC_WCNT_RX_OK_LAST2S, 1291 BTC_WCNT_RX_ERR_LAST, 1292 BTC_WCNT_RX_ERR_LAST2S, 1293 BTC_WCNT_RX_LAST, 1294 BTC_WCNT_NUM 1295 }; 1296 1297 enum rtw89_btc_bt_state_cnt { 1298 BTC_BCNT_RETRY = 0x0, 1299 BTC_BCNT_REINIT, 1300 BTC_BCNT_REENABLE, 1301 BTC_BCNT_SCBDREAD, 1302 BTC_BCNT_RELINK, 1303 BTC_BCNT_IGNOWL, 1304 BTC_BCNT_INQPAG, 1305 BTC_BCNT_INQ, 1306 BTC_BCNT_PAGE, 1307 BTC_BCNT_ROLESW, 1308 BTC_BCNT_AFH, 1309 BTC_BCNT_INFOUPDATE, 1310 BTC_BCNT_INFOSAME, 1311 BTC_BCNT_SCBDUPDATE, 1312 BTC_BCNT_HIPRI_TX, 1313 BTC_BCNT_HIPRI_RX, 1314 BTC_BCNT_LOPRI_TX, 1315 BTC_BCNT_LOPRI_RX, 1316 BTC_BCNT_POLUT, 1317 BTC_BCNT_POLUT_NOW, 1318 BTC_BCNT_POLUT_DIFF, 1319 BTC_BCNT_RATECHG, 1320 BTC_BCNT_NUM, 1321 }; 1322 1323 enum rtw89_btc_bt_profile { 1324 BTC_BT_NOPROFILE = 0, 1325 BTC_BT_HFP = BIT(0), 1326 BTC_BT_HID = BIT(1), 1327 BTC_BT_A2DP = BIT(2), 1328 BTC_BT_PAN = BIT(3), 1329 BTC_PROFILE_MAX = 4, 1330 }; 1331 1332 struct rtw89_btc_ant_info { 1333 u8 type; /* shared, dedicated */ 1334 u8 num; 1335 u8 isolation; 1336 1337 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1338 u8 diversity: 1; 1339 u8 btg_pos: 2; 1340 u8 stream_cnt: 4; 1341 }; 1342 1343 struct rtw89_btc_ant_info_v7 { 1344 u8 type; /* shared, dedicated(non-shared) */ 1345 u8 num; /* antenna count */ 1346 u8 isolation; 1347 u8 single_pos;/* wifi 1ss-1ant at 0:S0 or 1:S1 */ 1348 1349 u8 diversity; /* only for wifi use 1-antenna */ 1350 u8 btg_pos; /* btg-circuit at 0:S0/1:S1/others:all */ 1351 u8 stream_cnt; /* spatial_stream count */ 1352 u8 rsvd; 1353 } __packed; 1354 1355 enum rtw89_tfc_dir { 1356 RTW89_TFC_UL, 1357 RTW89_TFC_DL, 1358 }; 1359 1360 struct rtw89_btc_wl_smap { 1361 u32 busy: 1; 1362 u32 scan: 1; 1363 u32 connecting: 1; 1364 u32 roaming: 1; 1365 u32 dbccing: 1; 1366 u32 _4way: 1; 1367 u32 rf_off: 1; 1368 u32 lps: 2; 1369 u32 ips: 1; 1370 u32 init_ok: 1; 1371 u32 traffic_dir : 2; 1372 u32 rf_off_pre: 1; 1373 u32 lps_pre: 2; 1374 u32 lps_exiting: 1; 1375 u32 emlsr: 1; 1376 }; 1377 1378 enum rtw89_tfc_lv { 1379 RTW89_TFC_IDLE, 1380 RTW89_TFC_ULTRA_LOW, 1381 RTW89_TFC_LOW, 1382 RTW89_TFC_MID, 1383 RTW89_TFC_HIGH, 1384 }; 1385 1386 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1387 DECLARE_EWMA(tp, 10, 2); 1388 1389 struct rtw89_traffic_stats { 1390 /* units in bytes */ 1391 u64 tx_unicast; 1392 u64 rx_unicast; 1393 u32 tx_avg_len; 1394 u32 rx_avg_len; 1395 1396 /* count for packets */ 1397 u64 tx_cnt; 1398 u64 rx_cnt; 1399 1400 /* units in Mbps */ 1401 u32 tx_throughput; 1402 u32 rx_throughput; 1403 u32 tx_throughput_raw; 1404 u32 rx_throughput_raw; 1405 1406 u32 rx_tf_acc; 1407 u32 rx_tf_periodic; 1408 1409 enum rtw89_tfc_lv tx_tfc_lv; 1410 enum rtw89_tfc_lv rx_tfc_lv; 1411 struct ewma_tp tx_ewma_tp; 1412 struct ewma_tp rx_ewma_tp; 1413 1414 u16 tx_rate; 1415 u16 rx_rate; 1416 }; 1417 1418 struct rtw89_btc_chdef { 1419 u8 center_ch; 1420 u8 band; 1421 u8 chan; 1422 enum rtw89_sc_offset offset; 1423 enum rtw89_bandwidth bw; 1424 }; 1425 1426 struct rtw89_btc_statistic { 1427 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1428 struct rtw89_traffic_stats traffic; 1429 }; 1430 1431 #define BTC_WL_RSSI_THMAX 4 1432 1433 struct rtw89_btc_wl_link_info { 1434 struct rtw89_btc_chdef chdef; 1435 struct rtw89_btc_statistic stat; 1436 enum rtw89_tfc_dir dir; 1437 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1438 u8 mac_addr[ETH_ALEN]; 1439 u8 busy; 1440 u8 ch; 1441 u8 bw; 1442 u8 band; 1443 u8 role; 1444 u8 pid; 1445 u8 phy; 1446 u8 dtim_period; 1447 u8 mode; 1448 u8 tx_1ss_limit; 1449 1450 u8 mac_id; 1451 u8 tx_retry; 1452 1453 u32 bcn_period; 1454 u32 busy_t; 1455 u32 tx_time; 1456 u32 client_cnt; 1457 u32 rx_rate_drop_cnt; 1458 u32 noa_duration; 1459 1460 u32 active: 1; 1461 u32 noa: 1; 1462 u32 client_ps: 1; 1463 u32 connected: 2; 1464 }; 1465 1466 union rtw89_btc_wl_state_map { 1467 u32 val; 1468 struct rtw89_btc_wl_smap map; 1469 }; 1470 1471 struct rtw89_btc_bt_hfp_desc { 1472 u32 exist: 1; 1473 u32 type: 2; 1474 u32 rsvd: 29; 1475 }; 1476 1477 struct rtw89_btc_bt_hid_desc { 1478 u32 exist: 1; 1479 u32 slot_info: 2; 1480 u32 pair_cnt: 2; 1481 u32 type: 8; 1482 u32 rsvd: 19; 1483 }; 1484 1485 struct rtw89_btc_bt_a2dp_desc { 1486 u8 exist: 1; 1487 u8 exist_last: 1; 1488 u8 play_latency: 1; 1489 u8 type: 3; 1490 u8 active: 1; 1491 u8 sink: 1; 1492 u32 handle_update: 1; 1493 u32 devinfo_query: 1; 1494 u32 no_empty_streak_2s: 8; 1495 u32 no_empty_streak_max: 8; 1496 u32 rsvd: 6; 1497 1498 u8 bitpool; 1499 u16 vendor_id; 1500 u32 device_name; 1501 u32 flush_time; 1502 }; 1503 1504 struct rtw89_btc_bt_pan_desc { 1505 u32 exist: 1; 1506 u32 type: 1; 1507 u32 active: 1; 1508 u32 rsvd: 29; 1509 }; 1510 1511 struct rtw89_btc_bt_rfk_info { 1512 u32 run: 1; 1513 u32 req: 1; 1514 u32 timeout: 1; 1515 u32 rsvd: 29; 1516 }; 1517 1518 union rtw89_btc_bt_rfk_info_map { 1519 u32 val; 1520 struct rtw89_btc_bt_rfk_info map; 1521 }; 1522 1523 struct rtw89_btc_bt_ver_info { 1524 u32 fw_coex; /* match with which coex_ver */ 1525 u32 fw; 1526 }; 1527 1528 struct rtw89_btc_bool_sta_chg { 1529 u32 now: 1; 1530 u32 last: 1; 1531 u32 remain: 1; 1532 u32 srvd: 29; 1533 }; 1534 1535 struct rtw89_btc_u8_sta_chg { 1536 u8 now; 1537 u8 last; 1538 u8 remain; 1539 u8 rsvd; 1540 }; 1541 1542 struct rtw89_btc_wl_scan_info { 1543 u8 band[RTW89_PHY_MAX]; 1544 u8 phy_map; 1545 u8 rsvd; 1546 }; 1547 1548 struct rtw89_btc_wl_dbcc_info { 1549 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1550 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1551 u8 real_band[RTW89_PHY_MAX]; 1552 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1553 }; 1554 1555 struct rtw89_btc_wl_active_role { 1556 u8 connected: 1; 1557 u8 pid: 3; 1558 u8 phy: 1; 1559 u8 noa: 1; 1560 u8 band: 2; 1561 1562 u8 client_ps: 1; 1563 u8 bw: 7; 1564 1565 u8 role; 1566 u8 ch; 1567 1568 u16 tx_lvl; 1569 u16 rx_lvl; 1570 u16 tx_rate; 1571 u16 rx_rate; 1572 }; 1573 1574 struct rtw89_btc_wl_active_role_v1 { 1575 u8 connected: 1; 1576 u8 pid: 3; 1577 u8 phy: 1; 1578 u8 noa: 1; 1579 u8 band: 2; 1580 1581 u8 client_ps: 1; 1582 u8 bw: 7; 1583 1584 u8 role; 1585 u8 ch; 1586 1587 u16 tx_lvl; 1588 u16 rx_lvl; 1589 u16 tx_rate; 1590 u16 rx_rate; 1591 1592 u32 noa_duration; /* ms */ 1593 }; 1594 1595 struct rtw89_btc_wl_active_role_v2 { 1596 u8 connected: 1; 1597 u8 pid: 3; 1598 u8 phy: 1; 1599 u8 noa: 1; 1600 u8 band: 2; 1601 1602 u8 client_ps: 1; 1603 u8 bw: 7; 1604 1605 u8 role; 1606 u8 ch; 1607 1608 u32 noa_duration; /* ms */ 1609 }; 1610 1611 struct rtw89_btc_wl_active_role_v7 { 1612 u8 connected; 1613 u8 pid; 1614 u8 phy; 1615 u8 noa; 1616 1617 u8 band; 1618 u8 client_ps; 1619 u8 bw; 1620 u8 role; 1621 1622 u8 ch; 1623 u8 noa_dur; 1624 u8 client_cnt; 1625 u8 rsvd2; 1626 } __packed; 1627 1628 struct rtw89_btc_wl_role_info_bpos { 1629 u16 none: 1; 1630 u16 station: 1; 1631 u16 ap: 1; 1632 u16 vap: 1; 1633 u16 adhoc: 1; 1634 u16 adhoc_master: 1; 1635 u16 mesh: 1; 1636 u16 moniter: 1; 1637 u16 p2p_device: 1; 1638 u16 p2p_gc: 1; 1639 u16 p2p_go: 1; 1640 u16 nan: 1; 1641 }; 1642 1643 struct rtw89_btc_wl_scc_ctrl { 1644 u8 null_role1; 1645 u8 null_role2; 1646 u8 ebt_null; /* if tx null at EBT slot */ 1647 }; 1648 1649 union rtw89_btc_wl_role_info_map { 1650 u16 val; 1651 struct rtw89_btc_wl_role_info_bpos role; 1652 }; 1653 1654 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1655 u8 connect_cnt; 1656 u8 link_mode; 1657 union rtw89_btc_wl_role_info_map role_map; 1658 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1659 }; 1660 1661 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1662 u8 connect_cnt; 1663 u8 link_mode; 1664 union rtw89_btc_wl_role_info_map role_map; 1665 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1666 u32 mrole_type; /* btc_wl_mrole_type */ 1667 u32 mrole_noa_duration; /* ms */ 1668 1669 u32 dbcc_en: 1; 1670 u32 dbcc_chg: 1; 1671 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1672 u32 link_mode_chg: 1; 1673 u32 rsvd: 27; 1674 }; 1675 1676 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1677 u8 connect_cnt; 1678 u8 link_mode; 1679 union rtw89_btc_wl_role_info_map role_map; 1680 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1681 u32 mrole_type; /* btc_wl_mrole_type */ 1682 u32 mrole_noa_duration; /* ms */ 1683 1684 u32 dbcc_en: 1; 1685 u32 dbcc_chg: 1; 1686 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1687 u32 link_mode_chg: 1; 1688 u32 rsvd: 27; 1689 }; 1690 1691 struct rtw89_btc_wl_rlink { /* H2C info, struct size must be n*4 bytes */ 1692 u8 connected; 1693 u8 pid; 1694 u8 phy; 1695 u8 noa; 1696 1697 u8 rf_band; /* enum band_type RF band: 2.4G/5G/6G */ 1698 u8 active; /* 0:rlink is under doze */ 1699 u8 bw; /* enum channel_width */ 1700 u8 role; /*enum role_type */ 1701 1702 u8 ch; 1703 u8 noa_dur; /* ms */ 1704 u8 client_cnt; /* for Role = P2P-Go/AP */ 1705 u8 mode; /* wifi protocol */ 1706 } __packed; 1707 1708 #define RTW89_BE_BTC_WL_MAX_ROLE_NUMBER 6 1709 struct rtw89_btc_wl_role_info_v7 { /* struct size must be n*4 bytes */ 1710 u8 connect_cnt; 1711 u8 link_mode; 1712 u8 link_mode_chg; 1713 u8 p2p_2g; 1714 1715 struct rtw89_btc_wl_active_role_v7 active_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 1716 1717 u32 role_map; 1718 u32 mrole_type; /* btc_wl_mrole_type */ 1719 u32 mrole_noa_duration; /* ms */ 1720 u32 dbcc_en; 1721 u32 dbcc_chg; 1722 u32 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1723 } __packed; 1724 1725 struct rtw89_btc_wl_role_info_v8 { /* H2C info, struct size must be n*4 bytes */ 1726 u8 connect_cnt; 1727 u8 link_mode; 1728 u8 link_mode_chg; 1729 u8 p2p_2g; 1730 1731 u8 pta_req_band; 1732 u8 dbcc_en; /* 1+1 and 2.4G-included */ 1733 u8 dbcc_chg; 1734 u8 dbcc_2g_phy; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1735 1736 struct rtw89_btc_wl_rlink rlink[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1737 1738 u32 role_map; 1739 u32 mrole_type; /* btc_wl_mrole_type */ 1740 u32 mrole_noa_duration; /* ms */ 1741 } __packed; 1742 1743 struct rtw89_btc_wl_ver_info { 1744 u32 fw_coex; /* match with which coex_ver */ 1745 u32 fw; 1746 u32 mac; 1747 u32 bb; 1748 u32 rf; 1749 }; 1750 1751 struct rtw89_btc_wl_afh_info { 1752 u8 en; 1753 u8 ch; 1754 u8 bw; 1755 u8 rsvd; 1756 } __packed; 1757 1758 struct rtw89_btc_wl_rfk_info { 1759 u32 state: 2; 1760 u32 path_map: 4; 1761 u32 phy_map: 2; 1762 u32 band: 2; 1763 u32 type: 8; 1764 u32 rsvd: 14; 1765 1766 u32 start_time; 1767 u32 proc_time; 1768 }; 1769 1770 struct rtw89_btc_bt_smap { 1771 u32 connect: 1; 1772 u32 ble_connect: 1; 1773 u32 acl_busy: 1; 1774 u32 sco_busy: 1; 1775 u32 mesh_busy: 1; 1776 u32 inq_pag: 1; 1777 }; 1778 1779 union rtw89_btc_bt_state_map { 1780 u32 val; 1781 struct rtw89_btc_bt_smap map; 1782 }; 1783 1784 #define BTC_BT_RSSI_THMAX 4 1785 #define BTC_BT_AFH_GROUP 12 1786 #define BTC_BT_AFH_LE_GROUP 5 1787 1788 struct rtw89_btc_bt_link_info { 1789 struct rtw89_btc_u8_sta_chg profile_cnt; 1790 struct rtw89_btc_bool_sta_chg multi_link; 1791 struct rtw89_btc_bool_sta_chg relink; 1792 struct rtw89_btc_bt_hfp_desc hfp_desc; 1793 struct rtw89_btc_bt_hid_desc hid_desc; 1794 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1795 struct rtw89_btc_bt_pan_desc pan_desc; 1796 union rtw89_btc_bt_state_map status; 1797 1798 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1799 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1800 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1801 u8 afh_map[BTC_BT_AFH_GROUP]; 1802 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1803 1804 u32 role_sw: 1; 1805 u32 slave_role: 1; 1806 u32 afh_update: 1; 1807 u32 cqddr: 1; 1808 u32 rssi: 8; 1809 u32 tx_3m: 1; 1810 u32 rsvd: 19; 1811 }; 1812 1813 struct rtw89_btc_3rdcx_info { 1814 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1815 u8 hw_coex; 1816 u16 rsvd; 1817 }; 1818 1819 struct rtw89_btc_dm_emap { 1820 u32 init: 1; 1821 u32 pta_owner: 1; 1822 u32 wl_rfk_timeout: 1; 1823 u32 bt_rfk_timeout: 1; 1824 u32 wl_fw_hang: 1; 1825 u32 cycle_hang: 1; 1826 u32 w1_hang: 1; 1827 u32 b1_hang: 1; 1828 u32 tdma_no_sync: 1; 1829 u32 slot_no_sync: 1; 1830 u32 wl_slot_drift: 1; 1831 u32 bt_slot_drift: 1; 1832 u32 role_num_mismatch: 1; 1833 u32 null1_tx_late: 1; 1834 u32 bt_afh_conflict: 1; 1835 u32 bt_leafh_conflict: 1; 1836 u32 bt_slot_flood: 1; 1837 u32 wl_e2g_hang: 1; 1838 u32 wl_ver_mismatch: 1; 1839 u32 bt_ver_mismatch: 1; 1840 u32 rfe_type0: 1; 1841 u32 h2c_buffer_over: 1; 1842 u32 bt_tx_hang: 1; /* for SNR too low bug, BT has no Tx req*/ 1843 u32 wl_no_sta_ntfy: 1; 1844 1845 u32 h2c_bmap_mismatch: 1; 1846 u32 c2h_bmap_mismatch: 1; 1847 u32 h2c_struct_invalid: 1; 1848 u32 c2h_struct_invalid: 1; 1849 u32 h2c_c2h_buffer_mismatch: 1; 1850 }; 1851 1852 union rtw89_btc_dm_error_map { 1853 u32 val; 1854 struct rtw89_btc_dm_emap map; 1855 }; 1856 1857 struct rtw89_btc_rf_para { 1858 u32 tx_pwr_freerun; 1859 u32 rx_gain_freerun; 1860 u32 tx_pwr_perpkt; 1861 u32 rx_gain_perpkt; 1862 }; 1863 1864 struct rtw89_btc_wl_nhm { 1865 u8 instant_wl_nhm_dbm; 1866 u8 instant_wl_nhm_per_mhz; 1867 u16 valid_record_times; 1868 s8 record_pwr[16]; 1869 u8 record_ratio[16]; 1870 s8 pwr; /* dbm_per_MHz */ 1871 u8 ratio; 1872 u8 current_status; 1873 u8 refresh; 1874 bool start_flag; 1875 s8 pwr_max; 1876 s8 pwr_min; 1877 }; 1878 1879 struct rtw89_btc_wl_info { 1880 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1881 struct rtw89_btc_wl_link_info rlink_info[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER][RTW89_MAC_NUM]; 1882 struct rtw89_btc_wl_rfk_info rfk_info; 1883 struct rtw89_btc_wl_ver_info ver_info; 1884 struct rtw89_btc_wl_afh_info afh_info; 1885 struct rtw89_btc_wl_role_info role_info; 1886 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1887 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1888 struct rtw89_btc_wl_role_info_v7 role_info_v7; 1889 struct rtw89_btc_wl_role_info_v8 role_info_v8; 1890 struct rtw89_btc_wl_scan_info scan_info; 1891 struct rtw89_btc_wl_dbcc_info dbcc_info; 1892 struct rtw89_btc_rf_para rf_para; 1893 struct rtw89_btc_wl_nhm nhm; 1894 union rtw89_btc_wl_state_map status; 1895 1896 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1897 u8 rssi_level; 1898 u8 cn_report; 1899 u8 coex_mode; 1900 u8 pta_req_mac; 1901 u8 bt_polut_type[RTW89_PHY_MAX]; /* BT polluted WL-Tx type for phy0/1 */ 1902 1903 bool is_5g_hi_channel; 1904 bool pta_reg_mac_chg; 1905 bool bg_mode; 1906 bool he_mode; 1907 bool scbd_change; 1908 bool fw_ver_mismatch; 1909 bool client_cnt_inc_2g; 1910 u32 scbd; 1911 }; 1912 1913 struct rtw89_btc_module { 1914 struct rtw89_btc_ant_info ant; 1915 u8 rfe_type; 1916 u8 cv; 1917 1918 u8 bt_solo: 1; 1919 u8 bt_pos: 1; 1920 u8 switch_type: 1; 1921 u8 wa_type: 3; 1922 1923 u8 kt_ver_adie; 1924 }; 1925 1926 struct rtw89_btc_module_v7 { 1927 u8 rfe_type; 1928 u8 kt_ver; 1929 u8 bt_solo; 1930 u8 bt_pos; /* wl-end view: get from efuse, must compare bt.btg_type*/ 1931 1932 u8 switch_type; /* WL/BT switch type: 0: internal, 1: external */ 1933 u8 wa_type; /* WA type: 0:none, 1: 51B 5G_Hi-Ch_Rx */ 1934 u8 kt_ver_adie; 1935 u8 rsvd; 1936 1937 struct rtw89_btc_ant_info_v7 ant; 1938 } __packed; 1939 1940 union rtw89_btc_module_info { 1941 struct rtw89_btc_module md; 1942 struct rtw89_btc_module_v7 md_v7; 1943 }; 1944 1945 #define RTW89_BTC_DM_MAXSTEP 30 1946 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1947 1948 struct rtw89_btc_dm_step { 1949 u16 step[RTW89_BTC_DM_MAXSTEP]; 1950 u8 step_pos; 1951 bool step_ov; 1952 }; 1953 1954 struct rtw89_btc_init_info { 1955 struct rtw89_btc_module module; 1956 u8 wl_guard_ch; 1957 1958 u8 wl_only: 1; 1959 u8 wl_init_ok: 1; 1960 u8 dbcc_en: 1; 1961 u8 cx_other: 1; 1962 u8 bt_only: 1; 1963 1964 u16 rsvd; 1965 }; 1966 1967 struct rtw89_btc_init_info_v7 { 1968 u8 wl_guard_ch; 1969 u8 wl_only; 1970 u8 wl_init_ok; 1971 u8 rsvd3; 1972 1973 u8 cx_other; 1974 u8 bt_only; 1975 u8 pta_mode; 1976 u8 pta_direction; 1977 1978 struct rtw89_btc_module_v7 module; 1979 } __packed; 1980 1981 union rtw89_btc_init_info_u { 1982 struct rtw89_btc_init_info init; 1983 struct rtw89_btc_init_info_v7 init_v7; 1984 }; 1985 1986 struct rtw89_btc_wl_tx_limit_para { 1987 u16 enable; 1988 u32 tx_time; /* unit: us */ 1989 u16 tx_retry; 1990 }; 1991 1992 enum rtw89_btc_bt_scan_type { 1993 BTC_SCAN_INQ = 0, 1994 BTC_SCAN_PAGE, 1995 BTC_SCAN_BLE, 1996 BTC_SCAN_INIT, 1997 BTC_SCAN_TV, 1998 BTC_SCAN_ADV, 1999 BTC_SCAN_MAX1, 2000 }; 2001 2002 enum rtw89_btc_ble_scan_type { 2003 CXSCAN_BG = 0, 2004 CXSCAN_INIT, 2005 CXSCAN_LE, 2006 CXSCAN_MAX 2007 }; 2008 2009 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 2010 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 2011 2012 struct rtw89_btc_bt_scan_info_v1 { 2013 __le16 win; 2014 __le16 intvl; 2015 __le32 flags; 2016 } __packed; 2017 2018 struct rtw89_btc_bt_scan_info_v2 { 2019 __le16 win; 2020 __le16 intvl; 2021 } __packed; 2022 2023 struct rtw89_btc_fbtc_btscan_v1 { 2024 u8 fver; /* btc_ver::fcxbtscan */ 2025 u8 rsvd; 2026 __le16 rsvd2; 2027 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 2028 } __packed; 2029 2030 struct rtw89_btc_fbtc_btscan_v2 { 2031 u8 fver; /* btc_ver::fcxbtscan */ 2032 u8 type; 2033 __le16 rsvd2; 2034 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2035 } __packed; 2036 2037 struct rtw89_btc_fbtc_btscan_v7 { 2038 u8 fver; /* btc_ver::fcxbtscan */ 2039 u8 type; 2040 u8 rsvd0; 2041 u8 rsvd1; 2042 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 2043 } __packed; 2044 2045 union rtw89_btc_fbtc_btscan { 2046 struct rtw89_btc_fbtc_btscan_v1 v1; 2047 struct rtw89_btc_fbtc_btscan_v2 v2; 2048 struct rtw89_btc_fbtc_btscan_v7 v7; 2049 }; 2050 2051 struct rtw89_btc_bt_info { 2052 struct rtw89_btc_bt_link_info link_info; 2053 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 2054 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 2055 struct rtw89_btc_bt_ver_info ver_info; 2056 struct rtw89_btc_bool_sta_chg enable; 2057 struct rtw89_btc_bool_sta_chg inq_pag; 2058 struct rtw89_btc_rf_para rf_para; 2059 union rtw89_btc_bt_rfk_info_map rfk_info; 2060 2061 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 2062 u8 rssi_level; 2063 2064 u32 scbd; 2065 u32 feature; 2066 2067 u32 mbx_avl: 1; 2068 u32 whql_test: 1; 2069 u32 igno_wl: 1; 2070 u32 reinit: 1; 2071 u32 ble_scan_en: 1; 2072 u32 btg_type: 1; 2073 u32 inq: 1; 2074 u32 pag: 1; 2075 u32 run_patch_code: 1; 2076 u32 hi_lna_rx: 1; 2077 u32 scan_rx_low_pri: 1; 2078 u32 scan_info_update: 1; 2079 u32 lna_constrain: 3; 2080 u32 rsvd: 17; 2081 }; 2082 2083 struct rtw89_btc_cx { 2084 struct rtw89_btc_wl_info wl; 2085 struct rtw89_btc_bt_info bt; 2086 struct rtw89_btc_3rdcx_info other; 2087 u32 state_map; 2088 u32 cnt_bt[BTC_BCNT_NUM]; 2089 u32 cnt_wl[BTC_WCNT_NUM]; 2090 }; 2091 2092 struct rtw89_btc_fbtc_tdma { 2093 u8 type; /* btc_ver::fcxtdma */ 2094 u8 rxflctrl; 2095 u8 txpause; 2096 u8 wtgle_n; 2097 u8 leak_n; 2098 u8 ext_ctrl; 2099 u8 rxflctrl_role; 2100 u8 option_ctrl; 2101 } __packed; 2102 2103 struct rtw89_btc_fbtc_tdma_v3 { 2104 u8 fver; /* btc_ver::fcxtdma */ 2105 u8 rsvd; 2106 __le16 rsvd1; 2107 struct rtw89_btc_fbtc_tdma tdma; 2108 } __packed; 2109 2110 union rtw89_btc_fbtc_tdma_le32 { 2111 struct rtw89_btc_fbtc_tdma v1; 2112 struct rtw89_btc_fbtc_tdma_v3 v3; 2113 }; 2114 2115 #define CXMREG_MAX 30 2116 #define CXMREG_MAX_V2 20 2117 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 2118 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 2119 2120 enum rtw89_btc_bt_sta_counter { 2121 BTC_BCNT_RFK_REQ = 0, 2122 BTC_BCNT_RFK_GO = 1, 2123 BTC_BCNT_RFK_REJECT = 2, 2124 BTC_BCNT_RFK_FAIL = 3, 2125 BTC_BCNT_RFK_TIMEOUT = 4, 2126 BTC_BCNT_HI_TX = 5, 2127 BTC_BCNT_HI_RX = 6, 2128 BTC_BCNT_LO_TX = 7, 2129 BTC_BCNT_LO_RX = 8, 2130 BTC_BCNT_POLLUTED = 9, 2131 BTC_BCNT_STA_MAX 2132 }; 2133 2134 enum rtw89_btc_bt_sta_counter_v105 { 2135 BTC_BCNT_RFK_REQ_V105 = 0, 2136 BTC_BCNT_HI_TX_V105 = 1, 2137 BTC_BCNT_HI_RX_V105 = 2, 2138 BTC_BCNT_LO_TX_V105 = 3, 2139 BTC_BCNT_LO_RX_V105 = 4, 2140 BTC_BCNT_POLLUTED_V105 = 5, 2141 BTC_BCNT_STA_MAX_V105 2142 }; 2143 2144 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 2145 u16 fver; /* btc_ver::fcxbtcrpt */ 2146 u16 rpt_cnt; /* tmr counters */ 2147 u32 wl_fw_coex_ver; /* match which driver's coex version */ 2148 u32 wl_fw_cx_offload; 2149 u32 wl_fw_ver; 2150 u32 rpt_enable; 2151 u32 rpt_para; /* ms */ 2152 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 2153 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 2154 u32 mb_recv_cnt; /* fw recv mailbox counter */ 2155 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 2156 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 2157 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 2158 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 2159 u32 c2h_cnt; /* fw send c2h counter */ 2160 u32 h2c_cnt; /* fw recv h2c counter */ 2161 } __packed; 2162 2163 struct rtw89_btc_fbtc_rpt_ctrl_info { 2164 __le32 cnt; /* fw report counter */ 2165 __le32 en; /* report map */ 2166 __le32 para; /* not used */ 2167 2168 __le32 cnt_c2h; /* fw send c2h counter */ 2169 __le32 cnt_h2c; /* fw recv h2c counter */ 2170 __le32 len_c2h; /* The total length of the last C2H */ 2171 2172 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2173 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2174 } __packed; 2175 2176 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 2177 __le32 cx_ver; /* match which driver's coex version */ 2178 __le32 fw_ver; 2179 __le32 en; /* report map */ 2180 2181 __le16 cnt; /* fw report counter */ 2182 __le16 cnt_c2h; /* fw send c2h counter */ 2183 __le16 cnt_h2c; /* fw recv h2c counter */ 2184 __le16 len_c2h; /* The total length of the last C2H */ 2185 2186 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2187 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2188 } __packed; 2189 2190 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 { 2191 __le16 cnt; /* fw report counter */ 2192 __le16 cnt_c2h; /* fw send c2h counter */ 2193 __le16 cnt_h2c; /* fw recv h2c counter */ 2194 __le16 len_c2h; /* The total length of the last C2H */ 2195 2196 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 2197 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 2198 2199 __le32 cx_ver; /* match which driver's coex version */ 2200 __le32 fw_ver; 2201 __le32 en; /* report map */ 2202 } __packed; 2203 2204 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 2205 __le32 cx_ver; /* match which driver's coex version */ 2206 __le32 cx_offload; 2207 __le32 fw_ver; 2208 } __packed; 2209 2210 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 2211 __le32 cnt_empty; /* a2dp empty count */ 2212 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 2213 __le32 cnt_tx; 2214 __le32 cnt_ack; 2215 __le32 cnt_nack; 2216 } __packed; 2217 2218 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 2219 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 2220 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 2221 __le32 cnt_recv; /* fw recv mailbox counter */ 2222 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 2223 } __packed; 2224 2225 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 2226 u8 fver; 2227 u8 rsvd; 2228 __le16 rsvd1; 2229 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 2230 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 2231 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2232 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 2233 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 2234 } __packed; 2235 2236 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 2237 u8 fver; 2238 u8 rsvd; 2239 __le16 rsvd1; 2240 2241 u8 gnt_val[RTW89_PHY_MAX][4]; 2242 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 2243 2244 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2245 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2246 } __packed; 2247 2248 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 2249 u8 fver; 2250 u8 rsvd; 2251 __le16 rsvd1; 2252 2253 u8 gnt_val[RTW89_PHY_MAX][4]; 2254 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2255 2256 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 2257 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2258 } __packed; 2259 2260 struct rtw89_btc_fbtc_rpt_ctrl_v7 { 2261 u8 fver; 2262 u8 rsvd0; 2263 u8 rsvd1; 2264 u8 rsvd2; 2265 2266 u8 gnt_val[RTW89_PHY_MAX][4]; 2267 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2268 2269 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2270 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2271 } __packed; 2272 2273 struct rtw89_btc_fbtc_rpt_ctrl_v8 { 2274 u8 fver; 2275 u8 rsvd0; 2276 u8 rpt_len_max_l; /* BTC_RPT_MAX bit0~7 */ 2277 u8 rpt_len_max_h; /* BTC_RPT_MAX bit8~15 */ 2278 2279 u8 gnt_val[RTW89_PHY_MAX][4]; 2280 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 2281 2282 struct rtw89_btc_fbtc_rpt_ctrl_info_v8 rpt_info; 2283 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 2284 } __packed; 2285 2286 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 2287 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 2288 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 2289 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 2290 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 2291 struct rtw89_btc_fbtc_rpt_ctrl_v7 v7; 2292 struct rtw89_btc_fbtc_rpt_ctrl_v8 v8; 2293 }; 2294 2295 enum rtw89_fbtc_ext_ctrl_type { 2296 CXECTL_OFF = 0x0, /* tdma off */ 2297 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 2298 CXECTL_EXT = 0x2, 2299 CXECTL_MAX 2300 }; 2301 2302 union rtw89_btc_fbtc_rxflct { 2303 u8 val; 2304 u8 type: 3; 2305 u8 tgln_n: 5; 2306 }; 2307 2308 enum rtw89_btc_cxst_state { 2309 CXST_OFF = 0x0, 2310 CXST_B2W = 0x1, 2311 CXST_W1 = 0x2, 2312 CXST_W2 = 0x3, 2313 CXST_W2B = 0x4, 2314 CXST_B1 = 0x5, 2315 CXST_B2 = 0x6, 2316 CXST_B3 = 0x7, 2317 CXST_B4 = 0x8, 2318 CXST_LK = 0x9, 2319 CXST_BLK = 0xa, 2320 CXST_E2G = 0xb, 2321 CXST_E5G = 0xc, 2322 CXST_EBT = 0xd, 2323 CXST_ENULL = 0xe, 2324 CXST_WLK = 0xf, 2325 CXST_W1FDD = 0x10, 2326 CXST_B1FDD = 0x11, 2327 CXST_MAX = 0x12, 2328 }; 2329 2330 enum rtw89_btc_cxevnt { 2331 CXEVNT_TDMA_ENTRY = 0x0, 2332 CXEVNT_WL_TMR, 2333 CXEVNT_B1_TMR, 2334 CXEVNT_B2_TMR, 2335 CXEVNT_B3_TMR, 2336 CXEVNT_B4_TMR, 2337 CXEVNT_W2B_TMR, 2338 CXEVNT_B2W_TMR, 2339 CXEVNT_BCN_EARLY, 2340 CXEVNT_A2DP_EMPTY, 2341 CXEVNT_LK_END, 2342 CXEVNT_RX_ISR, 2343 CXEVNT_RX_FC0, 2344 CXEVNT_RX_FC1, 2345 CXEVNT_BT_RELINK, 2346 CXEVNT_BT_RETRY, 2347 CXEVNT_E2G, 2348 CXEVNT_E5G, 2349 CXEVNT_EBT, 2350 CXEVNT_ENULL, 2351 CXEVNT_DRV_WLK, 2352 CXEVNT_BCN_OK, 2353 CXEVNT_BT_CHANGE, 2354 CXEVNT_EBT_EXTEND, 2355 CXEVNT_E2G_NULL1, 2356 CXEVNT_B1FDD_TMR, 2357 CXEVNT_MAX 2358 }; 2359 2360 enum { 2361 CXBCN_ALL = 0x0, 2362 CXBCN_ALL_OK, 2363 CXBCN_BT_SLOT, 2364 CXBCN_BT_OK, 2365 CXBCN_MAX 2366 }; 2367 2368 enum btc_slot_type { 2369 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2370 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2371 CXSTYPE_NUM, 2372 }; 2373 2374 enum { /* TIME */ 2375 CXT_BT = 0x0, 2376 CXT_WL = 0x1, 2377 CXT_MAX 2378 }; 2379 2380 enum { /* TIME-A2DP */ 2381 CXT_FLCTRL_OFF = 0x0, 2382 CXT_FLCTRL_ON = 0x1, 2383 CXT_FLCTRL_MAX 2384 }; 2385 2386 enum { /* STEP TYPE */ 2387 CXSTEP_NONE = 0x0, 2388 CXSTEP_EVNT = 0x1, 2389 CXSTEP_SLOT = 0x2, 2390 CXSTEP_MAX, 2391 }; 2392 2393 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2394 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2395 RPT_BT_AFH_SEQ_LE = 0x20 2396 }; 2397 2398 #define BTC_DBG_MAX1 32 2399 struct rtw89_btc_fbtc_gpio_dbg_v1 { 2400 u8 fver; /* btc_ver::fcxgpiodbg */ 2401 u8 rsvd; 2402 __le16 rsvd2; 2403 __le32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2404 __le32 pre_state; /* the debug signal is 1 or 0 */ 2405 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2406 } __packed; 2407 2408 struct rtw89_btc_fbtc_gpio_dbg_v7 { 2409 u8 fver; 2410 u8 rsvd0; 2411 u8 rsvd1; 2412 u8 rsvd2; 2413 2414 u8 gpio_map[BTC_DBG_MAX1]; 2415 2416 __le32 en_map; 2417 __le32 pre_state; 2418 } __packed; 2419 2420 union rtw89_btc_fbtc_gpio_dbg { 2421 struct rtw89_btc_fbtc_gpio_dbg_v1 v1; 2422 struct rtw89_btc_fbtc_gpio_dbg_v7 v7; 2423 }; 2424 2425 struct rtw89_btc_fbtc_mreg_val_v1 { 2426 u8 fver; /* btc_ver::fcxmreg */ 2427 u8 reg_num; 2428 __le16 rsvd; 2429 __le32 mreg_val[CXMREG_MAX]; 2430 } __packed; 2431 2432 struct rtw89_btc_fbtc_mreg_val_v2 { 2433 u8 fver; /* btc_ver::fcxmreg */ 2434 u8 reg_num; 2435 __le16 rsvd; 2436 __le32 mreg_val[CXMREG_MAX_V2]; 2437 } __packed; 2438 2439 struct rtw89_btc_fbtc_mreg_val_v7 { 2440 u8 fver; 2441 u8 reg_num; 2442 u8 rsvd0; 2443 u8 rsvd1; 2444 __le32 mreg_val[CXMREG_MAX_V2]; 2445 } __packed; 2446 2447 union rtw89_btc_fbtc_mreg_val { 2448 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2449 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2450 struct rtw89_btc_fbtc_mreg_val_v7 v7; 2451 }; 2452 2453 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2454 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2455 .offset = cpu_to_le32(__offset), } 2456 2457 struct rtw89_btc_fbtc_mreg { 2458 __le16 type; 2459 __le16 bytes; 2460 __le32 offset; 2461 } __packed; 2462 2463 struct rtw89_btc_fbtc_slot { 2464 __le16 dur; 2465 __le32 cxtbl; 2466 __le16 cxtype; 2467 } __packed; 2468 2469 struct rtw89_btc_fbtc_slots { 2470 u8 fver; /* btc_ver::fcxslots */ 2471 u8 tbl_num; 2472 __le16 rsvd; 2473 __le32 update_map; 2474 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2475 } __packed; 2476 2477 struct rtw89_btc_fbtc_slot_v7 { 2478 __le16 dur; /* slot duration */ 2479 __le16 cxtype; 2480 __le32 cxtbl; 2481 } __packed; 2482 2483 struct rtw89_btc_fbtc_slot_u16 { 2484 __le16 dur; /* slot duration */ 2485 __le16 cxtype; 2486 __le16 cxtbl_l16; /* coex table [15:0] */ 2487 __le16 cxtbl_h16; /* coex table [31:16] */ 2488 } __packed; 2489 2490 struct rtw89_btc_fbtc_1slot_v7 { 2491 u8 fver; 2492 u8 sid; /* slot id */ 2493 __le16 rsvd; 2494 struct rtw89_btc_fbtc_slot_v7 slot; 2495 } __packed; 2496 2497 struct rtw89_btc_fbtc_slots_v7 { 2498 u8 fver; 2499 u8 slot_cnt; 2500 u8 rsvd0; 2501 u8 rsvd1; 2502 struct rtw89_btc_fbtc_slot_u16 slot[CXST_MAX]; 2503 __le32 update_map; 2504 } __packed; 2505 2506 union rtw89_btc_fbtc_slots_info { 2507 struct rtw89_btc_fbtc_slots v1; 2508 struct rtw89_btc_fbtc_slots_v7 v7; 2509 } __packed; 2510 2511 struct rtw89_btc_fbtc_step { 2512 u8 type; 2513 u8 val; 2514 __le16 difft; 2515 } __packed; 2516 2517 struct rtw89_btc_fbtc_steps_v2 { 2518 u8 fver; /* btc_ver::fcxstep */ 2519 u8 rsvd; 2520 __le16 cnt; 2521 __le16 pos_old; 2522 __le16 pos_new; 2523 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2524 } __packed; 2525 2526 struct rtw89_btc_fbtc_steps_v3 { 2527 u8 fver; 2528 u8 en; 2529 __le16 rsvd; 2530 __le32 cnt; 2531 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2532 } __packed; 2533 2534 union rtw89_btc_fbtc_steps_info { 2535 struct rtw89_btc_fbtc_steps_v2 v2; 2536 struct rtw89_btc_fbtc_steps_v3 v3; 2537 }; 2538 2539 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2540 u8 fver; /* btc_ver::fcxcysta */ 2541 u8 rsvd; 2542 __le16 cycles; /* total cycle number */ 2543 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2544 __le16 a2dpept; /* a2dp empty cnt */ 2545 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2546 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2547 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2548 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2549 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2550 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2551 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2552 __le16 tmax_a2dpept; /* max a2dp empty time */ 2553 __le16 tavg_lk; /* avg leak-slot time */ 2554 __le16 tmax_lk; /* max leak-slot time */ 2555 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2556 __le32 bcn_cnt[CXBCN_MAX]; 2557 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2558 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2559 __le32 skip_cnt; 2560 __le32 exception; 2561 __le32 except_cnt; 2562 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2563 } __packed; 2564 2565 struct rtw89_btc_fbtc_fdd_try_info { 2566 __le16 cycles[CXT_FLCTRL_MAX]; 2567 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2568 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2569 } __packed; 2570 2571 struct rtw89_btc_fbtc_cycle_time_info { 2572 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2573 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2574 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2575 } __packed; 2576 2577 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2578 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2579 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2580 } __packed; 2581 2582 struct rtw89_btc_fbtc_a2dp_trx_stat { 2583 u8 empty_cnt; 2584 u8 retry_cnt; 2585 u8 tx_rate; 2586 u8 tx_cnt; 2587 u8 ack_cnt; 2588 u8 nack_cnt; 2589 u8 rsvd1; 2590 u8 rsvd2; 2591 } __packed; 2592 2593 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2594 u8 empty_cnt; 2595 u8 retry_cnt; 2596 u8 tx_rate; 2597 u8 tx_cnt; 2598 u8 ack_cnt; 2599 u8 nack_cnt; 2600 u8 no_empty_cnt; 2601 u8 rsvd; 2602 } __packed; 2603 2604 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2605 __le16 cnt; /* a2dp empty cnt */ 2606 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2607 __le16 tavg; /* avg a2dp empty time */ 2608 __le16 tmax; /* max a2dp empty time */ 2609 } __packed; 2610 2611 struct rtw89_btc_fbtc_cycle_leak_info { 2612 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2613 __le16 tavg; /* avg leak-slot time */ 2614 __le16 tmax; /* max leak-slot time */ 2615 } __packed; 2616 2617 struct rtw89_btc_fbtc_cycle_leak_info_v7 { 2618 __le16 tavg; 2619 __le16 tamx; 2620 __le32 cnt_rximr; 2621 } __packed; 2622 2623 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2624 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2625 2626 struct rtw89_btc_fbtc_cycle_fddt_info { 2627 __le16 train_cycle; 2628 __le16 tp; 2629 2630 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2631 s8 bt_tx_power; /* decrease Tx power (dB) */ 2632 s8 bt_rx_gain; /* LNA constrain level */ 2633 u8 no_empty_cnt; 2634 2635 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2636 u8 cn; /* condition_num */ 2637 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2638 u8 train_result; /* refer to enum btc_fddt_check_map */ 2639 } __packed; 2640 2641 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2642 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2643 2644 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2645 __le16 train_cycle; 2646 __le16 tp; 2647 2648 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2649 s8 bt_tx_power; /* decrease Tx power (dB) */ 2650 s8 bt_rx_gain; /* LNA constrain level */ 2651 u8 no_empty_cnt; 2652 2653 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2654 u8 cn; /* condition_num */ 2655 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2656 u8 train_result; /* refer to enum btc_fddt_check_map */ 2657 } __packed; 2658 2659 struct rtw89_btc_fbtc_fddt_cell_status { 2660 s8 wl_tx_pwr; 2661 s8 bt_tx_pwr; 2662 s8 bt_rx_gain; 2663 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2664 } __packed; 2665 2666 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2667 u8 fver; 2668 u8 rsvd; 2669 __le16 cycles; /* total cycle number */ 2670 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2671 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2672 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2673 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2674 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2675 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2676 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2677 __le32 bcn_cnt[CXBCN_MAX]; 2678 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2679 __le32 skip_cnt; 2680 __le32 except_cnt; 2681 __le32 except_map; 2682 } __packed; 2683 2684 #define FDD_TRAIN_WL_DIRECTION 2 2685 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2686 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2687 2688 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2689 u8 fver; 2690 u8 rsvd; 2691 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2692 u8 except_cnt; 2693 2694 __le16 skip_cnt; 2695 __le16 cycles; /* total cycle number */ 2696 2697 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2698 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2699 __le16 bcn_cnt[CXBCN_MAX]; 2700 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2701 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2702 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2703 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2704 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2705 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2706 [FDD_TRAIN_WL_RSSI_LEVEL] 2707 [FDD_TRAIN_BT_RSSI_LEVEL]; 2708 __le32 except_map; 2709 } __packed; 2710 2711 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2712 u8 fver; 2713 u8 rsvd; 2714 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2715 u8 except_cnt; 2716 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2717 2718 __le16 skip_cnt; 2719 __le16 cycles; /* total cycle number */ 2720 2721 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2722 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2723 __le16 bcn_cnt[CXBCN_MAX]; 2724 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2725 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2726 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2727 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2728 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2729 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2730 [FDD_TRAIN_WL_RSSI_LEVEL] 2731 [FDD_TRAIN_BT_RSSI_LEVEL]; 2732 __le32 except_map; 2733 } __packed; 2734 2735 struct rtw89_btc_fbtc_cysta_v7 { /* statistics for cycles */ 2736 u8 fver; 2737 u8 rsvd; 2738 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2739 u8 except_cnt; 2740 2741 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2742 2743 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2744 2745 __le16 skip_cnt; 2746 __le16 cycles; /* total cycle number */ 2747 2748 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2749 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2750 __le16 bcn_cnt[CXBCN_MAX]; 2751 2752 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2753 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2754 struct rtw89_btc_fbtc_cycle_leak_info_v7 leak_slot; 2755 2756 __le32 except_map; 2757 } __packed; 2758 2759 union rtw89_btc_fbtc_cysta_info { 2760 struct rtw89_btc_fbtc_cysta_v2 v2; 2761 struct rtw89_btc_fbtc_cysta_v3 v3; 2762 struct rtw89_btc_fbtc_cysta_v4 v4; 2763 struct rtw89_btc_fbtc_cysta_v5 v5; 2764 struct rtw89_btc_fbtc_cysta_v7 v7; 2765 }; 2766 2767 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2768 u8 fver; /* btc_ver::fcxnullsta */ 2769 u8 rsvd; 2770 __le16 rsvd2; 2771 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2772 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2773 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2774 } __packed; 2775 2776 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2777 u8 fver; /* btc_ver::fcxnullsta */ 2778 u8 rsvd; 2779 __le16 rsvd2; 2780 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2781 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2782 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2783 } __packed; 2784 2785 struct rtw89_btc_fbtc_cynullsta_v7 { /* cycle null statistics */ 2786 u8 fver; 2787 u8 rsvd0; 2788 u8 rsvd1; 2789 u8 rsvd2; 2790 2791 __le32 tmax[2]; 2792 __le32 tavg[2]; 2793 __le32 result[2][5]; 2794 } __packed; 2795 2796 union rtw89_btc_fbtc_cynullsta_info { 2797 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2798 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2799 struct rtw89_btc_fbtc_cynullsta_v7 v7; 2800 }; 2801 2802 struct rtw89_btc_fbtc_btver_v1 { 2803 u8 fver; /* btc_ver::fcxbtver */ 2804 u8 rsvd; 2805 __le16 rsvd2; 2806 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2807 __le32 fw_ver; 2808 __le32 feature; 2809 } __packed; 2810 2811 struct rtw89_btc_fbtc_btver_v7 { 2812 u8 fver; 2813 u8 rsvd0; 2814 u8 rsvd1; 2815 u8 rsvd2; 2816 2817 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2818 __le32 fw_ver; 2819 __le32 feature; 2820 } __packed; 2821 2822 union rtw89_btc_fbtc_btver { 2823 struct rtw89_btc_fbtc_btver_v1 v1; 2824 struct rtw89_btc_fbtc_btver_v7 v7; 2825 } __packed; 2826 2827 struct rtw89_btc_fbtc_btafh { 2828 u8 fver; /* btc_ver::fcxbtafh */ 2829 u8 rsvd; 2830 __le16 rsvd2; 2831 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2832 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2833 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2834 } __packed; 2835 2836 struct rtw89_btc_fbtc_btafh_v2 { 2837 u8 fver; /* btc_ver::fcxbtafh */ 2838 u8 rsvd; 2839 u8 rsvd2; 2840 u8 map_type; 2841 u8 afh_l[4]; 2842 u8 afh_m[4]; 2843 u8 afh_h[4]; 2844 u8 afh_le_a[4]; 2845 u8 afh_le_b[4]; 2846 } __packed; 2847 2848 struct rtw89_btc_fbtc_btafh_v7 { 2849 u8 fver; 2850 u8 map_type; 2851 u8 rsvd0; 2852 u8 rsvd1; 2853 u8 afh_l[4]; /*bit0:2402, bit1:2403.... bit31:2433 */ 2854 u8 afh_m[4]; /*bit0:2434, bit1:2435.... bit31:2465 */ 2855 u8 afh_h[4]; /*bit0:2466, bit1:2467.....bit14:2480 */ 2856 u8 afh_le_a[4]; 2857 u8 afh_le_b[4]; 2858 } __packed; 2859 2860 struct rtw89_btc_fbtc_btdevinfo { 2861 u8 fver; /* btc_ver::fcxbtdevinfo */ 2862 u8 rsvd; 2863 __le16 vendor_id; 2864 __le32 dev_name; /* only 24 bits valid */ 2865 __le32 flush_time; 2866 } __packed; 2867 2868 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2869 struct rtw89_btc_rf_trx_para { 2870 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2871 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2872 u8 bt_tx_power; /* decrease Tx power (dB) */ 2873 u8 bt_rx_gain; /* LNA constrain level */ 2874 }; 2875 2876 struct rtw89_btc_trx_info { 2877 u8 tx_lvl; 2878 u8 rx_lvl; 2879 u8 wl_rssi; 2880 u8 bt_rssi; 2881 2882 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2883 s8 rx_gain; /* rx gain table index (TBD.) */ 2884 s8 bt_tx_power; /* decrease Tx power (dB) */ 2885 s8 bt_rx_gain; /* LNA constrain level */ 2886 2887 u8 cn; /* condition_num */ 2888 s8 nhm; 2889 u8 bt_profile; 2890 u8 rsvd2; 2891 2892 u16 tx_rate; 2893 u16 rx_rate; 2894 2895 u32 tx_tp; 2896 u32 rx_tp; 2897 u32 rx_err_ratio; 2898 }; 2899 2900 union rtw89_btc_fbtc_slot_u { 2901 struct rtw89_btc_fbtc_slot v1[CXST_MAX]; 2902 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 2903 }; 2904 2905 struct rtw89_btc_dm { 2906 union rtw89_btc_fbtc_slot_u slot; 2907 union rtw89_btc_fbtc_slot_u slot_now; 2908 struct rtw89_btc_fbtc_tdma tdma; 2909 struct rtw89_btc_fbtc_tdma tdma_now; 2910 struct rtw89_mac_ax_coex_gnt gnt; 2911 union rtw89_btc_init_info_u init_info; /* pass to wl_fw if offload */ 2912 struct rtw89_btc_rf_trx_para rf_trx_para; 2913 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2914 struct rtw89_btc_dm_step dm_step; 2915 struct rtw89_btc_wl_scc_ctrl wl_scc; 2916 struct rtw89_btc_trx_info trx_info; 2917 union rtw89_btc_dm_error_map error; 2918 u32 cnt_dm[BTC_DCNT_NUM]; 2919 u32 cnt_notify[BTC_NCNT_NUM]; 2920 2921 u32 update_slot_map; 2922 u32 set_ant_path; 2923 u32 e2g_slot_limit; 2924 u32 e2g_slot_nulltx_time; 2925 2926 u32 wl_only: 1; 2927 u32 wl_fw_cx_offload: 1; 2928 u32 freerun: 1; 2929 u32 fddt_train: 1; 2930 u32 wl_ps_ctrl: 2; 2931 u32 wl_mimo_ps: 1; 2932 u32 leak_ap: 1; 2933 u32 noisy_level: 3; 2934 u32 coex_info_map: 8; 2935 u32 bt_only: 1; 2936 u32 wl_btg_rx: 2; 2937 u32 trx_para_level: 8; 2938 u32 wl_stb_chg: 1; 2939 u32 pta_owner: 1; 2940 2941 u32 tdma_instant_excute: 1; 2942 u32 wl_btg_rx_rb: 2; 2943 2944 u16 slot_dur[CXST_MAX]; 2945 u16 bt_slot_flood; 2946 2947 u8 run_reason; 2948 u8 run_action; 2949 2950 u8 wl_pre_agc: 2; 2951 u8 wl_lna2: 1; 2952 u8 freerun_chk: 1; 2953 u8 wl_pre_agc_rb: 2; 2954 u8 bt_select: 2; /* 0:s0, 1:s1, 2:s0 & s1, refer to enum btc_bt_index */ 2955 u8 slot_req_more: 1; 2956 }; 2957 2958 struct rtw89_btc_ctrl { 2959 u32 manual: 1; 2960 u32 igno_bt: 1; 2961 u32 always_freerun: 1; 2962 u32 trace_step: 16; 2963 u32 rsvd: 12; 2964 }; 2965 2966 struct rtw89_btc_ctrl_v7 { 2967 u8 manual; 2968 u8 igno_bt; 2969 u8 always_freerun; 2970 u8 rsvd; 2971 } __packed; 2972 2973 union rtw89_btc_ctrl_list { 2974 struct rtw89_btc_ctrl ctrl; 2975 struct rtw89_btc_ctrl_v7 ctrl_v7; 2976 }; 2977 2978 struct rtw89_btc_dbg { 2979 /* cmd "rb" */ 2980 bool rb_done; 2981 u32 rb_val; 2982 }; 2983 2984 enum rtw89_btc_btf_fw_event { 2985 BTF_EVNT_RPT = 0, 2986 BTF_EVNT_BT_INFO = 1, 2987 BTF_EVNT_BT_SCBD = 2, 2988 BTF_EVNT_BT_REG = 3, 2989 BTF_EVNT_CX_RUNINFO = 4, 2990 BTF_EVNT_BT_PSD = 5, 2991 BTF_EVNT_BT_DEV_INFO = 6, /* fwc2hfunc > 0 */ 2992 BTF_EVNT_BT_LEAUDIO_INFO = 7, /* fwc2hfunc > 1 */ 2993 BTF_EVNT_BUF_OVERFLOW, 2994 BTF_EVNT_C2H_LOOPBACK, 2995 BTF_EVNT_MAX, 2996 }; 2997 2998 enum btf_fw_event_report { 2999 BTC_RPT_TYPE_CTRL = 0x0, 3000 BTC_RPT_TYPE_TDMA, 3001 BTC_RPT_TYPE_SLOT, 3002 BTC_RPT_TYPE_CYSTA, 3003 BTC_RPT_TYPE_STEP, 3004 BTC_RPT_TYPE_NULLSTA, 3005 BTC_RPT_TYPE_FDDT, /* added by ver->fwevntrptl == 1 */ 3006 BTC_RPT_TYPE_MREG, 3007 BTC_RPT_TYPE_GPIO_DBG, 3008 BTC_RPT_TYPE_BT_VER, 3009 BTC_RPT_TYPE_BT_SCAN, 3010 BTC_RPT_TYPE_BT_AFH, 3011 BTC_RPT_TYPE_BT_DEVICE, 3012 BTC_RPT_TYPE_TEST, 3013 BTC_RPT_TYPE_MAX = 31, 3014 3015 __BTC_RPT_TYPE_V0_SAME = BTC_RPT_TYPE_NULLSTA, 3016 __BTC_RPT_TYPE_V0_MAX = 12, 3017 }; 3018 3019 enum rtw_btc_btf_reg_type { 3020 REG_MAC = 0x0, 3021 REG_BB = 0x1, 3022 REG_RF = 0x2, 3023 REG_BT_RF = 0x3, 3024 REG_BT_MODEM = 0x4, 3025 REG_BT_BLUEWIZE = 0x5, 3026 REG_BT_VENDOR = 0x6, 3027 REG_BT_LE = 0x7, 3028 REG_MAX_TYPE, 3029 }; 3030 3031 struct rtw89_btc_rpt_cmn_info { 3032 u32 rx_cnt; 3033 u32 rx_len; 3034 u32 req_len; /* expected rsp len */ 3035 u8 req_fver; /* expected rsp fver */ 3036 u8 rsp_fver; /* fver from fw */ 3037 u8 valid; 3038 } __packed; 3039 3040 union rtw89_btc_fbtc_btafh_info { 3041 struct rtw89_btc_fbtc_btafh v1; 3042 struct rtw89_btc_fbtc_btafh_v2 v2; 3043 }; 3044 3045 struct rtw89_btc_report_ctrl_state { 3046 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3047 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 3048 }; 3049 3050 struct rtw89_btc_rpt_fbtc_tdma { 3051 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3052 union rtw89_btc_fbtc_tdma_le32 finfo; 3053 }; 3054 3055 struct rtw89_btc_rpt_fbtc_slots { 3056 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3057 union rtw89_btc_fbtc_slots_info finfo; /* info from fw */ 3058 }; 3059 3060 struct rtw89_btc_rpt_fbtc_cysta { 3061 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3062 union rtw89_btc_fbtc_cysta_info finfo; 3063 }; 3064 3065 struct rtw89_btc_rpt_fbtc_step { 3066 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3067 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 3068 }; 3069 3070 struct rtw89_btc_rpt_fbtc_nullsta { 3071 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3072 union rtw89_btc_fbtc_cynullsta_info finfo; 3073 }; 3074 3075 struct rtw89_btc_rpt_fbtc_mreg { 3076 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3077 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 3078 }; 3079 3080 struct rtw89_btc_rpt_fbtc_gpio_dbg { 3081 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3082 union rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 3083 }; 3084 3085 struct rtw89_btc_rpt_fbtc_btver { 3086 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3087 union rtw89_btc_fbtc_btver finfo; /* info from fw */ 3088 }; 3089 3090 struct rtw89_btc_rpt_fbtc_btscan { 3091 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3092 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 3093 }; 3094 3095 struct rtw89_btc_rpt_fbtc_btafh { 3096 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3097 union rtw89_btc_fbtc_btafh_info finfo; 3098 }; 3099 3100 struct rtw89_btc_rpt_fbtc_btdev { 3101 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 3102 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 3103 }; 3104 3105 enum rtw89_btc_btfre_type { 3106 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 3107 BTFRE_UNDEF_TYPE, 3108 BTFRE_EXCEPTION, 3109 BTFRE_MAX, 3110 }; 3111 3112 struct rtw89_btc_btf_fwinfo { 3113 u32 cnt_c2h; 3114 u32 cnt_h2c; 3115 u32 cnt_h2c_fail; 3116 u32 event[BTF_EVNT_MAX]; 3117 3118 u32 err[BTFRE_MAX]; 3119 u32 len_mismch; 3120 u32 fver_mismch; 3121 u32 rpt_en_map; 3122 3123 struct rtw89_btc_report_ctrl_state rpt_ctrl; 3124 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 3125 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 3126 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 3127 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 3128 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 3129 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 3130 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 3131 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 3132 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 3133 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 3134 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 3135 }; 3136 3137 struct rtw89_btc_ver { 3138 enum rtw89_core_chip_id chip_id; 3139 u32 fw_ver_code; 3140 3141 u8 fcxbtcrpt; 3142 u8 fcxtdma; 3143 u8 fcxslots; 3144 u8 fcxcysta; 3145 u8 fcxstep; 3146 u8 fcxnullsta; 3147 u8 fcxmreg; 3148 u8 fcxgpiodbg; 3149 u8 fcxbtver; 3150 u8 fcxbtscan; 3151 u8 fcxbtafh; 3152 u8 fcxbtdevinfo; 3153 u8 fwlrole; 3154 u8 frptmap; 3155 u8 fcxctrl; 3156 u8 fcxinit; 3157 3158 u8 fwevntrptl; 3159 u8 fwc2hfunc; 3160 u8 drvinfo_type; 3161 u16 info_buf; 3162 u8 max_role_num; 3163 }; 3164 3165 #define RTW89_BTC_POLICY_MAXLEN 512 3166 3167 struct rtw89_btc { 3168 const struct rtw89_btc_ver *ver; 3169 3170 struct rtw89_btc_cx cx; 3171 struct rtw89_btc_dm dm; 3172 union rtw89_btc_ctrl_list ctrl; 3173 union rtw89_btc_module_info mdinfo; 3174 struct rtw89_btc_btf_fwinfo fwinfo; 3175 struct rtw89_btc_dbg dbg; 3176 3177 struct work_struct eapol_notify_work; 3178 struct work_struct arp_notify_work; 3179 struct work_struct dhcp_notify_work; 3180 struct work_struct icmp_notify_work; 3181 3182 u32 bt_req_len; 3183 3184 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 3185 u8 ant_type; 3186 u8 btg_pos; 3187 u16 policy_len; 3188 u16 policy_type; 3189 u32 hubmsg_cnt; 3190 bool bt_req_en; 3191 bool update_policy_force; 3192 bool lps; 3193 bool manual_ctrl; 3194 }; 3195 3196 enum rtw89_btc_hmsg { 3197 RTW89_BTC_HMSG_TMR_EN = 0x0, 3198 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 3199 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 3200 RTW89_BTC_HMSG_FW_EV = 0x3, 3201 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 3202 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 3203 3204 NUM_OF_RTW89_BTC_HMSG, 3205 }; 3206 3207 enum rtw89_ra_mode { 3208 RTW89_RA_MODE_CCK = BIT(0), 3209 RTW89_RA_MODE_OFDM = BIT(1), 3210 RTW89_RA_MODE_HT = BIT(2), 3211 RTW89_RA_MODE_VHT = BIT(3), 3212 RTW89_RA_MODE_HE = BIT(4), 3213 RTW89_RA_MODE_EHT = BIT(5), 3214 }; 3215 3216 enum rtw89_ra_report_mode { 3217 RTW89_RA_RPT_MODE_LEGACY, 3218 RTW89_RA_RPT_MODE_HT, 3219 RTW89_RA_RPT_MODE_VHT, 3220 RTW89_RA_RPT_MODE_HE, 3221 RTW89_RA_RPT_MODE_EHT, 3222 }; 3223 3224 enum rtw89_dig_noisy_level { 3225 RTW89_DIG_NOISY_LEVEL0 = -1, 3226 RTW89_DIG_NOISY_LEVEL1 = 0, 3227 RTW89_DIG_NOISY_LEVEL2 = 1, 3228 RTW89_DIG_NOISY_LEVEL3 = 2, 3229 RTW89_DIG_NOISY_LEVEL_MAX = 3, 3230 }; 3231 3232 enum rtw89_gi_ltf { 3233 RTW89_GILTF_LGI_4XHE32 = 0, 3234 RTW89_GILTF_SGI_4XHE08 = 1, 3235 RTW89_GILTF_2XHE16 = 2, 3236 RTW89_GILTF_2XHE08 = 3, 3237 RTW89_GILTF_1XHE16 = 4, 3238 RTW89_GILTF_1XHE08 = 5, 3239 RTW89_GILTF_MAX 3240 }; 3241 3242 enum rtw89_rx_frame_type { 3243 RTW89_RX_TYPE_MGNT = 0, 3244 RTW89_RX_TYPE_CTRL = 1, 3245 RTW89_RX_TYPE_DATA = 2, 3246 RTW89_RX_TYPE_RSVD = 3, 3247 }; 3248 3249 enum rtw89_efuse_block { 3250 RTW89_EFUSE_BLOCK_SYS = 0, 3251 RTW89_EFUSE_BLOCK_RF = 1, 3252 RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO = 2, 3253 RTW89_EFUSE_BLOCK_HCI_DIG_USB = 3, 3254 RTW89_EFUSE_BLOCK_HCI_PHY_PCIE = 4, 3255 RTW89_EFUSE_BLOCK_HCI_PHY_USB3 = 5, 3256 RTW89_EFUSE_BLOCK_HCI_PHY_USB2 = 6, 3257 RTW89_EFUSE_BLOCK_ADIE = 7, 3258 3259 RTW89_EFUSE_BLOCK_NUM, 3260 RTW89_EFUSE_BLOCK_IGNORE, 3261 }; 3262 3263 struct rtw89_ra_info { 3264 u8 is_dis_ra:1; 3265 /* Bit0 : CCK 3266 * Bit1 : OFDM 3267 * Bit2 : HT 3268 * Bit3 : VHT 3269 * Bit4 : HE 3270 * Bit5 : EHT 3271 */ 3272 u8 mode_ctrl:6; 3273 u8 bw_cap:3; /* enum rtw89_bandwidth */ 3274 u8 macid; 3275 u8 dcm_cap:1; 3276 u8 er_cap:1; 3277 u8 init_rate_lv:2; 3278 u8 upd_all:1; 3279 u8 en_sgi:1; 3280 u8 ldpc_cap:1; 3281 u8 stbc_cap:1; 3282 u8 ss_num:3; 3283 u8 giltf:3; 3284 u8 upd_bw_nss_mask:1; 3285 u8 upd_mask:1; 3286 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 3287 /* BFee CSI */ 3288 u8 band_num; 3289 u8 ra_csi_rate_en:1; 3290 u8 fixed_csi_rate_en:1; 3291 u8 cr_tbl_sel:1; 3292 u8 fix_giltf_en:1; 3293 u8 fix_giltf:3; 3294 u8 rsvd2:1; 3295 u8 csi_mcs_ss_idx; 3296 u8 csi_mode:2; 3297 u8 csi_gi_ltf:3; 3298 u8 csi_bw:3; 3299 }; 3300 3301 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 3302 #define RTW89_PPDU_MAC_INFO_SIZE 8 3303 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 3304 #define RTW89_PPDU_MAC_RX_CNT_SIZE_V1 128 3305 3306 #define RTW89_MAX_RX_AGG_NUM 64 3307 #define RTW89_MAX_TX_AGG_NUM 128 3308 3309 struct rtw89_ampdu_params { 3310 u16 agg_num; 3311 bool amsdu; 3312 }; 3313 3314 struct rtw89_ra_report { 3315 struct rate_info txrate; 3316 u32 bit_rate; 3317 u16 hw_rate; 3318 bool might_fallback_legacy; 3319 }; 3320 3321 DECLARE_EWMA(rssi, 10, 16); 3322 DECLARE_EWMA(evm, 10, 16); 3323 DECLARE_EWMA(snr, 10, 16); 3324 3325 struct rtw89_ba_cam_entry { 3326 struct list_head list; 3327 u8 tid; 3328 }; 3329 3330 #define RTW89_MAX_ADDR_CAM_NUM 128 3331 #define RTW89_MAX_BSSID_CAM_NUM 20 3332 #define RTW89_MAX_SEC_CAM_NUM 128 3333 #define RTW89_MAX_BA_CAM_NUM 24 3334 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 3335 3336 struct rtw89_addr_cam_entry { 3337 u8 addr_cam_idx; 3338 u8 offset; 3339 u8 len; 3340 u8 valid : 1; 3341 u8 addr_mask : 6; 3342 u8 wapi : 1; 3343 u8 mask_sel : 2; 3344 u8 bssid_cam_idx: 6; 3345 3346 u8 sec_ent_mode; 3347 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 3348 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 3349 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 3350 }; 3351 3352 struct rtw89_bssid_cam_entry { 3353 u8 bssid[ETH_ALEN]; 3354 u8 phy_idx; 3355 u8 bssid_cam_idx; 3356 u8 offset; 3357 u8 len; 3358 u8 valid : 1; 3359 u8 num; 3360 }; 3361 3362 struct rtw89_sec_cam_entry { 3363 u8 sec_cam_idx; 3364 u8 offset; 3365 u8 len; 3366 u8 type : 4; 3367 u8 ext_key : 1; 3368 u8 spp_mode : 1; 3369 /* 256 bits */ 3370 u8 key[32]; 3371 3372 struct ieee80211_key_conf *key_conf; 3373 }; 3374 3375 struct rtw89_sta_link { 3376 struct rtw89_sta *rtwsta; 3377 unsigned int link_id; 3378 3379 u8 mac_id; 3380 bool er_cap; 3381 struct rtw89_vif_link *rtwvif_link; 3382 struct rtw89_ra_info ra; 3383 struct rtw89_ra_report ra_report; 3384 int max_agg_wait; 3385 u8 prev_rssi; 3386 struct ewma_rssi avg_rssi; 3387 struct ewma_rssi rssi[RF_PATH_MAX]; 3388 struct ewma_snr avg_snr; 3389 struct ewma_evm evm_1ss; 3390 struct ewma_evm evm_min[RF_PATH_MAX]; 3391 struct ewma_evm evm_max[RF_PATH_MAX]; 3392 struct ieee80211_rx_status rx_status; 3393 u16 rx_hw_rate; 3394 __le32 htc_template; 3395 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 3396 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 3397 struct list_head ba_cam_list; 3398 3399 bool use_cfg_mask; 3400 struct cfg80211_bitrate_mask mask; 3401 3402 bool cctl_tx_time; 3403 u32 ampdu_max_time:4; 3404 bool cctl_tx_retry_limit; 3405 u32 data_tx_cnt_lmt:6; 3406 }; 3407 3408 struct rtw89_efuse { 3409 bool valid; 3410 bool power_k_valid; 3411 u8 xtal_cap; 3412 u8 addr[ETH_ALEN]; 3413 u8 rfe_type; 3414 char country_code[2]; 3415 }; 3416 3417 struct rtw89_phy_rate_pattern { 3418 u64 ra_mask; 3419 u16 rate; 3420 u8 ra_mode; 3421 bool enable; 3422 }; 3423 3424 struct rtw89_tx_wait_info { 3425 struct rcu_head rcu_head; 3426 struct completion completion; 3427 bool tx_done; 3428 }; 3429 3430 struct rtw89_tx_skb_data { 3431 struct rtw89_tx_wait_info __rcu *wait; 3432 u8 hci_priv[]; 3433 }; 3434 3435 #define RTW89_ROC_IDLE_TIMEOUT 500 3436 #define RTW89_ROC_TX_TIMEOUT 30 3437 enum rtw89_roc_state { 3438 RTW89_ROC_IDLE, 3439 RTW89_ROC_NORMAL, 3440 RTW89_ROC_MGMT, 3441 }; 3442 3443 #define RTW89_ROC_BY_LINK_INDEX 0 3444 3445 struct rtw89_roc { 3446 struct ieee80211_channel chan; 3447 struct delayed_work roc_work; 3448 enum ieee80211_roc_type type; 3449 enum rtw89_roc_state state; 3450 int duration; 3451 }; 3452 3453 #define RTW89_P2P_MAX_NOA_NUM 2 3454 3455 struct rtw89_p2p_ie_head { 3456 u8 eid; 3457 u8 ie_len; 3458 u8 oui[3]; 3459 u8 oui_type; 3460 } __packed; 3461 3462 struct rtw89_noa_attr_head { 3463 u8 attr_type; 3464 __le16 attr_len; 3465 u8 index; 3466 u8 oppps_ctwindow; 3467 } __packed; 3468 3469 struct rtw89_p2p_noa_ie { 3470 struct rtw89_p2p_ie_head p2p_head; 3471 struct rtw89_noa_attr_head noa_head; 3472 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 3473 } __packed; 3474 3475 struct rtw89_p2p_noa_setter { 3476 struct rtw89_p2p_noa_ie ie; 3477 u8 noa_count; 3478 u8 noa_index; 3479 }; 3480 3481 struct rtw89_vif_link { 3482 struct rtw89_vif *rtwvif; 3483 unsigned int link_id; 3484 3485 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 3486 enum rtw89_chanctx_idx chanctx_idx; 3487 enum rtw89_reg_6ghz_power reg_6ghz_power; 3488 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 3489 3490 u8 mac_id; 3491 u8 port; 3492 u8 mac_addr[ETH_ALEN]; 3493 u8 bssid[ETH_ALEN]; 3494 u8 phy_idx; 3495 u8 mac_idx; 3496 u8 net_type; 3497 u8 wifi_role; 3498 u8 self_role; 3499 u8 wmm; 3500 u8 bcn_hit_cond; 3501 u8 hit_rule; 3502 u8 last_noa_nr; 3503 u64 sync_bcn_tsf; 3504 bool trigger; 3505 bool lsig_txop; 3506 u8 tgt_ind; 3507 u8 frm_tgt_ind; 3508 bool wowlan_pattern; 3509 bool wowlan_uc; 3510 bool wowlan_magic; 3511 bool is_hesta; 3512 bool last_a_ctrl; 3513 bool dyn_tb_bedge_en; 3514 bool pre_pwr_diff_en; 3515 bool pwr_diff_en; 3516 u8 def_tri_idx; 3517 struct work_struct update_beacon_work; 3518 struct rtw89_addr_cam_entry addr_cam; 3519 struct rtw89_bssid_cam_entry bssid_cam; 3520 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3521 struct rtw89_phy_rate_pattern rate_pattern; 3522 struct list_head general_pkt_list; 3523 struct rtw89_p2p_noa_setter p2p_noa; 3524 }; 3525 3526 enum rtw89_lv1_rcvy_step { 3527 RTW89_LV1_RCVY_STEP_1, 3528 RTW89_LV1_RCVY_STEP_2, 3529 }; 3530 3531 struct rtw89_hci_ops { 3532 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3533 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3534 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3535 void (*reset)(struct rtw89_dev *rtwdev); 3536 int (*start)(struct rtw89_dev *rtwdev); 3537 void (*stop)(struct rtw89_dev *rtwdev); 3538 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3539 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3540 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3541 3542 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3543 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3544 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3545 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3546 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3547 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3548 3549 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3550 int (*mac_pre_deinit)(struct rtw89_dev *rtwdev); 3551 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3552 int (*deinit)(struct rtw89_dev *rtwdev); 3553 3554 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3555 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3556 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3557 int (*napi_poll)(struct napi_struct *napi, int budget); 3558 3559 /* Deal with locks inside recovery_start and recovery_complete callbacks 3560 * by hci instance, and handle things which need to consider under SER. 3561 * e.g. turn on/off interrupts except for the one for halt notification. 3562 */ 3563 void (*recovery_start)(struct rtw89_dev *rtwdev); 3564 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3565 3566 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3567 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3568 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3569 int (*poll_txdma_ch_idle)(struct rtw89_dev *rtwdev); 3570 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3571 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3572 void (*disable_intr)(struct rtw89_dev *rtwdev); 3573 void (*enable_intr)(struct rtw89_dev *rtwdev); 3574 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3575 }; 3576 3577 struct rtw89_hci_info { 3578 const struct rtw89_hci_ops *ops; 3579 enum rtw89_hci_type type; 3580 u32 rpwm_addr; 3581 u32 cpwm_addr; 3582 bool paused; 3583 }; 3584 3585 struct rtw89_chip_ops { 3586 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3587 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3588 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3589 void (*bb_postinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3590 void (*bb_reset)(struct rtw89_dev *rtwdev, 3591 enum rtw89_phy_idx phy_idx); 3592 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3593 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3594 u32 addr, u32 mask); 3595 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3596 u32 addr, u32 mask, u32 data); 3597 void (*set_channel)(struct rtw89_dev *rtwdev, 3598 const struct rtw89_chan *chan, 3599 enum rtw89_mac_idx mac_idx, 3600 enum rtw89_phy_idx phy_idx); 3601 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3602 struct rtw89_channel_help_params *p, 3603 const struct rtw89_chan *chan, 3604 enum rtw89_mac_idx mac_idx, 3605 enum rtw89_phy_idx phy_idx); 3606 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 3607 enum rtw89_efuse_block block); 3608 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3609 void (*fem_setup)(struct rtw89_dev *rtwdev); 3610 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3611 void (*rfk_hw_init)(struct rtw89_dev *rtwdev); 3612 void (*rfk_init)(struct rtw89_dev *rtwdev); 3613 void (*rfk_init_late)(struct rtw89_dev *rtwdev); 3614 void (*rfk_channel)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link); 3615 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3616 enum rtw89_phy_idx phy_idx, 3617 const struct rtw89_chan *chan); 3618 void (*rfk_scan)(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3619 bool start); 3620 void (*rfk_track)(struct rtw89_dev *rtwdev); 3621 void (*power_trim)(struct rtw89_dev *rtwdev); 3622 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3623 const struct rtw89_chan *chan, 3624 enum rtw89_phy_idx phy_idx); 3625 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3626 enum rtw89_phy_idx phy_idx); 3627 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3628 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3629 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 3630 enum rtw89_phy_idx phy_idx); 3631 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3632 struct rtw89_rx_phy_ppdu *phy_ppdu, 3633 struct ieee80211_rx_status *status); 3634 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 3635 struct rtw89_rx_phy_ppdu *phy_ppdu); 3636 void (*phy_rpt_to_rssi)(struct rtw89_dev *rtwdev, 3637 struct rtw89_rx_desc_info *desc_info, 3638 struct ieee80211_rx_status *rx_status); 3639 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 3640 enum rtw89_phy_idx phy_idx); 3641 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3642 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3643 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3644 void (*digital_pwr_comp)(struct rtw89_dev *rtwdev, 3645 enum rtw89_phy_idx phy_idx); 3646 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3647 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3648 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3649 struct rtw89_rx_desc_info *desc_info, 3650 u8 *data, u32 data_offset); 3651 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3652 struct rtw89_tx_desc_info *desc_info, 3653 void *txdesc); 3654 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3655 struct rtw89_tx_desc_info *desc_info, 3656 void *txdesc); 3657 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3658 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3659 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3660 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3661 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3662 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3663 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3664 struct rtw89_vif_link *rtwvif_link, 3665 struct rtw89_sta_link *rtwsta_link); 3666 int (*h2c_default_cmac_tbl)(struct rtw89_dev *rtwdev, 3667 struct rtw89_vif_link *rtwvif_link, 3668 struct rtw89_sta_link *rtwsta_link); 3669 int (*h2c_assoc_cmac_tbl)(struct rtw89_dev *rtwdev, 3670 struct rtw89_vif_link *rtwvif_link, 3671 struct rtw89_sta_link *rtwsta_link); 3672 int (*h2c_ampdu_cmac_tbl)(struct rtw89_dev *rtwdev, 3673 struct rtw89_vif_link *rtwvif_link, 3674 struct rtw89_sta_link *rtwsta_link); 3675 int (*h2c_default_dmac_tbl)(struct rtw89_dev *rtwdev, 3676 struct rtw89_vif_link *rtwvif_link, 3677 struct rtw89_sta_link *rtwsta_link); 3678 int (*h2c_update_beacon)(struct rtw89_dev *rtwdev, 3679 struct rtw89_vif_link *rtwvif_link); 3680 int (*h2c_ba_cam)(struct rtw89_dev *rtwdev, 3681 struct rtw89_vif_link *rtwvif_link, 3682 struct rtw89_sta_link *rtwsta_link, 3683 bool valid, struct ieee80211_ampdu_params *params); 3684 3685 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3686 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3687 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3688 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3689 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3690 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3691 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3692 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3693 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3694 }; 3695 3696 enum rtw89_dma_ch { 3697 RTW89_DMA_ACH0 = 0, 3698 RTW89_DMA_ACH1 = 1, 3699 RTW89_DMA_ACH2 = 2, 3700 RTW89_DMA_ACH3 = 3, 3701 RTW89_DMA_ACH4 = 4, 3702 RTW89_DMA_ACH5 = 5, 3703 RTW89_DMA_ACH6 = 6, 3704 RTW89_DMA_ACH7 = 7, 3705 RTW89_DMA_B0MG = 8, 3706 RTW89_DMA_B0HI = 9, 3707 RTW89_DMA_B1MG = 10, 3708 RTW89_DMA_B1HI = 11, 3709 RTW89_DMA_H2C = 12, 3710 RTW89_DMA_CH_NUM = 13 3711 }; 3712 3713 #define MLO_MODE_FOR_BB0_BB1_RF(bb0, bb1, rf) ((rf) << 12 | (bb1) << 4 | (bb0)) 3714 3715 enum rtw89_mlo_dbcc_mode { 3716 MLO_DBCC_NOT_SUPPORT = 1, 3717 MLO_0_PLUS_2_1RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 1), 3718 MLO_0_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(0, 2, 2), 3719 MLO_1_PLUS_1_1RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 1), 3720 MLO_1_PLUS_1_2RF = MLO_MODE_FOR_BB0_BB1_RF(1, 1, 2), 3721 MLO_2_PLUS_0_1RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 1), 3722 MLO_2_PLUS_0_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 0, 2), 3723 MLO_2_PLUS_2_2RF = MLO_MODE_FOR_BB0_BB1_RF(2, 2, 2), 3724 DBCC_LEGACY = 0xffffffff, 3725 }; 3726 3727 enum rtw89_scan_be_operation { 3728 RTW89_SCAN_OP_STOP, 3729 RTW89_SCAN_OP_START, 3730 RTW89_SCAN_OP_SETPARM, 3731 RTW89_SCAN_OP_GETRPT, 3732 RTW89_SCAN_OP_NUM 3733 }; 3734 3735 enum rtw89_scan_be_mode { 3736 RTW89_SCAN_MODE_SA, 3737 RTW89_SCAN_MODE_MACC, 3738 RTW89_SCAN_MODE_NUM 3739 }; 3740 3741 enum rtw89_scan_be_opmode { 3742 RTW89_SCAN_OPMODE_NONE, 3743 RTW89_SCAN_OPMODE_TBTT, 3744 RTW89_SCAN_OPMODE_INTV, 3745 RTW89_SCAN_OPMODE_CNT, 3746 RTW89_SCAN_OPMODE_NUM, 3747 }; 3748 3749 struct rtw89_scan_option { 3750 bool enable; 3751 bool target_ch_mode; 3752 u8 num_macc_role; 3753 u8 num_opch; 3754 u8 repeat; 3755 u16 norm_pd; 3756 u16 slow_pd; 3757 u16 norm_cy; 3758 u8 opch_end; 3759 u16 delay; 3760 u64 prohib_chan; 3761 enum rtw89_phy_idx band; 3762 enum rtw89_scan_be_operation operation; 3763 enum rtw89_scan_be_mode scan_mode; 3764 enum rtw89_mlo_dbcc_mode mlo_mode; 3765 }; 3766 3767 enum rtw89_qta_mode { 3768 RTW89_QTA_SCC, 3769 RTW89_QTA_DBCC, 3770 RTW89_QTA_DLFW, 3771 RTW89_QTA_WOW, 3772 3773 /* keep last */ 3774 RTW89_QTA_INVALID, 3775 }; 3776 3777 struct rtw89_hfc_ch_cfg { 3778 u16 min; 3779 u16 max; 3780 #define grp_0 0 3781 #define grp_1 1 3782 #define grp_num 2 3783 u8 grp; 3784 }; 3785 3786 struct rtw89_hfc_ch_info { 3787 u16 aval; 3788 u16 used; 3789 }; 3790 3791 struct rtw89_hfc_pub_cfg { 3792 u16 grp0; 3793 u16 grp1; 3794 u16 pub_max; 3795 u16 wp_thrd; 3796 }; 3797 3798 struct rtw89_hfc_pub_info { 3799 u16 g0_used; 3800 u16 g1_used; 3801 u16 g0_aval; 3802 u16 g1_aval; 3803 u16 pub_aval; 3804 u16 wp_aval; 3805 }; 3806 3807 struct rtw89_hfc_prec_cfg { 3808 u16 ch011_prec; 3809 u16 h2c_prec; 3810 u16 wp_ch07_prec; 3811 u16 wp_ch811_prec; 3812 u8 ch011_full_cond; 3813 u8 h2c_full_cond; 3814 u8 wp_ch07_full_cond; 3815 u8 wp_ch811_full_cond; 3816 }; 3817 3818 struct rtw89_hfc_param { 3819 bool en; 3820 bool h2c_en; 3821 u8 mode; 3822 const struct rtw89_hfc_ch_cfg *ch_cfg; 3823 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3824 struct rtw89_hfc_pub_cfg pub_cfg; 3825 struct rtw89_hfc_pub_info pub_info; 3826 struct rtw89_hfc_prec_cfg prec_cfg; 3827 }; 3828 3829 struct rtw89_hfc_param_ini { 3830 const struct rtw89_hfc_ch_cfg *ch_cfg; 3831 const struct rtw89_hfc_pub_cfg *pub_cfg; 3832 const struct rtw89_hfc_prec_cfg *prec_cfg; 3833 u8 mode; 3834 }; 3835 3836 struct rtw89_dle_size { 3837 u16 pge_size; 3838 u16 lnk_pge_num; 3839 u16 unlnk_pge_num; 3840 /* for WiFi 7 chips below */ 3841 u32 srt_ofst; 3842 }; 3843 3844 struct rtw89_wde_quota { 3845 u16 hif; 3846 u16 wcpu; 3847 u16 pkt_in; 3848 u16 cpu_io; 3849 }; 3850 3851 struct rtw89_ple_quota { 3852 u16 cma0_tx; 3853 u16 cma1_tx; 3854 u16 c2h; 3855 u16 h2c; 3856 u16 wcpu; 3857 u16 mpdu_proc; 3858 u16 cma0_dma; 3859 u16 cma1_dma; 3860 u16 bb_rpt; 3861 u16 wd_rel; 3862 u16 cpu_io; 3863 u16 tx_rpt; 3864 /* for WiFi 7 chips below */ 3865 u16 h2d; 3866 }; 3867 3868 struct rtw89_rsvd_quota { 3869 u16 mpdu_info_tbl; 3870 u16 b0_csi; 3871 u16 b1_csi; 3872 u16 b0_lmr; 3873 u16 b1_lmr; 3874 u16 b0_ftm; 3875 u16 b1_ftm; 3876 u16 b0_smr; 3877 u16 b1_smr; 3878 u16 others; 3879 }; 3880 3881 struct rtw89_dle_rsvd_size { 3882 u32 srt_ofst; 3883 u32 size; 3884 }; 3885 3886 struct rtw89_dle_mem { 3887 enum rtw89_qta_mode mode; 3888 const struct rtw89_dle_size *wde_size; 3889 const struct rtw89_dle_size *ple_size; 3890 const struct rtw89_wde_quota *wde_min_qt; 3891 const struct rtw89_wde_quota *wde_max_qt; 3892 const struct rtw89_ple_quota *ple_min_qt; 3893 const struct rtw89_ple_quota *ple_max_qt; 3894 /* for WiFi 7 chips below */ 3895 const struct rtw89_rsvd_quota *rsvd_qt; 3896 const struct rtw89_dle_rsvd_size *rsvd0_size; 3897 const struct rtw89_dle_rsvd_size *rsvd1_size; 3898 }; 3899 3900 struct rtw89_reg_def { 3901 u32 addr; 3902 u32 mask; 3903 }; 3904 3905 struct rtw89_reg2_def { 3906 u32 addr; 3907 u32 data; 3908 }; 3909 3910 struct rtw89_reg3_def { 3911 u32 addr; 3912 u32 mask; 3913 u32 data; 3914 }; 3915 3916 struct rtw89_reg5_def { 3917 u8 flag; /* recognized by parsers */ 3918 u8 path; 3919 u32 addr; 3920 u32 mask; 3921 u32 data; 3922 }; 3923 3924 struct rtw89_reg_imr { 3925 u32 addr; 3926 u32 clr; 3927 u32 set; 3928 }; 3929 3930 struct rtw89_phy_table { 3931 const struct rtw89_reg2_def *regs; 3932 u32 n_regs; 3933 enum rtw89_rf_path rf_path; 3934 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3935 enum rtw89_rf_path rf_path, void *data); 3936 }; 3937 3938 struct rtw89_txpwr_table { 3939 const void *data; 3940 u32 size; 3941 void (*load)(struct rtw89_dev *rtwdev, 3942 const struct rtw89_txpwr_table *tbl); 3943 }; 3944 3945 struct rtw89_txpwr_rule_2ghz { 3946 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3947 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3948 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3949 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3950 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3951 }; 3952 3953 struct rtw89_txpwr_rule_5ghz { 3954 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3955 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3956 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3957 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3958 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3959 }; 3960 3961 struct rtw89_txpwr_rule_6ghz { 3962 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3963 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3964 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3965 [RTW89_6G_CH_NUM]; 3966 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3967 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3968 [RTW89_6G_CH_NUM]; 3969 }; 3970 3971 struct rtw89_tx_shape { 3972 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3973 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3974 }; 3975 3976 struct rtw89_rfe_parms { 3977 const struct rtw89_txpwr_table *byr_tbl; 3978 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3979 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3980 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3981 struct rtw89_tx_shape tx_shape; 3982 }; 3983 3984 struct rtw89_rfe_parms_conf { 3985 const struct rtw89_rfe_parms *rfe_parms; 3986 u8 rfe_type; 3987 }; 3988 3989 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3990 3991 struct rtw89_txpwr_conf { 3992 u8 rfe_type; 3993 u8 ent_sz; 3994 u32 num_ents; 3995 const void *data; 3996 }; 3997 3998 static inline bool rtw89_txpwr_entcpy(void *entry, const void *cursor, u8 size, 3999 const struct rtw89_txpwr_conf *conf) 4000 { 4001 u8 valid_size = min(size, conf->ent_sz); 4002 4003 memcpy(entry, cursor, valid_size); 4004 return true; 4005 } 4006 4007 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 4008 4009 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 4010 for (typecheck(const void *, cursor), (cursor) = (conf)->data; \ 4011 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 4012 (cursor) += (conf)->ent_sz) \ 4013 if (rtw89_txpwr_entcpy(&(entry), cursor, sizeof(entry), conf)) 4014 4015 struct rtw89_txpwr_byrate_data { 4016 struct rtw89_txpwr_conf conf; 4017 struct rtw89_txpwr_table tbl; 4018 }; 4019 4020 struct rtw89_txpwr_lmt_2ghz_data { 4021 struct rtw89_txpwr_conf conf; 4022 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 4023 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4024 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4025 }; 4026 4027 struct rtw89_txpwr_lmt_5ghz_data { 4028 struct rtw89_txpwr_conf conf; 4029 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 4030 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4031 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4032 }; 4033 4034 struct rtw89_txpwr_lmt_6ghz_data { 4035 struct rtw89_txpwr_conf conf; 4036 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 4037 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 4038 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4039 [RTW89_6G_CH_NUM]; 4040 }; 4041 4042 struct rtw89_txpwr_lmt_ru_2ghz_data { 4043 struct rtw89_txpwr_conf conf; 4044 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4045 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 4046 }; 4047 4048 struct rtw89_txpwr_lmt_ru_5ghz_data { 4049 struct rtw89_txpwr_conf conf; 4050 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4051 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 4052 }; 4053 4054 struct rtw89_txpwr_lmt_ru_6ghz_data { 4055 struct rtw89_txpwr_conf conf; 4056 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 4057 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 4058 [RTW89_6G_CH_NUM]; 4059 }; 4060 4061 struct rtw89_tx_shape_lmt_data { 4062 struct rtw89_txpwr_conf conf; 4063 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 4064 }; 4065 4066 struct rtw89_tx_shape_lmt_ru_data { 4067 struct rtw89_txpwr_conf conf; 4068 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 4069 }; 4070 4071 struct rtw89_rfe_data { 4072 struct rtw89_txpwr_byrate_data byrate; 4073 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 4074 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 4075 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 4076 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 4077 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 4078 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 4079 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 4080 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 4081 struct rtw89_rfe_parms rfe_parms; 4082 }; 4083 4084 struct rtw89_page_regs { 4085 u32 hci_fc_ctrl; 4086 u32 ch_page_ctrl; 4087 u32 ach_page_ctrl; 4088 u32 ach_page_info; 4089 u32 pub_page_info3; 4090 u32 pub_page_ctrl1; 4091 u32 pub_page_ctrl2; 4092 u32 pub_page_info1; 4093 u32 pub_page_info2; 4094 u32 wp_page_ctrl1; 4095 u32 wp_page_ctrl2; 4096 u32 wp_page_info1; 4097 }; 4098 4099 struct rtw89_imr_info { 4100 u32 wdrls_imr_set; 4101 u32 wsec_imr_reg; 4102 u32 wsec_imr_set; 4103 u32 mpdu_tx_imr_set; 4104 u32 mpdu_rx_imr_set; 4105 u32 sta_sch_imr_set; 4106 u32 txpktctl_imr_b0_reg; 4107 u32 txpktctl_imr_b0_clr; 4108 u32 txpktctl_imr_b0_set; 4109 u32 txpktctl_imr_b1_reg; 4110 u32 txpktctl_imr_b1_clr; 4111 u32 txpktctl_imr_b1_set; 4112 u32 wde_imr_clr; 4113 u32 wde_imr_set; 4114 u32 ple_imr_clr; 4115 u32 ple_imr_set; 4116 u32 host_disp_imr_clr; 4117 u32 host_disp_imr_set; 4118 u32 cpu_disp_imr_clr; 4119 u32 cpu_disp_imr_set; 4120 u32 other_disp_imr_clr; 4121 u32 other_disp_imr_set; 4122 u32 bbrpt_com_err_imr_reg; 4123 u32 bbrpt_chinfo_err_imr_reg; 4124 u32 bbrpt_err_imr_set; 4125 u32 bbrpt_dfs_err_imr_reg; 4126 u32 ptcl_imr_clr; 4127 u32 ptcl_imr_set; 4128 u32 cdma_imr_0_reg; 4129 u32 cdma_imr_0_clr; 4130 u32 cdma_imr_0_set; 4131 u32 cdma_imr_1_reg; 4132 u32 cdma_imr_1_clr; 4133 u32 cdma_imr_1_set; 4134 u32 phy_intf_imr_reg; 4135 u32 phy_intf_imr_clr; 4136 u32 phy_intf_imr_set; 4137 u32 rmac_imr_reg; 4138 u32 rmac_imr_clr; 4139 u32 rmac_imr_set; 4140 u32 tmac_imr_reg; 4141 u32 tmac_imr_clr; 4142 u32 tmac_imr_set; 4143 }; 4144 4145 struct rtw89_imr_table { 4146 const struct rtw89_reg_imr *regs; 4147 u32 n_regs; 4148 }; 4149 4150 struct rtw89_xtal_info { 4151 u32 xcap_reg; 4152 u32 sc_xo_mask; 4153 u32 sc_xi_mask; 4154 }; 4155 4156 struct rtw89_rrsr_cfgs { 4157 struct rtw89_reg3_def ref_rate; 4158 struct rtw89_reg3_def rsc; 4159 }; 4160 4161 struct rtw89_rfkill_regs { 4162 struct rtw89_reg3_def pinmux; 4163 struct rtw89_reg3_def mode; 4164 }; 4165 4166 struct rtw89_dig_regs { 4167 u32 seg0_pd_reg; 4168 u32 pd_lower_bound_mask; 4169 u32 pd_spatial_reuse_en; 4170 u32 bmode_pd_reg; 4171 u32 bmode_cca_rssi_limit_en; 4172 u32 bmode_pd_lower_bound_reg; 4173 u32 bmode_rssi_nocca_low_th_mask; 4174 struct rtw89_reg_def p0_lna_init; 4175 struct rtw89_reg_def p1_lna_init; 4176 struct rtw89_reg_def p0_tia_init; 4177 struct rtw89_reg_def p1_tia_init; 4178 struct rtw89_reg_def p0_rxb_init; 4179 struct rtw89_reg_def p1_rxb_init; 4180 struct rtw89_reg_def p0_p20_pagcugc_en; 4181 struct rtw89_reg_def p0_s20_pagcugc_en; 4182 struct rtw89_reg_def p1_p20_pagcugc_en; 4183 struct rtw89_reg_def p1_s20_pagcugc_en; 4184 }; 4185 4186 struct rtw89_edcca_regs { 4187 u32 edcca_level; 4188 u32 edcca_mask; 4189 u32 edcca_p_mask; 4190 u32 ppdu_level; 4191 u32 ppdu_mask; 4192 u32 rpt_a; 4193 u32 rpt_b; 4194 u32 rpt_sel; 4195 u32 rpt_sel_mask; 4196 u32 rpt_sel_be; 4197 u32 rpt_sel_be_mask; 4198 u32 tx_collision_t2r_st; 4199 u32 tx_collision_t2r_st_mask; 4200 }; 4201 4202 struct rtw89_phy_ul_tb_info { 4203 bool dyn_tb_tri_en; 4204 u8 def_if_bandedge; 4205 }; 4206 4207 struct rtw89_antdiv_stats { 4208 struct ewma_rssi cck_rssi_avg; 4209 struct ewma_rssi ofdm_rssi_avg; 4210 struct ewma_rssi non_legacy_rssi_avg; 4211 u16 pkt_cnt_cck; 4212 u16 pkt_cnt_ofdm; 4213 u16 pkt_cnt_non_legacy; 4214 u32 evm; 4215 }; 4216 4217 struct rtw89_antdiv_info { 4218 struct rtw89_antdiv_stats target_stats; 4219 struct rtw89_antdiv_stats main_stats; 4220 struct rtw89_antdiv_stats aux_stats; 4221 u8 training_count; 4222 u8 rssi_pre; 4223 bool get_stats; 4224 }; 4225 4226 enum rtw89_chanctx_state { 4227 RTW89_CHANCTX_STATE_MCC_START, 4228 RTW89_CHANCTX_STATE_MCC_STOP, 4229 }; 4230 4231 enum rtw89_chanctx_callbacks { 4232 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 4233 RTW89_CHANCTX_CALLBACK_RFK, 4234 4235 NUM_OF_RTW89_CHANCTX_CALLBACKS, 4236 }; 4237 4238 struct rtw89_chanctx_listener { 4239 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 4240 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 4241 }; 4242 4243 struct rtw89_chip_info { 4244 enum rtw89_core_chip_id chip_id; 4245 enum rtw89_chip_gen chip_gen; 4246 const struct rtw89_chip_ops *ops; 4247 const struct rtw89_mac_gen_def *mac_def; 4248 const struct rtw89_phy_gen_def *phy_def; 4249 const char *fw_basename; 4250 u8 fw_format_max; 4251 bool try_ce_fw; 4252 u8 bbmcu_nr; 4253 u32 needed_fw_elms; 4254 u32 fifo_size; 4255 bool small_fifo_size; 4256 u32 dle_scc_rsvd_size; 4257 u16 max_amsdu_limit; 4258 bool dis_2g_40m_ul_ofdma; 4259 u32 rsvd_ple_ofst; 4260 const struct rtw89_hfc_param_ini *hfc_param_ini; 4261 const struct rtw89_dle_mem *dle_mem; 4262 u8 wde_qempty_acq_grpnum; 4263 u8 wde_qempty_mgq_grpsel; 4264 u32 rf_base_addr[2]; 4265 u8 thermal_th[2]; 4266 u8 support_macid_num; 4267 u8 support_link_num; 4268 u8 support_chanctx_num; 4269 u8 support_bands; 4270 u16 support_bandwidths; 4271 bool support_unii4; 4272 bool support_rnr; 4273 bool support_ant_gain; 4274 bool ul_tb_waveform_ctrl; 4275 bool ul_tb_pwr_diff; 4276 bool hw_sec_hdr; 4277 bool hw_mgmt_tx_encrypt; 4278 u8 rf_path_num; 4279 u8 tx_nss; 4280 u8 rx_nss; 4281 u8 acam_num; 4282 u8 bcam_num; 4283 u8 scam_num; 4284 u8 bacam_num; 4285 u8 bacam_dynamic_num; 4286 enum rtw89_bacam_ver bacam_ver; 4287 u8 ppdu_max_usr; 4288 4289 u8 sec_ctrl_efuse_size; 4290 u32 physical_efuse_size; 4291 u32 logical_efuse_size; 4292 u32 limit_efuse_size; 4293 u32 dav_phy_efuse_size; 4294 u32 dav_log_efuse_size; 4295 u32 phycap_addr; 4296 u32 phycap_size; 4297 const struct rtw89_efuse_block_cfg *efuse_blocks; 4298 4299 const struct rtw89_pwr_cfg * const *pwr_on_seq; 4300 const struct rtw89_pwr_cfg * const *pwr_off_seq; 4301 const struct rtw89_phy_table *bb_table; 4302 const struct rtw89_phy_table *bb_gain_table; 4303 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 4304 const struct rtw89_phy_table *nctl_table; 4305 const struct rtw89_rfk_tbl *nctl_post_table; 4306 const struct rtw89_phy_dig_gain_table *dig_table; 4307 const struct rtw89_dig_regs *dig_regs; 4308 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 4309 4310 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 4311 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 4312 const struct rtw89_rfe_parms *dflt_parms; 4313 const struct rtw89_chanctx_listener *chanctx_listener; 4314 4315 u8 txpwr_factor_bb; 4316 u8 txpwr_factor_rf; 4317 u8 txpwr_factor_mac; 4318 4319 u32 para_ver; 4320 u32 wlcx_desired; 4321 u8 btcx_desired; 4322 u8 scbd; 4323 u8 mailbox; 4324 4325 u8 afh_guard_ch; 4326 const u8 *wl_rssi_thres; 4327 const u8 *bt_rssi_thres; 4328 u8 rssi_tol; 4329 4330 u8 mon_reg_num; 4331 const struct rtw89_btc_fbtc_mreg *mon_reg; 4332 u8 rf_para_ulink_num; 4333 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 4334 u8 rf_para_dlink_num; 4335 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 4336 u8 ps_mode_supported; 4337 u8 low_power_hci_modes; 4338 4339 u32 h2c_cctl_func_id; 4340 u32 hci_func_en_addr; 4341 u32 h2c_desc_size; 4342 u32 txwd_body_size; 4343 u32 txwd_info_size; 4344 u32 h2c_ctrl_reg; 4345 const u32 *h2c_regs; 4346 struct rtw89_reg_def h2c_counter_reg; 4347 u32 c2h_ctrl_reg; 4348 const u32 *c2h_regs; 4349 struct rtw89_reg_def c2h_counter_reg; 4350 const struct rtw89_page_regs *page_regs; 4351 const u32 *wow_reason_reg; 4352 bool cfo_src_fd; 4353 bool cfo_hw_comp; 4354 const struct rtw89_reg_def *dcfo_comp; 4355 u8 dcfo_comp_sft; 4356 const struct rtw89_imr_info *imr_info; 4357 const struct rtw89_imr_table *imr_dmac_table; 4358 const struct rtw89_imr_table *imr_cmac_table; 4359 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 4360 struct rtw89_reg_def bss_clr_vld; 4361 u32 bss_clr_map_reg; 4362 const struct rtw89_rfkill_regs *rfkill_init; 4363 struct rtw89_reg_def rfkill_get; 4364 u32 dma_ch_mask; 4365 const struct rtw89_edcca_regs *edcca_regs; 4366 const struct wiphy_wowlan_support *wowlan_stub; 4367 const struct rtw89_xtal_info *xtal_info; 4368 }; 4369 4370 struct rtw89_chip_variant { 4371 bool no_mcs_12_13: 1; 4372 u32 fw_min_ver_code; 4373 }; 4374 4375 union rtw89_bus_info { 4376 const struct rtw89_pci_info *pci; 4377 }; 4378 4379 struct rtw89_driver_info { 4380 const struct rtw89_chip_info *chip; 4381 const struct rtw89_chip_variant *variant; 4382 const struct dmi_system_id *quirks; 4383 union rtw89_bus_info bus; 4384 }; 4385 4386 enum rtw89_hcifc_mode { 4387 RTW89_HCIFC_POH = 0, 4388 RTW89_HCIFC_STF = 1, 4389 RTW89_HCIFC_SDIO = 2, 4390 4391 /* keep last */ 4392 RTW89_HCIFC_MODE_INVALID, 4393 }; 4394 4395 struct rtw89_dle_info { 4396 const struct rtw89_rsvd_quota *rsvd_qt; 4397 enum rtw89_qta_mode qta_mode; 4398 u16 ple_pg_size; 4399 u16 ple_free_pg; 4400 u16 c0_rx_qta; 4401 u16 c1_rx_qta; 4402 }; 4403 4404 enum rtw89_host_rpr_mode { 4405 RTW89_RPR_MODE_POH = 0, 4406 RTW89_RPR_MODE_STF 4407 }; 4408 4409 #define RTW89_COMPLETION_BUF_SIZE 40 4410 #define RTW89_WAIT_COND_IDLE UINT_MAX 4411 4412 struct rtw89_completion_data { 4413 bool err; 4414 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 4415 }; 4416 4417 struct rtw89_wait_info { 4418 atomic_t cond; 4419 struct completion completion; 4420 struct rtw89_completion_data data; 4421 }; 4422 4423 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 4424 4425 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 4426 { 4427 init_completion(&wait->completion); 4428 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4429 } 4430 4431 struct rtw89_mac_info { 4432 struct rtw89_dle_info dle_info; 4433 struct rtw89_hfc_param hfc_param; 4434 enum rtw89_qta_mode qta_mode; 4435 u8 rpwm_seq_num; 4436 u8 cpwm_seq_num; 4437 4438 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 4439 struct rtw89_wait_info fw_ofld_wait; 4440 /* see RTW89_PS_WAIT_COND series for wait condition */ 4441 struct rtw89_wait_info ps_wait; 4442 }; 4443 4444 enum rtw89_fwdl_check_type { 4445 RTW89_FWDL_CHECK_FREERTOS_DONE, 4446 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 4447 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 4448 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 4449 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 4450 }; 4451 4452 enum rtw89_fw_type { 4453 RTW89_FW_NORMAL = 1, 4454 RTW89_FW_WOWLAN = 3, 4455 RTW89_FW_NORMAL_CE = 5, 4456 RTW89_FW_BBMCU0 = 64, 4457 RTW89_FW_BBMCU1 = 65, 4458 RTW89_FW_LOGFMT = 255, 4459 }; 4460 4461 enum rtw89_fw_feature { 4462 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 4463 RTW89_FW_FEATURE_SCAN_OFFLOAD, 4464 RTW89_FW_FEATURE_TX_WAKE, 4465 RTW89_FW_FEATURE_CRASH_TRIGGER, 4466 RTW89_FW_FEATURE_NO_PACKET_DROP, 4467 RTW89_FW_FEATURE_NO_DEEP_PS, 4468 RTW89_FW_FEATURE_NO_LPS_PG, 4469 RTW89_FW_FEATURE_BEACON_FILTER, 4470 RTW89_FW_FEATURE_MACID_PAUSE_SLEEP, 4471 RTW89_FW_FEATURE_SCAN_OFFLOAD_BE_V0, 4472 RTW89_FW_FEATURE_WOW_REASON_V1, 4473 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V0, 4474 RTW89_FW_FEATURE_RFK_PRE_NOTIFY_V1, 4475 RTW89_FW_FEATURE_RFK_RXDCK_V0, 4476 RTW89_FW_FEATURE_NO_WOW_CPU_IO_RX, 4477 RTW89_FW_FEATURE_NOTIFY_AP_INFO, 4478 RTW89_FW_FEATURE_CH_INFO_BE_V0, 4479 RTW89_FW_FEATURE_LPS_CH_INFO, 4480 RTW89_FW_FEATURE_NO_PHYCAP_P1, 4481 }; 4482 4483 struct rtw89_fw_suit { 4484 enum rtw89_fw_type type; 4485 const u8 *data; 4486 u32 size; 4487 u8 major_ver; 4488 u8 minor_ver; 4489 u8 sub_ver; 4490 u8 sub_idex; 4491 u16 build_year; 4492 u16 build_mon; 4493 u16 build_date; 4494 u16 build_hour; 4495 u16 build_min; 4496 u8 cmd_ver; 4497 u8 hdr_ver; 4498 u32 commitid; 4499 }; 4500 4501 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 4502 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 4503 #define RTW89_FW_SUIT_VER_CODE(s) \ 4504 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 4505 4506 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 4507 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 4508 (mfw_hdr)->ver.minor, \ 4509 (mfw_hdr)->ver.sub, \ 4510 (mfw_hdr)->ver.idx) 4511 4512 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 4513 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 4514 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 4515 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 4516 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 4517 4518 struct rtw89_fw_req_info { 4519 const struct firmware *firmware; 4520 struct completion completion; 4521 }; 4522 4523 struct rtw89_fw_log { 4524 struct rtw89_fw_suit suit; 4525 bool enable; 4526 u32 last_fmt_id; 4527 u32 fmt_count; 4528 const __le32 *fmt_ids; 4529 const char *(*fmts)[]; 4530 }; 4531 4532 struct rtw89_fw_elm_info { 4533 struct rtw89_phy_table *bb_tbl; 4534 struct rtw89_phy_table *bb_gain; 4535 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 4536 struct rtw89_phy_table *rf_nctl; 4537 struct rtw89_fw_txpwr_track_cfg *txpwr_trk; 4538 struct rtw89_phy_rfk_log_fmt *rfk_log_fmt; 4539 }; 4540 4541 enum rtw89_fw_mss_dev_type { 4542 RTW89_FW_MSS_DEV_TYPE_FWSEC_DEF = 0xF, 4543 RTW89_FW_MSS_DEV_TYPE_FWSEC_INV = 0xFF, 4544 }; 4545 4546 struct rtw89_fw_secure { 4547 bool secure_boot: 1; 4548 bool can_mss_v1: 1; 4549 bool can_mss_v0: 1; 4550 u32 sb_sel_mgn; 4551 u8 mss_dev_type; 4552 u8 mss_cust_idx; 4553 u8 mss_key_num; 4554 u8 mss_idx; /* v0 */ 4555 }; 4556 4557 struct rtw89_fw_info { 4558 struct rtw89_fw_req_info req; 4559 int fw_format; 4560 u8 h2c_seq; 4561 u8 rec_seq; 4562 u8 h2c_counter; 4563 u8 c2h_counter; 4564 struct rtw89_fw_suit normal; 4565 struct rtw89_fw_suit wowlan; 4566 struct rtw89_fw_suit bbmcu0; 4567 struct rtw89_fw_suit bbmcu1; 4568 struct rtw89_fw_log log; 4569 u32 feature_map; 4570 struct rtw89_fw_elm_info elm_info; 4571 struct rtw89_fw_secure sec; 4572 }; 4573 4574 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 4575 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 4576 4577 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 4578 ((_fw)->feature_map |= BIT(_fw_feature)) 4579 4580 struct rtw89_cam_info { 4581 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 4582 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 4583 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 4584 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 4585 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 4586 const struct rtw89_sec_cam_entry *sec_entries[RTW89_MAX_SEC_CAM_NUM]; 4587 }; 4588 4589 enum rtw89_sar_sources { 4590 RTW89_SAR_SOURCE_NONE, 4591 RTW89_SAR_SOURCE_COMMON, 4592 4593 RTW89_SAR_SOURCE_NR, 4594 }; 4595 4596 enum rtw89_sar_subband { 4597 RTW89_SAR_2GHZ_SUBBAND, 4598 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 4599 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 4600 RTW89_SAR_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4601 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4602 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4603 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 4604 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4605 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4606 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 4607 4608 RTW89_SAR_SUBBAND_NR, 4609 }; 4610 4611 struct rtw89_sar_cfg_common { 4612 bool set[RTW89_SAR_SUBBAND_NR]; 4613 s32 cfg[RTW89_SAR_SUBBAND_NR]; 4614 }; 4615 4616 struct rtw89_sar_info { 4617 /* used to decide how to acces SAR cfg union */ 4618 enum rtw89_sar_sources src; 4619 4620 /* reserved for different knids of SAR cfg struct. 4621 * supposed that a single cfg struct cannot handle various SAR sources. 4622 */ 4623 union { 4624 struct rtw89_sar_cfg_common cfg_common; 4625 }; 4626 }; 4627 4628 enum rtw89_ant_gain_subband { 4629 RTW89_ANT_GAIN_2GHZ_SUBBAND, 4630 RTW89_ANT_GAIN_5GHZ_SUBBAND_1, /* U-NII-1 */ 4631 RTW89_ANT_GAIN_5GHZ_SUBBAND_2, /* U-NII-2 */ 4632 RTW89_ANT_GAIN_5GHZ_SUBBAND_2E, /* U-NII-2-Extended */ 4633 RTW89_ANT_GAIN_5GHZ_SUBBAND_3_4, /* U-NII-3 and U-NII-4 */ 4634 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 4635 RTW89_ANT_GAIN_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 4636 RTW89_ANT_GAIN_6GHZ_SUBBAND_6, /* U-NII-6 */ 4637 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 4638 RTW89_ANT_GAIN_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 4639 RTW89_ANT_GAIN_6GHZ_SUBBAND_8, /* U-NII-8 */ 4640 4641 RTW89_ANT_GAIN_SUBBAND_NR, 4642 }; 4643 4644 enum rtw89_ant_gain_domain_type { 4645 RTW89_ANT_GAIN_ETSI = 0, 4646 4647 RTW89_ANT_GAIN_DOMAIN_NUM, 4648 }; 4649 4650 #define RTW89_ANT_GAIN_CHAIN_NUM 2 4651 struct rtw89_ant_gain_info { 4652 s8 offset[RTW89_ANT_GAIN_CHAIN_NUM][RTW89_ANT_GAIN_SUBBAND_NR]; 4653 u32 regd_enabled; 4654 }; 4655 4656 struct rtw89_6ghz_span { 4657 enum rtw89_sar_subband sar_subband_low; 4658 enum rtw89_sar_subband sar_subband_high; 4659 enum rtw89_ant_gain_subband ant_gain_subband_low; 4660 enum rtw89_ant_gain_subband ant_gain_subband_high; 4661 }; 4662 4663 #define RTW89_SAR_SPAN_VALID(span) ((span)->sar_subband_high) 4664 #define RTW89_ANT_GAIN_SPAN_VALID(span) ((span)->ant_gain_subband_high) 4665 4666 enum rtw89_tas_state { 4667 RTW89_TAS_STATE_DPR_OFF, 4668 RTW89_TAS_STATE_DPR_ON, 4669 RTW89_TAS_STATE_DPR_FORBID, 4670 }; 4671 4672 #define RTW89_TAS_MAX_WINDOW 50 4673 struct rtw89_tas_info { 4674 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 4675 s32 total_txpwr; 4676 u8 cur_idx; 4677 s8 dpr_gap; 4678 s8 delta; 4679 enum rtw89_tas_state state; 4680 bool enable; 4681 }; 4682 4683 struct rtw89_chanctx_cfg { 4684 enum rtw89_chanctx_idx idx; 4685 int ref_count; 4686 }; 4687 4688 enum rtw89_chanctx_changes { 4689 RTW89_CHANCTX_REMOTE_STA_CHANGE, 4690 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 4691 RTW89_CHANCTX_P2P_PS_CHANGE, 4692 RTW89_CHANCTX_BT_SLOT_CHANGE, 4693 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 4694 4695 NUM_OF_RTW89_CHANCTX_CHANGES, 4696 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 4697 }; 4698 4699 enum rtw89_entity_mode { 4700 RTW89_ENTITY_MODE_SCC_OR_SMLD, 4701 RTW89_ENTITY_MODE_MCC_PREPARE, 4702 RTW89_ENTITY_MODE_MCC, 4703 4704 NUM_OF_RTW89_ENTITY_MODE, 4705 RTW89_ENTITY_MODE_INVALID = -EINVAL, 4706 RTW89_ENTITY_MODE_UNHANDLED = -ESRCH, 4707 }; 4708 4709 #define RTW89_MAX_INTERFACE_NUM 2 4710 4711 /* only valid when running with chanctx_ops */ 4712 struct rtw89_entity_mgnt { 4713 struct list_head active_list; 4714 struct rtw89_vif *active_roles[RTW89_MAX_INTERFACE_NUM]; 4715 enum rtw89_chanctx_idx chanctx_tbl[RTW89_MAX_INTERFACE_NUM] 4716 [__RTW89_MLD_MAX_LINK_NUM]; 4717 }; 4718 4719 struct rtw89_chanctx { 4720 struct cfg80211_chan_def chandef; 4721 struct rtw89_chan chan; 4722 struct rtw89_chan_rcd rcd; 4723 4724 /* only assigned when running with chanctx_ops */ 4725 struct rtw89_chanctx_cfg *cfg; 4726 }; 4727 4728 struct rtw89_edcca_bak { 4729 u8 a; 4730 u8 p; 4731 u8 ppdu; 4732 u8 th_old; 4733 }; 4734 4735 enum rtw89_dm_type { 4736 RTW89_DM_DYNAMIC_EDCCA, 4737 RTW89_DM_THERMAL_PROTECT, 4738 }; 4739 4740 #define RTW89_THERMAL_PROT_LV_MAX 5 4741 #define RTW89_THERMAL_PROT_STEP 5 /* -5% for each level */ 4742 4743 struct rtw89_hal { 4744 u32 rx_fltr; 4745 u8 cv; 4746 u8 acv; 4747 u32 antenna_tx; 4748 u32 antenna_rx; 4749 u8 tx_nss; 4750 u8 rx_nss; 4751 bool tx_path_diversity; 4752 bool ant_diversity; 4753 bool ant_diversity_fixed; 4754 bool support_cckpd; 4755 bool support_igi; 4756 bool no_mcs_12_13; 4757 4758 atomic_t roc_chanctx_idx; 4759 4760 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 4761 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_CHANCTX); 4762 struct rtw89_chanctx chanctx[NUM_OF_RTW89_CHANCTX]; 4763 struct cfg80211_chan_def roc_chandef; 4764 4765 bool entity_active[RTW89_PHY_MAX]; 4766 bool entity_pause; 4767 enum rtw89_entity_mode entity_mode; 4768 struct rtw89_entity_mgnt entity_mgnt; 4769 4770 struct rtw89_edcca_bak edcca_bak; 4771 u32 disabled_dm_bitmap; /* bitmap of enum rtw89_dm_type */ 4772 4773 u8 thermal_prot_th; 4774 u8 thermal_prot_lv; /* 0 ~ RTW89_THERMAL_PROT_LV_MAX */ 4775 }; 4776 4777 #define RTW89_MAX_MAC_ID_NUM 128 4778 #define RTW89_MAX_PKT_OFLD_NUM 255 4779 4780 enum rtw89_flags { 4781 RTW89_FLAG_POWERON, 4782 RTW89_FLAG_DMAC_FUNC, 4783 RTW89_FLAG_CMAC0_FUNC, 4784 RTW89_FLAG_CMAC1_FUNC, 4785 RTW89_FLAG_FW_RDY, 4786 RTW89_FLAG_RUNNING, 4787 RTW89_FLAG_PROBE_DONE, 4788 RTW89_FLAG_BFEE_MON, 4789 RTW89_FLAG_BFEE_EN, 4790 RTW89_FLAG_BFEE_TIMER_KEEP, 4791 RTW89_FLAG_NAPI_RUNNING, 4792 RTW89_FLAG_LEISURE_PS, 4793 RTW89_FLAG_LOW_POWER_MODE, 4794 RTW89_FLAG_INACTIVE_PS, 4795 RTW89_FLAG_CRASH_SIMULATING, 4796 RTW89_FLAG_SER_HANDLING, 4797 RTW89_FLAG_WOWLAN, 4798 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4799 RTW89_FLAG_CHANGING_INTERFACE, 4800 RTW89_FLAG_HW_RFKILL_STATE, 4801 4802 NUM_OF_RTW89_FLAGS, 4803 }; 4804 4805 enum rtw89_quirks { 4806 RTW89_QUIRK_PCI_BER, 4807 RTW89_QUIRK_THERMAL_PROT_120C, 4808 RTW89_QUIRK_THERMAL_PROT_110C, 4809 4810 NUM_OF_RTW89_QUIRKS, 4811 }; 4812 4813 enum rtw89_custid { 4814 RTW89_CUSTID_NONE, 4815 RTW89_CUSTID_ACER, 4816 RTW89_CUSTID_AMD, 4817 RTW89_CUSTID_ASUS, 4818 RTW89_CUSTID_DELL, 4819 RTW89_CUSTID_HP, 4820 RTW89_CUSTID_LENOVO, 4821 }; 4822 4823 enum rtw89_pkt_drop_sel { 4824 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4825 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4826 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4827 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4828 RTW89_PKT_DROP_SEL_MACID_ALL, 4829 RTW89_PKT_DROP_SEL_MG0_ONCE, 4830 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4831 RTW89_PKT_DROP_SEL_HIQ_PORT, 4832 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4833 RTW89_PKT_DROP_SEL_BAND, 4834 RTW89_PKT_DROP_SEL_BAND_ONCE, 4835 RTW89_PKT_DROP_SEL_REL_MACID, 4836 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4837 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4838 }; 4839 4840 struct rtw89_pkt_drop_params { 4841 enum rtw89_pkt_drop_sel sel; 4842 enum rtw89_mac_idx mac_band; 4843 u8 macid; 4844 u8 port; 4845 u8 mbssid; 4846 bool tf_trs; 4847 u32 macid_band_sel[4]; 4848 }; 4849 4850 struct rtw89_pkt_stat { 4851 u16 beacon_nr; 4852 u8 beacon_rate; 4853 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4854 }; 4855 4856 DECLARE_EWMA(thermal, 4, 4); 4857 4858 struct rtw89_phy_stat { 4859 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4860 u8 last_thermal_max; 4861 struct ewma_rssi bcn_rssi; 4862 struct rtw89_pkt_stat cur_pkt_stat; 4863 struct rtw89_pkt_stat last_pkt_stat; 4864 }; 4865 4866 enum rtw89_rfk_report_state { 4867 RTW89_RFK_STATE_START = 0x0, 4868 RTW89_RFK_STATE_OK = 0x1, 4869 RTW89_RFK_STATE_FAIL = 0x2, 4870 RTW89_RFK_STATE_TIMEOUT = 0x3, 4871 RTW89_RFK_STATE_H2C_CMD_ERR = 0x4, 4872 }; 4873 4874 struct rtw89_rfk_wait_info { 4875 struct completion completion; 4876 ktime_t start_time; 4877 enum rtw89_rfk_report_state state; 4878 u8 version; 4879 }; 4880 4881 #define RTW89_DACK_PATH_NR 2 4882 #define RTW89_DACK_IDX_NR 2 4883 #define RTW89_DACK_MSBK_NR 16 4884 struct rtw89_dack_info { 4885 bool dack_done; 4886 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4887 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4888 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4889 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4890 u32 dack_cnt; 4891 bool addck_timeout[RTW89_DACK_PATH_NR]; 4892 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4893 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4894 }; 4895 4896 enum rtw89_rfk_chs_nrs { 4897 __RTW89_RFK_CHS_NR_V0 = 2, 4898 __RTW89_RFK_CHS_NR_V1 = 3, 4899 4900 RTW89_RFK_CHS_NR = __RTW89_RFK_CHS_NR_V1, 4901 }; 4902 4903 struct rtw89_rfk_mcc_info_data { 4904 u8 ch[RTW89_RFK_CHS_NR]; 4905 u8 band[RTW89_RFK_CHS_NR]; 4906 u8 bw[RTW89_RFK_CHS_NR]; 4907 u8 table_idx; 4908 }; 4909 4910 struct rtw89_rfk_mcc_info { 4911 struct rtw89_rfk_mcc_info_data data[2]; 4912 }; 4913 4914 #define RTW89_IQK_CHS_NR 2 4915 #define RTW89_IQK_PATH_NR 4 4916 4917 struct rtw89_lck_info { 4918 u8 thermal[RF_PATH_MAX]; 4919 }; 4920 4921 struct rtw89_rx_dck_info { 4922 u8 thermal[RF_PATH_MAX]; 4923 }; 4924 4925 struct rtw89_iqk_info { 4926 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4927 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4928 bool lok_fail[RTW89_IQK_PATH_NR]; 4929 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4930 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4931 u32 iqk_fail_cnt; 4932 bool is_iqk_init; 4933 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4934 u8 iqk_band[RTW89_IQK_PATH_NR]; 4935 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4936 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4937 u8 iqk_times; 4938 u8 version; 4939 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4940 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4941 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4942 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4943 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4944 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4945 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4946 bool is_nbiqk; 4947 bool iqk_fft_en; 4948 bool iqk_xym_en; 4949 bool iqk_sram_en; 4950 bool iqk_cfir_en; 4951 u32 syn1to2; 4952 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4953 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4954 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4955 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4956 }; 4957 4958 #define RTW89_DPK_RF_PATH 2 4959 #define RTW89_DPK_AVG_THERMAL_NUM 8 4960 #define RTW89_DPK_BKUP_NUM 2 4961 struct rtw89_dpk_bkup_para { 4962 enum rtw89_band band; 4963 enum rtw89_bandwidth bw; 4964 u8 ch; 4965 bool path_ok; 4966 u8 mdpd_en; 4967 u8 txagc_dpk; 4968 u8 ther_dpk; 4969 u8 gs; 4970 u16 pwsf; 4971 }; 4972 4973 struct rtw89_dpk_info { 4974 bool is_dpk_enable; 4975 bool is_dpk_reload_en; 4976 u8 dpk_gs[RTW89_PHY_MAX]; 4977 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4978 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4979 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4980 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4981 u8 cur_idx[RTW89_DPK_RF_PATH]; 4982 u8 cur_k_set; 4983 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4984 u8 max_dpk_txagc[RTW89_DPK_RF_PATH]; 4985 u32 dpk_order[RTW89_DPK_RF_PATH]; 4986 }; 4987 4988 struct rtw89_fem_info { 4989 bool elna_2g; 4990 bool elna_5g; 4991 bool epa_2g; 4992 bool epa_5g; 4993 bool epa_6g; 4994 }; 4995 4996 struct rtw89_phy_ch_info { 4997 u8 rssi_min; 4998 u16 rssi_min_macid; 4999 u8 pre_rssi_min; 5000 u8 rssi_max; 5001 u16 rssi_max_macid; 5002 u8 rxsc_160; 5003 u8 rxsc_80; 5004 u8 rxsc_40; 5005 u8 rxsc_20; 5006 u8 rxsc_l; 5007 u8 is_noisy; 5008 }; 5009 5010 struct rtw89_agc_gaincode_set { 5011 u8 lna_idx; 5012 u8 tia_idx; 5013 u8 rxb_idx; 5014 }; 5015 5016 #define IGI_RSSI_TH_NUM 5 5017 #define FA_TH_NUM 4 5018 #define TIA_LNA_OP1DB_NUM 8 5019 #define LNA_GAIN_NUM 7 5020 #define TIA_GAIN_NUM 2 5021 struct rtw89_dig_info { 5022 struct rtw89_agc_gaincode_set cur_gaincode; 5023 bool force_gaincode_idx_en; 5024 struct rtw89_agc_gaincode_set force_gaincode; 5025 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 5026 u16 fa_th[FA_TH_NUM]; 5027 u8 igi_rssi; 5028 u8 igi_fa_rssi; 5029 u8 fa_rssi_ofst; 5030 u8 dyn_igi_max; 5031 u8 dyn_igi_min; 5032 bool dyn_pd_th_en; 5033 u8 dyn_pd_th_max; 5034 u8 pd_low_th_ofst; 5035 u8 ib_pbk; 5036 s8 ib_pkpwr; 5037 s8 lna_gain_a[LNA_GAIN_NUM]; 5038 s8 lna_gain_g[LNA_GAIN_NUM]; 5039 s8 *lna_gain; 5040 s8 tia_gain_a[TIA_GAIN_NUM]; 5041 s8 tia_gain_g[TIA_GAIN_NUM]; 5042 s8 *tia_gain; 5043 bool is_linked_pre; 5044 bool bypass_dig; 5045 }; 5046 5047 enum rtw89_multi_cfo_mode { 5048 RTW89_PKT_BASED_AVG_MODE = 0, 5049 RTW89_ENTRY_BASED_AVG_MODE = 1, 5050 RTW89_TP_BASED_AVG_MODE = 2, 5051 }; 5052 5053 enum rtw89_phy_cfo_status { 5054 RTW89_PHY_DCFO_STATE_NORMAL = 0, 5055 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 5056 RTW89_PHY_DCFO_STATE_HOLD = 2, 5057 RTW89_PHY_DCFO_STATE_MAX 5058 }; 5059 5060 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 5061 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 5062 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 5063 }; 5064 5065 struct rtw89_cfo_tracking_info { 5066 u16 cfo_timer_ms; 5067 bool cfo_trig_by_timer_en; 5068 enum rtw89_phy_cfo_status phy_cfo_status; 5069 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 5070 u8 phy_cfo_trk_cnt; 5071 bool is_adjust; 5072 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 5073 bool apply_compensation; 5074 u8 crystal_cap; 5075 u8 crystal_cap_default; 5076 u8 def_x_cap; 5077 s8 x_cap_ofst; 5078 u32 sta_cfo_tolerance; 5079 s32 cfo_tail[CFO_TRACK_MAX_USER]; 5080 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 5081 s32 cfo_avg_pre; 5082 s32 cfo_avg[CFO_TRACK_MAX_USER]; 5083 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 5084 s32 dcfo_avg; 5085 s32 dcfo_avg_pre; 5086 u32 packet_count; 5087 u32 packet_count_pre; 5088 s32 residual_cfo_acc; 5089 u8 phy_cfotrk_state; 5090 u8 phy_cfotrk_cnt; 5091 bool divergence_lock_en; 5092 u8 x_cap_lb; 5093 u8 x_cap_ub; 5094 u8 lock_cnt; 5095 }; 5096 5097 enum rtw89_tssi_mode { 5098 RTW89_TSSI_NORMAL = 0, 5099 RTW89_TSSI_SCAN = 1, 5100 }; 5101 5102 enum rtw89_tssi_alimk_band { 5103 TSSI_ALIMK_2G = 0, 5104 TSSI_ALIMK_5GL, 5105 TSSI_ALIMK_5GM, 5106 TSSI_ALIMK_5GH, 5107 TSSI_ALIMK_MAX 5108 }; 5109 5110 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 5111 #define TSSI_TRIM_CH_GROUP_NUM 8 5112 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 5113 5114 #define TSSI_CCK_CH_GROUP_NUM 6 5115 #define TSSI_MCS_2G_CH_GROUP_NUM 5 5116 #define TSSI_MCS_5G_CH_GROUP_NUM 14 5117 #define TSSI_MCS_6G_CH_GROUP_NUM 32 5118 #define TSSI_MCS_CH_GROUP_NUM \ 5119 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 5120 #define TSSI_MAX_CH_NUM 67 5121 #define TSSI_ALIMK_VALUE_NUM 8 5122 5123 struct rtw89_tssi_info { 5124 u8 thermal[RF_PATH_MAX]; 5125 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 5126 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 5127 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 5128 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 5129 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 5130 s8 extra_ofst[RF_PATH_MAX]; 5131 bool tssi_tracking_check[RF_PATH_MAX]; 5132 u8 default_txagc_offset[RF_PATH_MAX]; 5133 u32 base_thermal[RF_PATH_MAX]; 5134 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 5135 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 5136 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 5137 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 5138 u32 tssi_alimk_time; 5139 }; 5140 5141 struct rtw89_power_trim_info { 5142 bool pg_thermal_trim; 5143 bool pg_pa_bias_trim; 5144 u8 thermal_trim[RF_PATH_MAX]; 5145 u8 pa_bias_trim[RF_PATH_MAX]; 5146 u8 pad_bias_trim[RF_PATH_MAX]; 5147 }; 5148 5149 struct rtw89_regd { 5150 char alpha2[3]; 5151 u8 txpwr_regd[RTW89_BAND_NUM]; 5152 }; 5153 5154 #define RTW89_REGD_MAX_COUNTRY_NUM U8_MAX 5155 #define RTW89_5GHZ_UNII4_CHANNEL_NUM 3 5156 #define RTW89_5GHZ_UNII4_START_INDEX 25 5157 5158 struct rtw89_regulatory_info { 5159 const struct rtw89_regd *regd; 5160 enum rtw89_reg_6ghz_power reg_6ghz_power; 5161 struct rtw89_reg_6ghz_tpe reg_6ghz_tpe; 5162 DECLARE_BITMAP(block_unii4, RTW89_REGD_MAX_COUNTRY_NUM); 5163 DECLARE_BITMAP(block_6ghz, RTW89_REGD_MAX_COUNTRY_NUM); 5164 DECLARE_BITMAP(block_6ghz_sp, RTW89_REGD_MAX_COUNTRY_NUM); 5165 }; 5166 5167 enum rtw89_ifs_clm_application { 5168 RTW89_IFS_CLM_INIT = 0, 5169 RTW89_IFS_CLM_BACKGROUND = 1, 5170 RTW89_IFS_CLM_ACS = 2, 5171 RTW89_IFS_CLM_DIG = 3, 5172 RTW89_IFS_CLM_TDMA_DIG = 4, 5173 RTW89_IFS_CLM_DBG = 5, 5174 RTW89_IFS_CLM_DBG_MANUAL = 6 5175 }; 5176 5177 enum rtw89_env_racing_lv { 5178 RTW89_RAC_RELEASE = 0, 5179 RTW89_RAC_LV_1 = 1, 5180 RTW89_RAC_LV_2 = 2, 5181 RTW89_RAC_LV_3 = 3, 5182 RTW89_RAC_LV_4 = 4, 5183 RTW89_RAC_MAX_NUM = 5 5184 }; 5185 5186 struct rtw89_ccx_para_info { 5187 enum rtw89_env_racing_lv rac_lv; 5188 u16 mntr_time; 5189 u8 nhm_manual_th_ofst; 5190 u8 nhm_manual_th0; 5191 enum rtw89_ifs_clm_application ifs_clm_app; 5192 u32 ifs_clm_manual_th_times; 5193 u32 ifs_clm_manual_th0; 5194 u8 fahm_manual_th_ofst; 5195 u8 fahm_manual_th0; 5196 u8 fahm_numer_opt; 5197 u8 fahm_denom_opt; 5198 }; 5199 5200 enum rtw89_ccx_edcca_opt_sc_idx { 5201 RTW89_CCX_EDCCA_SEG0_P0 = 0, 5202 RTW89_CCX_EDCCA_SEG0_S1 = 1, 5203 RTW89_CCX_EDCCA_SEG0_S2 = 2, 5204 RTW89_CCX_EDCCA_SEG0_S3 = 3, 5205 RTW89_CCX_EDCCA_SEG1_P0 = 4, 5206 RTW89_CCX_EDCCA_SEG1_S1 = 5, 5207 RTW89_CCX_EDCCA_SEG1_S2 = 6, 5208 RTW89_CCX_EDCCA_SEG1_S3 = 7 5209 }; 5210 5211 enum rtw89_ccx_edcca_opt_bw_idx { 5212 RTW89_CCX_EDCCA_BW20_0 = 0, 5213 RTW89_CCX_EDCCA_BW20_1 = 1, 5214 RTW89_CCX_EDCCA_BW20_2 = 2, 5215 RTW89_CCX_EDCCA_BW20_3 = 3, 5216 RTW89_CCX_EDCCA_BW20_4 = 4, 5217 RTW89_CCX_EDCCA_BW20_5 = 5, 5218 RTW89_CCX_EDCCA_BW20_6 = 6, 5219 RTW89_CCX_EDCCA_BW20_7 = 7 5220 }; 5221 5222 #define RTW89_NHM_TH_NUM 11 5223 #define RTW89_FAHM_TH_NUM 11 5224 #define RTW89_NHM_RPT_NUM 12 5225 #define RTW89_FAHM_RPT_NUM 12 5226 #define RTW89_IFS_CLM_NUM 4 5227 struct rtw89_env_monitor_info { 5228 u8 ccx_watchdog_result; 5229 bool ccx_ongoing; 5230 u8 ccx_rac_lv; 5231 bool ccx_manual_ctrl; 5232 u16 ifs_clm_mntr_time; 5233 enum rtw89_ifs_clm_application ifs_clm_app; 5234 u16 ccx_period; 5235 u8 ccx_unit_idx; 5236 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 5237 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 5238 u16 ifs_clm_tx; 5239 u16 ifs_clm_edcca_excl_cca; 5240 u16 ifs_clm_ofdmfa; 5241 u16 ifs_clm_ofdmcca_excl_fa; 5242 u16 ifs_clm_cckfa; 5243 u16 ifs_clm_cckcca_excl_fa; 5244 u16 ifs_clm_total_ifs; 5245 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 5246 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 5247 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 5248 u8 ifs_clm_tx_ratio; 5249 u8 ifs_clm_edcca_excl_cca_ratio; 5250 u8 ifs_clm_cck_fa_ratio; 5251 u8 ifs_clm_ofdm_fa_ratio; 5252 u8 ifs_clm_cck_cca_excl_fa_ratio; 5253 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 5254 u16 ifs_clm_cck_fa_permil; 5255 u16 ifs_clm_ofdm_fa_permil; 5256 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 5257 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 5258 }; 5259 5260 enum rtw89_ser_rcvy_step { 5261 RTW89_SER_DRV_STOP_TX, 5262 RTW89_SER_DRV_STOP_RX, 5263 RTW89_SER_DRV_STOP_RUN, 5264 RTW89_SER_HAL_STOP_DMA, 5265 RTW89_SER_SUPPRESS_LOG, 5266 RTW89_NUM_OF_SER_FLAGS 5267 }; 5268 5269 struct rtw89_ser { 5270 u8 state; 5271 u8 alarm_event; 5272 bool prehandle_l1; 5273 5274 struct work_struct ser_hdl_work; 5275 struct delayed_work ser_alarm_work; 5276 const struct state_ent *st_tbl; 5277 const struct event_ent *ev_tbl; 5278 struct list_head msg_q; 5279 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 5280 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 5281 }; 5282 5283 enum rtw89_mac_ax_ps_mode { 5284 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 5285 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 5286 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 5287 RTW89_MAC_AX_PS_MODE_MAX = 3, 5288 }; 5289 5290 enum rtw89_last_rpwm_mode { 5291 RTW89_LAST_RPWM_PS = 0x0, 5292 RTW89_LAST_RPWM_ACTIVE = 0x6, 5293 }; 5294 5295 struct rtw89_lps_parm { 5296 u8 macid; 5297 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 5298 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 5299 }; 5300 5301 struct rtw89_ppdu_sts_info { 5302 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 5303 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 5304 }; 5305 5306 struct rtw89_early_h2c { 5307 struct list_head list; 5308 u8 *h2c; 5309 u16 h2c_len; 5310 }; 5311 5312 struct rtw89_hw_scan_info { 5313 struct rtw89_vif_link *scanning_vif; 5314 struct list_head pkt_list[NUM_NL80211_BANDS]; 5315 struct rtw89_chan op_chan; 5316 bool abort; 5317 u32 last_chan_idx; 5318 }; 5319 5320 enum rtw89_phy_bb_gain_band { 5321 RTW89_BB_GAIN_BAND_2G = 0, 5322 RTW89_BB_GAIN_BAND_5G_L = 1, 5323 RTW89_BB_GAIN_BAND_5G_M = 2, 5324 RTW89_BB_GAIN_BAND_5G_H = 3, 5325 RTW89_BB_GAIN_BAND_6G_L = 4, 5326 RTW89_BB_GAIN_BAND_6G_M = 5, 5327 RTW89_BB_GAIN_BAND_6G_H = 6, 5328 RTW89_BB_GAIN_BAND_6G_UH = 7, 5329 5330 RTW89_BB_GAIN_BAND_NR, 5331 }; 5332 5333 enum rtw89_phy_gain_band_be { 5334 RTW89_BB_GAIN_BAND_2G_BE = 0, 5335 RTW89_BB_GAIN_BAND_5G_L_BE = 1, 5336 RTW89_BB_GAIN_BAND_5G_M_BE = 2, 5337 RTW89_BB_GAIN_BAND_5G_H_BE = 3, 5338 RTW89_BB_GAIN_BAND_6G_L0_BE = 4, 5339 RTW89_BB_GAIN_BAND_6G_L1_BE = 5, 5340 RTW89_BB_GAIN_BAND_6G_M0_BE = 6, 5341 RTW89_BB_GAIN_BAND_6G_M1_BE = 7, 5342 RTW89_BB_GAIN_BAND_6G_H0_BE = 8, 5343 RTW89_BB_GAIN_BAND_6G_H1_BE = 9, 5344 RTW89_BB_GAIN_BAND_6G_UH0_BE = 10, 5345 RTW89_BB_GAIN_BAND_6G_UH1_BE = 11, 5346 5347 RTW89_BB_GAIN_BAND_NR_BE, 5348 }; 5349 5350 enum rtw89_phy_bb_bw_be { 5351 RTW89_BB_BW_20_40 = 0, 5352 RTW89_BB_BW_80_160_320 = 1, 5353 5354 RTW89_BB_BW_NR_BE, 5355 }; 5356 5357 enum rtw89_bw20_sc { 5358 RTW89_BW20_SC_20M = 1, 5359 RTW89_BW20_SC_40M = 2, 5360 RTW89_BW20_SC_80M = 4, 5361 RTW89_BW20_SC_160M = 8, 5362 RTW89_BW20_SC_320M = 16, 5363 }; 5364 5365 enum rtw89_cmac_table_bw { 5366 RTW89_CMAC_BW_20M = 0, 5367 RTW89_CMAC_BW_40M = 1, 5368 RTW89_CMAC_BW_80M = 2, 5369 RTW89_CMAC_BW_160M = 3, 5370 RTW89_CMAC_BW_320M = 4, 5371 5372 RTW89_CMAC_BW_NR, 5373 }; 5374 5375 enum rtw89_phy_bb_rxsc_num { 5376 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 5377 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 5378 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 5379 }; 5380 5381 struct rtw89_phy_bb_gain_info { 5382 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5383 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 5384 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5385 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 5386 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5387 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 5388 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 5389 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5390 [RTW89_BB_RXSC_NUM_40]; 5391 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5392 [RTW89_BB_RXSC_NUM_80]; 5393 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 5394 [RTW89_BB_RXSC_NUM_160]; 5395 }; 5396 5397 struct rtw89_phy_bb_gain_info_be { 5398 s8 lna_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5399 [LNA_GAIN_NUM]; 5400 s8 tia_gain[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE][RF_PATH_MAX] 5401 [TIA_GAIN_NUM]; 5402 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5403 [RF_PATH_MAX][LNA_GAIN_NUM]; 5404 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5405 [RF_PATH_MAX][LNA_GAIN_NUM]; 5406 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR_BE][RTW89_BB_BW_NR_BE] 5407 [RF_PATH_MAX][LNA_GAIN_NUM + 1]; 5408 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5409 [RTW89_BW20_SC_20M]; 5410 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5411 [RTW89_BW20_SC_40M]; 5412 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5413 [RTW89_BW20_SC_80M]; 5414 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR_BE][RF_PATH_MAX] 5415 [RTW89_BW20_SC_160M]; 5416 }; 5417 5418 struct rtw89_phy_efuse_gain { 5419 bool offset_valid; 5420 bool comp_valid; 5421 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 5422 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5423 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 5424 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 5425 }; 5426 5427 #define RTW89_MAX_PATTERN_NUM 18 5428 #define RTW89_MAX_PATTERN_MASK_SIZE 4 5429 #define RTW89_MAX_PATTERN_SIZE 128 5430 5431 struct rtw89_wow_cam_info { 5432 bool r_w; 5433 u8 idx; 5434 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 5435 u16 crc; 5436 bool negative_pattern_match; 5437 bool skip_mac_hdr; 5438 bool uc; 5439 bool mc; 5440 bool bc; 5441 bool valid; 5442 }; 5443 5444 struct rtw89_wow_key_info { 5445 u8 ptk_tx_iv[8]; 5446 u8 valid_check; 5447 u8 symbol_check_en; 5448 u8 gtk_keyidx; 5449 u8 rsvd[5]; 5450 u8 ptk_rx_iv[8]; 5451 u8 gtk_rx_iv[4][8]; 5452 } __packed; 5453 5454 struct rtw89_wow_gtk_info { 5455 u8 kck[32]; 5456 u8 kek[32]; 5457 u8 tk1[16]; 5458 u8 txmickey[8]; 5459 u8 rxmickey[8]; 5460 __le32 igtk_keyid; 5461 __le64 ipn; 5462 u8 igtk[2][32]; 5463 u8 psk[32]; 5464 } __packed; 5465 5466 struct rtw89_wow_aoac_report { 5467 u8 rpt_ver; 5468 u8 sec_type; 5469 u8 key_idx; 5470 u8 pattern_idx; 5471 u8 rekey_ok; 5472 u8 ptk_tx_iv[8]; 5473 u8 eapol_key_replay_count[8]; 5474 u8 gtk[32]; 5475 u8 ptk_rx_iv[8]; 5476 u8 gtk_rx_iv[4][8]; 5477 u64 igtk_key_id; 5478 u64 igtk_ipn; 5479 u8 igtk[32]; 5480 u8 csa_pri_ch; 5481 u8 csa_bw; 5482 u8 csa_ch_offset; 5483 u8 csa_chsw_failed; 5484 u8 csa_ch_band; 5485 }; 5486 5487 struct rtw89_wow_param { 5488 struct rtw89_vif_link *rtwvif_link; 5489 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 5490 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 5491 struct rtw89_wow_key_info key_info; 5492 struct rtw89_wow_gtk_info gtk_info; 5493 struct rtw89_wow_aoac_report aoac_rpt; 5494 u8 pattern_cnt; 5495 u8 ptk_alg; 5496 u8 gtk_alg; 5497 u8 ptk_keyidx; 5498 u8 akm; 5499 5500 /* see RTW89_WOW_WAIT_COND series for wait condition */ 5501 struct rtw89_wait_info wait; 5502 5503 bool pno_inited; 5504 struct list_head pno_pkt_list; 5505 struct cfg80211_sched_scan_request *nd_config; 5506 }; 5507 5508 struct rtw89_mcc_limit { 5509 bool enable; 5510 u16 max_tob; /* TU; max time offset behind */ 5511 u16 max_toa; /* TU; max time offset ahead */ 5512 u16 max_dur; /* TU */ 5513 }; 5514 5515 struct rtw89_mcc_policy { 5516 u8 c2h_rpt; 5517 u8 tx_null_early; 5518 u8 dis_tx_null; 5519 u8 in_curr_ch; 5520 u8 dis_sw_retry; 5521 u8 sw_retry_count; 5522 }; 5523 5524 struct rtw89_mcc_role { 5525 struct rtw89_vif_link *rtwvif_link; 5526 struct rtw89_mcc_policy policy; 5527 struct rtw89_mcc_limit limit; 5528 5529 /* only valid when running with FW MRC mechanism */ 5530 u8 slot_idx; 5531 5532 /* byte-array in LE order for FW */ 5533 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 5534 5535 u16 duration; /* TU */ 5536 u16 beacon_interval; /* TU */ 5537 bool is_2ghz; 5538 bool is_go; 5539 bool is_gc; 5540 }; 5541 5542 struct rtw89_mcc_bt_role { 5543 u16 duration; /* TU */ 5544 }; 5545 5546 struct rtw89_mcc_courtesy { 5547 bool enable; 5548 u8 slot_num; 5549 u8 macid_src; 5550 u8 macid_tgt; 5551 }; 5552 5553 enum rtw89_mcc_plan { 5554 RTW89_MCC_PLAN_TAIL_BT, 5555 RTW89_MCC_PLAN_MID_BT, 5556 RTW89_MCC_PLAN_NO_BT, 5557 5558 NUM_OF_RTW89_MCC_PLAN, 5559 }; 5560 5561 struct rtw89_mcc_pattern { 5562 s16 tob_ref; /* TU; time offset behind of reference role */ 5563 s16 toa_ref; /* TU; time offset ahead of reference role */ 5564 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 5565 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 5566 5567 enum rtw89_mcc_plan plan; 5568 struct rtw89_mcc_courtesy courtesy; 5569 }; 5570 5571 struct rtw89_mcc_sync { 5572 bool enable; 5573 u16 offset; /* TU */ 5574 u8 macid_src; 5575 u8 band_src; 5576 u8 port_src; 5577 u8 macid_tgt; 5578 u8 band_tgt; 5579 u8 port_tgt; 5580 }; 5581 5582 struct rtw89_mcc_config { 5583 struct rtw89_mcc_pattern pattern; 5584 struct rtw89_mcc_sync sync; 5585 u64 start_tsf; 5586 u16 mcc_interval; /* TU */ 5587 u16 beacon_offset; /* TU */ 5588 }; 5589 5590 enum rtw89_mcc_mode { 5591 RTW89_MCC_MODE_GO_STA, 5592 RTW89_MCC_MODE_GC_STA, 5593 }; 5594 5595 struct rtw89_mcc_info { 5596 struct rtw89_wait_info wait; 5597 5598 u8 group; 5599 enum rtw89_mcc_mode mode; 5600 struct rtw89_mcc_role role_ref; /* reference role */ 5601 struct rtw89_mcc_role role_aux; /* auxiliary role */ 5602 struct rtw89_mcc_bt_role bt_role; 5603 struct rtw89_mcc_config config; 5604 }; 5605 5606 struct rtw89_dev { 5607 struct ieee80211_hw *hw; 5608 struct device *dev; 5609 const struct ieee80211_ops *ops; 5610 5611 bool dbcc_en; 5612 bool support_mlo; 5613 enum rtw89_mlo_dbcc_mode mlo_dbcc_mode; 5614 struct rtw89_hw_scan_info scan_info; 5615 const struct rtw89_chip_info *chip; 5616 const struct rtw89_chip_variant *variant; 5617 const struct rtw89_pci_info *pci_info; 5618 const struct rtw89_rfe_parms *rfe_parms; 5619 struct rtw89_hal hal; 5620 struct rtw89_mcc_info mcc; 5621 struct rtw89_mac_info mac; 5622 struct rtw89_fw_info fw; 5623 struct rtw89_hci_info hci; 5624 struct rtw89_efuse efuse; 5625 struct rtw89_traffic_stats stats; 5626 struct rtw89_rfe_data *rfe_data; 5627 enum rtw89_custid custid; 5628 5629 struct rtw89_sta_link __rcu *assoc_link_on_macid[RTW89_MAX_MAC_ID_NUM]; 5630 refcount_t refcount_ap_info; 5631 5632 /* ensures exclusive access from mac80211 callbacks */ 5633 struct mutex mutex; 5634 struct list_head rtwvifs_list; 5635 /* used to protect rf read write */ 5636 struct mutex rf_mutex; 5637 struct workqueue_struct *txq_wq; 5638 struct work_struct txq_work; 5639 struct delayed_work txq_reinvoke_work; 5640 /* used to protect ba_list and forbid_ba_list */ 5641 spinlock_t ba_lock; 5642 /* txqs to setup ba session */ 5643 struct list_head ba_list; 5644 /* txqs to forbid ba session */ 5645 struct list_head forbid_ba_list; 5646 struct work_struct ba_work; 5647 /* used to protect rpwm */ 5648 spinlock_t rpwm_lock; 5649 5650 struct rtw89_cam_info cam_info; 5651 5652 struct sk_buff_head c2h_queue; 5653 struct work_struct c2h_work; 5654 struct work_struct ips_work; 5655 struct work_struct load_firmware_work; 5656 struct work_struct cancel_6ghz_probe_work; 5657 5658 struct list_head early_h2c_list; 5659 5660 struct rtw89_ser ser; 5661 5662 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 5663 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 5664 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 5665 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 5666 DECLARE_BITMAP(quirks, NUM_OF_RTW89_QUIRKS); 5667 5668 struct rtw89_phy_stat phystat; 5669 struct rtw89_rfk_wait_info rfk_wait; 5670 struct rtw89_dack_info dack; 5671 struct rtw89_iqk_info iqk; 5672 struct rtw89_dpk_info dpk; 5673 struct rtw89_rfk_mcc_info rfk_mcc; 5674 struct rtw89_lck_info lck; 5675 struct rtw89_rx_dck_info rx_dck; 5676 bool is_tssi_mode[RF_PATH_MAX]; 5677 bool is_bt_iqk_timeout; 5678 5679 struct rtw89_fem_info fem; 5680 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 5681 struct rtw89_tssi_info tssi; 5682 struct rtw89_power_trim_info pwr_trim; 5683 5684 struct rtw89_cfo_tracking_info cfo_tracking; 5685 struct rtw89_env_monitor_info env_monitor; 5686 struct rtw89_dig_info dig; 5687 struct rtw89_phy_ch_info ch_info; 5688 union { 5689 struct rtw89_phy_bb_gain_info ax; 5690 struct rtw89_phy_bb_gain_info_be be; 5691 } bb_gain; 5692 struct rtw89_phy_efuse_gain efuse_gain; 5693 struct rtw89_phy_ul_tb_info ul_tb_info; 5694 struct rtw89_antdiv_info antdiv; 5695 5696 struct delayed_work track_work; 5697 struct delayed_work chanctx_work; 5698 struct delayed_work coex_act1_work; 5699 struct delayed_work coex_bt_devinfo_work; 5700 struct delayed_work coex_rfk_chk_work; 5701 struct delayed_work cfo_track_work; 5702 struct delayed_work forbid_ba_work; 5703 struct delayed_work roc_work; 5704 struct delayed_work antdiv_work; 5705 struct rtw89_ppdu_sts_info ppdu_sts; 5706 u8 total_sta_assoc; 5707 bool scanning; 5708 5709 struct rtw89_regulatory_info regulatory; 5710 struct rtw89_sar_info sar; 5711 struct rtw89_tas_info tas; 5712 struct rtw89_ant_gain_info ant_gain; 5713 5714 struct rtw89_btc btc; 5715 enum rtw89_ps_mode ps_mode; 5716 bool lps_enabled; 5717 5718 struct rtw89_wow_param wow; 5719 5720 /* napi structure */ 5721 struct net_device *netdev; 5722 struct napi_struct napi; 5723 int napi_budget_countdown; 5724 5725 struct rtw89_debugfs *debugfs; 5726 5727 /* HCI related data, keep last */ 5728 u8 priv[] __aligned(sizeof(void *)); 5729 }; 5730 5731 struct rtw89_link_conf_container { 5732 struct ieee80211_bss_conf *link_conf[IEEE80211_MLD_MAX_NUM_LINKS]; 5733 }; 5734 5735 #define RTW89_VIF_IDLE_LINK_ID 0 5736 5737 struct rtw89_vif { 5738 struct rtw89_dev *rtwdev; 5739 struct list_head list; 5740 struct list_head mgnt_entry; 5741 struct rtw89_link_conf_container __rcu *snap_link_confs; 5742 5743 u8 mac_addr[ETH_ALEN]; 5744 __be32 ip_addr; 5745 5746 struct rtw89_traffic_stats stats; 5747 u32 tdls_peer; 5748 5749 struct ieee80211_scan_ies *scan_ies; 5750 struct cfg80211_scan_request *scan_req; 5751 5752 struct rtw89_roc roc; 5753 bool offchan; 5754 5755 u8 links_inst_valid_num; 5756 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5757 struct rtw89_vif_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5758 struct rtw89_vif_link links_inst[] __counted_by(links_inst_valid_num); 5759 }; 5760 5761 static inline bool rtw89_vif_assign_link_is_valid(struct rtw89_vif_link **rtwvif_link, 5762 const struct rtw89_vif *rtwvif, 5763 unsigned int link_id) 5764 { 5765 *rtwvif_link = rtwvif->links[link_id]; 5766 return !!*rtwvif_link; 5767 } 5768 5769 #define rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) \ 5770 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5771 if (rtw89_vif_assign_link_is_valid(&(rtwvif_link), rtwvif, link_id)) 5772 5773 enum rtw89_sta_flags { 5774 RTW89_REMOTE_STA_IN_PS, 5775 5776 NUM_OF_RTW89_STA_FLAGS, 5777 }; 5778 5779 struct rtw89_sta { 5780 struct rtw89_dev *rtwdev; 5781 struct rtw89_vif *rtwvif; 5782 5783 DECLARE_BITMAP(flags, NUM_OF_RTW89_STA_FLAGS); 5784 5785 bool disassoc; 5786 5787 struct sk_buff_head roc_queue; 5788 5789 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 5790 DECLARE_BITMAP(ampdu_map, IEEE80211_NUM_TIDS); 5791 5792 DECLARE_BITMAP(pairwise_sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 5793 5794 u8 links_inst_valid_num; 5795 DECLARE_BITMAP(links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 5796 struct rtw89_sta_link *links[IEEE80211_MLD_MAX_NUM_LINKS]; 5797 struct rtw89_sta_link links_inst[] __counted_by(links_inst_valid_num); 5798 }; 5799 5800 static inline bool rtw89_sta_assign_link_is_valid(struct rtw89_sta_link **rtwsta_link, 5801 const struct rtw89_sta *rtwsta, 5802 unsigned int link_id) 5803 { 5804 *rtwsta_link = rtwsta->links[link_id]; 5805 return !!*rtwsta_link; 5806 } 5807 5808 #define rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) \ 5809 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) \ 5810 if (rtw89_sta_assign_link_is_valid(&(rtwsta_link), rtwsta, link_id)) 5811 5812 static inline u8 rtw89_vif_get_main_macid(struct rtw89_vif *rtwvif) 5813 { 5814 /* const after init, so no need to check if active first */ 5815 return rtwvif->links_inst[0].mac_id; 5816 } 5817 5818 static inline u8 rtw89_vif_get_main_port(struct rtw89_vif *rtwvif) 5819 { 5820 /* const after init, so no need to check if active first */ 5821 return rtwvif->links_inst[0].port; 5822 } 5823 5824 static inline struct rtw89_vif_link * 5825 rtw89_vif_get_link_inst(struct rtw89_vif *rtwvif, u8 index) 5826 { 5827 if (index >= rtwvif->links_inst_valid_num || 5828 !test_bit(index, rtwvif->links_inst_map)) 5829 return NULL; 5830 return &rtwvif->links_inst[index]; 5831 } 5832 5833 static inline 5834 u8 rtw89_vif_link_inst_get_index(struct rtw89_vif_link *rtwvif_link) 5835 { 5836 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 5837 5838 return rtwvif_link - rtwvif->links_inst; 5839 } 5840 5841 static inline u8 rtw89_sta_get_main_macid(struct rtw89_sta *rtwsta) 5842 { 5843 /* const after init, so no need to check if active first */ 5844 return rtwsta->links_inst[0].mac_id; 5845 } 5846 5847 static inline struct rtw89_sta_link * 5848 rtw89_sta_get_link_inst(struct rtw89_sta *rtwsta, u8 index) 5849 { 5850 if (index >= rtwsta->links_inst_valid_num || 5851 !test_bit(index, rtwsta->links_inst_map)) 5852 return NULL; 5853 return &rtwsta->links_inst[index]; 5854 } 5855 5856 static inline 5857 u8 rtw89_sta_link_inst_get_index(struct rtw89_sta_link *rtwsta_link) 5858 { 5859 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5860 5861 return rtwsta_link - rtwsta->links_inst; 5862 } 5863 5864 static inline void rtw89_assoc_link_set(struct rtw89_sta_link *rtwsta_link) 5865 { 5866 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5867 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5868 5869 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5870 rtwsta_link); 5871 } 5872 5873 static inline void rtw89_assoc_link_clr(struct rtw89_sta_link *rtwsta_link) 5874 { 5875 struct rtw89_sta *rtwsta = rtwsta_link->rtwsta; 5876 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 5877 5878 rcu_assign_pointer(rtwdev->assoc_link_on_macid[rtwsta_link->mac_id], 5879 NULL); 5880 synchronize_rcu(); 5881 } 5882 5883 static inline struct rtw89_sta_link * 5884 rtw89_assoc_link_rcu_dereference(struct rtw89_dev *rtwdev, u8 macid) 5885 { 5886 return rcu_dereference(rtwdev->assoc_link_on_macid[macid]); 5887 } 5888 5889 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 5890 struct rtw89_core_tx_request *tx_req) 5891 { 5892 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 5893 } 5894 5895 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 5896 { 5897 rtwdev->hci.ops->reset(rtwdev); 5898 } 5899 5900 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 5901 { 5902 return rtwdev->hci.ops->start(rtwdev); 5903 } 5904 5905 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 5906 { 5907 rtwdev->hci.ops->stop(rtwdev); 5908 } 5909 5910 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 5911 { 5912 return rtwdev->hci.ops->deinit(rtwdev); 5913 } 5914 5915 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 5916 { 5917 rtwdev->hci.ops->pause(rtwdev, pause); 5918 } 5919 5920 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 5921 { 5922 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 5923 } 5924 5925 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 5926 { 5927 rtwdev->hci.ops->recalc_int_mit(rtwdev); 5928 } 5929 5930 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 5931 { 5932 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 5933 } 5934 5935 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 5936 { 5937 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 5938 } 5939 5940 static inline int rtw89_hci_mac_pre_deinit(struct rtw89_dev *rtwdev) 5941 { 5942 return rtwdev->hci.ops->mac_pre_deinit(rtwdev); 5943 } 5944 5945 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 5946 bool drop) 5947 { 5948 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5949 return; 5950 5951 if (rtwdev->hci.ops->flush_queues) 5952 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 5953 } 5954 5955 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 5956 { 5957 if (rtwdev->hci.ops->recovery_start) 5958 rtwdev->hci.ops->recovery_start(rtwdev); 5959 } 5960 5961 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 5962 { 5963 if (rtwdev->hci.ops->recovery_complete) 5964 rtwdev->hci.ops->recovery_complete(rtwdev); 5965 } 5966 5967 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 5968 { 5969 if (rtwdev->hci.ops->enable_intr) 5970 rtwdev->hci.ops->enable_intr(rtwdev); 5971 } 5972 5973 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 5974 { 5975 if (rtwdev->hci.ops->disable_intr) 5976 rtwdev->hci.ops->disable_intr(rtwdev); 5977 } 5978 5979 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 5980 { 5981 if (rtwdev->hci.ops->ctrl_txdma_ch) 5982 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 5983 } 5984 5985 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 5986 { 5987 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 5988 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 5989 } 5990 5991 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 5992 { 5993 if (rtwdev->hci.ops->ctrl_trxhci) 5994 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 5995 } 5996 5997 static inline int rtw89_hci_poll_txdma_ch_idle(struct rtw89_dev *rtwdev) 5998 { 5999 int ret = 0; 6000 6001 if (rtwdev->hci.ops->poll_txdma_ch_idle) 6002 ret = rtwdev->hci.ops->poll_txdma_ch_idle(rtwdev); 6003 return ret; 6004 } 6005 6006 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 6007 { 6008 if (rtwdev->hci.ops->clr_idx_all) 6009 rtwdev->hci.ops->clr_idx_all(rtwdev); 6010 } 6011 6012 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 6013 { 6014 int ret = 0; 6015 6016 if (rtwdev->hci.ops->rst_bdram) 6017 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 6018 return ret; 6019 } 6020 6021 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 6022 { 6023 if (rtwdev->hci.ops->clear) 6024 rtwdev->hci.ops->clear(rtwdev, pdev); 6025 } 6026 6027 static inline 6028 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 6029 { 6030 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 6031 6032 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 6033 } 6034 6035 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 6036 { 6037 return rtwdev->hci.ops->read8(rtwdev, addr); 6038 } 6039 6040 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 6041 { 6042 return rtwdev->hci.ops->read16(rtwdev, addr); 6043 } 6044 6045 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 6046 { 6047 return rtwdev->hci.ops->read32(rtwdev, addr); 6048 } 6049 6050 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 6051 { 6052 rtwdev->hci.ops->write8(rtwdev, addr, data); 6053 } 6054 6055 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 6056 { 6057 rtwdev->hci.ops->write16(rtwdev, addr, data); 6058 } 6059 6060 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 6061 { 6062 rtwdev->hci.ops->write32(rtwdev, addr, data); 6063 } 6064 6065 static inline void 6066 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6067 { 6068 u8 val; 6069 6070 val = rtw89_read8(rtwdev, addr); 6071 rtw89_write8(rtwdev, addr, val | bit); 6072 } 6073 6074 static inline void 6075 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6076 { 6077 u16 val; 6078 6079 val = rtw89_read16(rtwdev, addr); 6080 rtw89_write16(rtwdev, addr, val | bit); 6081 } 6082 6083 static inline void 6084 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6085 { 6086 u32 val; 6087 6088 val = rtw89_read32(rtwdev, addr); 6089 rtw89_write32(rtwdev, addr, val | bit); 6090 } 6091 6092 static inline void 6093 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 6094 { 6095 u8 val; 6096 6097 val = rtw89_read8(rtwdev, addr); 6098 rtw89_write8(rtwdev, addr, val & ~bit); 6099 } 6100 6101 static inline void 6102 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 6103 { 6104 u16 val; 6105 6106 val = rtw89_read16(rtwdev, addr); 6107 rtw89_write16(rtwdev, addr, val & ~bit); 6108 } 6109 6110 static inline void 6111 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 6112 { 6113 u32 val; 6114 6115 val = rtw89_read32(rtwdev, addr); 6116 rtw89_write32(rtwdev, addr, val & ~bit); 6117 } 6118 6119 static inline u32 6120 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6121 { 6122 u32 shift = __ffs(mask); 6123 u32 orig; 6124 u32 ret; 6125 6126 orig = rtw89_read32(rtwdev, addr); 6127 ret = (orig & mask) >> shift; 6128 6129 return ret; 6130 } 6131 6132 static inline u16 6133 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6134 { 6135 u32 shift = __ffs(mask); 6136 u32 orig; 6137 u32 ret; 6138 6139 orig = rtw89_read16(rtwdev, addr); 6140 ret = (orig & mask) >> shift; 6141 6142 return ret; 6143 } 6144 6145 static inline u8 6146 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 6147 { 6148 u32 shift = __ffs(mask); 6149 u32 orig; 6150 u32 ret; 6151 6152 orig = rtw89_read8(rtwdev, addr); 6153 ret = (orig & mask) >> shift; 6154 6155 return ret; 6156 } 6157 6158 static inline void 6159 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 6160 { 6161 u32 shift = __ffs(mask); 6162 u32 orig; 6163 u32 set; 6164 6165 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 6166 6167 orig = rtw89_read32(rtwdev, addr); 6168 set = (orig & ~mask) | ((data << shift) & mask); 6169 rtw89_write32(rtwdev, addr, set); 6170 } 6171 6172 static inline void 6173 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 6174 { 6175 u32 shift; 6176 u16 orig, set; 6177 6178 mask &= 0xffff; 6179 shift = __ffs(mask); 6180 6181 orig = rtw89_read16(rtwdev, addr); 6182 set = (orig & ~mask) | ((data << shift) & mask); 6183 rtw89_write16(rtwdev, addr, set); 6184 } 6185 6186 static inline void 6187 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 6188 { 6189 u32 shift; 6190 u8 orig, set; 6191 6192 mask &= 0xff; 6193 shift = __ffs(mask); 6194 6195 orig = rtw89_read8(rtwdev, addr); 6196 set = (orig & ~mask) | ((data << shift) & mask); 6197 rtw89_write8(rtwdev, addr, set); 6198 } 6199 6200 static inline u32 6201 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6202 u32 addr, u32 mask) 6203 { 6204 u32 val; 6205 6206 mutex_lock(&rtwdev->rf_mutex); 6207 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 6208 mutex_unlock(&rtwdev->rf_mutex); 6209 6210 return val; 6211 } 6212 6213 static inline void 6214 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 6215 u32 addr, u32 mask, u32 data) 6216 { 6217 mutex_lock(&rtwdev->rf_mutex); 6218 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 6219 mutex_unlock(&rtwdev->rf_mutex); 6220 } 6221 6222 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 6223 { 6224 void *p = rtwtxq; 6225 6226 return container_of(p, struct ieee80211_txq, drv_priv); 6227 } 6228 6229 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 6230 struct ieee80211_txq *txq) 6231 { 6232 struct rtw89_txq *rtwtxq; 6233 6234 if (!txq) 6235 return; 6236 6237 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 6238 INIT_LIST_HEAD(&rtwtxq->list); 6239 } 6240 6241 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 6242 { 6243 void *p = rtwvif; 6244 6245 return container_of(p, struct ieee80211_vif, drv_priv); 6246 } 6247 6248 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 6249 { 6250 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 6251 } 6252 6253 static inline 6254 struct ieee80211_vif *rtwvif_link_to_vif(struct rtw89_vif_link *rtwvif_link) 6255 { 6256 return rtwvif_to_vif(rtwvif_link->rtwvif); 6257 } 6258 6259 static inline 6260 struct ieee80211_vif *rtwvif_link_to_vif_safe(struct rtw89_vif_link *rtwvif_link) 6261 { 6262 return rtwvif_link ? rtwvif_link_to_vif(rtwvif_link) : NULL; 6263 } 6264 6265 static inline struct rtw89_vif *vif_to_rtwvif(struct ieee80211_vif *vif) 6266 { 6267 return (struct rtw89_vif *)vif->drv_priv; 6268 } 6269 6270 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 6271 { 6272 return vif ? vif_to_rtwvif(vif) : NULL; 6273 } 6274 6275 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 6276 { 6277 void *p = rtwsta; 6278 6279 return container_of(p, struct ieee80211_sta, drv_priv); 6280 } 6281 6282 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 6283 { 6284 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 6285 } 6286 6287 static inline 6288 struct ieee80211_sta *rtwsta_link_to_sta(struct rtw89_sta_link *rtwsta_link) 6289 { 6290 return rtwsta_to_sta(rtwsta_link->rtwsta); 6291 } 6292 6293 static inline 6294 struct ieee80211_sta *rtwsta_link_to_sta_safe(struct rtw89_sta_link *rtwsta_link) 6295 { 6296 return rtwsta_link ? rtwsta_link_to_sta(rtwsta_link) : NULL; 6297 } 6298 6299 static inline struct rtw89_sta *sta_to_rtwsta(struct ieee80211_sta *sta) 6300 { 6301 return (struct rtw89_sta *)sta->drv_priv; 6302 } 6303 6304 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 6305 { 6306 return sta ? sta_to_rtwsta(sta) : NULL; 6307 } 6308 6309 static inline struct ieee80211_bss_conf * 6310 __rtw89_vif_rcu_dereference_link(struct rtw89_vif_link *rtwvif_link, bool *nolink) 6311 { 6312 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 6313 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 6314 struct rtw89_link_conf_container *snap; 6315 struct ieee80211_bss_conf *bss_conf; 6316 6317 snap = rcu_dereference(rtwvif->snap_link_confs); 6318 if (snap) { 6319 bss_conf = snap->link_conf[rtwvif_link->link_id]; 6320 goto out; 6321 } 6322 6323 bss_conf = rcu_dereference(vif->link_conf[rtwvif_link->link_id]); 6324 6325 out: 6326 if (unlikely(!bss_conf)) { 6327 *nolink = true; 6328 return &vif->bss_conf; 6329 } 6330 6331 *nolink = false; 6332 return bss_conf; 6333 } 6334 6335 #define rtw89_vif_rcu_dereference_link(rtwvif_link, assert) \ 6336 ({ \ 6337 typeof(rtwvif_link) p = rtwvif_link; \ 6338 struct ieee80211_bss_conf *bss_conf; \ 6339 bool nolink; \ 6340 \ 6341 bss_conf = __rtw89_vif_rcu_dereference_link(p, &nolink); \ 6342 if (unlikely(nolink) && (assert)) \ 6343 rtw89_err(p->rtwvif->rtwdev, \ 6344 "%s: cannot find exact bss_conf for link_id %u\n",\ 6345 __func__, p->link_id); \ 6346 bss_conf; \ 6347 }) 6348 6349 static inline struct ieee80211_link_sta * 6350 __rtw89_sta_rcu_dereference_link(struct rtw89_sta_link *rtwsta_link, bool *nolink) 6351 { 6352 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6353 struct ieee80211_link_sta *link_sta; 6354 6355 link_sta = rcu_dereference(sta->link[rtwsta_link->link_id]); 6356 if (unlikely(!link_sta)) { 6357 *nolink = true; 6358 return &sta->deflink; 6359 } 6360 6361 *nolink = false; 6362 return link_sta; 6363 } 6364 6365 #define rtw89_sta_rcu_dereference_link(rtwsta_link, assert) \ 6366 ({ \ 6367 typeof(rtwsta_link) p = rtwsta_link; \ 6368 struct ieee80211_link_sta *link_sta; \ 6369 bool nolink; \ 6370 \ 6371 link_sta = __rtw89_sta_rcu_dereference_link(p, &nolink); \ 6372 if (unlikely(nolink) && (assert)) \ 6373 rtw89_err(p->rtwsta->rtwdev, \ 6374 "%s: cannot find exact link_sta for link_id %u\n",\ 6375 __func__, p->link_id); \ 6376 link_sta; \ 6377 }) 6378 6379 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 6380 { 6381 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 6382 return RATE_INFO_BW_160; 6383 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 6384 return RATE_INFO_BW_80; 6385 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 6386 return RATE_INFO_BW_40; 6387 else 6388 return RATE_INFO_BW_20; 6389 } 6390 6391 static inline 6392 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 6393 { 6394 switch (hw_band) { 6395 default: 6396 case RTW89_BAND_2G: 6397 return NL80211_BAND_2GHZ; 6398 case RTW89_BAND_5G: 6399 return NL80211_BAND_5GHZ; 6400 case RTW89_BAND_6G: 6401 return NL80211_BAND_6GHZ; 6402 } 6403 } 6404 6405 static inline 6406 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 6407 { 6408 switch (nl_band) { 6409 default: 6410 case NL80211_BAND_2GHZ: 6411 return RTW89_BAND_2G; 6412 case NL80211_BAND_5GHZ: 6413 return RTW89_BAND_5G; 6414 case NL80211_BAND_6GHZ: 6415 return RTW89_BAND_6G; 6416 } 6417 } 6418 6419 static inline 6420 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 6421 { 6422 switch (width) { 6423 default: 6424 WARN(1, "Not support bandwidth %d\n", width); 6425 fallthrough; 6426 case NL80211_CHAN_WIDTH_20_NOHT: 6427 case NL80211_CHAN_WIDTH_20: 6428 return RTW89_CHANNEL_WIDTH_20; 6429 case NL80211_CHAN_WIDTH_40: 6430 return RTW89_CHANNEL_WIDTH_40; 6431 case NL80211_CHAN_WIDTH_80: 6432 return RTW89_CHANNEL_WIDTH_80; 6433 case NL80211_CHAN_WIDTH_160: 6434 return RTW89_CHANNEL_WIDTH_160; 6435 } 6436 } 6437 6438 static inline 6439 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 6440 { 6441 switch (rua) { 6442 default: 6443 WARN(1, "Invalid RU allocation: %d\n", rua); 6444 fallthrough; 6445 case 0 ... 36: 6446 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 6447 case 37 ... 52: 6448 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 6449 case 53 ... 60: 6450 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 6451 case 61 ... 64: 6452 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 6453 case 65 ... 66: 6454 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 6455 case 67: 6456 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 6457 case 68: 6458 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 6459 } 6460 } 6461 6462 static inline 6463 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif_link *rtwvif_link, 6464 struct rtw89_sta_link *rtwsta_link) 6465 { 6466 if (rtwsta_link) { 6467 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6468 6469 if (rtwvif_link->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 6470 return &rtwsta_link->addr_cam; 6471 } 6472 return &rtwvif_link->addr_cam; 6473 } 6474 6475 static inline 6476 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif_link *rtwvif_link, 6477 struct rtw89_sta_link *rtwsta_link) 6478 { 6479 if (rtwsta_link) { 6480 struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 6481 6482 if (sta->tdls) 6483 return &rtwsta_link->bssid_cam; 6484 } 6485 return &rtwvif_link->bssid_cam; 6486 } 6487 6488 static inline 6489 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 6490 struct rtw89_channel_help_params *p, 6491 const struct rtw89_chan *chan, 6492 enum rtw89_mac_idx mac_idx, 6493 enum rtw89_phy_idx phy_idx) 6494 { 6495 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 6496 mac_idx, phy_idx); 6497 } 6498 6499 static inline 6500 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 6501 struct rtw89_channel_help_params *p, 6502 const struct rtw89_chan *chan, 6503 enum rtw89_mac_idx mac_idx, 6504 enum rtw89_phy_idx phy_idx) 6505 { 6506 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 6507 mac_idx, phy_idx); 6508 } 6509 6510 static inline 6511 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 6512 enum rtw89_chanctx_idx idx) 6513 { 6514 struct rtw89_hal *hal = &rtwdev->hal; 6515 enum rtw89_chanctx_idx roc_idx = atomic_read(&hal->roc_chanctx_idx); 6516 6517 if (roc_idx == idx) 6518 return &hal->roc_chandef; 6519 6520 return &hal->chanctx[idx].chandef; 6521 } 6522 6523 static inline 6524 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 6525 enum rtw89_chanctx_idx idx) 6526 { 6527 struct rtw89_hal *hal = &rtwdev->hal; 6528 6529 return &hal->chanctx[idx].chan; 6530 } 6531 6532 static inline 6533 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 6534 enum rtw89_chanctx_idx idx) 6535 { 6536 struct rtw89_hal *hal = &rtwdev->hal; 6537 6538 return &hal->chanctx[idx].rcd; 6539 } 6540 6541 static inline 6542 const struct rtw89_chan_rcd *rtw89_chan_rcd_get_by_chan(const struct rtw89_chan *chan) 6543 { 6544 const struct rtw89_chanctx *chanctx = 6545 container_of_const(chan, struct rtw89_chanctx, chan); 6546 6547 return &chanctx->rcd; 6548 } 6549 6550 static inline 6551 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 6552 { 6553 struct rtw89_vif_link *rtwvif_link = rtwdev->scan_info.scanning_vif; 6554 6555 if (rtwvif_link) 6556 return rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 6557 else 6558 return rtw89_chan_get(rtwdev, RTW89_CHANCTX_0); 6559 } 6560 6561 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 6562 { 6563 const struct rtw89_chip_info *chip = rtwdev->chip; 6564 6565 if (chip->ops->fem_setup) 6566 chip->ops->fem_setup(rtwdev); 6567 } 6568 6569 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 6570 { 6571 const struct rtw89_chip_info *chip = rtwdev->chip; 6572 6573 if (chip->ops->rfe_gpio) 6574 chip->ops->rfe_gpio(rtwdev); 6575 } 6576 6577 static inline void rtw89_chip_rfk_hw_init(struct rtw89_dev *rtwdev) 6578 { 6579 const struct rtw89_chip_info *chip = rtwdev->chip; 6580 6581 if (chip->ops->rfk_hw_init) 6582 chip->ops->rfk_hw_init(rtwdev); 6583 } 6584 6585 static inline 6586 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 6587 { 6588 const struct rtw89_chip_info *chip = rtwdev->chip; 6589 6590 if (chip->ops->bb_preinit) 6591 chip->ops->bb_preinit(rtwdev, phy_idx); 6592 } 6593 6594 static inline 6595 void rtw89_chip_bb_postinit(struct rtw89_dev *rtwdev) 6596 { 6597 const struct rtw89_chip_info *chip = rtwdev->chip; 6598 6599 if (!chip->ops->bb_postinit) 6600 return; 6601 6602 chip->ops->bb_postinit(rtwdev, RTW89_PHY_0); 6603 6604 if (rtwdev->dbcc_en) 6605 chip->ops->bb_postinit(rtwdev, RTW89_PHY_1); 6606 } 6607 6608 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 6609 { 6610 const struct rtw89_chip_info *chip = rtwdev->chip; 6611 6612 if (chip->ops->bb_sethw) 6613 chip->ops->bb_sethw(rtwdev); 6614 } 6615 6616 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 6617 { 6618 const struct rtw89_chip_info *chip = rtwdev->chip; 6619 6620 if (chip->ops->rfk_init) 6621 chip->ops->rfk_init(rtwdev); 6622 } 6623 6624 static inline void rtw89_chip_rfk_init_late(struct rtw89_dev *rtwdev) 6625 { 6626 const struct rtw89_chip_info *chip = rtwdev->chip; 6627 6628 if (chip->ops->rfk_init_late) 6629 chip->ops->rfk_init_late(rtwdev); 6630 } 6631 6632 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev, 6633 struct rtw89_vif_link *rtwvif_link) 6634 { 6635 const struct rtw89_chip_info *chip = rtwdev->chip; 6636 6637 if (chip->ops->rfk_channel) 6638 chip->ops->rfk_channel(rtwdev, rtwvif_link); 6639 } 6640 6641 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 6642 enum rtw89_phy_idx phy_idx, 6643 const struct rtw89_chan *chan) 6644 { 6645 const struct rtw89_chip_info *chip = rtwdev->chip; 6646 6647 if (chip->ops->rfk_band_changed) 6648 chip->ops->rfk_band_changed(rtwdev, phy_idx, chan); 6649 } 6650 6651 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, 6652 struct rtw89_vif_link *rtwvif_link, bool start) 6653 { 6654 const struct rtw89_chip_info *chip = rtwdev->chip; 6655 6656 if (chip->ops->rfk_scan) 6657 chip->ops->rfk_scan(rtwdev, rtwvif_link, start); 6658 } 6659 6660 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 6661 { 6662 const struct rtw89_chip_info *chip = rtwdev->chip; 6663 6664 if (chip->ops->rfk_track) 6665 chip->ops->rfk_track(rtwdev); 6666 } 6667 6668 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 6669 { 6670 const struct rtw89_chip_info *chip = rtwdev->chip; 6671 6672 if (!chip->ops->set_txpwr_ctrl) 6673 return; 6674 6675 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 6676 if (rtwdev->dbcc_en) 6677 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_1); 6678 } 6679 6680 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 6681 { 6682 const struct rtw89_chip_info *chip = rtwdev->chip; 6683 6684 if (chip->ops->power_trim) 6685 chip->ops->power_trim(rtwdev); 6686 } 6687 6688 static inline void __rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 6689 enum rtw89_phy_idx phy_idx) 6690 { 6691 const struct rtw89_chip_info *chip = rtwdev->chip; 6692 6693 if (chip->ops->init_txpwr_unit) 6694 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 6695 } 6696 6697 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev) 6698 { 6699 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_0); 6700 if (rtwdev->dbcc_en) 6701 __rtw89_chip_init_txpwr_unit(rtwdev, RTW89_PHY_1); 6702 } 6703 6704 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 6705 enum rtw89_rf_path rf_path) 6706 { 6707 const struct rtw89_chip_info *chip = rtwdev->chip; 6708 6709 if (!chip->ops->get_thermal) 6710 return 0x10; 6711 6712 return chip->ops->get_thermal(rtwdev, rf_path); 6713 } 6714 6715 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 6716 struct rtw89_rx_phy_ppdu *phy_ppdu, 6717 struct ieee80211_rx_status *status) 6718 { 6719 const struct rtw89_chip_info *chip = rtwdev->chip; 6720 6721 if (chip->ops->query_ppdu) 6722 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 6723 } 6724 6725 static inline void rtw89_chip_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 6726 struct rtw89_rx_phy_ppdu *phy_ppdu) 6727 { 6728 const struct rtw89_chip_info *chip = rtwdev->chip; 6729 6730 if (chip->ops->convert_rpl_to_rssi) 6731 chip->ops->convert_rpl_to_rssi(rtwdev, phy_ppdu); 6732 } 6733 6734 static inline void rtw89_chip_phy_rpt_to_rssi(struct rtw89_dev *rtwdev, 6735 struct rtw89_rx_desc_info *desc_info, 6736 struct ieee80211_rx_status *rx_status) 6737 { 6738 const struct rtw89_chip_info *chip = rtwdev->chip; 6739 6740 if (chip->ops->phy_rpt_to_rssi) 6741 chip->ops->phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 6742 } 6743 6744 static inline void rtw89_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 6745 enum rtw89_phy_idx phy_idx) 6746 { 6747 const struct rtw89_chip_info *chip = rtwdev->chip; 6748 6749 if (chip->ops->ctrl_nbtg_bt_tx) 6750 chip->ops->ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 6751 } 6752 6753 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 6754 { 6755 const struct rtw89_chip_info *chip = rtwdev->chip; 6756 6757 if (chip->ops->cfg_txrx_path) 6758 chip->ops->cfg_txrx_path(rtwdev); 6759 } 6760 6761 static inline void rtw89_chip_digital_pwr_comp(struct rtw89_dev *rtwdev, 6762 enum rtw89_phy_idx phy_idx) 6763 { 6764 const struct rtw89_chip_info *chip = rtwdev->chip; 6765 6766 if (chip->ops->digital_pwr_comp) 6767 chip->ops->digital_pwr_comp(rtwdev, phy_idx); 6768 } 6769 6770 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 6771 const struct rtw89_txpwr_table *tbl) 6772 { 6773 tbl->load(rtwdev, tbl); 6774 } 6775 6776 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 6777 { 6778 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 6779 6780 return regd->txpwr_regd[band]; 6781 } 6782 6783 static inline void rtw89_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 6784 enum rtw89_phy_idx phy_idx) 6785 { 6786 const struct rtw89_chip_info *chip = rtwdev->chip; 6787 6788 if (chip->ops->ctrl_btg_bt_rx) 6789 chip->ops->ctrl_btg_bt_rx(rtwdev, en, phy_idx); 6790 } 6791 6792 static inline 6793 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 6794 struct rtw89_rx_desc_info *desc_info, 6795 u8 *data, u32 data_offset) 6796 { 6797 const struct rtw89_chip_info *chip = rtwdev->chip; 6798 6799 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 6800 } 6801 6802 static inline 6803 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 6804 struct rtw89_tx_desc_info *desc_info, 6805 void *txdesc) 6806 { 6807 const struct rtw89_chip_info *chip = rtwdev->chip; 6808 6809 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 6810 } 6811 6812 static inline 6813 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 6814 struct rtw89_tx_desc_info *desc_info, 6815 void *txdesc) 6816 { 6817 const struct rtw89_chip_info *chip = rtwdev->chip; 6818 6819 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 6820 } 6821 6822 static inline 6823 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 6824 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 6825 { 6826 const struct rtw89_chip_info *chip = rtwdev->chip; 6827 6828 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 6829 } 6830 6831 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 6832 { 6833 const struct rtw89_chip_info *chip = rtwdev->chip; 6834 6835 chip->ops->cfg_ctrl_path(rtwdev, wl); 6836 } 6837 6838 static inline 6839 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 6840 u32 *tx_en, enum rtw89_sch_tx_sel sel) 6841 { 6842 const struct rtw89_chip_info *chip = rtwdev->chip; 6843 6844 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 6845 } 6846 6847 static inline 6848 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 6849 { 6850 const struct rtw89_chip_info *chip = rtwdev->chip; 6851 6852 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 6853 } 6854 6855 static inline 6856 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 6857 struct rtw89_vif_link *rtwvif_link, 6858 struct rtw89_sta_link *rtwsta_link) 6859 { 6860 const struct rtw89_chip_info *chip = rtwdev->chip; 6861 6862 if (!chip->ops->h2c_dctl_sec_cam) 6863 return 0; 6864 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif_link, rtwsta_link); 6865 } 6866 6867 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 6868 { 6869 __le16 fc = hdr->frame_control; 6870 6871 if (ieee80211_has_tods(fc)) 6872 return hdr->addr1; 6873 else if (ieee80211_has_fromds(fc)) 6874 return hdr->addr2; 6875 else 6876 return hdr->addr3; 6877 } 6878 6879 static inline 6880 bool rtw89_sta_has_beamformer_cap(struct ieee80211_link_sta *link_sta) 6881 { 6882 if ((link_sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 6883 (link_sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 6884 (link_sta->he_cap.he_cap_elem.phy_cap_info[3] & 6885 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 6886 (link_sta->he_cap.he_cap_elem.phy_cap_info[4] & 6887 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 6888 return true; 6889 return false; 6890 } 6891 6892 static inline 6893 bool rtw89_sta_link_has_su_mu_4xhe08(struct ieee80211_link_sta *link_sta) 6894 { 6895 if (link_sta->he_cap.he_cap_elem.phy_cap_info[7] & 6896 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI) 6897 return true; 6898 6899 return false; 6900 } 6901 6902 static inline 6903 bool rtw89_sta_link_has_er_su_4xhe08(struct ieee80211_link_sta *link_sta) 6904 { 6905 if (link_sta->he_cap.he_cap_elem.phy_cap_info[8] & 6906 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI) 6907 return true; 6908 6909 return false; 6910 } 6911 6912 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 6913 enum rtw89_fw_type type) 6914 { 6915 struct rtw89_fw_info *fw_info = &rtwdev->fw; 6916 6917 switch (type) { 6918 case RTW89_FW_WOWLAN: 6919 return &fw_info->wowlan; 6920 case RTW89_FW_LOGFMT: 6921 return &fw_info->log.suit; 6922 case RTW89_FW_BBMCU0: 6923 return &fw_info->bbmcu0; 6924 case RTW89_FW_BBMCU1: 6925 return &fw_info->bbmcu1; 6926 default: 6927 break; 6928 } 6929 6930 return &fw_info->normal; 6931 } 6932 6933 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 6934 unsigned int length) 6935 { 6936 struct sk_buff *skb; 6937 6938 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 6939 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 6940 if (!skb) 6941 return NULL; 6942 6943 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 6944 return skb; 6945 } 6946 6947 return dev_alloc_skb(length); 6948 } 6949 6950 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 6951 struct rtw89_tx_skb_data *skb_data, 6952 bool tx_done) 6953 { 6954 struct rtw89_tx_wait_info *wait; 6955 6956 rcu_read_lock(); 6957 6958 wait = rcu_dereference(skb_data->wait); 6959 if (!wait) 6960 goto out; 6961 6962 wait->tx_done = tx_done; 6963 complete(&wait->completion); 6964 6965 out: 6966 rcu_read_unlock(); 6967 } 6968 6969 static inline bool rtw89_is_mlo_1_1(struct rtw89_dev *rtwdev) 6970 { 6971 switch (rtwdev->mlo_dbcc_mode) { 6972 case MLO_1_PLUS_1_1RF: 6973 case MLO_1_PLUS_1_2RF: 6974 case DBCC_LEGACY: 6975 return true; 6976 default: 6977 return false; 6978 } 6979 } 6980 6981 static inline bool rtw89_is_rtl885xb(struct rtw89_dev *rtwdev) 6982 { 6983 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 6984 6985 if (chip_id == RTL8852B || chip_id == RTL8851B || chip_id == RTL8852BT) 6986 return true; 6987 6988 return false; 6989 } 6990 6991 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6992 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 6993 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 6994 struct sk_buff *skb, bool fwdl); 6995 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 6996 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 6997 int qsel, unsigned int timeout); 6998 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 6999 struct rtw89_tx_desc_info *desc_info, 7000 void *txdesc); 7001 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 7002 struct rtw89_tx_desc_info *desc_info, 7003 void *txdesc); 7004 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 7005 struct rtw89_tx_desc_info *desc_info, 7006 void *txdesc); 7007 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 7008 struct rtw89_tx_desc_info *desc_info, 7009 void *txdesc); 7010 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 7011 struct rtw89_tx_desc_info *desc_info, 7012 void *txdesc); 7013 void rtw89_core_rx(struct rtw89_dev *rtwdev, 7014 struct rtw89_rx_desc_info *desc_info, 7015 struct sk_buff *skb); 7016 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 7017 struct rtw89_rx_desc_info *desc_info, 7018 u8 *data, u32 data_offset); 7019 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 7020 struct rtw89_rx_desc_info *desc_info, 7021 u8 *data, u32 data_offset); 7022 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 7023 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 7024 int rtw89_core_napi_init(struct rtw89_dev *rtwdev); 7025 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 7026 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 7027 struct rtw89_vif_link *rtwvif_link, 7028 struct rtw89_sta_link *rtwsta_link); 7029 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 7030 struct rtw89_vif_link *rtwvif_link, 7031 struct rtw89_sta_link *rtwsta_link); 7032 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 7033 struct rtw89_vif_link *rtwvif_link, 7034 struct rtw89_sta_link *rtwsta_link); 7035 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 7036 struct rtw89_vif_link *rtwvif_link, 7037 struct rtw89_sta_link *rtwsta_link); 7038 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 7039 struct rtw89_vif_link *rtwvif_link, 7040 struct rtw89_sta_link *rtwsta_link); 7041 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 7042 struct ieee80211_sta *sta, 7043 struct cfg80211_tid_config *tid_config); 7044 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force); 7045 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks); 7046 int rtw89_core_init(struct rtw89_dev *rtwdev); 7047 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 7048 int rtw89_core_register(struct rtw89_dev *rtwdev); 7049 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 7050 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 7051 u32 bus_data_size, 7052 const struct rtw89_chip_info *chip, 7053 const struct rtw89_chip_variant *variant); 7054 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 7055 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev); 7056 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id); 7057 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7058 u8 mac_id, u8 port); 7059 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 7060 struct rtw89_sta *rtwsta, u8 mac_id); 7061 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 7062 unsigned int link_id); 7063 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id); 7064 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 7065 unsigned int link_id); 7066 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id); 7067 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 7068 const struct rtw89_6ghz_span * 7069 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq); 7070 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 7071 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 7072 struct rtw89_chan *chan); 7073 int rtw89_set_channel(struct rtw89_dev *rtwdev); 7074 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 7075 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 7076 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 7077 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 7078 struct rtw89_sta_link *rtwsta_link, u8 tid, 7079 u8 *cam_idx); 7080 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 7081 struct rtw89_sta_link *rtwsta_link, u8 tid, 7082 u8 *cam_idx); 7083 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 7084 struct ieee80211_sta *sta); 7085 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 7086 struct ieee80211_sta *sta); 7087 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 7088 struct ieee80211_sta *sta); 7089 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc); 7090 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 7091 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 7092 struct rtw89_vif_link *rtwvif_link); 7093 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 7094 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 7095 int rtw89_regd_init(struct rtw89_dev *rtwdev, 7096 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 7097 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 7098 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 7099 struct rtw89_traffic_stats *stats); 7100 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 7101 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 7102 const struct rtw89_completion_data *data); 7103 int rtw89_core_start(struct rtw89_dev *rtwdev); 7104 void rtw89_core_stop(struct rtw89_dev *rtwdev); 7105 void rtw89_core_update_beacon_work(struct work_struct *work); 7106 void rtw89_roc_work(struct work_struct *work); 7107 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7108 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 7109 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7110 const u8 *mac_addr, bool hw_scan); 7111 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 7112 struct rtw89_vif_link *rtwvif_link, bool hw_scan); 7113 int rtw89_reg_6ghz_recalc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 7114 bool active); 7115 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 7116 struct rtw89_vif_link *rtwvif_link, 7117 struct ieee80211_bss_conf *bss_conf); 7118 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 7119 7120 #endif 7121