1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 17 extern const struct ieee80211_ops rtw89_ops; 18 19 #define MASKBYTE0 0xff 20 #define MASKBYTE1 0xff00 21 #define MASKBYTE2 0xff0000 22 #define MASKBYTE3 0xff000000 23 #define MASKBYTE4 0xff00000000ULL 24 #define MASKHWORD 0xffff0000 25 #define MASKLWORD 0x0000ffff 26 #define MASKDWORD 0xffffffff 27 #define RFREG_MASK 0xfffff 28 #define INV_RF_DATA 0xffffffff 29 30 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 31 #define CFO_TRACK_MAX_USER 64 32 #define MAX_RSSI 110 33 #define RSSI_FACTOR 1 34 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 35 36 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 37 #define RTW89_HTC_VARIANT_HE 3 38 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 39 #define RTW89_HTC_VARIANT_HE_CID_OM 1 40 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 41 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 42 43 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 44 enum htc_om_channel_width { 45 HTC_OM_CHANNEL_WIDTH_20 = 0, 46 HTC_OM_CHANNEL_WIDTH_40 = 1, 47 HTC_OM_CHANNEL_WIDTH_80 = 2, 48 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 49 }; 50 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 51 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 52 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 53 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 54 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 55 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 56 57 enum rtw89_subband { 58 RTW89_CH_2G = 0, 59 RTW89_CH_5G_BAND_1 = 1, 60 /* RTW89_CH_5G_BAND_2 = 2, unused */ 61 RTW89_CH_5G_BAND_3 = 3, 62 RTW89_CH_5G_BAND_4 = 4, 63 64 RTW89_SUBBAND_NR, 65 }; 66 67 enum rtw89_hci_type { 68 RTW89_HCI_TYPE_PCIE, 69 RTW89_HCI_TYPE_USB, 70 RTW89_HCI_TYPE_SDIO, 71 }; 72 73 enum rtw89_core_chip_id { 74 RTL8852A, 75 RTL8852B, 76 RTL8852C, 77 }; 78 79 enum rtw89_cv { 80 CHIP_CAV, 81 CHIP_CBV, 82 CHIP_CCV, 83 CHIP_CDV, 84 CHIP_CEV, 85 CHIP_CFV, 86 CHIP_CV_MAX, 87 CHIP_CV_INVALID = CHIP_CV_MAX, 88 }; 89 90 enum rtw89_core_tx_type { 91 RTW89_CORE_TX_TYPE_DATA, 92 RTW89_CORE_TX_TYPE_MGMT, 93 RTW89_CORE_TX_TYPE_FWCMD, 94 }; 95 96 enum rtw89_core_rx_type { 97 RTW89_CORE_RX_TYPE_WIFI = 0, 98 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 99 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 100 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 101 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 102 RTW89_CORE_RX_TYPE_SS2FW = 5, 103 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 104 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 105 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 106 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 107 RTW89_CORE_RX_TYPE_C2H = 10, 108 RTW89_CORE_RX_TYPE_CSI = 11, 109 RTW89_CORE_RX_TYPE_CQI = 12, 110 }; 111 112 enum rtw89_txq_flags { 113 RTW89_TXQ_F_AMPDU = 0, 114 RTW89_TXQ_F_BLOCK_BA = 1, 115 }; 116 117 enum rtw89_net_type { 118 RTW89_NET_TYPE_NO_LINK = 0, 119 RTW89_NET_TYPE_AD_HOC = 1, 120 RTW89_NET_TYPE_INFRA = 2, 121 RTW89_NET_TYPE_AP_MODE = 3, 122 }; 123 124 enum rtw89_wifi_role { 125 RTW89_WIFI_ROLE_NONE, 126 RTW89_WIFI_ROLE_STATION, 127 RTW89_WIFI_ROLE_AP, 128 RTW89_WIFI_ROLE_AP_VLAN, 129 RTW89_WIFI_ROLE_ADHOC, 130 RTW89_WIFI_ROLE_ADHOC_MASTER, 131 RTW89_WIFI_ROLE_MESH_POINT, 132 RTW89_WIFI_ROLE_MONITOR, 133 RTW89_WIFI_ROLE_P2P_DEVICE, 134 RTW89_WIFI_ROLE_P2P_CLIENT, 135 RTW89_WIFI_ROLE_P2P_GO, 136 RTW89_WIFI_ROLE_NAN, 137 RTW89_WIFI_ROLE_MLME_MAX 138 }; 139 140 enum rtw89_upd_mode { 141 RTW89_ROLE_CREATE, 142 RTW89_ROLE_REMOVE, 143 RTW89_ROLE_TYPE_CHANGE, 144 RTW89_ROLE_INFO_CHANGE, 145 RTW89_ROLE_CON_DISCONN 146 }; 147 148 enum rtw89_self_role { 149 RTW89_SELF_ROLE_CLIENT, 150 RTW89_SELF_ROLE_AP, 151 RTW89_SELF_ROLE_AP_CLIENT 152 }; 153 154 enum rtw89_msk_sO_el { 155 RTW89_NO_MSK, 156 RTW89_SMA, 157 RTW89_TMA, 158 RTW89_BSSID 159 }; 160 161 enum rtw89_sch_tx_sel { 162 RTW89_SCH_TX_SEL_ALL, 163 RTW89_SCH_TX_SEL_HIQ, 164 RTW89_SCH_TX_SEL_MG0, 165 RTW89_SCH_TX_SEL_MACID, 166 }; 167 168 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 169 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 170 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 171 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 172 */ 173 enum rtw89_add_cam_sec_mode { 174 RTW89_ADDR_CAM_SEC_NONE = 0, 175 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 176 RTW89_ADDR_CAM_SEC_NORMAL = 2, 177 RTW89_ADDR_CAM_SEC_4GROUP = 3, 178 }; 179 180 enum rtw89_sec_key_type { 181 RTW89_SEC_KEY_TYPE_NONE = 0, 182 RTW89_SEC_KEY_TYPE_WEP40 = 1, 183 RTW89_SEC_KEY_TYPE_WEP104 = 2, 184 RTW89_SEC_KEY_TYPE_TKIP = 3, 185 RTW89_SEC_KEY_TYPE_WAPI = 4, 186 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 187 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 188 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 189 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 190 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 191 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 192 }; 193 194 enum rtw89_port { 195 RTW89_PORT_0 = 0, 196 RTW89_PORT_1 = 1, 197 RTW89_PORT_2 = 2, 198 RTW89_PORT_3 = 3, 199 RTW89_PORT_4 = 4, 200 RTW89_PORT_NUM 201 }; 202 203 enum rtw89_band { 204 RTW89_BAND_2G = 0, 205 RTW89_BAND_5G = 1, 206 RTW89_BAND_6G = 2, 207 RTW89_BAND_MAX, 208 }; 209 210 enum rtw89_hw_rate { 211 RTW89_HW_RATE_CCK1 = 0x0, 212 RTW89_HW_RATE_CCK2 = 0x1, 213 RTW89_HW_RATE_CCK5_5 = 0x2, 214 RTW89_HW_RATE_CCK11 = 0x3, 215 RTW89_HW_RATE_OFDM6 = 0x4, 216 RTW89_HW_RATE_OFDM9 = 0x5, 217 RTW89_HW_RATE_OFDM12 = 0x6, 218 RTW89_HW_RATE_OFDM18 = 0x7, 219 RTW89_HW_RATE_OFDM24 = 0x8, 220 RTW89_HW_RATE_OFDM36 = 0x9, 221 RTW89_HW_RATE_OFDM48 = 0xA, 222 RTW89_HW_RATE_OFDM54 = 0xB, 223 RTW89_HW_RATE_MCS0 = 0x80, 224 RTW89_HW_RATE_MCS1 = 0x81, 225 RTW89_HW_RATE_MCS2 = 0x82, 226 RTW89_HW_RATE_MCS3 = 0x83, 227 RTW89_HW_RATE_MCS4 = 0x84, 228 RTW89_HW_RATE_MCS5 = 0x85, 229 RTW89_HW_RATE_MCS6 = 0x86, 230 RTW89_HW_RATE_MCS7 = 0x87, 231 RTW89_HW_RATE_MCS8 = 0x88, 232 RTW89_HW_RATE_MCS9 = 0x89, 233 RTW89_HW_RATE_MCS10 = 0x8A, 234 RTW89_HW_RATE_MCS11 = 0x8B, 235 RTW89_HW_RATE_MCS12 = 0x8C, 236 RTW89_HW_RATE_MCS13 = 0x8D, 237 RTW89_HW_RATE_MCS14 = 0x8E, 238 RTW89_HW_RATE_MCS15 = 0x8F, 239 RTW89_HW_RATE_MCS16 = 0x90, 240 RTW89_HW_RATE_MCS17 = 0x91, 241 RTW89_HW_RATE_MCS18 = 0x92, 242 RTW89_HW_RATE_MCS19 = 0x93, 243 RTW89_HW_RATE_MCS20 = 0x94, 244 RTW89_HW_RATE_MCS21 = 0x95, 245 RTW89_HW_RATE_MCS22 = 0x96, 246 RTW89_HW_RATE_MCS23 = 0x97, 247 RTW89_HW_RATE_MCS24 = 0x98, 248 RTW89_HW_RATE_MCS25 = 0x99, 249 RTW89_HW_RATE_MCS26 = 0x9A, 250 RTW89_HW_RATE_MCS27 = 0x9B, 251 RTW89_HW_RATE_MCS28 = 0x9C, 252 RTW89_HW_RATE_MCS29 = 0x9D, 253 RTW89_HW_RATE_MCS30 = 0x9E, 254 RTW89_HW_RATE_MCS31 = 0x9F, 255 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 256 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 257 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 258 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 259 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 260 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 261 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 262 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 263 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 264 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 265 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 266 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 267 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 268 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 269 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 270 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 271 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 272 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 273 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 274 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 275 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 276 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 277 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 278 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 279 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 280 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 281 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 282 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 283 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 284 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 285 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 286 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 287 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 288 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 289 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 290 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 291 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 292 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 293 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 294 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 295 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 296 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 297 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 298 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 299 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 300 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 301 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 302 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 303 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 304 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 305 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 306 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 307 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 308 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 309 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 310 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 311 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 312 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 313 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 314 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 315 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 316 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 317 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 318 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 319 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 320 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 321 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 322 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 323 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 324 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 325 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 326 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 327 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 328 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 329 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 330 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 331 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 332 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 333 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 334 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 335 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 336 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 337 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 338 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 339 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 340 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 341 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 342 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 343 RTW89_HW_RATE_NR, 344 345 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 346 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 347 }; 348 349 /* 2G channels, 350 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 351 */ 352 #define RTW89_2G_CH_NUM 14 353 354 /* 5G channels, 355 * 36, 38, 40, 42, 44, 46, 48, 50, 356 * 52, 54, 56, 58, 60, 62, 64, 357 * 100, 102, 104, 106, 108, 110, 112, 114, 358 * 116, 118, 120, 122, 124, 126, 128, 130, 359 * 132, 134, 136, 138, 140, 142, 144, 360 * 149, 151, 153, 155, 157, 159, 161, 163, 361 * 165, 167, 169, 171, 173, 175, 177 362 */ 363 #define RTW89_5G_CH_NUM 53 364 365 enum rtw89_rate_section { 366 RTW89_RS_CCK, 367 RTW89_RS_OFDM, 368 RTW89_RS_MCS, /* for HT/VHT/HE */ 369 RTW89_RS_HEDCM, 370 RTW89_RS_OFFSET, 371 RTW89_RS_MAX, 372 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 373 }; 374 375 enum rtw89_rate_max { 376 RTW89_RATE_CCK_MAX = 4, 377 RTW89_RATE_OFDM_MAX = 8, 378 RTW89_RATE_MCS_MAX = 12, 379 RTW89_RATE_HEDCM_MAX = 4, /* for HEDCM MCS0/1/3/4 */ 380 RTW89_RATE_OFFSET_MAX = 5, /* for HE(HEDCM)/VHT/HT/OFDM/CCK offset */ 381 }; 382 383 enum rtw89_nss { 384 RTW89_NSS_1 = 0, 385 RTW89_NSS_2 = 1, 386 /* HE DCM only support 1ss and 2ss */ 387 RTW89_NSS_HEDCM_MAX = RTW89_NSS_2 + 1, 388 RTW89_NSS_3 = 2, 389 RTW89_NSS_4 = 3, 390 RTW89_NSS_MAX, 391 }; 392 393 enum rtw89_ntx { 394 RTW89_1TX = 0, 395 RTW89_2TX = 1, 396 RTW89_NTX_NUM, 397 }; 398 399 enum rtw89_beamforming_type { 400 RTW89_NONBF = 0, 401 RTW89_BF = 1, 402 RTW89_BF_NUM, 403 }; 404 405 enum rtw89_regulation_type { 406 RTW89_WW = 0, 407 RTW89_ETSI = 1, 408 RTW89_FCC = 2, 409 RTW89_MKK = 3, 410 RTW89_NA = 4, 411 RTW89_IC = 5, 412 RTW89_KCC = 6, 413 RTW89_ACMA = 7, 414 RTW89_NCC = 8, 415 RTW89_MEXICO = 9, 416 RTW89_CHILE = 10, 417 RTW89_UKRAINE = 11, 418 RTW89_CN = 12, 419 RTW89_QATAR = 13, 420 RTW89_REGD_NUM, 421 }; 422 423 struct rtw89_txpwr_byrate { 424 s8 cck[RTW89_RATE_CCK_MAX]; 425 s8 ofdm[RTW89_RATE_OFDM_MAX]; 426 s8 mcs[RTW89_NSS_MAX][RTW89_RATE_MCS_MAX]; 427 s8 hedcm[RTW89_NSS_HEDCM_MAX][RTW89_RATE_HEDCM_MAX]; 428 s8 offset[RTW89_RATE_OFFSET_MAX]; 429 }; 430 431 enum rtw89_bandwidth_section_num { 432 RTW89_BW20_SEC_NUM = 8, 433 RTW89_BW40_SEC_NUM = 4, 434 RTW89_BW80_SEC_NUM = 2, 435 }; 436 437 struct rtw89_txpwr_limit { 438 s8 cck_20m[RTW89_BF_NUM]; 439 s8 cck_40m[RTW89_BF_NUM]; 440 s8 ofdm[RTW89_BF_NUM]; 441 s8 mcs_20m[RTW89_BW20_SEC_NUM][RTW89_BF_NUM]; 442 s8 mcs_40m[RTW89_BW40_SEC_NUM][RTW89_BF_NUM]; 443 s8 mcs_80m[RTW89_BW80_SEC_NUM][RTW89_BF_NUM]; 444 s8 mcs_160m[RTW89_BF_NUM]; 445 s8 mcs_40m_0p5[RTW89_BF_NUM]; 446 s8 mcs_40m_2p5[RTW89_BF_NUM]; 447 }; 448 449 #define RTW89_RU_SEC_NUM 8 450 451 struct rtw89_txpwr_limit_ru { 452 s8 ru26[RTW89_RU_SEC_NUM]; 453 s8 ru52[RTW89_RU_SEC_NUM]; 454 s8 ru106[RTW89_RU_SEC_NUM]; 455 }; 456 457 struct rtw89_rate_desc { 458 enum rtw89_nss nss; 459 enum rtw89_rate_section rs; 460 u8 idx; 461 }; 462 463 #define PHY_STS_HDR_LEN 8 464 #define RF_PATH_MAX 4 465 #define RTW89_MAX_PPDU_CNT 8 466 struct rtw89_rx_phy_ppdu { 467 u8 *buf; 468 u32 len; 469 u8 rssi_avg; 470 s8 rssi[RF_PATH_MAX]; 471 u8 mac_id; 472 u8 chan_idx; 473 u8 ie; 474 u16 rate; 475 bool to_self; 476 bool valid; 477 }; 478 479 enum rtw89_mac_idx { 480 RTW89_MAC_0 = 0, 481 RTW89_MAC_1 = 1, 482 }; 483 484 enum rtw89_phy_idx { 485 RTW89_PHY_0 = 0, 486 RTW89_PHY_1 = 1, 487 RTW89_PHY_MAX 488 }; 489 490 enum rtw89_rf_path { 491 RF_PATH_A = 0, 492 RF_PATH_B = 1, 493 RF_PATH_C = 2, 494 RF_PATH_D = 3, 495 RF_PATH_AB, 496 RF_PATH_AC, 497 RF_PATH_AD, 498 RF_PATH_BC, 499 RF_PATH_BD, 500 RF_PATH_CD, 501 RF_PATH_ABC, 502 RF_PATH_ABD, 503 RF_PATH_ACD, 504 RF_PATH_BCD, 505 RF_PATH_ABCD, 506 }; 507 508 enum rtw89_rf_path_bit { 509 RF_A = BIT(0), 510 RF_B = BIT(1), 511 RF_C = BIT(2), 512 RF_D = BIT(3), 513 514 RF_AB = (RF_A | RF_B), 515 RF_AC = (RF_A | RF_C), 516 RF_AD = (RF_A | RF_D), 517 RF_BC = (RF_B | RF_C), 518 RF_BD = (RF_B | RF_D), 519 RF_CD = (RF_C | RF_D), 520 521 RF_ABC = (RF_A | RF_B | RF_C), 522 RF_ABD = (RF_A | RF_B | RF_D), 523 RF_ACD = (RF_A | RF_C | RF_D), 524 RF_BCD = (RF_B | RF_C | RF_D), 525 526 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 527 }; 528 529 enum rtw89_bandwidth { 530 RTW89_CHANNEL_WIDTH_20 = 0, 531 RTW89_CHANNEL_WIDTH_40 = 1, 532 RTW89_CHANNEL_WIDTH_80 = 2, 533 RTW89_CHANNEL_WIDTH_160 = 3, 534 RTW89_CHANNEL_WIDTH_80_80 = 4, 535 RTW89_CHANNEL_WIDTH_5 = 5, 536 RTW89_CHANNEL_WIDTH_10 = 6, 537 }; 538 539 enum rtw89_ps_mode { 540 RTW89_PS_MODE_NONE = 0, 541 RTW89_PS_MODE_RFOFF = 1, 542 RTW89_PS_MODE_CLK_GATED = 2, 543 RTW89_PS_MODE_PWR_GATED = 3, 544 }; 545 546 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 547 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1) 548 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_80 + 1) 549 550 enum rtw89_ru_bandwidth { 551 RTW89_RU26 = 0, 552 RTW89_RU52 = 1, 553 RTW89_RU106 = 2, 554 RTW89_RU_NUM, 555 }; 556 557 enum rtw89_sc_offset { 558 RTW89_SC_DONT_CARE = 0, 559 RTW89_SC_20_UPPER = 1, 560 RTW89_SC_20_LOWER = 2, 561 RTW89_SC_20_UPMOST = 3, 562 RTW89_SC_20_LOWEST = 4, 563 RTW89_SC_40_UPPER = 9, 564 RTW89_SC_40_LOWER = 10, 565 }; 566 567 struct rtw89_channel_params { 568 u8 center_chan; 569 u8 primary_chan; 570 u8 bandwidth; 571 u8 pri_ch_idx; 572 u8 band_type; 573 u8 subband_type; 574 }; 575 576 struct rtw89_channel_help_params { 577 u16 tx_en; 578 }; 579 580 struct rtw89_port_reg { 581 u32 port_cfg; 582 u32 tbtt_prohib; 583 u32 bcn_area; 584 u32 bcn_early; 585 u32 tbtt_early; 586 u32 tbtt_agg; 587 u32 bcn_space; 588 u32 bcn_forcetx; 589 u32 bcn_err_cnt; 590 u32 bcn_err_flag; 591 u32 dtim_ctrl; 592 u32 tbtt_shift; 593 u32 bcn_cnt_tmr; 594 u32 tsftr_l; 595 u32 tsftr_h; 596 }; 597 598 struct rtw89_txwd_body { 599 __le32 dword0; 600 __le32 dword1; 601 __le32 dword2; 602 __le32 dword3; 603 __le32 dword4; 604 __le32 dword5; 605 } __packed; 606 607 struct rtw89_txwd_info { 608 __le32 dword0; 609 __le32 dword1; 610 __le32 dword2; 611 __le32 dword3; 612 __le32 dword4; 613 __le32 dword5; 614 } __packed; 615 616 struct rtw89_rx_desc_info { 617 u16 pkt_size; 618 u8 pkt_type; 619 u8 drv_info_size; 620 u8 shift; 621 u8 wl_hd_iv_len; 622 bool long_rxdesc; 623 bool bb_sel; 624 bool mac_info_valid; 625 u16 data_rate; 626 u8 gi_ltf; 627 u8 bw; 628 u32 free_run_cnt; 629 u8 user_id; 630 bool sr_en; 631 u8 ppdu_cnt; 632 u8 ppdu_type; 633 bool icv_err; 634 bool crc32_err; 635 bool hw_dec; 636 bool sw_dec; 637 bool addr1_match; 638 u8 frag; 639 u16 seq; 640 u8 frame_type; 641 u8 rx_pl_id; 642 bool addr_cam_valid; 643 u8 addr_cam_id; 644 u8 sec_cam_id; 645 u8 mac_id; 646 u16 offset; 647 bool ready; 648 }; 649 650 struct rtw89_rxdesc_short { 651 __le32 dword0; 652 __le32 dword1; 653 __le32 dword2; 654 __le32 dword3; 655 } __packed; 656 657 struct rtw89_rxdesc_long { 658 __le32 dword0; 659 __le32 dword1; 660 __le32 dword2; 661 __le32 dword3; 662 __le32 dword4; 663 __le32 dword5; 664 __le32 dword6; 665 __le32 dword7; 666 } __packed; 667 668 struct rtw89_tx_desc_info { 669 u16 pkt_size; 670 u8 wp_offset; 671 u8 mac_id; 672 u8 qsel; 673 u8 ch_dma; 674 u8 hdr_llc_len; 675 bool is_bmc; 676 bool en_wd_info; 677 bool wd_page; 678 bool use_rate; 679 bool dis_data_fb; 680 bool tid_indicate; 681 bool agg_en; 682 bool bk; 683 u8 ampdu_density; 684 u8 ampdu_num; 685 bool sec_en; 686 u8 sec_type; 687 u8 sec_cam_idx; 688 u16 data_rate; 689 u16 data_retry_lowest_rate; 690 bool fw_dl; 691 u16 seq; 692 bool a_ctrl_bsr; 693 u8 hw_ssn_sel; 694 #define RTW89_MGMT_HW_SSN_SEL 1 695 u8 hw_seq_mode; 696 #define RTW89_MGMT_HW_SEQ_MODE 1 697 bool hiq; 698 u8 port; 699 }; 700 701 struct rtw89_core_tx_request { 702 enum rtw89_core_tx_type tx_type; 703 704 struct sk_buff *skb; 705 struct ieee80211_vif *vif; 706 struct ieee80211_sta *sta; 707 struct rtw89_tx_desc_info desc_info; 708 }; 709 710 struct rtw89_txq { 711 struct list_head list; 712 unsigned long flags; 713 int wait_cnt; 714 }; 715 716 struct rtw89_mac_ax_gnt { 717 u8 gnt_bt_sw_en; 718 u8 gnt_bt; 719 u8 gnt_wl_sw_en; 720 u8 gnt_wl; 721 }; 722 723 #define RTW89_MAC_AX_COEX_GNT_NR 2 724 struct rtw89_mac_ax_coex_gnt { 725 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 726 }; 727 728 enum rtw89_btc_ncnt { 729 BTC_NCNT_POWER_ON = 0x0, 730 BTC_NCNT_POWER_OFF, 731 BTC_NCNT_INIT_COEX, 732 BTC_NCNT_SCAN_START, 733 BTC_NCNT_SCAN_FINISH, 734 BTC_NCNT_SPECIAL_PACKET, 735 BTC_NCNT_SWITCH_BAND, 736 BTC_NCNT_RFK_TIMEOUT, 737 BTC_NCNT_SHOW_COEX_INFO, 738 BTC_NCNT_ROLE_INFO, 739 BTC_NCNT_CONTROL, 740 BTC_NCNT_RADIO_STATE, 741 BTC_NCNT_CUSTOMERIZE, 742 BTC_NCNT_WL_RFK, 743 BTC_NCNT_WL_STA, 744 BTC_NCNT_FWINFO, 745 BTC_NCNT_TIMER, 746 BTC_NCNT_NUM 747 }; 748 749 enum rtw89_btc_btinfo { 750 BTC_BTINFO_L0 = 0, 751 BTC_BTINFO_L1, 752 BTC_BTINFO_L2, 753 BTC_BTINFO_L3, 754 BTC_BTINFO_H0, 755 BTC_BTINFO_H1, 756 BTC_BTINFO_H2, 757 BTC_BTINFO_H3, 758 BTC_BTINFO_MAX 759 }; 760 761 enum rtw89_btc_dcnt { 762 BTC_DCNT_RUN = 0x0, 763 BTC_DCNT_CX_RUNINFO, 764 BTC_DCNT_RPT, 765 BTC_DCNT_RPT_FREEZE, 766 BTC_DCNT_CYCLE, 767 BTC_DCNT_CYCLE_FREEZE, 768 BTC_DCNT_W1, 769 BTC_DCNT_W1_FREEZE, 770 BTC_DCNT_B1, 771 BTC_DCNT_B1_FREEZE, 772 BTC_DCNT_TDMA_NONSYNC, 773 BTC_DCNT_SLOT_NONSYNC, 774 BTC_DCNT_BTCNT_FREEZE, 775 BTC_DCNT_WL_SLOT_DRIFT, 776 BTC_DCNT_WL_STA_LAST, 777 BTC_DCNT_NUM, 778 }; 779 780 enum rtw89_btc_wl_state_cnt { 781 BTC_WCNT_SCANAP = 0x0, 782 BTC_WCNT_DHCP, 783 BTC_WCNT_EAPOL, 784 BTC_WCNT_ARP, 785 BTC_WCNT_SCBDUPDATE, 786 BTC_WCNT_RFK_REQ, 787 BTC_WCNT_RFK_GO, 788 BTC_WCNT_RFK_REJECT, 789 BTC_WCNT_RFK_TIMEOUT, 790 BTC_WCNT_CH_UPDATE, 791 BTC_WCNT_NUM 792 }; 793 794 enum rtw89_btc_bt_state_cnt { 795 BTC_BCNT_RETRY = 0x0, 796 BTC_BCNT_REINIT, 797 BTC_BCNT_REENABLE, 798 BTC_BCNT_SCBDREAD, 799 BTC_BCNT_RELINK, 800 BTC_BCNT_IGNOWL, 801 BTC_BCNT_INQPAG, 802 BTC_BCNT_INQ, 803 BTC_BCNT_PAGE, 804 BTC_BCNT_ROLESW, 805 BTC_BCNT_AFH, 806 BTC_BCNT_INFOUPDATE, 807 BTC_BCNT_INFOSAME, 808 BTC_BCNT_SCBDUPDATE, 809 BTC_BCNT_HIPRI_TX, 810 BTC_BCNT_HIPRI_RX, 811 BTC_BCNT_LOPRI_TX, 812 BTC_BCNT_LOPRI_RX, 813 BTC_BCNT_POLUT, 814 BTC_BCNT_RATECHG, 815 BTC_BCNT_NUM 816 }; 817 818 enum rtw89_btc_bt_profile { 819 BTC_BT_NOPROFILE = 0, 820 BTC_BT_HFP = BIT(0), 821 BTC_BT_HID = BIT(1), 822 BTC_BT_A2DP = BIT(2), 823 BTC_BT_PAN = BIT(3), 824 BTC_PROFILE_MAX = 4, 825 }; 826 827 struct rtw89_btc_ant_info { 828 u8 type; /* shared, dedicated */ 829 u8 num; 830 u8 isolation; 831 832 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 833 u8 diversity: 1; 834 }; 835 836 enum rtw89_tfc_dir { 837 RTW89_TFC_UL, 838 RTW89_TFC_DL, 839 }; 840 841 struct rtw89_btc_wl_smap { 842 u32 busy: 1; 843 u32 scan: 1; 844 u32 connecting: 1; 845 u32 roaming: 1; 846 u32 _4way: 1; 847 u32 rf_off: 1; 848 u32 lps: 1; 849 u32 ips: 1; 850 u32 init_ok: 1; 851 u32 traffic_dir : 2; 852 u32 rf_off_pre: 1; 853 u32 lps_pre: 1; 854 }; 855 856 enum rtw89_tfc_lv { 857 RTW89_TFC_IDLE, 858 RTW89_TFC_ULTRA_LOW, 859 RTW89_TFC_LOW, 860 RTW89_TFC_MID, 861 RTW89_TFC_HIGH, 862 }; 863 864 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 865 DECLARE_EWMA(tp, 10, 2); 866 867 struct rtw89_traffic_stats { 868 /* units in bytes */ 869 u64 tx_unicast; 870 u64 rx_unicast; 871 u32 tx_avg_len; 872 u32 rx_avg_len; 873 874 /* count for packets */ 875 u64 tx_cnt; 876 u64 rx_cnt; 877 878 /* units in Mbps */ 879 u32 tx_throughput; 880 u32 rx_throughput; 881 u32 tx_throughput_raw; 882 u32 rx_throughput_raw; 883 enum rtw89_tfc_lv tx_tfc_lv; 884 enum rtw89_tfc_lv rx_tfc_lv; 885 struct ewma_tp tx_ewma_tp; 886 struct ewma_tp rx_ewma_tp; 887 888 u16 tx_rate; 889 u16 rx_rate; 890 }; 891 892 struct rtw89_btc_statistic { 893 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 894 struct rtw89_traffic_stats traffic; 895 }; 896 897 #define BTC_WL_RSSI_THMAX 4 898 899 struct rtw89_btc_wl_link_info { 900 struct rtw89_btc_statistic stat; 901 enum rtw89_tfc_dir dir; 902 u8 rssi_state[BTC_WL_RSSI_THMAX]; 903 u8 mac_addr[ETH_ALEN]; 904 u8 busy; 905 u8 ch; 906 u8 bw; 907 u8 band; 908 u8 role; 909 u8 pid; 910 u8 phy; 911 u8 dtim_period; 912 u8 mode; 913 914 u8 mac_id; 915 u8 tx_retry; 916 917 u32 bcn_period; 918 u32 busy_t; 919 u32 tx_time; 920 u32 client_cnt; 921 u32 rx_rate_drop_cnt; 922 923 u32 active: 1; 924 u32 noa: 1; 925 u32 client_ps: 1; 926 u32 connected: 2; 927 }; 928 929 union rtw89_btc_wl_state_map { 930 u32 val; 931 struct rtw89_btc_wl_smap map; 932 }; 933 934 struct rtw89_btc_bt_hfp_desc { 935 u32 exist: 1; 936 u32 type: 2; 937 u32 rsvd: 29; 938 }; 939 940 struct rtw89_btc_bt_hid_desc { 941 u32 exist: 1; 942 u32 slot_info: 2; 943 u32 pair_cnt: 2; 944 u32 type: 8; 945 u32 rsvd: 19; 946 }; 947 948 struct rtw89_btc_bt_a2dp_desc { 949 u8 exist: 1; 950 u8 exist_last: 1; 951 u8 play_latency: 1; 952 u8 type: 3; 953 u8 active: 1; 954 u8 sink: 1; 955 956 u8 bitpool; 957 u16 vendor_id; 958 u32 device_name; 959 u32 flush_time; 960 }; 961 962 struct rtw89_btc_bt_pan_desc { 963 u32 exist: 1; 964 u32 type: 1; 965 u32 active: 1; 966 u32 rsvd: 29; 967 }; 968 969 struct rtw89_btc_bt_rfk_info { 970 u32 run: 1; 971 u32 req: 1; 972 u32 timeout: 1; 973 u32 rsvd: 29; 974 }; 975 976 union rtw89_btc_bt_rfk_info_map { 977 u32 val; 978 struct rtw89_btc_bt_rfk_info map; 979 }; 980 981 struct rtw89_btc_bt_ver_info { 982 u32 fw_coex; /* match with which coex_ver */ 983 u32 fw; 984 }; 985 986 struct rtw89_btc_bool_sta_chg { 987 u32 now: 1; 988 u32 last: 1; 989 u32 remain: 1; 990 u32 srvd: 29; 991 }; 992 993 struct rtw89_btc_u8_sta_chg { 994 u8 now; 995 u8 last; 996 u8 remain; 997 u8 rsvd; 998 }; 999 1000 struct rtw89_btc_wl_scan_info { 1001 u8 band[RTW89_PHY_MAX]; 1002 u8 phy_map; 1003 u8 rsvd; 1004 }; 1005 1006 struct rtw89_btc_wl_dbcc_info { 1007 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1008 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1009 u8 real_band[RTW89_PHY_MAX]; 1010 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1011 }; 1012 1013 struct rtw89_btc_wl_active_role { 1014 u8 connected: 1; 1015 u8 pid: 3; 1016 u8 phy: 1; 1017 u8 noa: 1; 1018 u8 band: 2; 1019 1020 u8 client_ps: 1; 1021 u8 bw: 7; 1022 1023 u8 role; 1024 u8 ch; 1025 1026 u16 tx_lvl; 1027 u16 rx_lvl; 1028 u16 tx_rate; 1029 u16 rx_rate; 1030 }; 1031 1032 struct rtw89_btc_wl_role_info_bpos { 1033 u16 none: 1; 1034 u16 station: 1; 1035 u16 ap: 1; 1036 u16 vap: 1; 1037 u16 adhoc: 1; 1038 u16 adhoc_master: 1; 1039 u16 mesh: 1; 1040 u16 moniter: 1; 1041 u16 p2p_device: 1; 1042 u16 p2p_gc: 1; 1043 u16 p2p_go: 1; 1044 u16 nan: 1; 1045 }; 1046 1047 union rtw89_btc_wl_role_info_map { 1048 u16 val; 1049 struct rtw89_btc_wl_role_info_bpos role; 1050 }; 1051 1052 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1053 u8 connect_cnt; 1054 u8 link_mode; 1055 union rtw89_btc_wl_role_info_map role_map; 1056 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1057 }; 1058 1059 struct rtw89_btc_wl_ver_info { 1060 u32 fw_coex; /* match with which coex_ver */ 1061 u32 fw; 1062 u32 mac; 1063 u32 bb; 1064 u32 rf; 1065 }; 1066 1067 struct rtw89_btc_wl_afh_info { 1068 u8 en; 1069 u8 ch; 1070 u8 bw; 1071 u8 rsvd; 1072 } __packed; 1073 1074 struct rtw89_btc_wl_rfk_info { 1075 u32 state: 2; 1076 u32 path_map: 4; 1077 u32 phy_map: 2; 1078 u32 band: 2; 1079 u32 type: 8; 1080 u32 rsvd: 14; 1081 }; 1082 1083 struct rtw89_btc_bt_smap { 1084 u32 connect: 1; 1085 u32 ble_connect: 1; 1086 u32 acl_busy: 1; 1087 u32 sco_busy: 1; 1088 u32 mesh_busy: 1; 1089 u32 inq_pag: 1; 1090 }; 1091 1092 union rtw89_btc_bt_state_map { 1093 u32 val; 1094 struct rtw89_btc_bt_smap map; 1095 }; 1096 1097 #define BTC_BT_RSSI_THMAX 4 1098 #define BTC_BT_AFH_GROUP 12 1099 1100 struct rtw89_btc_bt_link_info { 1101 struct rtw89_btc_u8_sta_chg profile_cnt; 1102 struct rtw89_btc_bool_sta_chg multi_link; 1103 struct rtw89_btc_bool_sta_chg relink; 1104 struct rtw89_btc_bt_hfp_desc hfp_desc; 1105 struct rtw89_btc_bt_hid_desc hid_desc; 1106 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1107 struct rtw89_btc_bt_pan_desc pan_desc; 1108 union rtw89_btc_bt_state_map status; 1109 1110 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1111 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1112 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1113 u8 afh_map[BTC_BT_AFH_GROUP]; 1114 1115 u32 role_sw: 1; 1116 u32 slave_role: 1; 1117 u32 afh_update: 1; 1118 u32 cqddr: 1; 1119 u32 rssi: 8; 1120 u32 tx_3m: 1; 1121 u32 rsvd: 19; 1122 }; 1123 1124 struct rtw89_btc_3rdcx_info { 1125 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1126 u8 hw_coex; 1127 u16 rsvd; 1128 }; 1129 1130 struct rtw89_btc_dm_emap { 1131 u32 init: 1; 1132 u32 pta_owner: 1; 1133 u32 wl_rfk_timeout: 1; 1134 u32 bt_rfk_timeout: 1; 1135 1136 u32 wl_fw_hang: 1; 1137 u32 offload_mismatch: 1; 1138 u32 cycle_hang: 1; 1139 u32 w1_hang: 1; 1140 1141 u32 b1_hang: 1; 1142 u32 tdma_no_sync: 1; 1143 u32 wl_slot_drift: 1; 1144 }; 1145 1146 union rtw89_btc_dm_error_map { 1147 u32 val; 1148 struct rtw89_btc_dm_emap map; 1149 }; 1150 1151 struct rtw89_btc_rf_para { 1152 u32 tx_pwr_freerun; 1153 u32 rx_gain_freerun; 1154 u32 tx_pwr_perpkt; 1155 u32 rx_gain_perpkt; 1156 }; 1157 1158 struct rtw89_btc_wl_info { 1159 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1160 struct rtw89_btc_wl_rfk_info rfk_info; 1161 struct rtw89_btc_wl_ver_info ver_info; 1162 struct rtw89_btc_wl_afh_info afh_info; 1163 struct rtw89_btc_wl_role_info role_info; 1164 struct rtw89_btc_wl_scan_info scan_info; 1165 struct rtw89_btc_wl_dbcc_info dbcc_info; 1166 struct rtw89_btc_rf_para rf_para; 1167 union rtw89_btc_wl_state_map status; 1168 1169 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1170 u8 rssi_level; 1171 1172 u32 scbd; 1173 }; 1174 1175 struct rtw89_btc_module { 1176 struct rtw89_btc_ant_info ant; 1177 u8 rfe_type; 1178 u8 cv; 1179 1180 u8 bt_solo: 1; 1181 u8 bt_pos: 1; 1182 u8 switch_type: 1; 1183 1184 u8 rsvd; 1185 }; 1186 1187 #define RTW89_BTC_DM_MAXSTEP 30 1188 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1189 1190 struct rtw89_btc_dm_step { 1191 u16 step[RTW89_BTC_DM_MAXSTEP]; 1192 u8 step_pos; 1193 bool step_ov; 1194 }; 1195 1196 struct rtw89_btc_init_info { 1197 struct rtw89_btc_module module; 1198 u8 wl_guard_ch; 1199 1200 u8 wl_only: 1; 1201 u8 wl_init_ok: 1; 1202 u8 dbcc_en: 1; 1203 u8 cx_other: 1; 1204 u8 bt_only: 1; 1205 1206 u16 rsvd; 1207 }; 1208 1209 struct rtw89_btc_wl_tx_limit_para { 1210 u16 enable; 1211 u32 tx_time; /* unit: us */ 1212 u16 tx_retry; 1213 }; 1214 1215 struct rtw89_btc_bt_scan_info { 1216 u16 win; 1217 u16 intvl; 1218 u32 enable: 1; 1219 u32 interlace: 1; 1220 u32 rsvd: 30; 1221 }; 1222 1223 enum rtw89_btc_bt_scan_type { 1224 BTC_SCAN_INQ = 0, 1225 BTC_SCAN_PAGE, 1226 BTC_SCAN_BLE, 1227 BTC_SCAN_INIT, 1228 BTC_SCAN_TV, 1229 BTC_SCAN_ADV, 1230 BTC_SCAN_MAX1, 1231 }; 1232 1233 struct rtw89_btc_bt_info { 1234 struct rtw89_btc_bt_link_info link_info; 1235 struct rtw89_btc_bt_scan_info scan_info[BTC_SCAN_MAX1]; 1236 struct rtw89_btc_bt_ver_info ver_info; 1237 struct rtw89_btc_bool_sta_chg enable; 1238 struct rtw89_btc_bool_sta_chg inq_pag; 1239 struct rtw89_btc_rf_para rf_para; 1240 union rtw89_btc_bt_rfk_info_map rfk_info; 1241 1242 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1243 1244 u32 scbd; 1245 u32 feature; 1246 1247 u32 mbx_avl: 1; 1248 u32 whql_test: 1; 1249 u32 igno_wl: 1; 1250 u32 reinit: 1; 1251 u32 ble_scan_en: 1; 1252 u32 btg_type: 1; 1253 u32 inq: 1; 1254 u32 pag: 1; 1255 u32 run_patch_code: 1; 1256 u32 hi_lna_rx: 1; 1257 u32 rsvd: 22; 1258 }; 1259 1260 struct rtw89_btc_cx { 1261 struct rtw89_btc_wl_info wl; 1262 struct rtw89_btc_bt_info bt; 1263 struct rtw89_btc_3rdcx_info other; 1264 u32 state_map; 1265 u32 cnt_bt[BTC_BCNT_NUM]; 1266 u32 cnt_wl[BTC_WCNT_NUM]; 1267 }; 1268 1269 struct rtw89_btc_fbtc_tdma { 1270 u8 type; 1271 u8 rxflctrl; 1272 u8 txpause; 1273 u8 wtgle_n; 1274 u8 leak_n; 1275 u8 ext_ctrl; 1276 u8 rsvd0; 1277 u8 rsvd1; 1278 } __packed; 1279 1280 #define CXMREG_MAX 30 1281 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1282 #define BTCRPT_VER 1 1283 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1284 1285 enum rtw89_btc_bt_rfk_counter { 1286 BTC_BCNT_RFK_REQ = 0, 1287 BTC_BCNT_RFK_GO = 1, 1288 BTC_BCNT_RFK_REJECT = 2, 1289 BTC_BCNT_RFK_FAIL = 3, 1290 BTC_BCNT_RFK_TIMEOUT = 4, 1291 BTC_BCNT_RFK_MAX 1292 }; 1293 1294 struct rtw89_btc_fbtc_rpt_ctrl { 1295 u16 fver; 1296 u16 rpt_cnt; /* tmr counters */ 1297 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1298 u32 wl_fw_cx_offload; 1299 u32 wl_fw_ver; 1300 u32 rpt_enable; 1301 u32 rpt_para; /* ms */ 1302 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1303 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1304 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1305 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1306 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1307 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1308 u32 bt_rfk_cnt[BTC_BCNT_RFK_MAX]; 1309 u32 c2h_cnt; /* fw send c2h counter */ 1310 u32 h2c_cnt; /* fw recv h2c counter */ 1311 } __packed; 1312 1313 enum rtw89_fbtc_ext_ctrl_type { 1314 CXECTL_OFF = 0x0, /* tdma off */ 1315 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1316 CXECTL_EXT = 0x2, 1317 CXECTL_MAX 1318 }; 1319 1320 union rtw89_btc_fbtc_rxflct { 1321 u8 val; 1322 u8 type: 3; 1323 u8 tgln_n: 5; 1324 }; 1325 1326 enum rtw89_btc_cxst_state { 1327 CXST_OFF = 0x0, 1328 CXST_B2W = 0x1, 1329 CXST_W1 = 0x2, 1330 CXST_W2 = 0x3, 1331 CXST_W2B = 0x4, 1332 CXST_B1 = 0x5, 1333 CXST_B2 = 0x6, 1334 CXST_B3 = 0x7, 1335 CXST_B4 = 0x8, 1336 CXST_LK = 0x9, 1337 CXST_BLK = 0xa, 1338 CXST_E2G = 0xb, 1339 CXST_E5G = 0xc, 1340 CXST_EBT = 0xd, 1341 CXST_ENULL = 0xe, 1342 CXST_WLK = 0xf, 1343 CXST_W1FDD = 0x10, 1344 CXST_B1FDD = 0x11, 1345 CXST_MAX = 0x12, 1346 }; 1347 1348 enum { 1349 CXBCN_ALL = 0x0, 1350 CXBCN_ALL_OK, 1351 CXBCN_BT_SLOT, 1352 CXBCN_BT_OK, 1353 CXBCN_MAX 1354 }; 1355 1356 enum btc_slot_type { 1357 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 1358 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 1359 CXSTYPE_NUM, 1360 }; 1361 1362 enum { /* TIME */ 1363 CXT_BT = 0x0, 1364 CXT_WL = 0x1, 1365 CXT_MAX 1366 }; 1367 1368 enum { /* TIME-A2DP */ 1369 CXT_FLCTRL_OFF = 0x0, 1370 CXT_FLCTRL_ON = 0x1, 1371 CXT_FLCTRL_MAX 1372 }; 1373 1374 enum { /* STEP TYPE */ 1375 CXSTEP_NONE = 0x0, 1376 CXSTEP_EVNT = 0x1, 1377 CXSTEP_SLOT = 0x2, 1378 CXSTEP_MAX, 1379 }; 1380 1381 #define FCXGPIODBG_VER 1 1382 #define BTC_DBG_MAX1 32 1383 struct rtw89_btc_fbtc_gpio_dbg { 1384 u8 fver; 1385 u8 rsvd; 1386 u16 rsvd2; 1387 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 1388 u32 pre_state; /* the debug signal is 1 or 0 */ 1389 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 1390 } __packed; 1391 1392 #define FCXMREG_VER 1 1393 struct rtw89_btc_fbtc_mreg_val { 1394 u8 fver; 1395 u8 reg_num; 1396 __le16 rsvd; 1397 __le32 mreg_val[CXMREG_MAX]; 1398 } __packed; 1399 1400 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 1401 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 1402 .offset = cpu_to_le32(__offset), } 1403 1404 struct rtw89_btc_fbtc_mreg { 1405 __le16 type; 1406 __le16 bytes; 1407 __le32 offset; 1408 } __packed; 1409 1410 struct rtw89_btc_fbtc_slot { 1411 __le16 dur; 1412 __le32 cxtbl; 1413 __le16 cxtype; 1414 } __packed; 1415 1416 #define FCXSLOTS_VER 1 1417 struct rtw89_btc_fbtc_slots { 1418 u8 fver; 1419 u8 tbl_num; 1420 __le16 rsvd; 1421 __le32 update_map; 1422 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1423 } __packed; 1424 1425 #define FCXSTEP_VER 2 1426 struct rtw89_btc_fbtc_step { 1427 u8 type; 1428 u8 val; 1429 __le16 difft; 1430 } __packed; 1431 1432 struct rtw89_btc_fbtc_steps { 1433 u8 fver; 1434 u8 rsvd; 1435 __le16 cnt; 1436 __le16 pos_old; 1437 __le16 pos_new; 1438 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 1439 } __packed; 1440 1441 #define FCXCYSTA_VER 2 1442 struct rtw89_btc_fbtc_cysta { /* statistics for cycles */ 1443 u8 fver; 1444 u8 rsvd; 1445 __le16 cycles; /* total cycle number */ 1446 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 1447 __le16 a2dpept; /* a2dp empty cnt */ 1448 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 1449 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 1450 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 1451 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 1452 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 1453 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 1454 __le16 tavg_a2dpept; /* avg a2dp empty time */ 1455 __le16 tmax_a2dpept; /* max a2dp empty time */ 1456 __le16 tavg_lk; /* avg leak-slot time */ 1457 __le16 tmax_lk; /* max leak-slot time */ 1458 __le32 slot_cnt[CXST_MAX]; /* slot count */ 1459 __le32 bcn_cnt[CXBCN_MAX]; 1460 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 1461 __le32 collision_cnt; /* counter for event/timer occur at same time */ 1462 __le32 skip_cnt; 1463 __le32 exception; 1464 __le32 except_cnt; 1465 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 1466 } __packed; 1467 1468 #define FCXNULLSTA_VER 1 1469 struct rtw89_btc_fbtc_cynullsta { /* cycle null statistics */ 1470 u8 fver; 1471 u8 rsvd; 1472 __le16 rsvd2; 1473 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 1474 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 1475 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 1476 } __packed; 1477 1478 #define FCX_BTVER_VER 1 1479 struct rtw89_btc_fbtc_btver { 1480 u8 fver; 1481 u8 rsvd; 1482 __le16 rsvd2; 1483 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 1484 __le32 fw_ver; 1485 __le32 feature; 1486 } __packed; 1487 1488 #define FCX_BTSCAN_VER 1 1489 struct rtw89_btc_fbtc_btscan { 1490 u8 fver; 1491 u8 rsvd; 1492 __le16 rsvd2; 1493 u8 scan[6]; 1494 } __packed; 1495 1496 #define FCX_BTAFH_VER 1 1497 struct rtw89_btc_fbtc_btafh { 1498 u8 fver; 1499 u8 rsvd; 1500 __le16 rsvd2; 1501 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 1502 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 1503 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 1504 } __packed; 1505 1506 #define FCX_BTDEVINFO_VER 1 1507 struct rtw89_btc_fbtc_btdevinfo { 1508 u8 fver; 1509 u8 rsvd; 1510 __le16 vendor_id; 1511 __le32 dev_name; /* only 24 bits valid */ 1512 __le32 flush_time; 1513 } __packed; 1514 1515 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 1516 struct rtw89_btc_rf_trx_para { 1517 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 1518 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 1519 u8 bt_tx_power; /* decrease Tx power (dB) */ 1520 u8 bt_rx_gain; /* LNA constrain level */ 1521 }; 1522 1523 struct rtw89_btc_dm { 1524 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 1525 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 1526 struct rtw89_btc_fbtc_tdma tdma; 1527 struct rtw89_btc_fbtc_tdma tdma_now; 1528 struct rtw89_mac_ax_coex_gnt gnt; 1529 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 1530 struct rtw89_btc_rf_trx_para rf_trx_para; 1531 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 1532 struct rtw89_btc_dm_step dm_step; 1533 union rtw89_btc_dm_error_map error; 1534 u32 cnt_dm[BTC_DCNT_NUM]; 1535 u32 cnt_notify[BTC_NCNT_NUM]; 1536 1537 u32 update_slot_map; 1538 u32 set_ant_path; 1539 1540 u32 wl_only: 1; 1541 u32 wl_fw_cx_offload: 1; 1542 u32 freerun: 1; 1543 u32 wl_ps_ctrl: 2; 1544 u32 wl_mimo_ps: 1; 1545 u32 leak_ap: 1; 1546 u32 noisy_level: 3; 1547 u32 coex_info_map: 8; 1548 u32 bt_only: 1; 1549 u32 wl_btg_rx: 1; 1550 u32 trx_para_level: 8; 1551 u32 wl_stb_chg: 1; 1552 u32 rsvd: 3; 1553 1554 u16 slot_dur[CXST_MAX]; 1555 1556 u8 run_reason; 1557 u8 run_action; 1558 }; 1559 1560 struct rtw89_btc_ctrl { 1561 u32 manual: 1; 1562 u32 igno_bt: 1; 1563 u32 always_freerun: 1; 1564 u32 trace_step: 16; 1565 u32 rsvd: 12; 1566 }; 1567 1568 struct rtw89_btc_dbg { 1569 /* cmd "rb" */ 1570 bool rb_done; 1571 u32 rb_val; 1572 }; 1573 1574 #define FCXTDMA_VER 1 1575 1576 enum rtw89_btc_btf_fw_event { 1577 BTF_EVNT_RPT = 0, 1578 BTF_EVNT_BT_INFO = 1, 1579 BTF_EVNT_BT_SCBD = 2, 1580 BTF_EVNT_BT_REG = 3, 1581 BTF_EVNT_CX_RUNINFO = 4, 1582 BTF_EVNT_BT_PSD = 5, 1583 BTF_EVNT_BUF_OVERFLOW, 1584 BTF_EVNT_C2H_LOOPBACK, 1585 BTF_EVNT_MAX, 1586 }; 1587 1588 enum btf_fw_event_report { 1589 BTC_RPT_TYPE_CTRL = 0x0, 1590 BTC_RPT_TYPE_TDMA, 1591 BTC_RPT_TYPE_SLOT, 1592 BTC_RPT_TYPE_CYSTA, 1593 BTC_RPT_TYPE_STEP, 1594 BTC_RPT_TYPE_NULLSTA, 1595 BTC_RPT_TYPE_MREG, 1596 BTC_RPT_TYPE_GPIO_DBG, 1597 BTC_RPT_TYPE_BT_VER, 1598 BTC_RPT_TYPE_BT_SCAN, 1599 BTC_RPT_TYPE_BT_AFH, 1600 BTC_RPT_TYPE_BT_DEVICE, 1601 BTC_RPT_TYPE_TEST, 1602 BTC_RPT_TYPE_MAX = 31 1603 }; 1604 1605 enum rtw_btc_btf_reg_type { 1606 REG_MAC = 0x0, 1607 REG_BB = 0x1, 1608 REG_RF = 0x2, 1609 REG_BT_RF = 0x3, 1610 REG_BT_MODEM = 0x4, 1611 REG_BT_BLUEWIZE = 0x5, 1612 REG_BT_VENDOR = 0x6, 1613 REG_BT_LE = 0x7, 1614 REG_MAX_TYPE, 1615 }; 1616 1617 struct rtw89_btc_rpt_cmn_info { 1618 u32 rx_cnt; 1619 u32 rx_len; 1620 u32 req_len; /* expected rsp len */ 1621 u8 req_fver; /* expected rsp fver */ 1622 u8 rsp_fver; /* fver from fw */ 1623 u8 valid; 1624 } __packed; 1625 1626 struct rtw89_btc_report_ctrl_state { 1627 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1628 struct rtw89_btc_fbtc_rpt_ctrl finfo; /* info from fw */ 1629 }; 1630 1631 struct rtw89_btc_rpt_fbtc_tdma { 1632 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1633 struct rtw89_btc_fbtc_tdma finfo; /* info from fw */ 1634 }; 1635 1636 struct rtw89_btc_rpt_fbtc_slots { 1637 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1638 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 1639 }; 1640 1641 struct rtw89_btc_rpt_fbtc_cysta { 1642 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1643 struct rtw89_btc_fbtc_cysta finfo; /* info from fw */ 1644 }; 1645 1646 struct rtw89_btc_rpt_fbtc_step { 1647 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1648 struct rtw89_btc_fbtc_steps finfo; /* info from fw */ 1649 }; 1650 1651 struct rtw89_btc_rpt_fbtc_nullsta { 1652 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1653 struct rtw89_btc_fbtc_cynullsta finfo; /* info from fw */ 1654 }; 1655 1656 struct rtw89_btc_rpt_fbtc_mreg { 1657 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1658 struct rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 1659 }; 1660 1661 struct rtw89_btc_rpt_fbtc_gpio_dbg { 1662 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1663 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 1664 }; 1665 1666 struct rtw89_btc_rpt_fbtc_btver { 1667 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1668 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 1669 }; 1670 1671 struct rtw89_btc_rpt_fbtc_btscan { 1672 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1673 struct rtw89_btc_fbtc_btscan finfo; /* info from fw */ 1674 }; 1675 1676 struct rtw89_btc_rpt_fbtc_btafh { 1677 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1678 struct rtw89_btc_fbtc_btafh finfo; /* info from fw */ 1679 }; 1680 1681 struct rtw89_btc_rpt_fbtc_btdev { 1682 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 1683 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 1684 }; 1685 1686 enum rtw89_btc_btfre_type { 1687 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 1688 BTFRE_UNDEF_TYPE, 1689 BTFRE_EXCEPTION, 1690 BTFRE_MAX, 1691 }; 1692 1693 struct rtw89_btc_btf_fwinfo { 1694 u32 cnt_c2h; 1695 u32 cnt_h2c; 1696 u32 cnt_h2c_fail; 1697 u32 event[BTF_EVNT_MAX]; 1698 1699 u32 err[BTFRE_MAX]; 1700 u32 len_mismch; 1701 u32 fver_mismch; 1702 u32 rpt_en_map; 1703 1704 struct rtw89_btc_report_ctrl_state rpt_ctrl; 1705 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 1706 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 1707 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 1708 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 1709 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 1710 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 1711 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 1712 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 1713 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 1714 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 1715 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 1716 }; 1717 1718 #define RTW89_BTC_POLICY_MAXLEN 512 1719 1720 struct rtw89_btc { 1721 struct rtw89_btc_cx cx; 1722 struct rtw89_btc_dm dm; 1723 struct rtw89_btc_ctrl ctrl; 1724 struct rtw89_btc_module mdinfo; 1725 struct rtw89_btc_btf_fwinfo fwinfo; 1726 struct rtw89_btc_dbg dbg; 1727 1728 struct work_struct eapol_notify_work; 1729 struct work_struct arp_notify_work; 1730 struct work_struct dhcp_notify_work; 1731 struct work_struct icmp_notify_work; 1732 1733 u32 bt_req_len; 1734 1735 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 1736 u16 policy_len; 1737 u16 policy_type; 1738 bool bt_req_en; 1739 bool update_policy_force; 1740 bool lps; 1741 }; 1742 1743 enum rtw89_ra_mode { 1744 RTW89_RA_MODE_CCK = BIT(0), 1745 RTW89_RA_MODE_OFDM = BIT(1), 1746 RTW89_RA_MODE_HT = BIT(2), 1747 RTW89_RA_MODE_VHT = BIT(3), 1748 RTW89_RA_MODE_HE = BIT(4), 1749 }; 1750 1751 enum rtw89_ra_report_mode { 1752 RTW89_RA_RPT_MODE_LEGACY, 1753 RTW89_RA_RPT_MODE_HT, 1754 RTW89_RA_RPT_MODE_VHT, 1755 RTW89_RA_RPT_MODE_HE, 1756 }; 1757 1758 enum rtw89_dig_noisy_level { 1759 RTW89_DIG_NOISY_LEVEL0 = -1, 1760 RTW89_DIG_NOISY_LEVEL1 = 0, 1761 RTW89_DIG_NOISY_LEVEL2 = 1, 1762 RTW89_DIG_NOISY_LEVEL3 = 2, 1763 RTW89_DIG_NOISY_LEVEL_MAX = 3, 1764 }; 1765 1766 enum rtw89_gi_ltf { 1767 RTW89_GILTF_LGI_4XHE32 = 0, 1768 RTW89_GILTF_SGI_4XHE08 = 1, 1769 RTW89_GILTF_2XHE16 = 2, 1770 RTW89_GILTF_2XHE08 = 3, 1771 RTW89_GILTF_1XHE16 = 4, 1772 RTW89_GILTF_1XHE08 = 5, 1773 RTW89_GILTF_MAX 1774 }; 1775 1776 enum rtw89_rx_frame_type { 1777 RTW89_RX_TYPE_MGNT = 0, 1778 RTW89_RX_TYPE_CTRL = 1, 1779 RTW89_RX_TYPE_DATA = 2, 1780 RTW89_RX_TYPE_RSVD = 3, 1781 }; 1782 1783 struct rtw89_ra_info { 1784 u8 is_dis_ra:1; 1785 /* Bit0 : CCK 1786 * Bit1 : OFDM 1787 * Bit2 : HT 1788 * Bit3 : VHT 1789 * Bit4 : HE 1790 */ 1791 u8 mode_ctrl:5; 1792 u8 bw_cap:2; 1793 u8 macid; 1794 u8 dcm_cap:1; 1795 u8 er_cap:1; 1796 u8 init_rate_lv:2; 1797 u8 upd_all:1; 1798 u8 en_sgi:1; 1799 u8 ldpc_cap:1; 1800 u8 stbc_cap:1; 1801 u8 ss_num:3; 1802 u8 giltf:3; 1803 u8 upd_bw_nss_mask:1; 1804 u8 upd_mask:1; 1805 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 1806 /* BFee CSI */ 1807 u8 band_num; 1808 u8 ra_csi_rate_en:1; 1809 u8 fixed_csi_rate_en:1; 1810 u8 cr_tbl_sel:1; 1811 u8 rsvd2:5; 1812 u8 csi_mcs_ss_idx; 1813 u8 csi_mode:2; 1814 u8 csi_gi_ltf:3; 1815 u8 csi_bw:3; 1816 }; 1817 1818 #define RTW89_PPDU_MAX_USR 4 1819 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 1820 #define RTW89_PPDU_MAC_INFO_SIZE 8 1821 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 1822 1823 #define RTW89_MAX_RX_AGG_NUM 64 1824 #define RTW89_MAX_TX_AGG_NUM 128 1825 1826 struct rtw89_ampdu_params { 1827 u16 agg_num; 1828 bool amsdu; 1829 }; 1830 1831 struct rtw89_ra_report { 1832 struct rate_info txrate; 1833 u32 bit_rate; 1834 u16 hw_rate; 1835 }; 1836 1837 DECLARE_EWMA(rssi, 10, 16); 1838 1839 #define RTW89_BA_CAM_NUM 2 1840 1841 struct rtw89_ba_cam_entry { 1842 u8 tid; 1843 }; 1844 1845 #define RTW89_MAX_ADDR_CAM_NUM 128 1846 #define RTW89_MAX_BSSID_CAM_NUM 20 1847 #define RTW89_MAX_SEC_CAM_NUM 128 1848 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 1849 1850 struct rtw89_addr_cam_entry { 1851 u8 addr_cam_idx; 1852 u8 offset; 1853 u8 len; 1854 u8 valid : 1; 1855 u8 addr_mask : 6; 1856 u8 wapi : 1; 1857 u8 mask_sel : 2; 1858 u8 bssid_cam_idx: 6; 1859 1860 u8 sec_ent_mode; 1861 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 1862 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 1863 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 1864 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 1865 }; 1866 1867 struct rtw89_bssid_cam_entry { 1868 u8 bssid[ETH_ALEN]; 1869 u8 phy_idx; 1870 u8 bssid_cam_idx; 1871 u8 offset; 1872 u8 len; 1873 u8 valid : 1; 1874 u8 num; 1875 }; 1876 1877 struct rtw89_sec_cam_entry { 1878 u8 sec_cam_idx; 1879 u8 offset; 1880 u8 len; 1881 u8 type : 4; 1882 u8 ext_key : 1; 1883 u8 spp_mode : 1; 1884 /* 256 bits */ 1885 u8 key[32]; 1886 }; 1887 1888 struct rtw89_sta { 1889 u8 mac_id; 1890 bool disassoc; 1891 struct rtw89_vif *rtwvif; 1892 struct rtw89_ra_info ra; 1893 struct rtw89_ra_report ra_report; 1894 int max_agg_wait; 1895 u8 prev_rssi; 1896 struct ewma_rssi avg_rssi; 1897 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 1898 struct ieee80211_rx_status rx_status; 1899 u16 rx_hw_rate; 1900 __le32 htc_template; 1901 struct rtw89_addr_cam_entry addr_cam; /* AP mode only */ 1902 1903 bool use_cfg_mask; 1904 struct cfg80211_bitrate_mask mask; 1905 1906 bool cctl_tx_time; 1907 u32 ampdu_max_time:4; 1908 bool cctl_tx_retry_limit; 1909 u32 data_tx_cnt_lmt:6; 1910 1911 DECLARE_BITMAP(ba_cam_map, RTW89_BA_CAM_NUM); 1912 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_BA_CAM_NUM]; 1913 }; 1914 1915 struct rtw89_efuse { 1916 bool valid; 1917 u8 xtal_cap; 1918 u8 addr[ETH_ALEN]; 1919 u8 rfe_type; 1920 char country_code[2]; 1921 }; 1922 1923 struct rtw89_phy_rate_pattern { 1924 u64 ra_mask; 1925 u16 rate; 1926 u8 ra_mode; 1927 bool enable; 1928 }; 1929 1930 struct rtw89_vif { 1931 struct list_head list; 1932 struct rtw89_dev *rtwdev; 1933 u8 mac_id; 1934 u8 port; 1935 u8 mac_addr[ETH_ALEN]; 1936 u8 bssid[ETH_ALEN]; 1937 u8 phy_idx; 1938 u8 mac_idx; 1939 u8 net_type; 1940 u8 wifi_role; 1941 u8 self_role; 1942 u8 wmm; 1943 u8 bcn_hit_cond; 1944 u8 hit_rule; 1945 bool trigger; 1946 bool lsig_txop; 1947 u8 tgt_ind; 1948 u8 frm_tgt_ind; 1949 bool wowlan_pattern; 1950 bool wowlan_uc; 1951 bool wowlan_magic; 1952 bool is_hesta; 1953 bool last_a_ctrl; 1954 struct work_struct update_beacon_work; 1955 struct rtw89_addr_cam_entry addr_cam; 1956 struct rtw89_bssid_cam_entry bssid_cam; 1957 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 1958 struct rtw89_traffic_stats stats; 1959 struct rtw89_phy_rate_pattern rate_pattern; 1960 }; 1961 1962 enum rtw89_lv1_rcvy_step { 1963 RTW89_LV1_RCVY_STEP_1, 1964 RTW89_LV1_RCVY_STEP_2, 1965 }; 1966 1967 struct rtw89_hci_ops { 1968 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 1969 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 1970 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 1971 void (*reset)(struct rtw89_dev *rtwdev); 1972 int (*start)(struct rtw89_dev *rtwdev); 1973 void (*stop)(struct rtw89_dev *rtwdev); 1974 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 1975 1976 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 1977 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 1978 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 1979 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 1980 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 1981 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 1982 1983 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 1984 int (*mac_post_init)(struct rtw89_dev *rtwdev); 1985 int (*deinit)(struct rtw89_dev *rtwdev); 1986 1987 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 1988 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 1989 void (*dump_err_status)(struct rtw89_dev *rtwdev); 1990 int (*napi_poll)(struct napi_struct *napi, int budget); 1991 }; 1992 1993 struct rtw89_hci_info { 1994 const struct rtw89_hci_ops *ops; 1995 enum rtw89_hci_type type; 1996 u32 rpwm_addr; 1997 u32 cpwm_addr; 1998 }; 1999 2000 struct rtw89_chip_ops { 2001 void (*bb_reset)(struct rtw89_dev *rtwdev, 2002 enum rtw89_phy_idx phy_idx); 2003 void (*bb_sethw)(struct rtw89_dev *rtwdev); 2004 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2005 u32 addr, u32 mask); 2006 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 2007 u32 addr, u32 mask, u32 data); 2008 void (*set_channel)(struct rtw89_dev *rtwdev, 2009 struct rtw89_channel_params *param); 2010 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 2011 struct rtw89_channel_help_params *p); 2012 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 2013 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 2014 void (*fem_setup)(struct rtw89_dev *rtwdev); 2015 void (*rfk_init)(struct rtw89_dev *rtwdev); 2016 void (*rfk_channel)(struct rtw89_dev *rtwdev); 2017 void (*rfk_band_changed)(struct rtw89_dev *rtwdev); 2018 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 2019 void (*rfk_track)(struct rtw89_dev *rtwdev); 2020 void (*power_trim)(struct rtw89_dev *rtwdev); 2021 void (*set_txpwr)(struct rtw89_dev *rtwdev); 2022 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev); 2023 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 2024 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 2025 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 2026 void (*query_ppdu)(struct rtw89_dev *rtwdev, 2027 struct rtw89_rx_phy_ppdu *phy_ppdu, 2028 struct ieee80211_rx_status *status); 2029 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 2030 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 2031 s16 pw_ofst, enum rtw89_mac_idx mac_idx); 2032 2033 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 2034 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 2035 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 2036 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 2037 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 2038 void (*btc_bt_aci_imp)(struct rtw89_dev *rtwdev); 2039 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 2040 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 2041 }; 2042 2043 enum rtw89_dma_ch { 2044 RTW89_DMA_ACH0 = 0, 2045 RTW89_DMA_ACH1 = 1, 2046 RTW89_DMA_ACH2 = 2, 2047 RTW89_DMA_ACH3 = 3, 2048 RTW89_DMA_ACH4 = 4, 2049 RTW89_DMA_ACH5 = 5, 2050 RTW89_DMA_ACH6 = 6, 2051 RTW89_DMA_ACH7 = 7, 2052 RTW89_DMA_B0MG = 8, 2053 RTW89_DMA_B0HI = 9, 2054 RTW89_DMA_B1MG = 10, 2055 RTW89_DMA_B1HI = 11, 2056 RTW89_DMA_H2C = 12, 2057 RTW89_DMA_CH_NUM = 13 2058 }; 2059 2060 enum rtw89_qta_mode { 2061 RTW89_QTA_SCC, 2062 RTW89_QTA_DLFW, 2063 2064 /* keep last */ 2065 RTW89_QTA_INVALID, 2066 }; 2067 2068 struct rtw89_hfc_ch_cfg { 2069 u16 min; 2070 u16 max; 2071 #define grp_0 0 2072 #define grp_1 1 2073 #define grp_num 2 2074 u8 grp; 2075 }; 2076 2077 struct rtw89_hfc_ch_info { 2078 u16 aval; 2079 u16 used; 2080 }; 2081 2082 struct rtw89_hfc_pub_cfg { 2083 u16 grp0; 2084 u16 grp1; 2085 u16 pub_max; 2086 u16 wp_thrd; 2087 }; 2088 2089 struct rtw89_hfc_pub_info { 2090 u16 g0_used; 2091 u16 g1_used; 2092 u16 g0_aval; 2093 u16 g1_aval; 2094 u16 pub_aval; 2095 u16 wp_aval; 2096 }; 2097 2098 struct rtw89_hfc_prec_cfg { 2099 u16 ch011_prec; 2100 u16 h2c_prec; 2101 u16 wp_ch07_prec; 2102 u16 wp_ch811_prec; 2103 u8 ch011_full_cond; 2104 u8 h2c_full_cond; 2105 u8 wp_ch07_full_cond; 2106 u8 wp_ch811_full_cond; 2107 }; 2108 2109 struct rtw89_hfc_param { 2110 bool en; 2111 bool h2c_en; 2112 u8 mode; 2113 const struct rtw89_hfc_ch_cfg *ch_cfg; 2114 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 2115 struct rtw89_hfc_pub_cfg pub_cfg; 2116 struct rtw89_hfc_pub_info pub_info; 2117 struct rtw89_hfc_prec_cfg prec_cfg; 2118 }; 2119 2120 struct rtw89_hfc_param_ini { 2121 const struct rtw89_hfc_ch_cfg *ch_cfg; 2122 const struct rtw89_hfc_pub_cfg *pub_cfg; 2123 const struct rtw89_hfc_prec_cfg *prec_cfg; 2124 u8 mode; 2125 }; 2126 2127 struct rtw89_dle_size { 2128 u16 pge_size; 2129 u16 lnk_pge_num; 2130 u16 unlnk_pge_num; 2131 }; 2132 2133 struct rtw89_wde_quota { 2134 u16 hif; 2135 u16 wcpu; 2136 u16 pkt_in; 2137 u16 cpu_io; 2138 }; 2139 2140 struct rtw89_ple_quota { 2141 u16 cma0_tx; 2142 u16 cma1_tx; 2143 u16 c2h; 2144 u16 h2c; 2145 u16 wcpu; 2146 u16 mpdu_proc; 2147 u16 cma0_dma; 2148 u16 cma1_dma; 2149 u16 bb_rpt; 2150 u16 wd_rel; 2151 u16 cpu_io; 2152 }; 2153 2154 struct rtw89_dle_mem { 2155 enum rtw89_qta_mode mode; 2156 const struct rtw89_dle_size *wde_size; 2157 const struct rtw89_dle_size *ple_size; 2158 const struct rtw89_wde_quota *wde_min_qt; 2159 const struct rtw89_wde_quota *wde_max_qt; 2160 const struct rtw89_ple_quota *ple_min_qt; 2161 const struct rtw89_ple_quota *ple_max_qt; 2162 }; 2163 2164 struct rtw89_reg_def { 2165 u32 addr; 2166 u32 mask; 2167 }; 2168 2169 struct rtw89_reg2_def { 2170 u32 addr; 2171 u32 data; 2172 }; 2173 2174 struct rtw89_reg3_def { 2175 u32 addr; 2176 u32 mask; 2177 u32 data; 2178 }; 2179 2180 struct rtw89_reg5_def { 2181 u8 flag; /* recognized by parsers */ 2182 u8 path; 2183 u32 addr; 2184 u32 mask; 2185 u32 data; 2186 }; 2187 2188 struct rtw89_phy_table { 2189 const struct rtw89_reg2_def *regs; 2190 u32 n_regs; 2191 enum rtw89_rf_path rf_path; 2192 }; 2193 2194 struct rtw89_txpwr_table { 2195 const void *data; 2196 u32 size; 2197 void (*load)(struct rtw89_dev *rtwdev, 2198 const struct rtw89_txpwr_table *tbl); 2199 }; 2200 2201 struct rtw89_chip_info { 2202 enum rtw89_core_chip_id chip_id; 2203 const struct rtw89_chip_ops *ops; 2204 const char *fw_name; 2205 u32 fifo_size; 2206 u16 max_amsdu_limit; 2207 bool dis_2g_40m_ul_ofdma; 2208 const struct rtw89_hfc_param_ini *hfc_param_ini; 2209 const struct rtw89_dle_mem *dle_mem; 2210 u32 rf_base_addr[2]; 2211 u8 support_bands; 2212 u8 rf_path_num; 2213 u8 tx_nss; 2214 u8 rx_nss; 2215 u8 acam_num; 2216 u8 bcam_num; 2217 u8 scam_num; 2218 2219 u8 sec_ctrl_efuse_size; 2220 u32 physical_efuse_size; 2221 u32 logical_efuse_size; 2222 u32 limit_efuse_size; 2223 u32 phycap_addr; 2224 u32 phycap_size; 2225 2226 const struct rtw89_pwr_cfg * const *pwr_on_seq; 2227 const struct rtw89_pwr_cfg * const *pwr_off_seq; 2228 const struct rtw89_phy_table *bb_table; 2229 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 2230 const struct rtw89_phy_table *nctl_table; 2231 const struct rtw89_txpwr_table *byr_table; 2232 const struct rtw89_phy_dig_gain_table *dig_table; 2233 const s8 (*txpwr_lmt_2g)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 2234 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2235 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2236 const s8 (*txpwr_lmt_5g)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 2237 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 2238 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2239 const s8 (*txpwr_lmt_ru_2g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2240 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 2241 const s8 (*txpwr_lmt_ru_5g)[RTW89_RU_NUM][RTW89_NTX_NUM] 2242 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 2243 2244 u8 txpwr_factor_rf; 2245 u8 txpwr_factor_mac; 2246 2247 u32 para_ver; 2248 u32 wlcx_desired; 2249 u8 btcx_desired; 2250 u8 scbd; 2251 u8 mailbox; 2252 2253 u8 afh_guard_ch; 2254 const u8 *wl_rssi_thres; 2255 const u8 *bt_rssi_thres; 2256 u8 rssi_tol; 2257 2258 u8 mon_reg_num; 2259 const struct rtw89_btc_fbtc_mreg *mon_reg; 2260 u8 rf_para_ulink_num; 2261 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 2262 u8 rf_para_dlink_num; 2263 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 2264 u8 ps_mode_supported; 2265 }; 2266 2267 struct rtw89_driver_info { 2268 const struct rtw89_chip_info *chip; 2269 }; 2270 2271 enum rtw89_hcifc_mode { 2272 RTW89_HCIFC_POH = 0, 2273 RTW89_HCIFC_STF = 1, 2274 RTW89_HCIFC_SDIO = 2, 2275 2276 /* keep last */ 2277 RTW89_HCIFC_MODE_INVALID, 2278 }; 2279 2280 struct rtw89_dle_info { 2281 enum rtw89_qta_mode qta_mode; 2282 u16 wde_pg_size; 2283 u16 ple_pg_size; 2284 u16 c0_rx_qta; 2285 u16 c1_rx_qta; 2286 }; 2287 2288 enum rtw89_host_rpr_mode { 2289 RTW89_RPR_MODE_POH = 0, 2290 RTW89_RPR_MODE_STF 2291 }; 2292 2293 struct rtw89_mac_info { 2294 struct rtw89_dle_info dle_info; 2295 struct rtw89_hfc_param hfc_param; 2296 enum rtw89_qta_mode qta_mode; 2297 u8 rpwm_seq_num; 2298 u8 cpwm_seq_num; 2299 }; 2300 2301 enum rtw89_fw_type { 2302 RTW89_FW_NORMAL = 1, 2303 RTW89_FW_WOWLAN = 3, 2304 }; 2305 2306 struct rtw89_fw_suit { 2307 const u8 *data; 2308 u32 size; 2309 u8 major_ver; 2310 u8 minor_ver; 2311 u8 sub_ver; 2312 u8 sub_idex; 2313 u16 build_year; 2314 u16 build_mon; 2315 u16 build_date; 2316 u16 build_hour; 2317 u16 build_min; 2318 u8 cmd_ver; 2319 }; 2320 2321 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 2322 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 2323 #define RTW89_FW_SUIT_VER_CODE(s) \ 2324 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 2325 2326 struct rtw89_fw_info { 2327 const struct firmware *firmware; 2328 struct rtw89_dev *rtwdev; 2329 struct completion completion; 2330 u8 h2c_seq; 2331 u8 rec_seq; 2332 struct rtw89_fw_suit normal; 2333 struct rtw89_fw_suit wowlan; 2334 bool fw_log_enable; 2335 bool old_ht_ra_format; 2336 }; 2337 2338 struct rtw89_cam_info { 2339 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 2340 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 2341 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 2342 }; 2343 2344 enum rtw89_sar_sources { 2345 RTW89_SAR_SOURCE_NONE, 2346 RTW89_SAR_SOURCE_COMMON, 2347 2348 RTW89_SAR_SOURCE_NR, 2349 }; 2350 2351 struct rtw89_sar_cfg_common { 2352 bool set[RTW89_SUBBAND_NR]; 2353 s32 cfg[RTW89_SUBBAND_NR]; 2354 }; 2355 2356 struct rtw89_sar_info { 2357 /* used to decide how to acces SAR cfg union */ 2358 enum rtw89_sar_sources src; 2359 2360 /* reserved for different knids of SAR cfg struct. 2361 * supposed that a single cfg struct cannot handle various SAR sources. 2362 */ 2363 union { 2364 struct rtw89_sar_cfg_common cfg_common; 2365 }; 2366 }; 2367 2368 struct rtw89_hal { 2369 u32 rx_fltr; 2370 u8 cv; 2371 u8 current_channel; 2372 u8 prev_primary_channel; 2373 u8 current_primary_channel; 2374 enum rtw89_subband current_subband; 2375 u8 current_band_width; 2376 u8 current_band_type; 2377 u32 sw_amsdu_max_size; 2378 u32 antenna_tx; 2379 u32 antenna_rx; 2380 u8 tx_nss; 2381 u8 rx_nss; 2382 bool support_cckpd; 2383 }; 2384 2385 #define RTW89_MAX_MAC_ID_NUM 128 2386 2387 enum rtw89_flags { 2388 RTW89_FLAG_POWERON, 2389 RTW89_FLAG_FW_RDY, 2390 RTW89_FLAG_RUNNING, 2391 RTW89_FLAG_BFEE_MON, 2392 RTW89_FLAG_BFEE_EN, 2393 RTW89_FLAG_NAPI_RUNNING, 2394 RTW89_FLAG_LEISURE_PS, 2395 RTW89_FLAG_LOW_POWER_MODE, 2396 RTW89_FLAG_INACTIVE_PS, 2397 2398 NUM_OF_RTW89_FLAGS, 2399 }; 2400 2401 struct rtw89_pkt_stat { 2402 u16 beacon_nr; 2403 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 2404 }; 2405 2406 DECLARE_EWMA(thermal, 4, 4); 2407 2408 struct rtw89_phy_stat { 2409 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 2410 struct rtw89_pkt_stat cur_pkt_stat; 2411 struct rtw89_pkt_stat last_pkt_stat; 2412 }; 2413 2414 #define RTW89_DACK_PATH_NR 2 2415 #define RTW89_DACK_IDX_NR 2 2416 #define RTW89_DACK_MSBK_NR 16 2417 struct rtw89_dack_info { 2418 bool dack_done; 2419 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 2420 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2421 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2422 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 2423 u32 dack_cnt; 2424 bool addck_timeout[RTW89_DACK_PATH_NR]; 2425 bool dadck_timeout[RTW89_DACK_PATH_NR]; 2426 bool msbk_timeout[RTW89_DACK_PATH_NR]; 2427 }; 2428 2429 #define RTW89_IQK_CHS_NR 2 2430 #define RTW89_IQK_PATH_NR 4 2431 struct rtw89_iqk_info { 2432 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2433 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2434 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2435 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2436 u32 iqk_fail_cnt; 2437 bool is_iqk_init; 2438 u32 iqk_channel[RTW89_IQK_CHS_NR]; 2439 u8 iqk_band[RTW89_IQK_PATH_NR]; 2440 u8 iqk_ch[RTW89_IQK_PATH_NR]; 2441 u8 iqk_bw[RTW89_IQK_PATH_NR]; 2442 u8 kcount; 2443 u8 iqk_times; 2444 u8 version; 2445 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 2446 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 2447 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 2448 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 2449 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 2450 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 2451 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 2452 bool is_nbiqk; 2453 bool iqk_fft_en; 2454 bool iqk_xym_en; 2455 bool iqk_sram_en; 2456 bool iqk_cfir_en; 2457 u8 thermal[RTW89_IQK_PATH_NR]; 2458 bool thermal_rek_en; 2459 u32 syn1to2; 2460 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 2461 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 2462 }; 2463 2464 #define RTW89_DPK_RF_PATH 2 2465 #define RTW89_DPK_AVG_THERMAL_NUM 8 2466 #define RTW89_DPK_BKUP_NUM 2 2467 struct rtw89_dpk_bkup_para { 2468 enum rtw89_band band; 2469 enum rtw89_bandwidth bw; 2470 u8 ch; 2471 bool path_ok; 2472 u8 txagc_dpk; 2473 u8 ther_dpk; 2474 u8 gs; 2475 u16 pwsf; 2476 }; 2477 2478 struct rtw89_dpk_info { 2479 bool is_dpk_enable; 2480 bool is_dpk_reload_en; 2481 u16 dc_i[RTW89_DPK_RF_PATH]; 2482 u16 dc_q[RTW89_DPK_RF_PATH]; 2483 u8 corr_val[RTW89_DPK_RF_PATH]; 2484 u8 corr_idx[RTW89_DPK_RF_PATH]; 2485 u8 cur_idx[RTW89_DPK_RF_PATH]; 2486 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 2487 }; 2488 2489 struct rtw89_fem_info { 2490 bool elna_2g; 2491 bool elna_5g; 2492 bool epa_2g; 2493 bool epa_5g; 2494 }; 2495 2496 struct rtw89_phy_ch_info { 2497 u8 rssi_min; 2498 u16 rssi_min_macid; 2499 u8 pre_rssi_min; 2500 u8 rssi_max; 2501 u16 rssi_max_macid; 2502 u8 rxsc_160; 2503 u8 rxsc_80; 2504 u8 rxsc_40; 2505 u8 rxsc_20; 2506 u8 rxsc_l; 2507 u8 is_noisy; 2508 }; 2509 2510 struct rtw89_agc_gaincode_set { 2511 u8 lna_idx; 2512 u8 tia_idx; 2513 u8 rxb_idx; 2514 }; 2515 2516 #define IGI_RSSI_TH_NUM 5 2517 #define FA_TH_NUM 4 2518 #define LNA_GAIN_NUM 7 2519 #define TIA_GAIN_NUM 2 2520 struct rtw89_dig_info { 2521 struct rtw89_agc_gaincode_set cur_gaincode; 2522 bool force_gaincode_idx_en; 2523 struct rtw89_agc_gaincode_set force_gaincode; 2524 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 2525 u16 fa_th[FA_TH_NUM]; 2526 u8 igi_rssi; 2527 u8 igi_fa_rssi; 2528 u8 fa_rssi_ofst; 2529 u8 dyn_igi_max; 2530 u8 dyn_igi_min; 2531 bool dyn_pd_th_en; 2532 u8 dyn_pd_th_max; 2533 u8 pd_low_th_ofst; 2534 u8 ib_pbk; 2535 s8 ib_pkpwr; 2536 s8 lna_gain_a[LNA_GAIN_NUM]; 2537 s8 lna_gain_g[LNA_GAIN_NUM]; 2538 s8 *lna_gain; 2539 s8 tia_gain_a[TIA_GAIN_NUM]; 2540 s8 tia_gain_g[TIA_GAIN_NUM]; 2541 s8 *tia_gain; 2542 bool is_linked_pre; 2543 bool bypass_dig; 2544 }; 2545 2546 enum rtw89_multi_cfo_mode { 2547 RTW89_PKT_BASED_AVG_MODE = 0, 2548 RTW89_ENTRY_BASED_AVG_MODE = 1, 2549 RTW89_TP_BASED_AVG_MODE = 2, 2550 }; 2551 2552 enum rtw89_phy_cfo_status { 2553 RTW89_PHY_DCFO_STATE_NORMAL = 0, 2554 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 2555 RTW89_PHY_DCFO_STATE_MAX 2556 }; 2557 2558 struct rtw89_cfo_tracking_info { 2559 u16 cfo_timer_ms; 2560 bool cfo_trig_by_timer_en; 2561 enum rtw89_phy_cfo_status phy_cfo_status; 2562 u8 phy_cfo_trk_cnt; 2563 bool is_adjust; 2564 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 2565 bool apply_compensation; 2566 u8 crystal_cap; 2567 u8 crystal_cap_default; 2568 u8 def_x_cap; 2569 s8 x_cap_ofst; 2570 u32 sta_cfo_tolerance; 2571 s32 cfo_tail[CFO_TRACK_MAX_USER]; 2572 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 2573 s32 cfo_avg_pre; 2574 s32 cfo_avg[CFO_TRACK_MAX_USER]; 2575 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 2576 u32 packet_count; 2577 u32 packet_count_pre; 2578 s32 residual_cfo_acc; 2579 u8 phy_cfotrk_state; 2580 u8 phy_cfotrk_cnt; 2581 }; 2582 2583 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 2584 #define TSSI_TRIM_CH_GROUP_NUM 8 2585 2586 #define TSSI_CCK_CH_GROUP_NUM 6 2587 #define TSSI_MCS_2G_CH_GROUP_NUM 5 2588 #define TSSI_MCS_5G_CH_GROUP_NUM 14 2589 #define TSSI_MCS_CH_GROUP_NUM \ 2590 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 2591 2592 struct rtw89_tssi_info { 2593 u8 thermal[RF_PATH_MAX]; 2594 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 2595 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 2596 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 2597 s8 extra_ofst[RF_PATH_MAX]; 2598 bool tssi_tracking_check[RF_PATH_MAX]; 2599 u8 default_txagc_offset[RF_PATH_MAX]; 2600 u32 base_thermal[RF_PATH_MAX]; 2601 }; 2602 2603 struct rtw89_power_trim_info { 2604 bool pg_thermal_trim; 2605 bool pg_pa_bias_trim; 2606 u8 thermal_trim[RF_PATH_MAX]; 2607 u8 pa_bias_trim[RF_PATH_MAX]; 2608 }; 2609 2610 struct rtw89_regulatory { 2611 char alpha2[3]; 2612 u8 txpwr_regd[RTW89_BAND_MAX]; 2613 }; 2614 2615 enum rtw89_ifs_clm_application { 2616 RTW89_IFS_CLM_INIT = 0, 2617 RTW89_IFS_CLM_BACKGROUND = 1, 2618 RTW89_IFS_CLM_ACS = 2, 2619 RTW89_IFS_CLM_DIG = 3, 2620 RTW89_IFS_CLM_TDMA_DIG = 4, 2621 RTW89_IFS_CLM_DBG = 5, 2622 RTW89_IFS_CLM_DBG_MANUAL = 6 2623 }; 2624 2625 enum rtw89_env_racing_lv { 2626 RTW89_RAC_RELEASE = 0, 2627 RTW89_RAC_LV_1 = 1, 2628 RTW89_RAC_LV_2 = 2, 2629 RTW89_RAC_LV_3 = 3, 2630 RTW89_RAC_LV_4 = 4, 2631 RTW89_RAC_MAX_NUM = 5 2632 }; 2633 2634 struct rtw89_ccx_para_info { 2635 enum rtw89_env_racing_lv rac_lv; 2636 u16 mntr_time; 2637 u8 nhm_manual_th_ofst; 2638 u8 nhm_manual_th0; 2639 enum rtw89_ifs_clm_application ifs_clm_app; 2640 u32 ifs_clm_manual_th_times; 2641 u32 ifs_clm_manual_th0; 2642 u8 fahm_manual_th_ofst; 2643 u8 fahm_manual_th0; 2644 u8 fahm_numer_opt; 2645 u8 fahm_denom_opt; 2646 }; 2647 2648 enum rtw89_ccx_edcca_opt_sc_idx { 2649 RTW89_CCX_EDCCA_SEG0_P0 = 0, 2650 RTW89_CCX_EDCCA_SEG0_S1 = 1, 2651 RTW89_CCX_EDCCA_SEG0_S2 = 2, 2652 RTW89_CCX_EDCCA_SEG0_S3 = 3, 2653 RTW89_CCX_EDCCA_SEG1_P0 = 4, 2654 RTW89_CCX_EDCCA_SEG1_S1 = 5, 2655 RTW89_CCX_EDCCA_SEG1_S2 = 6, 2656 RTW89_CCX_EDCCA_SEG1_S3 = 7 2657 }; 2658 2659 enum rtw89_ccx_edcca_opt_bw_idx { 2660 RTW89_CCX_EDCCA_BW20_0 = 0, 2661 RTW89_CCX_EDCCA_BW20_1 = 1, 2662 RTW89_CCX_EDCCA_BW20_2 = 2, 2663 RTW89_CCX_EDCCA_BW20_3 = 3, 2664 RTW89_CCX_EDCCA_BW20_4 = 4, 2665 RTW89_CCX_EDCCA_BW20_5 = 5, 2666 RTW89_CCX_EDCCA_BW20_6 = 6, 2667 RTW89_CCX_EDCCA_BW20_7 = 7 2668 }; 2669 2670 #define RTW89_NHM_TH_NUM 11 2671 #define RTW89_FAHM_TH_NUM 11 2672 #define RTW89_NHM_RPT_NUM 12 2673 #define RTW89_FAHM_RPT_NUM 12 2674 #define RTW89_IFS_CLM_NUM 4 2675 struct rtw89_env_monitor_info { 2676 u32 ccx_trigger_time; 2677 u64 start_time; 2678 u8 ccx_rpt_stamp; 2679 u8 ccx_watchdog_result; 2680 bool ccx_ongoing; 2681 u8 ccx_rac_lv; 2682 bool ccx_manual_ctrl; 2683 u8 ccx_pre_rssi; 2684 u16 clm_mntr_time; 2685 u16 nhm_mntr_time; 2686 u16 ifs_clm_mntr_time; 2687 enum rtw89_ifs_clm_application ifs_clm_app; 2688 u16 fahm_mntr_time; 2689 u16 edcca_clm_mntr_time; 2690 u16 ccx_period; 2691 u8 ccx_unit_idx; 2692 enum rtw89_ccx_edcca_opt_bw_idx ccx_edcca_opt_bw_idx; 2693 u8 nhm_th[RTW89_NHM_TH_NUM]; 2694 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 2695 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 2696 u8 fahm_numer_opt; 2697 u8 fahm_denom_opt; 2698 u8 fahm_th[RTW89_FAHM_TH_NUM]; 2699 u16 clm_result; 2700 u16 nhm_result[RTW89_NHM_RPT_NUM]; 2701 u8 nhm_wgt[RTW89_NHM_RPT_NUM]; 2702 u16 nhm_tx_cnt; 2703 u16 nhm_cca_cnt; 2704 u16 nhm_idle_cnt; 2705 u16 ifs_clm_tx; 2706 u16 ifs_clm_edcca_excl_cca; 2707 u16 ifs_clm_ofdmfa; 2708 u16 ifs_clm_ofdmcca_excl_fa; 2709 u16 ifs_clm_cckfa; 2710 u16 ifs_clm_cckcca_excl_fa; 2711 u16 ifs_clm_total_ifs; 2712 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 2713 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 2714 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 2715 u16 fahm_result[RTW89_FAHM_RPT_NUM]; 2716 u16 fahm_denom_result; 2717 u16 edcca_clm_result; 2718 u8 clm_ratio; 2719 u8 nhm_rpt[RTW89_NHM_RPT_NUM]; 2720 u8 nhm_tx_ratio; 2721 u8 nhm_cca_ratio; 2722 u8 nhm_idle_ratio; 2723 u8 nhm_ratio; 2724 u16 nhm_result_sum; 2725 u8 nhm_pwr; 2726 u8 ifs_clm_tx_ratio; 2727 u8 ifs_clm_edcca_excl_cca_ratio; 2728 u8 ifs_clm_cck_fa_ratio; 2729 u8 ifs_clm_ofdm_fa_ratio; 2730 u8 ifs_clm_cck_cca_excl_fa_ratio; 2731 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 2732 u16 ifs_clm_cck_fa_permil; 2733 u16 ifs_clm_ofdm_fa_permil; 2734 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 2735 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 2736 u8 fahm_rpt[RTW89_FAHM_RPT_NUM]; 2737 u16 fahm_result_sum; 2738 u8 fahm_ratio; 2739 u8 fahm_denom_ratio; 2740 u8 fahm_pwr; 2741 u8 edcca_clm_ratio; 2742 }; 2743 2744 enum rtw89_ser_rcvy_step { 2745 RTW89_SER_DRV_STOP_TX, 2746 RTW89_SER_DRV_STOP_RX, 2747 RTW89_SER_DRV_STOP_RUN, 2748 RTW89_SER_HAL_STOP_DMA, 2749 RTW89_NUM_OF_SER_FLAGS 2750 }; 2751 2752 struct rtw89_ser { 2753 u8 state; 2754 u8 alarm_event; 2755 2756 struct work_struct ser_hdl_work; 2757 struct delayed_work ser_alarm_work; 2758 struct state_ent *st_tbl; 2759 struct event_ent *ev_tbl; 2760 struct list_head msg_q; 2761 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 2762 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 2763 }; 2764 2765 enum rtw89_mac_ax_ps_mode { 2766 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 2767 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 2768 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 2769 RTW89_MAC_AX_PS_MODE_MAX = 3, 2770 }; 2771 2772 enum rtw89_last_rpwm_mode { 2773 RTW89_LAST_RPWM_PS = 0x0, 2774 RTW89_LAST_RPWM_ACTIVE = 0x6, 2775 }; 2776 2777 struct rtw89_lps_parm { 2778 u8 macid; 2779 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 2780 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 2781 }; 2782 2783 struct rtw89_ppdu_sts_info { 2784 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 2785 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 2786 }; 2787 2788 struct rtw89_early_h2c { 2789 struct list_head list; 2790 u8 *h2c; 2791 u16 h2c_len; 2792 }; 2793 2794 struct rtw89_dev { 2795 struct ieee80211_hw *hw; 2796 struct device *dev; 2797 2798 bool dbcc_en; 2799 const struct rtw89_chip_info *chip; 2800 struct rtw89_hal hal; 2801 struct rtw89_mac_info mac; 2802 struct rtw89_fw_info fw; 2803 struct rtw89_hci_info hci; 2804 struct rtw89_efuse efuse; 2805 struct rtw89_traffic_stats stats; 2806 2807 /* ensures exclusive access from mac80211 callbacks */ 2808 struct mutex mutex; 2809 struct list_head rtwvifs_list; 2810 /* used to protect rf read write */ 2811 struct mutex rf_mutex; 2812 struct workqueue_struct *txq_wq; 2813 struct work_struct txq_work; 2814 struct delayed_work txq_reinvoke_work; 2815 /* used to protect ba_list */ 2816 spinlock_t ba_lock; 2817 /* txqs to setup ba session */ 2818 struct list_head ba_list; 2819 struct work_struct ba_work; 2820 2821 struct rtw89_cam_info cam_info; 2822 2823 struct sk_buff_head c2h_queue; 2824 struct work_struct c2h_work; 2825 2826 struct list_head early_h2c_list; 2827 2828 struct rtw89_ser ser; 2829 2830 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 2831 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 2832 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 2833 2834 struct rtw89_phy_stat phystat; 2835 struct rtw89_dack_info dack; 2836 struct rtw89_iqk_info iqk; 2837 struct rtw89_dpk_info dpk; 2838 bool is_tssi_mode[RF_PATH_MAX]; 2839 bool is_bt_iqk_timeout; 2840 2841 struct rtw89_fem_info fem; 2842 struct rtw89_txpwr_byrate byr[RTW89_BAND_MAX]; 2843 struct rtw89_tssi_info tssi; 2844 struct rtw89_power_trim_info pwr_trim; 2845 2846 struct rtw89_cfo_tracking_info cfo_tracking; 2847 struct rtw89_env_monitor_info env_monitor; 2848 struct rtw89_dig_info dig; 2849 struct rtw89_phy_ch_info ch_info; 2850 struct delayed_work track_work; 2851 struct delayed_work coex_act1_work; 2852 struct delayed_work coex_bt_devinfo_work; 2853 struct delayed_work coex_rfk_chk_work; 2854 struct delayed_work cfo_track_work; 2855 struct rtw89_ppdu_sts_info ppdu_sts; 2856 u8 total_sta_assoc; 2857 bool scanning; 2858 2859 const struct rtw89_regulatory *regd; 2860 struct rtw89_sar_info sar; 2861 2862 struct rtw89_btc btc; 2863 enum rtw89_ps_mode ps_mode; 2864 bool lps_enabled; 2865 2866 /* napi structure */ 2867 struct net_device netdev; 2868 struct napi_struct napi; 2869 int napi_budget_countdown; 2870 2871 /* HCI related data, keep last */ 2872 u8 priv[0] __aligned(sizeof(void *)); 2873 }; 2874 2875 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 2876 struct rtw89_core_tx_request *tx_req) 2877 { 2878 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 2879 } 2880 2881 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 2882 { 2883 rtwdev->hci.ops->reset(rtwdev); 2884 } 2885 2886 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 2887 { 2888 return rtwdev->hci.ops->start(rtwdev); 2889 } 2890 2891 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 2892 { 2893 rtwdev->hci.ops->stop(rtwdev); 2894 } 2895 2896 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 2897 { 2898 return rtwdev->hci.ops->deinit(rtwdev); 2899 } 2900 2901 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 2902 { 2903 rtwdev->hci.ops->recalc_int_mit(rtwdev); 2904 } 2905 2906 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 2907 { 2908 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 2909 } 2910 2911 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 2912 { 2913 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 2914 } 2915 2916 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 2917 bool drop) 2918 { 2919 if (rtwdev->hci.ops->flush_queues) 2920 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 2921 } 2922 2923 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 2924 { 2925 return rtwdev->hci.ops->read8(rtwdev, addr); 2926 } 2927 2928 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 2929 { 2930 return rtwdev->hci.ops->read16(rtwdev, addr); 2931 } 2932 2933 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 2934 { 2935 return rtwdev->hci.ops->read32(rtwdev, addr); 2936 } 2937 2938 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 2939 { 2940 rtwdev->hci.ops->write8(rtwdev, addr, data); 2941 } 2942 2943 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 2944 { 2945 rtwdev->hci.ops->write16(rtwdev, addr, data); 2946 } 2947 2948 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 2949 { 2950 rtwdev->hci.ops->write32(rtwdev, addr, data); 2951 } 2952 2953 static inline void 2954 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 2955 { 2956 u8 val; 2957 2958 val = rtw89_read8(rtwdev, addr); 2959 rtw89_write8(rtwdev, addr, val | bit); 2960 } 2961 2962 static inline void 2963 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 2964 { 2965 u16 val; 2966 2967 val = rtw89_read16(rtwdev, addr); 2968 rtw89_write16(rtwdev, addr, val | bit); 2969 } 2970 2971 static inline void 2972 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 2973 { 2974 u32 val; 2975 2976 val = rtw89_read32(rtwdev, addr); 2977 rtw89_write32(rtwdev, addr, val | bit); 2978 } 2979 2980 static inline void 2981 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 2982 { 2983 u8 val; 2984 2985 val = rtw89_read8(rtwdev, addr); 2986 rtw89_write8(rtwdev, addr, val & ~bit); 2987 } 2988 2989 static inline void 2990 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 2991 { 2992 u16 val; 2993 2994 val = rtw89_read16(rtwdev, addr); 2995 rtw89_write16(rtwdev, addr, val & ~bit); 2996 } 2997 2998 static inline void 2999 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 3000 { 3001 u32 val; 3002 3003 val = rtw89_read32(rtwdev, addr); 3004 rtw89_write32(rtwdev, addr, val & ~bit); 3005 } 3006 3007 static inline u32 3008 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3009 { 3010 u32 shift = __ffs(mask); 3011 u32 orig; 3012 u32 ret; 3013 3014 orig = rtw89_read32(rtwdev, addr); 3015 ret = (orig & mask) >> shift; 3016 3017 return ret; 3018 } 3019 3020 static inline u16 3021 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3022 { 3023 u32 shift = __ffs(mask); 3024 u32 orig; 3025 u32 ret; 3026 3027 orig = rtw89_read16(rtwdev, addr); 3028 ret = (orig & mask) >> shift; 3029 3030 return ret; 3031 } 3032 3033 static inline u8 3034 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 3035 { 3036 u32 shift = __ffs(mask); 3037 u32 orig; 3038 u32 ret; 3039 3040 orig = rtw89_read8(rtwdev, addr); 3041 ret = (orig & mask) >> shift; 3042 3043 return ret; 3044 } 3045 3046 static inline void 3047 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 3048 { 3049 u32 shift = __ffs(mask); 3050 u32 orig; 3051 u32 set; 3052 3053 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 3054 3055 orig = rtw89_read32(rtwdev, addr); 3056 set = (orig & ~mask) | ((data << shift) & mask); 3057 rtw89_write32(rtwdev, addr, set); 3058 } 3059 3060 static inline void 3061 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 3062 { 3063 u32 shift; 3064 u16 orig, set; 3065 3066 mask &= 0xffff; 3067 shift = __ffs(mask); 3068 3069 orig = rtw89_read16(rtwdev, addr); 3070 set = (orig & ~mask) | ((data << shift) & mask); 3071 rtw89_write16(rtwdev, addr, set); 3072 } 3073 3074 static inline void 3075 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 3076 { 3077 u32 shift; 3078 u8 orig, set; 3079 3080 mask &= 0xff; 3081 shift = __ffs(mask); 3082 3083 orig = rtw89_read8(rtwdev, addr); 3084 set = (orig & ~mask) | ((data << shift) & mask); 3085 rtw89_write8(rtwdev, addr, set); 3086 } 3087 3088 static inline u32 3089 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3090 u32 addr, u32 mask) 3091 { 3092 u32 val; 3093 3094 mutex_lock(&rtwdev->rf_mutex); 3095 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 3096 mutex_unlock(&rtwdev->rf_mutex); 3097 3098 return val; 3099 } 3100 3101 static inline void 3102 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3103 u32 addr, u32 mask, u32 data) 3104 { 3105 mutex_lock(&rtwdev->rf_mutex); 3106 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 3107 mutex_unlock(&rtwdev->rf_mutex); 3108 } 3109 3110 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 3111 { 3112 void *p = rtwtxq; 3113 3114 return container_of(p, struct ieee80211_txq, drv_priv); 3115 } 3116 3117 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 3118 struct ieee80211_txq *txq) 3119 { 3120 struct rtw89_txq *rtwtxq; 3121 3122 if (!txq) 3123 return; 3124 3125 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3126 INIT_LIST_HEAD(&rtwtxq->list); 3127 } 3128 3129 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 3130 { 3131 void *p = rtwvif; 3132 3133 return container_of(p, struct ieee80211_vif, drv_priv); 3134 } 3135 3136 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 3137 { 3138 void *p = rtwsta; 3139 3140 return container_of(p, struct ieee80211_sta, drv_priv); 3141 } 3142 3143 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 3144 { 3145 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 3146 } 3147 3148 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 3149 { 3150 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 3151 } 3152 3153 static inline 3154 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 3155 struct rtw89_sta *rtwsta) 3156 { 3157 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE && rtwsta) 3158 return &rtwsta->addr_cam; 3159 return &rtwvif->addr_cam; 3160 } 3161 3162 static inline 3163 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 3164 struct rtw89_channel_help_params *p) 3165 { 3166 rtwdev->chip->ops->set_channel_help(rtwdev, true, p); 3167 } 3168 3169 static inline 3170 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 3171 struct rtw89_channel_help_params *p) 3172 { 3173 rtwdev->chip->ops->set_channel_help(rtwdev, false, p); 3174 } 3175 3176 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 3177 { 3178 const struct rtw89_chip_info *chip = rtwdev->chip; 3179 3180 if (chip->ops->fem_setup) 3181 chip->ops->fem_setup(rtwdev); 3182 } 3183 3184 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 3185 { 3186 const struct rtw89_chip_info *chip = rtwdev->chip; 3187 3188 if (chip->ops->bb_sethw) 3189 chip->ops->bb_sethw(rtwdev); 3190 } 3191 3192 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 3193 { 3194 const struct rtw89_chip_info *chip = rtwdev->chip; 3195 3196 if (chip->ops->rfk_init) 3197 chip->ops->rfk_init(rtwdev); 3198 } 3199 3200 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 3201 { 3202 const struct rtw89_chip_info *chip = rtwdev->chip; 3203 3204 if (chip->ops->rfk_channel) 3205 chip->ops->rfk_channel(rtwdev); 3206 } 3207 3208 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev) 3209 { 3210 const struct rtw89_chip_info *chip = rtwdev->chip; 3211 3212 if (chip->ops->rfk_band_changed) 3213 chip->ops->rfk_band_changed(rtwdev); 3214 } 3215 3216 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 3217 { 3218 const struct rtw89_chip_info *chip = rtwdev->chip; 3219 3220 if (chip->ops->rfk_scan) 3221 chip->ops->rfk_scan(rtwdev, start); 3222 } 3223 3224 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 3225 { 3226 const struct rtw89_chip_info *chip = rtwdev->chip; 3227 3228 if (chip->ops->rfk_track) 3229 chip->ops->rfk_track(rtwdev); 3230 } 3231 3232 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 3233 { 3234 const struct rtw89_chip_info *chip = rtwdev->chip; 3235 3236 if (chip->ops->set_txpwr_ctrl) 3237 chip->ops->set_txpwr_ctrl(rtwdev); 3238 } 3239 3240 static inline void rtw89_chip_set_txpwr(struct rtw89_dev *rtwdev) 3241 { 3242 const struct rtw89_chip_info *chip = rtwdev->chip; 3243 u8 ch = rtwdev->hal.current_channel; 3244 3245 if (!ch) 3246 return; 3247 3248 if (chip->ops->set_txpwr) 3249 chip->ops->set_txpwr(rtwdev); 3250 } 3251 3252 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 3253 { 3254 const struct rtw89_chip_info *chip = rtwdev->chip; 3255 3256 if (chip->ops->power_trim) 3257 chip->ops->power_trim(rtwdev); 3258 } 3259 3260 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 3261 enum rtw89_phy_idx phy_idx) 3262 { 3263 const struct rtw89_chip_info *chip = rtwdev->chip; 3264 3265 if (chip->ops->init_txpwr_unit) 3266 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 3267 } 3268 3269 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 3270 enum rtw89_rf_path rf_path) 3271 { 3272 const struct rtw89_chip_info *chip = rtwdev->chip; 3273 3274 if (!chip->ops->get_thermal) 3275 return 0x10; 3276 3277 return chip->ops->get_thermal(rtwdev, rf_path); 3278 } 3279 3280 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 3281 struct rtw89_rx_phy_ppdu *phy_ppdu, 3282 struct ieee80211_rx_status *status) 3283 { 3284 const struct rtw89_chip_info *chip = rtwdev->chip; 3285 3286 if (chip->ops->query_ppdu) 3287 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 3288 } 3289 3290 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 3291 bool bt_en) 3292 { 3293 const struct rtw89_chip_info *chip = rtwdev->chip; 3294 3295 if (chip->ops->bb_ctrl_btc_preagc) 3296 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 3297 } 3298 3299 static inline 3300 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 3301 struct ieee80211_vif *vif) 3302 { 3303 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3304 const struct rtw89_chip_info *chip = rtwdev->chip; 3305 3306 if (!vif->bss_conf.he_support || !vif->bss_conf.assoc) 3307 return; 3308 3309 if (chip->ops->set_txpwr_ul_tb_offset) 3310 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 3311 } 3312 3313 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 3314 const struct rtw89_txpwr_table *tbl) 3315 { 3316 tbl->load(rtwdev, tbl); 3317 } 3318 3319 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 3320 { 3321 return rtwdev->regd->txpwr_regd[band]; 3322 } 3323 3324 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 3325 { 3326 const struct rtw89_chip_info *chip = rtwdev->chip; 3327 3328 if (chip->ops->ctrl_btg) 3329 chip->ops->ctrl_btg(rtwdev, btg); 3330 } 3331 3332 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 3333 { 3334 __le16 fc = hdr->frame_control; 3335 3336 if (ieee80211_has_tods(fc)) 3337 return hdr->addr1; 3338 else if (ieee80211_has_fromds(fc)) 3339 return hdr->addr2; 3340 else 3341 return hdr->addr3; 3342 } 3343 3344 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 3345 { 3346 if ((sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 3347 (sta->vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 3348 (sta->he_cap.he_cap_elem.phy_cap_info[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 3349 (sta->he_cap.he_cap_elem.phy_cap_info[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 3350 return true; 3351 return false; 3352 } 3353 3354 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 3355 enum rtw89_fw_type type) 3356 { 3357 struct rtw89_fw_info *fw_info = &rtwdev->fw; 3358 3359 if (type == RTW89_FW_WOWLAN) 3360 return &fw_info->wowlan; 3361 return &fw_info->normal; 3362 } 3363 3364 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 3365 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 3366 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 3367 struct sk_buff *skb, bool fwdl); 3368 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 3369 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 3370 struct rtw89_tx_desc_info *desc_info, 3371 void *txdesc); 3372 void rtw89_core_rx(struct rtw89_dev *rtwdev, 3373 struct rtw89_rx_desc_info *desc_info, 3374 struct sk_buff *skb); 3375 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 3376 struct rtw89_rx_desc_info *desc_info, 3377 u8 *data, u32 data_offset); 3378 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 3379 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 3380 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 3381 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 3382 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3383 struct ieee80211_vif *vif, 3384 struct ieee80211_sta *sta); 3385 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3386 struct ieee80211_vif *vif, 3387 struct ieee80211_sta *sta); 3388 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3389 struct ieee80211_vif *vif, 3390 struct ieee80211_sta *sta); 3391 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3392 struct ieee80211_vif *vif, 3393 struct ieee80211_sta *sta); 3394 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3395 struct ieee80211_vif *vif, 3396 struct ieee80211_sta *sta); 3397 int rtw89_core_init(struct rtw89_dev *rtwdev); 3398 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 3399 int rtw89_core_register(struct rtw89_dev *rtwdev); 3400 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 3401 void rtw89_set_channel(struct rtw89_dev *rtwdev); 3402 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 3403 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 3404 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 3405 int rtw89_core_acquire_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 3406 int rtw89_core_release_sta_ba_entry(struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 3407 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 3408 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 3409 u16 rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate); 3410 int rtw89_regd_init(struct rtw89_dev *rtwdev, 3411 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 3412 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 3413 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3414 struct rtw89_traffic_stats *stats); 3415 int rtw89_core_start(struct rtw89_dev *rtwdev); 3416 void rtw89_core_stop(struct rtw89_dev *rtwdev); 3417 void rtw89_core_update_beacon_work(struct work_struct *work); 3418 3419 #endif 3420