1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CORE_H__ 6 #define __RTW89_CORE_H__ 7 8 #include <linux/average.h> 9 #include <linux/bitfield.h> 10 #include <linux/firmware.h> 11 #include <linux/iopoll.h> 12 #include <linux/workqueue.h> 13 #include <net/mac80211.h> 14 15 struct rtw89_dev; 16 struct rtw89_pci_info; 17 struct rtw89_mac_gen_def; 18 struct rtw89_phy_gen_def; 19 20 extern const struct ieee80211_ops rtw89_ops; 21 22 #define MASKBYTE0 0xff 23 #define MASKBYTE1 0xff00 24 #define MASKBYTE2 0xff0000 25 #define MASKBYTE3 0xff000000 26 #define MASKBYTE4 0xff00000000ULL 27 #define MASKHWORD 0xffff0000 28 #define MASKLWORD 0x0000ffff 29 #define MASKDWORD 0xffffffff 30 #define RFREG_MASK 0xfffff 31 #define INV_RF_DATA 0xffffffff 32 33 #define RTW89_TRACK_WORK_PERIOD round_jiffies_relative(HZ * 2) 34 #define RTW89_FORBID_BA_TIMER round_jiffies_relative(HZ * 4) 35 #define CFO_TRACK_MAX_USER 64 36 #define MAX_RSSI 110 37 #define RSSI_FACTOR 1 38 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI) 39 #define RTW89_TX_DIV_RSSI_RAW_TH (2 << RSSI_FACTOR) 40 #define RTW89_RADIOTAP_ROOM ALIGN(sizeof(struct ieee80211_radiotap_he), 64) 41 42 #define RTW89_HTC_MASK_VARIANT GENMASK(1, 0) 43 #define RTW89_HTC_VARIANT_HE 3 44 #define RTW89_HTC_MASK_CTL_ID GENMASK(5, 2) 45 #define RTW89_HTC_VARIANT_HE_CID_OM 1 46 #define RTW89_HTC_VARIANT_HE_CID_CAS 6 47 #define RTW89_HTC_MASK_CTL_INFO GENMASK(31, 6) 48 49 #define RTW89_HTC_MASK_HTC_OM_RX_NSS GENMASK(8, 6) 50 enum htc_om_channel_width { 51 HTC_OM_CHANNEL_WIDTH_20 = 0, 52 HTC_OM_CHANNEL_WIDTH_40 = 1, 53 HTC_OM_CHANNEL_WIDTH_80 = 2, 54 HTC_OM_CHANNEL_WIDTH_160_OR_80_80 = 3, 55 }; 56 #define RTW89_HTC_MASK_HTC_OM_CH_WIDTH GENMASK(10, 9) 57 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DIS BIT(11) 58 #define RTW89_HTC_MASK_HTC_OM_TX_NSTS GENMASK(14, 12) 59 #define RTW89_HTC_MASK_HTC_OM_ER_SU_DIS BIT(15) 60 #define RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR BIT(16) 61 #define RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS BIT(17) 62 63 #define RTW89_TF_PAD GENMASK(11, 0) 64 #define RTW89_TF_BASIC_USER_INFO_SZ 6 65 66 #define RTW89_GET_TF_USER_INFO_AID12(data) \ 67 le32_get_bits(*((const __le32 *)(data)), GENMASK(11, 0)) 68 #define RTW89_GET_TF_USER_INFO_RUA(data) \ 69 le32_get_bits(*((const __le32 *)(data)), GENMASK(19, 12)) 70 #define RTW89_GET_TF_USER_INFO_UL_MCS(data) \ 71 le32_get_bits(*((const __le32 *)(data)), GENMASK(24, 21)) 72 73 enum rtw89_subband { 74 RTW89_CH_2G = 0, 75 RTW89_CH_5G_BAND_1 = 1, 76 /* RTW89_CH_5G_BAND_2 = 2, unused */ 77 RTW89_CH_5G_BAND_3 = 3, 78 RTW89_CH_5G_BAND_4 = 4, 79 80 RTW89_CH_6G_BAND_IDX0, /* Low */ 81 RTW89_CH_6G_BAND_IDX1, /* Low */ 82 RTW89_CH_6G_BAND_IDX2, /* Mid */ 83 RTW89_CH_6G_BAND_IDX3, /* Mid */ 84 RTW89_CH_6G_BAND_IDX4, /* High */ 85 RTW89_CH_6G_BAND_IDX5, /* High */ 86 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */ 87 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */ 88 89 RTW89_SUBBAND_NR, 90 RTW89_SUBBAND_2GHZ_5GHZ_NR = RTW89_CH_5G_BAND_4 + 1, 91 }; 92 93 enum rtw89_gain_offset { 94 RTW89_GAIN_OFFSET_2G_CCK, 95 RTW89_GAIN_OFFSET_2G_OFDM, 96 RTW89_GAIN_OFFSET_5G_LOW, 97 RTW89_GAIN_OFFSET_5G_MID, 98 RTW89_GAIN_OFFSET_5G_HIGH, 99 100 RTW89_GAIN_OFFSET_NR, 101 }; 102 103 enum rtw89_hci_type { 104 RTW89_HCI_TYPE_PCIE, 105 RTW89_HCI_TYPE_USB, 106 RTW89_HCI_TYPE_SDIO, 107 }; 108 109 enum rtw89_core_chip_id { 110 RTL8852A, 111 RTL8852B, 112 RTL8852C, 113 RTL8851B, 114 RTL8922A, 115 }; 116 117 enum rtw89_chip_gen { 118 RTW89_CHIP_AX, 119 RTW89_CHIP_BE, 120 121 RTW89_CHIP_GEN_NUM, 122 }; 123 124 enum rtw89_cv { 125 CHIP_CAV, 126 CHIP_CBV, 127 CHIP_CCV, 128 CHIP_CDV, 129 CHIP_CEV, 130 CHIP_CFV, 131 CHIP_CV_MAX, 132 CHIP_CV_INVALID = CHIP_CV_MAX, 133 }; 134 135 enum rtw89_bacam_ver { 136 RTW89_BACAM_V0, 137 RTW89_BACAM_V1, 138 139 RTW89_BACAM_V0_EXT = 99, 140 }; 141 142 enum rtw89_core_tx_type { 143 RTW89_CORE_TX_TYPE_DATA, 144 RTW89_CORE_TX_TYPE_MGMT, 145 RTW89_CORE_TX_TYPE_FWCMD, 146 }; 147 148 enum rtw89_core_rx_type { 149 RTW89_CORE_RX_TYPE_WIFI = 0, 150 RTW89_CORE_RX_TYPE_PPDU_STAT = 1, 151 RTW89_CORE_RX_TYPE_CHAN_INFO = 2, 152 RTW89_CORE_RX_TYPE_BB_SCOPE = 3, 153 RTW89_CORE_RX_TYPE_F2P_TXCMD = 4, 154 RTW89_CORE_RX_TYPE_SS2FW = 5, 155 RTW89_CORE_RX_TYPE_TX_REPORT = 6, 156 RTW89_CORE_RX_TYPE_TX_REL_HOST = 7, 157 RTW89_CORE_RX_TYPE_DFS_REPORT = 8, 158 RTW89_CORE_RX_TYPE_TX_REL_CPU = 9, 159 RTW89_CORE_RX_TYPE_C2H = 10, 160 RTW89_CORE_RX_TYPE_CSI = 11, 161 RTW89_CORE_RX_TYPE_CQI = 12, 162 RTW89_CORE_RX_TYPE_H2C = 13, 163 RTW89_CORE_RX_TYPE_FWDL = 14, 164 }; 165 166 enum rtw89_txq_flags { 167 RTW89_TXQ_F_AMPDU = 0, 168 RTW89_TXQ_F_BLOCK_BA = 1, 169 RTW89_TXQ_F_FORBID_BA = 2, 170 }; 171 172 enum rtw89_net_type { 173 RTW89_NET_TYPE_NO_LINK = 0, 174 RTW89_NET_TYPE_AD_HOC = 1, 175 RTW89_NET_TYPE_INFRA = 2, 176 RTW89_NET_TYPE_AP_MODE = 3, 177 }; 178 179 enum rtw89_wifi_role { 180 RTW89_WIFI_ROLE_NONE, 181 RTW89_WIFI_ROLE_STATION, 182 RTW89_WIFI_ROLE_AP, 183 RTW89_WIFI_ROLE_AP_VLAN, 184 RTW89_WIFI_ROLE_ADHOC, 185 RTW89_WIFI_ROLE_ADHOC_MASTER, 186 RTW89_WIFI_ROLE_MESH_POINT, 187 RTW89_WIFI_ROLE_MONITOR, 188 RTW89_WIFI_ROLE_P2P_DEVICE, 189 RTW89_WIFI_ROLE_P2P_CLIENT, 190 RTW89_WIFI_ROLE_P2P_GO, 191 RTW89_WIFI_ROLE_NAN, 192 RTW89_WIFI_ROLE_MLME_MAX 193 }; 194 195 enum rtw89_upd_mode { 196 RTW89_ROLE_CREATE, 197 RTW89_ROLE_REMOVE, 198 RTW89_ROLE_TYPE_CHANGE, 199 RTW89_ROLE_INFO_CHANGE, 200 RTW89_ROLE_CON_DISCONN, 201 RTW89_ROLE_BAND_SW, 202 RTW89_ROLE_FW_RESTORE, 203 }; 204 205 enum rtw89_self_role { 206 RTW89_SELF_ROLE_CLIENT, 207 RTW89_SELF_ROLE_AP, 208 RTW89_SELF_ROLE_AP_CLIENT 209 }; 210 211 enum rtw89_msk_sO_el { 212 RTW89_NO_MSK, 213 RTW89_SMA, 214 RTW89_TMA, 215 RTW89_BSSID 216 }; 217 218 enum rtw89_sch_tx_sel { 219 RTW89_SCH_TX_SEL_ALL, 220 RTW89_SCH_TX_SEL_HIQ, 221 RTW89_SCH_TX_SEL_MG0, 222 RTW89_SCH_TX_SEL_MACID, 223 }; 224 225 /* RTW89_ADDR_CAM_SEC_NONE : not enabled 226 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast 227 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP 228 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP 229 */ 230 enum rtw89_add_cam_sec_mode { 231 RTW89_ADDR_CAM_SEC_NONE = 0, 232 RTW89_ADDR_CAM_SEC_ALL_UNI = 1, 233 RTW89_ADDR_CAM_SEC_NORMAL = 2, 234 RTW89_ADDR_CAM_SEC_4GROUP = 3, 235 }; 236 237 enum rtw89_sec_key_type { 238 RTW89_SEC_KEY_TYPE_NONE = 0, 239 RTW89_SEC_KEY_TYPE_WEP40 = 1, 240 RTW89_SEC_KEY_TYPE_WEP104 = 2, 241 RTW89_SEC_KEY_TYPE_TKIP = 3, 242 RTW89_SEC_KEY_TYPE_WAPI = 4, 243 RTW89_SEC_KEY_TYPE_GCMSMS4 = 5, 244 RTW89_SEC_KEY_TYPE_CCMP128 = 6, 245 RTW89_SEC_KEY_TYPE_CCMP256 = 7, 246 RTW89_SEC_KEY_TYPE_GCMP128 = 8, 247 RTW89_SEC_KEY_TYPE_GCMP256 = 9, 248 RTW89_SEC_KEY_TYPE_BIP_CCMP128 = 10, 249 }; 250 251 enum rtw89_port { 252 RTW89_PORT_0 = 0, 253 RTW89_PORT_1 = 1, 254 RTW89_PORT_2 = 2, 255 RTW89_PORT_3 = 3, 256 RTW89_PORT_4 = 4, 257 RTW89_PORT_NUM 258 }; 259 260 enum rtw89_band { 261 RTW89_BAND_2G = 0, 262 RTW89_BAND_5G = 1, 263 RTW89_BAND_6G = 2, 264 RTW89_BAND_NUM, 265 }; 266 267 enum rtw89_hw_rate { 268 RTW89_HW_RATE_CCK1 = 0x0, 269 RTW89_HW_RATE_CCK2 = 0x1, 270 RTW89_HW_RATE_CCK5_5 = 0x2, 271 RTW89_HW_RATE_CCK11 = 0x3, 272 RTW89_HW_RATE_OFDM6 = 0x4, 273 RTW89_HW_RATE_OFDM9 = 0x5, 274 RTW89_HW_RATE_OFDM12 = 0x6, 275 RTW89_HW_RATE_OFDM18 = 0x7, 276 RTW89_HW_RATE_OFDM24 = 0x8, 277 RTW89_HW_RATE_OFDM36 = 0x9, 278 RTW89_HW_RATE_OFDM48 = 0xA, 279 RTW89_HW_RATE_OFDM54 = 0xB, 280 RTW89_HW_RATE_MCS0 = 0x80, 281 RTW89_HW_RATE_MCS1 = 0x81, 282 RTW89_HW_RATE_MCS2 = 0x82, 283 RTW89_HW_RATE_MCS3 = 0x83, 284 RTW89_HW_RATE_MCS4 = 0x84, 285 RTW89_HW_RATE_MCS5 = 0x85, 286 RTW89_HW_RATE_MCS6 = 0x86, 287 RTW89_HW_RATE_MCS7 = 0x87, 288 RTW89_HW_RATE_MCS8 = 0x88, 289 RTW89_HW_RATE_MCS9 = 0x89, 290 RTW89_HW_RATE_MCS10 = 0x8A, 291 RTW89_HW_RATE_MCS11 = 0x8B, 292 RTW89_HW_RATE_MCS12 = 0x8C, 293 RTW89_HW_RATE_MCS13 = 0x8D, 294 RTW89_HW_RATE_MCS14 = 0x8E, 295 RTW89_HW_RATE_MCS15 = 0x8F, 296 RTW89_HW_RATE_MCS16 = 0x90, 297 RTW89_HW_RATE_MCS17 = 0x91, 298 RTW89_HW_RATE_MCS18 = 0x92, 299 RTW89_HW_RATE_MCS19 = 0x93, 300 RTW89_HW_RATE_MCS20 = 0x94, 301 RTW89_HW_RATE_MCS21 = 0x95, 302 RTW89_HW_RATE_MCS22 = 0x96, 303 RTW89_HW_RATE_MCS23 = 0x97, 304 RTW89_HW_RATE_MCS24 = 0x98, 305 RTW89_HW_RATE_MCS25 = 0x99, 306 RTW89_HW_RATE_MCS26 = 0x9A, 307 RTW89_HW_RATE_MCS27 = 0x9B, 308 RTW89_HW_RATE_MCS28 = 0x9C, 309 RTW89_HW_RATE_MCS29 = 0x9D, 310 RTW89_HW_RATE_MCS30 = 0x9E, 311 RTW89_HW_RATE_MCS31 = 0x9F, 312 RTW89_HW_RATE_VHT_NSS1_MCS0 = 0x100, 313 RTW89_HW_RATE_VHT_NSS1_MCS1 = 0x101, 314 RTW89_HW_RATE_VHT_NSS1_MCS2 = 0x102, 315 RTW89_HW_RATE_VHT_NSS1_MCS3 = 0x103, 316 RTW89_HW_RATE_VHT_NSS1_MCS4 = 0x104, 317 RTW89_HW_RATE_VHT_NSS1_MCS5 = 0x105, 318 RTW89_HW_RATE_VHT_NSS1_MCS6 = 0x106, 319 RTW89_HW_RATE_VHT_NSS1_MCS7 = 0x107, 320 RTW89_HW_RATE_VHT_NSS1_MCS8 = 0x108, 321 RTW89_HW_RATE_VHT_NSS1_MCS9 = 0x109, 322 RTW89_HW_RATE_VHT_NSS2_MCS0 = 0x110, 323 RTW89_HW_RATE_VHT_NSS2_MCS1 = 0x111, 324 RTW89_HW_RATE_VHT_NSS2_MCS2 = 0x112, 325 RTW89_HW_RATE_VHT_NSS2_MCS3 = 0x113, 326 RTW89_HW_RATE_VHT_NSS2_MCS4 = 0x114, 327 RTW89_HW_RATE_VHT_NSS2_MCS5 = 0x115, 328 RTW89_HW_RATE_VHT_NSS2_MCS6 = 0x116, 329 RTW89_HW_RATE_VHT_NSS2_MCS7 = 0x117, 330 RTW89_HW_RATE_VHT_NSS2_MCS8 = 0x118, 331 RTW89_HW_RATE_VHT_NSS2_MCS9 = 0x119, 332 RTW89_HW_RATE_VHT_NSS3_MCS0 = 0x120, 333 RTW89_HW_RATE_VHT_NSS3_MCS1 = 0x121, 334 RTW89_HW_RATE_VHT_NSS3_MCS2 = 0x122, 335 RTW89_HW_RATE_VHT_NSS3_MCS3 = 0x123, 336 RTW89_HW_RATE_VHT_NSS3_MCS4 = 0x124, 337 RTW89_HW_RATE_VHT_NSS3_MCS5 = 0x125, 338 RTW89_HW_RATE_VHT_NSS3_MCS6 = 0x126, 339 RTW89_HW_RATE_VHT_NSS3_MCS7 = 0x127, 340 RTW89_HW_RATE_VHT_NSS3_MCS8 = 0x128, 341 RTW89_HW_RATE_VHT_NSS3_MCS9 = 0x129, 342 RTW89_HW_RATE_VHT_NSS4_MCS0 = 0x130, 343 RTW89_HW_RATE_VHT_NSS4_MCS1 = 0x131, 344 RTW89_HW_RATE_VHT_NSS4_MCS2 = 0x132, 345 RTW89_HW_RATE_VHT_NSS4_MCS3 = 0x133, 346 RTW89_HW_RATE_VHT_NSS4_MCS4 = 0x134, 347 RTW89_HW_RATE_VHT_NSS4_MCS5 = 0x135, 348 RTW89_HW_RATE_VHT_NSS4_MCS6 = 0x136, 349 RTW89_HW_RATE_VHT_NSS4_MCS7 = 0x137, 350 RTW89_HW_RATE_VHT_NSS4_MCS8 = 0x138, 351 RTW89_HW_RATE_VHT_NSS4_MCS9 = 0x139, 352 RTW89_HW_RATE_HE_NSS1_MCS0 = 0x180, 353 RTW89_HW_RATE_HE_NSS1_MCS1 = 0x181, 354 RTW89_HW_RATE_HE_NSS1_MCS2 = 0x182, 355 RTW89_HW_RATE_HE_NSS1_MCS3 = 0x183, 356 RTW89_HW_RATE_HE_NSS1_MCS4 = 0x184, 357 RTW89_HW_RATE_HE_NSS1_MCS5 = 0x185, 358 RTW89_HW_RATE_HE_NSS1_MCS6 = 0x186, 359 RTW89_HW_RATE_HE_NSS1_MCS7 = 0x187, 360 RTW89_HW_RATE_HE_NSS1_MCS8 = 0x188, 361 RTW89_HW_RATE_HE_NSS1_MCS9 = 0x189, 362 RTW89_HW_RATE_HE_NSS1_MCS10 = 0x18A, 363 RTW89_HW_RATE_HE_NSS1_MCS11 = 0x18B, 364 RTW89_HW_RATE_HE_NSS2_MCS0 = 0x190, 365 RTW89_HW_RATE_HE_NSS2_MCS1 = 0x191, 366 RTW89_HW_RATE_HE_NSS2_MCS2 = 0x192, 367 RTW89_HW_RATE_HE_NSS2_MCS3 = 0x193, 368 RTW89_HW_RATE_HE_NSS2_MCS4 = 0x194, 369 RTW89_HW_RATE_HE_NSS2_MCS5 = 0x195, 370 RTW89_HW_RATE_HE_NSS2_MCS6 = 0x196, 371 RTW89_HW_RATE_HE_NSS2_MCS7 = 0x197, 372 RTW89_HW_RATE_HE_NSS2_MCS8 = 0x198, 373 RTW89_HW_RATE_HE_NSS2_MCS9 = 0x199, 374 RTW89_HW_RATE_HE_NSS2_MCS10 = 0x19A, 375 RTW89_HW_RATE_HE_NSS2_MCS11 = 0x19B, 376 RTW89_HW_RATE_HE_NSS3_MCS0 = 0x1A0, 377 RTW89_HW_RATE_HE_NSS3_MCS1 = 0x1A1, 378 RTW89_HW_RATE_HE_NSS3_MCS2 = 0x1A2, 379 RTW89_HW_RATE_HE_NSS3_MCS3 = 0x1A3, 380 RTW89_HW_RATE_HE_NSS3_MCS4 = 0x1A4, 381 RTW89_HW_RATE_HE_NSS3_MCS5 = 0x1A5, 382 RTW89_HW_RATE_HE_NSS3_MCS6 = 0x1A6, 383 RTW89_HW_RATE_HE_NSS3_MCS7 = 0x1A7, 384 RTW89_HW_RATE_HE_NSS3_MCS8 = 0x1A8, 385 RTW89_HW_RATE_HE_NSS3_MCS9 = 0x1A9, 386 RTW89_HW_RATE_HE_NSS3_MCS10 = 0x1AA, 387 RTW89_HW_RATE_HE_NSS3_MCS11 = 0x1AB, 388 RTW89_HW_RATE_HE_NSS4_MCS0 = 0x1B0, 389 RTW89_HW_RATE_HE_NSS4_MCS1 = 0x1B1, 390 RTW89_HW_RATE_HE_NSS4_MCS2 = 0x1B2, 391 RTW89_HW_RATE_HE_NSS4_MCS3 = 0x1B3, 392 RTW89_HW_RATE_HE_NSS4_MCS4 = 0x1B4, 393 RTW89_HW_RATE_HE_NSS4_MCS5 = 0x1B5, 394 RTW89_HW_RATE_HE_NSS4_MCS6 = 0x1B6, 395 RTW89_HW_RATE_HE_NSS4_MCS7 = 0x1B7, 396 RTW89_HW_RATE_HE_NSS4_MCS8 = 0x1B8, 397 RTW89_HW_RATE_HE_NSS4_MCS9 = 0x1B9, 398 RTW89_HW_RATE_HE_NSS4_MCS10 = 0x1BA, 399 RTW89_HW_RATE_HE_NSS4_MCS11 = 0x1BB, 400 401 RTW89_HW_RATE_V1_MCS0 = 0x100, 402 RTW89_HW_RATE_V1_MCS1 = 0x101, 403 RTW89_HW_RATE_V1_MCS2 = 0x102, 404 RTW89_HW_RATE_V1_MCS3 = 0x103, 405 RTW89_HW_RATE_V1_MCS4 = 0x104, 406 RTW89_HW_RATE_V1_MCS5 = 0x105, 407 RTW89_HW_RATE_V1_MCS6 = 0x106, 408 RTW89_HW_RATE_V1_MCS7 = 0x107, 409 RTW89_HW_RATE_V1_MCS8 = 0x108, 410 RTW89_HW_RATE_V1_MCS9 = 0x109, 411 RTW89_HW_RATE_V1_MCS10 = 0x10A, 412 RTW89_HW_RATE_V1_MCS11 = 0x10B, 413 RTW89_HW_RATE_V1_MCS12 = 0x10C, 414 RTW89_HW_RATE_V1_MCS13 = 0x10D, 415 RTW89_HW_RATE_V1_MCS14 = 0x10E, 416 RTW89_HW_RATE_V1_MCS15 = 0x10F, 417 RTW89_HW_RATE_V1_MCS16 = 0x110, 418 RTW89_HW_RATE_V1_MCS17 = 0x111, 419 RTW89_HW_RATE_V1_MCS18 = 0x112, 420 RTW89_HW_RATE_V1_MCS19 = 0x113, 421 RTW89_HW_RATE_V1_MCS20 = 0x114, 422 RTW89_HW_RATE_V1_MCS21 = 0x115, 423 RTW89_HW_RATE_V1_MCS22 = 0x116, 424 RTW89_HW_RATE_V1_MCS23 = 0x117, 425 RTW89_HW_RATE_V1_MCS24 = 0x118, 426 RTW89_HW_RATE_V1_MCS25 = 0x119, 427 RTW89_HW_RATE_V1_MCS26 = 0x11A, 428 RTW89_HW_RATE_V1_MCS27 = 0x11B, 429 RTW89_HW_RATE_V1_MCS28 = 0x11C, 430 RTW89_HW_RATE_V1_MCS29 = 0x11D, 431 RTW89_HW_RATE_V1_MCS30 = 0x11E, 432 RTW89_HW_RATE_V1_MCS31 = 0x11F, 433 RTW89_HW_RATE_V1_VHT_NSS1_MCS0 = 0x200, 434 RTW89_HW_RATE_V1_VHT_NSS1_MCS1 = 0x201, 435 RTW89_HW_RATE_V1_VHT_NSS1_MCS2 = 0x202, 436 RTW89_HW_RATE_V1_VHT_NSS1_MCS3 = 0x203, 437 RTW89_HW_RATE_V1_VHT_NSS1_MCS4 = 0x204, 438 RTW89_HW_RATE_V1_VHT_NSS1_MCS5 = 0x205, 439 RTW89_HW_RATE_V1_VHT_NSS1_MCS6 = 0x206, 440 RTW89_HW_RATE_V1_VHT_NSS1_MCS7 = 0x207, 441 RTW89_HW_RATE_V1_VHT_NSS1_MCS8 = 0x208, 442 RTW89_HW_RATE_V1_VHT_NSS1_MCS9 = 0x209, 443 RTW89_HW_RATE_V1_VHT_NSS1_MCS10 = 0x20A, 444 RTW89_HW_RATE_V1_VHT_NSS1_MCS11 = 0x20B, 445 RTW89_HW_RATE_V1_VHT_NSS2_MCS0 = 0x220, 446 RTW89_HW_RATE_V1_VHT_NSS2_MCS1 = 0x221, 447 RTW89_HW_RATE_V1_VHT_NSS2_MCS2 = 0x222, 448 RTW89_HW_RATE_V1_VHT_NSS2_MCS3 = 0x223, 449 RTW89_HW_RATE_V1_VHT_NSS2_MCS4 = 0x224, 450 RTW89_HW_RATE_V1_VHT_NSS2_MCS5 = 0x225, 451 RTW89_HW_RATE_V1_VHT_NSS2_MCS6 = 0x226, 452 RTW89_HW_RATE_V1_VHT_NSS2_MCS7 = 0x227, 453 RTW89_HW_RATE_V1_VHT_NSS2_MCS8 = 0x228, 454 RTW89_HW_RATE_V1_VHT_NSS2_MCS9 = 0x229, 455 RTW89_HW_RATE_V1_VHT_NSS2_MCS10 = 0x22A, 456 RTW89_HW_RATE_V1_VHT_NSS2_MCS11 = 0x22B, 457 RTW89_HW_RATE_V1_VHT_NSS3_MCS0 = 0x240, 458 RTW89_HW_RATE_V1_VHT_NSS3_MCS1 = 0x241, 459 RTW89_HW_RATE_V1_VHT_NSS3_MCS2 = 0x242, 460 RTW89_HW_RATE_V1_VHT_NSS3_MCS3 = 0x243, 461 RTW89_HW_RATE_V1_VHT_NSS3_MCS4 = 0x244, 462 RTW89_HW_RATE_V1_VHT_NSS3_MCS5 = 0x245, 463 RTW89_HW_RATE_V1_VHT_NSS3_MCS6 = 0x246, 464 RTW89_HW_RATE_V1_VHT_NSS3_MCS7 = 0x247, 465 RTW89_HW_RATE_V1_VHT_NSS3_MCS8 = 0x248, 466 RTW89_HW_RATE_V1_VHT_NSS3_MCS9 = 0x249, 467 RTW89_HW_RATE_V1_VHT_NSS3_MCS10 = 0x24A, 468 RTW89_HW_RATE_V1_VHT_NSS3_MCS11 = 0x24B, 469 RTW89_HW_RATE_V1_VHT_NSS4_MCS0 = 0x260, 470 RTW89_HW_RATE_V1_VHT_NSS4_MCS1 = 0x261, 471 RTW89_HW_RATE_V1_VHT_NSS4_MCS2 = 0x262, 472 RTW89_HW_RATE_V1_VHT_NSS4_MCS3 = 0x263, 473 RTW89_HW_RATE_V1_VHT_NSS4_MCS4 = 0x264, 474 RTW89_HW_RATE_V1_VHT_NSS4_MCS5 = 0x265, 475 RTW89_HW_RATE_V1_VHT_NSS4_MCS6 = 0x266, 476 RTW89_HW_RATE_V1_VHT_NSS4_MCS7 = 0x267, 477 RTW89_HW_RATE_V1_VHT_NSS4_MCS8 = 0x268, 478 RTW89_HW_RATE_V1_VHT_NSS4_MCS9 = 0x269, 479 RTW89_HW_RATE_V1_VHT_NSS4_MCS10 = 0x26A, 480 RTW89_HW_RATE_V1_VHT_NSS4_MCS11 = 0x26B, 481 RTW89_HW_RATE_V1_HE_NSS1_MCS0 = 0x300, 482 RTW89_HW_RATE_V1_HE_NSS1_MCS1 = 0x301, 483 RTW89_HW_RATE_V1_HE_NSS1_MCS2 = 0x302, 484 RTW89_HW_RATE_V1_HE_NSS1_MCS3 = 0x303, 485 RTW89_HW_RATE_V1_HE_NSS1_MCS4 = 0x304, 486 RTW89_HW_RATE_V1_HE_NSS1_MCS5 = 0x305, 487 RTW89_HW_RATE_V1_HE_NSS1_MCS6 = 0x306, 488 RTW89_HW_RATE_V1_HE_NSS1_MCS7 = 0x307, 489 RTW89_HW_RATE_V1_HE_NSS1_MCS8 = 0x308, 490 RTW89_HW_RATE_V1_HE_NSS1_MCS9 = 0x309, 491 RTW89_HW_RATE_V1_HE_NSS1_MCS10 = 0x30A, 492 RTW89_HW_RATE_V1_HE_NSS1_MCS11 = 0x30B, 493 RTW89_HW_RATE_V1_HE_NSS2_MCS0 = 0x320, 494 RTW89_HW_RATE_V1_HE_NSS2_MCS1 = 0x321, 495 RTW89_HW_RATE_V1_HE_NSS2_MCS2 = 0x322, 496 RTW89_HW_RATE_V1_HE_NSS2_MCS3 = 0x323, 497 RTW89_HW_RATE_V1_HE_NSS2_MCS4 = 0x324, 498 RTW89_HW_RATE_V1_HE_NSS2_MCS5 = 0x325, 499 RTW89_HW_RATE_V1_HE_NSS2_MCS6 = 0x326, 500 RTW89_HW_RATE_V1_HE_NSS2_MCS7 = 0x327, 501 RTW89_HW_RATE_V1_HE_NSS2_MCS8 = 0x328, 502 RTW89_HW_RATE_V1_HE_NSS2_MCS9 = 0x329, 503 RTW89_HW_RATE_V1_HE_NSS2_MCS10 = 0x32A, 504 RTW89_HW_RATE_V1_HE_NSS2_MCS11 = 0x32B, 505 RTW89_HW_RATE_V1_HE_NSS3_MCS0 = 0x340, 506 RTW89_HW_RATE_V1_HE_NSS3_MCS1 = 0x341, 507 RTW89_HW_RATE_V1_HE_NSS3_MCS2 = 0x342, 508 RTW89_HW_RATE_V1_HE_NSS3_MCS3 = 0x343, 509 RTW89_HW_RATE_V1_HE_NSS3_MCS4 = 0x344, 510 RTW89_HW_RATE_V1_HE_NSS3_MCS5 = 0x345, 511 RTW89_HW_RATE_V1_HE_NSS3_MCS6 = 0x346, 512 RTW89_HW_RATE_V1_HE_NSS3_MCS7 = 0x347, 513 RTW89_HW_RATE_V1_HE_NSS3_MCS8 = 0x348, 514 RTW89_HW_RATE_V1_HE_NSS3_MCS9 = 0x349, 515 RTW89_HW_RATE_V1_HE_NSS3_MCS10 = 0x34A, 516 RTW89_HW_RATE_V1_HE_NSS3_MCS11 = 0x34B, 517 RTW89_HW_RATE_V1_HE_NSS4_MCS0 = 0x360, 518 RTW89_HW_RATE_V1_HE_NSS4_MCS1 = 0x361, 519 RTW89_HW_RATE_V1_HE_NSS4_MCS2 = 0x362, 520 RTW89_HW_RATE_V1_HE_NSS4_MCS3 = 0x363, 521 RTW89_HW_RATE_V1_HE_NSS4_MCS4 = 0x364, 522 RTW89_HW_RATE_V1_HE_NSS4_MCS5 = 0x365, 523 RTW89_HW_RATE_V1_HE_NSS4_MCS6 = 0x366, 524 RTW89_HW_RATE_V1_HE_NSS4_MCS7 = 0x367, 525 RTW89_HW_RATE_V1_HE_NSS4_MCS8 = 0x368, 526 RTW89_HW_RATE_V1_HE_NSS4_MCS9 = 0x369, 527 RTW89_HW_RATE_V1_HE_NSS4_MCS10 = 0x36A, 528 RTW89_HW_RATE_V1_HE_NSS4_MCS11 = 0x36B, 529 RTW89_HW_RATE_V1_EHT_NSS1_MCS0 = 0x400, 530 RTW89_HW_RATE_V1_EHT_NSS1_MCS1 = 0x401, 531 RTW89_HW_RATE_V1_EHT_NSS1_MCS2 = 0x402, 532 RTW89_HW_RATE_V1_EHT_NSS1_MCS3 = 0x403, 533 RTW89_HW_RATE_V1_EHT_NSS1_MCS4 = 0x404, 534 RTW89_HW_RATE_V1_EHT_NSS1_MCS5 = 0x405, 535 RTW89_HW_RATE_V1_EHT_NSS1_MCS6 = 0x406, 536 RTW89_HW_RATE_V1_EHT_NSS1_MCS7 = 0x407, 537 RTW89_HW_RATE_V1_EHT_NSS1_MCS8 = 0x408, 538 RTW89_HW_RATE_V1_EHT_NSS1_MCS9 = 0x409, 539 RTW89_HW_RATE_V1_EHT_NSS1_MCS10 = 0x40A, 540 RTW89_HW_RATE_V1_EHT_NSS1_MCS11 = 0x40B, 541 RTW89_HW_RATE_V1_EHT_NSS1_MCS12 = 0x40C, 542 RTW89_HW_RATE_V1_EHT_NSS1_MCS13 = 0x40D, 543 RTW89_HW_RATE_V1_EHT_NSS1_MCS14 = 0x40E, 544 RTW89_HW_RATE_V1_EHT_NSS1_MCS15 = 0x40F, 545 RTW89_HW_RATE_V1_EHT_NSS2_MCS0 = 0x420, 546 RTW89_HW_RATE_V1_EHT_NSS2_MCS1 = 0x421, 547 RTW89_HW_RATE_V1_EHT_NSS2_MCS2 = 0x422, 548 RTW89_HW_RATE_V1_EHT_NSS2_MCS3 = 0x423, 549 RTW89_HW_RATE_V1_EHT_NSS2_MCS4 = 0x424, 550 RTW89_HW_RATE_V1_EHT_NSS2_MCS5 = 0x425, 551 RTW89_HW_RATE_V1_EHT_NSS2_MCS6 = 0x426, 552 RTW89_HW_RATE_V1_EHT_NSS2_MCS7 = 0x427, 553 RTW89_HW_RATE_V1_EHT_NSS2_MCS8 = 0x428, 554 RTW89_HW_RATE_V1_EHT_NSS2_MCS9 = 0x429, 555 RTW89_HW_RATE_V1_EHT_NSS2_MCS10 = 0x42A, 556 RTW89_HW_RATE_V1_EHT_NSS2_MCS11 = 0x42B, 557 RTW89_HW_RATE_V1_EHT_NSS2_MCS12 = 0x42C, 558 RTW89_HW_RATE_V1_EHT_NSS2_MCS13 = 0x42D, 559 RTW89_HW_RATE_V1_EHT_NSS3_MCS0 = 0x440, 560 RTW89_HW_RATE_V1_EHT_NSS3_MCS1 = 0x441, 561 RTW89_HW_RATE_V1_EHT_NSS3_MCS2 = 0x442, 562 RTW89_HW_RATE_V1_EHT_NSS3_MCS3 = 0x443, 563 RTW89_HW_RATE_V1_EHT_NSS3_MCS4 = 0x444, 564 RTW89_HW_RATE_V1_EHT_NSS3_MCS5 = 0x445, 565 RTW89_HW_RATE_V1_EHT_NSS3_MCS6 = 0x446, 566 RTW89_HW_RATE_V1_EHT_NSS3_MCS7 = 0x447, 567 RTW89_HW_RATE_V1_EHT_NSS3_MCS8 = 0x448, 568 RTW89_HW_RATE_V1_EHT_NSS3_MCS9 = 0x449, 569 RTW89_HW_RATE_V1_EHT_NSS3_MCS10 = 0x44A, 570 RTW89_HW_RATE_V1_EHT_NSS3_MCS11 = 0x44B, 571 RTW89_HW_RATE_V1_EHT_NSS3_MCS12 = 0x44C, 572 RTW89_HW_RATE_V1_EHT_NSS3_MCS13 = 0x44D, 573 RTW89_HW_RATE_V1_EHT_NSS4_MCS0 = 0x460, 574 RTW89_HW_RATE_V1_EHT_NSS4_MCS1 = 0x461, 575 RTW89_HW_RATE_V1_EHT_NSS4_MCS2 = 0x462, 576 RTW89_HW_RATE_V1_EHT_NSS4_MCS3 = 0x463, 577 RTW89_HW_RATE_V1_EHT_NSS4_MCS4 = 0x464, 578 RTW89_HW_RATE_V1_EHT_NSS4_MCS5 = 0x465, 579 RTW89_HW_RATE_V1_EHT_NSS4_MCS6 = 0x466, 580 RTW89_HW_RATE_V1_EHT_NSS4_MCS7 = 0x467, 581 RTW89_HW_RATE_V1_EHT_NSS4_MCS8 = 0x468, 582 RTW89_HW_RATE_V1_EHT_NSS4_MCS9 = 0x469, 583 RTW89_HW_RATE_V1_EHT_NSS4_MCS10 = 0x46A, 584 RTW89_HW_RATE_V1_EHT_NSS4_MCS11 = 0x46B, 585 RTW89_HW_RATE_V1_EHT_NSS4_MCS12 = 0x46C, 586 RTW89_HW_RATE_V1_EHT_NSS4_MCS13 = 0x46D, 587 588 RTW89_HW_RATE_NR, 589 RTW89_HW_RATE_INVAL, 590 591 RTW89_HW_RATE_MASK_MOD = GENMASK(8, 7), 592 RTW89_HW_RATE_MASK_VAL = GENMASK(6, 0), 593 RTW89_HW_RATE_V1_MASK_MOD = GENMASK(10, 8), 594 RTW89_HW_RATE_V1_MASK_VAL = GENMASK(7, 0), 595 }; 596 597 /* 2G channels, 598 * 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 599 */ 600 #define RTW89_2G_CH_NUM 14 601 602 /* 5G channels, 603 * 36, 38, 40, 42, 44, 46, 48, 50, 604 * 52, 54, 56, 58, 60, 62, 64, 605 * 100, 102, 104, 106, 108, 110, 112, 114, 606 * 116, 118, 120, 122, 124, 126, 128, 130, 607 * 132, 134, 136, 138, 140, 142, 144, 608 * 149, 151, 153, 155, 157, 159, 161, 163, 609 * 165, 167, 169, 171, 173, 175, 177 610 */ 611 #define RTW89_5G_CH_NUM 53 612 613 /* 6G channels, 614 * 1, 3, 5, 7, 9, 11, 13, 15, 615 * 17, 19, 21, 23, 25, 27, 29, 33, 616 * 35, 37, 39, 41, 43, 45, 47, 49, 617 * 51, 53, 55, 57, 59, 61, 65, 67, 618 * 69, 71, 73, 75, 77, 79, 81, 83, 619 * 85, 87, 89, 91, 93, 97, 99, 101, 620 * 103, 105, 107, 109, 111, 113, 115, 117, 621 * 119, 121, 123, 125, 129, 131, 133, 135, 622 * 137, 139, 141, 143, 145, 147, 149, 151, 623 * 153, 155, 157, 161, 163, 165, 167, 169, 624 * 171, 173, 175, 177, 179, 181, 183, 185, 625 * 187, 189, 193, 195, 197, 199, 201, 203, 626 * 205, 207, 209, 211, 213, 215, 217, 219, 627 * 221, 225, 227, 229, 231, 233, 235, 237, 628 * 239, 241, 243, 245, 247, 249, 251, 253, 629 */ 630 #define RTW89_6G_CH_NUM 120 631 632 enum rtw89_rate_section { 633 RTW89_RS_CCK, 634 RTW89_RS_OFDM, 635 RTW89_RS_MCS, /* for HT/VHT/HE */ 636 RTW89_RS_HEDCM, 637 RTW89_RS_OFFSET, 638 RTW89_RS_NUM, 639 RTW89_RS_LMT_NUM = RTW89_RS_MCS + 1, 640 RTW89_RS_TX_SHAPE_NUM = RTW89_RS_OFDM + 1, 641 }; 642 643 enum rtw89_rate_offset_indexes { 644 RTW89_RATE_OFFSET_HE, 645 RTW89_RATE_OFFSET_VHT, 646 RTW89_RATE_OFFSET_HT, 647 RTW89_RATE_OFFSET_OFDM, 648 RTW89_RATE_OFFSET_CCK, 649 RTW89_RATE_OFFSET_DLRU_EHT, 650 RTW89_RATE_OFFSET_DLRU_HE, 651 RTW89_RATE_OFFSET_EHT, 652 __RTW89_RATE_OFFSET_NUM, 653 654 RTW89_RATE_OFFSET_NUM_AX = RTW89_RATE_OFFSET_CCK + 1, 655 RTW89_RATE_OFFSET_NUM_BE = RTW89_RATE_OFFSET_EHT + 1, 656 }; 657 658 enum rtw89_rate_num { 659 RTW89_RATE_CCK_NUM = 4, 660 RTW89_RATE_OFDM_NUM = 8, 661 RTW89_RATE_HEDCM_NUM = 4, /* for HEDCM MCS0/1/3/4 */ 662 663 RTW89_RATE_MCS_NUM_AX = 12, 664 RTW89_RATE_MCS_NUM_BE = 16, 665 __RTW89_RATE_MCS_NUM = 16, 666 }; 667 668 enum rtw89_nss { 669 RTW89_NSS_1 = 0, 670 RTW89_NSS_2 = 1, 671 /* HE DCM only support 1ss and 2ss */ 672 RTW89_NSS_HEDCM_NUM = RTW89_NSS_2 + 1, 673 RTW89_NSS_3 = 2, 674 RTW89_NSS_4 = 3, 675 RTW89_NSS_NUM, 676 }; 677 678 enum rtw89_ntx { 679 RTW89_1TX = 0, 680 RTW89_2TX = 1, 681 RTW89_NTX_NUM, 682 }; 683 684 enum rtw89_beamforming_type { 685 RTW89_NONBF = 0, 686 RTW89_BF = 1, 687 RTW89_BF_NUM, 688 }; 689 690 enum rtw89_ofdma_type { 691 RTW89_NON_OFDMA = 0, 692 RTW89_OFDMA = 1, 693 RTW89_OFDMA_NUM, 694 }; 695 696 enum rtw89_regulation_type { 697 RTW89_WW = 0, 698 RTW89_ETSI = 1, 699 RTW89_FCC = 2, 700 RTW89_MKK = 3, 701 RTW89_NA = 4, 702 RTW89_IC = 5, 703 RTW89_KCC = 6, 704 RTW89_ACMA = 7, 705 RTW89_NCC = 8, 706 RTW89_MEXICO = 9, 707 RTW89_CHILE = 10, 708 RTW89_UKRAINE = 11, 709 RTW89_CN = 12, 710 RTW89_QATAR = 13, 711 RTW89_UK = 14, 712 RTW89_THAILAND = 15, 713 RTW89_REGD_NUM, 714 }; 715 716 enum rtw89_reg_6ghz_power { 717 RTW89_REG_6GHZ_POWER_VLP = 0, 718 RTW89_REG_6GHZ_POWER_LPI = 1, 719 RTW89_REG_6GHZ_POWER_STD = 2, 720 721 NUM_OF_RTW89_REG_6GHZ_POWER, 722 RTW89_REG_6GHZ_POWER_DFLT = RTW89_REG_6GHZ_POWER_VLP, 723 }; 724 725 enum rtw89_fw_pkt_ofld_type { 726 RTW89_PKT_OFLD_TYPE_PROBE_RSP = 0, 727 RTW89_PKT_OFLD_TYPE_PS_POLL = 1, 728 RTW89_PKT_OFLD_TYPE_NULL_DATA = 2, 729 RTW89_PKT_OFLD_TYPE_QOS_NULL = 3, 730 RTW89_PKT_OFLD_TYPE_CTS2SELF = 4, 731 RTW89_PKT_OFLD_TYPE_ARP_RSP = 5, 732 RTW89_PKT_OFLD_TYPE_NDP = 6, 733 RTW89_PKT_OFLD_TYPE_EAPOL_KEY = 7, 734 RTW89_PKT_OFLD_TYPE_SA_QUERY = 8, 735 RTW89_PKT_OFLD_TYPE_PROBE_REQ = 12, 736 RTW89_PKT_OFLD_TYPE_NUM, 737 }; 738 739 struct rtw89_txpwr_byrate { 740 s8 cck[RTW89_RATE_CCK_NUM]; 741 s8 ofdm[RTW89_RATE_OFDM_NUM]; 742 s8 mcs[RTW89_OFDMA_NUM][RTW89_NSS_NUM][__RTW89_RATE_MCS_NUM]; 743 s8 hedcm[RTW89_OFDMA_NUM][RTW89_NSS_HEDCM_NUM][RTW89_RATE_HEDCM_NUM]; 744 s8 offset[__RTW89_RATE_OFFSET_NUM]; 745 s8 trap; 746 }; 747 748 struct rtw89_rate_desc { 749 enum rtw89_nss nss; 750 enum rtw89_rate_section rs; 751 enum rtw89_ofdma_type ofdma; 752 u8 idx; 753 }; 754 755 #define PHY_STS_HDR_LEN 8 756 #define RF_PATH_MAX 4 757 #define RTW89_MAX_PPDU_CNT 8 758 struct rtw89_rx_phy_ppdu { 759 void *buf; 760 u32 len; 761 u8 rssi_avg; 762 u8 rssi[RF_PATH_MAX]; 763 u8 mac_id; 764 u8 chan_idx; 765 u8 ie; 766 u16 rate; 767 struct { 768 bool has; 769 u8 avg_snr; 770 u8 evm_max; 771 u8 evm_min; 772 } ofdm; 773 bool to_self; 774 bool valid; 775 }; 776 777 enum rtw89_mac_idx { 778 RTW89_MAC_0 = 0, 779 RTW89_MAC_1 = 1, 780 }; 781 782 enum rtw89_phy_idx { 783 RTW89_PHY_0 = 0, 784 RTW89_PHY_1 = 1, 785 RTW89_PHY_MAX 786 }; 787 788 enum rtw89_sub_entity_idx { 789 RTW89_SUB_ENTITY_0 = 0, 790 RTW89_SUB_ENTITY_1 = 1, 791 792 NUM_OF_RTW89_SUB_ENTITY, 793 RTW89_SUB_ENTITY_IDLE = NUM_OF_RTW89_SUB_ENTITY, 794 }; 795 796 enum rtw89_rf_path { 797 RF_PATH_A = 0, 798 RF_PATH_B = 1, 799 RF_PATH_C = 2, 800 RF_PATH_D = 3, 801 RF_PATH_AB, 802 RF_PATH_AC, 803 RF_PATH_AD, 804 RF_PATH_BC, 805 RF_PATH_BD, 806 RF_PATH_CD, 807 RF_PATH_ABC, 808 RF_PATH_ABD, 809 RF_PATH_ACD, 810 RF_PATH_BCD, 811 RF_PATH_ABCD, 812 }; 813 814 enum rtw89_rf_path_bit { 815 RF_A = BIT(0), 816 RF_B = BIT(1), 817 RF_C = BIT(2), 818 RF_D = BIT(3), 819 820 RF_AB = (RF_A | RF_B), 821 RF_AC = (RF_A | RF_C), 822 RF_AD = (RF_A | RF_D), 823 RF_BC = (RF_B | RF_C), 824 RF_BD = (RF_B | RF_D), 825 RF_CD = (RF_C | RF_D), 826 827 RF_ABC = (RF_A | RF_B | RF_C), 828 RF_ABD = (RF_A | RF_B | RF_D), 829 RF_ACD = (RF_A | RF_C | RF_D), 830 RF_BCD = (RF_B | RF_C | RF_D), 831 832 RF_ABCD = (RF_A | RF_B | RF_C | RF_D), 833 }; 834 835 enum rtw89_bandwidth { 836 RTW89_CHANNEL_WIDTH_20 = 0, 837 RTW89_CHANNEL_WIDTH_40 = 1, 838 RTW89_CHANNEL_WIDTH_80 = 2, 839 RTW89_CHANNEL_WIDTH_160 = 3, 840 RTW89_CHANNEL_WIDTH_320 = 4, 841 842 /* keep index order above */ 843 RTW89_CHANNEL_WIDTH_ORDINARY_NUM = 5, 844 845 RTW89_CHANNEL_WIDTH_80_80 = 5, 846 RTW89_CHANNEL_WIDTH_5 = 6, 847 RTW89_CHANNEL_WIDTH_10 = 7, 848 }; 849 850 enum rtw89_ps_mode { 851 RTW89_PS_MODE_NONE = 0, 852 RTW89_PS_MODE_RFOFF = 1, 853 RTW89_PS_MODE_CLK_GATED = 2, 854 RTW89_PS_MODE_PWR_GATED = 3, 855 }; 856 857 #define RTW89_2G_BW_NUM (RTW89_CHANNEL_WIDTH_40 + 1) 858 #define RTW89_5G_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 859 #define RTW89_6G_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 860 #define RTW89_BYR_BW_NUM (RTW89_CHANNEL_WIDTH_320 + 1) 861 #define RTW89_PPE_BW_NUM (RTW89_CHANNEL_WIDTH_160 + 1) 862 863 enum rtw89_ru_bandwidth { 864 RTW89_RU26 = 0, 865 RTW89_RU52 = 1, 866 RTW89_RU106 = 2, 867 RTW89_RU52_26 = 3, 868 RTW89_RU106_26 = 4, 869 RTW89_RU_NUM, 870 }; 871 872 enum rtw89_sc_offset { 873 RTW89_SC_DONT_CARE = 0, 874 RTW89_SC_20_UPPER = 1, 875 RTW89_SC_20_LOWER = 2, 876 RTW89_SC_20_UPMOST = 3, 877 RTW89_SC_20_LOWEST = 4, 878 RTW89_SC_20_UP2X = 5, 879 RTW89_SC_20_LOW2X = 6, 880 RTW89_SC_20_UP3X = 7, 881 RTW89_SC_20_LOW3X = 8, 882 RTW89_SC_40_UPPER = 9, 883 RTW89_SC_40_LOWER = 10, 884 }; 885 886 enum rtw89_wow_flags { 887 RTW89_WOW_FLAG_EN_MAGIC_PKT, 888 RTW89_WOW_FLAG_EN_REKEY_PKT, 889 RTW89_WOW_FLAG_EN_DISCONNECT, 890 RTW89_WOW_FLAG_NUM, 891 }; 892 893 struct rtw89_chan { 894 u8 channel; 895 u8 primary_channel; 896 enum rtw89_band band_type; 897 enum rtw89_bandwidth band_width; 898 899 /* The follow-up are derived from the above. We must ensure that it 900 * is assigned correctly in rtw89_chan_create() if new one is added. 901 */ 902 u32 freq; 903 enum rtw89_subband subband_type; 904 enum rtw89_sc_offset pri_ch_idx; 905 u8 pri_sb_idx; 906 }; 907 908 struct rtw89_chan_rcd { 909 u8 prev_primary_channel; 910 enum rtw89_band prev_band_type; 911 bool band_changed; 912 }; 913 914 struct rtw89_channel_help_params { 915 u32 tx_en; 916 }; 917 918 struct rtw89_port_reg { 919 u32 port_cfg; 920 u32 tbtt_prohib; 921 u32 bcn_area; 922 u32 bcn_early; 923 u32 tbtt_early; 924 u32 tbtt_agg; 925 u32 bcn_space; 926 u32 bcn_forcetx; 927 u32 bcn_err_cnt; 928 u32 bcn_err_flag; 929 u32 dtim_ctrl; 930 u32 tbtt_shift; 931 u32 bcn_cnt_tmr; 932 u32 tsftr_l; 933 u32 tsftr_h; 934 u32 md_tsft; 935 u32 bss_color; 936 u32 mbssid; 937 u32 mbssid_drop; 938 u32 tsf_sync; 939 u32 hiq_win[RTW89_PORT_NUM]; 940 }; 941 942 struct rtw89_txwd_body { 943 __le32 dword0; 944 __le32 dword1; 945 __le32 dword2; 946 __le32 dword3; 947 __le32 dword4; 948 __le32 dword5; 949 } __packed; 950 951 struct rtw89_txwd_body_v1 { 952 __le32 dword0; 953 __le32 dword1; 954 __le32 dword2; 955 __le32 dword3; 956 __le32 dword4; 957 __le32 dword5; 958 __le32 dword6; 959 __le32 dword7; 960 } __packed; 961 962 struct rtw89_txwd_body_v2 { 963 __le32 dword0; 964 __le32 dword1; 965 __le32 dword2; 966 __le32 dword3; 967 __le32 dword4; 968 __le32 dword5; 969 __le32 dword6; 970 __le32 dword7; 971 } __packed; 972 973 struct rtw89_txwd_info { 974 __le32 dword0; 975 __le32 dword1; 976 __le32 dword2; 977 __le32 dword3; 978 __le32 dword4; 979 __le32 dword5; 980 } __packed; 981 982 struct rtw89_txwd_info_v2 { 983 __le32 dword0; 984 __le32 dword1; 985 __le32 dword2; 986 __le32 dword3; 987 __le32 dword4; 988 __le32 dword5; 989 __le32 dword6; 990 __le32 dword7; 991 } __packed; 992 993 struct rtw89_rx_desc_info { 994 u16 pkt_size; 995 u8 pkt_type; 996 u8 drv_info_size; 997 u8 phy_rpt_size; 998 u8 hdr_cnv_size; 999 u8 shift; 1000 u8 wl_hd_iv_len; 1001 bool long_rxdesc; 1002 bool bb_sel; 1003 bool mac_info_valid; 1004 u16 data_rate; 1005 u8 gi_ltf; 1006 u8 bw; 1007 u32 free_run_cnt; 1008 u8 user_id; 1009 bool sr_en; 1010 u8 ppdu_cnt; 1011 u8 ppdu_type; 1012 bool icv_err; 1013 bool crc32_err; 1014 bool hw_dec; 1015 bool sw_dec; 1016 bool addr1_match; 1017 u8 frag; 1018 u16 seq; 1019 u8 frame_type; 1020 u8 rx_pl_id; 1021 bool addr_cam_valid; 1022 u8 addr_cam_id; 1023 u8 sec_cam_id; 1024 u8 mac_id; 1025 u16 offset; 1026 u16 rxd_len; 1027 bool ready; 1028 }; 1029 1030 struct rtw89_rxdesc_short { 1031 __le32 dword0; 1032 __le32 dword1; 1033 __le32 dword2; 1034 __le32 dword3; 1035 } __packed; 1036 1037 struct rtw89_rxdesc_short_v2 { 1038 __le32 dword0; 1039 __le32 dword1; 1040 __le32 dword2; 1041 __le32 dword3; 1042 __le32 dword4; 1043 __le32 dword5; 1044 } __packed; 1045 1046 struct rtw89_rxdesc_long { 1047 __le32 dword0; 1048 __le32 dword1; 1049 __le32 dword2; 1050 __le32 dword3; 1051 __le32 dword4; 1052 __le32 dword5; 1053 __le32 dword6; 1054 __le32 dword7; 1055 } __packed; 1056 1057 struct rtw89_rxdesc_long_v2 { 1058 __le32 dword0; 1059 __le32 dword1; 1060 __le32 dword2; 1061 __le32 dword3; 1062 __le32 dword4; 1063 __le32 dword5; 1064 __le32 dword6; 1065 __le32 dword7; 1066 __le32 dword8; 1067 __le32 dword9; 1068 } __packed; 1069 1070 struct rtw89_tx_desc_info { 1071 u16 pkt_size; 1072 u8 wp_offset; 1073 u8 mac_id; 1074 u8 qsel; 1075 u8 ch_dma; 1076 u8 hdr_llc_len; 1077 bool is_bmc; 1078 bool en_wd_info; 1079 bool wd_page; 1080 bool use_rate; 1081 bool dis_data_fb; 1082 bool tid_indicate; 1083 bool agg_en; 1084 bool bk; 1085 u8 ampdu_density; 1086 u8 ampdu_num; 1087 bool sec_en; 1088 u8 addr_info_nr; 1089 u8 sec_keyid; 1090 u8 sec_type; 1091 u8 sec_cam_idx; 1092 u8 sec_seq[6]; 1093 u16 data_rate; 1094 u16 data_retry_lowest_rate; 1095 bool fw_dl; 1096 u16 seq; 1097 bool a_ctrl_bsr; 1098 u8 hw_ssn_sel; 1099 #define RTW89_MGMT_HW_SSN_SEL 1 1100 u8 hw_seq_mode; 1101 #define RTW89_MGMT_HW_SEQ_MODE 1 1102 bool hiq; 1103 u8 port; 1104 bool er_cap; 1105 }; 1106 1107 struct rtw89_core_tx_request { 1108 enum rtw89_core_tx_type tx_type; 1109 1110 struct sk_buff *skb; 1111 struct ieee80211_vif *vif; 1112 struct ieee80211_sta *sta; 1113 struct rtw89_tx_desc_info desc_info; 1114 }; 1115 1116 struct rtw89_txq { 1117 struct list_head list; 1118 unsigned long flags; 1119 int wait_cnt; 1120 }; 1121 1122 struct rtw89_mac_ax_gnt { 1123 u8 gnt_bt_sw_en; 1124 u8 gnt_bt; 1125 u8 gnt_wl_sw_en; 1126 u8 gnt_wl; 1127 } __packed; 1128 1129 #define RTW89_MAC_AX_COEX_GNT_NR 2 1130 struct rtw89_mac_ax_coex_gnt { 1131 struct rtw89_mac_ax_gnt band[RTW89_MAC_AX_COEX_GNT_NR]; 1132 }; 1133 1134 enum rtw89_btc_ncnt { 1135 BTC_NCNT_POWER_ON = 0x0, 1136 BTC_NCNT_POWER_OFF, 1137 BTC_NCNT_INIT_COEX, 1138 BTC_NCNT_SCAN_START, 1139 BTC_NCNT_SCAN_FINISH, 1140 BTC_NCNT_SPECIAL_PACKET, 1141 BTC_NCNT_SWITCH_BAND, 1142 BTC_NCNT_RFK_TIMEOUT, 1143 BTC_NCNT_SHOW_COEX_INFO, 1144 BTC_NCNT_ROLE_INFO, 1145 BTC_NCNT_CONTROL, 1146 BTC_NCNT_RADIO_STATE, 1147 BTC_NCNT_CUSTOMERIZE, 1148 BTC_NCNT_WL_RFK, 1149 BTC_NCNT_WL_STA, 1150 BTC_NCNT_FWINFO, 1151 BTC_NCNT_TIMER, 1152 BTC_NCNT_NUM 1153 }; 1154 1155 enum rtw89_btc_btinfo { 1156 BTC_BTINFO_L0 = 0, 1157 BTC_BTINFO_L1, 1158 BTC_BTINFO_L2, 1159 BTC_BTINFO_L3, 1160 BTC_BTINFO_H0, 1161 BTC_BTINFO_H1, 1162 BTC_BTINFO_H2, 1163 BTC_BTINFO_H3, 1164 BTC_BTINFO_MAX 1165 }; 1166 1167 enum rtw89_btc_dcnt { 1168 BTC_DCNT_RUN = 0x0, 1169 BTC_DCNT_CX_RUNINFO, 1170 BTC_DCNT_RPT, 1171 BTC_DCNT_RPT_HANG, 1172 BTC_DCNT_CYCLE, 1173 BTC_DCNT_CYCLE_HANG, 1174 BTC_DCNT_W1, 1175 BTC_DCNT_W1_HANG, 1176 BTC_DCNT_B1, 1177 BTC_DCNT_B1_HANG, 1178 BTC_DCNT_TDMA_NONSYNC, 1179 BTC_DCNT_SLOT_NONSYNC, 1180 BTC_DCNT_BTCNT_HANG, 1181 BTC_DCNT_WL_SLOT_DRIFT, 1182 BTC_DCNT_WL_STA_LAST, 1183 BTC_DCNT_BT_SLOT_DRIFT, 1184 BTC_DCNT_BT_SLOT_FLOOD, 1185 BTC_DCNT_FDDT_TRIG, 1186 BTC_DCNT_E2G, 1187 BTC_DCNT_E2G_HANG, 1188 BTC_DCNT_NUM 1189 }; 1190 1191 enum rtw89_btc_wl_state_cnt { 1192 BTC_WCNT_SCANAP = 0x0, 1193 BTC_WCNT_DHCP, 1194 BTC_WCNT_EAPOL, 1195 BTC_WCNT_ARP, 1196 BTC_WCNT_SCBDUPDATE, 1197 BTC_WCNT_RFK_REQ, 1198 BTC_WCNT_RFK_GO, 1199 BTC_WCNT_RFK_REJECT, 1200 BTC_WCNT_RFK_TIMEOUT, 1201 BTC_WCNT_CH_UPDATE, 1202 BTC_WCNT_NUM 1203 }; 1204 1205 enum rtw89_btc_bt_state_cnt { 1206 BTC_BCNT_RETRY = 0x0, 1207 BTC_BCNT_REINIT, 1208 BTC_BCNT_REENABLE, 1209 BTC_BCNT_SCBDREAD, 1210 BTC_BCNT_RELINK, 1211 BTC_BCNT_IGNOWL, 1212 BTC_BCNT_INQPAG, 1213 BTC_BCNT_INQ, 1214 BTC_BCNT_PAGE, 1215 BTC_BCNT_ROLESW, 1216 BTC_BCNT_AFH, 1217 BTC_BCNT_INFOUPDATE, 1218 BTC_BCNT_INFOSAME, 1219 BTC_BCNT_SCBDUPDATE, 1220 BTC_BCNT_HIPRI_TX, 1221 BTC_BCNT_HIPRI_RX, 1222 BTC_BCNT_LOPRI_TX, 1223 BTC_BCNT_LOPRI_RX, 1224 BTC_BCNT_POLUT, 1225 BTC_BCNT_RATECHG, 1226 BTC_BCNT_NUM 1227 }; 1228 1229 enum rtw89_btc_bt_profile { 1230 BTC_BT_NOPROFILE = 0, 1231 BTC_BT_HFP = BIT(0), 1232 BTC_BT_HID = BIT(1), 1233 BTC_BT_A2DP = BIT(2), 1234 BTC_BT_PAN = BIT(3), 1235 BTC_PROFILE_MAX = 4, 1236 }; 1237 1238 struct rtw89_btc_ant_info { 1239 u8 type; /* shared, dedicated */ 1240 u8 num; 1241 u8 isolation; 1242 1243 u8 single_pos: 1;/* Single antenna at S0 or S1 */ 1244 u8 diversity: 1; 1245 u8 btg_pos: 2; 1246 u8 stream_cnt: 4; 1247 }; 1248 1249 enum rtw89_tfc_dir { 1250 RTW89_TFC_UL, 1251 RTW89_TFC_DL, 1252 }; 1253 1254 struct rtw89_btc_wl_smap { 1255 u32 busy: 1; 1256 u32 scan: 1; 1257 u32 connecting: 1; 1258 u32 roaming: 1; 1259 u32 _4way: 1; 1260 u32 rf_off: 1; 1261 u32 lps: 2; 1262 u32 ips: 1; 1263 u32 init_ok: 1; 1264 u32 traffic_dir : 2; 1265 u32 rf_off_pre: 1; 1266 u32 lps_pre: 2; 1267 }; 1268 1269 enum rtw89_tfc_lv { 1270 RTW89_TFC_IDLE, 1271 RTW89_TFC_ULTRA_LOW, 1272 RTW89_TFC_LOW, 1273 RTW89_TFC_MID, 1274 RTW89_TFC_HIGH, 1275 }; 1276 1277 #define RTW89_TP_SHIFT 18 /* bytes/2s --> Mbps */ 1278 DECLARE_EWMA(tp, 10, 2); 1279 1280 struct rtw89_traffic_stats { 1281 /* units in bytes */ 1282 u64 tx_unicast; 1283 u64 rx_unicast; 1284 u32 tx_avg_len; 1285 u32 rx_avg_len; 1286 1287 /* count for packets */ 1288 u64 tx_cnt; 1289 u64 rx_cnt; 1290 1291 /* units in Mbps */ 1292 u32 tx_throughput; 1293 u32 rx_throughput; 1294 u32 tx_throughput_raw; 1295 u32 rx_throughput_raw; 1296 1297 u32 rx_tf_acc; 1298 u32 rx_tf_periodic; 1299 1300 enum rtw89_tfc_lv tx_tfc_lv; 1301 enum rtw89_tfc_lv rx_tfc_lv; 1302 struct ewma_tp tx_ewma_tp; 1303 struct ewma_tp rx_ewma_tp; 1304 1305 u16 tx_rate; 1306 u16 rx_rate; 1307 }; 1308 1309 struct rtw89_btc_statistic { 1310 u8 rssi; /* 0%~110% (dBm = rssi -110) */ 1311 struct rtw89_traffic_stats traffic; 1312 }; 1313 1314 #define BTC_WL_RSSI_THMAX 4 1315 1316 struct rtw89_btc_wl_link_info { 1317 struct rtw89_btc_statistic stat; 1318 enum rtw89_tfc_dir dir; 1319 u8 rssi_state[BTC_WL_RSSI_THMAX]; 1320 u8 mac_addr[ETH_ALEN]; 1321 u8 busy; 1322 u8 ch; 1323 u8 bw; 1324 u8 band; 1325 u8 role; 1326 u8 pid; 1327 u8 phy; 1328 u8 dtim_period; 1329 u8 mode; 1330 1331 u8 mac_id; 1332 u8 tx_retry; 1333 1334 u32 bcn_period; 1335 u32 busy_t; 1336 u32 tx_time; 1337 u32 client_cnt; 1338 u32 rx_rate_drop_cnt; 1339 1340 u32 active: 1; 1341 u32 noa: 1; 1342 u32 client_ps: 1; 1343 u32 connected: 2; 1344 }; 1345 1346 union rtw89_btc_wl_state_map { 1347 u32 val; 1348 struct rtw89_btc_wl_smap map; 1349 }; 1350 1351 struct rtw89_btc_bt_hfp_desc { 1352 u32 exist: 1; 1353 u32 type: 2; 1354 u32 rsvd: 29; 1355 }; 1356 1357 struct rtw89_btc_bt_hid_desc { 1358 u32 exist: 1; 1359 u32 slot_info: 2; 1360 u32 pair_cnt: 2; 1361 u32 type: 8; 1362 u32 rsvd: 19; 1363 }; 1364 1365 struct rtw89_btc_bt_a2dp_desc { 1366 u8 exist: 1; 1367 u8 exist_last: 1; 1368 u8 play_latency: 1; 1369 u8 type: 3; 1370 u8 active: 1; 1371 u8 sink: 1; 1372 1373 u8 bitpool; 1374 u16 vendor_id; 1375 u32 device_name; 1376 u32 flush_time; 1377 }; 1378 1379 struct rtw89_btc_bt_pan_desc { 1380 u32 exist: 1; 1381 u32 type: 1; 1382 u32 active: 1; 1383 u32 rsvd: 29; 1384 }; 1385 1386 struct rtw89_btc_bt_rfk_info { 1387 u32 run: 1; 1388 u32 req: 1; 1389 u32 timeout: 1; 1390 u32 rsvd: 29; 1391 }; 1392 1393 union rtw89_btc_bt_rfk_info_map { 1394 u32 val; 1395 struct rtw89_btc_bt_rfk_info map; 1396 }; 1397 1398 struct rtw89_btc_bt_ver_info { 1399 u32 fw_coex; /* match with which coex_ver */ 1400 u32 fw; 1401 }; 1402 1403 struct rtw89_btc_bool_sta_chg { 1404 u32 now: 1; 1405 u32 last: 1; 1406 u32 remain: 1; 1407 u32 srvd: 29; 1408 }; 1409 1410 struct rtw89_btc_u8_sta_chg { 1411 u8 now; 1412 u8 last; 1413 u8 remain; 1414 u8 rsvd; 1415 }; 1416 1417 struct rtw89_btc_wl_scan_info { 1418 u8 band[RTW89_PHY_MAX]; 1419 u8 phy_map; 1420 u8 rsvd; 1421 }; 1422 1423 struct rtw89_btc_wl_dbcc_info { 1424 u8 op_band[RTW89_PHY_MAX]; /* op band in each phy */ 1425 u8 scan_band[RTW89_PHY_MAX]; /* scan band in each phy */ 1426 u8 real_band[RTW89_PHY_MAX]; 1427 u8 role[RTW89_PHY_MAX]; /* role in each phy */ 1428 }; 1429 1430 struct rtw89_btc_wl_active_role { 1431 u8 connected: 1; 1432 u8 pid: 3; 1433 u8 phy: 1; 1434 u8 noa: 1; 1435 u8 band: 2; 1436 1437 u8 client_ps: 1; 1438 u8 bw: 7; 1439 1440 u8 role; 1441 u8 ch; 1442 1443 u16 tx_lvl; 1444 u16 rx_lvl; 1445 u16 tx_rate; 1446 u16 rx_rate; 1447 }; 1448 1449 struct rtw89_btc_wl_active_role_v1 { 1450 u8 connected: 1; 1451 u8 pid: 3; 1452 u8 phy: 1; 1453 u8 noa: 1; 1454 u8 band: 2; 1455 1456 u8 client_ps: 1; 1457 u8 bw: 7; 1458 1459 u8 role; 1460 u8 ch; 1461 1462 u16 tx_lvl; 1463 u16 rx_lvl; 1464 u16 tx_rate; 1465 u16 rx_rate; 1466 1467 u32 noa_duration; /* ms */ 1468 }; 1469 1470 struct rtw89_btc_wl_active_role_v2 { 1471 u8 connected: 1; 1472 u8 pid: 3; 1473 u8 phy: 1; 1474 u8 noa: 1; 1475 u8 band: 2; 1476 1477 u8 client_ps: 1; 1478 u8 bw: 7; 1479 1480 u8 role; 1481 u8 ch; 1482 1483 u32 noa_duration; /* ms */ 1484 }; 1485 1486 struct rtw89_btc_wl_role_info_bpos { 1487 u16 none: 1; 1488 u16 station: 1; 1489 u16 ap: 1; 1490 u16 vap: 1; 1491 u16 adhoc: 1; 1492 u16 adhoc_master: 1; 1493 u16 mesh: 1; 1494 u16 moniter: 1; 1495 u16 p2p_device: 1; 1496 u16 p2p_gc: 1; 1497 u16 p2p_go: 1; 1498 u16 nan: 1; 1499 }; 1500 1501 struct rtw89_btc_wl_scc_ctrl { 1502 u8 null_role1; 1503 u8 null_role2; 1504 u8 ebt_null; /* if tx null at EBT slot */ 1505 }; 1506 1507 union rtw89_btc_wl_role_info_map { 1508 u16 val; 1509 struct rtw89_btc_wl_role_info_bpos role; 1510 }; 1511 1512 struct rtw89_btc_wl_role_info { /* struct size must be n*4 bytes */ 1513 u8 connect_cnt; 1514 u8 link_mode; 1515 union rtw89_btc_wl_role_info_map role_map; 1516 struct rtw89_btc_wl_active_role active_role[RTW89_PORT_NUM]; 1517 }; 1518 1519 struct rtw89_btc_wl_role_info_v1 { /* struct size must be n*4 bytes */ 1520 u8 connect_cnt; 1521 u8 link_mode; 1522 union rtw89_btc_wl_role_info_map role_map; 1523 struct rtw89_btc_wl_active_role_v1 active_role_v1[RTW89_PORT_NUM]; 1524 u32 mrole_type; /* btc_wl_mrole_type */ 1525 u32 mrole_noa_duration; /* ms */ 1526 1527 u32 dbcc_en: 1; 1528 u32 dbcc_chg: 1; 1529 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1530 u32 link_mode_chg: 1; 1531 u32 rsvd: 27; 1532 }; 1533 1534 struct rtw89_btc_wl_role_info_v2 { /* struct size must be n*4 bytes */ 1535 u8 connect_cnt; 1536 u8 link_mode; 1537 union rtw89_btc_wl_role_info_map role_map; 1538 struct rtw89_btc_wl_active_role_v2 active_role_v2[RTW89_PORT_NUM]; 1539 u32 mrole_type; /* btc_wl_mrole_type */ 1540 u32 mrole_noa_duration; /* ms */ 1541 1542 u32 dbcc_en: 1; 1543 u32 dbcc_chg: 1; 1544 u32 dbcc_2g_phy: 2; /* which phy operate in 2G, HW_PHY_0 or HW_PHY_1 */ 1545 u32 link_mode_chg: 1; 1546 u32 rsvd: 27; 1547 }; 1548 1549 struct rtw89_btc_wl_ver_info { 1550 u32 fw_coex; /* match with which coex_ver */ 1551 u32 fw; 1552 u32 mac; 1553 u32 bb; 1554 u32 rf; 1555 }; 1556 1557 struct rtw89_btc_wl_afh_info { 1558 u8 en; 1559 u8 ch; 1560 u8 bw; 1561 u8 rsvd; 1562 } __packed; 1563 1564 struct rtw89_btc_wl_rfk_info { 1565 u32 state: 2; 1566 u32 path_map: 4; 1567 u32 phy_map: 2; 1568 u32 band: 2; 1569 u32 type: 8; 1570 u32 rsvd: 14; 1571 }; 1572 1573 struct rtw89_btc_bt_smap { 1574 u32 connect: 1; 1575 u32 ble_connect: 1; 1576 u32 acl_busy: 1; 1577 u32 sco_busy: 1; 1578 u32 mesh_busy: 1; 1579 u32 inq_pag: 1; 1580 }; 1581 1582 union rtw89_btc_bt_state_map { 1583 u32 val; 1584 struct rtw89_btc_bt_smap map; 1585 }; 1586 1587 #define BTC_BT_RSSI_THMAX 4 1588 #define BTC_BT_AFH_GROUP 12 1589 #define BTC_BT_AFH_LE_GROUP 5 1590 1591 struct rtw89_btc_bt_link_info { 1592 struct rtw89_btc_u8_sta_chg profile_cnt; 1593 struct rtw89_btc_bool_sta_chg multi_link; 1594 struct rtw89_btc_bool_sta_chg relink; 1595 struct rtw89_btc_bt_hfp_desc hfp_desc; 1596 struct rtw89_btc_bt_hid_desc hid_desc; 1597 struct rtw89_btc_bt_a2dp_desc a2dp_desc; 1598 struct rtw89_btc_bt_pan_desc pan_desc; 1599 union rtw89_btc_bt_state_map status; 1600 1601 u8 sut_pwr_level[BTC_PROFILE_MAX]; 1602 u8 golden_rx_shift[BTC_PROFILE_MAX]; 1603 u8 rssi_state[BTC_BT_RSSI_THMAX]; 1604 u8 afh_map[BTC_BT_AFH_GROUP]; 1605 u8 afh_map_le[BTC_BT_AFH_LE_GROUP]; 1606 1607 u32 role_sw: 1; 1608 u32 slave_role: 1; 1609 u32 afh_update: 1; 1610 u32 cqddr: 1; 1611 u32 rssi: 8; 1612 u32 tx_3m: 1; 1613 u32 rsvd: 19; 1614 }; 1615 1616 struct rtw89_btc_3rdcx_info { 1617 u8 type; /* 0: none, 1:zigbee, 2:LTE */ 1618 u8 hw_coex; 1619 u16 rsvd; 1620 }; 1621 1622 struct rtw89_btc_dm_emap { 1623 u32 init: 1; 1624 u32 pta_owner: 1; 1625 u32 wl_rfk_timeout: 1; 1626 u32 bt_rfk_timeout: 1; 1627 u32 wl_fw_hang: 1; 1628 u32 cycle_hang: 1; 1629 u32 w1_hang: 1; 1630 u32 b1_hang: 1; 1631 u32 tdma_no_sync: 1; 1632 u32 slot_no_sync: 1; 1633 u32 wl_slot_drift: 1; 1634 u32 bt_slot_drift: 1; 1635 u32 role_num_mismatch: 1; 1636 u32 null1_tx_late: 1; 1637 u32 bt_afh_conflict: 1; 1638 u32 bt_leafh_conflict: 1; 1639 u32 bt_slot_flood: 1; 1640 u32 wl_e2g_hang: 1; 1641 u32 wl_ver_mismatch: 1; 1642 u32 bt_ver_mismatch: 1; 1643 }; 1644 1645 union rtw89_btc_dm_error_map { 1646 u32 val; 1647 struct rtw89_btc_dm_emap map; 1648 }; 1649 1650 struct rtw89_btc_rf_para { 1651 u32 tx_pwr_freerun; 1652 u32 rx_gain_freerun; 1653 u32 tx_pwr_perpkt; 1654 u32 rx_gain_perpkt; 1655 }; 1656 1657 struct rtw89_btc_wl_nhm { 1658 u8 instant_wl_nhm_dbm; 1659 u8 instant_wl_nhm_per_mhz; 1660 u16 valid_record_times; 1661 s8 record_pwr[16]; 1662 u8 record_ratio[16]; 1663 s8 pwr; /* dbm_per_MHz */ 1664 u8 ratio; 1665 u8 current_status; 1666 u8 refresh; 1667 bool start_flag; 1668 s8 pwr_max; 1669 s8 pwr_min; 1670 }; 1671 1672 struct rtw89_btc_wl_info { 1673 struct rtw89_btc_wl_link_info link_info[RTW89_PORT_NUM]; 1674 struct rtw89_btc_wl_rfk_info rfk_info; 1675 struct rtw89_btc_wl_ver_info ver_info; 1676 struct rtw89_btc_wl_afh_info afh_info; 1677 struct rtw89_btc_wl_role_info role_info; 1678 struct rtw89_btc_wl_role_info_v1 role_info_v1; 1679 struct rtw89_btc_wl_role_info_v2 role_info_v2; 1680 struct rtw89_btc_wl_scan_info scan_info; 1681 struct rtw89_btc_wl_dbcc_info dbcc_info; 1682 struct rtw89_btc_rf_para rf_para; 1683 struct rtw89_btc_wl_nhm nhm; 1684 union rtw89_btc_wl_state_map status; 1685 1686 u8 port_id[RTW89_WIFI_ROLE_MLME_MAX]; 1687 u8 rssi_level; 1688 u8 cn_report; 1689 1690 bool scbd_change; 1691 u32 scbd; 1692 }; 1693 1694 struct rtw89_btc_module { 1695 struct rtw89_btc_ant_info ant; 1696 u8 rfe_type; 1697 u8 cv; 1698 1699 u8 bt_solo: 1; 1700 u8 bt_pos: 1; 1701 u8 switch_type: 1; 1702 u8 wa_type: 3; 1703 1704 u8 kt_ver_adie; 1705 }; 1706 1707 #define RTW89_BTC_DM_MAXSTEP 30 1708 #define RTW89_BTC_DM_CNT_MAX (RTW89_BTC_DM_MAXSTEP * 8) 1709 1710 struct rtw89_btc_dm_step { 1711 u16 step[RTW89_BTC_DM_MAXSTEP]; 1712 u8 step_pos; 1713 bool step_ov; 1714 }; 1715 1716 struct rtw89_btc_init_info { 1717 struct rtw89_btc_module module; 1718 u8 wl_guard_ch; 1719 1720 u8 wl_only: 1; 1721 u8 wl_init_ok: 1; 1722 u8 dbcc_en: 1; 1723 u8 cx_other: 1; 1724 u8 bt_only: 1; 1725 1726 u16 rsvd; 1727 }; 1728 1729 struct rtw89_btc_wl_tx_limit_para { 1730 u16 enable; 1731 u32 tx_time; /* unit: us */ 1732 u16 tx_retry; 1733 }; 1734 1735 enum rtw89_btc_bt_scan_type { 1736 BTC_SCAN_INQ = 0, 1737 BTC_SCAN_PAGE, 1738 BTC_SCAN_BLE, 1739 BTC_SCAN_INIT, 1740 BTC_SCAN_TV, 1741 BTC_SCAN_ADV, 1742 BTC_SCAN_MAX1, 1743 }; 1744 1745 enum rtw89_btc_ble_scan_type { 1746 CXSCAN_BG = 0, 1747 CXSCAN_INIT, 1748 CXSCAN_LE, 1749 CXSCAN_MAX 1750 }; 1751 1752 #define RTW89_BTC_BTC_SCAN_V1_FLAG_ENABLE BIT(0) 1753 #define RTW89_BTC_BTC_SCAN_V1_FLAG_INTERLACE BIT(1) 1754 1755 struct rtw89_btc_bt_scan_info_v1 { 1756 __le16 win; 1757 __le16 intvl; 1758 __le32 flags; 1759 } __packed; 1760 1761 struct rtw89_btc_bt_scan_info_v2 { 1762 __le16 win; 1763 __le16 intvl; 1764 } __packed; 1765 1766 struct rtw89_btc_fbtc_btscan_v1 { 1767 u8 fver; /* btc_ver::fcxbtscan */ 1768 u8 rsvd; 1769 __le16 rsvd2; 1770 struct rtw89_btc_bt_scan_info_v1 scan[BTC_SCAN_MAX1]; 1771 } __packed; 1772 1773 struct rtw89_btc_fbtc_btscan_v2 { 1774 u8 fver; /* btc_ver::fcxbtscan */ 1775 u8 type; 1776 __le16 rsvd2; 1777 struct rtw89_btc_bt_scan_info_v2 para[CXSCAN_MAX]; 1778 } __packed; 1779 1780 union rtw89_btc_fbtc_btscan { 1781 struct rtw89_btc_fbtc_btscan_v1 v1; 1782 struct rtw89_btc_fbtc_btscan_v2 v2; 1783 }; 1784 1785 struct rtw89_btc_bt_info { 1786 struct rtw89_btc_bt_link_info link_info; 1787 struct rtw89_btc_bt_scan_info_v1 scan_info_v1[BTC_SCAN_MAX1]; 1788 struct rtw89_btc_bt_scan_info_v2 scan_info_v2[CXSCAN_MAX]; 1789 struct rtw89_btc_bt_ver_info ver_info; 1790 struct rtw89_btc_bool_sta_chg enable; 1791 struct rtw89_btc_bool_sta_chg inq_pag; 1792 struct rtw89_btc_rf_para rf_para; 1793 union rtw89_btc_bt_rfk_info_map rfk_info; 1794 1795 u8 raw_info[BTC_BTINFO_MAX]; /* raw bt info from mailbox */ 1796 1797 u32 scbd; 1798 u32 feature; 1799 1800 u32 mbx_avl: 1; 1801 u32 whql_test: 1; 1802 u32 igno_wl: 1; 1803 u32 reinit: 1; 1804 u32 ble_scan_en: 1; 1805 u32 btg_type: 1; 1806 u32 inq: 1; 1807 u32 pag: 1; 1808 u32 run_patch_code: 1; 1809 u32 hi_lna_rx: 1; 1810 u32 scan_rx_low_pri: 1; 1811 u32 scan_info_update: 1; 1812 u32 rsvd: 20; 1813 }; 1814 1815 struct rtw89_btc_cx { 1816 struct rtw89_btc_wl_info wl; 1817 struct rtw89_btc_bt_info bt; 1818 struct rtw89_btc_3rdcx_info other; 1819 u32 state_map; 1820 u32 cnt_bt[BTC_BCNT_NUM]; 1821 u32 cnt_wl[BTC_WCNT_NUM]; 1822 }; 1823 1824 struct rtw89_btc_fbtc_tdma { 1825 u8 type; /* btc_ver::fcxtdma */ 1826 u8 rxflctrl; 1827 u8 txpause; 1828 u8 wtgle_n; 1829 u8 leak_n; 1830 u8 ext_ctrl; 1831 u8 rxflctrl_role; 1832 u8 option_ctrl; 1833 } __packed; 1834 1835 struct rtw89_btc_fbtc_tdma_v3 { 1836 u8 fver; /* btc_ver::fcxtdma */ 1837 u8 rsvd; 1838 __le16 rsvd1; 1839 struct rtw89_btc_fbtc_tdma tdma; 1840 } __packed; 1841 1842 union rtw89_btc_fbtc_tdma_le32 { 1843 struct rtw89_btc_fbtc_tdma v1; 1844 struct rtw89_btc_fbtc_tdma_v3 v3; 1845 }; 1846 1847 #define CXMREG_MAX 30 1848 #define CXMREG_MAX_V2 20 1849 #define FCXMAX_STEP 255 /*STEP trace record cnt, Max:65535, default:255*/ 1850 #define BTC_CYCLE_SLOT_MAX 48 /* must be even number, non-zero */ 1851 1852 enum rtw89_btc_bt_sta_counter { 1853 BTC_BCNT_RFK_REQ = 0, 1854 BTC_BCNT_RFK_GO = 1, 1855 BTC_BCNT_RFK_REJECT = 2, 1856 BTC_BCNT_RFK_FAIL = 3, 1857 BTC_BCNT_RFK_TIMEOUT = 4, 1858 BTC_BCNT_HI_TX = 5, 1859 BTC_BCNT_HI_RX = 6, 1860 BTC_BCNT_LO_TX = 7, 1861 BTC_BCNT_LO_RX = 8, 1862 BTC_BCNT_POLLUTED = 9, 1863 BTC_BCNT_STA_MAX 1864 }; 1865 1866 enum rtw89_btc_bt_sta_counter_v105 { 1867 BTC_BCNT_RFK_REQ_V105 = 0, 1868 BTC_BCNT_HI_TX_V105 = 1, 1869 BTC_BCNT_HI_RX_V105 = 2, 1870 BTC_BCNT_LO_TX_V105 = 3, 1871 BTC_BCNT_LO_RX_V105 = 4, 1872 BTC_BCNT_POLLUTED_V105 = 5, 1873 BTC_BCNT_STA_MAX_V105 1874 }; 1875 1876 struct rtw89_btc_fbtc_rpt_ctrl_v1 { 1877 u16 fver; /* btc_ver::fcxbtcrpt */ 1878 u16 rpt_cnt; /* tmr counters */ 1879 u32 wl_fw_coex_ver; /* match which driver's coex version */ 1880 u32 wl_fw_cx_offload; 1881 u32 wl_fw_ver; 1882 u32 rpt_enable; 1883 u32 rpt_para; /* ms */ 1884 u32 mb_send_fail_cnt; /* fw send mailbox fail counter */ 1885 u32 mb_send_ok_cnt; /* fw send mailbox ok counter */ 1886 u32 mb_recv_cnt; /* fw recv mailbox counter */ 1887 u32 mb_a2dp_empty_cnt; /* a2dp empty count */ 1888 u32 mb_a2dp_flct_cnt; /* a2dp empty flow control counter */ 1889 u32 mb_a2dp_full_cnt; /* a2dp empty full counter */ 1890 u32 bt_rfk_cnt[BTC_BCNT_HI_TX]; 1891 u32 c2h_cnt; /* fw send c2h counter */ 1892 u32 h2c_cnt; /* fw recv h2c counter */ 1893 } __packed; 1894 1895 struct rtw89_btc_fbtc_rpt_ctrl_info { 1896 __le32 cnt; /* fw report counter */ 1897 __le32 en; /* report map */ 1898 __le32 para; /* not used */ 1899 1900 __le32 cnt_c2h; /* fw send c2h counter */ 1901 __le32 cnt_h2c; /* fw recv h2c counter */ 1902 __le32 len_c2h; /* The total length of the last C2H */ 1903 1904 __le32 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1905 __le32 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1906 } __packed; 1907 1908 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 { 1909 __le32 cx_ver; /* match which driver's coex version */ 1910 __le32 fw_ver; 1911 __le32 en; /* report map */ 1912 1913 __le16 cnt; /* fw report counter */ 1914 __le16 cnt_c2h; /* fw send c2h counter */ 1915 __le16 cnt_h2c; /* fw recv h2c counter */ 1916 __le16 len_c2h; /* The total length of the last C2H */ 1917 1918 __le16 cnt_aoac_rf_on; /* rf-on counter for aoac switch notify */ 1919 __le16 cnt_aoac_rf_off; /* rf-off counter for aoac switch notify */ 1920 } __packed; 1921 1922 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info { 1923 __le32 cx_ver; /* match which driver's coex version */ 1924 __le32 cx_offload; 1925 __le32 fw_ver; 1926 } __packed; 1927 1928 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty { 1929 __le32 cnt_empty; /* a2dp empty count */ 1930 __le32 cnt_flowctrl; /* a2dp empty flow control counter */ 1931 __le32 cnt_tx; 1932 __le32 cnt_ack; 1933 __le32 cnt_nack; 1934 } __packed; 1935 1936 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox { 1937 __le32 cnt_send_ok; /* fw send mailbox ok counter */ 1938 __le32 cnt_send_fail; /* fw send mailbox fail counter */ 1939 __le32 cnt_recv; /* fw recv mailbox counter */ 1940 struct rtw89_btc_fbtc_rpt_ctrl_a2dp_empty a2dp; 1941 } __packed; 1942 1943 struct rtw89_btc_fbtc_rpt_ctrl_v4 { 1944 u8 fver; 1945 u8 rsvd; 1946 __le16 rsvd1; 1947 struct rtw89_btc_fbtc_rpt_ctrl_info rpt_info; 1948 struct rtw89_btc_fbtc_rpt_ctrl_wl_fw_info wl_fw_info; 1949 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1950 __le32 bt_cnt[BTC_BCNT_STA_MAX]; 1951 struct rtw89_mac_ax_gnt gnt_val[RTW89_PHY_MAX]; 1952 } __packed; 1953 1954 struct rtw89_btc_fbtc_rpt_ctrl_v5 { 1955 u8 fver; 1956 u8 rsvd; 1957 __le16 rsvd1; 1958 1959 u8 gnt_val[RTW89_PHY_MAX][4]; 1960 __le16 bt_cnt[BTC_BCNT_STA_MAX]; 1961 1962 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1963 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1964 } __packed; 1965 1966 struct rtw89_btc_fbtc_rpt_ctrl_v105 { 1967 u8 fver; 1968 u8 rsvd; 1969 __le16 rsvd1; 1970 1971 u8 gnt_val[RTW89_PHY_MAX][4]; 1972 __le16 bt_cnt[BTC_BCNT_STA_MAX_V105]; 1973 1974 struct rtw89_btc_fbtc_rpt_ctrl_info_v5 rpt_info; 1975 struct rtw89_btc_fbtc_rpt_ctrl_bt_mailbox bt_mbx_info; 1976 } __packed; 1977 1978 union rtw89_btc_fbtc_rpt_ctrl_ver_info { 1979 struct rtw89_btc_fbtc_rpt_ctrl_v1 v1; 1980 struct rtw89_btc_fbtc_rpt_ctrl_v4 v4; 1981 struct rtw89_btc_fbtc_rpt_ctrl_v5 v5; 1982 struct rtw89_btc_fbtc_rpt_ctrl_v105 v105; 1983 }; 1984 1985 enum rtw89_fbtc_ext_ctrl_type { 1986 CXECTL_OFF = 0x0, /* tdma off */ 1987 CXECTL_B2 = 0x1, /* allow B2 (beacon-early) */ 1988 CXECTL_EXT = 0x2, 1989 CXECTL_MAX 1990 }; 1991 1992 union rtw89_btc_fbtc_rxflct { 1993 u8 val; 1994 u8 type: 3; 1995 u8 tgln_n: 5; 1996 }; 1997 1998 enum rtw89_btc_cxst_state { 1999 CXST_OFF = 0x0, 2000 CXST_B2W = 0x1, 2001 CXST_W1 = 0x2, 2002 CXST_W2 = 0x3, 2003 CXST_W2B = 0x4, 2004 CXST_B1 = 0x5, 2005 CXST_B2 = 0x6, 2006 CXST_B3 = 0x7, 2007 CXST_B4 = 0x8, 2008 CXST_LK = 0x9, 2009 CXST_BLK = 0xa, 2010 CXST_E2G = 0xb, 2011 CXST_E5G = 0xc, 2012 CXST_EBT = 0xd, 2013 CXST_ENULL = 0xe, 2014 CXST_WLK = 0xf, 2015 CXST_W1FDD = 0x10, 2016 CXST_B1FDD = 0x11, 2017 CXST_MAX = 0x12, 2018 }; 2019 2020 enum rtw89_btc_cxevnt { 2021 CXEVNT_TDMA_ENTRY = 0x0, 2022 CXEVNT_WL_TMR, 2023 CXEVNT_B1_TMR, 2024 CXEVNT_B2_TMR, 2025 CXEVNT_B3_TMR, 2026 CXEVNT_B4_TMR, 2027 CXEVNT_W2B_TMR, 2028 CXEVNT_B2W_TMR, 2029 CXEVNT_BCN_EARLY, 2030 CXEVNT_A2DP_EMPTY, 2031 CXEVNT_LK_END, 2032 CXEVNT_RX_ISR, 2033 CXEVNT_RX_FC0, 2034 CXEVNT_RX_FC1, 2035 CXEVNT_BT_RELINK, 2036 CXEVNT_BT_RETRY, 2037 CXEVNT_E2G, 2038 CXEVNT_E5G, 2039 CXEVNT_EBT, 2040 CXEVNT_ENULL, 2041 CXEVNT_DRV_WLK, 2042 CXEVNT_BCN_OK, 2043 CXEVNT_BT_CHANGE, 2044 CXEVNT_EBT_EXTEND, 2045 CXEVNT_E2G_NULL1, 2046 CXEVNT_B1FDD_TMR, 2047 CXEVNT_MAX 2048 }; 2049 2050 enum { 2051 CXBCN_ALL = 0x0, 2052 CXBCN_ALL_OK, 2053 CXBCN_BT_SLOT, 2054 CXBCN_BT_OK, 2055 CXBCN_MAX 2056 }; 2057 2058 enum btc_slot_type { 2059 SLOT_MIX = 0x0, /* accept BT Lower-Pri Tx/Rx request 0x778 = 1 */ 2060 SLOT_ISO = 0x1, /* no accept BT Lower-Pri Tx/Rx request 0x778 = d*/ 2061 CXSTYPE_NUM, 2062 }; 2063 2064 enum { /* TIME */ 2065 CXT_BT = 0x0, 2066 CXT_WL = 0x1, 2067 CXT_MAX 2068 }; 2069 2070 enum { /* TIME-A2DP */ 2071 CXT_FLCTRL_OFF = 0x0, 2072 CXT_FLCTRL_ON = 0x1, 2073 CXT_FLCTRL_MAX 2074 }; 2075 2076 enum { /* STEP TYPE */ 2077 CXSTEP_NONE = 0x0, 2078 CXSTEP_EVNT = 0x1, 2079 CXSTEP_SLOT = 0x2, 2080 CXSTEP_MAX, 2081 }; 2082 2083 enum rtw89_btc_afh_map_type { /*AFH MAP TYPE */ 2084 RPT_BT_AFH_SEQ_LEGACY = 0x10, 2085 RPT_BT_AFH_SEQ_LE = 0x20 2086 }; 2087 2088 #define BTC_DBG_MAX1 32 2089 struct rtw89_btc_fbtc_gpio_dbg { 2090 u8 fver; /* btc_ver::fcxgpiodbg */ 2091 u8 rsvd; 2092 u16 rsvd2; 2093 u32 en_map; /* which debug signal (see btc_wl_gpio_debug) is enable */ 2094 u32 pre_state; /* the debug signal is 1 or 0 */ 2095 u8 gpio_map[BTC_DBG_MAX1]; /*the debug signals to GPIO-Position */ 2096 } __packed; 2097 2098 struct rtw89_btc_fbtc_mreg_val_v1 { 2099 u8 fver; /* btc_ver::fcxmreg */ 2100 u8 reg_num; 2101 __le16 rsvd; 2102 __le32 mreg_val[CXMREG_MAX]; 2103 } __packed; 2104 2105 struct rtw89_btc_fbtc_mreg_val_v2 { 2106 u8 fver; /* btc_ver::fcxmreg */ 2107 u8 reg_num; 2108 __le16 rsvd; 2109 __le32 mreg_val[CXMREG_MAX_V2]; 2110 } __packed; 2111 2112 union rtw89_btc_fbtc_mreg_val { 2113 struct rtw89_btc_fbtc_mreg_val_v1 v1; 2114 struct rtw89_btc_fbtc_mreg_val_v2 v2; 2115 }; 2116 2117 #define RTW89_DEF_FBTC_MREG(__type, __bytes, __offset) \ 2118 { .type = cpu_to_le16(__type), .bytes = cpu_to_le16(__bytes), \ 2119 .offset = cpu_to_le32(__offset), } 2120 2121 struct rtw89_btc_fbtc_mreg { 2122 __le16 type; 2123 __le16 bytes; 2124 __le32 offset; 2125 } __packed; 2126 2127 struct rtw89_btc_fbtc_slot { 2128 __le16 dur; 2129 __le32 cxtbl; 2130 __le16 cxtype; 2131 } __packed; 2132 2133 struct rtw89_btc_fbtc_slots { 2134 u8 fver; /* btc_ver::fcxslots */ 2135 u8 tbl_num; 2136 __le16 rsvd; 2137 __le32 update_map; 2138 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2139 } __packed; 2140 2141 struct rtw89_btc_fbtc_step { 2142 u8 type; 2143 u8 val; 2144 __le16 difft; 2145 } __packed; 2146 2147 struct rtw89_btc_fbtc_steps_v2 { 2148 u8 fver; /* btc_ver::fcxstep */ 2149 u8 rsvd; 2150 __le16 cnt; 2151 __le16 pos_old; 2152 __le16 pos_new; 2153 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2154 } __packed; 2155 2156 struct rtw89_btc_fbtc_steps_v3 { 2157 u8 fver; 2158 u8 en; 2159 __le16 rsvd; 2160 __le32 cnt; 2161 struct rtw89_btc_fbtc_step step[FCXMAX_STEP]; 2162 } __packed; 2163 2164 union rtw89_btc_fbtc_steps_info { 2165 struct rtw89_btc_fbtc_steps_v2 v2; 2166 struct rtw89_btc_fbtc_steps_v3 v3; 2167 }; 2168 2169 struct rtw89_btc_fbtc_cysta_v2 { /* statistics for cycles */ 2170 u8 fver; /* btc_ver::fcxcysta */ 2171 u8 rsvd; 2172 __le16 cycles; /* total cycle number */ 2173 __le16 cycles_a2dp[CXT_FLCTRL_MAX]; 2174 __le16 a2dpept; /* a2dp empty cnt */ 2175 __le16 a2dpeptto; /* a2dp empty timeout cnt*/ 2176 __le16 tavg_cycle[CXT_MAX]; /* avg wl/bt cycle time */ 2177 __le16 tmax_cycle[CXT_MAX]; /* max wl/bt cycle time */ 2178 __le16 tmaxdiff_cycle[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2179 __le16 tavg_a2dp[CXT_FLCTRL_MAX]; /* avg a2dp PSTDMA/TDMA time */ 2180 __le16 tmax_a2dp[CXT_FLCTRL_MAX]; /* max a2dp PSTDMA/TDMA time */ 2181 __le16 tavg_a2dpept; /* avg a2dp empty time */ 2182 __le16 tmax_a2dpept; /* max a2dp empty time */ 2183 __le16 tavg_lk; /* avg leak-slot time */ 2184 __le16 tmax_lk; /* max leak-slot time */ 2185 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2186 __le32 bcn_cnt[CXBCN_MAX]; 2187 __le32 leakrx_cnt; /* the rximr occur at leak slot */ 2188 __le32 collision_cnt; /* counter for event/timer occur at same time */ 2189 __le32 skip_cnt; 2190 __le32 exception; 2191 __le32 except_cnt; 2192 __le16 tslot_cycle[BTC_CYCLE_SLOT_MAX]; 2193 } __packed; 2194 2195 struct rtw89_btc_fbtc_fdd_try_info { 2196 __le16 cycles[CXT_FLCTRL_MAX]; 2197 __le16 tavg[CXT_FLCTRL_MAX]; /* avg try BT-Slot-TDD/BT-slot-FDD time */ 2198 __le16 tmax[CXT_FLCTRL_MAX]; /* max try BT-Slot-TDD/BT-slot-FDD time */ 2199 } __packed; 2200 2201 struct rtw89_btc_fbtc_cycle_time_info { 2202 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2203 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2204 __le16 tmaxdiff[CXT_MAX]; /* max wl-wl bt-bt cycle diff time */ 2205 } __packed; 2206 2207 struct rtw89_btc_fbtc_cycle_time_info_v5 { 2208 __le16 tavg[CXT_MAX]; /* avg wl/bt cycle time */ 2209 __le16 tmax[CXT_MAX]; /* max wl/bt cycle time */ 2210 } __packed; 2211 2212 struct rtw89_btc_fbtc_a2dp_trx_stat { 2213 u8 empty_cnt; 2214 u8 retry_cnt; 2215 u8 tx_rate; 2216 u8 tx_cnt; 2217 u8 ack_cnt; 2218 u8 nack_cnt; 2219 u8 rsvd1; 2220 u8 rsvd2; 2221 } __packed; 2222 2223 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 { 2224 u8 empty_cnt; 2225 u8 retry_cnt; 2226 u8 tx_rate; 2227 u8 tx_cnt; 2228 u8 ack_cnt; 2229 u8 nack_cnt; 2230 u8 no_empty_cnt; 2231 u8 rsvd; 2232 } __packed; 2233 2234 struct rtw89_btc_fbtc_cycle_a2dp_empty_info { 2235 __le16 cnt; /* a2dp empty cnt */ 2236 __le16 cnt_timeout; /* a2dp empty timeout cnt*/ 2237 __le16 tavg; /* avg a2dp empty time */ 2238 __le16 tmax; /* max a2dp empty time */ 2239 } __packed; 2240 2241 struct rtw89_btc_fbtc_cycle_leak_info { 2242 __le32 cnt_rximr; /* the rximr occur at leak slot */ 2243 __le16 tavg; /* avg leak-slot time */ 2244 __le16 tmax; /* max leak-slot time */ 2245 } __packed; 2246 2247 #define RTW89_BTC_FDDT_PHASE_CYCLE GENMASK(9, 0) 2248 #define RTW89_BTC_FDDT_TRAIN_STEP GENMASK(15, 10) 2249 2250 struct rtw89_btc_fbtc_cycle_fddt_info { 2251 __le16 train_cycle; 2252 __le16 tp; 2253 2254 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2255 s8 bt_tx_power; /* decrease Tx power (dB) */ 2256 s8 bt_rx_gain; /* LNA constrain level */ 2257 u8 no_empty_cnt; 2258 2259 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2260 u8 cn; /* condition_num */ 2261 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2262 u8 train_result; /* refer to enum btc_fddt_check_map */ 2263 } __packed; 2264 2265 #define RTW89_BTC_FDDT_CELL_TRAIN_STATE GENMASK(3, 0) 2266 #define RTW89_BTC_FDDT_CELL_TRAIN_PHASE GENMASK(7, 4) 2267 2268 struct rtw89_btc_fbtc_cycle_fddt_info_v5 { 2269 __le16 train_cycle; 2270 __le16 tp; 2271 2272 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2273 s8 bt_tx_power; /* decrease Tx power (dB) */ 2274 s8 bt_rx_gain; /* LNA constrain level */ 2275 u8 no_empty_cnt; 2276 2277 u8 rssi; /* [7:4] -> bt_rssi_level, [3:0]-> wl_rssi_level */ 2278 u8 cn; /* condition_num */ 2279 u8 train_status; /* [7:4]-> train-state, [3:0]-> train-phase */ 2280 u8 train_result; /* refer to enum btc_fddt_check_map */ 2281 } __packed; 2282 2283 struct rtw89_btc_fbtc_fddt_cell_status { 2284 s8 wl_tx_pwr; 2285 s8 bt_tx_pwr; 2286 s8 bt_rx_gain; 2287 u8 state_phase; /* [0:3] train state, [4:7] train phase */ 2288 } __packed; 2289 2290 struct rtw89_btc_fbtc_fddt_cell_status_v5 { 2291 s8 wl_tx_pwr; 2292 s8 bt_tx_pwr; 2293 s8 bt_rx_gain; 2294 } __packed; 2295 2296 struct rtw89_btc_fbtc_cysta_v3 { /* statistics for cycles */ 2297 u8 fver; 2298 u8 rsvd; 2299 __le16 cycles; /* total cycle number */ 2300 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; 2301 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2302 struct rtw89_btc_fbtc_fdd_try_info fdd_try; 2303 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2304 struct rtw89_btc_fbtc_a2dp_trx_stat a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2305 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2306 __le32 slot_cnt[CXST_MAX]; /* slot count */ 2307 __le32 bcn_cnt[CXBCN_MAX]; 2308 __le32 collision_cnt; /* counter for event/timer occur at the same time */ 2309 __le32 skip_cnt; 2310 __le32 except_cnt; 2311 __le32 except_map; 2312 } __packed; 2313 2314 #define FDD_TRAIN_WL_DIRECTION 2 2315 #define FDD_TRAIN_WL_RSSI_LEVEL 5 2316 #define FDD_TRAIN_BT_RSSI_LEVEL 5 2317 2318 struct rtw89_btc_fbtc_cysta_v4 { /* statistics for cycles */ 2319 u8 fver; 2320 u8 rsvd; 2321 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2322 u8 except_cnt; 2323 2324 __le16 skip_cnt; 2325 __le16 cycles; /* total cycle number */ 2326 2327 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2328 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2329 __le16 bcn_cnt[CXBCN_MAX]; 2330 struct rtw89_btc_fbtc_cycle_time_info cycle_time; 2331 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2332 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2333 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2334 struct rtw89_btc_fbtc_cycle_fddt_info fddt_trx[BTC_CYCLE_SLOT_MAX]; 2335 struct rtw89_btc_fbtc_fddt_cell_status fddt_cells[FDD_TRAIN_WL_DIRECTION] 2336 [FDD_TRAIN_WL_RSSI_LEVEL] 2337 [FDD_TRAIN_BT_RSSI_LEVEL]; 2338 __le32 except_map; 2339 } __packed; 2340 2341 struct rtw89_btc_fbtc_cysta_v5 { /* statistics for cycles */ 2342 u8 fver; 2343 u8 rsvd; 2344 u8 collision_cnt; /* counter for event/timer occur at the same time */ 2345 u8 except_cnt; 2346 u8 wl_rx_err_ratio[BTC_CYCLE_SLOT_MAX]; 2347 2348 __le16 skip_cnt; 2349 __le16 cycles; /* total cycle number */ 2350 2351 __le16 slot_step_time[BTC_CYCLE_SLOT_MAX]; /* record the wl/bt slot time */ 2352 __le16 slot_cnt[CXST_MAX]; /* slot count */ 2353 __le16 bcn_cnt[CXBCN_MAX]; 2354 struct rtw89_btc_fbtc_cycle_time_info_v5 cycle_time; 2355 struct rtw89_btc_fbtc_cycle_leak_info leak_slot; 2356 struct rtw89_btc_fbtc_cycle_a2dp_empty_info a2dp_ept; 2357 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 a2dp_trx[BTC_CYCLE_SLOT_MAX]; 2358 struct rtw89_btc_fbtc_cycle_fddt_info_v5 fddt_trx[BTC_CYCLE_SLOT_MAX]; 2359 struct rtw89_btc_fbtc_fddt_cell_status_v5 fddt_cells[FDD_TRAIN_WL_DIRECTION] 2360 [FDD_TRAIN_WL_RSSI_LEVEL] 2361 [FDD_TRAIN_BT_RSSI_LEVEL]; 2362 __le32 except_map; 2363 } __packed; 2364 2365 union rtw89_btc_fbtc_cysta_info { 2366 struct rtw89_btc_fbtc_cysta_v2 v2; 2367 struct rtw89_btc_fbtc_cysta_v3 v3; 2368 struct rtw89_btc_fbtc_cysta_v4 v4; 2369 struct rtw89_btc_fbtc_cysta_v5 v5; 2370 }; 2371 2372 struct rtw89_btc_fbtc_cynullsta_v1 { /* cycle null statistics */ 2373 u8 fver; /* btc_ver::fcxnullsta */ 2374 u8 rsvd; 2375 __le16 rsvd2; 2376 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2377 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2378 __le32 result[2][4]; /* 0:fail, 1:ok, 2:on_time, 3:retry */ 2379 } __packed; 2380 2381 struct rtw89_btc_fbtc_cynullsta_v2 { /* cycle null statistics */ 2382 u8 fver; /* btc_ver::fcxnullsta */ 2383 u8 rsvd; 2384 __le16 rsvd2; 2385 __le32 max_t[2]; /* max_t for 0:null0/1:null1 */ 2386 __le32 avg_t[2]; /* avg_t for 0:null0/1:null1 */ 2387 __le32 result[2][5]; /* 0:fail, 1:ok, 2:on_time, 3:retry, 4:tx */ 2388 } __packed; 2389 2390 union rtw89_btc_fbtc_cynullsta_info { 2391 struct rtw89_btc_fbtc_cynullsta_v1 v1; /* info from fw */ 2392 struct rtw89_btc_fbtc_cynullsta_v2 v2; 2393 }; 2394 2395 struct rtw89_btc_fbtc_btver { 2396 u8 fver; /* btc_ver::fcxbtver */ 2397 u8 rsvd; 2398 __le16 rsvd2; 2399 __le32 coex_ver; /*bit[15:8]->shared, bit[7:0]->non-shared */ 2400 __le32 fw_ver; 2401 __le32 feature; 2402 } __packed; 2403 2404 struct rtw89_btc_fbtc_btafh { 2405 u8 fver; /* btc_ver::fcxbtafh */ 2406 u8 rsvd; 2407 __le16 rsvd2; 2408 u8 afh_l[4]; /*bit0:2402, bit1: 2403.... bit31:2433 */ 2409 u8 afh_m[4]; /*bit0:2434, bit1: 2435.... bit31:2465 */ 2410 u8 afh_h[4]; /*bit0:2466, bit1:2467......bit14:2480 */ 2411 } __packed; 2412 2413 struct rtw89_btc_fbtc_btafh_v2 { 2414 u8 fver; /* btc_ver::fcxbtafh */ 2415 u8 rsvd; 2416 u8 rsvd2; 2417 u8 map_type; 2418 u8 afh_l[4]; 2419 u8 afh_m[4]; 2420 u8 afh_h[4]; 2421 u8 afh_le_a[4]; 2422 u8 afh_le_b[4]; 2423 } __packed; 2424 2425 struct rtw89_btc_fbtc_btdevinfo { 2426 u8 fver; /* btc_ver::fcxbtdevinfo */ 2427 u8 rsvd; 2428 __le16 vendor_id; 2429 __le32 dev_name; /* only 24 bits valid */ 2430 __le32 flush_time; 2431 } __packed; 2432 2433 #define RTW89_BTC_WL_DEF_TX_PWR GENMASK(7, 0) 2434 struct rtw89_btc_rf_trx_para { 2435 u32 wl_tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2436 u32 wl_rx_gain; /* rx gain table index (TBD.) */ 2437 u8 bt_tx_power; /* decrease Tx power (dB) */ 2438 u8 bt_rx_gain; /* LNA constrain level */ 2439 }; 2440 2441 struct rtw89_btc_trx_info { 2442 u8 tx_lvl; 2443 u8 rx_lvl; 2444 u8 wl_rssi; 2445 u8 bt_rssi; 2446 2447 s8 tx_power; /* absolute Tx power (dBm), 0xff-> no BTC control */ 2448 s8 rx_gain; /* rx gain table index (TBD.) */ 2449 s8 bt_tx_power; /* decrease Tx power (dB) */ 2450 s8 bt_rx_gain; /* LNA constrain level */ 2451 2452 u8 cn; /* condition_num */ 2453 s8 nhm; 2454 u8 bt_profile; 2455 u8 rsvd2; 2456 2457 u16 tx_rate; 2458 u16 rx_rate; 2459 2460 u32 tx_tp; 2461 u32 rx_tp; 2462 u32 rx_err_ratio; 2463 }; 2464 2465 struct rtw89_btc_dm { 2466 struct rtw89_btc_fbtc_slot slot[CXST_MAX]; 2467 struct rtw89_btc_fbtc_slot slot_now[CXST_MAX]; 2468 struct rtw89_btc_fbtc_tdma tdma; 2469 struct rtw89_btc_fbtc_tdma tdma_now; 2470 struct rtw89_mac_ax_coex_gnt gnt; 2471 struct rtw89_btc_init_info init_info; /* pass to wl_fw if offload */ 2472 struct rtw89_btc_rf_trx_para rf_trx_para; 2473 struct rtw89_btc_wl_tx_limit_para wl_tx_limit; 2474 struct rtw89_btc_dm_step dm_step; 2475 struct rtw89_btc_wl_scc_ctrl wl_scc; 2476 struct rtw89_btc_trx_info trx_info; 2477 union rtw89_btc_dm_error_map error; 2478 u32 cnt_dm[BTC_DCNT_NUM]; 2479 u32 cnt_notify[BTC_NCNT_NUM]; 2480 2481 u32 update_slot_map; 2482 u32 set_ant_path; 2483 2484 u32 wl_only: 1; 2485 u32 wl_fw_cx_offload: 1; 2486 u32 freerun: 1; 2487 u32 fddt_train: 1; 2488 u32 wl_ps_ctrl: 2; 2489 u32 wl_mimo_ps: 1; 2490 u32 leak_ap: 1; 2491 u32 noisy_level: 3; 2492 u32 coex_info_map: 8; 2493 u32 bt_only: 1; 2494 u32 wl_btg_rx: 1; 2495 u32 trx_para_level: 8; 2496 u32 wl_stb_chg: 1; 2497 u32 pta_owner: 1; 2498 u32 tdma_instant_excute: 1; 2499 2500 u16 slot_dur[CXST_MAX]; 2501 2502 u8 run_reason; 2503 u8 run_action; 2504 2505 u8 wl_lna2: 1; 2506 }; 2507 2508 struct rtw89_btc_ctrl { 2509 u32 manual: 1; 2510 u32 igno_bt: 1; 2511 u32 always_freerun: 1; 2512 u32 trace_step: 16; 2513 u32 rsvd: 12; 2514 }; 2515 2516 struct rtw89_btc_dbg { 2517 /* cmd "rb" */ 2518 bool rb_done; 2519 u32 rb_val; 2520 }; 2521 2522 enum rtw89_btc_btf_fw_event { 2523 BTF_EVNT_RPT = 0, 2524 BTF_EVNT_BT_INFO = 1, 2525 BTF_EVNT_BT_SCBD = 2, 2526 BTF_EVNT_BT_REG = 3, 2527 BTF_EVNT_CX_RUNINFO = 4, 2528 BTF_EVNT_BT_PSD = 5, 2529 BTF_EVNT_BUF_OVERFLOW, 2530 BTF_EVNT_C2H_LOOPBACK, 2531 BTF_EVNT_MAX, 2532 }; 2533 2534 enum btf_fw_event_report { 2535 BTC_RPT_TYPE_CTRL = 0x0, 2536 BTC_RPT_TYPE_TDMA, 2537 BTC_RPT_TYPE_SLOT, 2538 BTC_RPT_TYPE_CYSTA, 2539 BTC_RPT_TYPE_STEP, 2540 BTC_RPT_TYPE_NULLSTA, 2541 BTC_RPT_TYPE_MREG, 2542 BTC_RPT_TYPE_GPIO_DBG, 2543 BTC_RPT_TYPE_BT_VER, 2544 BTC_RPT_TYPE_BT_SCAN, 2545 BTC_RPT_TYPE_BT_AFH, 2546 BTC_RPT_TYPE_BT_DEVICE, 2547 BTC_RPT_TYPE_TEST, 2548 BTC_RPT_TYPE_MAX = 31 2549 }; 2550 2551 enum rtw_btc_btf_reg_type { 2552 REG_MAC = 0x0, 2553 REG_BB = 0x1, 2554 REG_RF = 0x2, 2555 REG_BT_RF = 0x3, 2556 REG_BT_MODEM = 0x4, 2557 REG_BT_BLUEWIZE = 0x5, 2558 REG_BT_VENDOR = 0x6, 2559 REG_BT_LE = 0x7, 2560 REG_MAX_TYPE, 2561 }; 2562 2563 struct rtw89_btc_rpt_cmn_info { 2564 u32 rx_cnt; 2565 u32 rx_len; 2566 u32 req_len; /* expected rsp len */ 2567 u8 req_fver; /* expected rsp fver */ 2568 u8 rsp_fver; /* fver from fw */ 2569 u8 valid; 2570 } __packed; 2571 2572 union rtw89_btc_fbtc_btafh_info { 2573 struct rtw89_btc_fbtc_btafh v1; 2574 struct rtw89_btc_fbtc_btafh_v2 v2; 2575 }; 2576 2577 struct rtw89_btc_report_ctrl_state { 2578 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2579 union rtw89_btc_fbtc_rpt_ctrl_ver_info finfo; 2580 }; 2581 2582 struct rtw89_btc_rpt_fbtc_tdma { 2583 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2584 union rtw89_btc_fbtc_tdma_le32 finfo; 2585 }; 2586 2587 struct rtw89_btc_rpt_fbtc_slots { 2588 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2589 struct rtw89_btc_fbtc_slots finfo; /* info from fw */ 2590 }; 2591 2592 struct rtw89_btc_rpt_fbtc_cysta { 2593 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2594 union rtw89_btc_fbtc_cysta_info finfo; 2595 }; 2596 2597 struct rtw89_btc_rpt_fbtc_step { 2598 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2599 union rtw89_btc_fbtc_steps_info finfo; /* info from fw */ 2600 }; 2601 2602 struct rtw89_btc_rpt_fbtc_nullsta { 2603 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2604 union rtw89_btc_fbtc_cynullsta_info finfo; 2605 }; 2606 2607 struct rtw89_btc_rpt_fbtc_mreg { 2608 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2609 union rtw89_btc_fbtc_mreg_val finfo; /* info from fw */ 2610 }; 2611 2612 struct rtw89_btc_rpt_fbtc_gpio_dbg { 2613 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2614 struct rtw89_btc_fbtc_gpio_dbg finfo; /* info from fw */ 2615 }; 2616 2617 struct rtw89_btc_rpt_fbtc_btver { 2618 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2619 struct rtw89_btc_fbtc_btver finfo; /* info from fw */ 2620 }; 2621 2622 struct rtw89_btc_rpt_fbtc_btscan { 2623 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2624 union rtw89_btc_fbtc_btscan finfo; /* info from fw */ 2625 }; 2626 2627 struct rtw89_btc_rpt_fbtc_btafh { 2628 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2629 union rtw89_btc_fbtc_btafh_info finfo; 2630 }; 2631 2632 struct rtw89_btc_rpt_fbtc_btdev { 2633 struct rtw89_btc_rpt_cmn_info cinfo; /* common info, by driver */ 2634 struct rtw89_btc_fbtc_btdevinfo finfo; /* info from fw */ 2635 }; 2636 2637 enum rtw89_btc_btfre_type { 2638 BTFRE_INVALID_INPUT = 0x0, /* invalid input parameters */ 2639 BTFRE_UNDEF_TYPE, 2640 BTFRE_EXCEPTION, 2641 BTFRE_MAX, 2642 }; 2643 2644 struct rtw89_btc_btf_fwinfo { 2645 u32 cnt_c2h; 2646 u32 cnt_h2c; 2647 u32 cnt_h2c_fail; 2648 u32 event[BTF_EVNT_MAX]; 2649 2650 u32 err[BTFRE_MAX]; 2651 u32 len_mismch; 2652 u32 fver_mismch; 2653 u32 rpt_en_map; 2654 2655 struct rtw89_btc_report_ctrl_state rpt_ctrl; 2656 struct rtw89_btc_rpt_fbtc_tdma rpt_fbtc_tdma; 2657 struct rtw89_btc_rpt_fbtc_slots rpt_fbtc_slots; 2658 struct rtw89_btc_rpt_fbtc_cysta rpt_fbtc_cysta; 2659 struct rtw89_btc_rpt_fbtc_step rpt_fbtc_step; 2660 struct rtw89_btc_rpt_fbtc_nullsta rpt_fbtc_nullsta; 2661 struct rtw89_btc_rpt_fbtc_mreg rpt_fbtc_mregval; 2662 struct rtw89_btc_rpt_fbtc_gpio_dbg rpt_fbtc_gpio_dbg; 2663 struct rtw89_btc_rpt_fbtc_btver rpt_fbtc_btver; 2664 struct rtw89_btc_rpt_fbtc_btscan rpt_fbtc_btscan; 2665 struct rtw89_btc_rpt_fbtc_btafh rpt_fbtc_btafh; 2666 struct rtw89_btc_rpt_fbtc_btdev rpt_fbtc_btdev; 2667 }; 2668 2669 struct rtw89_btc_ver { 2670 enum rtw89_core_chip_id chip_id; 2671 u32 fw_ver_code; 2672 2673 u8 fcxbtcrpt; 2674 u8 fcxtdma; 2675 u8 fcxslots; 2676 u8 fcxcysta; 2677 u8 fcxstep; 2678 u8 fcxnullsta; 2679 u8 fcxmreg; 2680 u8 fcxgpiodbg; 2681 u8 fcxbtver; 2682 u8 fcxbtscan; 2683 u8 fcxbtafh; 2684 u8 fcxbtdevinfo; 2685 u8 fwlrole; 2686 u8 frptmap; 2687 u8 fcxctrl; 2688 2689 u16 info_buf; 2690 u8 max_role_num; 2691 }; 2692 2693 #define RTW89_BTC_POLICY_MAXLEN 512 2694 2695 struct rtw89_btc { 2696 const struct rtw89_btc_ver *ver; 2697 2698 struct rtw89_btc_cx cx; 2699 struct rtw89_btc_dm dm; 2700 struct rtw89_btc_ctrl ctrl; 2701 struct rtw89_btc_module mdinfo; 2702 struct rtw89_btc_btf_fwinfo fwinfo; 2703 struct rtw89_btc_dbg dbg; 2704 2705 struct work_struct eapol_notify_work; 2706 struct work_struct arp_notify_work; 2707 struct work_struct dhcp_notify_work; 2708 struct work_struct icmp_notify_work; 2709 2710 u32 bt_req_len; 2711 2712 u8 policy[RTW89_BTC_POLICY_MAXLEN]; 2713 u16 policy_len; 2714 u16 policy_type; 2715 bool bt_req_en; 2716 bool update_policy_force; 2717 bool lps; 2718 }; 2719 2720 enum rtw89_btc_hmsg { 2721 RTW89_BTC_HMSG_TMR_EN = 0x0, 2722 RTW89_BTC_HMSG_BT_REG_READBACK = 0x1, 2723 RTW89_BTC_HMSG_SET_BT_REQ_SLOT = 0x2, 2724 RTW89_BTC_HMSG_FW_EV = 0x3, 2725 RTW89_BTC_HMSG_BT_LINK_CHG = 0x4, 2726 RTW89_BTC_HMSG_SET_BT_REQ_STBC = 0x5, 2727 2728 NUM_OF_RTW89_BTC_HMSG, 2729 }; 2730 2731 enum rtw89_ra_mode { 2732 RTW89_RA_MODE_CCK = BIT(0), 2733 RTW89_RA_MODE_OFDM = BIT(1), 2734 RTW89_RA_MODE_HT = BIT(2), 2735 RTW89_RA_MODE_VHT = BIT(3), 2736 RTW89_RA_MODE_HE = BIT(4), 2737 }; 2738 2739 enum rtw89_ra_report_mode { 2740 RTW89_RA_RPT_MODE_LEGACY, 2741 RTW89_RA_RPT_MODE_HT, 2742 RTW89_RA_RPT_MODE_VHT, 2743 RTW89_RA_RPT_MODE_HE, 2744 }; 2745 2746 enum rtw89_dig_noisy_level { 2747 RTW89_DIG_NOISY_LEVEL0 = -1, 2748 RTW89_DIG_NOISY_LEVEL1 = 0, 2749 RTW89_DIG_NOISY_LEVEL2 = 1, 2750 RTW89_DIG_NOISY_LEVEL3 = 2, 2751 RTW89_DIG_NOISY_LEVEL_MAX = 3, 2752 }; 2753 2754 enum rtw89_gi_ltf { 2755 RTW89_GILTF_LGI_4XHE32 = 0, 2756 RTW89_GILTF_SGI_4XHE08 = 1, 2757 RTW89_GILTF_2XHE16 = 2, 2758 RTW89_GILTF_2XHE08 = 3, 2759 RTW89_GILTF_1XHE16 = 4, 2760 RTW89_GILTF_1XHE08 = 5, 2761 RTW89_GILTF_MAX 2762 }; 2763 2764 enum rtw89_rx_frame_type { 2765 RTW89_RX_TYPE_MGNT = 0, 2766 RTW89_RX_TYPE_CTRL = 1, 2767 RTW89_RX_TYPE_DATA = 2, 2768 RTW89_RX_TYPE_RSVD = 3, 2769 }; 2770 2771 struct rtw89_ra_info { 2772 u8 is_dis_ra:1; 2773 /* Bit0 : CCK 2774 * Bit1 : OFDM 2775 * Bit2 : HT 2776 * Bit3 : VHT 2777 * Bit4 : HE 2778 * Bit5 : EHT 2779 */ 2780 u8 mode_ctrl:6; 2781 u8 bw_cap:3; /* enum rtw89_bandwidth */ 2782 u8 macid; 2783 u8 dcm_cap:1; 2784 u8 er_cap:1; 2785 u8 init_rate_lv:2; 2786 u8 upd_all:1; 2787 u8 en_sgi:1; 2788 u8 ldpc_cap:1; 2789 u8 stbc_cap:1; 2790 u8 ss_num:3; 2791 u8 giltf:3; 2792 u8 upd_bw_nss_mask:1; 2793 u8 upd_mask:1; 2794 u64 ra_mask; /* 63 bits ra_mask + 1 bit CSI ctrl */ 2795 /* BFee CSI */ 2796 u8 band_num; 2797 u8 ra_csi_rate_en:1; 2798 u8 fixed_csi_rate_en:1; 2799 u8 cr_tbl_sel:1; 2800 u8 fix_giltf_en:1; 2801 u8 fix_giltf:3; 2802 u8 rsvd2:1; 2803 u8 csi_mcs_ss_idx; 2804 u8 csi_mode:2; 2805 u8 csi_gi_ltf:3; 2806 u8 csi_bw:3; 2807 }; 2808 2809 #define RTW89_PPDU_MAX_USR 4 2810 #define RTW89_PPDU_MAC_INFO_USR_SIZE 4 2811 #define RTW89_PPDU_MAC_INFO_SIZE 8 2812 #define RTW89_PPDU_MAC_RX_CNT_SIZE 96 2813 2814 #define RTW89_MAX_RX_AGG_NUM 64 2815 #define RTW89_MAX_TX_AGG_NUM 128 2816 2817 struct rtw89_ampdu_params { 2818 u16 agg_num; 2819 bool amsdu; 2820 }; 2821 2822 struct rtw89_ra_report { 2823 struct rate_info txrate; 2824 u32 bit_rate; 2825 u16 hw_rate; 2826 bool might_fallback_legacy; 2827 }; 2828 2829 DECLARE_EWMA(rssi, 10, 16); 2830 DECLARE_EWMA(evm, 10, 16); 2831 DECLARE_EWMA(snr, 10, 16); 2832 2833 struct rtw89_ba_cam_entry { 2834 struct list_head list; 2835 u8 tid; 2836 }; 2837 2838 #define RTW89_MAX_ADDR_CAM_NUM 128 2839 #define RTW89_MAX_BSSID_CAM_NUM 20 2840 #define RTW89_MAX_SEC_CAM_NUM 128 2841 #define RTW89_MAX_BA_CAM_NUM 8 2842 #define RTW89_SEC_CAM_IN_ADDR_CAM 7 2843 2844 struct rtw89_addr_cam_entry { 2845 u8 addr_cam_idx; 2846 u8 offset; 2847 u8 len; 2848 u8 valid : 1; 2849 u8 addr_mask : 6; 2850 u8 wapi : 1; 2851 u8 mask_sel : 2; 2852 u8 bssid_cam_idx: 6; 2853 2854 u8 sec_ent_mode; 2855 DECLARE_BITMAP(sec_cam_map, RTW89_SEC_CAM_IN_ADDR_CAM); 2856 u8 sec_ent_keyid[RTW89_SEC_CAM_IN_ADDR_CAM]; 2857 u8 sec_ent[RTW89_SEC_CAM_IN_ADDR_CAM]; 2858 struct rtw89_sec_cam_entry *sec_entries[RTW89_SEC_CAM_IN_ADDR_CAM]; 2859 }; 2860 2861 struct rtw89_bssid_cam_entry { 2862 u8 bssid[ETH_ALEN]; 2863 u8 phy_idx; 2864 u8 bssid_cam_idx; 2865 u8 offset; 2866 u8 len; 2867 u8 valid : 1; 2868 u8 num; 2869 }; 2870 2871 struct rtw89_sec_cam_entry { 2872 u8 sec_cam_idx; 2873 u8 offset; 2874 u8 len; 2875 u8 type : 4; 2876 u8 ext_key : 1; 2877 u8 spp_mode : 1; 2878 /* 256 bits */ 2879 u8 key[32]; 2880 }; 2881 2882 struct rtw89_sta { 2883 u8 mac_id; 2884 bool disassoc; 2885 bool er_cap; 2886 struct rtw89_dev *rtwdev; 2887 struct rtw89_vif *rtwvif; 2888 struct rtw89_ra_info ra; 2889 struct rtw89_ra_report ra_report; 2890 int max_agg_wait; 2891 u8 prev_rssi; 2892 struct ewma_rssi avg_rssi; 2893 struct ewma_rssi rssi[RF_PATH_MAX]; 2894 struct ewma_snr avg_snr; 2895 struct ewma_evm evm_min[RF_PATH_MAX]; 2896 struct ewma_evm evm_max[RF_PATH_MAX]; 2897 struct rtw89_ampdu_params ampdu_params[IEEE80211_NUM_TIDS]; 2898 struct ieee80211_rx_status rx_status; 2899 u16 rx_hw_rate; 2900 __le32 htc_template; 2901 struct rtw89_addr_cam_entry addr_cam; /* AP mode or TDLS peer only */ 2902 struct rtw89_bssid_cam_entry bssid_cam; /* TDLS peer only */ 2903 struct list_head ba_cam_list; 2904 struct sk_buff_head roc_queue; 2905 2906 bool use_cfg_mask; 2907 struct cfg80211_bitrate_mask mask; 2908 2909 bool cctl_tx_time; 2910 u32 ampdu_max_time:4; 2911 bool cctl_tx_retry_limit; 2912 u32 data_tx_cnt_lmt:6; 2913 }; 2914 2915 struct rtw89_efuse { 2916 bool valid; 2917 bool power_k_valid; 2918 u8 xtal_cap; 2919 u8 addr[ETH_ALEN]; 2920 u8 rfe_type; 2921 char country_code[2]; 2922 }; 2923 2924 struct rtw89_phy_rate_pattern { 2925 u64 ra_mask; 2926 u16 rate; 2927 u8 ra_mode; 2928 bool enable; 2929 }; 2930 2931 struct rtw89_tx_wait_info { 2932 struct rcu_head rcu_head; 2933 struct completion completion; 2934 bool tx_done; 2935 }; 2936 2937 struct rtw89_tx_skb_data { 2938 struct rtw89_tx_wait_info __rcu *wait; 2939 u8 hci_priv[]; 2940 }; 2941 2942 #define RTW89_ROC_IDLE_TIMEOUT 500 2943 #define RTW89_ROC_TX_TIMEOUT 30 2944 enum rtw89_roc_state { 2945 RTW89_ROC_IDLE, 2946 RTW89_ROC_NORMAL, 2947 RTW89_ROC_MGMT, 2948 }; 2949 2950 struct rtw89_roc { 2951 struct ieee80211_channel chan; 2952 struct delayed_work roc_work; 2953 enum ieee80211_roc_type type; 2954 enum rtw89_roc_state state; 2955 int duration; 2956 }; 2957 2958 #define RTW89_P2P_MAX_NOA_NUM 2 2959 2960 struct rtw89_p2p_ie_head { 2961 u8 eid; 2962 u8 ie_len; 2963 u8 oui[3]; 2964 u8 oui_type; 2965 } __packed; 2966 2967 struct rtw89_noa_attr_head { 2968 u8 attr_type; 2969 __le16 attr_len; 2970 u8 index; 2971 u8 oppps_ctwindow; 2972 } __packed; 2973 2974 struct rtw89_p2p_noa_ie { 2975 struct rtw89_p2p_ie_head p2p_head; 2976 struct rtw89_noa_attr_head noa_head; 2977 struct ieee80211_p2p_noa_desc noa_desc[RTW89_P2P_MAX_NOA_NUM]; 2978 } __packed; 2979 2980 struct rtw89_p2p_noa_setter { 2981 struct rtw89_p2p_noa_ie ie; 2982 u8 noa_count; 2983 u8 noa_index; 2984 }; 2985 2986 struct rtw89_vif { 2987 struct list_head list; 2988 struct rtw89_dev *rtwdev; 2989 struct rtw89_roc roc; 2990 bool chanctx_assigned; /* only valid when running with chanctx_ops */ 2991 enum rtw89_sub_entity_idx sub_entity_idx; 2992 enum rtw89_reg_6ghz_power reg_6ghz_power; 2993 2994 u8 mac_id; 2995 u8 port; 2996 u8 mac_addr[ETH_ALEN]; 2997 u8 bssid[ETH_ALEN]; 2998 u8 phy_idx; 2999 u8 mac_idx; 3000 u8 net_type; 3001 u8 wifi_role; 3002 u8 self_role; 3003 u8 wmm; 3004 u8 bcn_hit_cond; 3005 u8 hit_rule; 3006 u8 last_noa_nr; 3007 bool offchan; 3008 bool trigger; 3009 bool lsig_txop; 3010 u8 tgt_ind; 3011 u8 frm_tgt_ind; 3012 bool wowlan_pattern; 3013 bool wowlan_uc; 3014 bool wowlan_magic; 3015 bool is_hesta; 3016 bool last_a_ctrl; 3017 bool dyn_tb_bedge_en; 3018 bool pre_pwr_diff_en; 3019 bool pwr_diff_en; 3020 u8 def_tri_idx; 3021 u32 tdls_peer; 3022 struct work_struct update_beacon_work; 3023 struct rtw89_addr_cam_entry addr_cam; 3024 struct rtw89_bssid_cam_entry bssid_cam; 3025 struct ieee80211_tx_queue_params tx_params[IEEE80211_NUM_ACS]; 3026 struct rtw89_traffic_stats stats; 3027 struct rtw89_phy_rate_pattern rate_pattern; 3028 struct cfg80211_scan_request *scan_req; 3029 struct ieee80211_scan_ies *scan_ies; 3030 struct list_head general_pkt_list; 3031 struct rtw89_p2p_noa_setter p2p_noa; 3032 }; 3033 3034 enum rtw89_lv1_rcvy_step { 3035 RTW89_LV1_RCVY_STEP_1, 3036 RTW89_LV1_RCVY_STEP_2, 3037 }; 3038 3039 struct rtw89_hci_ops { 3040 int (*tx_write)(struct rtw89_dev *rtwdev, struct rtw89_core_tx_request *tx_req); 3041 void (*tx_kick_off)(struct rtw89_dev *rtwdev, u8 txch); 3042 void (*flush_queues)(struct rtw89_dev *rtwdev, u32 queues, bool drop); 3043 void (*reset)(struct rtw89_dev *rtwdev); 3044 int (*start)(struct rtw89_dev *rtwdev); 3045 void (*stop)(struct rtw89_dev *rtwdev); 3046 void (*pause)(struct rtw89_dev *rtwdev, bool pause); 3047 void (*switch_mode)(struct rtw89_dev *rtwdev, bool low_power); 3048 void (*recalc_int_mit)(struct rtw89_dev *rtwdev); 3049 3050 u8 (*read8)(struct rtw89_dev *rtwdev, u32 addr); 3051 u16 (*read16)(struct rtw89_dev *rtwdev, u32 addr); 3052 u32 (*read32)(struct rtw89_dev *rtwdev, u32 addr); 3053 void (*write8)(struct rtw89_dev *rtwdev, u32 addr, u8 data); 3054 void (*write16)(struct rtw89_dev *rtwdev, u32 addr, u16 data); 3055 void (*write32)(struct rtw89_dev *rtwdev, u32 addr, u32 data); 3056 3057 int (*mac_pre_init)(struct rtw89_dev *rtwdev); 3058 int (*mac_post_init)(struct rtw89_dev *rtwdev); 3059 int (*deinit)(struct rtw89_dev *rtwdev); 3060 3061 u32 (*check_and_reclaim_tx_resource)(struct rtw89_dev *rtwdev, u8 txch); 3062 int (*mac_lv1_rcvy)(struct rtw89_dev *rtwdev, enum rtw89_lv1_rcvy_step step); 3063 void (*dump_err_status)(struct rtw89_dev *rtwdev); 3064 int (*napi_poll)(struct napi_struct *napi, int budget); 3065 3066 /* Deal with locks inside recovery_start and recovery_complete callbacks 3067 * by hci instance, and handle things which need to consider under SER. 3068 * e.g. turn on/off interrupts except for the one for halt notification. 3069 */ 3070 void (*recovery_start)(struct rtw89_dev *rtwdev); 3071 void (*recovery_complete)(struct rtw89_dev *rtwdev); 3072 3073 void (*ctrl_txdma_ch)(struct rtw89_dev *rtwdev, bool enable); 3074 void (*ctrl_txdma_fw_ch)(struct rtw89_dev *rtwdev, bool enable); 3075 void (*ctrl_trxhci)(struct rtw89_dev *rtwdev, bool enable); 3076 int (*poll_txdma_ch)(struct rtw89_dev *rtwdev); 3077 void (*clr_idx_all)(struct rtw89_dev *rtwdev); 3078 void (*clear)(struct rtw89_dev *rtwdev, struct pci_dev *pdev); 3079 void (*disable_intr)(struct rtw89_dev *rtwdev); 3080 void (*enable_intr)(struct rtw89_dev *rtwdev); 3081 int (*rst_bdram)(struct rtw89_dev *rtwdev); 3082 }; 3083 3084 struct rtw89_hci_info { 3085 const struct rtw89_hci_ops *ops; 3086 enum rtw89_hci_type type; 3087 u32 rpwm_addr; 3088 u32 cpwm_addr; 3089 bool paused; 3090 }; 3091 3092 struct rtw89_chip_ops { 3093 int (*enable_bb_rf)(struct rtw89_dev *rtwdev); 3094 int (*disable_bb_rf)(struct rtw89_dev *rtwdev); 3095 void (*bb_preinit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3096 void (*bb_reset)(struct rtw89_dev *rtwdev, 3097 enum rtw89_phy_idx phy_idx); 3098 void (*bb_sethw)(struct rtw89_dev *rtwdev); 3099 u32 (*read_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3100 u32 addr, u32 mask); 3101 bool (*write_rf)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 3102 u32 addr, u32 mask, u32 data); 3103 void (*set_channel)(struct rtw89_dev *rtwdev, 3104 const struct rtw89_chan *chan, 3105 enum rtw89_mac_idx mac_idx, 3106 enum rtw89_phy_idx phy_idx); 3107 void (*set_channel_help)(struct rtw89_dev *rtwdev, bool enter, 3108 struct rtw89_channel_help_params *p, 3109 const struct rtw89_chan *chan, 3110 enum rtw89_mac_idx mac_idx, 3111 enum rtw89_phy_idx phy_idx); 3112 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map); 3113 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 3114 void (*fem_setup)(struct rtw89_dev *rtwdev); 3115 void (*rfe_gpio)(struct rtw89_dev *rtwdev); 3116 void (*rfk_init)(struct rtw89_dev *rtwdev); 3117 void (*rfk_channel)(struct rtw89_dev *rtwdev); 3118 void (*rfk_band_changed)(struct rtw89_dev *rtwdev, 3119 enum rtw89_phy_idx phy_idx); 3120 void (*rfk_scan)(struct rtw89_dev *rtwdev, bool start); 3121 void (*rfk_track)(struct rtw89_dev *rtwdev); 3122 void (*power_trim)(struct rtw89_dev *rtwdev); 3123 void (*set_txpwr)(struct rtw89_dev *rtwdev, 3124 const struct rtw89_chan *chan, 3125 enum rtw89_phy_idx phy_idx); 3126 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 3127 enum rtw89_phy_idx phy_idx); 3128 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 3129 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 3130 void (*ctrl_btg)(struct rtw89_dev *rtwdev, bool btg); 3131 void (*query_ppdu)(struct rtw89_dev *rtwdev, 3132 struct rtw89_rx_phy_ppdu *phy_ppdu, 3133 struct ieee80211_rx_status *status); 3134 void (*bb_ctrl_btc_preagc)(struct rtw89_dev *rtwdev, bool bt_en); 3135 void (*cfg_txrx_path)(struct rtw89_dev *rtwdev); 3136 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 3137 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 3138 int (*pwr_on_func)(struct rtw89_dev *rtwdev); 3139 int (*pwr_off_func)(struct rtw89_dev *rtwdev); 3140 void (*query_rxdesc)(struct rtw89_dev *rtwdev, 3141 struct rtw89_rx_desc_info *desc_info, 3142 u8 *data, u32 data_offset); 3143 void (*fill_txdesc)(struct rtw89_dev *rtwdev, 3144 struct rtw89_tx_desc_info *desc_info, 3145 void *txdesc); 3146 void (*fill_txdesc_fwcmd)(struct rtw89_dev *rtwdev, 3147 struct rtw89_tx_desc_info *desc_info, 3148 void *txdesc); 3149 int (*cfg_ctrl_path)(struct rtw89_dev *rtwdev, bool wl); 3150 int (*mac_cfg_gnt)(struct rtw89_dev *rtwdev, 3151 const struct rtw89_mac_ax_coex_gnt *gnt_cfg); 3152 int (*stop_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, 3153 u32 *tx_en, enum rtw89_sch_tx_sel sel); 3154 int (*resume_sch_tx)(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); 3155 int (*h2c_dctl_sec_cam)(struct rtw89_dev *rtwdev, 3156 struct rtw89_vif *rtwvif, 3157 struct rtw89_sta *rtwsta); 3158 3159 void (*btc_set_rfe)(struct rtw89_dev *rtwdev); 3160 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 3161 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 3162 void (*btc_set_wl_txpwr_ctrl)(struct rtw89_dev *rtwdev, u32 txpwr_val); 3163 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 3164 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 3165 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 3166 void (*btc_set_policy)(struct rtw89_dev *rtwdev, u16 policy_type); 3167 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 3168 }; 3169 3170 enum rtw89_dma_ch { 3171 RTW89_DMA_ACH0 = 0, 3172 RTW89_DMA_ACH1 = 1, 3173 RTW89_DMA_ACH2 = 2, 3174 RTW89_DMA_ACH3 = 3, 3175 RTW89_DMA_ACH4 = 4, 3176 RTW89_DMA_ACH5 = 5, 3177 RTW89_DMA_ACH6 = 6, 3178 RTW89_DMA_ACH7 = 7, 3179 RTW89_DMA_B0MG = 8, 3180 RTW89_DMA_B0HI = 9, 3181 RTW89_DMA_B1MG = 10, 3182 RTW89_DMA_B1HI = 11, 3183 RTW89_DMA_H2C = 12, 3184 RTW89_DMA_CH_NUM = 13 3185 }; 3186 3187 enum rtw89_qta_mode { 3188 RTW89_QTA_SCC, 3189 RTW89_QTA_DLFW, 3190 RTW89_QTA_WOW, 3191 3192 /* keep last */ 3193 RTW89_QTA_INVALID, 3194 }; 3195 3196 struct rtw89_hfc_ch_cfg { 3197 u16 min; 3198 u16 max; 3199 #define grp_0 0 3200 #define grp_1 1 3201 #define grp_num 2 3202 u8 grp; 3203 }; 3204 3205 struct rtw89_hfc_ch_info { 3206 u16 aval; 3207 u16 used; 3208 }; 3209 3210 struct rtw89_hfc_pub_cfg { 3211 u16 grp0; 3212 u16 grp1; 3213 u16 pub_max; 3214 u16 wp_thrd; 3215 }; 3216 3217 struct rtw89_hfc_pub_info { 3218 u16 g0_used; 3219 u16 g1_used; 3220 u16 g0_aval; 3221 u16 g1_aval; 3222 u16 pub_aval; 3223 u16 wp_aval; 3224 }; 3225 3226 struct rtw89_hfc_prec_cfg { 3227 u16 ch011_prec; 3228 u16 h2c_prec; 3229 u16 wp_ch07_prec; 3230 u16 wp_ch811_prec; 3231 u8 ch011_full_cond; 3232 u8 h2c_full_cond; 3233 u8 wp_ch07_full_cond; 3234 u8 wp_ch811_full_cond; 3235 }; 3236 3237 struct rtw89_hfc_param { 3238 bool en; 3239 bool h2c_en; 3240 u8 mode; 3241 const struct rtw89_hfc_ch_cfg *ch_cfg; 3242 struct rtw89_hfc_ch_info ch_info[RTW89_DMA_CH_NUM]; 3243 struct rtw89_hfc_pub_cfg pub_cfg; 3244 struct rtw89_hfc_pub_info pub_info; 3245 struct rtw89_hfc_prec_cfg prec_cfg; 3246 }; 3247 3248 struct rtw89_hfc_param_ini { 3249 const struct rtw89_hfc_ch_cfg *ch_cfg; 3250 const struct rtw89_hfc_pub_cfg *pub_cfg; 3251 const struct rtw89_hfc_prec_cfg *prec_cfg; 3252 u8 mode; 3253 }; 3254 3255 struct rtw89_dle_size { 3256 u16 pge_size; 3257 u16 lnk_pge_num; 3258 u16 unlnk_pge_num; 3259 }; 3260 3261 struct rtw89_wde_quota { 3262 u16 hif; 3263 u16 wcpu; 3264 u16 pkt_in; 3265 u16 cpu_io; 3266 }; 3267 3268 struct rtw89_ple_quota { 3269 u16 cma0_tx; 3270 u16 cma1_tx; 3271 u16 c2h; 3272 u16 h2c; 3273 u16 wcpu; 3274 u16 mpdu_proc; 3275 u16 cma0_dma; 3276 u16 cma1_dma; 3277 u16 bb_rpt; 3278 u16 wd_rel; 3279 u16 cpu_io; 3280 u16 tx_rpt; 3281 }; 3282 3283 struct rtw89_dle_mem { 3284 enum rtw89_qta_mode mode; 3285 const struct rtw89_dle_size *wde_size; 3286 const struct rtw89_dle_size *ple_size; 3287 const struct rtw89_wde_quota *wde_min_qt; 3288 const struct rtw89_wde_quota *wde_max_qt; 3289 const struct rtw89_ple_quota *ple_min_qt; 3290 const struct rtw89_ple_quota *ple_max_qt; 3291 }; 3292 3293 struct rtw89_reg_def { 3294 u32 addr; 3295 u32 mask; 3296 }; 3297 3298 struct rtw89_reg2_def { 3299 u32 addr; 3300 u32 data; 3301 }; 3302 3303 struct rtw89_reg3_def { 3304 u32 addr; 3305 u32 mask; 3306 u32 data; 3307 }; 3308 3309 struct rtw89_reg5_def { 3310 u8 flag; /* recognized by parsers */ 3311 u8 path; 3312 u32 addr; 3313 u32 mask; 3314 u32 data; 3315 }; 3316 3317 struct rtw89_phy_table { 3318 const struct rtw89_reg2_def *regs; 3319 u32 n_regs; 3320 enum rtw89_rf_path rf_path; 3321 void (*config)(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, 3322 enum rtw89_rf_path rf_path, void *data); 3323 }; 3324 3325 struct rtw89_txpwr_table { 3326 const void *data; 3327 u32 size; 3328 void (*load)(struct rtw89_dev *rtwdev, 3329 const struct rtw89_txpwr_table *tbl); 3330 }; 3331 3332 struct rtw89_txpwr_rule_2ghz { 3333 const s8 (*lmt)[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3334 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3335 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3336 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3337 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3338 }; 3339 3340 struct rtw89_txpwr_rule_5ghz { 3341 const s8 (*lmt)[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3342 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3343 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3344 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3345 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3346 }; 3347 3348 struct rtw89_txpwr_rule_6ghz { 3349 const s8 (*lmt)[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3350 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3351 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3352 [RTW89_6G_CH_NUM]; 3353 const s8 (*lmt_ru)[RTW89_RU_NUM][RTW89_NTX_NUM] 3354 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3355 [RTW89_6G_CH_NUM]; 3356 }; 3357 3358 struct rtw89_tx_shape { 3359 const u8 (*lmt)[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3360 const u8 (*lmt_ru)[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3361 }; 3362 3363 struct rtw89_rfe_parms { 3364 const struct rtw89_txpwr_table *byr_tbl; 3365 struct rtw89_txpwr_rule_2ghz rule_2ghz; 3366 struct rtw89_txpwr_rule_5ghz rule_5ghz; 3367 struct rtw89_txpwr_rule_6ghz rule_6ghz; 3368 struct rtw89_tx_shape tx_shape; 3369 }; 3370 3371 struct rtw89_rfe_parms_conf { 3372 const struct rtw89_rfe_parms *rfe_parms; 3373 u8 rfe_type; 3374 }; 3375 3376 #define RTW89_TXPWR_CONF_DFLT_RFE_TYPE 0x0 3377 3378 struct rtw89_txpwr_conf { 3379 u8 rfe_type; 3380 u8 ent_sz; 3381 u32 num_ents; 3382 const void *data; 3383 }; 3384 3385 #define rtw89_txpwr_conf_valid(conf) (!!(conf)->data) 3386 3387 #define rtw89_for_each_in_txpwr_conf(entry, cursor, conf) \ 3388 for (typecheck(const void *, cursor), (cursor) = (conf)->data, \ 3389 memcpy(&(entry), cursor, \ 3390 min_t(u8, sizeof(entry), (conf)->ent_sz)); \ 3391 (cursor) < (conf)->data + (conf)->num_ents * (conf)->ent_sz; \ 3392 (cursor) += (conf)->ent_sz, \ 3393 memcpy(&(entry), cursor, \ 3394 min_t(u8, sizeof(entry), (conf)->ent_sz))) 3395 3396 struct rtw89_txpwr_byrate_data { 3397 struct rtw89_txpwr_conf conf; 3398 struct rtw89_txpwr_table tbl; 3399 }; 3400 3401 struct rtw89_txpwr_lmt_2ghz_data { 3402 struct rtw89_txpwr_conf conf; 3403 s8 v[RTW89_2G_BW_NUM][RTW89_NTX_NUM] 3404 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3405 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3406 }; 3407 3408 struct rtw89_txpwr_lmt_5ghz_data { 3409 struct rtw89_txpwr_conf conf; 3410 s8 v[RTW89_5G_BW_NUM][RTW89_NTX_NUM] 3411 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3412 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3413 }; 3414 3415 struct rtw89_txpwr_lmt_6ghz_data { 3416 struct rtw89_txpwr_conf conf; 3417 s8 v[RTW89_6G_BW_NUM][RTW89_NTX_NUM] 3418 [RTW89_RS_LMT_NUM][RTW89_BF_NUM] 3419 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3420 [RTW89_6G_CH_NUM]; 3421 }; 3422 3423 struct rtw89_txpwr_lmt_ru_2ghz_data { 3424 struct rtw89_txpwr_conf conf; 3425 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3426 [RTW89_REGD_NUM][RTW89_2G_CH_NUM]; 3427 }; 3428 3429 struct rtw89_txpwr_lmt_ru_5ghz_data { 3430 struct rtw89_txpwr_conf conf; 3431 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3432 [RTW89_REGD_NUM][RTW89_5G_CH_NUM]; 3433 }; 3434 3435 struct rtw89_txpwr_lmt_ru_6ghz_data { 3436 struct rtw89_txpwr_conf conf; 3437 s8 v[RTW89_RU_NUM][RTW89_NTX_NUM] 3438 [RTW89_REGD_NUM][NUM_OF_RTW89_REG_6GHZ_POWER] 3439 [RTW89_6G_CH_NUM]; 3440 }; 3441 3442 struct rtw89_tx_shape_lmt_data { 3443 struct rtw89_txpwr_conf conf; 3444 u8 v[RTW89_BAND_NUM][RTW89_RS_TX_SHAPE_NUM][RTW89_REGD_NUM]; 3445 }; 3446 3447 struct rtw89_tx_shape_lmt_ru_data { 3448 struct rtw89_txpwr_conf conf; 3449 u8 v[RTW89_BAND_NUM][RTW89_REGD_NUM]; 3450 }; 3451 3452 struct rtw89_rfe_data { 3453 struct rtw89_txpwr_byrate_data byrate; 3454 struct rtw89_txpwr_lmt_2ghz_data lmt_2ghz; 3455 struct rtw89_txpwr_lmt_5ghz_data lmt_5ghz; 3456 struct rtw89_txpwr_lmt_6ghz_data lmt_6ghz; 3457 struct rtw89_txpwr_lmt_ru_2ghz_data lmt_ru_2ghz; 3458 struct rtw89_txpwr_lmt_ru_5ghz_data lmt_ru_5ghz; 3459 struct rtw89_txpwr_lmt_ru_6ghz_data lmt_ru_6ghz; 3460 struct rtw89_tx_shape_lmt_data tx_shape_lmt; 3461 struct rtw89_tx_shape_lmt_ru_data tx_shape_lmt_ru; 3462 struct rtw89_rfe_parms rfe_parms; 3463 }; 3464 3465 struct rtw89_page_regs { 3466 u32 hci_fc_ctrl; 3467 u32 ch_page_ctrl; 3468 u32 ach_page_ctrl; 3469 u32 ach_page_info; 3470 u32 pub_page_info3; 3471 u32 pub_page_ctrl1; 3472 u32 pub_page_ctrl2; 3473 u32 pub_page_info1; 3474 u32 pub_page_info2; 3475 u32 wp_page_ctrl1; 3476 u32 wp_page_ctrl2; 3477 u32 wp_page_info1; 3478 }; 3479 3480 struct rtw89_imr_info { 3481 u32 wdrls_imr_set; 3482 u32 wsec_imr_reg; 3483 u32 wsec_imr_set; 3484 u32 mpdu_tx_imr_set; 3485 u32 mpdu_rx_imr_set; 3486 u32 sta_sch_imr_set; 3487 u32 txpktctl_imr_b0_reg; 3488 u32 txpktctl_imr_b0_clr; 3489 u32 txpktctl_imr_b0_set; 3490 u32 txpktctl_imr_b1_reg; 3491 u32 txpktctl_imr_b1_clr; 3492 u32 txpktctl_imr_b1_set; 3493 u32 wde_imr_clr; 3494 u32 wde_imr_set; 3495 u32 ple_imr_clr; 3496 u32 ple_imr_set; 3497 u32 host_disp_imr_clr; 3498 u32 host_disp_imr_set; 3499 u32 cpu_disp_imr_clr; 3500 u32 cpu_disp_imr_set; 3501 u32 other_disp_imr_clr; 3502 u32 other_disp_imr_set; 3503 u32 bbrpt_com_err_imr_reg; 3504 u32 bbrpt_chinfo_err_imr_reg; 3505 u32 bbrpt_err_imr_set; 3506 u32 bbrpt_dfs_err_imr_reg; 3507 u32 ptcl_imr_clr; 3508 u32 ptcl_imr_set; 3509 u32 cdma_imr_0_reg; 3510 u32 cdma_imr_0_clr; 3511 u32 cdma_imr_0_set; 3512 u32 cdma_imr_1_reg; 3513 u32 cdma_imr_1_clr; 3514 u32 cdma_imr_1_set; 3515 u32 phy_intf_imr_reg; 3516 u32 phy_intf_imr_clr; 3517 u32 phy_intf_imr_set; 3518 u32 rmac_imr_reg; 3519 u32 rmac_imr_clr; 3520 u32 rmac_imr_set; 3521 u32 tmac_imr_reg; 3522 u32 tmac_imr_clr; 3523 u32 tmac_imr_set; 3524 }; 3525 3526 struct rtw89_xtal_info { 3527 u32 xcap_reg; 3528 u32 sc_xo_mask; 3529 u32 sc_xi_mask; 3530 }; 3531 3532 struct rtw89_rrsr_cfgs { 3533 struct rtw89_reg3_def ref_rate; 3534 struct rtw89_reg3_def rsc; 3535 }; 3536 3537 struct rtw89_dig_regs { 3538 u32 seg0_pd_reg; 3539 u32 pd_lower_bound_mask; 3540 u32 pd_spatial_reuse_en; 3541 u32 bmode_pd_reg; 3542 u32 bmode_cca_rssi_limit_en; 3543 u32 bmode_pd_lower_bound_reg; 3544 u32 bmode_rssi_nocca_low_th_mask; 3545 struct rtw89_reg_def p0_lna_init; 3546 struct rtw89_reg_def p1_lna_init; 3547 struct rtw89_reg_def p0_tia_init; 3548 struct rtw89_reg_def p1_tia_init; 3549 struct rtw89_reg_def p0_rxb_init; 3550 struct rtw89_reg_def p1_rxb_init; 3551 struct rtw89_reg_def p0_p20_pagcugc_en; 3552 struct rtw89_reg_def p0_s20_pagcugc_en; 3553 struct rtw89_reg_def p1_p20_pagcugc_en; 3554 struct rtw89_reg_def p1_s20_pagcugc_en; 3555 }; 3556 3557 struct rtw89_phy_ul_tb_info { 3558 bool dyn_tb_tri_en; 3559 u8 def_if_bandedge; 3560 }; 3561 3562 struct rtw89_antdiv_stats { 3563 struct ewma_rssi cck_rssi_avg; 3564 struct ewma_rssi ofdm_rssi_avg; 3565 struct ewma_rssi non_legacy_rssi_avg; 3566 u16 pkt_cnt_cck; 3567 u16 pkt_cnt_ofdm; 3568 u16 pkt_cnt_non_legacy; 3569 u32 evm; 3570 }; 3571 3572 struct rtw89_antdiv_info { 3573 struct rtw89_antdiv_stats target_stats; 3574 struct rtw89_antdiv_stats main_stats; 3575 struct rtw89_antdiv_stats aux_stats; 3576 u8 training_count; 3577 u8 rssi_pre; 3578 bool get_stats; 3579 }; 3580 3581 enum rtw89_chanctx_state { 3582 RTW89_CHANCTX_STATE_MCC_START, 3583 RTW89_CHANCTX_STATE_MCC_STOP, 3584 }; 3585 3586 enum rtw89_chanctx_callbacks { 3587 RTW89_CHANCTX_CALLBACK_PLACEHOLDER, 3588 RTW89_CHANCTX_CALLBACK_RFK, 3589 3590 NUM_OF_RTW89_CHANCTX_CALLBACKS, 3591 }; 3592 3593 struct rtw89_chanctx_listener { 3594 void (*callbacks[NUM_OF_RTW89_CHANCTX_CALLBACKS]) 3595 (struct rtw89_dev *rtwdev, enum rtw89_chanctx_state state); 3596 }; 3597 3598 struct rtw89_chip_info { 3599 enum rtw89_core_chip_id chip_id; 3600 enum rtw89_chip_gen chip_gen; 3601 const struct rtw89_chip_ops *ops; 3602 const struct rtw89_mac_gen_def *mac_def; 3603 const struct rtw89_phy_gen_def *phy_def; 3604 const char *fw_basename; 3605 u8 fw_format_max; 3606 bool try_ce_fw; 3607 u8 bbmcu_nr; 3608 u32 needed_fw_elms; 3609 u32 fifo_size; 3610 bool small_fifo_size; 3611 u32 dle_scc_rsvd_size; 3612 u16 max_amsdu_limit; 3613 bool dis_2g_40m_ul_ofdma; 3614 u32 rsvd_ple_ofst; 3615 const struct rtw89_hfc_param_ini *hfc_param_ini; 3616 const struct rtw89_dle_mem *dle_mem; 3617 u8 wde_qempty_acq_num; 3618 u8 wde_qempty_mgq_sel; 3619 u32 rf_base_addr[2]; 3620 u8 support_chanctx_num; 3621 u8 support_bands; 3622 bool support_bw160; 3623 bool support_unii4; 3624 bool ul_tb_waveform_ctrl; 3625 bool ul_tb_pwr_diff; 3626 bool hw_sec_hdr; 3627 u8 rf_path_num; 3628 u8 tx_nss; 3629 u8 rx_nss; 3630 u8 acam_num; 3631 u8 bcam_num; 3632 u8 scam_num; 3633 u8 bacam_num; 3634 u8 bacam_dynamic_num; 3635 enum rtw89_bacam_ver bacam_ver; 3636 3637 u8 sec_ctrl_efuse_size; 3638 u32 physical_efuse_size; 3639 u32 logical_efuse_size; 3640 u32 limit_efuse_size; 3641 u32 dav_phy_efuse_size; 3642 u32 dav_log_efuse_size; 3643 u32 phycap_addr; 3644 u32 phycap_size; 3645 3646 const struct rtw89_pwr_cfg * const *pwr_on_seq; 3647 const struct rtw89_pwr_cfg * const *pwr_off_seq; 3648 const struct rtw89_phy_table *bb_table; 3649 const struct rtw89_phy_table *bb_gain_table; 3650 const struct rtw89_phy_table *rf_table[RF_PATH_MAX]; 3651 const struct rtw89_phy_table *nctl_table; 3652 const struct rtw89_rfk_tbl *nctl_post_table; 3653 const struct rtw89_phy_dig_gain_table *dig_table; 3654 const struct rtw89_dig_regs *dig_regs; 3655 const struct rtw89_phy_tssi_dbw_table *tssi_dbw_table; 3656 3657 /* NULL if no rfe-specific, or a null-terminated array by rfe_parms */ 3658 const struct rtw89_rfe_parms_conf *rfe_parms_conf; 3659 const struct rtw89_rfe_parms *dflt_parms; 3660 const struct rtw89_chanctx_listener *chanctx_listener; 3661 3662 u8 txpwr_factor_rf; 3663 u8 txpwr_factor_mac; 3664 3665 u32 para_ver; 3666 u32 wlcx_desired; 3667 u8 btcx_desired; 3668 u8 scbd; 3669 u8 mailbox; 3670 3671 u8 afh_guard_ch; 3672 const u8 *wl_rssi_thres; 3673 const u8 *bt_rssi_thres; 3674 u8 rssi_tol; 3675 3676 u8 mon_reg_num; 3677 const struct rtw89_btc_fbtc_mreg *mon_reg; 3678 u8 rf_para_ulink_num; 3679 const struct rtw89_btc_rf_trx_para *rf_para_ulink; 3680 u8 rf_para_dlink_num; 3681 const struct rtw89_btc_rf_trx_para *rf_para_dlink; 3682 u8 ps_mode_supported; 3683 u8 low_power_hci_modes; 3684 3685 u32 h2c_cctl_func_id; 3686 u32 hci_func_en_addr; 3687 u32 h2c_desc_size; 3688 u32 txwd_body_size; 3689 u32 txwd_info_size; 3690 u32 h2c_ctrl_reg; 3691 const u32 *h2c_regs; 3692 struct rtw89_reg_def h2c_counter_reg; 3693 u32 c2h_ctrl_reg; 3694 const u32 *c2h_regs; 3695 struct rtw89_reg_def c2h_counter_reg; 3696 const struct rtw89_page_regs *page_regs; 3697 bool cfo_src_fd; 3698 bool cfo_hw_comp; 3699 const struct rtw89_reg_def *dcfo_comp; 3700 u8 dcfo_comp_sft; 3701 const struct rtw89_imr_info *imr_info; 3702 const struct rtw89_rrsr_cfgs *rrsr_cfgs; 3703 u32 bss_clr_map_reg; 3704 u32 dma_ch_mask; 3705 u32 edcca_lvl_reg; 3706 const struct wiphy_wowlan_support *wowlan_stub; 3707 const struct rtw89_xtal_info *xtal_info; 3708 }; 3709 3710 union rtw89_bus_info { 3711 const struct rtw89_pci_info *pci; 3712 }; 3713 3714 struct rtw89_driver_info { 3715 const struct rtw89_chip_info *chip; 3716 union rtw89_bus_info bus; 3717 }; 3718 3719 enum rtw89_hcifc_mode { 3720 RTW89_HCIFC_POH = 0, 3721 RTW89_HCIFC_STF = 1, 3722 RTW89_HCIFC_SDIO = 2, 3723 3724 /* keep last */ 3725 RTW89_HCIFC_MODE_INVALID, 3726 }; 3727 3728 struct rtw89_dle_info { 3729 enum rtw89_qta_mode qta_mode; 3730 u16 ple_pg_size; 3731 u16 c0_rx_qta; 3732 u16 c1_rx_qta; 3733 }; 3734 3735 enum rtw89_host_rpr_mode { 3736 RTW89_RPR_MODE_POH = 0, 3737 RTW89_RPR_MODE_STF 3738 }; 3739 3740 #define RTW89_COMPLETION_BUF_SIZE 24 3741 #define RTW89_WAIT_COND_IDLE UINT_MAX 3742 3743 struct rtw89_completion_data { 3744 bool err; 3745 u8 buf[RTW89_COMPLETION_BUF_SIZE]; 3746 }; 3747 3748 struct rtw89_wait_info { 3749 atomic_t cond; 3750 struct completion completion; 3751 struct rtw89_completion_data data; 3752 }; 3753 3754 #define RTW89_WAIT_FOR_COND_TIMEOUT msecs_to_jiffies(100) 3755 3756 static inline void rtw89_init_wait(struct rtw89_wait_info *wait) 3757 { 3758 init_completion(&wait->completion); 3759 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3760 } 3761 3762 struct rtw89_mac_info { 3763 struct rtw89_dle_info dle_info; 3764 struct rtw89_hfc_param hfc_param; 3765 enum rtw89_qta_mode qta_mode; 3766 u8 rpwm_seq_num; 3767 u8 cpwm_seq_num; 3768 3769 /* see RTW89_FW_OFLD_WAIT_COND series for wait condition */ 3770 struct rtw89_wait_info fw_ofld_wait; 3771 }; 3772 3773 enum rtw89_fwdl_check_type { 3774 RTW89_FWDL_CHECK_FREERTOS_DONE, 3775 RTW89_FWDL_CHECK_WCPU_FWDL_DONE, 3776 RTW89_FWDL_CHECK_DCPU_FWDL_DONE, 3777 RTW89_FWDL_CHECK_BB0_FWDL_DONE, 3778 RTW89_FWDL_CHECK_BB1_FWDL_DONE, 3779 }; 3780 3781 enum rtw89_fw_type { 3782 RTW89_FW_NORMAL = 1, 3783 RTW89_FW_WOWLAN = 3, 3784 RTW89_FW_NORMAL_CE = 5, 3785 RTW89_FW_BBMCU0 = 64, 3786 RTW89_FW_BBMCU1 = 65, 3787 RTW89_FW_LOGFMT = 255, 3788 }; 3789 3790 enum rtw89_fw_feature { 3791 RTW89_FW_FEATURE_OLD_HT_RA_FORMAT, 3792 RTW89_FW_FEATURE_SCAN_OFFLOAD, 3793 RTW89_FW_FEATURE_TX_WAKE, 3794 RTW89_FW_FEATURE_CRASH_TRIGGER, 3795 RTW89_FW_FEATURE_NO_PACKET_DROP, 3796 RTW89_FW_FEATURE_NO_DEEP_PS, 3797 RTW89_FW_FEATURE_NO_LPS_PG, 3798 RTW89_FW_FEATURE_BEACON_FILTER, 3799 }; 3800 3801 struct rtw89_fw_suit { 3802 enum rtw89_fw_type type; 3803 const u8 *data; 3804 u32 size; 3805 u8 major_ver; 3806 u8 minor_ver; 3807 u8 sub_ver; 3808 u8 sub_idex; 3809 u16 build_year; 3810 u16 build_mon; 3811 u16 build_date; 3812 u16 build_hour; 3813 u16 build_min; 3814 u8 cmd_ver; 3815 u8 hdr_ver; 3816 u32 commitid; 3817 }; 3818 3819 #define RTW89_FW_VER_CODE(major, minor, sub, idx) \ 3820 (((major) << 24) | ((minor) << 16) | ((sub) << 8) | (idx)) 3821 #define RTW89_FW_SUIT_VER_CODE(s) \ 3822 RTW89_FW_VER_CODE((s)->major_ver, (s)->minor_ver, (s)->sub_ver, (s)->sub_idex) 3823 3824 #define RTW89_MFW_HDR_VER_CODE(mfw_hdr) \ 3825 RTW89_FW_VER_CODE((mfw_hdr)->ver.major, \ 3826 (mfw_hdr)->ver.minor, \ 3827 (mfw_hdr)->ver.sub, \ 3828 (mfw_hdr)->ver.idx) 3829 3830 #define RTW89_FW_HDR_VER_CODE(fw_hdr) \ 3831 RTW89_FW_VER_CODE(le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MAJOR_VERSION), \ 3832 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_MINOR_VERSION), \ 3833 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBVERSION), \ 3834 le32_get_bits((fw_hdr)->w1, FW_HDR_W1_SUBINDEX)) 3835 3836 struct rtw89_fw_req_info { 3837 const struct firmware *firmware; 3838 struct completion completion; 3839 }; 3840 3841 struct rtw89_fw_log { 3842 struct rtw89_fw_suit suit; 3843 bool enable; 3844 u32 last_fmt_id; 3845 u32 fmt_count; 3846 const __le32 *fmt_ids; 3847 const char *(*fmts)[]; 3848 }; 3849 3850 struct rtw89_fw_elm_info { 3851 struct rtw89_phy_table *bb_tbl; 3852 struct rtw89_phy_table *bb_gain; 3853 struct rtw89_phy_table *rf_radio[RF_PATH_MAX]; 3854 struct rtw89_phy_table *rf_nctl; 3855 }; 3856 3857 struct rtw89_fw_info { 3858 struct rtw89_fw_req_info req; 3859 int fw_format; 3860 u8 h2c_seq; 3861 u8 rec_seq; 3862 u8 h2c_counter; 3863 u8 c2h_counter; 3864 struct rtw89_fw_suit normal; 3865 struct rtw89_fw_suit wowlan; 3866 struct rtw89_fw_suit bbmcu0; 3867 struct rtw89_fw_suit bbmcu1; 3868 struct rtw89_fw_log log; 3869 u32 feature_map; 3870 struct rtw89_fw_elm_info elm_info; 3871 }; 3872 3873 #define RTW89_CHK_FW_FEATURE(_feat, _fw) \ 3874 (!!((_fw)->feature_map & BIT(RTW89_FW_FEATURE_ ## _feat))) 3875 3876 #define RTW89_SET_FW_FEATURE(_fw_feature, _fw) \ 3877 ((_fw)->feature_map |= BIT(_fw_feature)) 3878 3879 struct rtw89_cam_info { 3880 DECLARE_BITMAP(addr_cam_map, RTW89_MAX_ADDR_CAM_NUM); 3881 DECLARE_BITMAP(bssid_cam_map, RTW89_MAX_BSSID_CAM_NUM); 3882 DECLARE_BITMAP(sec_cam_map, RTW89_MAX_SEC_CAM_NUM); 3883 DECLARE_BITMAP(ba_cam_map, RTW89_MAX_BA_CAM_NUM); 3884 struct rtw89_ba_cam_entry ba_cam_entry[RTW89_MAX_BA_CAM_NUM]; 3885 }; 3886 3887 enum rtw89_sar_sources { 3888 RTW89_SAR_SOURCE_NONE, 3889 RTW89_SAR_SOURCE_COMMON, 3890 3891 RTW89_SAR_SOURCE_NR, 3892 }; 3893 3894 enum rtw89_sar_subband { 3895 RTW89_SAR_2GHZ_SUBBAND, 3896 RTW89_SAR_5GHZ_SUBBAND_1_2, /* U-NII-1 and U-NII-2 */ 3897 RTW89_SAR_5GHZ_SUBBAND_2_E, /* U-NII-2-Extended */ 3898 RTW89_SAR_5GHZ_SUBBAND_3, /* U-NII-3 */ 3899 RTW89_SAR_6GHZ_SUBBAND_5_L, /* U-NII-5 lower part */ 3900 RTW89_SAR_6GHZ_SUBBAND_5_H, /* U-NII-5 higher part */ 3901 RTW89_SAR_6GHZ_SUBBAND_6, /* U-NII-6 */ 3902 RTW89_SAR_6GHZ_SUBBAND_7_L, /* U-NII-7 lower part */ 3903 RTW89_SAR_6GHZ_SUBBAND_7_H, /* U-NII-7 higher part */ 3904 RTW89_SAR_6GHZ_SUBBAND_8, /* U-NII-8 */ 3905 3906 RTW89_SAR_SUBBAND_NR, 3907 }; 3908 3909 struct rtw89_sar_cfg_common { 3910 bool set[RTW89_SAR_SUBBAND_NR]; 3911 s32 cfg[RTW89_SAR_SUBBAND_NR]; 3912 }; 3913 3914 struct rtw89_sar_info { 3915 /* used to decide how to acces SAR cfg union */ 3916 enum rtw89_sar_sources src; 3917 3918 /* reserved for different knids of SAR cfg struct. 3919 * supposed that a single cfg struct cannot handle various SAR sources. 3920 */ 3921 union { 3922 struct rtw89_sar_cfg_common cfg_common; 3923 }; 3924 }; 3925 3926 enum rtw89_tas_state { 3927 RTW89_TAS_STATE_DPR_OFF, 3928 RTW89_TAS_STATE_DPR_ON, 3929 RTW89_TAS_STATE_DPR_FORBID, 3930 }; 3931 3932 #define RTW89_TAS_MAX_WINDOW 50 3933 struct rtw89_tas_info { 3934 s16 txpwr_history[RTW89_TAS_MAX_WINDOW]; 3935 s32 total_txpwr; 3936 u8 cur_idx; 3937 s8 dpr_gap; 3938 s8 delta; 3939 enum rtw89_tas_state state; 3940 bool enable; 3941 }; 3942 3943 struct rtw89_chanctx_cfg { 3944 enum rtw89_sub_entity_idx idx; 3945 }; 3946 3947 enum rtw89_chanctx_changes { 3948 RTW89_CHANCTX_REMOTE_STA_CHANGE, 3949 RTW89_CHANCTX_BCN_OFFSET_CHANGE, 3950 RTW89_CHANCTX_P2P_PS_CHANGE, 3951 RTW89_CHANCTX_BT_SLOT_CHANGE, 3952 RTW89_CHANCTX_TSF32_TOGGLE_CHANGE, 3953 3954 NUM_OF_RTW89_CHANCTX_CHANGES, 3955 RTW89_CHANCTX_CHANGE_DFLT = NUM_OF_RTW89_CHANCTX_CHANGES, 3956 }; 3957 3958 enum rtw89_entity_mode { 3959 RTW89_ENTITY_MODE_SCC, 3960 RTW89_ENTITY_MODE_MCC_PREPARE, 3961 RTW89_ENTITY_MODE_MCC, 3962 3963 NUM_OF_RTW89_ENTITY_MODE, 3964 RTW89_ENTITY_MODE_INVALID = NUM_OF_RTW89_ENTITY_MODE, 3965 }; 3966 3967 struct rtw89_sub_entity { 3968 struct cfg80211_chan_def chandef; 3969 struct rtw89_chan chan; 3970 struct rtw89_chan_rcd rcd; 3971 struct rtw89_chanctx_cfg *cfg; 3972 }; 3973 3974 struct rtw89_hal { 3975 u32 rx_fltr; 3976 u8 cv; 3977 u8 acv; 3978 u32 antenna_tx; 3979 u32 antenna_rx; 3980 u8 tx_nss; 3981 u8 rx_nss; 3982 bool tx_path_diversity; 3983 bool ant_diversity; 3984 bool ant_diversity_fixed; 3985 bool support_cckpd; 3986 bool support_igi; 3987 atomic_t roc_entity_idx; 3988 3989 DECLARE_BITMAP(changes, NUM_OF_RTW89_CHANCTX_CHANGES); 3990 DECLARE_BITMAP(entity_map, NUM_OF_RTW89_SUB_ENTITY); 3991 struct rtw89_sub_entity sub[NUM_OF_RTW89_SUB_ENTITY]; 3992 struct cfg80211_chan_def roc_chandef; 3993 3994 bool entity_active; 3995 bool entity_pause; 3996 enum rtw89_entity_mode entity_mode; 3997 3998 u32 edcca_bak; 3999 }; 4000 4001 #define RTW89_MAX_MAC_ID_NUM 128 4002 #define RTW89_MAX_PKT_OFLD_NUM 255 4003 4004 enum rtw89_flags { 4005 RTW89_FLAG_POWERON, 4006 RTW89_FLAG_FW_RDY, 4007 RTW89_FLAG_RUNNING, 4008 RTW89_FLAG_BFEE_MON, 4009 RTW89_FLAG_BFEE_EN, 4010 RTW89_FLAG_BFEE_TIMER_KEEP, 4011 RTW89_FLAG_NAPI_RUNNING, 4012 RTW89_FLAG_LEISURE_PS, 4013 RTW89_FLAG_LOW_POWER_MODE, 4014 RTW89_FLAG_INACTIVE_PS, 4015 RTW89_FLAG_CRASH_SIMULATING, 4016 RTW89_FLAG_SER_HANDLING, 4017 RTW89_FLAG_WOWLAN, 4018 RTW89_FLAG_FORBIDDEN_TRACK_WROK, 4019 RTW89_FLAG_CHANGING_INTERFACE, 4020 4021 NUM_OF_RTW89_FLAGS, 4022 }; 4023 4024 enum rtw89_pkt_drop_sel { 4025 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 4026 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 4027 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 4028 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 4029 RTW89_PKT_DROP_SEL_MACID_ALL, 4030 RTW89_PKT_DROP_SEL_MG0_ONCE, 4031 RTW89_PKT_DROP_SEL_HIQ_ONCE, 4032 RTW89_PKT_DROP_SEL_HIQ_PORT, 4033 RTW89_PKT_DROP_SEL_HIQ_MBSSID, 4034 RTW89_PKT_DROP_SEL_BAND, 4035 RTW89_PKT_DROP_SEL_BAND_ONCE, 4036 RTW89_PKT_DROP_SEL_REL_MACID, 4037 RTW89_PKT_DROP_SEL_REL_HIQ_PORT, 4038 RTW89_PKT_DROP_SEL_REL_HIQ_MBSSID, 4039 }; 4040 4041 struct rtw89_pkt_drop_params { 4042 enum rtw89_pkt_drop_sel sel; 4043 enum rtw89_mac_idx mac_band; 4044 u8 macid; 4045 u8 port; 4046 u8 mbssid; 4047 bool tf_trs; 4048 u32 macid_band_sel[4]; 4049 }; 4050 4051 struct rtw89_pkt_stat { 4052 u16 beacon_nr; 4053 u32 rx_rate_cnt[RTW89_HW_RATE_NR]; 4054 }; 4055 4056 DECLARE_EWMA(thermal, 4, 4); 4057 4058 struct rtw89_phy_stat { 4059 struct ewma_thermal avg_thermal[RF_PATH_MAX]; 4060 struct rtw89_pkt_stat cur_pkt_stat; 4061 struct rtw89_pkt_stat last_pkt_stat; 4062 }; 4063 4064 #define RTW89_DACK_PATH_NR 2 4065 #define RTW89_DACK_IDX_NR 2 4066 #define RTW89_DACK_MSBK_NR 16 4067 struct rtw89_dack_info { 4068 bool dack_done; 4069 u8 msbk_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR][RTW89_DACK_MSBK_NR]; 4070 u8 dadck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4071 u16 addck_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4072 u16 biask_d[RTW89_DACK_PATH_NR][RTW89_DACK_IDX_NR]; 4073 u32 dack_cnt; 4074 bool addck_timeout[RTW89_DACK_PATH_NR]; 4075 bool dadck_timeout[RTW89_DACK_PATH_NR]; 4076 bool msbk_timeout[RTW89_DACK_PATH_NR]; 4077 }; 4078 4079 #define RTW89_IQK_CHS_NR 2 4080 #define RTW89_IQK_PATH_NR 4 4081 4082 struct rtw89_rfk_mcc_info { 4083 u8 ch[RTW89_IQK_CHS_NR]; 4084 u8 band[RTW89_IQK_CHS_NR]; 4085 u8 table_idx; 4086 }; 4087 4088 struct rtw89_lck_info { 4089 u8 thermal[RF_PATH_MAX]; 4090 }; 4091 4092 struct rtw89_rx_dck_info { 4093 u8 thermal[RF_PATH_MAX]; 4094 }; 4095 4096 struct rtw89_iqk_info { 4097 bool lok_cor_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4098 bool lok_fin_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4099 bool lok_fail[RTW89_IQK_PATH_NR]; 4100 bool iqk_tx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4101 bool iqk_rx_fail[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4102 u32 iqk_fail_cnt; 4103 bool is_iqk_init; 4104 u32 iqk_channel[RTW89_IQK_CHS_NR]; 4105 u8 iqk_band[RTW89_IQK_PATH_NR]; 4106 u8 iqk_ch[RTW89_IQK_PATH_NR]; 4107 u8 iqk_bw[RTW89_IQK_PATH_NR]; 4108 u8 iqk_times; 4109 u8 version; 4110 u32 nb_txcfir[RTW89_IQK_PATH_NR]; 4111 u32 nb_rxcfir[RTW89_IQK_PATH_NR]; 4112 u32 bp_txkresult[RTW89_IQK_PATH_NR]; 4113 u32 bp_rxkresult[RTW89_IQK_PATH_NR]; 4114 u32 bp_iqkenable[RTW89_IQK_PATH_NR]; 4115 bool is_wb_txiqk[RTW89_IQK_PATH_NR]; 4116 bool is_wb_rxiqk[RTW89_IQK_PATH_NR]; 4117 bool is_nbiqk; 4118 bool iqk_fft_en; 4119 bool iqk_xym_en; 4120 bool iqk_sram_en; 4121 bool iqk_cfir_en; 4122 u32 syn1to2; 4123 u8 iqk_mcc_ch[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4124 u8 iqk_table_idx[RTW89_IQK_PATH_NR]; 4125 u32 lok_idac[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4126 u32 lok_vbuf[RTW89_IQK_CHS_NR][RTW89_IQK_PATH_NR]; 4127 }; 4128 4129 #define RTW89_DPK_RF_PATH 2 4130 #define RTW89_DPK_AVG_THERMAL_NUM 8 4131 #define RTW89_DPK_BKUP_NUM 2 4132 struct rtw89_dpk_bkup_para { 4133 enum rtw89_band band; 4134 enum rtw89_bandwidth bw; 4135 u8 ch; 4136 bool path_ok; 4137 u8 mdpd_en; 4138 u8 txagc_dpk; 4139 u8 ther_dpk; 4140 u8 gs; 4141 u16 pwsf; 4142 }; 4143 4144 struct rtw89_dpk_info { 4145 bool is_dpk_enable; 4146 bool is_dpk_reload_en; 4147 u8 dpk_gs[RTW89_PHY_MAX]; 4148 u16 dc_i[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4149 u16 dc_q[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4150 u8 corr_val[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4151 u8 corr_idx[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4152 u8 cur_idx[RTW89_DPK_RF_PATH]; 4153 u8 cur_k_set; 4154 struct rtw89_dpk_bkup_para bp[RTW89_DPK_RF_PATH][RTW89_DPK_BKUP_NUM]; 4155 }; 4156 4157 struct rtw89_fem_info { 4158 bool elna_2g; 4159 bool elna_5g; 4160 bool epa_2g; 4161 bool epa_5g; 4162 bool epa_6g; 4163 }; 4164 4165 struct rtw89_phy_ch_info { 4166 u8 rssi_min; 4167 u16 rssi_min_macid; 4168 u8 pre_rssi_min; 4169 u8 rssi_max; 4170 u16 rssi_max_macid; 4171 u8 rxsc_160; 4172 u8 rxsc_80; 4173 u8 rxsc_40; 4174 u8 rxsc_20; 4175 u8 rxsc_l; 4176 u8 is_noisy; 4177 }; 4178 4179 struct rtw89_agc_gaincode_set { 4180 u8 lna_idx; 4181 u8 tia_idx; 4182 u8 rxb_idx; 4183 }; 4184 4185 #define IGI_RSSI_TH_NUM 5 4186 #define FA_TH_NUM 4 4187 #define LNA_GAIN_NUM 7 4188 #define TIA_GAIN_NUM 2 4189 struct rtw89_dig_info { 4190 struct rtw89_agc_gaincode_set cur_gaincode; 4191 bool force_gaincode_idx_en; 4192 struct rtw89_agc_gaincode_set force_gaincode; 4193 u8 igi_rssi_th[IGI_RSSI_TH_NUM]; 4194 u16 fa_th[FA_TH_NUM]; 4195 u8 igi_rssi; 4196 u8 igi_fa_rssi; 4197 u8 fa_rssi_ofst; 4198 u8 dyn_igi_max; 4199 u8 dyn_igi_min; 4200 bool dyn_pd_th_en; 4201 u8 dyn_pd_th_max; 4202 u8 pd_low_th_ofst; 4203 u8 ib_pbk; 4204 s8 ib_pkpwr; 4205 s8 lna_gain_a[LNA_GAIN_NUM]; 4206 s8 lna_gain_g[LNA_GAIN_NUM]; 4207 s8 *lna_gain; 4208 s8 tia_gain_a[TIA_GAIN_NUM]; 4209 s8 tia_gain_g[TIA_GAIN_NUM]; 4210 s8 *tia_gain; 4211 bool is_linked_pre; 4212 bool bypass_dig; 4213 }; 4214 4215 enum rtw89_multi_cfo_mode { 4216 RTW89_PKT_BASED_AVG_MODE = 0, 4217 RTW89_ENTRY_BASED_AVG_MODE = 1, 4218 RTW89_TP_BASED_AVG_MODE = 2, 4219 }; 4220 4221 enum rtw89_phy_cfo_status { 4222 RTW89_PHY_DCFO_STATE_NORMAL = 0, 4223 RTW89_PHY_DCFO_STATE_ENHANCE = 1, 4224 RTW89_PHY_DCFO_STATE_HOLD = 2, 4225 RTW89_PHY_DCFO_STATE_MAX 4226 }; 4227 4228 enum rtw89_phy_cfo_ul_ofdma_acc_mode { 4229 RTW89_CFO_UL_OFDMA_ACC_DISABLE = 0, 4230 RTW89_CFO_UL_OFDMA_ACC_ENABLE = 1 4231 }; 4232 4233 struct rtw89_cfo_tracking_info { 4234 u16 cfo_timer_ms; 4235 bool cfo_trig_by_timer_en; 4236 enum rtw89_phy_cfo_status phy_cfo_status; 4237 enum rtw89_phy_cfo_ul_ofdma_acc_mode cfo_ul_ofdma_acc_mode; 4238 u8 phy_cfo_trk_cnt; 4239 bool is_adjust; 4240 enum rtw89_multi_cfo_mode rtw89_multi_cfo_mode; 4241 bool apply_compensation; 4242 u8 crystal_cap; 4243 u8 crystal_cap_default; 4244 u8 def_x_cap; 4245 s8 x_cap_ofst; 4246 u32 sta_cfo_tolerance; 4247 s32 cfo_tail[CFO_TRACK_MAX_USER]; 4248 u16 cfo_cnt[CFO_TRACK_MAX_USER]; 4249 s32 cfo_avg_pre; 4250 s32 cfo_avg[CFO_TRACK_MAX_USER]; 4251 s32 pre_cfo_avg[CFO_TRACK_MAX_USER]; 4252 s32 dcfo_avg; 4253 s32 dcfo_avg_pre; 4254 u32 packet_count; 4255 u32 packet_count_pre; 4256 s32 residual_cfo_acc; 4257 u8 phy_cfotrk_state; 4258 u8 phy_cfotrk_cnt; 4259 bool divergence_lock_en; 4260 u8 x_cap_lb; 4261 u8 x_cap_ub; 4262 u8 lock_cnt; 4263 }; 4264 4265 enum rtw89_tssi_alimk_band { 4266 TSSI_ALIMK_2G = 0, 4267 TSSI_ALIMK_5GL, 4268 TSSI_ALIMK_5GM, 4269 TSSI_ALIMK_5GH, 4270 TSSI_ALIMK_MAX 4271 }; 4272 4273 /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ 4274 #define TSSI_TRIM_CH_GROUP_NUM 8 4275 #define TSSI_TRIM_CH_GROUP_NUM_6G 16 4276 4277 #define TSSI_CCK_CH_GROUP_NUM 6 4278 #define TSSI_MCS_2G_CH_GROUP_NUM 5 4279 #define TSSI_MCS_5G_CH_GROUP_NUM 14 4280 #define TSSI_MCS_6G_CH_GROUP_NUM 32 4281 #define TSSI_MCS_CH_GROUP_NUM \ 4282 (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) 4283 #define TSSI_MAX_CH_NUM 67 4284 #define TSSI_ALIMK_VALUE_NUM 8 4285 4286 struct rtw89_tssi_info { 4287 u8 thermal[RF_PATH_MAX]; 4288 s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM]; 4289 s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G]; 4290 s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM]; 4291 s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM]; 4292 s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM]; 4293 s8 extra_ofst[RF_PATH_MAX]; 4294 bool tssi_tracking_check[RF_PATH_MAX]; 4295 u8 default_txagc_offset[RF_PATH_MAX]; 4296 u32 base_thermal[RF_PATH_MAX]; 4297 bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM]; 4298 u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM]; 4299 u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM]; 4300 bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX]; 4301 u32 tssi_alimk_time; 4302 }; 4303 4304 struct rtw89_power_trim_info { 4305 bool pg_thermal_trim; 4306 bool pg_pa_bias_trim; 4307 u8 thermal_trim[RF_PATH_MAX]; 4308 u8 pa_bias_trim[RF_PATH_MAX]; 4309 }; 4310 4311 struct rtw89_regd { 4312 char alpha2[3]; 4313 u8 txpwr_regd[RTW89_BAND_NUM]; 4314 }; 4315 4316 struct rtw89_regulatory_info { 4317 const struct rtw89_regd *regd; 4318 enum rtw89_reg_6ghz_power reg_6ghz_power; 4319 }; 4320 4321 enum rtw89_ifs_clm_application { 4322 RTW89_IFS_CLM_INIT = 0, 4323 RTW89_IFS_CLM_BACKGROUND = 1, 4324 RTW89_IFS_CLM_ACS = 2, 4325 RTW89_IFS_CLM_DIG = 3, 4326 RTW89_IFS_CLM_TDMA_DIG = 4, 4327 RTW89_IFS_CLM_DBG = 5, 4328 RTW89_IFS_CLM_DBG_MANUAL = 6 4329 }; 4330 4331 enum rtw89_env_racing_lv { 4332 RTW89_RAC_RELEASE = 0, 4333 RTW89_RAC_LV_1 = 1, 4334 RTW89_RAC_LV_2 = 2, 4335 RTW89_RAC_LV_3 = 3, 4336 RTW89_RAC_LV_4 = 4, 4337 RTW89_RAC_MAX_NUM = 5 4338 }; 4339 4340 struct rtw89_ccx_para_info { 4341 enum rtw89_env_racing_lv rac_lv; 4342 u16 mntr_time; 4343 u8 nhm_manual_th_ofst; 4344 u8 nhm_manual_th0; 4345 enum rtw89_ifs_clm_application ifs_clm_app; 4346 u32 ifs_clm_manual_th_times; 4347 u32 ifs_clm_manual_th0; 4348 u8 fahm_manual_th_ofst; 4349 u8 fahm_manual_th0; 4350 u8 fahm_numer_opt; 4351 u8 fahm_denom_opt; 4352 }; 4353 4354 enum rtw89_ccx_edcca_opt_sc_idx { 4355 RTW89_CCX_EDCCA_SEG0_P0 = 0, 4356 RTW89_CCX_EDCCA_SEG0_S1 = 1, 4357 RTW89_CCX_EDCCA_SEG0_S2 = 2, 4358 RTW89_CCX_EDCCA_SEG0_S3 = 3, 4359 RTW89_CCX_EDCCA_SEG1_P0 = 4, 4360 RTW89_CCX_EDCCA_SEG1_S1 = 5, 4361 RTW89_CCX_EDCCA_SEG1_S2 = 6, 4362 RTW89_CCX_EDCCA_SEG1_S3 = 7 4363 }; 4364 4365 enum rtw89_ccx_edcca_opt_bw_idx { 4366 RTW89_CCX_EDCCA_BW20_0 = 0, 4367 RTW89_CCX_EDCCA_BW20_1 = 1, 4368 RTW89_CCX_EDCCA_BW20_2 = 2, 4369 RTW89_CCX_EDCCA_BW20_3 = 3, 4370 RTW89_CCX_EDCCA_BW20_4 = 4, 4371 RTW89_CCX_EDCCA_BW20_5 = 5, 4372 RTW89_CCX_EDCCA_BW20_6 = 6, 4373 RTW89_CCX_EDCCA_BW20_7 = 7 4374 }; 4375 4376 #define RTW89_NHM_TH_NUM 11 4377 #define RTW89_FAHM_TH_NUM 11 4378 #define RTW89_NHM_RPT_NUM 12 4379 #define RTW89_FAHM_RPT_NUM 12 4380 #define RTW89_IFS_CLM_NUM 4 4381 struct rtw89_env_monitor_info { 4382 u8 ccx_watchdog_result; 4383 bool ccx_ongoing; 4384 u8 ccx_rac_lv; 4385 bool ccx_manual_ctrl; 4386 u16 ifs_clm_mntr_time; 4387 enum rtw89_ifs_clm_application ifs_clm_app; 4388 u16 ccx_period; 4389 u8 ccx_unit_idx; 4390 u16 ifs_clm_th_l[RTW89_IFS_CLM_NUM]; 4391 u16 ifs_clm_th_h[RTW89_IFS_CLM_NUM]; 4392 u16 ifs_clm_tx; 4393 u16 ifs_clm_edcca_excl_cca; 4394 u16 ifs_clm_ofdmfa; 4395 u16 ifs_clm_ofdmcca_excl_fa; 4396 u16 ifs_clm_cckfa; 4397 u16 ifs_clm_cckcca_excl_fa; 4398 u16 ifs_clm_total_ifs; 4399 u8 ifs_clm_his[RTW89_IFS_CLM_NUM]; 4400 u16 ifs_clm_avg[RTW89_IFS_CLM_NUM]; 4401 u16 ifs_clm_cca[RTW89_IFS_CLM_NUM]; 4402 u8 ifs_clm_tx_ratio; 4403 u8 ifs_clm_edcca_excl_cca_ratio; 4404 u8 ifs_clm_cck_fa_ratio; 4405 u8 ifs_clm_ofdm_fa_ratio; 4406 u8 ifs_clm_cck_cca_excl_fa_ratio; 4407 u8 ifs_clm_ofdm_cca_excl_fa_ratio; 4408 u16 ifs_clm_cck_fa_permil; 4409 u16 ifs_clm_ofdm_fa_permil; 4410 u32 ifs_clm_ifs_avg[RTW89_IFS_CLM_NUM]; 4411 u32 ifs_clm_cca_avg[RTW89_IFS_CLM_NUM]; 4412 }; 4413 4414 enum rtw89_ser_rcvy_step { 4415 RTW89_SER_DRV_STOP_TX, 4416 RTW89_SER_DRV_STOP_RX, 4417 RTW89_SER_DRV_STOP_RUN, 4418 RTW89_SER_HAL_STOP_DMA, 4419 RTW89_SER_SUPPRESS_LOG, 4420 RTW89_NUM_OF_SER_FLAGS 4421 }; 4422 4423 struct rtw89_ser { 4424 u8 state; 4425 u8 alarm_event; 4426 bool prehandle_l1; 4427 4428 struct work_struct ser_hdl_work; 4429 struct delayed_work ser_alarm_work; 4430 const struct state_ent *st_tbl; 4431 const struct event_ent *ev_tbl; 4432 struct list_head msg_q; 4433 spinlock_t msg_q_lock; /* lock when read/write ser msg */ 4434 DECLARE_BITMAP(flags, RTW89_NUM_OF_SER_FLAGS); 4435 }; 4436 4437 enum rtw89_mac_ax_ps_mode { 4438 RTW89_MAC_AX_PS_MODE_ACTIVE = 0, 4439 RTW89_MAC_AX_PS_MODE_LEGACY = 1, 4440 RTW89_MAC_AX_PS_MODE_WMMPS = 2, 4441 RTW89_MAC_AX_PS_MODE_MAX = 3, 4442 }; 4443 4444 enum rtw89_last_rpwm_mode { 4445 RTW89_LAST_RPWM_PS = 0x0, 4446 RTW89_LAST_RPWM_ACTIVE = 0x6, 4447 }; 4448 4449 struct rtw89_lps_parm { 4450 u8 macid; 4451 u8 psmode; /* enum rtw89_mac_ax_ps_mode */ 4452 u8 lastrpwm; /* enum rtw89_last_rpwm_mode */ 4453 }; 4454 4455 struct rtw89_ppdu_sts_info { 4456 struct sk_buff_head rx_queue[RTW89_PHY_MAX]; 4457 u8 curr_rx_ppdu_cnt[RTW89_PHY_MAX]; 4458 }; 4459 4460 struct rtw89_early_h2c { 4461 struct list_head list; 4462 u8 *h2c; 4463 u16 h2c_len; 4464 }; 4465 4466 struct rtw89_hw_scan_info { 4467 struct ieee80211_vif *scanning_vif; 4468 struct list_head pkt_list[NUM_NL80211_BANDS]; 4469 struct rtw89_chan op_chan; 4470 u32 last_chan_idx; 4471 }; 4472 4473 enum rtw89_phy_bb_gain_band { 4474 RTW89_BB_GAIN_BAND_2G = 0, 4475 RTW89_BB_GAIN_BAND_5G_L = 1, 4476 RTW89_BB_GAIN_BAND_5G_M = 2, 4477 RTW89_BB_GAIN_BAND_5G_H = 3, 4478 RTW89_BB_GAIN_BAND_6G_L = 4, 4479 RTW89_BB_GAIN_BAND_6G_M = 5, 4480 RTW89_BB_GAIN_BAND_6G_H = 6, 4481 RTW89_BB_GAIN_BAND_6G_UH = 7, 4482 4483 RTW89_BB_GAIN_BAND_NR, 4484 }; 4485 4486 enum rtw89_phy_bb_rxsc_num { 4487 RTW89_BB_RXSC_NUM_40 = 9, /* SC: 0, 1~8 */ 4488 RTW89_BB_RXSC_NUM_80 = 13, /* SC: 0, 1~8, 9~12 */ 4489 RTW89_BB_RXSC_NUM_160 = 15, /* SC: 0, 1~8, 9~12, 13~14 */ 4490 }; 4491 4492 struct rtw89_phy_bb_gain_info { 4493 s8 lna_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4494 s8 tia_gain[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][TIA_GAIN_NUM]; 4495 s8 lna_gain_bypass[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4496 s8 lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX][LNA_GAIN_NUM]; 4497 s8 tia_lna_op1db[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4498 [LNA_GAIN_NUM + 1]; /* TIA0_LNA0~6 + TIA1_LNA6 */ 4499 s8 rpl_ofst_20[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX]; 4500 s8 rpl_ofst_40[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4501 [RTW89_BB_RXSC_NUM_40]; 4502 s8 rpl_ofst_80[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4503 [RTW89_BB_RXSC_NUM_80]; 4504 s8 rpl_ofst_160[RTW89_BB_GAIN_BAND_NR][RF_PATH_MAX] 4505 [RTW89_BB_RXSC_NUM_160]; 4506 }; 4507 4508 struct rtw89_phy_efuse_gain { 4509 bool offset_valid; 4510 bool comp_valid; 4511 s8 offset[RF_PATH_MAX][RTW89_GAIN_OFFSET_NR]; /* S(8, 0) */ 4512 s8 offset_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4513 s8 rssi_base[RTW89_PHY_MAX]; /* S(8, 4) */ 4514 s8 comp[RF_PATH_MAX][RTW89_SUBBAND_NR]; /* S(8, 0) */ 4515 }; 4516 4517 #define RTW89_MAX_PATTERN_NUM 18 4518 #define RTW89_MAX_PATTERN_MASK_SIZE 4 4519 #define RTW89_MAX_PATTERN_SIZE 128 4520 4521 struct rtw89_wow_cam_info { 4522 bool r_w; 4523 u8 idx; 4524 u32 mask[RTW89_MAX_PATTERN_MASK_SIZE]; 4525 u16 crc; 4526 bool negative_pattern_match; 4527 bool skip_mac_hdr; 4528 bool uc; 4529 bool mc; 4530 bool bc; 4531 bool valid; 4532 }; 4533 4534 struct rtw89_wow_param { 4535 struct ieee80211_vif *wow_vif; 4536 DECLARE_BITMAP(flags, RTW89_WOW_FLAG_NUM); 4537 struct rtw89_wow_cam_info patterns[RTW89_MAX_PATTERN_NUM]; 4538 u8 pattern_cnt; 4539 }; 4540 4541 struct rtw89_mcc_limit { 4542 bool enable; 4543 u16 max_tob; /* TU; max time offset behind */ 4544 u16 max_toa; /* TU; max time offset ahead */ 4545 u16 max_dur; /* TU */ 4546 }; 4547 4548 struct rtw89_mcc_policy { 4549 u8 c2h_rpt; 4550 u8 tx_null_early; 4551 u8 dis_tx_null; 4552 u8 in_curr_ch; 4553 u8 dis_sw_retry; 4554 u8 sw_retry_count; 4555 }; 4556 4557 struct rtw89_mcc_role { 4558 struct rtw89_vif *rtwvif; 4559 struct rtw89_mcc_policy policy; 4560 struct rtw89_mcc_limit limit; 4561 4562 /* byte-array in LE order for FW */ 4563 u8 macid_bitmap[BITS_TO_BYTES(RTW89_MAX_MAC_ID_NUM)]; 4564 4565 u16 duration; /* TU */ 4566 u16 beacon_interval; /* TU */ 4567 bool is_2ghz; 4568 bool is_go; 4569 bool is_gc; 4570 }; 4571 4572 struct rtw89_mcc_bt_role { 4573 u16 duration; /* TU */ 4574 }; 4575 4576 struct rtw89_mcc_courtesy { 4577 bool enable; 4578 u8 slot_num; 4579 u8 macid_src; 4580 u8 macid_tgt; 4581 }; 4582 4583 enum rtw89_mcc_plan { 4584 RTW89_MCC_PLAN_TAIL_BT, 4585 RTW89_MCC_PLAN_MID_BT, 4586 RTW89_MCC_PLAN_NO_BT, 4587 4588 NUM_OF_RTW89_MCC_PLAN, 4589 }; 4590 4591 struct rtw89_mcc_pattern { 4592 s16 tob_ref; /* TU; time offset behind of reference role */ 4593 s16 toa_ref; /* TU; time offset ahead of reference role */ 4594 s16 tob_aux; /* TU; time offset behind of auxiliary role */ 4595 s16 toa_aux; /* TU; time offset ahead of auxiliary role */ 4596 4597 enum rtw89_mcc_plan plan; 4598 struct rtw89_mcc_courtesy courtesy; 4599 }; 4600 4601 struct rtw89_mcc_sync { 4602 bool enable; 4603 u16 offset; /* TU */ 4604 u8 macid_src; 4605 u8 macid_tgt; 4606 }; 4607 4608 struct rtw89_mcc_config { 4609 struct rtw89_mcc_pattern pattern; 4610 struct rtw89_mcc_sync sync; 4611 u64 start_tsf; 4612 u16 mcc_interval; /* TU */ 4613 u16 beacon_offset; /* TU */ 4614 }; 4615 4616 enum rtw89_mcc_mode { 4617 RTW89_MCC_MODE_GO_STA, 4618 RTW89_MCC_MODE_GC_STA, 4619 }; 4620 4621 struct rtw89_mcc_info { 4622 struct rtw89_wait_info wait; 4623 4624 u8 group; 4625 enum rtw89_mcc_mode mode; 4626 struct rtw89_mcc_role role_ref; /* reference role */ 4627 struct rtw89_mcc_role role_aux; /* auxiliary role */ 4628 struct rtw89_mcc_bt_role bt_role; 4629 struct rtw89_mcc_config config; 4630 }; 4631 4632 struct rtw89_dev { 4633 struct ieee80211_hw *hw; 4634 struct device *dev; 4635 const struct ieee80211_ops *ops; 4636 4637 bool dbcc_en; 4638 struct rtw89_hw_scan_info scan_info; 4639 const struct rtw89_chip_info *chip; 4640 const struct rtw89_pci_info *pci_info; 4641 const struct rtw89_rfe_parms *rfe_parms; 4642 struct rtw89_hal hal; 4643 struct rtw89_mcc_info mcc; 4644 struct rtw89_mac_info mac; 4645 struct rtw89_fw_info fw; 4646 struct rtw89_hci_info hci; 4647 struct rtw89_efuse efuse; 4648 struct rtw89_traffic_stats stats; 4649 struct rtw89_rfe_data *rfe_data; 4650 4651 /* ensures exclusive access from mac80211 callbacks */ 4652 struct mutex mutex; 4653 struct list_head rtwvifs_list; 4654 /* used to protect rf read write */ 4655 struct mutex rf_mutex; 4656 struct workqueue_struct *txq_wq; 4657 struct work_struct txq_work; 4658 struct delayed_work txq_reinvoke_work; 4659 /* used to protect ba_list and forbid_ba_list */ 4660 spinlock_t ba_lock; 4661 /* txqs to setup ba session */ 4662 struct list_head ba_list; 4663 /* txqs to forbid ba session */ 4664 struct list_head forbid_ba_list; 4665 struct work_struct ba_work; 4666 /* used to protect rpwm */ 4667 spinlock_t rpwm_lock; 4668 4669 struct rtw89_cam_info cam_info; 4670 4671 struct sk_buff_head c2h_queue; 4672 struct work_struct c2h_work; 4673 struct work_struct ips_work; 4674 struct work_struct load_firmware_work; 4675 struct work_struct cancel_6ghz_probe_work; 4676 4677 struct list_head early_h2c_list; 4678 4679 struct rtw89_ser ser; 4680 4681 DECLARE_BITMAP(hw_port, RTW89_PORT_NUM); 4682 DECLARE_BITMAP(mac_id_map, RTW89_MAX_MAC_ID_NUM); 4683 DECLARE_BITMAP(flags, NUM_OF_RTW89_FLAGS); 4684 DECLARE_BITMAP(pkt_offload, RTW89_MAX_PKT_OFLD_NUM); 4685 4686 struct rtw89_phy_stat phystat; 4687 struct rtw89_dack_info dack; 4688 struct rtw89_iqk_info iqk; 4689 struct rtw89_dpk_info dpk; 4690 struct rtw89_rfk_mcc_info rfk_mcc; 4691 struct rtw89_lck_info lck; 4692 struct rtw89_rx_dck_info rx_dck; 4693 bool is_tssi_mode[RF_PATH_MAX]; 4694 bool is_bt_iqk_timeout; 4695 4696 struct rtw89_fem_info fem; 4697 struct rtw89_txpwr_byrate byr[RTW89_BAND_NUM][RTW89_BYR_BW_NUM]; 4698 struct rtw89_tssi_info tssi; 4699 struct rtw89_power_trim_info pwr_trim; 4700 4701 struct rtw89_cfo_tracking_info cfo_tracking; 4702 struct rtw89_env_monitor_info env_monitor; 4703 struct rtw89_dig_info dig; 4704 struct rtw89_phy_ch_info ch_info; 4705 struct rtw89_phy_bb_gain_info bb_gain; 4706 struct rtw89_phy_efuse_gain efuse_gain; 4707 struct rtw89_phy_ul_tb_info ul_tb_info; 4708 struct rtw89_antdiv_info antdiv; 4709 4710 struct delayed_work track_work; 4711 struct delayed_work chanctx_work; 4712 struct delayed_work coex_act1_work; 4713 struct delayed_work coex_bt_devinfo_work; 4714 struct delayed_work coex_rfk_chk_work; 4715 struct delayed_work cfo_track_work; 4716 struct delayed_work forbid_ba_work; 4717 struct delayed_work roc_work; 4718 struct delayed_work antdiv_work; 4719 struct rtw89_ppdu_sts_info ppdu_sts; 4720 u8 total_sta_assoc; 4721 bool scanning; 4722 4723 struct rtw89_regulatory_info regulatory; 4724 struct rtw89_sar_info sar; 4725 struct rtw89_tas_info tas; 4726 4727 struct rtw89_btc btc; 4728 enum rtw89_ps_mode ps_mode; 4729 bool lps_enabled; 4730 4731 struct rtw89_wow_param wow; 4732 4733 /* napi structure */ 4734 struct net_device netdev; 4735 struct napi_struct napi; 4736 int napi_budget_countdown; 4737 4738 /* HCI related data, keep last */ 4739 u8 priv[] __aligned(sizeof(void *)); 4740 }; 4741 4742 static inline int rtw89_hci_tx_write(struct rtw89_dev *rtwdev, 4743 struct rtw89_core_tx_request *tx_req) 4744 { 4745 return rtwdev->hci.ops->tx_write(rtwdev, tx_req); 4746 } 4747 4748 static inline void rtw89_hci_reset(struct rtw89_dev *rtwdev) 4749 { 4750 rtwdev->hci.ops->reset(rtwdev); 4751 } 4752 4753 static inline int rtw89_hci_start(struct rtw89_dev *rtwdev) 4754 { 4755 return rtwdev->hci.ops->start(rtwdev); 4756 } 4757 4758 static inline void rtw89_hci_stop(struct rtw89_dev *rtwdev) 4759 { 4760 rtwdev->hci.ops->stop(rtwdev); 4761 } 4762 4763 static inline int rtw89_hci_deinit(struct rtw89_dev *rtwdev) 4764 { 4765 return rtwdev->hci.ops->deinit(rtwdev); 4766 } 4767 4768 static inline void rtw89_hci_pause(struct rtw89_dev *rtwdev, bool pause) 4769 { 4770 rtwdev->hci.ops->pause(rtwdev, pause); 4771 } 4772 4773 static inline void rtw89_hci_switch_mode(struct rtw89_dev *rtwdev, bool low_power) 4774 { 4775 rtwdev->hci.ops->switch_mode(rtwdev, low_power); 4776 } 4777 4778 static inline void rtw89_hci_recalc_int_mit(struct rtw89_dev *rtwdev) 4779 { 4780 rtwdev->hci.ops->recalc_int_mit(rtwdev); 4781 } 4782 4783 static inline u32 rtw89_hci_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 txch) 4784 { 4785 return rtwdev->hci.ops->check_and_reclaim_tx_resource(rtwdev, txch); 4786 } 4787 4788 static inline void rtw89_hci_tx_kick_off(struct rtw89_dev *rtwdev, u8 txch) 4789 { 4790 return rtwdev->hci.ops->tx_kick_off(rtwdev, txch); 4791 } 4792 4793 static inline void rtw89_hci_flush_queues(struct rtw89_dev *rtwdev, u32 queues, 4794 bool drop) 4795 { 4796 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4797 return; 4798 4799 if (rtwdev->hci.ops->flush_queues) 4800 return rtwdev->hci.ops->flush_queues(rtwdev, queues, drop); 4801 } 4802 4803 static inline void rtw89_hci_recovery_start(struct rtw89_dev *rtwdev) 4804 { 4805 if (rtwdev->hci.ops->recovery_start) 4806 rtwdev->hci.ops->recovery_start(rtwdev); 4807 } 4808 4809 static inline void rtw89_hci_recovery_complete(struct rtw89_dev *rtwdev) 4810 { 4811 if (rtwdev->hci.ops->recovery_complete) 4812 rtwdev->hci.ops->recovery_complete(rtwdev); 4813 } 4814 4815 static inline void rtw89_hci_enable_intr(struct rtw89_dev *rtwdev) 4816 { 4817 if (rtwdev->hci.ops->enable_intr) 4818 rtwdev->hci.ops->enable_intr(rtwdev); 4819 } 4820 4821 static inline void rtw89_hci_disable_intr(struct rtw89_dev *rtwdev) 4822 { 4823 if (rtwdev->hci.ops->disable_intr) 4824 rtwdev->hci.ops->disable_intr(rtwdev); 4825 } 4826 4827 static inline void rtw89_hci_ctrl_txdma_ch(struct rtw89_dev *rtwdev, bool enable) 4828 { 4829 if (rtwdev->hci.ops->ctrl_txdma_ch) 4830 rtwdev->hci.ops->ctrl_txdma_ch(rtwdev, enable); 4831 } 4832 4833 static inline void rtw89_hci_ctrl_txdma_fw_ch(struct rtw89_dev *rtwdev, bool enable) 4834 { 4835 if (rtwdev->hci.ops->ctrl_txdma_fw_ch) 4836 rtwdev->hci.ops->ctrl_txdma_fw_ch(rtwdev, enable); 4837 } 4838 4839 static inline void rtw89_hci_ctrl_trxhci(struct rtw89_dev *rtwdev, bool enable) 4840 { 4841 if (rtwdev->hci.ops->ctrl_trxhci) 4842 rtwdev->hci.ops->ctrl_trxhci(rtwdev, enable); 4843 } 4844 4845 static inline int rtw89_hci_poll_txdma_ch(struct rtw89_dev *rtwdev) 4846 { 4847 int ret = 0; 4848 4849 if (rtwdev->hci.ops->poll_txdma_ch) 4850 ret = rtwdev->hci.ops->poll_txdma_ch(rtwdev); 4851 return ret; 4852 } 4853 4854 static inline void rtw89_hci_clr_idx_all(struct rtw89_dev *rtwdev) 4855 { 4856 if (rtwdev->hci.ops->clr_idx_all) 4857 rtwdev->hci.ops->clr_idx_all(rtwdev); 4858 } 4859 4860 static inline int rtw89_hci_rst_bdram(struct rtw89_dev *rtwdev) 4861 { 4862 int ret = 0; 4863 4864 if (rtwdev->hci.ops->rst_bdram) 4865 ret = rtwdev->hci.ops->rst_bdram(rtwdev); 4866 return ret; 4867 } 4868 4869 static inline void rtw89_hci_clear(struct rtw89_dev *rtwdev, struct pci_dev *pdev) 4870 { 4871 if (rtwdev->hci.ops->clear) 4872 rtwdev->hci.ops->clear(rtwdev, pdev); 4873 } 4874 4875 static inline 4876 struct rtw89_tx_skb_data *RTW89_TX_SKB_CB(struct sk_buff *skb) 4877 { 4878 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 4879 4880 return (struct rtw89_tx_skb_data *)info->status.status_driver_data; 4881 } 4882 4883 static inline u8 rtw89_read8(struct rtw89_dev *rtwdev, u32 addr) 4884 { 4885 return rtwdev->hci.ops->read8(rtwdev, addr); 4886 } 4887 4888 static inline u16 rtw89_read16(struct rtw89_dev *rtwdev, u32 addr) 4889 { 4890 return rtwdev->hci.ops->read16(rtwdev, addr); 4891 } 4892 4893 static inline u32 rtw89_read32(struct rtw89_dev *rtwdev, u32 addr) 4894 { 4895 return rtwdev->hci.ops->read32(rtwdev, addr); 4896 } 4897 4898 static inline void rtw89_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) 4899 { 4900 rtwdev->hci.ops->write8(rtwdev, addr, data); 4901 } 4902 4903 static inline void rtw89_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) 4904 { 4905 rtwdev->hci.ops->write16(rtwdev, addr, data); 4906 } 4907 4908 static inline void rtw89_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) 4909 { 4910 rtwdev->hci.ops->write32(rtwdev, addr, data); 4911 } 4912 4913 static inline void 4914 rtw89_write8_set(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4915 { 4916 u8 val; 4917 4918 val = rtw89_read8(rtwdev, addr); 4919 rtw89_write8(rtwdev, addr, val | bit); 4920 } 4921 4922 static inline void 4923 rtw89_write16_set(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4924 { 4925 u16 val; 4926 4927 val = rtw89_read16(rtwdev, addr); 4928 rtw89_write16(rtwdev, addr, val | bit); 4929 } 4930 4931 static inline void 4932 rtw89_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4933 { 4934 u32 val; 4935 4936 val = rtw89_read32(rtwdev, addr); 4937 rtw89_write32(rtwdev, addr, val | bit); 4938 } 4939 4940 static inline void 4941 rtw89_write8_clr(struct rtw89_dev *rtwdev, u32 addr, u8 bit) 4942 { 4943 u8 val; 4944 4945 val = rtw89_read8(rtwdev, addr); 4946 rtw89_write8(rtwdev, addr, val & ~bit); 4947 } 4948 4949 static inline void 4950 rtw89_write16_clr(struct rtw89_dev *rtwdev, u32 addr, u16 bit) 4951 { 4952 u16 val; 4953 4954 val = rtw89_read16(rtwdev, addr); 4955 rtw89_write16(rtwdev, addr, val & ~bit); 4956 } 4957 4958 static inline void 4959 rtw89_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bit) 4960 { 4961 u32 val; 4962 4963 val = rtw89_read32(rtwdev, addr); 4964 rtw89_write32(rtwdev, addr, val & ~bit); 4965 } 4966 4967 static inline u32 4968 rtw89_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4969 { 4970 u32 shift = __ffs(mask); 4971 u32 orig; 4972 u32 ret; 4973 4974 orig = rtw89_read32(rtwdev, addr); 4975 ret = (orig & mask) >> shift; 4976 4977 return ret; 4978 } 4979 4980 static inline u16 4981 rtw89_read16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4982 { 4983 u32 shift = __ffs(mask); 4984 u32 orig; 4985 u32 ret; 4986 4987 orig = rtw89_read16(rtwdev, addr); 4988 ret = (orig & mask) >> shift; 4989 4990 return ret; 4991 } 4992 4993 static inline u8 4994 rtw89_read8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) 4995 { 4996 u32 shift = __ffs(mask); 4997 u32 orig; 4998 u32 ret; 4999 5000 orig = rtw89_read8(rtwdev, addr); 5001 ret = (orig & mask) >> shift; 5002 5003 return ret; 5004 } 5005 5006 static inline void 5007 rtw89_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) 5008 { 5009 u32 shift = __ffs(mask); 5010 u32 orig; 5011 u32 set; 5012 5013 WARN(addr & 0x3, "should be 4-byte aligned, addr = 0x%08x\n", addr); 5014 5015 orig = rtw89_read32(rtwdev, addr); 5016 set = (orig & ~mask) | ((data << shift) & mask); 5017 rtw89_write32(rtwdev, addr, set); 5018 } 5019 5020 static inline void 5021 rtw89_write16_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u16 data) 5022 { 5023 u32 shift; 5024 u16 orig, set; 5025 5026 mask &= 0xffff; 5027 shift = __ffs(mask); 5028 5029 orig = rtw89_read16(rtwdev, addr); 5030 set = (orig & ~mask) | ((data << shift) & mask); 5031 rtw89_write16(rtwdev, addr, set); 5032 } 5033 5034 static inline void 5035 rtw89_write8_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u8 data) 5036 { 5037 u32 shift; 5038 u8 orig, set; 5039 5040 mask &= 0xff; 5041 shift = __ffs(mask); 5042 5043 orig = rtw89_read8(rtwdev, addr); 5044 set = (orig & ~mask) | ((data << shift) & mask); 5045 rtw89_write8(rtwdev, addr, set); 5046 } 5047 5048 static inline u32 5049 rtw89_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5050 u32 addr, u32 mask) 5051 { 5052 u32 val; 5053 5054 mutex_lock(&rtwdev->rf_mutex); 5055 val = rtwdev->chip->ops->read_rf(rtwdev, rf_path, addr, mask); 5056 mutex_unlock(&rtwdev->rf_mutex); 5057 5058 return val; 5059 } 5060 5061 static inline void 5062 rtw89_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, 5063 u32 addr, u32 mask, u32 data) 5064 { 5065 mutex_lock(&rtwdev->rf_mutex); 5066 rtwdev->chip->ops->write_rf(rtwdev, rf_path, addr, mask, data); 5067 mutex_unlock(&rtwdev->rf_mutex); 5068 } 5069 5070 static inline struct ieee80211_txq *rtw89_txq_to_txq(struct rtw89_txq *rtwtxq) 5071 { 5072 void *p = rtwtxq; 5073 5074 return container_of(p, struct ieee80211_txq, drv_priv); 5075 } 5076 5077 static inline void rtw89_core_txq_init(struct rtw89_dev *rtwdev, 5078 struct ieee80211_txq *txq) 5079 { 5080 struct rtw89_txq *rtwtxq; 5081 5082 if (!txq) 5083 return; 5084 5085 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 5086 INIT_LIST_HEAD(&rtwtxq->list); 5087 } 5088 5089 static inline struct ieee80211_vif *rtwvif_to_vif(struct rtw89_vif *rtwvif) 5090 { 5091 void *p = rtwvif; 5092 5093 return container_of(p, struct ieee80211_vif, drv_priv); 5094 } 5095 5096 static inline struct ieee80211_vif *rtwvif_to_vif_safe(struct rtw89_vif *rtwvif) 5097 { 5098 return rtwvif ? rtwvif_to_vif(rtwvif) : NULL; 5099 } 5100 5101 static inline struct rtw89_vif *vif_to_rtwvif_safe(struct ieee80211_vif *vif) 5102 { 5103 return vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 5104 } 5105 5106 static inline struct ieee80211_sta *rtwsta_to_sta(struct rtw89_sta *rtwsta) 5107 { 5108 void *p = rtwsta; 5109 5110 return container_of(p, struct ieee80211_sta, drv_priv); 5111 } 5112 5113 static inline struct ieee80211_sta *rtwsta_to_sta_safe(struct rtw89_sta *rtwsta) 5114 { 5115 return rtwsta ? rtwsta_to_sta(rtwsta) : NULL; 5116 } 5117 5118 static inline struct rtw89_sta *sta_to_rtwsta_safe(struct ieee80211_sta *sta) 5119 { 5120 return sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 5121 } 5122 5123 static inline u8 rtw89_hw_to_rate_info_bw(enum rtw89_bandwidth hw_bw) 5124 { 5125 if (hw_bw == RTW89_CHANNEL_WIDTH_160) 5126 return RATE_INFO_BW_160; 5127 else if (hw_bw == RTW89_CHANNEL_WIDTH_80) 5128 return RATE_INFO_BW_80; 5129 else if (hw_bw == RTW89_CHANNEL_WIDTH_40) 5130 return RATE_INFO_BW_40; 5131 else 5132 return RATE_INFO_BW_20; 5133 } 5134 5135 static inline 5136 enum nl80211_band rtw89_hw_to_nl80211_band(enum rtw89_band hw_band) 5137 { 5138 switch (hw_band) { 5139 default: 5140 case RTW89_BAND_2G: 5141 return NL80211_BAND_2GHZ; 5142 case RTW89_BAND_5G: 5143 return NL80211_BAND_5GHZ; 5144 case RTW89_BAND_6G: 5145 return NL80211_BAND_6GHZ; 5146 } 5147 } 5148 5149 static inline 5150 enum rtw89_band rtw89_nl80211_to_hw_band(enum nl80211_band nl_band) 5151 { 5152 switch (nl_band) { 5153 default: 5154 case NL80211_BAND_2GHZ: 5155 return RTW89_BAND_2G; 5156 case NL80211_BAND_5GHZ: 5157 return RTW89_BAND_5G; 5158 case NL80211_BAND_6GHZ: 5159 return RTW89_BAND_6G; 5160 } 5161 } 5162 5163 static inline 5164 enum rtw89_bandwidth nl_to_rtw89_bandwidth(enum nl80211_chan_width width) 5165 { 5166 switch (width) { 5167 default: 5168 WARN(1, "Not support bandwidth %d\n", width); 5169 fallthrough; 5170 case NL80211_CHAN_WIDTH_20_NOHT: 5171 case NL80211_CHAN_WIDTH_20: 5172 return RTW89_CHANNEL_WIDTH_20; 5173 case NL80211_CHAN_WIDTH_40: 5174 return RTW89_CHANNEL_WIDTH_40; 5175 case NL80211_CHAN_WIDTH_80: 5176 return RTW89_CHANNEL_WIDTH_80; 5177 case NL80211_CHAN_WIDTH_160: 5178 return RTW89_CHANNEL_WIDTH_160; 5179 } 5180 } 5181 5182 static inline 5183 enum nl80211_he_ru_alloc rtw89_he_rua_to_ru_alloc(u16 rua) 5184 { 5185 switch (rua) { 5186 default: 5187 WARN(1, "Invalid RU allocation: %d\n", rua); 5188 fallthrough; 5189 case 0 ... 36: 5190 return NL80211_RATE_INFO_HE_RU_ALLOC_26; 5191 case 37 ... 52: 5192 return NL80211_RATE_INFO_HE_RU_ALLOC_52; 5193 case 53 ... 60: 5194 return NL80211_RATE_INFO_HE_RU_ALLOC_106; 5195 case 61 ... 64: 5196 return NL80211_RATE_INFO_HE_RU_ALLOC_242; 5197 case 65 ... 66: 5198 return NL80211_RATE_INFO_HE_RU_ALLOC_484; 5199 case 67: 5200 return NL80211_RATE_INFO_HE_RU_ALLOC_996; 5201 case 68: 5202 return NL80211_RATE_INFO_HE_RU_ALLOC_2x996; 5203 } 5204 } 5205 5206 static inline 5207 struct rtw89_addr_cam_entry *rtw89_get_addr_cam_of(struct rtw89_vif *rtwvif, 5208 struct rtw89_sta *rtwsta) 5209 { 5210 if (rtwsta) { 5211 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5212 5213 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || sta->tdls) 5214 return &rtwsta->addr_cam; 5215 } 5216 return &rtwvif->addr_cam; 5217 } 5218 5219 static inline 5220 struct rtw89_bssid_cam_entry *rtw89_get_bssid_cam_of(struct rtw89_vif *rtwvif, 5221 struct rtw89_sta *rtwsta) 5222 { 5223 if (rtwsta) { 5224 struct ieee80211_sta *sta = rtwsta_to_sta(rtwsta); 5225 5226 if (sta->tdls) 5227 return &rtwsta->bssid_cam; 5228 } 5229 return &rtwvif->bssid_cam; 5230 } 5231 5232 static inline 5233 void rtw89_chip_set_channel_prepare(struct rtw89_dev *rtwdev, 5234 struct rtw89_channel_help_params *p, 5235 const struct rtw89_chan *chan, 5236 enum rtw89_mac_idx mac_idx, 5237 enum rtw89_phy_idx phy_idx) 5238 { 5239 rtwdev->chip->ops->set_channel_help(rtwdev, true, p, chan, 5240 mac_idx, phy_idx); 5241 } 5242 5243 static inline 5244 void rtw89_chip_set_channel_done(struct rtw89_dev *rtwdev, 5245 struct rtw89_channel_help_params *p, 5246 const struct rtw89_chan *chan, 5247 enum rtw89_mac_idx mac_idx, 5248 enum rtw89_phy_idx phy_idx) 5249 { 5250 rtwdev->chip->ops->set_channel_help(rtwdev, false, p, chan, 5251 mac_idx, phy_idx); 5252 } 5253 5254 static inline 5255 const struct cfg80211_chan_def *rtw89_chandef_get(struct rtw89_dev *rtwdev, 5256 enum rtw89_sub_entity_idx idx) 5257 { 5258 struct rtw89_hal *hal = &rtwdev->hal; 5259 enum rtw89_sub_entity_idx roc_idx = atomic_read(&hal->roc_entity_idx); 5260 5261 if (roc_idx == idx) 5262 return &hal->roc_chandef; 5263 5264 return &hal->sub[idx].chandef; 5265 } 5266 5267 static inline 5268 const struct rtw89_chan *rtw89_chan_get(struct rtw89_dev *rtwdev, 5269 enum rtw89_sub_entity_idx idx) 5270 { 5271 struct rtw89_hal *hal = &rtwdev->hal; 5272 5273 return &hal->sub[idx].chan; 5274 } 5275 5276 static inline 5277 const struct rtw89_chan_rcd *rtw89_chan_rcd_get(struct rtw89_dev *rtwdev, 5278 enum rtw89_sub_entity_idx idx) 5279 { 5280 struct rtw89_hal *hal = &rtwdev->hal; 5281 5282 return &hal->sub[idx].rcd; 5283 } 5284 5285 static inline 5286 const struct rtw89_chan *rtw89_scan_chan_get(struct rtw89_dev *rtwdev) 5287 { 5288 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 5289 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 5290 5291 if (rtwvif) 5292 return rtw89_chan_get(rtwdev, rtwvif->sub_entity_idx); 5293 else 5294 return rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 5295 } 5296 5297 static inline void rtw89_chip_fem_setup(struct rtw89_dev *rtwdev) 5298 { 5299 const struct rtw89_chip_info *chip = rtwdev->chip; 5300 5301 if (chip->ops->fem_setup) 5302 chip->ops->fem_setup(rtwdev); 5303 } 5304 5305 static inline void rtw89_chip_rfe_gpio(struct rtw89_dev *rtwdev) 5306 { 5307 const struct rtw89_chip_info *chip = rtwdev->chip; 5308 5309 if (chip->ops->rfe_gpio) 5310 chip->ops->rfe_gpio(rtwdev); 5311 } 5312 5313 static inline 5314 void rtw89_chip_bb_preinit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5315 { 5316 const struct rtw89_chip_info *chip = rtwdev->chip; 5317 5318 if (chip->ops->bb_preinit) 5319 chip->ops->bb_preinit(rtwdev, phy_idx); 5320 } 5321 5322 static inline void rtw89_chip_bb_sethw(struct rtw89_dev *rtwdev) 5323 { 5324 const struct rtw89_chip_info *chip = rtwdev->chip; 5325 5326 if (chip->ops->bb_sethw) 5327 chip->ops->bb_sethw(rtwdev); 5328 } 5329 5330 static inline void rtw89_chip_rfk_init(struct rtw89_dev *rtwdev) 5331 { 5332 const struct rtw89_chip_info *chip = rtwdev->chip; 5333 5334 if (chip->ops->rfk_init) 5335 chip->ops->rfk_init(rtwdev); 5336 } 5337 5338 static inline void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev) 5339 { 5340 const struct rtw89_chip_info *chip = rtwdev->chip; 5341 5342 if (chip->ops->rfk_channel) 5343 chip->ops->rfk_channel(rtwdev); 5344 } 5345 5346 static inline void rtw89_chip_rfk_band_changed(struct rtw89_dev *rtwdev, 5347 enum rtw89_phy_idx phy_idx) 5348 { 5349 const struct rtw89_chip_info *chip = rtwdev->chip; 5350 5351 if (chip->ops->rfk_band_changed) 5352 chip->ops->rfk_band_changed(rtwdev, phy_idx); 5353 } 5354 5355 static inline void rtw89_chip_rfk_scan(struct rtw89_dev *rtwdev, bool start) 5356 { 5357 const struct rtw89_chip_info *chip = rtwdev->chip; 5358 5359 if (chip->ops->rfk_scan) 5360 chip->ops->rfk_scan(rtwdev, start); 5361 } 5362 5363 static inline void rtw89_chip_rfk_track(struct rtw89_dev *rtwdev) 5364 { 5365 const struct rtw89_chip_info *chip = rtwdev->chip; 5366 5367 if (chip->ops->rfk_track) 5368 chip->ops->rfk_track(rtwdev); 5369 } 5370 5371 static inline void rtw89_chip_set_txpwr_ctrl(struct rtw89_dev *rtwdev) 5372 { 5373 const struct rtw89_chip_info *chip = rtwdev->chip; 5374 5375 if (chip->ops->set_txpwr_ctrl) 5376 chip->ops->set_txpwr_ctrl(rtwdev, RTW89_PHY_0); 5377 } 5378 5379 static inline void rtw89_chip_power_trim(struct rtw89_dev *rtwdev) 5380 { 5381 const struct rtw89_chip_info *chip = rtwdev->chip; 5382 5383 if (chip->ops->power_trim) 5384 chip->ops->power_trim(rtwdev); 5385 } 5386 5387 static inline void rtw89_chip_init_txpwr_unit(struct rtw89_dev *rtwdev, 5388 enum rtw89_phy_idx phy_idx) 5389 { 5390 const struct rtw89_chip_info *chip = rtwdev->chip; 5391 5392 if (chip->ops->init_txpwr_unit) 5393 chip->ops->init_txpwr_unit(rtwdev, phy_idx); 5394 } 5395 5396 static inline u8 rtw89_chip_get_thermal(struct rtw89_dev *rtwdev, 5397 enum rtw89_rf_path rf_path) 5398 { 5399 const struct rtw89_chip_info *chip = rtwdev->chip; 5400 5401 if (!chip->ops->get_thermal) 5402 return 0x10; 5403 5404 return chip->ops->get_thermal(rtwdev, rf_path); 5405 } 5406 5407 static inline void rtw89_chip_query_ppdu(struct rtw89_dev *rtwdev, 5408 struct rtw89_rx_phy_ppdu *phy_ppdu, 5409 struct ieee80211_rx_status *status) 5410 { 5411 const struct rtw89_chip_info *chip = rtwdev->chip; 5412 5413 if (chip->ops->query_ppdu) 5414 chip->ops->query_ppdu(rtwdev, phy_ppdu, status); 5415 } 5416 5417 static inline void rtw89_chip_bb_ctrl_btc_preagc(struct rtw89_dev *rtwdev, 5418 bool bt_en) 5419 { 5420 const struct rtw89_chip_info *chip = rtwdev->chip; 5421 5422 if (chip->ops->bb_ctrl_btc_preagc) 5423 chip->ops->bb_ctrl_btc_preagc(rtwdev, bt_en); 5424 } 5425 5426 static inline void rtw89_chip_cfg_txrx_path(struct rtw89_dev *rtwdev) 5427 { 5428 const struct rtw89_chip_info *chip = rtwdev->chip; 5429 5430 if (chip->ops->cfg_txrx_path) 5431 chip->ops->cfg_txrx_path(rtwdev); 5432 } 5433 5434 static inline 5435 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5436 struct ieee80211_vif *vif) 5437 { 5438 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5439 const struct rtw89_chip_info *chip = rtwdev->chip; 5440 5441 if (!vif->bss_conf.he_support || !vif->cfg.assoc) 5442 return; 5443 5444 if (chip->ops->set_txpwr_ul_tb_offset) 5445 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif->mac_idx); 5446 } 5447 5448 static inline void rtw89_load_txpwr_table(struct rtw89_dev *rtwdev, 5449 const struct rtw89_txpwr_table *tbl) 5450 { 5451 tbl->load(rtwdev, tbl); 5452 } 5453 5454 static inline u8 rtw89_regd_get(struct rtw89_dev *rtwdev, u8 band) 5455 { 5456 const struct rtw89_regd *regd = rtwdev->regulatory.regd; 5457 5458 return regd->txpwr_regd[band]; 5459 } 5460 5461 static inline void rtw89_ctrl_btg(struct rtw89_dev *rtwdev, bool btg) 5462 { 5463 const struct rtw89_chip_info *chip = rtwdev->chip; 5464 5465 if (chip->ops->ctrl_btg) 5466 chip->ops->ctrl_btg(rtwdev, btg); 5467 } 5468 5469 static inline 5470 void rtw89_chip_query_rxdesc(struct rtw89_dev *rtwdev, 5471 struct rtw89_rx_desc_info *desc_info, 5472 u8 *data, u32 data_offset) 5473 { 5474 const struct rtw89_chip_info *chip = rtwdev->chip; 5475 5476 chip->ops->query_rxdesc(rtwdev, desc_info, data, data_offset); 5477 } 5478 5479 static inline 5480 void rtw89_chip_fill_txdesc(struct rtw89_dev *rtwdev, 5481 struct rtw89_tx_desc_info *desc_info, 5482 void *txdesc) 5483 { 5484 const struct rtw89_chip_info *chip = rtwdev->chip; 5485 5486 chip->ops->fill_txdesc(rtwdev, desc_info, txdesc); 5487 } 5488 5489 static inline 5490 void rtw89_chip_fill_txdesc_fwcmd(struct rtw89_dev *rtwdev, 5491 struct rtw89_tx_desc_info *desc_info, 5492 void *txdesc) 5493 { 5494 const struct rtw89_chip_info *chip = rtwdev->chip; 5495 5496 chip->ops->fill_txdesc_fwcmd(rtwdev, desc_info, txdesc); 5497 } 5498 5499 static inline 5500 void rtw89_chip_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5501 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5502 { 5503 const struct rtw89_chip_info *chip = rtwdev->chip; 5504 5505 chip->ops->mac_cfg_gnt(rtwdev, gnt_cfg); 5506 } 5507 5508 static inline void rtw89_chip_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5509 { 5510 const struct rtw89_chip_info *chip = rtwdev->chip; 5511 5512 chip->ops->cfg_ctrl_path(rtwdev, wl); 5513 } 5514 5515 static inline 5516 int rtw89_chip_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 5517 u32 *tx_en, enum rtw89_sch_tx_sel sel) 5518 { 5519 const struct rtw89_chip_info *chip = rtwdev->chip; 5520 5521 return chip->ops->stop_sch_tx(rtwdev, mac_idx, tx_en, sel); 5522 } 5523 5524 static inline 5525 int rtw89_chip_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 5526 { 5527 const struct rtw89_chip_info *chip = rtwdev->chip; 5528 5529 return chip->ops->resume_sch_tx(rtwdev, mac_idx, tx_en); 5530 } 5531 5532 static inline 5533 int rtw89_chip_h2c_dctl_sec_cam(struct rtw89_dev *rtwdev, 5534 struct rtw89_vif *rtwvif, 5535 struct rtw89_sta *rtwsta) 5536 { 5537 const struct rtw89_chip_info *chip = rtwdev->chip; 5538 5539 if (!chip->ops->h2c_dctl_sec_cam) 5540 return 0; 5541 return chip->ops->h2c_dctl_sec_cam(rtwdev, rtwvif, rtwsta); 5542 } 5543 5544 static inline u8 *get_hdr_bssid(struct ieee80211_hdr *hdr) 5545 { 5546 __le16 fc = hdr->frame_control; 5547 5548 if (ieee80211_has_tods(fc)) 5549 return hdr->addr1; 5550 else if (ieee80211_has_fromds(fc)) 5551 return hdr->addr2; 5552 else 5553 return hdr->addr3; 5554 } 5555 5556 static inline bool rtw89_sta_has_beamformer_cap(struct ieee80211_sta *sta) 5557 { 5558 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5559 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE) || 5560 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[3] & 5561 IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5562 (sta->deflink.he_cap.he_cap_elem.phy_cap_info[4] & 5563 IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) 5564 return true; 5565 return false; 5566 } 5567 5568 static inline struct rtw89_fw_suit *rtw89_fw_suit_get(struct rtw89_dev *rtwdev, 5569 enum rtw89_fw_type type) 5570 { 5571 struct rtw89_fw_info *fw_info = &rtwdev->fw; 5572 5573 switch (type) { 5574 case RTW89_FW_WOWLAN: 5575 return &fw_info->wowlan; 5576 case RTW89_FW_LOGFMT: 5577 return &fw_info->log.suit; 5578 case RTW89_FW_BBMCU0: 5579 return &fw_info->bbmcu0; 5580 case RTW89_FW_BBMCU1: 5581 return &fw_info->bbmcu1; 5582 default: 5583 break; 5584 } 5585 5586 return &fw_info->normal; 5587 } 5588 5589 static inline struct sk_buff *rtw89_alloc_skb_for_rx(struct rtw89_dev *rtwdev, 5590 unsigned int length) 5591 { 5592 struct sk_buff *skb; 5593 5594 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 5595 skb = dev_alloc_skb(length + RTW89_RADIOTAP_ROOM); 5596 if (!skb) 5597 return NULL; 5598 5599 skb_reserve(skb, RTW89_RADIOTAP_ROOM); 5600 return skb; 5601 } 5602 5603 return dev_alloc_skb(length); 5604 } 5605 5606 static inline void rtw89_core_tx_wait_complete(struct rtw89_dev *rtwdev, 5607 struct rtw89_tx_skb_data *skb_data, 5608 bool tx_done) 5609 { 5610 struct rtw89_tx_wait_info *wait; 5611 5612 rcu_read_lock(); 5613 5614 wait = rcu_dereference(skb_data->wait); 5615 if (!wait) 5616 goto out; 5617 5618 wait->tx_done = tx_done; 5619 complete(&wait->completion); 5620 5621 out: 5622 rcu_read_unlock(); 5623 } 5624 5625 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 5626 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel); 5627 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 5628 struct sk_buff *skb, bool fwdl); 5629 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel); 5630 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5631 int qsel, unsigned int timeout); 5632 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 5633 struct rtw89_tx_desc_info *desc_info, 5634 void *txdesc); 5635 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 5636 struct rtw89_tx_desc_info *desc_info, 5637 void *txdesc); 5638 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 5639 struct rtw89_tx_desc_info *desc_info, 5640 void *txdesc); 5641 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 5642 struct rtw89_tx_desc_info *desc_info, 5643 void *txdesc); 5644 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 5645 struct rtw89_tx_desc_info *desc_info, 5646 void *txdesc); 5647 void rtw89_core_rx(struct rtw89_dev *rtwdev, 5648 struct rtw89_rx_desc_info *desc_info, 5649 struct sk_buff *skb); 5650 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 5651 struct rtw89_rx_desc_info *desc_info, 5652 u8 *data, u32 data_offset); 5653 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 5654 struct rtw89_rx_desc_info *desc_info, 5655 u8 *data, u32 data_offset); 5656 void rtw89_core_napi_start(struct rtw89_dev *rtwdev); 5657 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev); 5658 void rtw89_core_napi_init(struct rtw89_dev *rtwdev); 5659 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev); 5660 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 5661 struct ieee80211_vif *vif, 5662 struct ieee80211_sta *sta); 5663 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 5664 struct ieee80211_vif *vif, 5665 struct ieee80211_sta *sta); 5666 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 5667 struct ieee80211_vif *vif, 5668 struct ieee80211_sta *sta); 5669 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 5670 struct ieee80211_vif *vif, 5671 struct ieee80211_sta *sta); 5672 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 5673 struct ieee80211_vif *vif, 5674 struct ieee80211_sta *sta); 5675 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 5676 struct ieee80211_sta *sta, 5677 struct cfg80211_tid_config *tid_config); 5678 int rtw89_core_init(struct rtw89_dev *rtwdev); 5679 void rtw89_core_deinit(struct rtw89_dev *rtwdev); 5680 int rtw89_core_register(struct rtw89_dev *rtwdev); 5681 void rtw89_core_unregister(struct rtw89_dev *rtwdev); 5682 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5683 u32 bus_data_size, 5684 const struct rtw89_chip_info *chip); 5685 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev); 5686 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev); 5687 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef); 5688 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 5689 struct rtw89_chan *chan); 5690 void rtw89_set_channel(struct rtw89_dev *rtwdev); 5691 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5692 struct rtw89_chan *chan); 5693 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size); 5694 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit); 5695 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits); 5696 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 5697 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5698 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 5699 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx); 5700 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc); 5701 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev); 5702 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate); 5703 int rtw89_regd_setup(struct rtw89_dev *rtwdev); 5704 int rtw89_regd_init(struct rtw89_dev *rtwdev, 5705 void (*reg_notifier)(struct wiphy *wiphy, struct regulatory_request *request)); 5706 void rtw89_regd_notifier(struct wiphy *wiphy, struct regulatory_request *request); 5707 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 5708 struct rtw89_traffic_stats *stats); 5709 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond); 5710 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 5711 const struct rtw89_completion_data *data); 5712 int rtw89_core_start(struct rtw89_dev *rtwdev); 5713 void rtw89_core_stop(struct rtw89_dev *rtwdev); 5714 void rtw89_core_update_beacon_work(struct work_struct *work); 5715 void rtw89_roc_work(struct work_struct *work); 5716 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5717 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); 5718 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5719 const u8 *mac_addr, bool hw_scan); 5720 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5721 struct ieee80211_vif *vif, bool hw_scan); 5722 void rtw89_reg_6ghz_power_recalc(struct rtw89_dev *rtwdev, 5723 struct rtw89_vif *rtwvif, bool active); 5724 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); 5725 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event); 5726 5727 #endif 5728