1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 #include "wow.h" 22 23 static bool rtw89_disable_ps_mode; 24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 26 27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 37 38 static struct ieee80211_channel rtw89_channels_2ghz[] = { 39 RTW89_DEF_CHAN_2G(2412, 1), 40 RTW89_DEF_CHAN_2G(2417, 2), 41 RTW89_DEF_CHAN_2G(2422, 3), 42 RTW89_DEF_CHAN_2G(2427, 4), 43 RTW89_DEF_CHAN_2G(2432, 5), 44 RTW89_DEF_CHAN_2G(2437, 6), 45 RTW89_DEF_CHAN_2G(2442, 7), 46 RTW89_DEF_CHAN_2G(2447, 8), 47 RTW89_DEF_CHAN_2G(2452, 9), 48 RTW89_DEF_CHAN_2G(2457, 10), 49 RTW89_DEF_CHAN_2G(2462, 11), 50 RTW89_DEF_CHAN_2G(2467, 12), 51 RTW89_DEF_CHAN_2G(2472, 13), 52 RTW89_DEF_CHAN_2G(2484, 14), 53 }; 54 55 static struct ieee80211_channel rtw89_channels_5ghz[] = { 56 RTW89_DEF_CHAN_5G(5180, 36), 57 RTW89_DEF_CHAN_5G(5200, 40), 58 RTW89_DEF_CHAN_5G(5220, 44), 59 RTW89_DEF_CHAN_5G(5240, 48), 60 RTW89_DEF_CHAN_5G(5260, 52), 61 RTW89_DEF_CHAN_5G(5280, 56), 62 RTW89_DEF_CHAN_5G(5300, 60), 63 RTW89_DEF_CHAN_5G(5320, 64), 64 RTW89_DEF_CHAN_5G(5500, 100), 65 RTW89_DEF_CHAN_5G(5520, 104), 66 RTW89_DEF_CHAN_5G(5540, 108), 67 RTW89_DEF_CHAN_5G(5560, 112), 68 RTW89_DEF_CHAN_5G(5580, 116), 69 RTW89_DEF_CHAN_5G(5600, 120), 70 RTW89_DEF_CHAN_5G(5620, 124), 71 RTW89_DEF_CHAN_5G(5640, 128), 72 RTW89_DEF_CHAN_5G(5660, 132), 73 RTW89_DEF_CHAN_5G(5680, 136), 74 RTW89_DEF_CHAN_5G(5700, 140), 75 RTW89_DEF_CHAN_5G(5720, 144), 76 RTW89_DEF_CHAN_5G(5745, 149), 77 RTW89_DEF_CHAN_5G(5765, 153), 78 RTW89_DEF_CHAN_5G(5785, 157), 79 RTW89_DEF_CHAN_5G(5805, 161), 80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 81 RTW89_DEF_CHAN_5G(5845, 169), 82 RTW89_DEF_CHAN_5G(5865, 173), 83 RTW89_DEF_CHAN_5G(5885, 177), 84 }; 85 86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 87 ARRAY_SIZE(rtw89_channels_5ghz)); 88 89 static struct ieee80211_channel rtw89_channels_6ghz[] = { 90 RTW89_DEF_CHAN_6G(5955, 1), 91 RTW89_DEF_CHAN_6G(5975, 5), 92 RTW89_DEF_CHAN_6G(5995, 9), 93 RTW89_DEF_CHAN_6G(6015, 13), 94 RTW89_DEF_CHAN_6G(6035, 17), 95 RTW89_DEF_CHAN_6G(6055, 21), 96 RTW89_DEF_CHAN_6G(6075, 25), 97 RTW89_DEF_CHAN_6G(6095, 29), 98 RTW89_DEF_CHAN_6G(6115, 33), 99 RTW89_DEF_CHAN_6G(6135, 37), 100 RTW89_DEF_CHAN_6G(6155, 41), 101 RTW89_DEF_CHAN_6G(6175, 45), 102 RTW89_DEF_CHAN_6G(6195, 49), 103 RTW89_DEF_CHAN_6G(6215, 53), 104 RTW89_DEF_CHAN_6G(6235, 57), 105 RTW89_DEF_CHAN_6G(6255, 61), 106 RTW89_DEF_CHAN_6G(6275, 65), 107 RTW89_DEF_CHAN_6G(6295, 69), 108 RTW89_DEF_CHAN_6G(6315, 73), 109 RTW89_DEF_CHAN_6G(6335, 77), 110 RTW89_DEF_CHAN_6G(6355, 81), 111 RTW89_DEF_CHAN_6G(6375, 85), 112 RTW89_DEF_CHAN_6G(6395, 89), 113 RTW89_DEF_CHAN_6G(6415, 93), 114 RTW89_DEF_CHAN_6G(6435, 97), 115 RTW89_DEF_CHAN_6G(6455, 101), 116 RTW89_DEF_CHAN_6G(6475, 105), 117 RTW89_DEF_CHAN_6G(6495, 109), 118 RTW89_DEF_CHAN_6G(6515, 113), 119 RTW89_DEF_CHAN_6G(6535, 117), 120 RTW89_DEF_CHAN_6G(6555, 121), 121 RTW89_DEF_CHAN_6G(6575, 125), 122 RTW89_DEF_CHAN_6G(6595, 129), 123 RTW89_DEF_CHAN_6G(6615, 133), 124 RTW89_DEF_CHAN_6G(6635, 137), 125 RTW89_DEF_CHAN_6G(6655, 141), 126 RTW89_DEF_CHAN_6G(6675, 145), 127 RTW89_DEF_CHAN_6G(6695, 149), 128 RTW89_DEF_CHAN_6G(6715, 153), 129 RTW89_DEF_CHAN_6G(6735, 157), 130 RTW89_DEF_CHAN_6G(6755, 161), 131 RTW89_DEF_CHAN_6G(6775, 165), 132 RTW89_DEF_CHAN_6G(6795, 169), 133 RTW89_DEF_CHAN_6G(6815, 173), 134 RTW89_DEF_CHAN_6G(6835, 177), 135 RTW89_DEF_CHAN_6G(6855, 181), 136 RTW89_DEF_CHAN_6G(6875, 185), 137 RTW89_DEF_CHAN_6G(6895, 189), 138 RTW89_DEF_CHAN_6G(6915, 193), 139 RTW89_DEF_CHAN_6G(6935, 197), 140 RTW89_DEF_CHAN_6G(6955, 201), 141 RTW89_DEF_CHAN_6G(6975, 205), 142 RTW89_DEF_CHAN_6G(6995, 209), 143 RTW89_DEF_CHAN_6G(7015, 213), 144 RTW89_DEF_CHAN_6G(7035, 217), 145 RTW89_DEF_CHAN_6G(7055, 221), 146 RTW89_DEF_CHAN_6G(7075, 225), 147 RTW89_DEF_CHAN_6G(7095, 229), 148 RTW89_DEF_CHAN_6G(7115, 233), 149 }; 150 151 static struct ieee80211_rate rtw89_bitrates[] = { 152 { .bitrate = 10, .hw_value = 0x00, }, 153 { .bitrate = 20, .hw_value = 0x01, }, 154 { .bitrate = 55, .hw_value = 0x02, }, 155 { .bitrate = 110, .hw_value = 0x03, }, 156 { .bitrate = 60, .hw_value = 0x04, }, 157 { .bitrate = 90, .hw_value = 0x05, }, 158 { .bitrate = 120, .hw_value = 0x06, }, 159 { .bitrate = 180, .hw_value = 0x07, }, 160 { .bitrate = 240, .hw_value = 0x08, }, 161 { .bitrate = 360, .hw_value = 0x09, }, 162 { .bitrate = 480, .hw_value = 0x0a, }, 163 { .bitrate = 540, .hw_value = 0x0b, }, 164 }; 165 166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_STATION), 170 }, 171 { 172 .max = 1, 173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 174 BIT(NL80211_IFTYPE_P2P_GO) | 175 BIT(NL80211_IFTYPE_AP), 176 }, 177 }; 178 179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_STATION), 183 }, 184 { 185 .max = 1, 186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 187 BIT(NL80211_IFTYPE_P2P_GO), 188 }, 189 }; 190 191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 192 { 193 .limits = rtw89_iface_limits, 194 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 195 .max_interfaces = 2, 196 .num_different_channels = 1, 197 }, 198 { 199 .limits = rtw89_iface_limits_mcc, 200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 201 .max_interfaces = 2, 202 .num_different_channels = 2, 203 }, 204 }; 205 206 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 207 { 208 struct ieee80211_rate rate; 209 210 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 211 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 212 return false; 213 } 214 215 rate = rtw89_bitrates[rpt_rate]; 216 *bitrate = rate.bitrate; 217 218 return true; 219 } 220 221 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 222 .band = NL80211_BAND_2GHZ, 223 .channels = rtw89_channels_2ghz, 224 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 225 .bitrates = rtw89_bitrates, 226 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 227 .ht_cap = {0}, 228 .vht_cap = {0}, 229 }; 230 231 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 232 .band = NL80211_BAND_5GHZ, 233 .channels = rtw89_channels_5ghz, 234 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 235 236 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 237 .bitrates = rtw89_bitrates + 4, 238 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 239 .ht_cap = {0}, 240 .vht_cap = {0}, 241 }; 242 243 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 244 .band = NL80211_BAND_6GHZ, 245 .channels = rtw89_channels_6ghz, 246 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 247 248 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 249 .bitrates = rtw89_bitrates + 4, 250 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 251 }; 252 253 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 254 struct rtw89_traffic_stats *stats, 255 struct sk_buff *skb, bool tx) 256 { 257 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 258 259 if (tx && ieee80211_is_assoc_req(hdr->frame_control)) 260 rtw89_wow_parse_akm(rtwdev, skb); 261 262 if (!ieee80211_is_data(hdr->frame_control)) 263 return; 264 265 if (is_broadcast_ether_addr(hdr->addr1) || 266 is_multicast_ether_addr(hdr->addr1)) 267 return; 268 269 if (tx) { 270 stats->tx_cnt++; 271 stats->tx_unicast += skb->len; 272 } else { 273 stats->rx_cnt++; 274 stats->rx_unicast += skb->len; 275 } 276 } 277 278 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 279 { 280 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 281 NL80211_CHAN_NO_HT); 282 } 283 284 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 285 struct rtw89_chan *chan) 286 { 287 struct ieee80211_channel *channel = chandef->chan; 288 enum nl80211_chan_width width = chandef->width; 289 u32 primary_freq, center_freq; 290 u8 center_chan; 291 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 292 u32 offset; 293 u8 band; 294 295 center_chan = channel->hw_value; 296 primary_freq = channel->center_freq; 297 center_freq = chandef->center_freq1; 298 299 switch (width) { 300 case NL80211_CHAN_WIDTH_20_NOHT: 301 case NL80211_CHAN_WIDTH_20: 302 bandwidth = RTW89_CHANNEL_WIDTH_20; 303 break; 304 case NL80211_CHAN_WIDTH_40: 305 bandwidth = RTW89_CHANNEL_WIDTH_40; 306 if (primary_freq > center_freq) { 307 center_chan -= 2; 308 } else { 309 center_chan += 2; 310 } 311 break; 312 case NL80211_CHAN_WIDTH_80: 313 case NL80211_CHAN_WIDTH_160: 314 bandwidth = nl_to_rtw89_bandwidth(width); 315 if (primary_freq > center_freq) { 316 offset = (primary_freq - center_freq - 10) / 20; 317 center_chan -= 2 + offset * 4; 318 } else { 319 offset = (center_freq - primary_freq - 10) / 20; 320 center_chan += 2 + offset * 4; 321 } 322 break; 323 default: 324 center_chan = 0; 325 break; 326 } 327 328 switch (channel->band) { 329 default: 330 case NL80211_BAND_2GHZ: 331 band = RTW89_BAND_2G; 332 break; 333 case NL80211_BAND_5GHZ: 334 band = RTW89_BAND_5G; 335 break; 336 case NL80211_BAND_6GHZ: 337 band = RTW89_BAND_6G; 338 break; 339 } 340 341 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 342 } 343 344 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 345 { 346 struct rtw89_hal *hal = &rtwdev->hal; 347 const struct rtw89_chip_info *chip = rtwdev->chip; 348 const struct rtw89_chan *chan; 349 enum rtw89_sub_entity_idx sub_entity_idx; 350 enum rtw89_sub_entity_idx roc_idx; 351 enum rtw89_phy_idx phy_idx; 352 enum rtw89_entity_mode mode; 353 bool entity_active; 354 355 entity_active = rtw89_get_entity_state(rtwdev); 356 if (!entity_active) 357 return; 358 359 mode = rtw89_get_entity_mode(rtwdev); 360 switch (mode) { 361 case RTW89_ENTITY_MODE_SCC: 362 case RTW89_ENTITY_MODE_MCC: 363 sub_entity_idx = RTW89_SUB_ENTITY_0; 364 break; 365 case RTW89_ENTITY_MODE_MCC_PREPARE: 366 sub_entity_idx = RTW89_SUB_ENTITY_1; 367 break; 368 default: 369 WARN(1, "Invalid ent mode: %d\n", mode); 370 return; 371 } 372 373 roc_idx = atomic_read(&hal->roc_entity_idx); 374 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 375 sub_entity_idx = roc_idx; 376 377 phy_idx = RTW89_PHY_0; 378 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 379 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 380 } 381 382 int rtw89_set_channel(struct rtw89_dev *rtwdev) 383 { 384 struct rtw89_hal *hal = &rtwdev->hal; 385 const struct rtw89_chip_info *chip = rtwdev->chip; 386 const struct rtw89_chan_rcd *chan_rcd; 387 const struct rtw89_chan *chan; 388 enum rtw89_sub_entity_idx sub_entity_idx; 389 enum rtw89_sub_entity_idx roc_idx; 390 enum rtw89_mac_idx mac_idx; 391 enum rtw89_phy_idx phy_idx; 392 struct rtw89_channel_help_params bak; 393 enum rtw89_entity_mode mode; 394 bool entity_active; 395 396 entity_active = rtw89_get_entity_state(rtwdev); 397 398 mode = rtw89_entity_recalc(rtwdev); 399 switch (mode) { 400 case RTW89_ENTITY_MODE_SCC: 401 case RTW89_ENTITY_MODE_MCC: 402 sub_entity_idx = RTW89_SUB_ENTITY_0; 403 break; 404 case RTW89_ENTITY_MODE_MCC_PREPARE: 405 sub_entity_idx = RTW89_SUB_ENTITY_1; 406 break; 407 default: 408 WARN(1, "Invalid ent mode: %d\n", mode); 409 return -EINVAL; 410 } 411 412 roc_idx = atomic_read(&hal->roc_entity_idx); 413 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 414 sub_entity_idx = roc_idx; 415 416 mac_idx = RTW89_MAC_0; 417 phy_idx = RTW89_PHY_0; 418 419 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 420 chan_rcd = rtw89_chan_rcd_get(rtwdev, sub_entity_idx); 421 422 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 423 424 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 425 426 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 427 428 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 429 430 if (!entity_active || chan_rcd->band_changed) { 431 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 432 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 433 } 434 435 rtw89_set_entity_state(rtwdev, true); 436 return 0; 437 } 438 439 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 440 struct rtw89_chan *chan) 441 { 442 const struct cfg80211_chan_def *chandef; 443 444 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx); 445 rtw89_get_channel_params(chandef, chan); 446 } 447 448 static enum rtw89_core_tx_type 449 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 450 struct sk_buff *skb) 451 { 452 struct ieee80211_hdr *hdr = (void *)skb->data; 453 __le16 fc = hdr->frame_control; 454 455 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 456 return RTW89_CORE_TX_TYPE_MGMT; 457 458 return RTW89_CORE_TX_TYPE_DATA; 459 } 460 461 static void 462 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 463 struct rtw89_core_tx_request *tx_req, 464 enum btc_pkt_type pkt_type) 465 { 466 struct ieee80211_sta *sta = tx_req->sta; 467 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 468 struct sk_buff *skb = tx_req->skb; 469 struct rtw89_sta *rtwsta; 470 u8 ampdu_num; 471 u8 tid; 472 473 if (pkt_type == PACKET_EAPOL) { 474 desc_info->bk = true; 475 return; 476 } 477 478 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 479 return; 480 481 if (!sta) { 482 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 483 return; 484 } 485 486 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 487 rtwsta = (struct rtw89_sta *)sta->drv_priv; 488 489 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 490 rtwsta->ampdu_params[tid].agg_num : 491 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 492 493 desc_info->agg_en = true; 494 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 495 desc_info->ampdu_num = ampdu_num; 496 } 497 498 static void 499 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 500 struct rtw89_core_tx_request *tx_req) 501 { 502 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 503 const struct rtw89_chip_info *chip = rtwdev->chip; 504 const struct rtw89_sec_cam_entry *sec_cam; 505 struct ieee80211_tx_info *info; 506 struct ieee80211_key_conf *key; 507 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 508 struct sk_buff *skb = tx_req->skb; 509 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 510 u8 sec_cam_idx; 511 u64 pn64; 512 513 info = IEEE80211_SKB_CB(skb); 514 key = info->control.hw_key; 515 sec_cam_idx = key->hw_key_idx; 516 sec_cam = cam_info->sec_entries[sec_cam_idx]; 517 if (!sec_cam) { 518 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 519 return; 520 } 521 522 switch (key->cipher) { 523 case WLAN_CIPHER_SUITE_WEP40: 524 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 525 break; 526 case WLAN_CIPHER_SUITE_WEP104: 527 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 528 break; 529 case WLAN_CIPHER_SUITE_TKIP: 530 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 531 break; 532 case WLAN_CIPHER_SUITE_CCMP: 533 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 534 break; 535 case WLAN_CIPHER_SUITE_CCMP_256: 536 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 537 break; 538 case WLAN_CIPHER_SUITE_GCMP: 539 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 540 break; 541 case WLAN_CIPHER_SUITE_GCMP_256: 542 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 543 break; 544 default: 545 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 546 return; 547 } 548 549 desc_info->sec_en = true; 550 desc_info->sec_keyid = key->keyidx; 551 desc_info->sec_type = sec_type; 552 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 553 554 if (!chip->hw_sec_hdr) 555 return; 556 557 pn64 = atomic64_inc_return(&key->tx_pn); 558 desc_info->sec_seq[0] = pn64; 559 desc_info->sec_seq[1] = pn64 >> 8; 560 desc_info->sec_seq[2] = pn64 >> 16; 561 desc_info->sec_seq[3] = pn64 >> 24; 562 desc_info->sec_seq[4] = pn64 >> 32; 563 desc_info->sec_seq[5] = pn64 >> 40; 564 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 565 } 566 567 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 568 struct rtw89_core_tx_request *tx_req, 569 const struct rtw89_chan *chan) 570 { 571 struct sk_buff *skb = tx_req->skb; 572 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 573 struct ieee80211_vif *vif = tx_info->control.vif; 574 u16 lowest_rate; 575 576 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 577 (vif && vif->p2p)) 578 lowest_rate = RTW89_HW_RATE_OFDM6; 579 else if (chan->band_type == RTW89_BAND_2G) 580 lowest_rate = RTW89_HW_RATE_CCK1; 581 else 582 lowest_rate = RTW89_HW_RATE_OFDM6; 583 584 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 585 return lowest_rate; 586 587 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 588 } 589 590 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 591 struct rtw89_core_tx_request *tx_req) 592 { 593 struct ieee80211_vif *vif = tx_req->vif; 594 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 595 struct ieee80211_sta *sta = tx_req->sta; 596 struct rtw89_sta *rtwsta; 597 598 if (!sta) 599 return rtwvif->mac_id; 600 601 rtwsta = (struct rtw89_sta *)sta->drv_priv; 602 return rtwsta->mac_id; 603 } 604 605 static void 606 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 607 struct rtw89_core_tx_request *tx_req) 608 { 609 struct ieee80211_vif *vif = tx_req->vif; 610 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 611 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 612 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 613 rtwvif->sub_entity_idx); 614 u8 qsel, ch_dma; 615 616 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 617 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 618 619 desc_info->qsel = qsel; 620 desc_info->ch_dma = ch_dma; 621 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 622 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 623 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 624 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 625 626 /* fixed data rate for mgmt frames */ 627 desc_info->en_wd_info = true; 628 desc_info->use_rate = true; 629 desc_info->dis_data_fb = true; 630 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 631 632 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 633 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 634 desc_info->data_rate, chan->channel, chan->band_type, 635 chan->band_width); 636 } 637 638 static void 639 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 640 struct rtw89_core_tx_request *tx_req) 641 { 642 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 643 644 desc_info->is_bmc = false; 645 desc_info->wd_page = false; 646 desc_info->ch_dma = RTW89_DMA_H2C; 647 } 648 649 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 650 const struct rtw89_chan *chan) 651 { 652 static const u8 rtw89_bandwidth_to_om[] = { 653 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 654 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 655 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 656 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 657 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 658 }; 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 struct rtw89_hal *hal = &rtwdev->hal; 661 u8 om_bandwidth; 662 663 if (!chip->dis_2g_40m_ul_ofdma || 664 chan->band_type != RTW89_BAND_2G || 665 chan->band_width != RTW89_CHANNEL_WIDTH_40) 666 return; 667 668 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 669 rtw89_bandwidth_to_om[chan->band_width] : 0; 670 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 671 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 672 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 673 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 674 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 675 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 676 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 677 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 678 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 679 } 680 681 static bool 682 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 683 struct rtw89_core_tx_request *tx_req, 684 enum btc_pkt_type pkt_type) 685 { 686 struct ieee80211_sta *sta = tx_req->sta; 687 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 688 struct sk_buff *skb = tx_req->skb; 689 struct ieee80211_hdr *hdr = (void *)skb->data; 690 __le16 fc = hdr->frame_control; 691 692 /* AP IOT issue with EAPoL, ARP and DHCP */ 693 if (pkt_type < PACKET_MAX) 694 return false; 695 696 if (!sta || !sta->deflink.he_cap.has_he) 697 return false; 698 699 if (!ieee80211_is_data_qos(fc)) 700 return false; 701 702 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 703 return false; 704 705 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 706 return false; 707 708 return true; 709 } 710 711 static void 712 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 713 struct rtw89_core_tx_request *tx_req) 714 { 715 struct ieee80211_sta *sta = tx_req->sta; 716 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 717 struct sk_buff *skb = tx_req->skb; 718 struct ieee80211_hdr *hdr = (void *)skb->data; 719 __le16 fc = hdr->frame_control; 720 void *data; 721 __le32 *htc; 722 u8 *qc; 723 int hdr_len; 724 725 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 726 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 727 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 728 729 hdr = data; 730 htc = data + hdr_len; 731 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 732 *htc = rtwsta->htc_template ? rtwsta->htc_template : 733 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 734 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 735 736 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 737 qc[0] |= IEEE80211_QOS_CTL_EOSP; 738 } 739 740 static void 741 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 742 struct rtw89_core_tx_request *tx_req, 743 enum btc_pkt_type pkt_type) 744 { 745 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 746 struct ieee80211_vif *vif = tx_req->vif; 747 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 748 749 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 750 goto desc_bk; 751 752 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 753 754 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 755 desc_info->a_ctrl_bsr = true; 756 757 desc_bk: 758 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 759 return; 760 761 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 762 desc_info->bk = true; 763 } 764 765 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 766 struct rtw89_core_tx_request *tx_req) 767 { 768 struct ieee80211_vif *vif = tx_req->vif; 769 struct ieee80211_sta *sta = tx_req->sta; 770 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 771 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 772 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx; 773 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 774 u16 lowest_rate; 775 776 if (rate_pattern->enable) 777 return rate_pattern->rate; 778 779 if (vif->p2p) 780 lowest_rate = RTW89_HW_RATE_OFDM6; 781 else if (chan->band_type == RTW89_BAND_2G) 782 lowest_rate = RTW89_HW_RATE_CCK1; 783 else 784 lowest_rate = RTW89_HW_RATE_OFDM6; 785 786 if (!sta || !sta->deflink.supp_rates[chan->band_type]) 787 return lowest_rate; 788 789 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate; 790 } 791 792 static void 793 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 794 struct rtw89_core_tx_request *tx_req) 795 { 796 struct ieee80211_vif *vif = tx_req->vif; 797 struct ieee80211_sta *sta = tx_req->sta; 798 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 799 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 800 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 801 struct sk_buff *skb = tx_req->skb; 802 u8 tid, tid_indicate; 803 u8 qsel, ch_dma; 804 805 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 806 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 807 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 808 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 809 810 desc_info->ch_dma = ch_dma; 811 desc_info->tid_indicate = tid_indicate; 812 desc_info->qsel = qsel; 813 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 814 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 815 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 816 desc_info->stbc = rtwsta ? rtwsta->ra.stbc_cap : false; 817 desc_info->ldpc = rtwsta ? rtwsta->ra.ldpc_cap : false; 818 819 /* enable wd_info for AMPDU */ 820 desc_info->en_wd_info = true; 821 822 if (IEEE80211_SKB_CB(skb)->control.hw_key) 823 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 824 825 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 826 } 827 828 static enum btc_pkt_type 829 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 830 struct rtw89_core_tx_request *tx_req) 831 { 832 struct sk_buff *skb = tx_req->skb; 833 struct udphdr *udphdr; 834 835 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 836 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 837 return PACKET_EAPOL; 838 } 839 840 if (skb->protocol == htons(ETH_P_ARP)) { 841 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 842 return PACKET_ARP; 843 } 844 845 if (skb->protocol == htons(ETH_P_IP) && 846 ip_hdr(skb)->protocol == IPPROTO_UDP) { 847 udphdr = udp_hdr(skb); 848 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 849 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 850 skb->len > 282) { 851 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 852 return PACKET_DHCP; 853 } 854 } 855 856 if (skb->protocol == htons(ETH_P_IP) && 857 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 858 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 859 return PACKET_ICMP; 860 } 861 862 return PACKET_MAX; 863 } 864 865 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 866 struct rtw89_tx_desc_info *desc_info, 867 struct sk_buff *skb) 868 { 869 struct ieee80211_hdr *hdr = (void *)skb->data; 870 __le16 fc = hdr->frame_control; 871 872 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 873 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 874 } 875 876 static void 877 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 878 struct rtw89_core_tx_request *tx_req) 879 { 880 const struct rtw89_chip_info *chip = rtwdev->chip; 881 882 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 883 return; 884 885 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 886 return; 887 888 if (chip->chip_id != RTL8852C && 889 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 890 return; 891 892 rtw89_mac_notify_wake(rtwdev); 893 } 894 895 static void 896 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 897 struct rtw89_core_tx_request *tx_req) 898 { 899 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 900 struct sk_buff *skb = tx_req->skb; 901 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 902 struct ieee80211_hdr *hdr = (void *)skb->data; 903 enum rtw89_core_tx_type tx_type; 904 enum btc_pkt_type pkt_type; 905 bool is_bmc; 906 u16 seq; 907 908 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 909 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 910 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 911 tx_req->tx_type = tx_type; 912 } 913 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 914 is_multicast_ether_addr(hdr->addr1)); 915 916 desc_info->seq = seq; 917 desc_info->pkt_size = skb->len; 918 desc_info->is_bmc = is_bmc; 919 desc_info->wd_page = true; 920 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 921 922 switch (tx_req->tx_type) { 923 case RTW89_CORE_TX_TYPE_MGMT: 924 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 925 break; 926 case RTW89_CORE_TX_TYPE_DATA: 927 rtw89_core_tx_update_data_info(rtwdev, tx_req); 928 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 929 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 930 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 931 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 932 break; 933 case RTW89_CORE_TX_TYPE_FWCMD: 934 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 935 break; 936 } 937 } 938 939 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 940 { 941 u8 ch_dma; 942 943 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 944 945 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 946 } 947 948 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 949 int qsel, unsigned int timeout) 950 { 951 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 952 struct rtw89_tx_wait_info *wait; 953 unsigned long time_left; 954 int ret = 0; 955 956 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 957 if (!wait) { 958 rtw89_core_tx_kick_off(rtwdev, qsel); 959 return 0; 960 } 961 962 init_completion(&wait->completion); 963 rcu_assign_pointer(skb_data->wait, wait); 964 965 rtw89_core_tx_kick_off(rtwdev, qsel); 966 time_left = wait_for_completion_timeout(&wait->completion, 967 msecs_to_jiffies(timeout)); 968 if (time_left == 0) 969 ret = -ETIMEDOUT; 970 else if (!wait->tx_done) 971 ret = -EAGAIN; 972 973 rcu_assign_pointer(skb_data->wait, NULL); 974 kfree_rcu(wait, rcu_head); 975 976 return ret; 977 } 978 979 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 980 struct sk_buff *skb, bool fwdl) 981 { 982 struct rtw89_core_tx_request tx_req = {0}; 983 u32 cnt; 984 int ret; 985 986 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 987 rtw89_debug(rtwdev, RTW89_DBG_FW, 988 "ignore h2c due to power is off with firmware state=%d\n", 989 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 990 dev_kfree_skb(skb); 991 return 0; 992 } 993 994 tx_req.skb = skb; 995 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 996 if (fwdl) 997 tx_req.desc_info.fw_dl = true; 998 999 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1000 1001 if (!fwdl) 1002 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1003 1004 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1005 if (cnt == 0) { 1006 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1007 return -ENOSPC; 1008 } 1009 1010 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1011 if (ret) { 1012 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1013 return ret; 1014 } 1015 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1016 1017 return 0; 1018 } 1019 1020 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1021 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1022 { 1023 struct rtw89_core_tx_request tx_req = {0}; 1024 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1025 int ret; 1026 1027 tx_req.skb = skb; 1028 tx_req.sta = sta; 1029 tx_req.vif = vif; 1030 1031 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1032 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1033 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1034 rtw89_core_tx_wake(rtwdev, &tx_req); 1035 1036 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1037 if (ret) { 1038 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1039 return ret; 1040 } 1041 1042 if (qsel) 1043 *qsel = tx_req.desc_info.qsel; 1044 1045 return 0; 1046 } 1047 1048 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1049 { 1050 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1051 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1052 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1053 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1054 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1055 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1056 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1057 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1058 1059 return cpu_to_le32(dword); 1060 } 1061 1062 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1063 { 1064 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1065 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1066 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1067 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1068 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1069 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1070 1071 return cpu_to_le32(dword); 1072 } 1073 1074 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1075 { 1076 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1077 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1078 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1079 1080 return cpu_to_le32(dword); 1081 } 1082 1083 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1084 { 1085 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1086 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1087 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1088 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1089 1090 return cpu_to_le32(dword); 1091 } 1092 1093 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1094 { 1095 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1096 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1097 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1098 1099 return cpu_to_le32(dword); 1100 } 1101 1102 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1103 { 1104 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1105 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1106 1107 return cpu_to_le32(dword); 1108 } 1109 1110 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1111 { 1112 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1113 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1114 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1115 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1116 1117 return cpu_to_le32(dword); 1118 } 1119 1120 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1121 { 1122 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1123 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1124 1125 return cpu_to_le32(dword); 1126 } 1127 1128 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1129 { 1130 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1131 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1132 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1133 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1134 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1135 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1136 1137 return cpu_to_le32(dword); 1138 } 1139 1140 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1141 { 1142 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1143 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1144 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1145 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1146 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1147 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1148 1149 return cpu_to_le32(dword); 1150 } 1151 1152 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1153 { 1154 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1155 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1156 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1157 desc_info->data_retry_lowest_rate); 1158 1159 return cpu_to_le32(dword); 1160 } 1161 1162 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1163 { 1164 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1165 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1166 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1167 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1168 1169 return cpu_to_le32(dword); 1170 } 1171 1172 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1173 { 1174 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1175 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1176 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1177 1178 return cpu_to_le32(dword); 1179 } 1180 1181 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1182 { 1183 bool rts_en = !desc_info->is_bmc; 1184 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1185 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1186 1187 return cpu_to_le32(dword); 1188 } 1189 1190 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1191 struct rtw89_tx_desc_info *desc_info, 1192 void *txdesc) 1193 { 1194 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1195 struct rtw89_txwd_info *txwd_info; 1196 1197 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1198 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1199 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1200 1201 if (!desc_info->en_wd_info) 1202 return; 1203 1204 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1205 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1206 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1207 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1208 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1209 1210 } 1211 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1212 1213 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1214 struct rtw89_tx_desc_info *desc_info, 1215 void *txdesc) 1216 { 1217 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1218 struct rtw89_txwd_info *txwd_info; 1219 1220 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1221 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1222 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1223 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1224 if (desc_info->sec_en) { 1225 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1226 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1227 } 1228 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1229 1230 if (!desc_info->en_wd_info) 1231 return; 1232 1233 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1234 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1235 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1236 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1237 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1238 } 1239 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1240 1241 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1242 { 1243 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1244 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1245 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1246 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1247 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1248 1249 return cpu_to_le32(dword); 1250 } 1251 1252 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1253 { 1254 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1255 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1256 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1257 1258 return cpu_to_le32(dword); 1259 } 1260 1261 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1262 { 1263 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1264 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1265 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1266 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1267 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1268 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1269 1270 return cpu_to_le32(dword); 1271 } 1272 1273 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1274 { 1275 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq); 1276 1277 return cpu_to_le32(dword); 1278 } 1279 1280 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1281 { 1282 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1283 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1284 1285 return cpu_to_le32(dword); 1286 } 1287 1288 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1289 { 1290 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1291 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1292 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1293 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1294 1295 return cpu_to_le32(dword); 1296 } 1297 1298 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1299 { 1300 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1301 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1302 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1303 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1304 1305 return cpu_to_le32(dword); 1306 } 1307 1308 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1309 { 1310 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1311 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1312 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1313 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1314 1315 return cpu_to_le32(dword); 1316 } 1317 1318 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1319 { 1320 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1321 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1322 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1323 desc_info->data_retry_lowest_rate); 1324 1325 return cpu_to_le32(dword); 1326 } 1327 1328 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1329 { 1330 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1331 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1332 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1333 1334 return cpu_to_le32(dword); 1335 } 1336 1337 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1338 { 1339 bool rts_en = !desc_info->is_bmc; 1340 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1341 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1342 1343 return cpu_to_le32(dword); 1344 } 1345 1346 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1347 struct rtw89_tx_desc_info *desc_info, 1348 void *txdesc) 1349 { 1350 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1351 struct rtw89_txwd_info_v2 *txwd_info; 1352 1353 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1354 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1355 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1356 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1357 if (desc_info->sec_en) { 1358 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1359 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1360 } 1361 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1362 1363 if (!desc_info->en_wd_info) 1364 return; 1365 1366 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1367 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1368 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1369 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1370 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1371 } 1372 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1373 1374 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1375 { 1376 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1377 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1378 RTW89_CORE_RX_TYPE_FWDL : 1379 RTW89_CORE_RX_TYPE_H2C); 1380 1381 return cpu_to_le32(dword); 1382 } 1383 1384 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1385 struct rtw89_tx_desc_info *desc_info, 1386 void *txdesc) 1387 { 1388 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1389 1390 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1391 } 1392 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1393 1394 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1395 { 1396 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1397 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1398 RTW89_CORE_RX_TYPE_FWDL : 1399 RTW89_CORE_RX_TYPE_H2C); 1400 1401 return cpu_to_le32(dword); 1402 } 1403 1404 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1405 struct rtw89_tx_desc_info *desc_info, 1406 void *txdesc) 1407 { 1408 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1409 1410 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1411 } 1412 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1413 1414 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1415 struct sk_buff *skb, 1416 struct rtw89_rx_phy_ppdu *phy_ppdu) 1417 { 1418 const struct rtw89_chip_info *chip = rtwdev->chip; 1419 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1420 const struct rtw89_rxinfo_user *user; 1421 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1422 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1423 bool rx_cnt_valid = false; 1424 bool invalid = false; 1425 u8 plcp_size = 0; 1426 u8 *phy_sts; 1427 u8 usr_num; 1428 int i; 1429 1430 if (chip_gen == RTW89_CHIP_BE) { 1431 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1432 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1433 } 1434 1435 if (invalid) 1436 return -EINVAL; 1437 1438 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1439 if (chip_gen == RTW89_CHIP_BE) { 1440 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1441 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1442 } else { 1443 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1444 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1445 } 1446 if (usr_num > chip->ppdu_max_usr) { 1447 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1448 usr_num); 1449 return -EINVAL; 1450 } 1451 1452 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set by hardware, 1453 * so update mac_id by rxinfo_user[].mac_id. 1454 */ 1455 for (i = 0; i < usr_num && chip_gen == RTW89_CHIP_BE; i++) { 1456 user = &rxinfo->user[i]; 1457 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1458 continue; 1459 1460 phy_ppdu->mac_id = 1461 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1462 break; 1463 } 1464 1465 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1466 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1467 /* 8-byte alignment */ 1468 if (usr_num & BIT(0)) 1469 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1470 if (rx_cnt_valid) 1471 phy_sts += rx_cnt_size; 1472 phy_sts += plcp_size; 1473 1474 if (phy_sts > skb->data + skb->len) 1475 return -EINVAL; 1476 1477 phy_ppdu->buf = phy_sts; 1478 phy_ppdu->len = skb->data + skb->len - phy_sts; 1479 1480 return 0; 1481 } 1482 1483 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1484 struct ieee80211_sta *sta) 1485 { 1486 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1487 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1488 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1489 struct rtw89_hal *hal = &rtwdev->hal; 1490 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1491 u8 ant_pos = U8_MAX; 1492 u8 evm_pos = 0; 1493 int i; 1494 1495 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1496 return; 1497 1498 if (hal->ant_diversity && hal->antenna_rx) { 1499 ant_pos = __ffs(hal->antenna_rx); 1500 evm_pos = ant_pos; 1501 } 1502 1503 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1504 1505 if (ant_pos < ant_num) { 1506 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]); 1507 } else { 1508 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1509 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1510 } 1511 1512 if (phy_ppdu->ofdm.has) { 1513 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr); 1514 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min); 1515 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max); 1516 } 1517 } 1518 1519 #define VAR_LEN 0xff 1520 #define VAR_LEN_UNIT 8 1521 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1522 const struct rtw89_phy_sts_iehdr *iehdr) 1523 { 1524 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1525 [RTW89_CHIP_AX] = { 1526 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1527 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1528 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1529 }, 1530 [RTW89_CHIP_BE] = { 1531 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1532 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1533 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1534 }, 1535 }; 1536 const u8 *physts_ie_len_tab; 1537 u16 ie_len; 1538 u8 ie; 1539 1540 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1541 1542 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1543 if (physts_ie_len_tab[ie] != VAR_LEN) 1544 ie_len = physts_ie_len_tab[ie]; 1545 else 1546 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1547 1548 return ie_len; 1549 } 1550 1551 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1552 const struct rtw89_phy_sts_iehdr *iehdr, 1553 struct rtw89_rx_phy_ppdu *phy_ppdu) 1554 { 1555 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr; 1556 s16 cfo; 1557 u32 t; 1558 1559 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1560 1561 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1562 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1563 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1564 } 1565 1566 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1567 return; 1568 1569 if (!phy_ppdu->to_self) 1570 return; 1571 1572 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1573 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1574 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1575 phy_ppdu->ofdm.has = true; 1576 1577 /* sign conversion for S(12,2) */ 1578 if (rtwdev->chip->cfo_src_fd) { 1579 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1580 cfo = sign_extend32(t, 11); 1581 } else { 1582 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1583 cfo = sign_extend32(t, 11); 1584 } 1585 1586 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1587 } 1588 1589 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1590 const struct rtw89_phy_sts_iehdr *iehdr, 1591 struct rtw89_rx_phy_ppdu *phy_ppdu) 1592 { 1593 u8 ie; 1594 1595 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1596 1597 switch (ie) { 1598 case RTW89_PHYSTS_IE01_CMN_OFDM: 1599 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1600 break; 1601 default: 1602 break; 1603 } 1604 1605 return 0; 1606 } 1607 1608 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1609 { 1610 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1611 u8 *rssi = phy_ppdu->rssi; 1612 1613 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1614 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1615 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1616 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1617 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1618 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1619 } 1620 1621 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1622 struct rtw89_rx_phy_ppdu *phy_ppdu) 1623 { 1624 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1625 u32 len_from_header; 1626 bool physts_valid; 1627 1628 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1629 if (!physts_valid) 1630 return -EINVAL; 1631 1632 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1633 1634 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1635 len_from_header += PHY_STS_HDR_LEN; 1636 1637 if (len_from_header != phy_ppdu->len) { 1638 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1639 return -EINVAL; 1640 } 1641 rtw89_core_update_phy_ppdu(phy_ppdu); 1642 1643 return 0; 1644 } 1645 1646 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1647 struct rtw89_rx_phy_ppdu *phy_ppdu) 1648 { 1649 u16 ie_len; 1650 void *pos, *end; 1651 1652 /* mark invalid reports and bypass them */ 1653 if (phy_ppdu->ie < RTW89_CCK_PKT) 1654 return -EINVAL; 1655 1656 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1657 end = phy_ppdu->buf + phy_ppdu->len; 1658 while (pos < end) { 1659 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1660 1661 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1662 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1663 pos += ie_len; 1664 if (pos > end || ie_len == 0) { 1665 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1666 "phy status parse failed\n"); 1667 return -EINVAL; 1668 } 1669 } 1670 1671 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1672 1673 return 0; 1674 } 1675 1676 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1677 struct rtw89_rx_phy_ppdu *phy_ppdu) 1678 { 1679 int ret; 1680 1681 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1682 if (ret) 1683 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1684 else 1685 phy_ppdu->valid = true; 1686 1687 ieee80211_iterate_stations_atomic(rtwdev->hw, 1688 rtw89_core_rx_process_phy_ppdu_iter, 1689 phy_ppdu); 1690 } 1691 1692 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 1693 u8 desc_info_gi, 1694 bool rx_status, bool eht) 1695 { 1696 switch (desc_info_gi) { 1697 case RTW89_GILTF_SGI_4XHE08: 1698 case RTW89_GILTF_2XHE08: 1699 case RTW89_GILTF_1XHE08: 1700 return eht ? NL80211_RATE_INFO_EHT_GI_0_8 : 1701 NL80211_RATE_INFO_HE_GI_0_8; 1702 case RTW89_GILTF_2XHE16: 1703 case RTW89_GILTF_1XHE16: 1704 return eht ? NL80211_RATE_INFO_EHT_GI_1_6 : 1705 NL80211_RATE_INFO_HE_GI_1_6; 1706 case RTW89_GILTF_LGI_4XHE32: 1707 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1708 NL80211_RATE_INFO_HE_GI_3_2; 1709 default: 1710 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1711 if (rx_status) 1712 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1713 NL80211_RATE_INFO_HE_GI_3_2; 1714 return U8_MAX; 1715 } 1716 } 1717 1718 static 1719 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 1720 bool eht) 1721 { 1722 if (eht) 1723 return status->eht.gi == gi_ltf; 1724 1725 return status->he_gi == gi_ltf; 1726 } 1727 1728 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1729 struct rtw89_rx_desc_info *desc_info, 1730 struct ieee80211_rx_status *status) 1731 { 1732 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1733 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1734 bool eht = false; 1735 u16 data_rate; 1736 bool ret; 1737 1738 data_rate = desc_info->data_rate; 1739 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1740 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1741 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1742 /* rate_idx is still hardware value here */ 1743 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1744 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1745 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 1746 data_rate_mode == DATA_RATE_MODE_HE || 1747 data_rate_mode == DATA_RATE_MODE_EHT) { 1748 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1749 } else { 1750 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1751 } 1752 1753 eht = data_rate_mode == DATA_RATE_MODE_EHT; 1754 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1755 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 1756 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1757 status->rate_idx == rate_idx && 1758 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 1759 status->bw == bw; 1760 1761 return ret; 1762 } 1763 1764 struct rtw89_vif_rx_stats_iter_data { 1765 struct rtw89_dev *rtwdev; 1766 struct rtw89_rx_phy_ppdu *phy_ppdu; 1767 struct rtw89_rx_desc_info *desc_info; 1768 struct sk_buff *skb; 1769 const u8 *bssid; 1770 }; 1771 1772 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1773 struct ieee80211_vif *vif, 1774 struct sk_buff *skb) 1775 { 1776 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1777 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1778 u8 *pos, *end, type, tf_bw; 1779 u16 aid, tf_rua; 1780 1781 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1782 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1783 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1784 return; 1785 1786 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1787 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 1788 return; 1789 1790 end = (u8 *)tf + skb->len; 1791 pos = tf->variable; 1792 1793 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1794 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1795 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 1796 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 1797 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1798 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 1799 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1800 tf_rua, tf_bw); 1801 1802 if (aid == RTW89_TF_PAD) 1803 break; 1804 1805 if (aid == vif->cfg.aid) { 1806 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 1807 1808 rtwvif->stats.rx_tf_acc++; 1809 rtwdev->stats.rx_tf_acc++; 1810 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 1811 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 1812 rtwvif->pwr_diff_en = true; 1813 break; 1814 } 1815 1816 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1817 } 1818 } 1819 1820 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work) 1821 { 1822 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1823 cancel_6ghz_probe_work); 1824 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1825 struct rtw89_pktofld_info *info; 1826 1827 mutex_lock(&rtwdev->mutex); 1828 1829 if (!rtwdev->scanning) 1830 goto out; 1831 1832 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1833 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 1834 continue; 1835 1836 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1837 1838 /* Don't delete/free info from pkt_list at this moment. Let it 1839 * be deleted/freed in rtw89_release_pkt_list() after scanning, 1840 * since if during scanning, pkt_list is accessed in bottom half. 1841 */ 1842 } 1843 1844 out: 1845 mutex_unlock(&rtwdev->mutex); 1846 } 1847 1848 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1849 struct sk_buff *skb) 1850 { 1851 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1852 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1853 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1854 struct rtw89_pktofld_info *info; 1855 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1856 bool queue_work = false; 1857 1858 if (rx_status->band != NL80211_BAND_6GHZ) 1859 return; 1860 1861 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1862 1863 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1864 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1865 info->cancel = true; 1866 queue_work = true; 1867 continue; 1868 } 1869 1870 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1871 continue; 1872 1873 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 1874 info->cancel = true; 1875 queue_work = true; 1876 } 1877 } 1878 1879 if (queue_work) 1880 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work); 1881 } 1882 1883 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif *rtwvif, 1884 struct ieee80211_hdr *hdr, size_t len) 1885 { 1886 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 1887 1888 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 1889 return; 1890 1891 WRITE_ONCE(rtwvif->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 1892 } 1893 1894 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1895 struct ieee80211_vif *vif) 1896 { 1897 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1898 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1899 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1900 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1901 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1902 struct sk_buff *skb = iter_data->skb; 1903 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1904 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 1905 const u8 *bssid = iter_data->bssid; 1906 1907 if (rtwdev->scanning && 1908 (ieee80211_is_beacon(hdr->frame_control) || 1909 ieee80211_is_probe_resp(hdr->frame_control))) 1910 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1911 1912 if (!vif->bss_conf.bssid) 1913 return; 1914 1915 if (ieee80211_is_trigger(hdr->frame_control)) { 1916 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1917 return; 1918 } 1919 1920 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1921 return; 1922 1923 if (ieee80211_is_beacon(hdr->frame_control)) { 1924 if (vif->type == NL80211_IFTYPE_STATION) { 1925 rtw89_vif_sync_bcn_tsf(rtwvif, hdr, skb->len); 1926 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 1927 } 1928 pkt_stat->beacon_nr++; 1929 } 1930 1931 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1932 return; 1933 1934 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1935 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1936 1937 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1938 } 1939 1940 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1941 struct rtw89_rx_phy_ppdu *phy_ppdu, 1942 struct rtw89_rx_desc_info *desc_info, 1943 struct sk_buff *skb) 1944 { 1945 struct rtw89_vif_rx_stats_iter_data iter_data; 1946 1947 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1948 1949 iter_data.rtwdev = rtwdev; 1950 iter_data.phy_ppdu = phy_ppdu; 1951 iter_data.desc_info = desc_info; 1952 iter_data.skb = skb; 1953 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1954 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1955 } 1956 1957 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1958 struct ieee80211_rx_status *status) 1959 { 1960 const struct rtw89_chan_rcd *rcd = 1961 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1962 u16 chan = rcd->prev_primary_channel; 1963 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 1964 1965 if (status->band != NL80211_BAND_2GHZ && 1966 status->encoding == RX_ENC_LEGACY && 1967 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1968 status->freq = ieee80211_channel_to_frequency(chan, band); 1969 status->band = band; 1970 } 1971 } 1972 1973 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1974 { 1975 if (rx_status->band == NL80211_BAND_2GHZ || 1976 rx_status->encoding != RX_ENC_LEGACY) 1977 return; 1978 1979 /* Some control frames' freq(ACKs in this case) are reported wrong due 1980 * to FW notify timing, set to lowest rate to prevent overflow. 1981 */ 1982 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1983 rx_status->rate_idx = 0; 1984 return; 1985 } 1986 1987 /* No 4 CCK rates for non-2G */ 1988 rx_status->rate_idx -= 4; 1989 } 1990 1991 static 1992 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 1993 struct ieee80211_rx_status *rx_status, 1994 struct rtw89_rx_phy_ppdu *phy_ppdu) 1995 { 1996 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 1997 return; 1998 1999 if (!phy_ppdu) 2000 return; 2001 2002 if (phy_ppdu->ldpc) 2003 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2004 if (phy_ppdu->stbc) 2005 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 2006 } 2007 2008 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 2009 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 2010 [RATE_INFO_BW_5] = U8_MAX, 2011 [RATE_INFO_BW_10] = U8_MAX, 2012 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 2013 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 2014 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 2015 [RATE_INFO_BW_HE_RU] = U8_MAX, 2016 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 2017 [RATE_INFO_BW_EHT_RU] = U8_MAX, 2018 }; 2019 2020 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2021 struct sk_buff *skb, 2022 struct ieee80211_rx_status *rx_status) 2023 { 2024 struct ieee80211_radiotap_eht_usig *usig; 2025 struct ieee80211_radiotap_eht *eht; 2026 struct ieee80211_radiotap_tlv *tlv; 2027 int eht_len = struct_size(eht, user_info, 1); 2028 int usig_len = sizeof(*usig); 2029 int len; 2030 u8 bw; 2031 2032 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2033 sizeof(*tlv) + ALIGN(usig_len, 4); 2034 2035 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2036 skb_reset_mac_header(skb); 2037 2038 /* EHT */ 2039 tlv = skb_push(skb, len); 2040 memset(tlv, 0, len); 2041 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2042 tlv->len = cpu_to_le16(eht_len); 2043 2044 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2045 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2046 eht->data[0] = 2047 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2048 2049 eht->user_info[0] = 2050 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2051 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 2052 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 2053 eht->user_info[0] |= 2054 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2055 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2056 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 2057 eht->user_info[0] |= 2058 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 2059 2060 /* U-SIG */ 2061 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2062 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2063 tlv->len = cpu_to_le16(usig_len); 2064 2065 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2066 return; 2067 2068 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2069 if (bw == U8_MAX) 2070 return; 2071 2072 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2073 usig->common = 2074 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2075 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2076 } 2077 2078 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2079 struct sk_buff *skb, 2080 struct ieee80211_rx_status *rx_status) 2081 { 2082 static const struct ieee80211_radiotap_he known_he = { 2083 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2084 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 2085 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 2086 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2087 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2088 }; 2089 struct ieee80211_radiotap_he *he; 2090 2091 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2092 return; 2093 2094 if (rx_status->encoding == RX_ENC_HE) { 2095 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2096 he = skb_push(skb, sizeof(*he)); 2097 *he = known_he; 2098 } else if (rx_status->encoding == RX_ENC_EHT) { 2099 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2100 } 2101 } 2102 2103 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2104 struct rtw89_rx_phy_ppdu *phy_ppdu, 2105 struct rtw89_rx_desc_info *desc_info, 2106 struct sk_buff *skb_ppdu, 2107 struct ieee80211_rx_status *rx_status) 2108 { 2109 struct napi_struct *napi = &rtwdev->napi; 2110 2111 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2112 if (unlikely(!napi_is_scheduled(napi))) 2113 napi = NULL; 2114 2115 rtw89_core_hw_to_sband_rate(rx_status); 2116 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2117 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 2118 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2119 /* In low power mode, it does RX in thread context. */ 2120 local_bh_disable(); 2121 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2122 local_bh_enable(); 2123 rtwdev->napi_budget_countdown--; 2124 } 2125 2126 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2127 struct rtw89_rx_phy_ppdu *phy_ppdu, 2128 struct rtw89_rx_desc_info *desc_info, 2129 struct sk_buff *skb) 2130 { 2131 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2132 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2133 struct sk_buff *skb_ppdu = NULL, *tmp; 2134 struct ieee80211_rx_status *rx_status; 2135 2136 if (curr > RTW89_MAX_PPDU_CNT) 2137 return; 2138 2139 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2140 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2141 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2142 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2143 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2144 rtw89_correct_cck_chan(rtwdev, rx_status); 2145 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2146 } 2147 } 2148 2149 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2150 struct rtw89_rx_desc_info *desc_info, 2151 struct sk_buff *skb) 2152 { 2153 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2154 .len = skb->len, 2155 .to_self = desc_info->addr1_match, 2156 .rate = desc_info->data_rate, 2157 .mac_id = desc_info->mac_id}; 2158 int ret; 2159 2160 if (desc_info->mac_info_valid) { 2161 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2162 if (ret) 2163 goto out; 2164 } 2165 2166 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2167 if (ret) 2168 goto out; 2169 2170 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2171 2172 out: 2173 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2174 dev_kfree_skb_any(skb); 2175 } 2176 2177 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2178 struct rtw89_rx_desc_info *desc_info, 2179 struct sk_buff *skb) 2180 { 2181 switch (desc_info->pkt_type) { 2182 case RTW89_CORE_RX_TYPE_C2H: 2183 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2184 break; 2185 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2186 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2187 break; 2188 default: 2189 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2190 desc_info->pkt_type); 2191 dev_kfree_skb_any(skb); 2192 break; 2193 } 2194 } 2195 2196 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2197 struct rtw89_rx_desc_info *desc_info, 2198 u8 *data, u32 data_offset) 2199 { 2200 const struct rtw89_chip_info *chip = rtwdev->chip; 2201 struct rtw89_rxdesc_short *rxd_s; 2202 struct rtw89_rxdesc_long *rxd_l; 2203 u8 shift_len, drv_info_len; 2204 2205 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2206 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2207 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2208 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2209 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2210 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2211 if (chip->chip_id == RTL8852C) 2212 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2213 else 2214 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2215 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2216 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2217 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2218 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2219 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2220 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2221 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2222 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2223 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2224 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2225 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2226 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2227 2228 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2229 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2230 desc_info->offset = data_offset + shift_len + drv_info_len; 2231 if (desc_info->long_rxdesc) 2232 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2233 else 2234 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2235 desc_info->ready = true; 2236 2237 if (!desc_info->long_rxdesc) 2238 return; 2239 2240 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2241 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2242 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2243 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2244 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2245 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2246 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2247 } 2248 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2249 2250 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2251 struct rtw89_rx_desc_info *desc_info, 2252 u8 *data, u32 data_offset) 2253 { 2254 struct rtw89_rxdesc_short_v2 *rxd_s; 2255 struct rtw89_rxdesc_long_v2 *rxd_l; 2256 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2257 2258 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2259 2260 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2261 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2262 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2263 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2264 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2265 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2266 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2267 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2268 desc_info->mac_info_valid = true; 2269 2270 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2271 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2272 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2273 2274 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2275 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2276 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2277 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2278 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2279 2280 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2281 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2282 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2283 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2284 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2285 2286 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2287 2288 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2289 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2290 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2291 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2292 desc_info->offset = data_offset + shift_len + drv_info_len + 2293 phy_rtp_len + hdr_cnv_len; 2294 2295 if (desc_info->long_rxdesc) 2296 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2297 else 2298 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2299 desc_info->ready = true; 2300 2301 if (!desc_info->long_rxdesc) 2302 return; 2303 2304 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2305 2306 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2307 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2308 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2309 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2310 2311 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2312 } 2313 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2314 2315 struct rtw89_core_iter_rx_status { 2316 struct rtw89_dev *rtwdev; 2317 struct ieee80211_rx_status *rx_status; 2318 struct rtw89_rx_desc_info *desc_info; 2319 u8 mac_id; 2320 }; 2321 2322 static 2323 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2324 { 2325 struct rtw89_core_iter_rx_status *iter_data = 2326 (struct rtw89_core_iter_rx_status *)data; 2327 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2328 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2329 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2330 u8 mac_id = iter_data->mac_id; 2331 2332 if (mac_id != rtwsta->mac_id) 2333 return; 2334 2335 rtwsta->rx_status = *rx_status; 2336 rtwsta->rx_hw_rate = desc_info->data_rate; 2337 } 2338 2339 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2340 struct rtw89_rx_desc_info *desc_info, 2341 struct ieee80211_rx_status *rx_status) 2342 { 2343 struct rtw89_core_iter_rx_status iter_data; 2344 2345 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2346 return; 2347 2348 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2349 return; 2350 2351 iter_data.rtwdev = rtwdev; 2352 iter_data.rx_status = rx_status; 2353 iter_data.desc_info = desc_info; 2354 iter_data.mac_id = desc_info->mac_id; 2355 ieee80211_iterate_stations_atomic(rtwdev->hw, 2356 rtw89_core_stats_sta_rx_status_iter, 2357 &iter_data); 2358 } 2359 2360 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2361 struct rtw89_rx_desc_info *desc_info, 2362 struct ieee80211_rx_status *rx_status) 2363 { 2364 const struct cfg80211_chan_def *chandef = 2365 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 2366 u16 data_rate; 2367 u8 data_rate_mode; 2368 bool eht = false; 2369 u8 gi; 2370 2371 /* currently using single PHY */ 2372 rx_status->freq = chandef->chan->center_freq; 2373 rx_status->band = chandef->chan->band; 2374 2375 if (rtwdev->scanning && 2376 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2377 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2378 u8 chan = cur->primary_channel; 2379 u8 band = cur->band_type; 2380 enum nl80211_band nl_band; 2381 2382 nl_band = rtw89_hw_to_nl80211_band(band); 2383 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2384 rx_status->band = nl_band; 2385 } 2386 2387 if (desc_info->icv_err || desc_info->crc32_err) 2388 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2389 2390 if (desc_info->hw_dec && 2391 !(desc_info->sw_dec || desc_info->icv_err)) 2392 rx_status->flag |= RX_FLAG_DECRYPTED; 2393 2394 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2395 2396 data_rate = desc_info->data_rate; 2397 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2398 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2399 rx_status->encoding = RX_ENC_LEGACY; 2400 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2401 /* convert rate_idx after we get the correct band */ 2402 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2403 rx_status->encoding = RX_ENC_HT; 2404 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2405 if (desc_info->gi_ltf) 2406 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2407 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2408 rx_status->encoding = RX_ENC_VHT; 2409 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2410 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2411 if (desc_info->gi_ltf) 2412 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2413 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2414 rx_status->encoding = RX_ENC_HE; 2415 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2416 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2417 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2418 rx_status->encoding = RX_ENC_EHT; 2419 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2420 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2421 eht = true; 2422 } else { 2423 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2424 } 2425 2426 /* he_gi is used to match ppdu, so we always fill it. */ 2427 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2428 if (eht) 2429 rx_status->eht.gi = gi; 2430 else 2431 rx_status->he_gi = gi; 2432 rx_status->flag |= RX_FLAG_MACTIME_START; 2433 rx_status->mactime = desc_info->free_run_cnt; 2434 2435 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2436 } 2437 2438 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2439 { 2440 const struct rtw89_chip_info *chip = rtwdev->chip; 2441 2442 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2443 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2444 return RTW89_PS_MODE_NONE; 2445 2446 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2447 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2448 return RTW89_PS_MODE_PWR_GATED; 2449 2450 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2451 return RTW89_PS_MODE_CLK_GATED; 2452 2453 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2454 return RTW89_PS_MODE_RFOFF; 2455 2456 return RTW89_PS_MODE_NONE; 2457 } 2458 2459 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2460 struct rtw89_rx_desc_info *desc_info) 2461 { 2462 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2463 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2464 struct ieee80211_rx_status *rx_status; 2465 struct sk_buff *skb_ppdu, *tmp; 2466 2467 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2468 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2469 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2470 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2471 } 2472 } 2473 2474 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2475 struct rtw89_rx_desc_info *desc_info, 2476 struct sk_buff *skb) 2477 { 2478 struct ieee80211_rx_status *rx_status; 2479 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2480 u8 ppdu_cnt = desc_info->ppdu_cnt; 2481 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2482 2483 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2484 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2485 return; 2486 } 2487 2488 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2489 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2490 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2491 } 2492 2493 rx_status = IEEE80211_SKB_RXCB(skb); 2494 memset(rx_status, 0, sizeof(*rx_status)); 2495 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2496 if (desc_info->long_rxdesc && 2497 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2498 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2499 else 2500 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2501 } 2502 EXPORT_SYMBOL(rtw89_core_rx); 2503 2504 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2505 { 2506 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2507 return; 2508 2509 napi_enable(&rtwdev->napi); 2510 } 2511 EXPORT_SYMBOL(rtw89_core_napi_start); 2512 2513 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2514 { 2515 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2516 return; 2517 2518 napi_synchronize(&rtwdev->napi); 2519 napi_disable(&rtwdev->napi); 2520 } 2521 EXPORT_SYMBOL(rtw89_core_napi_stop); 2522 2523 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2524 { 2525 rtwdev->netdev = alloc_netdev_dummy(0); 2526 if (!rtwdev->netdev) 2527 return -ENOMEM; 2528 2529 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 2530 rtwdev->hci.ops->napi_poll); 2531 return 0; 2532 } 2533 EXPORT_SYMBOL(rtw89_core_napi_init); 2534 2535 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2536 { 2537 rtw89_core_napi_stop(rtwdev); 2538 netif_napi_del(&rtwdev->napi); 2539 free_netdev(rtwdev->netdev); 2540 } 2541 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2542 2543 static void rtw89_core_ba_work(struct work_struct *work) 2544 { 2545 struct rtw89_dev *rtwdev = 2546 container_of(work, struct rtw89_dev, ba_work); 2547 struct rtw89_txq *rtwtxq, *tmp; 2548 int ret; 2549 2550 spin_lock_bh(&rtwdev->ba_lock); 2551 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2552 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2553 struct ieee80211_sta *sta = txq->sta; 2554 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2555 u8 tid = txq->tid; 2556 2557 if (!sta) { 2558 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2559 goto skip_ba_work; 2560 } 2561 2562 if (rtwsta->disassoc) { 2563 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2564 "cannot start BA with disassoc sta\n"); 2565 goto skip_ba_work; 2566 } 2567 2568 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2569 if (ret) { 2570 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2571 "failed to setup BA session for %pM:%2d: %d\n", 2572 sta->addr, tid, ret); 2573 if (ret == -EINVAL) 2574 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2575 } 2576 skip_ba_work: 2577 list_del_init(&rtwtxq->list); 2578 } 2579 spin_unlock_bh(&rtwdev->ba_lock); 2580 } 2581 2582 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2583 struct ieee80211_sta *sta) 2584 { 2585 struct rtw89_txq *rtwtxq, *tmp; 2586 2587 spin_lock_bh(&rtwdev->ba_lock); 2588 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2589 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2590 2591 if (sta == txq->sta) 2592 list_del_init(&rtwtxq->list); 2593 } 2594 spin_unlock_bh(&rtwdev->ba_lock); 2595 } 2596 2597 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2598 struct ieee80211_sta *sta) 2599 { 2600 struct rtw89_txq *rtwtxq, *tmp; 2601 2602 spin_lock_bh(&rtwdev->ba_lock); 2603 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2604 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2605 2606 if (sta == txq->sta) { 2607 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2608 list_del_init(&rtwtxq->list); 2609 } 2610 } 2611 spin_unlock_bh(&rtwdev->ba_lock); 2612 } 2613 2614 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2615 struct ieee80211_sta *sta) 2616 { 2617 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2618 struct sk_buff *skb, *tmp; 2619 2620 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2621 skb_unlink(skb, &rtwsta->roc_queue); 2622 dev_kfree_skb_any(skb); 2623 } 2624 } 2625 2626 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2627 struct rtw89_txq *rtwtxq) 2628 { 2629 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2630 struct ieee80211_sta *sta = txq->sta; 2631 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2632 2633 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2634 return; 2635 2636 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2637 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2638 return; 2639 2640 spin_lock_bh(&rtwdev->ba_lock); 2641 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2642 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2643 spin_unlock_bh(&rtwdev->ba_lock); 2644 2645 ieee80211_stop_tx_ba_session(sta, txq->tid); 2646 cancel_delayed_work(&rtwdev->forbid_ba_work); 2647 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2648 RTW89_FORBID_BA_TIMER); 2649 } 2650 2651 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2652 struct rtw89_txq *rtwtxq, 2653 struct sk_buff *skb) 2654 { 2655 struct ieee80211_hw *hw = rtwdev->hw; 2656 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2657 struct ieee80211_sta *sta = txq->sta; 2658 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2659 2660 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2661 return; 2662 2663 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2664 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2665 return; 2666 } 2667 2668 if (unlikely(!sta)) 2669 return; 2670 2671 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2672 return; 2673 2674 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2675 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2676 return; 2677 } 2678 2679 spin_lock_bh(&rtwdev->ba_lock); 2680 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2681 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2682 ieee80211_queue_work(hw, &rtwdev->ba_work); 2683 } 2684 spin_unlock_bh(&rtwdev->ba_lock); 2685 } 2686 2687 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2688 struct rtw89_txq *rtwtxq, 2689 unsigned long frame_cnt, 2690 unsigned long byte_cnt) 2691 { 2692 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2693 struct ieee80211_vif *vif = txq->vif; 2694 struct ieee80211_sta *sta = txq->sta; 2695 struct sk_buff *skb; 2696 unsigned long i; 2697 int ret; 2698 2699 rcu_read_lock(); 2700 for (i = 0; i < frame_cnt; i++) { 2701 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2702 if (!skb) { 2703 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2704 goto out; 2705 } 2706 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2707 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2708 if (ret) { 2709 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2710 ieee80211_free_txskb(rtwdev->hw, skb); 2711 break; 2712 } 2713 } 2714 out: 2715 rcu_read_unlock(); 2716 } 2717 2718 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2719 { 2720 u8 qsel, ch_dma; 2721 2722 qsel = rtw89_core_get_qsel(rtwdev, tid); 2723 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2724 2725 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2726 } 2727 2728 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2729 struct ieee80211_txq *txq, 2730 unsigned long *frame_cnt, 2731 bool *sched_txq, bool *reinvoke) 2732 { 2733 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2734 struct ieee80211_sta *sta = txq->sta; 2735 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2736 2737 if (!sta || rtwsta->max_agg_wait <= 0) 2738 return false; 2739 2740 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2741 return false; 2742 2743 if (*frame_cnt > 1) { 2744 *frame_cnt -= 1; 2745 *sched_txq = true; 2746 *reinvoke = true; 2747 rtwtxq->wait_cnt = 1; 2748 return false; 2749 } 2750 2751 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2752 *reinvoke = true; 2753 rtwtxq->wait_cnt++; 2754 return true; 2755 } 2756 2757 rtwtxq->wait_cnt = 0; 2758 return false; 2759 } 2760 2761 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2762 { 2763 struct ieee80211_hw *hw = rtwdev->hw; 2764 struct ieee80211_txq *txq; 2765 struct rtw89_vif *rtwvif; 2766 struct rtw89_txq *rtwtxq; 2767 unsigned long frame_cnt; 2768 unsigned long byte_cnt; 2769 u32 tx_resource; 2770 bool sched_txq; 2771 2772 ieee80211_txq_schedule_start(hw, ac); 2773 while ((txq = ieee80211_next_txq(hw, ac))) { 2774 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2775 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv; 2776 2777 if (rtwvif->offchan) { 2778 ieee80211_return_txq(hw, txq, true); 2779 continue; 2780 } 2781 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2782 sched_txq = false; 2783 2784 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2785 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2786 ieee80211_return_txq(hw, txq, true); 2787 continue; 2788 } 2789 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2790 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2791 ieee80211_return_txq(hw, txq, sched_txq); 2792 if (frame_cnt != 0) 2793 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2794 2795 /* bound of tx_resource could get stuck due to burst traffic */ 2796 if (frame_cnt == tx_resource) 2797 *reinvoke = true; 2798 } 2799 ieee80211_txq_schedule_end(hw, ac); 2800 } 2801 2802 static void rtw89_ips_work(struct work_struct *work) 2803 { 2804 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2805 ips_work); 2806 mutex_lock(&rtwdev->mutex); 2807 rtw89_enter_ips_by_hwflags(rtwdev); 2808 mutex_unlock(&rtwdev->mutex); 2809 } 2810 2811 static void rtw89_core_txq_work(struct work_struct *w) 2812 { 2813 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2814 bool reinvoke = false; 2815 u8 ac; 2816 2817 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2818 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2819 2820 if (reinvoke) { 2821 /* reinvoke to process the last frame */ 2822 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2823 } 2824 } 2825 2826 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2827 { 2828 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2829 txq_reinvoke_work.work); 2830 2831 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2832 } 2833 2834 static void rtw89_forbid_ba_work(struct work_struct *w) 2835 { 2836 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2837 forbid_ba_work.work); 2838 struct rtw89_txq *rtwtxq, *tmp; 2839 2840 spin_lock_bh(&rtwdev->ba_lock); 2841 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2842 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2843 list_del_init(&rtwtxq->list); 2844 } 2845 spin_unlock_bh(&rtwdev->ba_lock); 2846 } 2847 2848 static void rtw89_core_sta_pending_tx_iter(void *data, 2849 struct ieee80211_sta *sta) 2850 { 2851 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2852 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif; 2853 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2854 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2855 struct sk_buff *skb, *tmp; 2856 int qsel, ret; 2857 2858 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx) 2859 return; 2860 2861 if (skb_queue_len(&rtwsta->roc_queue) == 0) 2862 return; 2863 2864 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2865 skb_unlink(skb, &rtwsta->roc_queue); 2866 2867 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2868 if (ret) { 2869 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 2870 dev_kfree_skb_any(skb); 2871 } else { 2872 rtw89_core_tx_kick_off(rtwdev, qsel); 2873 } 2874 } 2875 } 2876 2877 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 2878 struct rtw89_vif *rtwvif) 2879 { 2880 ieee80211_iterate_stations_atomic(rtwdev->hw, 2881 rtw89_core_sta_pending_tx_iter, 2882 rtwvif); 2883 } 2884 2885 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 2886 struct rtw89_vif *rtwvif, bool qos, bool ps) 2887 { 2888 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2889 struct ieee80211_sta *sta; 2890 struct ieee80211_hdr *hdr; 2891 struct sk_buff *skb; 2892 int ret, qsel; 2893 2894 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 2895 return 0; 2896 2897 rcu_read_lock(); 2898 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 2899 if (!sta) { 2900 ret = -EINVAL; 2901 goto out; 2902 } 2903 2904 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos); 2905 if (!skb) { 2906 ret = -ENOMEM; 2907 goto out; 2908 } 2909 2910 hdr = (struct ieee80211_hdr *)skb->data; 2911 if (ps) 2912 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2913 2914 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2915 if (ret) { 2916 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 2917 dev_kfree_skb_any(skb); 2918 goto out; 2919 } 2920 2921 rcu_read_unlock(); 2922 2923 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 2924 RTW89_ROC_TX_TIMEOUT); 2925 out: 2926 rcu_read_unlock(); 2927 2928 return ret; 2929 } 2930 2931 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2932 { 2933 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2934 struct ieee80211_hw *hw = rtwdev->hw; 2935 struct rtw89_roc *roc = &rtwvif->roc; 2936 struct cfg80211_chan_def roc_chan; 2937 struct rtw89_vif *tmp; 2938 int ret; 2939 2940 lockdep_assert_held(&rtwdev->mutex); 2941 2942 rtw89_leave_ips_by_hwflags(rtwdev); 2943 rtw89_leave_lps(rtwdev); 2944 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC); 2945 2946 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true); 2947 if (ret) 2948 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2949 "roc send null-1 failed: %d\n", ret); 2950 2951 rtw89_for_each_rtwvif(rtwdev, tmp) 2952 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2953 tmp->offchan = true; 2954 2955 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 2956 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan); 2957 rtw89_set_channel(rtwdev); 2958 rtw89_write32_clr(rtwdev, 2959 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2960 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 2961 2962 ieee80211_ready_on_channel(hw); 2963 cancel_delayed_work(&rtwvif->roc.roc_work); 2964 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 2965 msecs_to_jiffies(rtwvif->roc.duration)); 2966 } 2967 2968 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2969 { 2970 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2971 struct ieee80211_hw *hw = rtwdev->hw; 2972 struct rtw89_roc *roc = &rtwvif->roc; 2973 struct rtw89_vif *tmp; 2974 int ret; 2975 2976 lockdep_assert_held(&rtwdev->mutex); 2977 2978 ieee80211_remain_on_channel_expired(hw); 2979 2980 rtw89_leave_ips_by_hwflags(rtwdev); 2981 rtw89_leave_lps(rtwdev); 2982 2983 rtw89_write32_mask(rtwdev, 2984 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2985 B_AX_RX_FLTR_CFG_MASK, 2986 rtwdev->hal.rx_fltr); 2987 2988 roc->state = RTW89_ROC_IDLE; 2989 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL); 2990 rtw89_chanctx_proceed(rtwdev); 2991 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false); 2992 if (ret) 2993 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2994 "roc send null-0 failed: %d\n", ret); 2995 2996 rtw89_for_each_rtwvif(rtwdev, tmp) 2997 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2998 tmp->offchan = false; 2999 3000 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif); 3001 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3002 3003 if (hw->conf.flags & IEEE80211_CONF_IDLE) 3004 ieee80211_queue_delayed_work(hw, &roc->roc_work, 3005 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 3006 } 3007 3008 void rtw89_roc_work(struct work_struct *work) 3009 { 3010 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3011 roc.roc_work.work); 3012 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3013 struct rtw89_roc *roc = &rtwvif->roc; 3014 3015 mutex_lock(&rtwdev->mutex); 3016 3017 switch (roc->state) { 3018 case RTW89_ROC_IDLE: 3019 rtw89_enter_ips_by_hwflags(rtwdev); 3020 break; 3021 case RTW89_ROC_MGMT: 3022 case RTW89_ROC_NORMAL: 3023 rtw89_roc_end(rtwdev, rtwvif); 3024 break; 3025 default: 3026 break; 3027 } 3028 3029 mutex_unlock(&rtwdev->mutex); 3030 } 3031 3032 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3033 u32 throughput, u64 cnt) 3034 { 3035 if (cnt < 100) 3036 return RTW89_TFC_IDLE; 3037 if (throughput > 50) 3038 return RTW89_TFC_HIGH; 3039 if (throughput > 10) 3040 return RTW89_TFC_MID; 3041 if (throughput > 2) 3042 return RTW89_TFC_LOW; 3043 return RTW89_TFC_ULTRA_LOW; 3044 } 3045 3046 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3047 struct rtw89_traffic_stats *stats) 3048 { 3049 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3050 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3051 3052 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 3053 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3054 3055 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3056 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3057 3058 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3059 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3060 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3061 stats->tx_cnt); 3062 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3063 stats->rx_cnt); 3064 stats->tx_avg_len = stats->tx_cnt ? 3065 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3066 stats->rx_avg_len = stats->rx_cnt ? 3067 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3068 3069 stats->tx_unicast = 0; 3070 stats->rx_unicast = 0; 3071 stats->tx_cnt = 0; 3072 stats->rx_cnt = 0; 3073 stats->rx_tf_periodic = stats->rx_tf_acc; 3074 stats->rx_tf_acc = 0; 3075 3076 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3077 return true; 3078 3079 return false; 3080 } 3081 3082 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3083 { 3084 struct rtw89_vif *rtwvif; 3085 bool tfc_changed; 3086 3087 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3088 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3089 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3090 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif); 3091 } 3092 3093 return tfc_changed; 3094 } 3095 3096 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3097 { 3098 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 3099 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 3100 rtwvif->tdls_peer) 3101 return; 3102 3103 if (rtwvif->offchan) 3104 return; 3105 3106 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 3107 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 3108 rtw89_enter_lps(rtwdev, rtwvif, true); 3109 } 3110 3111 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3112 { 3113 struct rtw89_vif *rtwvif; 3114 3115 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3116 rtw89_vif_enter_lps(rtwdev, rtwvif); 3117 } 3118 3119 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3120 { 3121 enum rtw89_entity_mode mode; 3122 3123 mode = rtw89_get_entity_mode(rtwdev); 3124 if (mode == RTW89_ENTITY_MODE_MCC) 3125 return; 3126 3127 rtw89_chip_rfk_track(rtwdev); 3128 } 3129 3130 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3131 { 3132 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3133 3134 if (mode == RTW89_ENTITY_MODE_MCC) 3135 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3136 else 3137 rtw89_process_p2p_ps(rtwdev, vif); 3138 } 3139 3140 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3141 struct rtw89_traffic_stats *stats) 3142 { 3143 stats->tx_unicast = 0; 3144 stats->rx_unicast = 0; 3145 stats->tx_cnt = 0; 3146 stats->rx_cnt = 0; 3147 ewma_tp_init(&stats->tx_ewma_tp); 3148 ewma_tp_init(&stats->rx_ewma_tp); 3149 } 3150 3151 static void rtw89_track_work(struct work_struct *work) 3152 { 3153 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3154 track_work.work); 3155 bool tfc_changed; 3156 3157 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3158 return; 3159 3160 mutex_lock(&rtwdev->mutex); 3161 3162 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3163 goto out; 3164 3165 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3166 RTW89_TRACK_WORK_PERIOD); 3167 3168 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3169 if (rtwdev->scanning) 3170 goto out; 3171 3172 rtw89_leave_lps(rtwdev); 3173 3174 if (tfc_changed) { 3175 rtw89_hci_recalc_int_mit(rtwdev); 3176 rtw89_btc_ntfy_wl_sta(rtwdev); 3177 } 3178 rtw89_mac_bf_monitor_track(rtwdev); 3179 rtw89_phy_stat_track(rtwdev); 3180 rtw89_phy_env_monitor_track(rtwdev); 3181 rtw89_phy_dig(rtwdev); 3182 rtw89_core_rfk_track(rtwdev); 3183 rtw89_phy_ra_update(rtwdev); 3184 rtw89_phy_cfo_track(rtwdev); 3185 rtw89_phy_tx_path_div_track(rtwdev); 3186 rtw89_phy_antdiv_track(rtwdev); 3187 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3188 rtw89_phy_edcca_track(rtwdev); 3189 rtw89_tas_track(rtwdev); 3190 rtw89_chanctx_track(rtwdev); 3191 3192 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3193 rtw89_enter_lps_track(rtwdev); 3194 3195 out: 3196 mutex_unlock(&rtwdev->mutex); 3197 } 3198 3199 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3200 { 3201 unsigned long bit; 3202 3203 bit = find_first_zero_bit(addr, size); 3204 if (bit < size) 3205 set_bit(bit, addr); 3206 3207 return bit; 3208 } 3209 3210 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3211 { 3212 clear_bit(bit, addr); 3213 } 3214 3215 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3216 { 3217 bitmap_zero(addr, nbits); 3218 } 3219 3220 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3221 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3222 { 3223 const struct rtw89_chip_info *chip = rtwdev->chip; 3224 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3225 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3226 u8 idx; 3227 int i; 3228 3229 lockdep_assert_held(&rtwdev->mutex); 3230 3231 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3232 if (idx == chip->bacam_num) { 3233 /* allocate a static BA CAM to tid=0/5, so replace the existing 3234 * one if BA CAM is full. Hardware will process the original tid 3235 * automatically. 3236 */ 3237 if (tid != 0 && tid != 5) 3238 return -ENOSPC; 3239 3240 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3241 tmp = &cam_info->ba_cam_entry[i]; 3242 if (tmp->tid == 0 || tmp->tid == 5) 3243 continue; 3244 3245 idx = i; 3246 entry = tmp; 3247 list_del(&entry->list); 3248 break; 3249 } 3250 3251 if (!entry) 3252 return -ENOSPC; 3253 } else { 3254 entry = &cam_info->ba_cam_entry[idx]; 3255 } 3256 3257 entry->tid = tid; 3258 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 3259 3260 *cam_idx = idx; 3261 3262 return 0; 3263 } 3264 3265 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3266 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3267 { 3268 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3269 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3270 u8 idx; 3271 3272 lockdep_assert_held(&rtwdev->mutex); 3273 3274 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 3275 if (entry->tid != tid) 3276 continue; 3277 3278 idx = entry - cam_info->ba_cam_entry; 3279 list_del(&entry->list); 3280 3281 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3282 *cam_idx = idx; 3283 return 0; 3284 } 3285 3286 return -ENOENT; 3287 } 3288 3289 #define RTW89_TYPE_MAPPING(_type) \ 3290 case NL80211_IFTYPE_ ## _type: \ 3291 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3292 break 3293 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 3294 { 3295 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3296 3297 switch (vif->type) { 3298 case NL80211_IFTYPE_STATION: 3299 if (vif->p2p) 3300 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3301 else 3302 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 3303 break; 3304 case NL80211_IFTYPE_AP: 3305 if (vif->p2p) 3306 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3307 else 3308 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 3309 break; 3310 RTW89_TYPE_MAPPING(ADHOC); 3311 RTW89_TYPE_MAPPING(MONITOR); 3312 RTW89_TYPE_MAPPING(MESH_POINT); 3313 default: 3314 WARN_ON(1); 3315 break; 3316 } 3317 3318 switch (vif->type) { 3319 case NL80211_IFTYPE_AP: 3320 case NL80211_IFTYPE_MESH_POINT: 3321 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 3322 rtwvif->self_role = RTW89_SELF_ROLE_AP; 3323 break; 3324 case NL80211_IFTYPE_ADHOC: 3325 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 3326 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3327 break; 3328 case NL80211_IFTYPE_STATION: 3329 if (assoc) { 3330 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 3331 rtwvif->trigger = vif->bss_conf.he_support; 3332 } else { 3333 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 3334 rtwvif->trigger = false; 3335 } 3336 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3337 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3338 break; 3339 case NL80211_IFTYPE_MONITOR: 3340 break; 3341 default: 3342 WARN_ON(1); 3343 break; 3344 } 3345 } 3346 3347 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3348 struct ieee80211_vif *vif, 3349 struct ieee80211_sta *sta) 3350 { 3351 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3352 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3353 struct rtw89_hal *hal = &rtwdev->hal; 3354 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3355 int i; 3356 int ret; 3357 3358 rtwsta->rtwdev = rtwdev; 3359 rtwsta->rtwvif = rtwvif; 3360 rtwsta->prev_rssi = 0; 3361 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 3362 skb_queue_head_init(&rtwsta->roc_queue); 3363 3364 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 3365 rtw89_core_txq_init(rtwdev, sta->txq[i]); 3366 3367 ewma_rssi_init(&rtwsta->avg_rssi); 3368 ewma_snr_init(&rtwsta->avg_snr); 3369 for (i = 0; i < ant_num; i++) { 3370 ewma_rssi_init(&rtwsta->rssi[i]); 3371 ewma_evm_init(&rtwsta->evm_min[i]); 3372 ewma_evm_init(&rtwsta->evm_max[i]); 3373 } 3374 3375 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3376 /* for station mode, assign the mac_id from itself */ 3377 rtwsta->mac_id = rtwvif->mac_id; 3378 /* must do rtw89_reg_6ghz_power_recalc() before rfk channel */ 3379 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, true); 3380 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3381 BTC_ROLE_MSTS_STA_CONN_START); 3382 rtw89_chip_rfk_channel(rtwdev); 3383 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3384 rtwsta->mac_id = rtw89_acquire_mac_id(rtwdev); 3385 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 3386 return -ENOSPC; 3387 3388 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 3389 if (ret) { 3390 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3391 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3392 return ret; 3393 } 3394 3395 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3396 RTW89_ROLE_CREATE); 3397 if (ret) { 3398 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3399 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3400 return ret; 3401 } 3402 3403 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta); 3404 if (ret) 3405 return ret; 3406 3407 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta); 3408 if (ret) 3409 return ret; 3410 3411 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3412 } 3413 3414 return 0; 3415 } 3416 3417 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3418 struct ieee80211_vif *vif, 3419 struct ieee80211_sta *sta) 3420 { 3421 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3422 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3423 3424 if (vif->type == NL80211_IFTYPE_STATION) 3425 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false); 3426 3427 rtwdev->total_sta_assoc--; 3428 if (sta->tdls) 3429 rtwvif->tdls_peer--; 3430 rtwsta->disassoc = true; 3431 3432 return 0; 3433 } 3434 3435 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3436 struct ieee80211_vif *vif, 3437 struct ieee80211_sta *sta) 3438 { 3439 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3440 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3441 int ret; 3442 3443 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 3444 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 3445 rtw89_core_free_sta_pending_ba(rtwdev, sta); 3446 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 3447 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta); 3448 3449 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 3450 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 3451 if (sta->tdls) 3452 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 3453 3454 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3455 rtw89_vif_type_mapping(vif, false); 3456 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 3457 } 3458 3459 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3460 if (ret) { 3461 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3462 return ret; 3463 } 3464 3465 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 3466 if (ret) { 3467 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3468 return ret; 3469 } 3470 3471 /* update cam aid mac_id net_type */ 3472 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3473 if (ret) { 3474 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3475 return ret; 3476 } 3477 3478 return ret; 3479 } 3480 3481 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3482 struct ieee80211_vif *vif, 3483 struct ieee80211_sta *sta) 3484 { 3485 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3486 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3487 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 3488 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3489 rtwvif->sub_entity_idx); 3490 int ret; 3491 3492 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3493 if (sta->tdls) { 3494 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 3495 if (ret) { 3496 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3497 return ret; 3498 } 3499 } 3500 3501 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 3502 if (ret) { 3503 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3504 return ret; 3505 } 3506 } 3507 3508 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3509 if (ret) { 3510 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3511 return ret; 3512 } 3513 3514 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 3515 if (ret) { 3516 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3517 return ret; 3518 } 3519 3520 /* update cam aid mac_id net_type */ 3521 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3522 if (ret) { 3523 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3524 return ret; 3525 } 3526 3527 rtwdev->total_sta_assoc++; 3528 if (sta->tdls) 3529 rtwvif->tdls_peer++; 3530 rtw89_phy_ra_assoc(rtwdev, sta); 3531 rtw89_mac_bf_assoc(rtwdev, vif, sta); 3532 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 3533 3534 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3535 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 3536 3537 if (bss_conf->he_support && 3538 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 3539 rtwsta->er_cap = true; 3540 3541 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3542 BTC_ROLE_MSTS_STA_CONN_END); 3543 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan); 3544 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 3545 3546 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 3547 if (ret) { 3548 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3549 return ret; 3550 } 3551 3552 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 3553 } 3554 3555 return ret; 3556 } 3557 3558 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3559 struct ieee80211_vif *vif, 3560 struct ieee80211_sta *sta) 3561 { 3562 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3563 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3564 int ret; 3565 3566 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3567 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, false); 3568 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3569 BTC_ROLE_MSTS_STA_DIS_CONN); 3570 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3571 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3572 3573 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3574 RTW89_ROLE_REMOVE); 3575 if (ret) { 3576 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3577 return ret; 3578 } 3579 3580 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3581 } 3582 3583 return 0; 3584 } 3585 3586 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3587 struct ieee80211_sta *sta, 3588 struct cfg80211_tid_cfg *tid_conf) 3589 { 3590 struct ieee80211_txq *txq; 3591 struct rtw89_txq *rtwtxq; 3592 u32 mask = tid_conf->mask; 3593 u8 tids = tid_conf->tids; 3594 int tids_nbit = BITS_PER_BYTE; 3595 int i; 3596 3597 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3598 if (!tids) 3599 break; 3600 3601 if (!(tids & BIT(0))) 3602 continue; 3603 3604 txq = sta->txq[i]; 3605 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3606 3607 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 3608 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 3609 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3610 } else { 3611 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 3612 ieee80211_stop_tx_ba_session(sta, txq->tid); 3613 spin_lock_bh(&rtwdev->ba_lock); 3614 list_del_init(&rtwtxq->list); 3615 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3616 spin_unlock_bh(&rtwdev->ba_lock); 3617 } 3618 } 3619 3620 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 3621 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 3622 sta->max_amsdu_subframes = 0; 3623 else 3624 sta->max_amsdu_subframes = 1; 3625 } 3626 } 3627 } 3628 3629 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3630 struct ieee80211_sta *sta, 3631 struct cfg80211_tid_config *tid_config) 3632 { 3633 int i; 3634 3635 for (i = 0; i < tid_config->n_tid_conf; i++) 3636 _rtw89_core_set_tid_config(rtwdev, sta, 3637 &tid_config->tid_conf[i]); 3638 } 3639 3640 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 3641 struct ieee80211_sta_ht_cap *ht_cap) 3642 { 3643 static const __le16 highest[RF_PATH_MAX] = { 3644 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 3645 }; 3646 struct rtw89_hal *hal = &rtwdev->hal; 3647 u8 nss = hal->rx_nss; 3648 int i; 3649 3650 ht_cap->ht_supported = true; 3651 ht_cap->cap = 0; 3652 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 3653 IEEE80211_HT_CAP_MAX_AMSDU | 3654 IEEE80211_HT_CAP_TX_STBC | 3655 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 3656 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 3657 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 3658 IEEE80211_HT_CAP_DSSSCCK40 | 3659 IEEE80211_HT_CAP_SGI_40; 3660 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 3661 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 3662 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 3663 for (i = 0; i < nss; i++) 3664 ht_cap->mcs.rx_mask[i] = 0xFF; 3665 ht_cap->mcs.rx_mask[4] = 0x01; 3666 ht_cap->mcs.rx_highest = highest[nss - 1]; 3667 } 3668 3669 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 3670 struct ieee80211_sta_vht_cap *vht_cap) 3671 { 3672 static const __le16 highest_bw80[RF_PATH_MAX] = { 3673 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 3674 }; 3675 static const __le16 highest_bw160[RF_PATH_MAX] = { 3676 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 3677 }; 3678 const struct rtw89_chip_info *chip = rtwdev->chip; 3679 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 3680 highest_bw160 : highest_bw80; 3681 struct rtw89_hal *hal = &rtwdev->hal; 3682 u16 tx_mcs_map = 0, rx_mcs_map = 0; 3683 u8 sts_cap = 3; 3684 int i; 3685 3686 for (i = 0; i < 8; i++) { 3687 if (i < hal->tx_nss) 3688 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3689 else 3690 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3691 if (i < hal->rx_nss) 3692 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3693 else 3694 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3695 } 3696 3697 vht_cap->vht_supported = true; 3698 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 3699 IEEE80211_VHT_CAP_SHORT_GI_80 | 3700 IEEE80211_VHT_CAP_RXSTBC_1 | 3701 IEEE80211_VHT_CAP_HTC_VHT | 3702 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 3703 0; 3704 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 3705 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 3706 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 3707 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 3708 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 3709 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3710 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 3711 IEEE80211_VHT_CAP_SHORT_GI_160; 3712 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 3713 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 3714 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 3715 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 3716 3717 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 3718 vht_cap->vht_mcs.tx_highest |= 3719 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 3720 } 3721 3722 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 3723 enum nl80211_band band, 3724 enum nl80211_iftype iftype, 3725 struct ieee80211_sband_iftype_data *iftype_data) 3726 { 3727 const struct rtw89_chip_info *chip = rtwdev->chip; 3728 struct rtw89_hal *hal = &rtwdev->hal; 3729 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 3730 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 3731 struct ieee80211_sta_he_cap *he_cap; 3732 int nss = hal->rx_nss; 3733 u8 *mac_cap_info; 3734 u8 *phy_cap_info; 3735 u16 mcs_map = 0; 3736 int i; 3737 3738 for (i = 0; i < 8; i++) { 3739 if (i < nss) 3740 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 3741 else 3742 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 3743 } 3744 3745 he_cap = &iftype_data->he_cap; 3746 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 3747 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 3748 3749 he_cap->has_he = true; 3750 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 3751 if (iftype == NL80211_IFTYPE_STATION) 3752 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 3753 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 3754 IEEE80211_HE_MAC_CAP2_BSR; 3755 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 3756 if (iftype == NL80211_IFTYPE_AP) 3757 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 3758 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 3759 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 3760 if (iftype == NL80211_IFTYPE_STATION) 3761 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 3762 if (band == NL80211_BAND_2GHZ) { 3763 phy_cap_info[0] = 3764 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 3765 } else { 3766 phy_cap_info[0] = 3767 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 3768 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3769 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 3770 } 3771 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 3772 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 3773 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 3774 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 3775 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 3776 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 3777 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 3778 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 3779 if (iftype == NL80211_IFTYPE_STATION) 3780 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 3781 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 3782 if (iftype == NL80211_IFTYPE_AP) 3783 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 3784 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 3785 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 3786 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3787 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 3788 phy_cap_info[5] = no_ng16 ? 0 : 3789 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 3790 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 3791 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 3792 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 3793 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 3794 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 3795 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 3796 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 3797 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 3798 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 3799 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 3800 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 3801 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3802 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 3803 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 3804 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 3805 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 3806 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 3807 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 3808 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 3809 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 3810 if (iftype == NL80211_IFTYPE_STATION) 3811 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 3812 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 3813 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 3814 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 3815 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 3816 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 3817 } 3818 3819 if (band == NL80211_BAND_6GHZ) { 3820 __le16 capa; 3821 3822 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 3823 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 3824 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 3825 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 3826 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 3827 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 3828 iftype_data->he_6ghz_capa.capa = capa; 3829 } 3830 } 3831 3832 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 3833 enum nl80211_band band, 3834 enum nl80211_iftype iftype, 3835 struct ieee80211_sband_iftype_data *iftype_data) 3836 { 3837 const struct rtw89_chip_info *chip = rtwdev->chip; 3838 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 3839 struct ieee80211_eht_mcs_nss_supp *eht_nss; 3840 struct ieee80211_sta_eht_cap *eht_cap; 3841 struct rtw89_hal *hal = &rtwdev->hal; 3842 bool support_320mhz = false; 3843 int sts = 8; 3844 u8 val; 3845 3846 if (chip->chip_gen == RTW89_CHIP_AX) 3847 return; 3848 3849 if (band == NL80211_BAND_6GHZ && 3850 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 3851 support_320mhz = true; 3852 3853 eht_cap = &iftype_data->eht_cap; 3854 eht_cap_elem = &eht_cap->eht_cap_elem; 3855 eht_nss = &eht_cap->eht_mcs_nss_supp; 3856 3857 eht_cap->has_eht = true; 3858 3859 eht_cap_elem->mac_cap_info[0] = 3860 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 3861 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 3862 eht_cap_elem->mac_cap_info[1] = 0; 3863 3864 eht_cap_elem->phy_cap_info[0] = 3865 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 3866 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 3867 if (support_320mhz) 3868 eht_cap_elem->phy_cap_info[0] |= 3869 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 3870 3871 eht_cap_elem->phy_cap_info[0] |= 3872 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 3873 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 3874 eht_cap_elem->phy_cap_info[1] = 3875 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 3876 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 3877 u8_encode_bits(sts - 1, 3878 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 3879 if (support_320mhz) 3880 eht_cap_elem->phy_cap_info[1] |= 3881 u8_encode_bits(sts - 1, 3882 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 3883 3884 eht_cap_elem->phy_cap_info[2] = 0; 3885 3886 eht_cap_elem->phy_cap_info[3] = 3887 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 3888 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 3889 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 3890 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 3891 3892 eht_cap_elem->phy_cap_info[4] = 3893 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 3894 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 3895 3896 eht_cap_elem->phy_cap_info[5] = 3897 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 3898 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 3899 3900 eht_cap_elem->phy_cap_info[6] = 0; 3901 eht_cap_elem->phy_cap_info[7] = 0; 3902 eht_cap_elem->phy_cap_info[8] = 0; 3903 3904 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 3905 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 3906 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 3907 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 3908 eht_nss->bw._80.rx_tx_mcs13_max_nss = val; 3909 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 3910 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 3911 eht_nss->bw._160.rx_tx_mcs13_max_nss = val; 3912 if (support_320mhz) { 3913 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 3914 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 3915 eht_nss->bw._320.rx_tx_mcs13_max_nss = val; 3916 } 3917 } 3918 3919 #define RTW89_SBAND_IFTYPES_NR 2 3920 3921 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 3922 enum nl80211_band band, 3923 struct ieee80211_supported_band *sband) 3924 { 3925 struct ieee80211_sband_iftype_data *iftype_data; 3926 enum nl80211_iftype iftype; 3927 int idx = 0; 3928 3929 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 3930 if (!iftype_data) 3931 return; 3932 3933 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 3934 switch (iftype) { 3935 case NL80211_IFTYPE_STATION: 3936 case NL80211_IFTYPE_AP: 3937 break; 3938 default: 3939 continue; 3940 } 3941 3942 if (idx >= RTW89_SBAND_IFTYPES_NR) { 3943 rtw89_warn(rtwdev, "run out of iftype_data\n"); 3944 break; 3945 } 3946 3947 iftype_data[idx].types_mask = BIT(iftype); 3948 3949 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 3950 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 3951 3952 idx++; 3953 } 3954 3955 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 3956 } 3957 3958 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 3959 { 3960 struct ieee80211_hw *hw = rtwdev->hw; 3961 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 3962 struct ieee80211_supported_band *sband_6ghz = NULL; 3963 u32 size = sizeof(struct ieee80211_supported_band); 3964 u8 support_bands = rtwdev->chip->support_bands; 3965 3966 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 3967 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 3968 if (!sband_2ghz) 3969 goto err; 3970 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 3971 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 3972 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 3973 } 3974 3975 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 3976 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 3977 if (!sband_5ghz) 3978 goto err; 3979 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 3980 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 3981 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 3982 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 3983 } 3984 3985 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 3986 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 3987 if (!sband_6ghz) 3988 goto err; 3989 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 3990 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 3991 } 3992 3993 return 0; 3994 3995 err: 3996 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3997 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3998 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3999 if (sband_2ghz) 4000 kfree((__force void *)sband_2ghz->iftype_data); 4001 if (sband_5ghz) 4002 kfree((__force void *)sband_5ghz->iftype_data); 4003 if (sband_6ghz) 4004 kfree((__force void *)sband_6ghz->iftype_data); 4005 kfree(sband_2ghz); 4006 kfree(sband_5ghz); 4007 kfree(sband_6ghz); 4008 return -ENOMEM; 4009 } 4010 4011 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 4012 { 4013 struct ieee80211_hw *hw = rtwdev->hw; 4014 4015 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 4016 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 4017 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 4018 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 4019 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 4020 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 4021 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 4022 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 4023 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 4024 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4025 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4026 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4027 } 4028 4029 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 4030 { 4031 int i; 4032 4033 for (i = 0; i < RTW89_PHY_MAX; i++) 4034 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4035 for (i = 0; i < RTW89_PHY_MAX; i++) 4036 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4037 } 4038 4039 void rtw89_core_update_beacon_work(struct work_struct *work) 4040 { 4041 struct rtw89_dev *rtwdev; 4042 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 4043 update_beacon_work); 4044 4045 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 4046 return; 4047 4048 rtwdev = rtwvif->rtwdev; 4049 mutex_lock(&rtwdev->mutex); 4050 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif); 4051 mutex_unlock(&rtwdev->mutex); 4052 } 4053 4054 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4055 { 4056 struct completion *cmpl = &wait->completion; 4057 unsigned long timeout; 4058 unsigned int cur; 4059 4060 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4061 if (cur != RTW89_WAIT_COND_IDLE) 4062 return -EBUSY; 4063 4064 timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4065 if (timeout == 0) { 4066 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4067 return -ETIMEDOUT; 4068 } 4069 4070 if (wait->data.err) 4071 return -EFAULT; 4072 4073 return 0; 4074 } 4075 4076 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4077 const struct rtw89_completion_data *data) 4078 { 4079 unsigned int cur; 4080 4081 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4082 if (cur != cond) 4083 return; 4084 4085 wait->data = *data; 4086 complete(&wait->completion); 4087 } 4088 4089 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4090 { 4091 u16 bt_req_len; 4092 4093 switch (event) { 4094 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4095 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4096 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4097 "coex updates BT req len to %d TU\n", bt_req_len); 4098 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4099 break; 4100 default: 4101 if (event < NUM_OF_RTW89_BTC_HMSG) 4102 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4103 "unhandled BTC HMSG event: %d\n", event); 4104 else 4105 rtw89_warn(rtwdev, 4106 "unrecognized BTC HMSG event: %d\n", event); 4107 break; 4108 } 4109 } 4110 4111 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4112 { 4113 const struct dmi_system_id *match; 4114 enum rtw89_quirks quirk; 4115 4116 if (!quirks) 4117 return; 4118 4119 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4120 quirk = (uintptr_t)match->driver_data; 4121 if (quirk >= NUM_OF_RTW89_QUIRKS) 4122 continue; 4123 4124 set_bit(quirk, rtwdev->quirks); 4125 } 4126 } 4127 EXPORT_SYMBOL(rtw89_check_quirks); 4128 4129 int rtw89_core_start(struct rtw89_dev *rtwdev) 4130 { 4131 int ret; 4132 4133 ret = rtw89_mac_init(rtwdev); 4134 if (ret) { 4135 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4136 return ret; 4137 } 4138 4139 rtw89_btc_ntfy_poweron(rtwdev); 4140 4141 /* efuse process */ 4142 4143 /* pre-config BB/RF, BB reset/RFC reset */ 4144 ret = rtw89_chip_reset_bb_rf(rtwdev); 4145 if (ret) 4146 return ret; 4147 4148 rtw89_phy_init_bb_reg(rtwdev); 4149 rtw89_chip_bb_postinit(rtwdev); 4150 rtw89_phy_init_rf_reg(rtwdev, false); 4151 4152 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4153 4154 rtw89_phy_dm_init(rtwdev); 4155 4156 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 4157 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 4158 4159 rtw89_tas_reset(rtwdev); 4160 4161 ret = rtw89_hci_start(rtwdev); 4162 if (ret) { 4163 rtw89_err(rtwdev, "failed to start hci\n"); 4164 return ret; 4165 } 4166 4167 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 4168 RTW89_TRACK_WORK_PERIOD); 4169 4170 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4171 4172 rtw89_chip_rfk_init_late(rtwdev); 4173 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4174 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4175 rtw89_fw_h2c_init_ba_cam(rtwdev); 4176 4177 return 0; 4178 } 4179 4180 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4181 { 4182 struct rtw89_btc *btc = &rtwdev->btc; 4183 4184 /* Prvent to stop twice; enter_ips and ops_stop */ 4185 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4186 return; 4187 4188 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4189 4190 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4191 4192 mutex_unlock(&rtwdev->mutex); 4193 4194 cancel_work_sync(&rtwdev->c2h_work); 4195 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work); 4196 cancel_work_sync(&btc->eapol_notify_work); 4197 cancel_work_sync(&btc->arp_notify_work); 4198 cancel_work_sync(&btc->dhcp_notify_work); 4199 cancel_work_sync(&btc->icmp_notify_work); 4200 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4201 cancel_delayed_work_sync(&rtwdev->track_work); 4202 cancel_delayed_work_sync(&rtwdev->chanctx_work); 4203 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 4204 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 4205 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 4206 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 4207 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4208 cancel_delayed_work_sync(&rtwdev->antdiv_work); 4209 4210 mutex_lock(&rtwdev->mutex); 4211 4212 rtw89_btc_ntfy_poweroff(rtwdev); 4213 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4214 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4215 rtw89_hci_stop(rtwdev); 4216 rtw89_hci_deinit(rtwdev); 4217 rtw89_mac_pwr_off(rtwdev); 4218 rtw89_hci_reset(rtwdev); 4219 } 4220 4221 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 4222 { 4223 const struct rtw89_chip_info *chip = rtwdev->chip; 4224 u8 mac_id_num = chip->support_macid_num; 4225 u8 mac_id; 4226 4227 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 4228 if (mac_id == mac_id_num) 4229 return RTW89_MAX_MAC_ID_NUM; 4230 4231 set_bit(mac_id, rtwdev->mac_id_map); 4232 return mac_id; 4233 } 4234 4235 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 4236 { 4237 clear_bit(mac_id, rtwdev->mac_id_map); 4238 } 4239 4240 int rtw89_core_init(struct rtw89_dev *rtwdev) 4241 { 4242 struct rtw89_btc *btc = &rtwdev->btc; 4243 u8 band; 4244 4245 INIT_LIST_HEAD(&rtwdev->ba_list); 4246 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 4247 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 4248 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 4249 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 4250 if (!(rtwdev->chip->support_bands & BIT(band))) 4251 continue; 4252 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 4253 } 4254 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 4255 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 4256 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 4257 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 4258 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); 4259 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 4260 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 4261 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 4262 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 4263 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 4264 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 4265 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 4266 if (!rtwdev->txq_wq) 4267 return -ENOMEM; 4268 spin_lock_init(&rtwdev->ba_lock); 4269 spin_lock_init(&rtwdev->rpwm_lock); 4270 mutex_init(&rtwdev->mutex); 4271 mutex_init(&rtwdev->rf_mutex); 4272 rtwdev->total_sta_assoc = 0; 4273 4274 rtw89_init_wait(&rtwdev->mcc.wait); 4275 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 4276 4277 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 4278 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 4279 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 4280 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 4281 4282 skb_queue_head_init(&rtwdev->c2h_queue); 4283 rtw89_core_ppdu_sts_init(rtwdev); 4284 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 4285 4286 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 4287 rtwdev->dbcc_en = false; 4288 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 4289 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 4290 4291 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4292 rtwdev->dbcc_en = true; 4293 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 4294 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF; 4295 } 4296 4297 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 4298 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 4299 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 4300 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 4301 4302 init_completion(&rtwdev->fw.req.completion); 4303 init_completion(&rtwdev->rfk_wait.completion); 4304 4305 schedule_work(&rtwdev->load_firmware_work); 4306 4307 rtw89_ser_init(rtwdev); 4308 rtw89_entity_init(rtwdev); 4309 rtw89_tas_init(rtwdev); 4310 4311 return 0; 4312 } 4313 EXPORT_SYMBOL(rtw89_core_init); 4314 4315 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 4316 { 4317 rtw89_ser_deinit(rtwdev); 4318 rtw89_unload_firmware(rtwdev); 4319 rtw89_fw_free_all_early_h2c(rtwdev); 4320 4321 destroy_workqueue(rtwdev->txq_wq); 4322 mutex_destroy(&rtwdev->rf_mutex); 4323 mutex_destroy(&rtwdev->mutex); 4324 } 4325 EXPORT_SYMBOL(rtw89_core_deinit); 4326 4327 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4328 const u8 *mac_addr, bool hw_scan) 4329 { 4330 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4331 rtwvif->sub_entity_idx); 4332 4333 rtwdev->scanning = true; 4334 rtw89_leave_lps(rtwdev); 4335 if (hw_scan) 4336 rtw89_leave_ips_by_hwflags(rtwdev); 4337 4338 ether_addr_copy(rtwvif->mac_addr, mac_addr); 4339 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 4340 rtw89_chip_rfk_scan(rtwdev, true); 4341 rtw89_hci_recalc_int_mit(rtwdev); 4342 rtw89_phy_config_edcca(rtwdev, true); 4343 4344 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 4345 } 4346 4347 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4348 struct ieee80211_vif *vif, bool hw_scan) 4349 { 4350 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4351 4352 if (!rtwvif) 4353 return; 4354 4355 ether_addr_copy(rtwvif->mac_addr, vif->addr); 4356 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4357 4358 rtw89_chip_rfk_scan(rtwdev, false); 4359 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 4360 rtw89_phy_config_edcca(rtwdev, false); 4361 4362 rtwdev->scanning = false; 4363 rtwdev->dig.bypass_dig = true; 4364 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 4365 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 4366 } 4367 4368 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 4369 { 4370 const struct rtw89_chip_info *chip = rtwdev->chip; 4371 int ret; 4372 u8 val; 4373 u8 cv; 4374 4375 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 4376 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 4377 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 4378 cv = CHIP_CAV; 4379 else 4380 cv = CHIP_CBV; 4381 } 4382 4383 rtwdev->hal.cv = cv; 4384 4385 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) { 4386 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 4387 if (ret) 4388 return; 4389 4390 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 4391 } 4392 } 4393 4394 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 4395 { 4396 rtwdev->hal.support_cckpd = 4397 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 4398 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 4399 rtwdev->hal.support_igi = 4400 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 4401 } 4402 4403 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 4404 { 4405 const struct rtw89_chip_info *chip = rtwdev->chip; 4406 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 4407 struct rtw89_efuse *efuse = &rtwdev->efuse; 4408 const struct rtw89_rfe_parms *sel; 4409 u8 rfe_type = efuse->rfe_type; 4410 4411 if (!conf) { 4412 sel = chip->dflt_parms; 4413 goto out; 4414 } 4415 4416 while (conf->rfe_parms) { 4417 if (rfe_type == conf->rfe_type) { 4418 sel = conf->rfe_parms; 4419 goto out; 4420 } 4421 conf++; 4422 } 4423 4424 sel = chip->dflt_parms; 4425 4426 out: 4427 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 4428 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 4429 } 4430 4431 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 4432 { 4433 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4434 int ret; 4435 4436 ret = rtw89_mac_partial_init(rtwdev, false); 4437 if (ret) 4438 return ret; 4439 4440 ret = mac->parse_efuse_map(rtwdev); 4441 if (ret) 4442 return ret; 4443 4444 ret = mac->parse_phycap_map(rtwdev); 4445 if (ret) 4446 return ret; 4447 4448 ret = rtw89_mac_setup_phycap(rtwdev); 4449 if (ret) 4450 return ret; 4451 4452 rtw89_core_setup_phycap(rtwdev); 4453 4454 rtw89_hci_mac_pre_deinit(rtwdev); 4455 4456 rtw89_mac_pwr_off(rtwdev); 4457 4458 return 0; 4459 } 4460 4461 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 4462 { 4463 rtw89_chip_fem_setup(rtwdev); 4464 4465 return 0; 4466 } 4467 4468 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 4469 { 4470 int ret; 4471 4472 rtw89_read_chip_ver(rtwdev); 4473 4474 ret = rtw89_wait_firmware_completion(rtwdev); 4475 if (ret) { 4476 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 4477 return ret; 4478 } 4479 4480 ret = rtw89_fw_recognize(rtwdev); 4481 if (ret) { 4482 rtw89_err(rtwdev, "failed to recognize firmware\n"); 4483 return ret; 4484 } 4485 4486 ret = rtw89_chip_efuse_info_setup(rtwdev); 4487 if (ret) 4488 return ret; 4489 4490 ret = rtw89_fw_recognize_elements(rtwdev); 4491 if (ret) { 4492 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 4493 return ret; 4494 } 4495 4496 ret = rtw89_chip_board_info_setup(rtwdev); 4497 if (ret) 4498 return ret; 4499 4500 rtw89_core_setup_rfe_parms(rtwdev); 4501 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 4502 4503 return 0; 4504 } 4505 EXPORT_SYMBOL(rtw89_chip_info_setup); 4506 4507 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 4508 { 4509 const struct rtw89_chip_info *chip = rtwdev->chip; 4510 struct ieee80211_hw *hw = rtwdev->hw; 4511 struct rtw89_efuse *efuse = &rtwdev->efuse; 4512 struct rtw89_hal *hal = &rtwdev->hal; 4513 int ret; 4514 int tx_headroom = IEEE80211_HT_CTL_LEN; 4515 4516 hw->vif_data_size = sizeof(struct rtw89_vif); 4517 hw->sta_data_size = sizeof(struct rtw89_sta); 4518 hw->txq_data_size = sizeof(struct rtw89_txq); 4519 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 4520 4521 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 4522 4523 hw->extra_tx_headroom = tx_headroom; 4524 hw->queues = IEEE80211_NUM_ACS; 4525 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 4526 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 4527 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 4528 4529 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 4530 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 4531 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 4532 4533 ieee80211_hw_set(hw, SIGNAL_DBM); 4534 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 4535 ieee80211_hw_set(hw, MFP_CAPABLE); 4536 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 4537 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 4538 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 4539 ieee80211_hw_set(hw, TX_AMSDU); 4540 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 4541 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 4542 ieee80211_hw_set(hw, SUPPORTS_PS); 4543 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 4544 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 4545 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 4546 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 4547 4548 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4549 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 4550 4551 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 4552 ieee80211_hw_set(hw, CONNECTION_MONITOR); 4553 4554 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 4555 BIT(NL80211_IFTYPE_AP) | 4556 BIT(NL80211_IFTYPE_P2P_CLIENT) | 4557 BIT(NL80211_IFTYPE_P2P_GO); 4558 4559 if (hal->ant_diversity) { 4560 hw->wiphy->available_antennas_tx = 0x3; 4561 hw->wiphy->available_antennas_rx = 0x3; 4562 } else { 4563 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 4564 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 4565 } 4566 4567 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 4568 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 4569 WIPHY_FLAG_AP_UAPSD | 4570 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 4571 4572 if (!chip->support_rnr) 4573 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 4574 4575 if (chip->chip_gen == RTW89_CHIP_BE) 4576 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 4577 4578 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 4579 4580 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 4581 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 4582 4583 #ifdef CONFIG_PM 4584 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 4585 #endif 4586 4587 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4588 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4589 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4590 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4591 hw->wiphy->max_remain_on_channel_duration = 1000; 4592 4593 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 4594 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 4595 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 4596 4597 ret = rtw89_core_set_supported_band(rtwdev); 4598 if (ret) { 4599 rtw89_err(rtwdev, "failed to set supported band\n"); 4600 return ret; 4601 } 4602 4603 ret = rtw89_regd_setup(rtwdev); 4604 if (ret) { 4605 rtw89_err(rtwdev, "failed to set up regd\n"); 4606 goto err_free_supported_band; 4607 } 4608 4609 hw->wiphy->sar_capa = &rtw89_sar_capa; 4610 4611 ret = ieee80211_register_hw(hw); 4612 if (ret) { 4613 rtw89_err(rtwdev, "failed to register hw\n"); 4614 goto err_free_supported_band; 4615 } 4616 4617 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 4618 if (ret) { 4619 rtw89_err(rtwdev, "failed to init regd\n"); 4620 goto err_unregister_hw; 4621 } 4622 4623 return 0; 4624 4625 err_unregister_hw: 4626 ieee80211_unregister_hw(hw); 4627 err_free_supported_band: 4628 rtw89_core_clr_supported_band(rtwdev); 4629 4630 return ret; 4631 } 4632 4633 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 4634 { 4635 struct ieee80211_hw *hw = rtwdev->hw; 4636 4637 ieee80211_unregister_hw(hw); 4638 rtw89_core_clr_supported_band(rtwdev); 4639 } 4640 4641 int rtw89_core_register(struct rtw89_dev *rtwdev) 4642 { 4643 int ret; 4644 4645 ret = rtw89_core_register_hw(rtwdev); 4646 if (ret) { 4647 rtw89_err(rtwdev, "failed to register core hw\n"); 4648 return ret; 4649 } 4650 4651 rtw89_debugfs_init(rtwdev); 4652 4653 return 0; 4654 } 4655 EXPORT_SYMBOL(rtw89_core_register); 4656 4657 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 4658 { 4659 rtw89_core_unregister_hw(rtwdev); 4660 } 4661 EXPORT_SYMBOL(rtw89_core_unregister); 4662 4663 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4664 u32 bus_data_size, 4665 const struct rtw89_chip_info *chip) 4666 { 4667 struct rtw89_fw_info early_fw = {}; 4668 const struct firmware *firmware; 4669 struct ieee80211_hw *hw; 4670 struct rtw89_dev *rtwdev; 4671 struct ieee80211_ops *ops; 4672 u32 driver_data_size; 4673 int fw_format = -1; 4674 bool no_chanctx; 4675 4676 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 4677 4678 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 4679 if (!ops) 4680 goto err; 4681 4682 no_chanctx = chip->support_chanctx_num == 0 || 4683 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 4684 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 4685 4686 if (no_chanctx) { 4687 ops->add_chanctx = ieee80211_emulate_add_chanctx; 4688 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 4689 ops->change_chanctx = ieee80211_emulate_change_chanctx; 4690 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 4691 ops->assign_vif_chanctx = NULL; 4692 ops->unassign_vif_chanctx = NULL; 4693 ops->remain_on_channel = NULL; 4694 ops->cancel_remain_on_channel = NULL; 4695 } 4696 4697 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 4698 hw = ieee80211_alloc_hw(driver_data_size, ops); 4699 if (!hw) 4700 goto err; 4701 4702 hw->wiphy->iface_combinations = rtw89_iface_combs; 4703 4704 if (no_chanctx || chip->support_chanctx_num == 1) 4705 hw->wiphy->n_iface_combinations = 1; 4706 else 4707 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 4708 4709 rtwdev = hw->priv; 4710 rtwdev->hw = hw; 4711 rtwdev->dev = device; 4712 rtwdev->ops = ops; 4713 rtwdev->chip = chip; 4714 rtwdev->fw.req.firmware = firmware; 4715 rtwdev->fw.fw_format = fw_format; 4716 4717 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 4718 no_chanctx ? "without" : "with"); 4719 4720 return rtwdev; 4721 4722 err: 4723 kfree(ops); 4724 release_firmware(firmware); 4725 return NULL; 4726 } 4727 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 4728 4729 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 4730 { 4731 kfree(rtwdev->ops); 4732 kfree(rtwdev->rfe_data); 4733 release_firmware(rtwdev->fw.req.firmware); 4734 ieee80211_free_hw(rtwdev->hw); 4735 } 4736 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 4737 4738 MODULE_AUTHOR("Realtek Corporation"); 4739 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 4740 MODULE_LICENSE("Dual BSD/GPL"); 4741