1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 22 static bool rtw89_disable_ps_mode; 23 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 24 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 25 26 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 27 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 28 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 29 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 30 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 32 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 34 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 36 37 static struct ieee80211_channel rtw89_channels_2ghz[] = { 38 RTW89_DEF_CHAN_2G(2412, 1), 39 RTW89_DEF_CHAN_2G(2417, 2), 40 RTW89_DEF_CHAN_2G(2422, 3), 41 RTW89_DEF_CHAN_2G(2427, 4), 42 RTW89_DEF_CHAN_2G(2432, 5), 43 RTW89_DEF_CHAN_2G(2437, 6), 44 RTW89_DEF_CHAN_2G(2442, 7), 45 RTW89_DEF_CHAN_2G(2447, 8), 46 RTW89_DEF_CHAN_2G(2452, 9), 47 RTW89_DEF_CHAN_2G(2457, 10), 48 RTW89_DEF_CHAN_2G(2462, 11), 49 RTW89_DEF_CHAN_2G(2467, 12), 50 RTW89_DEF_CHAN_2G(2472, 13), 51 RTW89_DEF_CHAN_2G(2484, 14), 52 }; 53 54 static struct ieee80211_channel rtw89_channels_5ghz[] = { 55 RTW89_DEF_CHAN_5G(5180, 36), 56 RTW89_DEF_CHAN_5G(5200, 40), 57 RTW89_DEF_CHAN_5G(5220, 44), 58 RTW89_DEF_CHAN_5G(5240, 48), 59 RTW89_DEF_CHAN_5G(5260, 52), 60 RTW89_DEF_CHAN_5G(5280, 56), 61 RTW89_DEF_CHAN_5G(5300, 60), 62 RTW89_DEF_CHAN_5G(5320, 64), 63 RTW89_DEF_CHAN_5G(5500, 100), 64 RTW89_DEF_CHAN_5G(5520, 104), 65 RTW89_DEF_CHAN_5G(5540, 108), 66 RTW89_DEF_CHAN_5G(5560, 112), 67 RTW89_DEF_CHAN_5G(5580, 116), 68 RTW89_DEF_CHAN_5G(5600, 120), 69 RTW89_DEF_CHAN_5G(5620, 124), 70 RTW89_DEF_CHAN_5G(5640, 128), 71 RTW89_DEF_CHAN_5G(5660, 132), 72 RTW89_DEF_CHAN_5G(5680, 136), 73 RTW89_DEF_CHAN_5G(5700, 140), 74 RTW89_DEF_CHAN_5G(5720, 144), 75 RTW89_DEF_CHAN_5G(5745, 149), 76 RTW89_DEF_CHAN_5G(5765, 153), 77 RTW89_DEF_CHAN_5G(5785, 157), 78 RTW89_DEF_CHAN_5G(5805, 161), 79 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 80 }; 81 82 static struct ieee80211_channel rtw89_channels_6ghz[] = { 83 RTW89_DEF_CHAN_6G(5955, 1), 84 RTW89_DEF_CHAN_6G(5975, 5), 85 RTW89_DEF_CHAN_6G(5995, 9), 86 RTW89_DEF_CHAN_6G(6015, 13), 87 RTW89_DEF_CHAN_6G(6035, 17), 88 RTW89_DEF_CHAN_6G(6055, 21), 89 RTW89_DEF_CHAN_6G(6075, 25), 90 RTW89_DEF_CHAN_6G(6095, 29), 91 RTW89_DEF_CHAN_6G(6115, 33), 92 RTW89_DEF_CHAN_6G(6135, 37), 93 RTW89_DEF_CHAN_6G(6155, 41), 94 RTW89_DEF_CHAN_6G(6175, 45), 95 RTW89_DEF_CHAN_6G(6195, 49), 96 RTW89_DEF_CHAN_6G(6215, 53), 97 RTW89_DEF_CHAN_6G(6235, 57), 98 RTW89_DEF_CHAN_6G(6255, 61), 99 RTW89_DEF_CHAN_6G(6275, 65), 100 RTW89_DEF_CHAN_6G(6295, 69), 101 RTW89_DEF_CHAN_6G(6315, 73), 102 RTW89_DEF_CHAN_6G(6335, 77), 103 RTW89_DEF_CHAN_6G(6355, 81), 104 RTW89_DEF_CHAN_6G(6375, 85), 105 RTW89_DEF_CHAN_6G(6395, 89), 106 RTW89_DEF_CHAN_6G(6415, 93), 107 RTW89_DEF_CHAN_6G(6435, 97), 108 RTW89_DEF_CHAN_6G(6455, 101), 109 RTW89_DEF_CHAN_6G(6475, 105), 110 RTW89_DEF_CHAN_6G(6495, 109), 111 RTW89_DEF_CHAN_6G(6515, 113), 112 RTW89_DEF_CHAN_6G(6535, 117), 113 RTW89_DEF_CHAN_6G(6555, 121), 114 RTW89_DEF_CHAN_6G(6575, 125), 115 RTW89_DEF_CHAN_6G(6595, 129), 116 RTW89_DEF_CHAN_6G(6615, 133), 117 RTW89_DEF_CHAN_6G(6635, 137), 118 RTW89_DEF_CHAN_6G(6655, 141), 119 RTW89_DEF_CHAN_6G(6675, 145), 120 RTW89_DEF_CHAN_6G(6695, 149), 121 RTW89_DEF_CHAN_6G(6715, 153), 122 RTW89_DEF_CHAN_6G(6735, 157), 123 RTW89_DEF_CHAN_6G(6755, 161), 124 RTW89_DEF_CHAN_6G(6775, 165), 125 RTW89_DEF_CHAN_6G(6795, 169), 126 RTW89_DEF_CHAN_6G(6815, 173), 127 RTW89_DEF_CHAN_6G(6835, 177), 128 RTW89_DEF_CHAN_6G(6855, 181), 129 RTW89_DEF_CHAN_6G(6875, 185), 130 RTW89_DEF_CHAN_6G(6895, 189), 131 RTW89_DEF_CHAN_6G(6915, 193), 132 RTW89_DEF_CHAN_6G(6935, 197), 133 RTW89_DEF_CHAN_6G(6955, 201), 134 RTW89_DEF_CHAN_6G(6975, 205), 135 RTW89_DEF_CHAN_6G(6995, 209), 136 RTW89_DEF_CHAN_6G(7015, 213), 137 RTW89_DEF_CHAN_6G(7035, 217), 138 RTW89_DEF_CHAN_6G(7055, 221), 139 RTW89_DEF_CHAN_6G(7075, 225), 140 RTW89_DEF_CHAN_6G(7095, 229), 141 RTW89_DEF_CHAN_6G(7115, 233), 142 }; 143 144 static struct ieee80211_rate rtw89_bitrates[] = { 145 { .bitrate = 10, .hw_value = 0x00, }, 146 { .bitrate = 20, .hw_value = 0x01, }, 147 { .bitrate = 55, .hw_value = 0x02, }, 148 { .bitrate = 110, .hw_value = 0x03, }, 149 { .bitrate = 60, .hw_value = 0x04, }, 150 { .bitrate = 90, .hw_value = 0x05, }, 151 { .bitrate = 120, .hw_value = 0x06, }, 152 { .bitrate = 180, .hw_value = 0x07, }, 153 { .bitrate = 240, .hw_value = 0x08, }, 154 { .bitrate = 360, .hw_value = 0x09, }, 155 { .bitrate = 480, .hw_value = 0x0a, }, 156 { .bitrate = 540, .hw_value = 0x0b, }, 157 }; 158 159 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 160 { 161 struct ieee80211_rate rate; 162 163 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 164 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 165 return false; 166 } 167 168 rate = rtw89_bitrates[rpt_rate]; 169 *bitrate = rate.bitrate; 170 171 return true; 172 } 173 174 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 175 .band = NL80211_BAND_2GHZ, 176 .channels = rtw89_channels_2ghz, 177 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 178 .bitrates = rtw89_bitrates, 179 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 180 .ht_cap = {0}, 181 .vht_cap = {0}, 182 }; 183 184 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 185 .band = NL80211_BAND_5GHZ, 186 .channels = rtw89_channels_5ghz, 187 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 188 189 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 190 .bitrates = rtw89_bitrates + 4, 191 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 192 .ht_cap = {0}, 193 .vht_cap = {0}, 194 }; 195 196 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 197 .band = NL80211_BAND_6GHZ, 198 .channels = rtw89_channels_6ghz, 199 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 200 201 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 202 .bitrates = rtw89_bitrates + 4, 203 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 204 }; 205 206 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 207 struct rtw89_traffic_stats *stats, 208 struct sk_buff *skb, bool tx) 209 { 210 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 211 212 if (!ieee80211_is_data(hdr->frame_control)) 213 return; 214 215 if (is_broadcast_ether_addr(hdr->addr1) || 216 is_multicast_ether_addr(hdr->addr1)) 217 return; 218 219 if (tx) { 220 stats->tx_cnt++; 221 stats->tx_unicast += skb->len; 222 } else { 223 stats->rx_cnt++; 224 stats->rx_unicast += skb->len; 225 } 226 } 227 228 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 229 { 230 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 231 NL80211_CHAN_NO_HT); 232 } 233 234 static void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 235 struct rtw89_chan *chan) 236 { 237 struct ieee80211_channel *channel = chandef->chan; 238 enum nl80211_chan_width width = chandef->width; 239 u32 primary_freq, center_freq; 240 u8 center_chan; 241 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 242 u32 offset; 243 u8 band; 244 245 center_chan = channel->hw_value; 246 primary_freq = channel->center_freq; 247 center_freq = chandef->center_freq1; 248 249 switch (width) { 250 case NL80211_CHAN_WIDTH_20_NOHT: 251 case NL80211_CHAN_WIDTH_20: 252 bandwidth = RTW89_CHANNEL_WIDTH_20; 253 break; 254 case NL80211_CHAN_WIDTH_40: 255 bandwidth = RTW89_CHANNEL_WIDTH_40; 256 if (primary_freq > center_freq) { 257 center_chan -= 2; 258 } else { 259 center_chan += 2; 260 } 261 break; 262 case NL80211_CHAN_WIDTH_80: 263 case NL80211_CHAN_WIDTH_160: 264 bandwidth = nl_to_rtw89_bandwidth(width); 265 if (primary_freq > center_freq) { 266 offset = (primary_freq - center_freq - 10) / 20; 267 center_chan -= 2 + offset * 4; 268 } else { 269 offset = (center_freq - primary_freq - 10) / 20; 270 center_chan += 2 + offset * 4; 271 } 272 break; 273 default: 274 center_chan = 0; 275 break; 276 } 277 278 switch (channel->band) { 279 default: 280 case NL80211_BAND_2GHZ: 281 band = RTW89_BAND_2G; 282 break; 283 case NL80211_BAND_5GHZ: 284 band = RTW89_BAND_5G; 285 break; 286 case NL80211_BAND_6GHZ: 287 band = RTW89_BAND_6G; 288 break; 289 } 290 291 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 292 } 293 294 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 295 { 296 const struct rtw89_chip_info *chip = rtwdev->chip; 297 const struct rtw89_chan *chan; 298 enum rtw89_sub_entity_idx sub_entity_idx; 299 enum rtw89_phy_idx phy_idx; 300 enum rtw89_entity_mode mode; 301 bool entity_active; 302 303 entity_active = rtw89_get_entity_state(rtwdev); 304 if (!entity_active) 305 return; 306 307 mode = rtw89_get_entity_mode(rtwdev); 308 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 309 return; 310 311 sub_entity_idx = RTW89_SUB_ENTITY_0; 312 phy_idx = RTW89_PHY_0; 313 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 314 if (chip->ops->set_txpwr) 315 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 316 } 317 318 void rtw89_set_channel(struct rtw89_dev *rtwdev) 319 { 320 const struct rtw89_chip_info *chip = rtwdev->chip; 321 const struct cfg80211_chan_def *chandef; 322 enum rtw89_sub_entity_idx sub_entity_idx; 323 enum rtw89_mac_idx mac_idx; 324 enum rtw89_phy_idx phy_idx; 325 struct rtw89_chan chan; 326 struct rtw89_channel_help_params bak; 327 enum rtw89_entity_mode mode; 328 bool band_changed; 329 bool entity_active; 330 331 entity_active = rtw89_get_entity_state(rtwdev); 332 333 mode = rtw89_entity_recalc(rtwdev); 334 if (WARN(mode != RTW89_ENTITY_MODE_SCC, "Invalid ent mode: %d\n", mode)) 335 return; 336 337 sub_entity_idx = RTW89_SUB_ENTITY_0; 338 mac_idx = RTW89_MAC_0; 339 phy_idx = RTW89_PHY_0; 340 chandef = rtw89_chandef_get(rtwdev, sub_entity_idx); 341 rtw89_get_channel_params(chandef, &chan); 342 if (WARN(chan.channel == 0, "Invalid channel\n")) 343 return; 344 345 band_changed = rtw89_assign_entity_chan(rtwdev, sub_entity_idx, &chan); 346 347 rtw89_chip_set_channel_prepare(rtwdev, &bak, &chan, mac_idx, phy_idx); 348 349 chip->ops->set_channel(rtwdev, &chan, mac_idx, phy_idx); 350 351 rtw89_core_set_chip_txpwr(rtwdev); 352 353 rtw89_chip_set_channel_done(rtwdev, &bak, &chan, mac_idx, phy_idx); 354 355 if (!entity_active || band_changed) { 356 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan.band_type); 357 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 358 } 359 360 rtw89_set_entity_state(rtwdev, true); 361 } 362 363 static enum rtw89_core_tx_type 364 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 365 struct sk_buff *skb) 366 { 367 struct ieee80211_hdr *hdr = (void *)skb->data; 368 __le16 fc = hdr->frame_control; 369 370 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 371 return RTW89_CORE_TX_TYPE_MGMT; 372 373 return RTW89_CORE_TX_TYPE_DATA; 374 } 375 376 static void 377 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 378 struct rtw89_core_tx_request *tx_req, 379 enum btc_pkt_type pkt_type) 380 { 381 struct ieee80211_sta *sta = tx_req->sta; 382 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 383 struct sk_buff *skb = tx_req->skb; 384 struct rtw89_sta *rtwsta; 385 u8 ampdu_num; 386 u8 tid; 387 388 if (pkt_type == PACKET_EAPOL) { 389 desc_info->bk = true; 390 return; 391 } 392 393 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 394 return; 395 396 if (!sta) { 397 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 398 return; 399 } 400 401 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 402 rtwsta = (struct rtw89_sta *)sta->drv_priv; 403 404 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 405 rtwsta->ampdu_params[tid].agg_num : 406 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 407 408 desc_info->agg_en = true; 409 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 410 desc_info->ampdu_num = ampdu_num; 411 } 412 413 static void 414 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 415 struct rtw89_core_tx_request *tx_req) 416 { 417 const struct rtw89_chip_info *chip = rtwdev->chip; 418 struct ieee80211_vif *vif = tx_req->vif; 419 struct ieee80211_sta *sta = tx_req->sta; 420 struct ieee80211_tx_info *info; 421 struct ieee80211_key_conf *key; 422 struct rtw89_vif *rtwvif; 423 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 424 struct rtw89_addr_cam_entry *addr_cam; 425 struct rtw89_sec_cam_entry *sec_cam; 426 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 427 struct sk_buff *skb = tx_req->skb; 428 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 429 u64 pn64; 430 431 if (!vif) { 432 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 433 return; 434 } 435 436 rtwvif = (struct rtw89_vif *)vif->drv_priv; 437 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 438 439 info = IEEE80211_SKB_CB(skb); 440 key = info->control.hw_key; 441 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 442 if (!sec_cam) { 443 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 444 return; 445 } 446 447 switch (key->cipher) { 448 case WLAN_CIPHER_SUITE_WEP40: 449 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 450 break; 451 case WLAN_CIPHER_SUITE_WEP104: 452 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 453 break; 454 case WLAN_CIPHER_SUITE_TKIP: 455 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 456 break; 457 case WLAN_CIPHER_SUITE_CCMP: 458 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 459 break; 460 case WLAN_CIPHER_SUITE_CCMP_256: 461 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 462 break; 463 case WLAN_CIPHER_SUITE_GCMP: 464 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 465 break; 466 case WLAN_CIPHER_SUITE_GCMP_256: 467 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 468 break; 469 default: 470 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 471 return; 472 } 473 474 desc_info->sec_en = true; 475 desc_info->sec_keyid = key->keyidx; 476 desc_info->sec_type = sec_type; 477 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 478 479 if (!chip->hw_sec_hdr) 480 return; 481 482 pn64 = atomic64_inc_return(&key->tx_pn); 483 desc_info->sec_seq[0] = pn64; 484 desc_info->sec_seq[1] = pn64 >> 8; 485 desc_info->sec_seq[2] = pn64 >> 16; 486 desc_info->sec_seq[3] = pn64 >> 24; 487 desc_info->sec_seq[4] = pn64 >> 32; 488 desc_info->sec_seq[5] = pn64 >> 40; 489 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 490 } 491 492 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 493 struct rtw89_core_tx_request *tx_req) 494 { 495 struct sk_buff *skb = tx_req->skb; 496 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 497 struct ieee80211_vif *vif = tx_info->control.vif; 498 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 499 u16 lowest_rate; 500 501 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 502 (vif && vif->p2p)) 503 lowest_rate = RTW89_HW_RATE_OFDM6; 504 else if (chan->band_type == RTW89_BAND_2G) 505 lowest_rate = RTW89_HW_RATE_CCK1; 506 else 507 lowest_rate = RTW89_HW_RATE_OFDM6; 508 509 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 510 return lowest_rate; 511 512 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 513 } 514 515 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 516 struct rtw89_core_tx_request *tx_req) 517 { 518 struct ieee80211_vif *vif = tx_req->vif; 519 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 520 struct ieee80211_sta *sta = tx_req->sta; 521 struct rtw89_sta *rtwsta; 522 523 if (!sta) 524 return rtwvif->mac_id; 525 526 rtwsta = (struct rtw89_sta *)sta->drv_priv; 527 return rtwsta->mac_id; 528 } 529 530 static void 531 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 532 struct rtw89_core_tx_request *tx_req) 533 { 534 struct ieee80211_vif *vif = tx_req->vif; 535 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 536 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 537 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 538 u8 qsel, ch_dma; 539 540 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 541 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 542 543 desc_info->qsel = qsel; 544 desc_info->ch_dma = ch_dma; 545 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 546 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 547 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 548 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 549 550 /* fixed data rate for mgmt frames */ 551 desc_info->en_wd_info = true; 552 desc_info->use_rate = true; 553 desc_info->dis_data_fb = true; 554 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req); 555 556 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 557 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 558 desc_info->data_rate, chan->channel, chan->band_type, 559 chan->band_width); 560 } 561 562 static void 563 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 564 struct rtw89_core_tx_request *tx_req) 565 { 566 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 567 568 desc_info->is_bmc = false; 569 desc_info->wd_page = false; 570 desc_info->ch_dma = RTW89_DMA_H2C; 571 } 572 573 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc) 574 { 575 static const u8 rtw89_bandwidth_to_om[] = { 576 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 577 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 578 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 579 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 580 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 581 }; 582 const struct rtw89_chip_info *chip = rtwdev->chip; 583 struct rtw89_hal *hal = &rtwdev->hal; 584 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 585 u8 om_bandwidth; 586 587 if (!chip->dis_2g_40m_ul_ofdma || 588 chan->band_type != RTW89_BAND_2G || 589 chan->band_width != RTW89_CHANNEL_WIDTH_40) 590 return; 591 592 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 593 rtw89_bandwidth_to_om[chan->band_width] : 0; 594 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 595 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 596 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 597 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 598 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 599 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 600 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 601 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 602 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 603 } 604 605 static bool 606 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 607 struct rtw89_core_tx_request *tx_req, 608 enum btc_pkt_type pkt_type) 609 { 610 struct ieee80211_sta *sta = tx_req->sta; 611 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 612 struct sk_buff *skb = tx_req->skb; 613 struct ieee80211_hdr *hdr = (void *)skb->data; 614 __le16 fc = hdr->frame_control; 615 616 /* AP IOT issue with EAPoL, ARP and DHCP */ 617 if (pkt_type < PACKET_MAX) 618 return false; 619 620 if (!sta || !sta->deflink.he_cap.has_he) 621 return false; 622 623 if (!ieee80211_is_data_qos(fc)) 624 return false; 625 626 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 627 return false; 628 629 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 630 return false; 631 632 return true; 633 } 634 635 static void 636 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 637 struct rtw89_core_tx_request *tx_req) 638 { 639 struct ieee80211_sta *sta = tx_req->sta; 640 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 641 struct sk_buff *skb = tx_req->skb; 642 struct ieee80211_hdr *hdr = (void *)skb->data; 643 __le16 fc = hdr->frame_control; 644 void *data; 645 __le32 *htc; 646 u8 *qc; 647 int hdr_len; 648 649 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 650 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 651 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 652 653 hdr = data; 654 htc = data + hdr_len; 655 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 656 *htc = rtwsta->htc_template ? rtwsta->htc_template : 657 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 658 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 659 660 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 661 qc[0] |= IEEE80211_QOS_CTL_EOSP; 662 } 663 664 static void 665 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 666 struct rtw89_core_tx_request *tx_req, 667 enum btc_pkt_type pkt_type) 668 { 669 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 670 struct ieee80211_vif *vif = tx_req->vif; 671 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 672 673 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 674 goto desc_bk; 675 676 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 677 678 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 679 desc_info->a_ctrl_bsr = true; 680 681 desc_bk: 682 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 683 return; 684 685 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 686 desc_info->bk = true; 687 } 688 689 static void 690 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 691 struct rtw89_core_tx_request *tx_req) 692 { 693 struct ieee80211_vif *vif = tx_req->vif; 694 struct ieee80211_sta *sta = tx_req->sta; 695 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 696 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 697 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 698 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 699 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 700 struct sk_buff *skb = tx_req->skb; 701 u8 tid, tid_indicate; 702 u8 qsel, ch_dma; 703 704 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 705 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 706 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 707 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 708 709 desc_info->ch_dma = ch_dma; 710 desc_info->tid_indicate = tid_indicate; 711 desc_info->qsel = qsel; 712 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 713 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 714 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 715 716 /* enable wd_info for AMPDU */ 717 desc_info->en_wd_info = true; 718 719 if (IEEE80211_SKB_CB(skb)->control.hw_key) 720 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 721 722 if (vif->p2p) 723 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6; 724 else if (rate_pattern->enable) 725 desc_info->data_retry_lowest_rate = rate_pattern->rate; 726 else if (chan->band_type == RTW89_BAND_2G) 727 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_CCK1; 728 else 729 desc_info->data_retry_lowest_rate = RTW89_HW_RATE_OFDM6; 730 } 731 732 static enum btc_pkt_type 733 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 734 struct rtw89_core_tx_request *tx_req) 735 { 736 struct sk_buff *skb = tx_req->skb; 737 struct udphdr *udphdr; 738 739 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 740 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 741 return PACKET_EAPOL; 742 } 743 744 if (skb->protocol == htons(ETH_P_ARP)) { 745 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 746 return PACKET_ARP; 747 } 748 749 if (skb->protocol == htons(ETH_P_IP) && 750 ip_hdr(skb)->protocol == IPPROTO_UDP) { 751 udphdr = udp_hdr(skb); 752 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 753 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 754 skb->len > 282) { 755 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 756 return PACKET_DHCP; 757 } 758 } 759 760 if (skb->protocol == htons(ETH_P_IP) && 761 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 762 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 763 return PACKET_ICMP; 764 } 765 766 return PACKET_MAX; 767 } 768 769 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 770 struct rtw89_tx_desc_info *desc_info, 771 struct sk_buff *skb) 772 { 773 struct ieee80211_hdr *hdr = (void *)skb->data; 774 __le16 fc = hdr->frame_control; 775 776 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 777 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 778 } 779 780 static void 781 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 782 struct rtw89_core_tx_request *tx_req) 783 { 784 const struct rtw89_chip_info *chip = rtwdev->chip; 785 786 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 787 return; 788 789 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 790 return; 791 792 if (chip->chip_id != RTL8852C && 793 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 794 return; 795 796 rtw89_mac_notify_wake(rtwdev); 797 } 798 799 static void 800 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 801 struct rtw89_core_tx_request *tx_req) 802 { 803 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 804 struct sk_buff *skb = tx_req->skb; 805 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 806 struct ieee80211_hdr *hdr = (void *)skb->data; 807 enum rtw89_core_tx_type tx_type; 808 enum btc_pkt_type pkt_type; 809 bool is_bmc; 810 u16 seq; 811 812 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 813 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 814 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 815 tx_req->tx_type = tx_type; 816 } 817 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 818 is_multicast_ether_addr(hdr->addr1)); 819 820 desc_info->seq = seq; 821 desc_info->pkt_size = skb->len; 822 desc_info->is_bmc = is_bmc; 823 desc_info->wd_page = true; 824 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 825 826 switch (tx_req->tx_type) { 827 case RTW89_CORE_TX_TYPE_MGMT: 828 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 829 break; 830 case RTW89_CORE_TX_TYPE_DATA: 831 rtw89_core_tx_update_data_info(rtwdev, tx_req); 832 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 833 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 834 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 835 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 836 break; 837 case RTW89_CORE_TX_TYPE_FWCMD: 838 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 839 break; 840 } 841 } 842 843 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 844 { 845 u8 ch_dma; 846 847 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 848 849 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 850 } 851 852 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 853 struct sk_buff *skb, bool fwdl) 854 { 855 struct rtw89_core_tx_request tx_req = {0}; 856 u32 cnt; 857 int ret; 858 859 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 860 rtw89_debug(rtwdev, RTW89_DBG_FW, 861 "ignore h2c due to power is off with firmware state=%d\n", 862 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 863 dev_kfree_skb(skb); 864 return 0; 865 } 866 867 tx_req.skb = skb; 868 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 869 if (fwdl) 870 tx_req.desc_info.fw_dl = true; 871 872 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 873 874 if (!fwdl) 875 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 876 877 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 878 if (cnt == 0) { 879 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 880 return -ENOSPC; 881 } 882 883 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 884 if (ret) { 885 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 886 return ret; 887 } 888 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 889 890 return 0; 891 } 892 893 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 894 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 895 { 896 struct rtw89_core_tx_request tx_req = {0}; 897 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 898 int ret; 899 900 tx_req.skb = skb; 901 tx_req.sta = sta; 902 tx_req.vif = vif; 903 904 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 905 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 906 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 907 rtw89_core_tx_wake(rtwdev, &tx_req); 908 909 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 910 if (ret) { 911 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 912 return ret; 913 } 914 915 if (qsel) 916 *qsel = tx_req.desc_info.qsel; 917 918 return 0; 919 } 920 921 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 922 { 923 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 924 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 925 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 926 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 927 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 928 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 929 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 930 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 931 932 return cpu_to_le32(dword); 933 } 934 935 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 936 { 937 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 938 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 939 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 940 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 941 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 942 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 943 944 return cpu_to_le32(dword); 945 } 946 947 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 948 { 949 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 950 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 951 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 952 953 return cpu_to_le32(dword); 954 } 955 956 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 957 { 958 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 959 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 960 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 961 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 962 963 return cpu_to_le32(dword); 964 } 965 966 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 967 { 968 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 969 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 970 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 971 972 return cpu_to_le32(dword); 973 } 974 975 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 976 { 977 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 978 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 979 980 return cpu_to_le32(dword); 981 } 982 983 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 984 { 985 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 986 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 987 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 988 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 989 990 return cpu_to_le32(dword); 991 } 992 993 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 994 { 995 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 996 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 997 998 return cpu_to_le32(dword); 999 } 1000 1001 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1002 { 1003 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1004 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1005 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1006 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1007 1008 return cpu_to_le32(dword); 1009 } 1010 1011 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1012 { 1013 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1014 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1015 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1016 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1017 1018 return cpu_to_le32(dword); 1019 } 1020 1021 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1022 { 1023 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1024 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1025 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1026 desc_info->data_retry_lowest_rate); 1027 1028 return cpu_to_le32(dword); 1029 } 1030 1031 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1032 { 1033 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1034 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1035 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1036 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1037 1038 return cpu_to_le32(dword); 1039 } 1040 1041 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1042 { 1043 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1044 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1045 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1046 1047 return cpu_to_le32(dword); 1048 } 1049 1050 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1051 { 1052 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) | 1053 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1054 1055 return cpu_to_le32(dword); 1056 } 1057 1058 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1059 struct rtw89_tx_desc_info *desc_info, 1060 void *txdesc) 1061 { 1062 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1063 struct rtw89_txwd_info *txwd_info; 1064 1065 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1066 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1067 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1068 1069 if (!desc_info->en_wd_info) 1070 return; 1071 1072 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1073 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1074 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1075 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1076 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1077 1078 } 1079 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1080 1081 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1082 struct rtw89_tx_desc_info *desc_info, 1083 void *txdesc) 1084 { 1085 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1086 struct rtw89_txwd_info *txwd_info; 1087 1088 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1089 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1090 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1091 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1092 if (desc_info->sec_en) { 1093 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1094 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1095 } 1096 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1097 1098 if (!desc_info->en_wd_info) 1099 return; 1100 1101 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1102 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1103 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1104 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1105 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1106 } 1107 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1108 1109 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1110 { 1111 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1112 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1113 RTW89_CORE_RX_TYPE_FWDL : 1114 RTW89_CORE_RX_TYPE_H2C); 1115 1116 return cpu_to_le32(dword); 1117 } 1118 1119 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1120 struct rtw89_tx_desc_info *desc_info, 1121 void *txdesc) 1122 { 1123 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1124 1125 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1126 } 1127 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1128 1129 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1130 struct sk_buff *skb, 1131 struct rtw89_rx_phy_ppdu *phy_ppdu) 1132 { 1133 bool rx_cnt_valid = false; 1134 u8 plcp_size = 0; 1135 u8 usr_num = 0; 1136 u8 *phy_sts; 1137 1138 rx_cnt_valid = RTW89_GET_RXINFO_RX_CNT_VLD(skb->data); 1139 plcp_size = RTW89_GET_RXINFO_PLCP_LEN(skb->data) << 3; 1140 usr_num = RTW89_GET_RXINFO_USR_NUM(skb->data); 1141 if (usr_num > RTW89_PPDU_MAX_USR) { 1142 rtw89_warn(rtwdev, "Invalid user number in mac info\n"); 1143 return -EINVAL; 1144 } 1145 1146 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1147 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1148 /* 8-byte alignment */ 1149 if (usr_num & BIT(0)) 1150 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1151 if (rx_cnt_valid) 1152 phy_sts += RTW89_PPDU_MAC_RX_CNT_SIZE; 1153 phy_sts += plcp_size; 1154 1155 phy_ppdu->buf = phy_sts; 1156 phy_ppdu->len = skb->data + skb->len - phy_sts; 1157 1158 return 0; 1159 } 1160 1161 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1162 struct ieee80211_sta *sta) 1163 { 1164 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1165 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1166 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1167 int i; 1168 1169 if (rtwsta->mac_id == phy_ppdu->mac_id && phy_ppdu->to_self) { 1170 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1171 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1172 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1173 } 1174 } 1175 1176 #define VAR_LEN 0xff 1177 #define VAR_LEN_UNIT 8 1178 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, u8 *addr) 1179 { 1180 static const u8 physts_ie_len_tab[32] = { 1181 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1182 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1183 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1184 }; 1185 u16 ie_len; 1186 u8 ie; 1187 1188 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1189 if (physts_ie_len_tab[ie] != VAR_LEN) 1190 ie_len = physts_ie_len_tab[ie]; 1191 else 1192 ie_len = RTW89_GET_PHY_STS_IE_LEN(addr) * VAR_LEN_UNIT; 1193 1194 return ie_len; 1195 } 1196 1197 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, u8 *addr, 1198 struct rtw89_rx_phy_ppdu *phy_ppdu) 1199 { 1200 s16 cfo; 1201 1202 phy_ppdu->chan_idx = RTW89_GET_PHY_STS_IE01_CH_IDX(addr); 1203 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1204 return; 1205 /* sign conversion for S(12,2) */ 1206 if (rtwdev->chip->cfo_src_fd) 1207 cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_FD_CFO(addr), 11); 1208 else 1209 cfo = sign_extend32(RTW89_GET_PHY_STS_IE01_PREMB_CFO(addr), 11); 1210 1211 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1212 } 1213 1214 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, u8 *addr, 1215 struct rtw89_rx_phy_ppdu *phy_ppdu) 1216 { 1217 u8 ie; 1218 1219 ie = RTW89_GET_PHY_STS_IE_TYPE(addr); 1220 switch (ie) { 1221 case RTW89_PHYSTS_IE01_CMN_OFDM: 1222 rtw89_core_parse_phy_status_ie01(rtwdev, addr, phy_ppdu); 1223 break; 1224 default: 1225 break; 1226 } 1227 1228 return 0; 1229 } 1230 1231 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1232 { 1233 u8 *rssi = phy_ppdu->rssi; 1234 u8 *buf = phy_ppdu->buf; 1235 1236 phy_ppdu->ie = RTW89_GET_PHY_STS_IE_MAP(buf); 1237 phy_ppdu->rssi_avg = RTW89_GET_PHY_STS_RSSI_AVG(buf); 1238 rssi[RF_PATH_A] = RTW89_GET_PHY_STS_RSSI_A(buf); 1239 rssi[RF_PATH_B] = RTW89_GET_PHY_STS_RSSI_B(buf); 1240 rssi[RF_PATH_C] = RTW89_GET_PHY_STS_RSSI_C(buf); 1241 rssi[RF_PATH_D] = RTW89_GET_PHY_STS_RSSI_D(buf); 1242 } 1243 1244 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1245 struct rtw89_rx_phy_ppdu *phy_ppdu) 1246 { 1247 if (RTW89_GET_PHY_STS_LEN(phy_ppdu->buf) << 3 != phy_ppdu->len) { 1248 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1249 return -EINVAL; 1250 } 1251 rtw89_core_update_phy_ppdu(phy_ppdu); 1252 ieee80211_iterate_stations_atomic(rtwdev->hw, 1253 rtw89_core_rx_process_phy_ppdu_iter, 1254 phy_ppdu); 1255 1256 return 0; 1257 } 1258 1259 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1260 struct rtw89_rx_phy_ppdu *phy_ppdu) 1261 { 1262 u16 ie_len; 1263 u8 *pos, *end; 1264 1265 /* mark invalid reports and bypass them */ 1266 if (phy_ppdu->ie < RTW89_CCK_PKT) 1267 return -EINVAL; 1268 1269 if (!phy_ppdu->to_self) 1270 return 0; 1271 1272 pos = (u8 *)phy_ppdu->buf + PHY_STS_HDR_LEN; 1273 end = (u8 *)phy_ppdu->buf + phy_ppdu->len; 1274 while (pos < end) { 1275 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, pos); 1276 rtw89_core_process_phy_status_ie(rtwdev, pos, phy_ppdu); 1277 pos += ie_len; 1278 if (pos > end || ie_len == 0) { 1279 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1280 "phy status parse failed\n"); 1281 return -EINVAL; 1282 } 1283 } 1284 1285 return 0; 1286 } 1287 1288 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1289 struct rtw89_rx_phy_ppdu *phy_ppdu) 1290 { 1291 int ret; 1292 1293 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1294 if (ret) 1295 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1296 else 1297 phy_ppdu->valid = true; 1298 } 1299 1300 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1301 const struct rtw89_rx_desc_info *desc_info, 1302 bool rx_status) 1303 { 1304 switch (desc_info->gi_ltf) { 1305 case RTW89_GILTF_SGI_4XHE08: 1306 case RTW89_GILTF_2XHE08: 1307 case RTW89_GILTF_1XHE08: 1308 return NL80211_RATE_INFO_HE_GI_0_8; 1309 case RTW89_GILTF_2XHE16: 1310 case RTW89_GILTF_1XHE16: 1311 return NL80211_RATE_INFO_HE_GI_1_6; 1312 case RTW89_GILTF_LGI_4XHE32: 1313 return NL80211_RATE_INFO_HE_GI_3_2; 1314 default: 1315 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info->gi_ltf); 1316 return rx_status ? NL80211_RATE_INFO_HE_GI_3_2 : U8_MAX; 1317 } 1318 } 1319 1320 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1321 struct rtw89_rx_desc_info *desc_info, 1322 struct ieee80211_rx_status *status) 1323 { 1324 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1325 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1326 u16 data_rate; 1327 bool ret; 1328 1329 data_rate = desc_info->data_rate; 1330 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1331 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1332 rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1333 /* rate_idx is still hardware value here */ 1334 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1335 rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1336 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1337 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1338 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1339 rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1340 } else { 1341 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1342 } 1343 1344 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1345 gi_ltf = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, false); 1346 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1347 status->rate_idx == rate_idx && 1348 status->he_gi == gi_ltf && 1349 status->bw == bw; 1350 1351 return ret; 1352 } 1353 1354 struct rtw89_vif_rx_stats_iter_data { 1355 struct rtw89_dev *rtwdev; 1356 struct rtw89_rx_phy_ppdu *phy_ppdu; 1357 struct rtw89_rx_desc_info *desc_info; 1358 struct sk_buff *skb; 1359 const u8 *bssid; 1360 }; 1361 1362 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1363 struct ieee80211_vif *vif, 1364 struct sk_buff *skb) 1365 { 1366 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1367 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1368 u8 *pos, *end, type; 1369 u16 aid; 1370 1371 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1372 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1373 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1374 return; 1375 1376 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1377 if (type != IEEE80211_TRIGGER_TYPE_BASIC) 1378 return; 1379 1380 end = (u8 *)tf + skb->len; 1381 pos = tf->variable; 1382 1383 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1384 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1385 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1386 "[TF] aid: %d, ul_mcs: %d, rua: %d\n", 1387 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1388 RTW89_GET_TF_USER_INFO_RUA(pos)); 1389 1390 if (aid == RTW89_TF_PAD) 1391 break; 1392 1393 if (aid == vif->cfg.aid) { 1394 rtwvif->stats.rx_tf_acc++; 1395 rtwdev->stats.rx_tf_acc++; 1396 break; 1397 } 1398 1399 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1400 } 1401 } 1402 1403 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1404 struct sk_buff *skb) 1405 { 1406 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1407 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1408 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1409 struct rtw89_pktofld_info *info; 1410 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1411 1412 if (rx_status->band != NL80211_BAND_6GHZ) 1413 return; 1414 1415 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1416 1417 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1418 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1419 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1420 continue; 1421 } 1422 1423 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1424 continue; 1425 1426 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) 1427 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1428 } 1429 } 1430 1431 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1432 struct ieee80211_vif *vif) 1433 { 1434 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1435 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1436 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1437 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1438 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1439 struct sk_buff *skb = iter_data->skb; 1440 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1441 const u8 *bssid = iter_data->bssid; 1442 1443 if (rtwdev->scanning && 1444 (ieee80211_is_beacon(hdr->frame_control) || 1445 ieee80211_is_probe_resp(hdr->frame_control))) 1446 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1447 1448 if (!vif->bss_conf.bssid) 1449 return; 1450 1451 if (ieee80211_is_trigger(hdr->frame_control)) { 1452 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1453 return; 1454 } 1455 1456 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1457 return; 1458 1459 if (ieee80211_is_beacon(hdr->frame_control)) 1460 pkt_stat->beacon_nr++; 1461 1462 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1463 return; 1464 1465 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1466 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1467 1468 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1469 } 1470 1471 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1472 struct rtw89_rx_phy_ppdu *phy_ppdu, 1473 struct rtw89_rx_desc_info *desc_info, 1474 struct sk_buff *skb) 1475 { 1476 struct rtw89_vif_rx_stats_iter_data iter_data; 1477 1478 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1479 1480 iter_data.rtwdev = rtwdev; 1481 iter_data.phy_ppdu = phy_ppdu; 1482 iter_data.desc_info = desc_info; 1483 iter_data.skb = skb; 1484 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1485 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1486 } 1487 1488 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1489 struct ieee80211_rx_status *status) 1490 { 1491 const struct rtw89_chan_rcd *rcd = 1492 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1493 u16 chan = rcd->prev_primary_channel; 1494 u8 band = rcd->prev_band_type == RTW89_BAND_2G ? 1495 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ; 1496 1497 if (status->band != NL80211_BAND_2GHZ && 1498 status->encoding == RX_ENC_LEGACY && 1499 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1500 status->freq = ieee80211_channel_to_frequency(chan, band); 1501 status->band = band; 1502 } 1503 } 1504 1505 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1506 { 1507 if (rx_status->band == NL80211_BAND_2GHZ || 1508 rx_status->encoding != RX_ENC_LEGACY) 1509 return; 1510 1511 /* Some control frames' freq(ACKs in this case) are reported wrong due 1512 * to FW notify timing, set to lowest rate to prevent overflow. 1513 */ 1514 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1515 rx_status->rate_idx = 0; 1516 return; 1517 } 1518 1519 /* No 4 CCK rates for non-2G */ 1520 rx_status->rate_idx -= 4; 1521 } 1522 1523 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 1524 struct sk_buff *skb, 1525 struct ieee80211_rx_status *rx_status) 1526 { 1527 static const struct ieee80211_radiotap_he known_he = { 1528 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1529 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 1530 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 1531 }; 1532 struct ieee80211_radiotap_he *he; 1533 1534 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 1535 return; 1536 1537 if (rx_status->encoding == RX_ENC_HE) { 1538 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 1539 he = skb_push(skb, sizeof(*he)); 1540 *he = known_he; 1541 } 1542 } 1543 1544 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 1545 struct rtw89_rx_phy_ppdu *phy_ppdu, 1546 struct rtw89_rx_desc_info *desc_info, 1547 struct sk_buff *skb_ppdu, 1548 struct ieee80211_rx_status *rx_status) 1549 { 1550 struct napi_struct *napi = &rtwdev->napi; 1551 1552 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 1553 if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state))) 1554 napi = NULL; 1555 1556 rtw89_core_hw_to_sband_rate(rx_status); 1557 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 1558 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 1559 /* In low power mode, it does RX in thread context. */ 1560 local_bh_disable(); 1561 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 1562 local_bh_enable(); 1563 rtwdev->napi_budget_countdown--; 1564 } 1565 1566 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 1567 struct rtw89_rx_phy_ppdu *phy_ppdu, 1568 struct rtw89_rx_desc_info *desc_info, 1569 struct sk_buff *skb) 1570 { 1571 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1572 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 1573 struct sk_buff *skb_ppdu = NULL, *tmp; 1574 struct ieee80211_rx_status *rx_status; 1575 1576 if (curr > RTW89_MAX_PPDU_CNT) 1577 return; 1578 1579 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 1580 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 1581 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1582 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 1583 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 1584 rtw89_correct_cck_chan(rtwdev, rx_status); 1585 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 1586 } 1587 } 1588 1589 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 1590 struct rtw89_rx_desc_info *desc_info, 1591 struct sk_buff *skb) 1592 { 1593 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 1594 .len = skb->len, 1595 .to_self = desc_info->addr1_match, 1596 .rate = desc_info->data_rate, 1597 .mac_id = desc_info->mac_id}; 1598 int ret; 1599 1600 if (desc_info->mac_info_valid) 1601 rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 1602 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 1603 if (ret) 1604 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "process ppdu failed\n"); 1605 1606 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 1607 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 1608 dev_kfree_skb_any(skb); 1609 } 1610 1611 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 1612 struct rtw89_rx_desc_info *desc_info, 1613 struct sk_buff *skb) 1614 { 1615 switch (desc_info->pkt_type) { 1616 case RTW89_CORE_RX_TYPE_C2H: 1617 rtw89_fw_c2h_irqsafe(rtwdev, skb); 1618 break; 1619 case RTW89_CORE_RX_TYPE_PPDU_STAT: 1620 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 1621 break; 1622 default: 1623 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 1624 desc_info->pkt_type); 1625 dev_kfree_skb_any(skb); 1626 break; 1627 } 1628 } 1629 1630 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 1631 struct rtw89_rx_desc_info *desc_info, 1632 u8 *data, u32 data_offset) 1633 { 1634 const struct rtw89_chip_info *chip = rtwdev->chip; 1635 struct rtw89_rxdesc_short *rxd_s; 1636 struct rtw89_rxdesc_long *rxd_l; 1637 u8 shift_len, drv_info_len; 1638 1639 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 1640 desc_info->pkt_size = RTW89_GET_RXWD_PKT_SIZE(rxd_s); 1641 desc_info->drv_info_size = RTW89_GET_RXWD_DRV_INFO_SIZE(rxd_s); 1642 desc_info->long_rxdesc = RTW89_GET_RXWD_LONG_RXD(rxd_s); 1643 desc_info->pkt_type = RTW89_GET_RXWD_RPKT_TYPE(rxd_s); 1644 desc_info->mac_info_valid = RTW89_GET_RXWD_MAC_INFO_VALID(rxd_s); 1645 if (chip->chip_id == RTL8852C) 1646 desc_info->bw = RTW89_GET_RXWD_BW_V1(rxd_s); 1647 else 1648 desc_info->bw = RTW89_GET_RXWD_BW(rxd_s); 1649 desc_info->data_rate = RTW89_GET_RXWD_DATA_RATE(rxd_s); 1650 desc_info->gi_ltf = RTW89_GET_RXWD_GI_LTF(rxd_s); 1651 desc_info->user_id = RTW89_GET_RXWD_USER_ID(rxd_s); 1652 desc_info->sr_en = RTW89_GET_RXWD_SR_EN(rxd_s); 1653 desc_info->ppdu_cnt = RTW89_GET_RXWD_PPDU_CNT(rxd_s); 1654 desc_info->ppdu_type = RTW89_GET_RXWD_PPDU_TYPE(rxd_s); 1655 desc_info->free_run_cnt = RTW89_GET_RXWD_FREE_RUN_CNT(rxd_s); 1656 desc_info->icv_err = RTW89_GET_RXWD_ICV_ERR(rxd_s); 1657 desc_info->crc32_err = RTW89_GET_RXWD_CRC32_ERR(rxd_s); 1658 desc_info->hw_dec = RTW89_GET_RXWD_HW_DEC(rxd_s); 1659 desc_info->sw_dec = RTW89_GET_RXWD_SW_DEC(rxd_s); 1660 desc_info->addr1_match = RTW89_GET_RXWD_A1_MATCH(rxd_s); 1661 1662 shift_len = desc_info->shift << 1; /* 2-byte unit */ 1663 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 1664 desc_info->offset = data_offset + shift_len + drv_info_len; 1665 desc_info->ready = true; 1666 1667 if (!desc_info->long_rxdesc) 1668 return; 1669 1670 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 1671 desc_info->frame_type = RTW89_GET_RXWD_TYPE(rxd_l); 1672 desc_info->addr_cam_valid = RTW89_GET_RXWD_ADDR_CAM_VLD(rxd_l); 1673 desc_info->addr_cam_id = RTW89_GET_RXWD_ADDR_CAM_ID(rxd_l); 1674 desc_info->sec_cam_id = RTW89_GET_RXWD_SEC_CAM_ID(rxd_l); 1675 desc_info->mac_id = RTW89_GET_RXWD_MAC_ID(rxd_l); 1676 desc_info->rx_pl_id = RTW89_GET_RXWD_RX_PL_ID(rxd_l); 1677 } 1678 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 1679 1680 struct rtw89_core_iter_rx_status { 1681 struct rtw89_dev *rtwdev; 1682 struct ieee80211_rx_status *rx_status; 1683 struct rtw89_rx_desc_info *desc_info; 1684 u8 mac_id; 1685 }; 1686 1687 static 1688 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 1689 { 1690 struct rtw89_core_iter_rx_status *iter_data = 1691 (struct rtw89_core_iter_rx_status *)data; 1692 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 1693 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1694 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1695 u8 mac_id = iter_data->mac_id; 1696 1697 if (mac_id != rtwsta->mac_id) 1698 return; 1699 1700 rtwsta->rx_status = *rx_status; 1701 rtwsta->rx_hw_rate = desc_info->data_rate; 1702 } 1703 1704 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 1705 struct rtw89_rx_desc_info *desc_info, 1706 struct ieee80211_rx_status *rx_status) 1707 { 1708 struct rtw89_core_iter_rx_status iter_data; 1709 1710 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 1711 return; 1712 1713 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 1714 return; 1715 1716 iter_data.rtwdev = rtwdev; 1717 iter_data.rx_status = rx_status; 1718 iter_data.desc_info = desc_info; 1719 iter_data.mac_id = desc_info->mac_id; 1720 ieee80211_iterate_stations_atomic(rtwdev->hw, 1721 rtw89_core_stats_sta_rx_status_iter, 1722 &iter_data); 1723 } 1724 1725 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 1726 struct rtw89_rx_desc_info *desc_info, 1727 struct ieee80211_rx_status *rx_status) 1728 { 1729 const struct cfg80211_chan_def *chandef = 1730 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 1731 const struct rtw89_chan *cur = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 1732 u16 data_rate; 1733 u8 data_rate_mode; 1734 1735 /* currently using single PHY */ 1736 rx_status->freq = chandef->chan->center_freq; 1737 rx_status->band = chandef->chan->band; 1738 1739 if (rtwdev->scanning && 1740 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 1741 u8 chan = cur->primary_channel; 1742 u8 band = cur->band_type; 1743 enum nl80211_band nl_band; 1744 1745 nl_band = rtw89_hw_to_nl80211_band(band); 1746 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 1747 rx_status->band = nl_band; 1748 } 1749 1750 if (desc_info->icv_err || desc_info->crc32_err) 1751 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 1752 1753 if (desc_info->hw_dec && 1754 !(desc_info->sw_dec || desc_info->icv_err)) 1755 rx_status->flag |= RX_FLAG_DECRYPTED; 1756 1757 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1758 1759 data_rate = desc_info->data_rate; 1760 data_rate_mode = GET_DATA_RATE_MODE(data_rate); 1761 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1762 rx_status->encoding = RX_ENC_LEGACY; 1763 rx_status->rate_idx = GET_DATA_RATE_NOT_HT_IDX(data_rate); 1764 /* convert rate_idx after we get the correct band */ 1765 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1766 rx_status->encoding = RX_ENC_HT; 1767 rx_status->rate_idx = GET_DATA_RATE_HT_IDX(data_rate); 1768 if (desc_info->gi_ltf) 1769 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1770 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 1771 rx_status->encoding = RX_ENC_VHT; 1772 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1773 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1774 if (desc_info->gi_ltf) 1775 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 1776 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 1777 rx_status->encoding = RX_ENC_HE; 1778 rx_status->rate_idx = GET_DATA_RATE_VHT_HE_IDX(data_rate); 1779 rx_status->nss = GET_DATA_RATE_NSS(data_rate) + 1; 1780 } else { 1781 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1782 } 1783 1784 /* he_gi is used to match ppdu, so we always fill it. */ 1785 rx_status->he_gi = rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info, true); 1786 rx_status->flag |= RX_FLAG_MACTIME_START; 1787 rx_status->mactime = desc_info->free_run_cnt; 1788 1789 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 1790 } 1791 1792 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 1793 { 1794 const struct rtw89_chip_info *chip = rtwdev->chip; 1795 1796 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 1797 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 1798 return RTW89_PS_MODE_NONE; 1799 1800 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 1801 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 1802 return RTW89_PS_MODE_PWR_GATED; 1803 1804 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 1805 return RTW89_PS_MODE_CLK_GATED; 1806 1807 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 1808 return RTW89_PS_MODE_RFOFF; 1809 1810 return RTW89_PS_MODE_NONE; 1811 } 1812 1813 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 1814 struct rtw89_rx_desc_info *desc_info) 1815 { 1816 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1817 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1818 struct ieee80211_rx_status *rx_status; 1819 struct sk_buff *skb_ppdu, *tmp; 1820 1821 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 1822 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 1823 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 1824 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 1825 } 1826 } 1827 1828 void rtw89_core_rx(struct rtw89_dev *rtwdev, 1829 struct rtw89_rx_desc_info *desc_info, 1830 struct sk_buff *skb) 1831 { 1832 struct ieee80211_rx_status *rx_status; 1833 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 1834 u8 ppdu_cnt = desc_info->ppdu_cnt; 1835 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1836 1837 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 1838 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 1839 return; 1840 } 1841 1842 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 1843 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 1844 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 1845 } 1846 1847 rx_status = IEEE80211_SKB_RXCB(skb); 1848 memset(rx_status, 0, sizeof(*rx_status)); 1849 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 1850 if (desc_info->long_rxdesc && 1851 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 1852 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 1853 else 1854 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 1855 } 1856 EXPORT_SYMBOL(rtw89_core_rx); 1857 1858 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 1859 { 1860 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1861 return; 1862 1863 napi_enable(&rtwdev->napi); 1864 } 1865 EXPORT_SYMBOL(rtw89_core_napi_start); 1866 1867 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 1868 { 1869 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 1870 return; 1871 1872 napi_synchronize(&rtwdev->napi); 1873 napi_disable(&rtwdev->napi); 1874 } 1875 EXPORT_SYMBOL(rtw89_core_napi_stop); 1876 1877 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 1878 { 1879 init_dummy_netdev(&rtwdev->netdev); 1880 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 1881 rtwdev->hci.ops->napi_poll); 1882 } 1883 EXPORT_SYMBOL(rtw89_core_napi_init); 1884 1885 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 1886 { 1887 rtw89_core_napi_stop(rtwdev); 1888 netif_napi_del(&rtwdev->napi); 1889 } 1890 EXPORT_SYMBOL(rtw89_core_napi_deinit); 1891 1892 static void rtw89_core_ba_work(struct work_struct *work) 1893 { 1894 struct rtw89_dev *rtwdev = 1895 container_of(work, struct rtw89_dev, ba_work); 1896 struct rtw89_txq *rtwtxq, *tmp; 1897 int ret; 1898 1899 spin_lock_bh(&rtwdev->ba_lock); 1900 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1901 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1902 struct ieee80211_sta *sta = txq->sta; 1903 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1904 u8 tid = txq->tid; 1905 1906 if (!sta) { 1907 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 1908 goto skip_ba_work; 1909 } 1910 1911 if (rtwsta->disassoc) { 1912 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1913 "cannot start BA with disassoc sta\n"); 1914 goto skip_ba_work; 1915 } 1916 1917 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 1918 if (ret) { 1919 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1920 "failed to setup BA session for %pM:%2d: %d\n", 1921 sta->addr, tid, ret); 1922 if (ret == -EINVAL) 1923 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 1924 } 1925 skip_ba_work: 1926 list_del_init(&rtwtxq->list); 1927 } 1928 spin_unlock_bh(&rtwdev->ba_lock); 1929 } 1930 1931 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 1932 struct ieee80211_sta *sta) 1933 { 1934 struct rtw89_txq *rtwtxq, *tmp; 1935 1936 spin_lock_bh(&rtwdev->ba_lock); 1937 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 1938 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1939 1940 if (sta == txq->sta) 1941 list_del_init(&rtwtxq->list); 1942 } 1943 spin_unlock_bh(&rtwdev->ba_lock); 1944 } 1945 1946 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 1947 struct ieee80211_sta *sta) 1948 { 1949 struct rtw89_txq *rtwtxq, *tmp; 1950 1951 spin_lock_bh(&rtwdev->ba_lock); 1952 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 1953 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1954 1955 if (sta == txq->sta) { 1956 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 1957 list_del_init(&rtwtxq->list); 1958 } 1959 } 1960 spin_unlock_bh(&rtwdev->ba_lock); 1961 } 1962 1963 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 1964 struct rtw89_txq *rtwtxq) 1965 { 1966 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1967 struct ieee80211_sta *sta = txq->sta; 1968 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1969 1970 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 1971 return; 1972 1973 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 1974 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1975 return; 1976 1977 spin_lock_bh(&rtwdev->ba_lock); 1978 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1979 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 1980 spin_unlock_bh(&rtwdev->ba_lock); 1981 1982 ieee80211_stop_tx_ba_session(sta, txq->tid); 1983 cancel_delayed_work(&rtwdev->forbid_ba_work); 1984 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 1985 RTW89_FORBID_BA_TIMER); 1986 } 1987 1988 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 1989 struct rtw89_txq *rtwtxq, 1990 struct sk_buff *skb) 1991 { 1992 struct ieee80211_hw *hw = rtwdev->hw; 1993 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 1994 struct ieee80211_sta *sta = txq->sta; 1995 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 1996 1997 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 1998 return; 1999 2000 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2001 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2002 return; 2003 } 2004 2005 if (unlikely(!sta)) 2006 return; 2007 2008 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2009 return; 2010 2011 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2012 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2013 return; 2014 } 2015 2016 spin_lock_bh(&rtwdev->ba_lock); 2017 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2018 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2019 ieee80211_queue_work(hw, &rtwdev->ba_work); 2020 } 2021 spin_unlock_bh(&rtwdev->ba_lock); 2022 } 2023 2024 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2025 struct rtw89_txq *rtwtxq, 2026 unsigned long frame_cnt, 2027 unsigned long byte_cnt) 2028 { 2029 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2030 struct ieee80211_vif *vif = txq->vif; 2031 struct ieee80211_sta *sta = txq->sta; 2032 struct sk_buff *skb; 2033 unsigned long i; 2034 int ret; 2035 2036 rcu_read_lock(); 2037 for (i = 0; i < frame_cnt; i++) { 2038 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2039 if (!skb) { 2040 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2041 goto out; 2042 } 2043 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2044 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2045 if (ret) { 2046 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2047 ieee80211_free_txskb(rtwdev->hw, skb); 2048 break; 2049 } 2050 } 2051 out: 2052 rcu_read_unlock(); 2053 } 2054 2055 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2056 { 2057 u8 qsel, ch_dma; 2058 2059 qsel = rtw89_core_get_qsel(rtwdev, tid); 2060 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2061 2062 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2063 } 2064 2065 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2066 struct ieee80211_txq *txq, 2067 unsigned long *frame_cnt, 2068 bool *sched_txq, bool *reinvoke) 2069 { 2070 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2071 struct ieee80211_sta *sta = txq->sta; 2072 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2073 2074 if (!sta || rtwsta->max_agg_wait <= 0) 2075 return false; 2076 2077 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2078 return false; 2079 2080 if (*frame_cnt > 1) { 2081 *frame_cnt -= 1; 2082 *sched_txq = true; 2083 *reinvoke = true; 2084 rtwtxq->wait_cnt = 1; 2085 return false; 2086 } 2087 2088 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2089 *reinvoke = true; 2090 rtwtxq->wait_cnt++; 2091 return true; 2092 } 2093 2094 rtwtxq->wait_cnt = 0; 2095 return false; 2096 } 2097 2098 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2099 { 2100 struct ieee80211_hw *hw = rtwdev->hw; 2101 struct ieee80211_txq *txq; 2102 struct rtw89_txq *rtwtxq; 2103 unsigned long frame_cnt; 2104 unsigned long byte_cnt; 2105 u32 tx_resource; 2106 bool sched_txq; 2107 2108 ieee80211_txq_schedule_start(hw, ac); 2109 while ((txq = ieee80211_next_txq(hw, ac))) { 2110 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2111 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2112 sched_txq = false; 2113 2114 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2115 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2116 ieee80211_return_txq(hw, txq, true); 2117 continue; 2118 } 2119 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2120 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2121 ieee80211_return_txq(hw, txq, sched_txq); 2122 if (frame_cnt != 0) 2123 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2124 2125 /* bound of tx_resource could get stuck due to burst traffic */ 2126 if (frame_cnt == tx_resource) 2127 *reinvoke = true; 2128 } 2129 ieee80211_txq_schedule_end(hw, ac); 2130 } 2131 2132 static void rtw89_ips_work(struct work_struct *work) 2133 { 2134 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2135 ips_work); 2136 mutex_lock(&rtwdev->mutex); 2137 if (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE) 2138 rtw89_enter_ips(rtwdev); 2139 mutex_unlock(&rtwdev->mutex); 2140 } 2141 2142 static void rtw89_core_txq_work(struct work_struct *w) 2143 { 2144 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2145 bool reinvoke = false; 2146 u8 ac; 2147 2148 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2149 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2150 2151 if (reinvoke) { 2152 /* reinvoke to process the last frame */ 2153 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2154 } 2155 } 2156 2157 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2158 { 2159 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2160 txq_reinvoke_work.work); 2161 2162 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2163 } 2164 2165 static void rtw89_forbid_ba_work(struct work_struct *w) 2166 { 2167 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2168 forbid_ba_work.work); 2169 struct rtw89_txq *rtwtxq, *tmp; 2170 2171 spin_lock_bh(&rtwdev->ba_lock); 2172 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2173 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2174 list_del_init(&rtwtxq->list); 2175 } 2176 spin_unlock_bh(&rtwdev->ba_lock); 2177 } 2178 2179 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 2180 u32 throughput, u64 cnt) 2181 { 2182 if (cnt < 100) 2183 return RTW89_TFC_IDLE; 2184 if (throughput > 50) 2185 return RTW89_TFC_HIGH; 2186 if (throughput > 10) 2187 return RTW89_TFC_MID; 2188 if (throughput > 2) 2189 return RTW89_TFC_LOW; 2190 return RTW89_TFC_ULTRA_LOW; 2191 } 2192 2193 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 2194 struct rtw89_traffic_stats *stats) 2195 { 2196 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2197 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2198 2199 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 2200 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 2201 2202 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 2203 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 2204 2205 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 2206 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 2207 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 2208 stats->tx_cnt); 2209 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 2210 stats->rx_cnt); 2211 stats->tx_avg_len = stats->tx_cnt ? 2212 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 2213 stats->rx_avg_len = stats->rx_cnt ? 2214 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 2215 2216 stats->tx_unicast = 0; 2217 stats->rx_unicast = 0; 2218 stats->tx_cnt = 0; 2219 stats->rx_cnt = 0; 2220 stats->rx_tf_periodic = stats->rx_tf_acc; 2221 stats->rx_tf_acc = 0; 2222 2223 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 2224 return true; 2225 2226 return false; 2227 } 2228 2229 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 2230 { 2231 struct rtw89_vif *rtwvif; 2232 bool tfc_changed; 2233 2234 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 2235 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2236 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 2237 2238 return tfc_changed; 2239 } 2240 2241 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2242 { 2243 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 2244 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 2245 rtwvif->tdls_peer) 2246 return; 2247 2248 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 2249 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 2250 rtw89_enter_lps(rtwdev, rtwvif); 2251 } 2252 2253 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 2254 { 2255 struct rtw89_vif *rtwvif; 2256 2257 rtw89_for_each_rtwvif(rtwdev, rtwvif) 2258 rtw89_vif_enter_lps(rtwdev, rtwvif); 2259 } 2260 2261 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 2262 struct rtw89_traffic_stats *stats) 2263 { 2264 stats->tx_unicast = 0; 2265 stats->rx_unicast = 0; 2266 stats->tx_cnt = 0; 2267 stats->rx_cnt = 0; 2268 ewma_tp_init(&stats->tx_ewma_tp); 2269 ewma_tp_init(&stats->rx_ewma_tp); 2270 } 2271 2272 static void rtw89_track_work(struct work_struct *work) 2273 { 2274 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2275 track_work.work); 2276 bool tfc_changed; 2277 2278 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 2279 return; 2280 2281 mutex_lock(&rtwdev->mutex); 2282 2283 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 2284 goto out; 2285 2286 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 2287 RTW89_TRACK_WORK_PERIOD); 2288 2289 tfc_changed = rtw89_traffic_stats_track(rtwdev); 2290 if (rtwdev->scanning) 2291 goto out; 2292 2293 rtw89_leave_lps(rtwdev); 2294 2295 if (tfc_changed) { 2296 rtw89_hci_recalc_int_mit(rtwdev); 2297 rtw89_btc_ntfy_wl_sta(rtwdev); 2298 } 2299 rtw89_mac_bf_monitor_track(rtwdev); 2300 rtw89_phy_stat_track(rtwdev); 2301 rtw89_phy_env_monitor_track(rtwdev); 2302 rtw89_phy_dig(rtwdev); 2303 rtw89_chip_rfk_track(rtwdev); 2304 rtw89_phy_ra_update(rtwdev); 2305 rtw89_phy_cfo_track(rtwdev); 2306 rtw89_phy_tx_path_div_track(rtwdev); 2307 rtw89_phy_ul_tb_ctrl_track(rtwdev); 2308 2309 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 2310 rtw89_enter_lps_track(rtwdev); 2311 2312 out: 2313 mutex_unlock(&rtwdev->mutex); 2314 } 2315 2316 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 2317 { 2318 unsigned long bit; 2319 2320 bit = find_first_zero_bit(addr, size); 2321 if (bit < size) 2322 set_bit(bit, addr); 2323 2324 return bit; 2325 } 2326 2327 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 2328 { 2329 clear_bit(bit, addr); 2330 } 2331 2332 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 2333 { 2334 bitmap_zero(addr, nbits); 2335 } 2336 2337 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 2338 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2339 { 2340 const struct rtw89_chip_info *chip = rtwdev->chip; 2341 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2342 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2343 u8 idx; 2344 int i; 2345 2346 lockdep_assert_held(&rtwdev->mutex); 2347 2348 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 2349 if (idx == chip->bacam_num) { 2350 /* allocate a static BA CAM to tid=0/5, so replace the existing 2351 * one if BA CAM is full. Hardware will process the original tid 2352 * automatically. 2353 */ 2354 if (tid != 0 && tid != 5) 2355 return -ENOSPC; 2356 2357 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 2358 tmp = &cam_info->ba_cam_entry[i]; 2359 if (tmp->tid == 0 || tmp->tid == 5) 2360 continue; 2361 2362 idx = i; 2363 entry = tmp; 2364 list_del(&entry->list); 2365 break; 2366 } 2367 2368 if (!entry) 2369 return -ENOSPC; 2370 } else { 2371 entry = &cam_info->ba_cam_entry[idx]; 2372 } 2373 2374 entry->tid = tid; 2375 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 2376 2377 *cam_idx = idx; 2378 2379 return 0; 2380 } 2381 2382 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 2383 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 2384 { 2385 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 2386 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 2387 u8 idx; 2388 2389 lockdep_assert_held(&rtwdev->mutex); 2390 2391 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 2392 if (entry->tid != tid) 2393 continue; 2394 2395 idx = entry - cam_info->ba_cam_entry; 2396 list_del(&entry->list); 2397 2398 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 2399 *cam_idx = idx; 2400 return 0; 2401 } 2402 2403 return -ENOENT; 2404 } 2405 2406 #define RTW89_TYPE_MAPPING(_type) \ 2407 case NL80211_IFTYPE_ ## _type: \ 2408 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 2409 break 2410 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 2411 { 2412 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2413 2414 switch (vif->type) { 2415 case NL80211_IFTYPE_STATION: 2416 if (vif->p2p) 2417 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 2418 else 2419 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 2420 break; 2421 case NL80211_IFTYPE_AP: 2422 if (vif->p2p) 2423 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 2424 else 2425 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 2426 break; 2427 RTW89_TYPE_MAPPING(ADHOC); 2428 RTW89_TYPE_MAPPING(MONITOR); 2429 RTW89_TYPE_MAPPING(MESH_POINT); 2430 default: 2431 WARN_ON(1); 2432 break; 2433 } 2434 2435 switch (vif->type) { 2436 case NL80211_IFTYPE_AP: 2437 case NL80211_IFTYPE_MESH_POINT: 2438 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 2439 rtwvif->self_role = RTW89_SELF_ROLE_AP; 2440 break; 2441 case NL80211_IFTYPE_ADHOC: 2442 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 2443 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2444 break; 2445 case NL80211_IFTYPE_STATION: 2446 if (assoc) { 2447 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 2448 rtwvif->trigger = vif->bss_conf.he_support; 2449 } else { 2450 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 2451 rtwvif->trigger = false; 2452 } 2453 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 2454 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 2455 break; 2456 case NL80211_IFTYPE_MONITOR: 2457 break; 2458 default: 2459 WARN_ON(1); 2460 break; 2461 } 2462 } 2463 2464 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 2465 struct ieee80211_vif *vif, 2466 struct ieee80211_sta *sta) 2467 { 2468 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2469 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2470 int i; 2471 int ret; 2472 2473 rtwsta->rtwdev = rtwdev; 2474 rtwsta->rtwvif = rtwvif; 2475 rtwsta->prev_rssi = 0; 2476 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 2477 2478 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 2479 rtw89_core_txq_init(rtwdev, sta->txq[i]); 2480 2481 ewma_rssi_init(&rtwsta->avg_rssi); 2482 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 2483 ewma_rssi_init(&rtwsta->rssi[i]); 2484 2485 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2486 /* for station mode, assign the mac_id from itself */ 2487 rtwsta->mac_id = rtwvif->mac_id; 2488 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2489 BTC_ROLE_MSTS_STA_CONN_START); 2490 rtw89_chip_rfk_channel(rtwdev); 2491 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2492 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 2493 RTW89_MAX_MAC_ID_NUM); 2494 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 2495 return -ENOSPC; 2496 2497 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 2498 if (ret) { 2499 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2500 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 2501 return ret; 2502 } 2503 2504 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 2505 RTW89_ROLE_CREATE); 2506 if (ret) { 2507 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2508 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2509 return ret; 2510 } 2511 } 2512 2513 return 0; 2514 } 2515 2516 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 2517 struct ieee80211_vif *vif, 2518 struct ieee80211_sta *sta) 2519 { 2520 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2521 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2522 2523 rtwdev->total_sta_assoc--; 2524 if (sta->tdls) 2525 rtwvif->tdls_peer--; 2526 rtwsta->disassoc = true; 2527 2528 return 0; 2529 } 2530 2531 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 2532 struct ieee80211_vif *vif, 2533 struct ieee80211_sta *sta) 2534 { 2535 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2536 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2537 int ret; 2538 2539 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 2540 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 2541 rtw89_core_free_sta_pending_ba(rtwdev, sta); 2542 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 2543 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 2544 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 2545 if (sta->tdls) 2546 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 2547 2548 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2549 rtw89_vif_type_mapping(vif, false); 2550 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 2551 } 2552 2553 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2554 if (ret) { 2555 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2556 return ret; 2557 } 2558 2559 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 2560 if (ret) { 2561 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2562 return ret; 2563 } 2564 2565 /* update cam aid mac_id net_type */ 2566 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2567 if (ret) { 2568 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2569 return ret; 2570 } 2571 2572 return ret; 2573 } 2574 2575 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 2576 struct ieee80211_vif *vif, 2577 struct ieee80211_sta *sta) 2578 { 2579 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2580 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2581 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 2582 int ret; 2583 2584 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2585 if (sta->tdls) { 2586 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 2587 if (ret) { 2588 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 2589 return ret; 2590 } 2591 } 2592 2593 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 2594 if (ret) { 2595 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 2596 return ret; 2597 } 2598 } 2599 2600 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 2601 if (ret) { 2602 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 2603 return ret; 2604 } 2605 2606 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 2607 if (ret) { 2608 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 2609 return ret; 2610 } 2611 2612 /* update cam aid mac_id net_type */ 2613 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 2614 if (ret) { 2615 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 2616 return ret; 2617 } 2618 2619 rtwdev->total_sta_assoc++; 2620 if (sta->tdls) 2621 rtwvif->tdls_peer++; 2622 rtw89_phy_ra_assoc(rtwdev, sta); 2623 rtw89_mac_bf_assoc(rtwdev, vif, sta); 2624 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 2625 2626 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 2627 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 2628 2629 if (bss_conf->he_support && 2630 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 2631 rtwsta->er_cap = true; 2632 2633 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2634 BTC_ROLE_MSTS_STA_CONN_END); 2635 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template); 2636 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 2637 2638 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 2639 if (ret) { 2640 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 2641 return ret; 2642 } 2643 } 2644 2645 return ret; 2646 } 2647 2648 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 2649 struct ieee80211_vif *vif, 2650 struct ieee80211_sta *sta) 2651 { 2652 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 2653 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2654 int ret; 2655 2656 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) 2657 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 2658 BTC_ROLE_MSTS_STA_DIS_CONN); 2659 else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 2660 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 2661 2662 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 2663 RTW89_ROLE_REMOVE); 2664 if (ret) { 2665 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 2666 return ret; 2667 } 2668 } 2669 2670 return 0; 2671 } 2672 2673 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 2674 struct ieee80211_sta *sta, 2675 struct cfg80211_tid_cfg *tid_conf) 2676 { 2677 struct ieee80211_txq *txq; 2678 struct rtw89_txq *rtwtxq; 2679 u32 mask = tid_conf->mask; 2680 u8 tids = tid_conf->tids; 2681 int tids_nbit = BITS_PER_BYTE; 2682 int i; 2683 2684 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 2685 if (!tids) 2686 break; 2687 2688 if (!(tids & BIT(0))) 2689 continue; 2690 2691 txq = sta->txq[i]; 2692 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2693 2694 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 2695 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 2696 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2697 } else { 2698 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 2699 ieee80211_stop_tx_ba_session(sta, txq->tid); 2700 spin_lock_bh(&rtwdev->ba_lock); 2701 list_del_init(&rtwtxq->list); 2702 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2703 spin_unlock_bh(&rtwdev->ba_lock); 2704 } 2705 } 2706 2707 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 2708 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 2709 sta->max_amsdu_subframes = 0; 2710 else 2711 sta->max_amsdu_subframes = 1; 2712 } 2713 } 2714 } 2715 2716 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 2717 struct ieee80211_sta *sta, 2718 struct cfg80211_tid_config *tid_config) 2719 { 2720 int i; 2721 2722 for (i = 0; i < tid_config->n_tid_conf; i++) 2723 _rtw89_core_set_tid_config(rtwdev, sta, 2724 &tid_config->tid_conf[i]); 2725 } 2726 2727 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 2728 struct ieee80211_sta_ht_cap *ht_cap) 2729 { 2730 static const __le16 highest[RF_PATH_MAX] = { 2731 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 2732 }; 2733 struct rtw89_hal *hal = &rtwdev->hal; 2734 u8 nss = hal->rx_nss; 2735 int i; 2736 2737 ht_cap->ht_supported = true; 2738 ht_cap->cap = 0; 2739 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 2740 IEEE80211_HT_CAP_MAX_AMSDU | 2741 IEEE80211_HT_CAP_TX_STBC | 2742 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 2743 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 2744 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 2745 IEEE80211_HT_CAP_DSSSCCK40 | 2746 IEEE80211_HT_CAP_SGI_40; 2747 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 2748 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 2749 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 2750 for (i = 0; i < nss; i++) 2751 ht_cap->mcs.rx_mask[i] = 0xFF; 2752 ht_cap->mcs.rx_mask[4] = 0x01; 2753 ht_cap->mcs.rx_highest = highest[nss - 1]; 2754 } 2755 2756 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 2757 struct ieee80211_sta_vht_cap *vht_cap) 2758 { 2759 static const __le16 highest_bw80[RF_PATH_MAX] = { 2760 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 2761 }; 2762 static const __le16 highest_bw160[RF_PATH_MAX] = { 2763 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 2764 }; 2765 const struct rtw89_chip_info *chip = rtwdev->chip; 2766 const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80; 2767 struct rtw89_hal *hal = &rtwdev->hal; 2768 u16 tx_mcs_map = 0, rx_mcs_map = 0; 2769 u8 sts_cap = 3; 2770 int i; 2771 2772 for (i = 0; i < 8; i++) { 2773 if (i < hal->tx_nss) 2774 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2775 else 2776 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2777 if (i < hal->rx_nss) 2778 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 2779 else 2780 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 2781 } 2782 2783 vht_cap->vht_supported = true; 2784 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 2785 IEEE80211_VHT_CAP_SHORT_GI_80 | 2786 IEEE80211_VHT_CAP_RXSTBC_1 | 2787 IEEE80211_VHT_CAP_HTC_VHT | 2788 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 2789 0; 2790 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 2791 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 2792 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 2793 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 2794 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 2795 if (chip->support_bw160) 2796 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 2797 IEEE80211_VHT_CAP_SHORT_GI_160; 2798 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 2799 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 2800 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 2801 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 2802 } 2803 2804 #define RTW89_SBAND_IFTYPES_NR 2 2805 2806 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 2807 enum nl80211_band band, 2808 struct ieee80211_supported_band *sband) 2809 { 2810 const struct rtw89_chip_info *chip = rtwdev->chip; 2811 struct rtw89_hal *hal = &rtwdev->hal; 2812 struct ieee80211_sband_iftype_data *iftype_data; 2813 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 2814 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 2815 u16 mcs_map = 0; 2816 int i; 2817 int nss = hal->rx_nss; 2818 int idx = 0; 2819 2820 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 2821 if (!iftype_data) 2822 return; 2823 2824 for (i = 0; i < 8; i++) { 2825 if (i < nss) 2826 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 2827 else 2828 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 2829 } 2830 2831 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 2832 struct ieee80211_sta_he_cap *he_cap; 2833 u8 *mac_cap_info; 2834 u8 *phy_cap_info; 2835 2836 switch (i) { 2837 case NL80211_IFTYPE_STATION: 2838 case NL80211_IFTYPE_AP: 2839 break; 2840 default: 2841 continue; 2842 } 2843 2844 if (idx >= RTW89_SBAND_IFTYPES_NR) { 2845 rtw89_warn(rtwdev, "run out of iftype_data\n"); 2846 break; 2847 } 2848 2849 iftype_data[idx].types_mask = BIT(i); 2850 he_cap = &iftype_data[idx].he_cap; 2851 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 2852 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 2853 2854 he_cap->has_he = true; 2855 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 2856 if (i == NL80211_IFTYPE_STATION) 2857 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 2858 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 2859 IEEE80211_HE_MAC_CAP2_BSR; 2860 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 2861 if (i == NL80211_IFTYPE_AP) 2862 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 2863 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 2864 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 2865 if (i == NL80211_IFTYPE_STATION) 2866 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 2867 if (band == NL80211_BAND_2GHZ) { 2868 phy_cap_info[0] = 2869 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 2870 } else { 2871 phy_cap_info[0] = 2872 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 2873 if (chip->support_bw160) 2874 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 2875 } 2876 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 2877 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 2878 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 2879 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 2880 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 2881 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 2882 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 2883 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 2884 if (i == NL80211_IFTYPE_STATION) 2885 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 2886 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 2887 if (i == NL80211_IFTYPE_AP) 2888 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 2889 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 2890 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 2891 if (chip->support_bw160) 2892 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 2893 phy_cap_info[5] = no_ng16 ? 0 : 2894 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 2895 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 2896 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 2897 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 2898 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 2899 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 2900 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 2901 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 2902 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 2903 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 2904 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 2905 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 2906 if (chip->support_bw160) 2907 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 2908 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 2909 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 2910 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 2911 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 2912 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 2913 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 2914 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 2915 if (i == NL80211_IFTYPE_STATION) 2916 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 2917 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 2918 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 2919 if (chip->support_bw160) { 2920 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 2921 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 2922 } 2923 2924 if (band == NL80211_BAND_6GHZ) { 2925 __le16 capa; 2926 2927 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 2928 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 2929 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 2930 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 2931 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 2932 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 2933 iftype_data[idx].he_6ghz_capa.capa = capa; 2934 } 2935 2936 idx++; 2937 } 2938 2939 sband->iftype_data = iftype_data; 2940 sband->n_iftype_data = idx; 2941 } 2942 2943 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 2944 { 2945 struct ieee80211_hw *hw = rtwdev->hw; 2946 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 2947 struct ieee80211_supported_band *sband_6ghz = NULL; 2948 u32 size = sizeof(struct ieee80211_supported_band); 2949 u8 support_bands = rtwdev->chip->support_bands; 2950 2951 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 2952 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 2953 if (!sband_2ghz) 2954 goto err; 2955 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 2956 rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 2957 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 2958 } 2959 2960 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 2961 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 2962 if (!sband_5ghz) 2963 goto err; 2964 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 2965 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 2966 rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 2967 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 2968 } 2969 2970 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 2971 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 2972 if (!sband_6ghz) 2973 goto err; 2974 rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 2975 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 2976 } 2977 2978 return 0; 2979 2980 err: 2981 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 2982 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 2983 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 2984 if (sband_2ghz) 2985 kfree(sband_2ghz->iftype_data); 2986 if (sband_5ghz) 2987 kfree(sband_5ghz->iftype_data); 2988 if (sband_6ghz) 2989 kfree(sband_6ghz->iftype_data); 2990 kfree(sband_2ghz); 2991 kfree(sband_5ghz); 2992 kfree(sband_6ghz); 2993 return -ENOMEM; 2994 } 2995 2996 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 2997 { 2998 struct ieee80211_hw *hw = rtwdev->hw; 2999 3000 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 3001 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 3002 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 3003 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 3004 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 3005 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 3006 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 3007 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3008 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3009 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3010 } 3011 3012 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 3013 { 3014 int i; 3015 3016 for (i = 0; i < RTW89_PHY_MAX; i++) 3017 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 3018 for (i = 0; i < RTW89_PHY_MAX; i++) 3019 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 3020 } 3021 3022 void rtw89_core_update_beacon_work(struct work_struct *work) 3023 { 3024 struct rtw89_dev *rtwdev; 3025 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3026 update_beacon_work); 3027 3028 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 3029 return; 3030 3031 rtwdev = rtwvif->rtwdev; 3032 mutex_lock(&rtwdev->mutex); 3033 rtw89_fw_h2c_update_beacon(rtwdev, rtwvif); 3034 mutex_unlock(&rtwdev->mutex); 3035 } 3036 3037 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 3038 { 3039 struct completion *cmpl = &wait->completion; 3040 unsigned long timeout; 3041 unsigned int cur; 3042 3043 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 3044 if (cur != RTW89_WAIT_COND_IDLE) 3045 return -EBUSY; 3046 3047 timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 3048 if (timeout == 0) { 3049 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3050 return -ETIMEDOUT; 3051 } 3052 3053 if (wait->data.err) 3054 return -EFAULT; 3055 3056 return 0; 3057 } 3058 3059 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 3060 const struct rtw89_completion_data *data) 3061 { 3062 unsigned int cur; 3063 3064 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 3065 if (cur != cond) 3066 return; 3067 3068 wait->data = *data; 3069 complete(&wait->completion); 3070 } 3071 3072 int rtw89_core_start(struct rtw89_dev *rtwdev) 3073 { 3074 int ret; 3075 3076 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 3077 ret = rtw89_mac_init(rtwdev); 3078 if (ret) { 3079 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 3080 return ret; 3081 } 3082 3083 rtw89_btc_ntfy_poweron(rtwdev); 3084 3085 /* efuse process */ 3086 3087 /* pre-config BB/RF, BB reset/RFC reset */ 3088 ret = rtw89_chip_disable_bb_rf(rtwdev); 3089 if (ret) 3090 return ret; 3091 ret = rtw89_chip_enable_bb_rf(rtwdev); 3092 if (ret) 3093 return ret; 3094 3095 rtw89_phy_init_bb_reg(rtwdev); 3096 rtw89_phy_init_rf_reg(rtwdev, false); 3097 3098 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 3099 3100 rtw89_phy_dm_init(rtwdev); 3101 3102 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 3103 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 3104 3105 ret = rtw89_hci_start(rtwdev); 3106 if (ret) { 3107 rtw89_err(rtwdev, "failed to start hci\n"); 3108 return ret; 3109 } 3110 3111 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3112 RTW89_TRACK_WORK_PERIOD); 3113 3114 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3115 3116 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 3117 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.fw_log_enable); 3118 rtw89_fw_h2c_init_ba_cam(rtwdev); 3119 3120 return 0; 3121 } 3122 3123 void rtw89_core_stop(struct rtw89_dev *rtwdev) 3124 { 3125 struct rtw89_btc *btc = &rtwdev->btc; 3126 3127 /* Prvent to stop twice; enter_ips and ops_stop */ 3128 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3129 return; 3130 3131 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 3132 3133 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3134 3135 mutex_unlock(&rtwdev->mutex); 3136 3137 cancel_work_sync(&rtwdev->c2h_work); 3138 cancel_work_sync(&btc->eapol_notify_work); 3139 cancel_work_sync(&btc->arp_notify_work); 3140 cancel_work_sync(&btc->dhcp_notify_work); 3141 cancel_work_sync(&btc->icmp_notify_work); 3142 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 3143 cancel_delayed_work_sync(&rtwdev->track_work); 3144 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 3145 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 3146 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 3147 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 3148 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 3149 3150 mutex_lock(&rtwdev->mutex); 3151 3152 rtw89_btc_ntfy_poweroff(rtwdev); 3153 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3154 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 3155 rtw89_hci_stop(rtwdev); 3156 rtw89_hci_deinit(rtwdev); 3157 rtw89_mac_pwr_off(rtwdev); 3158 rtw89_hci_reset(rtwdev); 3159 } 3160 3161 int rtw89_core_init(struct rtw89_dev *rtwdev) 3162 { 3163 struct rtw89_btc *btc = &rtwdev->btc; 3164 int ret; 3165 u8 band; 3166 3167 INIT_LIST_HEAD(&rtwdev->ba_list); 3168 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 3169 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 3170 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 3171 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 3172 if (!(rtwdev->chip->support_bands & BIT(band))) 3173 continue; 3174 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 3175 } 3176 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 3177 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 3178 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 3179 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 3180 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 3181 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 3182 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 3183 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 3184 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 3185 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 3186 if (!rtwdev->txq_wq) 3187 return -ENOMEM; 3188 spin_lock_init(&rtwdev->ba_lock); 3189 spin_lock_init(&rtwdev->rpwm_lock); 3190 mutex_init(&rtwdev->mutex); 3191 mutex_init(&rtwdev->rf_mutex); 3192 rtwdev->total_sta_assoc = 0; 3193 3194 rtw89_init_wait(&rtwdev->mcc.wait); 3195 3196 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 3197 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 3198 skb_queue_head_init(&rtwdev->c2h_queue); 3199 rtw89_core_ppdu_sts_init(rtwdev); 3200 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 3201 3202 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 3203 3204 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 3205 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 3206 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 3207 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 3208 3209 ret = rtw89_load_firmware(rtwdev); 3210 if (ret) { 3211 rtw89_warn(rtwdev, "no firmware loaded\n"); 3212 destroy_workqueue(rtwdev->txq_wq); 3213 return ret; 3214 } 3215 rtw89_ser_init(rtwdev); 3216 rtw89_entity_init(rtwdev); 3217 3218 return 0; 3219 } 3220 EXPORT_SYMBOL(rtw89_core_init); 3221 3222 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 3223 { 3224 rtw89_ser_deinit(rtwdev); 3225 rtw89_unload_firmware(rtwdev); 3226 rtw89_fw_free_all_early_h2c(rtwdev); 3227 3228 destroy_workqueue(rtwdev->txq_wq); 3229 mutex_destroy(&rtwdev->rf_mutex); 3230 mutex_destroy(&rtwdev->mutex); 3231 } 3232 EXPORT_SYMBOL(rtw89_core_deinit); 3233 3234 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 3235 const u8 *mac_addr, bool hw_scan) 3236 { 3237 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0); 3238 3239 rtwdev->scanning = true; 3240 rtw89_leave_lps(rtwdev); 3241 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3242 rtw89_leave_ips(rtwdev); 3243 3244 ether_addr_copy(rtwvif->mac_addr, mac_addr); 3245 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 3246 rtw89_chip_rfk_scan(rtwdev, true); 3247 rtw89_hci_recalc_int_mit(rtwdev); 3248 3249 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 3250 } 3251 3252 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 3253 struct ieee80211_vif *vif, bool hw_scan) 3254 { 3255 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 3256 3257 if (!rtwvif) 3258 return; 3259 3260 ether_addr_copy(rtwvif->mac_addr, vif->addr); 3261 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 3262 3263 rtw89_chip_rfk_scan(rtwdev, false); 3264 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 3265 3266 rtwdev->scanning = false; 3267 rtwdev->dig.bypass_dig = true; 3268 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 3269 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 3270 } 3271 3272 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 3273 { 3274 const struct rtw89_chip_info *chip = rtwdev->chip; 3275 u8 cv; 3276 3277 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 3278 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 3279 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 3280 cv = CHIP_CAV; 3281 else 3282 cv = CHIP_CBV; 3283 } 3284 3285 rtwdev->hal.cv = cv; 3286 } 3287 3288 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 3289 { 3290 rtwdev->hal.support_cckpd = 3291 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 3292 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 3293 rtwdev->hal.support_igi = 3294 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 3295 } 3296 3297 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 3298 { 3299 int ret; 3300 3301 ret = rtw89_mac_partial_init(rtwdev); 3302 if (ret) 3303 return ret; 3304 3305 ret = rtw89_parse_efuse_map(rtwdev); 3306 if (ret) 3307 return ret; 3308 3309 ret = rtw89_parse_phycap_map(rtwdev); 3310 if (ret) 3311 return ret; 3312 3313 ret = rtw89_mac_setup_phycap(rtwdev); 3314 if (ret) 3315 return ret; 3316 3317 rtw89_core_setup_phycap(rtwdev); 3318 3319 rtw89_mac_pwr_off(rtwdev); 3320 3321 return 0; 3322 } 3323 3324 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 3325 { 3326 rtw89_chip_fem_setup(rtwdev); 3327 3328 return 0; 3329 } 3330 3331 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 3332 { 3333 int ret; 3334 3335 rtw89_read_chip_ver(rtwdev); 3336 3337 ret = rtw89_wait_firmware_completion(rtwdev); 3338 if (ret) { 3339 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 3340 return ret; 3341 } 3342 3343 ret = rtw89_fw_recognize(rtwdev); 3344 if (ret) { 3345 rtw89_err(rtwdev, "failed to recognize firmware\n"); 3346 return ret; 3347 } 3348 3349 ret = rtw89_chip_efuse_info_setup(rtwdev); 3350 if (ret) 3351 return ret; 3352 3353 ret = rtw89_chip_board_info_setup(rtwdev); 3354 if (ret) 3355 return ret; 3356 3357 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 3358 3359 return 0; 3360 } 3361 EXPORT_SYMBOL(rtw89_chip_info_setup); 3362 3363 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 3364 { 3365 struct ieee80211_hw *hw = rtwdev->hw; 3366 struct rtw89_efuse *efuse = &rtwdev->efuse; 3367 int ret; 3368 int tx_headroom = IEEE80211_HT_CTL_LEN; 3369 3370 hw->vif_data_size = sizeof(struct rtw89_vif); 3371 hw->sta_data_size = sizeof(struct rtw89_sta); 3372 hw->txq_data_size = sizeof(struct rtw89_txq); 3373 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 3374 3375 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 3376 3377 hw->extra_tx_headroom = tx_headroom; 3378 hw->queues = IEEE80211_NUM_ACS; 3379 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 3380 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 3381 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 3382 3383 ieee80211_hw_set(hw, SIGNAL_DBM); 3384 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 3385 ieee80211_hw_set(hw, MFP_CAPABLE); 3386 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 3387 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 3388 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 3389 ieee80211_hw_set(hw, TX_AMSDU); 3390 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 3391 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 3392 ieee80211_hw_set(hw, SUPPORTS_PS); 3393 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 3394 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 3395 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 3396 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 3397 3398 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 3399 BIT(NL80211_IFTYPE_AP) | 3400 BIT(NL80211_IFTYPE_P2P_CLIENT) | 3401 BIT(NL80211_IFTYPE_P2P_GO); 3402 3403 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 3404 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 3405 3406 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 3407 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 3408 WIPHY_FLAG_AP_UAPSD | WIPHY_FLAG_SPLIT_SCAN_6GHZ; 3409 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 3410 3411 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 3412 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 3413 3414 #ifdef CONFIG_PM 3415 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 3416 #endif 3417 3418 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3419 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 3420 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3421 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 3422 3423 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 3424 3425 ret = rtw89_core_set_supported_band(rtwdev); 3426 if (ret) { 3427 rtw89_err(rtwdev, "failed to set supported band\n"); 3428 return ret; 3429 } 3430 3431 hw->wiphy->reg_notifier = rtw89_regd_notifier; 3432 hw->wiphy->sar_capa = &rtw89_sar_capa; 3433 3434 ret = ieee80211_register_hw(hw); 3435 if (ret) { 3436 rtw89_err(rtwdev, "failed to register hw\n"); 3437 goto err; 3438 } 3439 3440 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 3441 if (ret) { 3442 rtw89_err(rtwdev, "failed to init regd\n"); 3443 goto err; 3444 } 3445 3446 return 0; 3447 3448 err: 3449 return ret; 3450 } 3451 3452 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 3453 { 3454 struct ieee80211_hw *hw = rtwdev->hw; 3455 3456 ieee80211_unregister_hw(hw); 3457 rtw89_core_clr_supported_band(rtwdev); 3458 } 3459 3460 int rtw89_core_register(struct rtw89_dev *rtwdev) 3461 { 3462 int ret; 3463 3464 ret = rtw89_core_register_hw(rtwdev); 3465 if (ret) { 3466 rtw89_err(rtwdev, "failed to register core hw\n"); 3467 return ret; 3468 } 3469 3470 rtw89_debugfs_init(rtwdev); 3471 3472 return 0; 3473 } 3474 EXPORT_SYMBOL(rtw89_core_register); 3475 3476 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 3477 { 3478 rtw89_core_unregister_hw(rtwdev); 3479 } 3480 EXPORT_SYMBOL(rtw89_core_unregister); 3481 3482 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 3483 u32 bus_data_size, 3484 const struct rtw89_chip_info *chip) 3485 { 3486 const struct firmware *firmware; 3487 struct ieee80211_hw *hw; 3488 struct rtw89_dev *rtwdev; 3489 struct ieee80211_ops *ops; 3490 u32 driver_data_size; 3491 u32 early_feat_map = 0; 3492 bool no_chanctx; 3493 3494 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_feat_map); 3495 3496 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 3497 if (!ops) 3498 goto err; 3499 3500 no_chanctx = chip->support_chanctx_num == 0 || 3501 !(early_feat_map & BIT(RTW89_FW_FEATURE_SCAN_OFFLOAD)); 3502 3503 if (no_chanctx) { 3504 ops->add_chanctx = NULL; 3505 ops->remove_chanctx = NULL; 3506 ops->change_chanctx = NULL; 3507 ops->assign_vif_chanctx = NULL; 3508 ops->unassign_vif_chanctx = NULL; 3509 } 3510 3511 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 3512 hw = ieee80211_alloc_hw(driver_data_size, ops); 3513 if (!hw) 3514 goto err; 3515 3516 rtwdev = hw->priv; 3517 rtwdev->hw = hw; 3518 rtwdev->dev = device; 3519 rtwdev->ops = ops; 3520 rtwdev->chip = chip; 3521 rtwdev->fw.firmware = firmware; 3522 3523 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 3524 no_chanctx ? "without" : "with"); 3525 3526 return rtwdev; 3527 3528 err: 3529 kfree(ops); 3530 release_firmware(firmware); 3531 return NULL; 3532 } 3533 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 3534 3535 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 3536 { 3537 kfree(rtwdev->ops); 3538 release_firmware(rtwdev->fw.firmware); 3539 ieee80211_free_hw(rtwdev->hw); 3540 } 3541 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 3542 3543 MODULE_AUTHOR("Realtek Corporation"); 3544 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 3545 MODULE_LICENSE("Dual BSD/GPL"); 3546