1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 #include "wow.h" 22 23 static bool rtw89_disable_ps_mode; 24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 26 27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 37 38 static struct ieee80211_channel rtw89_channels_2ghz[] = { 39 RTW89_DEF_CHAN_2G(2412, 1), 40 RTW89_DEF_CHAN_2G(2417, 2), 41 RTW89_DEF_CHAN_2G(2422, 3), 42 RTW89_DEF_CHAN_2G(2427, 4), 43 RTW89_DEF_CHAN_2G(2432, 5), 44 RTW89_DEF_CHAN_2G(2437, 6), 45 RTW89_DEF_CHAN_2G(2442, 7), 46 RTW89_DEF_CHAN_2G(2447, 8), 47 RTW89_DEF_CHAN_2G(2452, 9), 48 RTW89_DEF_CHAN_2G(2457, 10), 49 RTW89_DEF_CHAN_2G(2462, 11), 50 RTW89_DEF_CHAN_2G(2467, 12), 51 RTW89_DEF_CHAN_2G(2472, 13), 52 RTW89_DEF_CHAN_2G(2484, 14), 53 }; 54 55 static struct ieee80211_channel rtw89_channels_5ghz[] = { 56 RTW89_DEF_CHAN_5G(5180, 36), 57 RTW89_DEF_CHAN_5G(5200, 40), 58 RTW89_DEF_CHAN_5G(5220, 44), 59 RTW89_DEF_CHAN_5G(5240, 48), 60 RTW89_DEF_CHAN_5G(5260, 52), 61 RTW89_DEF_CHAN_5G(5280, 56), 62 RTW89_DEF_CHAN_5G(5300, 60), 63 RTW89_DEF_CHAN_5G(5320, 64), 64 RTW89_DEF_CHAN_5G(5500, 100), 65 RTW89_DEF_CHAN_5G(5520, 104), 66 RTW89_DEF_CHAN_5G(5540, 108), 67 RTW89_DEF_CHAN_5G(5560, 112), 68 RTW89_DEF_CHAN_5G(5580, 116), 69 RTW89_DEF_CHAN_5G(5600, 120), 70 RTW89_DEF_CHAN_5G(5620, 124), 71 RTW89_DEF_CHAN_5G(5640, 128), 72 RTW89_DEF_CHAN_5G(5660, 132), 73 RTW89_DEF_CHAN_5G(5680, 136), 74 RTW89_DEF_CHAN_5G(5700, 140), 75 RTW89_DEF_CHAN_5G(5720, 144), 76 RTW89_DEF_CHAN_5G(5745, 149), 77 RTW89_DEF_CHAN_5G(5765, 153), 78 RTW89_DEF_CHAN_5G(5785, 157), 79 RTW89_DEF_CHAN_5G(5805, 161), 80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 81 RTW89_DEF_CHAN_5G(5845, 169), 82 RTW89_DEF_CHAN_5G(5865, 173), 83 RTW89_DEF_CHAN_5G(5885, 177), 84 }; 85 86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 87 ARRAY_SIZE(rtw89_channels_5ghz)); 88 89 static struct ieee80211_channel rtw89_channels_6ghz[] = { 90 RTW89_DEF_CHAN_6G(5955, 1), 91 RTW89_DEF_CHAN_6G(5975, 5), 92 RTW89_DEF_CHAN_6G(5995, 9), 93 RTW89_DEF_CHAN_6G(6015, 13), 94 RTW89_DEF_CHAN_6G(6035, 17), 95 RTW89_DEF_CHAN_6G(6055, 21), 96 RTW89_DEF_CHAN_6G(6075, 25), 97 RTW89_DEF_CHAN_6G(6095, 29), 98 RTW89_DEF_CHAN_6G(6115, 33), 99 RTW89_DEF_CHAN_6G(6135, 37), 100 RTW89_DEF_CHAN_6G(6155, 41), 101 RTW89_DEF_CHAN_6G(6175, 45), 102 RTW89_DEF_CHAN_6G(6195, 49), 103 RTW89_DEF_CHAN_6G(6215, 53), 104 RTW89_DEF_CHAN_6G(6235, 57), 105 RTW89_DEF_CHAN_6G(6255, 61), 106 RTW89_DEF_CHAN_6G(6275, 65), 107 RTW89_DEF_CHAN_6G(6295, 69), 108 RTW89_DEF_CHAN_6G(6315, 73), 109 RTW89_DEF_CHAN_6G(6335, 77), 110 RTW89_DEF_CHAN_6G(6355, 81), 111 RTW89_DEF_CHAN_6G(6375, 85), 112 RTW89_DEF_CHAN_6G(6395, 89), 113 RTW89_DEF_CHAN_6G(6415, 93), 114 RTW89_DEF_CHAN_6G(6435, 97), 115 RTW89_DEF_CHAN_6G(6455, 101), 116 RTW89_DEF_CHAN_6G(6475, 105), 117 RTW89_DEF_CHAN_6G(6495, 109), 118 RTW89_DEF_CHAN_6G(6515, 113), 119 RTW89_DEF_CHAN_6G(6535, 117), 120 RTW89_DEF_CHAN_6G(6555, 121), 121 RTW89_DEF_CHAN_6G(6575, 125), 122 RTW89_DEF_CHAN_6G(6595, 129), 123 RTW89_DEF_CHAN_6G(6615, 133), 124 RTW89_DEF_CHAN_6G(6635, 137), 125 RTW89_DEF_CHAN_6G(6655, 141), 126 RTW89_DEF_CHAN_6G(6675, 145), 127 RTW89_DEF_CHAN_6G(6695, 149), 128 RTW89_DEF_CHAN_6G(6715, 153), 129 RTW89_DEF_CHAN_6G(6735, 157), 130 RTW89_DEF_CHAN_6G(6755, 161), 131 RTW89_DEF_CHAN_6G(6775, 165), 132 RTW89_DEF_CHAN_6G(6795, 169), 133 RTW89_DEF_CHAN_6G(6815, 173), 134 RTW89_DEF_CHAN_6G(6835, 177), 135 RTW89_DEF_CHAN_6G(6855, 181), 136 RTW89_DEF_CHAN_6G(6875, 185), 137 RTW89_DEF_CHAN_6G(6895, 189), 138 RTW89_DEF_CHAN_6G(6915, 193), 139 RTW89_DEF_CHAN_6G(6935, 197), 140 RTW89_DEF_CHAN_6G(6955, 201), 141 RTW89_DEF_CHAN_6G(6975, 205), 142 RTW89_DEF_CHAN_6G(6995, 209), 143 RTW89_DEF_CHAN_6G(7015, 213), 144 RTW89_DEF_CHAN_6G(7035, 217), 145 RTW89_DEF_CHAN_6G(7055, 221), 146 RTW89_DEF_CHAN_6G(7075, 225), 147 RTW89_DEF_CHAN_6G(7095, 229), 148 RTW89_DEF_CHAN_6G(7115, 233), 149 }; 150 151 static struct ieee80211_rate rtw89_bitrates[] = { 152 { .bitrate = 10, .hw_value = 0x00, }, 153 { .bitrate = 20, .hw_value = 0x01, }, 154 { .bitrate = 55, .hw_value = 0x02, }, 155 { .bitrate = 110, .hw_value = 0x03, }, 156 { .bitrate = 60, .hw_value = 0x04, }, 157 { .bitrate = 90, .hw_value = 0x05, }, 158 { .bitrate = 120, .hw_value = 0x06, }, 159 { .bitrate = 180, .hw_value = 0x07, }, 160 { .bitrate = 240, .hw_value = 0x08, }, 161 { .bitrate = 360, .hw_value = 0x09, }, 162 { .bitrate = 480, .hw_value = 0x0a, }, 163 { .bitrate = 540, .hw_value = 0x0b, }, 164 }; 165 166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_STATION), 170 }, 171 { 172 .max = 1, 173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 174 BIT(NL80211_IFTYPE_P2P_GO) | 175 BIT(NL80211_IFTYPE_AP), 176 }, 177 }; 178 179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_STATION), 183 }, 184 { 185 .max = 1, 186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 187 BIT(NL80211_IFTYPE_P2P_GO), 188 }, 189 }; 190 191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 192 { 193 .limits = rtw89_iface_limits, 194 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 195 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 196 .num_different_channels = 1, 197 }, 198 { 199 .limits = rtw89_iface_limits_mcc, 200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 201 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 202 .num_different_channels = 2, 203 }, 204 }; 205 206 static const u8 rtw89_ext_capa_sta[] = { 207 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING, 208 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT, 209 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF, 210 }; 211 212 static const struct wiphy_iftype_ext_capab rtw89_iftypes_ext_capa[] = { 213 { 214 .iftype = NL80211_IFTYPE_STATION, 215 .extended_capabilities = rtw89_ext_capa_sta, 216 .extended_capabilities_mask = rtw89_ext_capa_sta, 217 .extended_capabilities_len = sizeof(rtw89_ext_capa_sta), 218 /* relevant only if EHT is supported */ 219 .eml_capabilities = 0, 220 .mld_capa_and_ops = 0, 221 }, 222 }; 223 224 #define RTW89_6GHZ_SPAN_HEAD 6145 225 #define RTW89_6GHZ_SPAN_IDX(center_freq) \ 226 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2) 227 228 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \ 229 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \ 230 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \ 231 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \ 232 .acpi_sar_subband_low = RTW89_ACPI_SAR_6GHZ_ ## subband_l, \ 233 .acpi_sar_subband_high = RTW89_ACPI_SAR_6GHZ_ ## subband_h, \ 234 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \ 235 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \ 236 } 237 238 /* Since 6GHz subbands are not edge aligned, some cases span two subbands. 239 * In the following, we describe each of them with rtw89_6ghz_span. 240 */ 241 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = { 242 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H), 243 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H), 244 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H), 245 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L), 246 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L), 247 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L), 248 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H), 249 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H), 250 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8), 251 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8), 252 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8), 253 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8), 254 }; 255 256 const struct rtw89_6ghz_span * 257 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq) 258 { 259 int idx; 260 261 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) { 262 idx = RTW89_6GHZ_SPAN_IDX(center_freq); 263 /* To decrease size of rtw89_overlapping_6ghz[], 264 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs 265 * to make first span as index 0 of the table. So, if center 266 * frequency is less than the first one, it will get netative. 267 */ 268 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz)) 269 return &rtw89_overlapping_6ghz[idx]; 270 } 271 272 return NULL; 273 } 274 275 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 276 { 277 struct ieee80211_rate rate; 278 279 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 280 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 281 return false; 282 } 283 284 rate = rtw89_bitrates[rpt_rate]; 285 *bitrate = rate.bitrate; 286 287 return true; 288 } 289 290 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 291 .band = NL80211_BAND_2GHZ, 292 .channels = rtw89_channels_2ghz, 293 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 294 .bitrates = rtw89_bitrates, 295 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 296 .ht_cap = {0}, 297 .vht_cap = {0}, 298 }; 299 300 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 301 .band = NL80211_BAND_5GHZ, 302 .channels = rtw89_channels_5ghz, 303 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 304 305 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 306 .bitrates = rtw89_bitrates + 4, 307 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 308 .ht_cap = {0}, 309 .vht_cap = {0}, 310 }; 311 312 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 313 .band = NL80211_BAND_6GHZ, 314 .channels = rtw89_channels_6ghz, 315 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 316 317 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 318 .bitrates = rtw89_bitrates + 4, 319 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 320 }; 321 322 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 323 struct rtw89_traffic_stats *stats, 324 struct sk_buff *skb, bool tx) 325 { 326 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 327 328 if (tx && ieee80211_is_assoc_req(hdr->frame_control)) 329 rtw89_wow_parse_akm(rtwdev, skb); 330 331 if (!ieee80211_is_data(hdr->frame_control)) 332 return; 333 334 if (is_broadcast_ether_addr(hdr->addr1) || 335 is_multicast_ether_addr(hdr->addr1)) 336 return; 337 338 if (tx) { 339 stats->tx_cnt++; 340 stats->tx_unicast += skb->len; 341 } else { 342 stats->rx_cnt++; 343 stats->rx_unicast += skb->len; 344 } 345 } 346 347 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 348 { 349 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 350 NL80211_CHAN_NO_HT); 351 } 352 353 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 354 struct rtw89_chan *chan) 355 { 356 struct ieee80211_channel *channel = chandef->chan; 357 enum nl80211_chan_width width = chandef->width; 358 u32 primary_freq, center_freq; 359 u8 center_chan; 360 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 361 u32 offset; 362 u8 band; 363 364 center_chan = channel->hw_value; 365 primary_freq = channel->center_freq; 366 center_freq = chandef->center_freq1; 367 368 switch (width) { 369 case NL80211_CHAN_WIDTH_20_NOHT: 370 case NL80211_CHAN_WIDTH_20: 371 bandwidth = RTW89_CHANNEL_WIDTH_20; 372 break; 373 case NL80211_CHAN_WIDTH_40: 374 bandwidth = RTW89_CHANNEL_WIDTH_40; 375 if (primary_freq > center_freq) { 376 center_chan -= 2; 377 } else { 378 center_chan += 2; 379 } 380 break; 381 case NL80211_CHAN_WIDTH_80: 382 case NL80211_CHAN_WIDTH_160: 383 bandwidth = nl_to_rtw89_bandwidth(width); 384 if (primary_freq > center_freq) { 385 offset = (primary_freq - center_freq - 10) / 20; 386 center_chan -= 2 + offset * 4; 387 } else { 388 offset = (center_freq - primary_freq - 10) / 20; 389 center_chan += 2 + offset * 4; 390 } 391 break; 392 default: 393 center_chan = 0; 394 break; 395 } 396 397 switch (channel->band) { 398 default: 399 case NL80211_BAND_2GHZ: 400 band = RTW89_BAND_2G; 401 break; 402 case NL80211_BAND_5GHZ: 403 band = RTW89_BAND_5G; 404 break; 405 case NL80211_BAND_6GHZ: 406 band = RTW89_BAND_6G; 407 break; 408 } 409 410 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 411 } 412 413 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev, 414 const struct rtw89_chan *chan, 415 enum rtw89_phy_idx phy_idx) 416 { 417 const struct rtw89_chip_info *chip = rtwdev->chip; 418 bool entity_active; 419 420 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 421 if (!entity_active) 422 return; 423 424 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 425 } 426 427 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 428 { 429 const struct rtw89_chan *chan; 430 431 chan = rtw89_mgnt_chan_get(rtwdev, 0); 432 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0); 433 434 if (!rtwdev->support_mlo) 435 return; 436 437 chan = rtw89_mgnt_chan_get(rtwdev, 1); 438 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1); 439 } 440 441 static void __rtw89_set_channel(struct rtw89_dev *rtwdev, 442 const struct rtw89_chan *chan, 443 enum rtw89_mac_idx mac_idx, 444 enum rtw89_phy_idx phy_idx) 445 { 446 const struct rtw89_chip_info *chip = rtwdev->chip; 447 const struct rtw89_chan_rcd *chan_rcd; 448 struct rtw89_channel_help_params bak; 449 bool entity_active; 450 451 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 452 453 chan_rcd = rtw89_chan_rcd_get_by_chan(chan); 454 455 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 456 457 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 458 459 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 460 461 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 462 463 if (!entity_active || chan_rcd->band_changed) { 464 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 465 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan); 466 } 467 468 rtw89_set_entity_state(rtwdev, phy_idx, true); 469 } 470 471 int rtw89_set_channel(struct rtw89_dev *rtwdev) 472 { 473 const struct rtw89_chan *chan; 474 enum rtw89_entity_mode mode; 475 476 mode = rtw89_entity_recalc(rtwdev); 477 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) { 478 WARN(1, "Invalid ent mode: %d\n", mode); 479 return -EINVAL; 480 } 481 482 chan = rtw89_mgnt_chan_get(rtwdev, 0); 483 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0); 484 485 if (!rtwdev->support_mlo) 486 return 0; 487 488 chan = rtw89_mgnt_chan_get(rtwdev, 1); 489 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1); 490 491 return 0; 492 } 493 494 static enum rtw89_core_tx_type 495 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 496 struct sk_buff *skb) 497 { 498 struct ieee80211_hdr *hdr = (void *)skb->data; 499 __le16 fc = hdr->frame_control; 500 501 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 502 return RTW89_CORE_TX_TYPE_MGMT; 503 504 return RTW89_CORE_TX_TYPE_DATA; 505 } 506 507 static void 508 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 509 struct rtw89_core_tx_request *tx_req, 510 enum btc_pkt_type pkt_type) 511 { 512 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 513 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 514 struct ieee80211_link_sta *link_sta; 515 struct sk_buff *skb = tx_req->skb; 516 struct rtw89_sta *rtwsta; 517 u8 ampdu_num; 518 u8 tid; 519 520 if (pkt_type == PACKET_EAPOL) { 521 desc_info->bk = true; 522 return; 523 } 524 525 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 526 return; 527 528 if (!rtwsta_link) { 529 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 530 return; 531 } 532 533 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 534 rtwsta = rtwsta_link->rtwsta; 535 536 rcu_read_lock(); 537 538 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 539 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 540 rtwsta->ampdu_params[tid].agg_num : 541 4 << link_sta->ht_cap.ampdu_factor) - 1); 542 543 desc_info->agg_en = true; 544 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density; 545 desc_info->ampdu_num = ampdu_num; 546 547 rcu_read_unlock(); 548 } 549 550 static void 551 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 552 struct rtw89_core_tx_request *tx_req) 553 { 554 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 555 const struct rtw89_chip_info *chip = rtwdev->chip; 556 const struct rtw89_sec_cam_entry *sec_cam; 557 struct ieee80211_tx_info *info; 558 struct ieee80211_key_conf *key; 559 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 560 struct sk_buff *skb = tx_req->skb; 561 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 562 u8 sec_cam_idx; 563 u64 pn64; 564 565 info = IEEE80211_SKB_CB(skb); 566 key = info->control.hw_key; 567 sec_cam_idx = key->hw_key_idx; 568 sec_cam = cam_info->sec_entries[sec_cam_idx]; 569 if (!sec_cam) { 570 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 571 return; 572 } 573 574 switch (key->cipher) { 575 case WLAN_CIPHER_SUITE_WEP40: 576 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 577 break; 578 case WLAN_CIPHER_SUITE_WEP104: 579 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 580 break; 581 case WLAN_CIPHER_SUITE_TKIP: 582 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 583 break; 584 case WLAN_CIPHER_SUITE_CCMP: 585 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 586 break; 587 case WLAN_CIPHER_SUITE_CCMP_256: 588 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 589 break; 590 case WLAN_CIPHER_SUITE_GCMP: 591 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 592 break; 593 case WLAN_CIPHER_SUITE_GCMP_256: 594 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 595 break; 596 default: 597 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 598 return; 599 } 600 601 desc_info->sec_en = true; 602 desc_info->sec_keyid = key->keyidx; 603 desc_info->sec_type = sec_type; 604 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 605 606 if (!chip->hw_sec_hdr) 607 return; 608 609 pn64 = atomic64_inc_return(&key->tx_pn); 610 desc_info->sec_seq[0] = pn64; 611 desc_info->sec_seq[1] = pn64 >> 8; 612 desc_info->sec_seq[2] = pn64 >> 16; 613 desc_info->sec_seq[3] = pn64 >> 24; 614 desc_info->sec_seq[4] = pn64 >> 32; 615 desc_info->sec_seq[5] = pn64 >> 40; 616 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 617 } 618 619 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 620 struct rtw89_core_tx_request *tx_req, 621 const struct rtw89_chan *chan) 622 { 623 struct sk_buff *skb = tx_req->skb; 624 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 625 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 626 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 627 struct ieee80211_vif *vif = tx_info->control.vif; 628 struct ieee80211_bss_conf *bss_conf; 629 u16 lowest_rate; 630 u16 rate; 631 632 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 633 (vif && vif->p2p)) 634 lowest_rate = RTW89_HW_RATE_OFDM6; 635 else if (chan->band_type == RTW89_BAND_2G) 636 lowest_rate = RTW89_HW_RATE_CCK1; 637 else 638 lowest_rate = RTW89_HW_RATE_OFDM6; 639 640 if (!rtwvif_link) 641 return lowest_rate; 642 643 rcu_read_lock(); 644 645 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 646 if (!bss_conf->basic_rates || !rtwsta_link) { 647 rate = lowest_rate; 648 goto out; 649 } 650 651 rate = __ffs(bss_conf->basic_rates) + lowest_rate; 652 653 out: 654 rcu_read_unlock(); 655 656 return rate; 657 } 658 659 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 660 struct rtw89_core_tx_request *tx_req) 661 { 662 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 663 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 664 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 665 666 if (desc_info->mlo && !desc_info->sw_mld) { 667 if (rtwsta_link) 668 return rtw89_sta_get_main_macid(rtwsta_link->rtwsta); 669 else 670 return rtw89_vif_get_main_macid(rtwvif_link->rtwvif); 671 } 672 673 if (!rtwsta_link) 674 return rtwvif_link->mac_id; 675 676 return rtwsta_link->mac_id; 677 } 678 679 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 680 struct rtw89_tx_desc_info *desc_info, 681 struct sk_buff *skb) 682 { 683 struct ieee80211_hdr *hdr = (void *)skb->data; 684 __le16 fc = hdr->frame_control; 685 686 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 687 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 688 } 689 690 static void 691 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 692 struct rtw89_core_tx_request *tx_req) 693 { 694 const struct rtw89_chip_info *chip = rtwdev->chip; 695 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 696 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 697 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 698 rtwvif_link->chanctx_idx); 699 struct sk_buff *skb = tx_req->skb; 700 u8 qsel, ch_dma; 701 702 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req); 703 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 704 705 desc_info->qsel = qsel; 706 desc_info->ch_dma = ch_dma; 707 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 708 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 709 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 710 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 711 712 /* fixed data rate for mgmt frames */ 713 desc_info->en_wd_info = true; 714 desc_info->use_rate = true; 715 desc_info->dis_data_fb = true; 716 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 717 718 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) { 719 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 720 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 721 } 722 723 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 724 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 725 desc_info->data_rate, chan->channel, chan->band_type, 726 chan->band_width); 727 } 728 729 static void 730 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 731 struct rtw89_core_tx_request *tx_req) 732 { 733 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 734 735 desc_info->is_bmc = false; 736 desc_info->wd_page = false; 737 desc_info->ch_dma = RTW89_DMA_H2C; 738 } 739 740 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 741 const struct rtw89_chan *chan) 742 { 743 static const u8 rtw89_bandwidth_to_om[] = { 744 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 745 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 746 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 747 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 748 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 749 }; 750 const struct rtw89_chip_info *chip = rtwdev->chip; 751 struct rtw89_hal *hal = &rtwdev->hal; 752 u8 om_bandwidth; 753 754 if (!chip->dis_2g_40m_ul_ofdma || 755 chan->band_type != RTW89_BAND_2G || 756 chan->band_width != RTW89_CHANNEL_WIDTH_40) 757 return; 758 759 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 760 rtw89_bandwidth_to_om[chan->band_width] : 0; 761 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 762 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 763 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 764 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 765 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 766 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 767 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 768 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 769 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 770 } 771 772 static bool 773 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 774 struct rtw89_core_tx_request *tx_req, 775 enum btc_pkt_type pkt_type) 776 { 777 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 778 struct sk_buff *skb = tx_req->skb; 779 struct ieee80211_hdr *hdr = (void *)skb->data; 780 struct ieee80211_link_sta *link_sta; 781 __le16 fc = hdr->frame_control; 782 783 /* AP IOT issue with EAPoL, ARP and DHCP */ 784 if (pkt_type < PACKET_MAX) 785 return false; 786 787 if (!rtwsta_link) 788 return false; 789 790 rcu_read_lock(); 791 792 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 793 if (!link_sta->he_cap.has_he) { 794 rcu_read_unlock(); 795 return false; 796 } 797 798 rcu_read_unlock(); 799 800 if (!ieee80211_is_data_qos(fc)) 801 return false; 802 803 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 804 return false; 805 806 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy) 807 return false; 808 809 return true; 810 } 811 812 static void 813 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 814 struct rtw89_core_tx_request *tx_req) 815 { 816 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 817 struct sk_buff *skb = tx_req->skb; 818 struct ieee80211_hdr *hdr = (void *)skb->data; 819 __le16 fc = hdr->frame_control; 820 void *data; 821 __le32 *htc; 822 u8 *qc; 823 int hdr_len; 824 825 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 826 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 827 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 828 829 hdr = data; 830 htc = data + hdr_len; 831 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 832 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template : 833 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 834 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 835 836 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 837 qc[0] |= IEEE80211_QOS_CTL_EOSP; 838 } 839 840 static void 841 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 842 struct rtw89_core_tx_request *tx_req, 843 enum btc_pkt_type pkt_type) 844 { 845 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 846 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 847 848 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 849 goto desc_bk; 850 851 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 852 853 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 854 desc_info->a_ctrl_bsr = true; 855 856 desc_bk: 857 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr) 858 return; 859 860 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr; 861 desc_info->bk = true; 862 } 863 864 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 865 struct rtw89_core_tx_request *tx_req) 866 { 867 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 868 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 869 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 870 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 871 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx; 872 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 873 struct ieee80211_link_sta *link_sta; 874 u16 lowest_rate; 875 u16 rate; 876 877 if (rate_pattern->enable) 878 return rate_pattern->rate; 879 880 if (vif->p2p) 881 lowest_rate = RTW89_HW_RATE_OFDM6; 882 else if (chan->band_type == RTW89_BAND_2G) 883 lowest_rate = RTW89_HW_RATE_CCK1; 884 else 885 lowest_rate = RTW89_HW_RATE_OFDM6; 886 887 if (!rtwsta_link) 888 return lowest_rate; 889 890 rcu_read_lock(); 891 892 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 893 if (!link_sta->supp_rates[chan->band_type]) { 894 rate = lowest_rate; 895 goto out; 896 } 897 898 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate; 899 900 out: 901 rcu_read_unlock(); 902 903 return rate; 904 } 905 906 static void 907 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 908 struct rtw89_core_tx_request *tx_req) 909 { 910 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 911 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 912 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 913 struct sk_buff *skb = tx_req->skb; 914 u8 tid, tid_indicate; 915 u8 qsel, ch_dma; 916 917 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 918 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 919 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 920 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 921 922 desc_info->ch_dma = ch_dma; 923 desc_info->tid_indicate = tid_indicate; 924 desc_info->qsel = qsel; 925 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 926 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 927 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false; 928 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false; 929 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false; 930 931 /* enable wd_info for AMPDU */ 932 desc_info->en_wd_info = true; 933 934 if (IEEE80211_SKB_CB(skb)->control.hw_key) 935 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 936 937 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 938 } 939 940 static enum btc_pkt_type 941 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 942 struct rtw89_core_tx_request *tx_req) 943 { 944 struct wiphy *wiphy = rtwdev->hw->wiphy; 945 struct sk_buff *skb = tx_req->skb; 946 struct udphdr *udphdr; 947 948 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 949 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work); 950 return PACKET_EAPOL; 951 } 952 953 if (skb->protocol == htons(ETH_P_ARP)) { 954 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work); 955 return PACKET_ARP; 956 } 957 958 if (skb->protocol == htons(ETH_P_IP) && 959 ip_hdr(skb)->protocol == IPPROTO_UDP) { 960 udphdr = udp_hdr(skb); 961 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 962 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 963 skb->len > 282) { 964 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work); 965 return PACKET_DHCP; 966 } 967 } 968 969 if (skb->protocol == htons(ETH_P_IP) && 970 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 971 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work); 972 return PACKET_ICMP; 973 } 974 975 return PACKET_MAX; 976 } 977 978 static void 979 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 980 struct rtw89_core_tx_request *tx_req) 981 { 982 const struct rtw89_chip_info *chip = rtwdev->chip; 983 984 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 985 return; 986 987 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 988 return; 989 990 if (chip->chip_id != RTL8852C && 991 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 992 return; 993 994 rtw89_mac_notify_wake(rtwdev); 995 } 996 997 static void 998 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 999 struct rtw89_core_tx_request *tx_req) 1000 { 1001 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 1002 struct sk_buff *skb = tx_req->skb; 1003 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1004 struct ieee80211_hdr *hdr = (void *)skb->data; 1005 struct rtw89_addr_cam_entry *addr_cam; 1006 enum rtw89_core_tx_type tx_type; 1007 enum btc_pkt_type pkt_type; 1008 bool upd_wlan_hdr = false; 1009 bool is_bmc; 1010 u16 seq; 1011 1012 if (tx_req->sta) 1013 desc_info->mlo = tx_req->sta->mlo; 1014 else if (tx_req->vif) 1015 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif); 1016 1017 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 1018 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 1019 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 1020 tx_req->tx_type = tx_type; 1021 1022 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link, 1023 tx_req->rtwsta_link); 1024 if (addr_cam->valid && desc_info->mlo) 1025 upd_wlan_hdr = true; 1026 } 1027 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 1028 is_multicast_ether_addr(hdr->addr1)); 1029 1030 desc_info->seq = seq; 1031 desc_info->pkt_size = skb->len; 1032 desc_info->is_bmc = is_bmc; 1033 desc_info->wd_page = true; 1034 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 1035 desc_info->upd_wlan_hdr = upd_wlan_hdr; 1036 1037 switch (tx_req->tx_type) { 1038 case RTW89_CORE_TX_TYPE_MGMT: 1039 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 1040 break; 1041 case RTW89_CORE_TX_TYPE_DATA: 1042 rtw89_core_tx_update_data_info(rtwdev, tx_req); 1043 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 1044 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 1045 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 1046 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 1047 break; 1048 case RTW89_CORE_TX_TYPE_FWCMD: 1049 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 1050 break; 1051 } 1052 } 1053 1054 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 1055 { 1056 u8 ch_dma; 1057 1058 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 1059 1060 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 1061 } 1062 1063 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1064 int qsel, unsigned int timeout) 1065 { 1066 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1067 struct rtw89_tx_wait_info *wait; 1068 unsigned long time_left; 1069 int ret = 0; 1070 1071 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 1072 if (!wait) { 1073 rtw89_core_tx_kick_off(rtwdev, qsel); 1074 return 0; 1075 } 1076 1077 init_completion(&wait->completion); 1078 rcu_assign_pointer(skb_data->wait, wait); 1079 1080 rtw89_core_tx_kick_off(rtwdev, qsel); 1081 time_left = wait_for_completion_timeout(&wait->completion, 1082 msecs_to_jiffies(timeout)); 1083 if (time_left == 0) 1084 ret = -ETIMEDOUT; 1085 else if (!wait->tx_done) 1086 ret = -EAGAIN; 1087 1088 rcu_assign_pointer(skb_data->wait, NULL); 1089 kfree_rcu(wait, rcu_head); 1090 1091 return ret; 1092 } 1093 1094 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 1095 struct sk_buff *skb, bool fwdl) 1096 { 1097 struct rtw89_core_tx_request tx_req = {0}; 1098 u32 cnt; 1099 int ret; 1100 1101 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 1102 rtw89_debug(rtwdev, RTW89_DBG_FW, 1103 "ignore h2c due to power is off with firmware state=%d\n", 1104 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 1105 dev_kfree_skb(skb); 1106 return 0; 1107 } 1108 1109 tx_req.skb = skb; 1110 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1111 if (fwdl) 1112 tx_req.desc_info.fw_dl = true; 1113 1114 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1115 1116 if (!fwdl) 1117 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1118 1119 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1120 if (cnt == 0) { 1121 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1122 return -ENOSPC; 1123 } 1124 1125 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1126 if (ret) { 1127 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1128 return ret; 1129 } 1130 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1131 1132 return 0; 1133 } 1134 1135 static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev, 1136 struct rtw89_vif_link *rtwvif_link, 1137 struct rtw89_sta_link *rtwsta_link, 1138 struct sk_buff *skb, int *qsel, bool sw_mld) 1139 { 1140 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link); 1141 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 1142 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 1143 struct rtw89_core_tx_request tx_req = {}; 1144 int ret; 1145 1146 tx_req.skb = skb; 1147 tx_req.vif = vif; 1148 tx_req.sta = sta; 1149 tx_req.rtwvif_link = rtwvif_link; 1150 tx_req.rtwsta_link = rtwsta_link; 1151 tx_req.desc_info.sw_mld = sw_mld; 1152 1153 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1154 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1155 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1156 rtw89_core_tx_wake(rtwdev, &tx_req); 1157 1158 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1159 if (ret) { 1160 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1161 return ret; 1162 } 1163 1164 if (qsel) 1165 *qsel = tx_req.desc_info.qsel; 1166 1167 return 0; 1168 } 1169 1170 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1171 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1172 { 1173 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1174 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 1175 struct rtw89_sta_link *rtwsta_link = NULL; 1176 struct rtw89_vif_link *rtwvif_link; 1177 1178 if (rtwsta) { 1179 rtwsta_link = rtw89_get_designated_link(rtwsta); 1180 if (unlikely(!rtwsta_link)) { 1181 rtw89_err(rtwdev, "tx: find no sta designated link\n"); 1182 return -ENOLINK; 1183 } 1184 1185 rtwvif_link = rtwsta_link->rtwvif_link; 1186 } else { 1187 rtwvif_link = rtw89_get_designated_link(rtwvif); 1188 if (unlikely(!rtwvif_link)) { 1189 rtw89_err(rtwdev, "tx: find no vif designated link\n"); 1190 return -ENOLINK; 1191 } 1192 } 1193 1194 return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, false); 1195 } 1196 1197 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1198 { 1199 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1200 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1201 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1202 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1203 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1204 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1205 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1206 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1207 1208 return cpu_to_le32(dword); 1209 } 1210 1211 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1212 { 1213 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1214 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1215 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1216 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1217 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1218 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1219 1220 return cpu_to_le32(dword); 1221 } 1222 1223 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1224 { 1225 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1226 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1227 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1228 1229 return cpu_to_le32(dword); 1230 } 1231 1232 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1233 { 1234 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1235 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1236 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1237 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1238 1239 return cpu_to_le32(dword); 1240 } 1241 1242 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1243 { 1244 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1245 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1246 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1247 1248 return cpu_to_le32(dword); 1249 } 1250 1251 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1252 { 1253 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1254 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1255 1256 return cpu_to_le32(dword); 1257 } 1258 1259 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1260 { 1261 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1262 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1263 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1264 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1265 1266 return cpu_to_le32(dword); 1267 } 1268 1269 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1270 { 1271 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1272 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1273 1274 return cpu_to_le32(dword); 1275 } 1276 1277 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1278 { 1279 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1280 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1281 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1282 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1283 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1284 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1285 1286 return cpu_to_le32(dword); 1287 } 1288 1289 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1290 { 1291 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1292 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1293 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1294 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1295 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1296 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1297 1298 return cpu_to_le32(dword); 1299 } 1300 1301 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1302 { 1303 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1304 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1305 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1306 desc_info->data_retry_lowest_rate); 1307 1308 return cpu_to_le32(dword); 1309 } 1310 1311 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1312 { 1313 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1314 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1315 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1316 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1317 1318 return cpu_to_le32(dword); 1319 } 1320 1321 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1322 { 1323 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1324 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1325 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1326 1327 return cpu_to_le32(dword); 1328 } 1329 1330 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1331 { 1332 bool rts_en = !desc_info->is_bmc; 1333 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1334 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1335 1336 return cpu_to_le32(dword); 1337 } 1338 1339 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1340 struct rtw89_tx_desc_info *desc_info, 1341 void *txdesc) 1342 { 1343 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1344 struct rtw89_txwd_info *txwd_info; 1345 1346 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1347 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1348 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1349 1350 if (!desc_info->en_wd_info) 1351 return; 1352 1353 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1354 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1355 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1356 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1357 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1358 1359 } 1360 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1361 1362 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1363 struct rtw89_tx_desc_info *desc_info, 1364 void *txdesc) 1365 { 1366 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1367 struct rtw89_txwd_info *txwd_info; 1368 1369 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1370 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1371 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1372 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1373 if (desc_info->sec_en) { 1374 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1375 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1376 } 1377 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1378 1379 if (!desc_info->en_wd_info) 1380 return; 1381 1382 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1383 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1384 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1385 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1386 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1387 } 1388 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1389 1390 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1391 { 1392 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1393 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1394 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1395 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1396 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1397 1398 return cpu_to_le32(dword); 1399 } 1400 1401 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1402 { 1403 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1404 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1405 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1406 1407 return cpu_to_le32(dword); 1408 } 1409 1410 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1411 { 1412 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1413 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1414 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1415 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1416 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1417 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1418 1419 return cpu_to_le32(dword); 1420 } 1421 1422 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1423 { 1424 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) | 1425 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) | 1426 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld); 1427 1428 return cpu_to_le32(dword); 1429 } 1430 1431 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1432 { 1433 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1434 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1435 1436 return cpu_to_le32(dword); 1437 } 1438 1439 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1440 { 1441 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1442 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1443 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1444 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1445 1446 return cpu_to_le32(dword); 1447 } 1448 1449 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info) 1450 { 1451 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr); 1452 1453 return cpu_to_le32(dword); 1454 } 1455 1456 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1457 { 1458 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1459 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1460 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1461 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1462 1463 return cpu_to_le32(dword); 1464 } 1465 1466 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1467 { 1468 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1469 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1470 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1471 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1472 1473 return cpu_to_le32(dword); 1474 } 1475 1476 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1477 { 1478 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1479 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1480 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1481 desc_info->data_retry_lowest_rate); 1482 1483 return cpu_to_le32(dword); 1484 } 1485 1486 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1487 { 1488 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1489 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1490 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1491 1492 return cpu_to_le32(dword); 1493 } 1494 1495 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1496 { 1497 bool rts_en = !desc_info->is_bmc; 1498 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1499 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1500 1501 return cpu_to_le32(dword); 1502 } 1503 1504 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1505 struct rtw89_tx_desc_info *desc_info, 1506 void *txdesc) 1507 { 1508 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1509 struct rtw89_txwd_info_v2 *txwd_info; 1510 1511 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1512 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1513 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1514 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1515 if (desc_info->sec_en) { 1516 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1517 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1518 } 1519 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1520 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1521 1522 if (!desc_info->en_wd_info) 1523 return; 1524 1525 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1526 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1527 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1528 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1529 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1530 } 1531 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1532 1533 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1534 { 1535 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1536 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1537 RTW89_CORE_RX_TYPE_FWDL : 1538 RTW89_CORE_RX_TYPE_H2C); 1539 1540 return cpu_to_le32(dword); 1541 } 1542 1543 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1544 struct rtw89_tx_desc_info *desc_info, 1545 void *txdesc) 1546 { 1547 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1548 1549 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1550 } 1551 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1552 1553 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1554 { 1555 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1556 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1557 RTW89_CORE_RX_TYPE_FWDL : 1558 RTW89_CORE_RX_TYPE_H2C); 1559 1560 return cpu_to_le32(dword); 1561 } 1562 1563 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1564 struct rtw89_tx_desc_info *desc_info, 1565 void *txdesc) 1566 { 1567 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1568 1569 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1570 } 1571 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1572 1573 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1574 struct sk_buff *skb, 1575 struct rtw89_rx_phy_ppdu *phy_ppdu) 1576 { 1577 const struct rtw89_chip_info *chip = rtwdev->chip; 1578 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1579 const struct rtw89_rxinfo_user *user; 1580 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1581 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1582 bool rx_cnt_valid = false; 1583 bool invalid = false; 1584 u8 plcp_size = 0; 1585 u8 *phy_sts; 1586 u8 usr_num; 1587 int i; 1588 1589 if (chip_gen == RTW89_CHIP_BE) { 1590 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1591 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1592 } 1593 1594 if (invalid) 1595 return -EINVAL; 1596 1597 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1598 if (chip_gen == RTW89_CHIP_BE) { 1599 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1600 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1601 } else { 1602 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1603 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1604 } 1605 if (usr_num > chip->ppdu_max_usr) { 1606 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1607 usr_num); 1608 return -EINVAL; 1609 } 1610 1611 for (i = 0; i < usr_num; i++) { 1612 user = &rxinfo->user[i]; 1613 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1614 continue; 1615 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set 1616 * by hardware, so update mac_id by rxinfo_user[].mac_id. 1617 */ 1618 if (chip_gen == RTW89_CHIP_BE) 1619 phy_ppdu->mac_id = 1620 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1621 phy_ppdu->has_data = 1622 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA); 1623 phy_ppdu->has_bcn = 1624 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN); 1625 break; 1626 } 1627 1628 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1629 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1630 /* 8-byte alignment */ 1631 if (usr_num & BIT(0)) 1632 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1633 if (rx_cnt_valid) 1634 phy_sts += rx_cnt_size; 1635 phy_sts += plcp_size; 1636 1637 if (phy_sts > skb->data + skb->len) 1638 return -EINVAL; 1639 1640 phy_ppdu->buf = phy_sts; 1641 phy_ppdu->len = skb->data + skb->len - phy_sts; 1642 1643 return 0; 1644 } 1645 1646 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate) 1647 { 1648 u8 data_rate_mode; 1649 1650 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1651 switch (data_rate_mode) { 1652 case DATA_RATE_MODE_NON_HT: 1653 return 1; 1654 case DATA_RATE_MODE_HT: 1655 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1; 1656 case DATA_RATE_MODE_VHT: 1657 case DATA_RATE_MODE_HE: 1658 case DATA_RATE_MODE_EHT: 1659 return rtw89_get_data_nss(rtwdev, data_rate) + 1; 1660 default: 1661 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1662 return 0; 1663 } 1664 } 1665 1666 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1667 struct ieee80211_sta *sta) 1668 { 1669 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1670 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 1671 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1672 struct rtw89_hal *hal = &rtwdev->hal; 1673 struct rtw89_sta_link *rtwsta_link; 1674 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1675 u8 ant_pos = U8_MAX; 1676 u8 evm_pos = 0; 1677 int i; 1678 1679 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, phy_ppdu->phy_idx); 1680 if (unlikely(!rtwsta_link)) 1681 return; 1682 1683 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1684 return; 1685 1686 if (hal->ant_diversity && hal->antenna_rx) { 1687 ant_pos = __ffs(hal->antenna_rx); 1688 evm_pos = ant_pos; 1689 } 1690 1691 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg); 1692 1693 if (ant_pos < ant_num) { 1694 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]); 1695 } else { 1696 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1697 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]); 1698 } 1699 1700 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) { 1701 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr); 1702 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) { 1703 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min); 1704 } else { 1705 ewma_evm_add(&rtwsta_link->evm_min[evm_pos], 1706 phy_ppdu->ofdm.evm_min); 1707 ewma_evm_add(&rtwsta_link->evm_max[evm_pos], 1708 phy_ppdu->ofdm.evm_max); 1709 } 1710 } 1711 } 1712 1713 #define VAR_LEN 0xff 1714 #define VAR_LEN_UNIT 8 1715 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1716 const struct rtw89_phy_sts_iehdr *iehdr) 1717 { 1718 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1719 [RTW89_CHIP_AX] = { 1720 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1721 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1722 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1723 }, 1724 [RTW89_CHIP_BE] = { 1725 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1726 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 88, 56, VAR_LEN, 1727 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1728 }, 1729 }; 1730 const u8 *physts_ie_len_tab; 1731 u16 ie_len; 1732 u8 ie; 1733 1734 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1735 1736 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1737 if (physts_ie_len_tab[ie] != VAR_LEN) 1738 ie_len = physts_ie_len_tab[ie]; 1739 else 1740 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1741 1742 return ie_len; 1743 } 1744 1745 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev, 1746 const struct rtw89_phy_sts_iehdr *iehdr, 1747 struct rtw89_rx_phy_ppdu *phy_ppdu) 1748 { 1749 const struct rtw89_phy_sts_ie01_v2 *ie; 1750 u8 *rpl_fd = phy_ppdu->rpl_fd; 1751 1752 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr; 1753 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A); 1754 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B); 1755 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C); 1756 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D); 1757 1758 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX); 1759 } 1760 1761 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1762 const struct rtw89_phy_sts_iehdr *iehdr, 1763 struct rtw89_rx_phy_ppdu *phy_ppdu) 1764 { 1765 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr; 1766 s16 cfo; 1767 u32 t; 1768 1769 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1770 1771 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1772 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1773 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1774 } 1775 1776 if (!phy_ppdu->hdr_2_en) 1777 phy_ppdu->rx_path_en = 1778 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN); 1779 1780 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1781 return; 1782 1783 if (!phy_ppdu->to_self) 1784 return; 1785 1786 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD); 1787 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1788 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1789 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1790 phy_ppdu->ofdm.has = true; 1791 1792 /* sign conversion for S(12,2) */ 1793 if (rtwdev->chip->cfo_src_fd) { 1794 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1795 cfo = sign_extend32(t, 11); 1796 } else { 1797 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1798 cfo = sign_extend32(t, 11); 1799 } 1800 1801 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1802 1803 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1804 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu); 1805 } 1806 1807 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev, 1808 const struct rtw89_phy_sts_iehdr *iehdr, 1809 struct rtw89_rx_phy_ppdu *phy_ppdu) 1810 { 1811 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr; 1812 u16 tmp_rpl; 1813 1814 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL); 1815 phy_ppdu->rpl_avg = tmp_rpl >> 1; 1816 } 1817 1818 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev, 1819 const struct rtw89_phy_sts_iehdr *iehdr, 1820 struct rtw89_rx_phy_ppdu *phy_ppdu) 1821 { 1822 const struct rtw89_phy_sts_ie00_v2 *ie; 1823 u8 *rpl_path = phy_ppdu->rpl_path; 1824 u16 tmp_rpl[RF_PATH_MAX]; 1825 u8 i; 1826 1827 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr; 1828 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A); 1829 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B); 1830 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C); 1831 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D); 1832 1833 for (i = 0; i < RF_PATH_MAX; i++) 1834 rpl_path[i] = tmp_rpl[i] >> 1; 1835 } 1836 1837 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1838 const struct rtw89_phy_sts_iehdr *iehdr, 1839 struct rtw89_rx_phy_ppdu *phy_ppdu) 1840 { 1841 u8 ie; 1842 1843 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1844 1845 switch (ie) { 1846 case RTW89_PHYSTS_IE00_CMN_CCK: 1847 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu); 1848 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1849 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu); 1850 break; 1851 case RTW89_PHYSTS_IE01_CMN_OFDM: 1852 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1853 break; 1854 default: 1855 break; 1856 } 1857 1858 return 0; 1859 } 1860 1861 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu) 1862 { 1863 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN; 1864 1865 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN); 1866 } 1867 1868 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1869 { 1870 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1871 u8 *rssi = phy_ppdu->rssi; 1872 1873 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1874 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1875 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1876 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1877 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1878 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1879 1880 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN); 1881 if (phy_ppdu->hdr_2_en) 1882 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu); 1883 } 1884 1885 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1886 struct rtw89_rx_phy_ppdu *phy_ppdu) 1887 { 1888 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1889 u32 len_from_header; 1890 bool physts_valid; 1891 1892 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1893 if (!physts_valid) 1894 return -EINVAL; 1895 1896 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1897 1898 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1899 len_from_header += PHY_STS_HDR_LEN; 1900 1901 if (len_from_header != phy_ppdu->len) { 1902 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1903 return -EINVAL; 1904 } 1905 rtw89_core_update_phy_ppdu(phy_ppdu); 1906 1907 return 0; 1908 } 1909 1910 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1911 struct rtw89_rx_phy_ppdu *phy_ppdu) 1912 { 1913 u16 ie_len; 1914 void *pos, *end; 1915 1916 /* mark invalid reports and bypass them */ 1917 if (phy_ppdu->ie < RTW89_CCK_PKT) 1918 return -EINVAL; 1919 1920 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1921 if (phy_ppdu->hdr_2_en) 1922 pos += PHY_STS_HDR_LEN; 1923 end = phy_ppdu->buf + phy_ppdu->len; 1924 while (pos < end) { 1925 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1926 1927 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1928 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1929 pos += ie_len; 1930 if (pos > end || ie_len == 0) { 1931 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1932 "phy status parse failed\n"); 1933 return -EINVAL; 1934 } 1935 } 1936 1937 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu); 1938 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1939 1940 return 0; 1941 } 1942 1943 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1944 struct rtw89_rx_phy_ppdu *phy_ppdu) 1945 { 1946 int ret; 1947 1948 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1949 if (ret) 1950 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1951 else 1952 phy_ppdu->valid = true; 1953 1954 ieee80211_iterate_stations_atomic(rtwdev->hw, 1955 rtw89_core_rx_process_phy_ppdu_iter, 1956 phy_ppdu); 1957 } 1958 1959 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1960 u8 desc_info_gi, 1961 bool rx_status) 1962 { 1963 switch (desc_info_gi) { 1964 case RTW89_GILTF_SGI_4XHE08: 1965 case RTW89_GILTF_2XHE08: 1966 case RTW89_GILTF_1XHE08: 1967 return NL80211_RATE_INFO_HE_GI_0_8; 1968 case RTW89_GILTF_2XHE16: 1969 case RTW89_GILTF_1XHE16: 1970 return NL80211_RATE_INFO_HE_GI_1_6; 1971 case RTW89_GILTF_LGI_4XHE32: 1972 return NL80211_RATE_INFO_HE_GI_3_2; 1973 default: 1974 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1975 if (rx_status) 1976 return NL80211_RATE_INFO_HE_GI_3_2; 1977 return U8_MAX; 1978 } 1979 } 1980 1981 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev, 1982 u8 desc_info_gi, 1983 bool rx_status) 1984 { 1985 switch (desc_info_gi) { 1986 case RTW89_GILTF_SGI_4XHE08: 1987 case RTW89_GILTF_2XHE08: 1988 case RTW89_GILTF_1XHE08: 1989 return NL80211_RATE_INFO_EHT_GI_0_8; 1990 case RTW89_GILTF_2XHE16: 1991 case RTW89_GILTF_1XHE16: 1992 return NL80211_RATE_INFO_EHT_GI_1_6; 1993 case RTW89_GILTF_LGI_4XHE32: 1994 return NL80211_RATE_INFO_EHT_GI_3_2; 1995 default: 1996 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1997 if (rx_status) 1998 return NL80211_RATE_INFO_EHT_GI_3_2; 1999 return U8_MAX; 2000 } 2001 } 2002 2003 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 2004 u8 desc_info_gi, 2005 bool rx_status, bool eht) 2006 { 2007 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) : 2008 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status); 2009 } 2010 2011 static 2012 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 2013 bool eht) 2014 { 2015 if (eht) 2016 return status->eht.gi == gi_ltf; 2017 2018 return status->he_gi == gi_ltf; 2019 } 2020 2021 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 2022 struct rtw89_rx_desc_info *desc_info, 2023 struct ieee80211_rx_status *status) 2024 { 2025 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2026 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 2027 bool eht = false; 2028 u16 data_rate; 2029 bool ret; 2030 2031 data_rate = desc_info->data_rate; 2032 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2033 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2034 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2035 /* rate_idx is still hardware value here */ 2036 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2037 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2038 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 2039 data_rate_mode == DATA_RATE_MODE_HE || 2040 data_rate_mode == DATA_RATE_MODE_EHT) { 2041 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2042 } else { 2043 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2044 } 2045 2046 eht = data_rate_mode == DATA_RATE_MODE_EHT; 2047 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2048 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 2049 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 2050 status->rate_idx == rate_idx && 2051 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 2052 status->bw == bw; 2053 2054 return ret; 2055 } 2056 2057 struct rtw89_vif_rx_stats_iter_data { 2058 struct rtw89_dev *rtwdev; 2059 struct rtw89_rx_phy_ppdu *phy_ppdu; 2060 struct rtw89_rx_desc_info *desc_info; 2061 struct sk_buff *skb; 2062 const u8 *bssid; 2063 }; 2064 2065 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 2066 struct rtw89_vif_link *rtwvif_link, 2067 struct ieee80211_bss_conf *bss_conf, 2068 struct sk_buff *skb) 2069 { 2070 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 2071 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 2072 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 2073 u8 *pos, *end, type, tf_bw; 2074 u16 aid, tf_rua; 2075 2076 if (!ether_addr_equal(bss_conf->bssid, tf->ta) || 2077 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION || 2078 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK) 2079 return; 2080 2081 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 2082 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 2083 return; 2084 2085 end = (u8 *)tf + skb->len; 2086 pos = tf->variable; 2087 2088 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 2089 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 2090 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 2091 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 2092 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2093 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 2094 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 2095 tf_rua, tf_bw); 2096 2097 if (aid == RTW89_TF_PAD) 2098 break; 2099 2100 if (aid == vif->cfg.aid) { 2101 enum nl80211_he_ru_alloc rua; 2102 2103 rtwvif->stats.rx_tf_acc++; 2104 rtwdev->stats.rx_tf_acc++; 2105 2106 /* The following only required for HE trigger frame, but we 2107 * cannot use UL HE-SIG-A2 reserved subfield to identify it 2108 * since some 11ax APs will fill it with all 0s, which will 2109 * be misunderstood as EHT trigger frame. 2110 */ 2111 if (bss_conf->eht_support) 2112 break; 2113 2114 rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 2115 2116 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 2117 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 2118 rtwvif_link->pwr_diff_en = true; 2119 break; 2120 } 2121 2122 pos += RTW89_TF_BASIC_USER_INFO_SZ; 2123 } 2124 } 2125 2126 static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work) 2127 { 2128 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2129 cancel_6ghz_probe_work); 2130 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2131 struct rtw89_pktofld_info *info; 2132 2133 lockdep_assert_wiphy(wiphy); 2134 2135 if (!rtwdev->scanning) 2136 return; 2137 2138 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2139 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 2140 continue; 2141 2142 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 2143 2144 /* Don't delete/free info from pkt_list at this moment. Let it 2145 * be deleted/freed in rtw89_release_pkt_list() after scanning, 2146 * since if during scanning, pkt_list is accessed in bottom half. 2147 */ 2148 } 2149 } 2150 2151 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 2152 struct sk_buff *skb) 2153 { 2154 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2155 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2156 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2157 struct rtw89_pktofld_info *info; 2158 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 2159 bool queue_work = false; 2160 2161 if (rx_status->band != NL80211_BAND_6GHZ) 2162 return; 2163 2164 if (unlikely(!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))) { 2165 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rx on unsupported 6 GHz\n"); 2166 return; 2167 } 2168 2169 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 2170 2171 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2172 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 2173 info->cancel = true; 2174 queue_work = true; 2175 continue; 2176 } 2177 2178 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 2179 continue; 2180 2181 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 2182 info->cancel = true; 2183 queue_work = true; 2184 } 2185 } 2186 2187 if (queue_work) 2188 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work); 2189 } 2190 2191 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link, 2192 struct ieee80211_hdr *hdr, size_t len) 2193 { 2194 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 2195 2196 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 2197 return; 2198 2199 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 2200 } 2201 2202 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 2203 struct ieee80211_vif *vif) 2204 { 2205 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 2206 struct rtw89_dev *rtwdev = iter_data->rtwdev; 2207 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 2208 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2209 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2210 struct sk_buff *skb = iter_data->skb; 2211 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2212 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2213 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 2214 bool is_mld = ieee80211_vif_is_mld(vif); 2215 struct ieee80211_bss_conf *bss_conf; 2216 struct rtw89_vif_link *rtwvif_link; 2217 const u8 *bssid = iter_data->bssid; 2218 2219 if (rtwdev->scanning && 2220 (ieee80211_is_beacon(hdr->frame_control) || 2221 ieee80211_is_probe_resp(hdr->frame_control))) 2222 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 2223 2224 rcu_read_lock(); 2225 2226 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, desc_info->bb_sel); 2227 if (unlikely(!rtwvif_link)) 2228 goto out; 2229 2230 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 2231 if (!bss_conf->bssid) 2232 goto out; 2233 2234 if (ieee80211_is_trigger(hdr->frame_control)) { 2235 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb); 2236 goto out; 2237 } 2238 2239 if (!ether_addr_equal(bss_conf->bssid, bssid)) 2240 goto out; 2241 2242 if (is_mld) { 2243 rx_status->link_valid = true; 2244 rx_status->link_id = rtwvif_link->link_id; 2245 } 2246 2247 if (ieee80211_is_beacon(hdr->frame_control)) { 2248 if (vif->type == NL80211_IFTYPE_STATION && 2249 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 2250 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len); 2251 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 2252 } 2253 pkt_stat->beacon_nr++; 2254 2255 if (phy_ppdu) { 2256 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg); 2257 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 2258 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx; 2259 } 2260 2261 pkt_stat->beacon_rate = desc_info->data_rate; 2262 } 2263 2264 if (!ether_addr_equal(bss_conf->addr, hdr->addr1)) 2265 goto out; 2266 2267 if (desc_info->data_rate < RTW89_HW_RATE_NR) 2268 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 2269 2270 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 2271 2272 out: 2273 rcu_read_unlock(); 2274 } 2275 2276 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 2277 struct rtw89_rx_phy_ppdu *phy_ppdu, 2278 struct rtw89_rx_desc_info *desc_info, 2279 struct sk_buff *skb) 2280 { 2281 struct rtw89_vif_rx_stats_iter_data iter_data; 2282 2283 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 2284 2285 iter_data.rtwdev = rtwdev; 2286 iter_data.phy_ppdu = phy_ppdu; 2287 iter_data.desc_info = desc_info; 2288 iter_data.skb = skb; 2289 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 2290 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 2291 } 2292 2293 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 2294 struct ieee80211_rx_status *status) 2295 { 2296 const struct rtw89_chan_rcd *rcd = 2297 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0); 2298 u16 chan = rcd->prev_primary_channel; 2299 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 2300 2301 if (status->band != NL80211_BAND_2GHZ && 2302 status->encoding == RX_ENC_LEGACY && 2303 status->rate_idx < RTW89_HW_RATE_OFDM6) { 2304 status->freq = ieee80211_channel_to_frequency(chan, band); 2305 status->band = band; 2306 } 2307 } 2308 2309 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 2310 { 2311 if (rx_status->band == NL80211_BAND_2GHZ || 2312 rx_status->encoding != RX_ENC_LEGACY) 2313 return; 2314 2315 /* Some control frames' freq(ACKs in this case) are reported wrong due 2316 * to FW notify timing, set to lowest rate to prevent overflow. 2317 */ 2318 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 2319 rx_status->rate_idx = 0; 2320 return; 2321 } 2322 2323 /* No 4 CCK rates for non-2G */ 2324 rx_status->rate_idx -= 4; 2325 } 2326 2327 static 2328 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 2329 struct ieee80211_rx_status *rx_status, 2330 struct rtw89_rx_phy_ppdu *phy_ppdu) 2331 { 2332 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2333 return; 2334 2335 if (!phy_ppdu) 2336 return; 2337 2338 if (phy_ppdu->ldpc) 2339 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2340 if (phy_ppdu->stbc) 2341 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 2342 } 2343 2344 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 2345 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 2346 [RATE_INFO_BW_5] = U8_MAX, 2347 [RATE_INFO_BW_10] = U8_MAX, 2348 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 2349 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 2350 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 2351 [RATE_INFO_BW_HE_RU] = U8_MAX, 2352 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 2353 [RATE_INFO_BW_EHT_RU] = U8_MAX, 2354 }; 2355 2356 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2357 struct sk_buff *skb, 2358 struct ieee80211_rx_status *rx_status) 2359 { 2360 struct ieee80211_radiotap_eht_usig *usig; 2361 struct ieee80211_radiotap_eht *eht; 2362 struct ieee80211_radiotap_tlv *tlv; 2363 int eht_len = struct_size(eht, user_info, 1); 2364 int usig_len = sizeof(*usig); 2365 int len; 2366 u8 bw; 2367 2368 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2369 sizeof(*tlv) + ALIGN(usig_len, 4); 2370 2371 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2372 skb_reset_mac_header(skb); 2373 2374 /* EHT */ 2375 tlv = skb_push(skb, len); 2376 memset(tlv, 0, len); 2377 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2378 tlv->len = cpu_to_le16(eht_len); 2379 2380 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2381 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2382 eht->data[0] = 2383 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2384 2385 eht->user_info[0] = 2386 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2387 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 2388 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 2389 eht->user_info[0] |= 2390 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2391 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2392 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 2393 eht->user_info[0] |= 2394 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 2395 2396 /* U-SIG */ 2397 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2398 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2399 tlv->len = cpu_to_le16(usig_len); 2400 2401 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2402 return; 2403 2404 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2405 if (bw == U8_MAX) 2406 return; 2407 2408 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2409 usig->common = 2410 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2411 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2412 } 2413 2414 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2415 struct sk_buff *skb, 2416 struct ieee80211_rx_status *rx_status) 2417 { 2418 static const struct ieee80211_radiotap_he known_he = { 2419 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2420 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 2421 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 2422 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2423 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2424 }; 2425 struct ieee80211_radiotap_he *he; 2426 2427 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2428 return; 2429 2430 if (rx_status->encoding == RX_ENC_HE) { 2431 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2432 he = skb_push(skb, sizeof(*he)); 2433 *he = known_he; 2434 } else if (rx_status->encoding == RX_ENC_EHT) { 2435 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2436 } 2437 } 2438 2439 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status) 2440 { 2441 if (!rx_status->signal) 2442 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2443 } 2444 2445 static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev, 2446 struct sk_buff *skb, 2447 struct ieee80211_rx_status *rx_status) 2448 { 2449 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2450 size_t hdr_len, ielen; 2451 u8 *variable; 2452 int chan; 2453 2454 if (!rtwdev->chip->rx_freq_frome_ie) 2455 return; 2456 2457 if (!rtwdev->scanning) 2458 return; 2459 2460 if (ieee80211_is_beacon(mgmt->frame_control)) { 2461 variable = mgmt->u.beacon.variable; 2462 hdr_len = offsetof(struct ieee80211_mgmt, 2463 u.beacon.variable); 2464 } else if (ieee80211_is_probe_resp(mgmt->frame_control)) { 2465 variable = mgmt->u.probe_resp.variable; 2466 hdr_len = offsetof(struct ieee80211_mgmt, 2467 u.probe_resp.variable); 2468 } else { 2469 return; 2470 } 2471 2472 if (skb->len > hdr_len) 2473 ielen = skb->len - hdr_len; 2474 else 2475 return; 2476 2477 /* The parsing code for both 2GHz and 5GHz bands is the same in this 2478 * function. 2479 */ 2480 chan = cfg80211_get_ies_channel_number(variable, ielen, NL80211_BAND_2GHZ); 2481 if (chan == -1) 2482 return; 2483 2484 rx_status->band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 2485 rx_status->freq = ieee80211_channel_to_frequency(chan, rx_status->band); 2486 } 2487 2488 static void rtw89_core_correct_mcc_chan(struct rtw89_dev *rtwdev, 2489 struct rtw89_rx_desc_info *desc_info, 2490 struct ieee80211_rx_status *rx_status, 2491 struct rtw89_rx_phy_ppdu *phy_ppdu) 2492 { 2493 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 2494 struct rtw89_vif_link *rtwvif_link; 2495 struct rtw89_sta_link *rtwsta_link; 2496 const struct rtw89_chan *chan; 2497 u8 mac_id = desc_info->mac_id; 2498 enum rtw89_entity_mode mode; 2499 enum nl80211_band band; 2500 2501 mode = rtw89_get_entity_mode(rtwdev); 2502 if (likely(mode != RTW89_ENTITY_MODE_MCC)) 2503 return; 2504 2505 if (chip_gen == RTW89_CHIP_BE && phy_ppdu) 2506 mac_id = phy_ppdu->mac_id; 2507 2508 rcu_read_lock(); 2509 2510 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, mac_id); 2511 if (!rtwsta_link) 2512 goto out; 2513 2514 rtwvif_link = rtwsta_link->rtwvif_link; 2515 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 2516 band = rtw89_hw_to_nl80211_band(chan->band_type); 2517 rx_status->freq = ieee80211_channel_to_frequency(chan->primary_channel, band); 2518 2519 out: 2520 rcu_read_unlock(); 2521 } 2522 2523 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2524 struct rtw89_rx_phy_ppdu *phy_ppdu, 2525 struct rtw89_rx_desc_info *desc_info, 2526 struct sk_buff *skb_ppdu, 2527 struct ieee80211_rx_status *rx_status) 2528 { 2529 struct napi_struct *napi = &rtwdev->napi; 2530 2531 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2532 if (unlikely(!napi_is_scheduled(napi))) 2533 napi = NULL; 2534 2535 rtw89_core_hw_to_sband_rate(rx_status); 2536 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2537 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 2538 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2539 rtw89_core_validate_rx_signal(rx_status); 2540 rtw89_core_update_rx_freq_from_ie(rtwdev, skb_ppdu, rx_status); 2541 rtw89_core_correct_mcc_chan(rtwdev, desc_info, rx_status, phy_ppdu); 2542 2543 /* In low power mode, it does RX in thread context. */ 2544 local_bh_disable(); 2545 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2546 local_bh_enable(); 2547 rtwdev->napi_budget_countdown--; 2548 } 2549 2550 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2551 struct rtw89_rx_phy_ppdu *phy_ppdu, 2552 struct rtw89_rx_desc_info *desc_info, 2553 struct sk_buff *skb) 2554 { 2555 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2556 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2557 struct sk_buff *skb_ppdu = NULL, *tmp; 2558 struct ieee80211_rx_status *rx_status; 2559 2560 if (curr > RTW89_MAX_PPDU_CNT) 2561 return; 2562 2563 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2564 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2565 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2566 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2567 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2568 rtw89_correct_cck_chan(rtwdev, rx_status); 2569 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2570 } 2571 } 2572 2573 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2574 struct rtw89_rx_desc_info *desc_info, 2575 struct sk_buff *skb) 2576 { 2577 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2578 .len = skb->len, 2579 .to_self = desc_info->addr1_match, 2580 .rate = desc_info->data_rate, 2581 .mac_id = desc_info->mac_id, 2582 .phy_idx = desc_info->bb_sel}; 2583 int ret; 2584 2585 if (desc_info->mac_info_valid) { 2586 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2587 if (ret) 2588 goto out; 2589 } 2590 2591 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2592 if (ret) 2593 goto out; 2594 2595 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2596 2597 out: 2598 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2599 dev_kfree_skb_any(skb); 2600 } 2601 2602 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2603 struct rtw89_rx_desc_info *desc_info, 2604 struct sk_buff *skb) 2605 { 2606 switch (desc_info->pkt_type) { 2607 case RTW89_CORE_RX_TYPE_C2H: 2608 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2609 break; 2610 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2611 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2612 break; 2613 default: 2614 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2615 desc_info->pkt_type); 2616 dev_kfree_skb_any(skb); 2617 break; 2618 } 2619 } 2620 2621 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2622 struct rtw89_rx_desc_info *desc_info, 2623 u8 *data, u32 data_offset) 2624 { 2625 const struct rtw89_chip_info *chip = rtwdev->chip; 2626 struct rtw89_rxdesc_short *rxd_s; 2627 struct rtw89_rxdesc_long *rxd_l; 2628 u8 shift_len, drv_info_len; 2629 2630 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2631 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2632 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2633 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2634 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2635 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2636 if (chip->chip_id == RTL8852C) 2637 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2638 else 2639 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2640 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2641 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2642 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2643 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2644 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2645 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2646 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2647 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2648 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2649 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2650 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2651 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2652 2653 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2654 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2655 desc_info->offset = data_offset + shift_len + drv_info_len; 2656 if (desc_info->long_rxdesc) 2657 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2658 else 2659 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2660 desc_info->ready = true; 2661 2662 if (!desc_info->long_rxdesc) 2663 return; 2664 2665 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2666 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2667 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2668 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2669 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2670 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2671 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2672 } 2673 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2674 2675 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2676 struct rtw89_rx_desc_info *desc_info, 2677 u8 *data, u32 data_offset) 2678 { 2679 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 2680 struct rtw89_rxdesc_short_v2 *rxd_s; 2681 struct rtw89_rxdesc_long_v2 *rxd_l; 2682 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2683 2684 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2685 2686 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2687 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2688 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2689 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2690 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2691 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2692 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2693 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL); 2694 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2695 desc_info->mac_info_valid = true; 2696 2697 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2698 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2699 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2700 2701 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2702 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2703 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2704 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2705 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2706 2707 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2708 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2709 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2710 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2711 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2712 2713 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2714 2715 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2716 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2717 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2718 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2719 desc_info->offset = data_offset + shift_len + drv_info_len + 2720 phy_rtp_len + hdr_cnv_len; 2721 2722 if (desc_info->long_rxdesc) 2723 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2724 else 2725 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2726 desc_info->ready = true; 2727 2728 if (phy_rtp_len == sizeof(*rxd_rpt)) { 2729 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 2730 desc_info->rxd_len); 2731 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 2732 } 2733 2734 if (!desc_info->long_rxdesc) 2735 return; 2736 2737 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2738 2739 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2740 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2741 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2742 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2743 2744 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2745 } 2746 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2747 2748 struct rtw89_core_iter_rx_status { 2749 struct rtw89_dev *rtwdev; 2750 struct ieee80211_rx_status *rx_status; 2751 struct rtw89_rx_desc_info *desc_info; 2752 u8 mac_id; 2753 }; 2754 2755 static 2756 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2757 { 2758 struct rtw89_core_iter_rx_status *iter_data = 2759 (struct rtw89_core_iter_rx_status *)data; 2760 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2761 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2762 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 2763 struct rtw89_sta_link *rtwsta_link; 2764 u8 mac_id = iter_data->mac_id; 2765 2766 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, desc_info->bb_sel); 2767 if (unlikely(!rtwsta_link)) 2768 return; 2769 2770 if (mac_id != rtwsta_link->mac_id) 2771 return; 2772 2773 rtwsta_link->rx_status = *rx_status; 2774 rtwsta_link->rx_hw_rate = desc_info->data_rate; 2775 } 2776 2777 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2778 struct rtw89_rx_desc_info *desc_info, 2779 struct ieee80211_rx_status *rx_status) 2780 { 2781 struct rtw89_core_iter_rx_status iter_data; 2782 2783 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2784 return; 2785 2786 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2787 return; 2788 2789 iter_data.rtwdev = rtwdev; 2790 iter_data.rx_status = rx_status; 2791 iter_data.desc_info = desc_info; 2792 iter_data.mac_id = desc_info->mac_id; 2793 ieee80211_iterate_stations_atomic(rtwdev->hw, 2794 rtw89_core_stats_sta_rx_status_iter, 2795 &iter_data); 2796 } 2797 2798 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2799 struct sk_buff *skb, 2800 struct rtw89_rx_desc_info *desc_info, 2801 struct ieee80211_rx_status *rx_status) 2802 { 2803 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2804 const struct cfg80211_chan_def *chandef = 2805 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0); 2806 u16 data_rate; 2807 u8 data_rate_mode; 2808 bool eht = false; 2809 u8 gi; 2810 2811 /* currently using single PHY */ 2812 rx_status->freq = chandef->chan->center_freq; 2813 rx_status->band = chandef->chan->band; 2814 2815 if (ieee80211_is_beacon(hdr->frame_control) || 2816 ieee80211_is_probe_resp(hdr->frame_control)) 2817 rx_status->boottime_ns = ktime_get_boottime_ns(); 2818 2819 if (rtwdev->scanning && 2820 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2821 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2822 u8 chan = cur->primary_channel; 2823 u8 band = cur->band_type; 2824 enum nl80211_band nl_band; 2825 2826 nl_band = rtw89_hw_to_nl80211_band(band); 2827 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2828 rx_status->band = nl_band; 2829 } 2830 2831 if (desc_info->icv_err || desc_info->crc32_err) 2832 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2833 2834 if (desc_info->hw_dec && 2835 !(desc_info->sw_dec || desc_info->icv_err)) 2836 rx_status->flag |= RX_FLAG_DECRYPTED; 2837 2838 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2839 2840 data_rate = desc_info->data_rate; 2841 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2842 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2843 rx_status->encoding = RX_ENC_LEGACY; 2844 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2845 /* convert rate_idx after we get the correct band */ 2846 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2847 rx_status->encoding = RX_ENC_HT; 2848 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2849 if (desc_info->gi_ltf) 2850 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2851 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2852 rx_status->encoding = RX_ENC_VHT; 2853 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2854 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2855 if (desc_info->gi_ltf) 2856 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2857 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2858 rx_status->encoding = RX_ENC_HE; 2859 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2860 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2861 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2862 rx_status->encoding = RX_ENC_EHT; 2863 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2864 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2865 eht = true; 2866 } else { 2867 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2868 } 2869 2870 /* he_gi is used to match ppdu, so we always fill it. */ 2871 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2872 if (eht) 2873 rx_status->eht.gi = gi; 2874 else 2875 rx_status->he_gi = gi; 2876 rx_status->flag |= RX_FLAG_MACTIME_START; 2877 rx_status->mactime = desc_info->free_run_cnt; 2878 2879 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 2880 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2881 } 2882 2883 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2884 { 2885 const struct rtw89_chip_info *chip = rtwdev->chip; 2886 2887 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2888 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2889 return RTW89_PS_MODE_NONE; 2890 2891 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2892 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2893 return RTW89_PS_MODE_PWR_GATED; 2894 2895 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2896 return RTW89_PS_MODE_CLK_GATED; 2897 2898 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2899 return RTW89_PS_MODE_RFOFF; 2900 2901 return RTW89_PS_MODE_NONE; 2902 } 2903 2904 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2905 struct rtw89_rx_desc_info *desc_info) 2906 { 2907 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2908 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2909 struct ieee80211_rx_status *rx_status; 2910 struct sk_buff *skb_ppdu, *tmp; 2911 2912 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2913 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2914 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2915 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2916 } 2917 } 2918 2919 static 2920 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb, 2921 const struct rtw89_rx_desc_info *desc) 2922 { 2923 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2924 struct rtw89_sta_link *rtwsta_link; 2925 struct ieee80211_sta *sta; 2926 struct rtw89_sta *rtwsta; 2927 u8 macid = desc->mac_id; 2928 2929 if (!refcount_read(&rtwdev->refcount_ap_info)) 2930 return; 2931 2932 rcu_read_lock(); 2933 2934 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 2935 if (!rtwsta_link) 2936 goto out; 2937 2938 rtwsta = rtwsta_link->rtwsta; 2939 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags)) 2940 goto out; 2941 2942 sta = rtwsta_to_sta(rtwsta); 2943 if (ieee80211_is_pspoll(hdr->frame_control)) 2944 ieee80211_sta_pspoll(sta); 2945 else if (ieee80211_has_pm(hdr->frame_control) && 2946 (ieee80211_is_data_qos(hdr->frame_control) || 2947 ieee80211_is_qos_nullfunc(hdr->frame_control))) 2948 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr)); 2949 2950 out: 2951 rcu_read_unlock(); 2952 } 2953 2954 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2955 struct rtw89_rx_desc_info *desc_info, 2956 struct sk_buff *skb) 2957 { 2958 struct ieee80211_rx_status *rx_status; 2959 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2960 u8 ppdu_cnt = desc_info->ppdu_cnt; 2961 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2962 2963 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2964 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2965 return; 2966 } 2967 2968 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2969 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2970 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2971 } 2972 2973 rx_status = IEEE80211_SKB_RXCB(skb); 2974 memset(rx_status, 0, sizeof(*rx_status)); 2975 rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status); 2976 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info); 2977 if (desc_info->long_rxdesc && 2978 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2979 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2980 else 2981 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2982 } 2983 EXPORT_SYMBOL(rtw89_core_rx); 2984 2985 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2986 { 2987 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2988 return; 2989 2990 napi_enable(&rtwdev->napi); 2991 } 2992 EXPORT_SYMBOL(rtw89_core_napi_start); 2993 2994 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2995 { 2996 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2997 return; 2998 2999 napi_synchronize(&rtwdev->napi); 3000 napi_disable(&rtwdev->napi); 3001 } 3002 EXPORT_SYMBOL(rtw89_core_napi_stop); 3003 3004 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 3005 { 3006 rtwdev->netdev = alloc_netdev_dummy(0); 3007 if (!rtwdev->netdev) 3008 return -ENOMEM; 3009 3010 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 3011 rtwdev->hci.ops->napi_poll); 3012 return 0; 3013 } 3014 EXPORT_SYMBOL(rtw89_core_napi_init); 3015 3016 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 3017 { 3018 rtw89_core_napi_stop(rtwdev); 3019 netif_napi_del(&rtwdev->napi); 3020 free_netdev(rtwdev->netdev); 3021 } 3022 EXPORT_SYMBOL(rtw89_core_napi_deinit); 3023 3024 static void rtw89_core_ba_work(struct work_struct *work) 3025 { 3026 struct rtw89_dev *rtwdev = 3027 container_of(work, struct rtw89_dev, ba_work); 3028 struct rtw89_txq *rtwtxq, *tmp; 3029 int ret; 3030 3031 spin_lock_bh(&rtwdev->ba_lock); 3032 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 3033 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3034 struct ieee80211_sta *sta = txq->sta; 3035 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3036 u8 tid = txq->tid; 3037 3038 if (!sta) { 3039 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 3040 goto skip_ba_work; 3041 } 3042 3043 if (rtwsta->disassoc) { 3044 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3045 "cannot start BA with disassoc sta\n"); 3046 goto skip_ba_work; 3047 } 3048 3049 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 3050 if (ret) { 3051 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3052 "failed to setup BA session for %pM:%2d: %d\n", 3053 sta->addr, tid, ret); 3054 if (ret == -EINVAL) 3055 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 3056 } 3057 skip_ba_work: 3058 list_del_init(&rtwtxq->list); 3059 } 3060 spin_unlock_bh(&rtwdev->ba_lock); 3061 } 3062 3063 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 3064 struct ieee80211_sta *sta) 3065 { 3066 struct rtw89_txq *rtwtxq, *tmp; 3067 3068 spin_lock_bh(&rtwdev->ba_lock); 3069 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 3070 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3071 3072 if (sta == txq->sta) 3073 list_del_init(&rtwtxq->list); 3074 } 3075 spin_unlock_bh(&rtwdev->ba_lock); 3076 } 3077 3078 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 3079 struct ieee80211_sta *sta) 3080 { 3081 struct rtw89_txq *rtwtxq, *tmp; 3082 3083 spin_lock_bh(&rtwdev->ba_lock); 3084 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 3085 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3086 3087 if (sta == txq->sta) { 3088 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3089 list_del_init(&rtwtxq->list); 3090 } 3091 } 3092 spin_unlock_bh(&rtwdev->ba_lock); 3093 } 3094 3095 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 3096 struct ieee80211_sta *sta) 3097 { 3098 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3099 struct sk_buff *skb, *tmp; 3100 3101 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 3102 skb_unlink(skb, &rtwsta->roc_queue); 3103 dev_kfree_skb_any(skb); 3104 } 3105 } 3106 3107 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 3108 struct rtw89_txq *rtwtxq) 3109 { 3110 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3111 struct ieee80211_sta *sta = txq->sta; 3112 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3113 3114 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 3115 return; 3116 3117 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 3118 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3119 return; 3120 3121 spin_lock_bh(&rtwdev->ba_lock); 3122 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3123 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 3124 spin_unlock_bh(&rtwdev->ba_lock); 3125 3126 ieee80211_stop_tx_ba_session(sta, txq->tid); 3127 cancel_delayed_work(&rtwdev->forbid_ba_work); 3128 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 3129 RTW89_FORBID_BA_TIMER); 3130 } 3131 3132 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 3133 struct rtw89_txq *rtwtxq, 3134 struct sk_buff *skb) 3135 { 3136 struct ieee80211_hw *hw = rtwdev->hw; 3137 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3138 struct ieee80211_sta *sta = txq->sta; 3139 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 3140 3141 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 3142 return; 3143 3144 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 3145 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 3146 return; 3147 } 3148 3149 if (unlikely(!sta)) 3150 return; 3151 3152 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 3153 return; 3154 3155 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 3156 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 3157 return; 3158 } 3159 3160 spin_lock_bh(&rtwdev->ba_lock); 3161 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 3162 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 3163 ieee80211_queue_work(hw, &rtwdev->ba_work); 3164 } 3165 spin_unlock_bh(&rtwdev->ba_lock); 3166 } 3167 3168 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 3169 struct rtw89_txq *rtwtxq, 3170 unsigned long frame_cnt, 3171 unsigned long byte_cnt) 3172 { 3173 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3174 struct ieee80211_vif *vif = txq->vif; 3175 struct ieee80211_sta *sta = txq->sta; 3176 struct sk_buff *skb; 3177 unsigned long i; 3178 int ret; 3179 3180 rcu_read_lock(); 3181 for (i = 0; i < frame_cnt; i++) { 3182 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 3183 if (!skb) { 3184 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 3185 goto out; 3186 } 3187 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 3188 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 3189 if (ret) { 3190 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 3191 ieee80211_free_txskb(rtwdev->hw, skb); 3192 break; 3193 } 3194 } 3195 out: 3196 rcu_read_unlock(); 3197 } 3198 3199 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 3200 { 3201 u8 qsel, ch_dma; 3202 3203 qsel = rtw89_core_get_qsel(rtwdev, tid); 3204 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 3205 3206 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 3207 } 3208 3209 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 3210 struct ieee80211_txq *txq, 3211 unsigned long *frame_cnt, 3212 bool *sched_txq, bool *reinvoke) 3213 { 3214 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3215 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta); 3216 struct rtw89_sta_link *rtwsta_link; 3217 3218 if (!rtwsta) 3219 return false; 3220 3221 rtwsta_link = rtw89_get_designated_link(rtwsta); 3222 if (unlikely(!rtwsta_link)) { 3223 rtw89_err(rtwdev, "agg wait: find no designated link\n"); 3224 return false; 3225 } 3226 3227 if (rtwsta_link->max_agg_wait <= 0) 3228 return false; 3229 3230 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 3231 return false; 3232 3233 if (*frame_cnt > 1) { 3234 *frame_cnt -= 1; 3235 *sched_txq = true; 3236 *reinvoke = true; 3237 rtwtxq->wait_cnt = 1; 3238 return false; 3239 } 3240 3241 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) { 3242 *reinvoke = true; 3243 rtwtxq->wait_cnt++; 3244 return true; 3245 } 3246 3247 rtwtxq->wait_cnt = 0; 3248 return false; 3249 } 3250 3251 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 3252 { 3253 struct ieee80211_hw *hw = rtwdev->hw; 3254 struct ieee80211_txq *txq; 3255 struct rtw89_vif *rtwvif; 3256 struct rtw89_txq *rtwtxq; 3257 unsigned long frame_cnt; 3258 unsigned long byte_cnt; 3259 u32 tx_resource; 3260 bool sched_txq; 3261 3262 ieee80211_txq_schedule_start(hw, ac); 3263 while ((txq = ieee80211_next_txq(hw, ac))) { 3264 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3265 rtwvif = vif_to_rtwvif(txq->vif); 3266 3267 if (rtwvif->offchan) { 3268 ieee80211_return_txq(hw, txq, true); 3269 continue; 3270 } 3271 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 3272 sched_txq = false; 3273 3274 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 3275 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 3276 ieee80211_return_txq(hw, txq, true); 3277 continue; 3278 } 3279 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 3280 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 3281 ieee80211_return_txq(hw, txq, sched_txq); 3282 if (frame_cnt != 0) 3283 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 3284 3285 /* bound of tx_resource could get stuck due to burst traffic */ 3286 if (frame_cnt == tx_resource) 3287 *reinvoke = true; 3288 } 3289 ieee80211_txq_schedule_end(hw, ac); 3290 } 3291 3292 static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work) 3293 { 3294 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3295 ips_work); 3296 3297 lockdep_assert_wiphy(wiphy); 3298 3299 rtw89_enter_ips_by_hwflags(rtwdev); 3300 } 3301 3302 static void rtw89_core_txq_work(struct work_struct *w) 3303 { 3304 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 3305 bool reinvoke = false; 3306 u8 ac; 3307 3308 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3309 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 3310 3311 if (reinvoke) { 3312 /* reinvoke to process the last frame */ 3313 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 3314 } 3315 } 3316 3317 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 3318 { 3319 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3320 txq_reinvoke_work.work); 3321 3322 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3323 } 3324 3325 static void rtw89_forbid_ba_work(struct work_struct *w) 3326 { 3327 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3328 forbid_ba_work.work); 3329 struct rtw89_txq *rtwtxq, *tmp; 3330 3331 spin_lock_bh(&rtwdev->ba_lock); 3332 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 3333 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3334 list_del_init(&rtwtxq->list); 3335 } 3336 spin_unlock_bh(&rtwdev->ba_lock); 3337 } 3338 3339 static void rtw89_core_sta_pending_tx_iter(void *data, 3340 struct ieee80211_sta *sta) 3341 { 3342 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3343 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3344 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3345 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3346 struct rtw89_vif_link *target = data; 3347 struct rtw89_vif_link *rtwvif_link; 3348 struct sk_buff *skb, *tmp; 3349 unsigned int link_id; 3350 int qsel, ret; 3351 3352 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3353 if (rtwvif_link->chanctx_idx == target->chanctx_idx) 3354 goto bottom; 3355 3356 return; 3357 3358 bottom: 3359 if (skb_queue_len(&rtwsta->roc_queue) == 0) 3360 return; 3361 3362 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 3363 skb_unlink(skb, &rtwsta->roc_queue); 3364 3365 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 3366 if (ret) { 3367 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 3368 dev_kfree_skb_any(skb); 3369 } else { 3370 rtw89_core_tx_kick_off(rtwdev, qsel); 3371 } 3372 } 3373 } 3374 3375 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 3376 struct rtw89_vif_link *rtwvif_link) 3377 { 3378 ieee80211_iterate_stations_atomic(rtwdev->hw, 3379 rtw89_core_sta_pending_tx_iter, 3380 rtwvif_link); 3381 } 3382 3383 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 3384 bool qos, bool ps, int timeout) 3385 { 3386 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3387 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1; 3388 struct rtw89_sta_link *rtwsta_link; 3389 struct ieee80211_sta *sta; 3390 struct ieee80211_hdr *hdr; 3391 struct rtw89_sta *rtwsta; 3392 struct sk_buff *skb; 3393 int ret, qsel; 3394 3395 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 3396 return 0; 3397 3398 rcu_read_lock(); 3399 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); 3400 if (!sta) { 3401 ret = -EINVAL; 3402 goto out; 3403 } 3404 rtwsta = sta_to_rtwsta(sta); 3405 3406 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos); 3407 if (!skb) { 3408 ret = -ENOMEM; 3409 goto out; 3410 } 3411 3412 hdr = (struct ieee80211_hdr *)skb->data; 3413 if (ps) 3414 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 3415 3416 rtwsta_link = rtwsta->links[rtwvif_link->link_id]; 3417 if (unlikely(!rtwsta_link)) { 3418 ret = -ENOLINK; 3419 goto out; 3420 } 3421 3422 ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, true); 3423 if (ret) { 3424 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 3425 dev_kfree_skb_any(skb); 3426 goto out; 3427 } 3428 3429 rcu_read_unlock(); 3430 3431 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 3432 timeout); 3433 out: 3434 rcu_read_unlock(); 3435 3436 return ret; 3437 } 3438 3439 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3440 { 3441 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3442 struct rtw89_chanctx_pause_parm pause_parm = { 3443 .rsn = RTW89_CHANCTX_PAUSE_REASON_ROC, 3444 }; 3445 struct ieee80211_hw *hw = rtwdev->hw; 3446 struct rtw89_roc *roc = &rtwvif->roc; 3447 struct rtw89_vif_link *rtwvif_link; 3448 struct cfg80211_chan_def roc_chan; 3449 struct rtw89_vif *tmp_vif; 3450 u32 reg; 3451 int ret; 3452 3453 lockdep_assert_wiphy(hw->wiphy); 3454 3455 rtw89_leave_ips_by_hwflags(rtwdev); 3456 rtw89_leave_lps(rtwdev); 3457 3458 rtwvif_link = rtw89_get_designated_link(rtwvif); 3459 if (unlikely(!rtwvif_link)) { 3460 rtw89_err(rtwdev, "roc start: find no designated link\n"); 3461 return; 3462 } 3463 3464 roc->link_id = rtwvif_link->link_id; 3465 3466 pause_parm.trigger = rtwvif_link; 3467 rtw89_chanctx_pause(rtwdev, &pause_parm); 3468 3469 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true, 3470 RTW89_ROC_TX_TIMEOUT); 3471 if (ret) 3472 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3473 "roc send null-1 failed: %d\n", ret); 3474 3475 rtw89_for_each_rtwvif(rtwdev, tmp_vif) { 3476 struct rtw89_vif_link *tmp_link; 3477 unsigned int link_id; 3478 3479 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) { 3480 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) { 3481 tmp_vif->offchan = true; 3482 break; 3483 } 3484 } 3485 } 3486 3487 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 3488 rtw89_config_roc_chandef(rtwdev, rtwvif_link, &roc_chan); 3489 rtw89_set_channel(rtwdev); 3490 3491 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3492 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 3493 3494 ieee80211_ready_on_channel(hw); 3495 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work); 3496 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work, 3497 msecs_to_jiffies(rtwvif->roc.duration)); 3498 } 3499 3500 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3501 { 3502 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3503 struct ieee80211_hw *hw = rtwdev->hw; 3504 struct rtw89_roc *roc = &rtwvif->roc; 3505 struct rtw89_vif_link *rtwvif_link; 3506 struct rtw89_vif *tmp_vif; 3507 u32 reg; 3508 int ret; 3509 3510 lockdep_assert_wiphy(hw->wiphy); 3511 3512 ieee80211_remain_on_channel_expired(hw); 3513 3514 rtw89_leave_ips_by_hwflags(rtwdev); 3515 rtw89_leave_lps(rtwdev); 3516 3517 rtwvif_link = rtwvif->links[roc->link_id]; 3518 if (unlikely(!rtwvif_link)) { 3519 rtw89_err(rtwdev, "roc end: find no link (link id %u)\n", 3520 roc->link_id); 3521 return; 3522 } 3523 3524 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3525 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr); 3526 3527 roc->state = RTW89_ROC_IDLE; 3528 rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL); 3529 rtw89_chanctx_proceed(rtwdev, NULL); 3530 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false, 3531 RTW89_ROC_TX_TIMEOUT); 3532 if (ret) 3533 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3534 "roc send null-0 failed: %d\n", ret); 3535 3536 rtw89_for_each_rtwvif(rtwdev, tmp_vif) 3537 tmp_vif->offchan = false; 3538 3539 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link); 3540 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3541 3542 if (hw->conf.flags & IEEE80211_CONF_IDLE) 3543 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work, 3544 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 3545 } 3546 3547 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work) 3548 { 3549 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3550 roc.roc_work.work); 3551 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3552 struct rtw89_roc *roc = &rtwvif->roc; 3553 3554 lockdep_assert_wiphy(wiphy); 3555 3556 switch (roc->state) { 3557 case RTW89_ROC_IDLE: 3558 rtw89_enter_ips_by_hwflags(rtwdev); 3559 break; 3560 case RTW89_ROC_MGMT: 3561 case RTW89_ROC_NORMAL: 3562 rtw89_roc_end(rtwdev, rtwvif); 3563 break; 3564 default: 3565 break; 3566 } 3567 } 3568 3569 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3570 u32 throughput, u64 cnt) 3571 { 3572 if (cnt < 100) 3573 return RTW89_TFC_IDLE; 3574 if (throughput > 50) 3575 return RTW89_TFC_HIGH; 3576 if (throughput > 10) 3577 return RTW89_TFC_MID; 3578 if (throughput > 2) 3579 return RTW89_TFC_LOW; 3580 return RTW89_TFC_ULTRA_LOW; 3581 } 3582 3583 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3584 struct rtw89_traffic_stats *stats) 3585 { 3586 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3587 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3588 3589 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 3590 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3591 3592 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3593 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3594 3595 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3596 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3597 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3598 stats->tx_cnt); 3599 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3600 stats->rx_cnt); 3601 stats->tx_avg_len = stats->tx_cnt ? 3602 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3603 stats->rx_avg_len = stats->rx_cnt ? 3604 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3605 3606 stats->tx_unicast = 0; 3607 stats->rx_unicast = 0; 3608 stats->tx_cnt = 0; 3609 stats->rx_cnt = 0; 3610 stats->rx_tf_periodic = stats->rx_tf_acc; 3611 stats->rx_tf_acc = 0; 3612 3613 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3614 return true; 3615 3616 return false; 3617 } 3618 3619 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3620 { 3621 struct rtw89_vif_link *rtwvif_link; 3622 struct rtw89_vif *rtwvif; 3623 unsigned int link_id; 3624 bool tfc_changed; 3625 3626 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3627 3628 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3629 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3630 3631 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3632 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link); 3633 } 3634 3635 return tfc_changed; 3636 } 3637 3638 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3639 { 3640 struct ieee80211_vif *vif; 3641 struct rtw89_vif *rtwvif; 3642 3643 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3644 if (rtwvif->tdls_peer) 3645 continue; 3646 if (rtwvif->offchan) 3647 continue; 3648 3649 if (rtwvif->stats.tx_tfc_lv != RTW89_TFC_IDLE || 3650 rtwvif->stats.rx_tfc_lv != RTW89_TFC_IDLE) 3651 continue; 3652 3653 vif = rtwvif_to_vif(rtwvif); 3654 3655 if (!(vif->type == NL80211_IFTYPE_STATION || 3656 vif->type == NL80211_IFTYPE_P2P_CLIENT)) 3657 continue; 3658 3659 rtw89_enter_lps(rtwdev, rtwvif, true); 3660 } 3661 } 3662 3663 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3664 { 3665 enum rtw89_entity_mode mode; 3666 3667 mode = rtw89_get_entity_mode(rtwdev); 3668 if (mode == RTW89_ENTITY_MODE_MCC) 3669 return; 3670 3671 rtw89_chip_rfk_track(rtwdev); 3672 } 3673 3674 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 3675 struct rtw89_vif_link *rtwvif_link, 3676 struct ieee80211_bss_conf *bss_conf) 3677 { 3678 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3679 3680 if (mode == RTW89_ENTITY_MODE_MCC) 3681 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3682 else 3683 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf); 3684 } 3685 3686 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3687 struct rtw89_traffic_stats *stats) 3688 { 3689 stats->tx_unicast = 0; 3690 stats->rx_unicast = 0; 3691 stats->tx_cnt = 0; 3692 stats->rx_cnt = 0; 3693 ewma_tp_init(&stats->tx_ewma_tp); 3694 ewma_tp_init(&stats->rx_ewma_tp); 3695 } 3696 3697 #define RTW89_MLSR_GOTO_2GHZ_THRESHOLD -53 3698 #define RTW89_MLSR_EXIT_2GHZ_THRESHOLD -38 3699 static void rtw89_core_mlsr_link_decision(struct rtw89_dev *rtwdev, 3700 struct rtw89_vif *rtwvif) 3701 { 3702 unsigned int sel_link_id = IEEE80211_MLD_MAX_NUM_LINKS; 3703 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3704 struct rtw89_vif_link *rtwvif_link; 3705 const struct rtw89_chan *chan; 3706 unsigned long usable_links; 3707 unsigned int link_id; 3708 u8 decided_bands; 3709 u8 rssi; 3710 3711 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi); 3712 if (unlikely(!rssi)) 3713 return; 3714 3715 if (RTW89_RSSI_RAW_TO_DBM(rssi) >= RTW89_MLSR_EXIT_2GHZ_THRESHOLD) 3716 decided_bands = BIT(RTW89_BAND_5G) | BIT(RTW89_BAND_6G); 3717 else if (RTW89_RSSI_RAW_TO_DBM(rssi) <= RTW89_MLSR_GOTO_2GHZ_THRESHOLD) 3718 decided_bands = BIT(RTW89_BAND_2G); 3719 else 3720 return; 3721 3722 usable_links = ieee80211_vif_usable_links(vif); 3723 3724 rtwvif_link = rtw89_get_designated_link(rtwvif); 3725 if (unlikely(!rtwvif_link)) 3726 goto select; 3727 3728 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx); 3729 if (decided_bands & BIT(chan->band_type)) 3730 return; 3731 3732 usable_links &= ~BIT(rtwvif_link->link_id); 3733 3734 select: 3735 rcu_read_lock(); 3736 3737 for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) { 3738 struct ieee80211_bss_conf *link_conf; 3739 struct ieee80211_channel *channel; 3740 enum rtw89_band band; 3741 3742 link_conf = rcu_dereference(vif->link_conf[link_id]); 3743 if (unlikely(!link_conf)) 3744 continue; 3745 3746 channel = link_conf->chanreq.oper.chan; 3747 if (unlikely(!channel)) 3748 continue; 3749 3750 band = rtw89_nl80211_to_hw_band(channel->band); 3751 if (decided_bands & BIT(band)) { 3752 sel_link_id = link_id; 3753 break; 3754 } 3755 } 3756 3757 rcu_read_unlock(); 3758 3759 if (sel_link_id == IEEE80211_MLD_MAX_NUM_LINKS) 3760 return; 3761 3762 rtw89_core_mlsr_switch(rtwdev, rtwvif, sel_link_id); 3763 } 3764 3765 static void rtw89_core_mlo_track(struct rtw89_dev *rtwdev) 3766 { 3767 struct rtw89_hal *hal = &rtwdev->hal; 3768 struct ieee80211_vif *vif; 3769 struct rtw89_vif *rtwvif; 3770 3771 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_MLO)) 3772 return; 3773 3774 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3775 vif = rtwvif_to_vif(rtwvif); 3776 if (!vif->cfg.assoc || !ieee80211_vif_is_mld(vif)) 3777 continue; 3778 3779 switch (rtwvif->mlo_mode) { 3780 case RTW89_MLO_MODE_MLSR: 3781 rtw89_core_mlsr_link_decision(rtwdev, rtwvif); 3782 break; 3783 default: 3784 break; 3785 } 3786 } 3787 } 3788 3789 static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work) 3790 { 3791 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3792 track_work.work); 3793 bool tfc_changed; 3794 3795 lockdep_assert_wiphy(wiphy); 3796 3797 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags)) 3798 return; 3799 3800 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3801 return; 3802 3803 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work, 3804 RTW89_TRACK_WORK_PERIOD); 3805 3806 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3807 if (rtwdev->scanning) 3808 return; 3809 3810 rtw89_leave_lps(rtwdev); 3811 3812 if (tfc_changed) { 3813 rtw89_hci_recalc_int_mit(rtwdev); 3814 rtw89_btc_ntfy_wl_sta(rtwdev); 3815 } 3816 rtw89_mac_bf_monitor_track(rtwdev); 3817 rtw89_phy_stat_track(rtwdev); 3818 rtw89_phy_env_monitor_track(rtwdev); 3819 rtw89_phy_dig(rtwdev); 3820 rtw89_core_rfk_track(rtwdev); 3821 rtw89_phy_ra_update(rtwdev); 3822 rtw89_phy_cfo_track(rtwdev); 3823 rtw89_phy_tx_path_div_track(rtwdev); 3824 rtw89_phy_antdiv_track(rtwdev); 3825 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3826 rtw89_phy_edcca_track(rtwdev); 3827 rtw89_sar_track(rtwdev); 3828 rtw89_chanctx_track(rtwdev); 3829 rtw89_core_rfkill_poll(rtwdev, false); 3830 rtw89_core_mlo_track(rtwdev); 3831 3832 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3833 rtw89_enter_lps_track(rtwdev); 3834 } 3835 3836 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3837 { 3838 unsigned long bit; 3839 3840 bit = find_first_zero_bit(addr, size); 3841 if (bit < size) 3842 set_bit(bit, addr); 3843 3844 return bit; 3845 } 3846 3847 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3848 { 3849 clear_bit(bit, addr); 3850 } 3851 3852 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3853 { 3854 bitmap_zero(addr, nbits); 3855 } 3856 3857 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3858 struct rtw89_sta_link *rtwsta_link, u8 tid, 3859 u8 *cam_idx) 3860 { 3861 const struct rtw89_chip_info *chip = rtwdev->chip; 3862 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3863 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3864 u8 idx; 3865 int i; 3866 3867 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3868 3869 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3870 if (idx == chip->bacam_num) { 3871 /* allocate a static BA CAM to tid=0/5, so replace the existing 3872 * one if BA CAM is full. Hardware will process the original tid 3873 * automatically. 3874 */ 3875 if (tid != 0 && tid != 5) 3876 return -ENOSPC; 3877 3878 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3879 tmp = &cam_info->ba_cam_entry[i]; 3880 if (tmp->tid == 0 || tmp->tid == 5) 3881 continue; 3882 3883 idx = i; 3884 entry = tmp; 3885 list_del(&entry->list); 3886 break; 3887 } 3888 3889 if (!entry) 3890 return -ENOSPC; 3891 } else { 3892 entry = &cam_info->ba_cam_entry[idx]; 3893 } 3894 3895 entry->tid = tid; 3896 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list); 3897 3898 *cam_idx = idx; 3899 3900 return 0; 3901 } 3902 3903 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3904 struct rtw89_sta_link *rtwsta_link, u8 tid, 3905 u8 *cam_idx) 3906 { 3907 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3908 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3909 u8 idx; 3910 3911 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3912 3913 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) { 3914 if (entry->tid != tid) 3915 continue; 3916 3917 idx = entry - cam_info->ba_cam_entry; 3918 list_del(&entry->list); 3919 3920 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3921 *cam_idx = idx; 3922 return 0; 3923 } 3924 3925 return -ENOENT; 3926 } 3927 3928 #define RTW89_TYPE_MAPPING(_type) \ 3929 case NL80211_IFTYPE_ ## _type: \ 3930 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3931 break 3932 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc) 3933 { 3934 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3935 const struct ieee80211_bss_conf *bss_conf; 3936 3937 switch (vif->type) { 3938 case NL80211_IFTYPE_STATION: 3939 if (vif->p2p) 3940 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3941 else 3942 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION; 3943 break; 3944 case NL80211_IFTYPE_AP: 3945 if (vif->p2p) 3946 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3947 else 3948 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP; 3949 break; 3950 RTW89_TYPE_MAPPING(ADHOC); 3951 RTW89_TYPE_MAPPING(MONITOR); 3952 RTW89_TYPE_MAPPING(MESH_POINT); 3953 default: 3954 WARN_ON(1); 3955 break; 3956 } 3957 3958 switch (vif->type) { 3959 case NL80211_IFTYPE_AP: 3960 case NL80211_IFTYPE_MESH_POINT: 3961 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE; 3962 rtwvif_link->self_role = RTW89_SELF_ROLE_AP; 3963 break; 3964 case NL80211_IFTYPE_ADHOC: 3965 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC; 3966 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 3967 break; 3968 case NL80211_IFTYPE_STATION: 3969 if (assoc) { 3970 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA; 3971 3972 rcu_read_lock(); 3973 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 3974 rtwvif_link->trigger = bss_conf->he_support; 3975 rcu_read_unlock(); 3976 } else { 3977 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 3978 rtwvif_link->trigger = false; 3979 } 3980 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 3981 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3982 break; 3983 case NL80211_IFTYPE_MONITOR: 3984 break; 3985 default: 3986 WARN_ON(1); 3987 break; 3988 } 3989 } 3990 3991 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 3992 struct rtw89_vif_link *rtwvif_link, 3993 struct rtw89_sta_link *rtwsta_link) 3994 { 3995 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3996 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3997 struct rtw89_hal *hal = &rtwdev->hal; 3998 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3999 int i; 4000 int ret; 4001 4002 rtwsta_link->prev_rssi = 0; 4003 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list); 4004 ewma_rssi_init(&rtwsta_link->avg_rssi); 4005 ewma_snr_init(&rtwsta_link->avg_snr); 4006 ewma_evm_init(&rtwsta_link->evm_1ss); 4007 for (i = 0; i < ant_num; i++) { 4008 ewma_rssi_init(&rtwsta_link->rssi[i]); 4009 ewma_evm_init(&rtwsta_link->evm_min[i]); 4010 ewma_evm_init(&rtwsta_link->evm_max[i]); 4011 } 4012 4013 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4014 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 4015 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true); 4016 if (ret) 4017 return ret; 4018 4019 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4020 BTC_ROLE_MSTS_STA_CONN_START); 4021 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 4022 4023 if (vif->p2p) { 4024 rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta_link, 4025 &rtwsta_link->tx_retry); 4026 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 60); 4027 } 4028 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4029 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false); 4030 if (ret) { 4031 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 4032 return ret; 4033 } 4034 4035 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 4036 RTW89_ROLE_CREATE); 4037 if (ret) { 4038 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 4039 return ret; 4040 } 4041 4042 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4043 if (ret) 4044 return ret; 4045 4046 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4047 if (ret) 4048 return ret; 4049 } 4050 4051 return 0; 4052 } 4053 4054 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 4055 struct rtw89_vif_link *rtwvif_link, 4056 struct rtw89_sta_link *rtwsta_link) 4057 { 4058 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4059 4060 rtw89_assoc_link_clr(rtwsta_link); 4061 4062 if (vif->type == NL80211_IFTYPE_STATION) 4063 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false); 4064 4065 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT) 4066 rtw89_p2p_noa_once_deinit(rtwvif_link); 4067 4068 return 0; 4069 } 4070 4071 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 4072 struct rtw89_vif_link *rtwvif_link, 4073 struct rtw89_sta_link *rtwsta_link) 4074 { 4075 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4076 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4077 int ret; 4078 4079 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true); 4080 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link); 4081 4082 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 4083 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam); 4084 if (sta->tdls) 4085 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam); 4086 4087 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4088 rtw89_vif_type_mapping(rtwvif_link, false); 4089 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true); 4090 } 4091 4092 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4093 if (ret) { 4094 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 4095 return ret; 4096 } 4097 4098 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true); 4099 if (ret) { 4100 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 4101 return ret; 4102 } 4103 4104 /* update cam aid mac_id net_type */ 4105 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 4106 if (ret) { 4107 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 4108 return ret; 4109 } 4110 4111 return ret; 4112 } 4113 4114 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev, 4115 struct ieee80211_bss_conf *bss_conf, 4116 struct ieee80211_link_sta *link_sta) 4117 { 4118 if (!bss_conf->he_support || 4119 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE) 4120 return false; 4121 4122 if (rtwdev->chip->chip_id == RTL8852C && 4123 rtw89_sta_link_has_su_mu_4xhe08(link_sta) && 4124 !rtw89_sta_link_has_er_su_4xhe08(link_sta)) 4125 return false; 4126 4127 return true; 4128 } 4129 4130 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 4131 struct rtw89_vif_link *rtwvif_link, 4132 struct rtw89_sta_link *rtwsta_link) 4133 { 4134 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4135 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4136 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link, 4137 rtwsta_link); 4138 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4139 rtwvif_link->chanctx_idx); 4140 struct ieee80211_link_sta *link_sta; 4141 int ret; 4142 4143 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4144 if (sta->tdls) { 4145 rcu_read_lock(); 4146 4147 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4148 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam, 4149 link_sta->addr); 4150 if (ret) { 4151 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 4152 rcu_read_unlock(); 4153 return ret; 4154 } 4155 4156 rcu_read_unlock(); 4157 } 4158 4159 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam); 4160 if (ret) { 4161 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 4162 return ret; 4163 } 4164 } 4165 4166 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 4167 if (ret) { 4168 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 4169 return ret; 4170 } 4171 4172 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false); 4173 if (ret) { 4174 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 4175 return ret; 4176 } 4177 4178 /* update cam aid mac_id net_type */ 4179 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 4180 if (ret) { 4181 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 4182 return ret; 4183 } 4184 4185 rtw89_phy_ra_assoc(rtwdev, rtwsta_link); 4186 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 4187 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false); 4188 4189 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4190 struct ieee80211_bss_conf *bss_conf; 4191 4192 rcu_read_lock(); 4193 4194 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4195 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 4196 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta); 4197 4198 rcu_read_unlock(); 4199 4200 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4201 BTC_ROLE_MSTS_STA_CONN_END); 4202 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan); 4203 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link); 4204 4205 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id); 4206 if (ret) { 4207 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 4208 return ret; 4209 } 4210 4211 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 4212 4213 if (vif->p2p) 4214 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 4215 rtwsta_link->tx_retry); 4216 } 4217 4218 rtw89_assoc_link_set(rtwsta_link); 4219 return ret; 4220 } 4221 4222 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 4223 struct rtw89_vif_link *rtwvif_link, 4224 struct rtw89_sta_link *rtwsta_link) 4225 { 4226 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 4227 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 4228 int ret; 4229 4230 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 4231 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false); 4232 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 4233 BTC_ROLE_MSTS_STA_DIS_CONN); 4234 4235 if (vif->p2p) 4236 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 4237 rtwsta_link->tx_retry); 4238 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 4239 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 4240 RTW89_ROLE_REMOVE); 4241 if (ret) { 4242 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 4243 return ret; 4244 } 4245 } 4246 4247 return 0; 4248 } 4249 4250 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4251 struct ieee80211_sta *sta, 4252 struct cfg80211_tid_cfg *tid_conf) 4253 { 4254 struct ieee80211_txq *txq; 4255 struct rtw89_txq *rtwtxq; 4256 u32 mask = tid_conf->mask; 4257 u8 tids = tid_conf->tids; 4258 int tids_nbit = BITS_PER_BYTE; 4259 int i; 4260 4261 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 4262 if (!tids) 4263 break; 4264 4265 if (!(tids & BIT(0))) 4266 continue; 4267 4268 txq = sta->txq[i]; 4269 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 4270 4271 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 4272 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 4273 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4274 } else { 4275 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 4276 ieee80211_stop_tx_ba_session(sta, txq->tid); 4277 spin_lock_bh(&rtwdev->ba_lock); 4278 list_del_init(&rtwtxq->list); 4279 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4280 spin_unlock_bh(&rtwdev->ba_lock); 4281 } 4282 } 4283 4284 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 4285 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 4286 sta->max_amsdu_subframes = 0; 4287 else 4288 sta->max_amsdu_subframes = 1; 4289 } 4290 } 4291 } 4292 4293 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4294 struct ieee80211_sta *sta, 4295 struct cfg80211_tid_config *tid_config) 4296 { 4297 int i; 4298 4299 for (i = 0; i < tid_config->n_tid_conf; i++) 4300 _rtw89_core_set_tid_config(rtwdev, sta, 4301 &tid_config->tid_conf[i]); 4302 } 4303 4304 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 4305 struct ieee80211_sta_ht_cap *ht_cap) 4306 { 4307 static const __le16 highest[RF_PATH_MAX] = { 4308 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 4309 }; 4310 struct rtw89_hal *hal = &rtwdev->hal; 4311 u8 nss = hal->rx_nss; 4312 int i; 4313 4314 ht_cap->ht_supported = true; 4315 ht_cap->cap = 0; 4316 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 4317 IEEE80211_HT_CAP_MAX_AMSDU | 4318 IEEE80211_HT_CAP_TX_STBC | 4319 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 4320 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 4321 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 4322 IEEE80211_HT_CAP_DSSSCCK40 | 4323 IEEE80211_HT_CAP_SGI_40; 4324 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 4325 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 4326 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 4327 for (i = 0; i < nss; i++) 4328 ht_cap->mcs.rx_mask[i] = 0xFF; 4329 ht_cap->mcs.rx_mask[4] = 0x01; 4330 ht_cap->mcs.rx_highest = highest[nss - 1]; 4331 } 4332 4333 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 4334 struct ieee80211_sta_vht_cap *vht_cap) 4335 { 4336 static const __le16 highest_bw80[RF_PATH_MAX] = { 4337 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 4338 }; 4339 static const __le16 highest_bw160[RF_PATH_MAX] = { 4340 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 4341 }; 4342 const struct rtw89_chip_info *chip = rtwdev->chip; 4343 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 4344 highest_bw160 : highest_bw80; 4345 struct rtw89_hal *hal = &rtwdev->hal; 4346 u16 tx_mcs_map = 0, rx_mcs_map = 0; 4347 u8 sts_cap = 3; 4348 int i; 4349 4350 for (i = 0; i < 8; i++) { 4351 if (i < hal->tx_nss) 4352 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4353 else 4354 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4355 if (i < hal->rx_nss) 4356 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4357 else 4358 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4359 } 4360 4361 vht_cap->vht_supported = true; 4362 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 4363 IEEE80211_VHT_CAP_SHORT_GI_80 | 4364 IEEE80211_VHT_CAP_RXSTBC_1 | 4365 IEEE80211_VHT_CAP_HTC_VHT | 4366 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 4367 0; 4368 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 4369 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 4370 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 4371 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 4372 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 4373 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4374 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 4375 IEEE80211_VHT_CAP_SHORT_GI_160; 4376 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 4377 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 4378 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 4379 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 4380 4381 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 4382 vht_cap->vht_mcs.tx_highest |= 4383 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 4384 } 4385 4386 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 4387 enum nl80211_band band, 4388 enum nl80211_iftype iftype, 4389 struct ieee80211_sband_iftype_data *iftype_data) 4390 { 4391 const struct rtw89_chip_info *chip = rtwdev->chip; 4392 struct rtw89_hal *hal = &rtwdev->hal; 4393 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 4394 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 4395 struct ieee80211_sta_he_cap *he_cap; 4396 int nss = hal->rx_nss; 4397 u8 *mac_cap_info; 4398 u8 *phy_cap_info; 4399 u16 mcs_map = 0; 4400 int i; 4401 4402 for (i = 0; i < 8; i++) { 4403 if (i < nss) 4404 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 4405 else 4406 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 4407 } 4408 4409 he_cap = &iftype_data->he_cap; 4410 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 4411 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 4412 4413 he_cap->has_he = true; 4414 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 4415 if (iftype == NL80211_IFTYPE_STATION) 4416 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 4417 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 4418 IEEE80211_HE_MAC_CAP2_BSR; 4419 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 4420 if (iftype == NL80211_IFTYPE_AP) 4421 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 4422 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 4423 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 4424 if (iftype == NL80211_IFTYPE_STATION) 4425 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 4426 if (band == NL80211_BAND_2GHZ) { 4427 phy_cap_info[0] = 4428 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 4429 } else { 4430 phy_cap_info[0] = 4431 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 4432 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4433 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 4434 } 4435 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 4436 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 4437 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 4438 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 4439 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 4440 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 4441 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 4442 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 4443 if (iftype == NL80211_IFTYPE_STATION) 4444 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 4445 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 4446 if (iftype == NL80211_IFTYPE_AP) 4447 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 4448 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 4449 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 4450 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4451 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 4452 phy_cap_info[5] = no_ng16 ? 0 : 4453 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 4454 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 4455 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 4456 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 4457 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 4458 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 4459 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 4460 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 4461 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 4462 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 4463 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 4464 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 4465 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4466 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 4467 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 4468 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 4469 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 4470 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 4471 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 4472 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 4473 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 4474 if (iftype == NL80211_IFTYPE_STATION) 4475 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 4476 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 4477 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 4478 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 4479 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 4480 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 4481 } 4482 4483 if (band == NL80211_BAND_6GHZ) { 4484 __le16 capa; 4485 4486 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 4487 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 4488 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 4489 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 4490 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 4491 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 4492 iftype_data->he_6ghz_capa.capa = capa; 4493 } 4494 } 4495 4496 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 4497 enum nl80211_band band, 4498 enum nl80211_iftype iftype, 4499 struct ieee80211_sband_iftype_data *iftype_data) 4500 { 4501 const struct rtw89_chip_info *chip = rtwdev->chip; 4502 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 4503 struct ieee80211_eht_mcs_nss_supp *eht_nss; 4504 struct ieee80211_sta_eht_cap *eht_cap; 4505 struct rtw89_hal *hal = &rtwdev->hal; 4506 bool support_mcs_12_13 = true; 4507 bool support_320mhz = false; 4508 u8 val, val_mcs13; 4509 int sts = 8; 4510 4511 if (chip->chip_gen == RTW89_CHIP_AX) 4512 return; 4513 4514 if (hal->no_mcs_12_13) 4515 support_mcs_12_13 = false; 4516 4517 if (band == NL80211_BAND_6GHZ && 4518 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 4519 support_320mhz = true; 4520 4521 eht_cap = &iftype_data->eht_cap; 4522 eht_cap_elem = &eht_cap->eht_cap_elem; 4523 eht_nss = &eht_cap->eht_mcs_nss_supp; 4524 4525 eht_cap->has_eht = true; 4526 4527 eht_cap_elem->mac_cap_info[0] = 4528 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 4529 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 4530 eht_cap_elem->mac_cap_info[1] = 0; 4531 4532 eht_cap_elem->phy_cap_info[0] = 4533 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 4534 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 4535 if (support_320mhz) 4536 eht_cap_elem->phy_cap_info[0] |= 4537 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 4538 4539 eht_cap_elem->phy_cap_info[0] |= 4540 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 4541 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 4542 eht_cap_elem->phy_cap_info[1] = 4543 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 4544 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 4545 u8_encode_bits(sts - 1, 4546 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 4547 if (support_320mhz) 4548 eht_cap_elem->phy_cap_info[1] |= 4549 u8_encode_bits(sts - 1, 4550 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 4551 4552 eht_cap_elem->phy_cap_info[2] = 0; 4553 4554 eht_cap_elem->phy_cap_info[3] = 4555 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 4556 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 4557 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 4558 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 4559 4560 eht_cap_elem->phy_cap_info[4] = 4561 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 4562 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 4563 4564 eht_cap_elem->phy_cap_info[5] = 4565 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 4566 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 4567 4568 eht_cap_elem->phy_cap_info[6] = 0; 4569 eht_cap_elem->phy_cap_info[7] = 0; 4570 eht_cap_elem->phy_cap_info[8] = 0; 4571 4572 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 4573 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 4574 val_mcs13 = support_mcs_12_13 ? val : 0; 4575 4576 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 4577 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 4578 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13; 4579 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 4580 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 4581 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13; 4582 if (support_320mhz) { 4583 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 4584 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 4585 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13; 4586 } 4587 } 4588 4589 #define RTW89_SBAND_IFTYPES_NR 2 4590 4591 static int rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 4592 enum nl80211_band band, 4593 struct ieee80211_supported_band *sband) 4594 { 4595 struct ieee80211_sband_iftype_data *iftype_data; 4596 enum nl80211_iftype iftype; 4597 int idx = 0; 4598 4599 iftype_data = devm_kcalloc(rtwdev->dev, RTW89_SBAND_IFTYPES_NR, 4600 sizeof(*iftype_data), GFP_KERNEL); 4601 if (!iftype_data) 4602 return -ENOMEM; 4603 4604 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 4605 switch (iftype) { 4606 case NL80211_IFTYPE_STATION: 4607 case NL80211_IFTYPE_AP: 4608 break; 4609 default: 4610 continue; 4611 } 4612 4613 if (idx >= RTW89_SBAND_IFTYPES_NR) { 4614 rtw89_warn(rtwdev, "run out of iftype_data\n"); 4615 break; 4616 } 4617 4618 iftype_data[idx].types_mask = BIT(iftype); 4619 4620 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 4621 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 4622 4623 idx++; 4624 } 4625 4626 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 4627 return 0; 4628 } 4629 4630 static struct ieee80211_supported_band * 4631 rtw89_core_sband_dup(struct rtw89_dev *rtwdev, 4632 const struct ieee80211_supported_band *sband) 4633 { 4634 struct ieee80211_supported_band *dup; 4635 4636 dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL); 4637 if (!dup) 4638 return NULL; 4639 4640 dup->channels = devm_kmemdup(rtwdev->dev, sband->channels, 4641 sizeof(*sband->channels) * sband->n_channels, 4642 GFP_KERNEL); 4643 if (!dup->channels) 4644 return NULL; 4645 4646 dup->bitrates = devm_kmemdup(rtwdev->dev, sband->bitrates, 4647 sizeof(*sband->bitrates) * sband->n_bitrates, 4648 GFP_KERNEL); 4649 if (!dup->bitrates) 4650 return NULL; 4651 4652 return dup; 4653 } 4654 4655 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 4656 { 4657 struct ieee80211_hw *hw = rtwdev->hw; 4658 struct ieee80211_supported_band *sband; 4659 u8 support_bands = rtwdev->chip->support_bands; 4660 int ret; 4661 4662 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 4663 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_2ghz); 4664 if (!sband) 4665 return -ENOMEM; 4666 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 4667 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband); 4668 if (ret) 4669 return ret; 4670 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 4671 } 4672 4673 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 4674 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_5ghz); 4675 if (!sband) 4676 return -ENOMEM; 4677 rtw89_init_ht_cap(rtwdev, &sband->ht_cap); 4678 rtw89_init_vht_cap(rtwdev, &sband->vht_cap); 4679 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband); 4680 if (ret) 4681 return ret; 4682 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 4683 } 4684 4685 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 4686 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_6ghz); 4687 if (!sband) 4688 return -ENOMEM; 4689 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband); 4690 if (ret) 4691 return ret; 4692 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband; 4693 } 4694 4695 return 0; 4696 } 4697 4698 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 4699 { 4700 int i; 4701 4702 for (i = 0; i < RTW89_PHY_NUM; i++) 4703 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4704 for (i = 0; i < RTW89_PHY_NUM; i++) 4705 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4706 } 4707 4708 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 4709 { 4710 struct rtw89_dev *rtwdev; 4711 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link, 4712 update_beacon_work); 4713 4714 lockdep_assert_wiphy(wiphy); 4715 4716 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4717 return; 4718 4719 rtwdev = rtwvif_link->rtwvif->rtwdev; 4720 4721 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 4722 } 4723 4724 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 4725 { 4726 struct rtw89_vif_link *rtwvif_link = 4727 container_of(work, struct rtw89_vif_link, csa_beacon_work.work); 4728 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 4729 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4730 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 4731 struct ieee80211_bss_conf *bss_conf; 4732 unsigned int delay; 4733 4734 lockdep_assert_wiphy(wiphy); 4735 4736 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4737 return; 4738 4739 rcu_read_lock(); 4740 4741 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4742 if (!bss_conf->csa_active) { 4743 rcu_read_unlock(); 4744 return; 4745 } 4746 4747 delay = ieee80211_tu_to_usec(bss_conf->beacon_int); 4748 4749 rcu_read_unlock(); 4750 4751 if (!ieee80211_beacon_cntdwn_is_complete(vif, rtwvif_link->link_id)) { 4752 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 4753 4754 wiphy_delayed_work_queue(wiphy, &rtwvif_link->csa_beacon_work, 4755 usecs_to_jiffies(delay)); 4756 } else { 4757 ieee80211_csa_finish(vif, rtwvif_link->link_id); 4758 } 4759 } 4760 4761 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4762 { 4763 struct completion *cmpl = &wait->completion; 4764 unsigned long time_left; 4765 unsigned int cur; 4766 4767 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4768 if (cur != RTW89_WAIT_COND_IDLE) 4769 return -EBUSY; 4770 4771 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4772 if (time_left == 0) { 4773 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4774 return -ETIMEDOUT; 4775 } 4776 4777 if (wait->data.err) 4778 return -EFAULT; 4779 4780 return 0; 4781 } 4782 4783 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4784 const struct rtw89_completion_data *data) 4785 { 4786 unsigned int cur; 4787 4788 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4789 if (cur != cond) 4790 return; 4791 4792 wait->data = *data; 4793 complete(&wait->completion); 4794 } 4795 4796 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4797 { 4798 u16 bt_req_len; 4799 4800 switch (event) { 4801 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4802 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4803 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4804 "coex updates BT req len to %d TU\n", bt_req_len); 4805 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4806 break; 4807 default: 4808 if (event < NUM_OF_RTW89_BTC_HMSG) 4809 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4810 "unhandled BTC HMSG event: %d\n", event); 4811 else 4812 rtw89_warn(rtwdev, 4813 "unrecognized BTC HMSG event: %d\n", event); 4814 break; 4815 } 4816 } 4817 4818 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4819 { 4820 const struct dmi_system_id *match; 4821 enum rtw89_quirks quirk; 4822 4823 if (!quirks) 4824 return; 4825 4826 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4827 quirk = (uintptr_t)match->driver_data; 4828 if (quirk >= NUM_OF_RTW89_QUIRKS) 4829 continue; 4830 4831 set_bit(quirk, rtwdev->quirks); 4832 } 4833 } 4834 EXPORT_SYMBOL(rtw89_check_quirks); 4835 4836 int rtw89_core_start(struct rtw89_dev *rtwdev) 4837 { 4838 int ret; 4839 4840 ret = rtw89_mac_init(rtwdev); 4841 if (ret) { 4842 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4843 return ret; 4844 } 4845 4846 rtw89_btc_ntfy_poweron(rtwdev); 4847 4848 /* efuse process */ 4849 4850 /* pre-config BB/RF, BB reset/RFC reset */ 4851 ret = rtw89_chip_reset_bb_rf(rtwdev); 4852 if (ret) 4853 return ret; 4854 4855 rtw89_phy_init_bb_reg(rtwdev); 4856 rtw89_chip_bb_postinit(rtwdev); 4857 rtw89_phy_init_rf_reg(rtwdev, false); 4858 4859 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4860 4861 rtw89_phy_dm_init(rtwdev); 4862 4863 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true); 4864 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true); 4865 rtw89_mac_update_rts_threshold(rtwdev); 4866 4867 ret = rtw89_hci_start(rtwdev); 4868 if (ret) { 4869 rtw89_err(rtwdev, "failed to start hci\n"); 4870 return ret; 4871 } 4872 4873 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work, 4874 RTW89_TRACK_WORK_PERIOD); 4875 4876 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4877 4878 rtw89_chip_rfk_init_late(rtwdev); 4879 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4880 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4881 rtw89_fw_h2c_init_ba_cam(rtwdev); 4882 4883 return 0; 4884 } 4885 4886 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4887 { 4888 struct wiphy *wiphy = rtwdev->hw->wiphy; 4889 struct rtw89_btc *btc = &rtwdev->btc; 4890 4891 lockdep_assert_wiphy(wiphy); 4892 4893 /* Prvent to stop twice; enter_ips and ops_stop */ 4894 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4895 return; 4896 4897 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4898 4899 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4900 4901 wiphy_work_cancel(wiphy, &rtwdev->c2h_work); 4902 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work); 4903 wiphy_work_cancel(wiphy, &btc->eapol_notify_work); 4904 wiphy_work_cancel(wiphy, &btc->arp_notify_work); 4905 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work); 4906 wiphy_work_cancel(wiphy, &btc->icmp_notify_work); 4907 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4908 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work); 4909 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work); 4910 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work); 4911 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work); 4912 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work); 4913 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work); 4914 wiphy_delayed_work_cancel(wiphy, &rtwdev->mcc_prepare_done_work); 4915 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4916 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work); 4917 4918 rtw89_btc_ntfy_poweroff(rtwdev); 4919 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4920 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4921 rtw89_hci_stop(rtwdev); 4922 rtw89_hci_deinit(rtwdev); 4923 rtw89_mac_pwr_off(rtwdev); 4924 rtw89_hci_reset(rtwdev); 4925 } 4926 4927 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 4928 { 4929 const struct rtw89_chip_info *chip = rtwdev->chip; 4930 u8 mac_id_num; 4931 u8 mac_id; 4932 4933 if (rtwdev->support_mlo) 4934 mac_id_num = chip->support_macid_num / chip->support_link_num; 4935 else 4936 mac_id_num = chip->support_macid_num; 4937 4938 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 4939 if (mac_id == mac_id_num) 4940 return RTW89_MAX_MAC_ID_NUM; 4941 4942 set_bit(mac_id, rtwdev->mac_id_map); 4943 return mac_id; 4944 } 4945 4946 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 4947 { 4948 clear_bit(mac_id, rtwdev->mac_id_map); 4949 } 4950 4951 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4952 u8 mac_id, u8 port) 4953 { 4954 const struct rtw89_chip_info *chip = rtwdev->chip; 4955 u8 support_link_num = chip->support_link_num; 4956 u8 support_mld_num = 0; 4957 unsigned int link_id; 4958 u8 index; 4959 4960 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 4961 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 4962 rtwvif->links[link_id] = NULL; 4963 4964 rtwvif->rtwdev = rtwdev; 4965 4966 if (rtwdev->support_mlo) { 4967 rtwvif->links_inst_valid_num = support_link_num; 4968 support_mld_num = chip->support_macid_num / support_link_num; 4969 } else { 4970 rtwvif->links_inst_valid_num = 1; 4971 } 4972 4973 for (index = 0; index < rtwvif->links_inst_valid_num; index++) { 4974 struct rtw89_vif_link *inst = &rtwvif->links_inst[index]; 4975 4976 inst->rtwvif = rtwvif; 4977 inst->mac_id = mac_id + index * support_mld_num; 4978 inst->mac_idx = RTW89_MAC_0 + index; 4979 inst->phy_idx = RTW89_PHY_0 + index; 4980 4981 /* multi-link use the same port id on different HW bands */ 4982 inst->port = port; 4983 } 4984 } 4985 4986 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4987 struct rtw89_sta *rtwsta, u8 mac_id) 4988 { 4989 const struct rtw89_chip_info *chip = rtwdev->chip; 4990 u8 support_link_num = chip->support_link_num; 4991 u8 support_mld_num = 0; 4992 unsigned int link_id; 4993 u8 index; 4994 4995 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 4996 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 4997 rtwsta->links[link_id] = NULL; 4998 4999 rtwsta->rtwdev = rtwdev; 5000 rtwsta->rtwvif = rtwvif; 5001 5002 if (rtwdev->support_mlo) { 5003 rtwsta->links_inst_valid_num = support_link_num; 5004 support_mld_num = chip->support_macid_num / support_link_num; 5005 } else { 5006 rtwsta->links_inst_valid_num = 1; 5007 } 5008 5009 for (index = 0; index < rtwsta->links_inst_valid_num; index++) { 5010 struct rtw89_sta_link *inst = &rtwsta->links_inst[index]; 5011 5012 inst->rtwvif_link = &rtwvif->links_inst[index]; 5013 5014 inst->rtwsta = rtwsta; 5015 inst->mac_id = mac_id + index * support_mld_num; 5016 } 5017 } 5018 5019 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 5020 unsigned int link_id) 5021 { 5022 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 5023 u8 index; 5024 int ret; 5025 5026 if (rtwvif_link) 5027 return rtwvif_link; 5028 5029 index = find_first_zero_bit(rtwvif->links_inst_map, 5030 rtwvif->links_inst_valid_num); 5031 if (index == rtwvif->links_inst_valid_num) { 5032 ret = -EBUSY; 5033 goto err; 5034 } 5035 5036 rtwvif_link = &rtwvif->links_inst[index]; 5037 rtwvif_link->link_id = link_id; 5038 5039 set_bit(index, rtwvif->links_inst_map); 5040 rtwvif->links[link_id] = rtwvif_link; 5041 list_add_tail(&rtwvif_link->dlink_schd, &rtwvif->dlink_pool); 5042 return rtwvif_link; 5043 5044 err: 5045 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n", 5046 link_id, ret); 5047 return NULL; 5048 } 5049 5050 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id) 5051 { 5052 struct rtw89_vif_link **container = &rtwvif->links[link_id]; 5053 struct rtw89_vif_link *link = *container; 5054 u8 index; 5055 5056 if (!link) 5057 return; 5058 5059 index = rtw89_vif_link_inst_get_index(link); 5060 clear_bit(index, rtwvif->links_inst_map); 5061 *container = NULL; 5062 list_del(&link->dlink_schd); 5063 } 5064 5065 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 5066 unsigned int link_id) 5067 { 5068 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 5069 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 5070 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id]; 5071 u8 index; 5072 int ret; 5073 5074 if (rtwsta_link) 5075 return rtwsta_link; 5076 5077 if (!rtwvif_link) { 5078 ret = -ENOLINK; 5079 goto err; 5080 } 5081 5082 index = rtw89_vif_link_inst_get_index(rtwvif_link); 5083 if (test_bit(index, rtwsta->links_inst_map)) { 5084 ret = -EBUSY; 5085 goto err; 5086 } 5087 5088 rtwsta_link = &rtwsta->links_inst[index]; 5089 rtwsta_link->link_id = link_id; 5090 5091 set_bit(index, rtwsta->links_inst_map); 5092 rtwsta->links[link_id] = rtwsta_link; 5093 list_add_tail(&rtwsta_link->dlink_schd, &rtwsta->dlink_pool); 5094 return rtwsta_link; 5095 5096 err: 5097 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n", 5098 link_id, ret); 5099 return NULL; 5100 } 5101 5102 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id) 5103 { 5104 struct rtw89_sta_link **container = &rtwsta->links[link_id]; 5105 struct rtw89_sta_link *link = *container; 5106 u8 index; 5107 5108 if (!link) 5109 return; 5110 5111 index = rtw89_sta_link_inst_get_index(link); 5112 clear_bit(index, rtwsta->links_inst_map); 5113 *container = NULL; 5114 list_del(&link->dlink_schd); 5115 } 5116 5117 int rtw89_core_init(struct rtw89_dev *rtwdev) 5118 { 5119 struct rtw89_btc *btc = &rtwdev->btc; 5120 u8 band; 5121 5122 INIT_LIST_HEAD(&rtwdev->ba_list); 5123 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 5124 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 5125 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 5126 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 5127 if (!(rtwdev->chip->support_bands & BIT(band))) 5128 continue; 5129 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 5130 } 5131 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list); 5132 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 5133 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 5134 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 5135 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work); 5136 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work); 5137 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 5138 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 5139 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 5140 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 5141 wiphy_delayed_work_init(&rtwdev->mcc_prepare_done_work, rtw89_mcc_prepare_done_work); 5142 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 5143 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 5144 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 5145 if (!rtwdev->txq_wq) 5146 return -ENOMEM; 5147 spin_lock_init(&rtwdev->ba_lock); 5148 spin_lock_init(&rtwdev->rpwm_lock); 5149 mutex_init(&rtwdev->rf_mutex); 5150 rtwdev->total_sta_assoc = 0; 5151 5152 rtw89_init_wait(&rtwdev->mcc.wait); 5153 rtw89_init_wait(&rtwdev->mlo.wait); 5154 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 5155 rtw89_init_wait(&rtwdev->wow.wait); 5156 rtw89_init_wait(&rtwdev->mac.ps_wait); 5157 5158 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work); 5159 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work); 5160 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 5161 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 5162 5163 skb_queue_head_init(&rtwdev->c2h_queue); 5164 rtw89_core_ppdu_sts_init(rtwdev); 5165 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 5166 5167 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 5168 rtwdev->dbcc_en = false; 5169 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 5170 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 5171 5172 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 5173 rtwdev->dbcc_en = true; 5174 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 5175 rtwdev->mlo_dbcc_mode = MLO_1_PLUS_1_1RF; 5176 } 5177 5178 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0; 5179 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1; 5180 5181 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 5182 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 5183 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 5184 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 5185 5186 init_completion(&rtwdev->fw.req.completion); 5187 init_completion(&rtwdev->rfk_wait.completion); 5188 5189 schedule_work(&rtwdev->load_firmware_work); 5190 5191 rtw89_ser_init(rtwdev); 5192 rtw89_entity_init(rtwdev); 5193 rtw89_sar_init(rtwdev); 5194 rtw89_phy_ant_gain_init(rtwdev); 5195 5196 return 0; 5197 } 5198 EXPORT_SYMBOL(rtw89_core_init); 5199 5200 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 5201 { 5202 rtw89_ser_deinit(rtwdev); 5203 rtw89_unload_firmware(rtwdev); 5204 __rtw89_fw_free_all_early_h2c(rtwdev); 5205 5206 destroy_workqueue(rtwdev->txq_wq); 5207 mutex_destroy(&rtwdev->rf_mutex); 5208 } 5209 EXPORT_SYMBOL(rtw89_core_deinit); 5210 5211 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 5212 const u8 *mac_addr, bool hw_scan) 5213 { 5214 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 5215 rtwvif_link->chanctx_idx); 5216 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5217 5218 rtwdev->scanning = true; 5219 5220 ether_addr_copy(rtwvif_link->mac_addr, mac_addr); 5221 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type); 5222 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true); 5223 rtw89_hci_recalc_int_mit(rtwdev); 5224 rtw89_phy_config_edcca(rtwdev, bb, true); 5225 rtw89_tas_scan(rtwdev, true); 5226 5227 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr); 5228 } 5229 5230 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 5231 struct rtw89_vif_link *rtwvif_link, bool hw_scan) 5232 { 5233 struct ieee80211_bss_conf *bss_conf; 5234 struct rtw89_bb_ctx *bb; 5235 int ret; 5236 5237 if (!rtwvif_link) 5238 return; 5239 5240 rcu_read_lock(); 5241 5242 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 5243 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr); 5244 5245 rcu_read_unlock(); 5246 5247 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 5248 5249 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false); 5250 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx); 5251 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 5252 rtw89_phy_config_edcca(rtwdev, bb, false); 5253 rtw89_tas_scan(rtwdev, false); 5254 5255 if (hw_scan) { 5256 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, false, false, 5257 RTW89_SCAN_NULL_TIMEOUT); 5258 if (ret) 5259 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 5260 "scan send null-0 failed: %d\n", ret); 5261 } 5262 5263 rtwdev->scanning = false; 5264 rtw89_for_each_active_bb(rtwdev, bb) 5265 bb->dig.bypass_dig = true; 5266 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 5267 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work); 5268 } 5269 5270 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 5271 { 5272 const struct rtw89_chip_info *chip = rtwdev->chip; 5273 int ret; 5274 u8 val; 5275 u8 cv; 5276 5277 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 5278 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 5279 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 5280 cv = CHIP_CAV; 5281 else 5282 cv = CHIP_CBV; 5283 } 5284 5285 rtwdev->hal.cv = cv; 5286 5287 if (rtw89_is_rtl885xb(rtwdev)) { 5288 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 5289 if (ret) 5290 return; 5291 5292 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 5293 } 5294 } 5295 5296 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 5297 { 5298 const struct rtw89_chip_info *chip = rtwdev->chip; 5299 5300 rtwdev->hal.support_cckpd = 5301 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 5302 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 5303 rtwdev->hal.support_igi = 5304 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 5305 5306 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks)) 5307 rtwdev->hal.thermal_prot_th = chip->thermal_th[1]; 5308 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks)) 5309 rtwdev->hal.thermal_prot_th = chip->thermal_th[0]; 5310 else 5311 rtwdev->hal.thermal_prot_th = 0; 5312 } 5313 5314 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 5315 { 5316 const struct rtw89_chip_info *chip = rtwdev->chip; 5317 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 5318 struct rtw89_efuse *efuse = &rtwdev->efuse; 5319 const struct rtw89_rfe_parms *sel; 5320 u8 rfe_type = efuse->rfe_type; 5321 5322 if (!conf) { 5323 sel = chip->dflt_parms; 5324 goto out; 5325 } 5326 5327 while (conf->rfe_parms) { 5328 if (rfe_type == conf->rfe_type) { 5329 sel = conf->rfe_parms; 5330 goto out; 5331 } 5332 conf++; 5333 } 5334 5335 sel = chip->dflt_parms; 5336 5337 out: 5338 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 5339 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 5340 } 5341 5342 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 5343 unsigned int link_id) 5344 { 5345 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 5346 u16 usable_links = ieee80211_vif_usable_links(vif); 5347 u16 active_links = vif->active_links; 5348 struct rtw89_vif_link *target, *cur; 5349 int ret; 5350 5351 lockdep_assert_wiphy(rtwdev->hw->wiphy); 5352 5353 if (unlikely(!ieee80211_vif_is_mld(vif))) 5354 return -EOPNOTSUPP; 5355 5356 if (unlikely(link_id >= IEEE80211_MLD_MAX_NUM_LINKS || 5357 !(usable_links & BIT(link_id)))) { 5358 rtw89_warn(rtwdev, "%s: link id %u is not usable\n", __func__, 5359 link_id); 5360 return -ENOLINK; 5361 } 5362 5363 if (active_links == BIT(link_id)) 5364 return 0; 5365 5366 rtw89_debug(rtwdev, RTW89_DBG_STATE, "%s: switch to link id %u MLSR\n", 5367 __func__, link_id); 5368 5369 rtw89_leave_lps(rtwdev); 5370 5371 ieee80211_stop_queues(rtwdev->hw); 5372 flush_work(&rtwdev->txq_work); 5373 5374 cur = rtw89_get_designated_link(rtwvif); 5375 5376 ret = ieee80211_set_active_links(vif, active_links | BIT(link_id)); 5377 if (ret) { 5378 rtw89_err(rtwdev, "%s: failed to activate link id %u\n", 5379 __func__, link_id); 5380 goto wake_queue; 5381 } 5382 5383 target = rtwvif->links[link_id]; 5384 if (unlikely(!target)) { 5385 rtw89_err(rtwdev, "%s: failed to confirm link id %u\n", 5386 __func__, link_id); 5387 5388 ieee80211_set_active_links(vif, active_links); 5389 ret = -EFAULT; 5390 goto wake_queue; 5391 } 5392 5393 if (likely(cur)) 5394 rtw89_fw_h2c_mlo_link_cfg(rtwdev, cur, false); 5395 5396 rtw89_fw_h2c_mlo_link_cfg(rtwdev, target, true); 5397 5398 ret = ieee80211_set_active_links(vif, BIT(link_id)); 5399 if (ret) 5400 rtw89_err(rtwdev, "%s: failed to inactivate links 0x%x\n", 5401 __func__, active_links); 5402 5403 rtw89_chip_rfk_channel(rtwdev, target); 5404 5405 rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR; 5406 5407 wake_queue: 5408 ieee80211_wake_queues(rtwdev->hw); 5409 5410 return ret; 5411 } 5412 5413 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 5414 { 5415 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5416 int ret; 5417 5418 ret = rtw89_mac_partial_init(rtwdev, false); 5419 if (ret) 5420 return ret; 5421 5422 ret = mac->parse_efuse_map(rtwdev); 5423 if (ret) 5424 return ret; 5425 5426 ret = mac->parse_phycap_map(rtwdev); 5427 if (ret) 5428 return ret; 5429 5430 ret = rtw89_mac_setup_phycap(rtwdev); 5431 if (ret) 5432 return ret; 5433 5434 rtw89_core_setup_phycap(rtwdev); 5435 5436 rtw89_hci_mac_pre_deinit(rtwdev); 5437 5438 return 0; 5439 } 5440 5441 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 5442 { 5443 rtw89_chip_fem_setup(rtwdev); 5444 5445 return 0; 5446 } 5447 5448 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev) 5449 { 5450 return !!rtwdev->chip->rfkill_init; 5451 } 5452 5453 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev) 5454 { 5455 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init; 5456 5457 rtw89_write16_mask(rtwdev, regs->pinmux.addr, 5458 regs->pinmux.mask, regs->pinmux.data); 5459 rtw89_write16_mask(rtwdev, regs->mode.addr, 5460 regs->mode.mask, regs->mode.data); 5461 } 5462 5463 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev) 5464 { 5465 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get; 5466 5467 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask); 5468 } 5469 5470 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev) 5471 { 5472 if (!rtw89_chip_has_rfkill(rtwdev)) 5473 return; 5474 5475 rtw89_core_rfkill_init(rtwdev); 5476 rtw89_core_rfkill_poll(rtwdev, true); 5477 wiphy_rfkill_start_polling(rtwdev->hw->wiphy); 5478 } 5479 5480 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev) 5481 { 5482 if (!rtw89_chip_has_rfkill(rtwdev)) 5483 return; 5484 5485 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy); 5486 } 5487 5488 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force) 5489 { 5490 bool prev, blocked; 5491 5492 if (!rtw89_chip_has_rfkill(rtwdev)) 5493 return; 5494 5495 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5496 blocked = rtw89_core_rfkill_get(rtwdev); 5497 5498 if (!force && prev == blocked) 5499 return; 5500 5501 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n", 5502 blocked ? "disable" : "enable"); 5503 5504 if (blocked) 5505 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5506 else 5507 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5508 5509 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked); 5510 } 5511 5512 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 5513 { 5514 int ret; 5515 5516 rtw89_read_chip_ver(rtwdev); 5517 5518 ret = rtw89_mac_pwr_on(rtwdev); 5519 if (ret) { 5520 rtw89_err(rtwdev, "failed to power on\n"); 5521 return ret; 5522 } 5523 5524 ret = rtw89_wait_firmware_completion(rtwdev); 5525 if (ret) { 5526 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 5527 goto out; 5528 } 5529 5530 ret = rtw89_fw_recognize(rtwdev); 5531 if (ret) { 5532 rtw89_err(rtwdev, "failed to recognize firmware\n"); 5533 goto out; 5534 } 5535 5536 ret = rtw89_chip_efuse_info_setup(rtwdev); 5537 if (ret) 5538 goto out; 5539 5540 ret = rtw89_fw_recognize_elements(rtwdev); 5541 if (ret) { 5542 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 5543 goto out; 5544 } 5545 5546 ret = rtw89_chip_board_info_setup(rtwdev); 5547 if (ret) 5548 goto out; 5549 5550 rtw89_core_setup_rfe_parms(rtwdev); 5551 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 5552 5553 out: 5554 rtw89_mac_pwr_off(rtwdev); 5555 5556 return ret; 5557 } 5558 EXPORT_SYMBOL(rtw89_chip_info_setup); 5559 5560 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5561 struct rtw89_vif_link *rtwvif_link) 5562 { 5563 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5564 const struct rtw89_chip_info *chip = rtwdev->chip; 5565 struct ieee80211_bss_conf *bss_conf; 5566 5567 rcu_read_lock(); 5568 5569 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 5570 if (!bss_conf->he_support || !vif->cfg.assoc) { 5571 rcu_read_unlock(); 5572 return; 5573 } 5574 5575 rcu_read_unlock(); 5576 5577 if (chip->ops->set_txpwr_ul_tb_offset) 5578 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx); 5579 } 5580 5581 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 5582 { 5583 const struct rtw89_chip_info *chip = rtwdev->chip; 5584 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1; 5585 struct ieee80211_hw *hw = rtwdev->hw; 5586 struct rtw89_efuse *efuse = &rtwdev->efuse; 5587 struct rtw89_hal *hal = &rtwdev->hal; 5588 int ret; 5589 int tx_headroom = IEEE80211_HT_CTL_LEN; 5590 5591 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n); 5592 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n); 5593 hw->txq_data_size = sizeof(struct rtw89_txq); 5594 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 5595 5596 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 5597 5598 hw->extra_tx_headroom = tx_headroom; 5599 hw->queues = IEEE80211_NUM_ACS; 5600 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 5601 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 5602 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 5603 5604 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 5605 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 5606 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 5607 5608 ieee80211_hw_set(hw, SIGNAL_DBM); 5609 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 5610 ieee80211_hw_set(hw, MFP_CAPABLE); 5611 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 5612 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 5613 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 5614 ieee80211_hw_set(hw, TX_AMSDU); 5615 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 5616 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 5617 ieee80211_hw_set(hw, SUPPORTS_PS); 5618 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 5619 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 5620 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 5621 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 5622 ieee80211_hw_set(hw, CHANCTX_STA_CSA); 5623 5624 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5625 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 5626 5627 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 5628 ieee80211_hw_set(hw, CONNECTION_MONITOR); 5629 5630 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw)) 5631 ieee80211_hw_set(hw, AP_LINK_PS); 5632 5633 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 5634 BIT(NL80211_IFTYPE_AP) | 5635 BIT(NL80211_IFTYPE_P2P_CLIENT) | 5636 BIT(NL80211_IFTYPE_P2P_GO); 5637 5638 if (hal->ant_diversity) { 5639 hw->wiphy->available_antennas_tx = 0x3; 5640 hw->wiphy->available_antennas_rx = 0x3; 5641 } else { 5642 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 5643 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 5644 } 5645 5646 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 5647 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 5648 WIPHY_FLAG_AP_UAPSD | 5649 WIPHY_FLAG_HAS_CHANNEL_SWITCH | 5650 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 5651 5652 if (!chip->support_rnr) 5653 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 5654 5655 if (chip->chip_gen == RTW89_CHIP_BE) 5656 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 5657 5658 if (rtwdev->support_mlo) { 5659 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; 5660 hw->wiphy->iftype_ext_capab = rtw89_iftypes_ext_capa; 5661 hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(rtw89_iftypes_ext_capa); 5662 } 5663 5664 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 5665 5666 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5667 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 5668 5669 #ifdef CONFIG_PM 5670 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 5671 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5672 #endif 5673 5674 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5675 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5676 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5677 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5678 hw->wiphy->max_remain_on_channel_duration = 1000; 5679 5680 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 5681 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 5682 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 5683 5684 ret = rtw89_core_set_supported_band(rtwdev); 5685 if (ret) { 5686 rtw89_err(rtwdev, "failed to set supported band\n"); 5687 return ret; 5688 } 5689 5690 ret = rtw89_regd_setup(rtwdev); 5691 if (ret) { 5692 rtw89_err(rtwdev, "failed to set up regd\n"); 5693 return ret; 5694 } 5695 5696 hw->wiphy->sar_capa = &rtw89_sar_capa; 5697 5698 ret = ieee80211_register_hw(hw); 5699 if (ret) { 5700 rtw89_err(rtwdev, "failed to register hw\n"); 5701 return ret; 5702 } 5703 5704 ret = rtw89_regd_init_hint(rtwdev); 5705 if (ret) { 5706 rtw89_err(rtwdev, "failed to init regd\n"); 5707 goto err_unregister_hw; 5708 } 5709 5710 rtw89_rfkill_polling_init(rtwdev); 5711 5712 return 0; 5713 5714 err_unregister_hw: 5715 ieee80211_unregister_hw(hw); 5716 5717 return ret; 5718 } 5719 5720 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 5721 { 5722 struct ieee80211_hw *hw = rtwdev->hw; 5723 5724 rtw89_rfkill_polling_deinit(rtwdev); 5725 ieee80211_unregister_hw(hw); 5726 } 5727 5728 int rtw89_core_register(struct rtw89_dev *rtwdev) 5729 { 5730 int ret; 5731 5732 ret = rtw89_core_register_hw(rtwdev); 5733 if (ret) { 5734 rtw89_err(rtwdev, "failed to register core hw\n"); 5735 return ret; 5736 } 5737 5738 rtw89_debugfs_init(rtwdev); 5739 5740 return 0; 5741 } 5742 EXPORT_SYMBOL(rtw89_core_register); 5743 5744 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 5745 { 5746 rtw89_core_unregister_hw(rtwdev); 5747 5748 rtw89_debugfs_deinit(rtwdev); 5749 } 5750 EXPORT_SYMBOL(rtw89_core_unregister); 5751 5752 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5753 u32 bus_data_size, 5754 const struct rtw89_chip_info *chip, 5755 const struct rtw89_chip_variant *variant) 5756 { 5757 struct rtw89_fw_info early_fw = {}; 5758 const struct firmware *firmware; 5759 struct ieee80211_hw *hw; 5760 struct rtw89_dev *rtwdev; 5761 struct ieee80211_ops *ops; 5762 u32 driver_data_size; 5763 int fw_format = -1; 5764 bool support_mlo; 5765 bool no_chanctx; 5766 5767 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 5768 5769 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 5770 if (!ops) 5771 goto err; 5772 5773 no_chanctx = chip->support_chanctx_num == 0 || 5774 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 5775 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 5776 5777 if (no_chanctx) { 5778 ops->add_chanctx = ieee80211_emulate_add_chanctx; 5779 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 5780 ops->change_chanctx = ieee80211_emulate_change_chanctx; 5781 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 5782 ops->assign_vif_chanctx = NULL; 5783 ops->unassign_vif_chanctx = NULL; 5784 ops->remain_on_channel = NULL; 5785 ops->cancel_remain_on_channel = NULL; 5786 } 5787 5788 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 5789 hw = ieee80211_alloc_hw(driver_data_size, ops); 5790 if (!hw) 5791 goto err; 5792 5793 /* Currently, our AP_LINK_PS handling only works for non-MLD softap 5794 * or MLD-single-link softap. If RTW89_MLD_NON_STA_LINK_NUM enlarges, 5795 * please tweak entire AP_LINKS_PS handling before supporting MLO. 5796 */ 5797 support_mlo = !no_chanctx && chip->support_link_num && 5798 RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &early_fw) && 5799 RTW89_MLD_NON_STA_LINK_NUM == 1; 5800 5801 hw->wiphy->iface_combinations = rtw89_iface_combs; 5802 5803 if (no_chanctx || chip->support_chanctx_num == 1) 5804 hw->wiphy->n_iface_combinations = 1; 5805 else 5806 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 5807 5808 rtwdev = hw->priv; 5809 rtwdev->hw = hw; 5810 rtwdev->dev = device; 5811 rtwdev->ops = ops; 5812 rtwdev->chip = chip; 5813 rtwdev->variant = variant; 5814 rtwdev->fw.req.firmware = firmware; 5815 rtwdev->fw.fw_format = fw_format; 5816 rtwdev->support_mlo = support_mlo; 5817 5818 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n", 5819 no_chanctx ? "without" : "with"); 5820 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n", 5821 support_mlo ? "with" : "without"); 5822 5823 return rtwdev; 5824 5825 err: 5826 kfree(ops); 5827 release_firmware(firmware); 5828 return NULL; 5829 } 5830 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 5831 5832 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 5833 { 5834 kfree(rtwdev->ops); 5835 kfree(rtwdev->rfe_data); 5836 release_firmware(rtwdev->fw.req.firmware); 5837 ieee80211_free_hw(rtwdev->hw); 5838 } 5839 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 5840 5841 MODULE_AUTHOR("Realtek Corporation"); 5842 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 5843 MODULE_LICENSE("Dual BSD/GPL"); 5844