1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 #include "wow.h" 22 23 static bool rtw89_disable_ps_mode; 24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 26 27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 37 38 static struct ieee80211_channel rtw89_channels_2ghz[] = { 39 RTW89_DEF_CHAN_2G(2412, 1), 40 RTW89_DEF_CHAN_2G(2417, 2), 41 RTW89_DEF_CHAN_2G(2422, 3), 42 RTW89_DEF_CHAN_2G(2427, 4), 43 RTW89_DEF_CHAN_2G(2432, 5), 44 RTW89_DEF_CHAN_2G(2437, 6), 45 RTW89_DEF_CHAN_2G(2442, 7), 46 RTW89_DEF_CHAN_2G(2447, 8), 47 RTW89_DEF_CHAN_2G(2452, 9), 48 RTW89_DEF_CHAN_2G(2457, 10), 49 RTW89_DEF_CHAN_2G(2462, 11), 50 RTW89_DEF_CHAN_2G(2467, 12), 51 RTW89_DEF_CHAN_2G(2472, 13), 52 RTW89_DEF_CHAN_2G(2484, 14), 53 }; 54 55 static struct ieee80211_channel rtw89_channels_5ghz[] = { 56 RTW89_DEF_CHAN_5G(5180, 36), 57 RTW89_DEF_CHAN_5G(5200, 40), 58 RTW89_DEF_CHAN_5G(5220, 44), 59 RTW89_DEF_CHAN_5G(5240, 48), 60 RTW89_DEF_CHAN_5G(5260, 52), 61 RTW89_DEF_CHAN_5G(5280, 56), 62 RTW89_DEF_CHAN_5G(5300, 60), 63 RTW89_DEF_CHAN_5G(5320, 64), 64 RTW89_DEF_CHAN_5G(5500, 100), 65 RTW89_DEF_CHAN_5G(5520, 104), 66 RTW89_DEF_CHAN_5G(5540, 108), 67 RTW89_DEF_CHAN_5G(5560, 112), 68 RTW89_DEF_CHAN_5G(5580, 116), 69 RTW89_DEF_CHAN_5G(5600, 120), 70 RTW89_DEF_CHAN_5G(5620, 124), 71 RTW89_DEF_CHAN_5G(5640, 128), 72 RTW89_DEF_CHAN_5G(5660, 132), 73 RTW89_DEF_CHAN_5G(5680, 136), 74 RTW89_DEF_CHAN_5G(5700, 140), 75 RTW89_DEF_CHAN_5G(5720, 144), 76 RTW89_DEF_CHAN_5G(5745, 149), 77 RTW89_DEF_CHAN_5G(5765, 153), 78 RTW89_DEF_CHAN_5G(5785, 157), 79 RTW89_DEF_CHAN_5G(5805, 161), 80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 81 RTW89_DEF_CHAN_5G(5845, 169), 82 RTW89_DEF_CHAN_5G(5865, 173), 83 RTW89_DEF_CHAN_5G(5885, 177), 84 }; 85 86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 87 ARRAY_SIZE(rtw89_channels_5ghz)); 88 89 static struct ieee80211_channel rtw89_channels_6ghz[] = { 90 RTW89_DEF_CHAN_6G(5955, 1), 91 RTW89_DEF_CHAN_6G(5975, 5), 92 RTW89_DEF_CHAN_6G(5995, 9), 93 RTW89_DEF_CHAN_6G(6015, 13), 94 RTW89_DEF_CHAN_6G(6035, 17), 95 RTW89_DEF_CHAN_6G(6055, 21), 96 RTW89_DEF_CHAN_6G(6075, 25), 97 RTW89_DEF_CHAN_6G(6095, 29), 98 RTW89_DEF_CHAN_6G(6115, 33), 99 RTW89_DEF_CHAN_6G(6135, 37), 100 RTW89_DEF_CHAN_6G(6155, 41), 101 RTW89_DEF_CHAN_6G(6175, 45), 102 RTW89_DEF_CHAN_6G(6195, 49), 103 RTW89_DEF_CHAN_6G(6215, 53), 104 RTW89_DEF_CHAN_6G(6235, 57), 105 RTW89_DEF_CHAN_6G(6255, 61), 106 RTW89_DEF_CHAN_6G(6275, 65), 107 RTW89_DEF_CHAN_6G(6295, 69), 108 RTW89_DEF_CHAN_6G(6315, 73), 109 RTW89_DEF_CHAN_6G(6335, 77), 110 RTW89_DEF_CHAN_6G(6355, 81), 111 RTW89_DEF_CHAN_6G(6375, 85), 112 RTW89_DEF_CHAN_6G(6395, 89), 113 RTW89_DEF_CHAN_6G(6415, 93), 114 RTW89_DEF_CHAN_6G(6435, 97), 115 RTW89_DEF_CHAN_6G(6455, 101), 116 RTW89_DEF_CHAN_6G(6475, 105), 117 RTW89_DEF_CHAN_6G(6495, 109), 118 RTW89_DEF_CHAN_6G(6515, 113), 119 RTW89_DEF_CHAN_6G(6535, 117), 120 RTW89_DEF_CHAN_6G(6555, 121), 121 RTW89_DEF_CHAN_6G(6575, 125), 122 RTW89_DEF_CHAN_6G(6595, 129), 123 RTW89_DEF_CHAN_6G(6615, 133), 124 RTW89_DEF_CHAN_6G(6635, 137), 125 RTW89_DEF_CHAN_6G(6655, 141), 126 RTW89_DEF_CHAN_6G(6675, 145), 127 RTW89_DEF_CHAN_6G(6695, 149), 128 RTW89_DEF_CHAN_6G(6715, 153), 129 RTW89_DEF_CHAN_6G(6735, 157), 130 RTW89_DEF_CHAN_6G(6755, 161), 131 RTW89_DEF_CHAN_6G(6775, 165), 132 RTW89_DEF_CHAN_6G(6795, 169), 133 RTW89_DEF_CHAN_6G(6815, 173), 134 RTW89_DEF_CHAN_6G(6835, 177), 135 RTW89_DEF_CHAN_6G(6855, 181), 136 RTW89_DEF_CHAN_6G(6875, 185), 137 RTW89_DEF_CHAN_6G(6895, 189), 138 RTW89_DEF_CHAN_6G(6915, 193), 139 RTW89_DEF_CHAN_6G(6935, 197), 140 RTW89_DEF_CHAN_6G(6955, 201), 141 RTW89_DEF_CHAN_6G(6975, 205), 142 RTW89_DEF_CHAN_6G(6995, 209), 143 RTW89_DEF_CHAN_6G(7015, 213), 144 RTW89_DEF_CHAN_6G(7035, 217), 145 RTW89_DEF_CHAN_6G(7055, 221), 146 RTW89_DEF_CHAN_6G(7075, 225), 147 RTW89_DEF_CHAN_6G(7095, 229), 148 RTW89_DEF_CHAN_6G(7115, 233), 149 }; 150 151 static struct ieee80211_rate rtw89_bitrates[] = { 152 { .bitrate = 10, .hw_value = 0x00, }, 153 { .bitrate = 20, .hw_value = 0x01, }, 154 { .bitrate = 55, .hw_value = 0x02, }, 155 { .bitrate = 110, .hw_value = 0x03, }, 156 { .bitrate = 60, .hw_value = 0x04, }, 157 { .bitrate = 90, .hw_value = 0x05, }, 158 { .bitrate = 120, .hw_value = 0x06, }, 159 { .bitrate = 180, .hw_value = 0x07, }, 160 { .bitrate = 240, .hw_value = 0x08, }, 161 { .bitrate = 360, .hw_value = 0x09, }, 162 { .bitrate = 480, .hw_value = 0x0a, }, 163 { .bitrate = 540, .hw_value = 0x0b, }, 164 }; 165 166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_STATION), 170 }, 171 { 172 .max = 1, 173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 174 BIT(NL80211_IFTYPE_P2P_GO) | 175 BIT(NL80211_IFTYPE_AP), 176 }, 177 }; 178 179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_STATION), 183 }, 184 { 185 .max = 1, 186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 187 BIT(NL80211_IFTYPE_P2P_GO), 188 }, 189 }; 190 191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 192 { 193 .limits = rtw89_iface_limits, 194 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 195 .max_interfaces = 2, 196 .num_different_channels = 1, 197 }, 198 { 199 .limits = rtw89_iface_limits_mcc, 200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 201 .max_interfaces = 2, 202 .num_different_channels = 2, 203 }, 204 }; 205 206 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 207 { 208 struct ieee80211_rate rate; 209 210 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 211 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 212 return false; 213 } 214 215 rate = rtw89_bitrates[rpt_rate]; 216 *bitrate = rate.bitrate; 217 218 return true; 219 } 220 221 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 222 .band = NL80211_BAND_2GHZ, 223 .channels = rtw89_channels_2ghz, 224 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 225 .bitrates = rtw89_bitrates, 226 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 227 .ht_cap = {0}, 228 .vht_cap = {0}, 229 }; 230 231 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 232 .band = NL80211_BAND_5GHZ, 233 .channels = rtw89_channels_5ghz, 234 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 235 236 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 237 .bitrates = rtw89_bitrates + 4, 238 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 239 .ht_cap = {0}, 240 .vht_cap = {0}, 241 }; 242 243 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 244 .band = NL80211_BAND_6GHZ, 245 .channels = rtw89_channels_6ghz, 246 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 247 248 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 249 .bitrates = rtw89_bitrates + 4, 250 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 251 }; 252 253 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 254 struct rtw89_traffic_stats *stats, 255 struct sk_buff *skb, bool tx) 256 { 257 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 258 259 if (tx && ieee80211_is_assoc_req(hdr->frame_control)) 260 rtw89_wow_parse_akm(rtwdev, skb); 261 262 if (!ieee80211_is_data(hdr->frame_control)) 263 return; 264 265 if (is_broadcast_ether_addr(hdr->addr1) || 266 is_multicast_ether_addr(hdr->addr1)) 267 return; 268 269 if (tx) { 270 stats->tx_cnt++; 271 stats->tx_unicast += skb->len; 272 } else { 273 stats->rx_cnt++; 274 stats->rx_unicast += skb->len; 275 } 276 } 277 278 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 279 { 280 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 281 NL80211_CHAN_NO_HT); 282 } 283 284 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 285 struct rtw89_chan *chan) 286 { 287 struct ieee80211_channel *channel = chandef->chan; 288 enum nl80211_chan_width width = chandef->width; 289 u32 primary_freq, center_freq; 290 u8 center_chan; 291 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 292 u32 offset; 293 u8 band; 294 295 center_chan = channel->hw_value; 296 primary_freq = channel->center_freq; 297 center_freq = chandef->center_freq1; 298 299 switch (width) { 300 case NL80211_CHAN_WIDTH_20_NOHT: 301 case NL80211_CHAN_WIDTH_20: 302 bandwidth = RTW89_CHANNEL_WIDTH_20; 303 break; 304 case NL80211_CHAN_WIDTH_40: 305 bandwidth = RTW89_CHANNEL_WIDTH_40; 306 if (primary_freq > center_freq) { 307 center_chan -= 2; 308 } else { 309 center_chan += 2; 310 } 311 break; 312 case NL80211_CHAN_WIDTH_80: 313 case NL80211_CHAN_WIDTH_160: 314 bandwidth = nl_to_rtw89_bandwidth(width); 315 if (primary_freq > center_freq) { 316 offset = (primary_freq - center_freq - 10) / 20; 317 center_chan -= 2 + offset * 4; 318 } else { 319 offset = (center_freq - primary_freq - 10) / 20; 320 center_chan += 2 + offset * 4; 321 } 322 break; 323 default: 324 center_chan = 0; 325 break; 326 } 327 328 switch (channel->band) { 329 default: 330 case NL80211_BAND_2GHZ: 331 band = RTW89_BAND_2G; 332 break; 333 case NL80211_BAND_5GHZ: 334 band = RTW89_BAND_5G; 335 break; 336 case NL80211_BAND_6GHZ: 337 band = RTW89_BAND_6G; 338 break; 339 } 340 341 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 342 } 343 344 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 345 { 346 struct rtw89_hal *hal = &rtwdev->hal; 347 const struct rtw89_chip_info *chip = rtwdev->chip; 348 const struct rtw89_chan *chan; 349 enum rtw89_chanctx_idx chanctx_idx; 350 enum rtw89_chanctx_idx roc_idx; 351 enum rtw89_phy_idx phy_idx; 352 enum rtw89_entity_mode mode; 353 bool entity_active; 354 355 entity_active = rtw89_get_entity_state(rtwdev); 356 if (!entity_active) 357 return; 358 359 mode = rtw89_get_entity_mode(rtwdev); 360 switch (mode) { 361 case RTW89_ENTITY_MODE_SCC: 362 case RTW89_ENTITY_MODE_MCC: 363 chanctx_idx = RTW89_CHANCTX_0; 364 break; 365 case RTW89_ENTITY_MODE_MCC_PREPARE: 366 chanctx_idx = RTW89_CHANCTX_1; 367 break; 368 default: 369 WARN(1, "Invalid ent mode: %d\n", mode); 370 return; 371 } 372 373 roc_idx = atomic_read(&hal->roc_entity_idx); 374 if (roc_idx != RTW89_CHANCTX_IDLE) 375 chanctx_idx = roc_idx; 376 377 phy_idx = RTW89_PHY_0; 378 chan = rtw89_chan_get(rtwdev, chanctx_idx); 379 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 380 } 381 382 int rtw89_set_channel(struct rtw89_dev *rtwdev) 383 { 384 struct rtw89_hal *hal = &rtwdev->hal; 385 const struct rtw89_chip_info *chip = rtwdev->chip; 386 const struct rtw89_chan_rcd *chan_rcd; 387 const struct rtw89_chan *chan; 388 enum rtw89_chanctx_idx chanctx_idx; 389 enum rtw89_chanctx_idx roc_idx; 390 enum rtw89_mac_idx mac_idx; 391 enum rtw89_phy_idx phy_idx; 392 struct rtw89_channel_help_params bak; 393 enum rtw89_entity_mode mode; 394 bool entity_active; 395 396 entity_active = rtw89_get_entity_state(rtwdev); 397 398 mode = rtw89_entity_recalc(rtwdev); 399 switch (mode) { 400 case RTW89_ENTITY_MODE_SCC: 401 case RTW89_ENTITY_MODE_MCC: 402 chanctx_idx = RTW89_CHANCTX_0; 403 break; 404 case RTW89_ENTITY_MODE_MCC_PREPARE: 405 chanctx_idx = RTW89_CHANCTX_1; 406 break; 407 default: 408 WARN(1, "Invalid ent mode: %d\n", mode); 409 return -EINVAL; 410 } 411 412 roc_idx = atomic_read(&hal->roc_entity_idx); 413 if (roc_idx != RTW89_CHANCTX_IDLE) 414 chanctx_idx = roc_idx; 415 416 mac_idx = RTW89_MAC_0; 417 phy_idx = RTW89_PHY_0; 418 419 chan = rtw89_chan_get(rtwdev, chanctx_idx); 420 chan_rcd = rtw89_chan_rcd_get(rtwdev, chanctx_idx); 421 422 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 423 424 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 425 426 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 427 428 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 429 430 if (!entity_active || chan_rcd->band_changed) { 431 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 432 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 433 } 434 435 rtw89_set_entity_state(rtwdev, true); 436 return 0; 437 } 438 439 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 440 struct rtw89_chan *chan) 441 { 442 const struct cfg80211_chan_def *chandef; 443 444 chandef = rtw89_chandef_get(rtwdev, rtwvif->chanctx_idx); 445 rtw89_get_channel_params(chandef, chan); 446 } 447 448 static enum rtw89_core_tx_type 449 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 450 struct sk_buff *skb) 451 { 452 struct ieee80211_hdr *hdr = (void *)skb->data; 453 __le16 fc = hdr->frame_control; 454 455 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 456 return RTW89_CORE_TX_TYPE_MGMT; 457 458 return RTW89_CORE_TX_TYPE_DATA; 459 } 460 461 static void 462 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 463 struct rtw89_core_tx_request *tx_req, 464 enum btc_pkt_type pkt_type) 465 { 466 struct ieee80211_sta *sta = tx_req->sta; 467 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 468 struct sk_buff *skb = tx_req->skb; 469 struct rtw89_sta *rtwsta; 470 u8 ampdu_num; 471 u8 tid; 472 473 if (pkt_type == PACKET_EAPOL) { 474 desc_info->bk = true; 475 return; 476 } 477 478 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 479 return; 480 481 if (!sta) { 482 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 483 return; 484 } 485 486 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 487 rtwsta = (struct rtw89_sta *)sta->drv_priv; 488 489 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 490 rtwsta->ampdu_params[tid].agg_num : 491 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 492 493 desc_info->agg_en = true; 494 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 495 desc_info->ampdu_num = ampdu_num; 496 } 497 498 static void 499 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 500 struct rtw89_core_tx_request *tx_req) 501 { 502 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 503 const struct rtw89_chip_info *chip = rtwdev->chip; 504 const struct rtw89_sec_cam_entry *sec_cam; 505 struct ieee80211_tx_info *info; 506 struct ieee80211_key_conf *key; 507 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 508 struct sk_buff *skb = tx_req->skb; 509 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 510 u8 sec_cam_idx; 511 u64 pn64; 512 513 info = IEEE80211_SKB_CB(skb); 514 key = info->control.hw_key; 515 sec_cam_idx = key->hw_key_idx; 516 sec_cam = cam_info->sec_entries[sec_cam_idx]; 517 if (!sec_cam) { 518 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 519 return; 520 } 521 522 switch (key->cipher) { 523 case WLAN_CIPHER_SUITE_WEP40: 524 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 525 break; 526 case WLAN_CIPHER_SUITE_WEP104: 527 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 528 break; 529 case WLAN_CIPHER_SUITE_TKIP: 530 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 531 break; 532 case WLAN_CIPHER_SUITE_CCMP: 533 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 534 break; 535 case WLAN_CIPHER_SUITE_CCMP_256: 536 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 537 break; 538 case WLAN_CIPHER_SUITE_GCMP: 539 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 540 break; 541 case WLAN_CIPHER_SUITE_GCMP_256: 542 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 543 break; 544 default: 545 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 546 return; 547 } 548 549 desc_info->sec_en = true; 550 desc_info->sec_keyid = key->keyidx; 551 desc_info->sec_type = sec_type; 552 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 553 554 if (!chip->hw_sec_hdr) 555 return; 556 557 pn64 = atomic64_inc_return(&key->tx_pn); 558 desc_info->sec_seq[0] = pn64; 559 desc_info->sec_seq[1] = pn64 >> 8; 560 desc_info->sec_seq[2] = pn64 >> 16; 561 desc_info->sec_seq[3] = pn64 >> 24; 562 desc_info->sec_seq[4] = pn64 >> 32; 563 desc_info->sec_seq[5] = pn64 >> 40; 564 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 565 } 566 567 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 568 struct rtw89_core_tx_request *tx_req, 569 const struct rtw89_chan *chan) 570 { 571 struct sk_buff *skb = tx_req->skb; 572 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 573 struct ieee80211_vif *vif = tx_info->control.vif; 574 u16 lowest_rate; 575 576 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 577 (vif && vif->p2p)) 578 lowest_rate = RTW89_HW_RATE_OFDM6; 579 else if (chan->band_type == RTW89_BAND_2G) 580 lowest_rate = RTW89_HW_RATE_CCK1; 581 else 582 lowest_rate = RTW89_HW_RATE_OFDM6; 583 584 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 585 return lowest_rate; 586 587 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 588 } 589 590 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 591 struct rtw89_core_tx_request *tx_req) 592 { 593 struct ieee80211_vif *vif = tx_req->vif; 594 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 595 struct ieee80211_sta *sta = tx_req->sta; 596 struct rtw89_sta *rtwsta; 597 598 if (!sta) 599 return rtwvif->mac_id; 600 601 rtwsta = (struct rtw89_sta *)sta->drv_priv; 602 return rtwsta->mac_id; 603 } 604 605 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 606 struct rtw89_tx_desc_info *desc_info, 607 struct sk_buff *skb) 608 { 609 struct ieee80211_hdr *hdr = (void *)skb->data; 610 __le16 fc = hdr->frame_control; 611 612 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 613 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 614 } 615 616 static void 617 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 618 struct rtw89_core_tx_request *tx_req) 619 { 620 const struct rtw89_chip_info *chip = rtwdev->chip; 621 struct ieee80211_vif *vif = tx_req->vif; 622 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 623 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 624 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 625 rtwvif->chanctx_idx); 626 struct sk_buff *skb = tx_req->skb; 627 u8 qsel, ch_dma; 628 629 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 630 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 631 632 desc_info->qsel = qsel; 633 desc_info->ch_dma = ch_dma; 634 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 635 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 636 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 637 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 638 639 /* fixed data rate for mgmt frames */ 640 desc_info->en_wd_info = true; 641 desc_info->use_rate = true; 642 desc_info->dis_data_fb = true; 643 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 644 645 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) { 646 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 647 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 648 } 649 650 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 651 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 652 desc_info->data_rate, chan->channel, chan->band_type, 653 chan->band_width); 654 } 655 656 static void 657 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 658 struct rtw89_core_tx_request *tx_req) 659 { 660 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 661 662 desc_info->is_bmc = false; 663 desc_info->wd_page = false; 664 desc_info->ch_dma = RTW89_DMA_H2C; 665 } 666 667 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 668 const struct rtw89_chan *chan) 669 { 670 static const u8 rtw89_bandwidth_to_om[] = { 671 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 672 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 673 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 674 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 675 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 676 }; 677 const struct rtw89_chip_info *chip = rtwdev->chip; 678 struct rtw89_hal *hal = &rtwdev->hal; 679 u8 om_bandwidth; 680 681 if (!chip->dis_2g_40m_ul_ofdma || 682 chan->band_type != RTW89_BAND_2G || 683 chan->band_width != RTW89_CHANNEL_WIDTH_40) 684 return; 685 686 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 687 rtw89_bandwidth_to_om[chan->band_width] : 0; 688 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 689 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 690 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 691 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 692 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 693 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 694 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 695 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 696 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 697 } 698 699 static bool 700 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 701 struct rtw89_core_tx_request *tx_req, 702 enum btc_pkt_type pkt_type) 703 { 704 struct ieee80211_sta *sta = tx_req->sta; 705 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 706 struct sk_buff *skb = tx_req->skb; 707 struct ieee80211_hdr *hdr = (void *)skb->data; 708 __le16 fc = hdr->frame_control; 709 710 /* AP IOT issue with EAPoL, ARP and DHCP */ 711 if (pkt_type < PACKET_MAX) 712 return false; 713 714 if (!sta || !sta->deflink.he_cap.has_he) 715 return false; 716 717 if (!ieee80211_is_data_qos(fc)) 718 return false; 719 720 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 721 return false; 722 723 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 724 return false; 725 726 return true; 727 } 728 729 static void 730 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 731 struct rtw89_core_tx_request *tx_req) 732 { 733 struct ieee80211_sta *sta = tx_req->sta; 734 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 735 struct sk_buff *skb = tx_req->skb; 736 struct ieee80211_hdr *hdr = (void *)skb->data; 737 __le16 fc = hdr->frame_control; 738 void *data; 739 __le32 *htc; 740 u8 *qc; 741 int hdr_len; 742 743 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 744 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 745 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 746 747 hdr = data; 748 htc = data + hdr_len; 749 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 750 *htc = rtwsta->htc_template ? rtwsta->htc_template : 751 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 752 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 753 754 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 755 qc[0] |= IEEE80211_QOS_CTL_EOSP; 756 } 757 758 static void 759 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 760 struct rtw89_core_tx_request *tx_req, 761 enum btc_pkt_type pkt_type) 762 { 763 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 764 struct ieee80211_vif *vif = tx_req->vif; 765 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 766 767 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 768 goto desc_bk; 769 770 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 771 772 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 773 desc_info->a_ctrl_bsr = true; 774 775 desc_bk: 776 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 777 return; 778 779 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 780 desc_info->bk = true; 781 } 782 783 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 784 struct rtw89_core_tx_request *tx_req) 785 { 786 struct ieee80211_vif *vif = tx_req->vif; 787 struct ieee80211_sta *sta = tx_req->sta; 788 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 789 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 790 enum rtw89_chanctx_idx idx = rtwvif->chanctx_idx; 791 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 792 u16 lowest_rate; 793 794 if (rate_pattern->enable) 795 return rate_pattern->rate; 796 797 if (vif->p2p) 798 lowest_rate = RTW89_HW_RATE_OFDM6; 799 else if (chan->band_type == RTW89_BAND_2G) 800 lowest_rate = RTW89_HW_RATE_CCK1; 801 else 802 lowest_rate = RTW89_HW_RATE_OFDM6; 803 804 if (!sta || !sta->deflink.supp_rates[chan->band_type]) 805 return lowest_rate; 806 807 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate; 808 } 809 810 static void 811 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 812 struct rtw89_core_tx_request *tx_req) 813 { 814 struct ieee80211_vif *vif = tx_req->vif; 815 struct ieee80211_sta *sta = tx_req->sta; 816 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 817 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 818 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 819 struct sk_buff *skb = tx_req->skb; 820 u8 tid, tid_indicate; 821 u8 qsel, ch_dma; 822 823 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 824 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 825 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 826 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 827 828 desc_info->ch_dma = ch_dma; 829 desc_info->tid_indicate = tid_indicate; 830 desc_info->qsel = qsel; 831 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 832 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 833 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 834 desc_info->stbc = rtwsta ? rtwsta->ra.stbc_cap : false; 835 desc_info->ldpc = rtwsta ? rtwsta->ra.ldpc_cap : false; 836 837 /* enable wd_info for AMPDU */ 838 desc_info->en_wd_info = true; 839 840 if (IEEE80211_SKB_CB(skb)->control.hw_key) 841 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 842 843 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 844 } 845 846 static enum btc_pkt_type 847 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 848 struct rtw89_core_tx_request *tx_req) 849 { 850 struct sk_buff *skb = tx_req->skb; 851 struct udphdr *udphdr; 852 853 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 854 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 855 return PACKET_EAPOL; 856 } 857 858 if (skb->protocol == htons(ETH_P_ARP)) { 859 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 860 return PACKET_ARP; 861 } 862 863 if (skb->protocol == htons(ETH_P_IP) && 864 ip_hdr(skb)->protocol == IPPROTO_UDP) { 865 udphdr = udp_hdr(skb); 866 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 867 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 868 skb->len > 282) { 869 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 870 return PACKET_DHCP; 871 } 872 } 873 874 if (skb->protocol == htons(ETH_P_IP) && 875 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 876 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 877 return PACKET_ICMP; 878 } 879 880 return PACKET_MAX; 881 } 882 883 static void 884 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 885 struct rtw89_core_tx_request *tx_req) 886 { 887 const struct rtw89_chip_info *chip = rtwdev->chip; 888 889 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 890 return; 891 892 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 893 return; 894 895 if (chip->chip_id != RTL8852C && 896 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 897 return; 898 899 rtw89_mac_notify_wake(rtwdev); 900 } 901 902 static void 903 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 904 struct rtw89_core_tx_request *tx_req) 905 { 906 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 907 struct sk_buff *skb = tx_req->skb; 908 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 909 struct ieee80211_hdr *hdr = (void *)skb->data; 910 enum rtw89_core_tx_type tx_type; 911 enum btc_pkt_type pkt_type; 912 bool is_bmc; 913 u16 seq; 914 915 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 916 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 917 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 918 tx_req->tx_type = tx_type; 919 } 920 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 921 is_multicast_ether_addr(hdr->addr1)); 922 923 desc_info->seq = seq; 924 desc_info->pkt_size = skb->len; 925 desc_info->is_bmc = is_bmc; 926 desc_info->wd_page = true; 927 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 928 929 switch (tx_req->tx_type) { 930 case RTW89_CORE_TX_TYPE_MGMT: 931 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 932 break; 933 case RTW89_CORE_TX_TYPE_DATA: 934 rtw89_core_tx_update_data_info(rtwdev, tx_req); 935 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 936 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 937 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 938 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 939 break; 940 case RTW89_CORE_TX_TYPE_FWCMD: 941 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 942 break; 943 } 944 } 945 946 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 947 { 948 u8 ch_dma; 949 950 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 951 952 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 953 } 954 955 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 956 int qsel, unsigned int timeout) 957 { 958 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 959 struct rtw89_tx_wait_info *wait; 960 unsigned long time_left; 961 int ret = 0; 962 963 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 964 if (!wait) { 965 rtw89_core_tx_kick_off(rtwdev, qsel); 966 return 0; 967 } 968 969 init_completion(&wait->completion); 970 rcu_assign_pointer(skb_data->wait, wait); 971 972 rtw89_core_tx_kick_off(rtwdev, qsel); 973 time_left = wait_for_completion_timeout(&wait->completion, 974 msecs_to_jiffies(timeout)); 975 if (time_left == 0) 976 ret = -ETIMEDOUT; 977 else if (!wait->tx_done) 978 ret = -EAGAIN; 979 980 rcu_assign_pointer(skb_data->wait, NULL); 981 kfree_rcu(wait, rcu_head); 982 983 return ret; 984 } 985 986 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 987 struct sk_buff *skb, bool fwdl) 988 { 989 struct rtw89_core_tx_request tx_req = {0}; 990 u32 cnt; 991 int ret; 992 993 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 994 rtw89_debug(rtwdev, RTW89_DBG_FW, 995 "ignore h2c due to power is off with firmware state=%d\n", 996 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 997 dev_kfree_skb(skb); 998 return 0; 999 } 1000 1001 tx_req.skb = skb; 1002 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1003 if (fwdl) 1004 tx_req.desc_info.fw_dl = true; 1005 1006 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1007 1008 if (!fwdl) 1009 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1010 1011 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1012 if (cnt == 0) { 1013 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1014 return -ENOSPC; 1015 } 1016 1017 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1018 if (ret) { 1019 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1020 return ret; 1021 } 1022 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1023 1024 return 0; 1025 } 1026 1027 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1028 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1029 { 1030 struct rtw89_core_tx_request tx_req = {0}; 1031 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1032 int ret; 1033 1034 tx_req.skb = skb; 1035 tx_req.sta = sta; 1036 tx_req.vif = vif; 1037 1038 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1039 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1040 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1041 rtw89_core_tx_wake(rtwdev, &tx_req); 1042 1043 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1044 if (ret) { 1045 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1046 return ret; 1047 } 1048 1049 if (qsel) 1050 *qsel = tx_req.desc_info.qsel; 1051 1052 return 0; 1053 } 1054 1055 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1056 { 1057 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1058 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1059 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1060 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1061 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1062 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1063 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1064 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1065 1066 return cpu_to_le32(dword); 1067 } 1068 1069 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1070 { 1071 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1072 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1073 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1074 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1075 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1076 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1077 1078 return cpu_to_le32(dword); 1079 } 1080 1081 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1082 { 1083 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1084 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1085 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1086 1087 return cpu_to_le32(dword); 1088 } 1089 1090 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1091 { 1092 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1093 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1094 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1095 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1096 1097 return cpu_to_le32(dword); 1098 } 1099 1100 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1101 { 1102 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1103 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1104 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1105 1106 return cpu_to_le32(dword); 1107 } 1108 1109 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1110 { 1111 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1112 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1113 1114 return cpu_to_le32(dword); 1115 } 1116 1117 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1118 { 1119 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1120 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1121 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1122 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1123 1124 return cpu_to_le32(dword); 1125 } 1126 1127 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1128 { 1129 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1130 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1131 1132 return cpu_to_le32(dword); 1133 } 1134 1135 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1136 { 1137 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1138 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1139 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1140 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1141 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1142 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1143 1144 return cpu_to_le32(dword); 1145 } 1146 1147 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1148 { 1149 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1150 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1151 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1152 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1153 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1154 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1155 1156 return cpu_to_le32(dword); 1157 } 1158 1159 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1160 { 1161 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1162 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1163 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1164 desc_info->data_retry_lowest_rate); 1165 1166 return cpu_to_le32(dword); 1167 } 1168 1169 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1170 { 1171 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1172 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1173 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1174 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1175 1176 return cpu_to_le32(dword); 1177 } 1178 1179 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1180 { 1181 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1182 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1183 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1184 1185 return cpu_to_le32(dword); 1186 } 1187 1188 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1189 { 1190 bool rts_en = !desc_info->is_bmc; 1191 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1192 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1193 1194 return cpu_to_le32(dword); 1195 } 1196 1197 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1198 struct rtw89_tx_desc_info *desc_info, 1199 void *txdesc) 1200 { 1201 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1202 struct rtw89_txwd_info *txwd_info; 1203 1204 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1205 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1206 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1207 1208 if (!desc_info->en_wd_info) 1209 return; 1210 1211 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1212 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1213 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1214 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1215 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1216 1217 } 1218 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1219 1220 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1221 struct rtw89_tx_desc_info *desc_info, 1222 void *txdesc) 1223 { 1224 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1225 struct rtw89_txwd_info *txwd_info; 1226 1227 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1228 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1229 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1230 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1231 if (desc_info->sec_en) { 1232 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1233 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1234 } 1235 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1236 1237 if (!desc_info->en_wd_info) 1238 return; 1239 1240 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1241 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1242 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1243 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1244 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1245 } 1246 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1247 1248 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1249 { 1250 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1251 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1252 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1253 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1254 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1255 1256 return cpu_to_le32(dword); 1257 } 1258 1259 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1260 { 1261 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1262 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1263 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1264 1265 return cpu_to_le32(dword); 1266 } 1267 1268 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1269 { 1270 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1271 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1272 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1273 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1274 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1275 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1276 1277 return cpu_to_le32(dword); 1278 } 1279 1280 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1281 { 1282 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq); 1283 1284 return cpu_to_le32(dword); 1285 } 1286 1287 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1288 { 1289 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1290 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1291 1292 return cpu_to_le32(dword); 1293 } 1294 1295 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1296 { 1297 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1298 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1299 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1300 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1301 1302 return cpu_to_le32(dword); 1303 } 1304 1305 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1306 { 1307 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1308 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1309 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1310 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1311 1312 return cpu_to_le32(dword); 1313 } 1314 1315 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1316 { 1317 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1318 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1319 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1320 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1321 1322 return cpu_to_le32(dword); 1323 } 1324 1325 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1326 { 1327 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1328 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1329 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1330 desc_info->data_retry_lowest_rate); 1331 1332 return cpu_to_le32(dword); 1333 } 1334 1335 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1336 { 1337 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1338 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1339 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1340 1341 return cpu_to_le32(dword); 1342 } 1343 1344 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1345 { 1346 bool rts_en = !desc_info->is_bmc; 1347 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1348 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1349 1350 return cpu_to_le32(dword); 1351 } 1352 1353 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1354 struct rtw89_tx_desc_info *desc_info, 1355 void *txdesc) 1356 { 1357 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1358 struct rtw89_txwd_info_v2 *txwd_info; 1359 1360 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1361 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1362 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1363 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1364 if (desc_info->sec_en) { 1365 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1366 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1367 } 1368 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1369 1370 if (!desc_info->en_wd_info) 1371 return; 1372 1373 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1374 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1375 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1376 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1377 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1378 } 1379 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1380 1381 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1382 { 1383 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1384 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1385 RTW89_CORE_RX_TYPE_FWDL : 1386 RTW89_CORE_RX_TYPE_H2C); 1387 1388 return cpu_to_le32(dword); 1389 } 1390 1391 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1392 struct rtw89_tx_desc_info *desc_info, 1393 void *txdesc) 1394 { 1395 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1396 1397 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1398 } 1399 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1400 1401 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1402 { 1403 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1404 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1405 RTW89_CORE_RX_TYPE_FWDL : 1406 RTW89_CORE_RX_TYPE_H2C); 1407 1408 return cpu_to_le32(dword); 1409 } 1410 1411 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1412 struct rtw89_tx_desc_info *desc_info, 1413 void *txdesc) 1414 { 1415 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1416 1417 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1418 } 1419 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1420 1421 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1422 struct sk_buff *skb, 1423 struct rtw89_rx_phy_ppdu *phy_ppdu) 1424 { 1425 const struct rtw89_chip_info *chip = rtwdev->chip; 1426 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1427 const struct rtw89_rxinfo_user *user; 1428 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1429 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1430 bool rx_cnt_valid = false; 1431 bool invalid = false; 1432 u8 plcp_size = 0; 1433 u8 *phy_sts; 1434 u8 usr_num; 1435 int i; 1436 1437 if (chip_gen == RTW89_CHIP_BE) { 1438 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1439 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1440 } 1441 1442 if (invalid) 1443 return -EINVAL; 1444 1445 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1446 if (chip_gen == RTW89_CHIP_BE) { 1447 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1448 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1449 } else { 1450 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1451 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1452 } 1453 if (usr_num > chip->ppdu_max_usr) { 1454 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1455 usr_num); 1456 return -EINVAL; 1457 } 1458 1459 for (i = 0; i < usr_num; i++) { 1460 user = &rxinfo->user[i]; 1461 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1462 continue; 1463 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set 1464 * by hardware, so update mac_id by rxinfo_user[].mac_id. 1465 */ 1466 if (chip_gen == RTW89_CHIP_BE) 1467 phy_ppdu->mac_id = 1468 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1469 phy_ppdu->has_data = 1470 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA); 1471 phy_ppdu->has_bcn = 1472 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN); 1473 break; 1474 } 1475 1476 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1477 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1478 /* 8-byte alignment */ 1479 if (usr_num & BIT(0)) 1480 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1481 if (rx_cnt_valid) 1482 phy_sts += rx_cnt_size; 1483 phy_sts += plcp_size; 1484 1485 if (phy_sts > skb->data + skb->len) 1486 return -EINVAL; 1487 1488 phy_ppdu->buf = phy_sts; 1489 phy_ppdu->len = skb->data + skb->len - phy_sts; 1490 1491 return 0; 1492 } 1493 1494 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate) 1495 { 1496 u8 data_rate_mode; 1497 1498 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1499 switch (data_rate_mode) { 1500 case DATA_RATE_MODE_NON_HT: 1501 return 1; 1502 case DATA_RATE_MODE_HT: 1503 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1; 1504 case DATA_RATE_MODE_VHT: 1505 case DATA_RATE_MODE_HE: 1506 case DATA_RATE_MODE_EHT: 1507 return rtw89_get_data_nss(rtwdev, data_rate) + 1; 1508 default: 1509 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1510 return 0; 1511 } 1512 } 1513 1514 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1515 struct ieee80211_sta *sta) 1516 { 1517 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1518 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1519 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1520 struct rtw89_hal *hal = &rtwdev->hal; 1521 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1522 u8 ant_pos = U8_MAX; 1523 u8 evm_pos = 0; 1524 int i; 1525 1526 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1527 return; 1528 1529 if (hal->ant_diversity && hal->antenna_rx) { 1530 ant_pos = __ffs(hal->antenna_rx); 1531 evm_pos = ant_pos; 1532 } 1533 1534 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1535 1536 if (ant_pos < ant_num) { 1537 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]); 1538 } else { 1539 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1540 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1541 } 1542 1543 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) { 1544 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr); 1545 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) { 1546 ewma_evm_add(&rtwsta->evm_1ss, phy_ppdu->ofdm.evm_min); 1547 } else { 1548 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min); 1549 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max); 1550 } 1551 } 1552 } 1553 1554 #define VAR_LEN 0xff 1555 #define VAR_LEN_UNIT 8 1556 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1557 const struct rtw89_phy_sts_iehdr *iehdr) 1558 { 1559 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1560 [RTW89_CHIP_AX] = { 1561 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1562 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1563 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1564 }, 1565 [RTW89_CHIP_BE] = { 1566 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1567 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1568 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1569 }, 1570 }; 1571 const u8 *physts_ie_len_tab; 1572 u16 ie_len; 1573 u8 ie; 1574 1575 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1576 1577 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1578 if (physts_ie_len_tab[ie] != VAR_LEN) 1579 ie_len = physts_ie_len_tab[ie]; 1580 else 1581 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1582 1583 return ie_len; 1584 } 1585 1586 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1587 const struct rtw89_phy_sts_iehdr *iehdr, 1588 struct rtw89_rx_phy_ppdu *phy_ppdu) 1589 { 1590 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr; 1591 s16 cfo; 1592 u32 t; 1593 1594 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1595 1596 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1597 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1598 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1599 } 1600 1601 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1602 return; 1603 1604 if (!phy_ppdu->to_self) 1605 return; 1606 1607 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1608 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1609 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1610 phy_ppdu->ofdm.has = true; 1611 1612 /* sign conversion for S(12,2) */ 1613 if (rtwdev->chip->cfo_src_fd) { 1614 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1615 cfo = sign_extend32(t, 11); 1616 } else { 1617 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1618 cfo = sign_extend32(t, 11); 1619 } 1620 1621 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1622 } 1623 1624 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1625 const struct rtw89_phy_sts_iehdr *iehdr, 1626 struct rtw89_rx_phy_ppdu *phy_ppdu) 1627 { 1628 u8 ie; 1629 1630 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1631 1632 switch (ie) { 1633 case RTW89_PHYSTS_IE01_CMN_OFDM: 1634 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1635 break; 1636 default: 1637 break; 1638 } 1639 1640 return 0; 1641 } 1642 1643 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1644 { 1645 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1646 u8 *rssi = phy_ppdu->rssi; 1647 1648 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1649 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1650 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1651 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1652 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1653 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1654 } 1655 1656 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1657 struct rtw89_rx_phy_ppdu *phy_ppdu) 1658 { 1659 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1660 u32 len_from_header; 1661 bool physts_valid; 1662 1663 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1664 if (!physts_valid) 1665 return -EINVAL; 1666 1667 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1668 1669 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1670 len_from_header += PHY_STS_HDR_LEN; 1671 1672 if (len_from_header != phy_ppdu->len) { 1673 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1674 return -EINVAL; 1675 } 1676 rtw89_core_update_phy_ppdu(phy_ppdu); 1677 1678 return 0; 1679 } 1680 1681 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1682 struct rtw89_rx_phy_ppdu *phy_ppdu) 1683 { 1684 u16 ie_len; 1685 void *pos, *end; 1686 1687 /* mark invalid reports and bypass them */ 1688 if (phy_ppdu->ie < RTW89_CCK_PKT) 1689 return -EINVAL; 1690 1691 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1692 end = phy_ppdu->buf + phy_ppdu->len; 1693 while (pos < end) { 1694 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1695 1696 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1697 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1698 pos += ie_len; 1699 if (pos > end || ie_len == 0) { 1700 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1701 "phy status parse failed\n"); 1702 return -EINVAL; 1703 } 1704 } 1705 1706 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1707 1708 return 0; 1709 } 1710 1711 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1712 struct rtw89_rx_phy_ppdu *phy_ppdu) 1713 { 1714 int ret; 1715 1716 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1717 if (ret) 1718 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1719 else 1720 phy_ppdu->valid = true; 1721 1722 ieee80211_iterate_stations_atomic(rtwdev->hw, 1723 rtw89_core_rx_process_phy_ppdu_iter, 1724 phy_ppdu); 1725 } 1726 1727 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 1728 u8 desc_info_gi, 1729 bool rx_status, bool eht) 1730 { 1731 switch (desc_info_gi) { 1732 case RTW89_GILTF_SGI_4XHE08: 1733 case RTW89_GILTF_2XHE08: 1734 case RTW89_GILTF_1XHE08: 1735 return eht ? NL80211_RATE_INFO_EHT_GI_0_8 : 1736 NL80211_RATE_INFO_HE_GI_0_8; 1737 case RTW89_GILTF_2XHE16: 1738 case RTW89_GILTF_1XHE16: 1739 return eht ? NL80211_RATE_INFO_EHT_GI_1_6 : 1740 NL80211_RATE_INFO_HE_GI_1_6; 1741 case RTW89_GILTF_LGI_4XHE32: 1742 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1743 NL80211_RATE_INFO_HE_GI_3_2; 1744 default: 1745 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1746 if (rx_status) 1747 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1748 NL80211_RATE_INFO_HE_GI_3_2; 1749 return U8_MAX; 1750 } 1751 } 1752 1753 static 1754 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 1755 bool eht) 1756 { 1757 if (eht) 1758 return status->eht.gi == gi_ltf; 1759 1760 return status->he_gi == gi_ltf; 1761 } 1762 1763 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1764 struct rtw89_rx_desc_info *desc_info, 1765 struct ieee80211_rx_status *status) 1766 { 1767 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1768 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1769 bool eht = false; 1770 u16 data_rate; 1771 bool ret; 1772 1773 data_rate = desc_info->data_rate; 1774 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1775 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1776 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1777 /* rate_idx is still hardware value here */ 1778 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1779 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1780 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 1781 data_rate_mode == DATA_RATE_MODE_HE || 1782 data_rate_mode == DATA_RATE_MODE_EHT) { 1783 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1784 } else { 1785 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1786 } 1787 1788 eht = data_rate_mode == DATA_RATE_MODE_EHT; 1789 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1790 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 1791 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1792 status->rate_idx == rate_idx && 1793 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 1794 status->bw == bw; 1795 1796 return ret; 1797 } 1798 1799 struct rtw89_vif_rx_stats_iter_data { 1800 struct rtw89_dev *rtwdev; 1801 struct rtw89_rx_phy_ppdu *phy_ppdu; 1802 struct rtw89_rx_desc_info *desc_info; 1803 struct sk_buff *skb; 1804 const u8 *bssid; 1805 }; 1806 1807 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1808 struct ieee80211_vif *vif, 1809 struct sk_buff *skb) 1810 { 1811 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1812 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1813 u8 *pos, *end, type, tf_bw; 1814 u16 aid, tf_rua; 1815 1816 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1817 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1818 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1819 return; 1820 1821 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1822 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 1823 return; 1824 1825 end = (u8 *)tf + skb->len; 1826 pos = tf->variable; 1827 1828 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1829 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1830 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 1831 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 1832 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1833 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 1834 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1835 tf_rua, tf_bw); 1836 1837 if (aid == RTW89_TF_PAD) 1838 break; 1839 1840 if (aid == vif->cfg.aid) { 1841 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 1842 1843 rtwvif->stats.rx_tf_acc++; 1844 rtwdev->stats.rx_tf_acc++; 1845 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 1846 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 1847 rtwvif->pwr_diff_en = true; 1848 break; 1849 } 1850 1851 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1852 } 1853 } 1854 1855 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work) 1856 { 1857 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1858 cancel_6ghz_probe_work); 1859 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1860 struct rtw89_pktofld_info *info; 1861 1862 mutex_lock(&rtwdev->mutex); 1863 1864 if (!rtwdev->scanning) 1865 goto out; 1866 1867 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1868 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 1869 continue; 1870 1871 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1872 1873 /* Don't delete/free info from pkt_list at this moment. Let it 1874 * be deleted/freed in rtw89_release_pkt_list() after scanning, 1875 * since if during scanning, pkt_list is accessed in bottom half. 1876 */ 1877 } 1878 1879 out: 1880 mutex_unlock(&rtwdev->mutex); 1881 } 1882 1883 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1884 struct sk_buff *skb) 1885 { 1886 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1887 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1888 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1889 struct rtw89_pktofld_info *info; 1890 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1891 bool queue_work = false; 1892 1893 if (rx_status->band != NL80211_BAND_6GHZ) 1894 return; 1895 1896 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1897 1898 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1899 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1900 info->cancel = true; 1901 queue_work = true; 1902 continue; 1903 } 1904 1905 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1906 continue; 1907 1908 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 1909 info->cancel = true; 1910 queue_work = true; 1911 } 1912 } 1913 1914 if (queue_work) 1915 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work); 1916 } 1917 1918 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif *rtwvif, 1919 struct ieee80211_hdr *hdr, size_t len) 1920 { 1921 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 1922 1923 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 1924 return; 1925 1926 WRITE_ONCE(rtwvif->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 1927 } 1928 1929 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1930 struct ieee80211_vif *vif) 1931 { 1932 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1933 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1934 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1935 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1936 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1937 struct sk_buff *skb = iter_data->skb; 1938 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1939 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 1940 const u8 *bssid = iter_data->bssid; 1941 1942 if (rtwdev->scanning && 1943 (ieee80211_is_beacon(hdr->frame_control) || 1944 ieee80211_is_probe_resp(hdr->frame_control))) 1945 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1946 1947 if (!vif->bss_conf.bssid) 1948 return; 1949 1950 if (ieee80211_is_trigger(hdr->frame_control)) { 1951 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1952 return; 1953 } 1954 1955 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1956 return; 1957 1958 if (ieee80211_is_beacon(hdr->frame_control)) { 1959 if (vif->type == NL80211_IFTYPE_STATION && 1960 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 1961 rtw89_vif_sync_bcn_tsf(rtwvif, hdr, skb->len); 1962 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 1963 } 1964 pkt_stat->beacon_nr++; 1965 } 1966 1967 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1968 return; 1969 1970 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1971 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1972 1973 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1974 } 1975 1976 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1977 struct rtw89_rx_phy_ppdu *phy_ppdu, 1978 struct rtw89_rx_desc_info *desc_info, 1979 struct sk_buff *skb) 1980 { 1981 struct rtw89_vif_rx_stats_iter_data iter_data; 1982 1983 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1984 1985 iter_data.rtwdev = rtwdev; 1986 iter_data.phy_ppdu = phy_ppdu; 1987 iter_data.desc_info = desc_info; 1988 iter_data.skb = skb; 1989 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1990 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1991 } 1992 1993 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1994 struct ieee80211_rx_status *status) 1995 { 1996 const struct rtw89_chan_rcd *rcd = 1997 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0); 1998 u16 chan = rcd->prev_primary_channel; 1999 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 2000 2001 if (status->band != NL80211_BAND_2GHZ && 2002 status->encoding == RX_ENC_LEGACY && 2003 status->rate_idx < RTW89_HW_RATE_OFDM6) { 2004 status->freq = ieee80211_channel_to_frequency(chan, band); 2005 status->band = band; 2006 } 2007 } 2008 2009 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 2010 { 2011 if (rx_status->band == NL80211_BAND_2GHZ || 2012 rx_status->encoding != RX_ENC_LEGACY) 2013 return; 2014 2015 /* Some control frames' freq(ACKs in this case) are reported wrong due 2016 * to FW notify timing, set to lowest rate to prevent overflow. 2017 */ 2018 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 2019 rx_status->rate_idx = 0; 2020 return; 2021 } 2022 2023 /* No 4 CCK rates for non-2G */ 2024 rx_status->rate_idx -= 4; 2025 } 2026 2027 static 2028 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 2029 struct ieee80211_rx_status *rx_status, 2030 struct rtw89_rx_phy_ppdu *phy_ppdu) 2031 { 2032 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2033 return; 2034 2035 if (!phy_ppdu) 2036 return; 2037 2038 if (phy_ppdu->ldpc) 2039 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2040 if (phy_ppdu->stbc) 2041 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 2042 } 2043 2044 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 2045 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 2046 [RATE_INFO_BW_5] = U8_MAX, 2047 [RATE_INFO_BW_10] = U8_MAX, 2048 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 2049 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 2050 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 2051 [RATE_INFO_BW_HE_RU] = U8_MAX, 2052 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 2053 [RATE_INFO_BW_EHT_RU] = U8_MAX, 2054 }; 2055 2056 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2057 struct sk_buff *skb, 2058 struct ieee80211_rx_status *rx_status) 2059 { 2060 struct ieee80211_radiotap_eht_usig *usig; 2061 struct ieee80211_radiotap_eht *eht; 2062 struct ieee80211_radiotap_tlv *tlv; 2063 int eht_len = struct_size(eht, user_info, 1); 2064 int usig_len = sizeof(*usig); 2065 int len; 2066 u8 bw; 2067 2068 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2069 sizeof(*tlv) + ALIGN(usig_len, 4); 2070 2071 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2072 skb_reset_mac_header(skb); 2073 2074 /* EHT */ 2075 tlv = skb_push(skb, len); 2076 memset(tlv, 0, len); 2077 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2078 tlv->len = cpu_to_le16(eht_len); 2079 2080 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2081 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2082 eht->data[0] = 2083 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2084 2085 eht->user_info[0] = 2086 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2087 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 2088 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 2089 eht->user_info[0] |= 2090 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2091 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2092 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 2093 eht->user_info[0] |= 2094 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 2095 2096 /* U-SIG */ 2097 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2098 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2099 tlv->len = cpu_to_le16(usig_len); 2100 2101 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2102 return; 2103 2104 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2105 if (bw == U8_MAX) 2106 return; 2107 2108 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2109 usig->common = 2110 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2111 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2112 } 2113 2114 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2115 struct sk_buff *skb, 2116 struct ieee80211_rx_status *rx_status) 2117 { 2118 static const struct ieee80211_radiotap_he known_he = { 2119 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2120 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 2121 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 2122 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2123 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2124 }; 2125 struct ieee80211_radiotap_he *he; 2126 2127 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2128 return; 2129 2130 if (rx_status->encoding == RX_ENC_HE) { 2131 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2132 he = skb_push(skb, sizeof(*he)); 2133 *he = known_he; 2134 } else if (rx_status->encoding == RX_ENC_EHT) { 2135 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2136 } 2137 } 2138 2139 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2140 struct rtw89_rx_phy_ppdu *phy_ppdu, 2141 struct rtw89_rx_desc_info *desc_info, 2142 struct sk_buff *skb_ppdu, 2143 struct ieee80211_rx_status *rx_status) 2144 { 2145 struct napi_struct *napi = &rtwdev->napi; 2146 2147 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2148 if (unlikely(!napi_is_scheduled(napi))) 2149 napi = NULL; 2150 2151 rtw89_core_hw_to_sband_rate(rx_status); 2152 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2153 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 2154 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2155 /* In low power mode, it does RX in thread context. */ 2156 local_bh_disable(); 2157 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2158 local_bh_enable(); 2159 rtwdev->napi_budget_countdown--; 2160 } 2161 2162 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2163 struct rtw89_rx_phy_ppdu *phy_ppdu, 2164 struct rtw89_rx_desc_info *desc_info, 2165 struct sk_buff *skb) 2166 { 2167 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2168 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2169 struct sk_buff *skb_ppdu = NULL, *tmp; 2170 struct ieee80211_rx_status *rx_status; 2171 2172 if (curr > RTW89_MAX_PPDU_CNT) 2173 return; 2174 2175 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2176 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2177 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2178 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2179 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2180 rtw89_correct_cck_chan(rtwdev, rx_status); 2181 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2182 } 2183 } 2184 2185 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2186 struct rtw89_rx_desc_info *desc_info, 2187 struct sk_buff *skb) 2188 { 2189 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2190 .len = skb->len, 2191 .to_self = desc_info->addr1_match, 2192 .rate = desc_info->data_rate, 2193 .mac_id = desc_info->mac_id}; 2194 int ret; 2195 2196 if (desc_info->mac_info_valid) { 2197 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2198 if (ret) 2199 goto out; 2200 } 2201 2202 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2203 if (ret) 2204 goto out; 2205 2206 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2207 2208 out: 2209 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2210 dev_kfree_skb_any(skb); 2211 } 2212 2213 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2214 struct rtw89_rx_desc_info *desc_info, 2215 struct sk_buff *skb) 2216 { 2217 switch (desc_info->pkt_type) { 2218 case RTW89_CORE_RX_TYPE_C2H: 2219 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2220 break; 2221 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2222 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2223 break; 2224 default: 2225 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2226 desc_info->pkt_type); 2227 dev_kfree_skb_any(skb); 2228 break; 2229 } 2230 } 2231 2232 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2233 struct rtw89_rx_desc_info *desc_info, 2234 u8 *data, u32 data_offset) 2235 { 2236 const struct rtw89_chip_info *chip = rtwdev->chip; 2237 struct rtw89_rxdesc_short *rxd_s; 2238 struct rtw89_rxdesc_long *rxd_l; 2239 u8 shift_len, drv_info_len; 2240 2241 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2242 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2243 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2244 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2245 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2246 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2247 if (chip->chip_id == RTL8852C) 2248 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2249 else 2250 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2251 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2252 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2253 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2254 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2255 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2256 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2257 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2258 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2259 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2260 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2261 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2262 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2263 2264 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2265 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2266 desc_info->offset = data_offset + shift_len + drv_info_len; 2267 if (desc_info->long_rxdesc) 2268 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2269 else 2270 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2271 desc_info->ready = true; 2272 2273 if (!desc_info->long_rxdesc) 2274 return; 2275 2276 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2277 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2278 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2279 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2280 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2281 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2282 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2283 } 2284 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2285 2286 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2287 struct rtw89_rx_desc_info *desc_info, 2288 u8 *data, u32 data_offset) 2289 { 2290 struct rtw89_rxdesc_short_v2 *rxd_s; 2291 struct rtw89_rxdesc_long_v2 *rxd_l; 2292 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2293 2294 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2295 2296 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2297 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2298 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2299 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2300 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2301 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2302 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2303 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2304 desc_info->mac_info_valid = true; 2305 2306 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2307 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2308 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2309 2310 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2311 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2312 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2313 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2314 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2315 2316 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2317 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2318 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2319 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2320 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2321 2322 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2323 2324 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2325 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2326 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2327 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2328 desc_info->offset = data_offset + shift_len + drv_info_len + 2329 phy_rtp_len + hdr_cnv_len; 2330 2331 if (desc_info->long_rxdesc) 2332 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2333 else 2334 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2335 desc_info->ready = true; 2336 2337 if (!desc_info->long_rxdesc) 2338 return; 2339 2340 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2341 2342 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2343 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2344 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2345 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2346 2347 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2348 } 2349 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2350 2351 struct rtw89_core_iter_rx_status { 2352 struct rtw89_dev *rtwdev; 2353 struct ieee80211_rx_status *rx_status; 2354 struct rtw89_rx_desc_info *desc_info; 2355 u8 mac_id; 2356 }; 2357 2358 static 2359 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2360 { 2361 struct rtw89_core_iter_rx_status *iter_data = 2362 (struct rtw89_core_iter_rx_status *)data; 2363 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2364 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2365 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2366 u8 mac_id = iter_data->mac_id; 2367 2368 if (mac_id != rtwsta->mac_id) 2369 return; 2370 2371 rtwsta->rx_status = *rx_status; 2372 rtwsta->rx_hw_rate = desc_info->data_rate; 2373 } 2374 2375 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2376 struct rtw89_rx_desc_info *desc_info, 2377 struct ieee80211_rx_status *rx_status) 2378 { 2379 struct rtw89_core_iter_rx_status iter_data; 2380 2381 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2382 return; 2383 2384 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2385 return; 2386 2387 iter_data.rtwdev = rtwdev; 2388 iter_data.rx_status = rx_status; 2389 iter_data.desc_info = desc_info; 2390 iter_data.mac_id = desc_info->mac_id; 2391 ieee80211_iterate_stations_atomic(rtwdev->hw, 2392 rtw89_core_stats_sta_rx_status_iter, 2393 &iter_data); 2394 } 2395 2396 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2397 struct rtw89_rx_desc_info *desc_info, 2398 struct ieee80211_rx_status *rx_status) 2399 { 2400 const struct cfg80211_chan_def *chandef = 2401 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0); 2402 u16 data_rate; 2403 u8 data_rate_mode; 2404 bool eht = false; 2405 u8 gi; 2406 2407 /* currently using single PHY */ 2408 rx_status->freq = chandef->chan->center_freq; 2409 rx_status->band = chandef->chan->band; 2410 2411 if (rtwdev->scanning && 2412 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2413 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2414 u8 chan = cur->primary_channel; 2415 u8 band = cur->band_type; 2416 enum nl80211_band nl_band; 2417 2418 nl_band = rtw89_hw_to_nl80211_band(band); 2419 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2420 rx_status->band = nl_band; 2421 } 2422 2423 if (desc_info->icv_err || desc_info->crc32_err) 2424 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2425 2426 if (desc_info->hw_dec && 2427 !(desc_info->sw_dec || desc_info->icv_err)) 2428 rx_status->flag |= RX_FLAG_DECRYPTED; 2429 2430 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2431 2432 data_rate = desc_info->data_rate; 2433 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2434 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2435 rx_status->encoding = RX_ENC_LEGACY; 2436 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2437 /* convert rate_idx after we get the correct band */ 2438 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2439 rx_status->encoding = RX_ENC_HT; 2440 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2441 if (desc_info->gi_ltf) 2442 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2443 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2444 rx_status->encoding = RX_ENC_VHT; 2445 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2446 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2447 if (desc_info->gi_ltf) 2448 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2449 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2450 rx_status->encoding = RX_ENC_HE; 2451 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2452 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2453 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2454 rx_status->encoding = RX_ENC_EHT; 2455 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2456 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2457 eht = true; 2458 } else { 2459 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2460 } 2461 2462 /* he_gi is used to match ppdu, so we always fill it. */ 2463 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2464 if (eht) 2465 rx_status->eht.gi = gi; 2466 else 2467 rx_status->he_gi = gi; 2468 rx_status->flag |= RX_FLAG_MACTIME_START; 2469 rx_status->mactime = desc_info->free_run_cnt; 2470 2471 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2472 } 2473 2474 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2475 { 2476 const struct rtw89_chip_info *chip = rtwdev->chip; 2477 2478 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2479 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2480 return RTW89_PS_MODE_NONE; 2481 2482 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2483 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2484 return RTW89_PS_MODE_PWR_GATED; 2485 2486 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2487 return RTW89_PS_MODE_CLK_GATED; 2488 2489 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2490 return RTW89_PS_MODE_RFOFF; 2491 2492 return RTW89_PS_MODE_NONE; 2493 } 2494 2495 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2496 struct rtw89_rx_desc_info *desc_info) 2497 { 2498 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2499 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2500 struct ieee80211_rx_status *rx_status; 2501 struct sk_buff *skb_ppdu, *tmp; 2502 2503 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2504 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2505 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2506 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2507 } 2508 } 2509 2510 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2511 struct rtw89_rx_desc_info *desc_info, 2512 struct sk_buff *skb) 2513 { 2514 struct ieee80211_rx_status *rx_status; 2515 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2516 u8 ppdu_cnt = desc_info->ppdu_cnt; 2517 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2518 2519 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2520 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2521 return; 2522 } 2523 2524 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2525 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2526 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2527 } 2528 2529 rx_status = IEEE80211_SKB_RXCB(skb); 2530 memset(rx_status, 0, sizeof(*rx_status)); 2531 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2532 if (desc_info->long_rxdesc && 2533 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2534 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2535 else 2536 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2537 } 2538 EXPORT_SYMBOL(rtw89_core_rx); 2539 2540 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2541 { 2542 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2543 return; 2544 2545 napi_enable(&rtwdev->napi); 2546 } 2547 EXPORT_SYMBOL(rtw89_core_napi_start); 2548 2549 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2550 { 2551 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2552 return; 2553 2554 napi_synchronize(&rtwdev->napi); 2555 napi_disable(&rtwdev->napi); 2556 } 2557 EXPORT_SYMBOL(rtw89_core_napi_stop); 2558 2559 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2560 { 2561 rtwdev->netdev = alloc_netdev_dummy(0); 2562 if (!rtwdev->netdev) 2563 return -ENOMEM; 2564 2565 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 2566 rtwdev->hci.ops->napi_poll); 2567 return 0; 2568 } 2569 EXPORT_SYMBOL(rtw89_core_napi_init); 2570 2571 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2572 { 2573 rtw89_core_napi_stop(rtwdev); 2574 netif_napi_del(&rtwdev->napi); 2575 free_netdev(rtwdev->netdev); 2576 } 2577 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2578 2579 static void rtw89_core_ba_work(struct work_struct *work) 2580 { 2581 struct rtw89_dev *rtwdev = 2582 container_of(work, struct rtw89_dev, ba_work); 2583 struct rtw89_txq *rtwtxq, *tmp; 2584 int ret; 2585 2586 spin_lock_bh(&rtwdev->ba_lock); 2587 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2588 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2589 struct ieee80211_sta *sta = txq->sta; 2590 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2591 u8 tid = txq->tid; 2592 2593 if (!sta) { 2594 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2595 goto skip_ba_work; 2596 } 2597 2598 if (rtwsta->disassoc) { 2599 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2600 "cannot start BA with disassoc sta\n"); 2601 goto skip_ba_work; 2602 } 2603 2604 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2605 if (ret) { 2606 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2607 "failed to setup BA session for %pM:%2d: %d\n", 2608 sta->addr, tid, ret); 2609 if (ret == -EINVAL) 2610 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2611 } 2612 skip_ba_work: 2613 list_del_init(&rtwtxq->list); 2614 } 2615 spin_unlock_bh(&rtwdev->ba_lock); 2616 } 2617 2618 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2619 struct ieee80211_sta *sta) 2620 { 2621 struct rtw89_txq *rtwtxq, *tmp; 2622 2623 spin_lock_bh(&rtwdev->ba_lock); 2624 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2625 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2626 2627 if (sta == txq->sta) 2628 list_del_init(&rtwtxq->list); 2629 } 2630 spin_unlock_bh(&rtwdev->ba_lock); 2631 } 2632 2633 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2634 struct ieee80211_sta *sta) 2635 { 2636 struct rtw89_txq *rtwtxq, *tmp; 2637 2638 spin_lock_bh(&rtwdev->ba_lock); 2639 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2640 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2641 2642 if (sta == txq->sta) { 2643 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2644 list_del_init(&rtwtxq->list); 2645 } 2646 } 2647 spin_unlock_bh(&rtwdev->ba_lock); 2648 } 2649 2650 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2651 struct ieee80211_sta *sta) 2652 { 2653 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2654 struct sk_buff *skb, *tmp; 2655 2656 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2657 skb_unlink(skb, &rtwsta->roc_queue); 2658 dev_kfree_skb_any(skb); 2659 } 2660 } 2661 2662 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2663 struct rtw89_txq *rtwtxq) 2664 { 2665 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2666 struct ieee80211_sta *sta = txq->sta; 2667 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2668 2669 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2670 return; 2671 2672 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2673 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2674 return; 2675 2676 spin_lock_bh(&rtwdev->ba_lock); 2677 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2678 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2679 spin_unlock_bh(&rtwdev->ba_lock); 2680 2681 ieee80211_stop_tx_ba_session(sta, txq->tid); 2682 cancel_delayed_work(&rtwdev->forbid_ba_work); 2683 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2684 RTW89_FORBID_BA_TIMER); 2685 } 2686 2687 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2688 struct rtw89_txq *rtwtxq, 2689 struct sk_buff *skb) 2690 { 2691 struct ieee80211_hw *hw = rtwdev->hw; 2692 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2693 struct ieee80211_sta *sta = txq->sta; 2694 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2695 2696 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2697 return; 2698 2699 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2700 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2701 return; 2702 } 2703 2704 if (unlikely(!sta)) 2705 return; 2706 2707 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2708 return; 2709 2710 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2711 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2712 return; 2713 } 2714 2715 spin_lock_bh(&rtwdev->ba_lock); 2716 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2717 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2718 ieee80211_queue_work(hw, &rtwdev->ba_work); 2719 } 2720 spin_unlock_bh(&rtwdev->ba_lock); 2721 } 2722 2723 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2724 struct rtw89_txq *rtwtxq, 2725 unsigned long frame_cnt, 2726 unsigned long byte_cnt) 2727 { 2728 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2729 struct ieee80211_vif *vif = txq->vif; 2730 struct ieee80211_sta *sta = txq->sta; 2731 struct sk_buff *skb; 2732 unsigned long i; 2733 int ret; 2734 2735 rcu_read_lock(); 2736 for (i = 0; i < frame_cnt; i++) { 2737 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2738 if (!skb) { 2739 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2740 goto out; 2741 } 2742 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2743 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2744 if (ret) { 2745 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2746 ieee80211_free_txskb(rtwdev->hw, skb); 2747 break; 2748 } 2749 } 2750 out: 2751 rcu_read_unlock(); 2752 } 2753 2754 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2755 { 2756 u8 qsel, ch_dma; 2757 2758 qsel = rtw89_core_get_qsel(rtwdev, tid); 2759 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2760 2761 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2762 } 2763 2764 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2765 struct ieee80211_txq *txq, 2766 unsigned long *frame_cnt, 2767 bool *sched_txq, bool *reinvoke) 2768 { 2769 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2770 struct ieee80211_sta *sta = txq->sta; 2771 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2772 2773 if (!sta || rtwsta->max_agg_wait <= 0) 2774 return false; 2775 2776 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2777 return false; 2778 2779 if (*frame_cnt > 1) { 2780 *frame_cnt -= 1; 2781 *sched_txq = true; 2782 *reinvoke = true; 2783 rtwtxq->wait_cnt = 1; 2784 return false; 2785 } 2786 2787 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2788 *reinvoke = true; 2789 rtwtxq->wait_cnt++; 2790 return true; 2791 } 2792 2793 rtwtxq->wait_cnt = 0; 2794 return false; 2795 } 2796 2797 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2798 { 2799 struct ieee80211_hw *hw = rtwdev->hw; 2800 struct ieee80211_txq *txq; 2801 struct rtw89_vif *rtwvif; 2802 struct rtw89_txq *rtwtxq; 2803 unsigned long frame_cnt; 2804 unsigned long byte_cnt; 2805 u32 tx_resource; 2806 bool sched_txq; 2807 2808 ieee80211_txq_schedule_start(hw, ac); 2809 while ((txq = ieee80211_next_txq(hw, ac))) { 2810 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2811 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv; 2812 2813 if (rtwvif->offchan) { 2814 ieee80211_return_txq(hw, txq, true); 2815 continue; 2816 } 2817 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2818 sched_txq = false; 2819 2820 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2821 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2822 ieee80211_return_txq(hw, txq, true); 2823 continue; 2824 } 2825 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2826 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2827 ieee80211_return_txq(hw, txq, sched_txq); 2828 if (frame_cnt != 0) 2829 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2830 2831 /* bound of tx_resource could get stuck due to burst traffic */ 2832 if (frame_cnt == tx_resource) 2833 *reinvoke = true; 2834 } 2835 ieee80211_txq_schedule_end(hw, ac); 2836 } 2837 2838 static void rtw89_ips_work(struct work_struct *work) 2839 { 2840 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2841 ips_work); 2842 mutex_lock(&rtwdev->mutex); 2843 rtw89_enter_ips_by_hwflags(rtwdev); 2844 mutex_unlock(&rtwdev->mutex); 2845 } 2846 2847 static void rtw89_core_txq_work(struct work_struct *w) 2848 { 2849 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2850 bool reinvoke = false; 2851 u8 ac; 2852 2853 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2854 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2855 2856 if (reinvoke) { 2857 /* reinvoke to process the last frame */ 2858 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2859 } 2860 } 2861 2862 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2863 { 2864 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2865 txq_reinvoke_work.work); 2866 2867 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2868 } 2869 2870 static void rtw89_forbid_ba_work(struct work_struct *w) 2871 { 2872 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2873 forbid_ba_work.work); 2874 struct rtw89_txq *rtwtxq, *tmp; 2875 2876 spin_lock_bh(&rtwdev->ba_lock); 2877 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2878 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2879 list_del_init(&rtwtxq->list); 2880 } 2881 spin_unlock_bh(&rtwdev->ba_lock); 2882 } 2883 2884 static void rtw89_core_sta_pending_tx_iter(void *data, 2885 struct ieee80211_sta *sta) 2886 { 2887 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2888 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif; 2889 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2890 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2891 struct sk_buff *skb, *tmp; 2892 int qsel, ret; 2893 2894 if (rtwvif->chanctx_idx != rtwvif_target->chanctx_idx) 2895 return; 2896 2897 if (skb_queue_len(&rtwsta->roc_queue) == 0) 2898 return; 2899 2900 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2901 skb_unlink(skb, &rtwsta->roc_queue); 2902 2903 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2904 if (ret) { 2905 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 2906 dev_kfree_skb_any(skb); 2907 } else { 2908 rtw89_core_tx_kick_off(rtwdev, qsel); 2909 } 2910 } 2911 } 2912 2913 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 2914 struct rtw89_vif *rtwvif) 2915 { 2916 ieee80211_iterate_stations_atomic(rtwdev->hw, 2917 rtw89_core_sta_pending_tx_iter, 2918 rtwvif); 2919 } 2920 2921 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 2922 struct rtw89_vif *rtwvif, bool qos, bool ps) 2923 { 2924 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2925 struct ieee80211_sta *sta; 2926 struct ieee80211_hdr *hdr; 2927 struct sk_buff *skb; 2928 int ret, qsel; 2929 2930 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 2931 return 0; 2932 2933 rcu_read_lock(); 2934 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 2935 if (!sta) { 2936 ret = -EINVAL; 2937 goto out; 2938 } 2939 2940 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos); 2941 if (!skb) { 2942 ret = -ENOMEM; 2943 goto out; 2944 } 2945 2946 hdr = (struct ieee80211_hdr *)skb->data; 2947 if (ps) 2948 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2949 2950 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2951 if (ret) { 2952 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 2953 dev_kfree_skb_any(skb); 2954 goto out; 2955 } 2956 2957 rcu_read_unlock(); 2958 2959 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 2960 RTW89_ROC_TX_TIMEOUT); 2961 out: 2962 rcu_read_unlock(); 2963 2964 return ret; 2965 } 2966 2967 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2968 { 2969 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2970 struct ieee80211_hw *hw = rtwdev->hw; 2971 struct rtw89_roc *roc = &rtwvif->roc; 2972 struct cfg80211_chan_def roc_chan; 2973 struct rtw89_vif *tmp; 2974 int ret; 2975 2976 lockdep_assert_held(&rtwdev->mutex); 2977 2978 rtw89_leave_ips_by_hwflags(rtwdev); 2979 rtw89_leave_lps(rtwdev); 2980 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC); 2981 2982 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true); 2983 if (ret) 2984 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2985 "roc send null-1 failed: %d\n", ret); 2986 2987 rtw89_for_each_rtwvif(rtwdev, tmp) 2988 if (tmp->chanctx_idx == rtwvif->chanctx_idx) 2989 tmp->offchan = true; 2990 2991 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 2992 rtw89_config_roc_chandef(rtwdev, rtwvif->chanctx_idx, &roc_chan); 2993 rtw89_set_channel(rtwdev); 2994 rtw89_write32_clr(rtwdev, 2995 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2996 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 2997 2998 ieee80211_ready_on_channel(hw); 2999 cancel_delayed_work(&rtwvif->roc.roc_work); 3000 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 3001 msecs_to_jiffies(rtwvif->roc.duration)); 3002 } 3003 3004 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3005 { 3006 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3007 struct ieee80211_hw *hw = rtwdev->hw; 3008 struct rtw89_roc *roc = &rtwvif->roc; 3009 struct rtw89_vif *tmp; 3010 int ret; 3011 3012 lockdep_assert_held(&rtwdev->mutex); 3013 3014 ieee80211_remain_on_channel_expired(hw); 3015 3016 rtw89_leave_ips_by_hwflags(rtwdev); 3017 rtw89_leave_lps(rtwdev); 3018 3019 rtw89_write32_mask(rtwdev, 3020 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 3021 B_AX_RX_FLTR_CFG_MASK, 3022 rtwdev->hal.rx_fltr); 3023 3024 roc->state = RTW89_ROC_IDLE; 3025 rtw89_config_roc_chandef(rtwdev, rtwvif->chanctx_idx, NULL); 3026 rtw89_chanctx_proceed(rtwdev); 3027 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false); 3028 if (ret) 3029 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3030 "roc send null-0 failed: %d\n", ret); 3031 3032 rtw89_for_each_rtwvif(rtwdev, tmp) 3033 if (tmp->chanctx_idx == rtwvif->chanctx_idx) 3034 tmp->offchan = false; 3035 3036 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif); 3037 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3038 3039 if (hw->conf.flags & IEEE80211_CONF_IDLE) 3040 ieee80211_queue_delayed_work(hw, &roc->roc_work, 3041 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 3042 } 3043 3044 void rtw89_roc_work(struct work_struct *work) 3045 { 3046 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3047 roc.roc_work.work); 3048 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3049 struct rtw89_roc *roc = &rtwvif->roc; 3050 3051 mutex_lock(&rtwdev->mutex); 3052 3053 switch (roc->state) { 3054 case RTW89_ROC_IDLE: 3055 rtw89_enter_ips_by_hwflags(rtwdev); 3056 break; 3057 case RTW89_ROC_MGMT: 3058 case RTW89_ROC_NORMAL: 3059 rtw89_roc_end(rtwdev, rtwvif); 3060 break; 3061 default: 3062 break; 3063 } 3064 3065 mutex_unlock(&rtwdev->mutex); 3066 } 3067 3068 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3069 u32 throughput, u64 cnt) 3070 { 3071 if (cnt < 100) 3072 return RTW89_TFC_IDLE; 3073 if (throughput > 50) 3074 return RTW89_TFC_HIGH; 3075 if (throughput > 10) 3076 return RTW89_TFC_MID; 3077 if (throughput > 2) 3078 return RTW89_TFC_LOW; 3079 return RTW89_TFC_ULTRA_LOW; 3080 } 3081 3082 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3083 struct rtw89_traffic_stats *stats) 3084 { 3085 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3086 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3087 3088 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 3089 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3090 3091 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3092 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3093 3094 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3095 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3096 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3097 stats->tx_cnt); 3098 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3099 stats->rx_cnt); 3100 stats->tx_avg_len = stats->tx_cnt ? 3101 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3102 stats->rx_avg_len = stats->rx_cnt ? 3103 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3104 3105 stats->tx_unicast = 0; 3106 stats->rx_unicast = 0; 3107 stats->tx_cnt = 0; 3108 stats->rx_cnt = 0; 3109 stats->rx_tf_periodic = stats->rx_tf_acc; 3110 stats->rx_tf_acc = 0; 3111 3112 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3113 return true; 3114 3115 return false; 3116 } 3117 3118 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3119 { 3120 struct rtw89_vif *rtwvif; 3121 bool tfc_changed; 3122 3123 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3124 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3125 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3126 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif); 3127 } 3128 3129 return tfc_changed; 3130 } 3131 3132 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3133 { 3134 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 3135 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 3136 rtwvif->tdls_peer) 3137 return; 3138 3139 if (rtwvif->offchan) 3140 return; 3141 3142 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 3143 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 3144 rtw89_enter_lps(rtwdev, rtwvif, true); 3145 } 3146 3147 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3148 { 3149 struct rtw89_vif *rtwvif; 3150 3151 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3152 rtw89_vif_enter_lps(rtwdev, rtwvif); 3153 } 3154 3155 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3156 { 3157 enum rtw89_entity_mode mode; 3158 3159 mode = rtw89_get_entity_mode(rtwdev); 3160 if (mode == RTW89_ENTITY_MODE_MCC) 3161 return; 3162 3163 rtw89_chip_rfk_track(rtwdev); 3164 } 3165 3166 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3167 { 3168 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3169 3170 if (mode == RTW89_ENTITY_MODE_MCC) 3171 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3172 else 3173 rtw89_process_p2p_ps(rtwdev, vif); 3174 } 3175 3176 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3177 struct rtw89_traffic_stats *stats) 3178 { 3179 stats->tx_unicast = 0; 3180 stats->rx_unicast = 0; 3181 stats->tx_cnt = 0; 3182 stats->rx_cnt = 0; 3183 ewma_tp_init(&stats->tx_ewma_tp); 3184 ewma_tp_init(&stats->rx_ewma_tp); 3185 } 3186 3187 static void rtw89_track_work(struct work_struct *work) 3188 { 3189 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3190 track_work.work); 3191 bool tfc_changed; 3192 3193 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3194 return; 3195 3196 mutex_lock(&rtwdev->mutex); 3197 3198 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3199 goto out; 3200 3201 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3202 RTW89_TRACK_WORK_PERIOD); 3203 3204 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3205 if (rtwdev->scanning) 3206 goto out; 3207 3208 rtw89_leave_lps(rtwdev); 3209 3210 if (tfc_changed) { 3211 rtw89_hci_recalc_int_mit(rtwdev); 3212 rtw89_btc_ntfy_wl_sta(rtwdev); 3213 } 3214 rtw89_mac_bf_monitor_track(rtwdev); 3215 rtw89_phy_stat_track(rtwdev); 3216 rtw89_phy_env_monitor_track(rtwdev); 3217 rtw89_phy_dig(rtwdev); 3218 rtw89_core_rfk_track(rtwdev); 3219 rtw89_phy_ra_update(rtwdev); 3220 rtw89_phy_cfo_track(rtwdev); 3221 rtw89_phy_tx_path_div_track(rtwdev); 3222 rtw89_phy_antdiv_track(rtwdev); 3223 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3224 rtw89_phy_edcca_track(rtwdev); 3225 rtw89_tas_track(rtwdev); 3226 rtw89_chanctx_track(rtwdev); 3227 rtw89_core_rfkill_poll(rtwdev, false); 3228 3229 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3230 rtw89_enter_lps_track(rtwdev); 3231 3232 out: 3233 mutex_unlock(&rtwdev->mutex); 3234 } 3235 3236 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3237 { 3238 unsigned long bit; 3239 3240 bit = find_first_zero_bit(addr, size); 3241 if (bit < size) 3242 set_bit(bit, addr); 3243 3244 return bit; 3245 } 3246 3247 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3248 { 3249 clear_bit(bit, addr); 3250 } 3251 3252 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3253 { 3254 bitmap_zero(addr, nbits); 3255 } 3256 3257 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3258 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3259 { 3260 const struct rtw89_chip_info *chip = rtwdev->chip; 3261 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3262 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3263 u8 idx; 3264 int i; 3265 3266 lockdep_assert_held(&rtwdev->mutex); 3267 3268 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3269 if (idx == chip->bacam_num) { 3270 /* allocate a static BA CAM to tid=0/5, so replace the existing 3271 * one if BA CAM is full. Hardware will process the original tid 3272 * automatically. 3273 */ 3274 if (tid != 0 && tid != 5) 3275 return -ENOSPC; 3276 3277 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3278 tmp = &cam_info->ba_cam_entry[i]; 3279 if (tmp->tid == 0 || tmp->tid == 5) 3280 continue; 3281 3282 idx = i; 3283 entry = tmp; 3284 list_del(&entry->list); 3285 break; 3286 } 3287 3288 if (!entry) 3289 return -ENOSPC; 3290 } else { 3291 entry = &cam_info->ba_cam_entry[idx]; 3292 } 3293 3294 entry->tid = tid; 3295 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 3296 3297 *cam_idx = idx; 3298 3299 return 0; 3300 } 3301 3302 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3303 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3304 { 3305 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3306 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3307 u8 idx; 3308 3309 lockdep_assert_held(&rtwdev->mutex); 3310 3311 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 3312 if (entry->tid != tid) 3313 continue; 3314 3315 idx = entry - cam_info->ba_cam_entry; 3316 list_del(&entry->list); 3317 3318 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3319 *cam_idx = idx; 3320 return 0; 3321 } 3322 3323 return -ENOENT; 3324 } 3325 3326 #define RTW89_TYPE_MAPPING(_type) \ 3327 case NL80211_IFTYPE_ ## _type: \ 3328 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3329 break 3330 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 3331 { 3332 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3333 3334 switch (vif->type) { 3335 case NL80211_IFTYPE_STATION: 3336 if (vif->p2p) 3337 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3338 else 3339 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 3340 break; 3341 case NL80211_IFTYPE_AP: 3342 if (vif->p2p) 3343 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3344 else 3345 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 3346 break; 3347 RTW89_TYPE_MAPPING(ADHOC); 3348 RTW89_TYPE_MAPPING(MONITOR); 3349 RTW89_TYPE_MAPPING(MESH_POINT); 3350 default: 3351 WARN_ON(1); 3352 break; 3353 } 3354 3355 switch (vif->type) { 3356 case NL80211_IFTYPE_AP: 3357 case NL80211_IFTYPE_MESH_POINT: 3358 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 3359 rtwvif->self_role = RTW89_SELF_ROLE_AP; 3360 break; 3361 case NL80211_IFTYPE_ADHOC: 3362 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 3363 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3364 break; 3365 case NL80211_IFTYPE_STATION: 3366 if (assoc) { 3367 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 3368 rtwvif->trigger = vif->bss_conf.he_support; 3369 } else { 3370 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 3371 rtwvif->trigger = false; 3372 } 3373 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3374 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3375 break; 3376 case NL80211_IFTYPE_MONITOR: 3377 break; 3378 default: 3379 WARN_ON(1); 3380 break; 3381 } 3382 } 3383 3384 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3385 struct ieee80211_vif *vif, 3386 struct ieee80211_sta *sta) 3387 { 3388 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3389 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3390 struct rtw89_hal *hal = &rtwdev->hal; 3391 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3392 int i; 3393 int ret; 3394 3395 rtwsta->rtwdev = rtwdev; 3396 rtwsta->rtwvif = rtwvif; 3397 rtwsta->prev_rssi = 0; 3398 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 3399 skb_queue_head_init(&rtwsta->roc_queue); 3400 3401 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 3402 rtw89_core_txq_init(rtwdev, sta->txq[i]); 3403 3404 ewma_rssi_init(&rtwsta->avg_rssi); 3405 ewma_snr_init(&rtwsta->avg_snr); 3406 ewma_evm_init(&rtwsta->evm_1ss); 3407 for (i = 0; i < ant_num; i++) { 3408 ewma_rssi_init(&rtwsta->rssi[i]); 3409 ewma_evm_init(&rtwsta->evm_min[i]); 3410 ewma_evm_init(&rtwsta->evm_max[i]); 3411 } 3412 3413 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3414 /* for station mode, assign the mac_id from itself */ 3415 rtwsta->mac_id = rtwvif->mac_id; 3416 3417 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 3418 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif, true); 3419 if (ret) 3420 return ret; 3421 3422 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3423 BTC_ROLE_MSTS_STA_CONN_START); 3424 rtw89_chip_rfk_channel(rtwdev, rtwvif); 3425 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3426 rtwsta->mac_id = rtw89_acquire_mac_id(rtwdev); 3427 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 3428 return -ENOSPC; 3429 3430 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 3431 if (ret) { 3432 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3433 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3434 return ret; 3435 } 3436 3437 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3438 RTW89_ROLE_CREATE); 3439 if (ret) { 3440 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3441 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3442 return ret; 3443 } 3444 3445 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta); 3446 if (ret) 3447 return ret; 3448 3449 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta); 3450 if (ret) 3451 return ret; 3452 3453 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3454 } 3455 3456 return 0; 3457 } 3458 3459 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3460 struct ieee80211_vif *vif, 3461 struct ieee80211_sta *sta) 3462 { 3463 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3464 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3465 3466 if (vif->type == NL80211_IFTYPE_STATION) 3467 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false); 3468 3469 rtwdev->total_sta_assoc--; 3470 if (sta->tdls) 3471 rtwvif->tdls_peer--; 3472 rtwsta->disassoc = true; 3473 3474 return 0; 3475 } 3476 3477 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3478 struct ieee80211_vif *vif, 3479 struct ieee80211_sta *sta) 3480 { 3481 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3482 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3483 int ret; 3484 3485 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 3486 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 3487 rtw89_core_free_sta_pending_ba(rtwdev, sta); 3488 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 3489 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta); 3490 3491 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 3492 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 3493 if (sta->tdls) 3494 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 3495 3496 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3497 rtw89_vif_type_mapping(vif, false); 3498 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 3499 } 3500 3501 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3502 if (ret) { 3503 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3504 return ret; 3505 } 3506 3507 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 3508 if (ret) { 3509 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3510 return ret; 3511 } 3512 3513 /* update cam aid mac_id net_type */ 3514 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3515 if (ret) { 3516 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3517 return ret; 3518 } 3519 3520 return ret; 3521 } 3522 3523 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3524 struct ieee80211_vif *vif, 3525 struct ieee80211_sta *sta) 3526 { 3527 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3528 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3529 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 3530 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3531 rtwvif->chanctx_idx); 3532 int ret; 3533 3534 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3535 if (sta->tdls) { 3536 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 3537 if (ret) { 3538 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3539 return ret; 3540 } 3541 } 3542 3543 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 3544 if (ret) { 3545 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3546 return ret; 3547 } 3548 } 3549 3550 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3551 if (ret) { 3552 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3553 return ret; 3554 } 3555 3556 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 3557 if (ret) { 3558 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3559 return ret; 3560 } 3561 3562 /* update cam aid mac_id net_type */ 3563 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3564 if (ret) { 3565 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3566 return ret; 3567 } 3568 3569 rtwdev->total_sta_assoc++; 3570 if (sta->tdls) 3571 rtwvif->tdls_peer++; 3572 rtw89_phy_ra_assoc(rtwdev, sta); 3573 rtw89_mac_bf_assoc(rtwdev, vif, sta); 3574 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 3575 3576 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3577 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 3578 3579 if (bss_conf->he_support && 3580 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 3581 rtwsta->er_cap = true; 3582 3583 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3584 BTC_ROLE_MSTS_STA_CONN_END); 3585 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan); 3586 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 3587 3588 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 3589 if (ret) { 3590 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3591 return ret; 3592 } 3593 3594 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 3595 } 3596 3597 return ret; 3598 } 3599 3600 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3601 struct ieee80211_vif *vif, 3602 struct ieee80211_sta *sta) 3603 { 3604 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3605 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3606 int ret; 3607 3608 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3609 rtw89_reg_6ghz_recalc(rtwdev, rtwvif, false); 3610 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3611 BTC_ROLE_MSTS_STA_DIS_CONN); 3612 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3613 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3614 3615 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3616 RTW89_ROLE_REMOVE); 3617 if (ret) { 3618 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3619 return ret; 3620 } 3621 3622 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3623 } 3624 3625 return 0; 3626 } 3627 3628 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3629 struct ieee80211_sta *sta, 3630 struct cfg80211_tid_cfg *tid_conf) 3631 { 3632 struct ieee80211_txq *txq; 3633 struct rtw89_txq *rtwtxq; 3634 u32 mask = tid_conf->mask; 3635 u8 tids = tid_conf->tids; 3636 int tids_nbit = BITS_PER_BYTE; 3637 int i; 3638 3639 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3640 if (!tids) 3641 break; 3642 3643 if (!(tids & BIT(0))) 3644 continue; 3645 3646 txq = sta->txq[i]; 3647 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3648 3649 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 3650 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 3651 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3652 } else { 3653 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 3654 ieee80211_stop_tx_ba_session(sta, txq->tid); 3655 spin_lock_bh(&rtwdev->ba_lock); 3656 list_del_init(&rtwtxq->list); 3657 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3658 spin_unlock_bh(&rtwdev->ba_lock); 3659 } 3660 } 3661 3662 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 3663 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 3664 sta->max_amsdu_subframes = 0; 3665 else 3666 sta->max_amsdu_subframes = 1; 3667 } 3668 } 3669 } 3670 3671 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3672 struct ieee80211_sta *sta, 3673 struct cfg80211_tid_config *tid_config) 3674 { 3675 int i; 3676 3677 for (i = 0; i < tid_config->n_tid_conf; i++) 3678 _rtw89_core_set_tid_config(rtwdev, sta, 3679 &tid_config->tid_conf[i]); 3680 } 3681 3682 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 3683 struct ieee80211_sta_ht_cap *ht_cap) 3684 { 3685 static const __le16 highest[RF_PATH_MAX] = { 3686 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 3687 }; 3688 struct rtw89_hal *hal = &rtwdev->hal; 3689 u8 nss = hal->rx_nss; 3690 int i; 3691 3692 ht_cap->ht_supported = true; 3693 ht_cap->cap = 0; 3694 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 3695 IEEE80211_HT_CAP_MAX_AMSDU | 3696 IEEE80211_HT_CAP_TX_STBC | 3697 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 3698 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 3699 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 3700 IEEE80211_HT_CAP_DSSSCCK40 | 3701 IEEE80211_HT_CAP_SGI_40; 3702 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 3703 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 3704 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 3705 for (i = 0; i < nss; i++) 3706 ht_cap->mcs.rx_mask[i] = 0xFF; 3707 ht_cap->mcs.rx_mask[4] = 0x01; 3708 ht_cap->mcs.rx_highest = highest[nss - 1]; 3709 } 3710 3711 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 3712 struct ieee80211_sta_vht_cap *vht_cap) 3713 { 3714 static const __le16 highest_bw80[RF_PATH_MAX] = { 3715 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 3716 }; 3717 static const __le16 highest_bw160[RF_PATH_MAX] = { 3718 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 3719 }; 3720 const struct rtw89_chip_info *chip = rtwdev->chip; 3721 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 3722 highest_bw160 : highest_bw80; 3723 struct rtw89_hal *hal = &rtwdev->hal; 3724 u16 tx_mcs_map = 0, rx_mcs_map = 0; 3725 u8 sts_cap = 3; 3726 int i; 3727 3728 for (i = 0; i < 8; i++) { 3729 if (i < hal->tx_nss) 3730 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3731 else 3732 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3733 if (i < hal->rx_nss) 3734 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3735 else 3736 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3737 } 3738 3739 vht_cap->vht_supported = true; 3740 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 3741 IEEE80211_VHT_CAP_SHORT_GI_80 | 3742 IEEE80211_VHT_CAP_RXSTBC_1 | 3743 IEEE80211_VHT_CAP_HTC_VHT | 3744 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 3745 0; 3746 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 3747 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 3748 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 3749 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 3750 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 3751 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3752 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 3753 IEEE80211_VHT_CAP_SHORT_GI_160; 3754 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 3755 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 3756 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 3757 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 3758 3759 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 3760 vht_cap->vht_mcs.tx_highest |= 3761 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 3762 } 3763 3764 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 3765 enum nl80211_band band, 3766 enum nl80211_iftype iftype, 3767 struct ieee80211_sband_iftype_data *iftype_data) 3768 { 3769 const struct rtw89_chip_info *chip = rtwdev->chip; 3770 struct rtw89_hal *hal = &rtwdev->hal; 3771 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 3772 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 3773 struct ieee80211_sta_he_cap *he_cap; 3774 int nss = hal->rx_nss; 3775 u8 *mac_cap_info; 3776 u8 *phy_cap_info; 3777 u16 mcs_map = 0; 3778 int i; 3779 3780 for (i = 0; i < 8; i++) { 3781 if (i < nss) 3782 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 3783 else 3784 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 3785 } 3786 3787 he_cap = &iftype_data->he_cap; 3788 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 3789 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 3790 3791 he_cap->has_he = true; 3792 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 3793 if (iftype == NL80211_IFTYPE_STATION) 3794 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 3795 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 3796 IEEE80211_HE_MAC_CAP2_BSR; 3797 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 3798 if (iftype == NL80211_IFTYPE_AP) 3799 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 3800 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 3801 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 3802 if (iftype == NL80211_IFTYPE_STATION) 3803 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 3804 if (band == NL80211_BAND_2GHZ) { 3805 phy_cap_info[0] = 3806 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 3807 } else { 3808 phy_cap_info[0] = 3809 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 3810 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3811 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 3812 } 3813 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 3814 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 3815 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 3816 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 3817 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 3818 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 3819 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 3820 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 3821 if (iftype == NL80211_IFTYPE_STATION) 3822 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 3823 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 3824 if (iftype == NL80211_IFTYPE_AP) 3825 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 3826 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 3827 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 3828 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3829 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 3830 phy_cap_info[5] = no_ng16 ? 0 : 3831 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 3832 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 3833 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 3834 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 3835 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 3836 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 3837 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 3838 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 3839 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 3840 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 3841 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 3842 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 3843 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3844 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 3845 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 3846 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 3847 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 3848 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 3849 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 3850 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 3851 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 3852 if (iftype == NL80211_IFTYPE_STATION) 3853 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 3854 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 3855 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 3856 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 3857 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 3858 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 3859 } 3860 3861 if (band == NL80211_BAND_6GHZ) { 3862 __le16 capa; 3863 3864 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 3865 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 3866 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 3867 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 3868 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 3869 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 3870 iftype_data->he_6ghz_capa.capa = capa; 3871 } 3872 } 3873 3874 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 3875 enum nl80211_band band, 3876 enum nl80211_iftype iftype, 3877 struct ieee80211_sband_iftype_data *iftype_data) 3878 { 3879 const struct rtw89_chip_info *chip = rtwdev->chip; 3880 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 3881 struct ieee80211_eht_mcs_nss_supp *eht_nss; 3882 struct ieee80211_sta_eht_cap *eht_cap; 3883 struct rtw89_hal *hal = &rtwdev->hal; 3884 bool support_320mhz = false; 3885 int sts = 8; 3886 u8 val; 3887 3888 if (chip->chip_gen == RTW89_CHIP_AX) 3889 return; 3890 3891 if (band == NL80211_BAND_6GHZ && 3892 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 3893 support_320mhz = true; 3894 3895 eht_cap = &iftype_data->eht_cap; 3896 eht_cap_elem = &eht_cap->eht_cap_elem; 3897 eht_nss = &eht_cap->eht_mcs_nss_supp; 3898 3899 eht_cap->has_eht = true; 3900 3901 eht_cap_elem->mac_cap_info[0] = 3902 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 3903 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 3904 eht_cap_elem->mac_cap_info[1] = 0; 3905 3906 eht_cap_elem->phy_cap_info[0] = 3907 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 3908 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 3909 if (support_320mhz) 3910 eht_cap_elem->phy_cap_info[0] |= 3911 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 3912 3913 eht_cap_elem->phy_cap_info[0] |= 3914 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 3915 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 3916 eht_cap_elem->phy_cap_info[1] = 3917 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 3918 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 3919 u8_encode_bits(sts - 1, 3920 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 3921 if (support_320mhz) 3922 eht_cap_elem->phy_cap_info[1] |= 3923 u8_encode_bits(sts - 1, 3924 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 3925 3926 eht_cap_elem->phy_cap_info[2] = 0; 3927 3928 eht_cap_elem->phy_cap_info[3] = 3929 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 3930 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 3931 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 3932 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 3933 3934 eht_cap_elem->phy_cap_info[4] = 3935 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 3936 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 3937 3938 eht_cap_elem->phy_cap_info[5] = 3939 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 3940 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 3941 3942 eht_cap_elem->phy_cap_info[6] = 0; 3943 eht_cap_elem->phy_cap_info[7] = 0; 3944 eht_cap_elem->phy_cap_info[8] = 0; 3945 3946 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 3947 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 3948 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 3949 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 3950 eht_nss->bw._80.rx_tx_mcs13_max_nss = val; 3951 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 3952 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 3953 eht_nss->bw._160.rx_tx_mcs13_max_nss = val; 3954 if (support_320mhz) { 3955 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 3956 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 3957 eht_nss->bw._320.rx_tx_mcs13_max_nss = val; 3958 } 3959 } 3960 3961 #define RTW89_SBAND_IFTYPES_NR 2 3962 3963 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 3964 enum nl80211_band band, 3965 struct ieee80211_supported_band *sband) 3966 { 3967 struct ieee80211_sband_iftype_data *iftype_data; 3968 enum nl80211_iftype iftype; 3969 int idx = 0; 3970 3971 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 3972 if (!iftype_data) 3973 return; 3974 3975 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 3976 switch (iftype) { 3977 case NL80211_IFTYPE_STATION: 3978 case NL80211_IFTYPE_AP: 3979 break; 3980 default: 3981 continue; 3982 } 3983 3984 if (idx >= RTW89_SBAND_IFTYPES_NR) { 3985 rtw89_warn(rtwdev, "run out of iftype_data\n"); 3986 break; 3987 } 3988 3989 iftype_data[idx].types_mask = BIT(iftype); 3990 3991 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 3992 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 3993 3994 idx++; 3995 } 3996 3997 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 3998 } 3999 4000 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 4001 { 4002 struct ieee80211_hw *hw = rtwdev->hw; 4003 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 4004 struct ieee80211_supported_band *sband_6ghz = NULL; 4005 u32 size = sizeof(struct ieee80211_supported_band); 4006 u8 support_bands = rtwdev->chip->support_bands; 4007 4008 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 4009 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 4010 if (!sband_2ghz) 4011 goto err; 4012 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 4013 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 4014 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 4015 } 4016 4017 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 4018 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 4019 if (!sband_5ghz) 4020 goto err; 4021 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 4022 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 4023 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 4024 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 4025 } 4026 4027 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 4028 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 4029 if (!sband_6ghz) 4030 goto err; 4031 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 4032 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 4033 } 4034 4035 return 0; 4036 4037 err: 4038 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4039 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4040 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4041 if (sband_2ghz) 4042 kfree((__force void *)sband_2ghz->iftype_data); 4043 if (sband_5ghz) 4044 kfree((__force void *)sband_5ghz->iftype_data); 4045 if (sband_6ghz) 4046 kfree((__force void *)sband_6ghz->iftype_data); 4047 kfree(sband_2ghz); 4048 kfree(sband_5ghz); 4049 kfree(sband_6ghz); 4050 return -ENOMEM; 4051 } 4052 4053 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 4054 { 4055 struct ieee80211_hw *hw = rtwdev->hw; 4056 4057 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 4058 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 4059 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 4060 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 4061 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 4062 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 4063 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 4064 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 4065 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 4066 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4067 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4068 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4069 } 4070 4071 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 4072 { 4073 int i; 4074 4075 for (i = 0; i < RTW89_PHY_MAX; i++) 4076 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4077 for (i = 0; i < RTW89_PHY_MAX; i++) 4078 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4079 } 4080 4081 void rtw89_core_update_beacon_work(struct work_struct *work) 4082 { 4083 struct rtw89_dev *rtwdev; 4084 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 4085 update_beacon_work); 4086 4087 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 4088 return; 4089 4090 rtwdev = rtwvif->rtwdev; 4091 mutex_lock(&rtwdev->mutex); 4092 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif); 4093 mutex_unlock(&rtwdev->mutex); 4094 } 4095 4096 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4097 { 4098 struct completion *cmpl = &wait->completion; 4099 unsigned long time_left; 4100 unsigned int cur; 4101 4102 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4103 if (cur != RTW89_WAIT_COND_IDLE) 4104 return -EBUSY; 4105 4106 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4107 if (time_left == 0) { 4108 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4109 return -ETIMEDOUT; 4110 } 4111 4112 if (wait->data.err) 4113 return -EFAULT; 4114 4115 return 0; 4116 } 4117 4118 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4119 const struct rtw89_completion_data *data) 4120 { 4121 unsigned int cur; 4122 4123 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4124 if (cur != cond) 4125 return; 4126 4127 wait->data = *data; 4128 complete(&wait->completion); 4129 } 4130 4131 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4132 { 4133 u16 bt_req_len; 4134 4135 switch (event) { 4136 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4137 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4138 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4139 "coex updates BT req len to %d TU\n", bt_req_len); 4140 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4141 break; 4142 default: 4143 if (event < NUM_OF_RTW89_BTC_HMSG) 4144 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4145 "unhandled BTC HMSG event: %d\n", event); 4146 else 4147 rtw89_warn(rtwdev, 4148 "unrecognized BTC HMSG event: %d\n", event); 4149 break; 4150 } 4151 } 4152 4153 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4154 { 4155 const struct dmi_system_id *match; 4156 enum rtw89_quirks quirk; 4157 4158 if (!quirks) 4159 return; 4160 4161 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4162 quirk = (uintptr_t)match->driver_data; 4163 if (quirk >= NUM_OF_RTW89_QUIRKS) 4164 continue; 4165 4166 set_bit(quirk, rtwdev->quirks); 4167 } 4168 } 4169 EXPORT_SYMBOL(rtw89_check_quirks); 4170 4171 int rtw89_core_start(struct rtw89_dev *rtwdev) 4172 { 4173 int ret; 4174 4175 ret = rtw89_mac_init(rtwdev); 4176 if (ret) { 4177 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4178 return ret; 4179 } 4180 4181 rtw89_btc_ntfy_poweron(rtwdev); 4182 4183 /* efuse process */ 4184 4185 /* pre-config BB/RF, BB reset/RFC reset */ 4186 ret = rtw89_chip_reset_bb_rf(rtwdev); 4187 if (ret) 4188 return ret; 4189 4190 rtw89_phy_init_bb_reg(rtwdev); 4191 rtw89_chip_bb_postinit(rtwdev); 4192 rtw89_phy_init_rf_reg(rtwdev, false); 4193 4194 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4195 4196 rtw89_phy_dm_init(rtwdev); 4197 4198 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 4199 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 4200 4201 rtw89_tas_reset(rtwdev); 4202 4203 ret = rtw89_hci_start(rtwdev); 4204 if (ret) { 4205 rtw89_err(rtwdev, "failed to start hci\n"); 4206 return ret; 4207 } 4208 4209 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 4210 RTW89_TRACK_WORK_PERIOD); 4211 4212 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4213 4214 rtw89_chip_rfk_init_late(rtwdev); 4215 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4216 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4217 rtw89_fw_h2c_init_ba_cam(rtwdev); 4218 4219 return 0; 4220 } 4221 4222 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4223 { 4224 struct rtw89_btc *btc = &rtwdev->btc; 4225 4226 /* Prvent to stop twice; enter_ips and ops_stop */ 4227 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4228 return; 4229 4230 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4231 4232 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4233 4234 mutex_unlock(&rtwdev->mutex); 4235 4236 cancel_work_sync(&rtwdev->c2h_work); 4237 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work); 4238 cancel_work_sync(&btc->eapol_notify_work); 4239 cancel_work_sync(&btc->arp_notify_work); 4240 cancel_work_sync(&btc->dhcp_notify_work); 4241 cancel_work_sync(&btc->icmp_notify_work); 4242 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4243 cancel_delayed_work_sync(&rtwdev->track_work); 4244 cancel_delayed_work_sync(&rtwdev->chanctx_work); 4245 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 4246 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 4247 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 4248 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 4249 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4250 cancel_delayed_work_sync(&rtwdev->antdiv_work); 4251 4252 mutex_lock(&rtwdev->mutex); 4253 4254 rtw89_btc_ntfy_poweroff(rtwdev); 4255 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4256 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4257 rtw89_hci_stop(rtwdev); 4258 rtw89_hci_deinit(rtwdev); 4259 rtw89_mac_pwr_off(rtwdev); 4260 rtw89_hci_reset(rtwdev); 4261 } 4262 4263 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 4264 { 4265 const struct rtw89_chip_info *chip = rtwdev->chip; 4266 u8 mac_id_num = chip->support_macid_num; 4267 u8 mac_id; 4268 4269 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 4270 if (mac_id == mac_id_num) 4271 return RTW89_MAX_MAC_ID_NUM; 4272 4273 set_bit(mac_id, rtwdev->mac_id_map); 4274 return mac_id; 4275 } 4276 4277 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 4278 { 4279 clear_bit(mac_id, rtwdev->mac_id_map); 4280 } 4281 4282 int rtw89_core_init(struct rtw89_dev *rtwdev) 4283 { 4284 struct rtw89_btc *btc = &rtwdev->btc; 4285 u8 band; 4286 4287 INIT_LIST_HEAD(&rtwdev->ba_list); 4288 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 4289 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 4290 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 4291 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 4292 if (!(rtwdev->chip->support_bands & BIT(band))) 4293 continue; 4294 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 4295 } 4296 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 4297 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 4298 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 4299 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 4300 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); 4301 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 4302 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 4303 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 4304 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 4305 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 4306 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 4307 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 4308 if (!rtwdev->txq_wq) 4309 return -ENOMEM; 4310 spin_lock_init(&rtwdev->ba_lock); 4311 spin_lock_init(&rtwdev->rpwm_lock); 4312 mutex_init(&rtwdev->mutex); 4313 mutex_init(&rtwdev->rf_mutex); 4314 rtwdev->total_sta_assoc = 0; 4315 4316 rtw89_init_wait(&rtwdev->mcc.wait); 4317 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 4318 4319 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 4320 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 4321 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 4322 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 4323 4324 skb_queue_head_init(&rtwdev->c2h_queue); 4325 rtw89_core_ppdu_sts_init(rtwdev); 4326 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 4327 4328 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 4329 rtwdev->dbcc_en = false; 4330 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 4331 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 4332 4333 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4334 rtwdev->dbcc_en = true; 4335 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 4336 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF; 4337 } 4338 4339 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 4340 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 4341 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 4342 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 4343 4344 init_completion(&rtwdev->fw.req.completion); 4345 init_completion(&rtwdev->rfk_wait.completion); 4346 4347 schedule_work(&rtwdev->load_firmware_work); 4348 4349 rtw89_ser_init(rtwdev); 4350 rtw89_entity_init(rtwdev); 4351 rtw89_tas_init(rtwdev); 4352 4353 return 0; 4354 } 4355 EXPORT_SYMBOL(rtw89_core_init); 4356 4357 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 4358 { 4359 rtw89_ser_deinit(rtwdev); 4360 rtw89_unload_firmware(rtwdev); 4361 rtw89_fw_free_all_early_h2c(rtwdev); 4362 4363 destroy_workqueue(rtwdev->txq_wq); 4364 mutex_destroy(&rtwdev->rf_mutex); 4365 mutex_destroy(&rtwdev->mutex); 4366 } 4367 EXPORT_SYMBOL(rtw89_core_deinit); 4368 4369 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4370 const u8 *mac_addr, bool hw_scan) 4371 { 4372 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4373 rtwvif->chanctx_idx); 4374 4375 rtwdev->scanning = true; 4376 rtw89_leave_lps(rtwdev); 4377 if (hw_scan) 4378 rtw89_leave_ips_by_hwflags(rtwdev); 4379 4380 ether_addr_copy(rtwvif->mac_addr, mac_addr); 4381 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 4382 rtw89_chip_rfk_scan(rtwdev, rtwvif, true); 4383 rtw89_hci_recalc_int_mit(rtwdev); 4384 rtw89_phy_config_edcca(rtwdev, true); 4385 4386 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 4387 } 4388 4389 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4390 struct ieee80211_vif *vif, bool hw_scan) 4391 { 4392 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4393 4394 if (!rtwvif) 4395 return; 4396 4397 ether_addr_copy(rtwvif->mac_addr, vif->addr); 4398 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4399 4400 rtw89_chip_rfk_scan(rtwdev, rtwvif, false); 4401 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 4402 rtw89_phy_config_edcca(rtwdev, false); 4403 4404 rtwdev->scanning = false; 4405 rtwdev->dig.bypass_dig = true; 4406 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 4407 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 4408 } 4409 4410 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 4411 { 4412 const struct rtw89_chip_info *chip = rtwdev->chip; 4413 int ret; 4414 u8 val; 4415 u8 cv; 4416 4417 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 4418 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 4419 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 4420 cv = CHIP_CAV; 4421 else 4422 cv = CHIP_CBV; 4423 } 4424 4425 rtwdev->hal.cv = cv; 4426 4427 if (rtw89_is_rtl885xb(rtwdev)) { 4428 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 4429 if (ret) 4430 return; 4431 4432 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 4433 } 4434 } 4435 4436 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 4437 { 4438 rtwdev->hal.support_cckpd = 4439 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 4440 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 4441 rtwdev->hal.support_igi = 4442 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 4443 } 4444 4445 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 4446 { 4447 const struct rtw89_chip_info *chip = rtwdev->chip; 4448 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 4449 struct rtw89_efuse *efuse = &rtwdev->efuse; 4450 const struct rtw89_rfe_parms *sel; 4451 u8 rfe_type = efuse->rfe_type; 4452 4453 if (!conf) { 4454 sel = chip->dflt_parms; 4455 goto out; 4456 } 4457 4458 while (conf->rfe_parms) { 4459 if (rfe_type == conf->rfe_type) { 4460 sel = conf->rfe_parms; 4461 goto out; 4462 } 4463 conf++; 4464 } 4465 4466 sel = chip->dflt_parms; 4467 4468 out: 4469 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 4470 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 4471 } 4472 4473 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 4474 { 4475 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4476 int ret; 4477 4478 ret = rtw89_mac_partial_init(rtwdev, false); 4479 if (ret) 4480 return ret; 4481 4482 ret = mac->parse_efuse_map(rtwdev); 4483 if (ret) 4484 return ret; 4485 4486 ret = mac->parse_phycap_map(rtwdev); 4487 if (ret) 4488 return ret; 4489 4490 ret = rtw89_mac_setup_phycap(rtwdev); 4491 if (ret) 4492 return ret; 4493 4494 rtw89_core_setup_phycap(rtwdev); 4495 4496 rtw89_hci_mac_pre_deinit(rtwdev); 4497 4498 rtw89_mac_pwr_off(rtwdev); 4499 4500 return 0; 4501 } 4502 4503 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 4504 { 4505 rtw89_chip_fem_setup(rtwdev); 4506 4507 return 0; 4508 } 4509 4510 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev) 4511 { 4512 return !!rtwdev->chip->rfkill_init; 4513 } 4514 4515 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev) 4516 { 4517 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init; 4518 4519 rtw89_write16_mask(rtwdev, regs->pinmux.addr, 4520 regs->pinmux.mask, regs->pinmux.data); 4521 rtw89_write16_mask(rtwdev, regs->mode.addr, 4522 regs->mode.mask, regs->mode.data); 4523 } 4524 4525 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev) 4526 { 4527 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get; 4528 4529 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask); 4530 } 4531 4532 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev) 4533 { 4534 if (!rtw89_chip_has_rfkill(rtwdev)) 4535 return; 4536 4537 rtw89_core_rfkill_init(rtwdev); 4538 rtw89_core_rfkill_poll(rtwdev, true); 4539 wiphy_rfkill_start_polling(rtwdev->hw->wiphy); 4540 } 4541 4542 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev) 4543 { 4544 if (!rtw89_chip_has_rfkill(rtwdev)) 4545 return; 4546 4547 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy); 4548 } 4549 4550 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force) 4551 { 4552 bool prev, blocked; 4553 4554 if (!rtw89_chip_has_rfkill(rtwdev)) 4555 return; 4556 4557 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 4558 blocked = rtw89_core_rfkill_get(rtwdev); 4559 4560 if (!force && prev == blocked) 4561 return; 4562 4563 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n", 4564 blocked ? "disable" : "enable"); 4565 4566 if (blocked) 4567 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 4568 else 4569 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 4570 4571 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked); 4572 } 4573 4574 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 4575 { 4576 int ret; 4577 4578 rtw89_read_chip_ver(rtwdev); 4579 4580 ret = rtw89_wait_firmware_completion(rtwdev); 4581 if (ret) { 4582 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 4583 return ret; 4584 } 4585 4586 ret = rtw89_fw_recognize(rtwdev); 4587 if (ret) { 4588 rtw89_err(rtwdev, "failed to recognize firmware\n"); 4589 return ret; 4590 } 4591 4592 ret = rtw89_chip_efuse_info_setup(rtwdev); 4593 if (ret) 4594 return ret; 4595 4596 ret = rtw89_fw_recognize_elements(rtwdev); 4597 if (ret) { 4598 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 4599 return ret; 4600 } 4601 4602 ret = rtw89_chip_board_info_setup(rtwdev); 4603 if (ret) 4604 return ret; 4605 4606 rtw89_core_setup_rfe_parms(rtwdev); 4607 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 4608 4609 return 0; 4610 } 4611 EXPORT_SYMBOL(rtw89_chip_info_setup); 4612 4613 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 4614 { 4615 const struct rtw89_chip_info *chip = rtwdev->chip; 4616 struct ieee80211_hw *hw = rtwdev->hw; 4617 struct rtw89_efuse *efuse = &rtwdev->efuse; 4618 struct rtw89_hal *hal = &rtwdev->hal; 4619 int ret; 4620 int tx_headroom = IEEE80211_HT_CTL_LEN; 4621 4622 hw->vif_data_size = sizeof(struct rtw89_vif); 4623 hw->sta_data_size = sizeof(struct rtw89_sta); 4624 hw->txq_data_size = sizeof(struct rtw89_txq); 4625 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 4626 4627 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 4628 4629 hw->extra_tx_headroom = tx_headroom; 4630 hw->queues = IEEE80211_NUM_ACS; 4631 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 4632 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 4633 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 4634 4635 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 4636 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 4637 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 4638 4639 ieee80211_hw_set(hw, SIGNAL_DBM); 4640 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 4641 ieee80211_hw_set(hw, MFP_CAPABLE); 4642 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 4643 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 4644 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 4645 ieee80211_hw_set(hw, TX_AMSDU); 4646 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 4647 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 4648 ieee80211_hw_set(hw, SUPPORTS_PS); 4649 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 4650 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 4651 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 4652 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 4653 4654 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4655 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 4656 4657 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 4658 ieee80211_hw_set(hw, CONNECTION_MONITOR); 4659 4660 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 4661 BIT(NL80211_IFTYPE_AP) | 4662 BIT(NL80211_IFTYPE_P2P_CLIENT) | 4663 BIT(NL80211_IFTYPE_P2P_GO); 4664 4665 if (hal->ant_diversity) { 4666 hw->wiphy->available_antennas_tx = 0x3; 4667 hw->wiphy->available_antennas_rx = 0x3; 4668 } else { 4669 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 4670 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 4671 } 4672 4673 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 4674 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 4675 WIPHY_FLAG_AP_UAPSD | 4676 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 4677 4678 if (!chip->support_rnr) 4679 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 4680 4681 if (chip->chip_gen == RTW89_CHIP_BE) 4682 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 4683 4684 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 4685 4686 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 4687 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 4688 4689 #ifdef CONFIG_PM 4690 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 4691 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 4692 #endif 4693 4694 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4695 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4696 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4697 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4698 hw->wiphy->max_remain_on_channel_duration = 1000; 4699 4700 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 4701 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 4702 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 4703 4704 ret = rtw89_core_set_supported_band(rtwdev); 4705 if (ret) { 4706 rtw89_err(rtwdev, "failed to set supported band\n"); 4707 return ret; 4708 } 4709 4710 ret = rtw89_regd_setup(rtwdev); 4711 if (ret) { 4712 rtw89_err(rtwdev, "failed to set up regd\n"); 4713 goto err_free_supported_band; 4714 } 4715 4716 hw->wiphy->sar_capa = &rtw89_sar_capa; 4717 4718 ret = ieee80211_register_hw(hw); 4719 if (ret) { 4720 rtw89_err(rtwdev, "failed to register hw\n"); 4721 goto err_free_supported_band; 4722 } 4723 4724 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 4725 if (ret) { 4726 rtw89_err(rtwdev, "failed to init regd\n"); 4727 goto err_unregister_hw; 4728 } 4729 4730 rtw89_rfkill_polling_init(rtwdev); 4731 4732 return 0; 4733 4734 err_unregister_hw: 4735 ieee80211_unregister_hw(hw); 4736 err_free_supported_band: 4737 rtw89_core_clr_supported_band(rtwdev); 4738 4739 return ret; 4740 } 4741 4742 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 4743 { 4744 struct ieee80211_hw *hw = rtwdev->hw; 4745 4746 rtw89_rfkill_polling_deinit(rtwdev); 4747 ieee80211_unregister_hw(hw); 4748 rtw89_core_clr_supported_band(rtwdev); 4749 } 4750 4751 int rtw89_core_register(struct rtw89_dev *rtwdev) 4752 { 4753 int ret; 4754 4755 ret = rtw89_core_register_hw(rtwdev); 4756 if (ret) { 4757 rtw89_err(rtwdev, "failed to register core hw\n"); 4758 return ret; 4759 } 4760 4761 rtw89_debugfs_init(rtwdev); 4762 4763 return 0; 4764 } 4765 EXPORT_SYMBOL(rtw89_core_register); 4766 4767 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 4768 { 4769 rtw89_core_unregister_hw(rtwdev); 4770 } 4771 EXPORT_SYMBOL(rtw89_core_unregister); 4772 4773 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4774 u32 bus_data_size, 4775 const struct rtw89_chip_info *chip) 4776 { 4777 struct rtw89_fw_info early_fw = {}; 4778 const struct firmware *firmware; 4779 struct ieee80211_hw *hw; 4780 struct rtw89_dev *rtwdev; 4781 struct ieee80211_ops *ops; 4782 u32 driver_data_size; 4783 int fw_format = -1; 4784 bool no_chanctx; 4785 4786 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 4787 4788 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 4789 if (!ops) 4790 goto err; 4791 4792 no_chanctx = chip->support_chanctx_num == 0 || 4793 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 4794 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 4795 4796 if (no_chanctx) { 4797 ops->add_chanctx = ieee80211_emulate_add_chanctx; 4798 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 4799 ops->change_chanctx = ieee80211_emulate_change_chanctx; 4800 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 4801 ops->assign_vif_chanctx = NULL; 4802 ops->unassign_vif_chanctx = NULL; 4803 ops->remain_on_channel = NULL; 4804 ops->cancel_remain_on_channel = NULL; 4805 } 4806 4807 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 4808 hw = ieee80211_alloc_hw(driver_data_size, ops); 4809 if (!hw) 4810 goto err; 4811 4812 hw->wiphy->iface_combinations = rtw89_iface_combs; 4813 4814 if (no_chanctx || chip->support_chanctx_num == 1) 4815 hw->wiphy->n_iface_combinations = 1; 4816 else 4817 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 4818 4819 rtwdev = hw->priv; 4820 rtwdev->hw = hw; 4821 rtwdev->dev = device; 4822 rtwdev->ops = ops; 4823 rtwdev->chip = chip; 4824 rtwdev->fw.req.firmware = firmware; 4825 rtwdev->fw.fw_format = fw_format; 4826 4827 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 4828 no_chanctx ? "without" : "with"); 4829 4830 return rtwdev; 4831 4832 err: 4833 kfree(ops); 4834 release_firmware(firmware); 4835 return NULL; 4836 } 4837 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 4838 4839 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 4840 { 4841 kfree(rtwdev->ops); 4842 kfree(rtwdev->rfe_data); 4843 release_firmware(rtwdev->fw.req.firmware); 4844 ieee80211_free_hw(rtwdev->hw); 4845 } 4846 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 4847 4848 MODULE_AUTHOR("Realtek Corporation"); 4849 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 4850 MODULE_LICENSE("Dual BSD/GPL"); 4851