1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 22 static bool rtw89_disable_ps_mode; 23 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 24 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 25 26 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 27 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 28 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 29 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 30 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 32 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 34 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 36 37 static struct ieee80211_channel rtw89_channels_2ghz[] = { 38 RTW89_DEF_CHAN_2G(2412, 1), 39 RTW89_DEF_CHAN_2G(2417, 2), 40 RTW89_DEF_CHAN_2G(2422, 3), 41 RTW89_DEF_CHAN_2G(2427, 4), 42 RTW89_DEF_CHAN_2G(2432, 5), 43 RTW89_DEF_CHAN_2G(2437, 6), 44 RTW89_DEF_CHAN_2G(2442, 7), 45 RTW89_DEF_CHAN_2G(2447, 8), 46 RTW89_DEF_CHAN_2G(2452, 9), 47 RTW89_DEF_CHAN_2G(2457, 10), 48 RTW89_DEF_CHAN_2G(2462, 11), 49 RTW89_DEF_CHAN_2G(2467, 12), 50 RTW89_DEF_CHAN_2G(2472, 13), 51 RTW89_DEF_CHAN_2G(2484, 14), 52 }; 53 54 static struct ieee80211_channel rtw89_channels_5ghz[] = { 55 RTW89_DEF_CHAN_5G(5180, 36), 56 RTW89_DEF_CHAN_5G(5200, 40), 57 RTW89_DEF_CHAN_5G(5220, 44), 58 RTW89_DEF_CHAN_5G(5240, 48), 59 RTW89_DEF_CHAN_5G(5260, 52), 60 RTW89_DEF_CHAN_5G(5280, 56), 61 RTW89_DEF_CHAN_5G(5300, 60), 62 RTW89_DEF_CHAN_5G(5320, 64), 63 RTW89_DEF_CHAN_5G(5500, 100), 64 RTW89_DEF_CHAN_5G(5520, 104), 65 RTW89_DEF_CHAN_5G(5540, 108), 66 RTW89_DEF_CHAN_5G(5560, 112), 67 RTW89_DEF_CHAN_5G(5580, 116), 68 RTW89_DEF_CHAN_5G(5600, 120), 69 RTW89_DEF_CHAN_5G(5620, 124), 70 RTW89_DEF_CHAN_5G(5640, 128), 71 RTW89_DEF_CHAN_5G(5660, 132), 72 RTW89_DEF_CHAN_5G(5680, 136), 73 RTW89_DEF_CHAN_5G(5700, 140), 74 RTW89_DEF_CHAN_5G(5720, 144), 75 RTW89_DEF_CHAN_5G(5745, 149), 76 RTW89_DEF_CHAN_5G(5765, 153), 77 RTW89_DEF_CHAN_5G(5785, 157), 78 RTW89_DEF_CHAN_5G(5805, 161), 79 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 80 RTW89_DEF_CHAN_5G(5845, 169), 81 RTW89_DEF_CHAN_5G(5865, 173), 82 RTW89_DEF_CHAN_5G(5885, 177), 83 }; 84 85 static struct ieee80211_channel rtw89_channels_6ghz[] = { 86 RTW89_DEF_CHAN_6G(5955, 1), 87 RTW89_DEF_CHAN_6G(5975, 5), 88 RTW89_DEF_CHAN_6G(5995, 9), 89 RTW89_DEF_CHAN_6G(6015, 13), 90 RTW89_DEF_CHAN_6G(6035, 17), 91 RTW89_DEF_CHAN_6G(6055, 21), 92 RTW89_DEF_CHAN_6G(6075, 25), 93 RTW89_DEF_CHAN_6G(6095, 29), 94 RTW89_DEF_CHAN_6G(6115, 33), 95 RTW89_DEF_CHAN_6G(6135, 37), 96 RTW89_DEF_CHAN_6G(6155, 41), 97 RTW89_DEF_CHAN_6G(6175, 45), 98 RTW89_DEF_CHAN_6G(6195, 49), 99 RTW89_DEF_CHAN_6G(6215, 53), 100 RTW89_DEF_CHAN_6G(6235, 57), 101 RTW89_DEF_CHAN_6G(6255, 61), 102 RTW89_DEF_CHAN_6G(6275, 65), 103 RTW89_DEF_CHAN_6G(6295, 69), 104 RTW89_DEF_CHAN_6G(6315, 73), 105 RTW89_DEF_CHAN_6G(6335, 77), 106 RTW89_DEF_CHAN_6G(6355, 81), 107 RTW89_DEF_CHAN_6G(6375, 85), 108 RTW89_DEF_CHAN_6G(6395, 89), 109 RTW89_DEF_CHAN_6G(6415, 93), 110 RTW89_DEF_CHAN_6G(6435, 97), 111 RTW89_DEF_CHAN_6G(6455, 101), 112 RTW89_DEF_CHAN_6G(6475, 105), 113 RTW89_DEF_CHAN_6G(6495, 109), 114 RTW89_DEF_CHAN_6G(6515, 113), 115 RTW89_DEF_CHAN_6G(6535, 117), 116 RTW89_DEF_CHAN_6G(6555, 121), 117 RTW89_DEF_CHAN_6G(6575, 125), 118 RTW89_DEF_CHAN_6G(6595, 129), 119 RTW89_DEF_CHAN_6G(6615, 133), 120 RTW89_DEF_CHAN_6G(6635, 137), 121 RTW89_DEF_CHAN_6G(6655, 141), 122 RTW89_DEF_CHAN_6G(6675, 145), 123 RTW89_DEF_CHAN_6G(6695, 149), 124 RTW89_DEF_CHAN_6G(6715, 153), 125 RTW89_DEF_CHAN_6G(6735, 157), 126 RTW89_DEF_CHAN_6G(6755, 161), 127 RTW89_DEF_CHAN_6G(6775, 165), 128 RTW89_DEF_CHAN_6G(6795, 169), 129 RTW89_DEF_CHAN_6G(6815, 173), 130 RTW89_DEF_CHAN_6G(6835, 177), 131 RTW89_DEF_CHAN_6G(6855, 181), 132 RTW89_DEF_CHAN_6G(6875, 185), 133 RTW89_DEF_CHAN_6G(6895, 189), 134 RTW89_DEF_CHAN_6G(6915, 193), 135 RTW89_DEF_CHAN_6G(6935, 197), 136 RTW89_DEF_CHAN_6G(6955, 201), 137 RTW89_DEF_CHAN_6G(6975, 205), 138 RTW89_DEF_CHAN_6G(6995, 209), 139 RTW89_DEF_CHAN_6G(7015, 213), 140 RTW89_DEF_CHAN_6G(7035, 217), 141 RTW89_DEF_CHAN_6G(7055, 221), 142 RTW89_DEF_CHAN_6G(7075, 225), 143 RTW89_DEF_CHAN_6G(7095, 229), 144 RTW89_DEF_CHAN_6G(7115, 233), 145 }; 146 147 static struct ieee80211_rate rtw89_bitrates[] = { 148 { .bitrate = 10, .hw_value = 0x00, }, 149 { .bitrate = 20, .hw_value = 0x01, }, 150 { .bitrate = 55, .hw_value = 0x02, }, 151 { .bitrate = 110, .hw_value = 0x03, }, 152 { .bitrate = 60, .hw_value = 0x04, }, 153 { .bitrate = 90, .hw_value = 0x05, }, 154 { .bitrate = 120, .hw_value = 0x06, }, 155 { .bitrate = 180, .hw_value = 0x07, }, 156 { .bitrate = 240, .hw_value = 0x08, }, 157 { .bitrate = 360, .hw_value = 0x09, }, 158 { .bitrate = 480, .hw_value = 0x0a, }, 159 { .bitrate = 540, .hw_value = 0x0b, }, 160 }; 161 162 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 163 { 164 .max = 1, 165 .types = BIT(NL80211_IFTYPE_STATION), 166 }, 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 170 BIT(NL80211_IFTYPE_P2P_GO) | 171 BIT(NL80211_IFTYPE_AP), 172 }, 173 }; 174 175 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 176 { 177 .max = 1, 178 .types = BIT(NL80211_IFTYPE_STATION), 179 }, 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 183 BIT(NL80211_IFTYPE_P2P_GO), 184 }, 185 }; 186 187 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 188 { 189 .limits = rtw89_iface_limits, 190 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 191 .max_interfaces = 2, 192 .num_different_channels = 1, 193 }, 194 { 195 .limits = rtw89_iface_limits_mcc, 196 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 197 .max_interfaces = 2, 198 .num_different_channels = 2, 199 }, 200 }; 201 202 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 203 { 204 struct ieee80211_rate rate; 205 206 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 207 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 208 return false; 209 } 210 211 rate = rtw89_bitrates[rpt_rate]; 212 *bitrate = rate.bitrate; 213 214 return true; 215 } 216 217 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 218 .band = NL80211_BAND_2GHZ, 219 .channels = rtw89_channels_2ghz, 220 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 221 .bitrates = rtw89_bitrates, 222 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 223 .ht_cap = {0}, 224 .vht_cap = {0}, 225 }; 226 227 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 228 .band = NL80211_BAND_5GHZ, 229 .channels = rtw89_channels_5ghz, 230 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 231 232 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 233 .bitrates = rtw89_bitrates + 4, 234 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 235 .ht_cap = {0}, 236 .vht_cap = {0}, 237 }; 238 239 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 240 .band = NL80211_BAND_6GHZ, 241 .channels = rtw89_channels_6ghz, 242 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 243 244 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 245 .bitrates = rtw89_bitrates + 4, 246 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 247 }; 248 249 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 250 struct rtw89_traffic_stats *stats, 251 struct sk_buff *skb, bool tx) 252 { 253 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 254 255 if (!ieee80211_is_data(hdr->frame_control)) 256 return; 257 258 if (is_broadcast_ether_addr(hdr->addr1) || 259 is_multicast_ether_addr(hdr->addr1)) 260 return; 261 262 if (tx) { 263 stats->tx_cnt++; 264 stats->tx_unicast += skb->len; 265 } else { 266 stats->rx_cnt++; 267 stats->rx_unicast += skb->len; 268 } 269 } 270 271 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 272 { 273 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 274 NL80211_CHAN_NO_HT); 275 } 276 277 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 278 struct rtw89_chan *chan) 279 { 280 struct ieee80211_channel *channel = chandef->chan; 281 enum nl80211_chan_width width = chandef->width; 282 u32 primary_freq, center_freq; 283 u8 center_chan; 284 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 285 u32 offset; 286 u8 band; 287 288 center_chan = channel->hw_value; 289 primary_freq = channel->center_freq; 290 center_freq = chandef->center_freq1; 291 292 switch (width) { 293 case NL80211_CHAN_WIDTH_20_NOHT: 294 case NL80211_CHAN_WIDTH_20: 295 bandwidth = RTW89_CHANNEL_WIDTH_20; 296 break; 297 case NL80211_CHAN_WIDTH_40: 298 bandwidth = RTW89_CHANNEL_WIDTH_40; 299 if (primary_freq > center_freq) { 300 center_chan -= 2; 301 } else { 302 center_chan += 2; 303 } 304 break; 305 case NL80211_CHAN_WIDTH_80: 306 case NL80211_CHAN_WIDTH_160: 307 bandwidth = nl_to_rtw89_bandwidth(width); 308 if (primary_freq > center_freq) { 309 offset = (primary_freq - center_freq - 10) / 20; 310 center_chan -= 2 + offset * 4; 311 } else { 312 offset = (center_freq - primary_freq - 10) / 20; 313 center_chan += 2 + offset * 4; 314 } 315 break; 316 default: 317 center_chan = 0; 318 break; 319 } 320 321 switch (channel->band) { 322 default: 323 case NL80211_BAND_2GHZ: 324 band = RTW89_BAND_2G; 325 break; 326 case NL80211_BAND_5GHZ: 327 band = RTW89_BAND_5G; 328 break; 329 case NL80211_BAND_6GHZ: 330 band = RTW89_BAND_6G; 331 break; 332 } 333 334 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 335 } 336 337 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 338 { 339 struct rtw89_hal *hal = &rtwdev->hal; 340 const struct rtw89_chip_info *chip = rtwdev->chip; 341 const struct rtw89_chan *chan; 342 enum rtw89_sub_entity_idx sub_entity_idx; 343 enum rtw89_sub_entity_idx roc_idx; 344 enum rtw89_phy_idx phy_idx; 345 enum rtw89_entity_mode mode; 346 bool entity_active; 347 348 entity_active = rtw89_get_entity_state(rtwdev); 349 if (!entity_active) 350 return; 351 352 mode = rtw89_get_entity_mode(rtwdev); 353 switch (mode) { 354 case RTW89_ENTITY_MODE_SCC: 355 case RTW89_ENTITY_MODE_MCC: 356 sub_entity_idx = RTW89_SUB_ENTITY_0; 357 break; 358 case RTW89_ENTITY_MODE_MCC_PREPARE: 359 sub_entity_idx = RTW89_SUB_ENTITY_1; 360 break; 361 default: 362 WARN(1, "Invalid ent mode: %d\n", mode); 363 return; 364 } 365 366 roc_idx = atomic_read(&hal->roc_entity_idx); 367 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 368 sub_entity_idx = roc_idx; 369 370 phy_idx = RTW89_PHY_0; 371 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 372 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 373 } 374 375 void rtw89_set_channel(struct rtw89_dev *rtwdev) 376 { 377 struct rtw89_hal *hal = &rtwdev->hal; 378 const struct rtw89_chip_info *chip = rtwdev->chip; 379 const struct rtw89_chan_rcd *chan_rcd; 380 const struct rtw89_chan *chan; 381 enum rtw89_sub_entity_idx sub_entity_idx; 382 enum rtw89_sub_entity_idx roc_idx; 383 enum rtw89_mac_idx mac_idx; 384 enum rtw89_phy_idx phy_idx; 385 struct rtw89_channel_help_params bak; 386 enum rtw89_entity_mode mode; 387 bool entity_active; 388 389 entity_active = rtw89_get_entity_state(rtwdev); 390 391 mode = rtw89_entity_recalc(rtwdev); 392 switch (mode) { 393 case RTW89_ENTITY_MODE_SCC: 394 case RTW89_ENTITY_MODE_MCC: 395 sub_entity_idx = RTW89_SUB_ENTITY_0; 396 break; 397 case RTW89_ENTITY_MODE_MCC_PREPARE: 398 sub_entity_idx = RTW89_SUB_ENTITY_1; 399 break; 400 default: 401 WARN(1, "Invalid ent mode: %d\n", mode); 402 return; 403 } 404 405 roc_idx = atomic_read(&hal->roc_entity_idx); 406 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 407 sub_entity_idx = roc_idx; 408 409 mac_idx = RTW89_MAC_0; 410 phy_idx = RTW89_PHY_0; 411 412 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 413 chan_rcd = rtw89_chan_rcd_get(rtwdev, sub_entity_idx); 414 415 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 416 417 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 418 419 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 420 421 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 422 423 if (!entity_active || chan_rcd->band_changed) { 424 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 425 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 426 } 427 428 rtw89_set_entity_state(rtwdev, true); 429 } 430 431 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 432 struct rtw89_chan *chan) 433 { 434 const struct cfg80211_chan_def *chandef; 435 436 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx); 437 rtw89_get_channel_params(chandef, chan); 438 } 439 440 static enum rtw89_core_tx_type 441 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 442 struct sk_buff *skb) 443 { 444 struct ieee80211_hdr *hdr = (void *)skb->data; 445 __le16 fc = hdr->frame_control; 446 447 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 448 return RTW89_CORE_TX_TYPE_MGMT; 449 450 return RTW89_CORE_TX_TYPE_DATA; 451 } 452 453 static void 454 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 455 struct rtw89_core_tx_request *tx_req, 456 enum btc_pkt_type pkt_type) 457 { 458 struct ieee80211_sta *sta = tx_req->sta; 459 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 460 struct sk_buff *skb = tx_req->skb; 461 struct rtw89_sta *rtwsta; 462 u8 ampdu_num; 463 u8 tid; 464 465 if (pkt_type == PACKET_EAPOL) { 466 desc_info->bk = true; 467 return; 468 } 469 470 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 471 return; 472 473 if (!sta) { 474 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 475 return; 476 } 477 478 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 479 rtwsta = (struct rtw89_sta *)sta->drv_priv; 480 481 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 482 rtwsta->ampdu_params[tid].agg_num : 483 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 484 485 desc_info->agg_en = true; 486 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 487 desc_info->ampdu_num = ampdu_num; 488 } 489 490 static void 491 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 492 struct rtw89_core_tx_request *tx_req) 493 { 494 const struct rtw89_chip_info *chip = rtwdev->chip; 495 struct ieee80211_vif *vif = tx_req->vif; 496 struct ieee80211_sta *sta = tx_req->sta; 497 struct ieee80211_tx_info *info; 498 struct ieee80211_key_conf *key; 499 struct rtw89_vif *rtwvif; 500 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 501 struct rtw89_addr_cam_entry *addr_cam; 502 struct rtw89_sec_cam_entry *sec_cam; 503 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 504 struct sk_buff *skb = tx_req->skb; 505 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 506 u64 pn64; 507 508 if (!vif) { 509 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 510 return; 511 } 512 513 rtwvif = (struct rtw89_vif *)vif->drv_priv; 514 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 515 516 info = IEEE80211_SKB_CB(skb); 517 key = info->control.hw_key; 518 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 519 if (!sec_cam) { 520 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 521 return; 522 } 523 524 switch (key->cipher) { 525 case WLAN_CIPHER_SUITE_WEP40: 526 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 527 break; 528 case WLAN_CIPHER_SUITE_WEP104: 529 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 530 break; 531 case WLAN_CIPHER_SUITE_TKIP: 532 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 533 break; 534 case WLAN_CIPHER_SUITE_CCMP: 535 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 536 break; 537 case WLAN_CIPHER_SUITE_CCMP_256: 538 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 539 break; 540 case WLAN_CIPHER_SUITE_GCMP: 541 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 542 break; 543 case WLAN_CIPHER_SUITE_GCMP_256: 544 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 545 break; 546 default: 547 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 548 return; 549 } 550 551 desc_info->sec_en = true; 552 desc_info->sec_keyid = key->keyidx; 553 desc_info->sec_type = sec_type; 554 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 555 556 if (!chip->hw_sec_hdr) 557 return; 558 559 pn64 = atomic64_inc_return(&key->tx_pn); 560 desc_info->sec_seq[0] = pn64; 561 desc_info->sec_seq[1] = pn64 >> 8; 562 desc_info->sec_seq[2] = pn64 >> 16; 563 desc_info->sec_seq[3] = pn64 >> 24; 564 desc_info->sec_seq[4] = pn64 >> 32; 565 desc_info->sec_seq[5] = pn64 >> 40; 566 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 567 } 568 569 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 570 struct rtw89_core_tx_request *tx_req, 571 const struct rtw89_chan *chan) 572 { 573 struct sk_buff *skb = tx_req->skb; 574 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 575 struct ieee80211_vif *vif = tx_info->control.vif; 576 u16 lowest_rate; 577 578 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 579 (vif && vif->p2p)) 580 lowest_rate = RTW89_HW_RATE_OFDM6; 581 else if (chan->band_type == RTW89_BAND_2G) 582 lowest_rate = RTW89_HW_RATE_CCK1; 583 else 584 lowest_rate = RTW89_HW_RATE_OFDM6; 585 586 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 587 return lowest_rate; 588 589 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 590 } 591 592 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 593 struct rtw89_core_tx_request *tx_req) 594 { 595 struct ieee80211_vif *vif = tx_req->vif; 596 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 597 struct ieee80211_sta *sta = tx_req->sta; 598 struct rtw89_sta *rtwsta; 599 600 if (!sta) 601 return rtwvif->mac_id; 602 603 rtwsta = (struct rtw89_sta *)sta->drv_priv; 604 return rtwsta->mac_id; 605 } 606 607 static void 608 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 609 struct rtw89_core_tx_request *tx_req) 610 { 611 struct ieee80211_vif *vif = tx_req->vif; 612 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 613 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 614 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 615 rtwvif->sub_entity_idx); 616 u8 qsel, ch_dma; 617 618 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 619 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 620 621 desc_info->qsel = qsel; 622 desc_info->ch_dma = ch_dma; 623 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 624 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 625 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 626 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 627 628 /* fixed data rate for mgmt frames */ 629 desc_info->en_wd_info = true; 630 desc_info->use_rate = true; 631 desc_info->dis_data_fb = true; 632 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 633 634 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 635 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 636 desc_info->data_rate, chan->channel, chan->band_type, 637 chan->band_width); 638 } 639 640 static void 641 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 642 struct rtw89_core_tx_request *tx_req) 643 { 644 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 645 646 desc_info->is_bmc = false; 647 desc_info->wd_page = false; 648 desc_info->ch_dma = RTW89_DMA_H2C; 649 } 650 651 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 652 const struct rtw89_chan *chan) 653 { 654 static const u8 rtw89_bandwidth_to_om[] = { 655 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 656 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 657 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 658 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 659 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 660 }; 661 const struct rtw89_chip_info *chip = rtwdev->chip; 662 struct rtw89_hal *hal = &rtwdev->hal; 663 u8 om_bandwidth; 664 665 if (!chip->dis_2g_40m_ul_ofdma || 666 chan->band_type != RTW89_BAND_2G || 667 chan->band_width != RTW89_CHANNEL_WIDTH_40) 668 return; 669 670 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 671 rtw89_bandwidth_to_om[chan->band_width] : 0; 672 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 673 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 674 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 675 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 676 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 677 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 678 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 679 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 680 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 681 } 682 683 static bool 684 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 685 struct rtw89_core_tx_request *tx_req, 686 enum btc_pkt_type pkt_type) 687 { 688 struct ieee80211_sta *sta = tx_req->sta; 689 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 690 struct sk_buff *skb = tx_req->skb; 691 struct ieee80211_hdr *hdr = (void *)skb->data; 692 __le16 fc = hdr->frame_control; 693 694 /* AP IOT issue with EAPoL, ARP and DHCP */ 695 if (pkt_type < PACKET_MAX) 696 return false; 697 698 if (!sta || !sta->deflink.he_cap.has_he) 699 return false; 700 701 if (!ieee80211_is_data_qos(fc)) 702 return false; 703 704 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 705 return false; 706 707 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 708 return false; 709 710 return true; 711 } 712 713 static void 714 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 715 struct rtw89_core_tx_request *tx_req) 716 { 717 struct ieee80211_sta *sta = tx_req->sta; 718 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 719 struct sk_buff *skb = tx_req->skb; 720 struct ieee80211_hdr *hdr = (void *)skb->data; 721 __le16 fc = hdr->frame_control; 722 void *data; 723 __le32 *htc; 724 u8 *qc; 725 int hdr_len; 726 727 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 728 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 729 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 730 731 hdr = data; 732 htc = data + hdr_len; 733 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 734 *htc = rtwsta->htc_template ? rtwsta->htc_template : 735 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 736 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 737 738 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 739 qc[0] |= IEEE80211_QOS_CTL_EOSP; 740 } 741 742 static void 743 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 744 struct rtw89_core_tx_request *tx_req, 745 enum btc_pkt_type pkt_type) 746 { 747 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 748 struct ieee80211_vif *vif = tx_req->vif; 749 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 750 751 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 752 goto desc_bk; 753 754 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 755 756 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 757 desc_info->a_ctrl_bsr = true; 758 759 desc_bk: 760 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 761 return; 762 763 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 764 desc_info->bk = true; 765 } 766 767 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 768 struct rtw89_core_tx_request *tx_req) 769 { 770 struct ieee80211_vif *vif = tx_req->vif; 771 struct ieee80211_sta *sta = tx_req->sta; 772 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 773 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 774 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx; 775 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 776 u16 lowest_rate; 777 778 if (rate_pattern->enable) 779 return rate_pattern->rate; 780 781 if (vif->p2p) 782 lowest_rate = RTW89_HW_RATE_OFDM6; 783 else if (chan->band_type == RTW89_BAND_2G) 784 lowest_rate = RTW89_HW_RATE_CCK1; 785 else 786 lowest_rate = RTW89_HW_RATE_OFDM6; 787 788 if (!sta || !sta->deflink.supp_rates[chan->band_type]) 789 return lowest_rate; 790 791 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate; 792 } 793 794 static void 795 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 796 struct rtw89_core_tx_request *tx_req) 797 { 798 struct ieee80211_vif *vif = tx_req->vif; 799 struct ieee80211_sta *sta = tx_req->sta; 800 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 801 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 802 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 803 struct sk_buff *skb = tx_req->skb; 804 u8 tid, tid_indicate; 805 u8 qsel, ch_dma; 806 807 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 808 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 809 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 810 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 811 812 desc_info->ch_dma = ch_dma; 813 desc_info->tid_indicate = tid_indicate; 814 desc_info->qsel = qsel; 815 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 816 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 817 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 818 819 /* enable wd_info for AMPDU */ 820 desc_info->en_wd_info = true; 821 822 if (IEEE80211_SKB_CB(skb)->control.hw_key) 823 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 824 825 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 826 } 827 828 static enum btc_pkt_type 829 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 830 struct rtw89_core_tx_request *tx_req) 831 { 832 struct sk_buff *skb = tx_req->skb; 833 struct udphdr *udphdr; 834 835 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 836 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 837 return PACKET_EAPOL; 838 } 839 840 if (skb->protocol == htons(ETH_P_ARP)) { 841 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 842 return PACKET_ARP; 843 } 844 845 if (skb->protocol == htons(ETH_P_IP) && 846 ip_hdr(skb)->protocol == IPPROTO_UDP) { 847 udphdr = udp_hdr(skb); 848 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 849 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 850 skb->len > 282) { 851 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 852 return PACKET_DHCP; 853 } 854 } 855 856 if (skb->protocol == htons(ETH_P_IP) && 857 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 858 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 859 return PACKET_ICMP; 860 } 861 862 return PACKET_MAX; 863 } 864 865 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 866 struct rtw89_tx_desc_info *desc_info, 867 struct sk_buff *skb) 868 { 869 struct ieee80211_hdr *hdr = (void *)skb->data; 870 __le16 fc = hdr->frame_control; 871 872 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 873 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 874 } 875 876 static void 877 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 878 struct rtw89_core_tx_request *tx_req) 879 { 880 const struct rtw89_chip_info *chip = rtwdev->chip; 881 882 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 883 return; 884 885 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 886 return; 887 888 if (chip->chip_id != RTL8852C && 889 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 890 return; 891 892 rtw89_mac_notify_wake(rtwdev); 893 } 894 895 static void 896 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 897 struct rtw89_core_tx_request *tx_req) 898 { 899 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 900 struct sk_buff *skb = tx_req->skb; 901 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 902 struct ieee80211_hdr *hdr = (void *)skb->data; 903 enum rtw89_core_tx_type tx_type; 904 enum btc_pkt_type pkt_type; 905 bool is_bmc; 906 u16 seq; 907 908 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 909 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 910 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 911 tx_req->tx_type = tx_type; 912 } 913 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 914 is_multicast_ether_addr(hdr->addr1)); 915 916 desc_info->seq = seq; 917 desc_info->pkt_size = skb->len; 918 desc_info->is_bmc = is_bmc; 919 desc_info->wd_page = true; 920 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 921 922 switch (tx_req->tx_type) { 923 case RTW89_CORE_TX_TYPE_MGMT: 924 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 925 break; 926 case RTW89_CORE_TX_TYPE_DATA: 927 rtw89_core_tx_update_data_info(rtwdev, tx_req); 928 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 929 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 930 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 931 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 932 break; 933 case RTW89_CORE_TX_TYPE_FWCMD: 934 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 935 break; 936 } 937 } 938 939 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 940 { 941 u8 ch_dma; 942 943 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 944 945 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 946 } 947 948 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 949 int qsel, unsigned int timeout) 950 { 951 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 952 struct rtw89_tx_wait_info *wait; 953 unsigned long time_left; 954 int ret = 0; 955 956 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 957 if (!wait) { 958 rtw89_core_tx_kick_off(rtwdev, qsel); 959 return 0; 960 } 961 962 init_completion(&wait->completion); 963 rcu_assign_pointer(skb_data->wait, wait); 964 965 rtw89_core_tx_kick_off(rtwdev, qsel); 966 time_left = wait_for_completion_timeout(&wait->completion, 967 msecs_to_jiffies(timeout)); 968 if (time_left == 0) 969 ret = -ETIMEDOUT; 970 else if (!wait->tx_done) 971 ret = -EAGAIN; 972 973 rcu_assign_pointer(skb_data->wait, NULL); 974 kfree_rcu(wait, rcu_head); 975 976 return ret; 977 } 978 979 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 980 struct sk_buff *skb, bool fwdl) 981 { 982 struct rtw89_core_tx_request tx_req = {0}; 983 u32 cnt; 984 int ret; 985 986 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 987 rtw89_debug(rtwdev, RTW89_DBG_FW, 988 "ignore h2c due to power is off with firmware state=%d\n", 989 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 990 dev_kfree_skb(skb); 991 return 0; 992 } 993 994 tx_req.skb = skb; 995 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 996 if (fwdl) 997 tx_req.desc_info.fw_dl = true; 998 999 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1000 1001 if (!fwdl) 1002 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1003 1004 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1005 if (cnt == 0) { 1006 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1007 return -ENOSPC; 1008 } 1009 1010 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1011 if (ret) { 1012 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1013 return ret; 1014 } 1015 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1016 1017 return 0; 1018 } 1019 1020 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1021 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1022 { 1023 struct rtw89_core_tx_request tx_req = {0}; 1024 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1025 int ret; 1026 1027 tx_req.skb = skb; 1028 tx_req.sta = sta; 1029 tx_req.vif = vif; 1030 1031 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1032 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1033 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1034 rtw89_core_tx_wake(rtwdev, &tx_req); 1035 1036 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1037 if (ret) { 1038 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1039 return ret; 1040 } 1041 1042 if (qsel) 1043 *qsel = tx_req.desc_info.qsel; 1044 1045 return 0; 1046 } 1047 1048 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1049 { 1050 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1051 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1052 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1053 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1054 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1055 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1056 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1057 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1058 1059 return cpu_to_le32(dword); 1060 } 1061 1062 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1063 { 1064 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1065 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1066 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1067 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1068 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1069 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1070 1071 return cpu_to_le32(dword); 1072 } 1073 1074 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1075 { 1076 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1077 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1078 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1079 1080 return cpu_to_le32(dword); 1081 } 1082 1083 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1084 { 1085 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1086 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1087 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1088 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1089 1090 return cpu_to_le32(dword); 1091 } 1092 1093 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1094 { 1095 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1096 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1097 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1098 1099 return cpu_to_le32(dword); 1100 } 1101 1102 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1103 { 1104 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1105 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1106 1107 return cpu_to_le32(dword); 1108 } 1109 1110 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1111 { 1112 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1113 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1114 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1115 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1116 1117 return cpu_to_le32(dword); 1118 } 1119 1120 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1121 { 1122 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1123 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1124 1125 return cpu_to_le32(dword); 1126 } 1127 1128 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1129 { 1130 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1131 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1132 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1133 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1134 1135 return cpu_to_le32(dword); 1136 } 1137 1138 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1139 { 1140 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1141 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1142 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1143 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1144 1145 return cpu_to_le32(dword); 1146 } 1147 1148 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1149 { 1150 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1151 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1152 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1153 desc_info->data_retry_lowest_rate); 1154 1155 return cpu_to_le32(dword); 1156 } 1157 1158 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1159 { 1160 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1161 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1162 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1163 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1164 1165 return cpu_to_le32(dword); 1166 } 1167 1168 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1169 { 1170 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1171 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1172 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1173 1174 return cpu_to_le32(dword); 1175 } 1176 1177 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1178 { 1179 bool rts_en = !desc_info->is_bmc; 1180 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1181 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1182 1183 return cpu_to_le32(dword); 1184 } 1185 1186 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1187 struct rtw89_tx_desc_info *desc_info, 1188 void *txdesc) 1189 { 1190 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1191 struct rtw89_txwd_info *txwd_info; 1192 1193 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1194 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1195 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1196 1197 if (!desc_info->en_wd_info) 1198 return; 1199 1200 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1201 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1202 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1203 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1204 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1205 1206 } 1207 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1208 1209 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1210 struct rtw89_tx_desc_info *desc_info, 1211 void *txdesc) 1212 { 1213 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1214 struct rtw89_txwd_info *txwd_info; 1215 1216 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1217 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1218 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1219 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1220 if (desc_info->sec_en) { 1221 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1222 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1223 } 1224 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1225 1226 if (!desc_info->en_wd_info) 1227 return; 1228 1229 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1230 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1231 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1232 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1233 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1234 } 1235 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1236 1237 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1238 { 1239 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1240 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1241 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1242 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1243 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1244 1245 return cpu_to_le32(dword); 1246 } 1247 1248 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1249 { 1250 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1251 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1252 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1253 1254 return cpu_to_le32(dword); 1255 } 1256 1257 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1258 { 1259 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1260 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1261 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1262 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1263 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1264 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1265 1266 return cpu_to_le32(dword); 1267 } 1268 1269 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1270 { 1271 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq); 1272 1273 return cpu_to_le32(dword); 1274 } 1275 1276 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1277 { 1278 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1279 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1280 1281 return cpu_to_le32(dword); 1282 } 1283 1284 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1285 { 1286 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1287 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1288 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1289 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1290 1291 return cpu_to_le32(dword); 1292 } 1293 1294 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1295 { 1296 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1297 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1298 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1299 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1300 1301 return cpu_to_le32(dword); 1302 } 1303 1304 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1305 { 1306 u32 dword = FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1307 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1308 1309 return cpu_to_le32(dword); 1310 } 1311 1312 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1313 { 1314 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1315 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1316 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1317 desc_info->data_retry_lowest_rate); 1318 1319 return cpu_to_le32(dword); 1320 } 1321 1322 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1323 { 1324 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1325 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1326 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1327 1328 return cpu_to_le32(dword); 1329 } 1330 1331 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1332 { 1333 bool rts_en = !desc_info->is_bmc; 1334 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1335 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1336 1337 return cpu_to_le32(dword); 1338 } 1339 1340 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1341 struct rtw89_tx_desc_info *desc_info, 1342 void *txdesc) 1343 { 1344 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1345 struct rtw89_txwd_info_v2 *txwd_info; 1346 1347 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1348 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1349 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1350 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1351 if (desc_info->sec_en) { 1352 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1353 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1354 } 1355 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1356 1357 if (!desc_info->en_wd_info) 1358 return; 1359 1360 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1361 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1362 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1363 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1364 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1365 } 1366 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1367 1368 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1369 { 1370 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1371 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1372 RTW89_CORE_RX_TYPE_FWDL : 1373 RTW89_CORE_RX_TYPE_H2C); 1374 1375 return cpu_to_le32(dword); 1376 } 1377 1378 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1379 struct rtw89_tx_desc_info *desc_info, 1380 void *txdesc) 1381 { 1382 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1383 1384 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1385 } 1386 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1387 1388 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1389 { 1390 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1391 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1392 RTW89_CORE_RX_TYPE_FWDL : 1393 RTW89_CORE_RX_TYPE_H2C); 1394 1395 return cpu_to_le32(dword); 1396 } 1397 1398 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1399 struct rtw89_tx_desc_info *desc_info, 1400 void *txdesc) 1401 { 1402 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1403 1404 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1405 } 1406 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1407 1408 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1409 struct sk_buff *skb, 1410 struct rtw89_rx_phy_ppdu *phy_ppdu) 1411 { 1412 const struct rtw89_chip_info *chip = rtwdev->chip; 1413 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1414 const struct rtw89_rxinfo_user *user; 1415 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1416 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1417 bool rx_cnt_valid = false; 1418 bool invalid = false; 1419 u8 plcp_size = 0; 1420 u8 *phy_sts; 1421 u8 usr_num; 1422 int i; 1423 1424 if (chip_gen == RTW89_CHIP_BE) { 1425 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1426 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1427 } 1428 1429 if (invalid) 1430 return -EINVAL; 1431 1432 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1433 if (chip_gen == RTW89_CHIP_BE) { 1434 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1435 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1436 } else { 1437 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1438 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1439 } 1440 if (usr_num > chip->ppdu_max_usr) { 1441 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1442 usr_num); 1443 return -EINVAL; 1444 } 1445 1446 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set by hardware, 1447 * so update mac_id by rxinfo_user[].mac_id. 1448 */ 1449 for (i = 0; i < usr_num && chip_gen == RTW89_CHIP_BE; i++) { 1450 user = &rxinfo->user[i]; 1451 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1452 continue; 1453 1454 phy_ppdu->mac_id = 1455 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1456 break; 1457 } 1458 1459 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1460 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1461 /* 8-byte alignment */ 1462 if (usr_num & BIT(0)) 1463 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1464 if (rx_cnt_valid) 1465 phy_sts += rx_cnt_size; 1466 phy_sts += plcp_size; 1467 1468 if (phy_sts > skb->data + skb->len) 1469 return -EINVAL; 1470 1471 phy_ppdu->buf = phy_sts; 1472 phy_ppdu->len = skb->data + skb->len - phy_sts; 1473 1474 return 0; 1475 } 1476 1477 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1478 struct ieee80211_sta *sta) 1479 { 1480 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1481 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1482 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1483 struct rtw89_hal *hal = &rtwdev->hal; 1484 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1485 u8 ant_pos = U8_MAX; 1486 u8 evm_pos = 0; 1487 int i; 1488 1489 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1490 return; 1491 1492 if (hal->ant_diversity && hal->antenna_rx) { 1493 ant_pos = __ffs(hal->antenna_rx); 1494 evm_pos = ant_pos; 1495 } 1496 1497 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1498 1499 if (ant_pos < ant_num) { 1500 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]); 1501 } else { 1502 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1503 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1504 } 1505 1506 if (phy_ppdu->ofdm.has) { 1507 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr); 1508 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min); 1509 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max); 1510 } 1511 } 1512 1513 #define VAR_LEN 0xff 1514 #define VAR_LEN_UNIT 8 1515 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1516 const struct rtw89_phy_sts_iehdr *iehdr) 1517 { 1518 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1519 [RTW89_CHIP_AX] = { 1520 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1521 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1522 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1523 }, 1524 [RTW89_CHIP_BE] = { 1525 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1526 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1527 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1528 }, 1529 }; 1530 const u8 *physts_ie_len_tab; 1531 u16 ie_len; 1532 u8 ie; 1533 1534 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1535 1536 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1537 if (physts_ie_len_tab[ie] != VAR_LEN) 1538 ie_len = physts_ie_len_tab[ie]; 1539 else 1540 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1541 1542 return ie_len; 1543 } 1544 1545 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1546 const struct rtw89_phy_sts_iehdr *iehdr, 1547 struct rtw89_rx_phy_ppdu *phy_ppdu) 1548 { 1549 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr; 1550 s16 cfo; 1551 u32 t; 1552 1553 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1554 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1555 return; 1556 1557 if (!phy_ppdu->to_self) 1558 return; 1559 1560 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1561 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1562 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1563 phy_ppdu->ofdm.has = true; 1564 1565 /* sign conversion for S(12,2) */ 1566 if (rtwdev->chip->cfo_src_fd) { 1567 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1568 cfo = sign_extend32(t, 11); 1569 } else { 1570 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1571 cfo = sign_extend32(t, 11); 1572 } 1573 1574 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1575 } 1576 1577 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1578 const struct rtw89_phy_sts_iehdr *iehdr, 1579 struct rtw89_rx_phy_ppdu *phy_ppdu) 1580 { 1581 u8 ie; 1582 1583 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1584 1585 switch (ie) { 1586 case RTW89_PHYSTS_IE01_CMN_OFDM: 1587 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1588 break; 1589 default: 1590 break; 1591 } 1592 1593 return 0; 1594 } 1595 1596 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1597 { 1598 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1599 u8 *rssi = phy_ppdu->rssi; 1600 1601 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1602 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1603 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1604 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1605 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1606 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1607 } 1608 1609 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1610 struct rtw89_rx_phy_ppdu *phy_ppdu) 1611 { 1612 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1613 u32 len_from_header; 1614 bool physts_valid; 1615 1616 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1617 if (!physts_valid) 1618 return -EINVAL; 1619 1620 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1621 1622 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1623 len_from_header += PHY_STS_HDR_LEN; 1624 1625 if (len_from_header != phy_ppdu->len) { 1626 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1627 return -EINVAL; 1628 } 1629 rtw89_core_update_phy_ppdu(phy_ppdu); 1630 1631 return 0; 1632 } 1633 1634 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1635 struct rtw89_rx_phy_ppdu *phy_ppdu) 1636 { 1637 u16 ie_len; 1638 void *pos, *end; 1639 1640 /* mark invalid reports and bypass them */ 1641 if (phy_ppdu->ie < RTW89_CCK_PKT) 1642 return -EINVAL; 1643 1644 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1645 end = phy_ppdu->buf + phy_ppdu->len; 1646 while (pos < end) { 1647 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1648 1649 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1650 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1651 pos += ie_len; 1652 if (pos > end || ie_len == 0) { 1653 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1654 "phy status parse failed\n"); 1655 return -EINVAL; 1656 } 1657 } 1658 1659 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1660 1661 return 0; 1662 } 1663 1664 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1665 struct rtw89_rx_phy_ppdu *phy_ppdu) 1666 { 1667 int ret; 1668 1669 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1670 if (ret) 1671 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1672 else 1673 phy_ppdu->valid = true; 1674 1675 ieee80211_iterate_stations_atomic(rtwdev->hw, 1676 rtw89_core_rx_process_phy_ppdu_iter, 1677 phy_ppdu); 1678 } 1679 1680 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 1681 u8 desc_info_gi, 1682 bool rx_status, bool eht) 1683 { 1684 switch (desc_info_gi) { 1685 case RTW89_GILTF_SGI_4XHE08: 1686 case RTW89_GILTF_2XHE08: 1687 case RTW89_GILTF_1XHE08: 1688 return eht ? NL80211_RATE_INFO_EHT_GI_0_8 : 1689 NL80211_RATE_INFO_HE_GI_0_8; 1690 case RTW89_GILTF_2XHE16: 1691 case RTW89_GILTF_1XHE16: 1692 return eht ? NL80211_RATE_INFO_EHT_GI_1_6 : 1693 NL80211_RATE_INFO_HE_GI_1_6; 1694 case RTW89_GILTF_LGI_4XHE32: 1695 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1696 NL80211_RATE_INFO_HE_GI_3_2; 1697 default: 1698 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1699 if (rx_status) 1700 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1701 NL80211_RATE_INFO_HE_GI_3_2; 1702 return U8_MAX; 1703 } 1704 } 1705 1706 static 1707 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 1708 bool eht) 1709 { 1710 if (eht) 1711 return status->eht.gi == gi_ltf; 1712 1713 return status->he_gi == gi_ltf; 1714 } 1715 1716 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1717 struct rtw89_rx_desc_info *desc_info, 1718 struct ieee80211_rx_status *status) 1719 { 1720 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1721 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1722 bool eht = false; 1723 u16 data_rate; 1724 bool ret; 1725 1726 data_rate = desc_info->data_rate; 1727 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1728 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1729 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1730 /* rate_idx is still hardware value here */ 1731 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1732 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1733 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 1734 data_rate_mode == DATA_RATE_MODE_HE || 1735 data_rate_mode == DATA_RATE_MODE_EHT) { 1736 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1737 } else { 1738 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1739 } 1740 1741 eht = data_rate_mode == DATA_RATE_MODE_EHT; 1742 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1743 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 1744 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1745 status->rate_idx == rate_idx && 1746 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 1747 status->bw == bw; 1748 1749 return ret; 1750 } 1751 1752 struct rtw89_vif_rx_stats_iter_data { 1753 struct rtw89_dev *rtwdev; 1754 struct rtw89_rx_phy_ppdu *phy_ppdu; 1755 struct rtw89_rx_desc_info *desc_info; 1756 struct sk_buff *skb; 1757 const u8 *bssid; 1758 }; 1759 1760 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1761 struct ieee80211_vif *vif, 1762 struct sk_buff *skb) 1763 { 1764 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1765 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1766 u8 *pos, *end, type, tf_bw; 1767 u16 aid, tf_rua; 1768 1769 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1770 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1771 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1772 return; 1773 1774 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1775 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 1776 return; 1777 1778 end = (u8 *)tf + skb->len; 1779 pos = tf->variable; 1780 1781 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1782 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1783 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 1784 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 1785 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1786 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 1787 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1788 tf_rua, tf_bw); 1789 1790 if (aid == RTW89_TF_PAD) 1791 break; 1792 1793 if (aid == vif->cfg.aid) { 1794 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 1795 1796 rtwvif->stats.rx_tf_acc++; 1797 rtwdev->stats.rx_tf_acc++; 1798 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 1799 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 1800 rtwvif->pwr_diff_en = true; 1801 break; 1802 } 1803 1804 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1805 } 1806 } 1807 1808 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work) 1809 { 1810 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1811 cancel_6ghz_probe_work); 1812 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1813 struct rtw89_pktofld_info *info; 1814 1815 mutex_lock(&rtwdev->mutex); 1816 1817 if (!rtwdev->scanning) 1818 goto out; 1819 1820 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1821 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 1822 continue; 1823 1824 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1825 1826 /* Don't delete/free info from pkt_list at this moment. Let it 1827 * be deleted/freed in rtw89_release_pkt_list() after scanning, 1828 * since if during scanning, pkt_list is accessed in bottom half. 1829 */ 1830 } 1831 1832 out: 1833 mutex_unlock(&rtwdev->mutex); 1834 } 1835 1836 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1837 struct sk_buff *skb) 1838 { 1839 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1840 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1841 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1842 struct rtw89_pktofld_info *info; 1843 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1844 bool queue_work = false; 1845 1846 if (rx_status->band != NL80211_BAND_6GHZ) 1847 return; 1848 1849 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1850 1851 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1852 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1853 info->cancel = true; 1854 queue_work = true; 1855 continue; 1856 } 1857 1858 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1859 continue; 1860 1861 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 1862 info->cancel = true; 1863 queue_work = true; 1864 } 1865 } 1866 1867 if (queue_work) 1868 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work); 1869 } 1870 1871 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1872 struct ieee80211_vif *vif) 1873 { 1874 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1875 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1876 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1877 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1878 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1879 struct sk_buff *skb = iter_data->skb; 1880 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1881 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 1882 const u8 *bssid = iter_data->bssid; 1883 1884 if (rtwdev->scanning && 1885 (ieee80211_is_beacon(hdr->frame_control) || 1886 ieee80211_is_probe_resp(hdr->frame_control))) 1887 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1888 1889 if (!vif->bss_conf.bssid) 1890 return; 1891 1892 if (ieee80211_is_trigger(hdr->frame_control)) { 1893 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1894 return; 1895 } 1896 1897 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1898 return; 1899 1900 if (ieee80211_is_beacon(hdr->frame_control)) { 1901 if (vif->type == NL80211_IFTYPE_STATION) 1902 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 1903 pkt_stat->beacon_nr++; 1904 } 1905 1906 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1907 return; 1908 1909 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1910 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1911 1912 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1913 } 1914 1915 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1916 struct rtw89_rx_phy_ppdu *phy_ppdu, 1917 struct rtw89_rx_desc_info *desc_info, 1918 struct sk_buff *skb) 1919 { 1920 struct rtw89_vif_rx_stats_iter_data iter_data; 1921 1922 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1923 1924 iter_data.rtwdev = rtwdev; 1925 iter_data.phy_ppdu = phy_ppdu; 1926 iter_data.desc_info = desc_info; 1927 iter_data.skb = skb; 1928 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1929 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1930 } 1931 1932 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1933 struct ieee80211_rx_status *status) 1934 { 1935 const struct rtw89_chan_rcd *rcd = 1936 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1937 u16 chan = rcd->prev_primary_channel; 1938 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 1939 1940 if (status->band != NL80211_BAND_2GHZ && 1941 status->encoding == RX_ENC_LEGACY && 1942 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1943 status->freq = ieee80211_channel_to_frequency(chan, band); 1944 status->band = band; 1945 } 1946 } 1947 1948 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1949 { 1950 if (rx_status->band == NL80211_BAND_2GHZ || 1951 rx_status->encoding != RX_ENC_LEGACY) 1952 return; 1953 1954 /* Some control frames' freq(ACKs in this case) are reported wrong due 1955 * to FW notify timing, set to lowest rate to prevent overflow. 1956 */ 1957 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1958 rx_status->rate_idx = 0; 1959 return; 1960 } 1961 1962 /* No 4 CCK rates for non-2G */ 1963 rx_status->rate_idx -= 4; 1964 } 1965 1966 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 1967 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 1968 [RATE_INFO_BW_5] = U8_MAX, 1969 [RATE_INFO_BW_10] = U8_MAX, 1970 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 1971 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 1972 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 1973 [RATE_INFO_BW_HE_RU] = U8_MAX, 1974 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 1975 [RATE_INFO_BW_EHT_RU] = U8_MAX, 1976 }; 1977 1978 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 1979 struct sk_buff *skb, 1980 struct ieee80211_rx_status *rx_status) 1981 { 1982 struct ieee80211_radiotap_eht_usig *usig; 1983 struct ieee80211_radiotap_eht *eht; 1984 struct ieee80211_radiotap_tlv *tlv; 1985 int eht_len = struct_size(eht, user_info, 1); 1986 int usig_len = sizeof(*usig); 1987 int len; 1988 u8 bw; 1989 1990 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 1991 sizeof(*tlv) + ALIGN(usig_len, 4); 1992 1993 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 1994 skb_reset_mac_header(skb); 1995 1996 /* EHT */ 1997 tlv = skb_push(skb, len); 1998 memset(tlv, 0, len); 1999 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2000 tlv->len = cpu_to_le16(eht_len); 2001 2002 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2003 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2004 eht->data[0] = 2005 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2006 2007 eht->user_info[0] = 2008 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2009 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O); 2010 eht->user_info[0] |= 2011 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2012 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2013 2014 /* U-SIG */ 2015 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2016 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2017 tlv->len = cpu_to_le16(usig_len); 2018 2019 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2020 return; 2021 2022 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2023 if (bw == U8_MAX) 2024 return; 2025 2026 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2027 usig->common = 2028 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2029 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2030 } 2031 2032 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2033 struct sk_buff *skb, 2034 struct ieee80211_rx_status *rx_status) 2035 { 2036 static const struct ieee80211_radiotap_he known_he = { 2037 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2038 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2039 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2040 }; 2041 struct ieee80211_radiotap_he *he; 2042 2043 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2044 return; 2045 2046 if (rx_status->encoding == RX_ENC_HE) { 2047 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2048 he = skb_push(skb, sizeof(*he)); 2049 *he = known_he; 2050 } else if (rx_status->encoding == RX_ENC_EHT) { 2051 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2052 } 2053 } 2054 2055 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2056 struct rtw89_rx_phy_ppdu *phy_ppdu, 2057 struct rtw89_rx_desc_info *desc_info, 2058 struct sk_buff *skb_ppdu, 2059 struct ieee80211_rx_status *rx_status) 2060 { 2061 struct napi_struct *napi = &rtwdev->napi; 2062 2063 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2064 if (unlikely(!napi_is_scheduled(napi))) 2065 napi = NULL; 2066 2067 rtw89_core_hw_to_sband_rate(rx_status); 2068 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2069 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2070 /* In low power mode, it does RX in thread context. */ 2071 local_bh_disable(); 2072 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2073 local_bh_enable(); 2074 rtwdev->napi_budget_countdown--; 2075 } 2076 2077 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2078 struct rtw89_rx_phy_ppdu *phy_ppdu, 2079 struct rtw89_rx_desc_info *desc_info, 2080 struct sk_buff *skb) 2081 { 2082 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2083 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2084 struct sk_buff *skb_ppdu = NULL, *tmp; 2085 struct ieee80211_rx_status *rx_status; 2086 2087 if (curr > RTW89_MAX_PPDU_CNT) 2088 return; 2089 2090 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2091 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2092 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2093 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2094 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2095 rtw89_correct_cck_chan(rtwdev, rx_status); 2096 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2097 } 2098 } 2099 2100 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2101 struct rtw89_rx_desc_info *desc_info, 2102 struct sk_buff *skb) 2103 { 2104 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2105 .len = skb->len, 2106 .to_self = desc_info->addr1_match, 2107 .rate = desc_info->data_rate, 2108 .mac_id = desc_info->mac_id}; 2109 int ret; 2110 2111 if (desc_info->mac_info_valid) { 2112 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2113 if (ret) 2114 goto out; 2115 } 2116 2117 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2118 if (ret) 2119 goto out; 2120 2121 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2122 2123 out: 2124 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2125 dev_kfree_skb_any(skb); 2126 } 2127 2128 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2129 struct rtw89_rx_desc_info *desc_info, 2130 struct sk_buff *skb) 2131 { 2132 switch (desc_info->pkt_type) { 2133 case RTW89_CORE_RX_TYPE_C2H: 2134 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2135 break; 2136 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2137 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2138 break; 2139 default: 2140 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2141 desc_info->pkt_type); 2142 dev_kfree_skb_any(skb); 2143 break; 2144 } 2145 } 2146 2147 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2148 struct rtw89_rx_desc_info *desc_info, 2149 u8 *data, u32 data_offset) 2150 { 2151 const struct rtw89_chip_info *chip = rtwdev->chip; 2152 struct rtw89_rxdesc_short *rxd_s; 2153 struct rtw89_rxdesc_long *rxd_l; 2154 u8 shift_len, drv_info_len; 2155 2156 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2157 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2158 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2159 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2160 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2161 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2162 if (chip->chip_id == RTL8852C) 2163 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2164 else 2165 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2166 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2167 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2168 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2169 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2170 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2171 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2172 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2173 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2174 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2175 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2176 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2177 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2178 2179 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2180 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2181 desc_info->offset = data_offset + shift_len + drv_info_len; 2182 if (desc_info->long_rxdesc) 2183 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2184 else 2185 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2186 desc_info->ready = true; 2187 2188 if (!desc_info->long_rxdesc) 2189 return; 2190 2191 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2192 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2193 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2194 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2195 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2196 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2197 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2198 } 2199 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2200 2201 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2202 struct rtw89_rx_desc_info *desc_info, 2203 u8 *data, u32 data_offset) 2204 { 2205 struct rtw89_rxdesc_short_v2 *rxd_s; 2206 struct rtw89_rxdesc_long_v2 *rxd_l; 2207 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2208 2209 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2210 2211 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2212 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2213 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2214 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2215 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2216 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2217 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2218 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2219 desc_info->mac_info_valid = true; 2220 2221 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2222 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2223 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2224 2225 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2226 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2227 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2228 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2229 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2230 2231 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2232 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2233 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2234 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2235 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2236 2237 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2238 2239 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2240 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2241 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2242 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2243 desc_info->offset = data_offset + shift_len + drv_info_len + 2244 phy_rtp_len + hdr_cnv_len; 2245 2246 if (desc_info->long_rxdesc) 2247 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2248 else 2249 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2250 desc_info->ready = true; 2251 2252 if (!desc_info->long_rxdesc) 2253 return; 2254 2255 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2256 2257 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2258 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2259 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2260 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2261 2262 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2263 } 2264 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2265 2266 struct rtw89_core_iter_rx_status { 2267 struct rtw89_dev *rtwdev; 2268 struct ieee80211_rx_status *rx_status; 2269 struct rtw89_rx_desc_info *desc_info; 2270 u8 mac_id; 2271 }; 2272 2273 static 2274 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2275 { 2276 struct rtw89_core_iter_rx_status *iter_data = 2277 (struct rtw89_core_iter_rx_status *)data; 2278 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2279 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2280 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2281 u8 mac_id = iter_data->mac_id; 2282 2283 if (mac_id != rtwsta->mac_id) 2284 return; 2285 2286 rtwsta->rx_status = *rx_status; 2287 rtwsta->rx_hw_rate = desc_info->data_rate; 2288 } 2289 2290 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2291 struct rtw89_rx_desc_info *desc_info, 2292 struct ieee80211_rx_status *rx_status) 2293 { 2294 struct rtw89_core_iter_rx_status iter_data; 2295 2296 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2297 return; 2298 2299 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2300 return; 2301 2302 iter_data.rtwdev = rtwdev; 2303 iter_data.rx_status = rx_status; 2304 iter_data.desc_info = desc_info; 2305 iter_data.mac_id = desc_info->mac_id; 2306 ieee80211_iterate_stations_atomic(rtwdev->hw, 2307 rtw89_core_stats_sta_rx_status_iter, 2308 &iter_data); 2309 } 2310 2311 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2312 struct rtw89_rx_desc_info *desc_info, 2313 struct ieee80211_rx_status *rx_status) 2314 { 2315 const struct cfg80211_chan_def *chandef = 2316 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 2317 u16 data_rate; 2318 u8 data_rate_mode; 2319 bool eht = false; 2320 u8 gi; 2321 2322 /* currently using single PHY */ 2323 rx_status->freq = chandef->chan->center_freq; 2324 rx_status->band = chandef->chan->band; 2325 2326 if (rtwdev->scanning && 2327 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2328 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2329 u8 chan = cur->primary_channel; 2330 u8 band = cur->band_type; 2331 enum nl80211_band nl_band; 2332 2333 nl_band = rtw89_hw_to_nl80211_band(band); 2334 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2335 rx_status->band = nl_band; 2336 } 2337 2338 if (desc_info->icv_err || desc_info->crc32_err) 2339 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2340 2341 if (desc_info->hw_dec && 2342 !(desc_info->sw_dec || desc_info->icv_err)) 2343 rx_status->flag |= RX_FLAG_DECRYPTED; 2344 2345 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2346 2347 data_rate = desc_info->data_rate; 2348 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2349 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2350 rx_status->encoding = RX_ENC_LEGACY; 2351 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2352 /* convert rate_idx after we get the correct band */ 2353 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2354 rx_status->encoding = RX_ENC_HT; 2355 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2356 if (desc_info->gi_ltf) 2357 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2358 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2359 rx_status->encoding = RX_ENC_VHT; 2360 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2361 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2362 if (desc_info->gi_ltf) 2363 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2364 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2365 rx_status->encoding = RX_ENC_HE; 2366 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2367 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2368 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2369 rx_status->encoding = RX_ENC_EHT; 2370 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2371 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2372 eht = true; 2373 } else { 2374 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2375 } 2376 2377 /* he_gi is used to match ppdu, so we always fill it. */ 2378 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2379 if (eht) 2380 rx_status->eht.gi = gi; 2381 else 2382 rx_status->he_gi = gi; 2383 rx_status->flag |= RX_FLAG_MACTIME_START; 2384 rx_status->mactime = desc_info->free_run_cnt; 2385 2386 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2387 } 2388 2389 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2390 { 2391 const struct rtw89_chip_info *chip = rtwdev->chip; 2392 2393 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2394 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2395 return RTW89_PS_MODE_NONE; 2396 2397 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2398 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2399 return RTW89_PS_MODE_PWR_GATED; 2400 2401 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2402 return RTW89_PS_MODE_CLK_GATED; 2403 2404 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2405 return RTW89_PS_MODE_RFOFF; 2406 2407 return RTW89_PS_MODE_NONE; 2408 } 2409 2410 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2411 struct rtw89_rx_desc_info *desc_info) 2412 { 2413 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2414 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2415 struct ieee80211_rx_status *rx_status; 2416 struct sk_buff *skb_ppdu, *tmp; 2417 2418 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2419 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2420 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2421 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2422 } 2423 } 2424 2425 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2426 struct rtw89_rx_desc_info *desc_info, 2427 struct sk_buff *skb) 2428 { 2429 struct ieee80211_rx_status *rx_status; 2430 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2431 u8 ppdu_cnt = desc_info->ppdu_cnt; 2432 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2433 2434 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2435 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2436 return; 2437 } 2438 2439 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2440 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2441 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2442 } 2443 2444 rx_status = IEEE80211_SKB_RXCB(skb); 2445 memset(rx_status, 0, sizeof(*rx_status)); 2446 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2447 if (desc_info->long_rxdesc && 2448 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2449 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2450 else 2451 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2452 } 2453 EXPORT_SYMBOL(rtw89_core_rx); 2454 2455 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2456 { 2457 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2458 return; 2459 2460 napi_enable(&rtwdev->napi); 2461 } 2462 EXPORT_SYMBOL(rtw89_core_napi_start); 2463 2464 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2465 { 2466 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2467 return; 2468 2469 napi_synchronize(&rtwdev->napi); 2470 napi_disable(&rtwdev->napi); 2471 } 2472 EXPORT_SYMBOL(rtw89_core_napi_stop); 2473 2474 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2475 { 2476 init_dummy_netdev(&rtwdev->netdev); 2477 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 2478 rtwdev->hci.ops->napi_poll); 2479 } 2480 EXPORT_SYMBOL(rtw89_core_napi_init); 2481 2482 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2483 { 2484 rtw89_core_napi_stop(rtwdev); 2485 netif_napi_del(&rtwdev->napi); 2486 } 2487 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2488 2489 static void rtw89_core_ba_work(struct work_struct *work) 2490 { 2491 struct rtw89_dev *rtwdev = 2492 container_of(work, struct rtw89_dev, ba_work); 2493 struct rtw89_txq *rtwtxq, *tmp; 2494 int ret; 2495 2496 spin_lock_bh(&rtwdev->ba_lock); 2497 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2498 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2499 struct ieee80211_sta *sta = txq->sta; 2500 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2501 u8 tid = txq->tid; 2502 2503 if (!sta) { 2504 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2505 goto skip_ba_work; 2506 } 2507 2508 if (rtwsta->disassoc) { 2509 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2510 "cannot start BA with disassoc sta\n"); 2511 goto skip_ba_work; 2512 } 2513 2514 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2515 if (ret) { 2516 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2517 "failed to setup BA session for %pM:%2d: %d\n", 2518 sta->addr, tid, ret); 2519 if (ret == -EINVAL) 2520 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2521 } 2522 skip_ba_work: 2523 list_del_init(&rtwtxq->list); 2524 } 2525 spin_unlock_bh(&rtwdev->ba_lock); 2526 } 2527 2528 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2529 struct ieee80211_sta *sta) 2530 { 2531 struct rtw89_txq *rtwtxq, *tmp; 2532 2533 spin_lock_bh(&rtwdev->ba_lock); 2534 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2535 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2536 2537 if (sta == txq->sta) 2538 list_del_init(&rtwtxq->list); 2539 } 2540 spin_unlock_bh(&rtwdev->ba_lock); 2541 } 2542 2543 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2544 struct ieee80211_sta *sta) 2545 { 2546 struct rtw89_txq *rtwtxq, *tmp; 2547 2548 spin_lock_bh(&rtwdev->ba_lock); 2549 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2550 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2551 2552 if (sta == txq->sta) { 2553 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2554 list_del_init(&rtwtxq->list); 2555 } 2556 } 2557 spin_unlock_bh(&rtwdev->ba_lock); 2558 } 2559 2560 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2561 struct ieee80211_sta *sta) 2562 { 2563 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2564 struct sk_buff *skb, *tmp; 2565 2566 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2567 skb_unlink(skb, &rtwsta->roc_queue); 2568 dev_kfree_skb_any(skb); 2569 } 2570 } 2571 2572 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2573 struct rtw89_txq *rtwtxq) 2574 { 2575 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2576 struct ieee80211_sta *sta = txq->sta; 2577 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2578 2579 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2580 return; 2581 2582 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2583 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2584 return; 2585 2586 spin_lock_bh(&rtwdev->ba_lock); 2587 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2588 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2589 spin_unlock_bh(&rtwdev->ba_lock); 2590 2591 ieee80211_stop_tx_ba_session(sta, txq->tid); 2592 cancel_delayed_work(&rtwdev->forbid_ba_work); 2593 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2594 RTW89_FORBID_BA_TIMER); 2595 } 2596 2597 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2598 struct rtw89_txq *rtwtxq, 2599 struct sk_buff *skb) 2600 { 2601 struct ieee80211_hw *hw = rtwdev->hw; 2602 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2603 struct ieee80211_sta *sta = txq->sta; 2604 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2605 2606 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2607 return; 2608 2609 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2610 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2611 return; 2612 } 2613 2614 if (unlikely(!sta)) 2615 return; 2616 2617 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2618 return; 2619 2620 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2621 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2622 return; 2623 } 2624 2625 spin_lock_bh(&rtwdev->ba_lock); 2626 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2627 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2628 ieee80211_queue_work(hw, &rtwdev->ba_work); 2629 } 2630 spin_unlock_bh(&rtwdev->ba_lock); 2631 } 2632 2633 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2634 struct rtw89_txq *rtwtxq, 2635 unsigned long frame_cnt, 2636 unsigned long byte_cnt) 2637 { 2638 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2639 struct ieee80211_vif *vif = txq->vif; 2640 struct ieee80211_sta *sta = txq->sta; 2641 struct sk_buff *skb; 2642 unsigned long i; 2643 int ret; 2644 2645 rcu_read_lock(); 2646 for (i = 0; i < frame_cnt; i++) { 2647 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2648 if (!skb) { 2649 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2650 goto out; 2651 } 2652 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2653 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2654 if (ret) { 2655 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2656 ieee80211_free_txskb(rtwdev->hw, skb); 2657 break; 2658 } 2659 } 2660 out: 2661 rcu_read_unlock(); 2662 } 2663 2664 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2665 { 2666 u8 qsel, ch_dma; 2667 2668 qsel = rtw89_core_get_qsel(rtwdev, tid); 2669 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2670 2671 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2672 } 2673 2674 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2675 struct ieee80211_txq *txq, 2676 unsigned long *frame_cnt, 2677 bool *sched_txq, bool *reinvoke) 2678 { 2679 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2680 struct ieee80211_sta *sta = txq->sta; 2681 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2682 2683 if (!sta || rtwsta->max_agg_wait <= 0) 2684 return false; 2685 2686 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2687 return false; 2688 2689 if (*frame_cnt > 1) { 2690 *frame_cnt -= 1; 2691 *sched_txq = true; 2692 *reinvoke = true; 2693 rtwtxq->wait_cnt = 1; 2694 return false; 2695 } 2696 2697 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2698 *reinvoke = true; 2699 rtwtxq->wait_cnt++; 2700 return true; 2701 } 2702 2703 rtwtxq->wait_cnt = 0; 2704 return false; 2705 } 2706 2707 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2708 { 2709 struct ieee80211_hw *hw = rtwdev->hw; 2710 struct ieee80211_txq *txq; 2711 struct rtw89_vif *rtwvif; 2712 struct rtw89_txq *rtwtxq; 2713 unsigned long frame_cnt; 2714 unsigned long byte_cnt; 2715 u32 tx_resource; 2716 bool sched_txq; 2717 2718 ieee80211_txq_schedule_start(hw, ac); 2719 while ((txq = ieee80211_next_txq(hw, ac))) { 2720 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2721 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv; 2722 2723 if (rtwvif->offchan) { 2724 ieee80211_return_txq(hw, txq, true); 2725 continue; 2726 } 2727 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2728 sched_txq = false; 2729 2730 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2731 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2732 ieee80211_return_txq(hw, txq, true); 2733 continue; 2734 } 2735 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2736 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2737 ieee80211_return_txq(hw, txq, sched_txq); 2738 if (frame_cnt != 0) 2739 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2740 2741 /* bound of tx_resource could get stuck due to burst traffic */ 2742 if (frame_cnt == tx_resource) 2743 *reinvoke = true; 2744 } 2745 ieee80211_txq_schedule_end(hw, ac); 2746 } 2747 2748 static void rtw89_ips_work(struct work_struct *work) 2749 { 2750 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2751 ips_work); 2752 mutex_lock(&rtwdev->mutex); 2753 rtw89_enter_ips_by_hwflags(rtwdev); 2754 mutex_unlock(&rtwdev->mutex); 2755 } 2756 2757 static void rtw89_core_txq_work(struct work_struct *w) 2758 { 2759 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2760 bool reinvoke = false; 2761 u8 ac; 2762 2763 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2764 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2765 2766 if (reinvoke) { 2767 /* reinvoke to process the last frame */ 2768 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2769 } 2770 } 2771 2772 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2773 { 2774 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2775 txq_reinvoke_work.work); 2776 2777 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2778 } 2779 2780 static void rtw89_forbid_ba_work(struct work_struct *w) 2781 { 2782 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2783 forbid_ba_work.work); 2784 struct rtw89_txq *rtwtxq, *tmp; 2785 2786 spin_lock_bh(&rtwdev->ba_lock); 2787 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2788 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2789 list_del_init(&rtwtxq->list); 2790 } 2791 spin_unlock_bh(&rtwdev->ba_lock); 2792 } 2793 2794 static void rtw89_core_sta_pending_tx_iter(void *data, 2795 struct ieee80211_sta *sta) 2796 { 2797 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2798 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif; 2799 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2800 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2801 struct sk_buff *skb, *tmp; 2802 int qsel, ret; 2803 2804 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx) 2805 return; 2806 2807 if (skb_queue_len(&rtwsta->roc_queue) == 0) 2808 return; 2809 2810 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2811 skb_unlink(skb, &rtwsta->roc_queue); 2812 2813 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2814 if (ret) { 2815 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 2816 dev_kfree_skb_any(skb); 2817 } else { 2818 rtw89_core_tx_kick_off(rtwdev, qsel); 2819 } 2820 } 2821 } 2822 2823 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 2824 struct rtw89_vif *rtwvif) 2825 { 2826 ieee80211_iterate_stations_atomic(rtwdev->hw, 2827 rtw89_core_sta_pending_tx_iter, 2828 rtwvif); 2829 } 2830 2831 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 2832 struct rtw89_vif *rtwvif, bool qos, bool ps) 2833 { 2834 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2835 struct ieee80211_sta *sta; 2836 struct ieee80211_hdr *hdr; 2837 struct sk_buff *skb; 2838 int ret, qsel; 2839 2840 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 2841 return 0; 2842 2843 rcu_read_lock(); 2844 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 2845 if (!sta) { 2846 ret = -EINVAL; 2847 goto out; 2848 } 2849 2850 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos); 2851 if (!skb) { 2852 ret = -ENOMEM; 2853 goto out; 2854 } 2855 2856 hdr = (struct ieee80211_hdr *)skb->data; 2857 if (ps) 2858 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2859 2860 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2861 if (ret) { 2862 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 2863 dev_kfree_skb_any(skb); 2864 goto out; 2865 } 2866 2867 rcu_read_unlock(); 2868 2869 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 2870 RTW89_ROC_TX_TIMEOUT); 2871 out: 2872 rcu_read_unlock(); 2873 2874 return ret; 2875 } 2876 2877 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2878 { 2879 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2880 struct ieee80211_hw *hw = rtwdev->hw; 2881 struct rtw89_roc *roc = &rtwvif->roc; 2882 struct cfg80211_chan_def roc_chan; 2883 struct rtw89_vif *tmp; 2884 int ret; 2885 2886 lockdep_assert_held(&rtwdev->mutex); 2887 2888 rtw89_leave_ips_by_hwflags(rtwdev); 2889 rtw89_leave_lps(rtwdev); 2890 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC); 2891 2892 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true); 2893 if (ret) 2894 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2895 "roc send null-1 failed: %d\n", ret); 2896 2897 rtw89_for_each_rtwvif(rtwdev, tmp) 2898 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2899 tmp->offchan = true; 2900 2901 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 2902 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan); 2903 rtw89_set_channel(rtwdev); 2904 rtw89_write32_clr(rtwdev, 2905 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2906 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 2907 2908 ieee80211_ready_on_channel(hw); 2909 cancel_delayed_work(&rtwvif->roc.roc_work); 2910 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 2911 msecs_to_jiffies(rtwvif->roc.duration)); 2912 } 2913 2914 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2915 { 2916 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2917 struct ieee80211_hw *hw = rtwdev->hw; 2918 struct rtw89_roc *roc = &rtwvif->roc; 2919 struct rtw89_vif *tmp; 2920 int ret; 2921 2922 lockdep_assert_held(&rtwdev->mutex); 2923 2924 ieee80211_remain_on_channel_expired(hw); 2925 2926 rtw89_leave_ips_by_hwflags(rtwdev); 2927 rtw89_leave_lps(rtwdev); 2928 2929 rtw89_write32_mask(rtwdev, 2930 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2931 B_AX_RX_FLTR_CFG_MASK, 2932 rtwdev->hal.rx_fltr); 2933 2934 roc->state = RTW89_ROC_IDLE; 2935 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL); 2936 rtw89_chanctx_proceed(rtwdev); 2937 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false); 2938 if (ret) 2939 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2940 "roc send null-0 failed: %d\n", ret); 2941 2942 rtw89_for_each_rtwvif(rtwdev, tmp) 2943 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2944 tmp->offchan = false; 2945 2946 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif); 2947 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2948 2949 if (hw->conf.flags & IEEE80211_CONF_IDLE) 2950 ieee80211_queue_delayed_work(hw, &roc->roc_work, 2951 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 2952 } 2953 2954 void rtw89_roc_work(struct work_struct *work) 2955 { 2956 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 2957 roc.roc_work.work); 2958 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2959 struct rtw89_roc *roc = &rtwvif->roc; 2960 2961 mutex_lock(&rtwdev->mutex); 2962 2963 switch (roc->state) { 2964 case RTW89_ROC_IDLE: 2965 rtw89_enter_ips_by_hwflags(rtwdev); 2966 break; 2967 case RTW89_ROC_MGMT: 2968 case RTW89_ROC_NORMAL: 2969 rtw89_roc_end(rtwdev, rtwvif); 2970 break; 2971 default: 2972 break; 2973 } 2974 2975 mutex_unlock(&rtwdev->mutex); 2976 } 2977 2978 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 2979 u32 throughput, u64 cnt) 2980 { 2981 if (cnt < 100) 2982 return RTW89_TFC_IDLE; 2983 if (throughput > 50) 2984 return RTW89_TFC_HIGH; 2985 if (throughput > 10) 2986 return RTW89_TFC_MID; 2987 if (throughput > 2) 2988 return RTW89_TFC_LOW; 2989 return RTW89_TFC_ULTRA_LOW; 2990 } 2991 2992 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 2993 struct rtw89_traffic_stats *stats) 2994 { 2995 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2996 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2997 2998 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 2999 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3000 3001 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3002 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3003 3004 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3005 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3006 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3007 stats->tx_cnt); 3008 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3009 stats->rx_cnt); 3010 stats->tx_avg_len = stats->tx_cnt ? 3011 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3012 stats->rx_avg_len = stats->rx_cnt ? 3013 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3014 3015 stats->tx_unicast = 0; 3016 stats->rx_unicast = 0; 3017 stats->tx_cnt = 0; 3018 stats->rx_cnt = 0; 3019 stats->rx_tf_periodic = stats->rx_tf_acc; 3020 stats->rx_tf_acc = 0; 3021 3022 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3023 return true; 3024 3025 return false; 3026 } 3027 3028 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3029 { 3030 struct rtw89_vif *rtwvif; 3031 bool tfc_changed; 3032 3033 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3034 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3035 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3036 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif); 3037 } 3038 3039 return tfc_changed; 3040 } 3041 3042 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3043 { 3044 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 3045 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 3046 rtwvif->tdls_peer) 3047 return; 3048 3049 if (rtwvif->offchan) 3050 return; 3051 3052 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 3053 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 3054 rtw89_enter_lps(rtwdev, rtwvif, true); 3055 } 3056 3057 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3058 { 3059 struct rtw89_vif *rtwvif; 3060 3061 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3062 rtw89_vif_enter_lps(rtwdev, rtwvif); 3063 } 3064 3065 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3066 { 3067 enum rtw89_entity_mode mode; 3068 3069 mode = rtw89_get_entity_mode(rtwdev); 3070 if (mode == RTW89_ENTITY_MODE_MCC) 3071 return; 3072 3073 rtw89_chip_rfk_track(rtwdev); 3074 } 3075 3076 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3077 { 3078 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3079 3080 if (mode == RTW89_ENTITY_MODE_MCC) 3081 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3082 else 3083 rtw89_process_p2p_ps(rtwdev, vif); 3084 } 3085 3086 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3087 struct rtw89_traffic_stats *stats) 3088 { 3089 stats->tx_unicast = 0; 3090 stats->rx_unicast = 0; 3091 stats->tx_cnt = 0; 3092 stats->rx_cnt = 0; 3093 ewma_tp_init(&stats->tx_ewma_tp); 3094 ewma_tp_init(&stats->rx_ewma_tp); 3095 } 3096 3097 static void rtw89_track_work(struct work_struct *work) 3098 { 3099 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3100 track_work.work); 3101 bool tfc_changed; 3102 3103 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3104 return; 3105 3106 mutex_lock(&rtwdev->mutex); 3107 3108 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3109 goto out; 3110 3111 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3112 RTW89_TRACK_WORK_PERIOD); 3113 3114 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3115 if (rtwdev->scanning) 3116 goto out; 3117 3118 rtw89_leave_lps(rtwdev); 3119 3120 if (tfc_changed) { 3121 rtw89_hci_recalc_int_mit(rtwdev); 3122 rtw89_btc_ntfy_wl_sta(rtwdev); 3123 } 3124 rtw89_mac_bf_monitor_track(rtwdev); 3125 rtw89_phy_stat_track(rtwdev); 3126 rtw89_phy_env_monitor_track(rtwdev); 3127 rtw89_phy_dig(rtwdev); 3128 rtw89_core_rfk_track(rtwdev); 3129 rtw89_phy_ra_update(rtwdev); 3130 rtw89_phy_cfo_track(rtwdev); 3131 rtw89_phy_tx_path_div_track(rtwdev); 3132 rtw89_phy_antdiv_track(rtwdev); 3133 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3134 rtw89_phy_edcca_track(rtwdev); 3135 rtw89_tas_track(rtwdev); 3136 rtw89_chanctx_track(rtwdev); 3137 3138 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3139 rtw89_enter_lps_track(rtwdev); 3140 3141 out: 3142 mutex_unlock(&rtwdev->mutex); 3143 } 3144 3145 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3146 { 3147 unsigned long bit; 3148 3149 bit = find_first_zero_bit(addr, size); 3150 if (bit < size) 3151 set_bit(bit, addr); 3152 3153 return bit; 3154 } 3155 3156 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3157 { 3158 clear_bit(bit, addr); 3159 } 3160 3161 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3162 { 3163 bitmap_zero(addr, nbits); 3164 } 3165 3166 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3167 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3168 { 3169 const struct rtw89_chip_info *chip = rtwdev->chip; 3170 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3171 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3172 u8 idx; 3173 int i; 3174 3175 lockdep_assert_held(&rtwdev->mutex); 3176 3177 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3178 if (idx == chip->bacam_num) { 3179 /* allocate a static BA CAM to tid=0/5, so replace the existing 3180 * one if BA CAM is full. Hardware will process the original tid 3181 * automatically. 3182 */ 3183 if (tid != 0 && tid != 5) 3184 return -ENOSPC; 3185 3186 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3187 tmp = &cam_info->ba_cam_entry[i]; 3188 if (tmp->tid == 0 || tmp->tid == 5) 3189 continue; 3190 3191 idx = i; 3192 entry = tmp; 3193 list_del(&entry->list); 3194 break; 3195 } 3196 3197 if (!entry) 3198 return -ENOSPC; 3199 } else { 3200 entry = &cam_info->ba_cam_entry[idx]; 3201 } 3202 3203 entry->tid = tid; 3204 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 3205 3206 *cam_idx = idx; 3207 3208 return 0; 3209 } 3210 3211 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3212 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3213 { 3214 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3215 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3216 u8 idx; 3217 3218 lockdep_assert_held(&rtwdev->mutex); 3219 3220 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 3221 if (entry->tid != tid) 3222 continue; 3223 3224 idx = entry - cam_info->ba_cam_entry; 3225 list_del(&entry->list); 3226 3227 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3228 *cam_idx = idx; 3229 return 0; 3230 } 3231 3232 return -ENOENT; 3233 } 3234 3235 #define RTW89_TYPE_MAPPING(_type) \ 3236 case NL80211_IFTYPE_ ## _type: \ 3237 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3238 break 3239 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 3240 { 3241 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3242 3243 switch (vif->type) { 3244 case NL80211_IFTYPE_STATION: 3245 if (vif->p2p) 3246 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3247 else 3248 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 3249 break; 3250 case NL80211_IFTYPE_AP: 3251 if (vif->p2p) 3252 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3253 else 3254 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 3255 break; 3256 RTW89_TYPE_MAPPING(ADHOC); 3257 RTW89_TYPE_MAPPING(MONITOR); 3258 RTW89_TYPE_MAPPING(MESH_POINT); 3259 default: 3260 WARN_ON(1); 3261 break; 3262 } 3263 3264 switch (vif->type) { 3265 case NL80211_IFTYPE_AP: 3266 case NL80211_IFTYPE_MESH_POINT: 3267 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 3268 rtwvif->self_role = RTW89_SELF_ROLE_AP; 3269 break; 3270 case NL80211_IFTYPE_ADHOC: 3271 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 3272 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3273 break; 3274 case NL80211_IFTYPE_STATION: 3275 if (assoc) { 3276 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 3277 rtwvif->trigger = vif->bss_conf.he_support; 3278 } else { 3279 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 3280 rtwvif->trigger = false; 3281 } 3282 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3283 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3284 break; 3285 case NL80211_IFTYPE_MONITOR: 3286 break; 3287 default: 3288 WARN_ON(1); 3289 break; 3290 } 3291 } 3292 3293 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3294 struct ieee80211_vif *vif, 3295 struct ieee80211_sta *sta) 3296 { 3297 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3298 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3299 struct rtw89_hal *hal = &rtwdev->hal; 3300 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3301 int i; 3302 int ret; 3303 3304 rtwsta->rtwdev = rtwdev; 3305 rtwsta->rtwvif = rtwvif; 3306 rtwsta->prev_rssi = 0; 3307 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 3308 skb_queue_head_init(&rtwsta->roc_queue); 3309 3310 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 3311 rtw89_core_txq_init(rtwdev, sta->txq[i]); 3312 3313 ewma_rssi_init(&rtwsta->avg_rssi); 3314 ewma_snr_init(&rtwsta->avg_snr); 3315 for (i = 0; i < ant_num; i++) { 3316 ewma_rssi_init(&rtwsta->rssi[i]); 3317 ewma_evm_init(&rtwsta->evm_min[i]); 3318 ewma_evm_init(&rtwsta->evm_max[i]); 3319 } 3320 3321 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3322 /* for station mode, assign the mac_id from itself */ 3323 rtwsta->mac_id = rtwvif->mac_id; 3324 /* must do rtw89_reg_6ghz_power_recalc() before rfk channel */ 3325 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, true); 3326 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3327 BTC_ROLE_MSTS_STA_CONN_START); 3328 rtw89_chip_rfk_channel(rtwdev); 3329 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3330 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 3331 RTW89_MAX_MAC_ID_NUM); 3332 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 3333 return -ENOSPC; 3334 3335 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 3336 if (ret) { 3337 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3338 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3339 return ret; 3340 } 3341 3342 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3343 RTW89_ROLE_CREATE); 3344 if (ret) { 3345 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3346 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3347 return ret; 3348 } 3349 3350 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta); 3351 if (ret) 3352 return ret; 3353 3354 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta); 3355 if (ret) 3356 return ret; 3357 3358 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3359 } 3360 3361 return 0; 3362 } 3363 3364 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3365 struct ieee80211_vif *vif, 3366 struct ieee80211_sta *sta) 3367 { 3368 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3369 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3370 3371 if (vif->type == NL80211_IFTYPE_STATION) 3372 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false); 3373 3374 rtwdev->total_sta_assoc--; 3375 if (sta->tdls) 3376 rtwvif->tdls_peer--; 3377 rtwsta->disassoc = true; 3378 3379 return 0; 3380 } 3381 3382 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3383 struct ieee80211_vif *vif, 3384 struct ieee80211_sta *sta) 3385 { 3386 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3387 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3388 int ret; 3389 3390 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 3391 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 3392 rtw89_core_free_sta_pending_ba(rtwdev, sta); 3393 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 3394 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta); 3395 3396 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 3397 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 3398 if (sta->tdls) 3399 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 3400 3401 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3402 rtw89_vif_type_mapping(vif, false); 3403 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 3404 } 3405 3406 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3407 if (ret) { 3408 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3409 return ret; 3410 } 3411 3412 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 3413 if (ret) { 3414 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3415 return ret; 3416 } 3417 3418 /* update cam aid mac_id net_type */ 3419 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3420 if (ret) { 3421 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3422 return ret; 3423 } 3424 3425 return ret; 3426 } 3427 3428 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3429 struct ieee80211_vif *vif, 3430 struct ieee80211_sta *sta) 3431 { 3432 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3433 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3434 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 3435 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3436 rtwvif->sub_entity_idx); 3437 int ret; 3438 3439 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3440 if (sta->tdls) { 3441 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 3442 if (ret) { 3443 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3444 return ret; 3445 } 3446 } 3447 3448 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 3449 if (ret) { 3450 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3451 return ret; 3452 } 3453 } 3454 3455 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3456 if (ret) { 3457 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3458 return ret; 3459 } 3460 3461 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 3462 if (ret) { 3463 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3464 return ret; 3465 } 3466 3467 /* update cam aid mac_id net_type */ 3468 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3469 if (ret) { 3470 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3471 return ret; 3472 } 3473 3474 rtwdev->total_sta_assoc++; 3475 if (sta->tdls) 3476 rtwvif->tdls_peer++; 3477 rtw89_phy_ra_assoc(rtwdev, sta); 3478 rtw89_mac_bf_assoc(rtwdev, vif, sta); 3479 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 3480 3481 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3482 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 3483 3484 if (bss_conf->he_support && 3485 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 3486 rtwsta->er_cap = true; 3487 3488 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3489 BTC_ROLE_MSTS_STA_CONN_END); 3490 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan); 3491 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 3492 3493 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 3494 if (ret) { 3495 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3496 return ret; 3497 } 3498 3499 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 3500 } 3501 3502 return ret; 3503 } 3504 3505 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3506 struct ieee80211_vif *vif, 3507 struct ieee80211_sta *sta) 3508 { 3509 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3510 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3511 int ret; 3512 3513 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3514 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, false); 3515 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3516 BTC_ROLE_MSTS_STA_DIS_CONN); 3517 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3518 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3519 3520 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3521 RTW89_ROLE_REMOVE); 3522 if (ret) { 3523 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3524 return ret; 3525 } 3526 3527 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3528 } 3529 3530 return 0; 3531 } 3532 3533 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3534 struct ieee80211_sta *sta, 3535 struct cfg80211_tid_cfg *tid_conf) 3536 { 3537 struct ieee80211_txq *txq; 3538 struct rtw89_txq *rtwtxq; 3539 u32 mask = tid_conf->mask; 3540 u8 tids = tid_conf->tids; 3541 int tids_nbit = BITS_PER_BYTE; 3542 int i; 3543 3544 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3545 if (!tids) 3546 break; 3547 3548 if (!(tids & BIT(0))) 3549 continue; 3550 3551 txq = sta->txq[i]; 3552 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3553 3554 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 3555 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 3556 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3557 } else { 3558 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 3559 ieee80211_stop_tx_ba_session(sta, txq->tid); 3560 spin_lock_bh(&rtwdev->ba_lock); 3561 list_del_init(&rtwtxq->list); 3562 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3563 spin_unlock_bh(&rtwdev->ba_lock); 3564 } 3565 } 3566 3567 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 3568 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 3569 sta->max_amsdu_subframes = 0; 3570 else 3571 sta->max_amsdu_subframes = 1; 3572 } 3573 } 3574 } 3575 3576 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3577 struct ieee80211_sta *sta, 3578 struct cfg80211_tid_config *tid_config) 3579 { 3580 int i; 3581 3582 for (i = 0; i < tid_config->n_tid_conf; i++) 3583 _rtw89_core_set_tid_config(rtwdev, sta, 3584 &tid_config->tid_conf[i]); 3585 } 3586 3587 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 3588 struct ieee80211_sta_ht_cap *ht_cap) 3589 { 3590 static const __le16 highest[RF_PATH_MAX] = { 3591 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 3592 }; 3593 struct rtw89_hal *hal = &rtwdev->hal; 3594 u8 nss = hal->rx_nss; 3595 int i; 3596 3597 ht_cap->ht_supported = true; 3598 ht_cap->cap = 0; 3599 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 3600 IEEE80211_HT_CAP_MAX_AMSDU | 3601 IEEE80211_HT_CAP_TX_STBC | 3602 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 3603 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 3604 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 3605 IEEE80211_HT_CAP_DSSSCCK40 | 3606 IEEE80211_HT_CAP_SGI_40; 3607 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 3608 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 3609 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 3610 for (i = 0; i < nss; i++) 3611 ht_cap->mcs.rx_mask[i] = 0xFF; 3612 ht_cap->mcs.rx_mask[4] = 0x01; 3613 ht_cap->mcs.rx_highest = highest[nss - 1]; 3614 } 3615 3616 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 3617 struct ieee80211_sta_vht_cap *vht_cap) 3618 { 3619 static const __le16 highest_bw80[RF_PATH_MAX] = { 3620 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 3621 }; 3622 static const __le16 highest_bw160[RF_PATH_MAX] = { 3623 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 3624 }; 3625 const struct rtw89_chip_info *chip = rtwdev->chip; 3626 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 3627 highest_bw160 : highest_bw80; 3628 struct rtw89_hal *hal = &rtwdev->hal; 3629 u16 tx_mcs_map = 0, rx_mcs_map = 0; 3630 u8 sts_cap = 3; 3631 int i; 3632 3633 for (i = 0; i < 8; i++) { 3634 if (i < hal->tx_nss) 3635 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3636 else 3637 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3638 if (i < hal->rx_nss) 3639 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3640 else 3641 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3642 } 3643 3644 vht_cap->vht_supported = true; 3645 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 3646 IEEE80211_VHT_CAP_SHORT_GI_80 | 3647 IEEE80211_VHT_CAP_RXSTBC_1 | 3648 IEEE80211_VHT_CAP_HTC_VHT | 3649 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 3650 0; 3651 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 3652 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 3653 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 3654 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 3655 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 3656 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3657 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 3658 IEEE80211_VHT_CAP_SHORT_GI_160; 3659 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 3660 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 3661 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 3662 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 3663 3664 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 3665 vht_cap->vht_mcs.tx_highest |= 3666 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 3667 } 3668 3669 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 3670 enum nl80211_band band, 3671 enum nl80211_iftype iftype, 3672 struct ieee80211_sband_iftype_data *iftype_data) 3673 { 3674 const struct rtw89_chip_info *chip = rtwdev->chip; 3675 struct rtw89_hal *hal = &rtwdev->hal; 3676 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 3677 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 3678 struct ieee80211_sta_he_cap *he_cap; 3679 int nss = hal->rx_nss; 3680 u8 *mac_cap_info; 3681 u8 *phy_cap_info; 3682 u16 mcs_map = 0; 3683 int i; 3684 3685 for (i = 0; i < 8; i++) { 3686 if (i < nss) 3687 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 3688 else 3689 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 3690 } 3691 3692 he_cap = &iftype_data->he_cap; 3693 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 3694 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 3695 3696 he_cap->has_he = true; 3697 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 3698 if (iftype == NL80211_IFTYPE_STATION) 3699 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 3700 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 3701 IEEE80211_HE_MAC_CAP2_BSR; 3702 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 3703 if (iftype == NL80211_IFTYPE_AP) 3704 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 3705 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 3706 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 3707 if (iftype == NL80211_IFTYPE_STATION) 3708 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 3709 if (band == NL80211_BAND_2GHZ) { 3710 phy_cap_info[0] = 3711 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 3712 } else { 3713 phy_cap_info[0] = 3714 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 3715 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3716 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 3717 } 3718 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 3719 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 3720 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 3721 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 3722 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 3723 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 3724 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 3725 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 3726 if (iftype == NL80211_IFTYPE_STATION) 3727 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 3728 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 3729 if (iftype == NL80211_IFTYPE_AP) 3730 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 3731 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 3732 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 3733 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3734 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 3735 phy_cap_info[5] = no_ng16 ? 0 : 3736 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 3737 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 3738 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 3739 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 3740 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 3741 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 3742 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 3743 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 3744 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 3745 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 3746 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 3747 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 3748 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3749 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 3750 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 3751 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 3752 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 3753 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 3754 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 3755 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 3756 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 3757 if (iftype == NL80211_IFTYPE_STATION) 3758 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 3759 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 3760 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 3761 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 3762 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 3763 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 3764 } 3765 3766 if (band == NL80211_BAND_6GHZ) { 3767 __le16 capa; 3768 3769 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 3770 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 3771 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 3772 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 3773 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 3774 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 3775 iftype_data->he_6ghz_capa.capa = capa; 3776 } 3777 } 3778 3779 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 3780 enum nl80211_band band, 3781 enum nl80211_iftype iftype, 3782 struct ieee80211_sband_iftype_data *iftype_data) 3783 { 3784 const struct rtw89_chip_info *chip = rtwdev->chip; 3785 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 3786 struct ieee80211_eht_mcs_nss_supp *eht_nss; 3787 struct ieee80211_sta_eht_cap *eht_cap; 3788 struct rtw89_hal *hal = &rtwdev->hal; 3789 bool support_320mhz = false; 3790 int sts = 3; 3791 u8 val; 3792 3793 if (chip->chip_gen == RTW89_CHIP_AX) 3794 return; 3795 3796 if (band == NL80211_BAND_6GHZ && 3797 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 3798 support_320mhz = true; 3799 3800 eht_cap = &iftype_data->eht_cap; 3801 eht_cap_elem = &eht_cap->eht_cap_elem; 3802 eht_nss = &eht_cap->eht_mcs_nss_supp; 3803 3804 eht_cap->has_eht = true; 3805 3806 eht_cap_elem->mac_cap_info[0] = 3807 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 3808 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 3809 eht_cap_elem->mac_cap_info[1] = 0; 3810 3811 eht_cap_elem->phy_cap_info[0] = 3812 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 3813 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 3814 if (support_320mhz) 3815 eht_cap_elem->phy_cap_info[0] |= 3816 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 3817 3818 eht_cap_elem->phy_cap_info[0] |= 3819 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 3820 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 3821 eht_cap_elem->phy_cap_info[1] = 3822 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 3823 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 3824 u8_encode_bits(sts - 1, 3825 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 3826 if (support_320mhz) 3827 eht_cap_elem->phy_cap_info[1] |= 3828 u8_encode_bits(sts - 1, 3829 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 3830 3831 eht_cap_elem->phy_cap_info[2] = 0; 3832 3833 eht_cap_elem->phy_cap_info[3] = 3834 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK | 3835 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK | 3836 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 3837 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 3838 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK; 3839 3840 eht_cap_elem->phy_cap_info[4] = 3841 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 3842 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 3843 3844 eht_cap_elem->phy_cap_info[5] = 3845 IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK | 3846 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 3847 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 3848 3849 eht_cap_elem->phy_cap_info[6] = 0; 3850 eht_cap_elem->phy_cap_info[7] = 0; 3851 eht_cap_elem->phy_cap_info[8] = 0; 3852 3853 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 3854 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 3855 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 3856 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 3857 eht_nss->bw._80.rx_tx_mcs13_max_nss = val; 3858 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 3859 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 3860 eht_nss->bw._160.rx_tx_mcs13_max_nss = val; 3861 if (support_320mhz) { 3862 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 3863 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 3864 eht_nss->bw._320.rx_tx_mcs13_max_nss = val; 3865 } 3866 } 3867 3868 #define RTW89_SBAND_IFTYPES_NR 2 3869 3870 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 3871 enum nl80211_band band, 3872 struct ieee80211_supported_band *sband) 3873 { 3874 struct ieee80211_sband_iftype_data *iftype_data; 3875 enum nl80211_iftype iftype; 3876 int idx = 0; 3877 3878 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 3879 if (!iftype_data) 3880 return; 3881 3882 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 3883 switch (iftype) { 3884 case NL80211_IFTYPE_STATION: 3885 case NL80211_IFTYPE_AP: 3886 break; 3887 default: 3888 continue; 3889 } 3890 3891 if (idx >= RTW89_SBAND_IFTYPES_NR) { 3892 rtw89_warn(rtwdev, "run out of iftype_data\n"); 3893 break; 3894 } 3895 3896 iftype_data[idx].types_mask = BIT(iftype); 3897 3898 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 3899 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 3900 3901 idx++; 3902 } 3903 3904 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 3905 } 3906 3907 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 3908 { 3909 struct ieee80211_hw *hw = rtwdev->hw; 3910 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 3911 struct ieee80211_supported_band *sband_6ghz = NULL; 3912 u32 size = sizeof(struct ieee80211_supported_band); 3913 u8 support_bands = rtwdev->chip->support_bands; 3914 3915 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 3916 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 3917 if (!sband_2ghz) 3918 goto err; 3919 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 3920 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 3921 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 3922 } 3923 3924 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 3925 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 3926 if (!sband_5ghz) 3927 goto err; 3928 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 3929 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 3930 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 3931 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 3932 } 3933 3934 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 3935 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 3936 if (!sband_6ghz) 3937 goto err; 3938 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 3939 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 3940 } 3941 3942 return 0; 3943 3944 err: 3945 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3946 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3947 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3948 if (sband_2ghz) 3949 kfree((__force void *)sband_2ghz->iftype_data); 3950 if (sband_5ghz) 3951 kfree((__force void *)sband_5ghz->iftype_data); 3952 if (sband_6ghz) 3953 kfree((__force void *)sband_6ghz->iftype_data); 3954 kfree(sband_2ghz); 3955 kfree(sband_5ghz); 3956 kfree(sband_6ghz); 3957 return -ENOMEM; 3958 } 3959 3960 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 3961 { 3962 struct ieee80211_hw *hw = rtwdev->hw; 3963 3964 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 3965 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 3966 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 3967 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 3968 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 3969 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 3970 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 3971 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 3972 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 3973 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3974 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3975 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3976 } 3977 3978 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 3979 { 3980 int i; 3981 3982 for (i = 0; i < RTW89_PHY_MAX; i++) 3983 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 3984 for (i = 0; i < RTW89_PHY_MAX; i++) 3985 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 3986 } 3987 3988 void rtw89_core_update_beacon_work(struct work_struct *work) 3989 { 3990 struct rtw89_dev *rtwdev; 3991 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3992 update_beacon_work); 3993 3994 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 3995 return; 3996 3997 rtwdev = rtwvif->rtwdev; 3998 mutex_lock(&rtwdev->mutex); 3999 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif); 4000 mutex_unlock(&rtwdev->mutex); 4001 } 4002 4003 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4004 { 4005 struct completion *cmpl = &wait->completion; 4006 unsigned long timeout; 4007 unsigned int cur; 4008 4009 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4010 if (cur != RTW89_WAIT_COND_IDLE) 4011 return -EBUSY; 4012 4013 timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4014 if (timeout == 0) { 4015 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4016 return -ETIMEDOUT; 4017 } 4018 4019 if (wait->data.err) 4020 return -EFAULT; 4021 4022 return 0; 4023 } 4024 4025 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4026 const struct rtw89_completion_data *data) 4027 { 4028 unsigned int cur; 4029 4030 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4031 if (cur != cond) 4032 return; 4033 4034 wait->data = *data; 4035 complete(&wait->completion); 4036 } 4037 4038 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4039 { 4040 u16 bt_req_len; 4041 4042 switch (event) { 4043 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4044 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4045 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4046 "coex updates BT req len to %d TU\n", bt_req_len); 4047 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4048 break; 4049 default: 4050 if (event < NUM_OF_RTW89_BTC_HMSG) 4051 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4052 "unhandled BTC HMSG event: %d\n", event); 4053 else 4054 rtw89_warn(rtwdev, 4055 "unrecognized BTC HMSG event: %d\n", event); 4056 break; 4057 } 4058 } 4059 4060 int rtw89_core_start(struct rtw89_dev *rtwdev) 4061 { 4062 int ret; 4063 4064 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 4065 ret = rtw89_mac_init(rtwdev); 4066 if (ret) { 4067 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4068 return ret; 4069 } 4070 4071 rtw89_btc_ntfy_poweron(rtwdev); 4072 4073 /* efuse process */ 4074 4075 /* pre-config BB/RF, BB reset/RFC reset */ 4076 ret = rtw89_chip_reset_bb_rf(rtwdev); 4077 if (ret) 4078 return ret; 4079 4080 rtw89_phy_init_bb_reg(rtwdev); 4081 rtw89_chip_bb_postinit(rtwdev); 4082 rtw89_phy_init_rf_reg(rtwdev, false); 4083 4084 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4085 4086 rtw89_phy_dm_init(rtwdev); 4087 4088 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 4089 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 4090 4091 rtw89_tas_reset(rtwdev); 4092 4093 ret = rtw89_hci_start(rtwdev); 4094 if (ret) { 4095 rtw89_err(rtwdev, "failed to start hci\n"); 4096 return ret; 4097 } 4098 4099 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 4100 RTW89_TRACK_WORK_PERIOD); 4101 4102 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4103 4104 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4105 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4106 rtw89_fw_h2c_init_ba_cam(rtwdev); 4107 4108 return 0; 4109 } 4110 4111 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4112 { 4113 struct rtw89_btc *btc = &rtwdev->btc; 4114 4115 /* Prvent to stop twice; enter_ips and ops_stop */ 4116 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4117 return; 4118 4119 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4120 4121 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4122 4123 mutex_unlock(&rtwdev->mutex); 4124 4125 cancel_work_sync(&rtwdev->c2h_work); 4126 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work); 4127 cancel_work_sync(&btc->eapol_notify_work); 4128 cancel_work_sync(&btc->arp_notify_work); 4129 cancel_work_sync(&btc->dhcp_notify_work); 4130 cancel_work_sync(&btc->icmp_notify_work); 4131 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4132 cancel_delayed_work_sync(&rtwdev->track_work); 4133 cancel_delayed_work_sync(&rtwdev->chanctx_work); 4134 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 4135 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 4136 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 4137 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 4138 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4139 cancel_delayed_work_sync(&rtwdev->antdiv_work); 4140 4141 mutex_lock(&rtwdev->mutex); 4142 4143 rtw89_btc_ntfy_poweroff(rtwdev); 4144 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4145 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4146 rtw89_hci_stop(rtwdev); 4147 rtw89_hci_deinit(rtwdev); 4148 rtw89_mac_pwr_off(rtwdev); 4149 rtw89_hci_reset(rtwdev); 4150 } 4151 4152 int rtw89_core_init(struct rtw89_dev *rtwdev) 4153 { 4154 struct rtw89_btc *btc = &rtwdev->btc; 4155 u8 band; 4156 4157 INIT_LIST_HEAD(&rtwdev->ba_list); 4158 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 4159 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 4160 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 4161 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 4162 if (!(rtwdev->chip->support_bands & BIT(band))) 4163 continue; 4164 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 4165 } 4166 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 4167 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 4168 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 4169 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 4170 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); 4171 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 4172 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 4173 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 4174 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 4175 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 4176 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 4177 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 4178 if (!rtwdev->txq_wq) 4179 return -ENOMEM; 4180 spin_lock_init(&rtwdev->ba_lock); 4181 spin_lock_init(&rtwdev->rpwm_lock); 4182 mutex_init(&rtwdev->mutex); 4183 mutex_init(&rtwdev->rf_mutex); 4184 rtwdev->total_sta_assoc = 0; 4185 4186 rtw89_init_wait(&rtwdev->mcc.wait); 4187 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 4188 4189 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 4190 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 4191 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 4192 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 4193 4194 skb_queue_head_init(&rtwdev->c2h_queue); 4195 rtw89_core_ppdu_sts_init(rtwdev); 4196 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 4197 4198 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 4199 rtwdev->dbcc_en = false; 4200 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 4201 4202 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 4203 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 4204 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 4205 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 4206 4207 init_completion(&rtwdev->fw.req.completion); 4208 4209 schedule_work(&rtwdev->load_firmware_work); 4210 4211 rtw89_ser_init(rtwdev); 4212 rtw89_entity_init(rtwdev); 4213 rtw89_tas_init(rtwdev); 4214 4215 return 0; 4216 } 4217 EXPORT_SYMBOL(rtw89_core_init); 4218 4219 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 4220 { 4221 rtw89_ser_deinit(rtwdev); 4222 rtw89_unload_firmware(rtwdev); 4223 rtw89_fw_free_all_early_h2c(rtwdev); 4224 4225 destroy_workqueue(rtwdev->txq_wq); 4226 mutex_destroy(&rtwdev->rf_mutex); 4227 mutex_destroy(&rtwdev->mutex); 4228 } 4229 EXPORT_SYMBOL(rtw89_core_deinit); 4230 4231 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4232 const u8 *mac_addr, bool hw_scan) 4233 { 4234 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4235 rtwvif->sub_entity_idx); 4236 4237 rtwdev->scanning = true; 4238 rtw89_leave_lps(rtwdev); 4239 if (hw_scan) 4240 rtw89_leave_ips_by_hwflags(rtwdev); 4241 4242 ether_addr_copy(rtwvif->mac_addr, mac_addr); 4243 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 4244 rtw89_chip_rfk_scan(rtwdev, true); 4245 rtw89_hci_recalc_int_mit(rtwdev); 4246 rtw89_phy_config_edcca(rtwdev, true); 4247 4248 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 4249 } 4250 4251 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4252 struct ieee80211_vif *vif, bool hw_scan) 4253 { 4254 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4255 4256 if (!rtwvif) 4257 return; 4258 4259 ether_addr_copy(rtwvif->mac_addr, vif->addr); 4260 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4261 4262 rtw89_chip_rfk_scan(rtwdev, false); 4263 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 4264 rtw89_phy_config_edcca(rtwdev, false); 4265 4266 rtwdev->scanning = false; 4267 rtwdev->dig.bypass_dig = true; 4268 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 4269 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 4270 } 4271 4272 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 4273 { 4274 const struct rtw89_chip_info *chip = rtwdev->chip; 4275 int ret; 4276 u8 val; 4277 u8 cv; 4278 4279 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 4280 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 4281 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 4282 cv = CHIP_CAV; 4283 else 4284 cv = CHIP_CBV; 4285 } 4286 4287 rtwdev->hal.cv = cv; 4288 4289 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) { 4290 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 4291 if (ret) 4292 return; 4293 4294 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 4295 } 4296 } 4297 4298 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 4299 { 4300 rtwdev->hal.support_cckpd = 4301 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 4302 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 4303 rtwdev->hal.support_igi = 4304 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 4305 } 4306 4307 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 4308 { 4309 const struct rtw89_chip_info *chip = rtwdev->chip; 4310 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 4311 struct rtw89_efuse *efuse = &rtwdev->efuse; 4312 const struct rtw89_rfe_parms *sel; 4313 u8 rfe_type = efuse->rfe_type; 4314 4315 if (!conf) { 4316 sel = chip->dflt_parms; 4317 goto out; 4318 } 4319 4320 while (conf->rfe_parms) { 4321 if (rfe_type == conf->rfe_type) { 4322 sel = conf->rfe_parms; 4323 goto out; 4324 } 4325 conf++; 4326 } 4327 4328 sel = chip->dflt_parms; 4329 4330 out: 4331 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 4332 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 4333 } 4334 4335 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 4336 { 4337 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4338 int ret; 4339 4340 ret = rtw89_mac_partial_init(rtwdev, false); 4341 if (ret) 4342 return ret; 4343 4344 ret = mac->parse_efuse_map(rtwdev); 4345 if (ret) 4346 return ret; 4347 4348 ret = mac->parse_phycap_map(rtwdev); 4349 if (ret) 4350 return ret; 4351 4352 ret = rtw89_mac_setup_phycap(rtwdev); 4353 if (ret) 4354 return ret; 4355 4356 rtw89_core_setup_phycap(rtwdev); 4357 4358 rtw89_hci_mac_pre_deinit(rtwdev); 4359 4360 rtw89_mac_pwr_off(rtwdev); 4361 4362 return 0; 4363 } 4364 4365 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 4366 { 4367 rtw89_chip_fem_setup(rtwdev); 4368 4369 return 0; 4370 } 4371 4372 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 4373 { 4374 int ret; 4375 4376 rtw89_read_chip_ver(rtwdev); 4377 4378 ret = rtw89_wait_firmware_completion(rtwdev); 4379 if (ret) { 4380 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 4381 return ret; 4382 } 4383 4384 ret = rtw89_fw_recognize(rtwdev); 4385 if (ret) { 4386 rtw89_err(rtwdev, "failed to recognize firmware\n"); 4387 return ret; 4388 } 4389 4390 ret = rtw89_chip_efuse_info_setup(rtwdev); 4391 if (ret) 4392 return ret; 4393 4394 ret = rtw89_fw_recognize_elements(rtwdev); 4395 if (ret) { 4396 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 4397 return ret; 4398 } 4399 4400 ret = rtw89_chip_board_info_setup(rtwdev); 4401 if (ret) 4402 return ret; 4403 4404 rtw89_core_setup_rfe_parms(rtwdev); 4405 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 4406 4407 return 0; 4408 } 4409 EXPORT_SYMBOL(rtw89_chip_info_setup); 4410 4411 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 4412 { 4413 const struct rtw89_chip_info *chip = rtwdev->chip; 4414 struct ieee80211_hw *hw = rtwdev->hw; 4415 struct rtw89_efuse *efuse = &rtwdev->efuse; 4416 struct rtw89_hal *hal = &rtwdev->hal; 4417 int ret; 4418 int tx_headroom = IEEE80211_HT_CTL_LEN; 4419 4420 hw->vif_data_size = sizeof(struct rtw89_vif); 4421 hw->sta_data_size = sizeof(struct rtw89_sta); 4422 hw->txq_data_size = sizeof(struct rtw89_txq); 4423 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 4424 4425 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 4426 4427 hw->extra_tx_headroom = tx_headroom; 4428 hw->queues = IEEE80211_NUM_ACS; 4429 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 4430 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 4431 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 4432 4433 ieee80211_hw_set(hw, SIGNAL_DBM); 4434 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 4435 ieee80211_hw_set(hw, MFP_CAPABLE); 4436 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 4437 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 4438 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 4439 ieee80211_hw_set(hw, TX_AMSDU); 4440 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 4441 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 4442 ieee80211_hw_set(hw, SUPPORTS_PS); 4443 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 4444 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 4445 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 4446 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 4447 4448 /* ref: description of rtw89_mcc_get_tbtt_ofst() in chan.c */ 4449 ieee80211_hw_set(hw, TIMING_BEACON_ONLY); 4450 4451 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4452 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 4453 4454 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 4455 ieee80211_hw_set(hw, CONNECTION_MONITOR); 4456 4457 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 4458 BIT(NL80211_IFTYPE_AP) | 4459 BIT(NL80211_IFTYPE_P2P_CLIENT) | 4460 BIT(NL80211_IFTYPE_P2P_GO); 4461 4462 if (hal->ant_diversity) { 4463 hw->wiphy->available_antennas_tx = 0x3; 4464 hw->wiphy->available_antennas_rx = 0x3; 4465 } else { 4466 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 4467 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 4468 } 4469 4470 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 4471 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 4472 WIPHY_FLAG_AP_UAPSD | WIPHY_FLAG_SPLIT_SCAN_6GHZ; 4473 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 4474 4475 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 4476 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 4477 4478 #ifdef CONFIG_PM 4479 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 4480 #endif 4481 4482 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4483 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4484 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4485 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4486 hw->wiphy->max_remain_on_channel_duration = 1000; 4487 4488 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 4489 4490 ret = rtw89_core_set_supported_band(rtwdev); 4491 if (ret) { 4492 rtw89_err(rtwdev, "failed to set supported band\n"); 4493 return ret; 4494 } 4495 4496 ret = rtw89_regd_setup(rtwdev); 4497 if (ret) { 4498 rtw89_err(rtwdev, "failed to set up regd\n"); 4499 goto err_free_supported_band; 4500 } 4501 4502 hw->wiphy->sar_capa = &rtw89_sar_capa; 4503 4504 ret = ieee80211_register_hw(hw); 4505 if (ret) { 4506 rtw89_err(rtwdev, "failed to register hw\n"); 4507 goto err_free_supported_band; 4508 } 4509 4510 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 4511 if (ret) { 4512 rtw89_err(rtwdev, "failed to init regd\n"); 4513 goto err_unregister_hw; 4514 } 4515 4516 return 0; 4517 4518 err_unregister_hw: 4519 ieee80211_unregister_hw(hw); 4520 err_free_supported_band: 4521 rtw89_core_clr_supported_band(rtwdev); 4522 4523 return ret; 4524 } 4525 4526 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 4527 { 4528 struct ieee80211_hw *hw = rtwdev->hw; 4529 4530 ieee80211_unregister_hw(hw); 4531 rtw89_core_clr_supported_band(rtwdev); 4532 } 4533 4534 int rtw89_core_register(struct rtw89_dev *rtwdev) 4535 { 4536 int ret; 4537 4538 ret = rtw89_core_register_hw(rtwdev); 4539 if (ret) { 4540 rtw89_err(rtwdev, "failed to register core hw\n"); 4541 return ret; 4542 } 4543 4544 rtw89_debugfs_init(rtwdev); 4545 4546 return 0; 4547 } 4548 EXPORT_SYMBOL(rtw89_core_register); 4549 4550 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 4551 { 4552 rtw89_core_unregister_hw(rtwdev); 4553 } 4554 EXPORT_SYMBOL(rtw89_core_unregister); 4555 4556 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4557 u32 bus_data_size, 4558 const struct rtw89_chip_info *chip) 4559 { 4560 struct rtw89_fw_info early_fw = {}; 4561 const struct firmware *firmware; 4562 struct ieee80211_hw *hw; 4563 struct rtw89_dev *rtwdev; 4564 struct ieee80211_ops *ops; 4565 u32 driver_data_size; 4566 int fw_format = -1; 4567 bool no_chanctx; 4568 4569 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 4570 4571 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 4572 if (!ops) 4573 goto err; 4574 4575 no_chanctx = chip->support_chanctx_num == 0 || 4576 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 4577 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 4578 4579 if (no_chanctx) { 4580 ops->add_chanctx = NULL; 4581 ops->remove_chanctx = NULL; 4582 ops->change_chanctx = NULL; 4583 ops->assign_vif_chanctx = NULL; 4584 ops->unassign_vif_chanctx = NULL; 4585 ops->remain_on_channel = NULL; 4586 ops->cancel_remain_on_channel = NULL; 4587 } 4588 4589 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 4590 hw = ieee80211_alloc_hw(driver_data_size, ops); 4591 if (!hw) 4592 goto err; 4593 4594 hw->wiphy->iface_combinations = rtw89_iface_combs; 4595 4596 if (no_chanctx || chip->support_chanctx_num == 1) 4597 hw->wiphy->n_iface_combinations = 1; 4598 else 4599 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 4600 4601 rtwdev = hw->priv; 4602 rtwdev->hw = hw; 4603 rtwdev->dev = device; 4604 rtwdev->ops = ops; 4605 rtwdev->chip = chip; 4606 rtwdev->fw.req.firmware = firmware; 4607 rtwdev->fw.fw_format = fw_format; 4608 4609 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 4610 no_chanctx ? "without" : "with"); 4611 4612 return rtwdev; 4613 4614 err: 4615 kfree(ops); 4616 release_firmware(firmware); 4617 return NULL; 4618 } 4619 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 4620 4621 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 4622 { 4623 kfree(rtwdev->ops); 4624 kfree(rtwdev->rfe_data); 4625 release_firmware(rtwdev->fw.req.firmware); 4626 ieee80211_free_hw(rtwdev->hw); 4627 } 4628 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 4629 4630 MODULE_AUTHOR("Realtek Corporation"); 4631 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 4632 MODULE_LICENSE("Dual BSD/GPL"); 4633