1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 #include "wow.h" 22 23 static bool rtw89_disable_ps_mode; 24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 26 27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 37 38 static struct ieee80211_channel rtw89_channels_2ghz[] = { 39 RTW89_DEF_CHAN_2G(2412, 1), 40 RTW89_DEF_CHAN_2G(2417, 2), 41 RTW89_DEF_CHAN_2G(2422, 3), 42 RTW89_DEF_CHAN_2G(2427, 4), 43 RTW89_DEF_CHAN_2G(2432, 5), 44 RTW89_DEF_CHAN_2G(2437, 6), 45 RTW89_DEF_CHAN_2G(2442, 7), 46 RTW89_DEF_CHAN_2G(2447, 8), 47 RTW89_DEF_CHAN_2G(2452, 9), 48 RTW89_DEF_CHAN_2G(2457, 10), 49 RTW89_DEF_CHAN_2G(2462, 11), 50 RTW89_DEF_CHAN_2G(2467, 12), 51 RTW89_DEF_CHAN_2G(2472, 13), 52 RTW89_DEF_CHAN_2G(2484, 14), 53 }; 54 55 static struct ieee80211_channel rtw89_channels_5ghz[] = { 56 RTW89_DEF_CHAN_5G(5180, 36), 57 RTW89_DEF_CHAN_5G(5200, 40), 58 RTW89_DEF_CHAN_5G(5220, 44), 59 RTW89_DEF_CHAN_5G(5240, 48), 60 RTW89_DEF_CHAN_5G(5260, 52), 61 RTW89_DEF_CHAN_5G(5280, 56), 62 RTW89_DEF_CHAN_5G(5300, 60), 63 RTW89_DEF_CHAN_5G(5320, 64), 64 RTW89_DEF_CHAN_5G(5500, 100), 65 RTW89_DEF_CHAN_5G(5520, 104), 66 RTW89_DEF_CHAN_5G(5540, 108), 67 RTW89_DEF_CHAN_5G(5560, 112), 68 RTW89_DEF_CHAN_5G(5580, 116), 69 RTW89_DEF_CHAN_5G(5600, 120), 70 RTW89_DEF_CHAN_5G(5620, 124), 71 RTW89_DEF_CHAN_5G(5640, 128), 72 RTW89_DEF_CHAN_5G(5660, 132), 73 RTW89_DEF_CHAN_5G(5680, 136), 74 RTW89_DEF_CHAN_5G(5700, 140), 75 RTW89_DEF_CHAN_5G(5720, 144), 76 RTW89_DEF_CHAN_5G(5745, 149), 77 RTW89_DEF_CHAN_5G(5765, 153), 78 RTW89_DEF_CHAN_5G(5785, 157), 79 RTW89_DEF_CHAN_5G(5805, 161), 80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 81 RTW89_DEF_CHAN_5G(5845, 169), 82 RTW89_DEF_CHAN_5G(5865, 173), 83 RTW89_DEF_CHAN_5G(5885, 177), 84 }; 85 86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 87 ARRAY_SIZE(rtw89_channels_5ghz)); 88 89 static struct ieee80211_channel rtw89_channels_6ghz[] = { 90 RTW89_DEF_CHAN_6G(5955, 1), 91 RTW89_DEF_CHAN_6G(5975, 5), 92 RTW89_DEF_CHAN_6G(5995, 9), 93 RTW89_DEF_CHAN_6G(6015, 13), 94 RTW89_DEF_CHAN_6G(6035, 17), 95 RTW89_DEF_CHAN_6G(6055, 21), 96 RTW89_DEF_CHAN_6G(6075, 25), 97 RTW89_DEF_CHAN_6G(6095, 29), 98 RTW89_DEF_CHAN_6G(6115, 33), 99 RTW89_DEF_CHAN_6G(6135, 37), 100 RTW89_DEF_CHAN_6G(6155, 41), 101 RTW89_DEF_CHAN_6G(6175, 45), 102 RTW89_DEF_CHAN_6G(6195, 49), 103 RTW89_DEF_CHAN_6G(6215, 53), 104 RTW89_DEF_CHAN_6G(6235, 57), 105 RTW89_DEF_CHAN_6G(6255, 61), 106 RTW89_DEF_CHAN_6G(6275, 65), 107 RTW89_DEF_CHAN_6G(6295, 69), 108 RTW89_DEF_CHAN_6G(6315, 73), 109 RTW89_DEF_CHAN_6G(6335, 77), 110 RTW89_DEF_CHAN_6G(6355, 81), 111 RTW89_DEF_CHAN_6G(6375, 85), 112 RTW89_DEF_CHAN_6G(6395, 89), 113 RTW89_DEF_CHAN_6G(6415, 93), 114 RTW89_DEF_CHAN_6G(6435, 97), 115 RTW89_DEF_CHAN_6G(6455, 101), 116 RTW89_DEF_CHAN_6G(6475, 105), 117 RTW89_DEF_CHAN_6G(6495, 109), 118 RTW89_DEF_CHAN_6G(6515, 113), 119 RTW89_DEF_CHAN_6G(6535, 117), 120 RTW89_DEF_CHAN_6G(6555, 121), 121 RTW89_DEF_CHAN_6G(6575, 125), 122 RTW89_DEF_CHAN_6G(6595, 129), 123 RTW89_DEF_CHAN_6G(6615, 133), 124 RTW89_DEF_CHAN_6G(6635, 137), 125 RTW89_DEF_CHAN_6G(6655, 141), 126 RTW89_DEF_CHAN_6G(6675, 145), 127 RTW89_DEF_CHAN_6G(6695, 149), 128 RTW89_DEF_CHAN_6G(6715, 153), 129 RTW89_DEF_CHAN_6G(6735, 157), 130 RTW89_DEF_CHAN_6G(6755, 161), 131 RTW89_DEF_CHAN_6G(6775, 165), 132 RTW89_DEF_CHAN_6G(6795, 169), 133 RTW89_DEF_CHAN_6G(6815, 173), 134 RTW89_DEF_CHAN_6G(6835, 177), 135 RTW89_DEF_CHAN_6G(6855, 181), 136 RTW89_DEF_CHAN_6G(6875, 185), 137 RTW89_DEF_CHAN_6G(6895, 189), 138 RTW89_DEF_CHAN_6G(6915, 193), 139 RTW89_DEF_CHAN_6G(6935, 197), 140 RTW89_DEF_CHAN_6G(6955, 201), 141 RTW89_DEF_CHAN_6G(6975, 205), 142 RTW89_DEF_CHAN_6G(6995, 209), 143 RTW89_DEF_CHAN_6G(7015, 213), 144 RTW89_DEF_CHAN_6G(7035, 217), 145 RTW89_DEF_CHAN_6G(7055, 221), 146 RTW89_DEF_CHAN_6G(7075, 225), 147 RTW89_DEF_CHAN_6G(7095, 229), 148 RTW89_DEF_CHAN_6G(7115, 233), 149 }; 150 151 static struct ieee80211_rate rtw89_bitrates[] = { 152 { .bitrate = 10, .hw_value = 0x00, }, 153 { .bitrate = 20, .hw_value = 0x01, }, 154 { .bitrate = 55, .hw_value = 0x02, }, 155 { .bitrate = 110, .hw_value = 0x03, }, 156 { .bitrate = 60, .hw_value = 0x04, }, 157 { .bitrate = 90, .hw_value = 0x05, }, 158 { .bitrate = 120, .hw_value = 0x06, }, 159 { .bitrate = 180, .hw_value = 0x07, }, 160 { .bitrate = 240, .hw_value = 0x08, }, 161 { .bitrate = 360, .hw_value = 0x09, }, 162 { .bitrate = 480, .hw_value = 0x0a, }, 163 { .bitrate = 540, .hw_value = 0x0b, }, 164 }; 165 166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_STATION), 170 }, 171 { 172 .max = 1, 173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 174 BIT(NL80211_IFTYPE_P2P_GO) | 175 BIT(NL80211_IFTYPE_AP), 176 }, 177 }; 178 179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_STATION), 183 }, 184 { 185 .max = 1, 186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 187 BIT(NL80211_IFTYPE_P2P_GO), 188 }, 189 }; 190 191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 192 { 193 .limits = rtw89_iface_limits, 194 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 195 .max_interfaces = 2, 196 .num_different_channels = 1, 197 }, 198 { 199 .limits = rtw89_iface_limits_mcc, 200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 201 .max_interfaces = 2, 202 .num_different_channels = 2, 203 }, 204 }; 205 206 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 207 { 208 struct ieee80211_rate rate; 209 210 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 211 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 212 return false; 213 } 214 215 rate = rtw89_bitrates[rpt_rate]; 216 *bitrate = rate.bitrate; 217 218 return true; 219 } 220 221 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 222 .band = NL80211_BAND_2GHZ, 223 .channels = rtw89_channels_2ghz, 224 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 225 .bitrates = rtw89_bitrates, 226 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 227 .ht_cap = {0}, 228 .vht_cap = {0}, 229 }; 230 231 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 232 .band = NL80211_BAND_5GHZ, 233 .channels = rtw89_channels_5ghz, 234 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 235 236 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 237 .bitrates = rtw89_bitrates + 4, 238 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 239 .ht_cap = {0}, 240 .vht_cap = {0}, 241 }; 242 243 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 244 .band = NL80211_BAND_6GHZ, 245 .channels = rtw89_channels_6ghz, 246 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 247 248 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 249 .bitrates = rtw89_bitrates + 4, 250 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 251 }; 252 253 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 254 struct rtw89_traffic_stats *stats, 255 struct sk_buff *skb, bool tx) 256 { 257 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 258 259 if (tx && ieee80211_is_assoc_req(hdr->frame_control)) 260 rtw89_wow_parse_akm(rtwdev, skb); 261 262 if (!ieee80211_is_data(hdr->frame_control)) 263 return; 264 265 if (is_broadcast_ether_addr(hdr->addr1) || 266 is_multicast_ether_addr(hdr->addr1)) 267 return; 268 269 if (tx) { 270 stats->tx_cnt++; 271 stats->tx_unicast += skb->len; 272 } else { 273 stats->rx_cnt++; 274 stats->rx_unicast += skb->len; 275 } 276 } 277 278 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 279 { 280 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 281 NL80211_CHAN_NO_HT); 282 } 283 284 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 285 struct rtw89_chan *chan) 286 { 287 struct ieee80211_channel *channel = chandef->chan; 288 enum nl80211_chan_width width = chandef->width; 289 u32 primary_freq, center_freq; 290 u8 center_chan; 291 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 292 u32 offset; 293 u8 band; 294 295 center_chan = channel->hw_value; 296 primary_freq = channel->center_freq; 297 center_freq = chandef->center_freq1; 298 299 switch (width) { 300 case NL80211_CHAN_WIDTH_20_NOHT: 301 case NL80211_CHAN_WIDTH_20: 302 bandwidth = RTW89_CHANNEL_WIDTH_20; 303 break; 304 case NL80211_CHAN_WIDTH_40: 305 bandwidth = RTW89_CHANNEL_WIDTH_40; 306 if (primary_freq > center_freq) { 307 center_chan -= 2; 308 } else { 309 center_chan += 2; 310 } 311 break; 312 case NL80211_CHAN_WIDTH_80: 313 case NL80211_CHAN_WIDTH_160: 314 bandwidth = nl_to_rtw89_bandwidth(width); 315 if (primary_freq > center_freq) { 316 offset = (primary_freq - center_freq - 10) / 20; 317 center_chan -= 2 + offset * 4; 318 } else { 319 offset = (center_freq - primary_freq - 10) / 20; 320 center_chan += 2 + offset * 4; 321 } 322 break; 323 default: 324 center_chan = 0; 325 break; 326 } 327 328 switch (channel->band) { 329 default: 330 case NL80211_BAND_2GHZ: 331 band = RTW89_BAND_2G; 332 break; 333 case NL80211_BAND_5GHZ: 334 band = RTW89_BAND_5G; 335 break; 336 case NL80211_BAND_6GHZ: 337 band = RTW89_BAND_6G; 338 break; 339 } 340 341 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 342 } 343 344 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 345 { 346 struct rtw89_hal *hal = &rtwdev->hal; 347 const struct rtw89_chip_info *chip = rtwdev->chip; 348 const struct rtw89_chan *chan; 349 enum rtw89_sub_entity_idx sub_entity_idx; 350 enum rtw89_sub_entity_idx roc_idx; 351 enum rtw89_phy_idx phy_idx; 352 enum rtw89_entity_mode mode; 353 bool entity_active; 354 355 entity_active = rtw89_get_entity_state(rtwdev); 356 if (!entity_active) 357 return; 358 359 mode = rtw89_get_entity_mode(rtwdev); 360 switch (mode) { 361 case RTW89_ENTITY_MODE_SCC: 362 case RTW89_ENTITY_MODE_MCC: 363 sub_entity_idx = RTW89_SUB_ENTITY_0; 364 break; 365 case RTW89_ENTITY_MODE_MCC_PREPARE: 366 sub_entity_idx = RTW89_SUB_ENTITY_1; 367 break; 368 default: 369 WARN(1, "Invalid ent mode: %d\n", mode); 370 return; 371 } 372 373 roc_idx = atomic_read(&hal->roc_entity_idx); 374 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 375 sub_entity_idx = roc_idx; 376 377 phy_idx = RTW89_PHY_0; 378 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 379 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 380 } 381 382 int rtw89_set_channel(struct rtw89_dev *rtwdev) 383 { 384 struct rtw89_hal *hal = &rtwdev->hal; 385 const struct rtw89_chip_info *chip = rtwdev->chip; 386 const struct rtw89_chan_rcd *chan_rcd; 387 const struct rtw89_chan *chan; 388 enum rtw89_sub_entity_idx sub_entity_idx; 389 enum rtw89_sub_entity_idx roc_idx; 390 enum rtw89_mac_idx mac_idx; 391 enum rtw89_phy_idx phy_idx; 392 struct rtw89_channel_help_params bak; 393 enum rtw89_entity_mode mode; 394 bool entity_active; 395 396 entity_active = rtw89_get_entity_state(rtwdev); 397 398 mode = rtw89_entity_recalc(rtwdev); 399 switch (mode) { 400 case RTW89_ENTITY_MODE_SCC: 401 case RTW89_ENTITY_MODE_MCC: 402 sub_entity_idx = RTW89_SUB_ENTITY_0; 403 break; 404 case RTW89_ENTITY_MODE_MCC_PREPARE: 405 sub_entity_idx = RTW89_SUB_ENTITY_1; 406 break; 407 default: 408 WARN(1, "Invalid ent mode: %d\n", mode); 409 return -EINVAL; 410 } 411 412 roc_idx = atomic_read(&hal->roc_entity_idx); 413 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 414 sub_entity_idx = roc_idx; 415 416 mac_idx = RTW89_MAC_0; 417 phy_idx = RTW89_PHY_0; 418 419 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 420 chan_rcd = rtw89_chan_rcd_get(rtwdev, sub_entity_idx); 421 422 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 423 424 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 425 426 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 427 428 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 429 430 if (!entity_active || chan_rcd->band_changed) { 431 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 432 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 433 } 434 435 rtw89_set_entity_state(rtwdev, true); 436 return 0; 437 } 438 439 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 440 struct rtw89_chan *chan) 441 { 442 const struct cfg80211_chan_def *chandef; 443 444 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx); 445 rtw89_get_channel_params(chandef, chan); 446 } 447 448 static enum rtw89_core_tx_type 449 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 450 struct sk_buff *skb) 451 { 452 struct ieee80211_hdr *hdr = (void *)skb->data; 453 __le16 fc = hdr->frame_control; 454 455 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 456 return RTW89_CORE_TX_TYPE_MGMT; 457 458 return RTW89_CORE_TX_TYPE_DATA; 459 } 460 461 static void 462 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 463 struct rtw89_core_tx_request *tx_req, 464 enum btc_pkt_type pkt_type) 465 { 466 struct ieee80211_sta *sta = tx_req->sta; 467 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 468 struct sk_buff *skb = tx_req->skb; 469 struct rtw89_sta *rtwsta; 470 u8 ampdu_num; 471 u8 tid; 472 473 if (pkt_type == PACKET_EAPOL) { 474 desc_info->bk = true; 475 return; 476 } 477 478 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 479 return; 480 481 if (!sta) { 482 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 483 return; 484 } 485 486 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 487 rtwsta = (struct rtw89_sta *)sta->drv_priv; 488 489 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 490 rtwsta->ampdu_params[tid].agg_num : 491 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 492 493 desc_info->agg_en = true; 494 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 495 desc_info->ampdu_num = ampdu_num; 496 } 497 498 static void 499 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 500 struct rtw89_core_tx_request *tx_req) 501 { 502 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 503 const struct rtw89_chip_info *chip = rtwdev->chip; 504 const struct rtw89_sec_cam_entry *sec_cam; 505 struct ieee80211_tx_info *info; 506 struct ieee80211_key_conf *key; 507 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 508 struct sk_buff *skb = tx_req->skb; 509 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 510 u8 sec_cam_idx; 511 u64 pn64; 512 513 info = IEEE80211_SKB_CB(skb); 514 key = info->control.hw_key; 515 sec_cam_idx = key->hw_key_idx; 516 sec_cam = cam_info->sec_entries[sec_cam_idx]; 517 if (!sec_cam) { 518 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 519 return; 520 } 521 522 switch (key->cipher) { 523 case WLAN_CIPHER_SUITE_WEP40: 524 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 525 break; 526 case WLAN_CIPHER_SUITE_WEP104: 527 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 528 break; 529 case WLAN_CIPHER_SUITE_TKIP: 530 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 531 break; 532 case WLAN_CIPHER_SUITE_CCMP: 533 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 534 break; 535 case WLAN_CIPHER_SUITE_CCMP_256: 536 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 537 break; 538 case WLAN_CIPHER_SUITE_GCMP: 539 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 540 break; 541 case WLAN_CIPHER_SUITE_GCMP_256: 542 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 543 break; 544 default: 545 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 546 return; 547 } 548 549 desc_info->sec_en = true; 550 desc_info->sec_keyid = key->keyidx; 551 desc_info->sec_type = sec_type; 552 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 553 554 if (!chip->hw_sec_hdr) 555 return; 556 557 pn64 = atomic64_inc_return(&key->tx_pn); 558 desc_info->sec_seq[0] = pn64; 559 desc_info->sec_seq[1] = pn64 >> 8; 560 desc_info->sec_seq[2] = pn64 >> 16; 561 desc_info->sec_seq[3] = pn64 >> 24; 562 desc_info->sec_seq[4] = pn64 >> 32; 563 desc_info->sec_seq[5] = pn64 >> 40; 564 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 565 } 566 567 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 568 struct rtw89_core_tx_request *tx_req, 569 const struct rtw89_chan *chan) 570 { 571 struct sk_buff *skb = tx_req->skb; 572 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 573 struct ieee80211_vif *vif = tx_info->control.vif; 574 u16 lowest_rate; 575 576 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 577 (vif && vif->p2p)) 578 lowest_rate = RTW89_HW_RATE_OFDM6; 579 else if (chan->band_type == RTW89_BAND_2G) 580 lowest_rate = RTW89_HW_RATE_CCK1; 581 else 582 lowest_rate = RTW89_HW_RATE_OFDM6; 583 584 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 585 return lowest_rate; 586 587 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 588 } 589 590 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 591 struct rtw89_core_tx_request *tx_req) 592 { 593 struct ieee80211_vif *vif = tx_req->vif; 594 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 595 struct ieee80211_sta *sta = tx_req->sta; 596 struct rtw89_sta *rtwsta; 597 598 if (!sta) 599 return rtwvif->mac_id; 600 601 rtwsta = (struct rtw89_sta *)sta->drv_priv; 602 return rtwsta->mac_id; 603 } 604 605 static void 606 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 607 struct rtw89_core_tx_request *tx_req) 608 { 609 struct ieee80211_vif *vif = tx_req->vif; 610 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 611 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 612 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 613 rtwvif->sub_entity_idx); 614 u8 qsel, ch_dma; 615 616 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 617 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 618 619 desc_info->qsel = qsel; 620 desc_info->ch_dma = ch_dma; 621 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 622 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 623 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 624 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 625 626 /* fixed data rate for mgmt frames */ 627 desc_info->en_wd_info = true; 628 desc_info->use_rate = true; 629 desc_info->dis_data_fb = true; 630 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 631 632 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 633 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 634 desc_info->data_rate, chan->channel, chan->band_type, 635 chan->band_width); 636 } 637 638 static void 639 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 640 struct rtw89_core_tx_request *tx_req) 641 { 642 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 643 644 desc_info->is_bmc = false; 645 desc_info->wd_page = false; 646 desc_info->ch_dma = RTW89_DMA_H2C; 647 } 648 649 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 650 const struct rtw89_chan *chan) 651 { 652 static const u8 rtw89_bandwidth_to_om[] = { 653 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 654 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 655 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 656 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 657 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 658 }; 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 struct rtw89_hal *hal = &rtwdev->hal; 661 u8 om_bandwidth; 662 663 if (!chip->dis_2g_40m_ul_ofdma || 664 chan->band_type != RTW89_BAND_2G || 665 chan->band_width != RTW89_CHANNEL_WIDTH_40) 666 return; 667 668 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 669 rtw89_bandwidth_to_om[chan->band_width] : 0; 670 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 671 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 672 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 673 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 674 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 675 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 676 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 677 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 678 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 679 } 680 681 static bool 682 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 683 struct rtw89_core_tx_request *tx_req, 684 enum btc_pkt_type pkt_type) 685 { 686 struct ieee80211_sta *sta = tx_req->sta; 687 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 688 struct sk_buff *skb = tx_req->skb; 689 struct ieee80211_hdr *hdr = (void *)skb->data; 690 __le16 fc = hdr->frame_control; 691 692 /* AP IOT issue with EAPoL, ARP and DHCP */ 693 if (pkt_type < PACKET_MAX) 694 return false; 695 696 if (!sta || !sta->deflink.he_cap.has_he) 697 return false; 698 699 if (!ieee80211_is_data_qos(fc)) 700 return false; 701 702 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 703 return false; 704 705 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 706 return false; 707 708 return true; 709 } 710 711 static void 712 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 713 struct rtw89_core_tx_request *tx_req) 714 { 715 struct ieee80211_sta *sta = tx_req->sta; 716 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 717 struct sk_buff *skb = tx_req->skb; 718 struct ieee80211_hdr *hdr = (void *)skb->data; 719 __le16 fc = hdr->frame_control; 720 void *data; 721 __le32 *htc; 722 u8 *qc; 723 int hdr_len; 724 725 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 726 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 727 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 728 729 hdr = data; 730 htc = data + hdr_len; 731 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 732 *htc = rtwsta->htc_template ? rtwsta->htc_template : 733 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 734 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 735 736 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 737 qc[0] |= IEEE80211_QOS_CTL_EOSP; 738 } 739 740 static void 741 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 742 struct rtw89_core_tx_request *tx_req, 743 enum btc_pkt_type pkt_type) 744 { 745 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 746 struct ieee80211_vif *vif = tx_req->vif; 747 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 748 749 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 750 goto desc_bk; 751 752 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 753 754 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 755 desc_info->a_ctrl_bsr = true; 756 757 desc_bk: 758 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 759 return; 760 761 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 762 desc_info->bk = true; 763 } 764 765 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 766 struct rtw89_core_tx_request *tx_req) 767 { 768 struct ieee80211_vif *vif = tx_req->vif; 769 struct ieee80211_sta *sta = tx_req->sta; 770 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 771 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 772 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx; 773 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 774 u16 lowest_rate; 775 776 if (rate_pattern->enable) 777 return rate_pattern->rate; 778 779 if (vif->p2p) 780 lowest_rate = RTW89_HW_RATE_OFDM6; 781 else if (chan->band_type == RTW89_BAND_2G) 782 lowest_rate = RTW89_HW_RATE_CCK1; 783 else 784 lowest_rate = RTW89_HW_RATE_OFDM6; 785 786 if (!sta || !sta->deflink.supp_rates[chan->band_type]) 787 return lowest_rate; 788 789 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate; 790 } 791 792 static void 793 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 794 struct rtw89_core_tx_request *tx_req) 795 { 796 struct ieee80211_vif *vif = tx_req->vif; 797 struct ieee80211_sta *sta = tx_req->sta; 798 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 799 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 800 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 801 struct sk_buff *skb = tx_req->skb; 802 u8 tid, tid_indicate; 803 u8 qsel, ch_dma; 804 805 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 806 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 807 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 808 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 809 810 desc_info->ch_dma = ch_dma; 811 desc_info->tid_indicate = tid_indicate; 812 desc_info->qsel = qsel; 813 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 814 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 815 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 816 desc_info->stbc = rtwsta ? rtwsta->ra.stbc_cap : false; 817 desc_info->ldpc = rtwsta ? rtwsta->ra.ldpc_cap : false; 818 819 /* enable wd_info for AMPDU */ 820 desc_info->en_wd_info = true; 821 822 if (IEEE80211_SKB_CB(skb)->control.hw_key) 823 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 824 825 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 826 } 827 828 static enum btc_pkt_type 829 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 830 struct rtw89_core_tx_request *tx_req) 831 { 832 struct sk_buff *skb = tx_req->skb; 833 struct udphdr *udphdr; 834 835 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 836 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 837 return PACKET_EAPOL; 838 } 839 840 if (skb->protocol == htons(ETH_P_ARP)) { 841 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 842 return PACKET_ARP; 843 } 844 845 if (skb->protocol == htons(ETH_P_IP) && 846 ip_hdr(skb)->protocol == IPPROTO_UDP) { 847 udphdr = udp_hdr(skb); 848 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 849 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 850 skb->len > 282) { 851 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 852 return PACKET_DHCP; 853 } 854 } 855 856 if (skb->protocol == htons(ETH_P_IP) && 857 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 858 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 859 return PACKET_ICMP; 860 } 861 862 return PACKET_MAX; 863 } 864 865 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 866 struct rtw89_tx_desc_info *desc_info, 867 struct sk_buff *skb) 868 { 869 struct ieee80211_hdr *hdr = (void *)skb->data; 870 __le16 fc = hdr->frame_control; 871 872 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 873 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 874 } 875 876 static void 877 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 878 struct rtw89_core_tx_request *tx_req) 879 { 880 const struct rtw89_chip_info *chip = rtwdev->chip; 881 882 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 883 return; 884 885 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 886 return; 887 888 if (chip->chip_id != RTL8852C && 889 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 890 return; 891 892 rtw89_mac_notify_wake(rtwdev); 893 } 894 895 static void 896 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 897 struct rtw89_core_tx_request *tx_req) 898 { 899 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 900 struct sk_buff *skb = tx_req->skb; 901 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 902 struct ieee80211_hdr *hdr = (void *)skb->data; 903 enum rtw89_core_tx_type tx_type; 904 enum btc_pkt_type pkt_type; 905 bool is_bmc; 906 u16 seq; 907 908 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 909 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 910 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 911 tx_req->tx_type = tx_type; 912 } 913 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 914 is_multicast_ether_addr(hdr->addr1)); 915 916 desc_info->seq = seq; 917 desc_info->pkt_size = skb->len; 918 desc_info->is_bmc = is_bmc; 919 desc_info->wd_page = true; 920 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 921 922 switch (tx_req->tx_type) { 923 case RTW89_CORE_TX_TYPE_MGMT: 924 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 925 break; 926 case RTW89_CORE_TX_TYPE_DATA: 927 rtw89_core_tx_update_data_info(rtwdev, tx_req); 928 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 929 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 930 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 931 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 932 break; 933 case RTW89_CORE_TX_TYPE_FWCMD: 934 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 935 break; 936 } 937 } 938 939 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 940 { 941 u8 ch_dma; 942 943 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 944 945 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 946 } 947 948 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 949 int qsel, unsigned int timeout) 950 { 951 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 952 struct rtw89_tx_wait_info *wait; 953 unsigned long time_left; 954 int ret = 0; 955 956 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 957 if (!wait) { 958 rtw89_core_tx_kick_off(rtwdev, qsel); 959 return 0; 960 } 961 962 init_completion(&wait->completion); 963 rcu_assign_pointer(skb_data->wait, wait); 964 965 rtw89_core_tx_kick_off(rtwdev, qsel); 966 time_left = wait_for_completion_timeout(&wait->completion, 967 msecs_to_jiffies(timeout)); 968 if (time_left == 0) 969 ret = -ETIMEDOUT; 970 else if (!wait->tx_done) 971 ret = -EAGAIN; 972 973 rcu_assign_pointer(skb_data->wait, NULL); 974 kfree_rcu(wait, rcu_head); 975 976 return ret; 977 } 978 979 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 980 struct sk_buff *skb, bool fwdl) 981 { 982 struct rtw89_core_tx_request tx_req = {0}; 983 u32 cnt; 984 int ret; 985 986 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 987 rtw89_debug(rtwdev, RTW89_DBG_FW, 988 "ignore h2c due to power is off with firmware state=%d\n", 989 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 990 dev_kfree_skb(skb); 991 return 0; 992 } 993 994 tx_req.skb = skb; 995 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 996 if (fwdl) 997 tx_req.desc_info.fw_dl = true; 998 999 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1000 1001 if (!fwdl) 1002 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1003 1004 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1005 if (cnt == 0) { 1006 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1007 return -ENOSPC; 1008 } 1009 1010 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1011 if (ret) { 1012 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1013 return ret; 1014 } 1015 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1016 1017 return 0; 1018 } 1019 1020 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1021 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1022 { 1023 struct rtw89_core_tx_request tx_req = {0}; 1024 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1025 int ret; 1026 1027 tx_req.skb = skb; 1028 tx_req.sta = sta; 1029 tx_req.vif = vif; 1030 1031 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1032 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1033 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1034 rtw89_core_tx_wake(rtwdev, &tx_req); 1035 1036 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1037 if (ret) { 1038 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1039 return ret; 1040 } 1041 1042 if (qsel) 1043 *qsel = tx_req.desc_info.qsel; 1044 1045 return 0; 1046 } 1047 1048 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1049 { 1050 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1051 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1052 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1053 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1054 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1055 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1056 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1057 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1058 1059 return cpu_to_le32(dword); 1060 } 1061 1062 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1063 { 1064 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1065 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1066 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1067 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1068 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1069 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1070 1071 return cpu_to_le32(dword); 1072 } 1073 1074 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1075 { 1076 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1077 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1078 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1079 1080 return cpu_to_le32(dword); 1081 } 1082 1083 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1084 { 1085 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1086 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1087 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1088 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1089 1090 return cpu_to_le32(dword); 1091 } 1092 1093 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1094 { 1095 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1096 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1097 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1098 1099 return cpu_to_le32(dword); 1100 } 1101 1102 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1103 { 1104 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1105 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1106 1107 return cpu_to_le32(dword); 1108 } 1109 1110 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1111 { 1112 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1113 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1114 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1115 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1116 1117 return cpu_to_le32(dword); 1118 } 1119 1120 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1121 { 1122 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1123 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1124 1125 return cpu_to_le32(dword); 1126 } 1127 1128 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1129 { 1130 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1131 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1132 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1133 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1134 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1135 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1136 1137 return cpu_to_le32(dword); 1138 } 1139 1140 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1141 { 1142 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1143 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1144 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1145 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1146 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1147 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1148 1149 return cpu_to_le32(dword); 1150 } 1151 1152 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1153 { 1154 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1155 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1156 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1157 desc_info->data_retry_lowest_rate); 1158 1159 return cpu_to_le32(dword); 1160 } 1161 1162 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1163 { 1164 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1165 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1166 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1167 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1168 1169 return cpu_to_le32(dword); 1170 } 1171 1172 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1173 { 1174 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1175 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1176 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1177 1178 return cpu_to_le32(dword); 1179 } 1180 1181 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1182 { 1183 bool rts_en = !desc_info->is_bmc; 1184 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1185 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1186 1187 return cpu_to_le32(dword); 1188 } 1189 1190 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1191 struct rtw89_tx_desc_info *desc_info, 1192 void *txdesc) 1193 { 1194 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1195 struct rtw89_txwd_info *txwd_info; 1196 1197 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1198 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1199 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1200 1201 if (!desc_info->en_wd_info) 1202 return; 1203 1204 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1205 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1206 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1207 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1208 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1209 1210 } 1211 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1212 1213 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1214 struct rtw89_tx_desc_info *desc_info, 1215 void *txdesc) 1216 { 1217 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1218 struct rtw89_txwd_info *txwd_info; 1219 1220 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1221 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1222 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1223 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1224 if (desc_info->sec_en) { 1225 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1226 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1227 } 1228 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1229 1230 if (!desc_info->en_wd_info) 1231 return; 1232 1233 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1234 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1235 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1236 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1237 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1238 } 1239 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1240 1241 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1242 { 1243 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1244 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1245 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1246 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1247 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1248 1249 return cpu_to_le32(dword); 1250 } 1251 1252 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1253 { 1254 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1255 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1256 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1257 1258 return cpu_to_le32(dword); 1259 } 1260 1261 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1262 { 1263 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1264 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1265 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1266 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1267 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1268 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1269 1270 return cpu_to_le32(dword); 1271 } 1272 1273 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1274 { 1275 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq); 1276 1277 return cpu_to_le32(dword); 1278 } 1279 1280 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1281 { 1282 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1283 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1284 1285 return cpu_to_le32(dword); 1286 } 1287 1288 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1289 { 1290 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1291 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1292 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1293 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1294 1295 return cpu_to_le32(dword); 1296 } 1297 1298 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1299 { 1300 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1301 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1302 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1303 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1304 1305 return cpu_to_le32(dword); 1306 } 1307 1308 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1309 { 1310 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1311 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1312 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1313 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1314 1315 return cpu_to_le32(dword); 1316 } 1317 1318 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1319 { 1320 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1321 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1322 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1323 desc_info->data_retry_lowest_rate); 1324 1325 return cpu_to_le32(dword); 1326 } 1327 1328 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1329 { 1330 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1331 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1332 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1333 1334 return cpu_to_le32(dword); 1335 } 1336 1337 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1338 { 1339 bool rts_en = !desc_info->is_bmc; 1340 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1341 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1342 1343 return cpu_to_le32(dword); 1344 } 1345 1346 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1347 struct rtw89_tx_desc_info *desc_info, 1348 void *txdesc) 1349 { 1350 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1351 struct rtw89_txwd_info_v2 *txwd_info; 1352 1353 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1354 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1355 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1356 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1357 if (desc_info->sec_en) { 1358 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1359 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1360 } 1361 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1362 1363 if (!desc_info->en_wd_info) 1364 return; 1365 1366 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1367 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1368 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1369 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1370 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1371 } 1372 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1373 1374 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1375 { 1376 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1377 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1378 RTW89_CORE_RX_TYPE_FWDL : 1379 RTW89_CORE_RX_TYPE_H2C); 1380 1381 return cpu_to_le32(dword); 1382 } 1383 1384 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1385 struct rtw89_tx_desc_info *desc_info, 1386 void *txdesc) 1387 { 1388 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1389 1390 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1391 } 1392 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1393 1394 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1395 { 1396 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1397 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1398 RTW89_CORE_RX_TYPE_FWDL : 1399 RTW89_CORE_RX_TYPE_H2C); 1400 1401 return cpu_to_le32(dword); 1402 } 1403 1404 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1405 struct rtw89_tx_desc_info *desc_info, 1406 void *txdesc) 1407 { 1408 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1409 1410 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1411 } 1412 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1413 1414 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1415 struct sk_buff *skb, 1416 struct rtw89_rx_phy_ppdu *phy_ppdu) 1417 { 1418 const struct rtw89_chip_info *chip = rtwdev->chip; 1419 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1420 const struct rtw89_rxinfo_user *user; 1421 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1422 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1423 bool rx_cnt_valid = false; 1424 bool invalid = false; 1425 u8 plcp_size = 0; 1426 u8 *phy_sts; 1427 u8 usr_num; 1428 int i; 1429 1430 if (chip_gen == RTW89_CHIP_BE) { 1431 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1432 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1433 } 1434 1435 if (invalid) 1436 return -EINVAL; 1437 1438 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1439 if (chip_gen == RTW89_CHIP_BE) { 1440 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1441 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1442 } else { 1443 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1444 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1445 } 1446 if (usr_num > chip->ppdu_max_usr) { 1447 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1448 usr_num); 1449 return -EINVAL; 1450 } 1451 1452 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set by hardware, 1453 * so update mac_id by rxinfo_user[].mac_id. 1454 */ 1455 for (i = 0; i < usr_num && chip_gen == RTW89_CHIP_BE; i++) { 1456 user = &rxinfo->user[i]; 1457 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1458 continue; 1459 1460 phy_ppdu->mac_id = 1461 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1462 break; 1463 } 1464 1465 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1466 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1467 /* 8-byte alignment */ 1468 if (usr_num & BIT(0)) 1469 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1470 if (rx_cnt_valid) 1471 phy_sts += rx_cnt_size; 1472 phy_sts += plcp_size; 1473 1474 if (phy_sts > skb->data + skb->len) 1475 return -EINVAL; 1476 1477 phy_ppdu->buf = phy_sts; 1478 phy_ppdu->len = skb->data + skb->len - phy_sts; 1479 1480 return 0; 1481 } 1482 1483 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1484 struct ieee80211_sta *sta) 1485 { 1486 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1487 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1488 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1489 struct rtw89_hal *hal = &rtwdev->hal; 1490 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1491 u8 ant_pos = U8_MAX; 1492 u8 evm_pos = 0; 1493 int i; 1494 1495 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1496 return; 1497 1498 if (hal->ant_diversity && hal->antenna_rx) { 1499 ant_pos = __ffs(hal->antenna_rx); 1500 evm_pos = ant_pos; 1501 } 1502 1503 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1504 1505 if (ant_pos < ant_num) { 1506 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]); 1507 } else { 1508 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1509 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1510 } 1511 1512 if (phy_ppdu->ofdm.has) { 1513 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr); 1514 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min); 1515 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max); 1516 } 1517 } 1518 1519 #define VAR_LEN 0xff 1520 #define VAR_LEN_UNIT 8 1521 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1522 const struct rtw89_phy_sts_iehdr *iehdr) 1523 { 1524 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1525 [RTW89_CHIP_AX] = { 1526 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1527 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1528 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1529 }, 1530 [RTW89_CHIP_BE] = { 1531 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1532 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1533 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1534 }, 1535 }; 1536 const u8 *physts_ie_len_tab; 1537 u16 ie_len; 1538 u8 ie; 1539 1540 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1541 1542 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1543 if (physts_ie_len_tab[ie] != VAR_LEN) 1544 ie_len = physts_ie_len_tab[ie]; 1545 else 1546 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1547 1548 return ie_len; 1549 } 1550 1551 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1552 const struct rtw89_phy_sts_iehdr *iehdr, 1553 struct rtw89_rx_phy_ppdu *phy_ppdu) 1554 { 1555 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr; 1556 s16 cfo; 1557 u32 t; 1558 1559 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1560 1561 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1562 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1563 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1564 } 1565 1566 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1567 return; 1568 1569 if (!phy_ppdu->to_self) 1570 return; 1571 1572 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1573 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1574 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1575 phy_ppdu->ofdm.has = true; 1576 1577 /* sign conversion for S(12,2) */ 1578 if (rtwdev->chip->cfo_src_fd) { 1579 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1580 cfo = sign_extend32(t, 11); 1581 } else { 1582 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1583 cfo = sign_extend32(t, 11); 1584 } 1585 1586 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1587 } 1588 1589 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1590 const struct rtw89_phy_sts_iehdr *iehdr, 1591 struct rtw89_rx_phy_ppdu *phy_ppdu) 1592 { 1593 u8 ie; 1594 1595 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1596 1597 switch (ie) { 1598 case RTW89_PHYSTS_IE01_CMN_OFDM: 1599 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1600 break; 1601 default: 1602 break; 1603 } 1604 1605 return 0; 1606 } 1607 1608 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1609 { 1610 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1611 u8 *rssi = phy_ppdu->rssi; 1612 1613 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1614 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1615 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1616 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1617 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1618 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1619 } 1620 1621 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1622 struct rtw89_rx_phy_ppdu *phy_ppdu) 1623 { 1624 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1625 u32 len_from_header; 1626 bool physts_valid; 1627 1628 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1629 if (!physts_valid) 1630 return -EINVAL; 1631 1632 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1633 1634 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1635 len_from_header += PHY_STS_HDR_LEN; 1636 1637 if (len_from_header != phy_ppdu->len) { 1638 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1639 return -EINVAL; 1640 } 1641 rtw89_core_update_phy_ppdu(phy_ppdu); 1642 1643 return 0; 1644 } 1645 1646 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1647 struct rtw89_rx_phy_ppdu *phy_ppdu) 1648 { 1649 u16 ie_len; 1650 void *pos, *end; 1651 1652 /* mark invalid reports and bypass them */ 1653 if (phy_ppdu->ie < RTW89_CCK_PKT) 1654 return -EINVAL; 1655 1656 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1657 end = phy_ppdu->buf + phy_ppdu->len; 1658 while (pos < end) { 1659 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1660 1661 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1662 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1663 pos += ie_len; 1664 if (pos > end || ie_len == 0) { 1665 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1666 "phy status parse failed\n"); 1667 return -EINVAL; 1668 } 1669 } 1670 1671 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1672 1673 return 0; 1674 } 1675 1676 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1677 struct rtw89_rx_phy_ppdu *phy_ppdu) 1678 { 1679 int ret; 1680 1681 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1682 if (ret) 1683 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1684 else 1685 phy_ppdu->valid = true; 1686 1687 ieee80211_iterate_stations_atomic(rtwdev->hw, 1688 rtw89_core_rx_process_phy_ppdu_iter, 1689 phy_ppdu); 1690 } 1691 1692 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 1693 u8 desc_info_gi, 1694 bool rx_status, bool eht) 1695 { 1696 switch (desc_info_gi) { 1697 case RTW89_GILTF_SGI_4XHE08: 1698 case RTW89_GILTF_2XHE08: 1699 case RTW89_GILTF_1XHE08: 1700 return eht ? NL80211_RATE_INFO_EHT_GI_0_8 : 1701 NL80211_RATE_INFO_HE_GI_0_8; 1702 case RTW89_GILTF_2XHE16: 1703 case RTW89_GILTF_1XHE16: 1704 return eht ? NL80211_RATE_INFO_EHT_GI_1_6 : 1705 NL80211_RATE_INFO_HE_GI_1_6; 1706 case RTW89_GILTF_LGI_4XHE32: 1707 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1708 NL80211_RATE_INFO_HE_GI_3_2; 1709 default: 1710 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1711 if (rx_status) 1712 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1713 NL80211_RATE_INFO_HE_GI_3_2; 1714 return U8_MAX; 1715 } 1716 } 1717 1718 static 1719 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 1720 bool eht) 1721 { 1722 if (eht) 1723 return status->eht.gi == gi_ltf; 1724 1725 return status->he_gi == gi_ltf; 1726 } 1727 1728 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1729 struct rtw89_rx_desc_info *desc_info, 1730 struct ieee80211_rx_status *status) 1731 { 1732 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1733 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1734 bool eht = false; 1735 u16 data_rate; 1736 bool ret; 1737 1738 data_rate = desc_info->data_rate; 1739 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1740 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1741 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1742 /* rate_idx is still hardware value here */ 1743 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1744 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1745 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 1746 data_rate_mode == DATA_RATE_MODE_HE || 1747 data_rate_mode == DATA_RATE_MODE_EHT) { 1748 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1749 } else { 1750 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1751 } 1752 1753 eht = data_rate_mode == DATA_RATE_MODE_EHT; 1754 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1755 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 1756 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1757 status->rate_idx == rate_idx && 1758 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 1759 status->bw == bw; 1760 1761 return ret; 1762 } 1763 1764 struct rtw89_vif_rx_stats_iter_data { 1765 struct rtw89_dev *rtwdev; 1766 struct rtw89_rx_phy_ppdu *phy_ppdu; 1767 struct rtw89_rx_desc_info *desc_info; 1768 struct sk_buff *skb; 1769 const u8 *bssid; 1770 }; 1771 1772 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1773 struct ieee80211_vif *vif, 1774 struct sk_buff *skb) 1775 { 1776 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1777 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1778 u8 *pos, *end, type, tf_bw; 1779 u16 aid, tf_rua; 1780 1781 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1782 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1783 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1784 return; 1785 1786 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1787 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 1788 return; 1789 1790 end = (u8 *)tf + skb->len; 1791 pos = tf->variable; 1792 1793 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1794 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1795 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 1796 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 1797 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1798 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 1799 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1800 tf_rua, tf_bw); 1801 1802 if (aid == RTW89_TF_PAD) 1803 break; 1804 1805 if (aid == vif->cfg.aid) { 1806 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 1807 1808 rtwvif->stats.rx_tf_acc++; 1809 rtwdev->stats.rx_tf_acc++; 1810 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 1811 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 1812 rtwvif->pwr_diff_en = true; 1813 break; 1814 } 1815 1816 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1817 } 1818 } 1819 1820 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work) 1821 { 1822 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1823 cancel_6ghz_probe_work); 1824 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1825 struct rtw89_pktofld_info *info; 1826 1827 mutex_lock(&rtwdev->mutex); 1828 1829 if (!rtwdev->scanning) 1830 goto out; 1831 1832 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1833 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 1834 continue; 1835 1836 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1837 1838 /* Don't delete/free info from pkt_list at this moment. Let it 1839 * be deleted/freed in rtw89_release_pkt_list() after scanning, 1840 * since if during scanning, pkt_list is accessed in bottom half. 1841 */ 1842 } 1843 1844 out: 1845 mutex_unlock(&rtwdev->mutex); 1846 } 1847 1848 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1849 struct sk_buff *skb) 1850 { 1851 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1852 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1853 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1854 struct rtw89_pktofld_info *info; 1855 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1856 bool queue_work = false; 1857 1858 if (rx_status->band != NL80211_BAND_6GHZ) 1859 return; 1860 1861 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1862 1863 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1864 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1865 info->cancel = true; 1866 queue_work = true; 1867 continue; 1868 } 1869 1870 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1871 continue; 1872 1873 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 1874 info->cancel = true; 1875 queue_work = true; 1876 } 1877 } 1878 1879 if (queue_work) 1880 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work); 1881 } 1882 1883 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif *rtwvif, 1884 struct ieee80211_hdr *hdr, size_t len) 1885 { 1886 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 1887 1888 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 1889 return; 1890 1891 WRITE_ONCE(rtwvif->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 1892 } 1893 1894 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1895 struct ieee80211_vif *vif) 1896 { 1897 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1898 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1899 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1900 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1901 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1902 struct sk_buff *skb = iter_data->skb; 1903 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1904 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 1905 const u8 *bssid = iter_data->bssid; 1906 1907 if (rtwdev->scanning && 1908 (ieee80211_is_beacon(hdr->frame_control) || 1909 ieee80211_is_probe_resp(hdr->frame_control))) 1910 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1911 1912 if (!vif->bss_conf.bssid) 1913 return; 1914 1915 if (ieee80211_is_trigger(hdr->frame_control)) { 1916 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1917 return; 1918 } 1919 1920 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1921 return; 1922 1923 if (ieee80211_is_beacon(hdr->frame_control)) { 1924 if (vif->type == NL80211_IFTYPE_STATION && 1925 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 1926 rtw89_vif_sync_bcn_tsf(rtwvif, hdr, skb->len); 1927 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 1928 } 1929 pkt_stat->beacon_nr++; 1930 } 1931 1932 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1933 return; 1934 1935 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1936 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1937 1938 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1939 } 1940 1941 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1942 struct rtw89_rx_phy_ppdu *phy_ppdu, 1943 struct rtw89_rx_desc_info *desc_info, 1944 struct sk_buff *skb) 1945 { 1946 struct rtw89_vif_rx_stats_iter_data iter_data; 1947 1948 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1949 1950 iter_data.rtwdev = rtwdev; 1951 iter_data.phy_ppdu = phy_ppdu; 1952 iter_data.desc_info = desc_info; 1953 iter_data.skb = skb; 1954 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1955 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1956 } 1957 1958 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1959 struct ieee80211_rx_status *status) 1960 { 1961 const struct rtw89_chan_rcd *rcd = 1962 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1963 u16 chan = rcd->prev_primary_channel; 1964 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 1965 1966 if (status->band != NL80211_BAND_2GHZ && 1967 status->encoding == RX_ENC_LEGACY && 1968 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1969 status->freq = ieee80211_channel_to_frequency(chan, band); 1970 status->band = band; 1971 } 1972 } 1973 1974 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1975 { 1976 if (rx_status->band == NL80211_BAND_2GHZ || 1977 rx_status->encoding != RX_ENC_LEGACY) 1978 return; 1979 1980 /* Some control frames' freq(ACKs in this case) are reported wrong due 1981 * to FW notify timing, set to lowest rate to prevent overflow. 1982 */ 1983 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1984 rx_status->rate_idx = 0; 1985 return; 1986 } 1987 1988 /* No 4 CCK rates for non-2G */ 1989 rx_status->rate_idx -= 4; 1990 } 1991 1992 static 1993 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 1994 struct ieee80211_rx_status *rx_status, 1995 struct rtw89_rx_phy_ppdu *phy_ppdu) 1996 { 1997 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 1998 return; 1999 2000 if (!phy_ppdu) 2001 return; 2002 2003 if (phy_ppdu->ldpc) 2004 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2005 if (phy_ppdu->stbc) 2006 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 2007 } 2008 2009 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 2010 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 2011 [RATE_INFO_BW_5] = U8_MAX, 2012 [RATE_INFO_BW_10] = U8_MAX, 2013 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 2014 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 2015 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 2016 [RATE_INFO_BW_HE_RU] = U8_MAX, 2017 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 2018 [RATE_INFO_BW_EHT_RU] = U8_MAX, 2019 }; 2020 2021 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2022 struct sk_buff *skb, 2023 struct ieee80211_rx_status *rx_status) 2024 { 2025 struct ieee80211_radiotap_eht_usig *usig; 2026 struct ieee80211_radiotap_eht *eht; 2027 struct ieee80211_radiotap_tlv *tlv; 2028 int eht_len = struct_size(eht, user_info, 1); 2029 int usig_len = sizeof(*usig); 2030 int len; 2031 u8 bw; 2032 2033 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2034 sizeof(*tlv) + ALIGN(usig_len, 4); 2035 2036 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2037 skb_reset_mac_header(skb); 2038 2039 /* EHT */ 2040 tlv = skb_push(skb, len); 2041 memset(tlv, 0, len); 2042 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2043 tlv->len = cpu_to_le16(eht_len); 2044 2045 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2046 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2047 eht->data[0] = 2048 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2049 2050 eht->user_info[0] = 2051 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2052 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 2053 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 2054 eht->user_info[0] |= 2055 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2056 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2057 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 2058 eht->user_info[0] |= 2059 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 2060 2061 /* U-SIG */ 2062 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2063 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2064 tlv->len = cpu_to_le16(usig_len); 2065 2066 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2067 return; 2068 2069 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2070 if (bw == U8_MAX) 2071 return; 2072 2073 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2074 usig->common = 2075 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2076 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2077 } 2078 2079 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2080 struct sk_buff *skb, 2081 struct ieee80211_rx_status *rx_status) 2082 { 2083 static const struct ieee80211_radiotap_he known_he = { 2084 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2085 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 2086 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 2087 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2088 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2089 }; 2090 struct ieee80211_radiotap_he *he; 2091 2092 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2093 return; 2094 2095 if (rx_status->encoding == RX_ENC_HE) { 2096 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2097 he = skb_push(skb, sizeof(*he)); 2098 *he = known_he; 2099 } else if (rx_status->encoding == RX_ENC_EHT) { 2100 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2101 } 2102 } 2103 2104 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2105 struct rtw89_rx_phy_ppdu *phy_ppdu, 2106 struct rtw89_rx_desc_info *desc_info, 2107 struct sk_buff *skb_ppdu, 2108 struct ieee80211_rx_status *rx_status) 2109 { 2110 struct napi_struct *napi = &rtwdev->napi; 2111 2112 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2113 if (unlikely(!napi_is_scheduled(napi))) 2114 napi = NULL; 2115 2116 rtw89_core_hw_to_sband_rate(rx_status); 2117 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2118 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 2119 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2120 /* In low power mode, it does RX in thread context. */ 2121 local_bh_disable(); 2122 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2123 local_bh_enable(); 2124 rtwdev->napi_budget_countdown--; 2125 } 2126 2127 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2128 struct rtw89_rx_phy_ppdu *phy_ppdu, 2129 struct rtw89_rx_desc_info *desc_info, 2130 struct sk_buff *skb) 2131 { 2132 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2133 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2134 struct sk_buff *skb_ppdu = NULL, *tmp; 2135 struct ieee80211_rx_status *rx_status; 2136 2137 if (curr > RTW89_MAX_PPDU_CNT) 2138 return; 2139 2140 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2141 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2142 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2143 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2144 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2145 rtw89_correct_cck_chan(rtwdev, rx_status); 2146 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2147 } 2148 } 2149 2150 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2151 struct rtw89_rx_desc_info *desc_info, 2152 struct sk_buff *skb) 2153 { 2154 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2155 .len = skb->len, 2156 .to_self = desc_info->addr1_match, 2157 .rate = desc_info->data_rate, 2158 .mac_id = desc_info->mac_id}; 2159 int ret; 2160 2161 if (desc_info->mac_info_valid) { 2162 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2163 if (ret) 2164 goto out; 2165 } 2166 2167 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2168 if (ret) 2169 goto out; 2170 2171 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2172 2173 out: 2174 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2175 dev_kfree_skb_any(skb); 2176 } 2177 2178 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2179 struct rtw89_rx_desc_info *desc_info, 2180 struct sk_buff *skb) 2181 { 2182 switch (desc_info->pkt_type) { 2183 case RTW89_CORE_RX_TYPE_C2H: 2184 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2185 break; 2186 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2187 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2188 break; 2189 default: 2190 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2191 desc_info->pkt_type); 2192 dev_kfree_skb_any(skb); 2193 break; 2194 } 2195 } 2196 2197 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2198 struct rtw89_rx_desc_info *desc_info, 2199 u8 *data, u32 data_offset) 2200 { 2201 const struct rtw89_chip_info *chip = rtwdev->chip; 2202 struct rtw89_rxdesc_short *rxd_s; 2203 struct rtw89_rxdesc_long *rxd_l; 2204 u8 shift_len, drv_info_len; 2205 2206 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2207 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2208 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2209 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2210 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2211 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2212 if (chip->chip_id == RTL8852C) 2213 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2214 else 2215 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2216 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2217 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2218 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2219 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2220 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2221 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2222 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2223 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2224 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2225 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2226 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2227 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2228 2229 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2230 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2231 desc_info->offset = data_offset + shift_len + drv_info_len; 2232 if (desc_info->long_rxdesc) 2233 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2234 else 2235 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2236 desc_info->ready = true; 2237 2238 if (!desc_info->long_rxdesc) 2239 return; 2240 2241 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2242 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2243 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2244 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2245 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2246 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2247 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2248 } 2249 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2250 2251 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2252 struct rtw89_rx_desc_info *desc_info, 2253 u8 *data, u32 data_offset) 2254 { 2255 struct rtw89_rxdesc_short_v2 *rxd_s; 2256 struct rtw89_rxdesc_long_v2 *rxd_l; 2257 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2258 2259 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2260 2261 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2262 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2263 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2264 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2265 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2266 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2267 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2268 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2269 desc_info->mac_info_valid = true; 2270 2271 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2272 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2273 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2274 2275 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2276 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2277 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2278 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2279 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2280 2281 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2282 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2283 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2284 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2285 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2286 2287 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2288 2289 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2290 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2291 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2292 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2293 desc_info->offset = data_offset + shift_len + drv_info_len + 2294 phy_rtp_len + hdr_cnv_len; 2295 2296 if (desc_info->long_rxdesc) 2297 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2298 else 2299 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2300 desc_info->ready = true; 2301 2302 if (!desc_info->long_rxdesc) 2303 return; 2304 2305 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2306 2307 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2308 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2309 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2310 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2311 2312 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2313 } 2314 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2315 2316 struct rtw89_core_iter_rx_status { 2317 struct rtw89_dev *rtwdev; 2318 struct ieee80211_rx_status *rx_status; 2319 struct rtw89_rx_desc_info *desc_info; 2320 u8 mac_id; 2321 }; 2322 2323 static 2324 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2325 { 2326 struct rtw89_core_iter_rx_status *iter_data = 2327 (struct rtw89_core_iter_rx_status *)data; 2328 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2329 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2330 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2331 u8 mac_id = iter_data->mac_id; 2332 2333 if (mac_id != rtwsta->mac_id) 2334 return; 2335 2336 rtwsta->rx_status = *rx_status; 2337 rtwsta->rx_hw_rate = desc_info->data_rate; 2338 } 2339 2340 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2341 struct rtw89_rx_desc_info *desc_info, 2342 struct ieee80211_rx_status *rx_status) 2343 { 2344 struct rtw89_core_iter_rx_status iter_data; 2345 2346 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2347 return; 2348 2349 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2350 return; 2351 2352 iter_data.rtwdev = rtwdev; 2353 iter_data.rx_status = rx_status; 2354 iter_data.desc_info = desc_info; 2355 iter_data.mac_id = desc_info->mac_id; 2356 ieee80211_iterate_stations_atomic(rtwdev->hw, 2357 rtw89_core_stats_sta_rx_status_iter, 2358 &iter_data); 2359 } 2360 2361 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2362 struct rtw89_rx_desc_info *desc_info, 2363 struct ieee80211_rx_status *rx_status) 2364 { 2365 const struct cfg80211_chan_def *chandef = 2366 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 2367 u16 data_rate; 2368 u8 data_rate_mode; 2369 bool eht = false; 2370 u8 gi; 2371 2372 /* currently using single PHY */ 2373 rx_status->freq = chandef->chan->center_freq; 2374 rx_status->band = chandef->chan->band; 2375 2376 if (rtwdev->scanning && 2377 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2378 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2379 u8 chan = cur->primary_channel; 2380 u8 band = cur->band_type; 2381 enum nl80211_band nl_band; 2382 2383 nl_band = rtw89_hw_to_nl80211_band(band); 2384 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2385 rx_status->band = nl_band; 2386 } 2387 2388 if (desc_info->icv_err || desc_info->crc32_err) 2389 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2390 2391 if (desc_info->hw_dec && 2392 !(desc_info->sw_dec || desc_info->icv_err)) 2393 rx_status->flag |= RX_FLAG_DECRYPTED; 2394 2395 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2396 2397 data_rate = desc_info->data_rate; 2398 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2399 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2400 rx_status->encoding = RX_ENC_LEGACY; 2401 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2402 /* convert rate_idx after we get the correct band */ 2403 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2404 rx_status->encoding = RX_ENC_HT; 2405 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2406 if (desc_info->gi_ltf) 2407 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2408 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2409 rx_status->encoding = RX_ENC_VHT; 2410 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2411 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2412 if (desc_info->gi_ltf) 2413 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2414 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2415 rx_status->encoding = RX_ENC_HE; 2416 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2417 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2418 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2419 rx_status->encoding = RX_ENC_EHT; 2420 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2421 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2422 eht = true; 2423 } else { 2424 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2425 } 2426 2427 /* he_gi is used to match ppdu, so we always fill it. */ 2428 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2429 if (eht) 2430 rx_status->eht.gi = gi; 2431 else 2432 rx_status->he_gi = gi; 2433 rx_status->flag |= RX_FLAG_MACTIME_START; 2434 rx_status->mactime = desc_info->free_run_cnt; 2435 2436 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2437 } 2438 2439 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2440 { 2441 const struct rtw89_chip_info *chip = rtwdev->chip; 2442 2443 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2444 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2445 return RTW89_PS_MODE_NONE; 2446 2447 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2448 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2449 return RTW89_PS_MODE_PWR_GATED; 2450 2451 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2452 return RTW89_PS_MODE_CLK_GATED; 2453 2454 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2455 return RTW89_PS_MODE_RFOFF; 2456 2457 return RTW89_PS_MODE_NONE; 2458 } 2459 2460 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2461 struct rtw89_rx_desc_info *desc_info) 2462 { 2463 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2464 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2465 struct ieee80211_rx_status *rx_status; 2466 struct sk_buff *skb_ppdu, *tmp; 2467 2468 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2469 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2470 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2471 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2472 } 2473 } 2474 2475 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2476 struct rtw89_rx_desc_info *desc_info, 2477 struct sk_buff *skb) 2478 { 2479 struct ieee80211_rx_status *rx_status; 2480 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2481 u8 ppdu_cnt = desc_info->ppdu_cnt; 2482 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2483 2484 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2485 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2486 return; 2487 } 2488 2489 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2490 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2491 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2492 } 2493 2494 rx_status = IEEE80211_SKB_RXCB(skb); 2495 memset(rx_status, 0, sizeof(*rx_status)); 2496 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2497 if (desc_info->long_rxdesc && 2498 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2499 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2500 else 2501 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2502 } 2503 EXPORT_SYMBOL(rtw89_core_rx); 2504 2505 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2506 { 2507 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2508 return; 2509 2510 napi_enable(&rtwdev->napi); 2511 } 2512 EXPORT_SYMBOL(rtw89_core_napi_start); 2513 2514 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2515 { 2516 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2517 return; 2518 2519 napi_synchronize(&rtwdev->napi); 2520 napi_disable(&rtwdev->napi); 2521 } 2522 EXPORT_SYMBOL(rtw89_core_napi_stop); 2523 2524 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2525 { 2526 rtwdev->netdev = alloc_netdev_dummy(0); 2527 if (!rtwdev->netdev) 2528 return -ENOMEM; 2529 2530 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 2531 rtwdev->hci.ops->napi_poll); 2532 return 0; 2533 } 2534 EXPORT_SYMBOL(rtw89_core_napi_init); 2535 2536 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2537 { 2538 rtw89_core_napi_stop(rtwdev); 2539 netif_napi_del(&rtwdev->napi); 2540 free_netdev(rtwdev->netdev); 2541 } 2542 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2543 2544 static void rtw89_core_ba_work(struct work_struct *work) 2545 { 2546 struct rtw89_dev *rtwdev = 2547 container_of(work, struct rtw89_dev, ba_work); 2548 struct rtw89_txq *rtwtxq, *tmp; 2549 int ret; 2550 2551 spin_lock_bh(&rtwdev->ba_lock); 2552 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2553 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2554 struct ieee80211_sta *sta = txq->sta; 2555 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2556 u8 tid = txq->tid; 2557 2558 if (!sta) { 2559 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2560 goto skip_ba_work; 2561 } 2562 2563 if (rtwsta->disassoc) { 2564 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2565 "cannot start BA with disassoc sta\n"); 2566 goto skip_ba_work; 2567 } 2568 2569 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2570 if (ret) { 2571 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2572 "failed to setup BA session for %pM:%2d: %d\n", 2573 sta->addr, tid, ret); 2574 if (ret == -EINVAL) 2575 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2576 } 2577 skip_ba_work: 2578 list_del_init(&rtwtxq->list); 2579 } 2580 spin_unlock_bh(&rtwdev->ba_lock); 2581 } 2582 2583 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2584 struct ieee80211_sta *sta) 2585 { 2586 struct rtw89_txq *rtwtxq, *tmp; 2587 2588 spin_lock_bh(&rtwdev->ba_lock); 2589 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2590 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2591 2592 if (sta == txq->sta) 2593 list_del_init(&rtwtxq->list); 2594 } 2595 spin_unlock_bh(&rtwdev->ba_lock); 2596 } 2597 2598 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2599 struct ieee80211_sta *sta) 2600 { 2601 struct rtw89_txq *rtwtxq, *tmp; 2602 2603 spin_lock_bh(&rtwdev->ba_lock); 2604 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2605 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2606 2607 if (sta == txq->sta) { 2608 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2609 list_del_init(&rtwtxq->list); 2610 } 2611 } 2612 spin_unlock_bh(&rtwdev->ba_lock); 2613 } 2614 2615 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2616 struct ieee80211_sta *sta) 2617 { 2618 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2619 struct sk_buff *skb, *tmp; 2620 2621 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2622 skb_unlink(skb, &rtwsta->roc_queue); 2623 dev_kfree_skb_any(skb); 2624 } 2625 } 2626 2627 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2628 struct rtw89_txq *rtwtxq) 2629 { 2630 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2631 struct ieee80211_sta *sta = txq->sta; 2632 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2633 2634 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2635 return; 2636 2637 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2638 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2639 return; 2640 2641 spin_lock_bh(&rtwdev->ba_lock); 2642 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2643 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2644 spin_unlock_bh(&rtwdev->ba_lock); 2645 2646 ieee80211_stop_tx_ba_session(sta, txq->tid); 2647 cancel_delayed_work(&rtwdev->forbid_ba_work); 2648 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2649 RTW89_FORBID_BA_TIMER); 2650 } 2651 2652 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2653 struct rtw89_txq *rtwtxq, 2654 struct sk_buff *skb) 2655 { 2656 struct ieee80211_hw *hw = rtwdev->hw; 2657 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2658 struct ieee80211_sta *sta = txq->sta; 2659 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2660 2661 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2662 return; 2663 2664 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2665 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2666 return; 2667 } 2668 2669 if (unlikely(!sta)) 2670 return; 2671 2672 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2673 return; 2674 2675 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2676 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2677 return; 2678 } 2679 2680 spin_lock_bh(&rtwdev->ba_lock); 2681 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2682 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2683 ieee80211_queue_work(hw, &rtwdev->ba_work); 2684 } 2685 spin_unlock_bh(&rtwdev->ba_lock); 2686 } 2687 2688 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2689 struct rtw89_txq *rtwtxq, 2690 unsigned long frame_cnt, 2691 unsigned long byte_cnt) 2692 { 2693 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2694 struct ieee80211_vif *vif = txq->vif; 2695 struct ieee80211_sta *sta = txq->sta; 2696 struct sk_buff *skb; 2697 unsigned long i; 2698 int ret; 2699 2700 rcu_read_lock(); 2701 for (i = 0; i < frame_cnt; i++) { 2702 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2703 if (!skb) { 2704 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2705 goto out; 2706 } 2707 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2708 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2709 if (ret) { 2710 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2711 ieee80211_free_txskb(rtwdev->hw, skb); 2712 break; 2713 } 2714 } 2715 out: 2716 rcu_read_unlock(); 2717 } 2718 2719 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2720 { 2721 u8 qsel, ch_dma; 2722 2723 qsel = rtw89_core_get_qsel(rtwdev, tid); 2724 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2725 2726 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2727 } 2728 2729 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2730 struct ieee80211_txq *txq, 2731 unsigned long *frame_cnt, 2732 bool *sched_txq, bool *reinvoke) 2733 { 2734 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2735 struct ieee80211_sta *sta = txq->sta; 2736 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2737 2738 if (!sta || rtwsta->max_agg_wait <= 0) 2739 return false; 2740 2741 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2742 return false; 2743 2744 if (*frame_cnt > 1) { 2745 *frame_cnt -= 1; 2746 *sched_txq = true; 2747 *reinvoke = true; 2748 rtwtxq->wait_cnt = 1; 2749 return false; 2750 } 2751 2752 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2753 *reinvoke = true; 2754 rtwtxq->wait_cnt++; 2755 return true; 2756 } 2757 2758 rtwtxq->wait_cnt = 0; 2759 return false; 2760 } 2761 2762 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2763 { 2764 struct ieee80211_hw *hw = rtwdev->hw; 2765 struct ieee80211_txq *txq; 2766 struct rtw89_vif *rtwvif; 2767 struct rtw89_txq *rtwtxq; 2768 unsigned long frame_cnt; 2769 unsigned long byte_cnt; 2770 u32 tx_resource; 2771 bool sched_txq; 2772 2773 ieee80211_txq_schedule_start(hw, ac); 2774 while ((txq = ieee80211_next_txq(hw, ac))) { 2775 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2776 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv; 2777 2778 if (rtwvif->offchan) { 2779 ieee80211_return_txq(hw, txq, true); 2780 continue; 2781 } 2782 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2783 sched_txq = false; 2784 2785 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2786 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2787 ieee80211_return_txq(hw, txq, true); 2788 continue; 2789 } 2790 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2791 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2792 ieee80211_return_txq(hw, txq, sched_txq); 2793 if (frame_cnt != 0) 2794 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2795 2796 /* bound of tx_resource could get stuck due to burst traffic */ 2797 if (frame_cnt == tx_resource) 2798 *reinvoke = true; 2799 } 2800 ieee80211_txq_schedule_end(hw, ac); 2801 } 2802 2803 static void rtw89_ips_work(struct work_struct *work) 2804 { 2805 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2806 ips_work); 2807 mutex_lock(&rtwdev->mutex); 2808 rtw89_enter_ips_by_hwflags(rtwdev); 2809 mutex_unlock(&rtwdev->mutex); 2810 } 2811 2812 static void rtw89_core_txq_work(struct work_struct *w) 2813 { 2814 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2815 bool reinvoke = false; 2816 u8 ac; 2817 2818 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2819 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2820 2821 if (reinvoke) { 2822 /* reinvoke to process the last frame */ 2823 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2824 } 2825 } 2826 2827 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2828 { 2829 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2830 txq_reinvoke_work.work); 2831 2832 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2833 } 2834 2835 static void rtw89_forbid_ba_work(struct work_struct *w) 2836 { 2837 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2838 forbid_ba_work.work); 2839 struct rtw89_txq *rtwtxq, *tmp; 2840 2841 spin_lock_bh(&rtwdev->ba_lock); 2842 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2843 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2844 list_del_init(&rtwtxq->list); 2845 } 2846 spin_unlock_bh(&rtwdev->ba_lock); 2847 } 2848 2849 static void rtw89_core_sta_pending_tx_iter(void *data, 2850 struct ieee80211_sta *sta) 2851 { 2852 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2853 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif; 2854 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2855 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2856 struct sk_buff *skb, *tmp; 2857 int qsel, ret; 2858 2859 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx) 2860 return; 2861 2862 if (skb_queue_len(&rtwsta->roc_queue) == 0) 2863 return; 2864 2865 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2866 skb_unlink(skb, &rtwsta->roc_queue); 2867 2868 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2869 if (ret) { 2870 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 2871 dev_kfree_skb_any(skb); 2872 } else { 2873 rtw89_core_tx_kick_off(rtwdev, qsel); 2874 } 2875 } 2876 } 2877 2878 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 2879 struct rtw89_vif *rtwvif) 2880 { 2881 ieee80211_iterate_stations_atomic(rtwdev->hw, 2882 rtw89_core_sta_pending_tx_iter, 2883 rtwvif); 2884 } 2885 2886 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 2887 struct rtw89_vif *rtwvif, bool qos, bool ps) 2888 { 2889 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2890 struct ieee80211_sta *sta; 2891 struct ieee80211_hdr *hdr; 2892 struct sk_buff *skb; 2893 int ret, qsel; 2894 2895 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 2896 return 0; 2897 2898 rcu_read_lock(); 2899 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 2900 if (!sta) { 2901 ret = -EINVAL; 2902 goto out; 2903 } 2904 2905 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos); 2906 if (!skb) { 2907 ret = -ENOMEM; 2908 goto out; 2909 } 2910 2911 hdr = (struct ieee80211_hdr *)skb->data; 2912 if (ps) 2913 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2914 2915 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2916 if (ret) { 2917 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 2918 dev_kfree_skb_any(skb); 2919 goto out; 2920 } 2921 2922 rcu_read_unlock(); 2923 2924 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 2925 RTW89_ROC_TX_TIMEOUT); 2926 out: 2927 rcu_read_unlock(); 2928 2929 return ret; 2930 } 2931 2932 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2933 { 2934 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2935 struct ieee80211_hw *hw = rtwdev->hw; 2936 struct rtw89_roc *roc = &rtwvif->roc; 2937 struct cfg80211_chan_def roc_chan; 2938 struct rtw89_vif *tmp; 2939 int ret; 2940 2941 lockdep_assert_held(&rtwdev->mutex); 2942 2943 rtw89_leave_ips_by_hwflags(rtwdev); 2944 rtw89_leave_lps(rtwdev); 2945 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC); 2946 2947 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true); 2948 if (ret) 2949 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2950 "roc send null-1 failed: %d\n", ret); 2951 2952 rtw89_for_each_rtwvif(rtwdev, tmp) 2953 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2954 tmp->offchan = true; 2955 2956 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 2957 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan); 2958 rtw89_set_channel(rtwdev); 2959 rtw89_write32_clr(rtwdev, 2960 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2961 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 2962 2963 ieee80211_ready_on_channel(hw); 2964 cancel_delayed_work(&rtwvif->roc.roc_work); 2965 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 2966 msecs_to_jiffies(rtwvif->roc.duration)); 2967 } 2968 2969 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2970 { 2971 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2972 struct ieee80211_hw *hw = rtwdev->hw; 2973 struct rtw89_roc *roc = &rtwvif->roc; 2974 struct rtw89_vif *tmp; 2975 int ret; 2976 2977 lockdep_assert_held(&rtwdev->mutex); 2978 2979 ieee80211_remain_on_channel_expired(hw); 2980 2981 rtw89_leave_ips_by_hwflags(rtwdev); 2982 rtw89_leave_lps(rtwdev); 2983 2984 rtw89_write32_mask(rtwdev, 2985 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2986 B_AX_RX_FLTR_CFG_MASK, 2987 rtwdev->hal.rx_fltr); 2988 2989 roc->state = RTW89_ROC_IDLE; 2990 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL); 2991 rtw89_chanctx_proceed(rtwdev); 2992 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false); 2993 if (ret) 2994 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2995 "roc send null-0 failed: %d\n", ret); 2996 2997 rtw89_for_each_rtwvif(rtwdev, tmp) 2998 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2999 tmp->offchan = false; 3000 3001 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif); 3002 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3003 3004 if (hw->conf.flags & IEEE80211_CONF_IDLE) 3005 ieee80211_queue_delayed_work(hw, &roc->roc_work, 3006 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 3007 } 3008 3009 void rtw89_roc_work(struct work_struct *work) 3010 { 3011 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3012 roc.roc_work.work); 3013 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3014 struct rtw89_roc *roc = &rtwvif->roc; 3015 3016 mutex_lock(&rtwdev->mutex); 3017 3018 switch (roc->state) { 3019 case RTW89_ROC_IDLE: 3020 rtw89_enter_ips_by_hwflags(rtwdev); 3021 break; 3022 case RTW89_ROC_MGMT: 3023 case RTW89_ROC_NORMAL: 3024 rtw89_roc_end(rtwdev, rtwvif); 3025 break; 3026 default: 3027 break; 3028 } 3029 3030 mutex_unlock(&rtwdev->mutex); 3031 } 3032 3033 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3034 u32 throughput, u64 cnt) 3035 { 3036 if (cnt < 100) 3037 return RTW89_TFC_IDLE; 3038 if (throughput > 50) 3039 return RTW89_TFC_HIGH; 3040 if (throughput > 10) 3041 return RTW89_TFC_MID; 3042 if (throughput > 2) 3043 return RTW89_TFC_LOW; 3044 return RTW89_TFC_ULTRA_LOW; 3045 } 3046 3047 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3048 struct rtw89_traffic_stats *stats) 3049 { 3050 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3051 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3052 3053 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 3054 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3055 3056 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3057 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3058 3059 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3060 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3061 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3062 stats->tx_cnt); 3063 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3064 stats->rx_cnt); 3065 stats->tx_avg_len = stats->tx_cnt ? 3066 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3067 stats->rx_avg_len = stats->rx_cnt ? 3068 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3069 3070 stats->tx_unicast = 0; 3071 stats->rx_unicast = 0; 3072 stats->tx_cnt = 0; 3073 stats->rx_cnt = 0; 3074 stats->rx_tf_periodic = stats->rx_tf_acc; 3075 stats->rx_tf_acc = 0; 3076 3077 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3078 return true; 3079 3080 return false; 3081 } 3082 3083 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3084 { 3085 struct rtw89_vif *rtwvif; 3086 bool tfc_changed; 3087 3088 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3089 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3090 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3091 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif); 3092 } 3093 3094 return tfc_changed; 3095 } 3096 3097 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3098 { 3099 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 3100 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 3101 rtwvif->tdls_peer) 3102 return; 3103 3104 if (rtwvif->offchan) 3105 return; 3106 3107 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 3108 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 3109 rtw89_enter_lps(rtwdev, rtwvif, true); 3110 } 3111 3112 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3113 { 3114 struct rtw89_vif *rtwvif; 3115 3116 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3117 rtw89_vif_enter_lps(rtwdev, rtwvif); 3118 } 3119 3120 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3121 { 3122 enum rtw89_entity_mode mode; 3123 3124 mode = rtw89_get_entity_mode(rtwdev); 3125 if (mode == RTW89_ENTITY_MODE_MCC) 3126 return; 3127 3128 rtw89_chip_rfk_track(rtwdev); 3129 } 3130 3131 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3132 { 3133 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3134 3135 if (mode == RTW89_ENTITY_MODE_MCC) 3136 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3137 else 3138 rtw89_process_p2p_ps(rtwdev, vif); 3139 } 3140 3141 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3142 struct rtw89_traffic_stats *stats) 3143 { 3144 stats->tx_unicast = 0; 3145 stats->rx_unicast = 0; 3146 stats->tx_cnt = 0; 3147 stats->rx_cnt = 0; 3148 ewma_tp_init(&stats->tx_ewma_tp); 3149 ewma_tp_init(&stats->rx_ewma_tp); 3150 } 3151 3152 static void rtw89_track_work(struct work_struct *work) 3153 { 3154 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3155 track_work.work); 3156 bool tfc_changed; 3157 3158 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3159 return; 3160 3161 mutex_lock(&rtwdev->mutex); 3162 3163 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3164 goto out; 3165 3166 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3167 RTW89_TRACK_WORK_PERIOD); 3168 3169 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3170 if (rtwdev->scanning) 3171 goto out; 3172 3173 rtw89_leave_lps(rtwdev); 3174 3175 if (tfc_changed) { 3176 rtw89_hci_recalc_int_mit(rtwdev); 3177 rtw89_btc_ntfy_wl_sta(rtwdev); 3178 } 3179 rtw89_mac_bf_monitor_track(rtwdev); 3180 rtw89_phy_stat_track(rtwdev); 3181 rtw89_phy_env_monitor_track(rtwdev); 3182 rtw89_phy_dig(rtwdev); 3183 rtw89_core_rfk_track(rtwdev); 3184 rtw89_phy_ra_update(rtwdev); 3185 rtw89_phy_cfo_track(rtwdev); 3186 rtw89_phy_tx_path_div_track(rtwdev); 3187 rtw89_phy_antdiv_track(rtwdev); 3188 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3189 rtw89_phy_edcca_track(rtwdev); 3190 rtw89_tas_track(rtwdev); 3191 rtw89_chanctx_track(rtwdev); 3192 3193 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3194 rtw89_enter_lps_track(rtwdev); 3195 3196 out: 3197 mutex_unlock(&rtwdev->mutex); 3198 } 3199 3200 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3201 { 3202 unsigned long bit; 3203 3204 bit = find_first_zero_bit(addr, size); 3205 if (bit < size) 3206 set_bit(bit, addr); 3207 3208 return bit; 3209 } 3210 3211 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3212 { 3213 clear_bit(bit, addr); 3214 } 3215 3216 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3217 { 3218 bitmap_zero(addr, nbits); 3219 } 3220 3221 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3222 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3223 { 3224 const struct rtw89_chip_info *chip = rtwdev->chip; 3225 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3226 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3227 u8 idx; 3228 int i; 3229 3230 lockdep_assert_held(&rtwdev->mutex); 3231 3232 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3233 if (idx == chip->bacam_num) { 3234 /* allocate a static BA CAM to tid=0/5, so replace the existing 3235 * one if BA CAM is full. Hardware will process the original tid 3236 * automatically. 3237 */ 3238 if (tid != 0 && tid != 5) 3239 return -ENOSPC; 3240 3241 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3242 tmp = &cam_info->ba_cam_entry[i]; 3243 if (tmp->tid == 0 || tmp->tid == 5) 3244 continue; 3245 3246 idx = i; 3247 entry = tmp; 3248 list_del(&entry->list); 3249 break; 3250 } 3251 3252 if (!entry) 3253 return -ENOSPC; 3254 } else { 3255 entry = &cam_info->ba_cam_entry[idx]; 3256 } 3257 3258 entry->tid = tid; 3259 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 3260 3261 *cam_idx = idx; 3262 3263 return 0; 3264 } 3265 3266 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3267 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3268 { 3269 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3270 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3271 u8 idx; 3272 3273 lockdep_assert_held(&rtwdev->mutex); 3274 3275 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 3276 if (entry->tid != tid) 3277 continue; 3278 3279 idx = entry - cam_info->ba_cam_entry; 3280 list_del(&entry->list); 3281 3282 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3283 *cam_idx = idx; 3284 return 0; 3285 } 3286 3287 return -ENOENT; 3288 } 3289 3290 #define RTW89_TYPE_MAPPING(_type) \ 3291 case NL80211_IFTYPE_ ## _type: \ 3292 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3293 break 3294 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 3295 { 3296 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3297 3298 switch (vif->type) { 3299 case NL80211_IFTYPE_STATION: 3300 if (vif->p2p) 3301 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3302 else 3303 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 3304 break; 3305 case NL80211_IFTYPE_AP: 3306 if (vif->p2p) 3307 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3308 else 3309 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 3310 break; 3311 RTW89_TYPE_MAPPING(ADHOC); 3312 RTW89_TYPE_MAPPING(MONITOR); 3313 RTW89_TYPE_MAPPING(MESH_POINT); 3314 default: 3315 WARN_ON(1); 3316 break; 3317 } 3318 3319 switch (vif->type) { 3320 case NL80211_IFTYPE_AP: 3321 case NL80211_IFTYPE_MESH_POINT: 3322 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 3323 rtwvif->self_role = RTW89_SELF_ROLE_AP; 3324 break; 3325 case NL80211_IFTYPE_ADHOC: 3326 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 3327 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3328 break; 3329 case NL80211_IFTYPE_STATION: 3330 if (assoc) { 3331 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 3332 rtwvif->trigger = vif->bss_conf.he_support; 3333 } else { 3334 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 3335 rtwvif->trigger = false; 3336 } 3337 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3338 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3339 break; 3340 case NL80211_IFTYPE_MONITOR: 3341 break; 3342 default: 3343 WARN_ON(1); 3344 break; 3345 } 3346 } 3347 3348 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3349 struct ieee80211_vif *vif, 3350 struct ieee80211_sta *sta) 3351 { 3352 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3353 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3354 struct rtw89_hal *hal = &rtwdev->hal; 3355 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3356 int i; 3357 int ret; 3358 3359 rtwsta->rtwdev = rtwdev; 3360 rtwsta->rtwvif = rtwvif; 3361 rtwsta->prev_rssi = 0; 3362 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 3363 skb_queue_head_init(&rtwsta->roc_queue); 3364 3365 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 3366 rtw89_core_txq_init(rtwdev, sta->txq[i]); 3367 3368 ewma_rssi_init(&rtwsta->avg_rssi); 3369 ewma_snr_init(&rtwsta->avg_snr); 3370 for (i = 0; i < ant_num; i++) { 3371 ewma_rssi_init(&rtwsta->rssi[i]); 3372 ewma_evm_init(&rtwsta->evm_min[i]); 3373 ewma_evm_init(&rtwsta->evm_max[i]); 3374 } 3375 3376 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3377 /* for station mode, assign the mac_id from itself */ 3378 rtwsta->mac_id = rtwvif->mac_id; 3379 3380 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 3381 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif, true); 3382 if (ret) 3383 return ret; 3384 3385 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3386 BTC_ROLE_MSTS_STA_CONN_START); 3387 rtw89_chip_rfk_channel(rtwdev); 3388 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3389 rtwsta->mac_id = rtw89_acquire_mac_id(rtwdev); 3390 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 3391 return -ENOSPC; 3392 3393 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 3394 if (ret) { 3395 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3396 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3397 return ret; 3398 } 3399 3400 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3401 RTW89_ROLE_CREATE); 3402 if (ret) { 3403 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3404 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3405 return ret; 3406 } 3407 3408 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta); 3409 if (ret) 3410 return ret; 3411 3412 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta); 3413 if (ret) 3414 return ret; 3415 3416 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3417 } 3418 3419 return 0; 3420 } 3421 3422 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3423 struct ieee80211_vif *vif, 3424 struct ieee80211_sta *sta) 3425 { 3426 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3427 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3428 3429 if (vif->type == NL80211_IFTYPE_STATION) 3430 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false); 3431 3432 rtwdev->total_sta_assoc--; 3433 if (sta->tdls) 3434 rtwvif->tdls_peer--; 3435 rtwsta->disassoc = true; 3436 3437 return 0; 3438 } 3439 3440 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3441 struct ieee80211_vif *vif, 3442 struct ieee80211_sta *sta) 3443 { 3444 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3445 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3446 int ret; 3447 3448 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 3449 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 3450 rtw89_core_free_sta_pending_ba(rtwdev, sta); 3451 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 3452 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta); 3453 3454 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 3455 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 3456 if (sta->tdls) 3457 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 3458 3459 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3460 rtw89_vif_type_mapping(vif, false); 3461 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 3462 } 3463 3464 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3465 if (ret) { 3466 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3467 return ret; 3468 } 3469 3470 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 3471 if (ret) { 3472 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3473 return ret; 3474 } 3475 3476 /* update cam aid mac_id net_type */ 3477 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3478 if (ret) { 3479 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3480 return ret; 3481 } 3482 3483 return ret; 3484 } 3485 3486 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3487 struct ieee80211_vif *vif, 3488 struct ieee80211_sta *sta) 3489 { 3490 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3491 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3492 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 3493 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3494 rtwvif->sub_entity_idx); 3495 int ret; 3496 3497 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3498 if (sta->tdls) { 3499 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 3500 if (ret) { 3501 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3502 return ret; 3503 } 3504 } 3505 3506 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 3507 if (ret) { 3508 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3509 return ret; 3510 } 3511 } 3512 3513 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3514 if (ret) { 3515 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3516 return ret; 3517 } 3518 3519 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 3520 if (ret) { 3521 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3522 return ret; 3523 } 3524 3525 /* update cam aid mac_id net_type */ 3526 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3527 if (ret) { 3528 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3529 return ret; 3530 } 3531 3532 rtwdev->total_sta_assoc++; 3533 if (sta->tdls) 3534 rtwvif->tdls_peer++; 3535 rtw89_phy_ra_assoc(rtwdev, sta); 3536 rtw89_mac_bf_assoc(rtwdev, vif, sta); 3537 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 3538 3539 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3540 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 3541 3542 if (bss_conf->he_support && 3543 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 3544 rtwsta->er_cap = true; 3545 3546 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3547 BTC_ROLE_MSTS_STA_CONN_END); 3548 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan); 3549 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 3550 3551 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 3552 if (ret) { 3553 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3554 return ret; 3555 } 3556 3557 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 3558 } 3559 3560 return ret; 3561 } 3562 3563 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3564 struct ieee80211_vif *vif, 3565 struct ieee80211_sta *sta) 3566 { 3567 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3568 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3569 int ret; 3570 3571 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3572 rtw89_reg_6ghz_recalc(rtwdev, rtwvif, false); 3573 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3574 BTC_ROLE_MSTS_STA_DIS_CONN); 3575 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3576 rtw89_release_mac_id(rtwdev, rtwsta->mac_id); 3577 3578 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3579 RTW89_ROLE_REMOVE); 3580 if (ret) { 3581 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3582 return ret; 3583 } 3584 3585 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3586 } 3587 3588 return 0; 3589 } 3590 3591 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3592 struct ieee80211_sta *sta, 3593 struct cfg80211_tid_cfg *tid_conf) 3594 { 3595 struct ieee80211_txq *txq; 3596 struct rtw89_txq *rtwtxq; 3597 u32 mask = tid_conf->mask; 3598 u8 tids = tid_conf->tids; 3599 int tids_nbit = BITS_PER_BYTE; 3600 int i; 3601 3602 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3603 if (!tids) 3604 break; 3605 3606 if (!(tids & BIT(0))) 3607 continue; 3608 3609 txq = sta->txq[i]; 3610 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3611 3612 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 3613 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 3614 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3615 } else { 3616 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 3617 ieee80211_stop_tx_ba_session(sta, txq->tid); 3618 spin_lock_bh(&rtwdev->ba_lock); 3619 list_del_init(&rtwtxq->list); 3620 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3621 spin_unlock_bh(&rtwdev->ba_lock); 3622 } 3623 } 3624 3625 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 3626 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 3627 sta->max_amsdu_subframes = 0; 3628 else 3629 sta->max_amsdu_subframes = 1; 3630 } 3631 } 3632 } 3633 3634 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3635 struct ieee80211_sta *sta, 3636 struct cfg80211_tid_config *tid_config) 3637 { 3638 int i; 3639 3640 for (i = 0; i < tid_config->n_tid_conf; i++) 3641 _rtw89_core_set_tid_config(rtwdev, sta, 3642 &tid_config->tid_conf[i]); 3643 } 3644 3645 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 3646 struct ieee80211_sta_ht_cap *ht_cap) 3647 { 3648 static const __le16 highest[RF_PATH_MAX] = { 3649 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 3650 }; 3651 struct rtw89_hal *hal = &rtwdev->hal; 3652 u8 nss = hal->rx_nss; 3653 int i; 3654 3655 ht_cap->ht_supported = true; 3656 ht_cap->cap = 0; 3657 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 3658 IEEE80211_HT_CAP_MAX_AMSDU | 3659 IEEE80211_HT_CAP_TX_STBC | 3660 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 3661 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 3662 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 3663 IEEE80211_HT_CAP_DSSSCCK40 | 3664 IEEE80211_HT_CAP_SGI_40; 3665 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 3666 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 3667 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 3668 for (i = 0; i < nss; i++) 3669 ht_cap->mcs.rx_mask[i] = 0xFF; 3670 ht_cap->mcs.rx_mask[4] = 0x01; 3671 ht_cap->mcs.rx_highest = highest[nss - 1]; 3672 } 3673 3674 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 3675 struct ieee80211_sta_vht_cap *vht_cap) 3676 { 3677 static const __le16 highest_bw80[RF_PATH_MAX] = { 3678 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 3679 }; 3680 static const __le16 highest_bw160[RF_PATH_MAX] = { 3681 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 3682 }; 3683 const struct rtw89_chip_info *chip = rtwdev->chip; 3684 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 3685 highest_bw160 : highest_bw80; 3686 struct rtw89_hal *hal = &rtwdev->hal; 3687 u16 tx_mcs_map = 0, rx_mcs_map = 0; 3688 u8 sts_cap = 3; 3689 int i; 3690 3691 for (i = 0; i < 8; i++) { 3692 if (i < hal->tx_nss) 3693 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3694 else 3695 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3696 if (i < hal->rx_nss) 3697 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3698 else 3699 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3700 } 3701 3702 vht_cap->vht_supported = true; 3703 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 3704 IEEE80211_VHT_CAP_SHORT_GI_80 | 3705 IEEE80211_VHT_CAP_RXSTBC_1 | 3706 IEEE80211_VHT_CAP_HTC_VHT | 3707 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 3708 0; 3709 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 3710 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 3711 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 3712 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 3713 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 3714 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3715 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 3716 IEEE80211_VHT_CAP_SHORT_GI_160; 3717 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 3718 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 3719 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 3720 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 3721 3722 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 3723 vht_cap->vht_mcs.tx_highest |= 3724 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 3725 } 3726 3727 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 3728 enum nl80211_band band, 3729 enum nl80211_iftype iftype, 3730 struct ieee80211_sband_iftype_data *iftype_data) 3731 { 3732 const struct rtw89_chip_info *chip = rtwdev->chip; 3733 struct rtw89_hal *hal = &rtwdev->hal; 3734 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 3735 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 3736 struct ieee80211_sta_he_cap *he_cap; 3737 int nss = hal->rx_nss; 3738 u8 *mac_cap_info; 3739 u8 *phy_cap_info; 3740 u16 mcs_map = 0; 3741 int i; 3742 3743 for (i = 0; i < 8; i++) { 3744 if (i < nss) 3745 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 3746 else 3747 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 3748 } 3749 3750 he_cap = &iftype_data->he_cap; 3751 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 3752 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 3753 3754 he_cap->has_he = true; 3755 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 3756 if (iftype == NL80211_IFTYPE_STATION) 3757 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 3758 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 3759 IEEE80211_HE_MAC_CAP2_BSR; 3760 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 3761 if (iftype == NL80211_IFTYPE_AP) 3762 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 3763 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 3764 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 3765 if (iftype == NL80211_IFTYPE_STATION) 3766 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 3767 if (band == NL80211_BAND_2GHZ) { 3768 phy_cap_info[0] = 3769 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 3770 } else { 3771 phy_cap_info[0] = 3772 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 3773 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3774 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 3775 } 3776 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 3777 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 3778 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 3779 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 3780 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 3781 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 3782 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 3783 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 3784 if (iftype == NL80211_IFTYPE_STATION) 3785 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 3786 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 3787 if (iftype == NL80211_IFTYPE_AP) 3788 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 3789 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 3790 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 3791 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3792 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 3793 phy_cap_info[5] = no_ng16 ? 0 : 3794 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 3795 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 3796 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 3797 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 3798 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 3799 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 3800 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 3801 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 3802 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 3803 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 3804 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 3805 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 3806 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3807 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 3808 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 3809 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 3810 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 3811 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 3812 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 3813 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 3814 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 3815 if (iftype == NL80211_IFTYPE_STATION) 3816 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 3817 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 3818 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 3819 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 3820 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 3821 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 3822 } 3823 3824 if (band == NL80211_BAND_6GHZ) { 3825 __le16 capa; 3826 3827 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 3828 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 3829 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 3830 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 3831 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 3832 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 3833 iftype_data->he_6ghz_capa.capa = capa; 3834 } 3835 } 3836 3837 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 3838 enum nl80211_band band, 3839 enum nl80211_iftype iftype, 3840 struct ieee80211_sband_iftype_data *iftype_data) 3841 { 3842 const struct rtw89_chip_info *chip = rtwdev->chip; 3843 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 3844 struct ieee80211_eht_mcs_nss_supp *eht_nss; 3845 struct ieee80211_sta_eht_cap *eht_cap; 3846 struct rtw89_hal *hal = &rtwdev->hal; 3847 bool support_320mhz = false; 3848 int sts = 8; 3849 u8 val; 3850 3851 if (chip->chip_gen == RTW89_CHIP_AX) 3852 return; 3853 3854 if (band == NL80211_BAND_6GHZ && 3855 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 3856 support_320mhz = true; 3857 3858 eht_cap = &iftype_data->eht_cap; 3859 eht_cap_elem = &eht_cap->eht_cap_elem; 3860 eht_nss = &eht_cap->eht_mcs_nss_supp; 3861 3862 eht_cap->has_eht = true; 3863 3864 eht_cap_elem->mac_cap_info[0] = 3865 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 3866 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 3867 eht_cap_elem->mac_cap_info[1] = 0; 3868 3869 eht_cap_elem->phy_cap_info[0] = 3870 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 3871 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 3872 if (support_320mhz) 3873 eht_cap_elem->phy_cap_info[0] |= 3874 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 3875 3876 eht_cap_elem->phy_cap_info[0] |= 3877 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 3878 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 3879 eht_cap_elem->phy_cap_info[1] = 3880 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 3881 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 3882 u8_encode_bits(sts - 1, 3883 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 3884 if (support_320mhz) 3885 eht_cap_elem->phy_cap_info[1] |= 3886 u8_encode_bits(sts - 1, 3887 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 3888 3889 eht_cap_elem->phy_cap_info[2] = 0; 3890 3891 eht_cap_elem->phy_cap_info[3] = 3892 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 3893 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 3894 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 3895 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 3896 3897 eht_cap_elem->phy_cap_info[4] = 3898 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 3899 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 3900 3901 eht_cap_elem->phy_cap_info[5] = 3902 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 3903 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 3904 3905 eht_cap_elem->phy_cap_info[6] = 0; 3906 eht_cap_elem->phy_cap_info[7] = 0; 3907 eht_cap_elem->phy_cap_info[8] = 0; 3908 3909 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 3910 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 3911 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 3912 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 3913 eht_nss->bw._80.rx_tx_mcs13_max_nss = val; 3914 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 3915 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 3916 eht_nss->bw._160.rx_tx_mcs13_max_nss = val; 3917 if (support_320mhz) { 3918 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 3919 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 3920 eht_nss->bw._320.rx_tx_mcs13_max_nss = val; 3921 } 3922 } 3923 3924 #define RTW89_SBAND_IFTYPES_NR 2 3925 3926 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 3927 enum nl80211_band band, 3928 struct ieee80211_supported_band *sband) 3929 { 3930 struct ieee80211_sband_iftype_data *iftype_data; 3931 enum nl80211_iftype iftype; 3932 int idx = 0; 3933 3934 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 3935 if (!iftype_data) 3936 return; 3937 3938 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 3939 switch (iftype) { 3940 case NL80211_IFTYPE_STATION: 3941 case NL80211_IFTYPE_AP: 3942 break; 3943 default: 3944 continue; 3945 } 3946 3947 if (idx >= RTW89_SBAND_IFTYPES_NR) { 3948 rtw89_warn(rtwdev, "run out of iftype_data\n"); 3949 break; 3950 } 3951 3952 iftype_data[idx].types_mask = BIT(iftype); 3953 3954 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 3955 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 3956 3957 idx++; 3958 } 3959 3960 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 3961 } 3962 3963 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 3964 { 3965 struct ieee80211_hw *hw = rtwdev->hw; 3966 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 3967 struct ieee80211_supported_band *sband_6ghz = NULL; 3968 u32 size = sizeof(struct ieee80211_supported_band); 3969 u8 support_bands = rtwdev->chip->support_bands; 3970 3971 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 3972 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 3973 if (!sband_2ghz) 3974 goto err; 3975 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 3976 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 3977 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 3978 } 3979 3980 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 3981 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 3982 if (!sband_5ghz) 3983 goto err; 3984 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 3985 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 3986 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 3987 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 3988 } 3989 3990 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 3991 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 3992 if (!sband_6ghz) 3993 goto err; 3994 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 3995 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 3996 } 3997 3998 return 0; 3999 4000 err: 4001 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4002 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4003 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4004 if (sband_2ghz) 4005 kfree((__force void *)sband_2ghz->iftype_data); 4006 if (sband_5ghz) 4007 kfree((__force void *)sband_5ghz->iftype_data); 4008 if (sband_6ghz) 4009 kfree((__force void *)sband_6ghz->iftype_data); 4010 kfree(sband_2ghz); 4011 kfree(sband_5ghz); 4012 kfree(sband_6ghz); 4013 return -ENOMEM; 4014 } 4015 4016 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 4017 { 4018 struct ieee80211_hw *hw = rtwdev->hw; 4019 4020 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 4021 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 4022 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 4023 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 4024 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 4025 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 4026 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 4027 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 4028 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 4029 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4030 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4031 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4032 } 4033 4034 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 4035 { 4036 int i; 4037 4038 for (i = 0; i < RTW89_PHY_MAX; i++) 4039 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4040 for (i = 0; i < RTW89_PHY_MAX; i++) 4041 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4042 } 4043 4044 void rtw89_core_update_beacon_work(struct work_struct *work) 4045 { 4046 struct rtw89_dev *rtwdev; 4047 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 4048 update_beacon_work); 4049 4050 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 4051 return; 4052 4053 rtwdev = rtwvif->rtwdev; 4054 mutex_lock(&rtwdev->mutex); 4055 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif); 4056 mutex_unlock(&rtwdev->mutex); 4057 } 4058 4059 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4060 { 4061 struct completion *cmpl = &wait->completion; 4062 unsigned long time_left; 4063 unsigned int cur; 4064 4065 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4066 if (cur != RTW89_WAIT_COND_IDLE) 4067 return -EBUSY; 4068 4069 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4070 if (time_left == 0) { 4071 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4072 return -ETIMEDOUT; 4073 } 4074 4075 if (wait->data.err) 4076 return -EFAULT; 4077 4078 return 0; 4079 } 4080 4081 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4082 const struct rtw89_completion_data *data) 4083 { 4084 unsigned int cur; 4085 4086 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4087 if (cur != cond) 4088 return; 4089 4090 wait->data = *data; 4091 complete(&wait->completion); 4092 } 4093 4094 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4095 { 4096 u16 bt_req_len; 4097 4098 switch (event) { 4099 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4100 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4101 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4102 "coex updates BT req len to %d TU\n", bt_req_len); 4103 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4104 break; 4105 default: 4106 if (event < NUM_OF_RTW89_BTC_HMSG) 4107 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4108 "unhandled BTC HMSG event: %d\n", event); 4109 else 4110 rtw89_warn(rtwdev, 4111 "unrecognized BTC HMSG event: %d\n", event); 4112 break; 4113 } 4114 } 4115 4116 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4117 { 4118 const struct dmi_system_id *match; 4119 enum rtw89_quirks quirk; 4120 4121 if (!quirks) 4122 return; 4123 4124 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4125 quirk = (uintptr_t)match->driver_data; 4126 if (quirk >= NUM_OF_RTW89_QUIRKS) 4127 continue; 4128 4129 set_bit(quirk, rtwdev->quirks); 4130 } 4131 } 4132 EXPORT_SYMBOL(rtw89_check_quirks); 4133 4134 int rtw89_core_start(struct rtw89_dev *rtwdev) 4135 { 4136 int ret; 4137 4138 ret = rtw89_mac_init(rtwdev); 4139 if (ret) { 4140 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4141 return ret; 4142 } 4143 4144 rtw89_btc_ntfy_poweron(rtwdev); 4145 4146 /* efuse process */ 4147 4148 /* pre-config BB/RF, BB reset/RFC reset */ 4149 ret = rtw89_chip_reset_bb_rf(rtwdev); 4150 if (ret) 4151 return ret; 4152 4153 rtw89_phy_init_bb_reg(rtwdev); 4154 rtw89_chip_bb_postinit(rtwdev); 4155 rtw89_phy_init_rf_reg(rtwdev, false); 4156 4157 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4158 4159 rtw89_phy_dm_init(rtwdev); 4160 4161 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 4162 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 4163 4164 rtw89_tas_reset(rtwdev); 4165 4166 ret = rtw89_hci_start(rtwdev); 4167 if (ret) { 4168 rtw89_err(rtwdev, "failed to start hci\n"); 4169 return ret; 4170 } 4171 4172 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 4173 RTW89_TRACK_WORK_PERIOD); 4174 4175 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4176 4177 rtw89_chip_rfk_init_late(rtwdev); 4178 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4179 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4180 rtw89_fw_h2c_init_ba_cam(rtwdev); 4181 4182 return 0; 4183 } 4184 4185 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4186 { 4187 struct rtw89_btc *btc = &rtwdev->btc; 4188 4189 /* Prvent to stop twice; enter_ips and ops_stop */ 4190 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4191 return; 4192 4193 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4194 4195 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4196 4197 mutex_unlock(&rtwdev->mutex); 4198 4199 cancel_work_sync(&rtwdev->c2h_work); 4200 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work); 4201 cancel_work_sync(&btc->eapol_notify_work); 4202 cancel_work_sync(&btc->arp_notify_work); 4203 cancel_work_sync(&btc->dhcp_notify_work); 4204 cancel_work_sync(&btc->icmp_notify_work); 4205 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4206 cancel_delayed_work_sync(&rtwdev->track_work); 4207 cancel_delayed_work_sync(&rtwdev->chanctx_work); 4208 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 4209 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 4210 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 4211 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 4212 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4213 cancel_delayed_work_sync(&rtwdev->antdiv_work); 4214 4215 mutex_lock(&rtwdev->mutex); 4216 4217 rtw89_btc_ntfy_poweroff(rtwdev); 4218 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4219 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4220 rtw89_hci_stop(rtwdev); 4221 rtw89_hci_deinit(rtwdev); 4222 rtw89_mac_pwr_off(rtwdev); 4223 rtw89_hci_reset(rtwdev); 4224 } 4225 4226 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 4227 { 4228 const struct rtw89_chip_info *chip = rtwdev->chip; 4229 u8 mac_id_num = chip->support_macid_num; 4230 u8 mac_id; 4231 4232 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 4233 if (mac_id == mac_id_num) 4234 return RTW89_MAX_MAC_ID_NUM; 4235 4236 set_bit(mac_id, rtwdev->mac_id_map); 4237 return mac_id; 4238 } 4239 4240 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 4241 { 4242 clear_bit(mac_id, rtwdev->mac_id_map); 4243 } 4244 4245 int rtw89_core_init(struct rtw89_dev *rtwdev) 4246 { 4247 struct rtw89_btc *btc = &rtwdev->btc; 4248 u8 band; 4249 4250 INIT_LIST_HEAD(&rtwdev->ba_list); 4251 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 4252 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 4253 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 4254 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 4255 if (!(rtwdev->chip->support_bands & BIT(band))) 4256 continue; 4257 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 4258 } 4259 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 4260 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 4261 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 4262 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 4263 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); 4264 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 4265 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 4266 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 4267 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 4268 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 4269 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 4270 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 4271 if (!rtwdev->txq_wq) 4272 return -ENOMEM; 4273 spin_lock_init(&rtwdev->ba_lock); 4274 spin_lock_init(&rtwdev->rpwm_lock); 4275 mutex_init(&rtwdev->mutex); 4276 mutex_init(&rtwdev->rf_mutex); 4277 rtwdev->total_sta_assoc = 0; 4278 4279 rtw89_init_wait(&rtwdev->mcc.wait); 4280 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 4281 4282 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 4283 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 4284 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 4285 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 4286 4287 skb_queue_head_init(&rtwdev->c2h_queue); 4288 rtw89_core_ppdu_sts_init(rtwdev); 4289 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 4290 4291 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 4292 rtwdev->dbcc_en = false; 4293 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 4294 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 4295 4296 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4297 rtwdev->dbcc_en = true; 4298 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 4299 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF; 4300 } 4301 4302 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 4303 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 4304 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 4305 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 4306 4307 init_completion(&rtwdev->fw.req.completion); 4308 init_completion(&rtwdev->rfk_wait.completion); 4309 4310 schedule_work(&rtwdev->load_firmware_work); 4311 4312 rtw89_ser_init(rtwdev); 4313 rtw89_entity_init(rtwdev); 4314 rtw89_tas_init(rtwdev); 4315 4316 return 0; 4317 } 4318 EXPORT_SYMBOL(rtw89_core_init); 4319 4320 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 4321 { 4322 rtw89_ser_deinit(rtwdev); 4323 rtw89_unload_firmware(rtwdev); 4324 rtw89_fw_free_all_early_h2c(rtwdev); 4325 4326 destroy_workqueue(rtwdev->txq_wq); 4327 mutex_destroy(&rtwdev->rf_mutex); 4328 mutex_destroy(&rtwdev->mutex); 4329 } 4330 EXPORT_SYMBOL(rtw89_core_deinit); 4331 4332 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4333 const u8 *mac_addr, bool hw_scan) 4334 { 4335 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4336 rtwvif->sub_entity_idx); 4337 4338 rtwdev->scanning = true; 4339 rtw89_leave_lps(rtwdev); 4340 if (hw_scan) 4341 rtw89_leave_ips_by_hwflags(rtwdev); 4342 4343 ether_addr_copy(rtwvif->mac_addr, mac_addr); 4344 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 4345 rtw89_chip_rfk_scan(rtwdev, true); 4346 rtw89_hci_recalc_int_mit(rtwdev); 4347 rtw89_phy_config_edcca(rtwdev, true); 4348 4349 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 4350 } 4351 4352 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4353 struct ieee80211_vif *vif, bool hw_scan) 4354 { 4355 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4356 4357 if (!rtwvif) 4358 return; 4359 4360 ether_addr_copy(rtwvif->mac_addr, vif->addr); 4361 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4362 4363 rtw89_chip_rfk_scan(rtwdev, false); 4364 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 4365 rtw89_phy_config_edcca(rtwdev, false); 4366 4367 rtwdev->scanning = false; 4368 rtwdev->dig.bypass_dig = true; 4369 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 4370 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 4371 } 4372 4373 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 4374 { 4375 const struct rtw89_chip_info *chip = rtwdev->chip; 4376 int ret; 4377 u8 val; 4378 u8 cv; 4379 4380 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 4381 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 4382 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 4383 cv = CHIP_CAV; 4384 else 4385 cv = CHIP_CBV; 4386 } 4387 4388 rtwdev->hal.cv = cv; 4389 4390 if (rtw89_is_rtl885xb(rtwdev)) { 4391 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 4392 if (ret) 4393 return; 4394 4395 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 4396 } 4397 } 4398 4399 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 4400 { 4401 rtwdev->hal.support_cckpd = 4402 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 4403 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 4404 rtwdev->hal.support_igi = 4405 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 4406 } 4407 4408 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 4409 { 4410 const struct rtw89_chip_info *chip = rtwdev->chip; 4411 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 4412 struct rtw89_efuse *efuse = &rtwdev->efuse; 4413 const struct rtw89_rfe_parms *sel; 4414 u8 rfe_type = efuse->rfe_type; 4415 4416 if (!conf) { 4417 sel = chip->dflt_parms; 4418 goto out; 4419 } 4420 4421 while (conf->rfe_parms) { 4422 if (rfe_type == conf->rfe_type) { 4423 sel = conf->rfe_parms; 4424 goto out; 4425 } 4426 conf++; 4427 } 4428 4429 sel = chip->dflt_parms; 4430 4431 out: 4432 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 4433 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 4434 } 4435 4436 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 4437 { 4438 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4439 int ret; 4440 4441 ret = rtw89_mac_partial_init(rtwdev, false); 4442 if (ret) 4443 return ret; 4444 4445 ret = mac->parse_efuse_map(rtwdev); 4446 if (ret) 4447 return ret; 4448 4449 ret = mac->parse_phycap_map(rtwdev); 4450 if (ret) 4451 return ret; 4452 4453 ret = rtw89_mac_setup_phycap(rtwdev); 4454 if (ret) 4455 return ret; 4456 4457 rtw89_core_setup_phycap(rtwdev); 4458 4459 rtw89_hci_mac_pre_deinit(rtwdev); 4460 4461 rtw89_mac_pwr_off(rtwdev); 4462 4463 return 0; 4464 } 4465 4466 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 4467 { 4468 rtw89_chip_fem_setup(rtwdev); 4469 4470 return 0; 4471 } 4472 4473 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 4474 { 4475 int ret; 4476 4477 rtw89_read_chip_ver(rtwdev); 4478 4479 ret = rtw89_wait_firmware_completion(rtwdev); 4480 if (ret) { 4481 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 4482 return ret; 4483 } 4484 4485 ret = rtw89_fw_recognize(rtwdev); 4486 if (ret) { 4487 rtw89_err(rtwdev, "failed to recognize firmware\n"); 4488 return ret; 4489 } 4490 4491 ret = rtw89_chip_efuse_info_setup(rtwdev); 4492 if (ret) 4493 return ret; 4494 4495 ret = rtw89_fw_recognize_elements(rtwdev); 4496 if (ret) { 4497 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 4498 return ret; 4499 } 4500 4501 ret = rtw89_chip_board_info_setup(rtwdev); 4502 if (ret) 4503 return ret; 4504 4505 rtw89_core_setup_rfe_parms(rtwdev); 4506 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 4507 4508 return 0; 4509 } 4510 EXPORT_SYMBOL(rtw89_chip_info_setup); 4511 4512 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 4513 { 4514 const struct rtw89_chip_info *chip = rtwdev->chip; 4515 struct ieee80211_hw *hw = rtwdev->hw; 4516 struct rtw89_efuse *efuse = &rtwdev->efuse; 4517 struct rtw89_hal *hal = &rtwdev->hal; 4518 int ret; 4519 int tx_headroom = IEEE80211_HT_CTL_LEN; 4520 4521 hw->vif_data_size = sizeof(struct rtw89_vif); 4522 hw->sta_data_size = sizeof(struct rtw89_sta); 4523 hw->txq_data_size = sizeof(struct rtw89_txq); 4524 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 4525 4526 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 4527 4528 hw->extra_tx_headroom = tx_headroom; 4529 hw->queues = IEEE80211_NUM_ACS; 4530 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 4531 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 4532 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 4533 4534 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 4535 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 4536 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 4537 4538 ieee80211_hw_set(hw, SIGNAL_DBM); 4539 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 4540 ieee80211_hw_set(hw, MFP_CAPABLE); 4541 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 4542 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 4543 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 4544 ieee80211_hw_set(hw, TX_AMSDU); 4545 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 4546 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 4547 ieee80211_hw_set(hw, SUPPORTS_PS); 4548 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 4549 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 4550 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 4551 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 4552 4553 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4554 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 4555 4556 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 4557 ieee80211_hw_set(hw, CONNECTION_MONITOR); 4558 4559 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 4560 BIT(NL80211_IFTYPE_AP) | 4561 BIT(NL80211_IFTYPE_P2P_CLIENT) | 4562 BIT(NL80211_IFTYPE_P2P_GO); 4563 4564 if (hal->ant_diversity) { 4565 hw->wiphy->available_antennas_tx = 0x3; 4566 hw->wiphy->available_antennas_rx = 0x3; 4567 } else { 4568 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 4569 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 4570 } 4571 4572 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 4573 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 4574 WIPHY_FLAG_AP_UAPSD | 4575 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 4576 4577 if (!chip->support_rnr) 4578 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 4579 4580 if (chip->chip_gen == RTW89_CHIP_BE) 4581 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 4582 4583 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 4584 4585 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 4586 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 4587 4588 #ifdef CONFIG_PM 4589 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 4590 #endif 4591 4592 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4593 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4594 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4595 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4596 hw->wiphy->max_remain_on_channel_duration = 1000; 4597 4598 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 4599 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 4600 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 4601 4602 ret = rtw89_core_set_supported_band(rtwdev); 4603 if (ret) { 4604 rtw89_err(rtwdev, "failed to set supported band\n"); 4605 return ret; 4606 } 4607 4608 ret = rtw89_regd_setup(rtwdev); 4609 if (ret) { 4610 rtw89_err(rtwdev, "failed to set up regd\n"); 4611 goto err_free_supported_band; 4612 } 4613 4614 hw->wiphy->sar_capa = &rtw89_sar_capa; 4615 4616 ret = ieee80211_register_hw(hw); 4617 if (ret) { 4618 rtw89_err(rtwdev, "failed to register hw\n"); 4619 goto err_free_supported_band; 4620 } 4621 4622 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 4623 if (ret) { 4624 rtw89_err(rtwdev, "failed to init regd\n"); 4625 goto err_unregister_hw; 4626 } 4627 4628 return 0; 4629 4630 err_unregister_hw: 4631 ieee80211_unregister_hw(hw); 4632 err_free_supported_band: 4633 rtw89_core_clr_supported_band(rtwdev); 4634 4635 return ret; 4636 } 4637 4638 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 4639 { 4640 struct ieee80211_hw *hw = rtwdev->hw; 4641 4642 ieee80211_unregister_hw(hw); 4643 rtw89_core_clr_supported_band(rtwdev); 4644 } 4645 4646 int rtw89_core_register(struct rtw89_dev *rtwdev) 4647 { 4648 int ret; 4649 4650 ret = rtw89_core_register_hw(rtwdev); 4651 if (ret) { 4652 rtw89_err(rtwdev, "failed to register core hw\n"); 4653 return ret; 4654 } 4655 4656 rtw89_debugfs_init(rtwdev); 4657 4658 return 0; 4659 } 4660 EXPORT_SYMBOL(rtw89_core_register); 4661 4662 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 4663 { 4664 rtw89_core_unregister_hw(rtwdev); 4665 } 4666 EXPORT_SYMBOL(rtw89_core_unregister); 4667 4668 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4669 u32 bus_data_size, 4670 const struct rtw89_chip_info *chip) 4671 { 4672 struct rtw89_fw_info early_fw = {}; 4673 const struct firmware *firmware; 4674 struct ieee80211_hw *hw; 4675 struct rtw89_dev *rtwdev; 4676 struct ieee80211_ops *ops; 4677 u32 driver_data_size; 4678 int fw_format = -1; 4679 bool no_chanctx; 4680 4681 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 4682 4683 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 4684 if (!ops) 4685 goto err; 4686 4687 no_chanctx = chip->support_chanctx_num == 0 || 4688 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 4689 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 4690 4691 if (no_chanctx) { 4692 ops->add_chanctx = ieee80211_emulate_add_chanctx; 4693 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 4694 ops->change_chanctx = ieee80211_emulate_change_chanctx; 4695 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 4696 ops->assign_vif_chanctx = NULL; 4697 ops->unassign_vif_chanctx = NULL; 4698 ops->remain_on_channel = NULL; 4699 ops->cancel_remain_on_channel = NULL; 4700 } 4701 4702 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 4703 hw = ieee80211_alloc_hw(driver_data_size, ops); 4704 if (!hw) 4705 goto err; 4706 4707 hw->wiphy->iface_combinations = rtw89_iface_combs; 4708 4709 if (no_chanctx || chip->support_chanctx_num == 1) 4710 hw->wiphy->n_iface_combinations = 1; 4711 else 4712 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 4713 4714 rtwdev = hw->priv; 4715 rtwdev->hw = hw; 4716 rtwdev->dev = device; 4717 rtwdev->ops = ops; 4718 rtwdev->chip = chip; 4719 rtwdev->fw.req.firmware = firmware; 4720 rtwdev->fw.fw_format = fw_format; 4721 4722 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 4723 no_chanctx ? "without" : "with"); 4724 4725 return rtwdev; 4726 4727 err: 4728 kfree(ops); 4729 release_firmware(firmware); 4730 return NULL; 4731 } 4732 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 4733 4734 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 4735 { 4736 kfree(rtwdev->ops); 4737 kfree(rtwdev->rfe_data); 4738 release_firmware(rtwdev->fw.req.firmware); 4739 ieee80211_free_hw(rtwdev->hw); 4740 } 4741 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 4742 4743 MODULE_AUTHOR("Realtek Corporation"); 4744 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 4745 MODULE_LICENSE("Dual BSD/GPL"); 4746