1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 #include "wow.h" 22 23 static bool rtw89_disable_ps_mode; 24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 26 27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 37 38 static struct ieee80211_channel rtw89_channels_2ghz[] = { 39 RTW89_DEF_CHAN_2G(2412, 1), 40 RTW89_DEF_CHAN_2G(2417, 2), 41 RTW89_DEF_CHAN_2G(2422, 3), 42 RTW89_DEF_CHAN_2G(2427, 4), 43 RTW89_DEF_CHAN_2G(2432, 5), 44 RTW89_DEF_CHAN_2G(2437, 6), 45 RTW89_DEF_CHAN_2G(2442, 7), 46 RTW89_DEF_CHAN_2G(2447, 8), 47 RTW89_DEF_CHAN_2G(2452, 9), 48 RTW89_DEF_CHAN_2G(2457, 10), 49 RTW89_DEF_CHAN_2G(2462, 11), 50 RTW89_DEF_CHAN_2G(2467, 12), 51 RTW89_DEF_CHAN_2G(2472, 13), 52 RTW89_DEF_CHAN_2G(2484, 14), 53 }; 54 55 static struct ieee80211_channel rtw89_channels_5ghz[] = { 56 RTW89_DEF_CHAN_5G(5180, 36), 57 RTW89_DEF_CHAN_5G(5200, 40), 58 RTW89_DEF_CHAN_5G(5220, 44), 59 RTW89_DEF_CHAN_5G(5240, 48), 60 RTW89_DEF_CHAN_5G(5260, 52), 61 RTW89_DEF_CHAN_5G(5280, 56), 62 RTW89_DEF_CHAN_5G(5300, 60), 63 RTW89_DEF_CHAN_5G(5320, 64), 64 RTW89_DEF_CHAN_5G(5500, 100), 65 RTW89_DEF_CHAN_5G(5520, 104), 66 RTW89_DEF_CHAN_5G(5540, 108), 67 RTW89_DEF_CHAN_5G(5560, 112), 68 RTW89_DEF_CHAN_5G(5580, 116), 69 RTW89_DEF_CHAN_5G(5600, 120), 70 RTW89_DEF_CHAN_5G(5620, 124), 71 RTW89_DEF_CHAN_5G(5640, 128), 72 RTW89_DEF_CHAN_5G(5660, 132), 73 RTW89_DEF_CHAN_5G(5680, 136), 74 RTW89_DEF_CHAN_5G(5700, 140), 75 RTW89_DEF_CHAN_5G(5720, 144), 76 RTW89_DEF_CHAN_5G(5745, 149), 77 RTW89_DEF_CHAN_5G(5765, 153), 78 RTW89_DEF_CHAN_5G(5785, 157), 79 RTW89_DEF_CHAN_5G(5805, 161), 80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 81 RTW89_DEF_CHAN_5G(5845, 169), 82 RTW89_DEF_CHAN_5G(5865, 173), 83 RTW89_DEF_CHAN_5G(5885, 177), 84 }; 85 86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 87 ARRAY_SIZE(rtw89_channels_5ghz)); 88 89 static struct ieee80211_channel rtw89_channels_6ghz[] = { 90 RTW89_DEF_CHAN_6G(5955, 1), 91 RTW89_DEF_CHAN_6G(5975, 5), 92 RTW89_DEF_CHAN_6G(5995, 9), 93 RTW89_DEF_CHAN_6G(6015, 13), 94 RTW89_DEF_CHAN_6G(6035, 17), 95 RTW89_DEF_CHAN_6G(6055, 21), 96 RTW89_DEF_CHAN_6G(6075, 25), 97 RTW89_DEF_CHAN_6G(6095, 29), 98 RTW89_DEF_CHAN_6G(6115, 33), 99 RTW89_DEF_CHAN_6G(6135, 37), 100 RTW89_DEF_CHAN_6G(6155, 41), 101 RTW89_DEF_CHAN_6G(6175, 45), 102 RTW89_DEF_CHAN_6G(6195, 49), 103 RTW89_DEF_CHAN_6G(6215, 53), 104 RTW89_DEF_CHAN_6G(6235, 57), 105 RTW89_DEF_CHAN_6G(6255, 61), 106 RTW89_DEF_CHAN_6G(6275, 65), 107 RTW89_DEF_CHAN_6G(6295, 69), 108 RTW89_DEF_CHAN_6G(6315, 73), 109 RTW89_DEF_CHAN_6G(6335, 77), 110 RTW89_DEF_CHAN_6G(6355, 81), 111 RTW89_DEF_CHAN_6G(6375, 85), 112 RTW89_DEF_CHAN_6G(6395, 89), 113 RTW89_DEF_CHAN_6G(6415, 93), 114 RTW89_DEF_CHAN_6G(6435, 97), 115 RTW89_DEF_CHAN_6G(6455, 101), 116 RTW89_DEF_CHAN_6G(6475, 105), 117 RTW89_DEF_CHAN_6G(6495, 109), 118 RTW89_DEF_CHAN_6G(6515, 113), 119 RTW89_DEF_CHAN_6G(6535, 117), 120 RTW89_DEF_CHAN_6G(6555, 121), 121 RTW89_DEF_CHAN_6G(6575, 125), 122 RTW89_DEF_CHAN_6G(6595, 129), 123 RTW89_DEF_CHAN_6G(6615, 133), 124 RTW89_DEF_CHAN_6G(6635, 137), 125 RTW89_DEF_CHAN_6G(6655, 141), 126 RTW89_DEF_CHAN_6G(6675, 145), 127 RTW89_DEF_CHAN_6G(6695, 149), 128 RTW89_DEF_CHAN_6G(6715, 153), 129 RTW89_DEF_CHAN_6G(6735, 157), 130 RTW89_DEF_CHAN_6G(6755, 161), 131 RTW89_DEF_CHAN_6G(6775, 165), 132 RTW89_DEF_CHAN_6G(6795, 169), 133 RTW89_DEF_CHAN_6G(6815, 173), 134 RTW89_DEF_CHAN_6G(6835, 177), 135 RTW89_DEF_CHAN_6G(6855, 181), 136 RTW89_DEF_CHAN_6G(6875, 185), 137 RTW89_DEF_CHAN_6G(6895, 189), 138 RTW89_DEF_CHAN_6G(6915, 193), 139 RTW89_DEF_CHAN_6G(6935, 197), 140 RTW89_DEF_CHAN_6G(6955, 201), 141 RTW89_DEF_CHAN_6G(6975, 205), 142 RTW89_DEF_CHAN_6G(6995, 209), 143 RTW89_DEF_CHAN_6G(7015, 213), 144 RTW89_DEF_CHAN_6G(7035, 217), 145 RTW89_DEF_CHAN_6G(7055, 221), 146 RTW89_DEF_CHAN_6G(7075, 225), 147 RTW89_DEF_CHAN_6G(7095, 229), 148 RTW89_DEF_CHAN_6G(7115, 233), 149 }; 150 151 static struct ieee80211_rate rtw89_bitrates[] = { 152 { .bitrate = 10, .hw_value = 0x00, }, 153 { .bitrate = 20, .hw_value = 0x01, }, 154 { .bitrate = 55, .hw_value = 0x02, }, 155 { .bitrate = 110, .hw_value = 0x03, }, 156 { .bitrate = 60, .hw_value = 0x04, }, 157 { .bitrate = 90, .hw_value = 0x05, }, 158 { .bitrate = 120, .hw_value = 0x06, }, 159 { .bitrate = 180, .hw_value = 0x07, }, 160 { .bitrate = 240, .hw_value = 0x08, }, 161 { .bitrate = 360, .hw_value = 0x09, }, 162 { .bitrate = 480, .hw_value = 0x0a, }, 163 { .bitrate = 540, .hw_value = 0x0b, }, 164 }; 165 166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_STATION), 170 }, 171 { 172 .max = 1, 173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 174 BIT(NL80211_IFTYPE_P2P_GO) | 175 BIT(NL80211_IFTYPE_AP), 176 }, 177 }; 178 179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_STATION), 183 }, 184 { 185 .max = 1, 186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 187 BIT(NL80211_IFTYPE_P2P_GO), 188 }, 189 }; 190 191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 192 { 193 .limits = rtw89_iface_limits, 194 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 195 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 196 .num_different_channels = 1, 197 }, 198 { 199 .limits = rtw89_iface_limits_mcc, 200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 201 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 202 .num_different_channels = 2, 203 }, 204 }; 205 206 #define RTW89_6GHZ_SPAN_HEAD 6145 207 #define RTW89_6GHZ_SPAN_IDX(center_freq) \ 208 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2) 209 210 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \ 211 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \ 212 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \ 213 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \ 214 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \ 215 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \ 216 } 217 218 /* Since 6GHz subbands are not edge aligned, some cases span two subbands. 219 * In the following, we describe each of them with rtw89_6ghz_span. 220 */ 221 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = { 222 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H), 223 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H), 224 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H), 225 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L), 226 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L), 227 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L), 228 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H), 229 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H), 230 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8), 231 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8), 232 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8), 233 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8), 234 }; 235 236 const struct rtw89_6ghz_span * 237 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq) 238 { 239 int idx; 240 241 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) { 242 idx = RTW89_6GHZ_SPAN_IDX(center_freq); 243 /* To decrease size of rtw89_overlapping_6ghz[], 244 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs 245 * to make first span as index 0 of the table. So, if center 246 * frequency is less than the first one, it will get netative. 247 */ 248 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz)) 249 return &rtw89_overlapping_6ghz[idx]; 250 } 251 252 return NULL; 253 } 254 255 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 256 { 257 struct ieee80211_rate rate; 258 259 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 260 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 261 return false; 262 } 263 264 rate = rtw89_bitrates[rpt_rate]; 265 *bitrate = rate.bitrate; 266 267 return true; 268 } 269 270 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 271 .band = NL80211_BAND_2GHZ, 272 .channels = rtw89_channels_2ghz, 273 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 274 .bitrates = rtw89_bitrates, 275 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 276 .ht_cap = {0}, 277 .vht_cap = {0}, 278 }; 279 280 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 281 .band = NL80211_BAND_5GHZ, 282 .channels = rtw89_channels_5ghz, 283 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 284 285 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 286 .bitrates = rtw89_bitrates + 4, 287 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 288 .ht_cap = {0}, 289 .vht_cap = {0}, 290 }; 291 292 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 293 .band = NL80211_BAND_6GHZ, 294 .channels = rtw89_channels_6ghz, 295 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 296 297 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 298 .bitrates = rtw89_bitrates + 4, 299 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 300 }; 301 302 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 303 struct rtw89_traffic_stats *stats, 304 struct sk_buff *skb, bool tx) 305 { 306 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 307 308 if (tx && ieee80211_is_assoc_req(hdr->frame_control)) 309 rtw89_wow_parse_akm(rtwdev, skb); 310 311 if (!ieee80211_is_data(hdr->frame_control)) 312 return; 313 314 if (is_broadcast_ether_addr(hdr->addr1) || 315 is_multicast_ether_addr(hdr->addr1)) 316 return; 317 318 if (tx) { 319 stats->tx_cnt++; 320 stats->tx_unicast += skb->len; 321 } else { 322 stats->rx_cnt++; 323 stats->rx_unicast += skb->len; 324 } 325 } 326 327 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 328 { 329 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 330 NL80211_CHAN_NO_HT); 331 } 332 333 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 334 struct rtw89_chan *chan) 335 { 336 struct ieee80211_channel *channel = chandef->chan; 337 enum nl80211_chan_width width = chandef->width; 338 u32 primary_freq, center_freq; 339 u8 center_chan; 340 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 341 u32 offset; 342 u8 band; 343 344 center_chan = channel->hw_value; 345 primary_freq = channel->center_freq; 346 center_freq = chandef->center_freq1; 347 348 switch (width) { 349 case NL80211_CHAN_WIDTH_20_NOHT: 350 case NL80211_CHAN_WIDTH_20: 351 bandwidth = RTW89_CHANNEL_WIDTH_20; 352 break; 353 case NL80211_CHAN_WIDTH_40: 354 bandwidth = RTW89_CHANNEL_WIDTH_40; 355 if (primary_freq > center_freq) { 356 center_chan -= 2; 357 } else { 358 center_chan += 2; 359 } 360 break; 361 case NL80211_CHAN_WIDTH_80: 362 case NL80211_CHAN_WIDTH_160: 363 bandwidth = nl_to_rtw89_bandwidth(width); 364 if (primary_freq > center_freq) { 365 offset = (primary_freq - center_freq - 10) / 20; 366 center_chan -= 2 + offset * 4; 367 } else { 368 offset = (center_freq - primary_freq - 10) / 20; 369 center_chan += 2 + offset * 4; 370 } 371 break; 372 default: 373 center_chan = 0; 374 break; 375 } 376 377 switch (channel->band) { 378 default: 379 case NL80211_BAND_2GHZ: 380 band = RTW89_BAND_2G; 381 break; 382 case NL80211_BAND_5GHZ: 383 band = RTW89_BAND_5G; 384 break; 385 case NL80211_BAND_6GHZ: 386 band = RTW89_BAND_6G; 387 break; 388 } 389 390 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 391 } 392 393 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev, 394 const struct rtw89_chan *chan, 395 enum rtw89_phy_idx phy_idx) 396 { 397 const struct rtw89_chip_info *chip = rtwdev->chip; 398 bool entity_active; 399 400 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 401 if (!entity_active) 402 return; 403 404 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 405 } 406 407 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 408 { 409 const struct rtw89_chan *chan; 410 411 chan = rtw89_mgnt_chan_get(rtwdev, 0); 412 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0); 413 414 if (!rtwdev->support_mlo) 415 return; 416 417 chan = rtw89_mgnt_chan_get(rtwdev, 1); 418 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1); 419 } 420 421 static void __rtw89_set_channel(struct rtw89_dev *rtwdev, 422 const struct rtw89_chan *chan, 423 enum rtw89_mac_idx mac_idx, 424 enum rtw89_phy_idx phy_idx) 425 { 426 const struct rtw89_chip_info *chip = rtwdev->chip; 427 const struct rtw89_chan_rcd *chan_rcd; 428 struct rtw89_channel_help_params bak; 429 bool entity_active; 430 431 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 432 433 chan_rcd = rtw89_chan_rcd_get_by_chan(chan); 434 435 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 436 437 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 438 439 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 440 441 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 442 443 if (!entity_active || chan_rcd->band_changed) { 444 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 445 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan); 446 } 447 448 rtw89_set_entity_state(rtwdev, phy_idx, true); 449 } 450 451 int rtw89_set_channel(struct rtw89_dev *rtwdev) 452 { 453 const struct rtw89_chan *chan; 454 enum rtw89_entity_mode mode; 455 456 mode = rtw89_entity_recalc(rtwdev); 457 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) { 458 WARN(1, "Invalid ent mode: %d\n", mode); 459 return -EINVAL; 460 } 461 462 chan = rtw89_mgnt_chan_get(rtwdev, 0); 463 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0); 464 465 if (!rtwdev->support_mlo) 466 return 0; 467 468 chan = rtw89_mgnt_chan_get(rtwdev, 1); 469 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1); 470 471 return 0; 472 } 473 474 static enum rtw89_core_tx_type 475 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 476 struct sk_buff *skb) 477 { 478 struct ieee80211_hdr *hdr = (void *)skb->data; 479 __le16 fc = hdr->frame_control; 480 481 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 482 return RTW89_CORE_TX_TYPE_MGMT; 483 484 return RTW89_CORE_TX_TYPE_DATA; 485 } 486 487 static void 488 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 489 struct rtw89_core_tx_request *tx_req, 490 enum btc_pkt_type pkt_type) 491 { 492 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 493 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 494 struct ieee80211_link_sta *link_sta; 495 struct sk_buff *skb = tx_req->skb; 496 struct rtw89_sta *rtwsta; 497 u8 ampdu_num; 498 u8 tid; 499 500 if (pkt_type == PACKET_EAPOL) { 501 desc_info->bk = true; 502 return; 503 } 504 505 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 506 return; 507 508 if (!rtwsta_link) { 509 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 510 return; 511 } 512 513 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 514 rtwsta = rtwsta_link->rtwsta; 515 516 rcu_read_lock(); 517 518 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 519 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 520 rtwsta->ampdu_params[tid].agg_num : 521 4 << link_sta->ht_cap.ampdu_factor) - 1); 522 523 desc_info->agg_en = true; 524 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density; 525 desc_info->ampdu_num = ampdu_num; 526 527 rcu_read_unlock(); 528 } 529 530 static void 531 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 532 struct rtw89_core_tx_request *tx_req) 533 { 534 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 535 const struct rtw89_chip_info *chip = rtwdev->chip; 536 const struct rtw89_sec_cam_entry *sec_cam; 537 struct ieee80211_tx_info *info; 538 struct ieee80211_key_conf *key; 539 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 540 struct sk_buff *skb = tx_req->skb; 541 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 542 u8 sec_cam_idx; 543 u64 pn64; 544 545 info = IEEE80211_SKB_CB(skb); 546 key = info->control.hw_key; 547 sec_cam_idx = key->hw_key_idx; 548 sec_cam = cam_info->sec_entries[sec_cam_idx]; 549 if (!sec_cam) { 550 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 551 return; 552 } 553 554 switch (key->cipher) { 555 case WLAN_CIPHER_SUITE_WEP40: 556 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 557 break; 558 case WLAN_CIPHER_SUITE_WEP104: 559 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 560 break; 561 case WLAN_CIPHER_SUITE_TKIP: 562 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 563 break; 564 case WLAN_CIPHER_SUITE_CCMP: 565 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 566 break; 567 case WLAN_CIPHER_SUITE_CCMP_256: 568 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 569 break; 570 case WLAN_CIPHER_SUITE_GCMP: 571 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 572 break; 573 case WLAN_CIPHER_SUITE_GCMP_256: 574 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 575 break; 576 default: 577 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 578 return; 579 } 580 581 desc_info->sec_en = true; 582 desc_info->sec_keyid = key->keyidx; 583 desc_info->sec_type = sec_type; 584 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 585 586 if (!chip->hw_sec_hdr) 587 return; 588 589 pn64 = atomic64_inc_return(&key->tx_pn); 590 desc_info->sec_seq[0] = pn64; 591 desc_info->sec_seq[1] = pn64 >> 8; 592 desc_info->sec_seq[2] = pn64 >> 16; 593 desc_info->sec_seq[3] = pn64 >> 24; 594 desc_info->sec_seq[4] = pn64 >> 32; 595 desc_info->sec_seq[5] = pn64 >> 40; 596 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 597 } 598 599 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 600 struct rtw89_core_tx_request *tx_req, 601 const struct rtw89_chan *chan) 602 { 603 struct sk_buff *skb = tx_req->skb; 604 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 605 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 606 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 607 struct ieee80211_vif *vif = tx_info->control.vif; 608 struct ieee80211_bss_conf *bss_conf; 609 u16 lowest_rate; 610 u16 rate; 611 612 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 613 (vif && vif->p2p)) 614 lowest_rate = RTW89_HW_RATE_OFDM6; 615 else if (chan->band_type == RTW89_BAND_2G) 616 lowest_rate = RTW89_HW_RATE_CCK1; 617 else 618 lowest_rate = RTW89_HW_RATE_OFDM6; 619 620 if (!rtwvif_link) 621 return lowest_rate; 622 623 rcu_read_lock(); 624 625 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 626 if (!bss_conf->basic_rates || !rtwsta_link) { 627 rate = lowest_rate; 628 goto out; 629 } 630 631 rate = __ffs(bss_conf->basic_rates) + lowest_rate; 632 633 out: 634 rcu_read_unlock(); 635 636 return rate; 637 } 638 639 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 640 struct rtw89_core_tx_request *tx_req) 641 { 642 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 643 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 644 645 if (!rtwsta_link) 646 return rtwvif_link->mac_id; 647 648 return rtwsta_link->mac_id; 649 } 650 651 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 652 struct rtw89_tx_desc_info *desc_info, 653 struct sk_buff *skb) 654 { 655 struct ieee80211_hdr *hdr = (void *)skb->data; 656 __le16 fc = hdr->frame_control; 657 658 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 659 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 660 } 661 662 static void 663 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 664 struct rtw89_core_tx_request *tx_req) 665 { 666 const struct rtw89_chip_info *chip = rtwdev->chip; 667 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 668 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 669 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 670 rtwvif_link->chanctx_idx); 671 struct sk_buff *skb = tx_req->skb; 672 u8 qsel, ch_dma; 673 674 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 675 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 676 677 desc_info->qsel = qsel; 678 desc_info->ch_dma = ch_dma; 679 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 680 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 681 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 682 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 683 684 /* fixed data rate for mgmt frames */ 685 desc_info->en_wd_info = true; 686 desc_info->use_rate = true; 687 desc_info->dis_data_fb = true; 688 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 689 690 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) { 691 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 692 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 693 } 694 695 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 696 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 697 desc_info->data_rate, chan->channel, chan->band_type, 698 chan->band_width); 699 } 700 701 static void 702 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 703 struct rtw89_core_tx_request *tx_req) 704 { 705 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 706 707 desc_info->is_bmc = false; 708 desc_info->wd_page = false; 709 desc_info->ch_dma = RTW89_DMA_H2C; 710 } 711 712 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 713 const struct rtw89_chan *chan) 714 { 715 static const u8 rtw89_bandwidth_to_om[] = { 716 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 717 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 718 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 719 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 720 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 721 }; 722 const struct rtw89_chip_info *chip = rtwdev->chip; 723 struct rtw89_hal *hal = &rtwdev->hal; 724 u8 om_bandwidth; 725 726 if (!chip->dis_2g_40m_ul_ofdma || 727 chan->band_type != RTW89_BAND_2G || 728 chan->band_width != RTW89_CHANNEL_WIDTH_40) 729 return; 730 731 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 732 rtw89_bandwidth_to_om[chan->band_width] : 0; 733 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 734 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 735 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 736 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 737 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 738 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 739 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 740 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 741 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 742 } 743 744 static bool 745 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 746 struct rtw89_core_tx_request *tx_req, 747 enum btc_pkt_type pkt_type) 748 { 749 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 750 struct sk_buff *skb = tx_req->skb; 751 struct ieee80211_hdr *hdr = (void *)skb->data; 752 struct ieee80211_link_sta *link_sta; 753 __le16 fc = hdr->frame_control; 754 755 /* AP IOT issue with EAPoL, ARP and DHCP */ 756 if (pkt_type < PACKET_MAX) 757 return false; 758 759 if (!rtwsta_link) 760 return false; 761 762 rcu_read_lock(); 763 764 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 765 if (!link_sta->he_cap.has_he) { 766 rcu_read_unlock(); 767 return false; 768 } 769 770 rcu_read_unlock(); 771 772 if (!ieee80211_is_data_qos(fc)) 773 return false; 774 775 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 776 return false; 777 778 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy) 779 return false; 780 781 return true; 782 } 783 784 static void 785 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 786 struct rtw89_core_tx_request *tx_req) 787 { 788 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 789 struct sk_buff *skb = tx_req->skb; 790 struct ieee80211_hdr *hdr = (void *)skb->data; 791 __le16 fc = hdr->frame_control; 792 void *data; 793 __le32 *htc; 794 u8 *qc; 795 int hdr_len; 796 797 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 798 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 799 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 800 801 hdr = data; 802 htc = data + hdr_len; 803 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 804 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template : 805 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 806 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 807 808 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 809 qc[0] |= IEEE80211_QOS_CTL_EOSP; 810 } 811 812 static void 813 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 814 struct rtw89_core_tx_request *tx_req, 815 enum btc_pkt_type pkt_type) 816 { 817 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 818 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 819 820 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 821 goto desc_bk; 822 823 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 824 825 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 826 desc_info->a_ctrl_bsr = true; 827 828 desc_bk: 829 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr) 830 return; 831 832 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr; 833 desc_info->bk = true; 834 } 835 836 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 837 struct rtw89_core_tx_request *tx_req) 838 { 839 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 840 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 841 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 842 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 843 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx; 844 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 845 struct ieee80211_link_sta *link_sta; 846 u16 lowest_rate; 847 u16 rate; 848 849 if (rate_pattern->enable) 850 return rate_pattern->rate; 851 852 if (vif->p2p) 853 lowest_rate = RTW89_HW_RATE_OFDM6; 854 else if (chan->band_type == RTW89_BAND_2G) 855 lowest_rate = RTW89_HW_RATE_CCK1; 856 else 857 lowest_rate = RTW89_HW_RATE_OFDM6; 858 859 if (!rtwsta_link) 860 return lowest_rate; 861 862 rcu_read_lock(); 863 864 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 865 if (!link_sta->supp_rates[chan->band_type]) { 866 rate = lowest_rate; 867 goto out; 868 } 869 870 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate; 871 872 out: 873 rcu_read_unlock(); 874 875 return rate; 876 } 877 878 static void 879 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 880 struct rtw89_core_tx_request *tx_req) 881 { 882 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 883 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 884 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 885 struct sk_buff *skb = tx_req->skb; 886 u8 tid, tid_indicate; 887 u8 qsel, ch_dma; 888 889 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 890 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 891 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 892 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 893 894 desc_info->ch_dma = ch_dma; 895 desc_info->tid_indicate = tid_indicate; 896 desc_info->qsel = qsel; 897 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 898 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 899 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false; 900 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false; 901 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false; 902 903 /* enable wd_info for AMPDU */ 904 desc_info->en_wd_info = true; 905 906 if (IEEE80211_SKB_CB(skb)->control.hw_key) 907 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 908 909 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 910 } 911 912 static enum btc_pkt_type 913 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 914 struct rtw89_core_tx_request *tx_req) 915 { 916 struct sk_buff *skb = tx_req->skb; 917 struct udphdr *udphdr; 918 919 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 920 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 921 return PACKET_EAPOL; 922 } 923 924 if (skb->protocol == htons(ETH_P_ARP)) { 925 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 926 return PACKET_ARP; 927 } 928 929 if (skb->protocol == htons(ETH_P_IP) && 930 ip_hdr(skb)->protocol == IPPROTO_UDP) { 931 udphdr = udp_hdr(skb); 932 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 933 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 934 skb->len > 282) { 935 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 936 return PACKET_DHCP; 937 } 938 } 939 940 if (skb->protocol == htons(ETH_P_IP) && 941 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 942 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 943 return PACKET_ICMP; 944 } 945 946 return PACKET_MAX; 947 } 948 949 static void 950 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 951 struct rtw89_core_tx_request *tx_req) 952 { 953 const struct rtw89_chip_info *chip = rtwdev->chip; 954 955 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 956 return; 957 958 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 959 return; 960 961 if (chip->chip_id != RTL8852C && 962 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 963 return; 964 965 rtw89_mac_notify_wake(rtwdev); 966 } 967 968 static void 969 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 970 struct rtw89_core_tx_request *tx_req) 971 { 972 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 973 struct sk_buff *skb = tx_req->skb; 974 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 975 struct ieee80211_hdr *hdr = (void *)skb->data; 976 struct rtw89_addr_cam_entry *addr_cam; 977 enum rtw89_core_tx_type tx_type; 978 enum btc_pkt_type pkt_type; 979 bool upd_wlan_hdr = false; 980 bool is_bmc; 981 u16 seq; 982 983 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 984 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 985 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 986 tx_req->tx_type = tx_type; 987 988 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link, 989 tx_req->rtwsta_link); 990 if (addr_cam->valid) 991 upd_wlan_hdr = true; 992 } 993 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 994 is_multicast_ether_addr(hdr->addr1)); 995 996 desc_info->seq = seq; 997 desc_info->pkt_size = skb->len; 998 desc_info->is_bmc = is_bmc; 999 desc_info->wd_page = true; 1000 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 1001 desc_info->upd_wlan_hdr = upd_wlan_hdr; 1002 1003 switch (tx_req->tx_type) { 1004 case RTW89_CORE_TX_TYPE_MGMT: 1005 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 1006 break; 1007 case RTW89_CORE_TX_TYPE_DATA: 1008 rtw89_core_tx_update_data_info(rtwdev, tx_req); 1009 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 1010 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 1011 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 1012 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 1013 break; 1014 case RTW89_CORE_TX_TYPE_FWCMD: 1015 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 1016 break; 1017 } 1018 } 1019 1020 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 1021 { 1022 u8 ch_dma; 1023 1024 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 1025 1026 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 1027 } 1028 1029 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1030 int qsel, unsigned int timeout) 1031 { 1032 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1033 struct rtw89_tx_wait_info *wait; 1034 unsigned long time_left; 1035 int ret = 0; 1036 1037 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 1038 if (!wait) { 1039 rtw89_core_tx_kick_off(rtwdev, qsel); 1040 return 0; 1041 } 1042 1043 init_completion(&wait->completion); 1044 rcu_assign_pointer(skb_data->wait, wait); 1045 1046 rtw89_core_tx_kick_off(rtwdev, qsel); 1047 time_left = wait_for_completion_timeout(&wait->completion, 1048 msecs_to_jiffies(timeout)); 1049 if (time_left == 0) 1050 ret = -ETIMEDOUT; 1051 else if (!wait->tx_done) 1052 ret = -EAGAIN; 1053 1054 rcu_assign_pointer(skb_data->wait, NULL); 1055 kfree_rcu(wait, rcu_head); 1056 1057 return ret; 1058 } 1059 1060 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 1061 struct sk_buff *skb, bool fwdl) 1062 { 1063 struct rtw89_core_tx_request tx_req = {0}; 1064 u32 cnt; 1065 int ret; 1066 1067 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 1068 rtw89_debug(rtwdev, RTW89_DBG_FW, 1069 "ignore h2c due to power is off with firmware state=%d\n", 1070 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 1071 dev_kfree_skb(skb); 1072 return 0; 1073 } 1074 1075 tx_req.skb = skb; 1076 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1077 if (fwdl) 1078 tx_req.desc_info.fw_dl = true; 1079 1080 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1081 1082 if (!fwdl) 1083 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1084 1085 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1086 if (cnt == 0) { 1087 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1088 return -ENOSPC; 1089 } 1090 1091 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1092 if (ret) { 1093 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1094 return ret; 1095 } 1096 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1097 1098 return 0; 1099 } 1100 1101 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1102 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1103 { 1104 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1105 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 1106 struct rtw89_core_tx_request tx_req = {0}; 1107 struct rtw89_sta_link *rtwsta_link = NULL; 1108 struct rtw89_vif_link *rtwvif_link; 1109 int ret; 1110 1111 /* By default, driver writes tx via the link on HW-0. And then, 1112 * according to links' status, HW can change tx to another link. 1113 */ 1114 1115 if (rtwsta) { 1116 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0); 1117 if (unlikely(!rtwsta_link)) { 1118 rtw89_err(rtwdev, "tx: find no sta link on HW-0\n"); 1119 return -ENOLINK; 1120 } 1121 } 1122 1123 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0); 1124 if (unlikely(!rtwvif_link)) { 1125 rtw89_err(rtwdev, "tx: find no vif link on HW-0\n"); 1126 return -ENOLINK; 1127 } 1128 1129 tx_req.skb = skb; 1130 tx_req.rtwvif_link = rtwvif_link; 1131 tx_req.rtwsta_link = rtwsta_link; 1132 1133 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1134 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1135 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1136 rtw89_core_tx_wake(rtwdev, &tx_req); 1137 1138 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1139 if (ret) { 1140 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1141 return ret; 1142 } 1143 1144 if (qsel) 1145 *qsel = tx_req.desc_info.qsel; 1146 1147 return 0; 1148 } 1149 1150 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1151 { 1152 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1153 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1154 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1155 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1156 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1157 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1158 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1159 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1160 1161 return cpu_to_le32(dword); 1162 } 1163 1164 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1165 { 1166 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1167 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1168 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1169 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1170 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1171 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1172 1173 return cpu_to_le32(dword); 1174 } 1175 1176 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1177 { 1178 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1179 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1180 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1181 1182 return cpu_to_le32(dword); 1183 } 1184 1185 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1186 { 1187 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1188 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1189 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1190 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1191 1192 return cpu_to_le32(dword); 1193 } 1194 1195 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1196 { 1197 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1198 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1199 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1200 1201 return cpu_to_le32(dword); 1202 } 1203 1204 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1205 { 1206 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1207 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1208 1209 return cpu_to_le32(dword); 1210 } 1211 1212 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1213 { 1214 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1215 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1216 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1217 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1218 1219 return cpu_to_le32(dword); 1220 } 1221 1222 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1223 { 1224 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1225 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1226 1227 return cpu_to_le32(dword); 1228 } 1229 1230 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1231 { 1232 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1233 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1234 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1235 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1236 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1237 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1238 1239 return cpu_to_le32(dword); 1240 } 1241 1242 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1243 { 1244 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1245 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1246 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1247 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1248 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1249 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1250 1251 return cpu_to_le32(dword); 1252 } 1253 1254 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1255 { 1256 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1257 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1258 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1259 desc_info->data_retry_lowest_rate); 1260 1261 return cpu_to_le32(dword); 1262 } 1263 1264 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1265 { 1266 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1267 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1268 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1269 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1270 1271 return cpu_to_le32(dword); 1272 } 1273 1274 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1275 { 1276 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1277 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1278 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1279 1280 return cpu_to_le32(dword); 1281 } 1282 1283 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1284 { 1285 bool rts_en = !desc_info->is_bmc; 1286 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1287 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1288 1289 return cpu_to_le32(dword); 1290 } 1291 1292 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1293 struct rtw89_tx_desc_info *desc_info, 1294 void *txdesc) 1295 { 1296 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1297 struct rtw89_txwd_info *txwd_info; 1298 1299 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1300 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1301 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1302 1303 if (!desc_info->en_wd_info) 1304 return; 1305 1306 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1307 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1308 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1309 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1310 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1311 1312 } 1313 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1314 1315 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1316 struct rtw89_tx_desc_info *desc_info, 1317 void *txdesc) 1318 { 1319 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1320 struct rtw89_txwd_info *txwd_info; 1321 1322 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1323 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1324 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1325 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1326 if (desc_info->sec_en) { 1327 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1328 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1329 } 1330 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1331 1332 if (!desc_info->en_wd_info) 1333 return; 1334 1335 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1336 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1337 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1338 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1339 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1340 } 1341 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1342 1343 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1344 { 1345 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1346 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1347 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1348 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1349 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1350 1351 return cpu_to_le32(dword); 1352 } 1353 1354 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1355 { 1356 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1357 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1358 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1359 1360 return cpu_to_le32(dword); 1361 } 1362 1363 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1364 { 1365 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1366 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1367 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1368 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1369 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1370 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1371 1372 return cpu_to_le32(dword); 1373 } 1374 1375 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1376 { 1377 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq); 1378 1379 return cpu_to_le32(dword); 1380 } 1381 1382 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1383 { 1384 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1385 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1386 1387 return cpu_to_le32(dword); 1388 } 1389 1390 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1391 { 1392 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1393 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1394 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1395 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1396 1397 return cpu_to_le32(dword); 1398 } 1399 1400 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info) 1401 { 1402 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr); 1403 1404 return cpu_to_le32(dword); 1405 } 1406 1407 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1408 { 1409 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1410 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1411 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1412 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1413 1414 return cpu_to_le32(dword); 1415 } 1416 1417 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1418 { 1419 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1420 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1421 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1422 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1423 1424 return cpu_to_le32(dword); 1425 } 1426 1427 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1428 { 1429 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1430 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1431 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1432 desc_info->data_retry_lowest_rate); 1433 1434 return cpu_to_le32(dword); 1435 } 1436 1437 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1438 { 1439 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1440 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1441 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1442 1443 return cpu_to_le32(dword); 1444 } 1445 1446 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1447 { 1448 bool rts_en = !desc_info->is_bmc; 1449 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1450 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1451 1452 return cpu_to_le32(dword); 1453 } 1454 1455 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1456 struct rtw89_tx_desc_info *desc_info, 1457 void *txdesc) 1458 { 1459 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1460 struct rtw89_txwd_info_v2 *txwd_info; 1461 1462 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1463 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1464 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1465 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1466 if (desc_info->sec_en) { 1467 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1468 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1469 } 1470 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1471 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1472 1473 if (!desc_info->en_wd_info) 1474 return; 1475 1476 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1477 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1478 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1479 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1480 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1481 } 1482 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1483 1484 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1485 { 1486 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1487 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1488 RTW89_CORE_RX_TYPE_FWDL : 1489 RTW89_CORE_RX_TYPE_H2C); 1490 1491 return cpu_to_le32(dword); 1492 } 1493 1494 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1495 struct rtw89_tx_desc_info *desc_info, 1496 void *txdesc) 1497 { 1498 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1499 1500 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1501 } 1502 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1503 1504 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1505 { 1506 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1507 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1508 RTW89_CORE_RX_TYPE_FWDL : 1509 RTW89_CORE_RX_TYPE_H2C); 1510 1511 return cpu_to_le32(dword); 1512 } 1513 1514 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1515 struct rtw89_tx_desc_info *desc_info, 1516 void *txdesc) 1517 { 1518 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1519 1520 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1521 } 1522 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1523 1524 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1525 struct sk_buff *skb, 1526 struct rtw89_rx_phy_ppdu *phy_ppdu) 1527 { 1528 const struct rtw89_chip_info *chip = rtwdev->chip; 1529 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1530 const struct rtw89_rxinfo_user *user; 1531 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1532 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1533 bool rx_cnt_valid = false; 1534 bool invalid = false; 1535 u8 plcp_size = 0; 1536 u8 *phy_sts; 1537 u8 usr_num; 1538 int i; 1539 1540 if (chip_gen == RTW89_CHIP_BE) { 1541 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1542 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1543 } 1544 1545 if (invalid) 1546 return -EINVAL; 1547 1548 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1549 if (chip_gen == RTW89_CHIP_BE) { 1550 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1551 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1552 } else { 1553 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1554 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1555 } 1556 if (usr_num > chip->ppdu_max_usr) { 1557 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1558 usr_num); 1559 return -EINVAL; 1560 } 1561 1562 for (i = 0; i < usr_num; i++) { 1563 user = &rxinfo->user[i]; 1564 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1565 continue; 1566 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set 1567 * by hardware, so update mac_id by rxinfo_user[].mac_id. 1568 */ 1569 if (chip_gen == RTW89_CHIP_BE) 1570 phy_ppdu->mac_id = 1571 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1572 phy_ppdu->has_data = 1573 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA); 1574 phy_ppdu->has_bcn = 1575 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN); 1576 break; 1577 } 1578 1579 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1580 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1581 /* 8-byte alignment */ 1582 if (usr_num & BIT(0)) 1583 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1584 if (rx_cnt_valid) 1585 phy_sts += rx_cnt_size; 1586 phy_sts += plcp_size; 1587 1588 if (phy_sts > skb->data + skb->len) 1589 return -EINVAL; 1590 1591 phy_ppdu->buf = phy_sts; 1592 phy_ppdu->len = skb->data + skb->len - phy_sts; 1593 1594 return 0; 1595 } 1596 1597 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate) 1598 { 1599 u8 data_rate_mode; 1600 1601 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1602 switch (data_rate_mode) { 1603 case DATA_RATE_MODE_NON_HT: 1604 return 1; 1605 case DATA_RATE_MODE_HT: 1606 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1; 1607 case DATA_RATE_MODE_VHT: 1608 case DATA_RATE_MODE_HE: 1609 case DATA_RATE_MODE_EHT: 1610 return rtw89_get_data_nss(rtwdev, data_rate) + 1; 1611 default: 1612 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1613 return 0; 1614 } 1615 } 1616 1617 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1618 struct ieee80211_sta *sta) 1619 { 1620 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1621 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 1622 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1623 struct rtw89_hal *hal = &rtwdev->hal; 1624 struct rtw89_sta_link *rtwsta_link; 1625 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1626 u8 ant_pos = U8_MAX; 1627 u8 evm_pos = 0; 1628 int i; 1629 1630 /* FIXME: For single link, taking link on HW-0 here is okay. But, when 1631 * enabling multiple active links, we should determine the right link. 1632 */ 1633 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0); 1634 if (unlikely(!rtwsta_link)) 1635 return; 1636 1637 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1638 return; 1639 1640 if (hal->ant_diversity && hal->antenna_rx) { 1641 ant_pos = __ffs(hal->antenna_rx); 1642 evm_pos = ant_pos; 1643 } 1644 1645 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg); 1646 1647 if (ant_pos < ant_num) { 1648 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]); 1649 } else { 1650 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1651 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]); 1652 } 1653 1654 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) { 1655 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr); 1656 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) { 1657 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min); 1658 } else { 1659 ewma_evm_add(&rtwsta_link->evm_min[evm_pos], 1660 phy_ppdu->ofdm.evm_min); 1661 ewma_evm_add(&rtwsta_link->evm_max[evm_pos], 1662 phy_ppdu->ofdm.evm_max); 1663 } 1664 } 1665 } 1666 1667 #define VAR_LEN 0xff 1668 #define VAR_LEN_UNIT 8 1669 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1670 const struct rtw89_phy_sts_iehdr *iehdr) 1671 { 1672 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1673 [RTW89_CHIP_AX] = { 1674 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1675 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1676 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1677 }, 1678 [RTW89_CHIP_BE] = { 1679 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1680 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1681 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1682 }, 1683 }; 1684 const u8 *physts_ie_len_tab; 1685 u16 ie_len; 1686 u8 ie; 1687 1688 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1689 1690 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1691 if (physts_ie_len_tab[ie] != VAR_LEN) 1692 ie_len = physts_ie_len_tab[ie]; 1693 else 1694 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1695 1696 return ie_len; 1697 } 1698 1699 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev, 1700 const struct rtw89_phy_sts_iehdr *iehdr, 1701 struct rtw89_rx_phy_ppdu *phy_ppdu) 1702 { 1703 const struct rtw89_phy_sts_ie01_v2 *ie; 1704 u8 *rpl_fd = phy_ppdu->rpl_fd; 1705 1706 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr; 1707 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A); 1708 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B); 1709 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C); 1710 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D); 1711 1712 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX); 1713 } 1714 1715 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1716 const struct rtw89_phy_sts_iehdr *iehdr, 1717 struct rtw89_rx_phy_ppdu *phy_ppdu) 1718 { 1719 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr; 1720 s16 cfo; 1721 u32 t; 1722 1723 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1724 1725 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1726 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1727 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1728 } 1729 1730 if (!phy_ppdu->hdr_2_en) 1731 phy_ppdu->rx_path_en = 1732 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN); 1733 1734 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1735 return; 1736 1737 if (!phy_ppdu->to_self) 1738 return; 1739 1740 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD); 1741 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1742 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1743 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1744 phy_ppdu->ofdm.has = true; 1745 1746 /* sign conversion for S(12,2) */ 1747 if (rtwdev->chip->cfo_src_fd) { 1748 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1749 cfo = sign_extend32(t, 11); 1750 } else { 1751 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1752 cfo = sign_extend32(t, 11); 1753 } 1754 1755 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1756 1757 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1758 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu); 1759 } 1760 1761 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev, 1762 const struct rtw89_phy_sts_iehdr *iehdr, 1763 struct rtw89_rx_phy_ppdu *phy_ppdu) 1764 { 1765 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr; 1766 u16 tmp_rpl; 1767 1768 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL); 1769 phy_ppdu->rpl_avg = tmp_rpl >> 1; 1770 } 1771 1772 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev, 1773 const struct rtw89_phy_sts_iehdr *iehdr, 1774 struct rtw89_rx_phy_ppdu *phy_ppdu) 1775 { 1776 const struct rtw89_phy_sts_ie00_v2 *ie; 1777 u8 *rpl_path = phy_ppdu->rpl_path; 1778 u16 tmp_rpl[RF_PATH_MAX]; 1779 u8 i; 1780 1781 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr; 1782 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A); 1783 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B); 1784 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C); 1785 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D); 1786 1787 for (i = 0; i < RF_PATH_MAX; i++) 1788 rpl_path[i] = tmp_rpl[i] >> 1; 1789 } 1790 1791 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1792 const struct rtw89_phy_sts_iehdr *iehdr, 1793 struct rtw89_rx_phy_ppdu *phy_ppdu) 1794 { 1795 u8 ie; 1796 1797 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1798 1799 switch (ie) { 1800 case RTW89_PHYSTS_IE00_CMN_CCK: 1801 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu); 1802 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1803 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu); 1804 break; 1805 case RTW89_PHYSTS_IE01_CMN_OFDM: 1806 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1807 break; 1808 default: 1809 break; 1810 } 1811 1812 return 0; 1813 } 1814 1815 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu) 1816 { 1817 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN; 1818 1819 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN); 1820 } 1821 1822 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1823 { 1824 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1825 u8 *rssi = phy_ppdu->rssi; 1826 1827 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1828 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1829 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1830 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1831 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1832 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1833 1834 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN); 1835 if (phy_ppdu->hdr_2_en) 1836 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu); 1837 } 1838 1839 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1840 struct rtw89_rx_phy_ppdu *phy_ppdu) 1841 { 1842 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1843 u32 len_from_header; 1844 bool physts_valid; 1845 1846 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1847 if (!physts_valid) 1848 return -EINVAL; 1849 1850 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1851 1852 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1853 len_from_header += PHY_STS_HDR_LEN; 1854 1855 if (len_from_header != phy_ppdu->len) { 1856 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1857 return -EINVAL; 1858 } 1859 rtw89_core_update_phy_ppdu(phy_ppdu); 1860 1861 return 0; 1862 } 1863 1864 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1865 struct rtw89_rx_phy_ppdu *phy_ppdu) 1866 { 1867 u16 ie_len; 1868 void *pos, *end; 1869 1870 /* mark invalid reports and bypass them */ 1871 if (phy_ppdu->ie < RTW89_CCK_PKT) 1872 return -EINVAL; 1873 1874 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1875 end = phy_ppdu->buf + phy_ppdu->len; 1876 while (pos < end) { 1877 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1878 1879 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1880 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1881 pos += ie_len; 1882 if (pos > end || ie_len == 0) { 1883 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1884 "phy status parse failed\n"); 1885 return -EINVAL; 1886 } 1887 } 1888 1889 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu); 1890 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1891 1892 return 0; 1893 } 1894 1895 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1896 struct rtw89_rx_phy_ppdu *phy_ppdu) 1897 { 1898 int ret; 1899 1900 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1901 if (ret) 1902 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1903 else 1904 phy_ppdu->valid = true; 1905 1906 ieee80211_iterate_stations_atomic(rtwdev->hw, 1907 rtw89_core_rx_process_phy_ppdu_iter, 1908 phy_ppdu); 1909 } 1910 1911 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1912 u8 desc_info_gi, 1913 bool rx_status) 1914 { 1915 switch (desc_info_gi) { 1916 case RTW89_GILTF_SGI_4XHE08: 1917 case RTW89_GILTF_2XHE08: 1918 case RTW89_GILTF_1XHE08: 1919 return NL80211_RATE_INFO_HE_GI_0_8; 1920 case RTW89_GILTF_2XHE16: 1921 case RTW89_GILTF_1XHE16: 1922 return NL80211_RATE_INFO_HE_GI_1_6; 1923 case RTW89_GILTF_LGI_4XHE32: 1924 return NL80211_RATE_INFO_HE_GI_3_2; 1925 default: 1926 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1927 if (rx_status) 1928 return NL80211_RATE_INFO_HE_GI_3_2; 1929 return U8_MAX; 1930 } 1931 } 1932 1933 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev, 1934 u8 desc_info_gi, 1935 bool rx_status) 1936 { 1937 switch (desc_info_gi) { 1938 case RTW89_GILTF_SGI_4XHE08: 1939 case RTW89_GILTF_2XHE08: 1940 case RTW89_GILTF_1XHE08: 1941 return NL80211_RATE_INFO_EHT_GI_0_8; 1942 case RTW89_GILTF_2XHE16: 1943 case RTW89_GILTF_1XHE16: 1944 return NL80211_RATE_INFO_EHT_GI_1_6; 1945 case RTW89_GILTF_LGI_4XHE32: 1946 return NL80211_RATE_INFO_EHT_GI_3_2; 1947 default: 1948 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1949 if (rx_status) 1950 return NL80211_RATE_INFO_EHT_GI_3_2; 1951 return U8_MAX; 1952 } 1953 } 1954 1955 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 1956 u8 desc_info_gi, 1957 bool rx_status, bool eht) 1958 { 1959 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) : 1960 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status); 1961 } 1962 1963 static 1964 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 1965 bool eht) 1966 { 1967 if (eht) 1968 return status->eht.gi == gi_ltf; 1969 1970 return status->he_gi == gi_ltf; 1971 } 1972 1973 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1974 struct rtw89_rx_desc_info *desc_info, 1975 struct ieee80211_rx_status *status) 1976 { 1977 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1978 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1979 bool eht = false; 1980 u16 data_rate; 1981 bool ret; 1982 1983 data_rate = desc_info->data_rate; 1984 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1985 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1986 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1987 /* rate_idx is still hardware value here */ 1988 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1989 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1990 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 1991 data_rate_mode == DATA_RATE_MODE_HE || 1992 data_rate_mode == DATA_RATE_MODE_EHT) { 1993 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1994 } else { 1995 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1996 } 1997 1998 eht = data_rate_mode == DATA_RATE_MODE_EHT; 1999 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2000 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 2001 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 2002 status->rate_idx == rate_idx && 2003 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 2004 status->bw == bw; 2005 2006 return ret; 2007 } 2008 2009 struct rtw89_vif_rx_stats_iter_data { 2010 struct rtw89_dev *rtwdev; 2011 struct rtw89_rx_phy_ppdu *phy_ppdu; 2012 struct rtw89_rx_desc_info *desc_info; 2013 struct sk_buff *skb; 2014 const u8 *bssid; 2015 }; 2016 2017 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 2018 struct rtw89_vif_link *rtwvif_link, 2019 struct ieee80211_bss_conf *bss_conf, 2020 struct sk_buff *skb) 2021 { 2022 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 2023 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 2024 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 2025 u8 *pos, *end, type, tf_bw; 2026 u16 aid, tf_rua; 2027 2028 if (!ether_addr_equal(bss_conf->bssid, tf->ta) || 2029 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION || 2030 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK) 2031 return; 2032 2033 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 2034 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 2035 return; 2036 2037 end = (u8 *)tf + skb->len; 2038 pos = tf->variable; 2039 2040 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 2041 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 2042 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 2043 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 2044 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2045 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 2046 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 2047 tf_rua, tf_bw); 2048 2049 if (aid == RTW89_TF_PAD) 2050 break; 2051 2052 if (aid == vif->cfg.aid) { 2053 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 2054 2055 rtwvif->stats.rx_tf_acc++; 2056 rtwdev->stats.rx_tf_acc++; 2057 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 2058 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 2059 rtwvif_link->pwr_diff_en = true; 2060 break; 2061 } 2062 2063 pos += RTW89_TF_BASIC_USER_INFO_SZ; 2064 } 2065 } 2066 2067 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work) 2068 { 2069 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2070 cancel_6ghz_probe_work); 2071 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2072 struct rtw89_pktofld_info *info; 2073 2074 mutex_lock(&rtwdev->mutex); 2075 2076 if (!rtwdev->scanning) 2077 goto out; 2078 2079 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2080 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 2081 continue; 2082 2083 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 2084 2085 /* Don't delete/free info from pkt_list at this moment. Let it 2086 * be deleted/freed in rtw89_release_pkt_list() after scanning, 2087 * since if during scanning, pkt_list is accessed in bottom half. 2088 */ 2089 } 2090 2091 out: 2092 mutex_unlock(&rtwdev->mutex); 2093 } 2094 2095 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 2096 struct sk_buff *skb) 2097 { 2098 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2099 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2100 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2101 struct rtw89_pktofld_info *info; 2102 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 2103 bool queue_work = false; 2104 2105 if (rx_status->band != NL80211_BAND_6GHZ) 2106 return; 2107 2108 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 2109 2110 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2111 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 2112 info->cancel = true; 2113 queue_work = true; 2114 continue; 2115 } 2116 2117 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 2118 continue; 2119 2120 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 2121 info->cancel = true; 2122 queue_work = true; 2123 } 2124 } 2125 2126 if (queue_work) 2127 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work); 2128 } 2129 2130 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link, 2131 struct ieee80211_hdr *hdr, size_t len) 2132 { 2133 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 2134 2135 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 2136 return; 2137 2138 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 2139 } 2140 2141 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 2142 struct ieee80211_vif *vif) 2143 { 2144 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 2145 struct rtw89_dev *rtwdev = iter_data->rtwdev; 2146 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 2147 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2148 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2149 struct sk_buff *skb = iter_data->skb; 2150 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2151 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 2152 struct ieee80211_bss_conf *bss_conf; 2153 struct rtw89_vif_link *rtwvif_link; 2154 const u8 *bssid = iter_data->bssid; 2155 2156 if (rtwdev->scanning && 2157 (ieee80211_is_beacon(hdr->frame_control) || 2158 ieee80211_is_probe_resp(hdr->frame_control))) 2159 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 2160 2161 rcu_read_lock(); 2162 2163 /* FIXME: For single link, taking link on HW-0 here is okay. But, when 2164 * enabling multiple active links, we should determine the right link. 2165 */ 2166 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0); 2167 if (unlikely(!rtwvif_link)) 2168 goto out; 2169 2170 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 2171 if (!bss_conf->bssid) 2172 goto out; 2173 2174 if (ieee80211_is_trigger(hdr->frame_control)) { 2175 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb); 2176 goto out; 2177 } 2178 2179 if (!ether_addr_equal(bss_conf->bssid, bssid)) 2180 goto out; 2181 2182 if (ieee80211_is_beacon(hdr->frame_control)) { 2183 if (vif->type == NL80211_IFTYPE_STATION && 2184 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 2185 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len); 2186 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 2187 } 2188 pkt_stat->beacon_nr++; 2189 2190 if (phy_ppdu) 2191 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg); 2192 2193 pkt_stat->beacon_rate = desc_info->data_rate; 2194 } 2195 2196 if (!ether_addr_equal(bss_conf->addr, hdr->addr1)) 2197 goto out; 2198 2199 if (desc_info->data_rate < RTW89_HW_RATE_NR) 2200 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 2201 2202 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 2203 2204 out: 2205 rcu_read_unlock(); 2206 } 2207 2208 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 2209 struct rtw89_rx_phy_ppdu *phy_ppdu, 2210 struct rtw89_rx_desc_info *desc_info, 2211 struct sk_buff *skb) 2212 { 2213 struct rtw89_vif_rx_stats_iter_data iter_data; 2214 2215 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 2216 2217 iter_data.rtwdev = rtwdev; 2218 iter_data.phy_ppdu = phy_ppdu; 2219 iter_data.desc_info = desc_info; 2220 iter_data.skb = skb; 2221 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 2222 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 2223 } 2224 2225 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 2226 struct ieee80211_rx_status *status) 2227 { 2228 const struct rtw89_chan_rcd *rcd = 2229 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0); 2230 u16 chan = rcd->prev_primary_channel; 2231 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 2232 2233 if (status->band != NL80211_BAND_2GHZ && 2234 status->encoding == RX_ENC_LEGACY && 2235 status->rate_idx < RTW89_HW_RATE_OFDM6) { 2236 status->freq = ieee80211_channel_to_frequency(chan, band); 2237 status->band = band; 2238 } 2239 } 2240 2241 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 2242 { 2243 if (rx_status->band == NL80211_BAND_2GHZ || 2244 rx_status->encoding != RX_ENC_LEGACY) 2245 return; 2246 2247 /* Some control frames' freq(ACKs in this case) are reported wrong due 2248 * to FW notify timing, set to lowest rate to prevent overflow. 2249 */ 2250 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 2251 rx_status->rate_idx = 0; 2252 return; 2253 } 2254 2255 /* No 4 CCK rates for non-2G */ 2256 rx_status->rate_idx -= 4; 2257 } 2258 2259 static 2260 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 2261 struct ieee80211_rx_status *rx_status, 2262 struct rtw89_rx_phy_ppdu *phy_ppdu) 2263 { 2264 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2265 return; 2266 2267 if (!phy_ppdu) 2268 return; 2269 2270 if (phy_ppdu->ldpc) 2271 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2272 if (phy_ppdu->stbc) 2273 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 2274 } 2275 2276 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 2277 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 2278 [RATE_INFO_BW_5] = U8_MAX, 2279 [RATE_INFO_BW_10] = U8_MAX, 2280 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 2281 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 2282 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 2283 [RATE_INFO_BW_HE_RU] = U8_MAX, 2284 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 2285 [RATE_INFO_BW_EHT_RU] = U8_MAX, 2286 }; 2287 2288 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2289 struct sk_buff *skb, 2290 struct ieee80211_rx_status *rx_status) 2291 { 2292 struct ieee80211_radiotap_eht_usig *usig; 2293 struct ieee80211_radiotap_eht *eht; 2294 struct ieee80211_radiotap_tlv *tlv; 2295 int eht_len = struct_size(eht, user_info, 1); 2296 int usig_len = sizeof(*usig); 2297 int len; 2298 u8 bw; 2299 2300 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2301 sizeof(*tlv) + ALIGN(usig_len, 4); 2302 2303 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2304 skb_reset_mac_header(skb); 2305 2306 /* EHT */ 2307 tlv = skb_push(skb, len); 2308 memset(tlv, 0, len); 2309 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2310 tlv->len = cpu_to_le16(eht_len); 2311 2312 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2313 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2314 eht->data[0] = 2315 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2316 2317 eht->user_info[0] = 2318 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2319 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 2320 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 2321 eht->user_info[0] |= 2322 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2323 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2324 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 2325 eht->user_info[0] |= 2326 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 2327 2328 /* U-SIG */ 2329 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2330 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2331 tlv->len = cpu_to_le16(usig_len); 2332 2333 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2334 return; 2335 2336 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2337 if (bw == U8_MAX) 2338 return; 2339 2340 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2341 usig->common = 2342 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2343 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2344 } 2345 2346 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2347 struct sk_buff *skb, 2348 struct ieee80211_rx_status *rx_status) 2349 { 2350 static const struct ieee80211_radiotap_he known_he = { 2351 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2352 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 2353 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 2354 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2355 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2356 }; 2357 struct ieee80211_radiotap_he *he; 2358 2359 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2360 return; 2361 2362 if (rx_status->encoding == RX_ENC_HE) { 2363 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2364 he = skb_push(skb, sizeof(*he)); 2365 *he = known_he; 2366 } else if (rx_status->encoding == RX_ENC_EHT) { 2367 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2368 } 2369 } 2370 2371 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status) 2372 { 2373 if (!rx_status->signal) 2374 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2375 } 2376 2377 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2378 struct rtw89_rx_phy_ppdu *phy_ppdu, 2379 struct rtw89_rx_desc_info *desc_info, 2380 struct sk_buff *skb_ppdu, 2381 struct ieee80211_rx_status *rx_status) 2382 { 2383 struct napi_struct *napi = &rtwdev->napi; 2384 2385 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2386 if (unlikely(!napi_is_scheduled(napi))) 2387 napi = NULL; 2388 2389 rtw89_core_hw_to_sband_rate(rx_status); 2390 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2391 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 2392 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2393 rtw89_core_validate_rx_signal(rx_status); 2394 2395 /* In low power mode, it does RX in thread context. */ 2396 local_bh_disable(); 2397 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2398 local_bh_enable(); 2399 rtwdev->napi_budget_countdown--; 2400 } 2401 2402 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2403 struct rtw89_rx_phy_ppdu *phy_ppdu, 2404 struct rtw89_rx_desc_info *desc_info, 2405 struct sk_buff *skb) 2406 { 2407 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2408 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2409 struct sk_buff *skb_ppdu = NULL, *tmp; 2410 struct ieee80211_rx_status *rx_status; 2411 2412 if (curr > RTW89_MAX_PPDU_CNT) 2413 return; 2414 2415 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2416 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2417 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2418 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2419 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2420 rtw89_correct_cck_chan(rtwdev, rx_status); 2421 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2422 } 2423 } 2424 2425 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2426 struct rtw89_rx_desc_info *desc_info, 2427 struct sk_buff *skb) 2428 { 2429 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2430 .len = skb->len, 2431 .to_self = desc_info->addr1_match, 2432 .rate = desc_info->data_rate, 2433 .mac_id = desc_info->mac_id}; 2434 int ret; 2435 2436 if (desc_info->mac_info_valid) { 2437 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2438 if (ret) 2439 goto out; 2440 } 2441 2442 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2443 if (ret) 2444 goto out; 2445 2446 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2447 2448 out: 2449 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2450 dev_kfree_skb_any(skb); 2451 } 2452 2453 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2454 struct rtw89_rx_desc_info *desc_info, 2455 struct sk_buff *skb) 2456 { 2457 switch (desc_info->pkt_type) { 2458 case RTW89_CORE_RX_TYPE_C2H: 2459 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2460 break; 2461 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2462 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2463 break; 2464 default: 2465 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2466 desc_info->pkt_type); 2467 dev_kfree_skb_any(skb); 2468 break; 2469 } 2470 } 2471 2472 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2473 struct rtw89_rx_desc_info *desc_info, 2474 u8 *data, u32 data_offset) 2475 { 2476 const struct rtw89_chip_info *chip = rtwdev->chip; 2477 struct rtw89_rxdesc_short *rxd_s; 2478 struct rtw89_rxdesc_long *rxd_l; 2479 u8 shift_len, drv_info_len; 2480 2481 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2482 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2483 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2484 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2485 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2486 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2487 if (chip->chip_id == RTL8852C) 2488 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2489 else 2490 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2491 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2492 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2493 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2494 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2495 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2496 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2497 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2498 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2499 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2500 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2501 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2502 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2503 2504 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2505 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2506 desc_info->offset = data_offset + shift_len + drv_info_len; 2507 if (desc_info->long_rxdesc) 2508 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2509 else 2510 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2511 desc_info->ready = true; 2512 2513 if (!desc_info->long_rxdesc) 2514 return; 2515 2516 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2517 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2518 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2519 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2520 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2521 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2522 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2523 } 2524 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2525 2526 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2527 struct rtw89_rx_desc_info *desc_info, 2528 u8 *data, u32 data_offset) 2529 { 2530 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 2531 struct rtw89_rxdesc_short_v2 *rxd_s; 2532 struct rtw89_rxdesc_long_v2 *rxd_l; 2533 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2534 2535 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2536 2537 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2538 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2539 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2540 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2541 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2542 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2543 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2544 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2545 desc_info->mac_info_valid = true; 2546 2547 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2548 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2549 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2550 2551 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2552 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2553 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2554 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2555 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2556 2557 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2558 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2559 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2560 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2561 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2562 2563 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2564 2565 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2566 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2567 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2568 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2569 desc_info->offset = data_offset + shift_len + drv_info_len + 2570 phy_rtp_len + hdr_cnv_len; 2571 2572 if (desc_info->long_rxdesc) 2573 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2574 else 2575 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2576 desc_info->ready = true; 2577 2578 if (phy_rtp_len == sizeof(*rxd_rpt)) { 2579 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 2580 desc_info->rxd_len); 2581 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 2582 } 2583 2584 if (!desc_info->long_rxdesc) 2585 return; 2586 2587 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2588 2589 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2590 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2591 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2592 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2593 2594 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2595 } 2596 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2597 2598 struct rtw89_core_iter_rx_status { 2599 struct rtw89_dev *rtwdev; 2600 struct ieee80211_rx_status *rx_status; 2601 struct rtw89_rx_desc_info *desc_info; 2602 u8 mac_id; 2603 }; 2604 2605 static 2606 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2607 { 2608 struct rtw89_core_iter_rx_status *iter_data = 2609 (struct rtw89_core_iter_rx_status *)data; 2610 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2611 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2612 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 2613 struct rtw89_sta_link *rtwsta_link; 2614 u8 mac_id = iter_data->mac_id; 2615 2616 /* FIXME: For single link, taking link on HW-0 here is okay. But, when 2617 * enabling multiple active links, we should determine the right link. 2618 */ 2619 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0); 2620 if (unlikely(!rtwsta_link)) 2621 return; 2622 2623 if (mac_id != rtwsta_link->mac_id) 2624 return; 2625 2626 rtwsta_link->rx_status = *rx_status; 2627 rtwsta_link->rx_hw_rate = desc_info->data_rate; 2628 } 2629 2630 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2631 struct rtw89_rx_desc_info *desc_info, 2632 struct ieee80211_rx_status *rx_status) 2633 { 2634 struct rtw89_core_iter_rx_status iter_data; 2635 2636 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2637 return; 2638 2639 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2640 return; 2641 2642 iter_data.rtwdev = rtwdev; 2643 iter_data.rx_status = rx_status; 2644 iter_data.desc_info = desc_info; 2645 iter_data.mac_id = desc_info->mac_id; 2646 ieee80211_iterate_stations_atomic(rtwdev->hw, 2647 rtw89_core_stats_sta_rx_status_iter, 2648 &iter_data); 2649 } 2650 2651 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2652 struct rtw89_rx_desc_info *desc_info, 2653 struct ieee80211_rx_status *rx_status) 2654 { 2655 const struct cfg80211_chan_def *chandef = 2656 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0); 2657 u16 data_rate; 2658 u8 data_rate_mode; 2659 bool eht = false; 2660 u8 gi; 2661 2662 /* currently using single PHY */ 2663 rx_status->freq = chandef->chan->center_freq; 2664 rx_status->band = chandef->chan->band; 2665 2666 if (rtwdev->scanning && 2667 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2668 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2669 u8 chan = cur->primary_channel; 2670 u8 band = cur->band_type; 2671 enum nl80211_band nl_band; 2672 2673 nl_band = rtw89_hw_to_nl80211_band(band); 2674 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2675 rx_status->band = nl_band; 2676 } 2677 2678 if (desc_info->icv_err || desc_info->crc32_err) 2679 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2680 2681 if (desc_info->hw_dec && 2682 !(desc_info->sw_dec || desc_info->icv_err)) 2683 rx_status->flag |= RX_FLAG_DECRYPTED; 2684 2685 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2686 2687 data_rate = desc_info->data_rate; 2688 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2689 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2690 rx_status->encoding = RX_ENC_LEGACY; 2691 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2692 /* convert rate_idx after we get the correct band */ 2693 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2694 rx_status->encoding = RX_ENC_HT; 2695 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2696 if (desc_info->gi_ltf) 2697 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2698 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2699 rx_status->encoding = RX_ENC_VHT; 2700 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2701 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2702 if (desc_info->gi_ltf) 2703 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2704 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2705 rx_status->encoding = RX_ENC_HE; 2706 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2707 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2708 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2709 rx_status->encoding = RX_ENC_EHT; 2710 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2711 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2712 eht = true; 2713 } else { 2714 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2715 } 2716 2717 /* he_gi is used to match ppdu, so we always fill it. */ 2718 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2719 if (eht) 2720 rx_status->eht.gi = gi; 2721 else 2722 rx_status->he_gi = gi; 2723 rx_status->flag |= RX_FLAG_MACTIME_START; 2724 rx_status->mactime = desc_info->free_run_cnt; 2725 2726 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 2727 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2728 } 2729 2730 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2731 { 2732 const struct rtw89_chip_info *chip = rtwdev->chip; 2733 2734 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2735 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2736 return RTW89_PS_MODE_NONE; 2737 2738 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2739 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2740 return RTW89_PS_MODE_PWR_GATED; 2741 2742 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2743 return RTW89_PS_MODE_CLK_GATED; 2744 2745 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2746 return RTW89_PS_MODE_RFOFF; 2747 2748 return RTW89_PS_MODE_NONE; 2749 } 2750 2751 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2752 struct rtw89_rx_desc_info *desc_info) 2753 { 2754 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2755 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2756 struct ieee80211_rx_status *rx_status; 2757 struct sk_buff *skb_ppdu, *tmp; 2758 2759 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2760 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2761 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2762 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2763 } 2764 } 2765 2766 static 2767 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb, 2768 const struct rtw89_rx_desc_info *desc) 2769 { 2770 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2771 struct rtw89_sta_link *rtwsta_link; 2772 struct ieee80211_sta *sta; 2773 struct rtw89_sta *rtwsta; 2774 u8 macid = desc->mac_id; 2775 2776 if (!refcount_read(&rtwdev->refcount_ap_info)) 2777 return; 2778 2779 rcu_read_lock(); 2780 2781 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 2782 if (!rtwsta_link) 2783 goto out; 2784 2785 rtwsta = rtwsta_link->rtwsta; 2786 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags)) 2787 goto out; 2788 2789 sta = rtwsta_to_sta(rtwsta); 2790 if (ieee80211_is_pspoll(hdr->frame_control)) 2791 ieee80211_sta_pspoll(sta); 2792 else if (ieee80211_has_pm(hdr->frame_control) && 2793 (ieee80211_is_data_qos(hdr->frame_control) || 2794 ieee80211_is_qos_nullfunc(hdr->frame_control))) 2795 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr)); 2796 2797 out: 2798 rcu_read_unlock(); 2799 } 2800 2801 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2802 struct rtw89_rx_desc_info *desc_info, 2803 struct sk_buff *skb) 2804 { 2805 struct ieee80211_rx_status *rx_status; 2806 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2807 u8 ppdu_cnt = desc_info->ppdu_cnt; 2808 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2809 2810 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2811 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2812 return; 2813 } 2814 2815 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2816 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2817 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2818 } 2819 2820 rx_status = IEEE80211_SKB_RXCB(skb); 2821 memset(rx_status, 0, sizeof(*rx_status)); 2822 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2823 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info); 2824 if (desc_info->long_rxdesc && 2825 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2826 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2827 else 2828 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2829 } 2830 EXPORT_SYMBOL(rtw89_core_rx); 2831 2832 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2833 { 2834 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2835 return; 2836 2837 napi_enable(&rtwdev->napi); 2838 } 2839 EXPORT_SYMBOL(rtw89_core_napi_start); 2840 2841 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2842 { 2843 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2844 return; 2845 2846 napi_synchronize(&rtwdev->napi); 2847 napi_disable(&rtwdev->napi); 2848 } 2849 EXPORT_SYMBOL(rtw89_core_napi_stop); 2850 2851 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2852 { 2853 rtwdev->netdev = alloc_netdev_dummy(0); 2854 if (!rtwdev->netdev) 2855 return -ENOMEM; 2856 2857 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 2858 rtwdev->hci.ops->napi_poll); 2859 return 0; 2860 } 2861 EXPORT_SYMBOL(rtw89_core_napi_init); 2862 2863 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2864 { 2865 rtw89_core_napi_stop(rtwdev); 2866 netif_napi_del(&rtwdev->napi); 2867 free_netdev(rtwdev->netdev); 2868 } 2869 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2870 2871 static void rtw89_core_ba_work(struct work_struct *work) 2872 { 2873 struct rtw89_dev *rtwdev = 2874 container_of(work, struct rtw89_dev, ba_work); 2875 struct rtw89_txq *rtwtxq, *tmp; 2876 int ret; 2877 2878 spin_lock_bh(&rtwdev->ba_lock); 2879 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2880 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2881 struct ieee80211_sta *sta = txq->sta; 2882 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2883 u8 tid = txq->tid; 2884 2885 if (!sta) { 2886 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2887 goto skip_ba_work; 2888 } 2889 2890 if (rtwsta->disassoc) { 2891 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2892 "cannot start BA with disassoc sta\n"); 2893 goto skip_ba_work; 2894 } 2895 2896 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2897 if (ret) { 2898 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2899 "failed to setup BA session for %pM:%2d: %d\n", 2900 sta->addr, tid, ret); 2901 if (ret == -EINVAL) 2902 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2903 } 2904 skip_ba_work: 2905 list_del_init(&rtwtxq->list); 2906 } 2907 spin_unlock_bh(&rtwdev->ba_lock); 2908 } 2909 2910 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2911 struct ieee80211_sta *sta) 2912 { 2913 struct rtw89_txq *rtwtxq, *tmp; 2914 2915 spin_lock_bh(&rtwdev->ba_lock); 2916 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2917 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2918 2919 if (sta == txq->sta) 2920 list_del_init(&rtwtxq->list); 2921 } 2922 spin_unlock_bh(&rtwdev->ba_lock); 2923 } 2924 2925 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2926 struct ieee80211_sta *sta) 2927 { 2928 struct rtw89_txq *rtwtxq, *tmp; 2929 2930 spin_lock_bh(&rtwdev->ba_lock); 2931 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2932 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2933 2934 if (sta == txq->sta) { 2935 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2936 list_del_init(&rtwtxq->list); 2937 } 2938 } 2939 spin_unlock_bh(&rtwdev->ba_lock); 2940 } 2941 2942 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2943 struct ieee80211_sta *sta) 2944 { 2945 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 2946 struct sk_buff *skb, *tmp; 2947 2948 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2949 skb_unlink(skb, &rtwsta->roc_queue); 2950 dev_kfree_skb_any(skb); 2951 } 2952 } 2953 2954 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2955 struct rtw89_txq *rtwtxq) 2956 { 2957 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2958 struct ieee80211_sta *sta = txq->sta; 2959 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2960 2961 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2962 return; 2963 2964 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2965 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2966 return; 2967 2968 spin_lock_bh(&rtwdev->ba_lock); 2969 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2970 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2971 spin_unlock_bh(&rtwdev->ba_lock); 2972 2973 ieee80211_stop_tx_ba_session(sta, txq->tid); 2974 cancel_delayed_work(&rtwdev->forbid_ba_work); 2975 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2976 RTW89_FORBID_BA_TIMER); 2977 } 2978 2979 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2980 struct rtw89_txq *rtwtxq, 2981 struct sk_buff *skb) 2982 { 2983 struct ieee80211_hw *hw = rtwdev->hw; 2984 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2985 struct ieee80211_sta *sta = txq->sta; 2986 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2987 2988 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2989 return; 2990 2991 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2992 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2993 return; 2994 } 2995 2996 if (unlikely(!sta)) 2997 return; 2998 2999 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 3000 return; 3001 3002 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 3003 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 3004 return; 3005 } 3006 3007 spin_lock_bh(&rtwdev->ba_lock); 3008 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 3009 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 3010 ieee80211_queue_work(hw, &rtwdev->ba_work); 3011 } 3012 spin_unlock_bh(&rtwdev->ba_lock); 3013 } 3014 3015 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 3016 struct rtw89_txq *rtwtxq, 3017 unsigned long frame_cnt, 3018 unsigned long byte_cnt) 3019 { 3020 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3021 struct ieee80211_vif *vif = txq->vif; 3022 struct ieee80211_sta *sta = txq->sta; 3023 struct sk_buff *skb; 3024 unsigned long i; 3025 int ret; 3026 3027 rcu_read_lock(); 3028 for (i = 0; i < frame_cnt; i++) { 3029 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 3030 if (!skb) { 3031 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 3032 goto out; 3033 } 3034 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 3035 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 3036 if (ret) { 3037 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 3038 ieee80211_free_txskb(rtwdev->hw, skb); 3039 break; 3040 } 3041 } 3042 out: 3043 rcu_read_unlock(); 3044 } 3045 3046 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 3047 { 3048 u8 qsel, ch_dma; 3049 3050 qsel = rtw89_core_get_qsel(rtwdev, tid); 3051 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 3052 3053 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 3054 } 3055 3056 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 3057 struct ieee80211_txq *txq, 3058 unsigned long *frame_cnt, 3059 bool *sched_txq, bool *reinvoke) 3060 { 3061 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3062 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta); 3063 struct rtw89_sta_link *rtwsta_link; 3064 3065 if (!rtwsta) 3066 return false; 3067 3068 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0); 3069 if (unlikely(!rtwsta_link)) { 3070 rtw89_err(rtwdev, "agg wait: find no link on HW-0\n"); 3071 return false; 3072 } 3073 3074 if (rtwsta_link->max_agg_wait <= 0) 3075 return false; 3076 3077 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 3078 return false; 3079 3080 if (*frame_cnt > 1) { 3081 *frame_cnt -= 1; 3082 *sched_txq = true; 3083 *reinvoke = true; 3084 rtwtxq->wait_cnt = 1; 3085 return false; 3086 } 3087 3088 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) { 3089 *reinvoke = true; 3090 rtwtxq->wait_cnt++; 3091 return true; 3092 } 3093 3094 rtwtxq->wait_cnt = 0; 3095 return false; 3096 } 3097 3098 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 3099 { 3100 struct ieee80211_hw *hw = rtwdev->hw; 3101 struct ieee80211_txq *txq; 3102 struct rtw89_vif *rtwvif; 3103 struct rtw89_txq *rtwtxq; 3104 unsigned long frame_cnt; 3105 unsigned long byte_cnt; 3106 u32 tx_resource; 3107 bool sched_txq; 3108 3109 ieee80211_txq_schedule_start(hw, ac); 3110 while ((txq = ieee80211_next_txq(hw, ac))) { 3111 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3112 rtwvif = vif_to_rtwvif(txq->vif); 3113 3114 if (rtwvif->offchan) { 3115 ieee80211_return_txq(hw, txq, true); 3116 continue; 3117 } 3118 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 3119 sched_txq = false; 3120 3121 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 3122 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 3123 ieee80211_return_txq(hw, txq, true); 3124 continue; 3125 } 3126 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 3127 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 3128 ieee80211_return_txq(hw, txq, sched_txq); 3129 if (frame_cnt != 0) 3130 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 3131 3132 /* bound of tx_resource could get stuck due to burst traffic */ 3133 if (frame_cnt == tx_resource) 3134 *reinvoke = true; 3135 } 3136 ieee80211_txq_schedule_end(hw, ac); 3137 } 3138 3139 static void rtw89_ips_work(struct work_struct *work) 3140 { 3141 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3142 ips_work); 3143 mutex_lock(&rtwdev->mutex); 3144 rtw89_enter_ips_by_hwflags(rtwdev); 3145 mutex_unlock(&rtwdev->mutex); 3146 } 3147 3148 static void rtw89_core_txq_work(struct work_struct *w) 3149 { 3150 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 3151 bool reinvoke = false; 3152 u8 ac; 3153 3154 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3155 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 3156 3157 if (reinvoke) { 3158 /* reinvoke to process the last frame */ 3159 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 3160 } 3161 } 3162 3163 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 3164 { 3165 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3166 txq_reinvoke_work.work); 3167 3168 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3169 } 3170 3171 static void rtw89_forbid_ba_work(struct work_struct *w) 3172 { 3173 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3174 forbid_ba_work.work); 3175 struct rtw89_txq *rtwtxq, *tmp; 3176 3177 spin_lock_bh(&rtwdev->ba_lock); 3178 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 3179 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3180 list_del_init(&rtwtxq->list); 3181 } 3182 spin_unlock_bh(&rtwdev->ba_lock); 3183 } 3184 3185 static void rtw89_core_sta_pending_tx_iter(void *data, 3186 struct ieee80211_sta *sta) 3187 { 3188 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3189 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3190 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3191 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3192 struct rtw89_vif_link *target = data; 3193 struct rtw89_vif_link *rtwvif_link; 3194 struct sk_buff *skb, *tmp; 3195 unsigned int link_id; 3196 int qsel, ret; 3197 3198 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3199 if (rtwvif_link->chanctx_idx == target->chanctx_idx) 3200 goto bottom; 3201 3202 return; 3203 3204 bottom: 3205 if (skb_queue_len(&rtwsta->roc_queue) == 0) 3206 return; 3207 3208 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 3209 skb_unlink(skb, &rtwsta->roc_queue); 3210 3211 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 3212 if (ret) { 3213 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 3214 dev_kfree_skb_any(skb); 3215 } else { 3216 rtw89_core_tx_kick_off(rtwdev, qsel); 3217 } 3218 } 3219 } 3220 3221 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 3222 struct rtw89_vif_link *rtwvif_link) 3223 { 3224 ieee80211_iterate_stations_atomic(rtwdev->hw, 3225 rtw89_core_sta_pending_tx_iter, 3226 rtwvif_link); 3227 } 3228 3229 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 3230 struct rtw89_vif_link *rtwvif_link, bool qos, bool ps) 3231 { 3232 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3233 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1; 3234 struct ieee80211_sta *sta; 3235 struct ieee80211_hdr *hdr; 3236 struct sk_buff *skb; 3237 int ret, qsel; 3238 3239 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 3240 return 0; 3241 3242 rcu_read_lock(); 3243 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); 3244 if (!sta) { 3245 ret = -EINVAL; 3246 goto out; 3247 } 3248 3249 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos); 3250 if (!skb) { 3251 ret = -ENOMEM; 3252 goto out; 3253 } 3254 3255 hdr = (struct ieee80211_hdr *)skb->data; 3256 if (ps) 3257 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 3258 3259 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 3260 if (ret) { 3261 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 3262 dev_kfree_skb_any(skb); 3263 goto out; 3264 } 3265 3266 rcu_read_unlock(); 3267 3268 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 3269 RTW89_ROC_TX_TIMEOUT); 3270 out: 3271 rcu_read_unlock(); 3272 3273 return ret; 3274 } 3275 3276 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3277 { 3278 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3279 struct ieee80211_hw *hw = rtwdev->hw; 3280 struct rtw89_roc *roc = &rtwvif->roc; 3281 struct rtw89_vif_link *rtwvif_link; 3282 struct cfg80211_chan_def roc_chan; 3283 struct rtw89_vif *tmp_vif; 3284 u32 reg; 3285 int ret; 3286 3287 lockdep_assert_held(&rtwdev->mutex); 3288 3289 rtw89_leave_ips_by_hwflags(rtwdev); 3290 rtw89_leave_lps(rtwdev); 3291 3292 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX); 3293 if (unlikely(!rtwvif_link)) { 3294 rtw89_err(rtwdev, "roc start: find no link on HW-%u\n", 3295 RTW89_ROC_BY_LINK_INDEX); 3296 return; 3297 } 3298 3299 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC); 3300 3301 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true); 3302 if (ret) 3303 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3304 "roc send null-1 failed: %d\n", ret); 3305 3306 rtw89_for_each_rtwvif(rtwdev, tmp_vif) { 3307 struct rtw89_vif_link *tmp_link; 3308 unsigned int link_id; 3309 3310 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) { 3311 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) { 3312 tmp_vif->offchan = true; 3313 break; 3314 } 3315 } 3316 } 3317 3318 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 3319 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, &roc_chan); 3320 rtw89_set_channel(rtwdev); 3321 3322 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3323 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 3324 3325 ieee80211_ready_on_channel(hw); 3326 cancel_delayed_work(&rtwvif->roc.roc_work); 3327 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 3328 msecs_to_jiffies(rtwvif->roc.duration)); 3329 } 3330 3331 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3332 { 3333 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3334 struct ieee80211_hw *hw = rtwdev->hw; 3335 struct rtw89_roc *roc = &rtwvif->roc; 3336 struct rtw89_vif_link *rtwvif_link; 3337 struct rtw89_vif *tmp_vif; 3338 u32 reg; 3339 int ret; 3340 3341 lockdep_assert_held(&rtwdev->mutex); 3342 3343 ieee80211_remain_on_channel_expired(hw); 3344 3345 rtw89_leave_ips_by_hwflags(rtwdev); 3346 rtw89_leave_lps(rtwdev); 3347 3348 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX); 3349 if (unlikely(!rtwvif_link)) { 3350 rtw89_err(rtwdev, "roc end: find no link on HW-%u\n", 3351 RTW89_ROC_BY_LINK_INDEX); 3352 return; 3353 } 3354 3355 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3356 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr); 3357 3358 roc->state = RTW89_ROC_IDLE; 3359 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, NULL); 3360 rtw89_chanctx_proceed(rtwdev); 3361 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false); 3362 if (ret) 3363 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3364 "roc send null-0 failed: %d\n", ret); 3365 3366 rtw89_for_each_rtwvif(rtwdev, tmp_vif) 3367 tmp_vif->offchan = false; 3368 3369 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link); 3370 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3371 3372 if (hw->conf.flags & IEEE80211_CONF_IDLE) 3373 ieee80211_queue_delayed_work(hw, &roc->roc_work, 3374 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 3375 } 3376 3377 void rtw89_roc_work(struct work_struct *work) 3378 { 3379 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3380 roc.roc_work.work); 3381 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3382 struct rtw89_roc *roc = &rtwvif->roc; 3383 3384 mutex_lock(&rtwdev->mutex); 3385 3386 switch (roc->state) { 3387 case RTW89_ROC_IDLE: 3388 rtw89_enter_ips_by_hwflags(rtwdev); 3389 break; 3390 case RTW89_ROC_MGMT: 3391 case RTW89_ROC_NORMAL: 3392 rtw89_roc_end(rtwdev, rtwvif); 3393 break; 3394 default: 3395 break; 3396 } 3397 3398 mutex_unlock(&rtwdev->mutex); 3399 } 3400 3401 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3402 u32 throughput, u64 cnt) 3403 { 3404 if (cnt < 100) 3405 return RTW89_TFC_IDLE; 3406 if (throughput > 50) 3407 return RTW89_TFC_HIGH; 3408 if (throughput > 10) 3409 return RTW89_TFC_MID; 3410 if (throughput > 2) 3411 return RTW89_TFC_LOW; 3412 return RTW89_TFC_ULTRA_LOW; 3413 } 3414 3415 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3416 struct rtw89_traffic_stats *stats) 3417 { 3418 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3419 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3420 3421 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 3422 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3423 3424 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3425 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3426 3427 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3428 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3429 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3430 stats->tx_cnt); 3431 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3432 stats->rx_cnt); 3433 stats->tx_avg_len = stats->tx_cnt ? 3434 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3435 stats->rx_avg_len = stats->rx_cnt ? 3436 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3437 3438 stats->tx_unicast = 0; 3439 stats->rx_unicast = 0; 3440 stats->tx_cnt = 0; 3441 stats->rx_cnt = 0; 3442 stats->rx_tf_periodic = stats->rx_tf_acc; 3443 stats->rx_tf_acc = 0; 3444 3445 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3446 return true; 3447 3448 return false; 3449 } 3450 3451 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3452 { 3453 struct rtw89_vif_link *rtwvif_link; 3454 struct rtw89_vif *rtwvif; 3455 unsigned int link_id; 3456 bool tfc_changed; 3457 3458 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3459 3460 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3461 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3462 3463 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3464 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link); 3465 } 3466 3467 return tfc_changed; 3468 } 3469 3470 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3471 { 3472 struct ieee80211_vif *vif; 3473 struct rtw89_vif *rtwvif; 3474 3475 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3476 if (rtwvif->tdls_peer) 3477 continue; 3478 if (rtwvif->offchan) 3479 continue; 3480 3481 if (rtwvif->stats.tx_tfc_lv != RTW89_TFC_IDLE || 3482 rtwvif->stats.rx_tfc_lv != RTW89_TFC_IDLE) 3483 continue; 3484 3485 vif = rtwvif_to_vif(rtwvif); 3486 3487 if (!(vif->type == NL80211_IFTYPE_STATION || 3488 vif->type == NL80211_IFTYPE_P2P_CLIENT)) 3489 continue; 3490 3491 rtw89_enter_lps(rtwdev, rtwvif, true); 3492 } 3493 } 3494 3495 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3496 { 3497 enum rtw89_entity_mode mode; 3498 3499 mode = rtw89_get_entity_mode(rtwdev); 3500 if (mode == RTW89_ENTITY_MODE_MCC) 3501 return; 3502 3503 rtw89_chip_rfk_track(rtwdev); 3504 } 3505 3506 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 3507 struct rtw89_vif_link *rtwvif_link, 3508 struct ieee80211_bss_conf *bss_conf) 3509 { 3510 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3511 3512 if (mode == RTW89_ENTITY_MODE_MCC) 3513 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3514 else 3515 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf); 3516 } 3517 3518 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3519 struct rtw89_traffic_stats *stats) 3520 { 3521 stats->tx_unicast = 0; 3522 stats->rx_unicast = 0; 3523 stats->tx_cnt = 0; 3524 stats->rx_cnt = 0; 3525 ewma_tp_init(&stats->tx_ewma_tp); 3526 ewma_tp_init(&stats->rx_ewma_tp); 3527 } 3528 3529 static void rtw89_track_work(struct work_struct *work) 3530 { 3531 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3532 track_work.work); 3533 bool tfc_changed; 3534 3535 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3536 return; 3537 3538 mutex_lock(&rtwdev->mutex); 3539 3540 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3541 goto out; 3542 3543 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3544 RTW89_TRACK_WORK_PERIOD); 3545 3546 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3547 if (rtwdev->scanning) 3548 goto out; 3549 3550 rtw89_leave_lps(rtwdev); 3551 3552 if (tfc_changed) { 3553 rtw89_hci_recalc_int_mit(rtwdev); 3554 rtw89_btc_ntfy_wl_sta(rtwdev); 3555 } 3556 rtw89_mac_bf_monitor_track(rtwdev); 3557 rtw89_phy_stat_track(rtwdev); 3558 rtw89_phy_env_monitor_track(rtwdev); 3559 rtw89_phy_dig(rtwdev); 3560 rtw89_core_rfk_track(rtwdev); 3561 rtw89_phy_ra_update(rtwdev); 3562 rtw89_phy_cfo_track(rtwdev); 3563 rtw89_phy_tx_path_div_track(rtwdev); 3564 rtw89_phy_antdiv_track(rtwdev); 3565 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3566 rtw89_phy_edcca_track(rtwdev); 3567 rtw89_tas_track(rtwdev); 3568 rtw89_chanctx_track(rtwdev); 3569 rtw89_core_rfkill_poll(rtwdev, false); 3570 3571 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3572 rtw89_enter_lps_track(rtwdev); 3573 3574 out: 3575 mutex_unlock(&rtwdev->mutex); 3576 } 3577 3578 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3579 { 3580 unsigned long bit; 3581 3582 bit = find_first_zero_bit(addr, size); 3583 if (bit < size) 3584 set_bit(bit, addr); 3585 3586 return bit; 3587 } 3588 3589 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3590 { 3591 clear_bit(bit, addr); 3592 } 3593 3594 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3595 { 3596 bitmap_zero(addr, nbits); 3597 } 3598 3599 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3600 struct rtw89_sta_link *rtwsta_link, u8 tid, 3601 u8 *cam_idx) 3602 { 3603 const struct rtw89_chip_info *chip = rtwdev->chip; 3604 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3605 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3606 u8 idx; 3607 int i; 3608 3609 lockdep_assert_held(&rtwdev->mutex); 3610 3611 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3612 if (idx == chip->bacam_num) { 3613 /* allocate a static BA CAM to tid=0/5, so replace the existing 3614 * one if BA CAM is full. Hardware will process the original tid 3615 * automatically. 3616 */ 3617 if (tid != 0 && tid != 5) 3618 return -ENOSPC; 3619 3620 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3621 tmp = &cam_info->ba_cam_entry[i]; 3622 if (tmp->tid == 0 || tmp->tid == 5) 3623 continue; 3624 3625 idx = i; 3626 entry = tmp; 3627 list_del(&entry->list); 3628 break; 3629 } 3630 3631 if (!entry) 3632 return -ENOSPC; 3633 } else { 3634 entry = &cam_info->ba_cam_entry[idx]; 3635 } 3636 3637 entry->tid = tid; 3638 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list); 3639 3640 *cam_idx = idx; 3641 3642 return 0; 3643 } 3644 3645 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3646 struct rtw89_sta_link *rtwsta_link, u8 tid, 3647 u8 *cam_idx) 3648 { 3649 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3650 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3651 u8 idx; 3652 3653 lockdep_assert_held(&rtwdev->mutex); 3654 3655 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) { 3656 if (entry->tid != tid) 3657 continue; 3658 3659 idx = entry - cam_info->ba_cam_entry; 3660 list_del(&entry->list); 3661 3662 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3663 *cam_idx = idx; 3664 return 0; 3665 } 3666 3667 return -ENOENT; 3668 } 3669 3670 #define RTW89_TYPE_MAPPING(_type) \ 3671 case NL80211_IFTYPE_ ## _type: \ 3672 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3673 break 3674 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc) 3675 { 3676 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3677 const struct ieee80211_bss_conf *bss_conf; 3678 3679 switch (vif->type) { 3680 case NL80211_IFTYPE_STATION: 3681 if (vif->p2p) 3682 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3683 else 3684 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION; 3685 break; 3686 case NL80211_IFTYPE_AP: 3687 if (vif->p2p) 3688 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3689 else 3690 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP; 3691 break; 3692 RTW89_TYPE_MAPPING(ADHOC); 3693 RTW89_TYPE_MAPPING(MONITOR); 3694 RTW89_TYPE_MAPPING(MESH_POINT); 3695 default: 3696 WARN_ON(1); 3697 break; 3698 } 3699 3700 switch (vif->type) { 3701 case NL80211_IFTYPE_AP: 3702 case NL80211_IFTYPE_MESH_POINT: 3703 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE; 3704 rtwvif_link->self_role = RTW89_SELF_ROLE_AP; 3705 break; 3706 case NL80211_IFTYPE_ADHOC: 3707 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC; 3708 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 3709 break; 3710 case NL80211_IFTYPE_STATION: 3711 if (assoc) { 3712 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA; 3713 3714 rcu_read_lock(); 3715 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 3716 rtwvif_link->trigger = bss_conf->he_support; 3717 rcu_read_unlock(); 3718 } else { 3719 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 3720 rtwvif_link->trigger = false; 3721 } 3722 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 3723 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3724 break; 3725 case NL80211_IFTYPE_MONITOR: 3726 break; 3727 default: 3728 WARN_ON(1); 3729 break; 3730 } 3731 } 3732 3733 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 3734 struct rtw89_vif_link *rtwvif_link, 3735 struct rtw89_sta_link *rtwsta_link) 3736 { 3737 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3738 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3739 struct rtw89_hal *hal = &rtwdev->hal; 3740 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3741 int i; 3742 int ret; 3743 3744 rtwsta_link->prev_rssi = 0; 3745 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list); 3746 ewma_rssi_init(&rtwsta_link->avg_rssi); 3747 ewma_snr_init(&rtwsta_link->avg_snr); 3748 ewma_evm_init(&rtwsta_link->evm_1ss); 3749 for (i = 0; i < ant_num; i++) { 3750 ewma_rssi_init(&rtwsta_link->rssi[i]); 3751 ewma_evm_init(&rtwsta_link->evm_min[i]); 3752 ewma_evm_init(&rtwsta_link->evm_max[i]); 3753 } 3754 3755 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3756 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 3757 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true); 3758 if (ret) 3759 return ret; 3760 3761 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 3762 BTC_ROLE_MSTS_STA_CONN_START); 3763 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 3764 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3765 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false); 3766 if (ret) { 3767 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3768 return ret; 3769 } 3770 3771 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 3772 RTW89_ROLE_CREATE); 3773 if (ret) { 3774 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3775 return ret; 3776 } 3777 3778 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3779 if (ret) 3780 return ret; 3781 3782 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3783 if (ret) 3784 return ret; 3785 } 3786 3787 return 0; 3788 } 3789 3790 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 3791 struct rtw89_vif_link *rtwvif_link, 3792 struct rtw89_sta_link *rtwsta_link) 3793 { 3794 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3795 3796 rtw89_assoc_link_clr(rtwsta_link); 3797 3798 if (vif->type == NL80211_IFTYPE_STATION) 3799 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false); 3800 3801 return 0; 3802 } 3803 3804 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 3805 struct rtw89_vif_link *rtwvif_link, 3806 struct rtw89_sta_link *rtwsta_link) 3807 { 3808 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3809 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3810 int ret; 3811 3812 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true); 3813 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link); 3814 3815 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 3816 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam); 3817 if (sta->tdls) 3818 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam); 3819 3820 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3821 rtw89_vif_type_mapping(rtwvif_link, false); 3822 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true); 3823 } 3824 3825 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3826 if (ret) { 3827 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3828 return ret; 3829 } 3830 3831 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true); 3832 if (ret) { 3833 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3834 return ret; 3835 } 3836 3837 /* update cam aid mac_id net_type */ 3838 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 3839 if (ret) { 3840 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3841 return ret; 3842 } 3843 3844 return ret; 3845 } 3846 3847 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev, 3848 struct ieee80211_bss_conf *bss_conf, 3849 struct ieee80211_link_sta *link_sta) 3850 { 3851 if (!bss_conf->he_support || 3852 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE) 3853 return false; 3854 3855 if (rtwdev->chip->chip_id == RTL8852C && 3856 rtw89_sta_link_has_su_mu_4xhe08(link_sta) && 3857 !rtw89_sta_link_has_er_su_4xhe08(link_sta)) 3858 return false; 3859 3860 return true; 3861 } 3862 3863 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 3864 struct rtw89_vif_link *rtwvif_link, 3865 struct rtw89_sta_link *rtwsta_link) 3866 { 3867 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3868 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3869 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link, 3870 rtwsta_link); 3871 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3872 rtwvif_link->chanctx_idx); 3873 struct ieee80211_link_sta *link_sta; 3874 int ret; 3875 3876 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3877 if (sta->tdls) { 3878 rcu_read_lock(); 3879 3880 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3881 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam, 3882 link_sta->addr); 3883 if (ret) { 3884 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3885 rcu_read_unlock(); 3886 return ret; 3887 } 3888 3889 rcu_read_unlock(); 3890 } 3891 3892 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam); 3893 if (ret) { 3894 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3895 return ret; 3896 } 3897 } 3898 3899 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3900 if (ret) { 3901 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3902 return ret; 3903 } 3904 3905 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false); 3906 if (ret) { 3907 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3908 return ret; 3909 } 3910 3911 /* update cam aid mac_id net_type */ 3912 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 3913 if (ret) { 3914 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3915 return ret; 3916 } 3917 3918 rtw89_phy_ra_assoc(rtwdev, rtwsta_link); 3919 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 3920 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false); 3921 3922 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3923 struct ieee80211_bss_conf *bss_conf; 3924 3925 rcu_read_lock(); 3926 3927 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 3928 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3929 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta); 3930 3931 rcu_read_unlock(); 3932 3933 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 3934 BTC_ROLE_MSTS_STA_CONN_END); 3935 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan); 3936 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link); 3937 3938 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id); 3939 if (ret) { 3940 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3941 return ret; 3942 } 3943 3944 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 3945 } 3946 3947 rtw89_assoc_link_set(rtwsta_link); 3948 return ret; 3949 } 3950 3951 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 3952 struct rtw89_vif_link *rtwvif_link, 3953 struct rtw89_sta_link *rtwsta_link) 3954 { 3955 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3956 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3957 int ret; 3958 3959 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3960 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false); 3961 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 3962 BTC_ROLE_MSTS_STA_DIS_CONN); 3963 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3964 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 3965 RTW89_ROLE_REMOVE); 3966 if (ret) { 3967 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3968 return ret; 3969 } 3970 } 3971 3972 return 0; 3973 } 3974 3975 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3976 struct ieee80211_sta *sta, 3977 struct cfg80211_tid_cfg *tid_conf) 3978 { 3979 struct ieee80211_txq *txq; 3980 struct rtw89_txq *rtwtxq; 3981 u32 mask = tid_conf->mask; 3982 u8 tids = tid_conf->tids; 3983 int tids_nbit = BITS_PER_BYTE; 3984 int i; 3985 3986 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3987 if (!tids) 3988 break; 3989 3990 if (!(tids & BIT(0))) 3991 continue; 3992 3993 txq = sta->txq[i]; 3994 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3995 3996 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 3997 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 3998 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3999 } else { 4000 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 4001 ieee80211_stop_tx_ba_session(sta, txq->tid); 4002 spin_lock_bh(&rtwdev->ba_lock); 4003 list_del_init(&rtwtxq->list); 4004 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4005 spin_unlock_bh(&rtwdev->ba_lock); 4006 } 4007 } 4008 4009 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 4010 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 4011 sta->max_amsdu_subframes = 0; 4012 else 4013 sta->max_amsdu_subframes = 1; 4014 } 4015 } 4016 } 4017 4018 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4019 struct ieee80211_sta *sta, 4020 struct cfg80211_tid_config *tid_config) 4021 { 4022 int i; 4023 4024 for (i = 0; i < tid_config->n_tid_conf; i++) 4025 _rtw89_core_set_tid_config(rtwdev, sta, 4026 &tid_config->tid_conf[i]); 4027 } 4028 4029 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 4030 struct ieee80211_sta_ht_cap *ht_cap) 4031 { 4032 static const __le16 highest[RF_PATH_MAX] = { 4033 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 4034 }; 4035 struct rtw89_hal *hal = &rtwdev->hal; 4036 u8 nss = hal->rx_nss; 4037 int i; 4038 4039 ht_cap->ht_supported = true; 4040 ht_cap->cap = 0; 4041 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 4042 IEEE80211_HT_CAP_MAX_AMSDU | 4043 IEEE80211_HT_CAP_TX_STBC | 4044 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 4045 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 4046 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 4047 IEEE80211_HT_CAP_DSSSCCK40 | 4048 IEEE80211_HT_CAP_SGI_40; 4049 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 4050 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 4051 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 4052 for (i = 0; i < nss; i++) 4053 ht_cap->mcs.rx_mask[i] = 0xFF; 4054 ht_cap->mcs.rx_mask[4] = 0x01; 4055 ht_cap->mcs.rx_highest = highest[nss - 1]; 4056 } 4057 4058 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 4059 struct ieee80211_sta_vht_cap *vht_cap) 4060 { 4061 static const __le16 highest_bw80[RF_PATH_MAX] = { 4062 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 4063 }; 4064 static const __le16 highest_bw160[RF_PATH_MAX] = { 4065 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 4066 }; 4067 const struct rtw89_chip_info *chip = rtwdev->chip; 4068 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 4069 highest_bw160 : highest_bw80; 4070 struct rtw89_hal *hal = &rtwdev->hal; 4071 u16 tx_mcs_map = 0, rx_mcs_map = 0; 4072 u8 sts_cap = 3; 4073 int i; 4074 4075 for (i = 0; i < 8; i++) { 4076 if (i < hal->tx_nss) 4077 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4078 else 4079 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4080 if (i < hal->rx_nss) 4081 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4082 else 4083 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4084 } 4085 4086 vht_cap->vht_supported = true; 4087 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 4088 IEEE80211_VHT_CAP_SHORT_GI_80 | 4089 IEEE80211_VHT_CAP_RXSTBC_1 | 4090 IEEE80211_VHT_CAP_HTC_VHT | 4091 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 4092 0; 4093 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 4094 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 4095 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 4096 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 4097 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 4098 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4099 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 4100 IEEE80211_VHT_CAP_SHORT_GI_160; 4101 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 4102 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 4103 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 4104 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 4105 4106 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 4107 vht_cap->vht_mcs.tx_highest |= 4108 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 4109 } 4110 4111 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 4112 enum nl80211_band band, 4113 enum nl80211_iftype iftype, 4114 struct ieee80211_sband_iftype_data *iftype_data) 4115 { 4116 const struct rtw89_chip_info *chip = rtwdev->chip; 4117 struct rtw89_hal *hal = &rtwdev->hal; 4118 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 4119 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 4120 struct ieee80211_sta_he_cap *he_cap; 4121 int nss = hal->rx_nss; 4122 u8 *mac_cap_info; 4123 u8 *phy_cap_info; 4124 u16 mcs_map = 0; 4125 int i; 4126 4127 for (i = 0; i < 8; i++) { 4128 if (i < nss) 4129 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 4130 else 4131 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 4132 } 4133 4134 he_cap = &iftype_data->he_cap; 4135 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 4136 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 4137 4138 he_cap->has_he = true; 4139 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 4140 if (iftype == NL80211_IFTYPE_STATION) 4141 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 4142 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 4143 IEEE80211_HE_MAC_CAP2_BSR; 4144 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 4145 if (iftype == NL80211_IFTYPE_AP) 4146 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 4147 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 4148 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 4149 if (iftype == NL80211_IFTYPE_STATION) 4150 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 4151 if (band == NL80211_BAND_2GHZ) { 4152 phy_cap_info[0] = 4153 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 4154 } else { 4155 phy_cap_info[0] = 4156 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 4157 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4158 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 4159 } 4160 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 4161 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 4162 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 4163 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 4164 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 4165 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 4166 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 4167 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 4168 if (iftype == NL80211_IFTYPE_STATION) 4169 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 4170 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 4171 if (iftype == NL80211_IFTYPE_AP) 4172 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 4173 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 4174 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 4175 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4176 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 4177 phy_cap_info[5] = no_ng16 ? 0 : 4178 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 4179 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 4180 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 4181 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 4182 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 4183 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 4184 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 4185 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 4186 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 4187 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 4188 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 4189 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 4190 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4191 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 4192 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 4193 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 4194 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 4195 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 4196 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 4197 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 4198 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 4199 if (iftype == NL80211_IFTYPE_STATION) 4200 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 4201 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 4202 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 4203 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 4204 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 4205 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 4206 } 4207 4208 if (band == NL80211_BAND_6GHZ) { 4209 __le16 capa; 4210 4211 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 4212 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 4213 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 4214 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 4215 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 4216 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 4217 iftype_data->he_6ghz_capa.capa = capa; 4218 } 4219 } 4220 4221 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 4222 enum nl80211_band band, 4223 enum nl80211_iftype iftype, 4224 struct ieee80211_sband_iftype_data *iftype_data) 4225 { 4226 const struct rtw89_chip_info *chip = rtwdev->chip; 4227 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 4228 struct ieee80211_eht_mcs_nss_supp *eht_nss; 4229 struct ieee80211_sta_eht_cap *eht_cap; 4230 struct rtw89_hal *hal = &rtwdev->hal; 4231 bool support_320mhz = false; 4232 int sts = 8; 4233 u8 val; 4234 4235 if (chip->chip_gen == RTW89_CHIP_AX) 4236 return; 4237 4238 if (band == NL80211_BAND_6GHZ && 4239 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 4240 support_320mhz = true; 4241 4242 eht_cap = &iftype_data->eht_cap; 4243 eht_cap_elem = &eht_cap->eht_cap_elem; 4244 eht_nss = &eht_cap->eht_mcs_nss_supp; 4245 4246 eht_cap->has_eht = true; 4247 4248 eht_cap_elem->mac_cap_info[0] = 4249 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 4250 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 4251 eht_cap_elem->mac_cap_info[1] = 0; 4252 4253 eht_cap_elem->phy_cap_info[0] = 4254 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 4255 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 4256 if (support_320mhz) 4257 eht_cap_elem->phy_cap_info[0] |= 4258 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 4259 4260 eht_cap_elem->phy_cap_info[0] |= 4261 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 4262 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 4263 eht_cap_elem->phy_cap_info[1] = 4264 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 4265 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 4266 u8_encode_bits(sts - 1, 4267 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 4268 if (support_320mhz) 4269 eht_cap_elem->phy_cap_info[1] |= 4270 u8_encode_bits(sts - 1, 4271 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 4272 4273 eht_cap_elem->phy_cap_info[2] = 0; 4274 4275 eht_cap_elem->phy_cap_info[3] = 4276 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 4277 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 4278 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 4279 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 4280 4281 eht_cap_elem->phy_cap_info[4] = 4282 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 4283 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 4284 4285 eht_cap_elem->phy_cap_info[5] = 4286 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 4287 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 4288 4289 eht_cap_elem->phy_cap_info[6] = 0; 4290 eht_cap_elem->phy_cap_info[7] = 0; 4291 eht_cap_elem->phy_cap_info[8] = 0; 4292 4293 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 4294 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 4295 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 4296 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 4297 eht_nss->bw._80.rx_tx_mcs13_max_nss = val; 4298 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 4299 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 4300 eht_nss->bw._160.rx_tx_mcs13_max_nss = val; 4301 if (support_320mhz) { 4302 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 4303 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 4304 eht_nss->bw._320.rx_tx_mcs13_max_nss = val; 4305 } 4306 } 4307 4308 #define RTW89_SBAND_IFTYPES_NR 2 4309 4310 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 4311 enum nl80211_band band, 4312 struct ieee80211_supported_band *sband) 4313 { 4314 struct ieee80211_sband_iftype_data *iftype_data; 4315 enum nl80211_iftype iftype; 4316 int idx = 0; 4317 4318 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 4319 if (!iftype_data) 4320 return; 4321 4322 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 4323 switch (iftype) { 4324 case NL80211_IFTYPE_STATION: 4325 case NL80211_IFTYPE_AP: 4326 break; 4327 default: 4328 continue; 4329 } 4330 4331 if (idx >= RTW89_SBAND_IFTYPES_NR) { 4332 rtw89_warn(rtwdev, "run out of iftype_data\n"); 4333 break; 4334 } 4335 4336 iftype_data[idx].types_mask = BIT(iftype); 4337 4338 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 4339 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 4340 4341 idx++; 4342 } 4343 4344 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 4345 } 4346 4347 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 4348 { 4349 struct ieee80211_hw *hw = rtwdev->hw; 4350 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 4351 struct ieee80211_supported_band *sband_6ghz = NULL; 4352 u32 size = sizeof(struct ieee80211_supported_band); 4353 u8 support_bands = rtwdev->chip->support_bands; 4354 4355 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 4356 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 4357 if (!sband_2ghz) 4358 goto err; 4359 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 4360 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 4361 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 4362 } 4363 4364 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 4365 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 4366 if (!sband_5ghz) 4367 goto err; 4368 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 4369 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 4370 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 4371 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 4372 } 4373 4374 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 4375 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 4376 if (!sband_6ghz) 4377 goto err; 4378 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 4379 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 4380 } 4381 4382 return 0; 4383 4384 err: 4385 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4386 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4387 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4388 if (sband_2ghz) 4389 kfree((__force void *)sband_2ghz->iftype_data); 4390 if (sband_5ghz) 4391 kfree((__force void *)sband_5ghz->iftype_data); 4392 if (sband_6ghz) 4393 kfree((__force void *)sband_6ghz->iftype_data); 4394 kfree(sband_2ghz); 4395 kfree(sband_5ghz); 4396 kfree(sband_6ghz); 4397 return -ENOMEM; 4398 } 4399 4400 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 4401 { 4402 struct ieee80211_hw *hw = rtwdev->hw; 4403 4404 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 4405 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 4406 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 4407 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 4408 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 4409 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 4410 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 4411 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 4412 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 4413 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4414 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4415 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4416 } 4417 4418 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 4419 { 4420 int i; 4421 4422 for (i = 0; i < RTW89_PHY_MAX; i++) 4423 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4424 for (i = 0; i < RTW89_PHY_MAX; i++) 4425 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4426 } 4427 4428 void rtw89_core_update_beacon_work(struct work_struct *work) 4429 { 4430 struct rtw89_dev *rtwdev; 4431 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link, 4432 update_beacon_work); 4433 4434 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4435 return; 4436 4437 rtwdev = rtwvif_link->rtwvif->rtwdev; 4438 4439 mutex_lock(&rtwdev->mutex); 4440 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 4441 mutex_unlock(&rtwdev->mutex); 4442 } 4443 4444 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4445 { 4446 struct completion *cmpl = &wait->completion; 4447 unsigned long time_left; 4448 unsigned int cur; 4449 4450 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4451 if (cur != RTW89_WAIT_COND_IDLE) 4452 return -EBUSY; 4453 4454 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4455 if (time_left == 0) { 4456 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4457 return -ETIMEDOUT; 4458 } 4459 4460 if (wait->data.err) 4461 return -EFAULT; 4462 4463 return 0; 4464 } 4465 4466 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4467 const struct rtw89_completion_data *data) 4468 { 4469 unsigned int cur; 4470 4471 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4472 if (cur != cond) 4473 return; 4474 4475 wait->data = *data; 4476 complete(&wait->completion); 4477 } 4478 4479 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4480 { 4481 u16 bt_req_len; 4482 4483 switch (event) { 4484 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4485 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4486 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4487 "coex updates BT req len to %d TU\n", bt_req_len); 4488 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4489 break; 4490 default: 4491 if (event < NUM_OF_RTW89_BTC_HMSG) 4492 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4493 "unhandled BTC HMSG event: %d\n", event); 4494 else 4495 rtw89_warn(rtwdev, 4496 "unrecognized BTC HMSG event: %d\n", event); 4497 break; 4498 } 4499 } 4500 4501 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4502 { 4503 const struct dmi_system_id *match; 4504 enum rtw89_quirks quirk; 4505 4506 if (!quirks) 4507 return; 4508 4509 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4510 quirk = (uintptr_t)match->driver_data; 4511 if (quirk >= NUM_OF_RTW89_QUIRKS) 4512 continue; 4513 4514 set_bit(quirk, rtwdev->quirks); 4515 } 4516 } 4517 EXPORT_SYMBOL(rtw89_check_quirks); 4518 4519 int rtw89_core_start(struct rtw89_dev *rtwdev) 4520 { 4521 int ret; 4522 4523 ret = rtw89_mac_init(rtwdev); 4524 if (ret) { 4525 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4526 return ret; 4527 } 4528 4529 rtw89_btc_ntfy_poweron(rtwdev); 4530 4531 /* efuse process */ 4532 4533 /* pre-config BB/RF, BB reset/RFC reset */ 4534 ret = rtw89_chip_reset_bb_rf(rtwdev); 4535 if (ret) 4536 return ret; 4537 4538 rtw89_phy_init_bb_reg(rtwdev); 4539 rtw89_chip_bb_postinit(rtwdev); 4540 rtw89_phy_init_rf_reg(rtwdev, false); 4541 4542 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4543 4544 rtw89_phy_dm_init(rtwdev); 4545 4546 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true); 4547 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true); 4548 rtw89_mac_update_rts_threshold(rtwdev); 4549 4550 rtw89_tas_reset(rtwdev); 4551 4552 ret = rtw89_hci_start(rtwdev); 4553 if (ret) { 4554 rtw89_err(rtwdev, "failed to start hci\n"); 4555 return ret; 4556 } 4557 4558 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 4559 RTW89_TRACK_WORK_PERIOD); 4560 4561 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4562 4563 rtw89_chip_rfk_init_late(rtwdev); 4564 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4565 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4566 rtw89_fw_h2c_init_ba_cam(rtwdev); 4567 4568 return 0; 4569 } 4570 4571 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4572 { 4573 struct rtw89_btc *btc = &rtwdev->btc; 4574 4575 /* Prvent to stop twice; enter_ips and ops_stop */ 4576 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4577 return; 4578 4579 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4580 4581 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4582 4583 mutex_unlock(&rtwdev->mutex); 4584 4585 cancel_work_sync(&rtwdev->c2h_work); 4586 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work); 4587 cancel_work_sync(&btc->eapol_notify_work); 4588 cancel_work_sync(&btc->arp_notify_work); 4589 cancel_work_sync(&btc->dhcp_notify_work); 4590 cancel_work_sync(&btc->icmp_notify_work); 4591 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4592 cancel_delayed_work_sync(&rtwdev->track_work); 4593 cancel_delayed_work_sync(&rtwdev->chanctx_work); 4594 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 4595 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 4596 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 4597 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 4598 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4599 cancel_delayed_work_sync(&rtwdev->antdiv_work); 4600 4601 mutex_lock(&rtwdev->mutex); 4602 4603 rtw89_btc_ntfy_poweroff(rtwdev); 4604 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4605 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4606 rtw89_hci_stop(rtwdev); 4607 rtw89_hci_deinit(rtwdev); 4608 rtw89_mac_pwr_off(rtwdev); 4609 rtw89_hci_reset(rtwdev); 4610 } 4611 4612 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 4613 { 4614 const struct rtw89_chip_info *chip = rtwdev->chip; 4615 u8 mac_id_num; 4616 u8 mac_id; 4617 4618 if (rtwdev->support_mlo) 4619 mac_id_num = chip->support_macid_num / chip->support_link_num; 4620 else 4621 mac_id_num = chip->support_macid_num; 4622 4623 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 4624 if (mac_id == mac_id_num) 4625 return RTW89_MAX_MAC_ID_NUM; 4626 4627 set_bit(mac_id, rtwdev->mac_id_map); 4628 return mac_id; 4629 } 4630 4631 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 4632 { 4633 clear_bit(mac_id, rtwdev->mac_id_map); 4634 } 4635 4636 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4637 u8 mac_id, u8 port) 4638 { 4639 const struct rtw89_chip_info *chip = rtwdev->chip; 4640 u8 support_link_num = chip->support_link_num; 4641 u8 support_mld_num = 0; 4642 unsigned int link_id; 4643 u8 index; 4644 4645 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 4646 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 4647 rtwvif->links[link_id] = NULL; 4648 4649 rtwvif->rtwdev = rtwdev; 4650 4651 if (rtwdev->support_mlo) { 4652 rtwvif->links_inst_valid_num = support_link_num; 4653 support_mld_num = chip->support_macid_num / support_link_num; 4654 } else { 4655 rtwvif->links_inst_valid_num = 1; 4656 } 4657 4658 for (index = 0; index < rtwvif->links_inst_valid_num; index++) { 4659 struct rtw89_vif_link *inst = &rtwvif->links_inst[index]; 4660 4661 inst->rtwvif = rtwvif; 4662 inst->mac_id = mac_id + index * support_mld_num; 4663 inst->mac_idx = RTW89_MAC_0 + index; 4664 inst->phy_idx = RTW89_PHY_0 + index; 4665 4666 /* multi-link use the same port id on different HW bands */ 4667 inst->port = port; 4668 } 4669 } 4670 4671 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4672 struct rtw89_sta *rtwsta, u8 mac_id) 4673 { 4674 const struct rtw89_chip_info *chip = rtwdev->chip; 4675 u8 support_link_num = chip->support_link_num; 4676 u8 support_mld_num = 0; 4677 unsigned int link_id; 4678 u8 index; 4679 4680 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 4681 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 4682 rtwsta->links[link_id] = NULL; 4683 4684 rtwsta->rtwdev = rtwdev; 4685 rtwsta->rtwvif = rtwvif; 4686 4687 if (rtwdev->support_mlo) { 4688 rtwsta->links_inst_valid_num = support_link_num; 4689 support_mld_num = chip->support_macid_num / support_link_num; 4690 } else { 4691 rtwsta->links_inst_valid_num = 1; 4692 } 4693 4694 for (index = 0; index < rtwsta->links_inst_valid_num; index++) { 4695 struct rtw89_sta_link *inst = &rtwsta->links_inst[index]; 4696 4697 inst->rtwvif_link = &rtwvif->links_inst[index]; 4698 4699 inst->rtwsta = rtwsta; 4700 inst->mac_id = mac_id + index * support_mld_num; 4701 } 4702 } 4703 4704 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 4705 unsigned int link_id) 4706 { 4707 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 4708 u8 index; 4709 int ret; 4710 4711 if (rtwvif_link) 4712 return rtwvif_link; 4713 4714 index = find_first_zero_bit(rtwvif->links_inst_map, 4715 rtwvif->links_inst_valid_num); 4716 if (index == rtwvif->links_inst_valid_num) { 4717 ret = -EBUSY; 4718 goto err; 4719 } 4720 4721 rtwvif_link = &rtwvif->links_inst[index]; 4722 rtwvif_link->link_id = link_id; 4723 4724 set_bit(index, rtwvif->links_inst_map); 4725 rtwvif->links[link_id] = rtwvif_link; 4726 return rtwvif_link; 4727 4728 err: 4729 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n", 4730 link_id, ret); 4731 return NULL; 4732 } 4733 4734 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id) 4735 { 4736 struct rtw89_vif_link **container = &rtwvif->links[link_id]; 4737 struct rtw89_vif_link *link = *container; 4738 u8 index; 4739 4740 if (!link) 4741 return; 4742 4743 index = rtw89_vif_link_inst_get_index(link); 4744 clear_bit(index, rtwvif->links_inst_map); 4745 *container = NULL; 4746 } 4747 4748 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 4749 unsigned int link_id) 4750 { 4751 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4752 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 4753 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id]; 4754 u8 index; 4755 int ret; 4756 4757 if (rtwsta_link) 4758 return rtwsta_link; 4759 4760 if (!rtwvif_link) { 4761 ret = -ENOLINK; 4762 goto err; 4763 } 4764 4765 index = rtw89_vif_link_inst_get_index(rtwvif_link); 4766 if (test_bit(index, rtwsta->links_inst_map)) { 4767 ret = -EBUSY; 4768 goto err; 4769 } 4770 4771 rtwsta_link = &rtwsta->links_inst[index]; 4772 rtwsta_link->link_id = link_id; 4773 4774 set_bit(index, rtwsta->links_inst_map); 4775 rtwsta->links[link_id] = rtwsta_link; 4776 return rtwsta_link; 4777 4778 err: 4779 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n", 4780 link_id, ret); 4781 return NULL; 4782 } 4783 4784 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id) 4785 { 4786 struct rtw89_sta_link **container = &rtwsta->links[link_id]; 4787 struct rtw89_sta_link *link = *container; 4788 u8 index; 4789 4790 if (!link) 4791 return; 4792 4793 index = rtw89_sta_link_inst_get_index(link); 4794 clear_bit(index, rtwsta->links_inst_map); 4795 *container = NULL; 4796 } 4797 4798 int rtw89_core_init(struct rtw89_dev *rtwdev) 4799 { 4800 struct rtw89_btc *btc = &rtwdev->btc; 4801 u8 band; 4802 4803 INIT_LIST_HEAD(&rtwdev->ba_list); 4804 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 4805 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 4806 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 4807 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 4808 if (!(rtwdev->chip->support_bands & BIT(band))) 4809 continue; 4810 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 4811 } 4812 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 4813 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 4814 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 4815 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 4816 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); 4817 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 4818 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 4819 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 4820 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 4821 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 4822 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 4823 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 4824 if (!rtwdev->txq_wq) 4825 return -ENOMEM; 4826 spin_lock_init(&rtwdev->ba_lock); 4827 spin_lock_init(&rtwdev->rpwm_lock); 4828 mutex_init(&rtwdev->mutex); 4829 mutex_init(&rtwdev->rf_mutex); 4830 rtwdev->total_sta_assoc = 0; 4831 4832 rtw89_init_wait(&rtwdev->mcc.wait); 4833 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 4834 rtw89_init_wait(&rtwdev->wow.wait); 4835 rtw89_init_wait(&rtwdev->mac.ps_wait); 4836 4837 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 4838 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 4839 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 4840 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 4841 4842 skb_queue_head_init(&rtwdev->c2h_queue); 4843 rtw89_core_ppdu_sts_init(rtwdev); 4844 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 4845 4846 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 4847 rtwdev->dbcc_en = false; 4848 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 4849 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 4850 4851 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4852 rtwdev->dbcc_en = true; 4853 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 4854 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF; 4855 } 4856 4857 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 4858 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 4859 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 4860 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 4861 4862 init_completion(&rtwdev->fw.req.completion); 4863 init_completion(&rtwdev->rfk_wait.completion); 4864 4865 schedule_work(&rtwdev->load_firmware_work); 4866 4867 rtw89_ser_init(rtwdev); 4868 rtw89_entity_init(rtwdev); 4869 rtw89_tas_init(rtwdev); 4870 rtw89_phy_ant_gain_init(rtwdev); 4871 4872 return 0; 4873 } 4874 EXPORT_SYMBOL(rtw89_core_init); 4875 4876 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 4877 { 4878 rtw89_ser_deinit(rtwdev); 4879 rtw89_unload_firmware(rtwdev); 4880 rtw89_fw_free_all_early_h2c(rtwdev); 4881 4882 destroy_workqueue(rtwdev->txq_wq); 4883 mutex_destroy(&rtwdev->rf_mutex); 4884 mutex_destroy(&rtwdev->mutex); 4885 } 4886 EXPORT_SYMBOL(rtw89_core_deinit); 4887 4888 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4889 const u8 *mac_addr, bool hw_scan) 4890 { 4891 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4892 rtwvif_link->chanctx_idx); 4893 4894 rtwdev->scanning = true; 4895 rtw89_leave_lps(rtwdev); 4896 if (hw_scan) 4897 rtw89_leave_ips_by_hwflags(rtwdev); 4898 4899 ether_addr_copy(rtwvif_link->mac_addr, mac_addr); 4900 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type); 4901 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true); 4902 rtw89_hci_recalc_int_mit(rtwdev); 4903 rtw89_phy_config_edcca(rtwdev, true); 4904 4905 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr); 4906 } 4907 4908 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4909 struct rtw89_vif_link *rtwvif_link, bool hw_scan) 4910 { 4911 struct ieee80211_bss_conf *bss_conf; 4912 4913 if (!rtwvif_link) 4914 return; 4915 4916 rcu_read_lock(); 4917 4918 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4919 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr); 4920 4921 rcu_read_unlock(); 4922 4923 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4924 4925 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false); 4926 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx); 4927 rtw89_phy_config_edcca(rtwdev, false); 4928 4929 rtwdev->scanning = false; 4930 rtwdev->dig.bypass_dig = true; 4931 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 4932 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 4933 } 4934 4935 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 4936 { 4937 const struct rtw89_chip_info *chip = rtwdev->chip; 4938 int ret; 4939 u8 val; 4940 u8 cv; 4941 4942 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 4943 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 4944 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 4945 cv = CHIP_CAV; 4946 else 4947 cv = CHIP_CBV; 4948 } 4949 4950 rtwdev->hal.cv = cv; 4951 4952 if (rtw89_is_rtl885xb(rtwdev)) { 4953 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 4954 if (ret) 4955 return; 4956 4957 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 4958 } 4959 } 4960 4961 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 4962 { 4963 const struct rtw89_chip_info *chip = rtwdev->chip; 4964 4965 rtwdev->hal.support_cckpd = 4966 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 4967 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 4968 rtwdev->hal.support_igi = 4969 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 4970 4971 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks)) 4972 rtwdev->hal.thermal_prot_th = chip->thermal_th[1]; 4973 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks)) 4974 rtwdev->hal.thermal_prot_th = chip->thermal_th[0]; 4975 else 4976 rtwdev->hal.thermal_prot_th = 0; 4977 } 4978 4979 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 4980 { 4981 const struct rtw89_chip_info *chip = rtwdev->chip; 4982 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 4983 struct rtw89_efuse *efuse = &rtwdev->efuse; 4984 const struct rtw89_rfe_parms *sel; 4985 u8 rfe_type = efuse->rfe_type; 4986 4987 if (!conf) { 4988 sel = chip->dflt_parms; 4989 goto out; 4990 } 4991 4992 while (conf->rfe_parms) { 4993 if (rfe_type == conf->rfe_type) { 4994 sel = conf->rfe_parms; 4995 goto out; 4996 } 4997 conf++; 4998 } 4999 5000 sel = chip->dflt_parms; 5001 5002 out: 5003 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 5004 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 5005 } 5006 5007 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 5008 { 5009 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5010 int ret; 5011 5012 ret = rtw89_mac_partial_init(rtwdev, false); 5013 if (ret) 5014 return ret; 5015 5016 ret = mac->parse_efuse_map(rtwdev); 5017 if (ret) 5018 return ret; 5019 5020 ret = mac->parse_phycap_map(rtwdev); 5021 if (ret) 5022 return ret; 5023 5024 ret = rtw89_mac_setup_phycap(rtwdev); 5025 if (ret) 5026 return ret; 5027 5028 rtw89_core_setup_phycap(rtwdev); 5029 5030 rtw89_hci_mac_pre_deinit(rtwdev); 5031 5032 rtw89_mac_pwr_off(rtwdev); 5033 5034 return 0; 5035 } 5036 5037 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 5038 { 5039 rtw89_chip_fem_setup(rtwdev); 5040 5041 return 0; 5042 } 5043 5044 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev) 5045 { 5046 return !!rtwdev->chip->rfkill_init; 5047 } 5048 5049 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev) 5050 { 5051 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init; 5052 5053 rtw89_write16_mask(rtwdev, regs->pinmux.addr, 5054 regs->pinmux.mask, regs->pinmux.data); 5055 rtw89_write16_mask(rtwdev, regs->mode.addr, 5056 regs->mode.mask, regs->mode.data); 5057 } 5058 5059 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev) 5060 { 5061 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get; 5062 5063 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask); 5064 } 5065 5066 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev) 5067 { 5068 if (!rtw89_chip_has_rfkill(rtwdev)) 5069 return; 5070 5071 rtw89_core_rfkill_init(rtwdev); 5072 rtw89_core_rfkill_poll(rtwdev, true); 5073 wiphy_rfkill_start_polling(rtwdev->hw->wiphy); 5074 } 5075 5076 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev) 5077 { 5078 if (!rtw89_chip_has_rfkill(rtwdev)) 5079 return; 5080 5081 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy); 5082 } 5083 5084 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force) 5085 { 5086 bool prev, blocked; 5087 5088 if (!rtw89_chip_has_rfkill(rtwdev)) 5089 return; 5090 5091 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5092 blocked = rtw89_core_rfkill_get(rtwdev); 5093 5094 if (!force && prev == blocked) 5095 return; 5096 5097 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n", 5098 blocked ? "disable" : "enable"); 5099 5100 if (blocked) 5101 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5102 else 5103 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5104 5105 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked); 5106 } 5107 5108 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 5109 { 5110 int ret; 5111 5112 rtw89_read_chip_ver(rtwdev); 5113 5114 ret = rtw89_wait_firmware_completion(rtwdev); 5115 if (ret) { 5116 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 5117 return ret; 5118 } 5119 5120 ret = rtw89_fw_recognize(rtwdev); 5121 if (ret) { 5122 rtw89_err(rtwdev, "failed to recognize firmware\n"); 5123 return ret; 5124 } 5125 5126 ret = rtw89_chip_efuse_info_setup(rtwdev); 5127 if (ret) 5128 return ret; 5129 5130 ret = rtw89_fw_recognize_elements(rtwdev); 5131 if (ret) { 5132 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 5133 return ret; 5134 } 5135 5136 ret = rtw89_chip_board_info_setup(rtwdev); 5137 if (ret) 5138 return ret; 5139 5140 rtw89_core_setup_rfe_parms(rtwdev); 5141 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 5142 5143 return 0; 5144 } 5145 EXPORT_SYMBOL(rtw89_chip_info_setup); 5146 5147 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5148 struct rtw89_vif_link *rtwvif_link) 5149 { 5150 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5151 const struct rtw89_chip_info *chip = rtwdev->chip; 5152 struct ieee80211_bss_conf *bss_conf; 5153 5154 rcu_read_lock(); 5155 5156 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 5157 if (!bss_conf->he_support || !vif->cfg.assoc) { 5158 rcu_read_unlock(); 5159 return; 5160 } 5161 5162 rcu_read_unlock(); 5163 5164 if (chip->ops->set_txpwr_ul_tb_offset) 5165 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx); 5166 } 5167 5168 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 5169 { 5170 const struct rtw89_chip_info *chip = rtwdev->chip; 5171 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1; 5172 struct ieee80211_hw *hw = rtwdev->hw; 5173 struct rtw89_efuse *efuse = &rtwdev->efuse; 5174 struct rtw89_hal *hal = &rtwdev->hal; 5175 int ret; 5176 int tx_headroom = IEEE80211_HT_CTL_LEN; 5177 5178 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n); 5179 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n); 5180 hw->txq_data_size = sizeof(struct rtw89_txq); 5181 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 5182 5183 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 5184 5185 hw->extra_tx_headroom = tx_headroom; 5186 hw->queues = IEEE80211_NUM_ACS; 5187 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 5188 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 5189 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 5190 5191 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 5192 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 5193 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 5194 5195 ieee80211_hw_set(hw, SIGNAL_DBM); 5196 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 5197 ieee80211_hw_set(hw, MFP_CAPABLE); 5198 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 5199 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 5200 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 5201 ieee80211_hw_set(hw, TX_AMSDU); 5202 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 5203 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 5204 ieee80211_hw_set(hw, SUPPORTS_PS); 5205 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 5206 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 5207 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 5208 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 5209 5210 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5211 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 5212 5213 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 5214 ieee80211_hw_set(hw, CONNECTION_MONITOR); 5215 5216 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw)) 5217 ieee80211_hw_set(hw, AP_LINK_PS); 5218 5219 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 5220 BIT(NL80211_IFTYPE_AP) | 5221 BIT(NL80211_IFTYPE_P2P_CLIENT) | 5222 BIT(NL80211_IFTYPE_P2P_GO); 5223 5224 if (hal->ant_diversity) { 5225 hw->wiphy->available_antennas_tx = 0x3; 5226 hw->wiphy->available_antennas_rx = 0x3; 5227 } else { 5228 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 5229 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 5230 } 5231 5232 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 5233 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 5234 WIPHY_FLAG_AP_UAPSD | 5235 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 5236 5237 if (!chip->support_rnr) 5238 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 5239 5240 if (chip->chip_gen == RTW89_CHIP_BE) 5241 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 5242 5243 if (rtwdev->support_mlo) 5244 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; 5245 5246 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 5247 5248 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5249 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 5250 5251 #ifdef CONFIG_PM 5252 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 5253 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5254 #endif 5255 5256 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5257 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5258 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5259 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5260 hw->wiphy->max_remain_on_channel_duration = 1000; 5261 5262 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 5263 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 5264 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 5265 5266 ret = rtw89_core_set_supported_band(rtwdev); 5267 if (ret) { 5268 rtw89_err(rtwdev, "failed to set supported band\n"); 5269 return ret; 5270 } 5271 5272 ret = rtw89_regd_setup(rtwdev); 5273 if (ret) { 5274 rtw89_err(rtwdev, "failed to set up regd\n"); 5275 goto err_free_supported_band; 5276 } 5277 5278 hw->wiphy->sar_capa = &rtw89_sar_capa; 5279 5280 ret = ieee80211_register_hw(hw); 5281 if (ret) { 5282 rtw89_err(rtwdev, "failed to register hw\n"); 5283 goto err_free_supported_band; 5284 } 5285 5286 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 5287 if (ret) { 5288 rtw89_err(rtwdev, "failed to init regd\n"); 5289 goto err_unregister_hw; 5290 } 5291 5292 rtw89_rfkill_polling_init(rtwdev); 5293 5294 return 0; 5295 5296 err_unregister_hw: 5297 ieee80211_unregister_hw(hw); 5298 err_free_supported_band: 5299 rtw89_core_clr_supported_band(rtwdev); 5300 5301 return ret; 5302 } 5303 5304 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 5305 { 5306 struct ieee80211_hw *hw = rtwdev->hw; 5307 5308 rtw89_rfkill_polling_deinit(rtwdev); 5309 ieee80211_unregister_hw(hw); 5310 rtw89_core_clr_supported_band(rtwdev); 5311 } 5312 5313 int rtw89_core_register(struct rtw89_dev *rtwdev) 5314 { 5315 int ret; 5316 5317 ret = rtw89_core_register_hw(rtwdev); 5318 if (ret) { 5319 rtw89_err(rtwdev, "failed to register core hw\n"); 5320 return ret; 5321 } 5322 5323 rtw89_debugfs_init(rtwdev); 5324 5325 return 0; 5326 } 5327 EXPORT_SYMBOL(rtw89_core_register); 5328 5329 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 5330 { 5331 rtw89_core_unregister_hw(rtwdev); 5332 5333 rtw89_debugfs_deinit(rtwdev); 5334 } 5335 EXPORT_SYMBOL(rtw89_core_unregister); 5336 5337 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5338 u32 bus_data_size, 5339 const struct rtw89_chip_info *chip) 5340 { 5341 struct rtw89_fw_info early_fw = {}; 5342 const struct firmware *firmware; 5343 struct ieee80211_hw *hw; 5344 struct rtw89_dev *rtwdev; 5345 struct ieee80211_ops *ops; 5346 u32 driver_data_size; 5347 int fw_format = -1; 5348 bool support_mlo; 5349 bool no_chanctx; 5350 5351 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 5352 5353 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 5354 if (!ops) 5355 goto err; 5356 5357 no_chanctx = chip->support_chanctx_num == 0 || 5358 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 5359 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 5360 5361 if (no_chanctx) { 5362 ops->add_chanctx = ieee80211_emulate_add_chanctx; 5363 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 5364 ops->change_chanctx = ieee80211_emulate_change_chanctx; 5365 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 5366 ops->assign_vif_chanctx = NULL; 5367 ops->unassign_vif_chanctx = NULL; 5368 ops->remain_on_channel = NULL; 5369 ops->cancel_remain_on_channel = NULL; 5370 } 5371 5372 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 5373 hw = ieee80211_alloc_hw(driver_data_size, ops); 5374 if (!hw) 5375 goto err; 5376 5377 /* TODO: When driver MLO arch. is done, determine whether to support MLO 5378 * according to the following conditions. 5379 * 1. run with chanctx_ops 5380 * 2. chip->support_link_num != 0 5381 * 3. FW feature supports AP_LINK_PS 5382 */ 5383 support_mlo = false; 5384 5385 hw->wiphy->iface_combinations = rtw89_iface_combs; 5386 5387 if (no_chanctx || chip->support_chanctx_num == 1) 5388 hw->wiphy->n_iface_combinations = 1; 5389 else 5390 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 5391 5392 rtwdev = hw->priv; 5393 rtwdev->hw = hw; 5394 rtwdev->dev = device; 5395 rtwdev->ops = ops; 5396 rtwdev->chip = chip; 5397 rtwdev->fw.req.firmware = firmware; 5398 rtwdev->fw.fw_format = fw_format; 5399 rtwdev->support_mlo = support_mlo; 5400 5401 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n", 5402 no_chanctx ? "without" : "with"); 5403 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n", 5404 support_mlo ? "with" : "without"); 5405 5406 return rtwdev; 5407 5408 err: 5409 kfree(ops); 5410 release_firmware(firmware); 5411 return NULL; 5412 } 5413 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 5414 5415 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 5416 { 5417 kfree(rtwdev->ops); 5418 kfree(rtwdev->rfe_data); 5419 release_firmware(rtwdev->fw.req.firmware); 5420 ieee80211_free_hw(rtwdev->hw); 5421 } 5422 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 5423 5424 MODULE_AUTHOR("Realtek Corporation"); 5425 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 5426 MODULE_LICENSE("Dual BSD/GPL"); 5427