1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 22 static bool rtw89_disable_ps_mode; 23 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 24 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 25 26 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 27 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 28 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 29 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 30 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 32 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 33 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 34 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 35 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 36 37 static struct ieee80211_channel rtw89_channels_2ghz[] = { 38 RTW89_DEF_CHAN_2G(2412, 1), 39 RTW89_DEF_CHAN_2G(2417, 2), 40 RTW89_DEF_CHAN_2G(2422, 3), 41 RTW89_DEF_CHAN_2G(2427, 4), 42 RTW89_DEF_CHAN_2G(2432, 5), 43 RTW89_DEF_CHAN_2G(2437, 6), 44 RTW89_DEF_CHAN_2G(2442, 7), 45 RTW89_DEF_CHAN_2G(2447, 8), 46 RTW89_DEF_CHAN_2G(2452, 9), 47 RTW89_DEF_CHAN_2G(2457, 10), 48 RTW89_DEF_CHAN_2G(2462, 11), 49 RTW89_DEF_CHAN_2G(2467, 12), 50 RTW89_DEF_CHAN_2G(2472, 13), 51 RTW89_DEF_CHAN_2G(2484, 14), 52 }; 53 54 static struct ieee80211_channel rtw89_channels_5ghz[] = { 55 RTW89_DEF_CHAN_5G(5180, 36), 56 RTW89_DEF_CHAN_5G(5200, 40), 57 RTW89_DEF_CHAN_5G(5220, 44), 58 RTW89_DEF_CHAN_5G(5240, 48), 59 RTW89_DEF_CHAN_5G(5260, 52), 60 RTW89_DEF_CHAN_5G(5280, 56), 61 RTW89_DEF_CHAN_5G(5300, 60), 62 RTW89_DEF_CHAN_5G(5320, 64), 63 RTW89_DEF_CHAN_5G(5500, 100), 64 RTW89_DEF_CHAN_5G(5520, 104), 65 RTW89_DEF_CHAN_5G(5540, 108), 66 RTW89_DEF_CHAN_5G(5560, 112), 67 RTW89_DEF_CHAN_5G(5580, 116), 68 RTW89_DEF_CHAN_5G(5600, 120), 69 RTW89_DEF_CHAN_5G(5620, 124), 70 RTW89_DEF_CHAN_5G(5640, 128), 71 RTW89_DEF_CHAN_5G(5660, 132), 72 RTW89_DEF_CHAN_5G(5680, 136), 73 RTW89_DEF_CHAN_5G(5700, 140), 74 RTW89_DEF_CHAN_5G(5720, 144), 75 RTW89_DEF_CHAN_5G(5745, 149), 76 RTW89_DEF_CHAN_5G(5765, 153), 77 RTW89_DEF_CHAN_5G(5785, 157), 78 RTW89_DEF_CHAN_5G(5805, 161), 79 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 80 RTW89_DEF_CHAN_5G(5845, 169), 81 RTW89_DEF_CHAN_5G(5865, 173), 82 RTW89_DEF_CHAN_5G(5885, 177), 83 }; 84 85 static struct ieee80211_channel rtw89_channels_6ghz[] = { 86 RTW89_DEF_CHAN_6G(5955, 1), 87 RTW89_DEF_CHAN_6G(5975, 5), 88 RTW89_DEF_CHAN_6G(5995, 9), 89 RTW89_DEF_CHAN_6G(6015, 13), 90 RTW89_DEF_CHAN_6G(6035, 17), 91 RTW89_DEF_CHAN_6G(6055, 21), 92 RTW89_DEF_CHAN_6G(6075, 25), 93 RTW89_DEF_CHAN_6G(6095, 29), 94 RTW89_DEF_CHAN_6G(6115, 33), 95 RTW89_DEF_CHAN_6G(6135, 37), 96 RTW89_DEF_CHAN_6G(6155, 41), 97 RTW89_DEF_CHAN_6G(6175, 45), 98 RTW89_DEF_CHAN_6G(6195, 49), 99 RTW89_DEF_CHAN_6G(6215, 53), 100 RTW89_DEF_CHAN_6G(6235, 57), 101 RTW89_DEF_CHAN_6G(6255, 61), 102 RTW89_DEF_CHAN_6G(6275, 65), 103 RTW89_DEF_CHAN_6G(6295, 69), 104 RTW89_DEF_CHAN_6G(6315, 73), 105 RTW89_DEF_CHAN_6G(6335, 77), 106 RTW89_DEF_CHAN_6G(6355, 81), 107 RTW89_DEF_CHAN_6G(6375, 85), 108 RTW89_DEF_CHAN_6G(6395, 89), 109 RTW89_DEF_CHAN_6G(6415, 93), 110 RTW89_DEF_CHAN_6G(6435, 97), 111 RTW89_DEF_CHAN_6G(6455, 101), 112 RTW89_DEF_CHAN_6G(6475, 105), 113 RTW89_DEF_CHAN_6G(6495, 109), 114 RTW89_DEF_CHAN_6G(6515, 113), 115 RTW89_DEF_CHAN_6G(6535, 117), 116 RTW89_DEF_CHAN_6G(6555, 121), 117 RTW89_DEF_CHAN_6G(6575, 125), 118 RTW89_DEF_CHAN_6G(6595, 129), 119 RTW89_DEF_CHAN_6G(6615, 133), 120 RTW89_DEF_CHAN_6G(6635, 137), 121 RTW89_DEF_CHAN_6G(6655, 141), 122 RTW89_DEF_CHAN_6G(6675, 145), 123 RTW89_DEF_CHAN_6G(6695, 149), 124 RTW89_DEF_CHAN_6G(6715, 153), 125 RTW89_DEF_CHAN_6G(6735, 157), 126 RTW89_DEF_CHAN_6G(6755, 161), 127 RTW89_DEF_CHAN_6G(6775, 165), 128 RTW89_DEF_CHAN_6G(6795, 169), 129 RTW89_DEF_CHAN_6G(6815, 173), 130 RTW89_DEF_CHAN_6G(6835, 177), 131 RTW89_DEF_CHAN_6G(6855, 181), 132 RTW89_DEF_CHAN_6G(6875, 185), 133 RTW89_DEF_CHAN_6G(6895, 189), 134 RTW89_DEF_CHAN_6G(6915, 193), 135 RTW89_DEF_CHAN_6G(6935, 197), 136 RTW89_DEF_CHAN_6G(6955, 201), 137 RTW89_DEF_CHAN_6G(6975, 205), 138 RTW89_DEF_CHAN_6G(6995, 209), 139 RTW89_DEF_CHAN_6G(7015, 213), 140 RTW89_DEF_CHAN_6G(7035, 217), 141 RTW89_DEF_CHAN_6G(7055, 221), 142 RTW89_DEF_CHAN_6G(7075, 225), 143 RTW89_DEF_CHAN_6G(7095, 229), 144 RTW89_DEF_CHAN_6G(7115, 233), 145 }; 146 147 static struct ieee80211_rate rtw89_bitrates[] = { 148 { .bitrate = 10, .hw_value = 0x00, }, 149 { .bitrate = 20, .hw_value = 0x01, }, 150 { .bitrate = 55, .hw_value = 0x02, }, 151 { .bitrate = 110, .hw_value = 0x03, }, 152 { .bitrate = 60, .hw_value = 0x04, }, 153 { .bitrate = 90, .hw_value = 0x05, }, 154 { .bitrate = 120, .hw_value = 0x06, }, 155 { .bitrate = 180, .hw_value = 0x07, }, 156 { .bitrate = 240, .hw_value = 0x08, }, 157 { .bitrate = 360, .hw_value = 0x09, }, 158 { .bitrate = 480, .hw_value = 0x0a, }, 159 { .bitrate = 540, .hw_value = 0x0b, }, 160 }; 161 162 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 163 { 164 .max = 1, 165 .types = BIT(NL80211_IFTYPE_STATION), 166 }, 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 170 BIT(NL80211_IFTYPE_P2P_GO) | 171 BIT(NL80211_IFTYPE_AP), 172 }, 173 }; 174 175 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 176 { 177 .max = 1, 178 .types = BIT(NL80211_IFTYPE_STATION), 179 }, 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 183 BIT(NL80211_IFTYPE_P2P_GO), 184 }, 185 }; 186 187 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 188 { 189 .limits = rtw89_iface_limits, 190 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 191 .max_interfaces = 2, 192 .num_different_channels = 1, 193 }, 194 { 195 .limits = rtw89_iface_limits_mcc, 196 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 197 .max_interfaces = 2, 198 .num_different_channels = 2, 199 }, 200 }; 201 202 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 203 { 204 struct ieee80211_rate rate; 205 206 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 207 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 208 return false; 209 } 210 211 rate = rtw89_bitrates[rpt_rate]; 212 *bitrate = rate.bitrate; 213 214 return true; 215 } 216 217 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 218 .band = NL80211_BAND_2GHZ, 219 .channels = rtw89_channels_2ghz, 220 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 221 .bitrates = rtw89_bitrates, 222 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 223 .ht_cap = {0}, 224 .vht_cap = {0}, 225 }; 226 227 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 228 .band = NL80211_BAND_5GHZ, 229 .channels = rtw89_channels_5ghz, 230 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 231 232 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 233 .bitrates = rtw89_bitrates + 4, 234 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 235 .ht_cap = {0}, 236 .vht_cap = {0}, 237 }; 238 239 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 240 .band = NL80211_BAND_6GHZ, 241 .channels = rtw89_channels_6ghz, 242 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 243 244 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 245 .bitrates = rtw89_bitrates + 4, 246 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 247 }; 248 249 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 250 struct rtw89_traffic_stats *stats, 251 struct sk_buff *skb, bool tx) 252 { 253 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 254 255 if (!ieee80211_is_data(hdr->frame_control)) 256 return; 257 258 if (is_broadcast_ether_addr(hdr->addr1) || 259 is_multicast_ether_addr(hdr->addr1)) 260 return; 261 262 if (tx) { 263 stats->tx_cnt++; 264 stats->tx_unicast += skb->len; 265 } else { 266 stats->rx_cnt++; 267 stats->rx_unicast += skb->len; 268 } 269 } 270 271 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 272 { 273 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 274 NL80211_CHAN_NO_HT); 275 } 276 277 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 278 struct rtw89_chan *chan) 279 { 280 struct ieee80211_channel *channel = chandef->chan; 281 enum nl80211_chan_width width = chandef->width; 282 u32 primary_freq, center_freq; 283 u8 center_chan; 284 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 285 u32 offset; 286 u8 band; 287 288 center_chan = channel->hw_value; 289 primary_freq = channel->center_freq; 290 center_freq = chandef->center_freq1; 291 292 switch (width) { 293 case NL80211_CHAN_WIDTH_20_NOHT: 294 case NL80211_CHAN_WIDTH_20: 295 bandwidth = RTW89_CHANNEL_WIDTH_20; 296 break; 297 case NL80211_CHAN_WIDTH_40: 298 bandwidth = RTW89_CHANNEL_WIDTH_40; 299 if (primary_freq > center_freq) { 300 center_chan -= 2; 301 } else { 302 center_chan += 2; 303 } 304 break; 305 case NL80211_CHAN_WIDTH_80: 306 case NL80211_CHAN_WIDTH_160: 307 bandwidth = nl_to_rtw89_bandwidth(width); 308 if (primary_freq > center_freq) { 309 offset = (primary_freq - center_freq - 10) / 20; 310 center_chan -= 2 + offset * 4; 311 } else { 312 offset = (center_freq - primary_freq - 10) / 20; 313 center_chan += 2 + offset * 4; 314 } 315 break; 316 default: 317 center_chan = 0; 318 break; 319 } 320 321 switch (channel->band) { 322 default: 323 case NL80211_BAND_2GHZ: 324 band = RTW89_BAND_2G; 325 break; 326 case NL80211_BAND_5GHZ: 327 band = RTW89_BAND_5G; 328 break; 329 case NL80211_BAND_6GHZ: 330 band = RTW89_BAND_6G; 331 break; 332 } 333 334 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 335 } 336 337 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 338 { 339 struct rtw89_hal *hal = &rtwdev->hal; 340 const struct rtw89_chip_info *chip = rtwdev->chip; 341 const struct rtw89_chan *chan; 342 enum rtw89_sub_entity_idx sub_entity_idx; 343 enum rtw89_sub_entity_idx roc_idx; 344 enum rtw89_phy_idx phy_idx; 345 enum rtw89_entity_mode mode; 346 bool entity_active; 347 348 entity_active = rtw89_get_entity_state(rtwdev); 349 if (!entity_active) 350 return; 351 352 mode = rtw89_get_entity_mode(rtwdev); 353 switch (mode) { 354 case RTW89_ENTITY_MODE_SCC: 355 case RTW89_ENTITY_MODE_MCC: 356 sub_entity_idx = RTW89_SUB_ENTITY_0; 357 break; 358 case RTW89_ENTITY_MODE_MCC_PREPARE: 359 sub_entity_idx = RTW89_SUB_ENTITY_1; 360 break; 361 default: 362 WARN(1, "Invalid ent mode: %d\n", mode); 363 return; 364 } 365 366 roc_idx = atomic_read(&hal->roc_entity_idx); 367 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 368 sub_entity_idx = roc_idx; 369 370 phy_idx = RTW89_PHY_0; 371 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 372 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 373 } 374 375 void rtw89_set_channel(struct rtw89_dev *rtwdev) 376 { 377 struct rtw89_hal *hal = &rtwdev->hal; 378 const struct rtw89_chip_info *chip = rtwdev->chip; 379 const struct rtw89_chan_rcd *chan_rcd; 380 const struct rtw89_chan *chan; 381 enum rtw89_sub_entity_idx sub_entity_idx; 382 enum rtw89_sub_entity_idx roc_idx; 383 enum rtw89_mac_idx mac_idx; 384 enum rtw89_phy_idx phy_idx; 385 struct rtw89_channel_help_params bak; 386 enum rtw89_entity_mode mode; 387 bool entity_active; 388 389 entity_active = rtw89_get_entity_state(rtwdev); 390 391 mode = rtw89_entity_recalc(rtwdev); 392 switch (mode) { 393 case RTW89_ENTITY_MODE_SCC: 394 case RTW89_ENTITY_MODE_MCC: 395 sub_entity_idx = RTW89_SUB_ENTITY_0; 396 break; 397 case RTW89_ENTITY_MODE_MCC_PREPARE: 398 sub_entity_idx = RTW89_SUB_ENTITY_1; 399 break; 400 default: 401 WARN(1, "Invalid ent mode: %d\n", mode); 402 return; 403 } 404 405 roc_idx = atomic_read(&hal->roc_entity_idx); 406 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 407 sub_entity_idx = roc_idx; 408 409 mac_idx = RTW89_MAC_0; 410 phy_idx = RTW89_PHY_0; 411 412 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 413 chan_rcd = rtw89_chan_rcd_get(rtwdev, sub_entity_idx); 414 415 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 416 417 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 418 419 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 420 421 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 422 423 if (!entity_active || chan_rcd->band_changed) { 424 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 425 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 426 } 427 428 rtw89_set_entity_state(rtwdev, true); 429 } 430 431 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 432 struct rtw89_chan *chan) 433 { 434 const struct cfg80211_chan_def *chandef; 435 436 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx); 437 rtw89_get_channel_params(chandef, chan); 438 } 439 440 static enum rtw89_core_tx_type 441 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 442 struct sk_buff *skb) 443 { 444 struct ieee80211_hdr *hdr = (void *)skb->data; 445 __le16 fc = hdr->frame_control; 446 447 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 448 return RTW89_CORE_TX_TYPE_MGMT; 449 450 return RTW89_CORE_TX_TYPE_DATA; 451 } 452 453 static void 454 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 455 struct rtw89_core_tx_request *tx_req, 456 enum btc_pkt_type pkt_type) 457 { 458 struct ieee80211_sta *sta = tx_req->sta; 459 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 460 struct sk_buff *skb = tx_req->skb; 461 struct rtw89_sta *rtwsta; 462 u8 ampdu_num; 463 u8 tid; 464 465 if (pkt_type == PACKET_EAPOL) { 466 desc_info->bk = true; 467 return; 468 } 469 470 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 471 return; 472 473 if (!sta) { 474 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 475 return; 476 } 477 478 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 479 rtwsta = (struct rtw89_sta *)sta->drv_priv; 480 481 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 482 rtwsta->ampdu_params[tid].agg_num : 483 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 484 485 desc_info->agg_en = true; 486 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 487 desc_info->ampdu_num = ampdu_num; 488 } 489 490 static void 491 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 492 struct rtw89_core_tx_request *tx_req) 493 { 494 const struct rtw89_chip_info *chip = rtwdev->chip; 495 struct ieee80211_vif *vif = tx_req->vif; 496 struct ieee80211_sta *sta = tx_req->sta; 497 struct ieee80211_tx_info *info; 498 struct ieee80211_key_conf *key; 499 struct rtw89_vif *rtwvif; 500 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 501 struct rtw89_addr_cam_entry *addr_cam; 502 struct rtw89_sec_cam_entry *sec_cam; 503 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 504 struct sk_buff *skb = tx_req->skb; 505 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 506 u64 pn64; 507 508 if (!vif) { 509 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 510 return; 511 } 512 513 rtwvif = (struct rtw89_vif *)vif->drv_priv; 514 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 515 516 info = IEEE80211_SKB_CB(skb); 517 key = info->control.hw_key; 518 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 519 if (!sec_cam) { 520 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 521 return; 522 } 523 524 switch (key->cipher) { 525 case WLAN_CIPHER_SUITE_WEP40: 526 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 527 break; 528 case WLAN_CIPHER_SUITE_WEP104: 529 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 530 break; 531 case WLAN_CIPHER_SUITE_TKIP: 532 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 533 break; 534 case WLAN_CIPHER_SUITE_CCMP: 535 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 536 break; 537 case WLAN_CIPHER_SUITE_CCMP_256: 538 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 539 break; 540 case WLAN_CIPHER_SUITE_GCMP: 541 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 542 break; 543 case WLAN_CIPHER_SUITE_GCMP_256: 544 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 545 break; 546 default: 547 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 548 return; 549 } 550 551 desc_info->sec_en = true; 552 desc_info->sec_keyid = key->keyidx; 553 desc_info->sec_type = sec_type; 554 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 555 556 if (!chip->hw_sec_hdr) 557 return; 558 559 pn64 = atomic64_inc_return(&key->tx_pn); 560 desc_info->sec_seq[0] = pn64; 561 desc_info->sec_seq[1] = pn64 >> 8; 562 desc_info->sec_seq[2] = pn64 >> 16; 563 desc_info->sec_seq[3] = pn64 >> 24; 564 desc_info->sec_seq[4] = pn64 >> 32; 565 desc_info->sec_seq[5] = pn64 >> 40; 566 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 567 } 568 569 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 570 struct rtw89_core_tx_request *tx_req, 571 const struct rtw89_chan *chan) 572 { 573 struct sk_buff *skb = tx_req->skb; 574 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 575 struct ieee80211_vif *vif = tx_info->control.vif; 576 u16 lowest_rate; 577 578 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 579 (vif && vif->p2p)) 580 lowest_rate = RTW89_HW_RATE_OFDM6; 581 else if (chan->band_type == RTW89_BAND_2G) 582 lowest_rate = RTW89_HW_RATE_CCK1; 583 else 584 lowest_rate = RTW89_HW_RATE_OFDM6; 585 586 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 587 return lowest_rate; 588 589 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 590 } 591 592 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 593 struct rtw89_core_tx_request *tx_req) 594 { 595 struct ieee80211_vif *vif = tx_req->vif; 596 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 597 struct ieee80211_sta *sta = tx_req->sta; 598 struct rtw89_sta *rtwsta; 599 600 if (!sta) 601 return rtwvif->mac_id; 602 603 rtwsta = (struct rtw89_sta *)sta->drv_priv; 604 return rtwsta->mac_id; 605 } 606 607 static void 608 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 609 struct rtw89_core_tx_request *tx_req) 610 { 611 struct ieee80211_vif *vif = tx_req->vif; 612 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 613 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 614 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 615 rtwvif->sub_entity_idx); 616 u8 qsel, ch_dma; 617 618 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 619 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 620 621 desc_info->qsel = qsel; 622 desc_info->ch_dma = ch_dma; 623 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 624 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 625 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 626 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 627 628 /* fixed data rate for mgmt frames */ 629 desc_info->en_wd_info = true; 630 desc_info->use_rate = true; 631 desc_info->dis_data_fb = true; 632 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 633 634 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 635 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 636 desc_info->data_rate, chan->channel, chan->band_type, 637 chan->band_width); 638 } 639 640 static void 641 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 642 struct rtw89_core_tx_request *tx_req) 643 { 644 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 645 646 desc_info->is_bmc = false; 647 desc_info->wd_page = false; 648 desc_info->ch_dma = RTW89_DMA_H2C; 649 } 650 651 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 652 const struct rtw89_chan *chan) 653 { 654 static const u8 rtw89_bandwidth_to_om[] = { 655 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 656 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 657 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 658 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 659 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 660 }; 661 const struct rtw89_chip_info *chip = rtwdev->chip; 662 struct rtw89_hal *hal = &rtwdev->hal; 663 u8 om_bandwidth; 664 665 if (!chip->dis_2g_40m_ul_ofdma || 666 chan->band_type != RTW89_BAND_2G || 667 chan->band_width != RTW89_CHANNEL_WIDTH_40) 668 return; 669 670 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 671 rtw89_bandwidth_to_om[chan->band_width] : 0; 672 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 673 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 674 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 675 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 676 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 677 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 678 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 679 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 680 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 681 } 682 683 static bool 684 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 685 struct rtw89_core_tx_request *tx_req, 686 enum btc_pkt_type pkt_type) 687 { 688 struct ieee80211_sta *sta = tx_req->sta; 689 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 690 struct sk_buff *skb = tx_req->skb; 691 struct ieee80211_hdr *hdr = (void *)skb->data; 692 __le16 fc = hdr->frame_control; 693 694 /* AP IOT issue with EAPoL, ARP and DHCP */ 695 if (pkt_type < PACKET_MAX) 696 return false; 697 698 if (!sta || !sta->deflink.he_cap.has_he) 699 return false; 700 701 if (!ieee80211_is_data_qos(fc)) 702 return false; 703 704 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 705 return false; 706 707 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 708 return false; 709 710 return true; 711 } 712 713 static void 714 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 715 struct rtw89_core_tx_request *tx_req) 716 { 717 struct ieee80211_sta *sta = tx_req->sta; 718 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 719 struct sk_buff *skb = tx_req->skb; 720 struct ieee80211_hdr *hdr = (void *)skb->data; 721 __le16 fc = hdr->frame_control; 722 void *data; 723 __le32 *htc; 724 u8 *qc; 725 int hdr_len; 726 727 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 728 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 729 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 730 731 hdr = data; 732 htc = data + hdr_len; 733 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 734 *htc = rtwsta->htc_template ? rtwsta->htc_template : 735 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 736 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 737 738 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 739 qc[0] |= IEEE80211_QOS_CTL_EOSP; 740 } 741 742 static void 743 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 744 struct rtw89_core_tx_request *tx_req, 745 enum btc_pkt_type pkt_type) 746 { 747 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 748 struct ieee80211_vif *vif = tx_req->vif; 749 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 750 751 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 752 goto desc_bk; 753 754 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 755 756 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 757 desc_info->a_ctrl_bsr = true; 758 759 desc_bk: 760 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 761 return; 762 763 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 764 desc_info->bk = true; 765 } 766 767 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 768 struct rtw89_core_tx_request *tx_req) 769 { 770 struct ieee80211_vif *vif = tx_req->vif; 771 struct ieee80211_sta *sta = tx_req->sta; 772 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 773 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 774 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx; 775 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 776 u16 lowest_rate; 777 778 if (rate_pattern->enable) 779 return rate_pattern->rate; 780 781 if (vif->p2p) 782 lowest_rate = RTW89_HW_RATE_OFDM6; 783 else if (chan->band_type == RTW89_BAND_2G) 784 lowest_rate = RTW89_HW_RATE_CCK1; 785 else 786 lowest_rate = RTW89_HW_RATE_OFDM6; 787 788 if (!sta || !sta->deflink.supp_rates[chan->band_type]) 789 return lowest_rate; 790 791 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate; 792 } 793 794 static void 795 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 796 struct rtw89_core_tx_request *tx_req) 797 { 798 struct ieee80211_vif *vif = tx_req->vif; 799 struct ieee80211_sta *sta = tx_req->sta; 800 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 801 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 802 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 803 struct sk_buff *skb = tx_req->skb; 804 u8 tid, tid_indicate; 805 u8 qsel, ch_dma; 806 807 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 808 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 809 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 810 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 811 812 desc_info->ch_dma = ch_dma; 813 desc_info->tid_indicate = tid_indicate; 814 desc_info->qsel = qsel; 815 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 816 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 817 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 818 819 /* enable wd_info for AMPDU */ 820 desc_info->en_wd_info = true; 821 822 if (IEEE80211_SKB_CB(skb)->control.hw_key) 823 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 824 825 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 826 } 827 828 static enum btc_pkt_type 829 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 830 struct rtw89_core_tx_request *tx_req) 831 { 832 struct sk_buff *skb = tx_req->skb; 833 struct udphdr *udphdr; 834 835 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 836 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 837 return PACKET_EAPOL; 838 } 839 840 if (skb->protocol == htons(ETH_P_ARP)) { 841 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 842 return PACKET_ARP; 843 } 844 845 if (skb->protocol == htons(ETH_P_IP) && 846 ip_hdr(skb)->protocol == IPPROTO_UDP) { 847 udphdr = udp_hdr(skb); 848 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 849 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 850 skb->len > 282) { 851 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 852 return PACKET_DHCP; 853 } 854 } 855 856 if (skb->protocol == htons(ETH_P_IP) && 857 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 858 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 859 return PACKET_ICMP; 860 } 861 862 return PACKET_MAX; 863 } 864 865 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 866 struct rtw89_tx_desc_info *desc_info, 867 struct sk_buff *skb) 868 { 869 struct ieee80211_hdr *hdr = (void *)skb->data; 870 __le16 fc = hdr->frame_control; 871 872 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 873 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 874 } 875 876 static void 877 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 878 struct rtw89_core_tx_request *tx_req) 879 { 880 const struct rtw89_chip_info *chip = rtwdev->chip; 881 882 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 883 return; 884 885 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 886 return; 887 888 if (chip->chip_id != RTL8852C && 889 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 890 return; 891 892 rtw89_mac_notify_wake(rtwdev); 893 } 894 895 static void 896 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 897 struct rtw89_core_tx_request *tx_req) 898 { 899 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 900 struct sk_buff *skb = tx_req->skb; 901 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 902 struct ieee80211_hdr *hdr = (void *)skb->data; 903 enum rtw89_core_tx_type tx_type; 904 enum btc_pkt_type pkt_type; 905 bool is_bmc; 906 u16 seq; 907 908 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 909 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 910 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 911 tx_req->tx_type = tx_type; 912 } 913 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 914 is_multicast_ether_addr(hdr->addr1)); 915 916 desc_info->seq = seq; 917 desc_info->pkt_size = skb->len; 918 desc_info->is_bmc = is_bmc; 919 desc_info->wd_page = true; 920 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 921 922 switch (tx_req->tx_type) { 923 case RTW89_CORE_TX_TYPE_MGMT: 924 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 925 break; 926 case RTW89_CORE_TX_TYPE_DATA: 927 rtw89_core_tx_update_data_info(rtwdev, tx_req); 928 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 929 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 930 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 931 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 932 break; 933 case RTW89_CORE_TX_TYPE_FWCMD: 934 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 935 break; 936 } 937 } 938 939 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 940 { 941 u8 ch_dma; 942 943 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 944 945 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 946 } 947 948 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 949 int qsel, unsigned int timeout) 950 { 951 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 952 struct rtw89_tx_wait_info *wait; 953 unsigned long time_left; 954 int ret = 0; 955 956 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 957 if (!wait) { 958 rtw89_core_tx_kick_off(rtwdev, qsel); 959 return 0; 960 } 961 962 init_completion(&wait->completion); 963 rcu_assign_pointer(skb_data->wait, wait); 964 965 rtw89_core_tx_kick_off(rtwdev, qsel); 966 time_left = wait_for_completion_timeout(&wait->completion, 967 msecs_to_jiffies(timeout)); 968 if (time_left == 0) 969 ret = -ETIMEDOUT; 970 else if (!wait->tx_done) 971 ret = -EAGAIN; 972 973 rcu_assign_pointer(skb_data->wait, NULL); 974 kfree_rcu(wait, rcu_head); 975 976 return ret; 977 } 978 979 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 980 struct sk_buff *skb, bool fwdl) 981 { 982 struct rtw89_core_tx_request tx_req = {0}; 983 u32 cnt; 984 int ret; 985 986 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 987 rtw89_debug(rtwdev, RTW89_DBG_FW, 988 "ignore h2c due to power is off with firmware state=%d\n", 989 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 990 dev_kfree_skb(skb); 991 return 0; 992 } 993 994 tx_req.skb = skb; 995 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 996 if (fwdl) 997 tx_req.desc_info.fw_dl = true; 998 999 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1000 1001 if (!fwdl) 1002 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1003 1004 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1005 if (cnt == 0) { 1006 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1007 return -ENOSPC; 1008 } 1009 1010 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1011 if (ret) { 1012 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1013 return ret; 1014 } 1015 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1016 1017 return 0; 1018 } 1019 1020 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1021 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1022 { 1023 struct rtw89_core_tx_request tx_req = {0}; 1024 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1025 int ret; 1026 1027 tx_req.skb = skb; 1028 tx_req.sta = sta; 1029 tx_req.vif = vif; 1030 1031 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1032 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1033 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1034 rtw89_core_tx_wake(rtwdev, &tx_req); 1035 1036 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1037 if (ret) { 1038 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1039 return ret; 1040 } 1041 1042 if (qsel) 1043 *qsel = tx_req.desc_info.qsel; 1044 1045 return 0; 1046 } 1047 1048 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1049 { 1050 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1051 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1052 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1053 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1054 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1055 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1056 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1057 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1058 1059 return cpu_to_le32(dword); 1060 } 1061 1062 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1063 { 1064 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1065 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1066 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1067 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1068 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1069 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1070 1071 return cpu_to_le32(dword); 1072 } 1073 1074 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1075 { 1076 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1077 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1078 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1079 1080 return cpu_to_le32(dword); 1081 } 1082 1083 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1084 { 1085 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1086 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1087 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1088 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1089 1090 return cpu_to_le32(dword); 1091 } 1092 1093 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1094 { 1095 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1096 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1097 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1098 1099 return cpu_to_le32(dword); 1100 } 1101 1102 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1103 { 1104 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1105 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1106 1107 return cpu_to_le32(dword); 1108 } 1109 1110 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1111 { 1112 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1113 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1114 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1115 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1116 1117 return cpu_to_le32(dword); 1118 } 1119 1120 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1121 { 1122 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1123 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1124 1125 return cpu_to_le32(dword); 1126 } 1127 1128 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1129 { 1130 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1131 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1132 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1133 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1134 1135 return cpu_to_le32(dword); 1136 } 1137 1138 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1139 { 1140 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1141 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1142 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1143 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1144 1145 return cpu_to_le32(dword); 1146 } 1147 1148 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1149 { 1150 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1151 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1152 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1153 desc_info->data_retry_lowest_rate); 1154 1155 return cpu_to_le32(dword); 1156 } 1157 1158 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1159 { 1160 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1161 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1162 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1163 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1164 1165 return cpu_to_le32(dword); 1166 } 1167 1168 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1169 { 1170 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1171 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1172 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1173 1174 return cpu_to_le32(dword); 1175 } 1176 1177 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1178 { 1179 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, 1) | 1180 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1181 1182 return cpu_to_le32(dword); 1183 } 1184 1185 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1186 struct rtw89_tx_desc_info *desc_info, 1187 void *txdesc) 1188 { 1189 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1190 struct rtw89_txwd_info *txwd_info; 1191 1192 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1193 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1194 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1195 1196 if (!desc_info->en_wd_info) 1197 return; 1198 1199 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1200 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1201 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1202 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1203 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1204 1205 } 1206 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1207 1208 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1209 struct rtw89_tx_desc_info *desc_info, 1210 void *txdesc) 1211 { 1212 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1213 struct rtw89_txwd_info *txwd_info; 1214 1215 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1216 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1217 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1218 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1219 if (desc_info->sec_en) { 1220 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1221 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1222 } 1223 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1224 1225 if (!desc_info->en_wd_info) 1226 return; 1227 1228 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1229 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1230 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1231 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1232 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1233 } 1234 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1235 1236 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1237 { 1238 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1239 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1240 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1241 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1242 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1243 1244 return cpu_to_le32(dword); 1245 } 1246 1247 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1248 { 1249 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1250 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1251 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1252 1253 return cpu_to_le32(dword); 1254 } 1255 1256 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1257 { 1258 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1259 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1260 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1261 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1262 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1263 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1264 1265 return cpu_to_le32(dword); 1266 } 1267 1268 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1269 { 1270 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq); 1271 1272 return cpu_to_le32(dword); 1273 } 1274 1275 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1276 { 1277 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1278 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1279 1280 return cpu_to_le32(dword); 1281 } 1282 1283 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1284 { 1285 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1286 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1287 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1288 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1289 1290 return cpu_to_le32(dword); 1291 } 1292 1293 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1294 { 1295 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1296 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1297 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1298 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1299 1300 return cpu_to_le32(dword); 1301 } 1302 1303 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1304 { 1305 u32 dword = FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1306 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1307 1308 return cpu_to_le32(dword); 1309 } 1310 1311 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1312 { 1313 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1314 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1315 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1316 desc_info->data_retry_lowest_rate); 1317 1318 return cpu_to_le32(dword); 1319 } 1320 1321 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1322 { 1323 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1324 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1325 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1326 1327 return cpu_to_le32(dword); 1328 } 1329 1330 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1331 { 1332 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, 1) | 1333 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1334 1335 return cpu_to_le32(dword); 1336 } 1337 1338 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1339 struct rtw89_tx_desc_info *desc_info, 1340 void *txdesc) 1341 { 1342 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1343 struct rtw89_txwd_info_v2 *txwd_info; 1344 1345 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1346 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1347 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1348 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1349 if (desc_info->sec_en) { 1350 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1351 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1352 } 1353 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1354 1355 if (!desc_info->en_wd_info) 1356 return; 1357 1358 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1359 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1360 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1361 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1362 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1363 } 1364 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1365 1366 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1367 { 1368 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1369 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1370 RTW89_CORE_RX_TYPE_FWDL : 1371 RTW89_CORE_RX_TYPE_H2C); 1372 1373 return cpu_to_le32(dword); 1374 } 1375 1376 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1377 struct rtw89_tx_desc_info *desc_info, 1378 void *txdesc) 1379 { 1380 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1381 1382 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1383 } 1384 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1385 1386 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1387 { 1388 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1389 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1390 RTW89_CORE_RX_TYPE_FWDL : 1391 RTW89_CORE_RX_TYPE_H2C); 1392 1393 return cpu_to_le32(dword); 1394 } 1395 1396 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1397 struct rtw89_tx_desc_info *desc_info, 1398 void *txdesc) 1399 { 1400 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1401 1402 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1403 } 1404 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1405 1406 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1407 struct sk_buff *skb, 1408 struct rtw89_rx_phy_ppdu *phy_ppdu) 1409 { 1410 const struct rtw89_chip_info *chip = rtwdev->chip; 1411 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1412 const struct rtw89_rxinfo_user *user; 1413 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1414 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1415 bool rx_cnt_valid = false; 1416 bool invalid = false; 1417 u8 plcp_size = 0; 1418 u8 *phy_sts; 1419 u8 usr_num; 1420 int i; 1421 1422 if (chip_gen == RTW89_CHIP_BE) { 1423 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1424 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1425 } 1426 1427 if (invalid) 1428 return -EINVAL; 1429 1430 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1431 if (chip_gen == RTW89_CHIP_BE) { 1432 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1433 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1434 } else { 1435 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1436 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1437 } 1438 if (usr_num > chip->ppdu_max_usr) { 1439 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1440 usr_num); 1441 return -EINVAL; 1442 } 1443 1444 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set by hardware, 1445 * so update mac_id by rxinfo_user[].mac_id. 1446 */ 1447 for (i = 0; i < usr_num && chip_gen == RTW89_CHIP_BE; i++) { 1448 user = &rxinfo->user[i]; 1449 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1450 continue; 1451 1452 phy_ppdu->mac_id = 1453 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1454 break; 1455 } 1456 1457 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1458 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1459 /* 8-byte alignment */ 1460 if (usr_num & BIT(0)) 1461 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1462 if (rx_cnt_valid) 1463 phy_sts += rx_cnt_size; 1464 phy_sts += plcp_size; 1465 1466 if (phy_sts > skb->data + skb->len) 1467 return -EINVAL; 1468 1469 phy_ppdu->buf = phy_sts; 1470 phy_ppdu->len = skb->data + skb->len - phy_sts; 1471 1472 return 0; 1473 } 1474 1475 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1476 struct ieee80211_sta *sta) 1477 { 1478 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1479 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1480 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1481 struct rtw89_hal *hal = &rtwdev->hal; 1482 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1483 u8 ant_pos = U8_MAX; 1484 u8 evm_pos = 0; 1485 int i; 1486 1487 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1488 return; 1489 1490 if (hal->ant_diversity && hal->antenna_rx) { 1491 ant_pos = __ffs(hal->antenna_rx); 1492 evm_pos = ant_pos; 1493 } 1494 1495 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1496 1497 if (ant_pos < ant_num) { 1498 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]); 1499 } else { 1500 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1501 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1502 } 1503 1504 if (phy_ppdu->ofdm.has) { 1505 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr); 1506 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min); 1507 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max); 1508 } 1509 } 1510 1511 #define VAR_LEN 0xff 1512 #define VAR_LEN_UNIT 8 1513 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1514 const struct rtw89_phy_sts_iehdr *iehdr) 1515 { 1516 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1517 [RTW89_CHIP_AX] = { 1518 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1519 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1520 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1521 }, 1522 [RTW89_CHIP_BE] = { 1523 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1524 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1525 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1526 }, 1527 }; 1528 const u8 *physts_ie_len_tab; 1529 u16 ie_len; 1530 u8 ie; 1531 1532 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1533 1534 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1535 if (physts_ie_len_tab[ie] != VAR_LEN) 1536 ie_len = physts_ie_len_tab[ie]; 1537 else 1538 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1539 1540 return ie_len; 1541 } 1542 1543 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1544 const struct rtw89_phy_sts_iehdr *iehdr, 1545 struct rtw89_rx_phy_ppdu *phy_ppdu) 1546 { 1547 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr; 1548 s16 cfo; 1549 u32 t; 1550 1551 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1552 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1553 return; 1554 1555 if (!phy_ppdu->to_self) 1556 return; 1557 1558 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1559 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1560 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1561 phy_ppdu->ofdm.has = true; 1562 1563 /* sign conversion for S(12,2) */ 1564 if (rtwdev->chip->cfo_src_fd) { 1565 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1566 cfo = sign_extend32(t, 11); 1567 } else { 1568 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1569 cfo = sign_extend32(t, 11); 1570 } 1571 1572 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1573 } 1574 1575 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1576 const struct rtw89_phy_sts_iehdr *iehdr, 1577 struct rtw89_rx_phy_ppdu *phy_ppdu) 1578 { 1579 u8 ie; 1580 1581 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1582 1583 switch (ie) { 1584 case RTW89_PHYSTS_IE01_CMN_OFDM: 1585 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1586 break; 1587 default: 1588 break; 1589 } 1590 1591 return 0; 1592 } 1593 1594 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1595 { 1596 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1597 u8 *rssi = phy_ppdu->rssi; 1598 1599 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1600 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1601 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1602 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1603 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1604 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1605 } 1606 1607 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1608 struct rtw89_rx_phy_ppdu *phy_ppdu) 1609 { 1610 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1611 u32 len_from_header; 1612 bool physts_valid; 1613 1614 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1615 if (!physts_valid) 1616 return -EINVAL; 1617 1618 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1619 1620 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1621 len_from_header += PHY_STS_HDR_LEN; 1622 1623 if (len_from_header != phy_ppdu->len) { 1624 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1625 return -EINVAL; 1626 } 1627 rtw89_core_update_phy_ppdu(phy_ppdu); 1628 1629 return 0; 1630 } 1631 1632 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1633 struct rtw89_rx_phy_ppdu *phy_ppdu) 1634 { 1635 u16 ie_len; 1636 void *pos, *end; 1637 1638 /* mark invalid reports and bypass them */ 1639 if (phy_ppdu->ie < RTW89_CCK_PKT) 1640 return -EINVAL; 1641 1642 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1643 end = phy_ppdu->buf + phy_ppdu->len; 1644 while (pos < end) { 1645 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1646 1647 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1648 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1649 pos += ie_len; 1650 if (pos > end || ie_len == 0) { 1651 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1652 "phy status parse failed\n"); 1653 return -EINVAL; 1654 } 1655 } 1656 1657 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1658 1659 return 0; 1660 } 1661 1662 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1663 struct rtw89_rx_phy_ppdu *phy_ppdu) 1664 { 1665 int ret; 1666 1667 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1668 if (ret) 1669 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1670 else 1671 phy_ppdu->valid = true; 1672 1673 ieee80211_iterate_stations_atomic(rtwdev->hw, 1674 rtw89_core_rx_process_phy_ppdu_iter, 1675 phy_ppdu); 1676 } 1677 1678 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 1679 u8 desc_info_gi, 1680 bool rx_status, bool eht) 1681 { 1682 switch (desc_info_gi) { 1683 case RTW89_GILTF_SGI_4XHE08: 1684 case RTW89_GILTF_2XHE08: 1685 case RTW89_GILTF_1XHE08: 1686 return eht ? NL80211_RATE_INFO_EHT_GI_0_8 : 1687 NL80211_RATE_INFO_HE_GI_0_8; 1688 case RTW89_GILTF_2XHE16: 1689 case RTW89_GILTF_1XHE16: 1690 return eht ? NL80211_RATE_INFO_EHT_GI_1_6 : 1691 NL80211_RATE_INFO_HE_GI_1_6; 1692 case RTW89_GILTF_LGI_4XHE32: 1693 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1694 NL80211_RATE_INFO_HE_GI_3_2; 1695 default: 1696 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1697 if (rx_status) 1698 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1699 NL80211_RATE_INFO_HE_GI_3_2; 1700 return U8_MAX; 1701 } 1702 } 1703 1704 static 1705 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 1706 bool eht) 1707 { 1708 if (eht) 1709 return status->eht.gi == gi_ltf; 1710 1711 return status->he_gi == gi_ltf; 1712 } 1713 1714 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1715 struct rtw89_rx_desc_info *desc_info, 1716 struct ieee80211_rx_status *status) 1717 { 1718 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1719 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1720 bool eht = false; 1721 u16 data_rate; 1722 bool ret; 1723 1724 data_rate = desc_info->data_rate; 1725 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1726 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1727 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1728 /* rate_idx is still hardware value here */ 1729 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1730 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1731 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 1732 data_rate_mode == DATA_RATE_MODE_HE || 1733 data_rate_mode == DATA_RATE_MODE_EHT) { 1734 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1735 } else { 1736 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1737 } 1738 1739 eht = data_rate_mode == DATA_RATE_MODE_EHT; 1740 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1741 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 1742 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1743 status->rate_idx == rate_idx && 1744 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 1745 status->bw == bw; 1746 1747 return ret; 1748 } 1749 1750 struct rtw89_vif_rx_stats_iter_data { 1751 struct rtw89_dev *rtwdev; 1752 struct rtw89_rx_phy_ppdu *phy_ppdu; 1753 struct rtw89_rx_desc_info *desc_info; 1754 struct sk_buff *skb; 1755 const u8 *bssid; 1756 }; 1757 1758 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1759 struct ieee80211_vif *vif, 1760 struct sk_buff *skb) 1761 { 1762 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1763 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1764 u8 *pos, *end, type, tf_bw; 1765 u16 aid, tf_rua; 1766 1767 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1768 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1769 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1770 return; 1771 1772 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1773 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 1774 return; 1775 1776 end = (u8 *)tf + skb->len; 1777 pos = tf->variable; 1778 1779 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1780 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1781 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 1782 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 1783 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1784 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 1785 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1786 tf_rua, tf_bw); 1787 1788 if (aid == RTW89_TF_PAD) 1789 break; 1790 1791 if (aid == vif->cfg.aid) { 1792 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 1793 1794 rtwvif->stats.rx_tf_acc++; 1795 rtwdev->stats.rx_tf_acc++; 1796 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 1797 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 1798 rtwvif->pwr_diff_en = true; 1799 break; 1800 } 1801 1802 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1803 } 1804 } 1805 1806 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work) 1807 { 1808 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1809 cancel_6ghz_probe_work); 1810 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1811 struct rtw89_pktofld_info *info; 1812 1813 mutex_lock(&rtwdev->mutex); 1814 1815 if (!rtwdev->scanning) 1816 goto out; 1817 1818 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1819 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 1820 continue; 1821 1822 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1823 1824 /* Don't delete/free info from pkt_list at this moment. Let it 1825 * be deleted/freed in rtw89_release_pkt_list() after scanning, 1826 * since if during scanning, pkt_list is accessed in bottom half. 1827 */ 1828 } 1829 1830 out: 1831 mutex_unlock(&rtwdev->mutex); 1832 } 1833 1834 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1835 struct sk_buff *skb) 1836 { 1837 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1838 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1839 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1840 struct rtw89_pktofld_info *info; 1841 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1842 bool queue_work = false; 1843 1844 if (rx_status->band != NL80211_BAND_6GHZ) 1845 return; 1846 1847 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1848 1849 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1850 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1851 info->cancel = true; 1852 queue_work = true; 1853 continue; 1854 } 1855 1856 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1857 continue; 1858 1859 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 1860 info->cancel = true; 1861 queue_work = true; 1862 } 1863 } 1864 1865 if (queue_work) 1866 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work); 1867 } 1868 1869 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1870 struct ieee80211_vif *vif) 1871 { 1872 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1873 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1874 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1875 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1876 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1877 struct sk_buff *skb = iter_data->skb; 1878 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1879 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 1880 const u8 *bssid = iter_data->bssid; 1881 1882 if (rtwdev->scanning && 1883 (ieee80211_is_beacon(hdr->frame_control) || 1884 ieee80211_is_probe_resp(hdr->frame_control))) 1885 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1886 1887 if (!vif->bss_conf.bssid) 1888 return; 1889 1890 if (ieee80211_is_trigger(hdr->frame_control)) { 1891 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1892 return; 1893 } 1894 1895 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1896 return; 1897 1898 if (ieee80211_is_beacon(hdr->frame_control)) { 1899 if (vif->type == NL80211_IFTYPE_STATION) 1900 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 1901 pkt_stat->beacon_nr++; 1902 } 1903 1904 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1905 return; 1906 1907 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1908 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1909 1910 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1911 } 1912 1913 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1914 struct rtw89_rx_phy_ppdu *phy_ppdu, 1915 struct rtw89_rx_desc_info *desc_info, 1916 struct sk_buff *skb) 1917 { 1918 struct rtw89_vif_rx_stats_iter_data iter_data; 1919 1920 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1921 1922 iter_data.rtwdev = rtwdev; 1923 iter_data.phy_ppdu = phy_ppdu; 1924 iter_data.desc_info = desc_info; 1925 iter_data.skb = skb; 1926 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1927 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1928 } 1929 1930 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1931 struct ieee80211_rx_status *status) 1932 { 1933 const struct rtw89_chan_rcd *rcd = 1934 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1935 u16 chan = rcd->prev_primary_channel; 1936 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 1937 1938 if (status->band != NL80211_BAND_2GHZ && 1939 status->encoding == RX_ENC_LEGACY && 1940 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1941 status->freq = ieee80211_channel_to_frequency(chan, band); 1942 status->band = band; 1943 } 1944 } 1945 1946 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1947 { 1948 if (rx_status->band == NL80211_BAND_2GHZ || 1949 rx_status->encoding != RX_ENC_LEGACY) 1950 return; 1951 1952 /* Some control frames' freq(ACKs in this case) are reported wrong due 1953 * to FW notify timing, set to lowest rate to prevent overflow. 1954 */ 1955 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1956 rx_status->rate_idx = 0; 1957 return; 1958 } 1959 1960 /* No 4 CCK rates for non-2G */ 1961 rx_status->rate_idx -= 4; 1962 } 1963 1964 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 1965 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 1966 [RATE_INFO_BW_5] = U8_MAX, 1967 [RATE_INFO_BW_10] = U8_MAX, 1968 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 1969 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 1970 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 1971 [RATE_INFO_BW_HE_RU] = U8_MAX, 1972 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 1973 [RATE_INFO_BW_EHT_RU] = U8_MAX, 1974 }; 1975 1976 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 1977 struct sk_buff *skb, 1978 struct ieee80211_rx_status *rx_status) 1979 { 1980 struct ieee80211_radiotap_eht_usig *usig; 1981 struct ieee80211_radiotap_eht *eht; 1982 struct ieee80211_radiotap_tlv *tlv; 1983 int eht_len = struct_size(eht, user_info, 1); 1984 int usig_len = sizeof(*usig); 1985 int len; 1986 u8 bw; 1987 1988 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 1989 sizeof(*tlv) + ALIGN(usig_len, 4); 1990 1991 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 1992 skb_reset_mac_header(skb); 1993 1994 /* EHT */ 1995 tlv = skb_push(skb, len); 1996 memset(tlv, 0, len); 1997 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 1998 tlv->len = cpu_to_le16(eht_len); 1999 2000 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2001 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2002 eht->data[0] = 2003 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2004 2005 eht->user_info[0] = 2006 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2007 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O); 2008 eht->user_info[0] |= 2009 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2010 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2011 2012 /* U-SIG */ 2013 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2014 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2015 tlv->len = cpu_to_le16(usig_len); 2016 2017 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2018 return; 2019 2020 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2021 if (bw == U8_MAX) 2022 return; 2023 2024 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2025 usig->common = 2026 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2027 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2028 } 2029 2030 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2031 struct sk_buff *skb, 2032 struct ieee80211_rx_status *rx_status) 2033 { 2034 static const struct ieee80211_radiotap_he known_he = { 2035 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2036 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2037 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2038 }; 2039 struct ieee80211_radiotap_he *he; 2040 2041 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2042 return; 2043 2044 if (rx_status->encoding == RX_ENC_HE) { 2045 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2046 he = skb_push(skb, sizeof(*he)); 2047 *he = known_he; 2048 } else if (rx_status->encoding == RX_ENC_EHT) { 2049 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2050 } 2051 } 2052 2053 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2054 struct rtw89_rx_phy_ppdu *phy_ppdu, 2055 struct rtw89_rx_desc_info *desc_info, 2056 struct sk_buff *skb_ppdu, 2057 struct ieee80211_rx_status *rx_status) 2058 { 2059 struct napi_struct *napi = &rtwdev->napi; 2060 2061 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2062 if (unlikely(!napi_is_scheduled(napi))) 2063 napi = NULL; 2064 2065 rtw89_core_hw_to_sband_rate(rx_status); 2066 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2067 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2068 /* In low power mode, it does RX in thread context. */ 2069 local_bh_disable(); 2070 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2071 local_bh_enable(); 2072 rtwdev->napi_budget_countdown--; 2073 } 2074 2075 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2076 struct rtw89_rx_phy_ppdu *phy_ppdu, 2077 struct rtw89_rx_desc_info *desc_info, 2078 struct sk_buff *skb) 2079 { 2080 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2081 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2082 struct sk_buff *skb_ppdu = NULL, *tmp; 2083 struct ieee80211_rx_status *rx_status; 2084 2085 if (curr > RTW89_MAX_PPDU_CNT) 2086 return; 2087 2088 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2089 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2090 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2091 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2092 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2093 rtw89_correct_cck_chan(rtwdev, rx_status); 2094 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2095 } 2096 } 2097 2098 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2099 struct rtw89_rx_desc_info *desc_info, 2100 struct sk_buff *skb) 2101 { 2102 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2103 .len = skb->len, 2104 .to_self = desc_info->addr1_match, 2105 .rate = desc_info->data_rate, 2106 .mac_id = desc_info->mac_id}; 2107 int ret; 2108 2109 if (desc_info->mac_info_valid) { 2110 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2111 if (ret) 2112 goto out; 2113 } 2114 2115 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2116 if (ret) 2117 goto out; 2118 2119 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2120 2121 out: 2122 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2123 dev_kfree_skb_any(skb); 2124 } 2125 2126 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2127 struct rtw89_rx_desc_info *desc_info, 2128 struct sk_buff *skb) 2129 { 2130 switch (desc_info->pkt_type) { 2131 case RTW89_CORE_RX_TYPE_C2H: 2132 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2133 break; 2134 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2135 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2136 break; 2137 default: 2138 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2139 desc_info->pkt_type); 2140 dev_kfree_skb_any(skb); 2141 break; 2142 } 2143 } 2144 2145 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2146 struct rtw89_rx_desc_info *desc_info, 2147 u8 *data, u32 data_offset) 2148 { 2149 const struct rtw89_chip_info *chip = rtwdev->chip; 2150 struct rtw89_rxdesc_short *rxd_s; 2151 struct rtw89_rxdesc_long *rxd_l; 2152 u8 shift_len, drv_info_len; 2153 2154 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2155 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2156 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2157 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2158 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2159 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2160 if (chip->chip_id == RTL8852C) 2161 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2162 else 2163 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2164 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2165 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2166 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2167 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2168 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2169 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2170 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2171 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2172 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2173 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2174 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2175 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2176 2177 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2178 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2179 desc_info->offset = data_offset + shift_len + drv_info_len; 2180 if (desc_info->long_rxdesc) 2181 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2182 else 2183 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2184 desc_info->ready = true; 2185 2186 if (!desc_info->long_rxdesc) 2187 return; 2188 2189 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2190 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2191 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2192 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2193 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2194 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2195 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2196 } 2197 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2198 2199 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2200 struct rtw89_rx_desc_info *desc_info, 2201 u8 *data, u32 data_offset) 2202 { 2203 struct rtw89_rxdesc_short_v2 *rxd_s; 2204 struct rtw89_rxdesc_long_v2 *rxd_l; 2205 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2206 2207 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2208 2209 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2210 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2211 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2212 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2213 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2214 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2215 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2216 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2217 desc_info->mac_info_valid = true; 2218 2219 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2220 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2221 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2222 2223 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2224 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2225 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2226 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2227 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2228 2229 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2230 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2231 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2232 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2233 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2234 2235 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2236 2237 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2238 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2239 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2240 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2241 desc_info->offset = data_offset + shift_len + drv_info_len + 2242 phy_rtp_len + hdr_cnv_len; 2243 2244 if (desc_info->long_rxdesc) 2245 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2246 else 2247 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2248 desc_info->ready = true; 2249 2250 if (!desc_info->long_rxdesc) 2251 return; 2252 2253 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2254 2255 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2256 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2257 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2258 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2259 2260 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2261 } 2262 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2263 2264 struct rtw89_core_iter_rx_status { 2265 struct rtw89_dev *rtwdev; 2266 struct ieee80211_rx_status *rx_status; 2267 struct rtw89_rx_desc_info *desc_info; 2268 u8 mac_id; 2269 }; 2270 2271 static 2272 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2273 { 2274 struct rtw89_core_iter_rx_status *iter_data = 2275 (struct rtw89_core_iter_rx_status *)data; 2276 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2277 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2278 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2279 u8 mac_id = iter_data->mac_id; 2280 2281 if (mac_id != rtwsta->mac_id) 2282 return; 2283 2284 rtwsta->rx_status = *rx_status; 2285 rtwsta->rx_hw_rate = desc_info->data_rate; 2286 } 2287 2288 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2289 struct rtw89_rx_desc_info *desc_info, 2290 struct ieee80211_rx_status *rx_status) 2291 { 2292 struct rtw89_core_iter_rx_status iter_data; 2293 2294 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2295 return; 2296 2297 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2298 return; 2299 2300 iter_data.rtwdev = rtwdev; 2301 iter_data.rx_status = rx_status; 2302 iter_data.desc_info = desc_info; 2303 iter_data.mac_id = desc_info->mac_id; 2304 ieee80211_iterate_stations_atomic(rtwdev->hw, 2305 rtw89_core_stats_sta_rx_status_iter, 2306 &iter_data); 2307 } 2308 2309 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2310 struct rtw89_rx_desc_info *desc_info, 2311 struct ieee80211_rx_status *rx_status) 2312 { 2313 const struct cfg80211_chan_def *chandef = 2314 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 2315 u16 data_rate; 2316 u8 data_rate_mode; 2317 bool eht = false; 2318 u8 gi; 2319 2320 /* currently using single PHY */ 2321 rx_status->freq = chandef->chan->center_freq; 2322 rx_status->band = chandef->chan->band; 2323 2324 if (rtwdev->scanning && 2325 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2326 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2327 u8 chan = cur->primary_channel; 2328 u8 band = cur->band_type; 2329 enum nl80211_band nl_band; 2330 2331 nl_band = rtw89_hw_to_nl80211_band(band); 2332 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2333 rx_status->band = nl_band; 2334 } 2335 2336 if (desc_info->icv_err || desc_info->crc32_err) 2337 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2338 2339 if (desc_info->hw_dec && 2340 !(desc_info->sw_dec || desc_info->icv_err)) 2341 rx_status->flag |= RX_FLAG_DECRYPTED; 2342 2343 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2344 2345 data_rate = desc_info->data_rate; 2346 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2347 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2348 rx_status->encoding = RX_ENC_LEGACY; 2349 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2350 /* convert rate_idx after we get the correct band */ 2351 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2352 rx_status->encoding = RX_ENC_HT; 2353 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2354 if (desc_info->gi_ltf) 2355 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2356 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2357 rx_status->encoding = RX_ENC_VHT; 2358 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2359 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2360 if (desc_info->gi_ltf) 2361 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2362 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2363 rx_status->encoding = RX_ENC_HE; 2364 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2365 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2366 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2367 rx_status->encoding = RX_ENC_EHT; 2368 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2369 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2370 eht = true; 2371 } else { 2372 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2373 } 2374 2375 /* he_gi is used to match ppdu, so we always fill it. */ 2376 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2377 if (eht) 2378 rx_status->eht.gi = gi; 2379 else 2380 rx_status->he_gi = gi; 2381 rx_status->flag |= RX_FLAG_MACTIME_START; 2382 rx_status->mactime = desc_info->free_run_cnt; 2383 2384 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2385 } 2386 2387 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2388 { 2389 const struct rtw89_chip_info *chip = rtwdev->chip; 2390 2391 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2392 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2393 return RTW89_PS_MODE_NONE; 2394 2395 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2396 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2397 return RTW89_PS_MODE_PWR_GATED; 2398 2399 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2400 return RTW89_PS_MODE_CLK_GATED; 2401 2402 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2403 return RTW89_PS_MODE_RFOFF; 2404 2405 return RTW89_PS_MODE_NONE; 2406 } 2407 2408 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2409 struct rtw89_rx_desc_info *desc_info) 2410 { 2411 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2412 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2413 struct ieee80211_rx_status *rx_status; 2414 struct sk_buff *skb_ppdu, *tmp; 2415 2416 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2417 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2418 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2419 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2420 } 2421 } 2422 2423 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2424 struct rtw89_rx_desc_info *desc_info, 2425 struct sk_buff *skb) 2426 { 2427 struct ieee80211_rx_status *rx_status; 2428 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2429 u8 ppdu_cnt = desc_info->ppdu_cnt; 2430 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2431 2432 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2433 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2434 return; 2435 } 2436 2437 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2438 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2439 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2440 } 2441 2442 rx_status = IEEE80211_SKB_RXCB(skb); 2443 memset(rx_status, 0, sizeof(*rx_status)); 2444 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2445 if (desc_info->long_rxdesc && 2446 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2447 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2448 else 2449 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2450 } 2451 EXPORT_SYMBOL(rtw89_core_rx); 2452 2453 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2454 { 2455 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2456 return; 2457 2458 napi_enable(&rtwdev->napi); 2459 } 2460 EXPORT_SYMBOL(rtw89_core_napi_start); 2461 2462 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2463 { 2464 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2465 return; 2466 2467 napi_synchronize(&rtwdev->napi); 2468 napi_disable(&rtwdev->napi); 2469 } 2470 EXPORT_SYMBOL(rtw89_core_napi_stop); 2471 2472 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2473 { 2474 init_dummy_netdev(&rtwdev->netdev); 2475 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 2476 rtwdev->hci.ops->napi_poll); 2477 } 2478 EXPORT_SYMBOL(rtw89_core_napi_init); 2479 2480 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2481 { 2482 rtw89_core_napi_stop(rtwdev); 2483 netif_napi_del(&rtwdev->napi); 2484 } 2485 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2486 2487 static void rtw89_core_ba_work(struct work_struct *work) 2488 { 2489 struct rtw89_dev *rtwdev = 2490 container_of(work, struct rtw89_dev, ba_work); 2491 struct rtw89_txq *rtwtxq, *tmp; 2492 int ret; 2493 2494 spin_lock_bh(&rtwdev->ba_lock); 2495 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2496 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2497 struct ieee80211_sta *sta = txq->sta; 2498 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2499 u8 tid = txq->tid; 2500 2501 if (!sta) { 2502 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2503 goto skip_ba_work; 2504 } 2505 2506 if (rtwsta->disassoc) { 2507 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2508 "cannot start BA with disassoc sta\n"); 2509 goto skip_ba_work; 2510 } 2511 2512 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2513 if (ret) { 2514 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2515 "failed to setup BA session for %pM:%2d: %d\n", 2516 sta->addr, tid, ret); 2517 if (ret == -EINVAL) 2518 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2519 } 2520 skip_ba_work: 2521 list_del_init(&rtwtxq->list); 2522 } 2523 spin_unlock_bh(&rtwdev->ba_lock); 2524 } 2525 2526 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2527 struct ieee80211_sta *sta) 2528 { 2529 struct rtw89_txq *rtwtxq, *tmp; 2530 2531 spin_lock_bh(&rtwdev->ba_lock); 2532 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2533 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2534 2535 if (sta == txq->sta) 2536 list_del_init(&rtwtxq->list); 2537 } 2538 spin_unlock_bh(&rtwdev->ba_lock); 2539 } 2540 2541 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2542 struct ieee80211_sta *sta) 2543 { 2544 struct rtw89_txq *rtwtxq, *tmp; 2545 2546 spin_lock_bh(&rtwdev->ba_lock); 2547 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2548 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2549 2550 if (sta == txq->sta) { 2551 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2552 list_del_init(&rtwtxq->list); 2553 } 2554 } 2555 spin_unlock_bh(&rtwdev->ba_lock); 2556 } 2557 2558 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2559 struct ieee80211_sta *sta) 2560 { 2561 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2562 struct sk_buff *skb, *tmp; 2563 2564 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2565 skb_unlink(skb, &rtwsta->roc_queue); 2566 dev_kfree_skb_any(skb); 2567 } 2568 } 2569 2570 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2571 struct rtw89_txq *rtwtxq) 2572 { 2573 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2574 struct ieee80211_sta *sta = txq->sta; 2575 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2576 2577 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2578 return; 2579 2580 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2581 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2582 return; 2583 2584 spin_lock_bh(&rtwdev->ba_lock); 2585 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2586 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2587 spin_unlock_bh(&rtwdev->ba_lock); 2588 2589 ieee80211_stop_tx_ba_session(sta, txq->tid); 2590 cancel_delayed_work(&rtwdev->forbid_ba_work); 2591 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2592 RTW89_FORBID_BA_TIMER); 2593 } 2594 2595 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2596 struct rtw89_txq *rtwtxq, 2597 struct sk_buff *skb) 2598 { 2599 struct ieee80211_hw *hw = rtwdev->hw; 2600 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2601 struct ieee80211_sta *sta = txq->sta; 2602 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2603 2604 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2605 return; 2606 2607 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2608 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2609 return; 2610 } 2611 2612 if (unlikely(!sta)) 2613 return; 2614 2615 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2616 return; 2617 2618 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2619 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2620 return; 2621 } 2622 2623 spin_lock_bh(&rtwdev->ba_lock); 2624 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2625 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2626 ieee80211_queue_work(hw, &rtwdev->ba_work); 2627 } 2628 spin_unlock_bh(&rtwdev->ba_lock); 2629 } 2630 2631 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2632 struct rtw89_txq *rtwtxq, 2633 unsigned long frame_cnt, 2634 unsigned long byte_cnt) 2635 { 2636 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2637 struct ieee80211_vif *vif = txq->vif; 2638 struct ieee80211_sta *sta = txq->sta; 2639 struct sk_buff *skb; 2640 unsigned long i; 2641 int ret; 2642 2643 rcu_read_lock(); 2644 for (i = 0; i < frame_cnt; i++) { 2645 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2646 if (!skb) { 2647 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2648 goto out; 2649 } 2650 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2651 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2652 if (ret) { 2653 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2654 ieee80211_free_txskb(rtwdev->hw, skb); 2655 break; 2656 } 2657 } 2658 out: 2659 rcu_read_unlock(); 2660 } 2661 2662 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2663 { 2664 u8 qsel, ch_dma; 2665 2666 qsel = rtw89_core_get_qsel(rtwdev, tid); 2667 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2668 2669 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2670 } 2671 2672 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2673 struct ieee80211_txq *txq, 2674 unsigned long *frame_cnt, 2675 bool *sched_txq, bool *reinvoke) 2676 { 2677 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2678 struct ieee80211_sta *sta = txq->sta; 2679 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2680 2681 if (!sta || rtwsta->max_agg_wait <= 0) 2682 return false; 2683 2684 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2685 return false; 2686 2687 if (*frame_cnt > 1) { 2688 *frame_cnt -= 1; 2689 *sched_txq = true; 2690 *reinvoke = true; 2691 rtwtxq->wait_cnt = 1; 2692 return false; 2693 } 2694 2695 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2696 *reinvoke = true; 2697 rtwtxq->wait_cnt++; 2698 return true; 2699 } 2700 2701 rtwtxq->wait_cnt = 0; 2702 return false; 2703 } 2704 2705 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2706 { 2707 struct ieee80211_hw *hw = rtwdev->hw; 2708 struct ieee80211_txq *txq; 2709 struct rtw89_vif *rtwvif; 2710 struct rtw89_txq *rtwtxq; 2711 unsigned long frame_cnt; 2712 unsigned long byte_cnt; 2713 u32 tx_resource; 2714 bool sched_txq; 2715 2716 ieee80211_txq_schedule_start(hw, ac); 2717 while ((txq = ieee80211_next_txq(hw, ac))) { 2718 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2719 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv; 2720 2721 if (rtwvif->offchan) { 2722 ieee80211_return_txq(hw, txq, true); 2723 continue; 2724 } 2725 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2726 sched_txq = false; 2727 2728 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2729 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2730 ieee80211_return_txq(hw, txq, true); 2731 continue; 2732 } 2733 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2734 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2735 ieee80211_return_txq(hw, txq, sched_txq); 2736 if (frame_cnt != 0) 2737 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2738 2739 /* bound of tx_resource could get stuck due to burst traffic */ 2740 if (frame_cnt == tx_resource) 2741 *reinvoke = true; 2742 } 2743 ieee80211_txq_schedule_end(hw, ac); 2744 } 2745 2746 static void rtw89_ips_work(struct work_struct *work) 2747 { 2748 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2749 ips_work); 2750 mutex_lock(&rtwdev->mutex); 2751 rtw89_enter_ips_by_hwflags(rtwdev); 2752 mutex_unlock(&rtwdev->mutex); 2753 } 2754 2755 static void rtw89_core_txq_work(struct work_struct *w) 2756 { 2757 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2758 bool reinvoke = false; 2759 u8 ac; 2760 2761 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2762 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2763 2764 if (reinvoke) { 2765 /* reinvoke to process the last frame */ 2766 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2767 } 2768 } 2769 2770 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2771 { 2772 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2773 txq_reinvoke_work.work); 2774 2775 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2776 } 2777 2778 static void rtw89_forbid_ba_work(struct work_struct *w) 2779 { 2780 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2781 forbid_ba_work.work); 2782 struct rtw89_txq *rtwtxq, *tmp; 2783 2784 spin_lock_bh(&rtwdev->ba_lock); 2785 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2786 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2787 list_del_init(&rtwtxq->list); 2788 } 2789 spin_unlock_bh(&rtwdev->ba_lock); 2790 } 2791 2792 static void rtw89_core_sta_pending_tx_iter(void *data, 2793 struct ieee80211_sta *sta) 2794 { 2795 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2796 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif; 2797 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2798 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2799 struct sk_buff *skb, *tmp; 2800 int qsel, ret; 2801 2802 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx) 2803 return; 2804 2805 if (skb_queue_len(&rtwsta->roc_queue) == 0) 2806 return; 2807 2808 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2809 skb_unlink(skb, &rtwsta->roc_queue); 2810 2811 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2812 if (ret) { 2813 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 2814 dev_kfree_skb_any(skb); 2815 } else { 2816 rtw89_core_tx_kick_off(rtwdev, qsel); 2817 } 2818 } 2819 } 2820 2821 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 2822 struct rtw89_vif *rtwvif) 2823 { 2824 ieee80211_iterate_stations_atomic(rtwdev->hw, 2825 rtw89_core_sta_pending_tx_iter, 2826 rtwvif); 2827 } 2828 2829 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 2830 struct rtw89_vif *rtwvif, bool qos, bool ps) 2831 { 2832 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2833 struct ieee80211_sta *sta; 2834 struct ieee80211_hdr *hdr; 2835 struct sk_buff *skb; 2836 int ret, qsel; 2837 2838 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 2839 return 0; 2840 2841 rcu_read_lock(); 2842 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 2843 if (!sta) { 2844 ret = -EINVAL; 2845 goto out; 2846 } 2847 2848 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos); 2849 if (!skb) { 2850 ret = -ENOMEM; 2851 goto out; 2852 } 2853 2854 hdr = (struct ieee80211_hdr *)skb->data; 2855 if (ps) 2856 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2857 2858 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2859 if (ret) { 2860 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 2861 dev_kfree_skb_any(skb); 2862 goto out; 2863 } 2864 2865 rcu_read_unlock(); 2866 2867 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 2868 RTW89_ROC_TX_TIMEOUT); 2869 out: 2870 rcu_read_unlock(); 2871 2872 return ret; 2873 } 2874 2875 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2876 { 2877 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2878 struct ieee80211_hw *hw = rtwdev->hw; 2879 struct rtw89_roc *roc = &rtwvif->roc; 2880 struct cfg80211_chan_def roc_chan; 2881 struct rtw89_vif *tmp; 2882 int ret; 2883 2884 lockdep_assert_held(&rtwdev->mutex); 2885 2886 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 2887 msecs_to_jiffies(rtwvif->roc.duration)); 2888 2889 rtw89_leave_ips_by_hwflags(rtwdev); 2890 rtw89_leave_lps(rtwdev); 2891 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC); 2892 2893 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true); 2894 if (ret) 2895 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2896 "roc send null-1 failed: %d\n", ret); 2897 2898 rtw89_for_each_rtwvif(rtwdev, tmp) 2899 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2900 tmp->offchan = true; 2901 2902 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 2903 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan); 2904 rtw89_set_channel(rtwdev); 2905 rtw89_write32_clr(rtwdev, 2906 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2907 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 2908 2909 ieee80211_ready_on_channel(hw); 2910 } 2911 2912 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2913 { 2914 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2915 struct ieee80211_hw *hw = rtwdev->hw; 2916 struct rtw89_roc *roc = &rtwvif->roc; 2917 struct rtw89_vif *tmp; 2918 int ret; 2919 2920 lockdep_assert_held(&rtwdev->mutex); 2921 2922 ieee80211_remain_on_channel_expired(hw); 2923 2924 rtw89_leave_ips_by_hwflags(rtwdev); 2925 rtw89_leave_lps(rtwdev); 2926 2927 rtw89_write32_mask(rtwdev, 2928 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2929 B_AX_RX_FLTR_CFG_MASK, 2930 rtwdev->hal.rx_fltr); 2931 2932 roc->state = RTW89_ROC_IDLE; 2933 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL); 2934 rtw89_chanctx_proceed(rtwdev); 2935 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false); 2936 if (ret) 2937 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2938 "roc send null-0 failed: %d\n", ret); 2939 2940 rtw89_for_each_rtwvif(rtwdev, tmp) 2941 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2942 tmp->offchan = false; 2943 2944 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif); 2945 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2946 2947 if (hw->conf.flags & IEEE80211_CONF_IDLE) 2948 ieee80211_queue_delayed_work(hw, &roc->roc_work, 2949 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 2950 } 2951 2952 void rtw89_roc_work(struct work_struct *work) 2953 { 2954 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 2955 roc.roc_work.work); 2956 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2957 struct rtw89_roc *roc = &rtwvif->roc; 2958 2959 mutex_lock(&rtwdev->mutex); 2960 2961 switch (roc->state) { 2962 case RTW89_ROC_IDLE: 2963 rtw89_enter_ips_by_hwflags(rtwdev); 2964 break; 2965 case RTW89_ROC_MGMT: 2966 case RTW89_ROC_NORMAL: 2967 rtw89_roc_end(rtwdev, rtwvif); 2968 break; 2969 default: 2970 break; 2971 } 2972 2973 mutex_unlock(&rtwdev->mutex); 2974 } 2975 2976 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 2977 u32 throughput, u64 cnt) 2978 { 2979 if (cnt < 100) 2980 return RTW89_TFC_IDLE; 2981 if (throughput > 50) 2982 return RTW89_TFC_HIGH; 2983 if (throughput > 10) 2984 return RTW89_TFC_MID; 2985 if (throughput > 2) 2986 return RTW89_TFC_LOW; 2987 return RTW89_TFC_ULTRA_LOW; 2988 } 2989 2990 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 2991 struct rtw89_traffic_stats *stats) 2992 { 2993 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 2994 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 2995 2996 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 2997 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 2998 2999 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3000 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3001 3002 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3003 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3004 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3005 stats->tx_cnt); 3006 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3007 stats->rx_cnt); 3008 stats->tx_avg_len = stats->tx_cnt ? 3009 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3010 stats->rx_avg_len = stats->rx_cnt ? 3011 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3012 3013 stats->tx_unicast = 0; 3014 stats->rx_unicast = 0; 3015 stats->tx_cnt = 0; 3016 stats->rx_cnt = 0; 3017 stats->rx_tf_periodic = stats->rx_tf_acc; 3018 stats->rx_tf_acc = 0; 3019 3020 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3021 return true; 3022 3023 return false; 3024 } 3025 3026 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3027 { 3028 struct rtw89_vif *rtwvif; 3029 bool tfc_changed; 3030 3031 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3032 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3033 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3034 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif); 3035 } 3036 3037 return tfc_changed; 3038 } 3039 3040 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3041 { 3042 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 3043 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 3044 rtwvif->tdls_peer) 3045 return; 3046 3047 if (rtwvif->offchan) 3048 return; 3049 3050 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 3051 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 3052 rtw89_enter_lps(rtwdev, rtwvif, true); 3053 } 3054 3055 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3056 { 3057 struct rtw89_vif *rtwvif; 3058 3059 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3060 rtw89_vif_enter_lps(rtwdev, rtwvif); 3061 } 3062 3063 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3064 { 3065 enum rtw89_entity_mode mode; 3066 3067 mode = rtw89_get_entity_mode(rtwdev); 3068 if (mode == RTW89_ENTITY_MODE_MCC) 3069 return; 3070 3071 rtw89_chip_rfk_track(rtwdev); 3072 } 3073 3074 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3075 { 3076 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3077 3078 if (mode == RTW89_ENTITY_MODE_MCC) 3079 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3080 else 3081 rtw89_process_p2p_ps(rtwdev, vif); 3082 } 3083 3084 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3085 struct rtw89_traffic_stats *stats) 3086 { 3087 stats->tx_unicast = 0; 3088 stats->rx_unicast = 0; 3089 stats->tx_cnt = 0; 3090 stats->rx_cnt = 0; 3091 ewma_tp_init(&stats->tx_ewma_tp); 3092 ewma_tp_init(&stats->rx_ewma_tp); 3093 } 3094 3095 static void rtw89_track_work(struct work_struct *work) 3096 { 3097 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3098 track_work.work); 3099 bool tfc_changed; 3100 3101 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3102 return; 3103 3104 mutex_lock(&rtwdev->mutex); 3105 3106 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3107 goto out; 3108 3109 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3110 RTW89_TRACK_WORK_PERIOD); 3111 3112 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3113 if (rtwdev->scanning) 3114 goto out; 3115 3116 rtw89_leave_lps(rtwdev); 3117 3118 if (tfc_changed) { 3119 rtw89_hci_recalc_int_mit(rtwdev); 3120 rtw89_btc_ntfy_wl_sta(rtwdev); 3121 } 3122 rtw89_mac_bf_monitor_track(rtwdev); 3123 rtw89_phy_stat_track(rtwdev); 3124 rtw89_phy_env_monitor_track(rtwdev); 3125 rtw89_phy_dig(rtwdev); 3126 rtw89_core_rfk_track(rtwdev); 3127 rtw89_phy_ra_update(rtwdev); 3128 rtw89_phy_cfo_track(rtwdev); 3129 rtw89_phy_tx_path_div_track(rtwdev); 3130 rtw89_phy_antdiv_track(rtwdev); 3131 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3132 rtw89_tas_track(rtwdev); 3133 rtw89_chanctx_track(rtwdev); 3134 3135 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3136 rtw89_enter_lps_track(rtwdev); 3137 3138 out: 3139 mutex_unlock(&rtwdev->mutex); 3140 } 3141 3142 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3143 { 3144 unsigned long bit; 3145 3146 bit = find_first_zero_bit(addr, size); 3147 if (bit < size) 3148 set_bit(bit, addr); 3149 3150 return bit; 3151 } 3152 3153 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3154 { 3155 clear_bit(bit, addr); 3156 } 3157 3158 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3159 { 3160 bitmap_zero(addr, nbits); 3161 } 3162 3163 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3164 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3165 { 3166 const struct rtw89_chip_info *chip = rtwdev->chip; 3167 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3168 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3169 u8 idx; 3170 int i; 3171 3172 lockdep_assert_held(&rtwdev->mutex); 3173 3174 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3175 if (idx == chip->bacam_num) { 3176 /* allocate a static BA CAM to tid=0/5, so replace the existing 3177 * one if BA CAM is full. Hardware will process the original tid 3178 * automatically. 3179 */ 3180 if (tid != 0 && tid != 5) 3181 return -ENOSPC; 3182 3183 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3184 tmp = &cam_info->ba_cam_entry[i]; 3185 if (tmp->tid == 0 || tmp->tid == 5) 3186 continue; 3187 3188 idx = i; 3189 entry = tmp; 3190 list_del(&entry->list); 3191 break; 3192 } 3193 3194 if (!entry) 3195 return -ENOSPC; 3196 } else { 3197 entry = &cam_info->ba_cam_entry[idx]; 3198 } 3199 3200 entry->tid = tid; 3201 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 3202 3203 *cam_idx = idx; 3204 3205 return 0; 3206 } 3207 3208 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3209 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3210 { 3211 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3212 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3213 u8 idx; 3214 3215 lockdep_assert_held(&rtwdev->mutex); 3216 3217 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 3218 if (entry->tid != tid) 3219 continue; 3220 3221 idx = entry - cam_info->ba_cam_entry; 3222 list_del(&entry->list); 3223 3224 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3225 *cam_idx = idx; 3226 return 0; 3227 } 3228 3229 return -ENOENT; 3230 } 3231 3232 #define RTW89_TYPE_MAPPING(_type) \ 3233 case NL80211_IFTYPE_ ## _type: \ 3234 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3235 break 3236 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 3237 { 3238 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3239 3240 switch (vif->type) { 3241 case NL80211_IFTYPE_STATION: 3242 if (vif->p2p) 3243 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3244 else 3245 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 3246 break; 3247 case NL80211_IFTYPE_AP: 3248 if (vif->p2p) 3249 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3250 else 3251 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 3252 break; 3253 RTW89_TYPE_MAPPING(ADHOC); 3254 RTW89_TYPE_MAPPING(MONITOR); 3255 RTW89_TYPE_MAPPING(MESH_POINT); 3256 default: 3257 WARN_ON(1); 3258 break; 3259 } 3260 3261 switch (vif->type) { 3262 case NL80211_IFTYPE_AP: 3263 case NL80211_IFTYPE_MESH_POINT: 3264 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 3265 rtwvif->self_role = RTW89_SELF_ROLE_AP; 3266 break; 3267 case NL80211_IFTYPE_ADHOC: 3268 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 3269 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3270 break; 3271 case NL80211_IFTYPE_STATION: 3272 if (assoc) { 3273 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 3274 rtwvif->trigger = vif->bss_conf.he_support; 3275 } else { 3276 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 3277 rtwvif->trigger = false; 3278 } 3279 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3280 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3281 break; 3282 case NL80211_IFTYPE_MONITOR: 3283 break; 3284 default: 3285 WARN_ON(1); 3286 break; 3287 } 3288 } 3289 3290 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3291 struct ieee80211_vif *vif, 3292 struct ieee80211_sta *sta) 3293 { 3294 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3295 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3296 struct rtw89_hal *hal = &rtwdev->hal; 3297 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3298 int i; 3299 int ret; 3300 3301 rtwsta->rtwdev = rtwdev; 3302 rtwsta->rtwvif = rtwvif; 3303 rtwsta->prev_rssi = 0; 3304 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 3305 skb_queue_head_init(&rtwsta->roc_queue); 3306 3307 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 3308 rtw89_core_txq_init(rtwdev, sta->txq[i]); 3309 3310 ewma_rssi_init(&rtwsta->avg_rssi); 3311 ewma_snr_init(&rtwsta->avg_snr); 3312 for (i = 0; i < ant_num; i++) { 3313 ewma_rssi_init(&rtwsta->rssi[i]); 3314 ewma_evm_init(&rtwsta->evm_min[i]); 3315 ewma_evm_init(&rtwsta->evm_max[i]); 3316 } 3317 3318 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3319 /* for station mode, assign the mac_id from itself */ 3320 rtwsta->mac_id = rtwvif->mac_id; 3321 /* must do rtw89_reg_6ghz_power_recalc() before rfk channel */ 3322 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, true); 3323 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3324 BTC_ROLE_MSTS_STA_CONN_START); 3325 rtw89_chip_rfk_channel(rtwdev); 3326 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3327 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 3328 RTW89_MAX_MAC_ID_NUM); 3329 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 3330 return -ENOSPC; 3331 3332 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 3333 if (ret) { 3334 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3335 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3336 return ret; 3337 } 3338 3339 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3340 RTW89_ROLE_CREATE); 3341 if (ret) { 3342 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3343 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3344 return ret; 3345 } 3346 3347 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3348 } 3349 3350 return 0; 3351 } 3352 3353 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3354 struct ieee80211_vif *vif, 3355 struct ieee80211_sta *sta) 3356 { 3357 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3358 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3359 3360 if (vif->type == NL80211_IFTYPE_STATION) 3361 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false); 3362 3363 rtwdev->total_sta_assoc--; 3364 if (sta->tdls) 3365 rtwvif->tdls_peer--; 3366 rtwsta->disassoc = true; 3367 3368 return 0; 3369 } 3370 3371 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3372 struct ieee80211_vif *vif, 3373 struct ieee80211_sta *sta) 3374 { 3375 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3376 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3377 int ret; 3378 3379 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 3380 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 3381 rtw89_core_free_sta_pending_ba(rtwdev, sta); 3382 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 3383 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta); 3384 3385 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 3386 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 3387 if (sta->tdls) 3388 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 3389 3390 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3391 rtw89_vif_type_mapping(vif, false); 3392 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 3393 } 3394 3395 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3396 if (ret) { 3397 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3398 return ret; 3399 } 3400 3401 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 3402 if (ret) { 3403 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3404 return ret; 3405 } 3406 3407 /* update cam aid mac_id net_type */ 3408 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3409 if (ret) { 3410 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3411 return ret; 3412 } 3413 3414 return ret; 3415 } 3416 3417 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3418 struct ieee80211_vif *vif, 3419 struct ieee80211_sta *sta) 3420 { 3421 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3422 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3423 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 3424 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3425 rtwvif->sub_entity_idx); 3426 int ret; 3427 3428 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3429 if (sta->tdls) { 3430 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 3431 if (ret) { 3432 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3433 return ret; 3434 } 3435 } 3436 3437 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 3438 if (ret) { 3439 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3440 return ret; 3441 } 3442 } 3443 3444 ret = rtw89_fw_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3445 if (ret) { 3446 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3447 return ret; 3448 } 3449 3450 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 3451 if (ret) { 3452 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3453 return ret; 3454 } 3455 3456 /* update cam aid mac_id net_type */ 3457 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3458 if (ret) { 3459 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3460 return ret; 3461 } 3462 3463 rtwdev->total_sta_assoc++; 3464 if (sta->tdls) 3465 rtwvif->tdls_peer++; 3466 rtw89_phy_ra_assoc(rtwdev, sta); 3467 rtw89_mac_bf_assoc(rtwdev, vif, sta); 3468 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 3469 3470 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3471 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 3472 3473 if (bss_conf->he_support && 3474 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 3475 rtwsta->er_cap = true; 3476 3477 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3478 BTC_ROLE_MSTS_STA_CONN_END); 3479 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan); 3480 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 3481 3482 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 3483 if (ret) { 3484 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3485 return ret; 3486 } 3487 } 3488 3489 return ret; 3490 } 3491 3492 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3493 struct ieee80211_vif *vif, 3494 struct ieee80211_sta *sta) 3495 { 3496 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3497 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3498 int ret; 3499 3500 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3501 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, false); 3502 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3503 BTC_ROLE_MSTS_STA_DIS_CONN); 3504 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3505 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3506 3507 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3508 RTW89_ROLE_REMOVE); 3509 if (ret) { 3510 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3511 return ret; 3512 } 3513 3514 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3515 } 3516 3517 return 0; 3518 } 3519 3520 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3521 struct ieee80211_sta *sta, 3522 struct cfg80211_tid_cfg *tid_conf) 3523 { 3524 struct ieee80211_txq *txq; 3525 struct rtw89_txq *rtwtxq; 3526 u32 mask = tid_conf->mask; 3527 u8 tids = tid_conf->tids; 3528 int tids_nbit = BITS_PER_BYTE; 3529 int i; 3530 3531 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3532 if (!tids) 3533 break; 3534 3535 if (!(tids & BIT(0))) 3536 continue; 3537 3538 txq = sta->txq[i]; 3539 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3540 3541 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 3542 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 3543 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3544 } else { 3545 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 3546 ieee80211_stop_tx_ba_session(sta, txq->tid); 3547 spin_lock_bh(&rtwdev->ba_lock); 3548 list_del_init(&rtwtxq->list); 3549 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3550 spin_unlock_bh(&rtwdev->ba_lock); 3551 } 3552 } 3553 3554 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 3555 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 3556 sta->max_amsdu_subframes = 0; 3557 else 3558 sta->max_amsdu_subframes = 1; 3559 } 3560 } 3561 } 3562 3563 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3564 struct ieee80211_sta *sta, 3565 struct cfg80211_tid_config *tid_config) 3566 { 3567 int i; 3568 3569 for (i = 0; i < tid_config->n_tid_conf; i++) 3570 _rtw89_core_set_tid_config(rtwdev, sta, 3571 &tid_config->tid_conf[i]); 3572 } 3573 3574 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 3575 struct ieee80211_sta_ht_cap *ht_cap) 3576 { 3577 static const __le16 highest[RF_PATH_MAX] = { 3578 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 3579 }; 3580 struct rtw89_hal *hal = &rtwdev->hal; 3581 u8 nss = hal->rx_nss; 3582 int i; 3583 3584 ht_cap->ht_supported = true; 3585 ht_cap->cap = 0; 3586 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 3587 IEEE80211_HT_CAP_MAX_AMSDU | 3588 IEEE80211_HT_CAP_TX_STBC | 3589 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 3590 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 3591 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 3592 IEEE80211_HT_CAP_DSSSCCK40 | 3593 IEEE80211_HT_CAP_SGI_40; 3594 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 3595 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 3596 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 3597 for (i = 0; i < nss; i++) 3598 ht_cap->mcs.rx_mask[i] = 0xFF; 3599 ht_cap->mcs.rx_mask[4] = 0x01; 3600 ht_cap->mcs.rx_highest = highest[nss - 1]; 3601 } 3602 3603 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 3604 struct ieee80211_sta_vht_cap *vht_cap) 3605 { 3606 static const __le16 highest_bw80[RF_PATH_MAX] = { 3607 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 3608 }; 3609 static const __le16 highest_bw160[RF_PATH_MAX] = { 3610 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 3611 }; 3612 const struct rtw89_chip_info *chip = rtwdev->chip; 3613 const __le16 *highest = chip->support_bw160 ? highest_bw160 : highest_bw80; 3614 struct rtw89_hal *hal = &rtwdev->hal; 3615 u16 tx_mcs_map = 0, rx_mcs_map = 0; 3616 u8 sts_cap = 3; 3617 int i; 3618 3619 for (i = 0; i < 8; i++) { 3620 if (i < hal->tx_nss) 3621 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3622 else 3623 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3624 if (i < hal->rx_nss) 3625 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3626 else 3627 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3628 } 3629 3630 vht_cap->vht_supported = true; 3631 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 3632 IEEE80211_VHT_CAP_SHORT_GI_80 | 3633 IEEE80211_VHT_CAP_RXSTBC_1 | 3634 IEEE80211_VHT_CAP_HTC_VHT | 3635 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 3636 0; 3637 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 3638 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 3639 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 3640 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 3641 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 3642 if (chip->support_bw160) 3643 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 3644 IEEE80211_VHT_CAP_SHORT_GI_160; 3645 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 3646 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 3647 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 3648 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 3649 } 3650 3651 #define RTW89_SBAND_IFTYPES_NR 2 3652 3653 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 3654 enum nl80211_band band, 3655 struct ieee80211_supported_band *sband) 3656 { 3657 const struct rtw89_chip_info *chip = rtwdev->chip; 3658 struct rtw89_hal *hal = &rtwdev->hal; 3659 struct ieee80211_sband_iftype_data *iftype_data; 3660 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 3661 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 3662 u16 mcs_map = 0; 3663 int i; 3664 int nss = hal->rx_nss; 3665 int idx = 0; 3666 3667 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 3668 if (!iftype_data) 3669 return; 3670 3671 for (i = 0; i < 8; i++) { 3672 if (i < nss) 3673 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 3674 else 3675 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 3676 } 3677 3678 for (i = 0; i < NUM_NL80211_IFTYPES; i++) { 3679 struct ieee80211_sta_he_cap *he_cap; 3680 u8 *mac_cap_info; 3681 u8 *phy_cap_info; 3682 3683 switch (i) { 3684 case NL80211_IFTYPE_STATION: 3685 case NL80211_IFTYPE_AP: 3686 break; 3687 default: 3688 continue; 3689 } 3690 3691 if (idx >= RTW89_SBAND_IFTYPES_NR) { 3692 rtw89_warn(rtwdev, "run out of iftype_data\n"); 3693 break; 3694 } 3695 3696 iftype_data[idx].types_mask = BIT(i); 3697 he_cap = &iftype_data[idx].he_cap; 3698 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 3699 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 3700 3701 he_cap->has_he = true; 3702 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 3703 if (i == NL80211_IFTYPE_STATION) 3704 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 3705 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 3706 IEEE80211_HE_MAC_CAP2_BSR; 3707 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 3708 if (i == NL80211_IFTYPE_AP) 3709 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 3710 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 3711 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 3712 if (i == NL80211_IFTYPE_STATION) 3713 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 3714 if (band == NL80211_BAND_2GHZ) { 3715 phy_cap_info[0] = 3716 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 3717 } else { 3718 phy_cap_info[0] = 3719 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 3720 if (chip->support_bw160) 3721 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 3722 } 3723 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 3724 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 3725 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 3726 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 3727 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 3728 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 3729 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 3730 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 3731 if (i == NL80211_IFTYPE_STATION) 3732 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 3733 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 3734 if (i == NL80211_IFTYPE_AP) 3735 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 3736 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 3737 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 3738 if (chip->support_bw160) 3739 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 3740 phy_cap_info[5] = no_ng16 ? 0 : 3741 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 3742 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 3743 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 3744 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 3745 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 3746 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 3747 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 3748 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 3749 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 3750 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 3751 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 3752 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 3753 if (chip->support_bw160) 3754 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 3755 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 3756 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 3757 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 3758 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 3759 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 3760 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 3761 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 3762 if (i == NL80211_IFTYPE_STATION) 3763 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 3764 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 3765 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 3766 if (chip->support_bw160) { 3767 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 3768 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 3769 } 3770 3771 if (band == NL80211_BAND_6GHZ) { 3772 __le16 capa; 3773 3774 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 3775 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 3776 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 3777 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 3778 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 3779 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 3780 iftype_data[idx].he_6ghz_capa.capa = capa; 3781 } 3782 3783 idx++; 3784 } 3785 3786 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 3787 } 3788 3789 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 3790 { 3791 struct ieee80211_hw *hw = rtwdev->hw; 3792 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 3793 struct ieee80211_supported_band *sband_6ghz = NULL; 3794 u32 size = sizeof(struct ieee80211_supported_band); 3795 u8 support_bands = rtwdev->chip->support_bands; 3796 3797 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 3798 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 3799 if (!sband_2ghz) 3800 goto err; 3801 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 3802 rtw89_init_he_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 3803 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 3804 } 3805 3806 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 3807 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 3808 if (!sband_5ghz) 3809 goto err; 3810 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 3811 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 3812 rtw89_init_he_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 3813 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 3814 } 3815 3816 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 3817 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 3818 if (!sband_6ghz) 3819 goto err; 3820 rtw89_init_he_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 3821 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 3822 } 3823 3824 return 0; 3825 3826 err: 3827 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3828 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3829 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3830 if (sband_2ghz) 3831 kfree((__force void *)sband_2ghz->iftype_data); 3832 if (sband_5ghz) 3833 kfree((__force void *)sband_5ghz->iftype_data); 3834 if (sband_6ghz) 3835 kfree((__force void *)sband_6ghz->iftype_data); 3836 kfree(sband_2ghz); 3837 kfree(sband_5ghz); 3838 kfree(sband_6ghz); 3839 return -ENOMEM; 3840 } 3841 3842 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 3843 { 3844 struct ieee80211_hw *hw = rtwdev->hw; 3845 3846 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 3847 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 3848 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 3849 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 3850 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 3851 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 3852 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 3853 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 3854 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 3855 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3856 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3857 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3858 } 3859 3860 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 3861 { 3862 int i; 3863 3864 for (i = 0; i < RTW89_PHY_MAX; i++) 3865 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 3866 for (i = 0; i < RTW89_PHY_MAX; i++) 3867 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 3868 } 3869 3870 void rtw89_core_update_beacon_work(struct work_struct *work) 3871 { 3872 struct rtw89_dev *rtwdev; 3873 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3874 update_beacon_work); 3875 3876 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 3877 return; 3878 3879 rtwdev = rtwvif->rtwdev; 3880 mutex_lock(&rtwdev->mutex); 3881 rtw89_fw_h2c_update_beacon(rtwdev, rtwvif); 3882 mutex_unlock(&rtwdev->mutex); 3883 } 3884 3885 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 3886 { 3887 struct completion *cmpl = &wait->completion; 3888 unsigned long timeout; 3889 unsigned int cur; 3890 3891 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 3892 if (cur != RTW89_WAIT_COND_IDLE) 3893 return -EBUSY; 3894 3895 timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 3896 if (timeout == 0) { 3897 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 3898 return -ETIMEDOUT; 3899 } 3900 3901 if (wait->data.err) 3902 return -EFAULT; 3903 3904 return 0; 3905 } 3906 3907 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 3908 const struct rtw89_completion_data *data) 3909 { 3910 unsigned int cur; 3911 3912 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 3913 if (cur != cond) 3914 return; 3915 3916 wait->data = *data; 3917 complete(&wait->completion); 3918 } 3919 3920 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 3921 { 3922 u16 bt_req_len; 3923 3924 switch (event) { 3925 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 3926 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 3927 rtw89_debug(rtwdev, RTW89_DBG_BTC, 3928 "coex updates BT req len to %d TU\n", bt_req_len); 3929 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 3930 break; 3931 default: 3932 if (event < NUM_OF_RTW89_BTC_HMSG) 3933 rtw89_debug(rtwdev, RTW89_DBG_BTC, 3934 "unhandled BTC HMSG event: %d\n", event); 3935 else 3936 rtw89_warn(rtwdev, 3937 "unrecognized BTC HMSG event: %d\n", event); 3938 break; 3939 } 3940 } 3941 3942 int rtw89_core_start(struct rtw89_dev *rtwdev) 3943 { 3944 int ret; 3945 3946 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 3947 ret = rtw89_mac_init(rtwdev); 3948 if (ret) { 3949 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 3950 return ret; 3951 } 3952 3953 rtw89_btc_ntfy_poweron(rtwdev); 3954 3955 /* efuse process */ 3956 3957 /* pre-config BB/RF, BB reset/RFC reset */ 3958 ret = rtw89_chip_disable_bb_rf(rtwdev); 3959 if (ret) 3960 return ret; 3961 ret = rtw89_chip_enable_bb_rf(rtwdev); 3962 if (ret) 3963 return ret; 3964 3965 rtw89_phy_init_bb_reg(rtwdev); 3966 rtw89_phy_init_rf_reg(rtwdev, false); 3967 3968 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 3969 3970 rtw89_phy_dm_init(rtwdev); 3971 3972 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 3973 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 3974 3975 rtw89_tas_reset(rtwdev); 3976 3977 ret = rtw89_hci_start(rtwdev); 3978 if (ret) { 3979 rtw89_err(rtwdev, "failed to start hci\n"); 3980 return ret; 3981 } 3982 3983 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3984 RTW89_TRACK_WORK_PERIOD); 3985 3986 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 3987 3988 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 3989 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 3990 rtw89_fw_h2c_init_ba_cam(rtwdev); 3991 3992 return 0; 3993 } 3994 3995 void rtw89_core_stop(struct rtw89_dev *rtwdev) 3996 { 3997 struct rtw89_btc *btc = &rtwdev->btc; 3998 3999 /* Prvent to stop twice; enter_ips and ops_stop */ 4000 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4001 return; 4002 4003 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4004 4005 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4006 4007 mutex_unlock(&rtwdev->mutex); 4008 4009 cancel_work_sync(&rtwdev->c2h_work); 4010 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work); 4011 cancel_work_sync(&btc->eapol_notify_work); 4012 cancel_work_sync(&btc->arp_notify_work); 4013 cancel_work_sync(&btc->dhcp_notify_work); 4014 cancel_work_sync(&btc->icmp_notify_work); 4015 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4016 cancel_delayed_work_sync(&rtwdev->track_work); 4017 cancel_delayed_work_sync(&rtwdev->chanctx_work); 4018 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 4019 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 4020 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 4021 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 4022 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4023 cancel_delayed_work_sync(&rtwdev->antdiv_work); 4024 4025 mutex_lock(&rtwdev->mutex); 4026 4027 rtw89_btc_ntfy_poweroff(rtwdev); 4028 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4029 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4030 rtw89_hci_stop(rtwdev); 4031 rtw89_hci_deinit(rtwdev); 4032 rtw89_mac_pwr_off(rtwdev); 4033 rtw89_hci_reset(rtwdev); 4034 } 4035 4036 int rtw89_core_init(struct rtw89_dev *rtwdev) 4037 { 4038 struct rtw89_btc *btc = &rtwdev->btc; 4039 u8 band; 4040 4041 INIT_LIST_HEAD(&rtwdev->ba_list); 4042 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 4043 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 4044 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 4045 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 4046 if (!(rtwdev->chip->support_bands & BIT(band))) 4047 continue; 4048 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 4049 } 4050 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 4051 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 4052 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 4053 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 4054 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); 4055 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 4056 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 4057 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 4058 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 4059 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 4060 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 4061 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 4062 if (!rtwdev->txq_wq) 4063 return -ENOMEM; 4064 spin_lock_init(&rtwdev->ba_lock); 4065 spin_lock_init(&rtwdev->rpwm_lock); 4066 mutex_init(&rtwdev->mutex); 4067 mutex_init(&rtwdev->rf_mutex); 4068 rtwdev->total_sta_assoc = 0; 4069 4070 rtw89_init_wait(&rtwdev->mcc.wait); 4071 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 4072 4073 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 4074 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 4075 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 4076 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 4077 4078 skb_queue_head_init(&rtwdev->c2h_queue); 4079 rtw89_core_ppdu_sts_init(rtwdev); 4080 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 4081 4082 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 4083 4084 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 4085 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 4086 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 4087 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 4088 4089 init_completion(&rtwdev->fw.req.completion); 4090 4091 schedule_work(&rtwdev->load_firmware_work); 4092 4093 rtw89_ser_init(rtwdev); 4094 rtw89_entity_init(rtwdev); 4095 rtw89_tas_init(rtwdev); 4096 4097 return 0; 4098 } 4099 EXPORT_SYMBOL(rtw89_core_init); 4100 4101 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 4102 { 4103 rtw89_ser_deinit(rtwdev); 4104 rtw89_unload_firmware(rtwdev); 4105 rtw89_fw_free_all_early_h2c(rtwdev); 4106 4107 destroy_workqueue(rtwdev->txq_wq); 4108 mutex_destroy(&rtwdev->rf_mutex); 4109 mutex_destroy(&rtwdev->mutex); 4110 } 4111 EXPORT_SYMBOL(rtw89_core_deinit); 4112 4113 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4114 const u8 *mac_addr, bool hw_scan) 4115 { 4116 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4117 rtwvif->sub_entity_idx); 4118 4119 rtwdev->scanning = true; 4120 rtw89_leave_lps(rtwdev); 4121 if (hw_scan) 4122 rtw89_leave_ips_by_hwflags(rtwdev); 4123 4124 ether_addr_copy(rtwvif->mac_addr, mac_addr); 4125 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 4126 rtw89_chip_rfk_scan(rtwdev, true); 4127 rtw89_hci_recalc_int_mit(rtwdev); 4128 rtw89_phy_config_edcca(rtwdev, true); 4129 4130 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 4131 } 4132 4133 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4134 struct ieee80211_vif *vif, bool hw_scan) 4135 { 4136 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4137 4138 if (!rtwvif) 4139 return; 4140 4141 ether_addr_copy(rtwvif->mac_addr, vif->addr); 4142 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4143 4144 rtw89_chip_rfk_scan(rtwdev, false); 4145 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 4146 rtw89_phy_config_edcca(rtwdev, false); 4147 4148 rtwdev->scanning = false; 4149 rtwdev->dig.bypass_dig = true; 4150 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 4151 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 4152 } 4153 4154 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 4155 { 4156 const struct rtw89_chip_info *chip = rtwdev->chip; 4157 int ret; 4158 u8 val; 4159 u8 cv; 4160 4161 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 4162 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 4163 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 4164 cv = CHIP_CAV; 4165 else 4166 cv = CHIP_CBV; 4167 } 4168 4169 rtwdev->hal.cv = cv; 4170 4171 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) { 4172 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 4173 if (ret) 4174 return; 4175 4176 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 4177 } 4178 } 4179 4180 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 4181 { 4182 rtwdev->hal.support_cckpd = 4183 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 4184 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 4185 rtwdev->hal.support_igi = 4186 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 4187 } 4188 4189 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 4190 { 4191 const struct rtw89_chip_info *chip = rtwdev->chip; 4192 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 4193 struct rtw89_efuse *efuse = &rtwdev->efuse; 4194 const struct rtw89_rfe_parms *sel; 4195 u8 rfe_type = efuse->rfe_type; 4196 4197 if (!conf) { 4198 sel = chip->dflt_parms; 4199 goto out; 4200 } 4201 4202 while (conf->rfe_parms) { 4203 if (rfe_type == conf->rfe_type) { 4204 sel = conf->rfe_parms; 4205 goto out; 4206 } 4207 conf++; 4208 } 4209 4210 sel = chip->dflt_parms; 4211 4212 out: 4213 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 4214 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 4215 } 4216 4217 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 4218 { 4219 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4220 int ret; 4221 4222 ret = rtw89_mac_partial_init(rtwdev, false); 4223 if (ret) 4224 return ret; 4225 4226 ret = mac->parse_efuse_map(rtwdev); 4227 if (ret) 4228 return ret; 4229 4230 ret = mac->parse_phycap_map(rtwdev); 4231 if (ret) 4232 return ret; 4233 4234 ret = rtw89_mac_setup_phycap(rtwdev); 4235 if (ret) 4236 return ret; 4237 4238 rtw89_core_setup_phycap(rtwdev); 4239 4240 rtw89_hci_mac_pre_deinit(rtwdev); 4241 4242 rtw89_mac_pwr_off(rtwdev); 4243 4244 return 0; 4245 } 4246 4247 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 4248 { 4249 rtw89_chip_fem_setup(rtwdev); 4250 4251 return 0; 4252 } 4253 4254 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 4255 { 4256 int ret; 4257 4258 rtw89_read_chip_ver(rtwdev); 4259 4260 ret = rtw89_wait_firmware_completion(rtwdev); 4261 if (ret) { 4262 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 4263 return ret; 4264 } 4265 4266 ret = rtw89_fw_recognize(rtwdev); 4267 if (ret) { 4268 rtw89_err(rtwdev, "failed to recognize firmware\n"); 4269 return ret; 4270 } 4271 4272 ret = rtw89_chip_efuse_info_setup(rtwdev); 4273 if (ret) 4274 return ret; 4275 4276 ret = rtw89_fw_recognize_elements(rtwdev); 4277 if (ret) { 4278 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 4279 return ret; 4280 } 4281 4282 ret = rtw89_chip_board_info_setup(rtwdev); 4283 if (ret) 4284 return ret; 4285 4286 rtw89_core_setup_rfe_parms(rtwdev); 4287 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 4288 4289 return 0; 4290 } 4291 EXPORT_SYMBOL(rtw89_chip_info_setup); 4292 4293 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 4294 { 4295 struct ieee80211_hw *hw = rtwdev->hw; 4296 struct rtw89_efuse *efuse = &rtwdev->efuse; 4297 struct rtw89_hal *hal = &rtwdev->hal; 4298 int ret; 4299 int tx_headroom = IEEE80211_HT_CTL_LEN; 4300 4301 hw->vif_data_size = sizeof(struct rtw89_vif); 4302 hw->sta_data_size = sizeof(struct rtw89_sta); 4303 hw->txq_data_size = sizeof(struct rtw89_txq); 4304 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 4305 4306 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 4307 4308 hw->extra_tx_headroom = tx_headroom; 4309 hw->queues = IEEE80211_NUM_ACS; 4310 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 4311 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 4312 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 4313 4314 ieee80211_hw_set(hw, SIGNAL_DBM); 4315 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 4316 ieee80211_hw_set(hw, MFP_CAPABLE); 4317 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 4318 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 4319 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 4320 ieee80211_hw_set(hw, TX_AMSDU); 4321 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 4322 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 4323 ieee80211_hw_set(hw, SUPPORTS_PS); 4324 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 4325 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 4326 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 4327 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 4328 4329 /* ref: description of rtw89_mcc_get_tbtt_ofst() in chan.c */ 4330 ieee80211_hw_set(hw, TIMING_BEACON_ONLY); 4331 4332 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 4333 ieee80211_hw_set(hw, CONNECTION_MONITOR); 4334 4335 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 4336 BIT(NL80211_IFTYPE_AP) | 4337 BIT(NL80211_IFTYPE_P2P_CLIENT) | 4338 BIT(NL80211_IFTYPE_P2P_GO); 4339 4340 if (hal->ant_diversity) { 4341 hw->wiphy->available_antennas_tx = 0x3; 4342 hw->wiphy->available_antennas_rx = 0x3; 4343 } else { 4344 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 4345 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 4346 } 4347 4348 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 4349 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 4350 WIPHY_FLAG_AP_UAPSD | WIPHY_FLAG_SPLIT_SCAN_6GHZ; 4351 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 4352 4353 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 4354 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 4355 4356 #ifdef CONFIG_PM 4357 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 4358 #endif 4359 4360 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4361 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4362 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4363 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4364 hw->wiphy->max_remain_on_channel_duration = 1000; 4365 4366 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 4367 4368 ret = rtw89_core_set_supported_band(rtwdev); 4369 if (ret) { 4370 rtw89_err(rtwdev, "failed to set supported band\n"); 4371 return ret; 4372 } 4373 4374 ret = rtw89_regd_setup(rtwdev); 4375 if (ret) { 4376 rtw89_err(rtwdev, "failed to set up regd\n"); 4377 goto err_free_supported_band; 4378 } 4379 4380 hw->wiphy->sar_capa = &rtw89_sar_capa; 4381 4382 ret = ieee80211_register_hw(hw); 4383 if (ret) { 4384 rtw89_err(rtwdev, "failed to register hw\n"); 4385 goto err_free_supported_band; 4386 } 4387 4388 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 4389 if (ret) { 4390 rtw89_err(rtwdev, "failed to init regd\n"); 4391 goto err_unregister_hw; 4392 } 4393 4394 return 0; 4395 4396 err_unregister_hw: 4397 ieee80211_unregister_hw(hw); 4398 err_free_supported_band: 4399 rtw89_core_clr_supported_band(rtwdev); 4400 4401 return ret; 4402 } 4403 4404 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 4405 { 4406 struct ieee80211_hw *hw = rtwdev->hw; 4407 4408 ieee80211_unregister_hw(hw); 4409 rtw89_core_clr_supported_band(rtwdev); 4410 } 4411 4412 int rtw89_core_register(struct rtw89_dev *rtwdev) 4413 { 4414 int ret; 4415 4416 ret = rtw89_core_register_hw(rtwdev); 4417 if (ret) { 4418 rtw89_err(rtwdev, "failed to register core hw\n"); 4419 return ret; 4420 } 4421 4422 rtw89_debugfs_init(rtwdev); 4423 4424 return 0; 4425 } 4426 EXPORT_SYMBOL(rtw89_core_register); 4427 4428 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 4429 { 4430 rtw89_core_unregister_hw(rtwdev); 4431 } 4432 EXPORT_SYMBOL(rtw89_core_unregister); 4433 4434 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4435 u32 bus_data_size, 4436 const struct rtw89_chip_info *chip) 4437 { 4438 struct rtw89_fw_info early_fw = {}; 4439 const struct firmware *firmware; 4440 struct ieee80211_hw *hw; 4441 struct rtw89_dev *rtwdev; 4442 struct ieee80211_ops *ops; 4443 u32 driver_data_size; 4444 int fw_format = -1; 4445 bool no_chanctx; 4446 4447 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 4448 4449 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 4450 if (!ops) 4451 goto err; 4452 4453 no_chanctx = chip->support_chanctx_num == 0 || 4454 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 4455 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 4456 4457 if (no_chanctx) { 4458 ops->add_chanctx = NULL; 4459 ops->remove_chanctx = NULL; 4460 ops->change_chanctx = NULL; 4461 ops->assign_vif_chanctx = NULL; 4462 ops->unassign_vif_chanctx = NULL; 4463 ops->remain_on_channel = NULL; 4464 ops->cancel_remain_on_channel = NULL; 4465 } 4466 4467 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 4468 hw = ieee80211_alloc_hw(driver_data_size, ops); 4469 if (!hw) 4470 goto err; 4471 4472 hw->wiphy->iface_combinations = rtw89_iface_combs; 4473 4474 if (no_chanctx || chip->support_chanctx_num == 1) 4475 hw->wiphy->n_iface_combinations = 1; 4476 else 4477 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 4478 4479 rtwdev = hw->priv; 4480 rtwdev->hw = hw; 4481 rtwdev->dev = device; 4482 rtwdev->ops = ops; 4483 rtwdev->chip = chip; 4484 rtwdev->fw.req.firmware = firmware; 4485 rtwdev->fw.fw_format = fw_format; 4486 4487 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 4488 no_chanctx ? "without" : "with"); 4489 4490 return rtwdev; 4491 4492 err: 4493 kfree(ops); 4494 release_firmware(firmware); 4495 return NULL; 4496 } 4497 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 4498 4499 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 4500 { 4501 kfree(rtwdev->ops); 4502 kfree(rtwdev->rfe_data); 4503 release_firmware(rtwdev->fw.req.firmware); 4504 ieee80211_free_hw(rtwdev->hw); 4505 } 4506 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 4507 4508 MODULE_AUTHOR("Realtek Corporation"); 4509 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 4510 MODULE_LICENSE("Dual BSD/GPL"); 4511