1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 #include "wow.h" 22 23 static bool rtw89_disable_ps_mode; 24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 26 27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 37 38 static struct ieee80211_channel rtw89_channels_2ghz[] = { 39 RTW89_DEF_CHAN_2G(2412, 1), 40 RTW89_DEF_CHAN_2G(2417, 2), 41 RTW89_DEF_CHAN_2G(2422, 3), 42 RTW89_DEF_CHAN_2G(2427, 4), 43 RTW89_DEF_CHAN_2G(2432, 5), 44 RTW89_DEF_CHAN_2G(2437, 6), 45 RTW89_DEF_CHAN_2G(2442, 7), 46 RTW89_DEF_CHAN_2G(2447, 8), 47 RTW89_DEF_CHAN_2G(2452, 9), 48 RTW89_DEF_CHAN_2G(2457, 10), 49 RTW89_DEF_CHAN_2G(2462, 11), 50 RTW89_DEF_CHAN_2G(2467, 12), 51 RTW89_DEF_CHAN_2G(2472, 13), 52 RTW89_DEF_CHAN_2G(2484, 14), 53 }; 54 55 static struct ieee80211_channel rtw89_channels_5ghz[] = { 56 RTW89_DEF_CHAN_5G(5180, 36), 57 RTW89_DEF_CHAN_5G(5200, 40), 58 RTW89_DEF_CHAN_5G(5220, 44), 59 RTW89_DEF_CHAN_5G(5240, 48), 60 RTW89_DEF_CHAN_5G(5260, 52), 61 RTW89_DEF_CHAN_5G(5280, 56), 62 RTW89_DEF_CHAN_5G(5300, 60), 63 RTW89_DEF_CHAN_5G(5320, 64), 64 RTW89_DEF_CHAN_5G(5500, 100), 65 RTW89_DEF_CHAN_5G(5520, 104), 66 RTW89_DEF_CHAN_5G(5540, 108), 67 RTW89_DEF_CHAN_5G(5560, 112), 68 RTW89_DEF_CHAN_5G(5580, 116), 69 RTW89_DEF_CHAN_5G(5600, 120), 70 RTW89_DEF_CHAN_5G(5620, 124), 71 RTW89_DEF_CHAN_5G(5640, 128), 72 RTW89_DEF_CHAN_5G(5660, 132), 73 RTW89_DEF_CHAN_5G(5680, 136), 74 RTW89_DEF_CHAN_5G(5700, 140), 75 RTW89_DEF_CHAN_5G(5720, 144), 76 RTW89_DEF_CHAN_5G(5745, 149), 77 RTW89_DEF_CHAN_5G(5765, 153), 78 RTW89_DEF_CHAN_5G(5785, 157), 79 RTW89_DEF_CHAN_5G(5805, 161), 80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 81 RTW89_DEF_CHAN_5G(5845, 169), 82 RTW89_DEF_CHAN_5G(5865, 173), 83 RTW89_DEF_CHAN_5G(5885, 177), 84 }; 85 86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 87 ARRAY_SIZE(rtw89_channels_5ghz)); 88 89 static struct ieee80211_channel rtw89_channels_6ghz[] = { 90 RTW89_DEF_CHAN_6G(5955, 1), 91 RTW89_DEF_CHAN_6G(5975, 5), 92 RTW89_DEF_CHAN_6G(5995, 9), 93 RTW89_DEF_CHAN_6G(6015, 13), 94 RTW89_DEF_CHAN_6G(6035, 17), 95 RTW89_DEF_CHAN_6G(6055, 21), 96 RTW89_DEF_CHAN_6G(6075, 25), 97 RTW89_DEF_CHAN_6G(6095, 29), 98 RTW89_DEF_CHAN_6G(6115, 33), 99 RTW89_DEF_CHAN_6G(6135, 37), 100 RTW89_DEF_CHAN_6G(6155, 41), 101 RTW89_DEF_CHAN_6G(6175, 45), 102 RTW89_DEF_CHAN_6G(6195, 49), 103 RTW89_DEF_CHAN_6G(6215, 53), 104 RTW89_DEF_CHAN_6G(6235, 57), 105 RTW89_DEF_CHAN_6G(6255, 61), 106 RTW89_DEF_CHAN_6G(6275, 65), 107 RTW89_DEF_CHAN_6G(6295, 69), 108 RTW89_DEF_CHAN_6G(6315, 73), 109 RTW89_DEF_CHAN_6G(6335, 77), 110 RTW89_DEF_CHAN_6G(6355, 81), 111 RTW89_DEF_CHAN_6G(6375, 85), 112 RTW89_DEF_CHAN_6G(6395, 89), 113 RTW89_DEF_CHAN_6G(6415, 93), 114 RTW89_DEF_CHAN_6G(6435, 97), 115 RTW89_DEF_CHAN_6G(6455, 101), 116 RTW89_DEF_CHAN_6G(6475, 105), 117 RTW89_DEF_CHAN_6G(6495, 109), 118 RTW89_DEF_CHAN_6G(6515, 113), 119 RTW89_DEF_CHAN_6G(6535, 117), 120 RTW89_DEF_CHAN_6G(6555, 121), 121 RTW89_DEF_CHAN_6G(6575, 125), 122 RTW89_DEF_CHAN_6G(6595, 129), 123 RTW89_DEF_CHAN_6G(6615, 133), 124 RTW89_DEF_CHAN_6G(6635, 137), 125 RTW89_DEF_CHAN_6G(6655, 141), 126 RTW89_DEF_CHAN_6G(6675, 145), 127 RTW89_DEF_CHAN_6G(6695, 149), 128 RTW89_DEF_CHAN_6G(6715, 153), 129 RTW89_DEF_CHAN_6G(6735, 157), 130 RTW89_DEF_CHAN_6G(6755, 161), 131 RTW89_DEF_CHAN_6G(6775, 165), 132 RTW89_DEF_CHAN_6G(6795, 169), 133 RTW89_DEF_CHAN_6G(6815, 173), 134 RTW89_DEF_CHAN_6G(6835, 177), 135 RTW89_DEF_CHAN_6G(6855, 181), 136 RTW89_DEF_CHAN_6G(6875, 185), 137 RTW89_DEF_CHAN_6G(6895, 189), 138 RTW89_DEF_CHAN_6G(6915, 193), 139 RTW89_DEF_CHAN_6G(6935, 197), 140 RTW89_DEF_CHAN_6G(6955, 201), 141 RTW89_DEF_CHAN_6G(6975, 205), 142 RTW89_DEF_CHAN_6G(6995, 209), 143 RTW89_DEF_CHAN_6G(7015, 213), 144 RTW89_DEF_CHAN_6G(7035, 217), 145 RTW89_DEF_CHAN_6G(7055, 221), 146 RTW89_DEF_CHAN_6G(7075, 225), 147 RTW89_DEF_CHAN_6G(7095, 229), 148 RTW89_DEF_CHAN_6G(7115, 233), 149 }; 150 151 static struct ieee80211_rate rtw89_bitrates[] = { 152 { .bitrate = 10, .hw_value = 0x00, }, 153 { .bitrate = 20, .hw_value = 0x01, }, 154 { .bitrate = 55, .hw_value = 0x02, }, 155 { .bitrate = 110, .hw_value = 0x03, }, 156 { .bitrate = 60, .hw_value = 0x04, }, 157 { .bitrate = 90, .hw_value = 0x05, }, 158 { .bitrate = 120, .hw_value = 0x06, }, 159 { .bitrate = 180, .hw_value = 0x07, }, 160 { .bitrate = 240, .hw_value = 0x08, }, 161 { .bitrate = 360, .hw_value = 0x09, }, 162 { .bitrate = 480, .hw_value = 0x0a, }, 163 { .bitrate = 540, .hw_value = 0x0b, }, 164 }; 165 166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_STATION), 170 }, 171 { 172 .max = 1, 173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 174 BIT(NL80211_IFTYPE_P2P_GO) | 175 BIT(NL80211_IFTYPE_AP), 176 }, 177 }; 178 179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_STATION), 183 }, 184 { 185 .max = 1, 186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 187 BIT(NL80211_IFTYPE_P2P_GO), 188 }, 189 }; 190 191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 192 { 193 .limits = rtw89_iface_limits, 194 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 195 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 196 .num_different_channels = 1, 197 }, 198 { 199 .limits = rtw89_iface_limits_mcc, 200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 201 .max_interfaces = RTW89_MAX_INTERFACE_NUM, 202 .num_different_channels = 2, 203 }, 204 }; 205 206 #define RTW89_6GHZ_SPAN_HEAD 6145 207 #define RTW89_6GHZ_SPAN_IDX(center_freq) \ 208 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2) 209 210 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \ 211 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \ 212 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \ 213 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \ 214 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \ 215 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \ 216 } 217 218 /* Since 6GHz subbands are not edge aligned, some cases span two subbands. 219 * In the following, we describe each of them with rtw89_6ghz_span. 220 */ 221 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = { 222 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H), 223 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H), 224 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H), 225 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L), 226 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L), 227 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L), 228 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H), 229 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H), 230 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8), 231 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8), 232 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8), 233 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8), 234 }; 235 236 const struct rtw89_6ghz_span * 237 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq) 238 { 239 int idx; 240 241 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) { 242 idx = RTW89_6GHZ_SPAN_IDX(center_freq); 243 /* To decrease size of rtw89_overlapping_6ghz[], 244 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs 245 * to make first span as index 0 of the table. So, if center 246 * frequency is less than the first one, it will get netative. 247 */ 248 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz)) 249 return &rtw89_overlapping_6ghz[idx]; 250 } 251 252 return NULL; 253 } 254 255 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 256 { 257 struct ieee80211_rate rate; 258 259 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 260 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 261 return false; 262 } 263 264 rate = rtw89_bitrates[rpt_rate]; 265 *bitrate = rate.bitrate; 266 267 return true; 268 } 269 270 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 271 .band = NL80211_BAND_2GHZ, 272 .channels = rtw89_channels_2ghz, 273 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 274 .bitrates = rtw89_bitrates, 275 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 276 .ht_cap = {0}, 277 .vht_cap = {0}, 278 }; 279 280 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 281 .band = NL80211_BAND_5GHZ, 282 .channels = rtw89_channels_5ghz, 283 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 284 285 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 286 .bitrates = rtw89_bitrates + 4, 287 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 288 .ht_cap = {0}, 289 .vht_cap = {0}, 290 }; 291 292 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 293 .band = NL80211_BAND_6GHZ, 294 .channels = rtw89_channels_6ghz, 295 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 296 297 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 298 .bitrates = rtw89_bitrates + 4, 299 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 300 }; 301 302 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 303 struct rtw89_traffic_stats *stats, 304 struct sk_buff *skb, bool tx) 305 { 306 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 307 308 if (tx && ieee80211_is_assoc_req(hdr->frame_control)) 309 rtw89_wow_parse_akm(rtwdev, skb); 310 311 if (!ieee80211_is_data(hdr->frame_control)) 312 return; 313 314 if (is_broadcast_ether_addr(hdr->addr1) || 315 is_multicast_ether_addr(hdr->addr1)) 316 return; 317 318 if (tx) { 319 stats->tx_cnt++; 320 stats->tx_unicast += skb->len; 321 } else { 322 stats->rx_cnt++; 323 stats->rx_unicast += skb->len; 324 } 325 } 326 327 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 328 { 329 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 330 NL80211_CHAN_NO_HT); 331 } 332 333 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 334 struct rtw89_chan *chan) 335 { 336 struct ieee80211_channel *channel = chandef->chan; 337 enum nl80211_chan_width width = chandef->width; 338 u32 primary_freq, center_freq; 339 u8 center_chan; 340 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 341 u32 offset; 342 u8 band; 343 344 center_chan = channel->hw_value; 345 primary_freq = channel->center_freq; 346 center_freq = chandef->center_freq1; 347 348 switch (width) { 349 case NL80211_CHAN_WIDTH_20_NOHT: 350 case NL80211_CHAN_WIDTH_20: 351 bandwidth = RTW89_CHANNEL_WIDTH_20; 352 break; 353 case NL80211_CHAN_WIDTH_40: 354 bandwidth = RTW89_CHANNEL_WIDTH_40; 355 if (primary_freq > center_freq) { 356 center_chan -= 2; 357 } else { 358 center_chan += 2; 359 } 360 break; 361 case NL80211_CHAN_WIDTH_80: 362 case NL80211_CHAN_WIDTH_160: 363 bandwidth = nl_to_rtw89_bandwidth(width); 364 if (primary_freq > center_freq) { 365 offset = (primary_freq - center_freq - 10) / 20; 366 center_chan -= 2 + offset * 4; 367 } else { 368 offset = (center_freq - primary_freq - 10) / 20; 369 center_chan += 2 + offset * 4; 370 } 371 break; 372 default: 373 center_chan = 0; 374 break; 375 } 376 377 switch (channel->band) { 378 default: 379 case NL80211_BAND_2GHZ: 380 band = RTW89_BAND_2G; 381 break; 382 case NL80211_BAND_5GHZ: 383 band = RTW89_BAND_5G; 384 break; 385 case NL80211_BAND_6GHZ: 386 band = RTW89_BAND_6G; 387 break; 388 } 389 390 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 391 } 392 393 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev, 394 const struct rtw89_chan *chan, 395 enum rtw89_phy_idx phy_idx) 396 { 397 const struct rtw89_chip_info *chip = rtwdev->chip; 398 bool entity_active; 399 400 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 401 if (!entity_active) 402 return; 403 404 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 405 } 406 407 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 408 { 409 const struct rtw89_chan *chan; 410 411 chan = rtw89_mgnt_chan_get(rtwdev, 0); 412 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0); 413 414 if (!rtwdev->support_mlo) 415 return; 416 417 chan = rtw89_mgnt_chan_get(rtwdev, 1); 418 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1); 419 } 420 421 static void __rtw89_set_channel(struct rtw89_dev *rtwdev, 422 const struct rtw89_chan *chan, 423 enum rtw89_mac_idx mac_idx, 424 enum rtw89_phy_idx phy_idx) 425 { 426 const struct rtw89_chip_info *chip = rtwdev->chip; 427 const struct rtw89_chan_rcd *chan_rcd; 428 struct rtw89_channel_help_params bak; 429 bool entity_active; 430 431 entity_active = rtw89_get_entity_state(rtwdev, phy_idx); 432 433 chan_rcd = rtw89_chan_rcd_get_by_chan(chan); 434 435 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 436 437 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 438 439 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 440 441 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 442 443 if (!entity_active || chan_rcd->band_changed) { 444 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 445 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan); 446 } 447 448 rtw89_set_entity_state(rtwdev, phy_idx, true); 449 } 450 451 int rtw89_set_channel(struct rtw89_dev *rtwdev) 452 { 453 const struct rtw89_chan *chan; 454 enum rtw89_entity_mode mode; 455 456 mode = rtw89_entity_recalc(rtwdev); 457 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) { 458 WARN(1, "Invalid ent mode: %d\n", mode); 459 return -EINVAL; 460 } 461 462 chan = rtw89_mgnt_chan_get(rtwdev, 0); 463 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0); 464 465 if (!rtwdev->support_mlo) 466 return 0; 467 468 chan = rtw89_mgnt_chan_get(rtwdev, 1); 469 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1); 470 471 return 0; 472 } 473 474 static enum rtw89_core_tx_type 475 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 476 struct sk_buff *skb) 477 { 478 struct ieee80211_hdr *hdr = (void *)skb->data; 479 __le16 fc = hdr->frame_control; 480 481 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 482 return RTW89_CORE_TX_TYPE_MGMT; 483 484 return RTW89_CORE_TX_TYPE_DATA; 485 } 486 487 static void 488 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 489 struct rtw89_core_tx_request *tx_req, 490 enum btc_pkt_type pkt_type) 491 { 492 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 493 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 494 struct ieee80211_link_sta *link_sta; 495 struct sk_buff *skb = tx_req->skb; 496 struct rtw89_sta *rtwsta; 497 u8 ampdu_num; 498 u8 tid; 499 500 if (pkt_type == PACKET_EAPOL) { 501 desc_info->bk = true; 502 return; 503 } 504 505 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 506 return; 507 508 if (!rtwsta_link) { 509 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 510 return; 511 } 512 513 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 514 rtwsta = rtwsta_link->rtwsta; 515 516 rcu_read_lock(); 517 518 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 519 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 520 rtwsta->ampdu_params[tid].agg_num : 521 4 << link_sta->ht_cap.ampdu_factor) - 1); 522 523 desc_info->agg_en = true; 524 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density; 525 desc_info->ampdu_num = ampdu_num; 526 527 rcu_read_unlock(); 528 } 529 530 static void 531 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 532 struct rtw89_core_tx_request *tx_req) 533 { 534 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 535 const struct rtw89_chip_info *chip = rtwdev->chip; 536 const struct rtw89_sec_cam_entry *sec_cam; 537 struct ieee80211_tx_info *info; 538 struct ieee80211_key_conf *key; 539 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 540 struct sk_buff *skb = tx_req->skb; 541 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 542 u8 sec_cam_idx; 543 u64 pn64; 544 545 info = IEEE80211_SKB_CB(skb); 546 key = info->control.hw_key; 547 sec_cam_idx = key->hw_key_idx; 548 sec_cam = cam_info->sec_entries[sec_cam_idx]; 549 if (!sec_cam) { 550 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 551 return; 552 } 553 554 switch (key->cipher) { 555 case WLAN_CIPHER_SUITE_WEP40: 556 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 557 break; 558 case WLAN_CIPHER_SUITE_WEP104: 559 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 560 break; 561 case WLAN_CIPHER_SUITE_TKIP: 562 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 563 break; 564 case WLAN_CIPHER_SUITE_CCMP: 565 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 566 break; 567 case WLAN_CIPHER_SUITE_CCMP_256: 568 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 569 break; 570 case WLAN_CIPHER_SUITE_GCMP: 571 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 572 break; 573 case WLAN_CIPHER_SUITE_GCMP_256: 574 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 575 break; 576 default: 577 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 578 return; 579 } 580 581 desc_info->sec_en = true; 582 desc_info->sec_keyid = key->keyidx; 583 desc_info->sec_type = sec_type; 584 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 585 586 if (!chip->hw_sec_hdr) 587 return; 588 589 pn64 = atomic64_inc_return(&key->tx_pn); 590 desc_info->sec_seq[0] = pn64; 591 desc_info->sec_seq[1] = pn64 >> 8; 592 desc_info->sec_seq[2] = pn64 >> 16; 593 desc_info->sec_seq[3] = pn64 >> 24; 594 desc_info->sec_seq[4] = pn64 >> 32; 595 desc_info->sec_seq[5] = pn64 >> 40; 596 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 597 } 598 599 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 600 struct rtw89_core_tx_request *tx_req, 601 const struct rtw89_chan *chan) 602 { 603 struct sk_buff *skb = tx_req->skb; 604 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 605 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 606 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 607 struct ieee80211_vif *vif = tx_info->control.vif; 608 struct ieee80211_bss_conf *bss_conf; 609 u16 lowest_rate; 610 u16 rate; 611 612 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 613 (vif && vif->p2p)) 614 lowest_rate = RTW89_HW_RATE_OFDM6; 615 else if (chan->band_type == RTW89_BAND_2G) 616 lowest_rate = RTW89_HW_RATE_CCK1; 617 else 618 lowest_rate = RTW89_HW_RATE_OFDM6; 619 620 if (!rtwvif_link) 621 return lowest_rate; 622 623 rcu_read_lock(); 624 625 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 626 if (!bss_conf->basic_rates || !rtwsta_link) { 627 rate = lowest_rate; 628 goto out; 629 } 630 631 rate = __ffs(bss_conf->basic_rates) + lowest_rate; 632 633 out: 634 rcu_read_unlock(); 635 636 return rate; 637 } 638 639 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 640 struct rtw89_core_tx_request *tx_req) 641 { 642 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 643 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 644 645 if (!rtwsta_link) 646 return rtwvif_link->mac_id; 647 648 return rtwsta_link->mac_id; 649 } 650 651 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 652 struct rtw89_tx_desc_info *desc_info, 653 struct sk_buff *skb) 654 { 655 struct ieee80211_hdr *hdr = (void *)skb->data; 656 __le16 fc = hdr->frame_control; 657 658 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 659 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 660 } 661 662 static void 663 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 664 struct rtw89_core_tx_request *tx_req) 665 { 666 const struct rtw89_chip_info *chip = rtwdev->chip; 667 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 668 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 669 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 670 rtwvif_link->chanctx_idx); 671 struct sk_buff *skb = tx_req->skb; 672 u8 qsel, ch_dma; 673 674 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 675 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 676 677 desc_info->qsel = qsel; 678 desc_info->ch_dma = ch_dma; 679 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 680 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 681 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 682 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 683 684 /* fixed data rate for mgmt frames */ 685 desc_info->en_wd_info = true; 686 desc_info->use_rate = true; 687 desc_info->dis_data_fb = true; 688 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 689 690 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) { 691 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 692 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 693 } 694 695 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 696 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 697 desc_info->data_rate, chan->channel, chan->band_type, 698 chan->band_width); 699 } 700 701 static void 702 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 703 struct rtw89_core_tx_request *tx_req) 704 { 705 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 706 707 desc_info->is_bmc = false; 708 desc_info->wd_page = false; 709 desc_info->ch_dma = RTW89_DMA_H2C; 710 } 711 712 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 713 const struct rtw89_chan *chan) 714 { 715 static const u8 rtw89_bandwidth_to_om[] = { 716 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 717 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 718 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 719 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 720 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 721 }; 722 const struct rtw89_chip_info *chip = rtwdev->chip; 723 struct rtw89_hal *hal = &rtwdev->hal; 724 u8 om_bandwidth; 725 726 if (!chip->dis_2g_40m_ul_ofdma || 727 chan->band_type != RTW89_BAND_2G || 728 chan->band_width != RTW89_CHANNEL_WIDTH_40) 729 return; 730 731 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 732 rtw89_bandwidth_to_om[chan->band_width] : 0; 733 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 734 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 735 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 736 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 737 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 738 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 739 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 740 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 741 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 742 } 743 744 static bool 745 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 746 struct rtw89_core_tx_request *tx_req, 747 enum btc_pkt_type pkt_type) 748 { 749 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 750 struct sk_buff *skb = tx_req->skb; 751 struct ieee80211_hdr *hdr = (void *)skb->data; 752 struct ieee80211_link_sta *link_sta; 753 __le16 fc = hdr->frame_control; 754 755 /* AP IOT issue with EAPoL, ARP and DHCP */ 756 if (pkt_type < PACKET_MAX) 757 return false; 758 759 if (!rtwsta_link) 760 return false; 761 762 rcu_read_lock(); 763 764 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 765 if (!link_sta->he_cap.has_he) { 766 rcu_read_unlock(); 767 return false; 768 } 769 770 rcu_read_unlock(); 771 772 if (!ieee80211_is_data_qos(fc)) 773 return false; 774 775 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 776 return false; 777 778 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy) 779 return false; 780 781 return true; 782 } 783 784 static void 785 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 786 struct rtw89_core_tx_request *tx_req) 787 { 788 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 789 struct sk_buff *skb = tx_req->skb; 790 struct ieee80211_hdr *hdr = (void *)skb->data; 791 __le16 fc = hdr->frame_control; 792 void *data; 793 __le32 *htc; 794 u8 *qc; 795 int hdr_len; 796 797 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 798 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 799 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 800 801 hdr = data; 802 htc = data + hdr_len; 803 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 804 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template : 805 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 806 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 807 808 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 809 qc[0] |= IEEE80211_QOS_CTL_EOSP; 810 } 811 812 static void 813 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 814 struct rtw89_core_tx_request *tx_req, 815 enum btc_pkt_type pkt_type) 816 { 817 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 818 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 819 820 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 821 goto desc_bk; 822 823 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 824 825 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 826 desc_info->a_ctrl_bsr = true; 827 828 desc_bk: 829 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr) 830 return; 831 832 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr; 833 desc_info->bk = true; 834 } 835 836 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 837 struct rtw89_core_tx_request *tx_req) 838 { 839 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 840 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 841 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 842 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern; 843 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx; 844 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 845 struct ieee80211_link_sta *link_sta; 846 u16 lowest_rate; 847 u16 rate; 848 849 if (rate_pattern->enable) 850 return rate_pattern->rate; 851 852 if (vif->p2p) 853 lowest_rate = RTW89_HW_RATE_OFDM6; 854 else if (chan->band_type == RTW89_BAND_2G) 855 lowest_rate = RTW89_HW_RATE_CCK1; 856 else 857 lowest_rate = RTW89_HW_RATE_OFDM6; 858 859 if (!rtwsta_link) 860 return lowest_rate; 861 862 rcu_read_lock(); 863 864 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 865 if (!link_sta->supp_rates[chan->band_type]) { 866 rate = lowest_rate; 867 goto out; 868 } 869 870 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate; 871 872 out: 873 rcu_read_unlock(); 874 875 return rate; 876 } 877 878 static void 879 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 880 struct rtw89_core_tx_request *tx_req) 881 { 882 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link; 883 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link; 884 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 885 struct sk_buff *skb = tx_req->skb; 886 u8 tid, tid_indicate; 887 u8 qsel, ch_dma; 888 889 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 890 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 891 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 892 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 893 894 desc_info->ch_dma = ch_dma; 895 desc_info->tid_indicate = tid_indicate; 896 desc_info->qsel = qsel; 897 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 898 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0; 899 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false; 900 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false; 901 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false; 902 903 /* enable wd_info for AMPDU */ 904 desc_info->en_wd_info = true; 905 906 if (IEEE80211_SKB_CB(skb)->control.hw_key) 907 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 908 909 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 910 } 911 912 static enum btc_pkt_type 913 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 914 struct rtw89_core_tx_request *tx_req) 915 { 916 struct wiphy *wiphy = rtwdev->hw->wiphy; 917 struct sk_buff *skb = tx_req->skb; 918 struct udphdr *udphdr; 919 920 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 921 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work); 922 return PACKET_EAPOL; 923 } 924 925 if (skb->protocol == htons(ETH_P_ARP)) { 926 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work); 927 return PACKET_ARP; 928 } 929 930 if (skb->protocol == htons(ETH_P_IP) && 931 ip_hdr(skb)->protocol == IPPROTO_UDP) { 932 udphdr = udp_hdr(skb); 933 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 934 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 935 skb->len > 282) { 936 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work); 937 return PACKET_DHCP; 938 } 939 } 940 941 if (skb->protocol == htons(ETH_P_IP) && 942 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 943 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work); 944 return PACKET_ICMP; 945 } 946 947 return PACKET_MAX; 948 } 949 950 static void 951 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 952 struct rtw89_core_tx_request *tx_req) 953 { 954 const struct rtw89_chip_info *chip = rtwdev->chip; 955 956 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 957 return; 958 959 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 960 return; 961 962 if (chip->chip_id != RTL8852C && 963 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 964 return; 965 966 rtw89_mac_notify_wake(rtwdev); 967 } 968 969 static void 970 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 971 struct rtw89_core_tx_request *tx_req) 972 { 973 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 974 struct sk_buff *skb = tx_req->skb; 975 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 976 struct ieee80211_hdr *hdr = (void *)skb->data; 977 struct rtw89_addr_cam_entry *addr_cam; 978 enum rtw89_core_tx_type tx_type; 979 enum btc_pkt_type pkt_type; 980 bool upd_wlan_hdr = false; 981 bool is_bmc; 982 u16 seq; 983 984 if (tx_req->sta) 985 desc_info->mlo = tx_req->sta->mlo; 986 else if (tx_req->vif) 987 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif); 988 989 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 990 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 991 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 992 tx_req->tx_type = tx_type; 993 994 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link, 995 tx_req->rtwsta_link); 996 if (addr_cam->valid && desc_info->mlo) 997 upd_wlan_hdr = true; 998 } 999 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 1000 is_multicast_ether_addr(hdr->addr1)); 1001 1002 desc_info->seq = seq; 1003 desc_info->pkt_size = skb->len; 1004 desc_info->is_bmc = is_bmc; 1005 desc_info->wd_page = true; 1006 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 1007 desc_info->upd_wlan_hdr = upd_wlan_hdr; 1008 1009 switch (tx_req->tx_type) { 1010 case RTW89_CORE_TX_TYPE_MGMT: 1011 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 1012 break; 1013 case RTW89_CORE_TX_TYPE_DATA: 1014 rtw89_core_tx_update_data_info(rtwdev, tx_req); 1015 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 1016 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 1017 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 1018 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 1019 break; 1020 case RTW89_CORE_TX_TYPE_FWCMD: 1021 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 1022 break; 1023 } 1024 } 1025 1026 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 1027 { 1028 u8 ch_dma; 1029 1030 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 1031 1032 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 1033 } 1034 1035 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 1036 int qsel, unsigned int timeout) 1037 { 1038 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 1039 struct rtw89_tx_wait_info *wait; 1040 unsigned long time_left; 1041 int ret = 0; 1042 1043 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 1044 if (!wait) { 1045 rtw89_core_tx_kick_off(rtwdev, qsel); 1046 return 0; 1047 } 1048 1049 init_completion(&wait->completion); 1050 rcu_assign_pointer(skb_data->wait, wait); 1051 1052 rtw89_core_tx_kick_off(rtwdev, qsel); 1053 time_left = wait_for_completion_timeout(&wait->completion, 1054 msecs_to_jiffies(timeout)); 1055 if (time_left == 0) 1056 ret = -ETIMEDOUT; 1057 else if (!wait->tx_done) 1058 ret = -EAGAIN; 1059 1060 rcu_assign_pointer(skb_data->wait, NULL); 1061 kfree_rcu(wait, rcu_head); 1062 1063 return ret; 1064 } 1065 1066 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 1067 struct sk_buff *skb, bool fwdl) 1068 { 1069 struct rtw89_core_tx_request tx_req = {0}; 1070 u32 cnt; 1071 int ret; 1072 1073 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 1074 rtw89_debug(rtwdev, RTW89_DBG_FW, 1075 "ignore h2c due to power is off with firmware state=%d\n", 1076 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 1077 dev_kfree_skb(skb); 1078 return 0; 1079 } 1080 1081 tx_req.skb = skb; 1082 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1083 if (fwdl) 1084 tx_req.desc_info.fw_dl = true; 1085 1086 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1087 1088 if (!fwdl) 1089 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1090 1091 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1092 if (cnt == 0) { 1093 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1094 return -ENOSPC; 1095 } 1096 1097 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1098 if (ret) { 1099 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1100 return ret; 1101 } 1102 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1103 1104 return 0; 1105 } 1106 1107 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1108 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1109 { 1110 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 1111 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 1112 struct rtw89_core_tx_request tx_req = {0}; 1113 struct rtw89_sta_link *rtwsta_link = NULL; 1114 struct rtw89_vif_link *rtwvif_link; 1115 int ret; 1116 1117 /* By default, driver writes tx via the link on HW-0. And then, 1118 * according to links' status, HW can change tx to another link. 1119 */ 1120 1121 if (rtwsta) { 1122 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0); 1123 if (unlikely(!rtwsta_link)) { 1124 rtw89_err(rtwdev, "tx: find no sta link on HW-0\n"); 1125 return -ENOLINK; 1126 } 1127 } 1128 1129 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0); 1130 if (unlikely(!rtwvif_link)) { 1131 rtw89_err(rtwdev, "tx: find no vif link on HW-0\n"); 1132 return -ENOLINK; 1133 } 1134 1135 tx_req.skb = skb; 1136 tx_req.vif = vif; 1137 tx_req.sta = sta; 1138 tx_req.rtwvif_link = rtwvif_link; 1139 tx_req.rtwsta_link = rtwsta_link; 1140 1141 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1142 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1143 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1144 rtw89_core_tx_wake(rtwdev, &tx_req); 1145 1146 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1147 if (ret) { 1148 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1149 return ret; 1150 } 1151 1152 if (qsel) 1153 *qsel = tx_req.desc_info.qsel; 1154 1155 return 0; 1156 } 1157 1158 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1159 { 1160 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1161 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1162 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1163 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1164 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1165 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1166 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1167 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1168 1169 return cpu_to_le32(dword); 1170 } 1171 1172 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1173 { 1174 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1175 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1176 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1177 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1178 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1179 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1180 1181 return cpu_to_le32(dword); 1182 } 1183 1184 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1185 { 1186 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1187 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1188 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1189 1190 return cpu_to_le32(dword); 1191 } 1192 1193 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1194 { 1195 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1196 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1197 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1198 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1199 1200 return cpu_to_le32(dword); 1201 } 1202 1203 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1204 { 1205 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1206 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1207 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1208 1209 return cpu_to_le32(dword); 1210 } 1211 1212 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1213 { 1214 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1215 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1216 1217 return cpu_to_le32(dword); 1218 } 1219 1220 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1221 { 1222 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1223 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1224 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1225 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1226 1227 return cpu_to_le32(dword); 1228 } 1229 1230 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1231 { 1232 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1233 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1234 1235 return cpu_to_le32(dword); 1236 } 1237 1238 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1239 { 1240 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1241 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1242 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1243 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1244 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1245 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1246 1247 return cpu_to_le32(dword); 1248 } 1249 1250 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1251 { 1252 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) | 1253 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) | 1254 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1255 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1256 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1257 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1258 1259 return cpu_to_le32(dword); 1260 } 1261 1262 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1263 { 1264 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1265 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1266 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1267 desc_info->data_retry_lowest_rate); 1268 1269 return cpu_to_le32(dword); 1270 } 1271 1272 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1273 { 1274 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1275 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1276 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1277 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1278 1279 return cpu_to_le32(dword); 1280 } 1281 1282 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1283 { 1284 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1285 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1286 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1287 1288 return cpu_to_le32(dword); 1289 } 1290 1291 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1292 { 1293 bool rts_en = !desc_info->is_bmc; 1294 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1295 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1296 1297 return cpu_to_le32(dword); 1298 } 1299 1300 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1301 struct rtw89_tx_desc_info *desc_info, 1302 void *txdesc) 1303 { 1304 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1305 struct rtw89_txwd_info *txwd_info; 1306 1307 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1308 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1309 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1310 1311 if (!desc_info->en_wd_info) 1312 return; 1313 1314 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1315 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1316 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1317 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1318 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1319 1320 } 1321 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1322 1323 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1324 struct rtw89_tx_desc_info *desc_info, 1325 void *txdesc) 1326 { 1327 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1328 struct rtw89_txwd_info *txwd_info; 1329 1330 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1331 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1332 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1333 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1334 if (desc_info->sec_en) { 1335 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1336 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1337 } 1338 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1339 1340 if (!desc_info->en_wd_info) 1341 return; 1342 1343 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1344 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1345 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1346 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1347 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1348 } 1349 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1350 1351 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1352 { 1353 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1354 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1355 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1356 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1357 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1358 1359 return cpu_to_le32(dword); 1360 } 1361 1362 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1363 { 1364 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1365 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1366 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1367 1368 return cpu_to_le32(dword); 1369 } 1370 1371 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1372 { 1373 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1374 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1375 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1376 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1377 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1378 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1379 1380 return cpu_to_le32(dword); 1381 } 1382 1383 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1384 { 1385 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq); 1386 1387 return cpu_to_le32(dword); 1388 } 1389 1390 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1391 { 1392 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1393 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1394 1395 return cpu_to_le32(dword); 1396 } 1397 1398 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1399 { 1400 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1401 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1402 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1403 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1404 1405 return cpu_to_le32(dword); 1406 } 1407 1408 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info) 1409 { 1410 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr); 1411 1412 return cpu_to_le32(dword); 1413 } 1414 1415 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1416 { 1417 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1418 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1419 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1420 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1421 1422 return cpu_to_le32(dword); 1423 } 1424 1425 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1426 { 1427 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) | 1428 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) | 1429 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1430 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1431 1432 return cpu_to_le32(dword); 1433 } 1434 1435 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1436 { 1437 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1438 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1439 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1440 desc_info->data_retry_lowest_rate); 1441 1442 return cpu_to_le32(dword); 1443 } 1444 1445 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1446 { 1447 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1448 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1449 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1450 1451 return cpu_to_le32(dword); 1452 } 1453 1454 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1455 { 1456 bool rts_en = !desc_info->is_bmc; 1457 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1458 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1459 1460 return cpu_to_le32(dword); 1461 } 1462 1463 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1464 struct rtw89_tx_desc_info *desc_info, 1465 void *txdesc) 1466 { 1467 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1468 struct rtw89_txwd_info_v2 *txwd_info; 1469 1470 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1471 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1472 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1473 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1474 if (desc_info->sec_en) { 1475 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1476 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1477 } 1478 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info); 1479 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1480 1481 if (!desc_info->en_wd_info) 1482 return; 1483 1484 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1485 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1486 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1487 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1488 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1489 } 1490 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1491 1492 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1493 { 1494 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1495 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1496 RTW89_CORE_RX_TYPE_FWDL : 1497 RTW89_CORE_RX_TYPE_H2C); 1498 1499 return cpu_to_le32(dword); 1500 } 1501 1502 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1503 struct rtw89_tx_desc_info *desc_info, 1504 void *txdesc) 1505 { 1506 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1507 1508 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1509 } 1510 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1511 1512 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1513 { 1514 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1515 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1516 RTW89_CORE_RX_TYPE_FWDL : 1517 RTW89_CORE_RX_TYPE_H2C); 1518 1519 return cpu_to_le32(dword); 1520 } 1521 1522 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1523 struct rtw89_tx_desc_info *desc_info, 1524 void *txdesc) 1525 { 1526 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1527 1528 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1529 } 1530 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1531 1532 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1533 struct sk_buff *skb, 1534 struct rtw89_rx_phy_ppdu *phy_ppdu) 1535 { 1536 const struct rtw89_chip_info *chip = rtwdev->chip; 1537 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1538 const struct rtw89_rxinfo_user *user; 1539 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1540 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1541 bool rx_cnt_valid = false; 1542 bool invalid = false; 1543 u8 plcp_size = 0; 1544 u8 *phy_sts; 1545 u8 usr_num; 1546 int i; 1547 1548 if (chip_gen == RTW89_CHIP_BE) { 1549 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1550 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1551 } 1552 1553 if (invalid) 1554 return -EINVAL; 1555 1556 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1557 if (chip_gen == RTW89_CHIP_BE) { 1558 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1559 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1560 } else { 1561 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1562 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1563 } 1564 if (usr_num > chip->ppdu_max_usr) { 1565 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1566 usr_num); 1567 return -EINVAL; 1568 } 1569 1570 for (i = 0; i < usr_num; i++) { 1571 user = &rxinfo->user[i]; 1572 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1573 continue; 1574 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set 1575 * by hardware, so update mac_id by rxinfo_user[].mac_id. 1576 */ 1577 if (chip_gen == RTW89_CHIP_BE) 1578 phy_ppdu->mac_id = 1579 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1580 phy_ppdu->has_data = 1581 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA); 1582 phy_ppdu->has_bcn = 1583 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN); 1584 break; 1585 } 1586 1587 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1588 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1589 /* 8-byte alignment */ 1590 if (usr_num & BIT(0)) 1591 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1592 if (rx_cnt_valid) 1593 phy_sts += rx_cnt_size; 1594 phy_sts += plcp_size; 1595 1596 if (phy_sts > skb->data + skb->len) 1597 return -EINVAL; 1598 1599 phy_ppdu->buf = phy_sts; 1600 phy_ppdu->len = skb->data + skb->len - phy_sts; 1601 1602 return 0; 1603 } 1604 1605 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate) 1606 { 1607 u8 data_rate_mode; 1608 1609 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1610 switch (data_rate_mode) { 1611 case DATA_RATE_MODE_NON_HT: 1612 return 1; 1613 case DATA_RATE_MODE_HT: 1614 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1; 1615 case DATA_RATE_MODE_VHT: 1616 case DATA_RATE_MODE_HE: 1617 case DATA_RATE_MODE_EHT: 1618 return rtw89_get_data_nss(rtwdev, data_rate) + 1; 1619 default: 1620 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1621 return 0; 1622 } 1623 } 1624 1625 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1626 struct ieee80211_sta *sta) 1627 { 1628 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1629 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 1630 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1631 struct rtw89_hal *hal = &rtwdev->hal; 1632 struct rtw89_sta_link *rtwsta_link; 1633 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1634 u8 ant_pos = U8_MAX; 1635 u8 evm_pos = 0; 1636 int i; 1637 1638 /* FIXME: For single link, taking link on HW-0 here is okay. But, when 1639 * enabling multiple active links, we should determine the right link. 1640 */ 1641 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0); 1642 if (unlikely(!rtwsta_link)) 1643 return; 1644 1645 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1646 return; 1647 1648 if (hal->ant_diversity && hal->antenna_rx) { 1649 ant_pos = __ffs(hal->antenna_rx); 1650 evm_pos = ant_pos; 1651 } 1652 1653 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg); 1654 1655 if (ant_pos < ant_num) { 1656 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]); 1657 } else { 1658 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1659 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]); 1660 } 1661 1662 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) { 1663 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr); 1664 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) { 1665 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min); 1666 } else { 1667 ewma_evm_add(&rtwsta_link->evm_min[evm_pos], 1668 phy_ppdu->ofdm.evm_min); 1669 ewma_evm_add(&rtwsta_link->evm_max[evm_pos], 1670 phy_ppdu->ofdm.evm_max); 1671 } 1672 } 1673 } 1674 1675 #define VAR_LEN 0xff 1676 #define VAR_LEN_UNIT 8 1677 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1678 const struct rtw89_phy_sts_iehdr *iehdr) 1679 { 1680 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1681 [RTW89_CHIP_AX] = { 1682 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1683 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1684 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1685 }, 1686 [RTW89_CHIP_BE] = { 1687 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1688 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1689 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1690 }, 1691 }; 1692 const u8 *physts_ie_len_tab; 1693 u16 ie_len; 1694 u8 ie; 1695 1696 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1697 1698 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1699 if (physts_ie_len_tab[ie] != VAR_LEN) 1700 ie_len = physts_ie_len_tab[ie]; 1701 else 1702 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1703 1704 return ie_len; 1705 } 1706 1707 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev, 1708 const struct rtw89_phy_sts_iehdr *iehdr, 1709 struct rtw89_rx_phy_ppdu *phy_ppdu) 1710 { 1711 const struct rtw89_phy_sts_ie01_v2 *ie; 1712 u8 *rpl_fd = phy_ppdu->rpl_fd; 1713 1714 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr; 1715 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A); 1716 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B); 1717 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C); 1718 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D); 1719 1720 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX); 1721 } 1722 1723 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1724 const struct rtw89_phy_sts_iehdr *iehdr, 1725 struct rtw89_rx_phy_ppdu *phy_ppdu) 1726 { 1727 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr; 1728 s16 cfo; 1729 u32 t; 1730 1731 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1732 1733 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) { 1734 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC); 1735 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC); 1736 } 1737 1738 if (!phy_ppdu->hdr_2_en) 1739 phy_ppdu->rx_path_en = 1740 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN); 1741 1742 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1743 return; 1744 1745 if (!phy_ppdu->to_self) 1746 return; 1747 1748 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD); 1749 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1750 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1751 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1752 phy_ppdu->ofdm.has = true; 1753 1754 /* sign conversion for S(12,2) */ 1755 if (rtwdev->chip->cfo_src_fd) { 1756 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1757 cfo = sign_extend32(t, 11); 1758 } else { 1759 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1760 cfo = sign_extend32(t, 11); 1761 } 1762 1763 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1764 1765 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1766 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu); 1767 } 1768 1769 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev, 1770 const struct rtw89_phy_sts_iehdr *iehdr, 1771 struct rtw89_rx_phy_ppdu *phy_ppdu) 1772 { 1773 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr; 1774 u16 tmp_rpl; 1775 1776 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL); 1777 phy_ppdu->rpl_avg = tmp_rpl >> 1; 1778 } 1779 1780 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev, 1781 const struct rtw89_phy_sts_iehdr *iehdr, 1782 struct rtw89_rx_phy_ppdu *phy_ppdu) 1783 { 1784 const struct rtw89_phy_sts_ie00_v2 *ie; 1785 u8 *rpl_path = phy_ppdu->rpl_path; 1786 u16 tmp_rpl[RF_PATH_MAX]; 1787 u8 i; 1788 1789 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr; 1790 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A); 1791 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B); 1792 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C); 1793 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D); 1794 1795 for (i = 0; i < RF_PATH_MAX; i++) 1796 rpl_path[i] = tmp_rpl[i] >> 1; 1797 } 1798 1799 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1800 const struct rtw89_phy_sts_iehdr *iehdr, 1801 struct rtw89_rx_phy_ppdu *phy_ppdu) 1802 { 1803 u8 ie; 1804 1805 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1806 1807 switch (ie) { 1808 case RTW89_PHYSTS_IE00_CMN_CCK: 1809 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu); 1810 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1811 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu); 1812 break; 1813 case RTW89_PHYSTS_IE01_CMN_OFDM: 1814 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1815 break; 1816 default: 1817 break; 1818 } 1819 1820 return 0; 1821 } 1822 1823 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu) 1824 { 1825 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN; 1826 1827 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN); 1828 } 1829 1830 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1831 { 1832 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1833 u8 *rssi = phy_ppdu->rssi; 1834 1835 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1836 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1837 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1838 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1839 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1840 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1841 1842 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN); 1843 if (phy_ppdu->hdr_2_en) 1844 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu); 1845 } 1846 1847 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1848 struct rtw89_rx_phy_ppdu *phy_ppdu) 1849 { 1850 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1851 u32 len_from_header; 1852 bool physts_valid; 1853 1854 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1855 if (!physts_valid) 1856 return -EINVAL; 1857 1858 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1859 1860 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1861 len_from_header += PHY_STS_HDR_LEN; 1862 1863 if (len_from_header != phy_ppdu->len) { 1864 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1865 return -EINVAL; 1866 } 1867 rtw89_core_update_phy_ppdu(phy_ppdu); 1868 1869 return 0; 1870 } 1871 1872 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1873 struct rtw89_rx_phy_ppdu *phy_ppdu) 1874 { 1875 u16 ie_len; 1876 void *pos, *end; 1877 1878 /* mark invalid reports and bypass them */ 1879 if (phy_ppdu->ie < RTW89_CCK_PKT) 1880 return -EINVAL; 1881 1882 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1883 end = phy_ppdu->buf + phy_ppdu->len; 1884 while (pos < end) { 1885 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1886 1887 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1888 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1889 pos += ie_len; 1890 if (pos > end || ie_len == 0) { 1891 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1892 "phy status parse failed\n"); 1893 return -EINVAL; 1894 } 1895 } 1896 1897 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu); 1898 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1899 1900 return 0; 1901 } 1902 1903 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1904 struct rtw89_rx_phy_ppdu *phy_ppdu) 1905 { 1906 int ret; 1907 1908 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1909 if (ret) 1910 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1911 else 1912 phy_ppdu->valid = true; 1913 1914 ieee80211_iterate_stations_atomic(rtwdev->hw, 1915 rtw89_core_rx_process_phy_ppdu_iter, 1916 phy_ppdu); 1917 } 1918 1919 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev, 1920 u8 desc_info_gi, 1921 bool rx_status) 1922 { 1923 switch (desc_info_gi) { 1924 case RTW89_GILTF_SGI_4XHE08: 1925 case RTW89_GILTF_2XHE08: 1926 case RTW89_GILTF_1XHE08: 1927 return NL80211_RATE_INFO_HE_GI_0_8; 1928 case RTW89_GILTF_2XHE16: 1929 case RTW89_GILTF_1XHE16: 1930 return NL80211_RATE_INFO_HE_GI_1_6; 1931 case RTW89_GILTF_LGI_4XHE32: 1932 return NL80211_RATE_INFO_HE_GI_3_2; 1933 default: 1934 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1935 if (rx_status) 1936 return NL80211_RATE_INFO_HE_GI_3_2; 1937 return U8_MAX; 1938 } 1939 } 1940 1941 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev, 1942 u8 desc_info_gi, 1943 bool rx_status) 1944 { 1945 switch (desc_info_gi) { 1946 case RTW89_GILTF_SGI_4XHE08: 1947 case RTW89_GILTF_2XHE08: 1948 case RTW89_GILTF_1XHE08: 1949 return NL80211_RATE_INFO_EHT_GI_0_8; 1950 case RTW89_GILTF_2XHE16: 1951 case RTW89_GILTF_1XHE16: 1952 return NL80211_RATE_INFO_EHT_GI_1_6; 1953 case RTW89_GILTF_LGI_4XHE32: 1954 return NL80211_RATE_INFO_EHT_GI_3_2; 1955 default: 1956 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1957 if (rx_status) 1958 return NL80211_RATE_INFO_EHT_GI_3_2; 1959 return U8_MAX; 1960 } 1961 } 1962 1963 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 1964 u8 desc_info_gi, 1965 bool rx_status, bool eht) 1966 { 1967 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) : 1968 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status); 1969 } 1970 1971 static 1972 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 1973 bool eht) 1974 { 1975 if (eht) 1976 return status->eht.gi == gi_ltf; 1977 1978 return status->he_gi == gi_ltf; 1979 } 1980 1981 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1982 struct rtw89_rx_desc_info *desc_info, 1983 struct ieee80211_rx_status *status) 1984 { 1985 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1986 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1987 bool eht = false; 1988 u16 data_rate; 1989 bool ret; 1990 1991 data_rate = desc_info->data_rate; 1992 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1993 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1994 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1995 /* rate_idx is still hardware value here */ 1996 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1997 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1998 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 1999 data_rate_mode == DATA_RATE_MODE_HE || 2000 data_rate_mode == DATA_RATE_MODE_EHT) { 2001 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2002 } else { 2003 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2004 } 2005 2006 eht = data_rate_mode == DATA_RATE_MODE_EHT; 2007 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2008 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 2009 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 2010 status->rate_idx == rate_idx && 2011 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 2012 status->bw == bw; 2013 2014 return ret; 2015 } 2016 2017 struct rtw89_vif_rx_stats_iter_data { 2018 struct rtw89_dev *rtwdev; 2019 struct rtw89_rx_phy_ppdu *phy_ppdu; 2020 struct rtw89_rx_desc_info *desc_info; 2021 struct sk_buff *skb; 2022 const u8 *bssid; 2023 }; 2024 2025 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 2026 struct rtw89_vif_link *rtwvif_link, 2027 struct ieee80211_bss_conf *bss_conf, 2028 struct sk_buff *skb) 2029 { 2030 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 2031 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 2032 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 2033 u8 *pos, *end, type, tf_bw; 2034 u16 aid, tf_rua; 2035 2036 if (!ether_addr_equal(bss_conf->bssid, tf->ta) || 2037 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION || 2038 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK) 2039 return; 2040 2041 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 2042 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 2043 return; 2044 2045 end = (u8 *)tf + skb->len; 2046 pos = tf->variable; 2047 2048 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 2049 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 2050 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 2051 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 2052 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2053 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 2054 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 2055 tf_rua, tf_bw); 2056 2057 if (aid == RTW89_TF_PAD) 2058 break; 2059 2060 if (aid == vif->cfg.aid) { 2061 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 2062 2063 rtwvif->stats.rx_tf_acc++; 2064 rtwdev->stats.rx_tf_acc++; 2065 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 2066 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 2067 rtwvif_link->pwr_diff_en = true; 2068 break; 2069 } 2070 2071 pos += RTW89_TF_BASIC_USER_INFO_SZ; 2072 } 2073 } 2074 2075 static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work) 2076 { 2077 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2078 cancel_6ghz_probe_work); 2079 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2080 struct rtw89_pktofld_info *info; 2081 2082 lockdep_assert_wiphy(wiphy); 2083 2084 if (!rtwdev->scanning) 2085 return; 2086 2087 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2088 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 2089 continue; 2090 2091 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 2092 2093 /* Don't delete/free info from pkt_list at this moment. Let it 2094 * be deleted/freed in rtw89_release_pkt_list() after scanning, 2095 * since if during scanning, pkt_list is accessed in bottom half. 2096 */ 2097 } 2098 } 2099 2100 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 2101 struct sk_buff *skb) 2102 { 2103 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 2104 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 2105 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 2106 struct rtw89_pktofld_info *info; 2107 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 2108 bool queue_work = false; 2109 2110 if (rx_status->band != NL80211_BAND_6GHZ) 2111 return; 2112 2113 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 2114 2115 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 2116 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 2117 info->cancel = true; 2118 queue_work = true; 2119 continue; 2120 } 2121 2122 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 2123 continue; 2124 2125 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 2126 info->cancel = true; 2127 queue_work = true; 2128 } 2129 } 2130 2131 if (queue_work) 2132 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work); 2133 } 2134 2135 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link, 2136 struct ieee80211_hdr *hdr, size_t len) 2137 { 2138 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 2139 2140 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 2141 return; 2142 2143 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 2144 } 2145 2146 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 2147 struct ieee80211_vif *vif) 2148 { 2149 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 2150 struct rtw89_dev *rtwdev = iter_data->rtwdev; 2151 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif); 2152 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 2153 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2154 struct sk_buff *skb = iter_data->skb; 2155 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2156 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 2157 struct ieee80211_bss_conf *bss_conf; 2158 struct rtw89_vif_link *rtwvif_link; 2159 const u8 *bssid = iter_data->bssid; 2160 2161 if (rtwdev->scanning && 2162 (ieee80211_is_beacon(hdr->frame_control) || 2163 ieee80211_is_probe_resp(hdr->frame_control))) 2164 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 2165 2166 rcu_read_lock(); 2167 2168 /* FIXME: For single link, taking link on HW-0 here is okay. But, when 2169 * enabling multiple active links, we should determine the right link. 2170 */ 2171 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, 0); 2172 if (unlikely(!rtwvif_link)) 2173 goto out; 2174 2175 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 2176 if (!bss_conf->bssid) 2177 goto out; 2178 2179 if (ieee80211_is_trigger(hdr->frame_control)) { 2180 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb); 2181 goto out; 2182 } 2183 2184 if (!ether_addr_equal(bss_conf->bssid, bssid)) 2185 goto out; 2186 2187 if (ieee80211_is_beacon(hdr->frame_control)) { 2188 if (vif->type == NL80211_IFTYPE_STATION && 2189 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) { 2190 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len); 2191 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 2192 } 2193 pkt_stat->beacon_nr++; 2194 2195 if (phy_ppdu) { 2196 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg); 2197 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 2198 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx; 2199 } 2200 2201 pkt_stat->beacon_rate = desc_info->data_rate; 2202 } 2203 2204 if (!ether_addr_equal(bss_conf->addr, hdr->addr1)) 2205 goto out; 2206 2207 if (desc_info->data_rate < RTW89_HW_RATE_NR) 2208 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 2209 2210 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 2211 2212 out: 2213 rcu_read_unlock(); 2214 } 2215 2216 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 2217 struct rtw89_rx_phy_ppdu *phy_ppdu, 2218 struct rtw89_rx_desc_info *desc_info, 2219 struct sk_buff *skb) 2220 { 2221 struct rtw89_vif_rx_stats_iter_data iter_data; 2222 2223 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 2224 2225 iter_data.rtwdev = rtwdev; 2226 iter_data.phy_ppdu = phy_ppdu; 2227 iter_data.desc_info = desc_info; 2228 iter_data.skb = skb; 2229 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 2230 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 2231 } 2232 2233 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 2234 struct ieee80211_rx_status *status) 2235 { 2236 const struct rtw89_chan_rcd *rcd = 2237 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0); 2238 u16 chan = rcd->prev_primary_channel; 2239 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 2240 2241 if (status->band != NL80211_BAND_2GHZ && 2242 status->encoding == RX_ENC_LEGACY && 2243 status->rate_idx < RTW89_HW_RATE_OFDM6) { 2244 status->freq = ieee80211_channel_to_frequency(chan, band); 2245 status->band = band; 2246 } 2247 } 2248 2249 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 2250 { 2251 if (rx_status->band == NL80211_BAND_2GHZ || 2252 rx_status->encoding != RX_ENC_LEGACY) 2253 return; 2254 2255 /* Some control frames' freq(ACKs in this case) are reported wrong due 2256 * to FW notify timing, set to lowest rate to prevent overflow. 2257 */ 2258 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 2259 rx_status->rate_idx = 0; 2260 return; 2261 } 2262 2263 /* No 4 CCK rates for non-2G */ 2264 rx_status->rate_idx -= 4; 2265 } 2266 2267 static 2268 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev, 2269 struct ieee80211_rx_status *rx_status, 2270 struct rtw89_rx_phy_ppdu *phy_ppdu) 2271 { 2272 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2273 return; 2274 2275 if (!phy_ppdu) 2276 return; 2277 2278 if (phy_ppdu->ldpc) 2279 rx_status->enc_flags |= RX_ENC_FLAG_LDPC; 2280 if (phy_ppdu->stbc) 2281 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK); 2282 } 2283 2284 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 2285 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 2286 [RATE_INFO_BW_5] = U8_MAX, 2287 [RATE_INFO_BW_10] = U8_MAX, 2288 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 2289 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 2290 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 2291 [RATE_INFO_BW_HE_RU] = U8_MAX, 2292 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 2293 [RATE_INFO_BW_EHT_RU] = U8_MAX, 2294 }; 2295 2296 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2297 struct sk_buff *skb, 2298 struct ieee80211_rx_status *rx_status) 2299 { 2300 struct ieee80211_radiotap_eht_usig *usig; 2301 struct ieee80211_radiotap_eht *eht; 2302 struct ieee80211_radiotap_tlv *tlv; 2303 int eht_len = struct_size(eht, user_info, 1); 2304 int usig_len = sizeof(*usig); 2305 int len; 2306 u8 bw; 2307 2308 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2309 sizeof(*tlv) + ALIGN(usig_len, 4); 2310 2311 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2312 skb_reset_mac_header(skb); 2313 2314 /* EHT */ 2315 tlv = skb_push(skb, len); 2316 memset(tlv, 0, len); 2317 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2318 tlv->len = cpu_to_le16(eht_len); 2319 2320 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2321 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2322 eht->data[0] = 2323 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2324 2325 eht->user_info[0] = 2326 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2327 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O | 2328 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN); 2329 eht->user_info[0] |= 2330 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2331 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2332 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC) 2333 eht->user_info[0] |= 2334 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING); 2335 2336 /* U-SIG */ 2337 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2338 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2339 tlv->len = cpu_to_le16(usig_len); 2340 2341 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2342 return; 2343 2344 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2345 if (bw == U8_MAX) 2346 return; 2347 2348 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2349 usig->common = 2350 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2351 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2352 } 2353 2354 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2355 struct sk_buff *skb, 2356 struct ieee80211_rx_status *rx_status) 2357 { 2358 static const struct ieee80211_radiotap_he known_he = { 2359 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2360 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN | 2361 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN | 2362 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2363 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2364 }; 2365 struct ieee80211_radiotap_he *he; 2366 2367 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2368 return; 2369 2370 if (rx_status->encoding == RX_ENC_HE) { 2371 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2372 he = skb_push(skb, sizeof(*he)); 2373 *he = known_he; 2374 } else if (rx_status->encoding == RX_ENC_EHT) { 2375 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2376 } 2377 } 2378 2379 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status) 2380 { 2381 if (!rx_status->signal) 2382 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2383 } 2384 2385 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2386 struct rtw89_rx_phy_ppdu *phy_ppdu, 2387 struct rtw89_rx_desc_info *desc_info, 2388 struct sk_buff *skb_ppdu, 2389 struct ieee80211_rx_status *rx_status) 2390 { 2391 struct napi_struct *napi = &rtwdev->napi; 2392 2393 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2394 if (unlikely(!napi_is_scheduled(napi))) 2395 napi = NULL; 2396 2397 rtw89_core_hw_to_sband_rate(rx_status); 2398 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2399 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu); 2400 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2401 rtw89_core_validate_rx_signal(rx_status); 2402 2403 /* In low power mode, it does RX in thread context. */ 2404 local_bh_disable(); 2405 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2406 local_bh_enable(); 2407 rtwdev->napi_budget_countdown--; 2408 } 2409 2410 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2411 struct rtw89_rx_phy_ppdu *phy_ppdu, 2412 struct rtw89_rx_desc_info *desc_info, 2413 struct sk_buff *skb) 2414 { 2415 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2416 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2417 struct sk_buff *skb_ppdu = NULL, *tmp; 2418 struct ieee80211_rx_status *rx_status; 2419 2420 if (curr > RTW89_MAX_PPDU_CNT) 2421 return; 2422 2423 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2424 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2425 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2426 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2427 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2428 rtw89_correct_cck_chan(rtwdev, rx_status); 2429 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2430 } 2431 } 2432 2433 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2434 struct rtw89_rx_desc_info *desc_info, 2435 struct sk_buff *skb) 2436 { 2437 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2438 .len = skb->len, 2439 .to_self = desc_info->addr1_match, 2440 .rate = desc_info->data_rate, 2441 .mac_id = desc_info->mac_id}; 2442 int ret; 2443 2444 if (desc_info->mac_info_valid) { 2445 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2446 if (ret) 2447 goto out; 2448 } 2449 2450 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2451 if (ret) 2452 goto out; 2453 2454 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2455 2456 out: 2457 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2458 dev_kfree_skb_any(skb); 2459 } 2460 2461 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2462 struct rtw89_rx_desc_info *desc_info, 2463 struct sk_buff *skb) 2464 { 2465 switch (desc_info->pkt_type) { 2466 case RTW89_CORE_RX_TYPE_C2H: 2467 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2468 break; 2469 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2470 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2471 break; 2472 default: 2473 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2474 desc_info->pkt_type); 2475 dev_kfree_skb_any(skb); 2476 break; 2477 } 2478 } 2479 2480 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2481 struct rtw89_rx_desc_info *desc_info, 2482 u8 *data, u32 data_offset) 2483 { 2484 const struct rtw89_chip_info *chip = rtwdev->chip; 2485 struct rtw89_rxdesc_short *rxd_s; 2486 struct rtw89_rxdesc_long *rxd_l; 2487 u8 shift_len, drv_info_len; 2488 2489 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2490 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2491 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2492 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2493 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2494 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2495 if (chip->chip_id == RTL8852C) 2496 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2497 else 2498 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2499 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2500 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2501 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2502 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2503 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2504 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2505 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2506 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2507 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2508 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2509 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2510 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2511 2512 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2513 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2514 desc_info->offset = data_offset + shift_len + drv_info_len; 2515 if (desc_info->long_rxdesc) 2516 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2517 else 2518 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2519 desc_info->ready = true; 2520 2521 if (!desc_info->long_rxdesc) 2522 return; 2523 2524 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2525 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2526 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2527 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2528 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2529 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2530 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2531 } 2532 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2533 2534 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2535 struct rtw89_rx_desc_info *desc_info, 2536 u8 *data, u32 data_offset) 2537 { 2538 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt; 2539 struct rtw89_rxdesc_short_v2 *rxd_s; 2540 struct rtw89_rxdesc_long_v2 *rxd_l; 2541 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2542 2543 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2544 2545 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2546 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2547 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2548 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2549 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2550 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2551 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2552 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2553 desc_info->mac_info_valid = true; 2554 2555 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2556 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2557 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2558 2559 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2560 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2561 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2562 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2563 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2564 2565 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2566 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2567 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2568 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2569 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2570 2571 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2572 2573 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2574 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2575 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2576 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2577 desc_info->offset = data_offset + shift_len + drv_info_len + 2578 phy_rtp_len + hdr_cnv_len; 2579 2580 if (desc_info->long_rxdesc) 2581 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2582 else 2583 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2584 desc_info->ready = true; 2585 2586 if (phy_rtp_len == sizeof(*rxd_rpt)) { 2587 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset + 2588 desc_info->rxd_len); 2589 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI); 2590 } 2591 2592 if (!desc_info->long_rxdesc) 2593 return; 2594 2595 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2596 2597 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2598 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2599 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2600 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2601 2602 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2603 } 2604 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2605 2606 struct rtw89_core_iter_rx_status { 2607 struct rtw89_dev *rtwdev; 2608 struct ieee80211_rx_status *rx_status; 2609 struct rtw89_rx_desc_info *desc_info; 2610 u8 mac_id; 2611 }; 2612 2613 static 2614 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2615 { 2616 struct rtw89_core_iter_rx_status *iter_data = 2617 (struct rtw89_core_iter_rx_status *)data; 2618 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2619 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2620 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 2621 struct rtw89_sta_link *rtwsta_link; 2622 u8 mac_id = iter_data->mac_id; 2623 2624 /* FIXME: For single link, taking link on HW-0 here is okay. But, when 2625 * enabling multiple active links, we should determine the right link. 2626 */ 2627 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0); 2628 if (unlikely(!rtwsta_link)) 2629 return; 2630 2631 if (mac_id != rtwsta_link->mac_id) 2632 return; 2633 2634 rtwsta_link->rx_status = *rx_status; 2635 rtwsta_link->rx_hw_rate = desc_info->data_rate; 2636 } 2637 2638 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2639 struct rtw89_rx_desc_info *desc_info, 2640 struct ieee80211_rx_status *rx_status) 2641 { 2642 struct rtw89_core_iter_rx_status iter_data; 2643 2644 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2645 return; 2646 2647 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2648 return; 2649 2650 iter_data.rtwdev = rtwdev; 2651 iter_data.rx_status = rx_status; 2652 iter_data.desc_info = desc_info; 2653 iter_data.mac_id = desc_info->mac_id; 2654 ieee80211_iterate_stations_atomic(rtwdev->hw, 2655 rtw89_core_stats_sta_rx_status_iter, 2656 &iter_data); 2657 } 2658 2659 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2660 struct rtw89_rx_desc_info *desc_info, 2661 struct ieee80211_rx_status *rx_status) 2662 { 2663 const struct cfg80211_chan_def *chandef = 2664 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0); 2665 u16 data_rate; 2666 u8 data_rate_mode; 2667 bool eht = false; 2668 u8 gi; 2669 2670 /* currently using single PHY */ 2671 rx_status->freq = chandef->chan->center_freq; 2672 rx_status->band = chandef->chan->band; 2673 2674 if (rtwdev->scanning && 2675 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2676 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2677 u8 chan = cur->primary_channel; 2678 u8 band = cur->band_type; 2679 enum nl80211_band nl_band; 2680 2681 nl_band = rtw89_hw_to_nl80211_band(band); 2682 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2683 rx_status->band = nl_band; 2684 } 2685 2686 if (desc_info->icv_err || desc_info->crc32_err) 2687 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2688 2689 if (desc_info->hw_dec && 2690 !(desc_info->sw_dec || desc_info->icv_err)) 2691 rx_status->flag |= RX_FLAG_DECRYPTED; 2692 2693 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2694 2695 data_rate = desc_info->data_rate; 2696 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2697 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2698 rx_status->encoding = RX_ENC_LEGACY; 2699 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2700 /* convert rate_idx after we get the correct band */ 2701 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2702 rx_status->encoding = RX_ENC_HT; 2703 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2704 if (desc_info->gi_ltf) 2705 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2706 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2707 rx_status->encoding = RX_ENC_VHT; 2708 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2709 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2710 if (desc_info->gi_ltf) 2711 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2712 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2713 rx_status->encoding = RX_ENC_HE; 2714 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2715 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2716 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2717 rx_status->encoding = RX_ENC_EHT; 2718 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2719 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2720 eht = true; 2721 } else { 2722 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2723 } 2724 2725 /* he_gi is used to match ppdu, so we always fill it. */ 2726 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2727 if (eht) 2728 rx_status->eht.gi = gi; 2729 else 2730 rx_status->he_gi = gi; 2731 rx_status->flag |= RX_FLAG_MACTIME_START; 2732 rx_status->mactime = desc_info->free_run_cnt; 2733 2734 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status); 2735 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2736 } 2737 2738 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2739 { 2740 const struct rtw89_chip_info *chip = rtwdev->chip; 2741 2742 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2743 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2744 return RTW89_PS_MODE_NONE; 2745 2746 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2747 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2748 return RTW89_PS_MODE_PWR_GATED; 2749 2750 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2751 return RTW89_PS_MODE_CLK_GATED; 2752 2753 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2754 return RTW89_PS_MODE_RFOFF; 2755 2756 return RTW89_PS_MODE_NONE; 2757 } 2758 2759 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2760 struct rtw89_rx_desc_info *desc_info) 2761 { 2762 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2763 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2764 struct ieee80211_rx_status *rx_status; 2765 struct sk_buff *skb_ppdu, *tmp; 2766 2767 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2768 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2769 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2770 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2771 } 2772 } 2773 2774 static 2775 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb, 2776 const struct rtw89_rx_desc_info *desc) 2777 { 2778 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2779 struct rtw89_sta_link *rtwsta_link; 2780 struct ieee80211_sta *sta; 2781 struct rtw89_sta *rtwsta; 2782 u8 macid = desc->mac_id; 2783 2784 if (!refcount_read(&rtwdev->refcount_ap_info)) 2785 return; 2786 2787 rcu_read_lock(); 2788 2789 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid); 2790 if (!rtwsta_link) 2791 goto out; 2792 2793 rtwsta = rtwsta_link->rtwsta; 2794 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags)) 2795 goto out; 2796 2797 sta = rtwsta_to_sta(rtwsta); 2798 if (ieee80211_is_pspoll(hdr->frame_control)) 2799 ieee80211_sta_pspoll(sta); 2800 else if (ieee80211_has_pm(hdr->frame_control) && 2801 (ieee80211_is_data_qos(hdr->frame_control) || 2802 ieee80211_is_qos_nullfunc(hdr->frame_control))) 2803 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr)); 2804 2805 out: 2806 rcu_read_unlock(); 2807 } 2808 2809 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2810 struct rtw89_rx_desc_info *desc_info, 2811 struct sk_buff *skb) 2812 { 2813 struct ieee80211_rx_status *rx_status; 2814 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2815 u8 ppdu_cnt = desc_info->ppdu_cnt; 2816 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2817 2818 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2819 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2820 return; 2821 } 2822 2823 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2824 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2825 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2826 } 2827 2828 rx_status = IEEE80211_SKB_RXCB(skb); 2829 memset(rx_status, 0, sizeof(*rx_status)); 2830 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2831 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info); 2832 if (desc_info->long_rxdesc && 2833 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2834 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2835 else 2836 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2837 } 2838 EXPORT_SYMBOL(rtw89_core_rx); 2839 2840 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2841 { 2842 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2843 return; 2844 2845 napi_enable(&rtwdev->napi); 2846 } 2847 EXPORT_SYMBOL(rtw89_core_napi_start); 2848 2849 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2850 { 2851 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2852 return; 2853 2854 napi_synchronize(&rtwdev->napi); 2855 napi_disable(&rtwdev->napi); 2856 } 2857 EXPORT_SYMBOL(rtw89_core_napi_stop); 2858 2859 int rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2860 { 2861 rtwdev->netdev = alloc_netdev_dummy(0); 2862 if (!rtwdev->netdev) 2863 return -ENOMEM; 2864 2865 netif_napi_add(rtwdev->netdev, &rtwdev->napi, 2866 rtwdev->hci.ops->napi_poll); 2867 return 0; 2868 } 2869 EXPORT_SYMBOL(rtw89_core_napi_init); 2870 2871 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2872 { 2873 rtw89_core_napi_stop(rtwdev); 2874 netif_napi_del(&rtwdev->napi); 2875 free_netdev(rtwdev->netdev); 2876 } 2877 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2878 2879 static void rtw89_core_ba_work(struct work_struct *work) 2880 { 2881 struct rtw89_dev *rtwdev = 2882 container_of(work, struct rtw89_dev, ba_work); 2883 struct rtw89_txq *rtwtxq, *tmp; 2884 int ret; 2885 2886 spin_lock_bh(&rtwdev->ba_lock); 2887 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2888 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2889 struct ieee80211_sta *sta = txq->sta; 2890 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2891 u8 tid = txq->tid; 2892 2893 if (!sta) { 2894 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2895 goto skip_ba_work; 2896 } 2897 2898 if (rtwsta->disassoc) { 2899 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2900 "cannot start BA with disassoc sta\n"); 2901 goto skip_ba_work; 2902 } 2903 2904 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2905 if (ret) { 2906 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2907 "failed to setup BA session for %pM:%2d: %d\n", 2908 sta->addr, tid, ret); 2909 if (ret == -EINVAL) 2910 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2911 } 2912 skip_ba_work: 2913 list_del_init(&rtwtxq->list); 2914 } 2915 spin_unlock_bh(&rtwdev->ba_lock); 2916 } 2917 2918 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2919 struct ieee80211_sta *sta) 2920 { 2921 struct rtw89_txq *rtwtxq, *tmp; 2922 2923 spin_lock_bh(&rtwdev->ba_lock); 2924 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2925 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2926 2927 if (sta == txq->sta) 2928 list_del_init(&rtwtxq->list); 2929 } 2930 spin_unlock_bh(&rtwdev->ba_lock); 2931 } 2932 2933 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2934 struct ieee80211_sta *sta) 2935 { 2936 struct rtw89_txq *rtwtxq, *tmp; 2937 2938 spin_lock_bh(&rtwdev->ba_lock); 2939 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2940 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2941 2942 if (sta == txq->sta) { 2943 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2944 list_del_init(&rtwtxq->list); 2945 } 2946 } 2947 spin_unlock_bh(&rtwdev->ba_lock); 2948 } 2949 2950 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2951 struct ieee80211_sta *sta) 2952 { 2953 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 2954 struct sk_buff *skb, *tmp; 2955 2956 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2957 skb_unlink(skb, &rtwsta->roc_queue); 2958 dev_kfree_skb_any(skb); 2959 } 2960 } 2961 2962 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2963 struct rtw89_txq *rtwtxq) 2964 { 2965 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2966 struct ieee80211_sta *sta = txq->sta; 2967 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2968 2969 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2970 return; 2971 2972 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2973 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2974 return; 2975 2976 spin_lock_bh(&rtwdev->ba_lock); 2977 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2978 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2979 spin_unlock_bh(&rtwdev->ba_lock); 2980 2981 ieee80211_stop_tx_ba_session(sta, txq->tid); 2982 cancel_delayed_work(&rtwdev->forbid_ba_work); 2983 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2984 RTW89_FORBID_BA_TIMER); 2985 } 2986 2987 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2988 struct rtw89_txq *rtwtxq, 2989 struct sk_buff *skb) 2990 { 2991 struct ieee80211_hw *hw = rtwdev->hw; 2992 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2993 struct ieee80211_sta *sta = txq->sta; 2994 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2995 2996 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2997 return; 2998 2999 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 3000 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 3001 return; 3002 } 3003 3004 if (unlikely(!sta)) 3005 return; 3006 3007 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 3008 return; 3009 3010 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 3011 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 3012 return; 3013 } 3014 3015 spin_lock_bh(&rtwdev->ba_lock); 3016 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 3017 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 3018 ieee80211_queue_work(hw, &rtwdev->ba_work); 3019 } 3020 spin_unlock_bh(&rtwdev->ba_lock); 3021 } 3022 3023 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 3024 struct rtw89_txq *rtwtxq, 3025 unsigned long frame_cnt, 3026 unsigned long byte_cnt) 3027 { 3028 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 3029 struct ieee80211_vif *vif = txq->vif; 3030 struct ieee80211_sta *sta = txq->sta; 3031 struct sk_buff *skb; 3032 unsigned long i; 3033 int ret; 3034 3035 rcu_read_lock(); 3036 for (i = 0; i < frame_cnt; i++) { 3037 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 3038 if (!skb) { 3039 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 3040 goto out; 3041 } 3042 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 3043 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 3044 if (ret) { 3045 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 3046 ieee80211_free_txskb(rtwdev->hw, skb); 3047 break; 3048 } 3049 } 3050 out: 3051 rcu_read_unlock(); 3052 } 3053 3054 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 3055 { 3056 u8 qsel, ch_dma; 3057 3058 qsel = rtw89_core_get_qsel(rtwdev, tid); 3059 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 3060 3061 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 3062 } 3063 3064 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 3065 struct ieee80211_txq *txq, 3066 unsigned long *frame_cnt, 3067 bool *sched_txq, bool *reinvoke) 3068 { 3069 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3070 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta); 3071 struct rtw89_sta_link *rtwsta_link; 3072 3073 if (!rtwsta) 3074 return false; 3075 3076 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, 0); 3077 if (unlikely(!rtwsta_link)) { 3078 rtw89_err(rtwdev, "agg wait: find no link on HW-0\n"); 3079 return false; 3080 } 3081 3082 if (rtwsta_link->max_agg_wait <= 0) 3083 return false; 3084 3085 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 3086 return false; 3087 3088 if (*frame_cnt > 1) { 3089 *frame_cnt -= 1; 3090 *sched_txq = true; 3091 *reinvoke = true; 3092 rtwtxq->wait_cnt = 1; 3093 return false; 3094 } 3095 3096 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) { 3097 *reinvoke = true; 3098 rtwtxq->wait_cnt++; 3099 return true; 3100 } 3101 3102 rtwtxq->wait_cnt = 0; 3103 return false; 3104 } 3105 3106 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 3107 { 3108 struct ieee80211_hw *hw = rtwdev->hw; 3109 struct ieee80211_txq *txq; 3110 struct rtw89_vif *rtwvif; 3111 struct rtw89_txq *rtwtxq; 3112 unsigned long frame_cnt; 3113 unsigned long byte_cnt; 3114 u32 tx_resource; 3115 bool sched_txq; 3116 3117 ieee80211_txq_schedule_start(hw, ac); 3118 while ((txq = ieee80211_next_txq(hw, ac))) { 3119 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3120 rtwvif = vif_to_rtwvif(txq->vif); 3121 3122 if (rtwvif->offchan) { 3123 ieee80211_return_txq(hw, txq, true); 3124 continue; 3125 } 3126 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 3127 sched_txq = false; 3128 3129 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 3130 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 3131 ieee80211_return_txq(hw, txq, true); 3132 continue; 3133 } 3134 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 3135 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 3136 ieee80211_return_txq(hw, txq, sched_txq); 3137 if (frame_cnt != 0) 3138 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 3139 3140 /* bound of tx_resource could get stuck due to burst traffic */ 3141 if (frame_cnt == tx_resource) 3142 *reinvoke = true; 3143 } 3144 ieee80211_txq_schedule_end(hw, ac); 3145 } 3146 3147 static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work) 3148 { 3149 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3150 ips_work); 3151 3152 lockdep_assert_wiphy(wiphy); 3153 3154 rtw89_enter_ips_by_hwflags(rtwdev); 3155 } 3156 3157 static void rtw89_core_txq_work(struct work_struct *w) 3158 { 3159 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 3160 bool reinvoke = false; 3161 u8 ac; 3162 3163 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 3164 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 3165 3166 if (reinvoke) { 3167 /* reinvoke to process the last frame */ 3168 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 3169 } 3170 } 3171 3172 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 3173 { 3174 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3175 txq_reinvoke_work.work); 3176 3177 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3178 } 3179 3180 static void rtw89_forbid_ba_work(struct work_struct *w) 3181 { 3182 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 3183 forbid_ba_work.work); 3184 struct rtw89_txq *rtwtxq, *tmp; 3185 3186 spin_lock_bh(&rtwdev->ba_lock); 3187 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 3188 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3189 list_del_init(&rtwtxq->list); 3190 } 3191 spin_unlock_bh(&rtwdev->ba_lock); 3192 } 3193 3194 static void rtw89_core_sta_pending_tx_iter(void *data, 3195 struct ieee80211_sta *sta) 3196 { 3197 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 3198 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 3199 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 3200 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 3201 struct rtw89_vif_link *target = data; 3202 struct rtw89_vif_link *rtwvif_link; 3203 struct sk_buff *skb, *tmp; 3204 unsigned int link_id; 3205 int qsel, ret; 3206 3207 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3208 if (rtwvif_link->chanctx_idx == target->chanctx_idx) 3209 goto bottom; 3210 3211 return; 3212 3213 bottom: 3214 if (skb_queue_len(&rtwsta->roc_queue) == 0) 3215 return; 3216 3217 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 3218 skb_unlink(skb, &rtwsta->roc_queue); 3219 3220 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 3221 if (ret) { 3222 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 3223 dev_kfree_skb_any(skb); 3224 } else { 3225 rtw89_core_tx_kick_off(rtwdev, qsel); 3226 } 3227 } 3228 } 3229 3230 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 3231 struct rtw89_vif_link *rtwvif_link) 3232 { 3233 ieee80211_iterate_stations_atomic(rtwdev->hw, 3234 rtw89_core_sta_pending_tx_iter, 3235 rtwvif_link); 3236 } 3237 3238 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 3239 struct rtw89_vif_link *rtwvif_link, bool qos, bool ps) 3240 { 3241 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3242 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1; 3243 struct ieee80211_sta *sta; 3244 struct ieee80211_hdr *hdr; 3245 struct sk_buff *skb; 3246 int ret, qsel; 3247 3248 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 3249 return 0; 3250 3251 rcu_read_lock(); 3252 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr); 3253 if (!sta) { 3254 ret = -EINVAL; 3255 goto out; 3256 } 3257 3258 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos); 3259 if (!skb) { 3260 ret = -ENOMEM; 3261 goto out; 3262 } 3263 3264 hdr = (struct ieee80211_hdr *)skb->data; 3265 if (ps) 3266 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 3267 3268 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 3269 if (ret) { 3270 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 3271 dev_kfree_skb_any(skb); 3272 goto out; 3273 } 3274 3275 rcu_read_unlock(); 3276 3277 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 3278 RTW89_ROC_TX_TIMEOUT); 3279 out: 3280 rcu_read_unlock(); 3281 3282 return ret; 3283 } 3284 3285 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3286 { 3287 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3288 struct ieee80211_hw *hw = rtwdev->hw; 3289 struct rtw89_roc *roc = &rtwvif->roc; 3290 struct rtw89_vif_link *rtwvif_link; 3291 struct cfg80211_chan_def roc_chan; 3292 struct rtw89_vif *tmp_vif; 3293 u32 reg; 3294 int ret; 3295 3296 lockdep_assert_wiphy(hw->wiphy); 3297 3298 rtw89_leave_ips_by_hwflags(rtwdev); 3299 rtw89_leave_lps(rtwdev); 3300 3301 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX); 3302 if (unlikely(!rtwvif_link)) { 3303 rtw89_err(rtwdev, "roc start: find no link on HW-%u\n", 3304 RTW89_ROC_BY_LINK_INDEX); 3305 return; 3306 } 3307 3308 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC); 3309 3310 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true); 3311 if (ret) 3312 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3313 "roc send null-1 failed: %d\n", ret); 3314 3315 rtw89_for_each_rtwvif(rtwdev, tmp_vif) { 3316 struct rtw89_vif_link *tmp_link; 3317 unsigned int link_id; 3318 3319 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) { 3320 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) { 3321 tmp_vif->offchan = true; 3322 break; 3323 } 3324 } 3325 } 3326 3327 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 3328 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, &roc_chan); 3329 rtw89_set_channel(rtwdev); 3330 3331 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3332 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 3333 3334 ieee80211_ready_on_channel(hw); 3335 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work); 3336 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work, 3337 msecs_to_jiffies(rtwvif->roc.duration)); 3338 } 3339 3340 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3341 { 3342 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3343 struct ieee80211_hw *hw = rtwdev->hw; 3344 struct rtw89_roc *roc = &rtwvif->roc; 3345 struct rtw89_vif_link *rtwvif_link; 3346 struct rtw89_vif *tmp_vif; 3347 u32 reg; 3348 int ret; 3349 3350 lockdep_assert_wiphy(hw->wiphy); 3351 3352 ieee80211_remain_on_channel_expired(hw); 3353 3354 rtw89_leave_ips_by_hwflags(rtwdev); 3355 rtw89_leave_lps(rtwdev); 3356 3357 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, RTW89_ROC_BY_LINK_INDEX); 3358 if (unlikely(!rtwvif_link)) { 3359 rtw89_err(rtwdev, "roc end: find no link on HW-%u\n", 3360 RTW89_ROC_BY_LINK_INDEX); 3361 return; 3362 } 3363 3364 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx); 3365 rtw89_write32_mask(rtwdev, reg, B_AX_RX_FLTR_CFG_MASK, rtwdev->hal.rx_fltr); 3366 3367 roc->state = RTW89_ROC_IDLE; 3368 rtw89_config_roc_chandef(rtwdev, rtwvif_link->chanctx_idx, NULL); 3369 rtw89_chanctx_proceed(rtwdev, NULL); 3370 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false); 3371 if (ret) 3372 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 3373 "roc send null-0 failed: %d\n", ret); 3374 3375 rtw89_for_each_rtwvif(rtwdev, tmp_vif) 3376 tmp_vif->offchan = false; 3377 3378 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link); 3379 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 3380 3381 if (hw->conf.flags & IEEE80211_CONF_IDLE) 3382 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work, 3383 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 3384 } 3385 3386 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work) 3387 { 3388 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 3389 roc.roc_work.work); 3390 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 3391 struct rtw89_roc *roc = &rtwvif->roc; 3392 3393 lockdep_assert_wiphy(wiphy); 3394 3395 switch (roc->state) { 3396 case RTW89_ROC_IDLE: 3397 rtw89_enter_ips_by_hwflags(rtwdev); 3398 break; 3399 case RTW89_ROC_MGMT: 3400 case RTW89_ROC_NORMAL: 3401 rtw89_roc_end(rtwdev, rtwvif); 3402 break; 3403 default: 3404 break; 3405 } 3406 } 3407 3408 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3409 u32 throughput, u64 cnt) 3410 { 3411 if (cnt < 100) 3412 return RTW89_TFC_IDLE; 3413 if (throughput > 50) 3414 return RTW89_TFC_HIGH; 3415 if (throughput > 10) 3416 return RTW89_TFC_MID; 3417 if (throughput > 2) 3418 return RTW89_TFC_LOW; 3419 return RTW89_TFC_ULTRA_LOW; 3420 } 3421 3422 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3423 struct rtw89_traffic_stats *stats) 3424 { 3425 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3426 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3427 3428 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 3429 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3430 3431 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3432 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3433 3434 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3435 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3436 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3437 stats->tx_cnt); 3438 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3439 stats->rx_cnt); 3440 stats->tx_avg_len = stats->tx_cnt ? 3441 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3442 stats->rx_avg_len = stats->rx_cnt ? 3443 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3444 3445 stats->tx_unicast = 0; 3446 stats->rx_unicast = 0; 3447 stats->tx_cnt = 0; 3448 stats->rx_cnt = 0; 3449 stats->rx_tf_periodic = stats->rx_tf_acc; 3450 stats->rx_tf_acc = 0; 3451 3452 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3453 return true; 3454 3455 return false; 3456 } 3457 3458 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3459 { 3460 struct rtw89_vif_link *rtwvif_link; 3461 struct rtw89_vif *rtwvif; 3462 unsigned int link_id; 3463 bool tfc_changed; 3464 3465 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3466 3467 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3468 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3469 3470 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) 3471 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link); 3472 } 3473 3474 return tfc_changed; 3475 } 3476 3477 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3478 { 3479 struct ieee80211_vif *vif; 3480 struct rtw89_vif *rtwvif; 3481 3482 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3483 if (rtwvif->tdls_peer) 3484 continue; 3485 if (rtwvif->offchan) 3486 continue; 3487 3488 if (rtwvif->stats.tx_tfc_lv != RTW89_TFC_IDLE || 3489 rtwvif->stats.rx_tfc_lv != RTW89_TFC_IDLE) 3490 continue; 3491 3492 vif = rtwvif_to_vif(rtwvif); 3493 3494 if (!(vif->type == NL80211_IFTYPE_STATION || 3495 vif->type == NL80211_IFTYPE_P2P_CLIENT)) 3496 continue; 3497 3498 rtw89_enter_lps(rtwdev, rtwvif, true); 3499 } 3500 } 3501 3502 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3503 { 3504 enum rtw89_entity_mode mode; 3505 3506 mode = rtw89_get_entity_mode(rtwdev); 3507 if (mode == RTW89_ENTITY_MODE_MCC) 3508 return; 3509 3510 rtw89_chip_rfk_track(rtwdev); 3511 } 3512 3513 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, 3514 struct rtw89_vif_link *rtwvif_link, 3515 struct ieee80211_bss_conf *bss_conf) 3516 { 3517 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3518 3519 if (mode == RTW89_ENTITY_MODE_MCC) 3520 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3521 else 3522 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf); 3523 } 3524 3525 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3526 struct rtw89_traffic_stats *stats) 3527 { 3528 stats->tx_unicast = 0; 3529 stats->rx_unicast = 0; 3530 stats->tx_cnt = 0; 3531 stats->rx_cnt = 0; 3532 ewma_tp_init(&stats->tx_ewma_tp); 3533 ewma_tp_init(&stats->rx_ewma_tp); 3534 } 3535 3536 static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work) 3537 { 3538 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3539 track_work.work); 3540 bool tfc_changed; 3541 3542 lockdep_assert_wiphy(wiphy); 3543 3544 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3545 return; 3546 3547 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3548 return; 3549 3550 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work, 3551 RTW89_TRACK_WORK_PERIOD); 3552 3553 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3554 if (rtwdev->scanning) 3555 return; 3556 3557 rtw89_leave_lps(rtwdev); 3558 3559 if (tfc_changed) { 3560 rtw89_hci_recalc_int_mit(rtwdev); 3561 rtw89_btc_ntfy_wl_sta(rtwdev); 3562 } 3563 rtw89_mac_bf_monitor_track(rtwdev); 3564 rtw89_phy_stat_track(rtwdev); 3565 rtw89_phy_env_monitor_track(rtwdev); 3566 rtw89_phy_dig(rtwdev); 3567 rtw89_core_rfk_track(rtwdev); 3568 rtw89_phy_ra_update(rtwdev); 3569 rtw89_phy_cfo_track(rtwdev); 3570 rtw89_phy_tx_path_div_track(rtwdev); 3571 rtw89_phy_antdiv_track(rtwdev); 3572 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3573 rtw89_phy_edcca_track(rtwdev); 3574 rtw89_tas_track(rtwdev); 3575 rtw89_chanctx_track(rtwdev); 3576 rtw89_core_rfkill_poll(rtwdev, false); 3577 3578 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3579 rtw89_enter_lps_track(rtwdev); 3580 } 3581 3582 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3583 { 3584 unsigned long bit; 3585 3586 bit = find_first_zero_bit(addr, size); 3587 if (bit < size) 3588 set_bit(bit, addr); 3589 3590 return bit; 3591 } 3592 3593 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3594 { 3595 clear_bit(bit, addr); 3596 } 3597 3598 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3599 { 3600 bitmap_zero(addr, nbits); 3601 } 3602 3603 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3604 struct rtw89_sta_link *rtwsta_link, u8 tid, 3605 u8 *cam_idx) 3606 { 3607 const struct rtw89_chip_info *chip = rtwdev->chip; 3608 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3609 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3610 u8 idx; 3611 int i; 3612 3613 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3614 3615 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3616 if (idx == chip->bacam_num) { 3617 /* allocate a static BA CAM to tid=0/5, so replace the existing 3618 * one if BA CAM is full. Hardware will process the original tid 3619 * automatically. 3620 */ 3621 if (tid != 0 && tid != 5) 3622 return -ENOSPC; 3623 3624 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3625 tmp = &cam_info->ba_cam_entry[i]; 3626 if (tmp->tid == 0 || tmp->tid == 5) 3627 continue; 3628 3629 idx = i; 3630 entry = tmp; 3631 list_del(&entry->list); 3632 break; 3633 } 3634 3635 if (!entry) 3636 return -ENOSPC; 3637 } else { 3638 entry = &cam_info->ba_cam_entry[idx]; 3639 } 3640 3641 entry->tid = tid; 3642 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list); 3643 3644 *cam_idx = idx; 3645 3646 return 0; 3647 } 3648 3649 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3650 struct rtw89_sta_link *rtwsta_link, u8 tid, 3651 u8 *cam_idx) 3652 { 3653 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3654 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3655 u8 idx; 3656 3657 lockdep_assert_wiphy(rtwdev->hw->wiphy); 3658 3659 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) { 3660 if (entry->tid != tid) 3661 continue; 3662 3663 idx = entry - cam_info->ba_cam_entry; 3664 list_del(&entry->list); 3665 3666 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3667 *cam_idx = idx; 3668 return 0; 3669 } 3670 3671 return -ENOENT; 3672 } 3673 3674 #define RTW89_TYPE_MAPPING(_type) \ 3675 case NL80211_IFTYPE_ ## _type: \ 3676 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3677 break 3678 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc) 3679 { 3680 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3681 const struct ieee80211_bss_conf *bss_conf; 3682 3683 switch (vif->type) { 3684 case NL80211_IFTYPE_STATION: 3685 if (vif->p2p) 3686 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3687 else 3688 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION; 3689 break; 3690 case NL80211_IFTYPE_AP: 3691 if (vif->p2p) 3692 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3693 else 3694 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP; 3695 break; 3696 RTW89_TYPE_MAPPING(ADHOC); 3697 RTW89_TYPE_MAPPING(MONITOR); 3698 RTW89_TYPE_MAPPING(MESH_POINT); 3699 default: 3700 WARN_ON(1); 3701 break; 3702 } 3703 3704 switch (vif->type) { 3705 case NL80211_IFTYPE_AP: 3706 case NL80211_IFTYPE_MESH_POINT: 3707 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE; 3708 rtwvif_link->self_role = RTW89_SELF_ROLE_AP; 3709 break; 3710 case NL80211_IFTYPE_ADHOC: 3711 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC; 3712 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 3713 break; 3714 case NL80211_IFTYPE_STATION: 3715 if (assoc) { 3716 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA; 3717 3718 rcu_read_lock(); 3719 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 3720 rtwvif_link->trigger = bss_conf->he_support; 3721 rcu_read_unlock(); 3722 } else { 3723 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK; 3724 rtwvif_link->trigger = false; 3725 } 3726 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT; 3727 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3728 break; 3729 case NL80211_IFTYPE_MONITOR: 3730 break; 3731 default: 3732 WARN_ON(1); 3733 break; 3734 } 3735 } 3736 3737 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev, 3738 struct rtw89_vif_link *rtwvif_link, 3739 struct rtw89_sta_link *rtwsta_link) 3740 { 3741 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3742 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3743 struct rtw89_hal *hal = &rtwdev->hal; 3744 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3745 int i; 3746 int ret; 3747 3748 rtwsta_link->prev_rssi = 0; 3749 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list); 3750 ewma_rssi_init(&rtwsta_link->avg_rssi); 3751 ewma_snr_init(&rtwsta_link->avg_snr); 3752 ewma_evm_init(&rtwsta_link->evm_1ss); 3753 for (i = 0; i < ant_num; i++) { 3754 ewma_rssi_init(&rtwsta_link->rssi[i]); 3755 ewma_evm_init(&rtwsta_link->evm_min[i]); 3756 ewma_evm_init(&rtwsta_link->evm_max[i]); 3757 } 3758 3759 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3760 /* must do rtw89_reg_6ghz_recalc() before rfk channel */ 3761 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true); 3762 if (ret) 3763 return ret; 3764 3765 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 3766 BTC_ROLE_MSTS_STA_CONN_START); 3767 rtw89_chip_rfk_channel(rtwdev, rtwvif_link); 3768 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3769 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false); 3770 if (ret) { 3771 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3772 return ret; 3773 } 3774 3775 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 3776 RTW89_ROLE_CREATE); 3777 if (ret) { 3778 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3779 return ret; 3780 } 3781 3782 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3783 if (ret) 3784 return ret; 3785 3786 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3787 if (ret) 3788 return ret; 3789 } 3790 3791 return 0; 3792 } 3793 3794 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev, 3795 struct rtw89_vif_link *rtwvif_link, 3796 struct rtw89_sta_link *rtwsta_link) 3797 { 3798 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3799 3800 rtw89_assoc_link_clr(rtwsta_link); 3801 3802 if (vif->type == NL80211_IFTYPE_STATION) 3803 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false); 3804 3805 return 0; 3806 } 3807 3808 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev, 3809 struct rtw89_vif_link *rtwvif_link, 3810 struct rtw89_sta_link *rtwsta_link) 3811 { 3812 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3813 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3814 int ret; 3815 3816 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true); 3817 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link); 3818 3819 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 3820 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam); 3821 if (sta->tdls) 3822 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam); 3823 3824 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3825 rtw89_vif_type_mapping(rtwvif_link, false); 3826 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true); 3827 } 3828 3829 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3830 if (ret) { 3831 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3832 return ret; 3833 } 3834 3835 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true); 3836 if (ret) { 3837 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3838 return ret; 3839 } 3840 3841 /* update cam aid mac_id net_type */ 3842 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 3843 if (ret) { 3844 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3845 return ret; 3846 } 3847 3848 return ret; 3849 } 3850 3851 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev, 3852 struct ieee80211_bss_conf *bss_conf, 3853 struct ieee80211_link_sta *link_sta) 3854 { 3855 if (!bss_conf->he_support || 3856 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE) 3857 return false; 3858 3859 if (rtwdev->chip->chip_id == RTL8852C && 3860 rtw89_sta_link_has_su_mu_4xhe08(link_sta) && 3861 !rtw89_sta_link_has_er_su_4xhe08(link_sta)) 3862 return false; 3863 3864 return true; 3865 } 3866 3867 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev, 3868 struct rtw89_vif_link *rtwvif_link, 3869 struct rtw89_sta_link *rtwsta_link) 3870 { 3871 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3872 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3873 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link, 3874 rtwsta_link); 3875 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3876 rtwvif_link->chanctx_idx); 3877 struct ieee80211_link_sta *link_sta; 3878 int ret; 3879 3880 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3881 if (sta->tdls) { 3882 rcu_read_lock(); 3883 3884 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3885 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam, 3886 link_sta->addr); 3887 if (ret) { 3888 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3889 rcu_read_unlock(); 3890 return ret; 3891 } 3892 3893 rcu_read_unlock(); 3894 } 3895 3896 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam); 3897 if (ret) { 3898 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3899 return ret; 3900 } 3901 } 3902 3903 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link); 3904 if (ret) { 3905 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3906 return ret; 3907 } 3908 3909 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false); 3910 if (ret) { 3911 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3912 return ret; 3913 } 3914 3915 /* update cam aid mac_id net_type */ 3916 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL); 3917 if (ret) { 3918 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3919 return ret; 3920 } 3921 3922 rtw89_phy_ra_assoc(rtwdev, rtwsta_link); 3923 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link); 3924 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false); 3925 3926 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3927 struct ieee80211_bss_conf *bss_conf; 3928 3929 rcu_read_lock(); 3930 3931 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 3932 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true); 3933 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta); 3934 3935 rcu_read_unlock(); 3936 3937 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 3938 BTC_ROLE_MSTS_STA_CONN_END); 3939 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan); 3940 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link); 3941 3942 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id); 3943 if (ret) { 3944 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3945 return ret; 3946 } 3947 3948 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true); 3949 } 3950 3951 rtw89_assoc_link_set(rtwsta_link); 3952 return ret; 3953 } 3954 3955 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev, 3956 struct rtw89_vif_link *rtwvif_link, 3957 struct rtw89_sta_link *rtwsta_link) 3958 { 3959 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 3960 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link); 3961 int ret; 3962 3963 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3964 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false); 3965 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link, 3966 BTC_ROLE_MSTS_STA_DIS_CONN); 3967 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3968 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link, 3969 RTW89_ROLE_REMOVE); 3970 if (ret) { 3971 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3972 return ret; 3973 } 3974 } 3975 3976 return 0; 3977 } 3978 3979 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3980 struct ieee80211_sta *sta, 3981 struct cfg80211_tid_cfg *tid_conf) 3982 { 3983 struct ieee80211_txq *txq; 3984 struct rtw89_txq *rtwtxq; 3985 u32 mask = tid_conf->mask; 3986 u8 tids = tid_conf->tids; 3987 int tids_nbit = BITS_PER_BYTE; 3988 int i; 3989 3990 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3991 if (!tids) 3992 break; 3993 3994 if (!(tids & BIT(0))) 3995 continue; 3996 3997 txq = sta->txq[i]; 3998 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3999 4000 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 4001 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 4002 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4003 } else { 4004 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 4005 ieee80211_stop_tx_ba_session(sta, txq->tid); 4006 spin_lock_bh(&rtwdev->ba_lock); 4007 list_del_init(&rtwtxq->list); 4008 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 4009 spin_unlock_bh(&rtwdev->ba_lock); 4010 } 4011 } 4012 4013 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 4014 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 4015 sta->max_amsdu_subframes = 0; 4016 else 4017 sta->max_amsdu_subframes = 1; 4018 } 4019 } 4020 } 4021 4022 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 4023 struct ieee80211_sta *sta, 4024 struct cfg80211_tid_config *tid_config) 4025 { 4026 int i; 4027 4028 for (i = 0; i < tid_config->n_tid_conf; i++) 4029 _rtw89_core_set_tid_config(rtwdev, sta, 4030 &tid_config->tid_conf[i]); 4031 } 4032 4033 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 4034 struct ieee80211_sta_ht_cap *ht_cap) 4035 { 4036 static const __le16 highest[RF_PATH_MAX] = { 4037 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 4038 }; 4039 struct rtw89_hal *hal = &rtwdev->hal; 4040 u8 nss = hal->rx_nss; 4041 int i; 4042 4043 ht_cap->ht_supported = true; 4044 ht_cap->cap = 0; 4045 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 4046 IEEE80211_HT_CAP_MAX_AMSDU | 4047 IEEE80211_HT_CAP_TX_STBC | 4048 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 4049 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 4050 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 4051 IEEE80211_HT_CAP_DSSSCCK40 | 4052 IEEE80211_HT_CAP_SGI_40; 4053 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 4054 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 4055 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 4056 for (i = 0; i < nss; i++) 4057 ht_cap->mcs.rx_mask[i] = 0xFF; 4058 ht_cap->mcs.rx_mask[4] = 0x01; 4059 ht_cap->mcs.rx_highest = highest[nss - 1]; 4060 } 4061 4062 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 4063 struct ieee80211_sta_vht_cap *vht_cap) 4064 { 4065 static const __le16 highest_bw80[RF_PATH_MAX] = { 4066 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 4067 }; 4068 static const __le16 highest_bw160[RF_PATH_MAX] = { 4069 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 4070 }; 4071 const struct rtw89_chip_info *chip = rtwdev->chip; 4072 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 4073 highest_bw160 : highest_bw80; 4074 struct rtw89_hal *hal = &rtwdev->hal; 4075 u16 tx_mcs_map = 0, rx_mcs_map = 0; 4076 u8 sts_cap = 3; 4077 int i; 4078 4079 for (i = 0; i < 8; i++) { 4080 if (i < hal->tx_nss) 4081 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4082 else 4083 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4084 if (i < hal->rx_nss) 4085 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 4086 else 4087 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 4088 } 4089 4090 vht_cap->vht_supported = true; 4091 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 4092 IEEE80211_VHT_CAP_SHORT_GI_80 | 4093 IEEE80211_VHT_CAP_RXSTBC_1 | 4094 IEEE80211_VHT_CAP_HTC_VHT | 4095 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 4096 0; 4097 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 4098 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 4099 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 4100 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 4101 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 4102 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4103 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 4104 IEEE80211_VHT_CAP_SHORT_GI_160; 4105 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 4106 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 4107 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 4108 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 4109 4110 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 4111 vht_cap->vht_mcs.tx_highest |= 4112 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 4113 } 4114 4115 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 4116 enum nl80211_band band, 4117 enum nl80211_iftype iftype, 4118 struct ieee80211_sband_iftype_data *iftype_data) 4119 { 4120 const struct rtw89_chip_info *chip = rtwdev->chip; 4121 struct rtw89_hal *hal = &rtwdev->hal; 4122 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 4123 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 4124 struct ieee80211_sta_he_cap *he_cap; 4125 int nss = hal->rx_nss; 4126 u8 *mac_cap_info; 4127 u8 *phy_cap_info; 4128 u16 mcs_map = 0; 4129 int i; 4130 4131 for (i = 0; i < 8; i++) { 4132 if (i < nss) 4133 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 4134 else 4135 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 4136 } 4137 4138 he_cap = &iftype_data->he_cap; 4139 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 4140 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 4141 4142 he_cap->has_he = true; 4143 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 4144 if (iftype == NL80211_IFTYPE_STATION) 4145 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 4146 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 4147 IEEE80211_HE_MAC_CAP2_BSR; 4148 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 4149 if (iftype == NL80211_IFTYPE_AP) 4150 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 4151 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 4152 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 4153 if (iftype == NL80211_IFTYPE_STATION) 4154 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 4155 if (band == NL80211_BAND_2GHZ) { 4156 phy_cap_info[0] = 4157 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 4158 } else { 4159 phy_cap_info[0] = 4160 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 4161 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4162 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 4163 } 4164 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 4165 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 4166 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 4167 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 4168 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 4169 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 4170 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 4171 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 4172 if (iftype == NL80211_IFTYPE_STATION) 4173 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 4174 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 4175 if (iftype == NL80211_IFTYPE_AP) 4176 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 4177 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 4178 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 4179 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4180 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 4181 phy_cap_info[5] = no_ng16 ? 0 : 4182 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 4183 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 4184 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 4185 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 4186 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 4187 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 4188 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 4189 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 4190 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 4191 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 4192 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 4193 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 4194 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4195 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 4196 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 4197 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 4198 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 4199 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 4200 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 4201 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 4202 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 4203 if (iftype == NL80211_IFTYPE_STATION) 4204 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 4205 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 4206 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 4207 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 4208 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 4209 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 4210 } 4211 4212 if (band == NL80211_BAND_6GHZ) { 4213 __le16 capa; 4214 4215 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 4216 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 4217 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 4218 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 4219 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 4220 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 4221 iftype_data->he_6ghz_capa.capa = capa; 4222 } 4223 } 4224 4225 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 4226 enum nl80211_band band, 4227 enum nl80211_iftype iftype, 4228 struct ieee80211_sband_iftype_data *iftype_data) 4229 { 4230 const struct rtw89_chip_info *chip = rtwdev->chip; 4231 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 4232 struct ieee80211_eht_mcs_nss_supp *eht_nss; 4233 struct ieee80211_sta_eht_cap *eht_cap; 4234 struct rtw89_hal *hal = &rtwdev->hal; 4235 bool support_mcs_12_13 = true; 4236 bool support_320mhz = false; 4237 u8 val, val_mcs13; 4238 int sts = 8; 4239 4240 if (chip->chip_gen == RTW89_CHIP_AX) 4241 return; 4242 4243 if (hal->no_mcs_12_13) 4244 support_mcs_12_13 = false; 4245 4246 if (band == NL80211_BAND_6GHZ && 4247 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 4248 support_320mhz = true; 4249 4250 eht_cap = &iftype_data->eht_cap; 4251 eht_cap_elem = &eht_cap->eht_cap_elem; 4252 eht_nss = &eht_cap->eht_mcs_nss_supp; 4253 4254 eht_cap->has_eht = true; 4255 4256 eht_cap_elem->mac_cap_info[0] = 4257 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 4258 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 4259 eht_cap_elem->mac_cap_info[1] = 0; 4260 4261 eht_cap_elem->phy_cap_info[0] = 4262 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 4263 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 4264 if (support_320mhz) 4265 eht_cap_elem->phy_cap_info[0] |= 4266 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 4267 4268 eht_cap_elem->phy_cap_info[0] |= 4269 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 4270 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 4271 eht_cap_elem->phy_cap_info[1] = 4272 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 4273 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 4274 u8_encode_bits(sts - 1, 4275 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 4276 if (support_320mhz) 4277 eht_cap_elem->phy_cap_info[1] |= 4278 u8_encode_bits(sts - 1, 4279 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 4280 4281 eht_cap_elem->phy_cap_info[2] = 0; 4282 4283 eht_cap_elem->phy_cap_info[3] = 4284 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 4285 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 4286 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 4287 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 4288 4289 eht_cap_elem->phy_cap_info[4] = 4290 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 4291 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 4292 4293 eht_cap_elem->phy_cap_info[5] = 4294 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 4295 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 4296 4297 eht_cap_elem->phy_cap_info[6] = 0; 4298 eht_cap_elem->phy_cap_info[7] = 0; 4299 eht_cap_elem->phy_cap_info[8] = 0; 4300 4301 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 4302 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 4303 val_mcs13 = support_mcs_12_13 ? val : 0; 4304 4305 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 4306 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 4307 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13; 4308 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 4309 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 4310 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13; 4311 if (support_320mhz) { 4312 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 4313 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 4314 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13; 4315 } 4316 } 4317 4318 #define RTW89_SBAND_IFTYPES_NR 2 4319 4320 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 4321 enum nl80211_band band, 4322 struct ieee80211_supported_band *sband) 4323 { 4324 struct ieee80211_sband_iftype_data *iftype_data; 4325 enum nl80211_iftype iftype; 4326 int idx = 0; 4327 4328 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 4329 if (!iftype_data) 4330 return; 4331 4332 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 4333 switch (iftype) { 4334 case NL80211_IFTYPE_STATION: 4335 case NL80211_IFTYPE_AP: 4336 break; 4337 default: 4338 continue; 4339 } 4340 4341 if (idx >= RTW89_SBAND_IFTYPES_NR) { 4342 rtw89_warn(rtwdev, "run out of iftype_data\n"); 4343 break; 4344 } 4345 4346 iftype_data[idx].types_mask = BIT(iftype); 4347 4348 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 4349 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 4350 4351 idx++; 4352 } 4353 4354 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 4355 } 4356 4357 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 4358 { 4359 struct ieee80211_hw *hw = rtwdev->hw; 4360 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 4361 struct ieee80211_supported_band *sband_6ghz = NULL; 4362 u32 size = sizeof(struct ieee80211_supported_band); 4363 u8 support_bands = rtwdev->chip->support_bands; 4364 4365 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 4366 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 4367 if (!sband_2ghz) 4368 goto err; 4369 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 4370 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 4371 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 4372 } 4373 4374 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 4375 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 4376 if (!sband_5ghz) 4377 goto err; 4378 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 4379 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 4380 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 4381 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 4382 } 4383 4384 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 4385 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 4386 if (!sband_6ghz) 4387 goto err; 4388 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 4389 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 4390 } 4391 4392 return 0; 4393 4394 err: 4395 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4396 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4397 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4398 if (sband_2ghz) 4399 kfree((__force void *)sband_2ghz->iftype_data); 4400 if (sband_5ghz) 4401 kfree((__force void *)sband_5ghz->iftype_data); 4402 if (sband_6ghz) 4403 kfree((__force void *)sband_6ghz->iftype_data); 4404 kfree(sband_2ghz); 4405 kfree(sband_5ghz); 4406 kfree(sband_6ghz); 4407 return -ENOMEM; 4408 } 4409 4410 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 4411 { 4412 struct ieee80211_hw *hw = rtwdev->hw; 4413 4414 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 4415 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 4416 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 4417 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 4418 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 4419 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 4420 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 4421 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 4422 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 4423 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 4424 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 4425 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 4426 } 4427 4428 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 4429 { 4430 int i; 4431 4432 for (i = 0; i < RTW89_PHY_NUM; i++) 4433 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4434 for (i = 0; i < RTW89_PHY_NUM; i++) 4435 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4436 } 4437 4438 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work) 4439 { 4440 struct rtw89_dev *rtwdev; 4441 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link, 4442 update_beacon_work); 4443 4444 lockdep_assert_wiphy(wiphy); 4445 4446 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE) 4447 return; 4448 4449 rtwdev = rtwvif_link->rtwvif->rtwdev; 4450 4451 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link); 4452 } 4453 4454 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4455 { 4456 struct completion *cmpl = &wait->completion; 4457 unsigned long time_left; 4458 unsigned int cur; 4459 4460 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4461 if (cur != RTW89_WAIT_COND_IDLE) 4462 return -EBUSY; 4463 4464 time_left = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4465 if (time_left == 0) { 4466 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4467 return -ETIMEDOUT; 4468 } 4469 4470 if (wait->data.err) 4471 return -EFAULT; 4472 4473 return 0; 4474 } 4475 4476 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4477 const struct rtw89_completion_data *data) 4478 { 4479 unsigned int cur; 4480 4481 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4482 if (cur != cond) 4483 return; 4484 4485 wait->data = *data; 4486 complete(&wait->completion); 4487 } 4488 4489 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4490 { 4491 u16 bt_req_len; 4492 4493 switch (event) { 4494 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4495 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4496 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4497 "coex updates BT req len to %d TU\n", bt_req_len); 4498 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4499 break; 4500 default: 4501 if (event < NUM_OF_RTW89_BTC_HMSG) 4502 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4503 "unhandled BTC HMSG event: %d\n", event); 4504 else 4505 rtw89_warn(rtwdev, 4506 "unrecognized BTC HMSG event: %d\n", event); 4507 break; 4508 } 4509 } 4510 4511 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4512 { 4513 const struct dmi_system_id *match; 4514 enum rtw89_quirks quirk; 4515 4516 if (!quirks) 4517 return; 4518 4519 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4520 quirk = (uintptr_t)match->driver_data; 4521 if (quirk >= NUM_OF_RTW89_QUIRKS) 4522 continue; 4523 4524 set_bit(quirk, rtwdev->quirks); 4525 } 4526 } 4527 EXPORT_SYMBOL(rtw89_check_quirks); 4528 4529 int rtw89_core_start(struct rtw89_dev *rtwdev) 4530 { 4531 int ret; 4532 4533 ret = rtw89_mac_init(rtwdev); 4534 if (ret) { 4535 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4536 return ret; 4537 } 4538 4539 rtw89_btc_ntfy_poweron(rtwdev); 4540 4541 /* efuse process */ 4542 4543 /* pre-config BB/RF, BB reset/RFC reset */ 4544 ret = rtw89_chip_reset_bb_rf(rtwdev); 4545 if (ret) 4546 return ret; 4547 4548 rtw89_phy_init_bb_reg(rtwdev); 4549 rtw89_chip_bb_postinit(rtwdev); 4550 rtw89_phy_init_rf_reg(rtwdev, false); 4551 4552 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4553 4554 rtw89_phy_dm_init(rtwdev); 4555 4556 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true); 4557 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true); 4558 rtw89_mac_update_rts_threshold(rtwdev); 4559 4560 rtw89_tas_reset(rtwdev); 4561 4562 ret = rtw89_hci_start(rtwdev); 4563 if (ret) { 4564 rtw89_err(rtwdev, "failed to start hci\n"); 4565 return ret; 4566 } 4567 4568 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work, 4569 RTW89_TRACK_WORK_PERIOD); 4570 4571 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4572 4573 rtw89_chip_rfk_init_late(rtwdev); 4574 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4575 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4576 rtw89_fw_h2c_init_ba_cam(rtwdev); 4577 4578 return 0; 4579 } 4580 4581 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4582 { 4583 struct wiphy *wiphy = rtwdev->hw->wiphy; 4584 struct rtw89_btc *btc = &rtwdev->btc; 4585 4586 lockdep_assert_wiphy(wiphy); 4587 4588 /* Prvent to stop twice; enter_ips and ops_stop */ 4589 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4590 return; 4591 4592 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4593 4594 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4595 4596 wiphy_work_cancel(wiphy, &rtwdev->c2h_work); 4597 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work); 4598 wiphy_work_cancel(wiphy, &btc->eapol_notify_work); 4599 wiphy_work_cancel(wiphy, &btc->arp_notify_work); 4600 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work); 4601 wiphy_work_cancel(wiphy, &btc->icmp_notify_work); 4602 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4603 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work); 4604 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work); 4605 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work); 4606 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work); 4607 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work); 4608 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work); 4609 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4610 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work); 4611 4612 rtw89_btc_ntfy_poweroff(rtwdev); 4613 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4614 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4615 rtw89_hci_stop(rtwdev); 4616 rtw89_hci_deinit(rtwdev); 4617 rtw89_mac_pwr_off(rtwdev); 4618 rtw89_hci_reset(rtwdev); 4619 } 4620 4621 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev) 4622 { 4623 const struct rtw89_chip_info *chip = rtwdev->chip; 4624 u8 mac_id_num; 4625 u8 mac_id; 4626 4627 if (rtwdev->support_mlo) 4628 mac_id_num = chip->support_macid_num / chip->support_link_num; 4629 else 4630 mac_id_num = chip->support_macid_num; 4631 4632 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num); 4633 if (mac_id == mac_id_num) 4634 return RTW89_MAX_MAC_ID_NUM; 4635 4636 set_bit(mac_id, rtwdev->mac_id_map); 4637 return mac_id; 4638 } 4639 4640 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id) 4641 { 4642 clear_bit(mac_id, rtwdev->mac_id_map); 4643 } 4644 4645 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4646 u8 mac_id, u8 port) 4647 { 4648 const struct rtw89_chip_info *chip = rtwdev->chip; 4649 u8 support_link_num = chip->support_link_num; 4650 u8 support_mld_num = 0; 4651 unsigned int link_id; 4652 u8 index; 4653 4654 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 4655 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 4656 rtwvif->links[link_id] = NULL; 4657 4658 rtwvif->rtwdev = rtwdev; 4659 4660 if (rtwdev->support_mlo) { 4661 rtwvif->links_inst_valid_num = support_link_num; 4662 support_mld_num = chip->support_macid_num / support_link_num; 4663 } else { 4664 rtwvif->links_inst_valid_num = 1; 4665 } 4666 4667 for (index = 0; index < rtwvif->links_inst_valid_num; index++) { 4668 struct rtw89_vif_link *inst = &rtwvif->links_inst[index]; 4669 4670 inst->rtwvif = rtwvif; 4671 inst->mac_id = mac_id + index * support_mld_num; 4672 inst->mac_idx = RTW89_MAC_0 + index; 4673 inst->phy_idx = RTW89_PHY_0 + index; 4674 4675 /* multi-link use the same port id on different HW bands */ 4676 inst->port = port; 4677 } 4678 } 4679 4680 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4681 struct rtw89_sta *rtwsta, u8 mac_id) 4682 { 4683 const struct rtw89_chip_info *chip = rtwdev->chip; 4684 u8 support_link_num = chip->support_link_num; 4685 u8 support_mld_num = 0; 4686 unsigned int link_id; 4687 u8 index; 4688 4689 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM); 4690 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++) 4691 rtwsta->links[link_id] = NULL; 4692 4693 rtwsta->rtwdev = rtwdev; 4694 rtwsta->rtwvif = rtwvif; 4695 4696 if (rtwdev->support_mlo) { 4697 rtwsta->links_inst_valid_num = support_link_num; 4698 support_mld_num = chip->support_macid_num / support_link_num; 4699 } else { 4700 rtwsta->links_inst_valid_num = 1; 4701 } 4702 4703 for (index = 0; index < rtwsta->links_inst_valid_num; index++) { 4704 struct rtw89_sta_link *inst = &rtwsta->links_inst[index]; 4705 4706 inst->rtwvif_link = &rtwvif->links_inst[index]; 4707 4708 inst->rtwsta = rtwsta; 4709 inst->mac_id = mac_id + index * support_mld_num; 4710 } 4711 } 4712 4713 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif, 4714 unsigned int link_id) 4715 { 4716 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 4717 u8 index; 4718 int ret; 4719 4720 if (rtwvif_link) 4721 return rtwvif_link; 4722 4723 index = find_first_zero_bit(rtwvif->links_inst_map, 4724 rtwvif->links_inst_valid_num); 4725 if (index == rtwvif->links_inst_valid_num) { 4726 ret = -EBUSY; 4727 goto err; 4728 } 4729 4730 rtwvif_link = &rtwvif->links_inst[index]; 4731 rtwvif_link->link_id = link_id; 4732 4733 set_bit(index, rtwvif->links_inst_map); 4734 rtwvif->links[link_id] = rtwvif_link; 4735 return rtwvif_link; 4736 4737 err: 4738 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n", 4739 link_id, ret); 4740 return NULL; 4741 } 4742 4743 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id) 4744 { 4745 struct rtw89_vif_link **container = &rtwvif->links[link_id]; 4746 struct rtw89_vif_link *link = *container; 4747 u8 index; 4748 4749 if (!link) 4750 return; 4751 4752 index = rtw89_vif_link_inst_get_index(link); 4753 clear_bit(index, rtwvif->links_inst_map); 4754 *container = NULL; 4755 } 4756 4757 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta, 4758 unsigned int link_id) 4759 { 4760 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 4761 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id]; 4762 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id]; 4763 u8 index; 4764 int ret; 4765 4766 if (rtwsta_link) 4767 return rtwsta_link; 4768 4769 if (!rtwvif_link) { 4770 ret = -ENOLINK; 4771 goto err; 4772 } 4773 4774 index = rtw89_vif_link_inst_get_index(rtwvif_link); 4775 if (test_bit(index, rtwsta->links_inst_map)) { 4776 ret = -EBUSY; 4777 goto err; 4778 } 4779 4780 rtwsta_link = &rtwsta->links_inst[index]; 4781 rtwsta_link->link_id = link_id; 4782 4783 set_bit(index, rtwsta->links_inst_map); 4784 rtwsta->links[link_id] = rtwsta_link; 4785 return rtwsta_link; 4786 4787 err: 4788 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n", 4789 link_id, ret); 4790 return NULL; 4791 } 4792 4793 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id) 4794 { 4795 struct rtw89_sta_link **container = &rtwsta->links[link_id]; 4796 struct rtw89_sta_link *link = *container; 4797 u8 index; 4798 4799 if (!link) 4800 return; 4801 4802 index = rtw89_sta_link_inst_get_index(link); 4803 clear_bit(index, rtwsta->links_inst_map); 4804 *container = NULL; 4805 } 4806 4807 int rtw89_core_init(struct rtw89_dev *rtwdev) 4808 { 4809 struct rtw89_btc *btc = &rtwdev->btc; 4810 u8 band; 4811 4812 INIT_LIST_HEAD(&rtwdev->ba_list); 4813 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 4814 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 4815 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 4816 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 4817 if (!(rtwdev->chip->support_bands & BIT(band))) 4818 continue; 4819 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 4820 } 4821 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 4822 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 4823 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 4824 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work); 4825 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work); 4826 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 4827 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 4828 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 4829 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 4830 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 4831 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 4832 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 4833 if (!rtwdev->txq_wq) 4834 return -ENOMEM; 4835 spin_lock_init(&rtwdev->ba_lock); 4836 spin_lock_init(&rtwdev->rpwm_lock); 4837 mutex_init(&rtwdev->rf_mutex); 4838 rtwdev->total_sta_assoc = 0; 4839 4840 rtw89_init_wait(&rtwdev->mcc.wait); 4841 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 4842 rtw89_init_wait(&rtwdev->wow.wait); 4843 rtw89_init_wait(&rtwdev->mac.ps_wait); 4844 4845 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work); 4846 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work); 4847 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 4848 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 4849 4850 skb_queue_head_init(&rtwdev->c2h_queue); 4851 rtw89_core_ppdu_sts_init(rtwdev); 4852 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 4853 4854 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 4855 rtwdev->dbcc_en = false; 4856 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 4857 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 4858 4859 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4860 rtwdev->dbcc_en = true; 4861 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 4862 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF; 4863 } 4864 4865 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0; 4866 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1; 4867 4868 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 4869 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 4870 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 4871 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 4872 4873 init_completion(&rtwdev->fw.req.completion); 4874 init_completion(&rtwdev->rfk_wait.completion); 4875 4876 schedule_work(&rtwdev->load_firmware_work); 4877 4878 rtw89_ser_init(rtwdev); 4879 rtw89_entity_init(rtwdev); 4880 rtw89_tas_init(rtwdev); 4881 rtw89_phy_ant_gain_init(rtwdev); 4882 4883 return 0; 4884 } 4885 EXPORT_SYMBOL(rtw89_core_init); 4886 4887 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 4888 { 4889 rtw89_ser_deinit(rtwdev); 4890 rtw89_unload_firmware(rtwdev); 4891 __rtw89_fw_free_all_early_h2c(rtwdev); 4892 4893 destroy_workqueue(rtwdev->txq_wq); 4894 mutex_destroy(&rtwdev->rf_mutex); 4895 } 4896 EXPORT_SYMBOL(rtw89_core_deinit); 4897 4898 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link, 4899 const u8 *mac_addr, bool hw_scan) 4900 { 4901 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4902 rtwvif_link->chanctx_idx); 4903 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 4904 4905 rtwdev->scanning = true; 4906 rtw89_leave_lps(rtwdev); 4907 if (hw_scan) 4908 rtw89_leave_ips_by_hwflags(rtwdev); 4909 4910 ether_addr_copy(rtwvif_link->mac_addr, mac_addr); 4911 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type); 4912 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true); 4913 rtw89_hci_recalc_int_mit(rtwdev); 4914 rtw89_phy_config_edcca(rtwdev, bb, true); 4915 4916 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr); 4917 } 4918 4919 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4920 struct rtw89_vif_link *rtwvif_link, bool hw_scan) 4921 { 4922 struct ieee80211_bss_conf *bss_conf; 4923 struct rtw89_bb_ctx *bb; 4924 4925 if (!rtwvif_link) 4926 return; 4927 4928 rcu_read_lock(); 4929 4930 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true); 4931 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr); 4932 4933 rcu_read_unlock(); 4934 4935 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL); 4936 4937 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false); 4938 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx); 4939 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx); 4940 rtw89_phy_config_edcca(rtwdev, bb, false); 4941 4942 rtwdev->scanning = false; 4943 rtw89_for_each_active_bb(rtwdev, bb) 4944 bb->dig.bypass_dig = true; 4945 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 4946 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work); 4947 } 4948 4949 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 4950 { 4951 const struct rtw89_chip_info *chip = rtwdev->chip; 4952 int ret; 4953 u8 val; 4954 u8 cv; 4955 4956 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 4957 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 4958 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 4959 cv = CHIP_CAV; 4960 else 4961 cv = CHIP_CBV; 4962 } 4963 4964 rtwdev->hal.cv = cv; 4965 4966 if (rtw89_is_rtl885xb(rtwdev)) { 4967 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 4968 if (ret) 4969 return; 4970 4971 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 4972 } 4973 } 4974 4975 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 4976 { 4977 const struct rtw89_chip_info *chip = rtwdev->chip; 4978 4979 rtwdev->hal.support_cckpd = 4980 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 4981 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 4982 rtwdev->hal.support_igi = 4983 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 4984 4985 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks)) 4986 rtwdev->hal.thermal_prot_th = chip->thermal_th[1]; 4987 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks)) 4988 rtwdev->hal.thermal_prot_th = chip->thermal_th[0]; 4989 else 4990 rtwdev->hal.thermal_prot_th = 0; 4991 } 4992 4993 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 4994 { 4995 const struct rtw89_chip_info *chip = rtwdev->chip; 4996 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 4997 struct rtw89_efuse *efuse = &rtwdev->efuse; 4998 const struct rtw89_rfe_parms *sel; 4999 u8 rfe_type = efuse->rfe_type; 5000 5001 if (!conf) { 5002 sel = chip->dflt_parms; 5003 goto out; 5004 } 5005 5006 while (conf->rfe_parms) { 5007 if (rfe_type == conf->rfe_type) { 5008 sel = conf->rfe_parms; 5009 goto out; 5010 } 5011 conf++; 5012 } 5013 5014 sel = chip->dflt_parms; 5015 5016 out: 5017 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 5018 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 5019 } 5020 5021 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 5022 { 5023 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5024 int ret; 5025 5026 ret = rtw89_mac_partial_init(rtwdev, false); 5027 if (ret) 5028 return ret; 5029 5030 ret = mac->parse_efuse_map(rtwdev); 5031 if (ret) 5032 return ret; 5033 5034 ret = mac->parse_phycap_map(rtwdev); 5035 if (ret) 5036 return ret; 5037 5038 ret = rtw89_mac_setup_phycap(rtwdev); 5039 if (ret) 5040 return ret; 5041 5042 rtw89_core_setup_phycap(rtwdev); 5043 5044 rtw89_hci_mac_pre_deinit(rtwdev); 5045 5046 return 0; 5047 } 5048 5049 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 5050 { 5051 rtw89_chip_fem_setup(rtwdev); 5052 5053 return 0; 5054 } 5055 5056 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev) 5057 { 5058 return !!rtwdev->chip->rfkill_init; 5059 } 5060 5061 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev) 5062 { 5063 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init; 5064 5065 rtw89_write16_mask(rtwdev, regs->pinmux.addr, 5066 regs->pinmux.mask, regs->pinmux.data); 5067 rtw89_write16_mask(rtwdev, regs->mode.addr, 5068 regs->mode.mask, regs->mode.data); 5069 } 5070 5071 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev) 5072 { 5073 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get; 5074 5075 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask); 5076 } 5077 5078 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev) 5079 { 5080 if (!rtw89_chip_has_rfkill(rtwdev)) 5081 return; 5082 5083 rtw89_core_rfkill_init(rtwdev); 5084 rtw89_core_rfkill_poll(rtwdev, true); 5085 wiphy_rfkill_start_polling(rtwdev->hw->wiphy); 5086 } 5087 5088 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev) 5089 { 5090 if (!rtw89_chip_has_rfkill(rtwdev)) 5091 return; 5092 5093 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy); 5094 } 5095 5096 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force) 5097 { 5098 bool prev, blocked; 5099 5100 if (!rtw89_chip_has_rfkill(rtwdev)) 5101 return; 5102 5103 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5104 blocked = rtw89_core_rfkill_get(rtwdev); 5105 5106 if (!force && prev == blocked) 5107 return; 5108 5109 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n", 5110 blocked ? "disable" : "enable"); 5111 5112 if (blocked) 5113 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5114 else 5115 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags); 5116 5117 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked); 5118 } 5119 5120 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 5121 { 5122 int ret; 5123 5124 rtw89_read_chip_ver(rtwdev); 5125 5126 ret = rtw89_mac_pwr_on(rtwdev); 5127 if (ret) { 5128 rtw89_err(rtwdev, "failed to power on\n"); 5129 return ret; 5130 } 5131 5132 ret = rtw89_wait_firmware_completion(rtwdev); 5133 if (ret) { 5134 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 5135 goto out; 5136 } 5137 5138 ret = rtw89_fw_recognize(rtwdev); 5139 if (ret) { 5140 rtw89_err(rtwdev, "failed to recognize firmware\n"); 5141 goto out; 5142 } 5143 5144 ret = rtw89_chip_efuse_info_setup(rtwdev); 5145 if (ret) 5146 goto out; 5147 5148 ret = rtw89_fw_recognize_elements(rtwdev); 5149 if (ret) { 5150 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 5151 goto out; 5152 } 5153 5154 ret = rtw89_chip_board_info_setup(rtwdev); 5155 if (ret) 5156 goto out; 5157 5158 rtw89_core_setup_rfe_parms(rtwdev); 5159 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 5160 5161 out: 5162 rtw89_mac_pwr_off(rtwdev); 5163 5164 return ret; 5165 } 5166 EXPORT_SYMBOL(rtw89_chip_info_setup); 5167 5168 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 5169 struct rtw89_vif_link *rtwvif_link) 5170 { 5171 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 5172 const struct rtw89_chip_info *chip = rtwdev->chip; 5173 struct ieee80211_bss_conf *bss_conf; 5174 5175 rcu_read_lock(); 5176 5177 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 5178 if (!bss_conf->he_support || !vif->cfg.assoc) { 5179 rcu_read_unlock(); 5180 return; 5181 } 5182 5183 rcu_read_unlock(); 5184 5185 if (chip->ops->set_txpwr_ul_tb_offset) 5186 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx); 5187 } 5188 5189 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 5190 { 5191 const struct rtw89_chip_info *chip = rtwdev->chip; 5192 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1; 5193 struct ieee80211_hw *hw = rtwdev->hw; 5194 struct rtw89_efuse *efuse = &rtwdev->efuse; 5195 struct rtw89_hal *hal = &rtwdev->hal; 5196 int ret; 5197 int tx_headroom = IEEE80211_HT_CTL_LEN; 5198 5199 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n); 5200 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n); 5201 hw->txq_data_size = sizeof(struct rtw89_txq); 5202 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 5203 5204 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 5205 5206 hw->extra_tx_headroom = tx_headroom; 5207 hw->queues = IEEE80211_NUM_ACS; 5208 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 5209 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 5210 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 5211 5212 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC | 5213 IEEE80211_RADIOTAP_MCS_HAVE_STBC; 5214 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC; 5215 5216 ieee80211_hw_set(hw, SIGNAL_DBM); 5217 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 5218 ieee80211_hw_set(hw, MFP_CAPABLE); 5219 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 5220 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 5221 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 5222 ieee80211_hw_set(hw, TX_AMSDU); 5223 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 5224 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 5225 ieee80211_hw_set(hw, SUPPORTS_PS); 5226 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 5227 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 5228 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 5229 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 5230 5231 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 5232 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 5233 5234 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 5235 ieee80211_hw_set(hw, CONNECTION_MONITOR); 5236 5237 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw)) 5238 ieee80211_hw_set(hw, AP_LINK_PS); 5239 5240 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 5241 BIT(NL80211_IFTYPE_AP) | 5242 BIT(NL80211_IFTYPE_P2P_CLIENT) | 5243 BIT(NL80211_IFTYPE_P2P_GO); 5244 5245 if (hal->ant_diversity) { 5246 hw->wiphy->available_antennas_tx = 0x3; 5247 hw->wiphy->available_antennas_rx = 0x3; 5248 } else { 5249 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 5250 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 5251 } 5252 5253 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 5254 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 5255 WIPHY_FLAG_AP_UAPSD | 5256 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 5257 5258 if (!chip->support_rnr) 5259 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 5260 5261 if (chip->chip_gen == RTW89_CHIP_BE) 5262 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 5263 5264 if (rtwdev->support_mlo) 5265 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO; 5266 5267 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 5268 5269 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5270 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 5271 5272 #ifdef CONFIG_PM 5273 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 5274 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 5275 #endif 5276 5277 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5278 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 5279 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5280 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 5281 hw->wiphy->max_remain_on_channel_duration = 1000; 5282 5283 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 5284 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 5285 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 5286 5287 ret = rtw89_core_set_supported_band(rtwdev); 5288 if (ret) { 5289 rtw89_err(rtwdev, "failed to set supported band\n"); 5290 return ret; 5291 } 5292 5293 ret = rtw89_regd_setup(rtwdev); 5294 if (ret) { 5295 rtw89_err(rtwdev, "failed to set up regd\n"); 5296 goto err_free_supported_band; 5297 } 5298 5299 hw->wiphy->sar_capa = &rtw89_sar_capa; 5300 5301 ret = ieee80211_register_hw(hw); 5302 if (ret) { 5303 rtw89_err(rtwdev, "failed to register hw\n"); 5304 goto err_free_supported_band; 5305 } 5306 5307 ret = rtw89_regd_init_hint(rtwdev); 5308 if (ret) { 5309 rtw89_err(rtwdev, "failed to init regd\n"); 5310 goto err_unregister_hw; 5311 } 5312 5313 rtw89_rfkill_polling_init(rtwdev); 5314 5315 return 0; 5316 5317 err_unregister_hw: 5318 ieee80211_unregister_hw(hw); 5319 err_free_supported_band: 5320 rtw89_core_clr_supported_band(rtwdev); 5321 5322 return ret; 5323 } 5324 5325 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 5326 { 5327 struct ieee80211_hw *hw = rtwdev->hw; 5328 5329 rtw89_rfkill_polling_deinit(rtwdev); 5330 ieee80211_unregister_hw(hw); 5331 rtw89_core_clr_supported_band(rtwdev); 5332 } 5333 5334 int rtw89_core_register(struct rtw89_dev *rtwdev) 5335 { 5336 int ret; 5337 5338 ret = rtw89_core_register_hw(rtwdev); 5339 if (ret) { 5340 rtw89_err(rtwdev, "failed to register core hw\n"); 5341 return ret; 5342 } 5343 5344 rtw89_debugfs_init(rtwdev); 5345 5346 return 0; 5347 } 5348 EXPORT_SYMBOL(rtw89_core_register); 5349 5350 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 5351 { 5352 rtw89_core_unregister_hw(rtwdev); 5353 5354 rtw89_debugfs_deinit(rtwdev); 5355 } 5356 EXPORT_SYMBOL(rtw89_core_unregister); 5357 5358 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 5359 u32 bus_data_size, 5360 const struct rtw89_chip_info *chip, 5361 const struct rtw89_chip_variant *variant) 5362 { 5363 struct rtw89_fw_info early_fw = {}; 5364 const struct firmware *firmware; 5365 struct ieee80211_hw *hw; 5366 struct rtw89_dev *rtwdev; 5367 struct ieee80211_ops *ops; 5368 u32 driver_data_size; 5369 int fw_format = -1; 5370 bool support_mlo; 5371 bool no_chanctx; 5372 5373 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 5374 5375 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 5376 if (!ops) 5377 goto err; 5378 5379 no_chanctx = chip->support_chanctx_num == 0 || 5380 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 5381 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 5382 5383 if (no_chanctx) { 5384 ops->add_chanctx = ieee80211_emulate_add_chanctx; 5385 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 5386 ops->change_chanctx = ieee80211_emulate_change_chanctx; 5387 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 5388 ops->assign_vif_chanctx = NULL; 5389 ops->unassign_vif_chanctx = NULL; 5390 ops->remain_on_channel = NULL; 5391 ops->cancel_remain_on_channel = NULL; 5392 } 5393 5394 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 5395 hw = ieee80211_alloc_hw(driver_data_size, ops); 5396 if (!hw) 5397 goto err; 5398 5399 /* TODO: When driver MLO arch. is done, determine whether to support MLO 5400 * according to the following conditions. 5401 * 1. run with chanctx_ops 5402 * 2. chip->support_link_num != 0 5403 * 3. FW feature supports AP_LINK_PS 5404 */ 5405 support_mlo = false; 5406 5407 hw->wiphy->iface_combinations = rtw89_iface_combs; 5408 5409 if (no_chanctx || chip->support_chanctx_num == 1) 5410 hw->wiphy->n_iface_combinations = 1; 5411 else 5412 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 5413 5414 rtwdev = hw->priv; 5415 rtwdev->hw = hw; 5416 rtwdev->dev = device; 5417 rtwdev->ops = ops; 5418 rtwdev->chip = chip; 5419 rtwdev->variant = variant; 5420 rtwdev->fw.req.firmware = firmware; 5421 rtwdev->fw.fw_format = fw_format; 5422 rtwdev->support_mlo = support_mlo; 5423 5424 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n", 5425 no_chanctx ? "without" : "with"); 5426 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n", 5427 support_mlo ? "with" : "without"); 5428 5429 return rtwdev; 5430 5431 err: 5432 kfree(ops); 5433 release_firmware(firmware); 5434 return NULL; 5435 } 5436 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 5437 5438 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 5439 { 5440 kfree(rtwdev->ops); 5441 kfree(rtwdev->rfe_data); 5442 release_firmware(rtwdev->fw.req.firmware); 5443 ieee80211_free_hw(rtwdev->hw); 5444 } 5445 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 5446 5447 MODULE_AUTHOR("Realtek Corporation"); 5448 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 5449 MODULE_LICENSE("Dual BSD/GPL"); 5450