1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 #include <linux/ip.h> 5 #include <linux/udp.h> 6 7 #include "cam.h" 8 #include "chan.h" 9 #include "coex.h" 10 #include "core.h" 11 #include "efuse.h" 12 #include "fw.h" 13 #include "mac.h" 14 #include "phy.h" 15 #include "ps.h" 16 #include "reg.h" 17 #include "sar.h" 18 #include "ser.h" 19 #include "txrx.h" 20 #include "util.h" 21 #include "wow.h" 22 23 static bool rtw89_disable_ps_mode; 24 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644); 25 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode"); 26 27 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \ 28 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, } 29 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \ 30 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ) 31 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \ 32 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ) 33 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \ 34 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ) 35 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \ 36 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ) 37 38 static struct ieee80211_channel rtw89_channels_2ghz[] = { 39 RTW89_DEF_CHAN_2G(2412, 1), 40 RTW89_DEF_CHAN_2G(2417, 2), 41 RTW89_DEF_CHAN_2G(2422, 3), 42 RTW89_DEF_CHAN_2G(2427, 4), 43 RTW89_DEF_CHAN_2G(2432, 5), 44 RTW89_DEF_CHAN_2G(2437, 6), 45 RTW89_DEF_CHAN_2G(2442, 7), 46 RTW89_DEF_CHAN_2G(2447, 8), 47 RTW89_DEF_CHAN_2G(2452, 9), 48 RTW89_DEF_CHAN_2G(2457, 10), 49 RTW89_DEF_CHAN_2G(2462, 11), 50 RTW89_DEF_CHAN_2G(2467, 12), 51 RTW89_DEF_CHAN_2G(2472, 13), 52 RTW89_DEF_CHAN_2G(2484, 14), 53 }; 54 55 static struct ieee80211_channel rtw89_channels_5ghz[] = { 56 RTW89_DEF_CHAN_5G(5180, 36), 57 RTW89_DEF_CHAN_5G(5200, 40), 58 RTW89_DEF_CHAN_5G(5220, 44), 59 RTW89_DEF_CHAN_5G(5240, 48), 60 RTW89_DEF_CHAN_5G(5260, 52), 61 RTW89_DEF_CHAN_5G(5280, 56), 62 RTW89_DEF_CHAN_5G(5300, 60), 63 RTW89_DEF_CHAN_5G(5320, 64), 64 RTW89_DEF_CHAN_5G(5500, 100), 65 RTW89_DEF_CHAN_5G(5520, 104), 66 RTW89_DEF_CHAN_5G(5540, 108), 67 RTW89_DEF_CHAN_5G(5560, 112), 68 RTW89_DEF_CHAN_5G(5580, 116), 69 RTW89_DEF_CHAN_5G(5600, 120), 70 RTW89_DEF_CHAN_5G(5620, 124), 71 RTW89_DEF_CHAN_5G(5640, 128), 72 RTW89_DEF_CHAN_5G(5660, 132), 73 RTW89_DEF_CHAN_5G(5680, 136), 74 RTW89_DEF_CHAN_5G(5700, 140), 75 RTW89_DEF_CHAN_5G(5720, 144), 76 RTW89_DEF_CHAN_5G(5745, 149), 77 RTW89_DEF_CHAN_5G(5765, 153), 78 RTW89_DEF_CHAN_5G(5785, 157), 79 RTW89_DEF_CHAN_5G(5805, 161), 80 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165), 81 RTW89_DEF_CHAN_5G(5845, 169), 82 RTW89_DEF_CHAN_5G(5865, 173), 83 RTW89_DEF_CHAN_5G(5885, 177), 84 }; 85 86 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM == 87 ARRAY_SIZE(rtw89_channels_5ghz)); 88 89 static struct ieee80211_channel rtw89_channels_6ghz[] = { 90 RTW89_DEF_CHAN_6G(5955, 1), 91 RTW89_DEF_CHAN_6G(5975, 5), 92 RTW89_DEF_CHAN_6G(5995, 9), 93 RTW89_DEF_CHAN_6G(6015, 13), 94 RTW89_DEF_CHAN_6G(6035, 17), 95 RTW89_DEF_CHAN_6G(6055, 21), 96 RTW89_DEF_CHAN_6G(6075, 25), 97 RTW89_DEF_CHAN_6G(6095, 29), 98 RTW89_DEF_CHAN_6G(6115, 33), 99 RTW89_DEF_CHAN_6G(6135, 37), 100 RTW89_DEF_CHAN_6G(6155, 41), 101 RTW89_DEF_CHAN_6G(6175, 45), 102 RTW89_DEF_CHAN_6G(6195, 49), 103 RTW89_DEF_CHAN_6G(6215, 53), 104 RTW89_DEF_CHAN_6G(6235, 57), 105 RTW89_DEF_CHAN_6G(6255, 61), 106 RTW89_DEF_CHAN_6G(6275, 65), 107 RTW89_DEF_CHAN_6G(6295, 69), 108 RTW89_DEF_CHAN_6G(6315, 73), 109 RTW89_DEF_CHAN_6G(6335, 77), 110 RTW89_DEF_CHAN_6G(6355, 81), 111 RTW89_DEF_CHAN_6G(6375, 85), 112 RTW89_DEF_CHAN_6G(6395, 89), 113 RTW89_DEF_CHAN_6G(6415, 93), 114 RTW89_DEF_CHAN_6G(6435, 97), 115 RTW89_DEF_CHAN_6G(6455, 101), 116 RTW89_DEF_CHAN_6G(6475, 105), 117 RTW89_DEF_CHAN_6G(6495, 109), 118 RTW89_DEF_CHAN_6G(6515, 113), 119 RTW89_DEF_CHAN_6G(6535, 117), 120 RTW89_DEF_CHAN_6G(6555, 121), 121 RTW89_DEF_CHAN_6G(6575, 125), 122 RTW89_DEF_CHAN_6G(6595, 129), 123 RTW89_DEF_CHAN_6G(6615, 133), 124 RTW89_DEF_CHAN_6G(6635, 137), 125 RTW89_DEF_CHAN_6G(6655, 141), 126 RTW89_DEF_CHAN_6G(6675, 145), 127 RTW89_DEF_CHAN_6G(6695, 149), 128 RTW89_DEF_CHAN_6G(6715, 153), 129 RTW89_DEF_CHAN_6G(6735, 157), 130 RTW89_DEF_CHAN_6G(6755, 161), 131 RTW89_DEF_CHAN_6G(6775, 165), 132 RTW89_DEF_CHAN_6G(6795, 169), 133 RTW89_DEF_CHAN_6G(6815, 173), 134 RTW89_DEF_CHAN_6G(6835, 177), 135 RTW89_DEF_CHAN_6G(6855, 181), 136 RTW89_DEF_CHAN_6G(6875, 185), 137 RTW89_DEF_CHAN_6G(6895, 189), 138 RTW89_DEF_CHAN_6G(6915, 193), 139 RTW89_DEF_CHAN_6G(6935, 197), 140 RTW89_DEF_CHAN_6G(6955, 201), 141 RTW89_DEF_CHAN_6G(6975, 205), 142 RTW89_DEF_CHAN_6G(6995, 209), 143 RTW89_DEF_CHAN_6G(7015, 213), 144 RTW89_DEF_CHAN_6G(7035, 217), 145 RTW89_DEF_CHAN_6G(7055, 221), 146 RTW89_DEF_CHAN_6G(7075, 225), 147 RTW89_DEF_CHAN_6G(7095, 229), 148 RTW89_DEF_CHAN_6G(7115, 233), 149 }; 150 151 static struct ieee80211_rate rtw89_bitrates[] = { 152 { .bitrate = 10, .hw_value = 0x00, }, 153 { .bitrate = 20, .hw_value = 0x01, }, 154 { .bitrate = 55, .hw_value = 0x02, }, 155 { .bitrate = 110, .hw_value = 0x03, }, 156 { .bitrate = 60, .hw_value = 0x04, }, 157 { .bitrate = 90, .hw_value = 0x05, }, 158 { .bitrate = 120, .hw_value = 0x06, }, 159 { .bitrate = 180, .hw_value = 0x07, }, 160 { .bitrate = 240, .hw_value = 0x08, }, 161 { .bitrate = 360, .hw_value = 0x09, }, 162 { .bitrate = 480, .hw_value = 0x0a, }, 163 { .bitrate = 540, .hw_value = 0x0b, }, 164 }; 165 166 static const struct ieee80211_iface_limit rtw89_iface_limits[] = { 167 { 168 .max = 1, 169 .types = BIT(NL80211_IFTYPE_STATION), 170 }, 171 { 172 .max = 1, 173 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 174 BIT(NL80211_IFTYPE_P2P_GO) | 175 BIT(NL80211_IFTYPE_AP), 176 }, 177 }; 178 179 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = { 180 { 181 .max = 1, 182 .types = BIT(NL80211_IFTYPE_STATION), 183 }, 184 { 185 .max = 1, 186 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) | 187 BIT(NL80211_IFTYPE_P2P_GO), 188 }, 189 }; 190 191 static const struct ieee80211_iface_combination rtw89_iface_combs[] = { 192 { 193 .limits = rtw89_iface_limits, 194 .n_limits = ARRAY_SIZE(rtw89_iface_limits), 195 .max_interfaces = 2, 196 .num_different_channels = 1, 197 }, 198 { 199 .limits = rtw89_iface_limits_mcc, 200 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc), 201 .max_interfaces = 2, 202 .num_different_channels = 2, 203 }, 204 }; 205 206 bool rtw89_ra_report_to_bitrate(struct rtw89_dev *rtwdev, u8 rpt_rate, u16 *bitrate) 207 { 208 struct ieee80211_rate rate; 209 210 if (unlikely(rpt_rate >= ARRAY_SIZE(rtw89_bitrates))) { 211 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rpt rate %d\n", rpt_rate); 212 return false; 213 } 214 215 rate = rtw89_bitrates[rpt_rate]; 216 *bitrate = rate.bitrate; 217 218 return true; 219 } 220 221 static const struct ieee80211_supported_band rtw89_sband_2ghz = { 222 .band = NL80211_BAND_2GHZ, 223 .channels = rtw89_channels_2ghz, 224 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz), 225 .bitrates = rtw89_bitrates, 226 .n_bitrates = ARRAY_SIZE(rtw89_bitrates), 227 .ht_cap = {0}, 228 .vht_cap = {0}, 229 }; 230 231 static const struct ieee80211_supported_band rtw89_sband_5ghz = { 232 .band = NL80211_BAND_5GHZ, 233 .channels = rtw89_channels_5ghz, 234 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz), 235 236 /* 5G has no CCK rates, 1M/2M/5.5M/11M */ 237 .bitrates = rtw89_bitrates + 4, 238 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 239 .ht_cap = {0}, 240 .vht_cap = {0}, 241 }; 242 243 static const struct ieee80211_supported_band rtw89_sband_6ghz = { 244 .band = NL80211_BAND_6GHZ, 245 .channels = rtw89_channels_6ghz, 246 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz), 247 248 /* 6G has no CCK rates, 1M/2M/5.5M/11M */ 249 .bitrates = rtw89_bitrates + 4, 250 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4, 251 }; 252 253 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev, 254 struct rtw89_traffic_stats *stats, 255 struct sk_buff *skb, bool tx) 256 { 257 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 258 259 if (tx && ieee80211_is_assoc_req(hdr->frame_control)) 260 rtw89_wow_parse_akm(rtwdev, skb); 261 262 if (!ieee80211_is_data(hdr->frame_control)) 263 return; 264 265 if (is_broadcast_ether_addr(hdr->addr1) || 266 is_multicast_ether_addr(hdr->addr1)) 267 return; 268 269 if (tx) { 270 stats->tx_cnt++; 271 stats->tx_unicast += skb->len; 272 } else { 273 stats->rx_cnt++; 274 stats->rx_unicast += skb->len; 275 } 276 } 277 278 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef) 279 { 280 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0], 281 NL80211_CHAN_NO_HT); 282 } 283 284 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef, 285 struct rtw89_chan *chan) 286 { 287 struct ieee80211_channel *channel = chandef->chan; 288 enum nl80211_chan_width width = chandef->width; 289 u32 primary_freq, center_freq; 290 u8 center_chan; 291 u8 bandwidth = RTW89_CHANNEL_WIDTH_20; 292 u32 offset; 293 u8 band; 294 295 center_chan = channel->hw_value; 296 primary_freq = channel->center_freq; 297 center_freq = chandef->center_freq1; 298 299 switch (width) { 300 case NL80211_CHAN_WIDTH_20_NOHT: 301 case NL80211_CHAN_WIDTH_20: 302 bandwidth = RTW89_CHANNEL_WIDTH_20; 303 break; 304 case NL80211_CHAN_WIDTH_40: 305 bandwidth = RTW89_CHANNEL_WIDTH_40; 306 if (primary_freq > center_freq) { 307 center_chan -= 2; 308 } else { 309 center_chan += 2; 310 } 311 break; 312 case NL80211_CHAN_WIDTH_80: 313 case NL80211_CHAN_WIDTH_160: 314 bandwidth = nl_to_rtw89_bandwidth(width); 315 if (primary_freq > center_freq) { 316 offset = (primary_freq - center_freq - 10) / 20; 317 center_chan -= 2 + offset * 4; 318 } else { 319 offset = (center_freq - primary_freq - 10) / 20; 320 center_chan += 2 + offset * 4; 321 } 322 break; 323 default: 324 center_chan = 0; 325 break; 326 } 327 328 switch (channel->band) { 329 default: 330 case NL80211_BAND_2GHZ: 331 band = RTW89_BAND_2G; 332 break; 333 case NL80211_BAND_5GHZ: 334 band = RTW89_BAND_5G; 335 break; 336 case NL80211_BAND_6GHZ: 337 band = RTW89_BAND_6G; 338 break; 339 } 340 341 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth); 342 } 343 344 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev) 345 { 346 struct rtw89_hal *hal = &rtwdev->hal; 347 const struct rtw89_chip_info *chip = rtwdev->chip; 348 const struct rtw89_chan *chan; 349 enum rtw89_sub_entity_idx sub_entity_idx; 350 enum rtw89_sub_entity_idx roc_idx; 351 enum rtw89_phy_idx phy_idx; 352 enum rtw89_entity_mode mode; 353 bool entity_active; 354 355 entity_active = rtw89_get_entity_state(rtwdev); 356 if (!entity_active) 357 return; 358 359 mode = rtw89_get_entity_mode(rtwdev); 360 switch (mode) { 361 case RTW89_ENTITY_MODE_SCC: 362 case RTW89_ENTITY_MODE_MCC: 363 sub_entity_idx = RTW89_SUB_ENTITY_0; 364 break; 365 case RTW89_ENTITY_MODE_MCC_PREPARE: 366 sub_entity_idx = RTW89_SUB_ENTITY_1; 367 break; 368 default: 369 WARN(1, "Invalid ent mode: %d\n", mode); 370 return; 371 } 372 373 roc_idx = atomic_read(&hal->roc_entity_idx); 374 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 375 sub_entity_idx = roc_idx; 376 377 phy_idx = RTW89_PHY_0; 378 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 379 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 380 } 381 382 int rtw89_set_channel(struct rtw89_dev *rtwdev) 383 { 384 struct rtw89_hal *hal = &rtwdev->hal; 385 const struct rtw89_chip_info *chip = rtwdev->chip; 386 const struct rtw89_chan_rcd *chan_rcd; 387 const struct rtw89_chan *chan; 388 enum rtw89_sub_entity_idx sub_entity_idx; 389 enum rtw89_sub_entity_idx roc_idx; 390 enum rtw89_mac_idx mac_idx; 391 enum rtw89_phy_idx phy_idx; 392 struct rtw89_channel_help_params bak; 393 enum rtw89_entity_mode mode; 394 bool entity_active; 395 396 entity_active = rtw89_get_entity_state(rtwdev); 397 398 mode = rtw89_entity_recalc(rtwdev); 399 switch (mode) { 400 case RTW89_ENTITY_MODE_SCC: 401 case RTW89_ENTITY_MODE_MCC: 402 sub_entity_idx = RTW89_SUB_ENTITY_0; 403 break; 404 case RTW89_ENTITY_MODE_MCC_PREPARE: 405 sub_entity_idx = RTW89_SUB_ENTITY_1; 406 break; 407 default: 408 WARN(1, "Invalid ent mode: %d\n", mode); 409 return -EINVAL; 410 } 411 412 roc_idx = atomic_read(&hal->roc_entity_idx); 413 if (roc_idx != RTW89_SUB_ENTITY_IDLE) 414 sub_entity_idx = roc_idx; 415 416 mac_idx = RTW89_MAC_0; 417 phy_idx = RTW89_PHY_0; 418 419 chan = rtw89_chan_get(rtwdev, sub_entity_idx); 420 chan_rcd = rtw89_chan_rcd_get(rtwdev, sub_entity_idx); 421 422 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx); 423 424 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx); 425 426 chip->ops->set_txpwr(rtwdev, chan, phy_idx); 427 428 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx); 429 430 if (!entity_active || chan_rcd->band_changed) { 431 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type); 432 rtw89_chip_rfk_band_changed(rtwdev, phy_idx); 433 } 434 435 rtw89_set_entity_state(rtwdev, true); 436 return 0; 437 } 438 439 void rtw89_get_channel(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 440 struct rtw89_chan *chan) 441 { 442 const struct cfg80211_chan_def *chandef; 443 444 chandef = rtw89_chandef_get(rtwdev, rtwvif->sub_entity_idx); 445 rtw89_get_channel_params(chandef, chan); 446 } 447 448 static enum rtw89_core_tx_type 449 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev, 450 struct sk_buff *skb) 451 { 452 struct ieee80211_hdr *hdr = (void *)skb->data; 453 __le16 fc = hdr->frame_control; 454 455 if (ieee80211_is_mgmt(fc) || ieee80211_is_nullfunc(fc)) 456 return RTW89_CORE_TX_TYPE_MGMT; 457 458 return RTW89_CORE_TX_TYPE_DATA; 459 } 460 461 static void 462 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev, 463 struct rtw89_core_tx_request *tx_req, 464 enum btc_pkt_type pkt_type) 465 { 466 struct ieee80211_sta *sta = tx_req->sta; 467 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 468 struct sk_buff *skb = tx_req->skb; 469 struct rtw89_sta *rtwsta; 470 u8 ampdu_num; 471 u8 tid; 472 473 if (pkt_type == PACKET_EAPOL) { 474 desc_info->bk = true; 475 return; 476 } 477 478 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU)) 479 return; 480 481 if (!sta) { 482 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n"); 483 return; 484 } 485 486 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 487 rtwsta = (struct rtw89_sta *)sta->drv_priv; 488 489 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ? 490 rtwsta->ampdu_params[tid].agg_num : 491 4 << sta->deflink.ht_cap.ampdu_factor) - 1); 492 493 desc_info->agg_en = true; 494 desc_info->ampdu_density = sta->deflink.ht_cap.ampdu_density; 495 desc_info->ampdu_num = ampdu_num; 496 } 497 498 static void 499 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev, 500 struct rtw89_core_tx_request *tx_req) 501 { 502 const struct rtw89_chip_info *chip = rtwdev->chip; 503 struct ieee80211_vif *vif = tx_req->vif; 504 struct ieee80211_sta *sta = tx_req->sta; 505 struct ieee80211_tx_info *info; 506 struct ieee80211_key_conf *key; 507 struct rtw89_vif *rtwvif; 508 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 509 struct rtw89_addr_cam_entry *addr_cam; 510 struct rtw89_sec_cam_entry *sec_cam; 511 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 512 struct sk_buff *skb = tx_req->skb; 513 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE; 514 u64 pn64; 515 516 if (!vif) { 517 rtw89_warn(rtwdev, "cannot set sec key without vif\n"); 518 return; 519 } 520 521 rtwvif = (struct rtw89_vif *)vif->drv_priv; 522 addr_cam = rtw89_get_addr_cam_of(rtwvif, rtwsta); 523 524 info = IEEE80211_SKB_CB(skb); 525 key = info->control.hw_key; 526 sec_cam = addr_cam->sec_entries[key->hw_key_idx]; 527 if (!sec_cam) { 528 rtw89_warn(rtwdev, "sec cam entry is empty\n"); 529 return; 530 } 531 532 switch (key->cipher) { 533 case WLAN_CIPHER_SUITE_WEP40: 534 sec_type = RTW89_SEC_KEY_TYPE_WEP40; 535 break; 536 case WLAN_CIPHER_SUITE_WEP104: 537 sec_type = RTW89_SEC_KEY_TYPE_WEP104; 538 break; 539 case WLAN_CIPHER_SUITE_TKIP: 540 sec_type = RTW89_SEC_KEY_TYPE_TKIP; 541 break; 542 case WLAN_CIPHER_SUITE_CCMP: 543 sec_type = RTW89_SEC_KEY_TYPE_CCMP128; 544 break; 545 case WLAN_CIPHER_SUITE_CCMP_256: 546 sec_type = RTW89_SEC_KEY_TYPE_CCMP256; 547 break; 548 case WLAN_CIPHER_SUITE_GCMP: 549 sec_type = RTW89_SEC_KEY_TYPE_GCMP128; 550 break; 551 case WLAN_CIPHER_SUITE_GCMP_256: 552 sec_type = RTW89_SEC_KEY_TYPE_GCMP256; 553 break; 554 default: 555 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher); 556 return; 557 } 558 559 desc_info->sec_en = true; 560 desc_info->sec_keyid = key->keyidx; 561 desc_info->sec_type = sec_type; 562 desc_info->sec_cam_idx = sec_cam->sec_cam_idx; 563 564 if (!chip->hw_sec_hdr) 565 return; 566 567 pn64 = atomic64_inc_return(&key->tx_pn); 568 desc_info->sec_seq[0] = pn64; 569 desc_info->sec_seq[1] = pn64 >> 8; 570 desc_info->sec_seq[2] = pn64 >> 16; 571 desc_info->sec_seq[3] = pn64 >> 24; 572 desc_info->sec_seq[4] = pn64 >> 32; 573 desc_info->sec_seq[5] = pn64 >> 40; 574 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */ 575 } 576 577 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev, 578 struct rtw89_core_tx_request *tx_req, 579 const struct rtw89_chan *chan) 580 { 581 struct sk_buff *skb = tx_req->skb; 582 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 583 struct ieee80211_vif *vif = tx_info->control.vif; 584 u16 lowest_rate; 585 586 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE || 587 (vif && vif->p2p)) 588 lowest_rate = RTW89_HW_RATE_OFDM6; 589 else if (chan->band_type == RTW89_BAND_2G) 590 lowest_rate = RTW89_HW_RATE_CCK1; 591 else 592 lowest_rate = RTW89_HW_RATE_OFDM6; 593 594 if (!vif || !vif->bss_conf.basic_rates || !tx_req->sta) 595 return lowest_rate; 596 597 return __ffs(vif->bss_conf.basic_rates) + lowest_rate; 598 } 599 600 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev, 601 struct rtw89_core_tx_request *tx_req) 602 { 603 struct ieee80211_vif *vif = tx_req->vif; 604 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 605 struct ieee80211_sta *sta = tx_req->sta; 606 struct rtw89_sta *rtwsta; 607 608 if (!sta) 609 return rtwvif->mac_id; 610 611 rtwsta = (struct rtw89_sta *)sta->drv_priv; 612 return rtwsta->mac_id; 613 } 614 615 static void 616 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev, 617 struct rtw89_core_tx_request *tx_req) 618 { 619 struct ieee80211_vif *vif = tx_req->vif; 620 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 621 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 622 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 623 rtwvif->sub_entity_idx); 624 u8 qsel, ch_dma; 625 626 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : RTW89_TX_QSEL_B0_MGMT; 627 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 628 629 desc_info->qsel = qsel; 630 desc_info->ch_dma = ch_dma; 631 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 632 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 633 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL; 634 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE; 635 636 /* fixed data rate for mgmt frames */ 637 desc_info->en_wd_info = true; 638 desc_info->use_rate = true; 639 desc_info->dis_data_fb = true; 640 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan); 641 642 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 643 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n", 644 desc_info->data_rate, chan->channel, chan->band_type, 645 chan->band_width); 646 } 647 648 static void 649 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev, 650 struct rtw89_core_tx_request *tx_req) 651 { 652 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 653 654 desc_info->is_bmc = false; 655 desc_info->wd_page = false; 656 desc_info->ch_dma = RTW89_DMA_H2C; 657 } 658 659 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc, 660 const struct rtw89_chan *chan) 661 { 662 static const u8 rtw89_bandwidth_to_om[] = { 663 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20, 664 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40, 665 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80, 666 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 667 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80, 668 }; 669 const struct rtw89_chip_info *chip = rtwdev->chip; 670 struct rtw89_hal *hal = &rtwdev->hal; 671 u8 om_bandwidth; 672 673 if (!chip->dis_2g_40m_ul_ofdma || 674 chan->band_type != RTW89_BAND_2G || 675 chan->band_width != RTW89_CHANNEL_WIDTH_40) 676 return; 677 678 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ? 679 rtw89_bandwidth_to_om[chan->band_width] : 0; 680 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 681 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) | 682 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) | 683 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) | 684 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) | 685 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) | 686 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) | 687 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) | 688 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS); 689 } 690 691 static bool 692 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev, 693 struct rtw89_core_tx_request *tx_req, 694 enum btc_pkt_type pkt_type) 695 { 696 struct ieee80211_sta *sta = tx_req->sta; 697 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 698 struct sk_buff *skb = tx_req->skb; 699 struct ieee80211_hdr *hdr = (void *)skb->data; 700 __le16 fc = hdr->frame_control; 701 702 /* AP IOT issue with EAPoL, ARP and DHCP */ 703 if (pkt_type < PACKET_MAX) 704 return false; 705 706 if (!sta || !sta->deflink.he_cap.has_he) 707 return false; 708 709 if (!ieee80211_is_data_qos(fc)) 710 return false; 711 712 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN) 713 return false; 714 715 if (rtwsta && rtwsta->ra_report.might_fallback_legacy) 716 return false; 717 718 return true; 719 } 720 721 static void 722 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev, 723 struct rtw89_core_tx_request *tx_req) 724 { 725 struct ieee80211_sta *sta = tx_req->sta; 726 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 727 struct sk_buff *skb = tx_req->skb; 728 struct ieee80211_hdr *hdr = (void *)skb->data; 729 __le16 fc = hdr->frame_control; 730 void *data; 731 __le32 *htc; 732 u8 *qc; 733 int hdr_len; 734 735 hdr_len = ieee80211_has_a4(fc) ? 32 : 26; 736 data = skb_push(skb, IEEE80211_HT_CTL_LEN); 737 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len); 738 739 hdr = data; 740 htc = data + hdr_len; 741 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER); 742 *htc = rtwsta->htc_template ? rtwsta->htc_template : 743 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) | 744 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID); 745 746 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN; 747 qc[0] |= IEEE80211_QOS_CTL_EOSP; 748 } 749 750 static void 751 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev, 752 struct rtw89_core_tx_request *tx_req, 753 enum btc_pkt_type pkt_type) 754 { 755 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 756 struct ieee80211_vif *vif = tx_req->vif; 757 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 758 759 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type)) 760 goto desc_bk; 761 762 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req); 763 764 desc_info->pkt_size += IEEE80211_HT_CTL_LEN; 765 desc_info->a_ctrl_bsr = true; 766 767 desc_bk: 768 if (!rtwvif || rtwvif->last_a_ctrl == desc_info->a_ctrl_bsr) 769 return; 770 771 rtwvif->last_a_ctrl = desc_info->a_ctrl_bsr; 772 desc_info->bk = true; 773 } 774 775 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev, 776 struct rtw89_core_tx_request *tx_req) 777 { 778 struct ieee80211_vif *vif = tx_req->vif; 779 struct ieee80211_sta *sta = tx_req->sta; 780 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 781 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif->rate_pattern; 782 enum rtw89_sub_entity_idx idx = rtwvif->sub_entity_idx; 783 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx); 784 u16 lowest_rate; 785 786 if (rate_pattern->enable) 787 return rate_pattern->rate; 788 789 if (vif->p2p) 790 lowest_rate = RTW89_HW_RATE_OFDM6; 791 else if (chan->band_type == RTW89_BAND_2G) 792 lowest_rate = RTW89_HW_RATE_CCK1; 793 else 794 lowest_rate = RTW89_HW_RATE_OFDM6; 795 796 if (!sta || !sta->deflink.supp_rates[chan->band_type]) 797 return lowest_rate; 798 799 return __ffs(sta->deflink.supp_rates[chan->band_type]) + lowest_rate; 800 } 801 802 static void 803 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev, 804 struct rtw89_core_tx_request *tx_req) 805 { 806 struct ieee80211_vif *vif = tx_req->vif; 807 struct ieee80211_sta *sta = tx_req->sta; 808 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 809 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 810 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 811 struct sk_buff *skb = tx_req->skb; 812 u8 tid, tid_indicate; 813 u8 qsel, ch_dma; 814 815 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK; 816 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid); 817 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid); 818 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 819 820 desc_info->ch_dma = ch_dma; 821 desc_info->tid_indicate = tid_indicate; 822 desc_info->qsel = qsel; 823 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req); 824 desc_info->port = desc_info->hiq ? rtwvif->port : 0; 825 desc_info->er_cap = rtwsta ? rtwsta->er_cap : false; 826 827 /* enable wd_info for AMPDU */ 828 desc_info->en_wd_info = true; 829 830 if (IEEE80211_SKB_CB(skb)->control.hw_key) 831 rtw89_core_tx_update_sec_key(rtwdev, tx_req); 832 833 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req); 834 } 835 836 static enum btc_pkt_type 837 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev, 838 struct rtw89_core_tx_request *tx_req) 839 { 840 struct sk_buff *skb = tx_req->skb; 841 struct udphdr *udphdr; 842 843 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) { 844 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.eapol_notify_work); 845 return PACKET_EAPOL; 846 } 847 848 if (skb->protocol == htons(ETH_P_ARP)) { 849 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.arp_notify_work); 850 return PACKET_ARP; 851 } 852 853 if (skb->protocol == htons(ETH_P_IP) && 854 ip_hdr(skb)->protocol == IPPROTO_UDP) { 855 udphdr = udp_hdr(skb); 856 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) || 857 (udphdr->source == htons(68) && udphdr->dest == htons(67))) && 858 skb->len > 282) { 859 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.dhcp_notify_work); 860 return PACKET_DHCP; 861 } 862 } 863 864 if (skb->protocol == htons(ETH_P_IP) && 865 ip_hdr(skb)->protocol == IPPROTO_ICMP) { 866 ieee80211_queue_work(rtwdev->hw, &rtwdev->btc.icmp_notify_work); 867 return PACKET_ICMP; 868 } 869 870 return PACKET_MAX; 871 } 872 873 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev, 874 struct rtw89_tx_desc_info *desc_info, 875 struct sk_buff *skb) 876 { 877 struct ieee80211_hdr *hdr = (void *)skb->data; 878 __le16 fc = hdr->frame_control; 879 880 desc_info->hdr_llc_len = ieee80211_hdrlen(fc); 881 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */ 882 } 883 884 static void 885 rtw89_core_tx_wake(struct rtw89_dev *rtwdev, 886 struct rtw89_core_tx_request *tx_req) 887 { 888 const struct rtw89_chip_info *chip = rtwdev->chip; 889 890 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw)) 891 return; 892 893 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags)) 894 return; 895 896 if (chip->chip_id != RTL8852C && 897 tx_req->tx_type != RTW89_CORE_TX_TYPE_MGMT) 898 return; 899 900 rtw89_mac_notify_wake(rtwdev); 901 } 902 903 static void 904 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev, 905 struct rtw89_core_tx_request *tx_req) 906 { 907 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info; 908 struct sk_buff *skb = tx_req->skb; 909 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 910 struct ieee80211_hdr *hdr = (void *)skb->data; 911 enum rtw89_core_tx_type tx_type; 912 enum btc_pkt_type pkt_type; 913 bool is_bmc; 914 u16 seq; 915 916 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4; 917 if (tx_req->tx_type != RTW89_CORE_TX_TYPE_FWCMD) { 918 tx_type = rtw89_core_get_tx_type(rtwdev, skb); 919 tx_req->tx_type = tx_type; 920 } 921 is_bmc = (is_broadcast_ether_addr(hdr->addr1) || 922 is_multicast_ether_addr(hdr->addr1)); 923 924 desc_info->seq = seq; 925 desc_info->pkt_size = skb->len; 926 desc_info->is_bmc = is_bmc; 927 desc_info->wd_page = true; 928 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM; 929 930 switch (tx_req->tx_type) { 931 case RTW89_CORE_TX_TYPE_MGMT: 932 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req); 933 break; 934 case RTW89_CORE_TX_TYPE_DATA: 935 rtw89_core_tx_update_data_info(rtwdev, tx_req); 936 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req); 937 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type); 938 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type); 939 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb); 940 break; 941 case RTW89_CORE_TX_TYPE_FWCMD: 942 rtw89_core_tx_update_h2c_info(rtwdev, tx_req); 943 break; 944 } 945 } 946 947 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel) 948 { 949 u8 ch_dma; 950 951 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 952 953 rtw89_hci_tx_kick_off(rtwdev, ch_dma); 954 } 955 956 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb, 957 int qsel, unsigned int timeout) 958 { 959 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb); 960 struct rtw89_tx_wait_info *wait; 961 unsigned long time_left; 962 int ret = 0; 963 964 wait = kzalloc(sizeof(*wait), GFP_KERNEL); 965 if (!wait) { 966 rtw89_core_tx_kick_off(rtwdev, qsel); 967 return 0; 968 } 969 970 init_completion(&wait->completion); 971 rcu_assign_pointer(skb_data->wait, wait); 972 973 rtw89_core_tx_kick_off(rtwdev, qsel); 974 time_left = wait_for_completion_timeout(&wait->completion, 975 msecs_to_jiffies(timeout)); 976 if (time_left == 0) 977 ret = -ETIMEDOUT; 978 else if (!wait->tx_done) 979 ret = -EAGAIN; 980 981 rcu_assign_pointer(skb_data->wait, NULL); 982 kfree_rcu(wait, rcu_head); 983 984 return ret; 985 } 986 987 int rtw89_h2c_tx(struct rtw89_dev *rtwdev, 988 struct sk_buff *skb, bool fwdl) 989 { 990 struct rtw89_core_tx_request tx_req = {0}; 991 u32 cnt; 992 int ret; 993 994 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) { 995 rtw89_debug(rtwdev, RTW89_DBG_FW, 996 "ignore h2c due to power is off with firmware state=%d\n", 997 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)); 998 dev_kfree_skb(skb); 999 return 0; 1000 } 1001 1002 tx_req.skb = skb; 1003 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD; 1004 if (fwdl) 1005 tx_req.desc_info.fw_dl = true; 1006 1007 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1008 1009 if (!fwdl) 1010 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len); 1011 1012 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12); 1013 if (cnt == 0) { 1014 rtw89_err(rtwdev, "no tx fwcmd resource\n"); 1015 return -ENOSPC; 1016 } 1017 1018 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1019 if (ret) { 1020 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1021 return ret; 1022 } 1023 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12); 1024 1025 return 0; 1026 } 1027 1028 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 1029 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel) 1030 { 1031 struct rtw89_core_tx_request tx_req = {0}; 1032 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1033 int ret; 1034 1035 tx_req.skb = skb; 1036 tx_req.sta = sta; 1037 tx_req.vif = vif; 1038 1039 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, true); 1040 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, true); 1041 rtw89_core_tx_update_desc_info(rtwdev, &tx_req); 1042 rtw89_core_tx_wake(rtwdev, &tx_req); 1043 1044 ret = rtw89_hci_tx_write(rtwdev, &tx_req); 1045 if (ret) { 1046 rtw89_err(rtwdev, "failed to transmit skb to HCI\n"); 1047 return ret; 1048 } 1049 1050 if (qsel) 1051 *qsel = tx_req.desc_info.qsel; 1052 1053 return 0; 1054 } 1055 1056 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info) 1057 { 1058 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) | 1059 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1060 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1061 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1062 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1063 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) | 1064 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) | 1065 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode); 1066 1067 return cpu_to_le32(dword); 1068 } 1069 1070 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info) 1071 { 1072 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1073 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) | 1074 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) | 1075 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1076 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) | 1077 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl); 1078 1079 return cpu_to_le32(dword); 1080 } 1081 1082 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info) 1083 { 1084 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1085 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1086 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type); 1087 1088 return cpu_to_le32(dword); 1089 } 1090 1091 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info) 1092 { 1093 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) | 1094 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) | 1095 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) | 1096 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id); 1097 1098 return cpu_to_le32(dword); 1099 } 1100 1101 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info) 1102 { 1103 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) | 1104 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) | 1105 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk); 1106 1107 return cpu_to_le32(dword); 1108 } 1109 1110 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info) 1111 { 1112 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1113 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1114 1115 return cpu_to_le32(dword); 1116 } 1117 1118 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info) 1119 { 1120 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1121 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1122 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1123 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1124 1125 return cpu_to_le32(dword); 1126 } 1127 1128 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info) 1129 { 1130 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) | 1131 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate); 1132 1133 return cpu_to_le32(dword); 1134 } 1135 1136 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info) 1137 { 1138 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) | 1139 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) | 1140 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1141 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port); 1142 1143 return cpu_to_le32(dword); 1144 } 1145 1146 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info) 1147 { 1148 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1149 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) | 1150 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) | 1151 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0); 1152 1153 return cpu_to_le32(dword); 1154 } 1155 1156 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info) 1157 { 1158 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) | 1159 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1160 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE, 1161 desc_info->data_retry_lowest_rate); 1162 1163 return cpu_to_le32(dword); 1164 } 1165 1166 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info) 1167 { 1168 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1169 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) | 1170 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) | 1171 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1172 1173 return cpu_to_le32(dword); 1174 } 1175 1176 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info) 1177 { 1178 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1179 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1180 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1181 1182 return cpu_to_le32(dword); 1183 } 1184 1185 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info) 1186 { 1187 bool rts_en = !desc_info->is_bmc; 1188 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) | 1189 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1); 1190 1191 return cpu_to_le32(dword); 1192 } 1193 1194 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev, 1195 struct rtw89_tx_desc_info *desc_info, 1196 void *txdesc) 1197 { 1198 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc; 1199 struct rtw89_txwd_info *txwd_info; 1200 1201 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info); 1202 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1203 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1204 1205 if (!desc_info->en_wd_info) 1206 return; 1207 1208 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1209 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info); 1210 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1211 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info); 1212 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1213 1214 } 1215 EXPORT_SYMBOL(rtw89_core_fill_txdesc); 1216 1217 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev, 1218 struct rtw89_tx_desc_info *desc_info, 1219 void *txdesc) 1220 { 1221 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc; 1222 struct rtw89_txwd_info *txwd_info; 1223 1224 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info); 1225 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info); 1226 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info); 1227 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info); 1228 if (desc_info->sec_en) { 1229 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info); 1230 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info); 1231 } 1232 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info); 1233 1234 if (!desc_info->en_wd_info) 1235 return; 1236 1237 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1); 1238 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info); 1239 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info); 1240 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info); 1241 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info); 1242 } 1243 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1); 1244 1245 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info) 1246 { 1247 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) | 1248 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) | 1249 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) | 1250 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) | 1251 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page); 1252 1253 return cpu_to_le32(dword); 1254 } 1255 1256 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info) 1257 { 1258 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) | 1259 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) | 1260 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type); 1261 1262 return cpu_to_le32(dword); 1263 } 1264 1265 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info) 1266 { 1267 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) | 1268 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) | 1269 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) | 1270 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) | 1271 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) | 1272 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id); 1273 1274 return cpu_to_le32(dword); 1275 } 1276 1277 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info) 1278 { 1279 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq); 1280 1281 return cpu_to_le32(dword); 1282 } 1283 1284 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info) 1285 { 1286 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) | 1287 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]); 1288 1289 return cpu_to_le32(dword); 1290 } 1291 1292 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info) 1293 { 1294 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) | 1295 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) | 1296 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) | 1297 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]); 1298 1299 return cpu_to_le32(dword); 1300 } 1301 1302 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info) 1303 { 1304 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) | 1305 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) | 1306 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) | 1307 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate); 1308 1309 return cpu_to_le32(dword); 1310 } 1311 1312 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info) 1313 { 1314 u32 dword = FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) | 1315 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port); 1316 1317 return cpu_to_le32(dword); 1318 } 1319 1320 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info) 1321 { 1322 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) | 1323 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) | 1324 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE, 1325 desc_info->data_retry_lowest_rate); 1326 1327 return cpu_to_le32(dword); 1328 } 1329 1330 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info) 1331 { 1332 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) | 1333 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) | 1334 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx); 1335 1336 return cpu_to_le32(dword); 1337 } 1338 1339 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info) 1340 { 1341 bool rts_en = !desc_info->is_bmc; 1342 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) | 1343 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1); 1344 1345 return cpu_to_le32(dword); 1346 } 1347 1348 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev, 1349 struct rtw89_tx_desc_info *desc_info, 1350 void *txdesc) 1351 { 1352 struct rtw89_txwd_body_v2 *txwd_body = txdesc; 1353 struct rtw89_txwd_info_v2 *txwd_info; 1354 1355 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info); 1356 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info); 1357 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info); 1358 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info); 1359 if (desc_info->sec_en) { 1360 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info); 1361 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info); 1362 } 1363 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info); 1364 1365 if (!desc_info->en_wd_info) 1366 return; 1367 1368 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1); 1369 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info); 1370 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info); 1371 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info); 1372 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info); 1373 } 1374 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2); 1375 1376 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info) 1377 { 1378 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1379 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1380 RTW89_CORE_RX_TYPE_FWDL : 1381 RTW89_CORE_RX_TYPE_H2C); 1382 1383 return cpu_to_le32(dword); 1384 } 1385 1386 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev, 1387 struct rtw89_tx_desc_info *desc_info, 1388 void *txdesc) 1389 { 1390 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc; 1391 1392 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info); 1393 } 1394 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1); 1395 1396 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info) 1397 { 1398 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) | 1399 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ? 1400 RTW89_CORE_RX_TYPE_FWDL : 1401 RTW89_CORE_RX_TYPE_H2C); 1402 1403 return cpu_to_le32(dword); 1404 } 1405 1406 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev, 1407 struct rtw89_tx_desc_info *desc_info, 1408 void *txdesc) 1409 { 1410 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc; 1411 1412 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info); 1413 } 1414 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2); 1415 1416 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev, 1417 struct sk_buff *skb, 1418 struct rtw89_rx_phy_ppdu *phy_ppdu) 1419 { 1420 const struct rtw89_chip_info *chip = rtwdev->chip; 1421 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data; 1422 const struct rtw89_rxinfo_user *user; 1423 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen; 1424 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE; 1425 bool rx_cnt_valid = false; 1426 bool invalid = false; 1427 u8 plcp_size = 0; 1428 u8 *phy_sts; 1429 u8 usr_num; 1430 int i; 1431 1432 if (chip_gen == RTW89_CHIP_BE) { 1433 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1); 1434 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1; 1435 } 1436 1437 if (invalid) 1438 return -EINVAL; 1439 1440 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD); 1441 if (chip_gen == RTW89_CHIP_BE) { 1442 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3; 1443 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1); 1444 } else { 1445 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3; 1446 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM); 1447 } 1448 if (usr_num > chip->ppdu_max_usr) { 1449 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n", 1450 usr_num); 1451 return -EINVAL; 1452 } 1453 1454 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set by hardware, 1455 * so update mac_id by rxinfo_user[].mac_id. 1456 */ 1457 for (i = 0; i < usr_num && chip_gen == RTW89_CHIP_BE; i++) { 1458 user = &rxinfo->user[i]; 1459 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID)) 1460 continue; 1461 1462 phy_ppdu->mac_id = 1463 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID); 1464 break; 1465 } 1466 1467 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE; 1468 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE; 1469 /* 8-byte alignment */ 1470 if (usr_num & BIT(0)) 1471 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE; 1472 if (rx_cnt_valid) 1473 phy_sts += rx_cnt_size; 1474 phy_sts += plcp_size; 1475 1476 if (phy_sts > skb->data + skb->len) 1477 return -EINVAL; 1478 1479 phy_ppdu->buf = phy_sts; 1480 phy_ppdu->len = skb->data + skb->len - phy_sts; 1481 1482 return 0; 1483 } 1484 1485 static void rtw89_core_rx_process_phy_ppdu_iter(void *data, 1486 struct ieee80211_sta *sta) 1487 { 1488 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 1489 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data; 1490 struct rtw89_dev *rtwdev = rtwsta->rtwdev; 1491 struct rtw89_hal *hal = &rtwdev->hal; 1492 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 1493 u8 ant_pos = U8_MAX; 1494 u8 evm_pos = 0; 1495 int i; 1496 1497 if (rtwsta->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self) 1498 return; 1499 1500 if (hal->ant_diversity && hal->antenna_rx) { 1501 ant_pos = __ffs(hal->antenna_rx); 1502 evm_pos = ant_pos; 1503 } 1504 1505 ewma_rssi_add(&rtwsta->avg_rssi, phy_ppdu->rssi_avg); 1506 1507 if (ant_pos < ant_num) { 1508 ewma_rssi_add(&rtwsta->rssi[ant_pos], phy_ppdu->rssi[0]); 1509 } else { 1510 for (i = 0; i < rtwdev->chip->rf_path_num; i++) 1511 ewma_rssi_add(&rtwsta->rssi[i], phy_ppdu->rssi[i]); 1512 } 1513 1514 if (phy_ppdu->ofdm.has) { 1515 ewma_snr_add(&rtwsta->avg_snr, phy_ppdu->ofdm.avg_snr); 1516 ewma_evm_add(&rtwsta->evm_min[evm_pos], phy_ppdu->ofdm.evm_min); 1517 ewma_evm_add(&rtwsta->evm_max[evm_pos], phy_ppdu->ofdm.evm_max); 1518 } 1519 } 1520 1521 #define VAR_LEN 0xff 1522 #define VAR_LEN_UNIT 8 1523 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev, 1524 const struct rtw89_phy_sts_iehdr *iehdr) 1525 { 1526 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = { 1527 [RTW89_CHIP_AX] = { 1528 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1529 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1530 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1531 }, 1532 [RTW89_CHIP_BE] = { 1533 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN, 1534 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN, 1535 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32 1536 }, 1537 }; 1538 const u8 *physts_ie_len_tab; 1539 u16 ie_len; 1540 u8 ie; 1541 1542 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen]; 1543 1544 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1545 if (physts_ie_len_tab[ie] != VAR_LEN) 1546 ie_len = physts_ie_len_tab[ie]; 1547 else 1548 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT; 1549 1550 return ie_len; 1551 } 1552 1553 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev, 1554 const struct rtw89_phy_sts_iehdr *iehdr, 1555 struct rtw89_rx_phy_ppdu *phy_ppdu) 1556 { 1557 const struct rtw89_phy_sts_ie0 *ie = (const struct rtw89_phy_sts_ie0 *)iehdr; 1558 s16 cfo; 1559 u32 t; 1560 1561 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX); 1562 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6) 1563 return; 1564 1565 if (!phy_ppdu->to_self) 1566 return; 1567 1568 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR); 1569 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX); 1570 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN); 1571 phy_ppdu->ofdm.has = true; 1572 1573 /* sign conversion for S(12,2) */ 1574 if (rtwdev->chip->cfo_src_fd) { 1575 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO); 1576 cfo = sign_extend32(t, 11); 1577 } else { 1578 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO); 1579 cfo = sign_extend32(t, 11); 1580 } 1581 1582 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu); 1583 } 1584 1585 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev, 1586 const struct rtw89_phy_sts_iehdr *iehdr, 1587 struct rtw89_rx_phy_ppdu *phy_ppdu) 1588 { 1589 u8 ie; 1590 1591 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE); 1592 1593 switch (ie) { 1594 case RTW89_PHYSTS_IE01_CMN_OFDM: 1595 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu); 1596 break; 1597 default: 1598 break; 1599 } 1600 1601 return 0; 1602 } 1603 1604 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu) 1605 { 1606 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1607 u8 *rssi = phy_ppdu->rssi; 1608 1609 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP); 1610 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG); 1611 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A); 1612 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B); 1613 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C); 1614 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D); 1615 } 1616 1617 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev, 1618 struct rtw89_rx_phy_ppdu *phy_ppdu) 1619 { 1620 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf; 1621 u32 len_from_header; 1622 bool physts_valid; 1623 1624 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID); 1625 if (!physts_valid) 1626 return -EINVAL; 1627 1628 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3; 1629 1630 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 1631 len_from_header += PHY_STS_HDR_LEN; 1632 1633 if (len_from_header != phy_ppdu->len) { 1634 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n"); 1635 return -EINVAL; 1636 } 1637 rtw89_core_update_phy_ppdu(phy_ppdu); 1638 1639 return 0; 1640 } 1641 1642 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev, 1643 struct rtw89_rx_phy_ppdu *phy_ppdu) 1644 { 1645 u16 ie_len; 1646 void *pos, *end; 1647 1648 /* mark invalid reports and bypass them */ 1649 if (phy_ppdu->ie < RTW89_CCK_PKT) 1650 return -EINVAL; 1651 1652 pos = phy_ppdu->buf + PHY_STS_HDR_LEN; 1653 end = phy_ppdu->buf + phy_ppdu->len; 1654 while (pos < end) { 1655 const struct rtw89_phy_sts_iehdr *iehdr = pos; 1656 1657 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr); 1658 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu); 1659 pos += ie_len; 1660 if (pos > end || ie_len == 0) { 1661 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1662 "phy status parse failed\n"); 1663 return -EINVAL; 1664 } 1665 } 1666 1667 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu); 1668 1669 return 0; 1670 } 1671 1672 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev, 1673 struct rtw89_rx_phy_ppdu *phy_ppdu) 1674 { 1675 int ret; 1676 1677 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu); 1678 if (ret) 1679 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n"); 1680 else 1681 phy_ppdu->valid = true; 1682 1683 ieee80211_iterate_stations_atomic(rtwdev->hw, 1684 rtw89_core_rx_process_phy_ppdu_iter, 1685 phy_ppdu); 1686 } 1687 1688 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev, 1689 u8 desc_info_gi, 1690 bool rx_status, bool eht) 1691 { 1692 switch (desc_info_gi) { 1693 case RTW89_GILTF_SGI_4XHE08: 1694 case RTW89_GILTF_2XHE08: 1695 case RTW89_GILTF_1XHE08: 1696 return eht ? NL80211_RATE_INFO_EHT_GI_0_8 : 1697 NL80211_RATE_INFO_HE_GI_0_8; 1698 case RTW89_GILTF_2XHE16: 1699 case RTW89_GILTF_1XHE16: 1700 return eht ? NL80211_RATE_INFO_EHT_GI_1_6 : 1701 NL80211_RATE_INFO_HE_GI_1_6; 1702 case RTW89_GILTF_LGI_4XHE32: 1703 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1704 NL80211_RATE_INFO_HE_GI_3_2; 1705 default: 1706 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi); 1707 if (rx_status) 1708 return eht ? NL80211_RATE_INFO_EHT_GI_3_2 : 1709 NL80211_RATE_INFO_HE_GI_3_2; 1710 return U8_MAX; 1711 } 1712 } 1713 1714 static 1715 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf, 1716 bool eht) 1717 { 1718 if (eht) 1719 return status->eht.gi == gi_ltf; 1720 1721 return status->he_gi == gi_ltf; 1722 } 1723 1724 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev, 1725 struct rtw89_rx_desc_info *desc_info, 1726 struct ieee80211_rx_status *status) 1727 { 1728 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 1729 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf; 1730 bool eht = false; 1731 u16 data_rate; 1732 bool ret; 1733 1734 data_rate = desc_info->data_rate; 1735 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 1736 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 1737 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 1738 /* rate_idx is still hardware value here */ 1739 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 1740 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 1741 } else if (data_rate_mode == DATA_RATE_MODE_VHT || 1742 data_rate_mode == DATA_RATE_MODE_HE || 1743 data_rate_mode == DATA_RATE_MODE_EHT) { 1744 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 1745 } else { 1746 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 1747 } 1748 1749 eht = data_rate_mode == DATA_RATE_MODE_EHT; 1750 bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 1751 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht); 1752 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt && 1753 status->rate_idx == rate_idx && 1754 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) && 1755 status->bw == bw; 1756 1757 return ret; 1758 } 1759 1760 struct rtw89_vif_rx_stats_iter_data { 1761 struct rtw89_dev *rtwdev; 1762 struct rtw89_rx_phy_ppdu *phy_ppdu; 1763 struct rtw89_rx_desc_info *desc_info; 1764 struct sk_buff *skb; 1765 const u8 *bssid; 1766 }; 1767 1768 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev, 1769 struct ieee80211_vif *vif, 1770 struct sk_buff *skb) 1771 { 1772 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1773 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data; 1774 u8 *pos, *end, type, tf_bw; 1775 u16 aid, tf_rua; 1776 1777 if (!ether_addr_equal(vif->bss_conf.bssid, tf->ta) || 1778 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION || 1779 rtwvif->net_type == RTW89_NET_TYPE_NO_LINK) 1780 return; 1781 1782 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK); 1783 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR) 1784 return; 1785 1786 end = (u8 *)tf + skb->len; 1787 pos = tf->variable; 1788 1789 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) { 1790 aid = RTW89_GET_TF_USER_INFO_AID12(pos); 1791 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos); 1792 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK); 1793 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 1794 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n", 1795 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos), 1796 tf_rua, tf_bw); 1797 1798 if (aid == RTW89_TF_PAD) 1799 break; 1800 1801 if (aid == vif->cfg.aid) { 1802 enum nl80211_he_ru_alloc rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1); 1803 1804 rtwvif->stats.rx_tf_acc++; 1805 rtwdev->stats.rx_tf_acc++; 1806 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ && 1807 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106) 1808 rtwvif->pwr_diff_en = true; 1809 break; 1810 } 1811 1812 pos += RTW89_TF_BASIC_USER_INFO_SZ; 1813 } 1814 } 1815 1816 static void rtw89_cancel_6ghz_probe_work(struct work_struct *work) 1817 { 1818 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 1819 cancel_6ghz_probe_work); 1820 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1821 struct rtw89_pktofld_info *info; 1822 1823 mutex_lock(&rtwdev->mutex); 1824 1825 if (!rtwdev->scanning) 1826 goto out; 1827 1828 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1829 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload)) 1830 continue; 1831 1832 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id); 1833 1834 /* Don't delete/free info from pkt_list at this moment. Let it 1835 * be deleted/freed in rtw89_release_pkt_list() after scanning, 1836 * since if during scanning, pkt_list is accessed in bottom half. 1837 */ 1838 } 1839 1840 out: 1841 mutex_unlock(&rtwdev->mutex); 1842 } 1843 1844 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev, 1845 struct sk_buff *skb) 1846 { 1847 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); 1848 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1849 struct list_head *pkt_list = rtwdev->scan_info.pkt_list; 1850 struct rtw89_pktofld_info *info; 1851 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie; 1852 bool queue_work = false; 1853 1854 if (rx_status->band != NL80211_BAND_6GHZ) 1855 return; 1856 1857 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len); 1858 1859 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) { 1860 if (ether_addr_equal(info->bssid, mgmt->bssid)) { 1861 info->cancel = true; 1862 queue_work = true; 1863 continue; 1864 } 1865 1866 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0) 1867 continue; 1868 1869 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) { 1870 info->cancel = true; 1871 queue_work = true; 1872 } 1873 } 1874 1875 if (queue_work) 1876 ieee80211_queue_work(rtwdev->hw, &rtwdev->cancel_6ghz_probe_work); 1877 } 1878 1879 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif *rtwvif, 1880 struct ieee80211_hdr *hdr, size_t len) 1881 { 1882 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr; 1883 1884 if (len < offsetof(typeof(*mgmt), u.beacon.variable)) 1885 return; 1886 1887 WRITE_ONCE(rtwvif->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp)); 1888 } 1889 1890 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac, 1891 struct ieee80211_vif *vif) 1892 { 1893 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 1894 struct rtw89_vif_rx_stats_iter_data *iter_data = data; 1895 struct rtw89_dev *rtwdev = iter_data->rtwdev; 1896 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat; 1897 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 1898 struct sk_buff *skb = iter_data->skb; 1899 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1900 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu; 1901 const u8 *bssid = iter_data->bssid; 1902 1903 if (rtwdev->scanning && 1904 (ieee80211_is_beacon(hdr->frame_control) || 1905 ieee80211_is_probe_resp(hdr->frame_control))) 1906 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb); 1907 1908 if (!vif->bss_conf.bssid) 1909 return; 1910 1911 if (ieee80211_is_trigger(hdr->frame_control)) { 1912 rtw89_stats_trigger_frame(rtwdev, vif, skb); 1913 return; 1914 } 1915 1916 if (!ether_addr_equal(vif->bss_conf.bssid, bssid)) 1917 return; 1918 1919 if (ieee80211_is_beacon(hdr->frame_control)) { 1920 if (vif->type == NL80211_IFTYPE_STATION) { 1921 rtw89_vif_sync_bcn_tsf(rtwvif, hdr, skb->len); 1922 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu); 1923 } 1924 pkt_stat->beacon_nr++; 1925 } 1926 1927 if (!ether_addr_equal(vif->addr, hdr->addr1)) 1928 return; 1929 1930 if (desc_info->data_rate < RTW89_HW_RATE_NR) 1931 pkt_stat->rx_rate_cnt[desc_info->data_rate]++; 1932 1933 rtw89_traffic_stats_accu(rtwdev, &rtwvif->stats, skb, false); 1934 } 1935 1936 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev, 1937 struct rtw89_rx_phy_ppdu *phy_ppdu, 1938 struct rtw89_rx_desc_info *desc_info, 1939 struct sk_buff *skb) 1940 { 1941 struct rtw89_vif_rx_stats_iter_data iter_data; 1942 1943 rtw89_traffic_stats_accu(rtwdev, &rtwdev->stats, skb, false); 1944 1945 iter_data.rtwdev = rtwdev; 1946 iter_data.phy_ppdu = phy_ppdu; 1947 iter_data.desc_info = desc_info; 1948 iter_data.skb = skb; 1949 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data); 1950 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data); 1951 } 1952 1953 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev, 1954 struct ieee80211_rx_status *status) 1955 { 1956 const struct rtw89_chan_rcd *rcd = 1957 rtw89_chan_rcd_get(rtwdev, RTW89_SUB_ENTITY_0); 1958 u16 chan = rcd->prev_primary_channel; 1959 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type); 1960 1961 if (status->band != NL80211_BAND_2GHZ && 1962 status->encoding == RX_ENC_LEGACY && 1963 status->rate_idx < RTW89_HW_RATE_OFDM6) { 1964 status->freq = ieee80211_channel_to_frequency(chan, band); 1965 status->band = band; 1966 } 1967 } 1968 1969 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status) 1970 { 1971 if (rx_status->band == NL80211_BAND_2GHZ || 1972 rx_status->encoding != RX_ENC_LEGACY) 1973 return; 1974 1975 /* Some control frames' freq(ACKs in this case) are reported wrong due 1976 * to FW notify timing, set to lowest rate to prevent overflow. 1977 */ 1978 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) { 1979 rx_status->rate_idx = 0; 1980 return; 1981 } 1982 1983 /* No 4 CCK rates for non-2G */ 1984 rx_status->rate_idx -= 4; 1985 } 1986 1987 static const u8 rx_status_bw_to_radiotap_eht_usig[] = { 1988 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ, 1989 [RATE_INFO_BW_5] = U8_MAX, 1990 [RATE_INFO_BW_10] = U8_MAX, 1991 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ, 1992 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ, 1993 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ, 1994 [RATE_INFO_BW_HE_RU] = U8_MAX, 1995 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1, 1996 [RATE_INFO_BW_EHT_RU] = U8_MAX, 1997 }; 1998 1999 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev, 2000 struct sk_buff *skb, 2001 struct ieee80211_rx_status *rx_status) 2002 { 2003 struct ieee80211_radiotap_eht_usig *usig; 2004 struct ieee80211_radiotap_eht *eht; 2005 struct ieee80211_radiotap_tlv *tlv; 2006 int eht_len = struct_size(eht, user_info, 1); 2007 int usig_len = sizeof(*usig); 2008 int len; 2009 u8 bw; 2010 2011 len = sizeof(*tlv) + ALIGN(eht_len, 4) + 2012 sizeof(*tlv) + ALIGN(usig_len, 4); 2013 2014 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END; 2015 skb_reset_mac_header(skb); 2016 2017 /* EHT */ 2018 tlv = skb_push(skb, len); 2019 memset(tlv, 0, len); 2020 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT); 2021 tlv->len = cpu_to_le16(eht_len); 2022 2023 eht = (struct ieee80211_radiotap_eht *)tlv->data; 2024 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI); 2025 eht->data[0] = 2026 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI); 2027 2028 eht->user_info[0] = 2029 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN | 2030 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O); 2031 eht->user_info[0] |= 2032 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) | 2033 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O); 2034 2035 /* U-SIG */ 2036 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4); 2037 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG); 2038 tlv->len = cpu_to_le16(usig_len); 2039 2040 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig)) 2041 return; 2042 2043 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw]; 2044 if (bw == U8_MAX) 2045 return; 2046 2047 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data; 2048 usig->common = 2049 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) | 2050 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW); 2051 } 2052 2053 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev, 2054 struct sk_buff *skb, 2055 struct ieee80211_rx_status *rx_status) 2056 { 2057 static const struct ieee80211_radiotap_he known_he = { 2058 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2059 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2060 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2061 }; 2062 struct ieee80211_radiotap_he *he; 2063 2064 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR)) 2065 return; 2066 2067 if (rx_status->encoding == RX_ENC_HE) { 2068 rx_status->flag |= RX_FLAG_RADIOTAP_HE; 2069 he = skb_push(skb, sizeof(*he)); 2070 *he = known_he; 2071 } else if (rx_status->encoding == RX_ENC_EHT) { 2072 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status); 2073 } 2074 } 2075 2076 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev, 2077 struct rtw89_rx_phy_ppdu *phy_ppdu, 2078 struct rtw89_rx_desc_info *desc_info, 2079 struct sk_buff *skb_ppdu, 2080 struct ieee80211_rx_status *rx_status) 2081 { 2082 struct napi_struct *napi = &rtwdev->napi; 2083 2084 /* In low power mode, napi isn't scheduled. Receive it to netif. */ 2085 if (unlikely(!napi_is_scheduled(napi))) 2086 napi = NULL; 2087 2088 rtw89_core_hw_to_sband_rate(rx_status); 2089 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu); 2090 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status); 2091 /* In low power mode, it does RX in thread context. */ 2092 local_bh_disable(); 2093 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi); 2094 local_bh_enable(); 2095 rtwdev->napi_budget_countdown--; 2096 } 2097 2098 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev, 2099 struct rtw89_rx_phy_ppdu *phy_ppdu, 2100 struct rtw89_rx_desc_info *desc_info, 2101 struct sk_buff *skb) 2102 { 2103 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2104 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band]; 2105 struct sk_buff *skb_ppdu = NULL, *tmp; 2106 struct ieee80211_rx_status *rx_status; 2107 2108 if (curr > RTW89_MAX_PPDU_CNT) 2109 return; 2110 2111 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) { 2112 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]); 2113 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2114 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status)) 2115 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status); 2116 rtw89_correct_cck_chan(rtwdev, rx_status); 2117 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status); 2118 } 2119 } 2120 2121 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev, 2122 struct rtw89_rx_desc_info *desc_info, 2123 struct sk_buff *skb) 2124 { 2125 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false, 2126 .len = skb->len, 2127 .to_self = desc_info->addr1_match, 2128 .rate = desc_info->data_rate, 2129 .mac_id = desc_info->mac_id}; 2130 int ret; 2131 2132 if (desc_info->mac_info_valid) { 2133 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu); 2134 if (ret) 2135 goto out; 2136 } 2137 2138 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu); 2139 if (ret) 2140 goto out; 2141 2142 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu); 2143 2144 out: 2145 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb); 2146 dev_kfree_skb_any(skb); 2147 } 2148 2149 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev, 2150 struct rtw89_rx_desc_info *desc_info, 2151 struct sk_buff *skb) 2152 { 2153 switch (desc_info->pkt_type) { 2154 case RTW89_CORE_RX_TYPE_C2H: 2155 rtw89_fw_c2h_irqsafe(rtwdev, skb); 2156 break; 2157 case RTW89_CORE_RX_TYPE_PPDU_STAT: 2158 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb); 2159 break; 2160 default: 2161 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n", 2162 desc_info->pkt_type); 2163 dev_kfree_skb_any(skb); 2164 break; 2165 } 2166 } 2167 2168 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev, 2169 struct rtw89_rx_desc_info *desc_info, 2170 u8 *data, u32 data_offset) 2171 { 2172 const struct rtw89_chip_info *chip = rtwdev->chip; 2173 struct rtw89_rxdesc_short *rxd_s; 2174 struct rtw89_rxdesc_long *rxd_l; 2175 u8 shift_len, drv_info_len; 2176 2177 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset); 2178 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK); 2179 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK); 2180 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD); 2181 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK); 2182 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD); 2183 if (chip->chip_id == RTL8852C) 2184 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK); 2185 else 2186 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK); 2187 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK); 2188 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK); 2189 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK); 2190 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN); 2191 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK); 2192 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK); 2193 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK); 2194 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR); 2195 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR); 2196 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC); 2197 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC); 2198 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH); 2199 2200 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2201 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2202 desc_info->offset = data_offset + shift_len + drv_info_len; 2203 if (desc_info->long_rxdesc) 2204 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long); 2205 else 2206 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short); 2207 desc_info->ready = true; 2208 2209 if (!desc_info->long_rxdesc) 2210 return; 2211 2212 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset); 2213 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK); 2214 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD); 2215 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK); 2216 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK); 2217 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK); 2218 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK); 2219 } 2220 EXPORT_SYMBOL(rtw89_core_query_rxdesc); 2221 2222 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev, 2223 struct rtw89_rx_desc_info *desc_info, 2224 u8 *data, u32 data_offset) 2225 { 2226 struct rtw89_rxdesc_short_v2 *rxd_s; 2227 struct rtw89_rxdesc_long_v2 *rxd_l; 2228 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len; 2229 2230 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset); 2231 2232 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK); 2233 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK); 2234 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK); 2235 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK); 2236 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK); 2237 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD); 2238 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK); 2239 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT) 2240 desc_info->mac_info_valid = true; 2241 2242 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK); 2243 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK); 2244 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD); 2245 2246 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR); 2247 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR); 2248 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC); 2249 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC); 2250 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH); 2251 2252 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK); 2253 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK); 2254 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK); 2255 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK); 2256 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK); 2257 2258 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5); 2259 2260 shift_len = desc_info->shift << 1; /* 2-byte unit */ 2261 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */ 2262 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */ 2263 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */ 2264 desc_info->offset = data_offset + shift_len + drv_info_len + 2265 phy_rtp_len + hdr_cnv_len; 2266 2267 if (desc_info->long_rxdesc) 2268 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2); 2269 else 2270 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2); 2271 desc_info->ready = true; 2272 2273 if (!desc_info->long_rxdesc) 2274 return; 2275 2276 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset); 2277 2278 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN); 2279 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK); 2280 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK); 2281 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK); 2282 2283 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK); 2284 } 2285 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2); 2286 2287 struct rtw89_core_iter_rx_status { 2288 struct rtw89_dev *rtwdev; 2289 struct ieee80211_rx_status *rx_status; 2290 struct rtw89_rx_desc_info *desc_info; 2291 u8 mac_id; 2292 }; 2293 2294 static 2295 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta) 2296 { 2297 struct rtw89_core_iter_rx_status *iter_data = 2298 (struct rtw89_core_iter_rx_status *)data; 2299 struct ieee80211_rx_status *rx_status = iter_data->rx_status; 2300 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2301 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info; 2302 u8 mac_id = iter_data->mac_id; 2303 2304 if (mac_id != rtwsta->mac_id) 2305 return; 2306 2307 rtwsta->rx_status = *rx_status; 2308 rtwsta->rx_hw_rate = desc_info->data_rate; 2309 } 2310 2311 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev, 2312 struct rtw89_rx_desc_info *desc_info, 2313 struct ieee80211_rx_status *rx_status) 2314 { 2315 struct rtw89_core_iter_rx_status iter_data; 2316 2317 if (!desc_info->addr1_match || !desc_info->long_rxdesc) 2318 return; 2319 2320 if (desc_info->frame_type != RTW89_RX_TYPE_DATA) 2321 return; 2322 2323 iter_data.rtwdev = rtwdev; 2324 iter_data.rx_status = rx_status; 2325 iter_data.desc_info = desc_info; 2326 iter_data.mac_id = desc_info->mac_id; 2327 ieee80211_iterate_stations_atomic(rtwdev->hw, 2328 rtw89_core_stats_sta_rx_status_iter, 2329 &iter_data); 2330 } 2331 2332 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev, 2333 struct rtw89_rx_desc_info *desc_info, 2334 struct ieee80211_rx_status *rx_status) 2335 { 2336 const struct cfg80211_chan_def *chandef = 2337 rtw89_chandef_get(rtwdev, RTW89_SUB_ENTITY_0); 2338 u16 data_rate; 2339 u8 data_rate_mode; 2340 bool eht = false; 2341 u8 gi; 2342 2343 /* currently using single PHY */ 2344 rx_status->freq = chandef->chan->center_freq; 2345 rx_status->band = chandef->chan->band; 2346 2347 if (rtwdev->scanning && 2348 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 2349 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev); 2350 u8 chan = cur->primary_channel; 2351 u8 band = cur->band_type; 2352 enum nl80211_band nl_band; 2353 2354 nl_band = rtw89_hw_to_nl80211_band(band); 2355 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band); 2356 rx_status->band = nl_band; 2357 } 2358 2359 if (desc_info->icv_err || desc_info->crc32_err) 2360 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2361 2362 if (desc_info->hw_dec && 2363 !(desc_info->sw_dec || desc_info->icv_err)) 2364 rx_status->flag |= RX_FLAG_DECRYPTED; 2365 2366 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw); 2367 2368 data_rate = desc_info->data_rate; 2369 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate); 2370 if (data_rate_mode == DATA_RATE_MODE_NON_HT) { 2371 rx_status->encoding = RX_ENC_LEGACY; 2372 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate); 2373 /* convert rate_idx after we get the correct band */ 2374 } else if (data_rate_mode == DATA_RATE_MODE_HT) { 2375 rx_status->encoding = RX_ENC_HT; 2376 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate); 2377 if (desc_info->gi_ltf) 2378 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2379 } else if (data_rate_mode == DATA_RATE_MODE_VHT) { 2380 rx_status->encoding = RX_ENC_VHT; 2381 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2382 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2383 if (desc_info->gi_ltf) 2384 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2385 } else if (data_rate_mode == DATA_RATE_MODE_HE) { 2386 rx_status->encoding = RX_ENC_HE; 2387 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2388 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2389 } else if (data_rate_mode == DATA_RATE_MODE_EHT) { 2390 rx_status->encoding = RX_ENC_EHT; 2391 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate); 2392 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1; 2393 eht = true; 2394 } else { 2395 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode); 2396 } 2397 2398 /* he_gi is used to match ppdu, so we always fill it. */ 2399 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht); 2400 if (eht) 2401 rx_status->eht.gi = gi; 2402 else 2403 rx_status->he_gi = gi; 2404 rx_status->flag |= RX_FLAG_MACTIME_START; 2405 rx_status->mactime = desc_info->free_run_cnt; 2406 2407 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status); 2408 } 2409 2410 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev) 2411 { 2412 const struct rtw89_chip_info *chip = rtwdev->chip; 2413 2414 if (rtw89_disable_ps_mode || !chip->ps_mode_supported || 2415 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw)) 2416 return RTW89_PS_MODE_NONE; 2417 2418 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) && 2419 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw)) 2420 return RTW89_PS_MODE_PWR_GATED; 2421 2422 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED)) 2423 return RTW89_PS_MODE_CLK_GATED; 2424 2425 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF)) 2426 return RTW89_PS_MODE_RFOFF; 2427 2428 return RTW89_PS_MODE_NONE; 2429 } 2430 2431 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev, 2432 struct rtw89_rx_desc_info *desc_info) 2433 { 2434 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2435 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2436 struct ieee80211_rx_status *rx_status; 2437 struct sk_buff *skb_ppdu, *tmp; 2438 2439 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) { 2440 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]); 2441 rx_status = IEEE80211_SKB_RXCB(skb_ppdu); 2442 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status); 2443 } 2444 } 2445 2446 void rtw89_core_rx(struct rtw89_dev *rtwdev, 2447 struct rtw89_rx_desc_info *desc_info, 2448 struct sk_buff *skb) 2449 { 2450 struct ieee80211_rx_status *rx_status; 2451 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts; 2452 u8 ppdu_cnt = desc_info->ppdu_cnt; 2453 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0; 2454 2455 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) { 2456 rtw89_core_rx_process_report(rtwdev, desc_info, skb); 2457 return; 2458 } 2459 2460 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) { 2461 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info); 2462 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt; 2463 } 2464 2465 rx_status = IEEE80211_SKB_RXCB(skb); 2466 memset(rx_status, 0, sizeof(*rx_status)); 2467 rtw89_core_update_rx_status(rtwdev, desc_info, rx_status); 2468 if (desc_info->long_rxdesc && 2469 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP) 2470 skb_queue_tail(&ppdu_sts->rx_queue[band], skb); 2471 else 2472 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status); 2473 } 2474 EXPORT_SYMBOL(rtw89_core_rx); 2475 2476 void rtw89_core_napi_start(struct rtw89_dev *rtwdev) 2477 { 2478 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2479 return; 2480 2481 napi_enable(&rtwdev->napi); 2482 } 2483 EXPORT_SYMBOL(rtw89_core_napi_start); 2484 2485 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev) 2486 { 2487 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags)) 2488 return; 2489 2490 napi_synchronize(&rtwdev->napi); 2491 napi_disable(&rtwdev->napi); 2492 } 2493 EXPORT_SYMBOL(rtw89_core_napi_stop); 2494 2495 void rtw89_core_napi_init(struct rtw89_dev *rtwdev) 2496 { 2497 init_dummy_netdev(&rtwdev->netdev); 2498 netif_napi_add(&rtwdev->netdev, &rtwdev->napi, 2499 rtwdev->hci.ops->napi_poll); 2500 } 2501 EXPORT_SYMBOL(rtw89_core_napi_init); 2502 2503 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev) 2504 { 2505 rtw89_core_napi_stop(rtwdev); 2506 netif_napi_del(&rtwdev->napi); 2507 } 2508 EXPORT_SYMBOL(rtw89_core_napi_deinit); 2509 2510 static void rtw89_core_ba_work(struct work_struct *work) 2511 { 2512 struct rtw89_dev *rtwdev = 2513 container_of(work, struct rtw89_dev, ba_work); 2514 struct rtw89_txq *rtwtxq, *tmp; 2515 int ret; 2516 2517 spin_lock_bh(&rtwdev->ba_lock); 2518 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2519 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2520 struct ieee80211_sta *sta = txq->sta; 2521 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2522 u8 tid = txq->tid; 2523 2524 if (!sta) { 2525 rtw89_warn(rtwdev, "cannot start BA without sta\n"); 2526 goto skip_ba_work; 2527 } 2528 2529 if (rtwsta->disassoc) { 2530 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2531 "cannot start BA with disassoc sta\n"); 2532 goto skip_ba_work; 2533 } 2534 2535 ret = ieee80211_start_tx_ba_session(sta, tid, 0); 2536 if (ret) { 2537 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2538 "failed to setup BA session for %pM:%2d: %d\n", 2539 sta->addr, tid, ret); 2540 if (ret == -EINVAL) 2541 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags); 2542 } 2543 skip_ba_work: 2544 list_del_init(&rtwtxq->list); 2545 } 2546 spin_unlock_bh(&rtwdev->ba_lock); 2547 } 2548 2549 static void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev, 2550 struct ieee80211_sta *sta) 2551 { 2552 struct rtw89_txq *rtwtxq, *tmp; 2553 2554 spin_lock_bh(&rtwdev->ba_lock); 2555 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) { 2556 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2557 2558 if (sta == txq->sta) 2559 list_del_init(&rtwtxq->list); 2560 } 2561 spin_unlock_bh(&rtwdev->ba_lock); 2562 } 2563 2564 static void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev, 2565 struct ieee80211_sta *sta) 2566 { 2567 struct rtw89_txq *rtwtxq, *tmp; 2568 2569 spin_lock_bh(&rtwdev->ba_lock); 2570 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2571 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2572 2573 if (sta == txq->sta) { 2574 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2575 list_del_init(&rtwtxq->list); 2576 } 2577 } 2578 spin_unlock_bh(&rtwdev->ba_lock); 2579 } 2580 2581 static void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev, 2582 struct ieee80211_sta *sta) 2583 { 2584 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2585 struct sk_buff *skb, *tmp; 2586 2587 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2588 skb_unlink(skb, &rtwsta->roc_queue); 2589 dev_kfree_skb_any(skb); 2590 } 2591 } 2592 2593 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev, 2594 struct rtw89_txq *rtwtxq) 2595 { 2596 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2597 struct ieee80211_sta *sta = txq->sta; 2598 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta); 2599 2600 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc)) 2601 return; 2602 2603 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) || 2604 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2605 return; 2606 2607 spin_lock_bh(&rtwdev->ba_lock); 2608 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2609 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list); 2610 spin_unlock_bh(&rtwdev->ba_lock); 2611 2612 ieee80211_stop_tx_ba_session(sta, txq->tid); 2613 cancel_delayed_work(&rtwdev->forbid_ba_work); 2614 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work, 2615 RTW89_FORBID_BA_TIMER); 2616 } 2617 2618 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev, 2619 struct rtw89_txq *rtwtxq, 2620 struct sk_buff *skb) 2621 { 2622 struct ieee80211_hw *hw = rtwdev->hw; 2623 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2624 struct ieee80211_sta *sta = txq->sta; 2625 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2626 2627 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags)) 2628 return; 2629 2630 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) { 2631 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq); 2632 return; 2633 } 2634 2635 if (unlikely(!sta)) 2636 return; 2637 2638 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags))) 2639 return; 2640 2641 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) { 2642 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU; 2643 return; 2644 } 2645 2646 spin_lock_bh(&rtwdev->ba_lock); 2647 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) { 2648 list_add_tail(&rtwtxq->list, &rtwdev->ba_list); 2649 ieee80211_queue_work(hw, &rtwdev->ba_work); 2650 } 2651 spin_unlock_bh(&rtwdev->ba_lock); 2652 } 2653 2654 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev, 2655 struct rtw89_txq *rtwtxq, 2656 unsigned long frame_cnt, 2657 unsigned long byte_cnt) 2658 { 2659 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq); 2660 struct ieee80211_vif *vif = txq->vif; 2661 struct ieee80211_sta *sta = txq->sta; 2662 struct sk_buff *skb; 2663 unsigned long i; 2664 int ret; 2665 2666 rcu_read_lock(); 2667 for (i = 0; i < frame_cnt; i++) { 2668 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq); 2669 if (!skb) { 2670 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n"); 2671 goto out; 2672 } 2673 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb); 2674 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL); 2675 if (ret) { 2676 rtw89_err(rtwdev, "failed to push txq: %d\n", ret); 2677 ieee80211_free_txskb(rtwdev->hw, skb); 2678 break; 2679 } 2680 } 2681 out: 2682 rcu_read_unlock(); 2683 } 2684 2685 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid) 2686 { 2687 u8 qsel, ch_dma; 2688 2689 qsel = rtw89_core_get_qsel(rtwdev, tid); 2690 ch_dma = rtw89_core_get_ch_dma(rtwdev, qsel); 2691 2692 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma); 2693 } 2694 2695 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev, 2696 struct ieee80211_txq *txq, 2697 unsigned long *frame_cnt, 2698 bool *sched_txq, bool *reinvoke) 2699 { 2700 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2701 struct ieee80211_sta *sta = txq->sta; 2702 struct rtw89_sta *rtwsta = sta ? (struct rtw89_sta *)sta->drv_priv : NULL; 2703 2704 if (!sta || rtwsta->max_agg_wait <= 0) 2705 return false; 2706 2707 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID) 2708 return false; 2709 2710 if (*frame_cnt > 1) { 2711 *frame_cnt -= 1; 2712 *sched_txq = true; 2713 *reinvoke = true; 2714 rtwtxq->wait_cnt = 1; 2715 return false; 2716 } 2717 2718 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta->max_agg_wait) { 2719 *reinvoke = true; 2720 rtwtxq->wait_cnt++; 2721 return true; 2722 } 2723 2724 rtwtxq->wait_cnt = 0; 2725 return false; 2726 } 2727 2728 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke) 2729 { 2730 struct ieee80211_hw *hw = rtwdev->hw; 2731 struct ieee80211_txq *txq; 2732 struct rtw89_vif *rtwvif; 2733 struct rtw89_txq *rtwtxq; 2734 unsigned long frame_cnt; 2735 unsigned long byte_cnt; 2736 u32 tx_resource; 2737 bool sched_txq; 2738 2739 ieee80211_txq_schedule_start(hw, ac); 2740 while ((txq = ieee80211_next_txq(hw, ac))) { 2741 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 2742 rtwvif = (struct rtw89_vif *)txq->vif->drv_priv; 2743 2744 if (rtwvif->offchan) { 2745 ieee80211_return_txq(hw, txq, true); 2746 continue; 2747 } 2748 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid); 2749 sched_txq = false; 2750 2751 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt); 2752 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) { 2753 ieee80211_return_txq(hw, txq, true); 2754 continue; 2755 } 2756 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource); 2757 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt); 2758 ieee80211_return_txq(hw, txq, sched_txq); 2759 if (frame_cnt != 0) 2760 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid)); 2761 2762 /* bound of tx_resource could get stuck due to burst traffic */ 2763 if (frame_cnt == tx_resource) 2764 *reinvoke = true; 2765 } 2766 ieee80211_txq_schedule_end(hw, ac); 2767 } 2768 2769 static void rtw89_ips_work(struct work_struct *work) 2770 { 2771 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 2772 ips_work); 2773 mutex_lock(&rtwdev->mutex); 2774 rtw89_enter_ips_by_hwflags(rtwdev); 2775 mutex_unlock(&rtwdev->mutex); 2776 } 2777 2778 static void rtw89_core_txq_work(struct work_struct *w) 2779 { 2780 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work); 2781 bool reinvoke = false; 2782 u8 ac; 2783 2784 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++) 2785 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke); 2786 2787 if (reinvoke) { 2788 /* reinvoke to process the last frame */ 2789 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1); 2790 } 2791 } 2792 2793 static void rtw89_core_txq_reinvoke_work(struct work_struct *w) 2794 { 2795 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2796 txq_reinvoke_work.work); 2797 2798 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2799 } 2800 2801 static void rtw89_forbid_ba_work(struct work_struct *w) 2802 { 2803 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, 2804 forbid_ba_work.work); 2805 struct rtw89_txq *rtwtxq, *tmp; 2806 2807 spin_lock_bh(&rtwdev->ba_lock); 2808 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) { 2809 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 2810 list_del_init(&rtwtxq->list); 2811 } 2812 spin_unlock_bh(&rtwdev->ba_lock); 2813 } 2814 2815 static void rtw89_core_sta_pending_tx_iter(void *data, 2816 struct ieee80211_sta *sta) 2817 { 2818 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 2819 struct rtw89_vif *rtwvif_target = data, *rtwvif = rtwsta->rtwvif; 2820 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2821 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2822 struct sk_buff *skb, *tmp; 2823 int qsel, ret; 2824 2825 if (rtwvif->sub_entity_idx != rtwvif_target->sub_entity_idx) 2826 return; 2827 2828 if (skb_queue_len(&rtwsta->roc_queue) == 0) 2829 return; 2830 2831 skb_queue_walk_safe(&rtwsta->roc_queue, skb, tmp) { 2832 skb_unlink(skb, &rtwsta->roc_queue); 2833 2834 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2835 if (ret) { 2836 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret); 2837 dev_kfree_skb_any(skb); 2838 } else { 2839 rtw89_core_tx_kick_off(rtwdev, qsel); 2840 } 2841 } 2842 } 2843 2844 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev, 2845 struct rtw89_vif *rtwvif) 2846 { 2847 ieee80211_iterate_stations_atomic(rtwdev->hw, 2848 rtw89_core_sta_pending_tx_iter, 2849 rtwvif); 2850 } 2851 2852 static int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, 2853 struct rtw89_vif *rtwvif, bool qos, bool ps) 2854 { 2855 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 2856 struct ieee80211_sta *sta; 2857 struct ieee80211_hdr *hdr; 2858 struct sk_buff *skb; 2859 int ret, qsel; 2860 2861 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc) 2862 return 0; 2863 2864 rcu_read_lock(); 2865 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid); 2866 if (!sta) { 2867 ret = -EINVAL; 2868 goto out; 2869 } 2870 2871 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, -1, qos); 2872 if (!skb) { 2873 ret = -ENOMEM; 2874 goto out; 2875 } 2876 2877 hdr = (struct ieee80211_hdr *)skb->data; 2878 if (ps) 2879 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2880 2881 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel); 2882 if (ret) { 2883 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret); 2884 dev_kfree_skb_any(skb); 2885 goto out; 2886 } 2887 2888 rcu_read_unlock(); 2889 2890 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, qsel, 2891 RTW89_ROC_TX_TIMEOUT); 2892 out: 2893 rcu_read_unlock(); 2894 2895 return ret; 2896 } 2897 2898 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2899 { 2900 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2901 struct ieee80211_hw *hw = rtwdev->hw; 2902 struct rtw89_roc *roc = &rtwvif->roc; 2903 struct cfg80211_chan_def roc_chan; 2904 struct rtw89_vif *tmp; 2905 int ret; 2906 2907 lockdep_assert_held(&rtwdev->mutex); 2908 2909 rtw89_leave_ips_by_hwflags(rtwdev); 2910 rtw89_leave_lps(rtwdev); 2911 rtw89_chanctx_pause(rtwdev, RTW89_CHANCTX_PAUSE_REASON_ROC); 2912 2913 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, true); 2914 if (ret) 2915 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2916 "roc send null-1 failed: %d\n", ret); 2917 2918 rtw89_for_each_rtwvif(rtwdev, tmp) 2919 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2920 tmp->offchan = true; 2921 2922 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT); 2923 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, &roc_chan); 2924 rtw89_set_channel(rtwdev); 2925 rtw89_write32_clr(rtwdev, 2926 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2927 B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH); 2928 2929 ieee80211_ready_on_channel(hw); 2930 cancel_delayed_work(&rtwvif->roc.roc_work); 2931 ieee80211_queue_delayed_work(hw, &rtwvif->roc.roc_work, 2932 msecs_to_jiffies(rtwvif->roc.duration)); 2933 } 2934 2935 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 2936 { 2937 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2938 struct ieee80211_hw *hw = rtwdev->hw; 2939 struct rtw89_roc *roc = &rtwvif->roc; 2940 struct rtw89_vif *tmp; 2941 int ret; 2942 2943 lockdep_assert_held(&rtwdev->mutex); 2944 2945 ieee80211_remain_on_channel_expired(hw); 2946 2947 rtw89_leave_ips_by_hwflags(rtwdev); 2948 rtw89_leave_lps(rtwdev); 2949 2950 rtw89_write32_mask(rtwdev, 2951 rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, RTW89_MAC_0), 2952 B_AX_RX_FLTR_CFG_MASK, 2953 rtwdev->hal.rx_fltr); 2954 2955 roc->state = RTW89_ROC_IDLE; 2956 rtw89_config_roc_chandef(rtwdev, rtwvif->sub_entity_idx, NULL); 2957 rtw89_chanctx_proceed(rtwdev); 2958 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif, true, false); 2959 if (ret) 2960 rtw89_debug(rtwdev, RTW89_DBG_TXRX, 2961 "roc send null-0 failed: %d\n", ret); 2962 2963 rtw89_for_each_rtwvif(rtwdev, tmp) 2964 if (tmp->sub_entity_idx == rtwvif->sub_entity_idx) 2965 tmp->offchan = false; 2966 2967 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif); 2968 queue_work(rtwdev->txq_wq, &rtwdev->txq_work); 2969 2970 if (hw->conf.flags & IEEE80211_CONF_IDLE) 2971 ieee80211_queue_delayed_work(hw, &roc->roc_work, 2972 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT)); 2973 } 2974 2975 void rtw89_roc_work(struct work_struct *work) 2976 { 2977 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 2978 roc.roc_work.work); 2979 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 2980 struct rtw89_roc *roc = &rtwvif->roc; 2981 2982 mutex_lock(&rtwdev->mutex); 2983 2984 switch (roc->state) { 2985 case RTW89_ROC_IDLE: 2986 rtw89_enter_ips_by_hwflags(rtwdev); 2987 break; 2988 case RTW89_ROC_MGMT: 2989 case RTW89_ROC_NORMAL: 2990 rtw89_roc_end(rtwdev, rtwvif); 2991 break; 2992 default: 2993 break; 2994 } 2995 2996 mutex_unlock(&rtwdev->mutex); 2997 } 2998 2999 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev, 3000 u32 throughput, u64 cnt) 3001 { 3002 if (cnt < 100) 3003 return RTW89_TFC_IDLE; 3004 if (throughput > 50) 3005 return RTW89_TFC_HIGH; 3006 if (throughput > 10) 3007 return RTW89_TFC_MID; 3008 if (throughput > 2) 3009 return RTW89_TFC_LOW; 3010 return RTW89_TFC_ULTRA_LOW; 3011 } 3012 3013 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev, 3014 struct rtw89_traffic_stats *stats) 3015 { 3016 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv; 3017 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv; 3018 3019 stats->tx_throughput_raw = (u32)(stats->tx_unicast >> RTW89_TP_SHIFT); 3020 stats->rx_throughput_raw = (u32)(stats->rx_unicast >> RTW89_TP_SHIFT); 3021 3022 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw); 3023 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw); 3024 3025 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp); 3026 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp); 3027 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput, 3028 stats->tx_cnt); 3029 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput, 3030 stats->rx_cnt); 3031 stats->tx_avg_len = stats->tx_cnt ? 3032 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0; 3033 stats->rx_avg_len = stats->rx_cnt ? 3034 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0; 3035 3036 stats->tx_unicast = 0; 3037 stats->rx_unicast = 0; 3038 stats->tx_cnt = 0; 3039 stats->rx_cnt = 0; 3040 stats->rx_tf_periodic = stats->rx_tf_acc; 3041 stats->rx_tf_acc = 0; 3042 3043 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv) 3044 return true; 3045 3046 return false; 3047 } 3048 3049 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev) 3050 { 3051 struct rtw89_vif *rtwvif; 3052 bool tfc_changed; 3053 3054 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats); 3055 rtw89_for_each_rtwvif(rtwdev, rtwvif) { 3056 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats); 3057 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif); 3058 } 3059 3060 return tfc_changed; 3061 } 3062 3063 static void rtw89_vif_enter_lps(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 3064 { 3065 if ((rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION && 3066 rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT) || 3067 rtwvif->tdls_peer) 3068 return; 3069 3070 if (rtwvif->offchan) 3071 return; 3072 3073 if (rtwvif->stats.tx_tfc_lv == RTW89_TFC_IDLE && 3074 rtwvif->stats.rx_tfc_lv == RTW89_TFC_IDLE) 3075 rtw89_enter_lps(rtwdev, rtwvif, true); 3076 } 3077 3078 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev) 3079 { 3080 struct rtw89_vif *rtwvif; 3081 3082 rtw89_for_each_rtwvif(rtwdev, rtwvif) 3083 rtw89_vif_enter_lps(rtwdev, rtwvif); 3084 } 3085 3086 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev) 3087 { 3088 enum rtw89_entity_mode mode; 3089 3090 mode = rtw89_get_entity_mode(rtwdev); 3091 if (mode == RTW89_ENTITY_MODE_MCC) 3092 return; 3093 3094 rtw89_chip_rfk_track(rtwdev); 3095 } 3096 3097 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif) 3098 { 3099 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev); 3100 3101 if (mode == RTW89_ENTITY_MODE_MCC) 3102 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE); 3103 else 3104 rtw89_process_p2p_ps(rtwdev, vif); 3105 } 3106 3107 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev, 3108 struct rtw89_traffic_stats *stats) 3109 { 3110 stats->tx_unicast = 0; 3111 stats->rx_unicast = 0; 3112 stats->tx_cnt = 0; 3113 stats->rx_cnt = 0; 3114 ewma_tp_init(&stats->tx_ewma_tp); 3115 ewma_tp_init(&stats->rx_ewma_tp); 3116 } 3117 3118 static void rtw89_track_work(struct work_struct *work) 3119 { 3120 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 3121 track_work.work); 3122 bool tfc_changed; 3123 3124 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WROK, rtwdev->flags)) 3125 return; 3126 3127 mutex_lock(&rtwdev->mutex); 3128 3129 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 3130 goto out; 3131 3132 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 3133 RTW89_TRACK_WORK_PERIOD); 3134 3135 tfc_changed = rtw89_traffic_stats_track(rtwdev); 3136 if (rtwdev->scanning) 3137 goto out; 3138 3139 rtw89_leave_lps(rtwdev); 3140 3141 if (tfc_changed) { 3142 rtw89_hci_recalc_int_mit(rtwdev); 3143 rtw89_btc_ntfy_wl_sta(rtwdev); 3144 } 3145 rtw89_mac_bf_monitor_track(rtwdev); 3146 rtw89_phy_stat_track(rtwdev); 3147 rtw89_phy_env_monitor_track(rtwdev); 3148 rtw89_phy_dig(rtwdev); 3149 rtw89_core_rfk_track(rtwdev); 3150 rtw89_phy_ra_update(rtwdev); 3151 rtw89_phy_cfo_track(rtwdev); 3152 rtw89_phy_tx_path_div_track(rtwdev); 3153 rtw89_phy_antdiv_track(rtwdev); 3154 rtw89_phy_ul_tb_ctrl_track(rtwdev); 3155 rtw89_phy_edcca_track(rtwdev); 3156 rtw89_tas_track(rtwdev); 3157 rtw89_chanctx_track(rtwdev); 3158 3159 if (rtwdev->lps_enabled && !rtwdev->btc.lps) 3160 rtw89_enter_lps_track(rtwdev); 3161 3162 out: 3163 mutex_unlock(&rtwdev->mutex); 3164 } 3165 3166 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size) 3167 { 3168 unsigned long bit; 3169 3170 bit = find_first_zero_bit(addr, size); 3171 if (bit < size) 3172 set_bit(bit, addr); 3173 3174 return bit; 3175 } 3176 3177 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit) 3178 { 3179 clear_bit(bit, addr); 3180 } 3181 3182 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits) 3183 { 3184 bitmap_zero(addr, nbits); 3185 } 3186 3187 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev, 3188 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3189 { 3190 const struct rtw89_chip_info *chip = rtwdev->chip; 3191 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3192 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3193 u8 idx; 3194 int i; 3195 3196 lockdep_assert_held(&rtwdev->mutex); 3197 3198 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num); 3199 if (idx == chip->bacam_num) { 3200 /* allocate a static BA CAM to tid=0/5, so replace the existing 3201 * one if BA CAM is full. Hardware will process the original tid 3202 * automatically. 3203 */ 3204 if (tid != 0 && tid != 5) 3205 return -ENOSPC; 3206 3207 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) { 3208 tmp = &cam_info->ba_cam_entry[i]; 3209 if (tmp->tid == 0 || tmp->tid == 5) 3210 continue; 3211 3212 idx = i; 3213 entry = tmp; 3214 list_del(&entry->list); 3215 break; 3216 } 3217 3218 if (!entry) 3219 return -ENOSPC; 3220 } else { 3221 entry = &cam_info->ba_cam_entry[idx]; 3222 } 3223 3224 entry->tid = tid; 3225 list_add_tail(&entry->list, &rtwsta->ba_cam_list); 3226 3227 *cam_idx = idx; 3228 3229 return 0; 3230 } 3231 3232 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev, 3233 struct rtw89_sta *rtwsta, u8 tid, u8 *cam_idx) 3234 { 3235 struct rtw89_cam_info *cam_info = &rtwdev->cam_info; 3236 struct rtw89_ba_cam_entry *entry = NULL, *tmp; 3237 u8 idx; 3238 3239 lockdep_assert_held(&rtwdev->mutex); 3240 3241 list_for_each_entry_safe(entry, tmp, &rtwsta->ba_cam_list, list) { 3242 if (entry->tid != tid) 3243 continue; 3244 3245 idx = entry - cam_info->ba_cam_entry; 3246 list_del(&entry->list); 3247 3248 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx); 3249 *cam_idx = idx; 3250 return 0; 3251 } 3252 3253 return -ENOENT; 3254 } 3255 3256 #define RTW89_TYPE_MAPPING(_type) \ 3257 case NL80211_IFTYPE_ ## _type: \ 3258 rtwvif->wifi_role = RTW89_WIFI_ROLE_ ## _type; \ 3259 break 3260 void rtw89_vif_type_mapping(struct ieee80211_vif *vif, bool assoc) 3261 { 3262 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3263 3264 switch (vif->type) { 3265 case NL80211_IFTYPE_STATION: 3266 if (vif->p2p) 3267 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT; 3268 else 3269 rtwvif->wifi_role = RTW89_WIFI_ROLE_STATION; 3270 break; 3271 case NL80211_IFTYPE_AP: 3272 if (vif->p2p) 3273 rtwvif->wifi_role = RTW89_WIFI_ROLE_P2P_GO; 3274 else 3275 rtwvif->wifi_role = RTW89_WIFI_ROLE_AP; 3276 break; 3277 RTW89_TYPE_MAPPING(ADHOC); 3278 RTW89_TYPE_MAPPING(MONITOR); 3279 RTW89_TYPE_MAPPING(MESH_POINT); 3280 default: 3281 WARN_ON(1); 3282 break; 3283 } 3284 3285 switch (vif->type) { 3286 case NL80211_IFTYPE_AP: 3287 case NL80211_IFTYPE_MESH_POINT: 3288 rtwvif->net_type = RTW89_NET_TYPE_AP_MODE; 3289 rtwvif->self_role = RTW89_SELF_ROLE_AP; 3290 break; 3291 case NL80211_IFTYPE_ADHOC: 3292 rtwvif->net_type = RTW89_NET_TYPE_AD_HOC; 3293 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3294 break; 3295 case NL80211_IFTYPE_STATION: 3296 if (assoc) { 3297 rtwvif->net_type = RTW89_NET_TYPE_INFRA; 3298 rtwvif->trigger = vif->bss_conf.he_support; 3299 } else { 3300 rtwvif->net_type = RTW89_NET_TYPE_NO_LINK; 3301 rtwvif->trigger = false; 3302 } 3303 rtwvif->self_role = RTW89_SELF_ROLE_CLIENT; 3304 rtwvif->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL; 3305 break; 3306 case NL80211_IFTYPE_MONITOR: 3307 break; 3308 default: 3309 WARN_ON(1); 3310 break; 3311 } 3312 } 3313 3314 int rtw89_core_sta_add(struct rtw89_dev *rtwdev, 3315 struct ieee80211_vif *vif, 3316 struct ieee80211_sta *sta) 3317 { 3318 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3319 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3320 struct rtw89_hal *hal = &rtwdev->hal; 3321 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num; 3322 int i; 3323 int ret; 3324 3325 rtwsta->rtwdev = rtwdev; 3326 rtwsta->rtwvif = rtwvif; 3327 rtwsta->prev_rssi = 0; 3328 INIT_LIST_HEAD(&rtwsta->ba_cam_list); 3329 skb_queue_head_init(&rtwsta->roc_queue); 3330 3331 for (i = 0; i < ARRAY_SIZE(sta->txq); i++) 3332 rtw89_core_txq_init(rtwdev, sta->txq[i]); 3333 3334 ewma_rssi_init(&rtwsta->avg_rssi); 3335 ewma_snr_init(&rtwsta->avg_snr); 3336 for (i = 0; i < ant_num; i++) { 3337 ewma_rssi_init(&rtwsta->rssi[i]); 3338 ewma_evm_init(&rtwsta->evm_min[i]); 3339 ewma_evm_init(&rtwsta->evm_max[i]); 3340 } 3341 3342 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3343 /* for station mode, assign the mac_id from itself */ 3344 rtwsta->mac_id = rtwvif->mac_id; 3345 /* must do rtw89_reg_6ghz_power_recalc() before rfk channel */ 3346 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, true); 3347 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3348 BTC_ROLE_MSTS_STA_CONN_START); 3349 rtw89_chip_rfk_channel(rtwdev); 3350 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3351 rtwsta->mac_id = rtw89_core_acquire_bit_map(rtwdev->mac_id_map, 3352 RTW89_MAX_MAC_ID_NUM); 3353 if (rtwsta->mac_id == RTW89_MAX_MAC_ID_NUM) 3354 return -ENOSPC; 3355 3356 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta->mac_id, false); 3357 if (ret) { 3358 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3359 rtw89_warn(rtwdev, "failed to send h2c macid pause\n"); 3360 return ret; 3361 } 3362 3363 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3364 RTW89_ROLE_CREATE); 3365 if (ret) { 3366 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3367 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3368 return ret; 3369 } 3370 3371 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, rtwsta); 3372 if (ret) 3373 return ret; 3374 3375 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, rtwsta); 3376 if (ret) 3377 return ret; 3378 3379 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3380 } 3381 3382 return 0; 3383 } 3384 3385 int rtw89_core_sta_disassoc(struct rtw89_dev *rtwdev, 3386 struct ieee80211_vif *vif, 3387 struct ieee80211_sta *sta) 3388 { 3389 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3390 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3391 3392 if (vif->type == NL80211_IFTYPE_STATION) 3393 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, false); 3394 3395 rtwdev->total_sta_assoc--; 3396 if (sta->tdls) 3397 rtwvif->tdls_peer--; 3398 rtwsta->disassoc = true; 3399 3400 return 0; 3401 } 3402 3403 int rtw89_core_sta_disconnect(struct rtw89_dev *rtwdev, 3404 struct ieee80211_vif *vif, 3405 struct ieee80211_sta *sta) 3406 { 3407 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3408 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3409 int ret; 3410 3411 rtw89_mac_bf_monitor_calc(rtwdev, sta, true); 3412 rtw89_mac_bf_disassoc(rtwdev, vif, sta); 3413 rtw89_core_free_sta_pending_ba(rtwdev, sta); 3414 rtw89_core_free_sta_pending_forbid_ba(rtwdev, sta); 3415 rtw89_core_free_sta_pending_roc_tx(rtwdev, sta); 3416 3417 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) 3418 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta->addr_cam); 3419 if (sta->tdls) 3420 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta->bssid_cam); 3421 3422 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3423 rtw89_vif_type_mapping(vif, false); 3424 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif, true); 3425 } 3426 3427 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3428 if (ret) { 3429 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3430 return ret; 3431 } 3432 3433 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, true); 3434 if (ret) { 3435 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3436 return ret; 3437 } 3438 3439 /* update cam aid mac_id net_type */ 3440 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3441 if (ret) { 3442 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3443 return ret; 3444 } 3445 3446 return ret; 3447 } 3448 3449 int rtw89_core_sta_assoc(struct rtw89_dev *rtwdev, 3450 struct ieee80211_vif *vif, 3451 struct ieee80211_sta *sta) 3452 { 3453 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3454 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3455 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif, rtwsta); 3456 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 3457 rtwvif->sub_entity_idx); 3458 int ret; 3459 3460 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3461 if (sta->tdls) { 3462 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif, bssid_cam, sta->addr); 3463 if (ret) { 3464 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n"); 3465 return ret; 3466 } 3467 } 3468 3469 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta->addr_cam, bssid_cam); 3470 if (ret) { 3471 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n"); 3472 return ret; 3473 } 3474 } 3475 3476 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, vif, sta); 3477 if (ret) { 3478 rtw89_warn(rtwdev, "failed to send h2c cmac table\n"); 3479 return ret; 3480 } 3481 3482 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, rtwsta, false); 3483 if (ret) { 3484 rtw89_warn(rtwdev, "failed to send h2c join info\n"); 3485 return ret; 3486 } 3487 3488 /* update cam aid mac_id net_type */ 3489 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, rtwsta, NULL); 3490 if (ret) { 3491 rtw89_warn(rtwdev, "failed to send h2c cam\n"); 3492 return ret; 3493 } 3494 3495 rtwdev->total_sta_assoc++; 3496 if (sta->tdls) 3497 rtwvif->tdls_peer++; 3498 rtw89_phy_ra_assoc(rtwdev, sta); 3499 rtw89_mac_bf_assoc(rtwdev, vif, sta); 3500 rtw89_mac_bf_monitor_calc(rtwdev, sta, false); 3501 3502 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3503 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf; 3504 3505 if (bss_conf->he_support && 3506 !(bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)) 3507 rtwsta->er_cap = true; 3508 3509 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3510 BTC_ROLE_MSTS_STA_CONN_END); 3511 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta->htc_template, chan); 3512 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif); 3513 3514 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif, rtwsta->mac_id); 3515 if (ret) { 3516 rtw89_warn(rtwdev, "failed to send h2c general packet\n"); 3517 return ret; 3518 } 3519 3520 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 3521 } 3522 3523 return ret; 3524 } 3525 3526 int rtw89_core_sta_remove(struct rtw89_dev *rtwdev, 3527 struct ieee80211_vif *vif, 3528 struct ieee80211_sta *sta) 3529 { 3530 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 3531 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 3532 int ret; 3533 3534 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) { 3535 rtw89_reg_6ghz_power_recalc(rtwdev, rtwvif, false); 3536 rtw89_btc_ntfy_role_info(rtwdev, rtwvif, rtwsta, 3537 BTC_ROLE_MSTS_STA_DIS_CONN); 3538 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) { 3539 rtw89_core_release_bit_map(rtwdev->mac_id_map, rtwsta->mac_id); 3540 3541 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, rtwsta, 3542 RTW89_ROLE_REMOVE); 3543 if (ret) { 3544 rtw89_warn(rtwdev, "failed to send h2c role info\n"); 3545 return ret; 3546 } 3547 3548 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_REMOTE_STA_CHANGE); 3549 } 3550 3551 return 0; 3552 } 3553 3554 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3555 struct ieee80211_sta *sta, 3556 struct cfg80211_tid_cfg *tid_conf) 3557 { 3558 struct ieee80211_txq *txq; 3559 struct rtw89_txq *rtwtxq; 3560 u32 mask = tid_conf->mask; 3561 u8 tids = tid_conf->tids; 3562 int tids_nbit = BITS_PER_BYTE; 3563 int i; 3564 3565 for (i = 0; i < tids_nbit; i++, tids >>= 1) { 3566 if (!tids) 3567 break; 3568 3569 if (!(tids & BIT(0))) 3570 continue; 3571 3572 txq = sta->txq[i]; 3573 rtwtxq = (struct rtw89_txq *)txq->drv_priv; 3574 3575 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) { 3576 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) { 3577 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3578 } else { 3579 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) 3580 ieee80211_stop_tx_ba_session(sta, txq->tid); 3581 spin_lock_bh(&rtwdev->ba_lock); 3582 list_del_init(&rtwtxq->list); 3583 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags); 3584 spin_unlock_bh(&rtwdev->ba_lock); 3585 } 3586 } 3587 3588 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) { 3589 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE) 3590 sta->max_amsdu_subframes = 0; 3591 else 3592 sta->max_amsdu_subframes = 1; 3593 } 3594 } 3595 } 3596 3597 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev, 3598 struct ieee80211_sta *sta, 3599 struct cfg80211_tid_config *tid_config) 3600 { 3601 int i; 3602 3603 for (i = 0; i < tid_config->n_tid_conf; i++) 3604 _rtw89_core_set_tid_config(rtwdev, sta, 3605 &tid_config->tid_conf[i]); 3606 } 3607 3608 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev, 3609 struct ieee80211_sta_ht_cap *ht_cap) 3610 { 3611 static const __le16 highest[RF_PATH_MAX] = { 3612 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600), 3613 }; 3614 struct rtw89_hal *hal = &rtwdev->hal; 3615 u8 nss = hal->rx_nss; 3616 int i; 3617 3618 ht_cap->ht_supported = true; 3619 ht_cap->cap = 0; 3620 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 | 3621 IEEE80211_HT_CAP_MAX_AMSDU | 3622 IEEE80211_HT_CAP_TX_STBC | 3623 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 3624 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING; 3625 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 3626 IEEE80211_HT_CAP_DSSSCCK40 | 3627 IEEE80211_HT_CAP_SGI_40; 3628 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 3629 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE; 3630 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; 3631 for (i = 0; i < nss; i++) 3632 ht_cap->mcs.rx_mask[i] = 0xFF; 3633 ht_cap->mcs.rx_mask[4] = 0x01; 3634 ht_cap->mcs.rx_highest = highest[nss - 1]; 3635 } 3636 3637 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev, 3638 struct ieee80211_sta_vht_cap *vht_cap) 3639 { 3640 static const __le16 highest_bw80[RF_PATH_MAX] = { 3641 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733), 3642 }; 3643 static const __le16 highest_bw160[RF_PATH_MAX] = { 3644 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467), 3645 }; 3646 const struct rtw89_chip_info *chip = rtwdev->chip; 3647 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ? 3648 highest_bw160 : highest_bw80; 3649 struct rtw89_hal *hal = &rtwdev->hal; 3650 u16 tx_mcs_map = 0, rx_mcs_map = 0; 3651 u8 sts_cap = 3; 3652 int i; 3653 3654 for (i = 0; i < 8; i++) { 3655 if (i < hal->tx_nss) 3656 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3657 else 3658 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3659 if (i < hal->rx_nss) 3660 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2); 3661 else 3662 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2); 3663 } 3664 3665 vht_cap->vht_supported = true; 3666 vht_cap->cap = IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454 | 3667 IEEE80211_VHT_CAP_SHORT_GI_80 | 3668 IEEE80211_VHT_CAP_RXSTBC_1 | 3669 IEEE80211_VHT_CAP_HTC_VHT | 3670 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK | 3671 0; 3672 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC; 3673 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC; 3674 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE | 3675 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE; 3676 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT; 3677 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3678 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ | 3679 IEEE80211_VHT_CAP_SHORT_GI_160; 3680 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map); 3681 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map); 3682 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1]; 3683 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1]; 3684 3685 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW)) 3686 vht_cap->vht_mcs.tx_highest |= 3687 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE); 3688 } 3689 3690 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev, 3691 enum nl80211_band band, 3692 enum nl80211_iftype iftype, 3693 struct ieee80211_sband_iftype_data *iftype_data) 3694 { 3695 const struct rtw89_chip_info *chip = rtwdev->chip; 3696 struct rtw89_hal *hal = &rtwdev->hal; 3697 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) || 3698 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV); 3699 struct ieee80211_sta_he_cap *he_cap; 3700 int nss = hal->rx_nss; 3701 u8 *mac_cap_info; 3702 u8 *phy_cap_info; 3703 u16 mcs_map = 0; 3704 int i; 3705 3706 for (i = 0; i < 8; i++) { 3707 if (i < nss) 3708 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2); 3709 else 3710 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2); 3711 } 3712 3713 he_cap = &iftype_data->he_cap; 3714 mac_cap_info = he_cap->he_cap_elem.mac_cap_info; 3715 phy_cap_info = he_cap->he_cap_elem.phy_cap_info; 3716 3717 he_cap->has_he = true; 3718 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE; 3719 if (iftype == NL80211_IFTYPE_STATION) 3720 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US; 3721 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK | 3722 IEEE80211_HE_MAC_CAP2_BSR; 3723 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2; 3724 if (iftype == NL80211_IFTYPE_AP) 3725 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL; 3726 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS | 3727 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU; 3728 if (iftype == NL80211_IFTYPE_STATION) 3729 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX; 3730 if (band == NL80211_BAND_2GHZ) { 3731 phy_cap_info[0] = 3732 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G; 3733 } else { 3734 phy_cap_info[0] = 3735 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G; 3736 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3737 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G; 3738 } 3739 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A | 3740 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD | 3741 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US; 3742 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US | 3743 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ | 3744 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ | 3745 IEEE80211_HE_PHY_CAP2_DOPPLER_TX; 3746 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM; 3747 if (iftype == NL80211_IFTYPE_STATION) 3748 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM | 3749 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2; 3750 if (iftype == NL80211_IFTYPE_AP) 3751 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU; 3752 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE | 3753 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4; 3754 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3755 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4; 3756 phy_cap_info[5] = no_ng16 ? 0 : 3757 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK | 3758 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK; 3759 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU | 3760 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU | 3761 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB | 3762 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE; 3763 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP | 3764 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI | 3765 IEEE80211_HE_PHY_CAP7_MAX_NC_1; 3766 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI | 3767 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI | 3768 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996; 3769 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 3770 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU | 3771 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU; 3772 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM | 3773 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU | 3774 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB | 3775 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB | 3776 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US, 3777 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK); 3778 if (iftype == NL80211_IFTYPE_STATION) 3779 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU; 3780 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map); 3781 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map); 3782 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) { 3783 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map); 3784 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map); 3785 } 3786 3787 if (band == NL80211_BAND_6GHZ) { 3788 __le16 capa; 3789 3790 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE, 3791 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) | 3792 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K, 3793 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) | 3794 le16_encode_bits(IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454, 3795 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN); 3796 iftype_data->he_6ghz_capa.capa = capa; 3797 } 3798 } 3799 3800 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev, 3801 enum nl80211_band band, 3802 enum nl80211_iftype iftype, 3803 struct ieee80211_sband_iftype_data *iftype_data) 3804 { 3805 const struct rtw89_chip_info *chip = rtwdev->chip; 3806 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem; 3807 struct ieee80211_eht_mcs_nss_supp *eht_nss; 3808 struct ieee80211_sta_eht_cap *eht_cap; 3809 struct rtw89_hal *hal = &rtwdev->hal; 3810 bool support_320mhz = false; 3811 int sts = 8; 3812 u8 val; 3813 3814 if (chip->chip_gen == RTW89_CHIP_AX) 3815 return; 3816 3817 if (band == NL80211_BAND_6GHZ && 3818 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320)) 3819 support_320mhz = true; 3820 3821 eht_cap = &iftype_data->eht_cap; 3822 eht_cap_elem = &eht_cap->eht_cap_elem; 3823 eht_nss = &eht_cap->eht_mcs_nss_supp; 3824 3825 eht_cap->has_eht = true; 3826 3827 eht_cap_elem->mac_cap_info[0] = 3828 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_7991, 3829 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK); 3830 eht_cap_elem->mac_cap_info[1] = 0; 3831 3832 eht_cap_elem->phy_cap_info[0] = 3833 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI | 3834 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE; 3835 if (support_320mhz) 3836 eht_cap_elem->phy_cap_info[0] |= 3837 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ; 3838 3839 eht_cap_elem->phy_cap_info[0] |= 3840 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)), 3841 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK); 3842 eht_cap_elem->phy_cap_info[1] = 3843 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)), 3844 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) | 3845 u8_encode_bits(sts - 1, 3846 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK); 3847 if (support_320mhz) 3848 eht_cap_elem->phy_cap_info[1] |= 3849 u8_encode_bits(sts - 1, 3850 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK); 3851 3852 eht_cap_elem->phy_cap_info[2] = 0; 3853 3854 eht_cap_elem->phy_cap_info[3] = 3855 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK | 3856 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK | 3857 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK | 3858 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK; 3859 3860 eht_cap_elem->phy_cap_info[4] = 3861 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP | 3862 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK); 3863 3864 eht_cap_elem->phy_cap_info[5] = 3865 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US, 3866 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK); 3867 3868 eht_cap_elem->phy_cap_info[6] = 0; 3869 eht_cap_elem->phy_cap_info[7] = 0; 3870 eht_cap_elem->phy_cap_info[8] = 0; 3871 3872 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) | 3873 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX); 3874 eht_nss->bw._80.rx_tx_mcs9_max_nss = val; 3875 eht_nss->bw._80.rx_tx_mcs11_max_nss = val; 3876 eht_nss->bw._80.rx_tx_mcs13_max_nss = val; 3877 eht_nss->bw._160.rx_tx_mcs9_max_nss = val; 3878 eht_nss->bw._160.rx_tx_mcs11_max_nss = val; 3879 eht_nss->bw._160.rx_tx_mcs13_max_nss = val; 3880 if (support_320mhz) { 3881 eht_nss->bw._320.rx_tx_mcs9_max_nss = val; 3882 eht_nss->bw._320.rx_tx_mcs11_max_nss = val; 3883 eht_nss->bw._320.rx_tx_mcs13_max_nss = val; 3884 } 3885 } 3886 3887 #define RTW89_SBAND_IFTYPES_NR 2 3888 3889 static void rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev, 3890 enum nl80211_band band, 3891 struct ieee80211_supported_band *sband) 3892 { 3893 struct ieee80211_sband_iftype_data *iftype_data; 3894 enum nl80211_iftype iftype; 3895 int idx = 0; 3896 3897 iftype_data = kcalloc(RTW89_SBAND_IFTYPES_NR, sizeof(*iftype_data), GFP_KERNEL); 3898 if (!iftype_data) 3899 return; 3900 3901 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) { 3902 switch (iftype) { 3903 case NL80211_IFTYPE_STATION: 3904 case NL80211_IFTYPE_AP: 3905 break; 3906 default: 3907 continue; 3908 } 3909 3910 if (idx >= RTW89_SBAND_IFTYPES_NR) { 3911 rtw89_warn(rtwdev, "run out of iftype_data\n"); 3912 break; 3913 } 3914 3915 iftype_data[idx].types_mask = BIT(iftype); 3916 3917 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]); 3918 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]); 3919 3920 idx++; 3921 } 3922 3923 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx); 3924 } 3925 3926 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev) 3927 { 3928 struct ieee80211_hw *hw = rtwdev->hw; 3929 struct ieee80211_supported_band *sband_2ghz = NULL, *sband_5ghz = NULL; 3930 struct ieee80211_supported_band *sband_6ghz = NULL; 3931 u32 size = sizeof(struct ieee80211_supported_band); 3932 u8 support_bands = rtwdev->chip->support_bands; 3933 3934 if (support_bands & BIT(NL80211_BAND_2GHZ)) { 3935 sband_2ghz = kmemdup(&rtw89_sband_2ghz, size, GFP_KERNEL); 3936 if (!sband_2ghz) 3937 goto err; 3938 rtw89_init_ht_cap(rtwdev, &sband_2ghz->ht_cap); 3939 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband_2ghz); 3940 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband_2ghz; 3941 } 3942 3943 if (support_bands & BIT(NL80211_BAND_5GHZ)) { 3944 sband_5ghz = kmemdup(&rtw89_sband_5ghz, size, GFP_KERNEL); 3945 if (!sband_5ghz) 3946 goto err; 3947 rtw89_init_ht_cap(rtwdev, &sband_5ghz->ht_cap); 3948 rtw89_init_vht_cap(rtwdev, &sband_5ghz->vht_cap); 3949 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband_5ghz); 3950 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband_5ghz; 3951 } 3952 3953 if (support_bands & BIT(NL80211_BAND_6GHZ)) { 3954 sband_6ghz = kmemdup(&rtw89_sband_6ghz, size, GFP_KERNEL); 3955 if (!sband_6ghz) 3956 goto err; 3957 rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband_6ghz); 3958 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband_6ghz; 3959 } 3960 3961 return 0; 3962 3963 err: 3964 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3965 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3966 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3967 if (sband_2ghz) 3968 kfree((__force void *)sband_2ghz->iftype_data); 3969 if (sband_5ghz) 3970 kfree((__force void *)sband_5ghz->iftype_data); 3971 if (sband_6ghz) 3972 kfree((__force void *)sband_6ghz->iftype_data); 3973 kfree(sband_2ghz); 3974 kfree(sband_5ghz); 3975 kfree(sband_6ghz); 3976 return -ENOMEM; 3977 } 3978 3979 static void rtw89_core_clr_supported_band(struct rtw89_dev *rtwdev) 3980 { 3981 struct ieee80211_hw *hw = rtwdev->hw; 3982 3983 if (hw->wiphy->bands[NL80211_BAND_2GHZ]) 3984 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_2GHZ]->iftype_data); 3985 if (hw->wiphy->bands[NL80211_BAND_5GHZ]) 3986 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_5GHZ]->iftype_data); 3987 if (hw->wiphy->bands[NL80211_BAND_6GHZ]) 3988 kfree((__force void *)hw->wiphy->bands[NL80211_BAND_6GHZ]->iftype_data); 3989 kfree(hw->wiphy->bands[NL80211_BAND_2GHZ]); 3990 kfree(hw->wiphy->bands[NL80211_BAND_5GHZ]); 3991 kfree(hw->wiphy->bands[NL80211_BAND_6GHZ]); 3992 hw->wiphy->bands[NL80211_BAND_2GHZ] = NULL; 3993 hw->wiphy->bands[NL80211_BAND_5GHZ] = NULL; 3994 hw->wiphy->bands[NL80211_BAND_6GHZ] = NULL; 3995 } 3996 3997 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev) 3998 { 3999 int i; 4000 4001 for (i = 0; i < RTW89_PHY_MAX; i++) 4002 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]); 4003 for (i = 0; i < RTW89_PHY_MAX; i++) 4004 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX; 4005 } 4006 4007 void rtw89_core_update_beacon_work(struct work_struct *work) 4008 { 4009 struct rtw89_dev *rtwdev; 4010 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif, 4011 update_beacon_work); 4012 4013 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE) 4014 return; 4015 4016 rtwdev = rtwvif->rtwdev; 4017 mutex_lock(&rtwdev->mutex); 4018 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif); 4019 mutex_unlock(&rtwdev->mutex); 4020 } 4021 4022 int rtw89_wait_for_cond(struct rtw89_wait_info *wait, unsigned int cond) 4023 { 4024 struct completion *cmpl = &wait->completion; 4025 unsigned long timeout; 4026 unsigned int cur; 4027 4028 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond); 4029 if (cur != RTW89_WAIT_COND_IDLE) 4030 return -EBUSY; 4031 4032 timeout = wait_for_completion_timeout(cmpl, RTW89_WAIT_FOR_COND_TIMEOUT); 4033 if (timeout == 0) { 4034 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE); 4035 return -ETIMEDOUT; 4036 } 4037 4038 if (wait->data.err) 4039 return -EFAULT; 4040 4041 return 0; 4042 } 4043 4044 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond, 4045 const struct rtw89_completion_data *data) 4046 { 4047 unsigned int cur; 4048 4049 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE); 4050 if (cur != cond) 4051 return; 4052 4053 wait->data = *data; 4054 complete(&wait->completion); 4055 } 4056 4057 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event) 4058 { 4059 u16 bt_req_len; 4060 4061 switch (event) { 4062 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT: 4063 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0); 4064 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4065 "coex updates BT req len to %d TU\n", bt_req_len); 4066 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE); 4067 break; 4068 default: 4069 if (event < NUM_OF_RTW89_BTC_HMSG) 4070 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4071 "unhandled BTC HMSG event: %d\n", event); 4072 else 4073 rtw89_warn(rtwdev, 4074 "unrecognized BTC HMSG event: %d\n", event); 4075 break; 4076 } 4077 } 4078 4079 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks) 4080 { 4081 const struct dmi_system_id *match; 4082 enum rtw89_quirks quirk; 4083 4084 if (!quirks) 4085 return; 4086 4087 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) { 4088 quirk = (uintptr_t)match->driver_data; 4089 if (quirk >= NUM_OF_RTW89_QUIRKS) 4090 continue; 4091 4092 set_bit(quirk, rtwdev->quirks); 4093 } 4094 } 4095 EXPORT_SYMBOL(rtw89_check_quirks); 4096 4097 int rtw89_core_start(struct rtw89_dev *rtwdev) 4098 { 4099 int ret; 4100 4101 ret = rtw89_mac_init(rtwdev); 4102 if (ret) { 4103 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret); 4104 return ret; 4105 } 4106 4107 rtw89_btc_ntfy_poweron(rtwdev); 4108 4109 /* efuse process */ 4110 4111 /* pre-config BB/RF, BB reset/RFC reset */ 4112 ret = rtw89_chip_reset_bb_rf(rtwdev); 4113 if (ret) 4114 return ret; 4115 4116 rtw89_phy_init_bb_reg(rtwdev); 4117 rtw89_chip_bb_postinit(rtwdev); 4118 rtw89_phy_init_rf_reg(rtwdev, false); 4119 4120 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL); 4121 4122 rtw89_phy_dm_init(rtwdev); 4123 4124 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 4125 rtw89_mac_update_rts_threshold(rtwdev, RTW89_MAC_0); 4126 4127 rtw89_tas_reset(rtwdev); 4128 4129 ret = rtw89_hci_start(rtwdev); 4130 if (ret) { 4131 rtw89_err(rtwdev, "failed to start hci\n"); 4132 return ret; 4133 } 4134 4135 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->track_work, 4136 RTW89_TRACK_WORK_PERIOD); 4137 4138 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4139 4140 rtw89_chip_rfk_init_late(rtwdev); 4141 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON); 4142 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable); 4143 rtw89_fw_h2c_init_ba_cam(rtwdev); 4144 4145 return 0; 4146 } 4147 4148 void rtw89_core_stop(struct rtw89_dev *rtwdev) 4149 { 4150 struct rtw89_btc *btc = &rtwdev->btc; 4151 4152 /* Prvent to stop twice; enter_ips and ops_stop */ 4153 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags)) 4154 return; 4155 4156 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF); 4157 4158 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags); 4159 4160 mutex_unlock(&rtwdev->mutex); 4161 4162 cancel_work_sync(&rtwdev->c2h_work); 4163 cancel_work_sync(&rtwdev->cancel_6ghz_probe_work); 4164 cancel_work_sync(&btc->eapol_notify_work); 4165 cancel_work_sync(&btc->arp_notify_work); 4166 cancel_work_sync(&btc->dhcp_notify_work); 4167 cancel_work_sync(&btc->icmp_notify_work); 4168 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work); 4169 cancel_delayed_work_sync(&rtwdev->track_work); 4170 cancel_delayed_work_sync(&rtwdev->chanctx_work); 4171 cancel_delayed_work_sync(&rtwdev->coex_act1_work); 4172 cancel_delayed_work_sync(&rtwdev->coex_bt_devinfo_work); 4173 cancel_delayed_work_sync(&rtwdev->coex_rfk_chk_work); 4174 cancel_delayed_work_sync(&rtwdev->cfo_track_work); 4175 cancel_delayed_work_sync(&rtwdev->forbid_ba_work); 4176 cancel_delayed_work_sync(&rtwdev->antdiv_work); 4177 4178 mutex_lock(&rtwdev->mutex); 4179 4180 rtw89_btc_ntfy_poweroff(rtwdev); 4181 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4182 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true); 4183 rtw89_hci_stop(rtwdev); 4184 rtw89_hci_deinit(rtwdev); 4185 rtw89_mac_pwr_off(rtwdev); 4186 rtw89_hci_reset(rtwdev); 4187 } 4188 4189 int rtw89_core_init(struct rtw89_dev *rtwdev) 4190 { 4191 struct rtw89_btc *btc = &rtwdev->btc; 4192 u8 band; 4193 4194 INIT_LIST_HEAD(&rtwdev->ba_list); 4195 INIT_LIST_HEAD(&rtwdev->forbid_ba_list); 4196 INIT_LIST_HEAD(&rtwdev->rtwvifs_list); 4197 INIT_LIST_HEAD(&rtwdev->early_h2c_list); 4198 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) { 4199 if (!(rtwdev->chip->support_bands & BIT(band))) 4200 continue; 4201 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]); 4202 } 4203 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work); 4204 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work); 4205 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work); 4206 INIT_DELAYED_WORK(&rtwdev->track_work, rtw89_track_work); 4207 INIT_DELAYED_WORK(&rtwdev->chanctx_work, rtw89_chanctx_work); 4208 INIT_DELAYED_WORK(&rtwdev->coex_act1_work, rtw89_coex_act1_work); 4209 INIT_DELAYED_WORK(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work); 4210 INIT_DELAYED_WORK(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work); 4211 INIT_DELAYED_WORK(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work); 4212 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work); 4213 INIT_DELAYED_WORK(&rtwdev->antdiv_work, rtw89_phy_antdiv_work); 4214 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0); 4215 if (!rtwdev->txq_wq) 4216 return -ENOMEM; 4217 spin_lock_init(&rtwdev->ba_lock); 4218 spin_lock_init(&rtwdev->rpwm_lock); 4219 mutex_init(&rtwdev->mutex); 4220 mutex_init(&rtwdev->rf_mutex); 4221 rtwdev->total_sta_assoc = 0; 4222 4223 rtw89_init_wait(&rtwdev->mcc.wait); 4224 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait); 4225 4226 INIT_WORK(&rtwdev->c2h_work, rtw89_fw_c2h_work); 4227 INIT_WORK(&rtwdev->ips_work, rtw89_ips_work); 4228 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work); 4229 INIT_WORK(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work); 4230 4231 skb_queue_head_init(&rtwdev->c2h_queue); 4232 rtw89_core_ppdu_sts_init(rtwdev); 4233 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats); 4234 4235 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR; 4236 rtwdev->dbcc_en = false; 4237 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT; 4238 rtwdev->mac.qta_mode = RTW89_QTA_SCC; 4239 4240 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4241 rtwdev->dbcc_en = true; 4242 rtwdev->mac.qta_mode = RTW89_QTA_DBCC; 4243 rtwdev->mlo_dbcc_mode = MLO_2_PLUS_0_1RF; 4244 } 4245 4246 INIT_WORK(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work); 4247 INIT_WORK(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work); 4248 INIT_WORK(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work); 4249 INIT_WORK(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work); 4250 4251 init_completion(&rtwdev->fw.req.completion); 4252 init_completion(&rtwdev->rfk_wait.completion); 4253 4254 schedule_work(&rtwdev->load_firmware_work); 4255 4256 rtw89_ser_init(rtwdev); 4257 rtw89_entity_init(rtwdev); 4258 rtw89_tas_init(rtwdev); 4259 4260 return 0; 4261 } 4262 EXPORT_SYMBOL(rtw89_core_init); 4263 4264 void rtw89_core_deinit(struct rtw89_dev *rtwdev) 4265 { 4266 rtw89_ser_deinit(rtwdev); 4267 rtw89_unload_firmware(rtwdev); 4268 rtw89_fw_free_all_early_h2c(rtwdev); 4269 4270 destroy_workqueue(rtwdev->txq_wq); 4271 mutex_destroy(&rtwdev->rf_mutex); 4272 mutex_destroy(&rtwdev->mutex); 4273 } 4274 EXPORT_SYMBOL(rtw89_core_deinit); 4275 4276 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4277 const u8 *mac_addr, bool hw_scan) 4278 { 4279 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 4280 rtwvif->sub_entity_idx); 4281 4282 rtwdev->scanning = true; 4283 rtw89_leave_lps(rtwdev); 4284 if (hw_scan) 4285 rtw89_leave_ips_by_hwflags(rtwdev); 4286 4287 ether_addr_copy(rtwvif->mac_addr, mac_addr); 4288 rtw89_btc_ntfy_scan_start(rtwdev, RTW89_PHY_0, chan->band_type); 4289 rtw89_chip_rfk_scan(rtwdev, true); 4290 rtw89_hci_recalc_int_mit(rtwdev); 4291 rtw89_phy_config_edcca(rtwdev, true); 4292 4293 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, mac_addr); 4294 } 4295 4296 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev, 4297 struct ieee80211_vif *vif, bool hw_scan) 4298 { 4299 struct rtw89_vif *rtwvif = vif ? (struct rtw89_vif *)vif->drv_priv : NULL; 4300 4301 if (!rtwvif) 4302 return; 4303 4304 ether_addr_copy(rtwvif->mac_addr, vif->addr); 4305 rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4306 4307 rtw89_chip_rfk_scan(rtwdev, false); 4308 rtw89_btc_ntfy_scan_finish(rtwdev, RTW89_PHY_0); 4309 rtw89_phy_config_edcca(rtwdev, false); 4310 4311 rtwdev->scanning = false; 4312 rtwdev->dig.bypass_dig = true; 4313 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE)) 4314 ieee80211_queue_work(rtwdev->hw, &rtwdev->ips_work); 4315 } 4316 4317 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev) 4318 { 4319 const struct rtw89_chip_info *chip = rtwdev->chip; 4320 int ret; 4321 u8 val; 4322 u8 cv; 4323 4324 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK); 4325 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) { 4326 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD) 4327 cv = CHIP_CAV; 4328 else 4329 cv = CHIP_CBV; 4330 } 4331 4332 rtwdev->hal.cv = cv; 4333 4334 if (chip->chip_id == RTL8852B || chip->chip_id == RTL8851B) { 4335 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val); 4336 if (ret) 4337 return; 4338 4339 rtwdev->hal.acv = u8_get_bits(val, XTAL_SI_ACV_MASK); 4340 } 4341 } 4342 4343 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev) 4344 { 4345 rtwdev->hal.support_cckpd = 4346 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) && 4347 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV); 4348 rtwdev->hal.support_igi = 4349 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV; 4350 } 4351 4352 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev) 4353 { 4354 const struct rtw89_chip_info *chip = rtwdev->chip; 4355 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf; 4356 struct rtw89_efuse *efuse = &rtwdev->efuse; 4357 const struct rtw89_rfe_parms *sel; 4358 u8 rfe_type = efuse->rfe_type; 4359 4360 if (!conf) { 4361 sel = chip->dflt_parms; 4362 goto out; 4363 } 4364 4365 while (conf->rfe_parms) { 4366 if (rfe_type == conf->rfe_type) { 4367 sel = conf->rfe_parms; 4368 goto out; 4369 } 4370 conf++; 4371 } 4372 4373 sel = chip->dflt_parms; 4374 4375 out: 4376 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel); 4377 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl); 4378 } 4379 4380 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev) 4381 { 4382 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4383 int ret; 4384 4385 ret = rtw89_mac_partial_init(rtwdev, false); 4386 if (ret) 4387 return ret; 4388 4389 ret = mac->parse_efuse_map(rtwdev); 4390 if (ret) 4391 return ret; 4392 4393 ret = mac->parse_phycap_map(rtwdev); 4394 if (ret) 4395 return ret; 4396 4397 ret = rtw89_mac_setup_phycap(rtwdev); 4398 if (ret) 4399 return ret; 4400 4401 rtw89_core_setup_phycap(rtwdev); 4402 4403 rtw89_hci_mac_pre_deinit(rtwdev); 4404 4405 rtw89_mac_pwr_off(rtwdev); 4406 4407 return 0; 4408 } 4409 4410 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev) 4411 { 4412 rtw89_chip_fem_setup(rtwdev); 4413 4414 return 0; 4415 } 4416 4417 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev) 4418 { 4419 int ret; 4420 4421 rtw89_read_chip_ver(rtwdev); 4422 4423 ret = rtw89_wait_firmware_completion(rtwdev); 4424 if (ret) { 4425 rtw89_err(rtwdev, "failed to wait firmware completion\n"); 4426 return ret; 4427 } 4428 4429 ret = rtw89_fw_recognize(rtwdev); 4430 if (ret) { 4431 rtw89_err(rtwdev, "failed to recognize firmware\n"); 4432 return ret; 4433 } 4434 4435 ret = rtw89_chip_efuse_info_setup(rtwdev); 4436 if (ret) 4437 return ret; 4438 4439 ret = rtw89_fw_recognize_elements(rtwdev); 4440 if (ret) { 4441 rtw89_err(rtwdev, "failed to recognize firmware elements\n"); 4442 return ret; 4443 } 4444 4445 ret = rtw89_chip_board_info_setup(rtwdev); 4446 if (ret) 4447 return ret; 4448 4449 rtw89_core_setup_rfe_parms(rtwdev); 4450 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev); 4451 4452 return 0; 4453 } 4454 EXPORT_SYMBOL(rtw89_chip_info_setup); 4455 4456 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev) 4457 { 4458 const struct rtw89_chip_info *chip = rtwdev->chip; 4459 struct ieee80211_hw *hw = rtwdev->hw; 4460 struct rtw89_efuse *efuse = &rtwdev->efuse; 4461 struct rtw89_hal *hal = &rtwdev->hal; 4462 int ret; 4463 int tx_headroom = IEEE80211_HT_CTL_LEN; 4464 4465 hw->vif_data_size = sizeof(struct rtw89_vif); 4466 hw->sta_data_size = sizeof(struct rtw89_sta); 4467 hw->txq_data_size = sizeof(struct rtw89_txq); 4468 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg); 4469 4470 SET_IEEE80211_PERM_ADDR(hw, efuse->addr); 4471 4472 hw->extra_tx_headroom = tx_headroom; 4473 hw->queues = IEEE80211_NUM_ACS; 4474 hw->max_rx_aggregation_subframes = RTW89_MAX_RX_AGG_NUM; 4475 hw->max_tx_aggregation_subframes = RTW89_MAX_TX_AGG_NUM; 4476 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL; 4477 4478 ieee80211_hw_set(hw, SIGNAL_DBM); 4479 ieee80211_hw_set(hw, HAS_RATE_CONTROL); 4480 ieee80211_hw_set(hw, MFP_CAPABLE); 4481 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 4482 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 4483 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 4484 ieee80211_hw_set(hw, TX_AMSDU); 4485 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT); 4486 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU); 4487 ieee80211_hw_set(hw, SUPPORTS_PS); 4488 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 4489 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS); 4490 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID); 4491 ieee80211_hw_set(hw, WANT_MONITOR_VIF); 4492 4493 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) 4494 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW); 4495 4496 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw)) 4497 ieee80211_hw_set(hw, CONNECTION_MONITOR); 4498 4499 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | 4500 BIT(NL80211_IFTYPE_AP) | 4501 BIT(NL80211_IFTYPE_P2P_CLIENT) | 4502 BIT(NL80211_IFTYPE_P2P_GO); 4503 4504 if (hal->ant_diversity) { 4505 hw->wiphy->available_antennas_tx = 0x3; 4506 hw->wiphy->available_antennas_rx = 0x3; 4507 } else { 4508 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1; 4509 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1; 4510 } 4511 4512 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS | 4513 WIPHY_FLAG_TDLS_EXTERNAL_SETUP | 4514 WIPHY_FLAG_AP_UAPSD | 4515 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK; 4516 4517 if (!chip->support_rnr) 4518 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ; 4519 4520 if (chip->chip_gen == RTW89_CHIP_BE) 4521 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT; 4522 4523 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR; 4524 4525 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID; 4526 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN; 4527 4528 #ifdef CONFIG_PM 4529 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub; 4530 #endif 4531 4532 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4533 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL); 4534 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4535 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL); 4536 hw->wiphy->max_remain_on_channel_duration = 1000; 4537 4538 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0); 4539 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN); 4540 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL); 4541 4542 ret = rtw89_core_set_supported_band(rtwdev); 4543 if (ret) { 4544 rtw89_err(rtwdev, "failed to set supported band\n"); 4545 return ret; 4546 } 4547 4548 ret = rtw89_regd_setup(rtwdev); 4549 if (ret) { 4550 rtw89_err(rtwdev, "failed to set up regd\n"); 4551 goto err_free_supported_band; 4552 } 4553 4554 hw->wiphy->sar_capa = &rtw89_sar_capa; 4555 4556 ret = ieee80211_register_hw(hw); 4557 if (ret) { 4558 rtw89_err(rtwdev, "failed to register hw\n"); 4559 goto err_free_supported_band; 4560 } 4561 4562 ret = rtw89_regd_init(rtwdev, rtw89_regd_notifier); 4563 if (ret) { 4564 rtw89_err(rtwdev, "failed to init regd\n"); 4565 goto err_unregister_hw; 4566 } 4567 4568 return 0; 4569 4570 err_unregister_hw: 4571 ieee80211_unregister_hw(hw); 4572 err_free_supported_band: 4573 rtw89_core_clr_supported_band(rtwdev); 4574 4575 return ret; 4576 } 4577 4578 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev) 4579 { 4580 struct ieee80211_hw *hw = rtwdev->hw; 4581 4582 ieee80211_unregister_hw(hw); 4583 rtw89_core_clr_supported_band(rtwdev); 4584 } 4585 4586 int rtw89_core_register(struct rtw89_dev *rtwdev) 4587 { 4588 int ret; 4589 4590 ret = rtw89_core_register_hw(rtwdev); 4591 if (ret) { 4592 rtw89_err(rtwdev, "failed to register core hw\n"); 4593 return ret; 4594 } 4595 4596 rtw89_debugfs_init(rtwdev); 4597 4598 return 0; 4599 } 4600 EXPORT_SYMBOL(rtw89_core_register); 4601 4602 void rtw89_core_unregister(struct rtw89_dev *rtwdev) 4603 { 4604 rtw89_core_unregister_hw(rtwdev); 4605 } 4606 EXPORT_SYMBOL(rtw89_core_unregister); 4607 4608 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device, 4609 u32 bus_data_size, 4610 const struct rtw89_chip_info *chip) 4611 { 4612 struct rtw89_fw_info early_fw = {}; 4613 const struct firmware *firmware; 4614 struct ieee80211_hw *hw; 4615 struct rtw89_dev *rtwdev; 4616 struct ieee80211_ops *ops; 4617 u32 driver_data_size; 4618 int fw_format = -1; 4619 bool no_chanctx; 4620 4621 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format); 4622 4623 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL); 4624 if (!ops) 4625 goto err; 4626 4627 no_chanctx = chip->support_chanctx_num == 0 || 4628 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) || 4629 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw); 4630 4631 if (no_chanctx) { 4632 ops->add_chanctx = ieee80211_emulate_add_chanctx; 4633 ops->remove_chanctx = ieee80211_emulate_remove_chanctx; 4634 ops->change_chanctx = ieee80211_emulate_change_chanctx; 4635 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx; 4636 ops->assign_vif_chanctx = NULL; 4637 ops->unassign_vif_chanctx = NULL; 4638 ops->remain_on_channel = NULL; 4639 ops->cancel_remain_on_channel = NULL; 4640 } 4641 4642 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size; 4643 hw = ieee80211_alloc_hw(driver_data_size, ops); 4644 if (!hw) 4645 goto err; 4646 4647 hw->wiphy->iface_combinations = rtw89_iface_combs; 4648 4649 if (no_chanctx || chip->support_chanctx_num == 1) 4650 hw->wiphy->n_iface_combinations = 1; 4651 else 4652 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs); 4653 4654 rtwdev = hw->priv; 4655 rtwdev->hw = hw; 4656 rtwdev->dev = device; 4657 rtwdev->ops = ops; 4658 rtwdev->chip = chip; 4659 rtwdev->fw.req.firmware = firmware; 4660 rtwdev->fw.fw_format = fw_format; 4661 4662 rtw89_debug(rtwdev, RTW89_DBG_FW, "probe driver %s chanctx\n", 4663 no_chanctx ? "without" : "with"); 4664 4665 return rtwdev; 4666 4667 err: 4668 kfree(ops); 4669 release_firmware(firmware); 4670 return NULL; 4671 } 4672 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw); 4673 4674 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev) 4675 { 4676 kfree(rtwdev->ops); 4677 kfree(rtwdev->rfe_data); 4678 release_firmware(rtwdev->fw.req.firmware); 4679 ieee80211_free_hw(rtwdev->hw); 4680 } 4681 EXPORT_SYMBOL(rtw89_free_ieee80211_hw); 4682 4683 MODULE_AUTHOR("Realtek Corporation"); 4684 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module"); 4685 MODULE_LICENSE("Dual BSD/GPL"); 4686