1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "coex.h" 6 #include "debug.h" 7 #include "fw.h" 8 #include "mac.h" 9 #include "phy.h" 10 #include "ps.h" 11 #include "reg.h" 12 13 #define RTW89_COEX_VERSION 0x07000113 14 #define FCXDEF_STEP 50 /* MUST <= FCXMAX_STEP and match with wl fw*/ 15 #define BTC_E2G_LIMIT_DEF 80 16 17 enum btc_fbtc_tdma_template { 18 CXTD_OFF = 0x0, 19 CXTD_OFF_B2, 20 CXTD_OFF_EXT, 21 CXTD_FIX, 22 CXTD_PFIX, 23 CXTD_AUTO, 24 CXTD_PAUTO, 25 CXTD_AUTO2, 26 CXTD_PAUTO2, 27 CXTD_MAX, 28 }; 29 30 enum btc_fbtc_tdma_type { 31 CXTDMA_OFF = 0x0, 32 CXTDMA_FIX = 0x1, 33 CXTDMA_AUTO = 0x2, 34 CXTDMA_AUTO2 = 0x3, 35 CXTDMA_MAX 36 }; 37 38 enum btc_fbtc_tdma_rx_flow_ctrl { 39 CXFLC_OFF = 0x0, 40 CXFLC_NULLP = 0x1, 41 CXFLC_QOSNULL = 0x2, 42 CXFLC_CTS = 0x3, 43 CXFLC_MAX 44 }; 45 46 enum btc_fbtc_tdma_wlan_tx_pause { 47 CXTPS_OFF = 0x0, /* no wl tx pause*/ 48 CXTPS_ON = 0x1, 49 CXTPS_MAX 50 }; 51 52 enum btc_mlme_state { 53 MLME_NO_LINK, 54 MLME_LINKING, 55 MLME_LINKED, 56 }; 57 58 struct btc_fbtc_1slot { 59 u8 fver; 60 u8 sid; /* slot id */ 61 struct rtw89_btc_fbtc_slot slot; 62 } __packed; 63 64 static const struct rtw89_btc_fbtc_tdma t_def[] = { 65 [CXTD_OFF] = { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, 66 [CXTD_OFF_B2] = { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 1, 0, 0}, 67 [CXTD_OFF_EXT] = { CXTDMA_OFF, CXFLC_OFF, CXTPS_OFF, 0, 0, 2, 0, 0}, 68 [CXTD_FIX] = { CXTDMA_FIX, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, 69 [CXTD_PFIX] = { CXTDMA_FIX, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, 70 [CXTD_AUTO] = { CXTDMA_AUTO, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, 71 [CXTD_PAUTO] = { CXTDMA_AUTO, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0}, 72 [CXTD_AUTO2] = {CXTDMA_AUTO2, CXFLC_OFF, CXTPS_OFF, 0, 0, 0, 0, 0}, 73 [CXTD_PAUTO2] = {CXTDMA_AUTO2, CXFLC_NULLP, CXTPS_ON, 0, 5, 0, 0, 0} 74 }; 75 76 #define __DEF_FBTC_SLOT(__dur, __cxtbl, __cxtype) \ 77 { .dur = cpu_to_le16(__dur), .cxtbl = cpu_to_le32(__cxtbl), \ 78 .cxtype = cpu_to_le16(__cxtype),} 79 80 static const struct rtw89_btc_fbtc_slot s_def[] = { 81 [CXST_OFF] = __DEF_FBTC_SLOT(100, 0x55555555, SLOT_MIX), 82 [CXST_B2W] = __DEF_FBTC_SLOT(5, 0xea5a5a5a, SLOT_ISO), 83 [CXST_W1] = __DEF_FBTC_SLOT(70, 0xea5a5a5a, SLOT_ISO), 84 [CXST_W2] = __DEF_FBTC_SLOT(15, 0xea5a5a5a, SLOT_ISO), 85 [CXST_W2B] = __DEF_FBTC_SLOT(15, 0xea5a5a5a, SLOT_ISO), 86 [CXST_B1] = __DEF_FBTC_SLOT(250, 0xe5555555, SLOT_MIX), 87 [CXST_B2] = __DEF_FBTC_SLOT(7, 0xea5a5a5a, SLOT_MIX), 88 [CXST_B3] = __DEF_FBTC_SLOT(5, 0xe5555555, SLOT_MIX), 89 [CXST_B4] = __DEF_FBTC_SLOT(50, 0xe5555555, SLOT_MIX), 90 [CXST_LK] = __DEF_FBTC_SLOT(20, 0xea5a5a5a, SLOT_ISO), 91 [CXST_BLK] = __DEF_FBTC_SLOT(500, 0x55555555, SLOT_MIX), 92 [CXST_E2G] = __DEF_FBTC_SLOT(0, 0xea5a5a5a, SLOT_MIX), 93 [CXST_E5G] = __DEF_FBTC_SLOT(0, 0xffffffff, SLOT_ISO), 94 [CXST_EBT] = __DEF_FBTC_SLOT(5, 0xe5555555, SLOT_MIX), 95 [CXST_ENULL] = __DEF_FBTC_SLOT(0, 0xaaaaaaaa, SLOT_ISO), 96 [CXST_WLK] = __DEF_FBTC_SLOT(250, 0xea5a5a5a, SLOT_MIX), 97 [CXST_W1FDD] = __DEF_FBTC_SLOT(50, 0xffffffff, SLOT_ISO), 98 [CXST_B1FDD] = __DEF_FBTC_SLOT(50, 0xffffdfff, SLOT_ISO), 99 }; 100 101 static const u32 cxtbl[] = { 102 0xffffffff, /* 0 */ 103 0xaaaaaaaa, /* 1 */ 104 0xe5555555, /* 2 */ 105 0xee555555, /* 3 */ 106 0xd5555555, /* 4 */ 107 0x5a5a5a5a, /* 5 */ 108 0xfa5a5a5a, /* 6 */ 109 0xda5a5a5a, /* 7 */ 110 0xea5a5a5a, /* 8 */ 111 0x6a5a5aaa, /* 9 */ 112 0x6a5a6a5a, /* 10 */ 113 0x6a5a6aaa, /* 11 */ 114 0x6afa5afa, /* 12 */ 115 0xaaaa5aaa, /* 13 */ 116 0xaaffffaa, /* 14 */ 117 0xaa5555aa, /* 15 */ 118 0xfafafafa, /* 16 */ 119 0xffffddff, /* 17 */ 120 0xdaffdaff, /* 18 */ 121 0xfafadafa, /* 19 */ 122 0xea6a6a6a, /* 20 */ 123 0xea55556a, /* 21 */ 124 0xaafafafa, /* 22 */ 125 0xfafaaafa, /* 23 */ 126 0xfafffaff, /* 24 */ 127 0xea6a5a5a, /* 25 */ 128 0xfaff5aff, /* 26 */ 129 0xffffdfff, /* 27 */ 130 0xe6555555, /* 28 */ 131 }; 132 133 static const struct rtw89_btc_ver rtw89_btc_ver_defs[] = { 134 /* firmware version must be in decreasing order for each chip */ 135 {RTL8852BT, RTW89_FW_VER_CODE(0, 29, 90, 0), 136 .fcxbtcrpt = 7, .fcxtdma = 7, .fcxslots = 7, .fcxcysta = 7, 137 .fcxstep = 7, .fcxnullsta = 7, .fcxmreg = 7, .fcxgpiodbg = 7, 138 .fcxbtver = 7, .fcxbtscan = 7, .fcxbtafh = 7, .fcxbtdevinfo = 7, 139 .fwlrole = 7, .frptmap = 3, .fcxctrl = 7, .fcxinit = 7, 140 .fwevntrptl = 1, .fwc2hfunc = 2, .drvinfo_type = 1, .info_buf = 1800, 141 .max_role_num = 6, 142 }, 143 {RTL8922A, RTW89_FW_VER_CODE(0, 35, 8, 0), 144 .fcxbtcrpt = 8, .fcxtdma = 7, .fcxslots = 7, .fcxcysta = 7, 145 .fcxstep = 7, .fcxnullsta = 7, .fcxmreg = 7, .fcxgpiodbg = 7, 146 .fcxbtver = 7, .fcxbtscan = 7, .fcxbtafh = 7, .fcxbtdevinfo = 7, 147 .fwlrole = 8, .frptmap = 3, .fcxctrl = 7, .fcxinit = 7, 148 .fwevntrptl = 1, .fwc2hfunc = 1, .drvinfo_type = 1, .info_buf = 1800, 149 .max_role_num = 6, 150 }, 151 {RTL8851B, RTW89_FW_VER_CODE(0, 29, 29, 0), 152 .fcxbtcrpt = 105, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 5, 153 .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 2, .fcxgpiodbg = 1, 154 .fcxbtver = 1, .fcxbtscan = 2, .fcxbtafh = 2, .fcxbtdevinfo = 1, 155 .fwlrole = 2, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, 156 .fwevntrptl = 0, .fwc2hfunc = 1, .drvinfo_type = 0, .info_buf = 1800, 157 .max_role_num = 6, 158 }, 159 {RTL8852C, RTW89_FW_VER_CODE(0, 27, 57, 0), 160 .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, 161 .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, 162 .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 2, .fcxbtdevinfo = 1, 163 .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, 164 .fwevntrptl = 0, .fwc2hfunc = 1, .drvinfo_type = 0, .info_buf = 1280, 165 .max_role_num = 5, 166 }, 167 {RTL8852C, RTW89_FW_VER_CODE(0, 27, 42, 0), 168 .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, 169 .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, 170 .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 2, .fcxbtdevinfo = 1, 171 .fwlrole = 1, .frptmap = 2, .fcxctrl = 1, .fcxinit = 0, 172 .fwevntrptl = 0, .fwc2hfunc = 1, .drvinfo_type = 0, .info_buf = 1280, 173 .max_role_num = 5, 174 }, 175 {RTL8852C, RTW89_FW_VER_CODE(0, 27, 0, 0), 176 .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, 177 .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, 178 .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 1, .fcxbtdevinfo = 1, 179 .fwlrole = 1, .frptmap = 2, .fcxctrl = 1, .fcxinit = 0, 180 .fwevntrptl = 0, .fwc2hfunc = 1, .drvinfo_type = 0, .info_buf = 1280, 181 .max_role_num = 5, 182 }, 183 {RTL8852B, RTW89_FW_VER_CODE(0, 29, 29, 0), 184 .fcxbtcrpt = 105, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 5, 185 .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 2, .fcxgpiodbg = 1, 186 .fcxbtver = 1, .fcxbtscan = 2, .fcxbtafh = 2, .fcxbtdevinfo = 1, 187 .fwlrole = 2, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, 188 .fwevntrptl = 0, .fwc2hfunc = 1, .drvinfo_type = 0, .info_buf = 1800, 189 .max_role_num = 6, 190 }, 191 {RTL8852B, RTW89_FW_VER_CODE(0, 29, 14, 0), 192 .fcxbtcrpt = 5, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 4, 193 .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, 194 .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 2, .fcxbtdevinfo = 1, 195 .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, 196 .fwevntrptl = 0, .fwc2hfunc = 1, .drvinfo_type = 0, .info_buf = 1800, 197 .max_role_num = 6, 198 }, 199 {RTL8852B, RTW89_FW_VER_CODE(0, 27, 0, 0), 200 .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, 201 .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, 202 .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 1, .fcxbtdevinfo = 1, 203 .fwlrole = 1, .frptmap = 1, .fcxctrl = 1, .fcxinit = 0, 204 .fwevntrptl = 0, .fwc2hfunc = 1, .drvinfo_type = 0, .info_buf = 1280, 205 .max_role_num = 5, 206 }, 207 {RTL8852A, RTW89_FW_VER_CODE(0, 13, 37, 0), 208 .fcxbtcrpt = 4, .fcxtdma = 3, .fcxslots = 1, .fcxcysta = 3, 209 .fcxstep = 3, .fcxnullsta = 2, .fcxmreg = 1, .fcxgpiodbg = 1, 210 .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 2, .fcxbtdevinfo = 1, 211 .fwlrole = 1, .frptmap = 3, .fcxctrl = 1, .fcxinit = 0, 212 .fwevntrptl = 0, .fwc2hfunc = 0, .drvinfo_type = 0, .info_buf = 1280, 213 .max_role_num = 5, 214 }, 215 {RTL8852A, RTW89_FW_VER_CODE(0, 13, 0, 0), 216 .fcxbtcrpt = 1, .fcxtdma = 1, .fcxslots = 1, .fcxcysta = 2, 217 .fcxstep = 2, .fcxnullsta = 1, .fcxmreg = 1, .fcxgpiodbg = 1, 218 .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 1, .fcxbtdevinfo = 1, 219 .fwlrole = 0, .frptmap = 0, .fcxctrl = 0, .fcxinit = 0, 220 .fwevntrptl = 0, .fwc2hfunc = 0, .drvinfo_type = 0, .info_buf = 1024, 221 .max_role_num = 5, 222 }, 223 224 /* keep it to be the last as default entry */ 225 {0, RTW89_FW_VER_CODE(0, 0, 0, 0), 226 .fcxbtcrpt = 1, .fcxtdma = 1, .fcxslots = 1, .fcxcysta = 2, 227 .fcxstep = 2, .fcxnullsta = 1, .fcxmreg = 1, .fcxgpiodbg = 1, 228 .fcxbtver = 1, .fcxbtscan = 1, .fcxbtafh = 1, .fcxbtdevinfo = 1, 229 .fwlrole = 0, .frptmap = 0, .fcxctrl = 0, .fcxinit = 0, 230 .fwevntrptl = 0, .fwc2hfunc = 1, .drvinfo_type = 0, .info_buf = 1024, 231 .max_role_num = 5, 232 }, 233 }; 234 235 #define RTW89_DEFAULT_BTC_VER_IDX (ARRAY_SIZE(rtw89_btc_ver_defs) - 1) 236 237 static const union rtw89_btc_wl_state_map btc_scanning_map = { 238 .map = { 239 .scan = 1, 240 .connecting = 1, 241 .roaming = 1, 242 .dbccing = 1, 243 ._4way = 1, 244 }, 245 }; 246 247 static u32 chip_id_to_bt_rom_code_id(u32 id) 248 { 249 switch (id) { 250 case RTL8852A: 251 case RTL8852B: 252 case RTL8852C: 253 case RTL8852BT: 254 return 0x8852; 255 case RTL8851B: 256 return 0x8851; 257 case RTL8922A: 258 return 0x8922; 259 default: 260 return 0; 261 } 262 } 263 264 struct rtw89_btc_btf_tlv { 265 u8 type; 266 u8 len; 267 u8 val[]; 268 } __packed; 269 270 struct rtw89_btc_btf_tlv_v7 { 271 u8 type; 272 u8 ver; 273 u8 len; 274 u8 val[]; 275 } __packed; 276 277 enum btc_btf_set_report_en { 278 RPT_EN_TDMA, 279 RPT_EN_CYCLE, 280 RPT_EN_MREG, 281 RPT_EN_BT_VER_INFO, 282 RPT_EN_BT_SCAN_INFO, 283 RPT_EN_BT_DEVICE_INFO, 284 RPT_EN_BT_AFH_MAP, 285 RPT_EN_BT_AFH_MAP_LE, 286 RPT_EN_FW_STEP_INFO, 287 RPT_EN_TEST, 288 RPT_EN_WL_ALL, 289 RPT_EN_BT_ALL, 290 RPT_EN_ALL, 291 RPT_EN_MONITER, 292 }; 293 294 struct rtw89_btc_btf_set_report_v1 { 295 u8 fver; 296 __le32 enable; 297 __le32 para; 298 } __packed; 299 300 struct rtw89_btc_btf_set_report_v8 { 301 u8 type; 302 u8 fver; 303 u8 len; 304 __le32 map; 305 } __packed; 306 307 union rtw89_fbtc_rtp_ctrl { 308 struct rtw89_btc_btf_set_report_v1 v1; 309 struct rtw89_btc_btf_set_report_v8 v8; 310 }; 311 312 #define BTF_SET_SLOT_TABLE_VER 1 313 struct rtw89_btc_btf_set_slot_table { 314 u8 fver; 315 u8 tbl_num; 316 struct rtw89_btc_fbtc_slot tbls[] __counted_by(tbl_num); 317 } __packed; 318 319 struct rtw89_btc_btf_set_slot_table_v7 { 320 u8 type; 321 u8 ver; 322 u8 len; 323 struct rtw89_btc_fbtc_slot_v7 v7[CXST_MAX]; 324 } __packed; 325 326 struct rtw89_btc_btf_set_mon_reg_v1 { 327 u8 fver; 328 u8 reg_num; 329 struct rtw89_btc_fbtc_mreg regs[] __counted_by(reg_num); 330 } __packed; 331 332 struct rtw89_btc_btf_set_mon_reg_v7 { 333 u8 type; 334 u8 fver; 335 u8 len; 336 struct rtw89_btc_fbtc_mreg regs[] __counted_by(len); 337 } __packed; 338 339 union rtw89_fbtc_set_mon_reg { 340 struct rtw89_btc_btf_set_mon_reg_v1 v1; 341 struct rtw89_btc_btf_set_mon_reg_v7 v7; 342 } __packed; 343 344 struct _wl_rinfo_now { 345 u8 link_mode; 346 u32 dbcc_2g_phy: 2; 347 }; 348 349 enum btc_btf_set_cx_policy { 350 CXPOLICY_TDMA = 0x0, 351 CXPOLICY_SLOT = 0x1, 352 CXPOLICY_TYPE = 0x2, 353 CXPOLICY_MAX, 354 }; 355 356 enum btc_b2w_scoreboard { 357 BTC_BSCB_ACT = BIT(0), 358 BTC_BSCB_ON = BIT(1), 359 BTC_BSCB_WHQL = BIT(2), 360 BTC_BSCB_BT_S1 = BIT(3), 361 BTC_BSCB_A2DP_ACT = BIT(4), 362 BTC_BSCB_RFK_RUN = BIT(5), 363 BTC_BSCB_RFK_REQ = BIT(6), 364 BTC_BSCB_LPS = BIT(7), 365 BTC_BSCB_BT_LNAB0 = BIT(8), 366 BTC_BSCB_BT_LNAB1 = BIT(10), 367 BTC_BSCB_WLRFK = BIT(11), 368 BTC_BSCB_BT_HILNA = BIT(13), 369 BTC_BSCB_BT_CONNECT = BIT(16), 370 BTC_BSCB_PATCH_CODE = BIT(30), 371 BTC_BSCB_ALL = GENMASK(30, 0), 372 }; 373 374 enum btc_phymap { 375 BTC_PHY_0 = BIT(0), 376 BTC_PHY_1 = BIT(1), 377 BTC_PHY_ALL = BIT(0) | BIT(1), 378 }; 379 380 enum btc_cx_state_map { 381 BTC_WIDLE = 0, 382 BTC_WBUSY_BNOSCAN, 383 BTC_WBUSY_BSCAN, 384 BTC_WSCAN_BNOSCAN, 385 BTC_WSCAN_BSCAN, 386 BTC_WLINKING 387 }; 388 389 enum btc_ant_phase { 390 BTC_ANT_WPOWERON = 0, 391 BTC_ANT_WINIT, 392 BTC_ANT_WONLY, 393 BTC_ANT_WOFF, 394 BTC_ANT_W2G, 395 BTC_ANT_W5G, 396 BTC_ANT_W25G, 397 BTC_ANT_FREERUN, 398 BTC_ANT_WRFK, 399 BTC_ANT_WRFK2, 400 BTC_ANT_BRFK, 401 BTC_ANT_MAX 402 }; 403 404 enum btc_plt { 405 BTC_PLT_NONE = 0, 406 BTC_PLT_LTE_RX = BIT(0), 407 BTC_PLT_GNT_BT_TX = BIT(1), 408 BTC_PLT_GNT_BT_RX = BIT(2), 409 BTC_PLT_GNT_WL = BIT(3), 410 BTC_PLT_BT = BIT(1) | BIT(2), 411 BTC_PLT_ALL = 0xf 412 }; 413 414 enum btc_cx_poicy_main_type { 415 BTC_CXP_OFF = 0, 416 BTC_CXP_OFFB, 417 BTC_CXP_OFFE, 418 BTC_CXP_FIX, 419 BTC_CXP_PFIX, 420 BTC_CXP_AUTO, 421 BTC_CXP_PAUTO, 422 BTC_CXP_AUTO2, 423 BTC_CXP_PAUTO2, 424 BTC_CXP_MANUAL, 425 BTC_CXP_USERDEF0, 426 BTC_CXP_MAIN_MAX 427 }; 428 429 enum btc_cx_poicy_type { 430 /* TDMA off + pri: BT > WL */ 431 BTC_CXP_OFF_BT = (BTC_CXP_OFF << 8) | 0, 432 433 /* TDMA off + pri: WL > BT */ 434 BTC_CXP_OFF_WL = (BTC_CXP_OFF << 8) | 1, 435 436 /* TDMA off + pri: BT = WL */ 437 BTC_CXP_OFF_EQ0 = (BTC_CXP_OFF << 8) | 2, 438 439 /* TDMA off + pri: BT = WL > BT_Lo */ 440 BTC_CXP_OFF_EQ1 = (BTC_CXP_OFF << 8) | 3, 441 442 /* TDMA off + pri: WL = BT, BT_Rx > WL_Lo_Tx */ 443 BTC_CXP_OFF_EQ2 = (BTC_CXP_OFF << 8) | 4, 444 445 /* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */ 446 BTC_CXP_OFF_EQ3 = (BTC_CXP_OFF << 8) | 5, 447 448 /* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */ 449 BTC_CXP_OFF_EQ4 = (BTC_CXP_OFF << 8) | 6, 450 451 /* TDMA off + pri: WL_Rx = BT, BT_HI > WL_Tx > BT_Lo */ 452 BTC_CXP_OFF_EQ5 = (BTC_CXP_OFF << 8) | 7, 453 454 /* TDMA off + pri: BT_Hi > WL > BT_Lo */ 455 BTC_CXP_OFF_BWB0 = (BTC_CXP_OFF << 8) | 8, 456 457 /* TDMA off + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo */ 458 BTC_CXP_OFF_BWB1 = (BTC_CXP_OFF << 8) | 9, 459 460 /* TDMA off + pri: WL_Hi-Tx > BT, BT_Hi > other-WL > BT_Lo */ 461 BTC_CXP_OFF_BWB2 = (BTC_CXP_OFF << 8) | 10, 462 463 /* TDMA off + pri: WL_Hi-Tx = BT */ 464 BTC_CXP_OFF_BWB3 = (BTC_CXP_OFF << 8) | 11, 465 466 /* TDMA off + pri: WL > BT, Block-BT*/ 467 BTC_CXP_OFF_WL2 = (BTC_CXP_OFF << 8) | 12, 468 469 /* TDMA off+Bcn-Protect + pri: WL_Hi-Tx > BT_Hi_Rx, BT_Hi > WL > BT_Lo*/ 470 BTC_CXP_OFFB_BWB0 = (BTC_CXP_OFFB << 8) | 0, 471 472 /* TDMA off + Ext-Ctrl + pri: default */ 473 BTC_CXP_OFFE_DEF = (BTC_CXP_OFFE << 8) | 0, 474 475 /* TDMA off + Ext-Ctrl + pri: E2G-slot block all BT */ 476 BTC_CXP_OFFE_DEF2 = (BTC_CXP_OFFE << 8) | 1, 477 478 /* TDMA off + Ext-Ctrl + pri: default */ 479 BTC_CXP_OFFE_2GBWISOB = (BTC_CXP_OFFE << 8) | 2, 480 481 /* TDMA off + Ext-Ctrl + pri: E2G-slot block all BT */ 482 BTC_CXP_OFFE_2GISOB = (BTC_CXP_OFFE << 8) | 3, 483 484 /* TDMA off + Ext-Ctrl + pri: E2G-slot WL > BT */ 485 BTC_CXP_OFFE_2GBWMIXB = (BTC_CXP_OFFE << 8) | 4, 486 487 /* TDMA off + Ext-Ctrl + pri: E2G/EBT-slot WL > BT */ 488 BTC_CXP_OFFE_WL = (BTC_CXP_OFFE << 8) | 5, 489 490 /* TDMA off + Ext-Ctrl + pri: default */ 491 BTC_CXP_OFFE_2GBWMIXB2 = (BTC_CXP_OFFE << 8) | 6, 492 493 /* TDMA Fix slot-0: W1:B1 = 30:30 */ 494 BTC_CXP_FIX_TD3030 = (BTC_CXP_FIX << 8) | 0, 495 496 /* TDMA Fix slot-1: W1:B1 = 50:50 */ 497 BTC_CXP_FIX_TD5050 = (BTC_CXP_FIX << 8) | 1, 498 499 /* TDMA Fix slot-2: W1:B1 = 20:30 */ 500 BTC_CXP_FIX_TD2030 = (BTC_CXP_FIX << 8) | 2, 501 502 /* TDMA Fix slot-3: W1:B1 = 40:10 */ 503 BTC_CXP_FIX_TD4010 = (BTC_CXP_FIX << 8) | 3, 504 505 /* TDMA Fix slot-4: W1:B1 = 70:10 */ 506 BTC_CXP_FIX_TD7010 = (BTC_CXP_FIX << 8) | 4, 507 508 /* TDMA Fix slot-5: W1:B1 = 20:60 */ 509 BTC_CXP_FIX_TD2060 = (BTC_CXP_FIX << 8) | 5, 510 511 /* TDMA Fix slot-6: W1:B1 = 30:60 */ 512 BTC_CXP_FIX_TD3060 = (BTC_CXP_FIX << 8) | 6, 513 514 /* TDMA Fix slot-7: W1:B1 = 20:80 */ 515 BTC_CXP_FIX_TD2080 = (BTC_CXP_FIX << 8) | 7, 516 517 /* TDMA Fix slot-8: W1:B1 = user-define */ 518 BTC_CXP_FIX_TDW1B1 = (BTC_CXP_FIX << 8) | 8, 519 520 /* TDMA Fix slot-9: W1:B1 = 40:10 */ 521 BTC_CXP_FIX_TD4010ISO = (BTC_CXP_FIX << 8) | 9, 522 523 /* TDMA Fix slot-10: W1:B1 = 40:10 */ 524 BTC_CXP_FIX_TD4010ISO_DL = (BTC_CXP_FIX << 8) | 10, 525 526 /* TDMA Fix slot-11: W1:B1 = 40:10 */ 527 BTC_CXP_FIX_TD4010ISO_UL = (BTC_CXP_FIX << 8) | 11, 528 529 /* PS-TDMA Fix slot-0: W1:B1 = 30:30 */ 530 BTC_CXP_PFIX_TD3030 = (BTC_CXP_PFIX << 8) | 0, 531 532 /* PS-TDMA Fix slot-1: W1:B1 = 50:50 */ 533 BTC_CXP_PFIX_TD5050 = (BTC_CXP_PFIX << 8) | 1, 534 535 /* PS-TDMA Fix slot-2: W1:B1 = 20:30 */ 536 BTC_CXP_PFIX_TD2030 = (BTC_CXP_PFIX << 8) | 2, 537 538 /* PS-TDMA Fix slot-3: W1:B1 = 20:60 */ 539 BTC_CXP_PFIX_TD2060 = (BTC_CXP_PFIX << 8) | 3, 540 541 /* PS-TDMA Fix slot-4: W1:B1 = 30:70 */ 542 BTC_CXP_PFIX_TD3070 = (BTC_CXP_PFIX << 8) | 4, 543 544 /* PS-TDMA Fix slot-5: W1:B1 = 20:80 */ 545 BTC_CXP_PFIX_TD2080 = (BTC_CXP_PFIX << 8) | 5, 546 547 /* PS-TDMA Fix slot-6: W1:B1 = user-define */ 548 BTC_CXP_PFIX_TDW1B1 = (BTC_CXP_PFIX << 8) | 6, 549 550 /* TDMA Auto slot-0: W1:B1 = 50:200 */ 551 BTC_CXP_AUTO_TD50B1 = (BTC_CXP_AUTO << 8) | 0, 552 553 /* TDMA Auto slot-1: W1:B1 = 60:200 */ 554 BTC_CXP_AUTO_TD60B1 = (BTC_CXP_AUTO << 8) | 1, 555 556 /* TDMA Auto slot-2: W1:B1 = 20:200 */ 557 BTC_CXP_AUTO_TD20B1 = (BTC_CXP_AUTO << 8) | 2, 558 559 /* TDMA Auto slot-3: W1:B1 = user-define */ 560 BTC_CXP_AUTO_TDW1B1 = (BTC_CXP_AUTO << 8) | 3, 561 562 /* PS-TDMA Auto slot-0: W1:B1 = 50:200 */ 563 BTC_CXP_PAUTO_TD50B1 = (BTC_CXP_PAUTO << 8) | 0, 564 565 /* PS-TDMA Auto slot-1: W1:B1 = 60:200 */ 566 BTC_CXP_PAUTO_TD60B1 = (BTC_CXP_PAUTO << 8) | 1, 567 568 /* PS-TDMA Auto slot-2: W1:B1 = 20:200 */ 569 BTC_CXP_PAUTO_TD20B1 = (BTC_CXP_PAUTO << 8) | 2, 570 571 /* PS-TDMA Auto slot-3: W1:B1 = user-define */ 572 BTC_CXP_PAUTO_TDW1B1 = (BTC_CXP_PAUTO << 8) | 3, 573 574 /* TDMA Auto slot2-0: W1:B4 = 30:50 */ 575 BTC_CXP_AUTO2_TD3050 = (BTC_CXP_AUTO2 << 8) | 0, 576 577 /* TDMA Auto slot2-1: W1:B4 = 30:70 */ 578 BTC_CXP_AUTO2_TD3070 = (BTC_CXP_AUTO2 << 8) | 1, 579 580 /* TDMA Auto slot2-2: W1:B4 = 50:50 */ 581 BTC_CXP_AUTO2_TD5050 = (BTC_CXP_AUTO2 << 8) | 2, 582 583 /* TDMA Auto slot2-3: W1:B4 = 60:60 */ 584 BTC_CXP_AUTO2_TD6060 = (BTC_CXP_AUTO2 << 8) | 3, 585 586 /* TDMA Auto slot2-4: W1:B4 = 20:80 */ 587 BTC_CXP_AUTO2_TD2080 = (BTC_CXP_AUTO2 << 8) | 4, 588 589 /* TDMA Auto slot2-5: W1:B4 = user-define */ 590 BTC_CXP_AUTO2_TDW1B4 = (BTC_CXP_AUTO2 << 8) | 5, 591 592 /* PS-TDMA Auto slot2-0: W1:B4 = 30:50 */ 593 BTC_CXP_PAUTO2_TD3050 = (BTC_CXP_PAUTO2 << 8) | 0, 594 595 /* PS-TDMA Auto slot2-1: W1:B4 = 30:70 */ 596 BTC_CXP_PAUTO2_TD3070 = (BTC_CXP_PAUTO2 << 8) | 1, 597 598 /* PS-TDMA Auto slot2-2: W1:B4 = 50:50 */ 599 BTC_CXP_PAUTO2_TD5050 = (BTC_CXP_PAUTO2 << 8) | 2, 600 601 /* PS-TDMA Auto slot2-3: W1:B4 = 60:60 */ 602 BTC_CXP_PAUTO2_TD6060 = (BTC_CXP_PAUTO2 << 8) | 3, 603 604 /* PS-TDMA Auto slot2-4: W1:B4 = 20:80 */ 605 BTC_CXP_PAUTO2_TD2080 = (BTC_CXP_PAUTO2 << 8) | 4, 606 607 /* PS-TDMA Auto slot2-5: W1:B4 = user-define */ 608 BTC_CXP_PAUTO2_TDW1B4 = (BTC_CXP_PAUTO2 << 8) | 5, 609 610 BTC_CXP_MAX = 0xffff 611 }; 612 613 enum btc_wl_rfk_result { 614 BTC_WRFK_REJECT = 0, 615 BTC_WRFK_ALLOW = 1, 616 }; 617 618 enum btc_coex_info_map_en { 619 BTC_COEX_INFO_CX = BIT(0), 620 BTC_COEX_INFO_WL = BIT(1), 621 BTC_COEX_INFO_BT = BIT(2), 622 BTC_COEX_INFO_DM = BIT(3), 623 BTC_COEX_INFO_MREG = BIT(4), 624 BTC_COEX_INFO_SUMMARY = BIT(5), 625 BTC_COEX_INFO_ALL = GENMASK(7, 0), 626 }; 627 628 #define BTC_CXP_MASK GENMASK(15, 8) 629 630 enum btc_w2b_scoreboard { 631 BTC_WSCB_ACTIVE = BIT(0), 632 BTC_WSCB_ON = BIT(1), 633 BTC_WSCB_SCAN = BIT(2), 634 BTC_WSCB_UNDERTEST = BIT(3), 635 BTC_WSCB_RXGAIN = BIT(4), 636 BTC_WSCB_WLBUSY = BIT(7), 637 BTC_WSCB_EXTFEM = BIT(8), 638 BTC_WSCB_TDMA = BIT(9), 639 BTC_WSCB_FIX2M = BIT(10), 640 BTC_WSCB_WLRFK = BIT(11), 641 BTC_WSCB_RXSCAN_PRI = BIT(12), 642 BTC_WSCB_BT_HILNA = BIT(13), 643 BTC_WSCB_BTLOG = BIT(14), 644 BTC_WSCB_ALL = GENMASK(23, 0), 645 }; 646 647 enum btc_wl_link_mode { 648 BTC_WLINK_NOLINK = 0x0, 649 BTC_WLINK_2G_STA, 650 BTC_WLINK_2G_AP, 651 BTC_WLINK_2G_GO, 652 BTC_WLINK_2G_GC, 653 BTC_WLINK_2G_SCC, 654 BTC_WLINK_2G_MCC, 655 BTC_WLINK_25G_MCC, 656 BTC_WLINK_25G_DBCC, 657 BTC_WLINK_5G, 658 BTC_WLINK_2G_NAN, 659 BTC_WLINK_OTHER, 660 BTC_WLINK_MAX 661 }; 662 663 enum btc_wl_mrole_type { 664 BTC_WLMROLE_NONE = 0x0, 665 BTC_WLMROLE_STA_GC, 666 BTC_WLMROLE_STA_GC_NOA, 667 BTC_WLMROLE_STA_GO, 668 BTC_WLMROLE_STA_GO_NOA, 669 BTC_WLMROLE_STA_STA, 670 BTC_WLMROLE_MAX 671 }; 672 673 enum btc_bt_hid_type { 674 BTC_HID_218 = BIT(0), 675 BTC_HID_418 = BIT(1), 676 BTC_HID_BLE = BIT(2), 677 BTC_HID_RCU = BIT(3), 678 BTC_HID_RCU_VOICE = BIT(4), 679 BTC_HID_OTHER_LEGACY = BIT(5) 680 }; 681 682 enum btc_reset_module { 683 BTC_RESET_CX = BIT(0), 684 BTC_RESET_DM = BIT(1), 685 BTC_RESET_CTRL = BIT(2), 686 BTC_RESET_CXDM = BIT(0) | BIT(1), 687 BTC_RESET_BTINFO = BIT(3), 688 BTC_RESET_MDINFO = BIT(4), 689 BTC_RESET_ALL = GENMASK(7, 0), 690 }; 691 692 enum btc_gnt_state { 693 BTC_GNT_HW = 0, 694 BTC_GNT_SW_LO, 695 BTC_GNT_SW_HI, 696 BTC_GNT_MAX 697 }; 698 699 enum btc_ctr_path { 700 BTC_CTRL_BY_BT = 0, 701 BTC_CTRL_BY_WL 702 }; 703 704 enum btc_wlact_state { 705 BTC_WLACT_HW = 0, 706 BTC_WLACT_SW_LO, 707 BTC_WLACT_SW_HI, 708 BTC_WLACT_MAX, 709 }; 710 711 enum btc_wl_max_tx_time { 712 BTC_MAX_TX_TIME_L1 = 500, 713 BTC_MAX_TX_TIME_L2 = 1000, 714 BTC_MAX_TX_TIME_L3 = 2000, 715 BTC_MAX_TX_TIME_DEF = 5280 716 }; 717 718 enum btc_wl_max_tx_retry { 719 BTC_MAX_TX_RETRY_L1 = 7, 720 BTC_MAX_TX_RETRY_L2 = 15, 721 BTC_MAX_TX_RETRY_DEF = 31, 722 }; 723 724 enum btc_reason_and_action { 725 BTC_RSN_NONE, 726 BTC_RSN_NTFY_INIT, 727 BTC_RSN_NTFY_SWBAND, 728 BTC_RSN_NTFY_WL_STA, 729 BTC_RSN_NTFY_RADIO_STATE, 730 BTC_RSN_UPDATE_BT_SCBD, 731 BTC_RSN_NTFY_WL_RFK, 732 BTC_RSN_UPDATE_BT_INFO, 733 BTC_RSN_NTFY_SCAN_START, 734 BTC_RSN_NTFY_SCAN_FINISH, 735 BTC_RSN_NTFY_SPECIFIC_PACKET, 736 BTC_RSN_NTFY_POWEROFF, 737 BTC_RSN_NTFY_ROLE_INFO, 738 BTC_RSN_CMD_SET_COEX, 739 BTC_RSN_ACT1_WORK, 740 BTC_RSN_BT_DEVINFO_WORK, 741 BTC_RSN_RFK_CHK_WORK, 742 BTC_RSN_NUM, 743 BTC_ACT_NONE = 100, 744 BTC_ACT_WL_ONLY, 745 BTC_ACT_WL_5G, 746 BTC_ACT_WL_OTHER, 747 BTC_ACT_WL_IDLE, 748 BTC_ACT_WL_NC, 749 BTC_ACT_WL_RFK, 750 BTC_ACT_WL_INIT, 751 BTC_ACT_WL_OFF, 752 BTC_ACT_FREERUN, 753 BTC_ACT_BT_WHQL, 754 BTC_ACT_BT_RFK, 755 BTC_ACT_BT_OFF, 756 BTC_ACT_BT_IDLE, 757 BTC_ACT_BT_HFP, 758 BTC_ACT_BT_HID, 759 BTC_ACT_BT_A2DP, 760 BTC_ACT_BT_A2DPSINK, 761 BTC_ACT_BT_PAN, 762 BTC_ACT_BT_A2DP_HID, 763 BTC_ACT_BT_A2DP_PAN, 764 BTC_ACT_BT_PAN_HID, 765 BTC_ACT_BT_A2DP_PAN_HID, 766 BTC_ACT_WL_25G_MCC, 767 BTC_ACT_WL_2G_MCC, 768 BTC_ACT_WL_2G_SCC, 769 BTC_ACT_WL_2G_AP, 770 BTC_ACT_WL_2G_GO, 771 BTC_ACT_WL_2G_GC, 772 BTC_ACT_WL_2G_NAN, 773 BTC_ACT_LAST, 774 BTC_ACT_NUM = BTC_ACT_LAST - BTC_ACT_NONE, 775 BTC_ACT_EXT_BIT = BIT(14), 776 BTC_POLICY_EXT_BIT = BIT(15), 777 }; 778 779 #define BTC_FREERUN_ANTISO_MIN 30 780 #define BTC_TDMA_BTHID_MAX 2 781 #define BTC_BLINK_NOCONNECT 0 782 #define BTC_B1_MAX 250 /* unit ms */ 783 784 static void _run_coex(struct rtw89_dev *rtwdev, 785 enum btc_reason_and_action reason); 786 static void _write_scbd(struct rtw89_dev *rtwdev, u32 val, bool state); 787 static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update); 788 789 static int _send_fw_cmd(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, 790 void *param, u16 len) 791 { 792 struct rtw89_btc *btc = &rtwdev->btc; 793 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 794 struct rtw89_btc_cx *cx = &btc->cx; 795 struct rtw89_btc_wl_info *wl = &cx->wl; 796 struct rtw89_btc_dm *dm = &btc->dm; 797 int ret; 798 799 if (len > BTC_H2C_MAXLEN || len == 0) { 800 btc->fwinfo.cnt_h2c_fail++; 801 dm->error.map.h2c_buffer_over = true; 802 return -EINVAL; 803 } else if (!wl->status.map.init_ok) { 804 rtw89_debug(rtwdev, RTW89_DBG_BTC, 805 "[BTC], %s(): return by btc not init!!\n", __func__); 806 pfwinfo->cnt_h2c_fail++; 807 return -EINVAL; 808 } else if ((wl->status.map.rf_off_pre == BTC_LPS_RF_OFF && 809 wl->status.map.rf_off == BTC_LPS_RF_OFF) || 810 (wl->status.map.lps_pre == BTC_LPS_RF_OFF && 811 wl->status.map.lps == BTC_LPS_RF_OFF)) { 812 rtw89_debug(rtwdev, RTW89_DBG_BTC, 813 "[BTC], %s(): return by wl off!!\n", __func__); 814 pfwinfo->cnt_h2c_fail++; 815 return -EINVAL; 816 } 817 818 ret = rtw89_fw_h2c_raw_with_hdr(rtwdev, h2c_class, h2c_func, param, len, 819 false, true); 820 if (ret) 821 pfwinfo->cnt_h2c_fail++; 822 else 823 pfwinfo->cnt_h2c++; 824 825 return ret; 826 } 827 828 static void _reset_btc_var(struct rtw89_dev *rtwdev, u8 type) 829 { 830 struct rtw89_btc *btc = &rtwdev->btc; 831 const struct rtw89_btc_ver *ver = btc->ver; 832 struct rtw89_btc_cx *cx = &btc->cx; 833 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 834 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 835 struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; 836 struct rtw89_btc_wl_link_info *wl_linfo; 837 u8 i; 838 839 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s\n", __func__); 840 841 if (type & BTC_RESET_CX) 842 memset(cx, 0, sizeof(*cx)); 843 844 if (type & BTC_RESET_BTINFO) /* only for BT enable */ 845 memset(bt, 0, sizeof(*bt)); 846 847 if (type & BTC_RESET_CTRL) { 848 memset(&btc->ctrl, 0, sizeof(btc->ctrl)); 849 btc->manual_ctrl = false; 850 if (ver->fcxctrl != 7) 851 btc->ctrl.ctrl.trace_step = FCXDEF_STEP; 852 } 853 854 /* Init Coex variables that are not zero */ 855 if (type & BTC_RESET_DM) { 856 memset(&btc->dm, 0, sizeof(btc->dm)); 857 memset(bt_linfo->rssi_state, 0, sizeof(bt_linfo->rssi_state)); 858 for (i = 0; i < RTW89_PORT_NUM; i++) { 859 if (btc->ver->fwlrole == 8) 860 wl_linfo = &wl->rlink_info[i][0]; 861 else 862 wl_linfo = &wl->link_info[i]; 863 memset(wl_linfo->rssi_state, 0, sizeof(wl_linfo->rssi_state)); 864 } 865 866 /* set the slot_now table to original */ 867 btc->dm.tdma_now = t_def[CXTD_OFF]; 868 btc->dm.tdma = t_def[CXTD_OFF]; 869 if (ver->fcxslots >= 7) { 870 for (i = 0; i < ARRAY_SIZE(s_def); i++) { 871 btc->dm.slot.v7[i].dur = s_def[i].dur; 872 btc->dm.slot.v7[i].cxtype = s_def[i].cxtype; 873 btc->dm.slot.v7[i].cxtbl = s_def[i].cxtbl; 874 } 875 memcpy(&btc->dm.slot_now.v7, &btc->dm.slot.v7, 876 sizeof(btc->dm.slot_now.v7)); 877 } else { 878 memcpy(&btc->dm.slot_now.v1, s_def, 879 sizeof(btc->dm.slot_now.v1)); 880 memcpy(&btc->dm.slot.v1, s_def, 881 sizeof(btc->dm.slot.v1)); 882 } 883 884 btc->policy_len = 0; 885 btc->bt_req_len = 0; 886 887 btc->dm.coex_info_map = BTC_COEX_INFO_ALL; 888 btc->dm.wl_tx_limit.tx_time = BTC_MAX_TX_TIME_DEF; 889 btc->dm.wl_tx_limit.tx_retry = BTC_MAX_TX_RETRY_DEF; 890 btc->dm.wl_pre_agc_rb = BTC_PREAGC_NOTFOUND; 891 btc->dm.wl_btg_rx_rb = BTC_BTGCTRL_BB_GNT_NOTFOUND; 892 } 893 894 if (type & BTC_RESET_MDINFO) 895 memset(&btc->mdinfo, 0, sizeof(btc->mdinfo)); 896 } 897 898 static u8 _search_reg_index(struct rtw89_dev *rtwdev, u8 mreg_num, u16 reg_type, u32 target) 899 { 900 const struct rtw89_chip_info *chip = rtwdev->chip; 901 u8 i; 902 903 for (i = 0; i < mreg_num; i++) 904 if (le16_to_cpu(chip->mon_reg[i].type) == reg_type && 905 le32_to_cpu(chip->mon_reg[i].offset) == target) { 906 return i; 907 } 908 return BTC_REG_NOTFOUND; 909 } 910 911 static void _get_reg_status(struct rtw89_dev *rtwdev, u8 type, u8 *val) 912 { 913 struct rtw89_btc *btc = &rtwdev->btc; 914 const struct rtw89_btc_ver *ver = btc->ver; 915 union rtw89_btc_module_info *md = &btc->mdinfo; 916 union rtw89_btc_fbtc_mreg_val *pmreg; 917 u32 pre_agc_addr = R_BTC_BB_PRE_AGC_S1; 918 u32 reg_val; 919 u8 idx, switch_type; 920 921 if (ver->fcxinit == 7) 922 switch_type = md->md_v7.switch_type; 923 else 924 switch_type = md->md.switch_type; 925 926 if (btc->btg_pos == RF_PATH_A) 927 pre_agc_addr = R_BTC_BB_PRE_AGC_S0; 928 929 switch (type) { 930 case BTC_CSTATUS_TXDIV_POS: 931 if (switch_type == BTC_SWITCH_INTERNAL) 932 *val = BTC_ANT_DIV_MAIN; 933 break; 934 case BTC_CSTATUS_RXDIV_POS: 935 if (switch_type == BTC_SWITCH_INTERNAL) 936 *val = BTC_ANT_DIV_MAIN; 937 break; 938 case BTC_CSTATUS_BB_GNT_MUX: 939 reg_val = rtw89_phy_read32(rtwdev, R_BTC_BB_BTG_RX); 940 *val = !(reg_val & B_BTC_BB_GNT_MUX); 941 break; 942 case BTC_CSTATUS_BB_GNT_MUX_MON: 943 if (!btc->fwinfo.rpt_fbtc_mregval.cinfo.valid) 944 return; 945 946 pmreg = &btc->fwinfo.rpt_fbtc_mregval.finfo; 947 if (ver->fcxmreg == 1) { 948 idx = _search_reg_index(rtwdev, pmreg->v1.reg_num, 949 REG_BB, R_BTC_BB_BTG_RX); 950 if (idx == BTC_REG_NOTFOUND) { 951 *val = BTC_BTGCTRL_BB_GNT_NOTFOUND; 952 } else { 953 reg_val = le32_to_cpu(pmreg->v1.mreg_val[idx]); 954 *val = !(reg_val & B_BTC_BB_GNT_MUX); 955 } 956 } else if (ver->fcxmreg == 2) { 957 idx = _search_reg_index(rtwdev, pmreg->v2.reg_num, 958 REG_BB, R_BTC_BB_BTG_RX); 959 if (idx == BTC_REG_NOTFOUND) { 960 *val = BTC_BTGCTRL_BB_GNT_NOTFOUND; 961 } else { 962 reg_val = le32_to_cpu(pmreg->v2.mreg_val[idx]); 963 *val = !(reg_val & B_BTC_BB_GNT_MUX); 964 } 965 } 966 break; 967 case BTC_CSTATUS_BB_PRE_AGC: 968 reg_val = rtw89_phy_read32(rtwdev, pre_agc_addr); 969 reg_val &= B_BTC_BB_PRE_AGC_MASK; 970 *val = (reg_val == B_BTC_BB_PRE_AGC_VAL); 971 break; 972 case BTC_CSTATUS_BB_PRE_AGC_MON: 973 if (!btc->fwinfo.rpt_fbtc_mregval.cinfo.valid) 974 return; 975 976 pmreg = &btc->fwinfo.rpt_fbtc_mregval.finfo; 977 if (ver->fcxmreg == 1) { 978 idx = _search_reg_index(rtwdev, pmreg->v1.reg_num, 979 REG_BB, pre_agc_addr); 980 if (idx == BTC_REG_NOTFOUND) { 981 *val = BTC_PREAGC_NOTFOUND; 982 } else { 983 reg_val = le32_to_cpu(pmreg->v1.mreg_val[idx]) & 984 B_BTC_BB_PRE_AGC_MASK; 985 *val = (reg_val == B_BTC_BB_PRE_AGC_VAL); 986 } 987 } else if (ver->fcxmreg == 2) { 988 idx = _search_reg_index(rtwdev, pmreg->v2.reg_num, 989 REG_BB, pre_agc_addr); 990 if (idx == BTC_REG_NOTFOUND) { 991 *val = BTC_PREAGC_NOTFOUND; 992 } else { 993 reg_val = le32_to_cpu(pmreg->v2.mreg_val[idx]) & 994 B_BTC_BB_PRE_AGC_MASK; 995 *val = (reg_val == B_BTC_BB_PRE_AGC_VAL); 996 } 997 } 998 break; 999 default: 1000 break; 1001 } 1002 } 1003 1004 #define BTC_RPT_HDR_SIZE 3 1005 #define BTC_CHK_WLSLOT_DRIFT_MAX 15 1006 #define BTC_CHK_BTSLOT_DRIFT_MAX 15 1007 #define BTC_CHK_HANG_MAX 3 1008 1009 static void _chk_btc_err(struct rtw89_dev *rtwdev, u8 type, u32 cnt) 1010 { 1011 struct rtw89_btc *btc = &rtwdev->btc; 1012 struct rtw89_btc_cx *cx = &btc->cx; 1013 struct rtw89_btc_bt_info *bt = &cx->bt; 1014 struct rtw89_btc_wl_info *wl = &cx->wl; 1015 struct rtw89_btc_dm *dm = &btc->dm; 1016 1017 rtw89_debug(rtwdev, RTW89_DBG_BTC, 1018 "[BTC], %s(): type:%d cnt:%d\n", 1019 __func__, type, cnt); 1020 1021 switch (type) { 1022 case BTC_DCNT_WL_FW_VER_MATCH: 1023 if ((wl->ver_info.fw_coex & 0xffff0000) != 1024 rtwdev->chip->wlcx_desired) { 1025 wl->fw_ver_mismatch = true; 1026 dm->error.map.wl_ver_mismatch = true; 1027 } else { 1028 wl->fw_ver_mismatch = false; 1029 dm->error.map.wl_ver_mismatch = false; 1030 } 1031 break; 1032 case BTC_DCNT_RPT_HANG: 1033 if (dm->cnt_dm[BTC_DCNT_RPT] == cnt && btc->fwinfo.rpt_en_map) 1034 dm->cnt_dm[BTC_DCNT_RPT_HANG]++; 1035 else 1036 dm->cnt_dm[BTC_DCNT_RPT_HANG] = 0; 1037 1038 if (dm->cnt_dm[BTC_DCNT_RPT_HANG] >= BTC_CHK_HANG_MAX) 1039 dm->error.map.wl_fw_hang = true; 1040 else 1041 dm->error.map.wl_fw_hang = false; 1042 1043 dm->cnt_dm[BTC_DCNT_RPT] = cnt; 1044 break; 1045 case BTC_DCNT_CYCLE_HANG: 1046 if (dm->cnt_dm[BTC_DCNT_CYCLE] == cnt && 1047 (dm->tdma_now.type != CXTDMA_OFF || 1048 dm->tdma_now.ext_ctrl == CXECTL_EXT)) 1049 dm->cnt_dm[BTC_DCNT_CYCLE_HANG]++; 1050 else 1051 dm->cnt_dm[BTC_DCNT_CYCLE_HANG] = 0; 1052 1053 if (dm->cnt_dm[BTC_DCNT_CYCLE_HANG] >= BTC_CHK_HANG_MAX) 1054 dm->error.map.cycle_hang = true; 1055 else 1056 dm->error.map.cycle_hang = false; 1057 1058 dm->cnt_dm[BTC_DCNT_CYCLE] = cnt; 1059 break; 1060 case BTC_DCNT_W1_HANG: 1061 if (dm->cnt_dm[BTC_DCNT_W1] == cnt && 1062 dm->tdma_now.type != CXTDMA_OFF) 1063 dm->cnt_dm[BTC_DCNT_W1_HANG]++; 1064 else 1065 dm->cnt_dm[BTC_DCNT_W1_HANG] = 0; 1066 1067 if (dm->cnt_dm[BTC_DCNT_W1_HANG] >= BTC_CHK_HANG_MAX) 1068 dm->error.map.w1_hang = true; 1069 else 1070 dm->error.map.w1_hang = false; 1071 1072 dm->cnt_dm[BTC_DCNT_W1] = cnt; 1073 break; 1074 case BTC_DCNT_B1_HANG: 1075 if (dm->cnt_dm[BTC_DCNT_B1] == cnt && 1076 dm->tdma_now.type != CXTDMA_OFF) 1077 dm->cnt_dm[BTC_DCNT_B1_HANG]++; 1078 else 1079 dm->cnt_dm[BTC_DCNT_B1_HANG] = 0; 1080 1081 if (dm->cnt_dm[BTC_DCNT_B1_HANG] >= BTC_CHK_HANG_MAX) 1082 dm->error.map.b1_hang = true; 1083 else 1084 dm->error.map.b1_hang = false; 1085 1086 dm->cnt_dm[BTC_DCNT_B1] = cnt; 1087 break; 1088 case BTC_DCNT_E2G_HANG: 1089 if (dm->cnt_dm[BTC_DCNT_E2G] == cnt && 1090 dm->tdma_now.ext_ctrl == CXECTL_EXT) 1091 dm->cnt_dm[BTC_DCNT_E2G_HANG]++; 1092 else 1093 dm->cnt_dm[BTC_DCNT_E2G_HANG] = 0; 1094 1095 if (dm->cnt_dm[BTC_DCNT_E2G_HANG] >= BTC_CHK_HANG_MAX) 1096 dm->error.map.wl_e2g_hang = true; 1097 else 1098 dm->error.map.wl_e2g_hang = false; 1099 1100 dm->cnt_dm[BTC_DCNT_E2G] = cnt; 1101 break; 1102 case BTC_DCNT_TDMA_NONSYNC: 1103 if (cnt != 0) /* if tdma not sync between drv/fw */ 1104 dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC]++; 1105 else 1106 dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] = 0; 1107 1108 if (dm->cnt_dm[BTC_DCNT_TDMA_NONSYNC] >= BTC_CHK_HANG_MAX) 1109 dm->error.map.tdma_no_sync = true; 1110 else 1111 dm->error.map.tdma_no_sync = false; 1112 break; 1113 case BTC_DCNT_SLOT_NONSYNC: 1114 if (cnt != 0) /* if slot not sync between drv/fw */ 1115 dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC]++; 1116 else 1117 dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] = 0; 1118 1119 if (dm->cnt_dm[BTC_DCNT_SLOT_NONSYNC] >= BTC_CHK_HANG_MAX) 1120 dm->error.map.slot_no_sync = true; 1121 else 1122 dm->error.map.slot_no_sync = false; 1123 break; 1124 case BTC_DCNT_BTTX_HANG: 1125 cnt = cx->cnt_bt[BTC_BCNT_LOPRI_TX]; 1126 1127 if (cnt == 0 && bt->link_info.slave_role) 1128 dm->cnt_dm[BTC_DCNT_BTTX_HANG]++; 1129 else 1130 dm->cnt_dm[BTC_DCNT_BTTX_HANG] = 0; 1131 1132 if (dm->cnt_dm[BTC_DCNT_BTTX_HANG] >= BTC_CHK_HANG_MAX) 1133 dm->error.map.bt_tx_hang = true; 1134 else 1135 dm->error.map.bt_tx_hang = false; 1136 break; 1137 case BTC_DCNT_BTCNT_HANG: 1138 cnt = cx->cnt_bt[BTC_BCNT_HIPRI_RX] + 1139 cx->cnt_bt[BTC_BCNT_HIPRI_TX] + 1140 cx->cnt_bt[BTC_BCNT_LOPRI_RX] + 1141 cx->cnt_bt[BTC_BCNT_LOPRI_TX]; 1142 1143 if (cnt == 0) 1144 dm->cnt_dm[BTC_DCNT_BTCNT_HANG]++; 1145 else 1146 dm->cnt_dm[BTC_DCNT_BTCNT_HANG] = 0; 1147 1148 if ((dm->cnt_dm[BTC_DCNT_BTCNT_HANG] >= BTC_CHK_HANG_MAX && 1149 bt->enable.now) || (!dm->cnt_dm[BTC_DCNT_BTCNT_HANG] && 1150 !bt->enable.now)) 1151 _update_bt_scbd(rtwdev, false); 1152 break; 1153 case BTC_DCNT_WL_SLOT_DRIFT: 1154 if (cnt >= BTC_CHK_WLSLOT_DRIFT_MAX) 1155 dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT]++; 1156 else 1157 dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] = 0; 1158 1159 if (dm->cnt_dm[BTC_DCNT_WL_SLOT_DRIFT] >= BTC_CHK_HANG_MAX) 1160 dm->error.map.wl_slot_drift = true; 1161 else 1162 dm->error.map.wl_slot_drift = false; 1163 break; 1164 case BTC_DCNT_BT_SLOT_DRIFT: 1165 if (cnt >= BTC_CHK_BTSLOT_DRIFT_MAX) 1166 dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT]++; 1167 else 1168 dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT] = 0; 1169 1170 if (dm->cnt_dm[BTC_DCNT_BT_SLOT_DRIFT] >= BTC_CHK_HANG_MAX) 1171 dm->error.map.bt_slot_drift = true; 1172 else 1173 dm->error.map.bt_slot_drift = false; 1174 1175 break; 1176 } 1177 } 1178 1179 static void _update_bt_report(struct rtw89_dev *rtwdev, u8 rpt_type, u8 *pfinfo) 1180 { 1181 struct rtw89_btc *btc = &rtwdev->btc; 1182 const struct rtw89_btc_ver *ver = btc->ver; 1183 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 1184 struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; 1185 struct rtw89_btc_bt_a2dp_desc *a2dp = &bt_linfo->a2dp_desc; 1186 union rtw89_btc_fbtc_btver *pver = &btc->fwinfo.rpt_fbtc_btver.finfo; 1187 struct rtw89_btc_fbtc_btafh_v2 *pafh_v2 = NULL; 1188 struct rtw89_btc_fbtc_btafh_v7 *pafh_v7 = NULL; 1189 struct rtw89_btc_fbtc_btdevinfo *pdev = NULL; 1190 struct rtw89_btc_fbtc_btafh *pafh_v1 = NULL; 1191 struct rtw89_btc_fbtc_btscan_v1 *pscan_v1; 1192 struct rtw89_btc_fbtc_btscan_v2 *pscan_v2; 1193 struct rtw89_btc_fbtc_btscan_v7 *pscan_v7; 1194 bool scan_update = true; 1195 int i; 1196 1197 rtw89_debug(rtwdev, RTW89_DBG_BTC, 1198 "[BTC], %s(): rpt_type:%d\n", 1199 __func__, rpt_type); 1200 1201 switch (rpt_type) { 1202 case BTC_RPT_TYPE_BT_VER: 1203 if (ver->fcxbtver == 7) { 1204 pver->v7 = *(struct rtw89_btc_fbtc_btver_v7 *)pfinfo; 1205 bt->ver_info.fw = le32_to_cpu(pver->v7.fw_ver); 1206 bt->ver_info.fw_coex = le32_get_bits(pver->v7.coex_ver, 1207 GENMASK(7, 0)); 1208 bt->feature = le32_to_cpu(pver->v7.feature); 1209 } else { 1210 pver->v1 = *(struct rtw89_btc_fbtc_btver_v1 *)pfinfo; 1211 bt->ver_info.fw = le32_to_cpu(pver->v1.fw_ver); 1212 bt->ver_info.fw_coex = le32_get_bits(pver->v1.coex_ver, 1213 GENMASK(7, 0)); 1214 bt->feature = le32_to_cpu(pver->v1.feature); 1215 } 1216 break; 1217 case BTC_RPT_TYPE_BT_SCAN: 1218 if (ver->fcxbtscan == 1) { 1219 pscan_v1 = (struct rtw89_btc_fbtc_btscan_v1 *)pfinfo; 1220 for (i = 0; i < BTC_SCAN_MAX1; i++) { 1221 bt->scan_info_v1[i] = pscan_v1->scan[i]; 1222 if (bt->scan_info_v1[i].win == 0 && 1223 bt->scan_info_v1[i].intvl == 0) 1224 scan_update = false; 1225 } 1226 } else if (ver->fcxbtscan == 2) { 1227 pscan_v2 = (struct rtw89_btc_fbtc_btscan_v2 *)pfinfo; 1228 for (i = 0; i < CXSCAN_MAX; i++) { 1229 bt->scan_info_v2[i] = pscan_v2->para[i]; 1230 if ((pscan_v2->type & BIT(i)) && 1231 pscan_v2->para[i].win == 0 && 1232 pscan_v2->para[i].intvl == 0) 1233 scan_update = false; 1234 } 1235 } else if (ver->fcxbtscan == 7) { 1236 pscan_v7 = (struct rtw89_btc_fbtc_btscan_v7 *)pfinfo; 1237 for (i = 0; i < CXSCAN_MAX; i++) { 1238 bt->scan_info_v2[i] = pscan_v7->para[i]; 1239 if ((pscan_v7->type & BIT(i)) && 1240 pscan_v7->para[i].win == 0 && 1241 pscan_v7->para[i].intvl == 0) 1242 scan_update = false; 1243 } 1244 } 1245 if (scan_update) 1246 bt->scan_info_update = 1; 1247 break; 1248 case BTC_RPT_TYPE_BT_AFH: 1249 if (ver->fcxbtafh == 2) { 1250 pafh_v2 = (struct rtw89_btc_fbtc_btafh_v2 *)pfinfo; 1251 if (pafh_v2->map_type & RPT_BT_AFH_SEQ_LEGACY) { 1252 memcpy(&bt_linfo->afh_map[0], pafh_v2->afh_l, 4); 1253 memcpy(&bt_linfo->afh_map[4], pafh_v2->afh_m, 4); 1254 memcpy(&bt_linfo->afh_map[8], pafh_v2->afh_h, 2); 1255 } 1256 if (pafh_v2->map_type & RPT_BT_AFH_SEQ_LE) { 1257 memcpy(&bt_linfo->afh_map_le[0], pafh_v2->afh_le_a, 4); 1258 memcpy(&bt_linfo->afh_map_le[4], pafh_v2->afh_le_b, 1); 1259 } 1260 } else if (ver->fcxbtafh == 7) { 1261 pafh_v7 = (struct rtw89_btc_fbtc_btafh_v7 *)pfinfo; 1262 if (pafh_v7->map_type & RPT_BT_AFH_SEQ_LEGACY) { 1263 memcpy(&bt_linfo->afh_map[0], pafh_v7->afh_l, 4); 1264 memcpy(&bt_linfo->afh_map[4], pafh_v7->afh_m, 4); 1265 memcpy(&bt_linfo->afh_map[8], pafh_v7->afh_h, 2); 1266 } 1267 if (pafh_v7->map_type & RPT_BT_AFH_SEQ_LE) { 1268 memcpy(&bt_linfo->afh_map_le[0], pafh_v7->afh_le_a, 4); 1269 memcpy(&bt_linfo->afh_map_le[4], pafh_v7->afh_le_b, 1); 1270 } 1271 } else if (ver->fcxbtafh == 1) { 1272 pafh_v1 = (struct rtw89_btc_fbtc_btafh *)pfinfo; 1273 memcpy(&bt_linfo->afh_map[0], pafh_v1->afh_l, 4); 1274 memcpy(&bt_linfo->afh_map[4], pafh_v1->afh_m, 4); 1275 memcpy(&bt_linfo->afh_map[8], pafh_v1->afh_h, 2); 1276 } 1277 break; 1278 case BTC_RPT_TYPE_BT_DEVICE: 1279 pdev = (struct rtw89_btc_fbtc_btdevinfo *)pfinfo; 1280 a2dp->device_name = le32_to_cpu(pdev->dev_name); 1281 a2dp->vendor_id = le16_to_cpu(pdev->vendor_id); 1282 a2dp->flush_time = le32_to_cpu(pdev->flush_time); 1283 break; 1284 default: 1285 break; 1286 } 1287 } 1288 1289 static void rtw89_btc_fw_rpt_evnt_ver(struct rtw89_dev *rtwdev, u8 *index) 1290 { 1291 struct rtw89_btc *btc = &rtwdev->btc; 1292 const struct rtw89_btc_ver *ver = btc->ver; 1293 1294 if (ver->fwevntrptl == 1) 1295 return; 1296 1297 if (*index <= __BTC_RPT_TYPE_V0_SAME) 1298 return; 1299 else if (*index <= __BTC_RPT_TYPE_V0_MAX) 1300 (*index)++; 1301 else 1302 *index = BTC_RPT_TYPE_MAX; 1303 } 1304 1305 #define BTC_LEAK_AP_TH 10 1306 #define BTC_CYSTA_CHK_PERIOD 100 1307 1308 struct rtw89_btc_prpt { 1309 u8 type; 1310 __le16 len; 1311 u8 content[]; 1312 } __packed; 1313 1314 static u32 _chk_btc_report(struct rtw89_dev *rtwdev, 1315 struct rtw89_btc_btf_fwinfo *pfwinfo, 1316 u8 *prptbuf, u32 index) 1317 { 1318 struct rtw89_btc *btc = &rtwdev->btc; 1319 const struct rtw89_btc_ver *ver = btc->ver; 1320 struct rtw89_btc_dm *dm = &btc->dm; 1321 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 1322 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 1323 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 1324 union rtw89_btc_fbtc_rpt_ctrl_ver_info *prpt = NULL; 1325 union rtw89_btc_fbtc_cysta_info *pcysta = NULL; 1326 struct rtw89_btc_prpt *btc_prpt = NULL; 1327 void *rpt_content = NULL, *pfinfo = NULL; 1328 u8 rpt_type = 0; 1329 u16 wl_slot_set = 0, wl_slot_real = 0, val16; 1330 u32 trace_step = 0, rpt_len = 0, diff_t = 0; 1331 u32 cnt_leak_slot, bt_slot_real, bt_slot_set, cnt_rx_imr; 1332 u8 i, val = 0, val1, val2; 1333 1334 rtw89_debug(rtwdev, RTW89_DBG_BTC, 1335 "[BTC], %s(): index:%d\n", 1336 __func__, index); 1337 1338 if (!prptbuf) { 1339 pfwinfo->err[BTFRE_INVALID_INPUT]++; 1340 return 0; 1341 } 1342 1343 btc_prpt = (struct rtw89_btc_prpt *)&prptbuf[index]; 1344 rpt_type = btc_prpt->type; 1345 rpt_len = le16_to_cpu(btc_prpt->len); 1346 rpt_content = btc_prpt->content; 1347 1348 rtw89_debug(rtwdev, RTW89_DBG_BTC, 1349 "[BTC], %s(): rpt_type:%d\n", 1350 __func__, rpt_type); 1351 1352 rtw89_btc_fw_rpt_evnt_ver(rtwdev, &rpt_type); 1353 1354 switch (rpt_type) { 1355 case BTC_RPT_TYPE_CTRL: 1356 pcinfo = &pfwinfo->rpt_ctrl.cinfo; 1357 prpt = &pfwinfo->rpt_ctrl.finfo; 1358 if (ver->fcxbtcrpt == 1) { 1359 pfinfo = &pfwinfo->rpt_ctrl.finfo.v1; 1360 pcinfo->req_len = sizeof(pfwinfo->rpt_ctrl.finfo.v1); 1361 } else if (ver->fcxbtcrpt == 4) { 1362 pfinfo = &pfwinfo->rpt_ctrl.finfo.v4; 1363 pcinfo->req_len = sizeof(pfwinfo->rpt_ctrl.finfo.v4); 1364 } else if (ver->fcxbtcrpt == 5) { 1365 pfinfo = &pfwinfo->rpt_ctrl.finfo.v5; 1366 pcinfo->req_len = sizeof(pfwinfo->rpt_ctrl.finfo.v5); 1367 } else if (ver->fcxbtcrpt == 105) { 1368 pfinfo = &pfwinfo->rpt_ctrl.finfo.v105; 1369 pcinfo->req_len = sizeof(pfwinfo->rpt_ctrl.finfo.v105); 1370 pcinfo->req_fver = 5; 1371 break; 1372 } else if (ver->fcxbtcrpt == 8) { 1373 pfinfo = &pfwinfo->rpt_ctrl.finfo.v8; 1374 pcinfo->req_len = sizeof(pfwinfo->rpt_ctrl.finfo.v8); 1375 break; 1376 } else if (ver->fcxbtcrpt == 7) { 1377 pfinfo = &pfwinfo->rpt_ctrl.finfo.v7; 1378 pcinfo->req_len = sizeof(pfwinfo->rpt_ctrl.finfo.v7); 1379 break; 1380 } else { 1381 goto err; 1382 } 1383 pcinfo->req_fver = ver->fcxbtcrpt; 1384 break; 1385 case BTC_RPT_TYPE_TDMA: 1386 pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo; 1387 if (ver->fcxtdma == 1) { 1388 pfinfo = &pfwinfo->rpt_fbtc_tdma.finfo.v1; 1389 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_tdma.finfo.v1); 1390 } else if (ver->fcxtdma == 3 || ver->fcxtdma == 7) { 1391 pfinfo = &pfwinfo->rpt_fbtc_tdma.finfo.v3; 1392 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_tdma.finfo.v3); 1393 } else { 1394 goto err; 1395 } 1396 pcinfo->req_fver = ver->fcxtdma; 1397 break; 1398 case BTC_RPT_TYPE_SLOT: 1399 pcinfo = &pfwinfo->rpt_fbtc_slots.cinfo; 1400 if (ver->fcxslots == 1) { 1401 pfinfo = &pfwinfo->rpt_fbtc_slots.finfo.v1; 1402 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_slots.finfo.v1); 1403 } else if (ver->fcxslots == 7) { 1404 pfinfo = &pfwinfo->rpt_fbtc_slots.finfo.v7; 1405 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_slots.finfo.v7); 1406 } else { 1407 goto err; 1408 } 1409 pcinfo->req_fver = ver->fcxslots; 1410 break; 1411 case BTC_RPT_TYPE_CYSTA: 1412 pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; 1413 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo; 1414 if (ver->fcxcysta == 2) { 1415 pfinfo = &pfwinfo->rpt_fbtc_cysta.finfo.v2; 1416 pcysta->v2 = pfwinfo->rpt_fbtc_cysta.finfo.v2; 1417 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo.v2); 1418 } else if (ver->fcxcysta == 3) { 1419 pfinfo = &pfwinfo->rpt_fbtc_cysta.finfo.v3; 1420 pcysta->v3 = pfwinfo->rpt_fbtc_cysta.finfo.v3; 1421 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo.v3); 1422 } else if (ver->fcxcysta == 4) { 1423 pfinfo = &pfwinfo->rpt_fbtc_cysta.finfo.v4; 1424 pcysta->v4 = pfwinfo->rpt_fbtc_cysta.finfo.v4; 1425 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo.v4); 1426 } else if (ver->fcxcysta == 5) { 1427 pfinfo = &pfwinfo->rpt_fbtc_cysta.finfo.v5; 1428 pcysta->v5 = pfwinfo->rpt_fbtc_cysta.finfo.v5; 1429 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo.v5); 1430 } else if (ver->fcxcysta == 7) { 1431 pfinfo = &pfwinfo->rpt_fbtc_cysta.finfo.v7; 1432 pcysta->v7 = pfwinfo->rpt_fbtc_cysta.finfo.v7; 1433 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_cysta.finfo.v7); 1434 } else { 1435 goto err; 1436 } 1437 pcinfo->req_fver = ver->fcxcysta; 1438 break; 1439 case BTC_RPT_TYPE_STEP: 1440 pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; 1441 if (ver->fcxctrl != 7) 1442 trace_step = btc->ctrl.ctrl.trace_step; 1443 1444 if (ver->fcxstep == 2) { 1445 pfinfo = &pfwinfo->rpt_fbtc_step.finfo.v2; 1446 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_step.finfo.v2.step[0]) * 1447 trace_step + 1448 offsetof(struct rtw89_btc_fbtc_steps_v2, step); 1449 } else if (ver->fcxstep == 3) { 1450 pfinfo = &pfwinfo->rpt_fbtc_step.finfo.v3; 1451 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_step.finfo.v3.step[0]) * 1452 trace_step + 1453 offsetof(struct rtw89_btc_fbtc_steps_v3, step); 1454 } else { 1455 goto err; 1456 } 1457 pcinfo->req_fver = ver->fcxstep; 1458 break; 1459 case BTC_RPT_TYPE_NULLSTA: 1460 pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo; 1461 if (ver->fcxnullsta == 1) { 1462 pfinfo = &pfwinfo->rpt_fbtc_nullsta.finfo.v1; 1463 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_nullsta.finfo.v1); 1464 } else if (ver->fcxnullsta == 2) { 1465 pfinfo = &pfwinfo->rpt_fbtc_nullsta.finfo.v2; 1466 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_nullsta.finfo.v2); 1467 } else if (ver->fcxnullsta == 7) { 1468 pfinfo = &pfwinfo->rpt_fbtc_nullsta.finfo.v7; 1469 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_nullsta.finfo.v7); 1470 } else { 1471 goto err; 1472 } 1473 pcinfo->req_fver = ver->fcxnullsta; 1474 break; 1475 case BTC_RPT_TYPE_MREG: 1476 pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; 1477 if (ver->fcxmreg == 1) { 1478 pfinfo = &pfwinfo->rpt_fbtc_mregval.finfo.v1; 1479 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_mregval.finfo.v1); 1480 } else if (ver->fcxmreg == 2) { 1481 pfinfo = &pfwinfo->rpt_fbtc_mregval.finfo.v2; 1482 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_mregval.finfo.v2); 1483 } else if (ver->fcxmreg == 7) { 1484 pfinfo = &pfwinfo->rpt_fbtc_mregval.finfo.v7; 1485 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_mregval.finfo.v7); 1486 } else { 1487 goto err; 1488 } 1489 pcinfo->req_fver = ver->fcxmreg; 1490 break; 1491 case BTC_RPT_TYPE_GPIO_DBG: 1492 pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo; 1493 if (ver->fcxgpiodbg == 7) { 1494 pfinfo = &pfwinfo->rpt_fbtc_gpio_dbg.finfo.v7; 1495 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_gpio_dbg.finfo.v7); 1496 } else { 1497 pfinfo = &pfwinfo->rpt_fbtc_gpio_dbg.finfo.v1; 1498 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_gpio_dbg.finfo.v1); 1499 } 1500 pcinfo->req_fver = ver->fcxgpiodbg; 1501 break; 1502 case BTC_RPT_TYPE_BT_VER: 1503 pcinfo = &pfwinfo->rpt_fbtc_btver.cinfo; 1504 if (ver->fcxbtver == 1) { 1505 pfinfo = &pfwinfo->rpt_fbtc_btver.finfo.v1; 1506 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btver.finfo.v1); 1507 } else if (ver->fcxbtver == 7) { 1508 pfinfo = &pfwinfo->rpt_fbtc_btver.finfo.v7; 1509 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btver.finfo.v7); 1510 } 1511 pcinfo->req_fver = ver->fcxbtver; 1512 break; 1513 case BTC_RPT_TYPE_BT_SCAN: 1514 pcinfo = &pfwinfo->rpt_fbtc_btscan.cinfo; 1515 if (ver->fcxbtscan == 1) { 1516 pfinfo = &pfwinfo->rpt_fbtc_btscan.finfo.v1; 1517 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btscan.finfo.v1); 1518 } else if (ver->fcxbtscan == 2) { 1519 pfinfo = &pfwinfo->rpt_fbtc_btscan.finfo.v2; 1520 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btscan.finfo.v2); 1521 } else if (ver->fcxbtscan == 7) { 1522 pfinfo = &pfwinfo->rpt_fbtc_btscan.finfo.v7; 1523 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btscan.finfo.v7); 1524 } else { 1525 goto err; 1526 } 1527 pcinfo->req_fver = ver->fcxbtscan; 1528 break; 1529 case BTC_RPT_TYPE_BT_AFH: 1530 pcinfo = &pfwinfo->rpt_fbtc_btafh.cinfo; 1531 if (ver->fcxbtafh == 1) { 1532 pfinfo = &pfwinfo->rpt_fbtc_btafh.finfo.v1; 1533 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btafh.finfo.v1); 1534 } else if (ver->fcxbtafh == 2) { 1535 pfinfo = &pfwinfo->rpt_fbtc_btafh.finfo.v2; 1536 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btafh.finfo.v2); 1537 } else { 1538 goto err; 1539 } 1540 pcinfo->req_fver = ver->fcxbtafh; 1541 break; 1542 case BTC_RPT_TYPE_BT_DEVICE: 1543 pcinfo = &pfwinfo->rpt_fbtc_btdev.cinfo; 1544 pfinfo = &pfwinfo->rpt_fbtc_btdev.finfo; 1545 pcinfo->req_len = sizeof(pfwinfo->rpt_fbtc_btdev.finfo); 1546 pcinfo->req_fver = ver->fcxbtdevinfo; 1547 break; 1548 default: 1549 pfwinfo->err[BTFRE_UNDEF_TYPE]++; 1550 return 0; 1551 } 1552 1553 pcinfo->rx_len = rpt_len; 1554 pcinfo->rx_cnt++; 1555 1556 if (rpt_len != pcinfo->req_len) { 1557 if (rpt_type < BTC_RPT_TYPE_MAX) 1558 pfwinfo->len_mismch |= (0x1 << rpt_type); 1559 else 1560 pfwinfo->len_mismch |= BIT(31); 1561 rtw89_debug(rtwdev, RTW89_DBG_BTC, 1562 "[BTC], %s(): %d rpt_len:%d!=req_len:%d\n", 1563 __func__, rpt_type, rpt_len, pcinfo->req_len); 1564 1565 pcinfo->valid = 0; 1566 return 0; 1567 } else if (!pfinfo || !rpt_content || !pcinfo->req_len) { 1568 pfwinfo->err[BTFRE_EXCEPTION]++; 1569 pcinfo->valid = 0; 1570 return 0; 1571 } 1572 1573 memcpy(pfinfo, rpt_content, pcinfo->req_len); 1574 pcinfo->valid = 1; 1575 1576 switch (rpt_type) { 1577 case BTC_RPT_TYPE_CTRL: 1578 if (ver->fcxbtcrpt == 1) { 1579 prpt->v1 = pfwinfo->rpt_ctrl.finfo.v1; 1580 btc->fwinfo.rpt_en_map = prpt->v1.rpt_enable; 1581 wl->ver_info.fw_coex = prpt->v1.wl_fw_coex_ver; 1582 wl->ver_info.fw = prpt->v1.wl_fw_ver; 1583 dm->wl_fw_cx_offload = !!prpt->v1.wl_fw_cx_offload; 1584 1585 _chk_btc_err(rtwdev, BTC_DCNT_RPT_HANG, 1586 pfwinfo->event[BTF_EVNT_RPT]); 1587 1588 /* To avoid I/O if WL LPS or power-off */ 1589 if (wl->status.map.lps != BTC_LPS_RF_OFF && 1590 !wl->status.map.rf_off) { 1591 rtwdev->chip->ops->btc_update_bt_cnt(rtwdev); 1592 _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_HANG, 0); 1593 1594 btc->cx.cnt_bt[BTC_BCNT_POLUT] = 1595 rtw89_mac_get_plt_cnt(rtwdev, 1596 RTW89_MAC_0); 1597 } 1598 } else if (ver->fcxbtcrpt == 4) { 1599 prpt->v4 = pfwinfo->rpt_ctrl.finfo.v4; 1600 btc->fwinfo.rpt_en_map = le32_to_cpu(prpt->v4.rpt_info.en); 1601 wl->ver_info.fw_coex = le32_to_cpu(prpt->v4.wl_fw_info.cx_ver); 1602 wl->ver_info.fw = le32_to_cpu(prpt->v4.wl_fw_info.fw_ver); 1603 dm->wl_fw_cx_offload = !!le32_to_cpu(prpt->v4.wl_fw_info.cx_offload); 1604 1605 for (i = RTW89_PHY_0; i < RTW89_PHY_MAX; i++) 1606 memcpy(&dm->gnt.band[i], &prpt->v4.gnt_val[i], 1607 sizeof(dm->gnt.band[i])); 1608 1609 btc->cx.cnt_bt[BTC_BCNT_HIPRI_TX] = 1610 le32_to_cpu(prpt->v4.bt_cnt[BTC_BCNT_HI_TX]); 1611 btc->cx.cnt_bt[BTC_BCNT_HIPRI_RX] = 1612 le32_to_cpu(prpt->v4.bt_cnt[BTC_BCNT_HI_RX]); 1613 btc->cx.cnt_bt[BTC_BCNT_LOPRI_TX] = 1614 le32_to_cpu(prpt->v4.bt_cnt[BTC_BCNT_LO_TX]); 1615 btc->cx.cnt_bt[BTC_BCNT_LOPRI_RX] = 1616 le32_to_cpu(prpt->v4.bt_cnt[BTC_BCNT_LO_RX]); 1617 btc->cx.cnt_bt[BTC_BCNT_POLUT] = 1618 le32_to_cpu(prpt->v4.bt_cnt[BTC_BCNT_POLLUTED]); 1619 1620 _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_HANG, 0); 1621 _chk_btc_err(rtwdev, BTC_DCNT_RPT_HANG, 1622 pfwinfo->event[BTF_EVNT_RPT]); 1623 1624 if (le32_to_cpu(prpt->v4.bt_cnt[BTC_BCNT_RFK_TIMEOUT]) > 0) 1625 bt->rfk_info.map.timeout = 1; 1626 else 1627 bt->rfk_info.map.timeout = 0; 1628 1629 dm->error.map.bt_rfk_timeout = bt->rfk_info.map.timeout; 1630 } else if (ver->fcxbtcrpt == 5) { 1631 prpt->v5 = pfwinfo->rpt_ctrl.finfo.v5; 1632 pfwinfo->rpt_en_map = le32_to_cpu(prpt->v5.rpt_info.en); 1633 wl->ver_info.fw_coex = le32_to_cpu(prpt->v5.rpt_info.cx_ver); 1634 wl->ver_info.fw = le32_to_cpu(prpt->v5.rpt_info.fw_ver); 1635 dm->wl_fw_cx_offload = 0; 1636 1637 for (i = RTW89_PHY_0; i < RTW89_PHY_MAX; i++) 1638 memcpy(&dm->gnt.band[i], &prpt->v5.gnt_val[i][0], 1639 sizeof(dm->gnt.band[i])); 1640 1641 btc->cx.cnt_bt[BTC_BCNT_HIPRI_TX] = 1642 le16_to_cpu(prpt->v5.bt_cnt[BTC_BCNT_HI_TX]); 1643 btc->cx.cnt_bt[BTC_BCNT_HIPRI_RX] = 1644 le16_to_cpu(prpt->v5.bt_cnt[BTC_BCNT_HI_RX]); 1645 btc->cx.cnt_bt[BTC_BCNT_LOPRI_TX] = 1646 le16_to_cpu(prpt->v5.bt_cnt[BTC_BCNT_LO_TX]); 1647 btc->cx.cnt_bt[BTC_BCNT_LOPRI_RX] = 1648 le16_to_cpu(prpt->v5.bt_cnt[BTC_BCNT_LO_RX]); 1649 btc->cx.cnt_bt[BTC_BCNT_POLUT] = 1650 le16_to_cpu(prpt->v5.bt_cnt[BTC_BCNT_POLLUTED]); 1651 1652 _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_HANG, 0); 1653 _chk_btc_err(rtwdev, BTC_DCNT_RPT_HANG, 1654 pfwinfo->event[BTF_EVNT_RPT]); 1655 1656 dm->error.map.bt_rfk_timeout = bt->rfk_info.map.timeout; 1657 } else if (ver->fcxbtcrpt == 105) { 1658 prpt->v105 = pfwinfo->rpt_ctrl.finfo.v105; 1659 pfwinfo->rpt_en_map = le32_to_cpu(prpt->v105.rpt_info.en); 1660 wl->ver_info.fw_coex = le32_to_cpu(prpt->v105.rpt_info.cx_ver); 1661 wl->ver_info.fw = le32_to_cpu(prpt->v105.rpt_info.fw_ver); 1662 dm->wl_fw_cx_offload = 0; 1663 1664 for (i = RTW89_PHY_0; i < RTW89_PHY_MAX; i++) 1665 memcpy(&dm->gnt.band[i], &prpt->v105.gnt_val[i][0], 1666 sizeof(dm->gnt.band[i])); 1667 1668 btc->cx.cnt_bt[BTC_BCNT_HIPRI_TX] = 1669 le16_to_cpu(prpt->v105.bt_cnt[BTC_BCNT_HI_TX_V105]); 1670 btc->cx.cnt_bt[BTC_BCNT_HIPRI_RX] = 1671 le16_to_cpu(prpt->v105.bt_cnt[BTC_BCNT_HI_RX_V105]); 1672 btc->cx.cnt_bt[BTC_BCNT_LOPRI_TX] = 1673 le16_to_cpu(prpt->v105.bt_cnt[BTC_BCNT_LO_TX_V105]); 1674 btc->cx.cnt_bt[BTC_BCNT_LOPRI_RX] = 1675 le16_to_cpu(prpt->v105.bt_cnt[BTC_BCNT_LO_RX_V105]); 1676 btc->cx.cnt_bt[BTC_BCNT_POLUT] = 1677 le16_to_cpu(prpt->v105.bt_cnt[BTC_BCNT_POLLUTED_V105]); 1678 1679 _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_HANG, 0); 1680 _chk_btc_err(rtwdev, BTC_DCNT_RPT_HANG, 1681 pfwinfo->event[BTF_EVNT_RPT]); 1682 1683 dm->error.map.bt_rfk_timeout = bt->rfk_info.map.timeout; 1684 } else if (ver->fcxbtcrpt == 7) { 1685 prpt->v7 = pfwinfo->rpt_ctrl.finfo.v7; 1686 pfwinfo->rpt_en_map = le32_to_cpu(prpt->v7.rpt_info.en); 1687 wl->ver_info.fw_coex = le32_to_cpu(prpt->v7.rpt_info.cx_ver); 1688 wl->ver_info.fw = le32_to_cpu(prpt->v7.rpt_info.fw_ver); 1689 1690 for (i = RTW89_PHY_0; i < RTW89_PHY_MAX; i++) 1691 memcpy(&dm->gnt.band[i], &prpt->v7.gnt_val[i][0], 1692 sizeof(dm->gnt.band[i])); 1693 1694 btc->cx.cnt_bt[BTC_BCNT_HIPRI_TX] = 1695 le16_to_cpu(prpt->v7.bt_cnt[BTC_BCNT_HI_TX_V105]); 1696 btc->cx.cnt_bt[BTC_BCNT_HIPRI_RX] = 1697 le16_to_cpu(prpt->v7.bt_cnt[BTC_BCNT_HI_RX_V105]); 1698 btc->cx.cnt_bt[BTC_BCNT_LOPRI_TX] = 1699 le16_to_cpu(prpt->v7.bt_cnt[BTC_BCNT_LO_TX_V105]); 1700 btc->cx.cnt_bt[BTC_BCNT_LOPRI_RX] = 1701 le16_to_cpu(prpt->v7.bt_cnt[BTC_BCNT_LO_RX_V105]); 1702 1703 val1 = le16_to_cpu(prpt->v7.bt_cnt[BTC_BCNT_POLLUTED_V105]); 1704 if (val1 > btc->cx.cnt_bt[BTC_BCNT_POLUT_NOW]) 1705 val1 -= btc->cx.cnt_bt[BTC_BCNT_POLUT_NOW]; /* diff */ 1706 1707 btc->cx.cnt_bt[BTC_BCNT_POLUT_DIFF] = val1; 1708 btc->cx.cnt_bt[BTC_BCNT_POLUT_NOW] = 1709 le16_to_cpu(prpt->v7.bt_cnt[BTC_BCNT_POLLUTED_V105]); 1710 1711 val1 = pfwinfo->event[BTF_EVNT_RPT]; 1712 _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_HANG, 0); 1713 _chk_btc_err(rtwdev, BTC_DCNT_RPT_HANG, val1); 1714 _chk_btc_err(rtwdev, BTC_DCNT_WL_FW_VER_MATCH, 0); 1715 _chk_btc_err(rtwdev, BTC_DCNT_BTTX_HANG, 0); 1716 } else if (ver->fcxbtcrpt == 8) { 1717 prpt->v8 = pfwinfo->rpt_ctrl.finfo.v8; 1718 pfwinfo->rpt_en_map = le32_to_cpu(prpt->v8.rpt_info.en); 1719 wl->ver_info.fw_coex = le32_to_cpu(prpt->v8.rpt_info.cx_ver); 1720 wl->ver_info.fw = le32_to_cpu(prpt->v8.rpt_info.fw_ver); 1721 1722 for (i = RTW89_PHY_0; i < RTW89_PHY_MAX; i++) 1723 memcpy(&dm->gnt.band[i], &prpt->v8.gnt_val[i][0], 1724 sizeof(dm->gnt.band[i])); 1725 1726 btc->cx.cnt_bt[BTC_BCNT_HIPRI_TX] = 1727 le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_HI_TX_V105]); 1728 btc->cx.cnt_bt[BTC_BCNT_HIPRI_RX] = 1729 le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_HI_RX_V105]); 1730 btc->cx.cnt_bt[BTC_BCNT_LOPRI_TX] = 1731 le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_LO_TX_V105]); 1732 btc->cx.cnt_bt[BTC_BCNT_LOPRI_RX] = 1733 le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_LO_RX_V105]); 1734 1735 val1 = le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_POLLUTED_V105]); 1736 if (val1 > btc->cx.cnt_bt[BTC_BCNT_POLUT_NOW]) 1737 val1 -= btc->cx.cnt_bt[BTC_BCNT_POLUT_NOW]; /* diff */ 1738 1739 btc->cx.cnt_bt[BTC_BCNT_POLUT_DIFF] = val1; 1740 btc->cx.cnt_bt[BTC_BCNT_POLUT_NOW] = 1741 le16_to_cpu(prpt->v8.bt_cnt[BTC_BCNT_POLLUTED_V105]); 1742 1743 val1 = pfwinfo->event[BTF_EVNT_RPT]; 1744 if (((prpt->v8.rpt_len_max_h << 8) + 1745 prpt->v8.rpt_len_max_l) != ver->info_buf) 1746 dm->error.map.h2c_c2h_buffer_mismatch = true; 1747 else 1748 dm->error.map.h2c_c2h_buffer_mismatch = false; 1749 1750 _chk_btc_err(rtwdev, BTC_DCNT_BTCNT_HANG, 0); 1751 _chk_btc_err(rtwdev, BTC_DCNT_RPT_HANG, val1); 1752 _chk_btc_err(rtwdev, BTC_DCNT_WL_FW_VER_MATCH, 0); 1753 _chk_btc_err(rtwdev, BTC_DCNT_BTTX_HANG, 0); 1754 } else { 1755 goto err; 1756 } 1757 break; 1758 case BTC_RPT_TYPE_TDMA: 1759 rtw89_debug(rtwdev, RTW89_DBG_BTC, 1760 "[BTC], %s(): check %d %zu\n", __func__, 1761 BTC_DCNT_TDMA_NONSYNC, 1762 sizeof(dm->tdma_now)); 1763 if (ver->fcxtdma == 1) 1764 _chk_btc_err(rtwdev, BTC_DCNT_TDMA_NONSYNC, 1765 memcmp(&dm->tdma_now, 1766 &pfwinfo->rpt_fbtc_tdma.finfo.v1, 1767 sizeof(dm->tdma_now))); 1768 else if (ver->fcxtdma == 3 || ver->fcxtdma == 7) 1769 _chk_btc_err(rtwdev, BTC_DCNT_TDMA_NONSYNC, 1770 memcmp(&dm->tdma_now, 1771 &pfwinfo->rpt_fbtc_tdma.finfo.v3.tdma, 1772 sizeof(dm->tdma_now))); 1773 else 1774 goto err; 1775 break; 1776 case BTC_RPT_TYPE_SLOT: 1777 if (ver->fcxslots == 7) { 1778 rtw89_debug(rtwdev, RTW89_DBG_BTC, 1779 "[BTC], %s(): check %d %zu\n", 1780 __func__, BTC_DCNT_SLOT_NONSYNC, 1781 sizeof(dm->slot_now.v7)); 1782 _chk_btc_err(rtwdev, BTC_DCNT_SLOT_NONSYNC, 1783 memcmp(dm->slot_now.v7, 1784 pfwinfo->rpt_fbtc_slots.finfo.v7.slot, 1785 sizeof(dm->slot_now.v7))); 1786 } else if (ver->fcxslots == 1) { 1787 rtw89_debug(rtwdev, RTW89_DBG_BTC, 1788 "[BTC], %s(): check %d %zu\n", 1789 __func__, BTC_DCNT_SLOT_NONSYNC, 1790 sizeof(dm->slot_now.v1)); 1791 _chk_btc_err(rtwdev, BTC_DCNT_SLOT_NONSYNC, 1792 memcmp(dm->slot_now.v1, 1793 pfwinfo->rpt_fbtc_slots.finfo.v1.slot, 1794 sizeof(dm->slot_now.v1))); 1795 } 1796 break; 1797 case BTC_RPT_TYPE_CYSTA: 1798 if (ver->fcxcysta == 2) { 1799 if (le16_to_cpu(pcysta->v2.cycles) < BTC_CYSTA_CHK_PERIOD) 1800 break; 1801 /* Check Leak-AP */ 1802 if (le32_to_cpu(pcysta->v2.slot_cnt[CXST_LK]) != 0 && 1803 le32_to_cpu(pcysta->v2.leakrx_cnt) != 0 && dm->tdma_now.rxflctrl) { 1804 if (le32_to_cpu(pcysta->v2.slot_cnt[CXST_LK]) < 1805 BTC_LEAK_AP_TH * le32_to_cpu(pcysta->v2.leakrx_cnt)) 1806 dm->leak_ap = 1; 1807 } 1808 1809 /* Check diff time between WL slot and W1/E2G slot */ 1810 if (dm->tdma_now.type == CXTDMA_OFF && 1811 dm->tdma_now.ext_ctrl == CXECTL_EXT) { 1812 if (ver->fcxslots == 1) 1813 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_E2G].dur); 1814 else if (ver->fcxslots == 7) 1815 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_E2G].dur); 1816 } else { 1817 if (ver->fcxslots == 1) 1818 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_W1].dur); 1819 else if (ver->fcxslots == 7) 1820 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_W1].dur); 1821 } 1822 1823 if (le16_to_cpu(pcysta->v2.tavg_cycle[CXT_WL]) > wl_slot_set) { 1824 diff_t = le16_to_cpu(pcysta->v2.tavg_cycle[CXT_WL]) - wl_slot_set; 1825 _chk_btc_err(rtwdev, 1826 BTC_DCNT_WL_SLOT_DRIFT, diff_t); 1827 } 1828 1829 _chk_btc_err(rtwdev, BTC_DCNT_W1_HANG, 1830 le32_to_cpu(pcysta->v2.slot_cnt[CXST_W1])); 1831 _chk_btc_err(rtwdev, BTC_DCNT_W1_HANG, 1832 le32_to_cpu(pcysta->v2.slot_cnt[CXST_B1])); 1833 _chk_btc_err(rtwdev, BTC_DCNT_CYCLE_HANG, 1834 le16_to_cpu(pcysta->v2.cycles)); 1835 } else if (ver->fcxcysta == 3) { 1836 if (le16_to_cpu(pcysta->v3.cycles) < BTC_CYSTA_CHK_PERIOD) 1837 break; 1838 1839 cnt_leak_slot = le32_to_cpu(pcysta->v3.slot_cnt[CXST_LK]); 1840 cnt_rx_imr = le32_to_cpu(pcysta->v3.leak_slot.cnt_rximr); 1841 1842 /* Check Leak-AP */ 1843 if (cnt_leak_slot != 0 && cnt_rx_imr != 0 && 1844 dm->tdma_now.rxflctrl) { 1845 if (cnt_leak_slot < BTC_LEAK_AP_TH * cnt_rx_imr) 1846 dm->leak_ap = 1; 1847 } 1848 1849 /* Check diff time between real WL slot and W1 slot */ 1850 if (dm->tdma_now.type == CXTDMA_OFF) { 1851 if (ver->fcxslots == 1) 1852 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_W1].dur); 1853 else if (ver->fcxslots == 7) 1854 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_W1].dur); 1855 wl_slot_real = le16_to_cpu(pcysta->v3.cycle_time.tavg[CXT_WL]); 1856 if (wl_slot_real > wl_slot_set) { 1857 diff_t = wl_slot_real - wl_slot_set; 1858 _chk_btc_err(rtwdev, BTC_DCNT_WL_SLOT_DRIFT, diff_t); 1859 } 1860 } 1861 1862 /* Check diff time between real BT slot and EBT/E5G slot */ 1863 if (dm->tdma_now.type == CXTDMA_OFF && 1864 dm->tdma_now.ext_ctrl == CXECTL_EXT && 1865 btc->bt_req_len != 0) { 1866 bt_slot_real = le16_to_cpu(pcysta->v3.cycle_time.tavg[CXT_BT]); 1867 if (btc->bt_req_len > bt_slot_real) { 1868 diff_t = btc->bt_req_len - bt_slot_real; 1869 _chk_btc_err(rtwdev, BTC_DCNT_BT_SLOT_DRIFT, diff_t); 1870 } 1871 } 1872 1873 _chk_btc_err(rtwdev, BTC_DCNT_W1_HANG, 1874 le32_to_cpu(pcysta->v3.slot_cnt[CXST_W1])); 1875 _chk_btc_err(rtwdev, BTC_DCNT_B1_HANG, 1876 le32_to_cpu(pcysta->v3.slot_cnt[CXST_B1])); 1877 _chk_btc_err(rtwdev, BTC_DCNT_CYCLE_HANG, 1878 le16_to_cpu(pcysta->v3.cycles)); 1879 } else if (ver->fcxcysta == 4) { 1880 if (le16_to_cpu(pcysta->v4.cycles) < BTC_CYSTA_CHK_PERIOD) 1881 break; 1882 1883 cnt_leak_slot = le16_to_cpu(pcysta->v4.slot_cnt[CXST_LK]); 1884 cnt_rx_imr = le32_to_cpu(pcysta->v4.leak_slot.cnt_rximr); 1885 1886 /* Check Leak-AP */ 1887 if (cnt_leak_slot != 0 && cnt_rx_imr != 0 && 1888 dm->tdma_now.rxflctrl) { 1889 if (cnt_leak_slot < BTC_LEAK_AP_TH * cnt_rx_imr) 1890 dm->leak_ap = 1; 1891 } 1892 1893 /* Check diff time between real WL slot and W1 slot */ 1894 if (dm->tdma_now.type == CXTDMA_OFF) { 1895 if (ver->fcxslots == 1) 1896 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_W1].dur); 1897 else if (ver->fcxslots == 7) 1898 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_W1].dur); 1899 wl_slot_real = le16_to_cpu(pcysta->v4.cycle_time.tavg[CXT_WL]); 1900 if (wl_slot_real > wl_slot_set) { 1901 diff_t = wl_slot_real - wl_slot_set; 1902 _chk_btc_err(rtwdev, BTC_DCNT_WL_SLOT_DRIFT, diff_t); 1903 } 1904 } 1905 1906 /* Check diff time between real BT slot and EBT/E5G slot */ 1907 if (dm->tdma_now.type == CXTDMA_OFF && 1908 dm->tdma_now.ext_ctrl == CXECTL_EXT && 1909 btc->bt_req_len != 0) { 1910 bt_slot_real = le16_to_cpu(pcysta->v4.cycle_time.tavg[CXT_BT]); 1911 1912 if (btc->bt_req_len > bt_slot_real) { 1913 diff_t = btc->bt_req_len - bt_slot_real; 1914 _chk_btc_err(rtwdev, BTC_DCNT_BT_SLOT_DRIFT, diff_t); 1915 } 1916 } 1917 1918 _chk_btc_err(rtwdev, BTC_DCNT_W1_HANG, 1919 le16_to_cpu(pcysta->v4.slot_cnt[CXST_W1])); 1920 _chk_btc_err(rtwdev, BTC_DCNT_B1_HANG, 1921 le16_to_cpu(pcysta->v4.slot_cnt[CXST_B1])); 1922 _chk_btc_err(rtwdev, BTC_DCNT_CYCLE_HANG, 1923 le16_to_cpu(pcysta->v4.cycles)); 1924 } else if (ver->fcxcysta == 5) { 1925 if (dm->fddt_train == BTC_FDDT_ENABLE) 1926 break; 1927 cnt_leak_slot = le16_to_cpu(pcysta->v5.slot_cnt[CXST_LK]); 1928 cnt_rx_imr = le32_to_cpu(pcysta->v5.leak_slot.cnt_rximr); 1929 1930 /* Check Leak-AP */ 1931 if (cnt_leak_slot != 0 && cnt_rx_imr != 0 && 1932 dm->tdma_now.rxflctrl) { 1933 if (le16_to_cpu(pcysta->v5.cycles) >= BTC_CYSTA_CHK_PERIOD && 1934 cnt_leak_slot < BTC_LEAK_AP_TH * cnt_rx_imr) 1935 dm->leak_ap = 1; 1936 } 1937 1938 /* Check diff time between real WL slot and W1 slot */ 1939 if (dm->tdma_now.type == CXTDMA_OFF) { 1940 if (ver->fcxslots == 1) 1941 wl_slot_set = le16_to_cpu(dm->slot_now.v1[CXST_W1].dur); 1942 else if (ver->fcxslots == 7) 1943 wl_slot_set = le16_to_cpu(dm->slot_now.v7[CXST_W1].dur); 1944 wl_slot_real = le16_to_cpu(pcysta->v5.cycle_time.tavg[CXT_WL]); 1945 1946 if (wl_slot_real > wl_slot_set) 1947 diff_t = wl_slot_real - wl_slot_set; 1948 else 1949 diff_t = wl_slot_set - wl_slot_real; 1950 } 1951 _chk_btc_err(rtwdev, BTC_DCNT_WL_SLOT_DRIFT, diff_t); 1952 1953 /* Check diff time between real BT slot and EBT/E5G slot */ 1954 bt_slot_set = btc->bt_req_len; 1955 bt_slot_real = le16_to_cpu(pcysta->v5.cycle_time.tavg[CXT_BT]); 1956 diff_t = 0; 1957 if (dm->tdma_now.type == CXTDMA_OFF && 1958 dm->tdma_now.ext_ctrl == CXECTL_EXT && 1959 bt_slot_set != 0) { 1960 if (bt_slot_set > bt_slot_real) 1961 diff_t = bt_slot_set - bt_slot_real; 1962 else 1963 diff_t = bt_slot_real - bt_slot_set; 1964 } 1965 1966 _chk_btc_err(rtwdev, BTC_DCNT_BT_SLOT_DRIFT, diff_t); 1967 _chk_btc_err(rtwdev, BTC_DCNT_E2G_HANG, 1968 le16_to_cpu(pcysta->v5.slot_cnt[CXST_E2G])); 1969 _chk_btc_err(rtwdev, BTC_DCNT_W1_HANG, 1970 le16_to_cpu(pcysta->v5.slot_cnt[CXST_W1])); 1971 _chk_btc_err(rtwdev, BTC_DCNT_B1_HANG, 1972 le16_to_cpu(pcysta->v5.slot_cnt[CXST_B1])); 1973 _chk_btc_err(rtwdev, BTC_DCNT_CYCLE_HANG, 1974 le16_to_cpu(pcysta->v5.cycles)); 1975 } else if (ver->fcxcysta == 7) { 1976 if (dm->fddt_train == BTC_FDDT_ENABLE) 1977 break; 1978 1979 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo; 1980 1981 if (dm->tdma_now.type != CXTDMA_OFF) { 1982 /* Check diff time between real WL slot and W1 slot */ 1983 val16 = le16_to_cpu(pcysta->v7.cycle_time.tavg[CXT_WL]); 1984 _chk_btc_err(rtwdev, BTC_DCNT_WL_SLOT_DRIFT, val16); 1985 1986 /* Check Leak-AP */ 1987 val1 = le32_to_cpu(pcysta->v7.leak_slot.cnt_rximr) * 1988 BTC_LEAK_AP_TH; 1989 val2 = le16_to_cpu(pcysta->v7.slot_cnt[CXST_LK]); 1990 1991 val16 = le16_to_cpu(pcysta->v7.cycles); 1992 if (dm->tdma_now.rxflctrl && 1993 val16 >= BTC_CYSTA_CHK_PERIOD && val1 > val2) 1994 dm->leak_ap = 1; 1995 } else if (dm->tdma_now.ext_ctrl == CXECTL_EXT) { 1996 val16 = le16_to_cpu(pcysta->v7.cycle_time.tavg[CXT_BT]); 1997 /* Check diff between real BT slot and EBT/E5G slot */ 1998 _chk_btc_err(rtwdev, BTC_DCNT_BT_SLOT_DRIFT, val16); 1999 2000 /* Check bt slot length for P2P mode*/ 2001 val1 = le16_to_cpu(pcysta->v7.a2dp_ept.cnt_timeout) * 2002 BTC_SLOT_REQ_TH; 2003 val2 = le16_to_cpu(pcysta->v7.a2dp_ept.cnt); 2004 2005 val16 = le16_to_cpu(pcysta->v7.cycles); 2006 if (val16 >= BTC_CYSTA_CHK_PERIOD && val1 > val2) 2007 dm->slot_req_more = 1; 2008 else if (bt->link_info.status.map.connect == 0) 2009 dm->slot_req_more = 0; 2010 } 2011 2012 _chk_btc_err(rtwdev, BTC_DCNT_E2G_HANG, 2013 le16_to_cpu(pcysta->v7.slot_cnt[CXST_E2G])); 2014 _chk_btc_err(rtwdev, BTC_DCNT_W1_HANG, 2015 le16_to_cpu(pcysta->v7.slot_cnt[CXST_W1])); 2016 _chk_btc_err(rtwdev, BTC_DCNT_B1_HANG, 2017 le16_to_cpu(pcysta->v7.slot_cnt[CXST_B1])); 2018 2019 /* "BT_SLOT_FLOOD" error-check MUST before "CYCLE_HANG" */ 2020 _chk_btc_err(rtwdev, BTC_DCNT_BT_SLOT_FLOOD, 2021 le16_to_cpu(pcysta->v7.cycles)); 2022 _chk_btc_err(rtwdev, BTC_DCNT_CYCLE_HANG, 2023 le16_to_cpu(pcysta->v7.cycles)); 2024 } else { 2025 goto err; 2026 } 2027 break; 2028 case BTC_RPT_TYPE_MREG: 2029 if (ver->fcxmreg == 7) 2030 break; 2031 _get_reg_status(rtwdev, BTC_CSTATUS_BB_GNT_MUX_MON, &val); 2032 if (dm->wl_btg_rx == BTC_BTGCTRL_BB_GNT_FWCTRL) 2033 dm->wl_btg_rx_rb = BTC_BTGCTRL_BB_GNT_FWCTRL; 2034 else 2035 dm->wl_btg_rx_rb = val; 2036 2037 _get_reg_status(rtwdev, BTC_CSTATUS_BB_PRE_AGC_MON, &val); 2038 if (dm->wl_pre_agc == BTC_PREAGC_BB_FWCTRL) 2039 dm->wl_pre_agc_rb = BTC_PREAGC_BB_FWCTRL; 2040 else 2041 dm->wl_pre_agc_rb = val; 2042 break; 2043 case BTC_RPT_TYPE_BT_VER: 2044 case BTC_RPT_TYPE_BT_SCAN: 2045 case BTC_RPT_TYPE_BT_AFH: 2046 case BTC_RPT_TYPE_BT_DEVICE: 2047 _update_bt_report(rtwdev, rpt_type, pfinfo); 2048 break; 2049 } 2050 return (rpt_len + BTC_RPT_HDR_SIZE); 2051 2052 err: 2053 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2054 "[BTC], %s(): Undefined version for type=%d\n", __func__, rpt_type); 2055 return 0; 2056 } 2057 2058 static void _parse_btc_report(struct rtw89_dev *rtwdev, 2059 struct rtw89_btc_btf_fwinfo *pfwinfo, 2060 u8 *pbuf, u32 buf_len) 2061 { 2062 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 2063 struct rtw89_btc_prpt *btc_prpt = NULL; 2064 u32 index = 0, rpt_len = 0; 2065 2066 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2067 "[BTC], %s(): buf_len:%d\n", 2068 __func__, buf_len); 2069 2070 while (pbuf) { 2071 btc_prpt = (struct rtw89_btc_prpt *)&pbuf[index]; 2072 if (index + 2 >= ver->info_buf) 2073 break; 2074 /* At least 3 bytes: type(1) & len(2) */ 2075 rpt_len = le16_to_cpu(btc_prpt->len); 2076 if ((index + rpt_len + BTC_RPT_HDR_SIZE) > buf_len) 2077 break; 2078 2079 rpt_len = _chk_btc_report(rtwdev, pfwinfo, pbuf, index); 2080 if (!rpt_len) 2081 break; 2082 index += rpt_len; 2083 } 2084 } 2085 2086 #define BTC_TLV_HDR_LEN 2 2087 #define BTC_TLV_HDR_LEN_V7 3 2088 2089 static void _append_tdma(struct rtw89_dev *rtwdev) 2090 { 2091 struct rtw89_btc *btc = &rtwdev->btc; 2092 const struct rtw89_btc_ver *ver = btc->ver; 2093 struct rtw89_btc_dm *dm = &btc->dm; 2094 struct rtw89_btc_btf_tlv *tlv; 2095 struct rtw89_btc_btf_tlv_v7 *tlv_v7; 2096 struct rtw89_btc_fbtc_tdma *v; 2097 struct rtw89_btc_fbtc_tdma_v3 *v3; 2098 u16 len = btc->policy_len; 2099 2100 if (!btc->update_policy_force && 2101 !memcmp(&dm->tdma, &dm->tdma_now, sizeof(dm->tdma))) { 2102 rtw89_debug(rtwdev, 2103 RTW89_DBG_BTC, "[BTC], %s(): tdma no change!\n", 2104 __func__); 2105 return; 2106 } 2107 2108 tlv = (struct rtw89_btc_btf_tlv *)&btc->policy[len]; 2109 tlv->type = CXPOLICY_TDMA; 2110 if (ver->fcxtdma == 1) { 2111 v = (struct rtw89_btc_fbtc_tdma *)&tlv->val[0]; 2112 tlv->len = sizeof(*v); 2113 *v = dm->tdma; 2114 btc->policy_len += BTC_TLV_HDR_LEN + sizeof(*v); 2115 } else if (ver->fcxtdma == 7) { 2116 tlv_v7 = (struct rtw89_btc_btf_tlv_v7 *)&btc->policy[len]; 2117 tlv_v7->len = sizeof(dm->tdma); 2118 tlv_v7->ver = ver->fcxtdma; 2119 tlv_v7->type = CXPOLICY_TDMA; 2120 memcpy(tlv_v7->val, &dm->tdma, tlv_v7->len); 2121 btc->policy_len += BTC_TLV_HDR_LEN_V7 + tlv_v7->len; 2122 } else { 2123 tlv->len = sizeof(*v3); 2124 v3 = (struct rtw89_btc_fbtc_tdma_v3 *)&tlv->val[0]; 2125 v3->fver = ver->fcxtdma; 2126 v3->tdma = dm->tdma; 2127 btc->policy_len += BTC_TLV_HDR_LEN + sizeof(*v3); 2128 } 2129 2130 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2131 "[BTC], %s(): type:%d, rxflctrl=%d, txpause=%d, wtgle_n=%d, leak_n=%d, ext_ctrl=%d\n", 2132 __func__, dm->tdma.type, dm->tdma.rxflctrl, 2133 dm->tdma.txpause, dm->tdma.wtgle_n, dm->tdma.leak_n, 2134 dm->tdma.ext_ctrl); 2135 } 2136 2137 static void _append_slot_v1(struct rtw89_dev *rtwdev) 2138 { 2139 struct rtw89_btc *btc = &rtwdev->btc; 2140 struct rtw89_btc_dm *dm = &btc->dm; 2141 struct rtw89_btc_btf_tlv *tlv = NULL; 2142 struct btc_fbtc_1slot *v = NULL; 2143 u16 len = 0; 2144 u8 i, cnt = 0; 2145 2146 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2147 "[BTC], %s(): A:btc->policy_len = %d\n", 2148 __func__, btc->policy_len); 2149 2150 for (i = 0; i < CXST_MAX; i++) { 2151 if (!btc->update_policy_force && 2152 !memcmp(&dm->slot.v1[i], &dm->slot_now.v1[i], 2153 sizeof(dm->slot.v1[i]))) 2154 continue; 2155 2156 len = btc->policy_len; 2157 2158 tlv = (struct rtw89_btc_btf_tlv *)&btc->policy[len]; 2159 v = (struct btc_fbtc_1slot *)&tlv->val[0]; 2160 tlv->type = CXPOLICY_SLOT; 2161 tlv->len = sizeof(*v); 2162 2163 v->fver = btc->ver->fcxslots; 2164 v->sid = i; 2165 v->slot = dm->slot.v1[i]; 2166 2167 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2168 "[BTC], %s(): slot-%d: dur=%d, table=0x%08x, type=%d\n", 2169 __func__, i, dm->slot.v1[i].dur, dm->slot.v1[i].cxtbl, 2170 dm->slot.v1[i].cxtype); 2171 cnt++; 2172 2173 btc->policy_len += BTC_TLV_HDR_LEN + sizeof(*v); 2174 } 2175 2176 if (cnt > 0) 2177 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2178 "[BTC], %s(): slot update (cnt=%d)!!\n", 2179 __func__, cnt); 2180 } 2181 2182 static void _append_slot_v7(struct rtw89_dev *rtwdev) 2183 { 2184 struct rtw89_btc_btf_tlv_v7 *tlv = NULL; 2185 struct rtw89_btc *btc = &rtwdev->btc; 2186 struct rtw89_btc_dm *dm = &btc->dm; 2187 u8 i, cnt = 0; 2188 u16 len; 2189 2190 for (i = 0; i < CXST_MAX; i++) { 2191 if (!btc->update_policy_force && 2192 !memcmp(&dm->slot.v7[i], &dm->slot_now.v7[i], 2193 sizeof(dm->slot.v7[i]))) 2194 continue; 2195 2196 len = btc->policy_len; 2197 2198 if (!tlv) { 2199 if ((len + BTC_TLV_HDR_LEN_V7) > RTW89_BTC_POLICY_MAXLEN) { 2200 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2201 "[BTC], %s(): buff overflow!\n", __func__); 2202 break; 2203 } 2204 2205 tlv = (struct rtw89_btc_btf_tlv_v7 *)&btc->policy[len]; 2206 tlv->type = CXPOLICY_SLOT; 2207 tlv->ver = btc->ver->fcxslots; 2208 tlv->len = sizeof(dm->slot.v7[0]) + BTC_TLV_SLOT_ID_LEN_V7; 2209 len += BTC_TLV_HDR_LEN_V7; 2210 } 2211 2212 if ((len + (u16)tlv->len) > RTW89_BTC_POLICY_MAXLEN) { 2213 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2214 "[BTC], %s(): buff overflow!\n", __func__); 2215 break; 2216 } 2217 2218 btc->policy[len] = i; /* slot-id */ 2219 memcpy(&btc->policy[len + 1], &dm->slot.v7[i], 2220 sizeof(dm->slot.v7[0])); 2221 len += tlv->len; 2222 2223 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2224 "[BTC], %s: policy_len=%d, slot-%d: dur=%d, type=%d, table=0x%08x\n", 2225 __func__, btc->policy_len, i, dm->slot.v7[i].dur, 2226 dm->slot.v7[i].cxtype, dm->slot.v7[i].cxtbl); 2227 cnt++; 2228 btc->policy_len = len; /* update total length */ 2229 } 2230 2231 if (cnt > 0) 2232 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2233 "[BTC], %s: slot update (cnt=%d, len=%d)!!\n", 2234 __func__, cnt, btc->policy_len); 2235 } 2236 2237 static void _append_slot(struct rtw89_dev *rtwdev) 2238 { 2239 struct rtw89_btc *btc = &rtwdev->btc; 2240 2241 if (btc->ver->fcxslots == 7) 2242 _append_slot_v7(rtwdev); 2243 else 2244 _append_slot_v1(rtwdev); 2245 } 2246 2247 static u32 rtw89_btc_fw_rpt_ver(struct rtw89_dev *rtwdev, u32 rpt_map) 2248 { 2249 struct rtw89_btc *btc = &rtwdev->btc; 2250 const struct rtw89_btc_ver *ver = btc->ver; 2251 u32 bit_map = 0; 2252 2253 switch (rpt_map) { 2254 case RPT_EN_TDMA: 2255 bit_map = BIT(0); 2256 break; 2257 case RPT_EN_CYCLE: 2258 bit_map = BIT(1); 2259 break; 2260 case RPT_EN_MREG: 2261 bit_map = BIT(2); 2262 break; 2263 case RPT_EN_BT_VER_INFO: 2264 bit_map = BIT(3); 2265 break; 2266 case RPT_EN_BT_SCAN_INFO: 2267 bit_map = BIT(4); 2268 break; 2269 case RPT_EN_BT_DEVICE_INFO: 2270 switch (ver->frptmap) { 2271 case 0: 2272 case 1: 2273 case 2: 2274 bit_map = BIT(6); 2275 break; 2276 case 3: 2277 bit_map = BIT(5); 2278 break; 2279 default: 2280 break; 2281 } 2282 break; 2283 case RPT_EN_BT_AFH_MAP: 2284 switch (ver->frptmap) { 2285 case 0: 2286 case 1: 2287 case 2: 2288 bit_map = BIT(5); 2289 break; 2290 case 3: 2291 bit_map = BIT(6); 2292 break; 2293 default: 2294 break; 2295 } 2296 break; 2297 case RPT_EN_BT_AFH_MAP_LE: 2298 switch (ver->frptmap) { 2299 case 2: 2300 bit_map = BIT(8); 2301 break; 2302 case 3: 2303 bit_map = BIT(7); 2304 break; 2305 default: 2306 break; 2307 } 2308 break; 2309 case RPT_EN_FW_STEP_INFO: 2310 switch (ver->frptmap) { 2311 case 1: 2312 case 2: 2313 bit_map = BIT(7); 2314 break; 2315 case 3: 2316 bit_map = BIT(8); 2317 break; 2318 default: 2319 break; 2320 } 2321 break; 2322 case RPT_EN_TEST: 2323 bit_map = BIT(31); 2324 break; 2325 case RPT_EN_WL_ALL: 2326 switch (ver->frptmap) { 2327 case 0: 2328 case 1: 2329 case 2: 2330 bit_map = GENMASK(2, 0); 2331 break; 2332 case 3: 2333 bit_map = GENMASK(2, 0) | BIT(8); 2334 break; 2335 default: 2336 break; 2337 } 2338 break; 2339 case RPT_EN_BT_ALL: 2340 switch (ver->frptmap) { 2341 case 0: 2342 case 1: 2343 bit_map = GENMASK(6, 3); 2344 break; 2345 case 2: 2346 bit_map = GENMASK(6, 3) | BIT(8); 2347 break; 2348 case 3: 2349 bit_map = GENMASK(7, 3); 2350 break; 2351 default: 2352 break; 2353 } 2354 break; 2355 case RPT_EN_ALL: 2356 switch (ver->frptmap) { 2357 case 0: 2358 bit_map = GENMASK(6, 0); 2359 break; 2360 case 1: 2361 bit_map = GENMASK(7, 0); 2362 break; 2363 case 2: 2364 case 3: 2365 bit_map = GENMASK(8, 0); 2366 break; 2367 default: 2368 break; 2369 } 2370 break; 2371 case RPT_EN_MONITER: 2372 switch (ver->frptmap) { 2373 case 0: 2374 case 1: 2375 bit_map = GENMASK(6, 2); 2376 break; 2377 case 2: 2378 bit_map = GENMASK(6, 2) | BIT(8); 2379 break; 2380 case 3: 2381 bit_map = GENMASK(8, 2); 2382 break; 2383 default: 2384 break; 2385 } 2386 break; 2387 } 2388 2389 return bit_map; 2390 } 2391 2392 static void rtw89_btc_fw_set_slots(struct rtw89_dev *rtwdev) 2393 { 2394 struct rtw89_btc *btc = &rtwdev->btc; 2395 const struct rtw89_btc_ver *ver = btc->ver; 2396 struct rtw89_btc_btf_tlv_v7 *tlv_v7 = NULL; 2397 struct rtw89_btc_btf_set_slot_table *tbl; 2398 struct rtw89_btc_dm *dm = &btc->dm; 2399 u16 n, len; 2400 2401 if (ver->fcxslots == 7) { 2402 len = sizeof(*tlv_v7) + sizeof(dm->slot.v7); 2403 tlv_v7 = kmalloc(len, GFP_KERNEL); 2404 if (!tlv_v7) 2405 return; 2406 2407 tlv_v7->type = SET_SLOT_TABLE; 2408 tlv_v7->ver = ver->fcxslots; 2409 tlv_v7->len = ARRAY_SIZE(dm->slot.v7); 2410 memcpy(tlv_v7->val, dm->slot.v7, sizeof(dm->slot.v7)); 2411 2412 _send_fw_cmd(rtwdev, BTFC_SET, SET_SLOT_TABLE, (u8 *)tlv_v7, len); 2413 2414 kfree(tlv_v7); 2415 } else { 2416 n = struct_size(tbl, tbls, CXST_MAX); 2417 tbl = kmalloc(n, GFP_KERNEL); 2418 if (!tbl) 2419 return; 2420 2421 tbl->fver = BTF_SET_SLOT_TABLE_VER; 2422 tbl->tbl_num = CXST_MAX; 2423 memcpy(tbl->tbls, dm->slot.v1, flex_array_size(tbl, tbls, CXST_MAX)); 2424 2425 _send_fw_cmd(rtwdev, BTFC_SET, SET_SLOT_TABLE, tbl, n); 2426 2427 kfree(tbl); 2428 } 2429 } 2430 2431 static void rtw89_btc_fw_en_rpt(struct rtw89_dev *rtwdev, 2432 u32 rpt_map, bool rpt_state) 2433 { 2434 struct rtw89_btc *btc = &rtwdev->btc; 2435 struct rtw89_btc_wl_smap *wl_smap = &btc->cx.wl.status.map; 2436 struct rtw89_btc_btf_fwinfo *fwinfo = &btc->fwinfo; 2437 union rtw89_fbtc_rtp_ctrl r; 2438 u32 val, bit_map; 2439 int ret; 2440 2441 if ((wl_smap->rf_off || wl_smap->lps != BTC_LPS_OFF) && rpt_state != 0) 2442 return; 2443 2444 bit_map = rtw89_btc_fw_rpt_ver(rtwdev, rpt_map); 2445 2446 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2447 "[BTC], %s(): rpt_map=%x, rpt_state=%x\n", 2448 __func__, rpt_map, rpt_state); 2449 2450 if (rpt_state) 2451 val = fwinfo->rpt_en_map | bit_map; 2452 else 2453 val = fwinfo->rpt_en_map & ~bit_map; 2454 2455 if (val == fwinfo->rpt_en_map) 2456 return; 2457 2458 if (btc->ver->fcxbtcrpt == 7 || btc->ver->fcxbtcrpt == 8) { 2459 r.v8.type = SET_REPORT_EN; 2460 r.v8.fver = btc->ver->fcxbtcrpt; 2461 r.v8.len = sizeof(r.v8.map); 2462 r.v8.map = cpu_to_le32(val); 2463 ret = _send_fw_cmd(rtwdev, BTFC_SET, SET_REPORT_EN, &r.v8, 2464 sizeof(r.v8)); 2465 } else { 2466 if (btc->ver->fcxbtcrpt == 105) 2467 r.v1.fver = 5; 2468 else 2469 r.v1.fver = btc->ver->fcxbtcrpt; 2470 r.v1.enable = cpu_to_le32(val); 2471 r.v1.para = cpu_to_le32(rpt_state); 2472 ret = _send_fw_cmd(rtwdev, BTFC_SET, SET_REPORT_EN, &r.v1, 2473 sizeof(r.v1)); 2474 } 2475 2476 if (!ret) 2477 fwinfo->rpt_en_map = val; 2478 } 2479 2480 static void btc_fw_set_monreg(struct rtw89_dev *rtwdev) 2481 { 2482 const struct rtw89_chip_info *chip = rtwdev->chip; 2483 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 2484 struct rtw89_btc_btf_set_mon_reg_v1 *v1 = NULL; 2485 struct rtw89_btc_btf_set_mon_reg_v7 *v7 = NULL; 2486 u8 i, n, ulen, cxmreg_max; 2487 u16 sz = 0; 2488 2489 n = chip->mon_reg_num; 2490 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2491 "[BTC], %s(): mon_reg_num=%d\n", __func__, n); 2492 2493 if (ver->fcxmreg == 1) 2494 cxmreg_max = CXMREG_MAX; 2495 else 2496 cxmreg_max = CXMREG_MAX_V2; 2497 2498 if (n > cxmreg_max) { 2499 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2500 "[BTC], %s(): mon reg count %d > %d\n", 2501 __func__, n, cxmreg_max); 2502 return; 2503 } 2504 2505 ulen = sizeof(struct rtw89_btc_fbtc_mreg); 2506 2507 if (ver->fcxmreg == 7) { 2508 sz = struct_size(v7, regs, n); 2509 v7 = kmalloc(sz, GFP_KERNEL); 2510 v7->type = RPT_EN_MREG; 2511 v7->fver = ver->fcxmreg; 2512 v7->len = n; 2513 for (i = 0; i < n; i++) { 2514 v7->regs[i].type = chip->mon_reg[i].type; 2515 v7->regs[i].bytes = chip->mon_reg[i].bytes; 2516 v7->regs[i].offset = chip->mon_reg[i].offset; 2517 } 2518 2519 _send_fw_cmd(rtwdev, BTFC_SET, SET_MREG_TABLE, v7, sz); 2520 kfree(v7); 2521 } else { 2522 sz = struct_size(v1, regs, n); 2523 v1 = kmalloc(sz, GFP_KERNEL); 2524 v1->fver = ver->fcxmreg; 2525 v1->reg_num = n; 2526 memcpy(v1->regs, chip->mon_reg, flex_array_size(v1, regs, n)); 2527 2528 _send_fw_cmd(rtwdev, BTFC_SET, SET_MREG_TABLE, v1, sz); 2529 kfree(v1); 2530 } 2531 2532 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2533 "[BTC], %s(): sz=%d ulen=%d n=%d\n", 2534 __func__, sz, ulen, n); 2535 2536 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_MREG, 1); 2537 } 2538 2539 static void _update_dm_step(struct rtw89_dev *rtwdev, 2540 enum btc_reason_and_action reason_or_action) 2541 { 2542 struct rtw89_btc *btc = &rtwdev->btc; 2543 struct rtw89_btc_dm *dm = &btc->dm; 2544 2545 /* use ring-structure to store dm step */ 2546 dm->dm_step.step[dm->dm_step.step_pos] = reason_or_action; 2547 dm->dm_step.step_pos++; 2548 2549 if (dm->dm_step.step_pos >= ARRAY_SIZE(dm->dm_step.step)) { 2550 dm->dm_step.step_pos = 0; 2551 dm->dm_step.step_ov = true; 2552 } 2553 } 2554 2555 static void _fw_set_policy(struct rtw89_dev *rtwdev, u16 policy_type, 2556 enum btc_reason_and_action action) 2557 { 2558 struct rtw89_btc *btc = &rtwdev->btc; 2559 struct rtw89_btc_dm *dm = &btc->dm; 2560 int ret; 2561 2562 dm->run_action = action; 2563 2564 _update_dm_step(rtwdev, action | BTC_ACT_EXT_BIT); 2565 _update_dm_step(rtwdev, policy_type | BTC_POLICY_EXT_BIT); 2566 2567 btc->policy_len = 0; 2568 btc->policy_type = policy_type; 2569 2570 _append_tdma(rtwdev); 2571 _append_slot(rtwdev); 2572 2573 if (btc->policy_len == 0 || btc->policy_len > RTW89_BTC_POLICY_MAXLEN) 2574 return; 2575 2576 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2577 "[BTC], %s(): action = %d -> policy type/len: 0x%04x/%d\n", 2578 __func__, action, policy_type, btc->policy_len); 2579 2580 if (dm->tdma.rxflctrl == CXFLC_NULLP || 2581 dm->tdma.rxflctrl == CXFLC_QOSNULL) 2582 btc->lps = 1; 2583 else 2584 btc->lps = 0; 2585 2586 if (btc->lps == 1) 2587 rtw89_set_coex_ctrl_lps(rtwdev, btc->lps); 2588 2589 ret = _send_fw_cmd(rtwdev, BTFC_SET, SET_CX_POLICY, 2590 btc->policy, btc->policy_len); 2591 if (!ret) { 2592 memcpy(&dm->tdma_now, &dm->tdma, sizeof(dm->tdma_now)); 2593 if (btc->ver->fcxslots == 7) 2594 memcpy(&dm->slot_now.v7, &dm->slot.v7, sizeof(dm->slot_now.v7)); 2595 else 2596 memcpy(&dm->slot_now.v1, &dm->slot.v1, sizeof(dm->slot_now.v1)); 2597 } 2598 2599 if (btc->update_policy_force) 2600 btc->update_policy_force = false; 2601 2602 if (btc->lps == 0) 2603 rtw89_set_coex_ctrl_lps(rtwdev, btc->lps); 2604 } 2605 2606 static void _fw_set_drv_info(struct rtw89_dev *rtwdev, u8 type) 2607 { 2608 struct rtw89_btc *btc = &rtwdev->btc; 2609 const struct rtw89_btc_ver *ver = btc->ver; 2610 struct rtw89_btc_dm *dm = &btc->dm; 2611 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 2612 struct rtw89_btc_rf_trx_para rf_para = dm->rf_trx_para; 2613 2614 switch (type) { 2615 case CXDRVINFO_INIT: 2616 if (ver->fcxinit == 7) 2617 rtw89_fw_h2c_cxdrv_init_v7(rtwdev, type); 2618 else 2619 rtw89_fw_h2c_cxdrv_init(rtwdev, type); 2620 break; 2621 case CXDRVINFO_ROLE: 2622 if (ver->fwlrole == 0) 2623 rtw89_fw_h2c_cxdrv_role(rtwdev, type); 2624 else if (ver->fwlrole == 1) 2625 rtw89_fw_h2c_cxdrv_role_v1(rtwdev, type); 2626 else if (ver->fwlrole == 2) 2627 rtw89_fw_h2c_cxdrv_role_v2(rtwdev, type); 2628 else if (ver->fwlrole == 7) 2629 rtw89_fw_h2c_cxdrv_role_v7(rtwdev, type); 2630 else if (ver->fwlrole == 8) 2631 rtw89_fw_h2c_cxdrv_role_v8(rtwdev, type); 2632 break; 2633 case CXDRVINFO_CTRL: 2634 if (ver->drvinfo_type == 1) 2635 type = 2; 2636 2637 if (ver->fcxctrl == 7) 2638 rtw89_fw_h2c_cxdrv_ctrl_v7(rtwdev, type); 2639 else 2640 rtw89_fw_h2c_cxdrv_ctrl(rtwdev, type); 2641 break; 2642 case CXDRVINFO_TRX: 2643 if (ver->drvinfo_type == 1) 2644 type = 3; 2645 2646 dm->trx_info.tx_power = u32_get_bits(rf_para.wl_tx_power, 2647 RTW89_BTC_WL_DEF_TX_PWR); 2648 dm->trx_info.rx_gain = u32_get_bits(rf_para.wl_rx_gain, 2649 RTW89_BTC_WL_DEF_TX_PWR); 2650 dm->trx_info.bt_tx_power = u32_get_bits(rf_para.bt_tx_power, 2651 RTW89_BTC_WL_DEF_TX_PWR); 2652 dm->trx_info.bt_rx_gain = u32_get_bits(rf_para.bt_rx_gain, 2653 RTW89_BTC_WL_DEF_TX_PWR); 2654 dm->trx_info.cn = wl->cn_report; 2655 dm->trx_info.nhm = wl->nhm.pwr; 2656 rtw89_fw_h2c_cxdrv_trx(rtwdev, type); 2657 break; 2658 case CXDRVINFO_RFK: 2659 if (ver->drvinfo_type == 1) 2660 return; 2661 2662 rtw89_fw_h2c_cxdrv_rfk(rtwdev, type); 2663 break; 2664 case CXDRVINFO_TXPWR: 2665 case CXDRVINFO_FDDT: 2666 case CXDRVINFO_MLO: 2667 case CXDRVINFO_OSI: 2668 default: 2669 break; 2670 } 2671 } 2672 2673 static 2674 void btc_fw_event(struct rtw89_dev *rtwdev, u8 evt_id, void *data, u32 len) 2675 { 2676 struct rtw89_btc *btc = &rtwdev->btc; 2677 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 2678 2679 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2680 "[BTC], %s(): evt_id:%d len:%d\n", 2681 __func__, evt_id, len); 2682 2683 if (!len || !data) 2684 return; 2685 2686 switch (evt_id) { 2687 case BTF_EVNT_RPT: 2688 _parse_btc_report(rtwdev, pfwinfo, data, len); 2689 break; 2690 default: 2691 break; 2692 } 2693 } 2694 2695 static void _set_gnt(struct rtw89_dev *rtwdev, u8 phy_map, u8 wl_state, u8 bt_state) 2696 { 2697 struct rtw89_btc *btc = &rtwdev->btc; 2698 struct rtw89_btc_dm *dm = &btc->dm; 2699 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 2700 u8 i; 2701 2702 if (phy_map > BTC_PHY_ALL) 2703 return; 2704 2705 for (i = 0; i < RTW89_PHY_MAX; i++) { 2706 if (!(phy_map & BIT(i))) 2707 continue; 2708 2709 switch (wl_state) { 2710 case BTC_GNT_HW: 2711 g[i].gnt_wl_sw_en = 0; 2712 g[i].gnt_wl = 0; 2713 break; 2714 case BTC_GNT_SW_LO: 2715 g[i].gnt_wl_sw_en = 1; 2716 g[i].gnt_wl = 0; 2717 break; 2718 case BTC_GNT_SW_HI: 2719 g[i].gnt_wl_sw_en = 1; 2720 g[i].gnt_wl = 1; 2721 break; 2722 } 2723 2724 switch (bt_state) { 2725 case BTC_GNT_HW: 2726 g[i].gnt_bt_sw_en = 0; 2727 g[i].gnt_bt = 0; 2728 break; 2729 case BTC_GNT_SW_LO: 2730 g[i].gnt_bt_sw_en = 1; 2731 g[i].gnt_bt = 0; 2732 break; 2733 case BTC_GNT_SW_HI: 2734 g[i].gnt_bt_sw_en = 1; 2735 g[i].gnt_bt = 1; 2736 break; 2737 } 2738 } 2739 2740 rtw89_chip_mac_cfg_gnt(rtwdev, &dm->gnt); 2741 } 2742 2743 static void _set_gnt_v1(struct rtw89_dev *rtwdev, u8 phy_map, 2744 u8 wl_state, u8 bt_state, u8 wlact_state) 2745 { 2746 struct rtw89_btc *btc = &rtwdev->btc; 2747 struct rtw89_btc_dm *dm = &btc->dm; 2748 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 2749 u8 i, bt_idx = dm->bt_select + 1; 2750 2751 if (phy_map > BTC_PHY_ALL) 2752 return; 2753 2754 for (i = 0; i < RTW89_PHY_MAX; i++) { 2755 if (!(phy_map & BIT(i))) 2756 continue; 2757 2758 switch (wl_state) { 2759 case BTC_GNT_HW: 2760 g[i].gnt_wl_sw_en = 0; 2761 g[i].gnt_wl = 0; 2762 break; 2763 case BTC_GNT_SW_LO: 2764 g[i].gnt_wl_sw_en = 1; 2765 g[i].gnt_wl = 0; 2766 break; 2767 case BTC_GNT_SW_HI: 2768 g[i].gnt_wl_sw_en = 1; 2769 g[i].gnt_wl = 1; 2770 break; 2771 } 2772 2773 switch (bt_state) { 2774 case BTC_GNT_HW: 2775 g[i].gnt_bt_sw_en = 0; 2776 g[i].gnt_bt = 0; 2777 break; 2778 case BTC_GNT_SW_LO: 2779 g[i].gnt_bt_sw_en = 1; 2780 g[i].gnt_bt = 0; 2781 break; 2782 case BTC_GNT_SW_HI: 2783 g[i].gnt_bt_sw_en = 1; 2784 g[i].gnt_bt = 1; 2785 break; 2786 } 2787 } 2788 2789 if (rtwdev->chip->para_ver & BTC_FEAT_WLAN_ACT_MUX) { 2790 for (i = 0; i < 2; i++) { 2791 if (!(bt_idx & BIT(i))) 2792 continue; 2793 2794 switch (wlact_state) { 2795 case BTC_WLACT_HW: 2796 dm->gnt.bt[i].wlan_act_en = 0; 2797 dm->gnt.bt[i].wlan_act = 0; 2798 break; 2799 case BTC_WLACT_SW_LO: 2800 dm->gnt.bt[i].wlan_act_en = 1; 2801 dm->gnt.bt[i].wlan_act = 0; 2802 break; 2803 case BTC_WLACT_SW_HI: 2804 dm->gnt.bt[i].wlan_act_en = 1; 2805 dm->gnt.bt[i].wlan_act = 1; 2806 break; 2807 } 2808 } 2809 } 2810 rtw89_mac_cfg_gnt_v2(rtwdev, &dm->gnt); 2811 } 2812 2813 #define BTC_TDMA_WLROLE_MAX 3 2814 2815 static void _set_bt_ignore_wlan_act(struct rtw89_dev *rtwdev, u8 enable) 2816 { 2817 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2818 "[BTC], %s(): set bt %s wlan_act\n", __func__, 2819 enable ? "ignore" : "do not ignore"); 2820 2821 _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_IGNORE_WLAN_ACT, &enable, 1); 2822 } 2823 2824 #define WL_TX_POWER_NO_BTC_CTRL GENMASK(31, 0) 2825 #define WL_TX_POWER_ALL_TIME GENMASK(15, 0) 2826 #define WL_TX_POWER_WITH_BT GENMASK(31, 16) 2827 #define WL_TX_POWER_INT_PART GENMASK(8, 2) 2828 #define WL_TX_POWER_FRA_PART GENMASK(1, 0) 2829 #define B_BTC_WL_TX_POWER_SIGN BIT(7) 2830 #define B_TSSI_WL_TX_POWER_SIGN BIT(8) 2831 2832 static void _set_wl_tx_power(struct rtw89_dev *rtwdev, u32 level) 2833 { 2834 const struct rtw89_chip_info *chip = rtwdev->chip; 2835 struct rtw89_btc *btc = &rtwdev->btc; 2836 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 2837 u32 pwr_val; 2838 2839 if (wl->rf_para.tx_pwr_freerun == level) 2840 return; 2841 2842 wl->rf_para.tx_pwr_freerun = level; 2843 btc->dm.rf_trx_para.wl_tx_power = level; 2844 2845 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2846 "[BTC], %s(): level = %d\n", 2847 __func__, level); 2848 2849 if (level == RTW89_BTC_WL_DEF_TX_PWR) { 2850 pwr_val = WL_TX_POWER_NO_BTC_CTRL; 2851 } else { /* only apply "force tx power" */ 2852 pwr_val = FIELD_PREP(WL_TX_POWER_INT_PART, level); 2853 if (pwr_val > RTW89_BTC_WL_DEF_TX_PWR) 2854 pwr_val = RTW89_BTC_WL_DEF_TX_PWR; 2855 2856 if (level & B_BTC_WL_TX_POWER_SIGN) 2857 pwr_val |= B_TSSI_WL_TX_POWER_SIGN; 2858 pwr_val |= WL_TX_POWER_WITH_BT; 2859 } 2860 2861 chip->ops->btc_set_wl_txpwr_ctrl(rtwdev, pwr_val); 2862 } 2863 2864 static void _set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 2865 { 2866 const struct rtw89_chip_info *chip = rtwdev->chip; 2867 struct rtw89_btc *btc = &rtwdev->btc; 2868 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 2869 2870 if (wl->rf_para.rx_gain_freerun == level) 2871 return; 2872 2873 wl->rf_para.rx_gain_freerun = level; 2874 btc->dm.rf_trx_para.wl_rx_gain = level; 2875 2876 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2877 "[BTC], %s(): level = %d\n", 2878 __func__, level); 2879 2880 chip->ops->btc_set_wl_rx_gain(rtwdev, level); 2881 } 2882 2883 static void _set_bt_tx_power(struct rtw89_dev *rtwdev, u8 level) 2884 { 2885 struct rtw89_btc *btc = &rtwdev->btc; 2886 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 2887 int ret; 2888 u8 buf; 2889 2890 if (btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE] == 0) 2891 return; 2892 2893 if (bt->rf_para.tx_pwr_freerun == level) 2894 return; 2895 2896 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2897 "[BTC], %s(): level = %d\n", 2898 __func__, level); 2899 2900 buf = (s8)(-level); 2901 ret = _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_TX_PWR, &buf, 1); 2902 if (!ret) { 2903 bt->rf_para.tx_pwr_freerun = level; 2904 btc->dm.rf_trx_para.bt_tx_power = level; 2905 } 2906 } 2907 2908 #define BTC_BT_RX_NORMAL_LVL 7 2909 2910 static void _set_bt_rx_gain(struct rtw89_dev *rtwdev, u8 level) 2911 { 2912 struct rtw89_btc *btc = &rtwdev->btc; 2913 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 2914 2915 if (btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE] == 0) 2916 return; 2917 2918 if ((bt->rf_para.rx_gain_freerun == level || 2919 level > BTC_BT_RX_NORMAL_LVL) && 2920 (!rtwdev->chip->scbd || bt->lna_constrain == level)) 2921 return; 2922 2923 bt->rf_para.rx_gain_freerun = level; 2924 btc->dm.rf_trx_para.bt_rx_gain = level; 2925 2926 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2927 "[BTC], %s(): level = %d\n", 2928 __func__, level); 2929 2930 if (level == BTC_BT_RX_NORMAL_LVL) 2931 _write_scbd(rtwdev, BTC_WSCB_RXGAIN, false); 2932 else 2933 _write_scbd(rtwdev, BTC_WSCB_RXGAIN, true); 2934 2935 _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_LNA_CONSTRAIN, &level, sizeof(level)); 2936 } 2937 2938 static void _set_rf_trx_para(struct rtw89_dev *rtwdev) 2939 { 2940 const struct rtw89_chip_info *chip = rtwdev->chip; 2941 struct rtw89_btc *btc = &rtwdev->btc; 2942 const struct rtw89_btc_ver *ver = btc->ver; 2943 struct rtw89_btc_dm *dm = &btc->dm; 2944 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 2945 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 2946 struct rtw89_btc_bt_link_info *b = &bt->link_info; 2947 struct rtw89_btc_wl_smap *wl_smap = &wl->status.map; 2948 struct rtw89_btc_rf_trx_para para; 2949 u32 wl_stb_chg = 0; 2950 u8 level_id = 0, link_mode = 0, i, dbcc_2g_phy = 0; 2951 2952 if (ver->fwlrole == 0) { 2953 link_mode = wl->role_info.link_mode; 2954 for (i = 0; i < RTW89_PHY_MAX; i++) { 2955 if (wl->dbcc_info.real_band[i] == RTW89_BAND_2G) 2956 dbcc_2g_phy = i; 2957 } 2958 } else if (ver->fwlrole == 1) { 2959 link_mode = wl->role_info_v1.link_mode; 2960 dbcc_2g_phy = wl->role_info_v1.dbcc_2g_phy; 2961 } else if (ver->fwlrole == 2) { 2962 link_mode = wl->role_info_v2.link_mode; 2963 dbcc_2g_phy = wl->role_info_v2.dbcc_2g_phy; 2964 } 2965 2966 /* decide trx_para_level */ 2967 if (btc->ant_type == BTC_ANT_SHARED) { 2968 /* fix LNA2 + TIA gain not change by GNT_BT */ 2969 if ((btc->dm.wl_btg_rx && b->profile_cnt.now != 0) || 2970 dm->bt_only == 1) 2971 dm->trx_para_level = 1; /* for better BT ACI issue */ 2972 else 2973 dm->trx_para_level = 0; 2974 } else { /* non-shared antenna */ 2975 dm->trx_para_level = 5; 2976 /* modify trx_para if WK 2.4G-STA-DL + bt link */ 2977 if (b->profile_cnt.now != 0 && 2978 link_mode == BTC_WLINK_2G_STA && 2979 wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) { /* uplink */ 2980 if (wl->rssi_level == 4 && bt->rssi_level > 2) 2981 dm->trx_para_level = 6; 2982 else if (wl->rssi_level == 3 && bt->rssi_level > 3) 2983 dm->trx_para_level = 7; 2984 } 2985 } 2986 2987 level_id = dm->trx_para_level; 2988 if (level_id >= chip->rf_para_dlink_num || 2989 level_id >= chip->rf_para_ulink_num) { 2990 rtw89_debug(rtwdev, RTW89_DBG_BTC, 2991 "[BTC], %s(): invalid level_id: %d\n", 2992 __func__, level_id); 2993 return; 2994 } 2995 2996 if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) 2997 para = chip->rf_para_ulink[level_id]; 2998 else 2999 para = chip->rf_para_dlink[level_id]; 3000 3001 if (dm->fddt_train) { 3002 _set_wl_rx_gain(rtwdev, 1); 3003 _write_scbd(rtwdev, BTC_WSCB_RXGAIN, true); 3004 } else { 3005 _set_wl_tx_power(rtwdev, para.wl_tx_power); 3006 _set_wl_rx_gain(rtwdev, para.wl_rx_gain); 3007 _set_bt_tx_power(rtwdev, para.bt_tx_power); 3008 _set_bt_rx_gain(rtwdev, para.bt_rx_gain); 3009 } 3010 3011 if (!bt->enable.now || dm->wl_only || wl_smap->rf_off || 3012 wl_smap->lps == BTC_LPS_RF_OFF || 3013 link_mode == BTC_WLINK_5G || 3014 link_mode == BTC_WLINK_NOLINK || 3015 (rtwdev->dbcc_en && dbcc_2g_phy != RTW89_PHY_1)) 3016 wl_stb_chg = 0; 3017 else 3018 wl_stb_chg = 1; 3019 3020 if (wl_stb_chg != dm->wl_stb_chg) { 3021 dm->wl_stb_chg = wl_stb_chg; 3022 chip->ops->btc_wl_s1_standby(rtwdev, dm->wl_stb_chg); 3023 } 3024 } 3025 3026 static void _update_btc_state_map(struct rtw89_dev *rtwdev) 3027 { 3028 struct rtw89_btc *btc = &rtwdev->btc; 3029 struct rtw89_btc_cx *cx = &btc->cx; 3030 struct rtw89_btc_wl_info *wl = &cx->wl; 3031 struct rtw89_btc_bt_info *bt = &cx->bt; 3032 struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; 3033 3034 if (wl->status.map.connecting || wl->status.map._4way || 3035 wl->status.map.roaming || wl->status.map.dbccing) { 3036 cx->state_map = BTC_WLINKING; 3037 } else if (wl->status.map.scan) { /* wl scan */ 3038 if (bt_linfo->status.map.inq_pag) 3039 cx->state_map = BTC_WSCAN_BSCAN; 3040 else 3041 cx->state_map = BTC_WSCAN_BNOSCAN; 3042 } else if (wl->status.map.busy) { /* only busy */ 3043 if (bt_linfo->status.map.inq_pag) 3044 cx->state_map = BTC_WBUSY_BSCAN; 3045 else 3046 cx->state_map = BTC_WBUSY_BNOSCAN; 3047 } else { /* wl idle */ 3048 cx->state_map = BTC_WIDLE; 3049 } 3050 } 3051 3052 static void _set_bt_afh_info(struct rtw89_dev *rtwdev) 3053 { 3054 const struct rtw89_chip_info *chip = rtwdev->chip; 3055 struct rtw89_btc *btc = &rtwdev->btc; 3056 const struct rtw89_btc_ver *ver = btc->ver; 3057 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 3058 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 3059 struct rtw89_btc_bt_link_info *b = &bt->link_info; 3060 struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; 3061 struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; 3062 struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; 3063 struct rtw89_btc_wl_role_info_v7 *wl_rinfo_v7 = &wl->role_info_v7; 3064 struct rtw89_btc_wl_role_info_v8 *wl_rinfo_v8 = &wl->role_info_v8; 3065 struct rtw89_btc_wl_active_role *r; 3066 struct rtw89_btc_wl_active_role_v1 *r1; 3067 struct rtw89_btc_wl_active_role_v2 *r2; 3068 struct rtw89_btc_wl_active_role_v7 *r7; 3069 struct rtw89_btc_wl_rlink *rlink; 3070 u8 en = 0, i, ch = 0, bw = 0; 3071 u8 mode, connect_cnt; 3072 3073 if (btc->manual_ctrl || wl->status.map.scan) 3074 return; 3075 3076 if (ver->fwlrole == 0) { 3077 mode = wl_rinfo->link_mode; 3078 connect_cnt = wl_rinfo->connect_cnt; 3079 } else if (ver->fwlrole == 1) { 3080 mode = wl_rinfo_v1->link_mode; 3081 connect_cnt = wl_rinfo_v1->connect_cnt; 3082 } else if (ver->fwlrole == 2) { 3083 mode = wl_rinfo_v2->link_mode; 3084 connect_cnt = wl_rinfo_v2->connect_cnt; 3085 } else if (ver->fwlrole == 7) { 3086 mode = wl_rinfo_v7->link_mode; 3087 connect_cnt = wl_rinfo_v7->connect_cnt; 3088 } else if (ver->fwlrole == 8) { 3089 mode = wl_rinfo_v8->link_mode; 3090 connect_cnt = wl_rinfo_v8->connect_cnt; 3091 } else { 3092 return; 3093 } 3094 3095 if (wl->status.map.rf_off || bt->whql_test || 3096 mode == BTC_WLINK_NOLINK || mode == BTC_WLINK_5G || 3097 connect_cnt > BTC_TDMA_WLROLE_MAX) { 3098 en = false; 3099 } else if (mode == BTC_WLINK_2G_MCC || mode == BTC_WLINK_2G_SCC) { 3100 en = true; 3101 /* get p2p channel */ 3102 for (i = 0; i < RTW89_PORT_NUM; i++) { 3103 r = &wl_rinfo->active_role[i]; 3104 r1 = &wl_rinfo_v1->active_role_v1[i]; 3105 r2 = &wl_rinfo_v2->active_role_v2[i]; 3106 r7 = &wl_rinfo_v7->active_role[i]; 3107 rlink = &wl_rinfo_v8->rlink[i][0]; 3108 3109 if (ver->fwlrole == 0 && 3110 (r->role == RTW89_WIFI_ROLE_P2P_GO || 3111 r->role == RTW89_WIFI_ROLE_P2P_CLIENT)) { 3112 ch = r->ch; 3113 bw = r->bw; 3114 break; 3115 } else if (ver->fwlrole == 1 && 3116 (r1->role == RTW89_WIFI_ROLE_P2P_GO || 3117 r1->role == RTW89_WIFI_ROLE_P2P_CLIENT)) { 3118 ch = r1->ch; 3119 bw = r1->bw; 3120 break; 3121 } else if (ver->fwlrole == 2 && 3122 (r2->role == RTW89_WIFI_ROLE_P2P_GO || 3123 r2->role == RTW89_WIFI_ROLE_P2P_CLIENT)) { 3124 ch = r2->ch; 3125 bw = r2->bw; 3126 break; 3127 } else if (ver->fwlrole == 7 && 3128 (r7->role == RTW89_WIFI_ROLE_P2P_GO || 3129 r7->role == RTW89_WIFI_ROLE_P2P_CLIENT)) { 3130 ch = r7->ch; 3131 bw = r7->bw; 3132 break; 3133 } else if (ver->fwlrole == 8 && 3134 (rlink->role == RTW89_WIFI_ROLE_P2P_GO || 3135 rlink->role == RTW89_WIFI_ROLE_P2P_CLIENT)) { 3136 ch = rlink->ch; 3137 bw = rlink->bw; 3138 break; 3139 } 3140 } 3141 } else { 3142 en = true; 3143 /* get 2g channel */ 3144 for (i = 0; i < RTW89_PORT_NUM; i++) { 3145 r = &wl_rinfo->active_role[i]; 3146 r1 = &wl_rinfo_v1->active_role_v1[i]; 3147 r2 = &wl_rinfo_v2->active_role_v2[i]; 3148 r7 = &wl_rinfo_v7->active_role[i]; 3149 rlink = &wl_rinfo_v8->rlink[i][0]; 3150 3151 if (ver->fwlrole == 0 && 3152 r->connected && r->band == RTW89_BAND_2G) { 3153 ch = r->ch; 3154 bw = r->bw; 3155 break; 3156 } else if (ver->fwlrole == 1 && 3157 r1->connected && r1->band == RTW89_BAND_2G) { 3158 ch = r1->ch; 3159 bw = r1->bw; 3160 break; 3161 } else if (ver->fwlrole == 2 && 3162 r2->connected && r2->band == RTW89_BAND_2G) { 3163 ch = r2->ch; 3164 bw = r2->bw; 3165 break; 3166 } else if (ver->fwlrole == 7 && 3167 r7->connected && r7->band == RTW89_BAND_2G) { 3168 ch = r7->ch; 3169 bw = r7->bw; 3170 break; 3171 } else if (ver->fwlrole == 8 && 3172 rlink->connected && rlink->rf_band == RTW89_BAND_2G) { 3173 ch = rlink->ch; 3174 bw = rlink->bw; 3175 break; 3176 } 3177 } 3178 } 3179 3180 switch (bw) { 3181 case RTW89_CHANNEL_WIDTH_20: 3182 bw = 20 + chip->afh_guard_ch * 2; 3183 break; 3184 case RTW89_CHANNEL_WIDTH_40: 3185 bw = 40 + chip->afh_guard_ch * 2; 3186 break; 3187 case RTW89_CHANNEL_WIDTH_5: 3188 bw = 5 + chip->afh_guard_ch * 2; 3189 break; 3190 case RTW89_CHANNEL_WIDTH_10: 3191 bw = 10 + chip->afh_guard_ch * 2; 3192 break; 3193 default: 3194 bw = 0; 3195 en = false; /* turn off AFH info if BW > 40 */ 3196 break; 3197 } 3198 3199 if (wl->afh_info.en == en && 3200 wl->afh_info.ch == ch && 3201 wl->afh_info.bw == bw && 3202 b->profile_cnt.last == b->profile_cnt.now) { 3203 rtw89_debug(rtwdev, RTW89_DBG_BTC, 3204 "[BTC], %s(): return because no change!\n", 3205 __func__); 3206 return; 3207 } 3208 3209 wl->afh_info.en = en; 3210 wl->afh_info.ch = ch; 3211 wl->afh_info.bw = bw; 3212 3213 _send_fw_cmd(rtwdev, BTFC_SET, SET_BT_WL_CH_INFO, &wl->afh_info, 3); 3214 3215 rtw89_debug(rtwdev, RTW89_DBG_BTC, 3216 "[BTC], %s(): en=%d, ch=%d, bw=%d\n", 3217 __func__, en, ch, bw); 3218 btc->cx.cnt_wl[BTC_WCNT_CH_UPDATE]++; 3219 } 3220 3221 static bool _check_freerun(struct rtw89_dev *rtwdev) 3222 { 3223 struct rtw89_btc *btc = &rtwdev->btc; 3224 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 3225 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 3226 struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; 3227 struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; 3228 struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; 3229 struct rtw89_btc_wl_role_info_v7 *wl_rinfo_v7 = &wl->role_info_v7; 3230 struct rtw89_btc_wl_role_info_v8 *wl_rinfo_v8 = &wl->role_info_v8; 3231 struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; 3232 struct rtw89_btc_bt_hid_desc *hid = &bt_linfo->hid_desc; 3233 union rtw89_btc_module_info *md = &btc->mdinfo; 3234 const struct rtw89_btc_ver *ver = btc->ver; 3235 u8 isolation, connect_cnt = 0; 3236 3237 if (ver->fcxinit == 7) 3238 isolation = md->md_v7.ant.isolation; 3239 else 3240 isolation = md->md.ant.isolation; 3241 3242 if (ver->fwlrole == 0) 3243 connect_cnt = wl_rinfo->connect_cnt; 3244 else if (ver->fwlrole == 1) 3245 connect_cnt = wl_rinfo_v1->connect_cnt; 3246 else if (ver->fwlrole == 2) 3247 connect_cnt = wl_rinfo_v2->connect_cnt; 3248 else if (ver->fwlrole == 7) 3249 connect_cnt = wl_rinfo_v7->connect_cnt; 3250 else if (ver->fwlrole == 8) 3251 connect_cnt = wl_rinfo_v8->connect_cnt; 3252 3253 if (btc->ant_type == BTC_ANT_SHARED) { 3254 btc->dm.trx_para_level = 0; 3255 return false; 3256 } 3257 3258 /* The below is dedicated antenna case */ 3259 if (connect_cnt > BTC_TDMA_WLROLE_MAX) { 3260 btc->dm.trx_para_level = 5; 3261 return true; 3262 } 3263 3264 if (bt_linfo->profile_cnt.now == 0) { 3265 btc->dm.trx_para_level = 5; 3266 return true; 3267 } 3268 3269 if (hid->pair_cnt > BTC_TDMA_BTHID_MAX) { 3270 btc->dm.trx_para_level = 5; 3271 return true; 3272 } 3273 3274 /* TODO get isolation by BT psd */ 3275 if (isolation >= BTC_FREERUN_ANTISO_MIN) { 3276 btc->dm.trx_para_level = 5; 3277 return true; 3278 } 3279 3280 if (!wl->status.map.busy) {/* wl idle -> freerun */ 3281 btc->dm.trx_para_level = 5; 3282 return true; 3283 } else if (wl->rssi_level > 1) {/* WL rssi < 50% (-60dBm) */ 3284 btc->dm.trx_para_level = 0; 3285 return false; 3286 } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) { 3287 if (wl->rssi_level == 0 && bt_linfo->rssi > 31) { 3288 btc->dm.trx_para_level = 6; 3289 return true; 3290 } else if (wl->rssi_level == 1 && bt_linfo->rssi > 36) { 3291 btc->dm.trx_para_level = 7; 3292 return true; 3293 } 3294 btc->dm.trx_para_level = 0; 3295 return false; 3296 } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_DL)) { 3297 if (bt_linfo->rssi > 28) { 3298 btc->dm.trx_para_level = 6; 3299 return true; 3300 } 3301 } 3302 3303 btc->dm.trx_para_level = 0; 3304 return false; 3305 } 3306 3307 #define _tdma_set_flctrl(btc, flc) ({(btc)->dm.tdma.rxflctrl = flc; }) 3308 #define _tdma_set_flctrl_role(btc, role) ({(btc)->dm.tdma.rxflctrl_role = role; }) 3309 #define _tdma_set_tog(btc, wtg) ({(btc)->dm.tdma.wtgle_n = wtg; }) 3310 #define _tdma_set_lek(btc, lek) ({(btc)->dm.tdma.leak_n = lek; }) 3311 3312 struct btc_btinfo_lb2 { 3313 u8 connect: 1; 3314 u8 sco_busy: 1; 3315 u8 inq_pag: 1; 3316 u8 acl_busy: 1; 3317 u8 hfp: 1; 3318 u8 hid: 1; 3319 u8 a2dp: 1; 3320 u8 pan: 1; 3321 }; 3322 3323 struct btc_btinfo_lb3 { 3324 u8 retry: 4; 3325 u8 cqddr: 1; 3326 u8 inq: 1; 3327 u8 mesh_busy: 1; 3328 u8 pag: 1; 3329 }; 3330 3331 struct btc_btinfo_hb0 { 3332 s8 rssi; 3333 }; 3334 3335 struct btc_btinfo_hb1 { 3336 u8 ble_connect: 1; 3337 u8 reinit: 1; 3338 u8 relink: 1; 3339 u8 igno_wl: 1; 3340 u8 voice: 1; 3341 u8 ble_scan: 1; 3342 u8 role_sw: 1; 3343 u8 multi_link: 1; 3344 }; 3345 3346 struct btc_btinfo_hb2 { 3347 u8 pan_active: 1; 3348 u8 afh_update: 1; 3349 u8 a2dp_active: 1; 3350 u8 slave: 1; 3351 u8 hid_slot: 2; 3352 u8 hid_cnt: 2; 3353 }; 3354 3355 struct btc_btinfo_hb3 { 3356 u8 a2dp_bitpool: 6; 3357 u8 tx_3m: 1; 3358 u8 a2dp_sink: 1; 3359 }; 3360 3361 union btc_btinfo { 3362 u8 val; 3363 struct btc_btinfo_lb2 lb2; 3364 struct btc_btinfo_lb3 lb3; 3365 struct btc_btinfo_hb0 hb0; 3366 struct btc_btinfo_hb1 hb1; 3367 struct btc_btinfo_hb2 hb2; 3368 struct btc_btinfo_hb3 hb3; 3369 }; 3370 3371 static void _set_policy(struct rtw89_dev *rtwdev, u16 policy_type, 3372 enum btc_reason_and_action action) 3373 { 3374 const struct rtw89_chip_info *chip = rtwdev->chip; 3375 3376 chip->ops->btc_set_policy(rtwdev, policy_type); 3377 _fw_set_policy(rtwdev, policy_type, action); 3378 } 3379 3380 #define BTC_B1_MAX 250 /* unit ms */ 3381 void rtw89_btc_set_policy(struct rtw89_dev *rtwdev, u16 policy_type) 3382 { 3383 struct rtw89_btc *btc = &rtwdev->btc; 3384 struct rtw89_btc_dm *dm = &btc->dm; 3385 struct rtw89_btc_fbtc_tdma *t = &dm->tdma; 3386 struct rtw89_btc_fbtc_slot *s = dm->slot.v1; 3387 u8 type; 3388 u32 tbl_w1, tbl_b1, tbl_b4; 3389 3390 if (btc->ant_type == BTC_ANT_SHARED) { 3391 if (btc->cx.wl.status.map._4way) 3392 tbl_w1 = cxtbl[1]; 3393 else 3394 tbl_w1 = cxtbl[8]; 3395 tbl_b1 = cxtbl[3]; 3396 tbl_b4 = cxtbl[3]; 3397 } else { 3398 tbl_w1 = cxtbl[16]; 3399 tbl_b1 = cxtbl[17]; 3400 tbl_b4 = cxtbl[17]; 3401 } 3402 3403 type = (u8)((policy_type & BTC_CXP_MASK) >> 8); 3404 btc->bt_req_en = false; 3405 3406 switch (type) { 3407 case BTC_CXP_USERDEF0: 3408 *t = t_def[CXTD_OFF]; 3409 s[CXST_OFF] = s_def[CXST_OFF]; 3410 _slot_set_tbl(btc, CXST_OFF, cxtbl[2]); 3411 btc->update_policy_force = true; 3412 break; 3413 case BTC_CXP_OFF: /* TDMA off */ 3414 _write_scbd(rtwdev, BTC_WSCB_TDMA, false); 3415 *t = t_def[CXTD_OFF]; 3416 s[CXST_OFF] = s_def[CXST_OFF]; 3417 3418 switch (policy_type) { 3419 case BTC_CXP_OFF_BT: 3420 _slot_set_tbl(btc, CXST_OFF, cxtbl[2]); 3421 break; 3422 case BTC_CXP_OFF_WL: 3423 _slot_set_tbl(btc, CXST_OFF, cxtbl[1]); 3424 break; 3425 case BTC_CXP_OFF_EQ0: 3426 _slot_set_tbl(btc, CXST_OFF, cxtbl[0]); 3427 break; 3428 case BTC_CXP_OFF_EQ1: 3429 _slot_set_tbl(btc, CXST_OFF, cxtbl[16]); 3430 break; 3431 case BTC_CXP_OFF_EQ2: 3432 _slot_set_tbl(btc, CXST_OFF, cxtbl[17]); 3433 break; 3434 case BTC_CXP_OFF_EQ3: 3435 _slot_set_tbl(btc, CXST_OFF, cxtbl[18]); 3436 break; 3437 case BTC_CXP_OFF_BWB0: 3438 _slot_set_tbl(btc, CXST_OFF, cxtbl[5]); 3439 break; 3440 case BTC_CXP_OFF_BWB1: 3441 _slot_set_tbl(btc, CXST_OFF, cxtbl[8]); 3442 break; 3443 case BTC_CXP_OFF_BWB3: 3444 _slot_set_tbl(btc, CXST_OFF, cxtbl[6]); 3445 break; 3446 } 3447 break; 3448 case BTC_CXP_OFFB: /* TDMA off + beacon protect */ 3449 _write_scbd(rtwdev, BTC_WSCB_TDMA, false); 3450 *t = t_def[CXTD_OFF_B2]; 3451 s[CXST_OFF] = s_def[CXST_OFF]; 3452 switch (policy_type) { 3453 case BTC_CXP_OFFB_BWB0: 3454 _slot_set_tbl(btc, CXST_OFF, cxtbl[8]); 3455 break; 3456 } 3457 break; 3458 case BTC_CXP_OFFE: /* TDMA off + beacon protect + Ext_control */ 3459 btc->bt_req_en = true; 3460 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3461 *t = t_def[CXTD_OFF_EXT]; 3462 switch (policy_type) { 3463 case BTC_CXP_OFFE_DEF: 3464 s[CXST_E2G] = s_def[CXST_E2G]; 3465 s[CXST_E5G] = s_def[CXST_E5G]; 3466 s[CXST_EBT] = s_def[CXST_EBT]; 3467 s[CXST_ENULL] = s_def[CXST_ENULL]; 3468 break; 3469 case BTC_CXP_OFFE_DEF2: 3470 _slot_set(btc, CXST_E2G, 20, cxtbl[1], SLOT_ISO); 3471 s[CXST_E5G] = s_def[CXST_E5G]; 3472 s[CXST_EBT] = s_def[CXST_EBT]; 3473 s[CXST_ENULL] = s_def[CXST_ENULL]; 3474 break; 3475 } 3476 break; 3477 case BTC_CXP_FIX: /* TDMA Fix-Slot */ 3478 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3479 *t = t_def[CXTD_FIX]; 3480 switch (policy_type) { 3481 case BTC_CXP_FIX_TD3030: 3482 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3483 _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); 3484 break; 3485 case BTC_CXP_FIX_TD5050: 3486 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 3487 _slot_set(btc, CXST_B1, 50, tbl_b1, SLOT_MIX); 3488 break; 3489 case BTC_CXP_FIX_TD2030: 3490 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3491 _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); 3492 break; 3493 case BTC_CXP_FIX_TD4010: 3494 _slot_set(btc, CXST_W1, 40, tbl_w1, SLOT_ISO); 3495 _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); 3496 break; 3497 case BTC_CXP_FIX_TD4010ISO: 3498 _slot_set(btc, CXST_W1, 40, cxtbl[1], SLOT_ISO); 3499 _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); 3500 break; 3501 case BTC_CXP_FIX_TD4010ISO_DL: 3502 _slot_set(btc, CXST_W1, 40, cxtbl[25], SLOT_ISO); 3503 _slot_set(btc, CXST_B1, 10, cxtbl[25], SLOT_ISO); 3504 break; 3505 case BTC_CXP_FIX_TD4010ISO_UL: 3506 _slot_set(btc, CXST_W1, 40, cxtbl[20], SLOT_ISO); 3507 _slot_set(btc, CXST_B1, 10, cxtbl[25], SLOT_MIX); 3508 break; 3509 case BTC_CXP_FIX_TD7010: 3510 _slot_set(btc, CXST_W1, 70, tbl_w1, SLOT_ISO); 3511 _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); 3512 break; 3513 case BTC_CXP_FIX_TD2060: 3514 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3515 _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); 3516 break; 3517 case BTC_CXP_FIX_TD3060: 3518 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3519 _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); 3520 break; 3521 case BTC_CXP_FIX_TD2080: 3522 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3523 _slot_set(btc, CXST_B1, 80, tbl_b1, SLOT_MIX); 3524 break; 3525 case BTC_CXP_FIX_TDW1B1: /* W1:B1 = user-define */ 3526 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 3527 tbl_w1, SLOT_ISO); 3528 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], 3529 tbl_b1, SLOT_MIX); 3530 break; 3531 } 3532 break; 3533 case BTC_CXP_PFIX: /* PS-TDMA Fix-Slot */ 3534 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3535 *t = t_def[CXTD_PFIX]; 3536 if (btc->cx.wl.role_info.role_map.role.ap) 3537 _tdma_set_flctrl(btc, CXFLC_QOSNULL); 3538 3539 switch (policy_type) { 3540 case BTC_CXP_PFIX_TD3030: 3541 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3542 _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); 3543 break; 3544 case BTC_CXP_PFIX_TD5050: 3545 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 3546 _slot_set(btc, CXST_B1, 50, tbl_b1, SLOT_MIX); 3547 break; 3548 case BTC_CXP_PFIX_TD2030: 3549 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3550 _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); 3551 break; 3552 case BTC_CXP_PFIX_TD2060: 3553 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3554 _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); 3555 break; 3556 case BTC_CXP_PFIX_TD3070: 3557 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3558 _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); 3559 break; 3560 case BTC_CXP_PFIX_TD2080: 3561 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3562 _slot_set(btc, CXST_B1, 80, tbl_b1, SLOT_MIX); 3563 break; 3564 } 3565 break; 3566 case BTC_CXP_AUTO: /* TDMA Auto-Slot */ 3567 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3568 *t = t_def[CXTD_AUTO]; 3569 switch (policy_type) { 3570 case BTC_CXP_AUTO_TD50B1: 3571 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 3572 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3573 break; 3574 case BTC_CXP_AUTO_TD60B1: 3575 _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); 3576 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3577 break; 3578 case BTC_CXP_AUTO_TD20B1: 3579 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3580 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3581 break; 3582 case BTC_CXP_AUTO_TDW1B1: /* W1:B1 = user-define */ 3583 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 3584 tbl_w1, SLOT_ISO); 3585 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], 3586 tbl_b1, SLOT_MIX); 3587 break; 3588 } 3589 break; 3590 case BTC_CXP_PAUTO: /* PS-TDMA Auto-Slot */ 3591 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3592 *t = t_def[CXTD_PAUTO]; 3593 switch (policy_type) { 3594 case BTC_CXP_PAUTO_TD50B1: 3595 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 3596 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3597 break; 3598 case BTC_CXP_PAUTO_TD60B1: 3599 _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); 3600 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3601 break; 3602 case BTC_CXP_PAUTO_TD20B1: 3603 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3604 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3605 break; 3606 case BTC_CXP_PAUTO_TDW1B1: 3607 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 3608 tbl_w1, SLOT_ISO); 3609 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], 3610 tbl_b1, SLOT_MIX); 3611 break; 3612 } 3613 break; 3614 case BTC_CXP_AUTO2: /* TDMA Auto-Slot2 */ 3615 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3616 *t = t_def[CXTD_AUTO2]; 3617 switch (policy_type) { 3618 case BTC_CXP_AUTO2_TD3050: 3619 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3620 _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); 3621 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3622 break; 3623 case BTC_CXP_AUTO2_TD3070: 3624 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3625 _slot_set(btc, CXST_B4, 70, tbl_b4, SLOT_MIX); 3626 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3627 break; 3628 case BTC_CXP_AUTO2_TD5050: 3629 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 3630 _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); 3631 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3632 break; 3633 case BTC_CXP_AUTO2_TD6060: 3634 _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); 3635 _slot_set(btc, CXST_B4, 60, tbl_b4, SLOT_MIX); 3636 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3637 break; 3638 case BTC_CXP_AUTO2_TD2080: 3639 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3640 _slot_set(btc, CXST_B4, 80, tbl_b4, SLOT_MIX); 3641 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3642 break; 3643 case BTC_CXP_AUTO2_TDW1B4: /* W1:B1 = user-define */ 3644 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 3645 tbl_w1, SLOT_ISO); 3646 _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4], 3647 tbl_b4, SLOT_MIX); 3648 break; 3649 } 3650 break; 3651 case BTC_CXP_PAUTO2: /* PS-TDMA Auto-Slot2 */ 3652 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3653 *t = t_def[CXTD_PAUTO2]; 3654 switch (policy_type) { 3655 case BTC_CXP_PAUTO2_TD3050: 3656 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3657 _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); 3658 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3659 break; 3660 case BTC_CXP_PAUTO2_TD3070: 3661 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3662 _slot_set(btc, CXST_B4, 70, tbl_b4, SLOT_MIX); 3663 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3664 break; 3665 case BTC_CXP_PAUTO2_TD5050: 3666 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 3667 _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); 3668 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3669 break; 3670 case BTC_CXP_PAUTO2_TD6060: 3671 _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); 3672 _slot_set(btc, CXST_B4, 60, tbl_b4, SLOT_MIX); 3673 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3674 break; 3675 case BTC_CXP_PAUTO2_TD2080: 3676 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3677 _slot_set(btc, CXST_B4, 80, tbl_b4, SLOT_MIX); 3678 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3679 break; 3680 case BTC_CXP_PAUTO2_TDW1B4: /* W1:B1 = user-define */ 3681 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 3682 tbl_w1, SLOT_ISO); 3683 _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4], 3684 tbl_b4, SLOT_MIX); 3685 break; 3686 } 3687 break; 3688 } 3689 } 3690 EXPORT_SYMBOL(rtw89_btc_set_policy); 3691 3692 void rtw89_btc_set_policy_v1(struct rtw89_dev *rtwdev, u16 policy_type) 3693 { 3694 struct rtw89_btc *btc = &rtwdev->btc; 3695 struct rtw89_btc_dm *dm = &btc->dm; 3696 struct rtw89_btc_fbtc_tdma *t = &dm->tdma; 3697 struct rtw89_btc_wl_role_info_v1 *wl_rinfo = &btc->cx.wl.role_info_v1; 3698 struct rtw89_btc_bt_hid_desc *hid = &btc->cx.bt.link_info.hid_desc; 3699 struct rtw89_btc_bt_hfp_desc *hfp = &btc->cx.bt.link_info.hfp_desc; 3700 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 3701 u8 type, null_role; 3702 u32 tbl_w1, tbl_b1, tbl_b4; 3703 u16 dur_2; 3704 3705 type = FIELD_GET(BTC_CXP_MASK, policy_type); 3706 3707 if (btc->ant_type == BTC_ANT_SHARED) { 3708 if (btc->cx.wl.status.map._4way) 3709 tbl_w1 = cxtbl[1]; 3710 else if (hid->exist && hid->type == BTC_HID_218) 3711 tbl_w1 = cxtbl[7]; /* Ack/BA no break bt Hi-Pri-rx */ 3712 else 3713 tbl_w1 = cxtbl[8]; 3714 3715 if (dm->leak_ap && 3716 (type == BTC_CXP_PFIX || type == BTC_CXP_PAUTO2)) { 3717 tbl_b1 = cxtbl[3]; 3718 tbl_b4 = cxtbl[3]; 3719 } else if (hid->exist && hid->type == BTC_HID_218) { 3720 tbl_b1 = cxtbl[4]; /* Ack/BA no break bt Hi-Pri-rx */ 3721 tbl_b4 = cxtbl[4]; 3722 } else { 3723 tbl_b1 = cxtbl[2]; 3724 tbl_b4 = cxtbl[2]; 3725 } 3726 } else { 3727 tbl_b1 = cxtbl[17]; 3728 tbl_b4 = cxtbl[17]; 3729 3730 if (wl->bg_mode) 3731 tbl_w1 = cxtbl[8]; 3732 else if ((wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) && 3733 hid->exist) 3734 tbl_w1 = cxtbl[19]; 3735 else 3736 tbl_w1 = cxtbl[16]; 3737 } 3738 3739 switch (type) { 3740 case BTC_CXP_USERDEF0: 3741 btc->update_policy_force = true; 3742 *t = t_def[CXTD_OFF]; 3743 _slot_set_le(btc, CXST_OFF, s_def[CXST_OFF].dur, 3744 s_def[CXST_OFF].cxtbl, s_def[CXST_OFF].cxtype); 3745 _slot_set_tbl(btc, CXST_OFF, cxtbl[2]); 3746 break; 3747 case BTC_CXP_OFF: /* TDMA off */ 3748 _write_scbd(rtwdev, BTC_WSCB_TDMA, false); 3749 *t = t_def[CXTD_OFF]; 3750 _slot_set_le(btc, CXST_OFF, s_def[CXST_OFF].dur, 3751 s_def[CXST_OFF].cxtbl, s_def[CXST_OFF].cxtype); 3752 3753 switch (policy_type) { 3754 case BTC_CXP_OFF_BT: 3755 _slot_set_tbl(btc, CXST_OFF, cxtbl[2]); 3756 break; 3757 case BTC_CXP_OFF_WL: 3758 _slot_set_tbl(btc, CXST_OFF, cxtbl[1]); 3759 break; 3760 case BTC_CXP_OFF_WL2: 3761 _slot_set_tbl(btc, CXST_OFF, cxtbl[1]); 3762 _slot_set_type(btc, CXST_OFF, SLOT_ISO); 3763 break; 3764 case BTC_CXP_OFF_EQ0: 3765 _slot_set_tbl(btc, CXST_OFF, cxtbl[0]); 3766 _slot_set_type(btc, CXST_OFF, SLOT_ISO); 3767 break; 3768 case BTC_CXP_OFF_EQ1: 3769 _slot_set_tbl(btc, CXST_OFF, cxtbl[16]); 3770 break; 3771 case BTC_CXP_OFF_EQ2: 3772 _slot_set_tbl(btc, CXST_OFF, cxtbl[0]); 3773 break; 3774 case BTC_CXP_OFF_EQ3: 3775 _slot_set_tbl(btc, CXST_OFF, cxtbl[24]); 3776 break; 3777 case BTC_CXP_OFF_EQ4: 3778 _slot_set_tbl(btc, CXST_OFF, cxtbl[26]); 3779 break; 3780 case BTC_CXP_OFF_EQ5: 3781 _slot_set_tbl(btc, CXST_OFF, cxtbl[27]); 3782 break; 3783 case BTC_CXP_OFF_BWB0: 3784 _slot_set_tbl(btc, CXST_OFF, cxtbl[5]); 3785 break; 3786 case BTC_CXP_OFF_BWB1: 3787 _slot_set_tbl(btc, CXST_OFF, cxtbl[8]); 3788 break; 3789 case BTC_CXP_OFF_BWB2: 3790 _slot_set_tbl(btc, CXST_OFF, cxtbl[7]); 3791 break; 3792 case BTC_CXP_OFF_BWB3: 3793 _slot_set_tbl(btc, CXST_OFF, cxtbl[6]); 3794 break; 3795 default: 3796 break; 3797 } 3798 break; 3799 case BTC_CXP_OFFB: /* TDMA off + beacon protect */ 3800 _write_scbd(rtwdev, BTC_WSCB_TDMA, false); 3801 *t = t_def[CXTD_OFF_B2]; 3802 _slot_set_le(btc, CXST_OFF, s_def[CXST_OFF].dur, 3803 s_def[CXST_OFF].cxtbl, s_def[CXST_OFF].cxtype); 3804 3805 switch (policy_type) { 3806 case BTC_CXP_OFFB_BWB0: 3807 _slot_set_tbl(btc, CXST_OFF, cxtbl[8]); 3808 break; 3809 default: 3810 break; 3811 } 3812 break; 3813 case BTC_CXP_OFFE: /* TDMA off + beacon protect + Ext_control */ 3814 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3815 *t = t_def[CXTD_OFF_EXT]; 3816 3817 /* To avoid wl-s0 tx break by hid/hfp tx */ 3818 if (hid->exist || hfp->exist) 3819 tbl_w1 = cxtbl[16]; 3820 3821 dur_2 = dm->e2g_slot_limit; 3822 3823 switch (policy_type) { 3824 case BTC_CXP_OFFE_2GBWISOB: /* for normal-case */ 3825 _slot_set(btc, CXST_E2G, 0, tbl_w1, SLOT_ISO); 3826 _slot_set_le(btc, CXST_EBT, s_def[CXST_EBT].dur, 3827 s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype); 3828 _slot_set_dur(btc, CXST_EBT, dur_2); 3829 break; 3830 case BTC_CXP_OFFE_2GISOB: /* for bt no-link */ 3831 _slot_set(btc, CXST_E2G, 0, cxtbl[1], SLOT_ISO); 3832 _slot_set_le(btc, CXST_EBT, s_def[CXST_EBT].dur, 3833 s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype); 3834 _slot_set_dur(btc, CXST_EBT, dur_2); 3835 break; 3836 case BTC_CXP_OFFE_DEF: 3837 _slot_set_le(btc, CXST_E2G, s_def[CXST_E2G].dur, 3838 s_def[CXST_E2G].cxtbl, s_def[CXST_E2G].cxtype); 3839 _slot_set_le(btc, CXST_E5G, s_def[CXST_E5G].dur, 3840 s_def[CXST_E5G].cxtbl, s_def[CXST_E5G].cxtype); 3841 _slot_set_le(btc, CXST_EBT, s_def[CXST_EBT].dur, 3842 s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype); 3843 _slot_set_le(btc, CXST_ENULL, s_def[CXST_ENULL].dur, 3844 s_def[CXST_ENULL].cxtbl, s_def[CXST_ENULL].cxtype); 3845 break; 3846 case BTC_CXP_OFFE_DEF2: 3847 _slot_set(btc, CXST_E2G, 20, cxtbl[1], SLOT_ISO); 3848 _slot_set_le(btc, CXST_E5G, s_def[CXST_E5G].dur, 3849 s_def[CXST_E5G].cxtbl, s_def[CXST_E5G].cxtype); 3850 _slot_set_le(btc, CXST_EBT, s_def[CXST_EBT].dur, 3851 s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype); 3852 _slot_set_le(btc, CXST_ENULL, s_def[CXST_ENULL].dur, 3853 s_def[CXST_ENULL].cxtbl, s_def[CXST_ENULL].cxtype); 3854 break; 3855 case BTC_CXP_OFFE_2GBWMIXB: 3856 _slot_set(btc, CXST_E2G, 0, 0xea5a5555, SLOT_MIX); 3857 _slot_set_le(btc, CXST_EBT, s_def[CXST_EBT].dur, 3858 s_def[CXST_EBT].cxtbl, s_def[CXST_EBT].cxtype); 3859 break; 3860 case BTC_CXP_OFFE_WL: /* for 4-way */ 3861 _slot_set(btc, CXST_E2G, 0, cxtbl[1], SLOT_MIX); 3862 _slot_set(btc, CXST_EBT, 0, cxtbl[1], SLOT_MIX); 3863 break; 3864 default: 3865 break; 3866 } 3867 _slot_set_le(btc, CXST_E5G, s_def[CXST_E5G].dur, 3868 s_def[CXST_E5G].cxtbl, s_def[CXST_E5G].cxtype); 3869 _slot_set_le(btc, CXST_OFF, s_def[CXST_OFF].dur, 3870 s_def[CXST_OFF].cxtbl, s_def[CXST_OFF].cxtype); 3871 break; 3872 case BTC_CXP_FIX: /* TDMA Fix-Slot */ 3873 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3874 *t = t_def[CXTD_FIX]; 3875 3876 switch (policy_type) { 3877 case BTC_CXP_FIX_TD3030: 3878 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3879 _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); 3880 break; 3881 case BTC_CXP_FIX_TD5050: 3882 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 3883 _slot_set(btc, CXST_B1, 50, tbl_b1, SLOT_MIX); 3884 break; 3885 case BTC_CXP_FIX_TD2030: 3886 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3887 _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); 3888 break; 3889 case BTC_CXP_FIX_TD4010: 3890 _slot_set(btc, CXST_W1, 40, tbl_w1, SLOT_ISO); 3891 _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); 3892 break; 3893 case BTC_CXP_FIX_TD4010ISO: 3894 _slot_set(btc, CXST_W1, 40, cxtbl[1], SLOT_ISO); 3895 _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); 3896 break; 3897 case BTC_CXP_FIX_TD4010ISO_DL: 3898 _slot_set(btc, CXST_W1, 40, cxtbl[25], SLOT_ISO); 3899 _slot_set(btc, CXST_B1, 10, cxtbl[25], SLOT_ISO); 3900 break; 3901 case BTC_CXP_FIX_TD4010ISO_UL: 3902 _slot_set(btc, CXST_W1, 40, cxtbl[20], SLOT_ISO); 3903 _slot_set(btc, CXST_B1, 10, cxtbl[25], SLOT_MIX); 3904 break; 3905 case BTC_CXP_FIX_TD7010: 3906 _slot_set(btc, CXST_W1, 70, tbl_w1, SLOT_ISO); 3907 _slot_set(btc, CXST_B1, 10, tbl_b1, SLOT_MIX); 3908 break; 3909 case BTC_CXP_FIX_TD2060: 3910 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3911 _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); 3912 break; 3913 case BTC_CXP_FIX_TD3060: 3914 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3915 _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); 3916 break; 3917 case BTC_CXP_FIX_TD2080: 3918 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3919 _slot_set(btc, CXST_B1, 80, tbl_b1, SLOT_MIX); 3920 break; 3921 case BTC_CXP_FIX_TDW1B1: /* W1:B1 = user-define */ 3922 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 3923 tbl_w1, SLOT_ISO); 3924 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], 3925 tbl_b1, SLOT_MIX); 3926 break; 3927 default: 3928 break; 3929 } 3930 break; 3931 case BTC_CXP_PFIX: /* PS-TDMA Fix-Slot */ 3932 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3933 *t = t_def[CXTD_PFIX]; 3934 3935 switch (policy_type) { 3936 case BTC_CXP_PFIX_TD3030: 3937 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3938 _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); 3939 break; 3940 case BTC_CXP_PFIX_TD5050: 3941 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 3942 _slot_set(btc, CXST_B1, 50, tbl_b1, SLOT_MIX); 3943 break; 3944 case BTC_CXP_PFIX_TD2030: 3945 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3946 _slot_set(btc, CXST_B1, 30, tbl_b1, SLOT_MIX); 3947 break; 3948 case BTC_CXP_PFIX_TD2060: 3949 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3950 _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); 3951 break; 3952 case BTC_CXP_PFIX_TD3070: 3953 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 3954 _slot_set(btc, CXST_B1, 60, tbl_b1, SLOT_MIX); 3955 break; 3956 case BTC_CXP_PFIX_TD2080: 3957 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3958 _slot_set(btc, CXST_B1, 80, tbl_b1, SLOT_MIX); 3959 break; 3960 case BTC_CXP_PFIX_TDW1B1: /* W1:B1 = user-define */ 3961 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 3962 tbl_w1, SLOT_ISO); 3963 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], 3964 tbl_b1, SLOT_MIX); 3965 break; 3966 default: 3967 break; 3968 } 3969 break; 3970 case BTC_CXP_AUTO: /* TDMA Auto-Slot */ 3971 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3972 *t = t_def[CXTD_AUTO]; 3973 3974 switch (policy_type) { 3975 case BTC_CXP_AUTO_TD50B1: 3976 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 3977 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3978 break; 3979 case BTC_CXP_AUTO_TD60B1: 3980 _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); 3981 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3982 break; 3983 case BTC_CXP_AUTO_TD20B1: 3984 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 3985 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 3986 break; 3987 case BTC_CXP_AUTO_TDW1B1: /* W1:B1 = user-define */ 3988 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 3989 tbl_w1, SLOT_ISO); 3990 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], 3991 tbl_b1, SLOT_MIX); 3992 break; 3993 default: 3994 break; 3995 } 3996 break; 3997 case BTC_CXP_PAUTO: /* PS-TDMA Auto-Slot */ 3998 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 3999 *t = t_def[CXTD_PAUTO]; 4000 4001 switch (policy_type) { 4002 case BTC_CXP_PAUTO_TD50B1: 4003 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 4004 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4005 break; 4006 case BTC_CXP_PAUTO_TD60B1: 4007 _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); 4008 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4009 break; 4010 case BTC_CXP_PAUTO_TD20B1: 4011 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 4012 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4013 break; 4014 case BTC_CXP_PAUTO_TDW1B1: 4015 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 4016 tbl_w1, SLOT_ISO); 4017 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], 4018 tbl_b1, SLOT_MIX); 4019 break; 4020 default: 4021 break; 4022 } 4023 break; 4024 case BTC_CXP_AUTO2: /* TDMA Auto-Slot2 */ 4025 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 4026 *t = t_def[CXTD_AUTO2]; 4027 4028 switch (policy_type) { 4029 case BTC_CXP_AUTO2_TD3050: 4030 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 4031 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4032 _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); 4033 break; 4034 case BTC_CXP_AUTO2_TD3070: 4035 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 4036 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4037 _slot_set(btc, CXST_B4, 70, tbl_b4, SLOT_MIX); 4038 break; 4039 case BTC_CXP_AUTO2_TD5050: 4040 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 4041 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4042 _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); 4043 break; 4044 case BTC_CXP_AUTO2_TD6060: 4045 _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); 4046 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4047 _slot_set(btc, CXST_B4, 60, tbl_b4, SLOT_MIX); 4048 break; 4049 case BTC_CXP_AUTO2_TD2080: 4050 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 4051 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4052 _slot_set(btc, CXST_B4, 80, tbl_b4, SLOT_MIX); 4053 break; 4054 case BTC_CXP_AUTO2_TDW1B4: /* W1:B1 = user-define */ 4055 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 4056 tbl_w1, SLOT_ISO); 4057 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], 4058 tbl_b1, SLOT_MIX); 4059 _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4], 4060 tbl_b4, SLOT_MIX); 4061 break; 4062 default: 4063 break; 4064 } 4065 break; 4066 case BTC_CXP_PAUTO2: /* PS-TDMA Auto-Slot2 */ 4067 _write_scbd(rtwdev, BTC_WSCB_TDMA, true); 4068 *t = t_def[CXTD_PAUTO2]; 4069 4070 switch (policy_type) { 4071 case BTC_CXP_PAUTO2_TD3050: 4072 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 4073 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4074 _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); 4075 break; 4076 case BTC_CXP_PAUTO2_TD3070: 4077 _slot_set(btc, CXST_W1, 30, tbl_w1, SLOT_ISO); 4078 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4079 _slot_set(btc, CXST_B4, 70, tbl_b4, SLOT_MIX); 4080 break; 4081 case BTC_CXP_PAUTO2_TD5050: 4082 _slot_set(btc, CXST_W1, 50, tbl_w1, SLOT_ISO); 4083 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4084 _slot_set(btc, CXST_B4, 50, tbl_b4, SLOT_MIX); 4085 break; 4086 case BTC_CXP_PAUTO2_TD6060: 4087 _slot_set(btc, CXST_W1, 60, tbl_w1, SLOT_ISO); 4088 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4089 _slot_set(btc, CXST_B4, 60, tbl_b4, SLOT_MIX); 4090 break; 4091 case BTC_CXP_PAUTO2_TD2080: 4092 _slot_set(btc, CXST_W1, 20, tbl_w1, SLOT_ISO); 4093 _slot_set(btc, CXST_B1, BTC_B1_MAX, tbl_b1, SLOT_MIX); 4094 _slot_set(btc, CXST_B4, 80, tbl_b4, SLOT_MIX); 4095 break; 4096 case BTC_CXP_PAUTO2_TDW1B4: /* W1:B1 = user-define */ 4097 _slot_set(btc, CXST_W1, dm->slot_dur[CXST_W1], 4098 tbl_w1, SLOT_ISO); 4099 _slot_set(btc, CXST_B1, dm->slot_dur[CXST_B1], 4100 tbl_b1, SLOT_MIX); 4101 _slot_set(btc, CXST_B4, dm->slot_dur[CXST_B4], 4102 tbl_b4, SLOT_MIX); 4103 break; 4104 default: 4105 break; 4106 } 4107 break; 4108 } 4109 4110 if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC && dm->tdma.rxflctrl) { 4111 null_role = FIELD_PREP(0x0f, dm->wl_scc.null_role1) | 4112 FIELD_PREP(0xf0, dm->wl_scc.null_role2); 4113 _tdma_set_flctrl_role(btc, null_role); 4114 } 4115 4116 /* enter leak_slot after each null-1 */ 4117 if (dm->leak_ap && dm->tdma.leak_n > 1) 4118 _tdma_set_lek(btc, 1); 4119 4120 if (dm->tdma_instant_excute) { 4121 btc->dm.tdma.option_ctrl |= BIT(0); 4122 btc->update_policy_force = true; 4123 } 4124 } 4125 EXPORT_SYMBOL(rtw89_btc_set_policy_v1); 4126 4127 static void _set_bt_plut(struct rtw89_dev *rtwdev, u8 phy_map, 4128 u8 tx_val, u8 rx_val) 4129 { 4130 struct rtw89_btc_wl_info *wl = &rtwdev->btc.cx.wl; 4131 struct rtw89_mac_ax_plt plt; 4132 4133 plt.tx = tx_val; 4134 plt.rx = rx_val; 4135 4136 if (rtwdev->btc.ver->fwlrole == 8) { 4137 plt.band = wl->pta_req_mac; 4138 if (wl->bt_polut_type[plt.band] == tx_val) 4139 return; 4140 4141 wl->bt_polut_type[plt.band] = tx_val; 4142 rtw89_mac_cfg_plt(rtwdev, &plt); 4143 } else { 4144 plt.band = RTW89_MAC_0; 4145 4146 if (phy_map & BTC_PHY_0) 4147 rtw89_mac_cfg_plt(rtwdev, &plt); 4148 4149 if (!rtwdev->dbcc_en) 4150 return; 4151 4152 plt.band = RTW89_MAC_1; 4153 if (phy_map & BTC_PHY_1) 4154 rtw89_mac_cfg_plt(rtwdev, &plt); 4155 } 4156 } 4157 4158 static void _set_ant_v0(struct rtw89_dev *rtwdev, bool force_exec, 4159 u8 phy_map, u8 type) 4160 { 4161 struct rtw89_btc *btc = &rtwdev->btc; 4162 struct rtw89_btc_dm *dm = &btc->dm; 4163 struct rtw89_btc_cx *cx = &btc->cx; 4164 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 4165 struct rtw89_btc_bt_info *bt = &cx->bt; 4166 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 4167 u8 gnt_wl_ctrl, gnt_bt_ctrl, plt_ctrl, i, b2g = 0; 4168 bool dbcc_chg = false; 4169 u32 ant_path_type; 4170 4171 ant_path_type = ((phy_map << 8) + type); 4172 4173 if (btc->ver->fwlrole == 1) 4174 dbcc_chg = wl->role_info_v1.dbcc_chg; 4175 else if (btc->ver->fwlrole == 2) 4176 dbcc_chg = wl->role_info_v2.dbcc_chg; 4177 else if (btc->ver->fwlrole == 7) 4178 dbcc_chg = wl->role_info_v7.dbcc_chg; 4179 else if (btc->ver->fwlrole == 8) 4180 dbcc_chg = wl->role_info_v8.dbcc_chg; 4181 4182 if (btc->dm.run_reason == BTC_RSN_NTFY_POWEROFF || 4183 btc->dm.run_reason == BTC_RSN_NTFY_RADIO_STATE || 4184 btc->dm.run_reason == BTC_RSN_CMD_SET_COEX || dbcc_chg) 4185 force_exec = FC_EXEC; 4186 4187 if (!force_exec && ant_path_type == dm->set_ant_path) { 4188 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4189 "[BTC], %s(): return by no change!!\n", 4190 __func__); 4191 return; 4192 } else if (bt->rfk_info.map.run) { 4193 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4194 "[BTC], %s(): return by bt rfk!!\n", __func__); 4195 return; 4196 } else if (btc->dm.run_reason != BTC_RSN_NTFY_WL_RFK && 4197 wl->rfk_info.state != BTC_WRFK_STOP) { 4198 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4199 "[BTC], %s(): return by wl rfk!!\n", __func__); 4200 return; 4201 } 4202 4203 dm->set_ant_path = ant_path_type; 4204 4205 rtw89_debug(rtwdev, 4206 RTW89_DBG_BTC, 4207 "[BTC], %s(): path=0x%x, set_type=0x%x\n", 4208 __func__, phy_map, dm->set_ant_path & 0xff); 4209 4210 switch (type) { 4211 case BTC_ANT_WPOWERON: 4212 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_BT); 4213 break; 4214 case BTC_ANT_WINIT: 4215 if (bt->enable.now) 4216 _set_gnt(rtwdev, phy_map, BTC_GNT_SW_LO, BTC_GNT_SW_HI); 4217 else 4218 _set_gnt(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_SW_LO); 4219 4220 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_WL); 4221 _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_BT, BTC_PLT_BT); 4222 break; 4223 case BTC_ANT_WONLY: 4224 _set_gnt(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_SW_LO); 4225 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_WL); 4226 _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); 4227 break; 4228 case BTC_ANT_WOFF: 4229 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_BT); 4230 _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); 4231 break; 4232 case BTC_ANT_W2G: 4233 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_WL); 4234 if (rtwdev->dbcc_en) { 4235 for (i = 0; i < RTW89_PHY_MAX; i++) { 4236 b2g = (wl_dinfo->real_band[i] == RTW89_BAND_2G); 4237 4238 gnt_wl_ctrl = b2g ? BTC_GNT_HW : BTC_GNT_SW_HI; 4239 gnt_bt_ctrl = b2g ? BTC_GNT_HW : BTC_GNT_SW_HI; 4240 /* BT should control by GNT_BT if WL_2G at S0 */ 4241 if (i == 1 && 4242 wl_dinfo->real_band[0] == RTW89_BAND_2G && 4243 wl_dinfo->real_band[1] == RTW89_BAND_5G) 4244 gnt_bt_ctrl = BTC_GNT_HW; 4245 _set_gnt(rtwdev, BIT(i), gnt_wl_ctrl, gnt_bt_ctrl); 4246 plt_ctrl = b2g ? BTC_PLT_BT : BTC_PLT_NONE; 4247 _set_bt_plut(rtwdev, BIT(i), 4248 plt_ctrl, plt_ctrl); 4249 } 4250 } else { 4251 _set_gnt(rtwdev, phy_map, BTC_GNT_HW, BTC_GNT_HW); 4252 _set_bt_plut(rtwdev, BTC_PHY_ALL, 4253 BTC_PLT_BT, BTC_PLT_BT); 4254 } 4255 break; 4256 case BTC_ANT_W5G: 4257 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_WL); 4258 _set_gnt(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_HW); 4259 _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); 4260 break; 4261 case BTC_ANT_W25G: 4262 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_WL); 4263 _set_gnt(rtwdev, phy_map, BTC_GNT_HW, BTC_GNT_HW); 4264 _set_bt_plut(rtwdev, BTC_PHY_ALL, 4265 BTC_PLT_GNT_WL, BTC_PLT_GNT_WL); 4266 break; 4267 case BTC_ANT_FREERUN: 4268 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_WL); 4269 _set_gnt(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_SW_HI); 4270 _set_bt_plut(rtwdev, BTC_PHY_ALL, BTC_PLT_NONE, BTC_PLT_NONE); 4271 break; 4272 case BTC_ANT_WRFK: 4273 case BTC_ANT_WRFK2: 4274 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_WL); 4275 _set_gnt(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_SW_LO); 4276 _set_bt_plut(rtwdev, phy_map, BTC_PLT_NONE, BTC_PLT_NONE); 4277 break; 4278 case BTC_ANT_BRFK: 4279 rtw89_chip_cfg_ctrl_path(rtwdev, BTC_CTRL_BY_BT); 4280 _set_gnt(rtwdev, phy_map, BTC_GNT_SW_LO, BTC_GNT_SW_HI); 4281 _set_bt_plut(rtwdev, phy_map, BTC_PLT_NONE, BTC_PLT_NONE); 4282 break; 4283 default: 4284 break; 4285 } 4286 } 4287 4288 static void _set_ant_v1(struct rtw89_dev *rtwdev, bool force_exec, 4289 u8 phy_map, u8 type) 4290 { 4291 struct rtw89_btc *btc = &rtwdev->btc; 4292 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 4293 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 4294 struct rtw89_btc_wl_role_info_v8 *wl_rinfo = &wl->role_info_v8; 4295 u32 ant_path_type = rtw89_get_antpath_type(phy_map, type); 4296 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 4297 struct rtw89_btc_dm *dm = &btc->dm; 4298 u8 gwl = BTC_GNT_HW; 4299 4300 if (btc->dm.run_reason == BTC_RSN_NTFY_POWEROFF || 4301 btc->dm.run_reason == BTC_RSN_NTFY_RADIO_STATE || 4302 btc->dm.run_reason == BTC_RSN_CMD_SET_COEX || wl_rinfo->dbcc_chg) 4303 force_exec = FC_EXEC; 4304 4305 if (wl_rinfo->link_mode != BTC_WLINK_25G_MCC && 4306 btc->dm.wl_btg_rx == 2) 4307 force_exec = FC_EXEC; 4308 4309 if (!force_exec && ant_path_type == dm->set_ant_path) { 4310 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4311 "[BTC], %s(): return by no change!!\n", 4312 __func__); 4313 return; 4314 } else if (bt->rfk_info.map.run) { 4315 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4316 "[BTC], %s(): return by bt rfk!!\n", __func__); 4317 return; 4318 } else if (btc->dm.run_reason != BTC_RSN_NTFY_WL_RFK && 4319 wl->rfk_info.state != BTC_WRFK_STOP) { 4320 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4321 "[BTC], %s(): return by wl rfk!!\n", __func__); 4322 return; 4323 } 4324 4325 dm->set_ant_path = ant_path_type; 4326 4327 rtw89_debug(rtwdev, RTW89_DBG_BTC, 4328 "[BTC], %s(): path=0x%x, set_type=0x%x\n", 4329 __func__, phy_map, dm->set_ant_path & 0xff); 4330 4331 switch (type) { 4332 case BTC_ANT_WINIT: 4333 /* To avoid BT MP driver case (bt_enable but no mailbox) */ 4334 if (bt->enable.now && bt->run_patch_code) 4335 _set_gnt_v1(rtwdev, phy_map, BTC_GNT_SW_LO, BTC_GNT_SW_HI, 4336 BTC_WLACT_SW_LO); 4337 else 4338 _set_gnt_v1(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_SW_LO, 4339 BTC_WLACT_SW_HI); 4340 break; 4341 case BTC_ANT_WONLY: 4342 _set_gnt_v1(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_SW_LO, 4343 BTC_WLACT_SW_HI); 4344 break; 4345 case BTC_ANT_WOFF: 4346 _set_gnt_v1(rtwdev, phy_map, BTC_GNT_SW_LO, BTC_GNT_SW_HI, 4347 BTC_WLACT_SW_LO); 4348 break; 4349 case BTC_ANT_W2G: 4350 case BTC_ANT_W25G: 4351 if (wl_rinfo->dbcc_en) { 4352 if (wl_dinfo->real_band[RTW89_PHY_0] == RTW89_BAND_2G) 4353 gwl = BTC_GNT_HW; 4354 else 4355 gwl = BTC_GNT_SW_HI; 4356 _set_gnt_v1(rtwdev, BTC_PHY_0, gwl, BTC_GNT_HW, BTC_WLACT_HW); 4357 4358 if (wl_dinfo->real_band[RTW89_PHY_1] == RTW89_BAND_2G) 4359 gwl = BTC_GNT_HW; 4360 else 4361 gwl = BTC_GNT_SW_HI; 4362 _set_gnt_v1(rtwdev, BTC_PHY_1, gwl, BTC_GNT_HW, BTC_WLACT_HW); 4363 } else { 4364 gwl = BTC_GNT_HW; 4365 _set_gnt_v1(rtwdev, phy_map, gwl, BTC_GNT_HW, BTC_WLACT_HW); 4366 } 4367 break; 4368 case BTC_ANT_W5G: 4369 _set_gnt_v1(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_HW, BTC_WLACT_HW); 4370 break; 4371 case BTC_ANT_FREERUN: 4372 _set_gnt_v1(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_SW_HI, 4373 BTC_WLACT_SW_LO); 4374 break; 4375 case BTC_ANT_WRFK: 4376 _set_gnt_v1(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_SW_LO, 4377 BTC_WLACT_HW); 4378 break; 4379 case BTC_ANT_WRFK2: 4380 _set_gnt_v1(rtwdev, phy_map, BTC_GNT_SW_HI, BTC_GNT_SW_LO, 4381 BTC_WLACT_SW_HI); /* no BT-Tx */ 4382 break; 4383 default: 4384 return; 4385 } 4386 4387 _set_bt_plut(rtwdev, phy_map, BTC_PLT_GNT_WL, BTC_PLT_GNT_WL); 4388 } 4389 4390 static void _set_ant(struct rtw89_dev *rtwdev, bool force_exec, 4391 u8 phy_map, u8 type) 4392 { 4393 if (rtwdev->chip->chip_id == RTL8922A) 4394 _set_ant_v1(rtwdev, force_exec, phy_map, type); 4395 else 4396 _set_ant_v0(rtwdev, force_exec, phy_map, type); 4397 } 4398 4399 static void _action_wl_only(struct rtw89_dev *rtwdev) 4400 { 4401 _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY); 4402 _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_ONLY); 4403 } 4404 4405 static void _action_wl_init(struct rtw89_dev *rtwdev) 4406 { 4407 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); 4408 4409 _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WINIT); 4410 _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_INIT); 4411 } 4412 4413 static void _action_wl_off(struct rtw89_dev *rtwdev, u8 mode) 4414 { 4415 struct rtw89_btc *btc = &rtwdev->btc; 4416 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 4417 4418 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); 4419 4420 if (wl->status.map.rf_off || btc->dm.bt_only) { 4421 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_WOFF); 4422 } else if (wl->status.map.lps == BTC_LPS_RF_ON) { 4423 if (mode == BTC_WLINK_5G) 4424 _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W5G); 4425 else 4426 _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4427 } 4428 4429 if (mode == BTC_WLINK_5G) { 4430 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_OFF); 4431 } else if (wl->status.map.lps == BTC_LPS_RF_ON) { 4432 if (btc->cx.bt.link_info.a2dp_desc.active) 4433 _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_OFF); 4434 else 4435 _set_policy(rtwdev, BTC_CXP_OFF_BWB1, BTC_ACT_WL_OFF); 4436 } else { 4437 _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_OFF); 4438 } 4439 } 4440 4441 static void _action_freerun(struct rtw89_dev *rtwdev) 4442 { 4443 struct rtw89_btc *btc = &rtwdev->btc; 4444 4445 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); 4446 4447 _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_FREERUN); 4448 _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_FREERUN); 4449 4450 btc->dm.freerun = true; 4451 } 4452 4453 static void _action_bt_whql(struct rtw89_dev *rtwdev) 4454 { 4455 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); 4456 4457 _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4458 _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_BT_WHQL); 4459 } 4460 4461 static void _action_bt_off(struct rtw89_dev *rtwdev) 4462 { 4463 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); 4464 4465 _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WONLY); 4466 _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_BT_OFF); 4467 } 4468 4469 static void _action_bt_idle(struct rtw89_dev *rtwdev) 4470 { 4471 struct rtw89_btc *btc = &rtwdev->btc; 4472 struct rtw89_btc_bt_link_info *b = &btc->cx.bt.link_info; 4473 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 4474 4475 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4476 4477 if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ 4478 switch (btc->cx.state_map) { 4479 case BTC_WBUSY_BNOSCAN: /*wl-busy + bt idle*/ 4480 case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-idle */ 4481 if (b->status.map.connect) 4482 _set_policy(rtwdev, BTC_CXP_FIX_TD4010, BTC_ACT_BT_IDLE); 4483 else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_DL)) 4484 _set_policy(rtwdev, BTC_CXP_FIX_TD4010ISO_DL, BTC_ACT_BT_IDLE); 4485 else 4486 _set_policy(rtwdev, BTC_CXP_FIX_TD4010ISO_UL, BTC_ACT_BT_IDLE); 4487 break; 4488 case BTC_WBUSY_BSCAN: /*wl-busy + bt-inq */ 4489 _set_policy(rtwdev, BTC_CXP_PFIX_TD5050, 4490 BTC_ACT_BT_IDLE); 4491 break; 4492 case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq */ 4493 _set_policy(rtwdev, BTC_CXP_FIX_TD5050, 4494 BTC_ACT_BT_IDLE); 4495 break; 4496 case BTC_WLINKING: /* wl-connecting + bt-inq or bt-idle */ 4497 _set_policy(rtwdev, BTC_CXP_FIX_TD7010, 4498 BTC_ACT_BT_IDLE); 4499 break; 4500 case BTC_WIDLE: /* wl-idle + bt-idle */ 4501 _set_policy(rtwdev, BTC_CXP_OFF_BWB1, BTC_ACT_BT_IDLE); 4502 break; 4503 } 4504 } else { /* dedicated-antenna */ 4505 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_BT_IDLE); 4506 } 4507 } 4508 4509 static void _action_bt_hfp(struct rtw89_dev *rtwdev) 4510 { 4511 struct rtw89_btc *btc = &rtwdev->btc; 4512 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 4513 4514 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4515 4516 if (btc->ant_type == BTC_ANT_SHARED) { 4517 if (btc->cx.wl.status.map._4way) { 4518 _set_policy(rtwdev, BTC_CXP_OFF_WL, BTC_ACT_BT_HFP); 4519 } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) { 4520 btc->cx.bt.scan_rx_low_pri = true; 4521 _set_policy(rtwdev, BTC_CXP_OFF_BWB2, BTC_ACT_BT_HFP); 4522 } else { 4523 _set_policy(rtwdev, BTC_CXP_OFF_BWB1, BTC_ACT_BT_HFP); 4524 } 4525 } else { 4526 if (wl->bg_mode) 4527 _set_policy(rtwdev, BTC_CXP_OFF_BWB1, BTC_ACT_BT_HFP); 4528 else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) 4529 _set_policy(rtwdev, BTC_CXP_OFF_EQ5, BTC_ACT_BT_HFP); 4530 else 4531 _set_policy(rtwdev, BTC_CXP_OFF_EQ2, BTC_ACT_BT_HFP); 4532 } 4533 } 4534 4535 static void _action_bt_hid(struct rtw89_dev *rtwdev) 4536 { 4537 const struct rtw89_chip_info *chip = rtwdev->chip; 4538 struct rtw89_btc *btc = &rtwdev->btc; 4539 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 4540 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 4541 struct rtw89_btc_bt_hid_desc *hid = &bt->link_info.hid_desc; 4542 u16 policy_type = BTC_CXP_OFF_BT; 4543 4544 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4545 4546 if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ 4547 if (wl->status.map._4way) { 4548 policy_type = BTC_CXP_OFF_WL; 4549 } else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) { 4550 btc->cx.bt.scan_rx_low_pri = true; 4551 if (hid->type & BTC_HID_BLE) 4552 policy_type = BTC_CXP_OFF_BWB0; 4553 else 4554 policy_type = BTC_CXP_OFF_BWB2; 4555 } else if (hid->type == BTC_HID_218) { 4556 bt->scan_rx_low_pri = true; 4557 policy_type = BTC_CXP_OFF_BWB2; 4558 } else if (chip->para_ver == 0x1) { 4559 policy_type = BTC_CXP_OFF_BWB3; 4560 } else { 4561 policy_type = BTC_CXP_OFF_BWB1; 4562 } 4563 } else { /* dedicated-antenna */ 4564 if (wl->bg_mode) 4565 policy_type = BTC_CXP_OFF_BWB1; 4566 else if (wl->status.map.traffic_dir & BIT(RTW89_TFC_UL)) 4567 policy_type = BTC_CXP_OFF_EQ4; 4568 else 4569 policy_type = BTC_CXP_OFF_EQ3; 4570 } 4571 4572 _set_policy(rtwdev, policy_type, BTC_ACT_BT_HID); 4573 } 4574 4575 static void _action_bt_a2dp(struct rtw89_dev *rtwdev) 4576 { 4577 struct rtw89_btc *btc = &rtwdev->btc; 4578 struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; 4579 struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; 4580 struct rtw89_btc_dm *dm = &btc->dm; 4581 4582 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4583 4584 switch (btc->cx.state_map) { 4585 case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP */ 4586 if (a2dp.vendor_id == 0x4c || dm->leak_ap) { 4587 dm->slot_dur[CXST_W1] = 40; 4588 dm->slot_dur[CXST_B1] = 200; 4589 _set_policy(rtwdev, 4590 BTC_CXP_PAUTO_TDW1B1, BTC_ACT_BT_A2DP); 4591 } else { 4592 _set_policy(rtwdev, 4593 BTC_CXP_PAUTO_TD50B1, BTC_ACT_BT_A2DP); 4594 } 4595 break; 4596 case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP */ 4597 _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3050, BTC_ACT_BT_A2DP); 4598 break; 4599 case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP */ 4600 _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, BTC_ACT_BT_A2DP); 4601 break; 4602 case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP */ 4603 case BTC_WLINKING: /* wl-connecting + bt-A2DP */ 4604 if (a2dp.vendor_id == 0x4c || dm->leak_ap) { 4605 dm->slot_dur[CXST_W1] = 40; 4606 dm->slot_dur[CXST_B1] = 200; 4607 _set_policy(rtwdev, BTC_CXP_AUTO_TDW1B1, 4608 BTC_ACT_BT_A2DP); 4609 } else { 4610 _set_policy(rtwdev, BTC_CXP_AUTO_TD50B1, 4611 BTC_ACT_BT_A2DP); 4612 } 4613 break; 4614 case BTC_WIDLE: /* wl-idle + bt-A2DP */ 4615 _set_policy(rtwdev, BTC_CXP_AUTO_TD20B1, BTC_ACT_BT_A2DP); 4616 break; 4617 } 4618 } 4619 4620 static void _action_bt_a2dpsink(struct rtw89_dev *rtwdev) 4621 { 4622 struct rtw89_btc *btc = &rtwdev->btc; 4623 4624 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4625 4626 switch (btc->cx.state_map) { 4627 case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2dp_Sink */ 4628 _set_policy(rtwdev, BTC_CXP_PFIX_TD2030, BTC_ACT_BT_A2DPSINK); 4629 break; 4630 case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2dp_Sink */ 4631 _set_policy(rtwdev, BTC_CXP_PFIX_TD2060, BTC_ACT_BT_A2DPSINK); 4632 break; 4633 case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2dp_Sink */ 4634 _set_policy(rtwdev, BTC_CXP_FIX_TD2030, BTC_ACT_BT_A2DPSINK); 4635 break; 4636 case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2dp_Sink */ 4637 _set_policy(rtwdev, BTC_CXP_FIX_TD2060, BTC_ACT_BT_A2DPSINK); 4638 break; 4639 case BTC_WLINKING: /* wl-connecting + bt-A2dp_Sink */ 4640 _set_policy(rtwdev, BTC_CXP_FIX_TD3030, BTC_ACT_BT_A2DPSINK); 4641 break; 4642 case BTC_WIDLE: /* wl-idle + bt-A2dp_Sink */ 4643 _set_policy(rtwdev, BTC_CXP_FIX_TD2080, BTC_ACT_BT_A2DPSINK); 4644 break; 4645 } 4646 } 4647 4648 static void _action_bt_pan(struct rtw89_dev *rtwdev) 4649 { 4650 struct rtw89_btc *btc = &rtwdev->btc; 4651 struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; 4652 struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; 4653 struct rtw89_btc_bt_pan_desc pan = bt_linfo->pan_desc; 4654 4655 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4656 4657 switch (btc->cx.state_map) { 4658 case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN */ 4659 if (a2dp.active || !pan.exist) { 4660 btc->dm.slot_dur[CXST_W1] = 80; 4661 btc->dm.slot_dur[CXST_B1] = 20; 4662 _set_policy(rtwdev, BTC_CXP_PFIX_TDW1B1, BTC_ACT_BT_PAN); 4663 } else { 4664 _set_policy(rtwdev, BTC_CXP_PFIX_TD5050, BTC_ACT_BT_PAN); 4665 } 4666 break; 4667 case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN */ 4668 _set_policy(rtwdev, BTC_CXP_PFIX_TD3070, BTC_ACT_BT_PAN); 4669 break; 4670 case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN */ 4671 _set_policy(rtwdev, BTC_CXP_FIX_TD3030, BTC_ACT_BT_PAN); 4672 break; 4673 case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN */ 4674 _set_policy(rtwdev, BTC_CXP_FIX_TD3060, BTC_ACT_BT_PAN); 4675 break; 4676 case BTC_WLINKING: /* wl-connecting + bt-PAN */ 4677 _set_policy(rtwdev, BTC_CXP_FIX_TD4010ISO, BTC_ACT_BT_PAN); 4678 break; 4679 case BTC_WIDLE: /* wl-idle + bt-pan */ 4680 _set_policy(rtwdev, BTC_CXP_PFIX_TD2080, BTC_ACT_BT_PAN); 4681 break; 4682 } 4683 } 4684 4685 static void _action_bt_a2dp_hid(struct rtw89_dev *rtwdev) 4686 { 4687 struct rtw89_btc *btc = &rtwdev->btc; 4688 struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; 4689 struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; 4690 struct rtw89_btc_dm *dm = &btc->dm; 4691 4692 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4693 4694 switch (btc->cx.state_map) { 4695 case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+HID */ 4696 case BTC_WIDLE: /* wl-idle + bt-A2DP */ 4697 if (a2dp.vendor_id == 0x4c || dm->leak_ap) { 4698 dm->slot_dur[CXST_W1] = 40; 4699 dm->slot_dur[CXST_B1] = 200; 4700 _set_policy(rtwdev, 4701 BTC_CXP_PAUTO_TDW1B1, BTC_ACT_BT_A2DP_HID); 4702 } else { 4703 _set_policy(rtwdev, 4704 BTC_CXP_PAUTO_TD50B1, BTC_ACT_BT_A2DP_HID); 4705 } 4706 break; 4707 case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+HID */ 4708 _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3050, BTC_ACT_BT_A2DP_HID); 4709 break; 4710 4711 case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+HID */ 4712 _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, BTC_ACT_BT_A2DP_HID); 4713 break; 4714 case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+HID */ 4715 case BTC_WLINKING: /* wl-connecting + bt-A2DP+HID */ 4716 if (a2dp.vendor_id == 0x4c || dm->leak_ap) { 4717 dm->slot_dur[CXST_W1] = 40; 4718 dm->slot_dur[CXST_B1] = 200; 4719 _set_policy(rtwdev, BTC_CXP_AUTO_TDW1B1, 4720 BTC_ACT_BT_A2DP_HID); 4721 } else { 4722 _set_policy(rtwdev, BTC_CXP_AUTO_TD50B1, 4723 BTC_ACT_BT_A2DP_HID); 4724 } 4725 break; 4726 } 4727 } 4728 4729 static void _action_bt_a2dp_pan(struct rtw89_dev *rtwdev) 4730 { 4731 struct rtw89_btc *btc = &rtwdev->btc; 4732 4733 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4734 4735 switch (btc->cx.state_map) { 4736 case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN */ 4737 _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, BTC_ACT_BT_A2DP_PAN); 4738 break; 4739 case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN */ 4740 _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, BTC_ACT_BT_A2DP_PAN); 4741 break; 4742 case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN */ 4743 _set_policy(rtwdev, BTC_CXP_AUTO2_TD5050, BTC_ACT_BT_A2DP_PAN); 4744 break; 4745 case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN */ 4746 _set_policy(rtwdev, BTC_CXP_AUTO2_TD3070, BTC_ACT_BT_A2DP_PAN); 4747 break; 4748 case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN */ 4749 _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, BTC_ACT_BT_A2DP_PAN); 4750 break; 4751 case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN */ 4752 _set_policy(rtwdev, BTC_CXP_PAUTO2_TD2080, BTC_ACT_BT_A2DP_PAN); 4753 break; 4754 } 4755 } 4756 4757 static void _action_bt_pan_hid(struct rtw89_dev *rtwdev) 4758 { 4759 struct rtw89_btc *btc = &rtwdev->btc; 4760 4761 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4762 4763 switch (btc->cx.state_map) { 4764 case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-PAN+HID */ 4765 _set_policy(rtwdev, BTC_CXP_PFIX_TD3030, BTC_ACT_BT_PAN_HID); 4766 break; 4767 case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-PAN+HID */ 4768 _set_policy(rtwdev, BTC_CXP_PFIX_TD3070, BTC_ACT_BT_PAN_HID); 4769 break; 4770 case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-PAN+HID */ 4771 _set_policy(rtwdev, BTC_CXP_FIX_TD3030, BTC_ACT_BT_PAN_HID); 4772 break; 4773 case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-PAN+HID */ 4774 _set_policy(rtwdev, BTC_CXP_FIX_TD3060, BTC_ACT_BT_PAN_HID); 4775 break; 4776 case BTC_WLINKING: /* wl-connecting + bt-PAN+HID */ 4777 _set_policy(rtwdev, BTC_CXP_FIX_TD4010, BTC_ACT_BT_PAN_HID); 4778 break; 4779 case BTC_WIDLE: /* wl-idle + bt-PAN+HID */ 4780 _set_policy(rtwdev, BTC_CXP_PFIX_TD2080, BTC_ACT_BT_PAN_HID); 4781 break; 4782 } 4783 } 4784 4785 static void _action_bt_a2dp_pan_hid(struct rtw89_dev *rtwdev) 4786 { 4787 struct rtw89_btc *btc = &rtwdev->btc; 4788 4789 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4790 4791 switch (btc->cx.state_map) { 4792 case BTC_WBUSY_BNOSCAN: /* wl-busy + bt-A2DP+PAN+HID */ 4793 _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, 4794 BTC_ACT_BT_A2DP_PAN_HID); 4795 break; 4796 case BTC_WBUSY_BSCAN: /* wl-busy + bt-inq + bt-A2DP+PAN+HID */ 4797 _set_policy(rtwdev, BTC_CXP_PAUTO2_TD3070, 4798 BTC_ACT_BT_A2DP_PAN_HID); 4799 break; 4800 case BTC_WSCAN_BSCAN: /* wl-scan + bt-inq + bt-A2DP+PAN+HID */ 4801 _set_policy(rtwdev, BTC_CXP_AUTO2_TD3070, 4802 BTC_ACT_BT_A2DP_PAN_HID); 4803 break; 4804 case BTC_WSCAN_BNOSCAN: /* wl-scan + bt-A2DP+PAN+HID */ 4805 case BTC_WLINKING: /* wl-connecting + bt-A2DP+PAN+HID */ 4806 _set_policy(rtwdev, BTC_CXP_AUTO2_TD3050, 4807 BTC_ACT_BT_A2DP_PAN_HID); 4808 break; 4809 case BTC_WIDLE: /* wl-idle + bt-A2DP+PAN+HID */ 4810 _set_policy(rtwdev, BTC_CXP_PAUTO2_TD2080, 4811 BTC_ACT_BT_A2DP_PAN_HID); 4812 break; 4813 } 4814 } 4815 4816 static void _action_wl_5g(struct rtw89_dev *rtwdev) 4817 { 4818 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W5G); 4819 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_5G); 4820 } 4821 4822 static void _action_wl_other(struct rtw89_dev *rtwdev) 4823 { 4824 struct rtw89_btc *btc = &rtwdev->btc; 4825 4826 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4827 4828 if (btc->ant_type == BTC_ANT_SHARED) 4829 _set_policy(rtwdev, BTC_CXP_OFFB_BWB0, BTC_ACT_WL_OTHER); 4830 else 4831 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_OTHER); 4832 } 4833 4834 static void _action_wl_nc(struct rtw89_dev *rtwdev) 4835 { 4836 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 4837 _set_policy(rtwdev, BTC_CXP_OFF_BT, BTC_ACT_WL_NC); 4838 } 4839 4840 static void _action_wl_rfk(struct rtw89_dev *rtwdev) 4841 { 4842 struct rtw89_btc *btc = &rtwdev->btc; 4843 struct rtw89_btc_wl_rfk_info rfk = btc->cx.wl.rfk_info; 4844 4845 if (rfk.state != BTC_WRFK_START) 4846 return; 4847 4848 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): band = %d\n", 4849 __func__, rfk.band); 4850 4851 btc->dm.tdma_instant_excute = 1; 4852 4853 if (rfk.state == BTC_WRFK_ONESHOT_START || 4854 btc->ant_type == BTC_ANT_SHARED) { 4855 _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WRFK2); 4856 _set_policy(rtwdev, BTC_CXP_OFF_WL2, BTC_ACT_WL_RFK); 4857 } else { 4858 _set_ant(rtwdev, FC_EXEC, BTC_PHY_ALL, BTC_ANT_WRFK); 4859 _set_policy(rtwdev, BTC_CXP_OFF_WL, BTC_ACT_WL_RFK); 4860 } 4861 } 4862 4863 static void _set_btg_ctrl(struct rtw89_dev *rtwdev) 4864 { 4865 struct rtw89_btc *btc = &rtwdev->btc; 4866 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 4867 struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; 4868 struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; 4869 struct rtw89_btc_wl_role_info_v7 *wl_rinfo_v7 = &wl->role_info_v7; 4870 struct rtw89_btc_wl_role_info_v8 *wl_rinfo_v8 = &wl->role_info_v8; 4871 struct rtw89_btc_wl_role_info *wl_rinfo_v0 = &wl->role_info; 4872 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 4873 const struct rtw89_chip_info *chip = rtwdev->chip; 4874 const struct rtw89_btc_ver *ver = btc->ver; 4875 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 4876 struct rtw89_btc_dm *dm = &btc->dm; 4877 struct _wl_rinfo_now wl_rinfo; 4878 u32 run_reason = btc->dm.run_reason; 4879 u32 is_btg; 4880 u8 i, val; 4881 4882 if (btc->manual_ctrl) 4883 return; 4884 4885 if (ver->fwlrole == 0) 4886 wl_rinfo.link_mode = wl_rinfo_v0->link_mode; 4887 else if (ver->fwlrole == 1) 4888 wl_rinfo.link_mode = wl_rinfo_v1->link_mode; 4889 else if (ver->fwlrole == 2) 4890 wl_rinfo.link_mode = wl_rinfo_v2->link_mode; 4891 else if (ver->fwlrole == 7) 4892 wl_rinfo.link_mode = wl_rinfo_v7->link_mode; 4893 else if (ver->fwlrole == 8) 4894 wl_rinfo.link_mode = wl_rinfo_v8->link_mode; 4895 else 4896 return; 4897 4898 if (rtwdev->dbcc_en) { 4899 if (ver->fwlrole == 0) { 4900 wl_rinfo.dbcc_2g_phy = RTW89_PHY_MAX; 4901 4902 for (i = 0; i < RTW89_PHY_MAX; i++) { 4903 if (wl_dinfo->real_band[i] == RTW89_BAND_2G) 4904 wl_rinfo.dbcc_2g_phy = i; 4905 } 4906 } else if (ver->fwlrole == 1) { 4907 wl_rinfo.dbcc_2g_phy = wl_rinfo_v1->dbcc_2g_phy; 4908 } else if (ver->fwlrole == 2) { 4909 wl_rinfo.dbcc_2g_phy = wl_rinfo_v2->dbcc_2g_phy; 4910 } else if (ver->fwlrole == 7) { 4911 wl_rinfo.dbcc_2g_phy = wl_rinfo_v7->dbcc_2g_phy; 4912 } else if (ver->fwlrole == 8) { 4913 wl_rinfo.dbcc_2g_phy = wl_rinfo_v8->dbcc_2g_phy; 4914 } else { 4915 return; 4916 } 4917 } 4918 4919 if (wl_rinfo.link_mode == BTC_WLINK_25G_MCC) 4920 is_btg = BTC_BTGCTRL_BB_GNT_FWCTRL; 4921 else if (!(bt->run_patch_code && bt->enable.now)) 4922 is_btg = BTC_BTGCTRL_DISABLE; 4923 else if (wl_rinfo.link_mode == BTC_WLINK_5G) 4924 is_btg = BTC_BTGCTRL_DISABLE; 4925 else if (dm->freerun) 4926 is_btg = BTC_BTGCTRL_DISABLE; 4927 else if (rtwdev->dbcc_en && wl_rinfo.dbcc_2g_phy != RTW89_PHY_1) 4928 is_btg = BTC_BTGCTRL_DISABLE; 4929 else 4930 is_btg = BTC_BTGCTRL_ENABLE; 4931 4932 if (dm->wl_btg_rx_rb != dm->wl_btg_rx && 4933 dm->wl_btg_rx_rb != BTC_BTGCTRL_BB_GNT_NOTFOUND) { 4934 _get_reg_status(rtwdev, BTC_CSTATUS_BB_GNT_MUX, &val); 4935 dm->wl_btg_rx_rb = val; 4936 } 4937 4938 if (run_reason == BTC_RSN_NTFY_INIT || 4939 run_reason == BTC_RSN_NTFY_SWBAND || 4940 dm->wl_btg_rx_rb != dm->wl_btg_rx || 4941 is_btg != dm->wl_btg_rx) { 4942 4943 dm->wl_btg_rx = is_btg; 4944 4945 if (is_btg > BTC_BTGCTRL_ENABLE) 4946 return; 4947 4948 chip->ops->ctrl_btg_bt_rx(rtwdev, is_btg, RTW89_PHY_0); 4949 } 4950 } 4951 4952 static void _set_wl_preagc_ctrl(struct rtw89_dev *rtwdev) 4953 { 4954 struct rtw89_btc *btc = &rtwdev->btc; 4955 struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; 4956 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 4957 struct rtw89_btc_wl_role_info_v2 *rinfo_v2 = &wl->role_info_v2; 4958 struct rtw89_btc_wl_role_info_v7 *rinfo_v7 = &wl->role_info_v7; 4959 struct rtw89_btc_wl_role_info_v8 *rinfo_v8 = &wl->role_info_v8; 4960 const struct rtw89_chip_info *chip = rtwdev->chip; 4961 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 4962 struct rtw89_btc_dm *dm = &btc->dm; 4963 u8 is_preagc, val, link_mode, dbcc_2g_phy; 4964 u8 role_ver = rtwdev->btc.ver->fwlrole; 4965 bool dbcc_en; 4966 4967 if (btc->manual_ctrl) 4968 return; 4969 4970 if (role_ver == 2) { 4971 dbcc_en = rinfo_v2->dbcc_en; 4972 link_mode = rinfo_v2->link_mode; 4973 dbcc_2g_phy = rinfo_v2->dbcc_2g_phy; 4974 } else if (role_ver == 7) { 4975 dbcc_en = rinfo_v7->dbcc_en; 4976 link_mode = rinfo_v7->link_mode; 4977 dbcc_2g_phy = rinfo_v7->dbcc_2g_phy; 4978 } else if (role_ver == 8) { 4979 dbcc_en = rinfo_v8->dbcc_en; 4980 link_mode = rinfo_v8->link_mode; 4981 dbcc_2g_phy = rinfo_v7->dbcc_2g_phy; 4982 } else { 4983 return; 4984 } 4985 4986 if (link_mode == BTC_WLINK_25G_MCC) { 4987 is_preagc = BTC_PREAGC_BB_FWCTRL; 4988 } else if (!(bt->run_patch_code && bt->enable.now)) { 4989 is_preagc = BTC_PREAGC_DISABLE; 4990 } else if (link_mode == BTC_WLINK_5G) { 4991 is_preagc = BTC_PREAGC_DISABLE; 4992 } else if (link_mode == BTC_WLINK_NOLINK || 4993 btc->cx.bt.link_info.profile_cnt.now == 0) { 4994 is_preagc = BTC_PREAGC_DISABLE; 4995 } else if (dm->tdma_now.type != CXTDMA_OFF && 4996 !bt_linfo->hfp_desc.exist && 4997 !bt_linfo->hid_desc.exist && 4998 dm->fddt_train == BTC_FDDT_DISABLE) { 4999 is_preagc = BTC_PREAGC_DISABLE; 5000 } else if (dbcc_en && (dbcc_2g_phy != RTW89_PHY_1)) { 5001 is_preagc = BTC_PREAGC_DISABLE; 5002 } else if (btc->ant_type == BTC_ANT_SHARED) { 5003 is_preagc = BTC_PREAGC_DISABLE; 5004 } else { 5005 is_preagc = BTC_PREAGC_ENABLE; 5006 } 5007 5008 if (dm->wl_pre_agc_rb != dm->wl_pre_agc && 5009 dm->wl_pre_agc_rb != BTC_PREAGC_NOTFOUND) { 5010 _get_reg_status(rtwdev, BTC_CSTATUS_BB_PRE_AGC, &val); 5011 dm->wl_pre_agc_rb = val; 5012 } 5013 5014 if ((wl->coex_mode == BTC_MODE_NORMAL && 5015 (dm->run_reason == BTC_RSN_NTFY_INIT || 5016 dm->run_reason == BTC_RSN_NTFY_SWBAND || 5017 dm->wl_pre_agc_rb != dm->wl_pre_agc)) || 5018 is_preagc != dm->wl_pre_agc) { 5019 dm->wl_pre_agc = is_preagc; 5020 5021 if (is_preagc > BTC_PREAGC_ENABLE) 5022 return; 5023 chip->ops->ctrl_nbtg_bt_tx(rtwdev, dm->wl_pre_agc, RTW89_PHY_0); 5024 } 5025 } 5026 5027 struct rtw89_txtime_data { 5028 struct rtw89_dev *rtwdev; 5029 int type; 5030 u32 tx_time; 5031 u8 tx_retry; 5032 u16 enable; 5033 bool reenable; 5034 }; 5035 5036 static void __rtw89_tx_time_iter(struct rtw89_vif_link *rtwvif_link, 5037 struct rtw89_sta_link *rtwsta_link, 5038 struct rtw89_txtime_data *iter_data) 5039 { 5040 struct rtw89_dev *rtwdev = iter_data->rtwdev; 5041 struct rtw89_btc *btc = &rtwdev->btc; 5042 struct rtw89_btc_cx *cx = &btc->cx; 5043 struct rtw89_btc_wl_info *wl = &cx->wl; 5044 struct rtw89_btc_wl_link_info *plink = NULL; 5045 u8 port = rtwvif_link->port; 5046 u32 tx_time = iter_data->tx_time; 5047 u8 tx_retry = iter_data->tx_retry; 5048 u16 enable = iter_data->enable; 5049 bool reenable = iter_data->reenable; 5050 5051 if (btc->ver->fwlrole == 8) 5052 plink = &wl->rlink_info[port][0]; 5053 else 5054 plink = &wl->link_info[port]; 5055 5056 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5057 "[BTC], %s(): port = %d\n", __func__, port); 5058 5059 if (!plink->connected) { 5060 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5061 "[BTC], %s(): connected = %d\n", 5062 __func__, plink->connected); 5063 return; 5064 } 5065 5066 /* backup the original tx time before tx-limit on */ 5067 if (reenable) { 5068 rtw89_mac_get_tx_time(rtwdev, rtwsta_link, &plink->tx_time); 5069 rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta_link, &plink->tx_retry); 5070 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5071 "[BTC], %s(): reenable, tx_time=%d tx_retry= %d\n", 5072 __func__, plink->tx_time, plink->tx_retry); 5073 } 5074 5075 /* restore the original tx time if no tx-limit */ 5076 if (!enable) { 5077 rtw89_mac_set_tx_time(rtwdev, rtwsta_link, true, plink->tx_time); 5078 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, true, 5079 plink->tx_retry); 5080 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5081 "[BTC], %s(): restore, tx_time=%d tx_retry= %d\n", 5082 __func__, plink->tx_time, plink->tx_retry); 5083 5084 } else { 5085 rtw89_mac_set_tx_time(rtwdev, rtwsta_link, false, tx_time); 5086 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, tx_retry); 5087 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5088 "[BTC], %s(): set, tx_time=%d tx_retry= %d\n", 5089 __func__, tx_time, tx_retry); 5090 } 5091 } 5092 5093 static void rtw89_tx_time_iter(void *data, struct ieee80211_sta *sta) 5094 { 5095 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 5096 struct rtw89_txtime_data *iter_data = 5097 (struct rtw89_txtime_data *)data; 5098 struct rtw89_vif_link *rtwvif_link; 5099 struct rtw89_sta_link *rtwsta_link; 5100 unsigned int link_id; 5101 5102 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 5103 rtwvif_link = rtwsta_link->rtwvif_link; 5104 __rtw89_tx_time_iter(rtwvif_link, rtwsta_link, iter_data); 5105 } 5106 } 5107 5108 static void _set_wl_tx_limit(struct rtw89_dev *rtwdev) 5109 { 5110 struct rtw89_btc *btc = &rtwdev->btc; 5111 const struct rtw89_btc_ver *ver = btc->ver; 5112 struct rtw89_btc_cx *cx = &btc->cx; 5113 struct rtw89_btc_dm *dm = &btc->dm; 5114 struct rtw89_btc_wl_info *wl = &cx->wl; 5115 struct rtw89_btc_bt_info *bt = &cx->bt; 5116 struct rtw89_btc_bt_link_info *b = &bt->link_info; 5117 struct rtw89_btc_bt_hfp_desc *hfp = &b->hfp_desc; 5118 struct rtw89_btc_bt_hid_desc *hid = &b->hid_desc; 5119 struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; 5120 struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; 5121 struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; 5122 struct rtw89_btc_wl_role_info_v7 *wl_rinfo_v7 = &wl->role_info_v7; 5123 struct rtw89_btc_wl_role_info_v8 *wl_rinfo_v8 = &wl->role_info_v8; 5124 struct rtw89_txtime_data data = {.rtwdev = rtwdev}; 5125 u8 mode, igno_bt, tx_retry; 5126 u32 tx_time; 5127 u16 enable; 5128 bool reenable = false; 5129 5130 if (btc->manual_ctrl) 5131 return; 5132 5133 if (ver->fwlrole == 0) 5134 mode = wl_rinfo->link_mode; 5135 else if (ver->fwlrole == 1) 5136 mode = wl_rinfo_v1->link_mode; 5137 else if (ver->fwlrole == 2) 5138 mode = wl_rinfo_v2->link_mode; 5139 else if (ver->fwlrole == 7) 5140 mode = wl_rinfo_v7->link_mode; 5141 else if (ver->fwlrole == 8) 5142 mode = wl_rinfo_v8->link_mode; 5143 else 5144 return; 5145 5146 if (ver->fcxctrl == 7) 5147 igno_bt = btc->ctrl.ctrl_v7.igno_bt; 5148 else 5149 igno_bt = btc->ctrl.ctrl.igno_bt; 5150 5151 if (btc->dm.freerun || igno_bt || b->profile_cnt.now == 0 || 5152 mode == BTC_WLINK_5G || mode == BTC_WLINK_NOLINK) { 5153 enable = 0; 5154 tx_time = BTC_MAX_TX_TIME_DEF; 5155 tx_retry = BTC_MAX_TX_RETRY_DEF; 5156 } else if ((hfp->exist && hid->exist) || hid->pair_cnt > 1) { 5157 enable = 1; 5158 tx_time = BTC_MAX_TX_TIME_L2; 5159 tx_retry = BTC_MAX_TX_RETRY_L1; 5160 } else if (hfp->exist || hid->exist) { 5161 enable = 1; 5162 tx_time = BTC_MAX_TX_TIME_L3; 5163 tx_retry = BTC_MAX_TX_RETRY_L1; 5164 } else { 5165 enable = 0; 5166 tx_time = BTC_MAX_TX_TIME_DEF; 5167 tx_retry = BTC_MAX_TX_RETRY_DEF; 5168 } 5169 5170 if (dm->wl_tx_limit.enable == enable && 5171 dm->wl_tx_limit.tx_time == tx_time && 5172 dm->wl_tx_limit.tx_retry == tx_retry) 5173 return; 5174 5175 if (!dm->wl_tx_limit.enable && enable) 5176 reenable = true; 5177 5178 dm->wl_tx_limit.enable = enable; 5179 dm->wl_tx_limit.tx_time = tx_time; 5180 dm->wl_tx_limit.tx_retry = tx_retry; 5181 5182 data.enable = enable; 5183 data.tx_time = tx_time; 5184 data.tx_retry = tx_retry; 5185 data.reenable = reenable; 5186 5187 ieee80211_iterate_stations_atomic(rtwdev->hw, 5188 rtw89_tx_time_iter, 5189 &data); 5190 } 5191 5192 static void _set_bt_rx_agc(struct rtw89_dev *rtwdev) 5193 { 5194 struct rtw89_btc *btc = &rtwdev->btc; 5195 const struct rtw89_btc_ver *ver = btc->ver; 5196 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 5197 struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; 5198 struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; 5199 struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; 5200 struct rtw89_btc_wl_role_info_v7 *wl_rinfo_v7 = &wl->role_info_v7; 5201 struct rtw89_btc_wl_role_info_v8 *wl_rinfo_v8 = &wl->role_info_v8; 5202 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 5203 bool bt_hi_lna_rx = false; 5204 u8 mode; 5205 5206 if (ver->fwlrole == 0) 5207 mode = wl_rinfo->link_mode; 5208 else if (ver->fwlrole == 1) 5209 mode = wl_rinfo_v1->link_mode; 5210 else if (ver->fwlrole == 2) 5211 mode = wl_rinfo_v2->link_mode; 5212 else if (ver->fwlrole == 7) 5213 mode = wl_rinfo_v7->link_mode; 5214 else if (ver->fwlrole == 8) 5215 mode = wl_rinfo_v8->link_mode; 5216 else 5217 return; 5218 5219 if (mode != BTC_WLINK_NOLINK && btc->dm.wl_btg_rx) 5220 bt_hi_lna_rx = true; 5221 5222 if (bt_hi_lna_rx == bt->hi_lna_rx) 5223 return; 5224 5225 _write_scbd(rtwdev, BTC_WSCB_BT_HILNA, bt_hi_lna_rx); 5226 } 5227 5228 static void _set_bt_rx_scan_pri(struct rtw89_dev *rtwdev) 5229 { 5230 struct rtw89_btc *btc = &rtwdev->btc; 5231 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 5232 5233 _write_scbd(rtwdev, BTC_WSCB_RXSCAN_PRI, (bool)(!!bt->scan_rx_low_pri)); 5234 } 5235 5236 static void _action_common(struct rtw89_dev *rtwdev) 5237 { 5238 struct rtw89_btc *btc = &rtwdev->btc; 5239 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 5240 struct rtw89_btc_wl_smap *wl_smap = &wl->status.map; 5241 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 5242 struct rtw89_btc_dm *dm = &btc->dm; 5243 u32 bt_rom_code_id, bt_fw_ver; 5244 5245 _set_btg_ctrl(rtwdev); 5246 _set_wl_preagc_ctrl(rtwdev); 5247 _set_wl_tx_limit(rtwdev); 5248 _set_bt_afh_info(rtwdev); 5249 _set_bt_rx_agc(rtwdev); 5250 _set_rf_trx_para(rtwdev); 5251 _set_bt_rx_scan_pri(rtwdev); 5252 5253 bt_rom_code_id = chip_id_to_bt_rom_code_id(rtwdev->btc.ver->chip_id); 5254 bt_fw_ver = bt->ver_info.fw & 0xffff; 5255 if (bt->enable.now && 5256 (bt_fw_ver == 0 || 5257 (bt_fw_ver == bt_rom_code_id && bt->run_patch_code && rtwdev->chip->scbd))) 5258 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_VER_INFO, 1); 5259 else 5260 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_VER_INFO, 0); 5261 5262 if (dm->run_reason == BTC_RSN_NTFY_INIT || 5263 dm->run_reason == BTC_RSN_NTFY_RADIO_STATE || 5264 dm->run_reason == BTC_RSN_NTFY_POWEROFF) { 5265 _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); 5266 5267 if (wl_smap->rf_off == 1 || wl_smap->lps != BTC_LPS_OFF) 5268 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_ALL, 0); 5269 else 5270 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_MREG, 1); 5271 } 5272 5273 if (wl->scbd_change) { 5274 rtw89_mac_cfg_sb(rtwdev, wl->scbd); 5275 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], write scbd: 0x%08x\n", 5276 wl->scbd); 5277 wl->scbd_change = false; 5278 btc->cx.cnt_wl[BTC_WCNT_SCBDUPDATE]++; 5279 } 5280 btc->dm.tdma_instant_excute = 0; 5281 } 5282 5283 static void _action_by_bt(struct rtw89_dev *rtwdev) 5284 { 5285 struct rtw89_btc *btc = &rtwdev->btc; 5286 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 5287 struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; 5288 struct rtw89_btc_bt_hid_desc hid = bt_linfo->hid_desc; 5289 struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; 5290 struct rtw89_btc_bt_pan_desc pan = bt_linfo->pan_desc; 5291 struct rtw89_btc_dm *dm = &btc->dm; 5292 u8 profile_map = 0; 5293 5294 if (dm->freerun_chk) { 5295 _action_freerun(rtwdev); 5296 return; 5297 } 5298 5299 if (bt_linfo->hfp_desc.exist) 5300 profile_map |= BTC_BT_HFP; 5301 5302 if (bt_linfo->hid_desc.exist) 5303 profile_map |= BTC_BT_HID; 5304 5305 if (bt_linfo->a2dp_desc.exist) 5306 profile_map |= BTC_BT_A2DP; 5307 5308 if (bt_linfo->pan_desc.exist) 5309 profile_map |= BTC_BT_PAN; 5310 5311 switch (profile_map) { 5312 case BTC_BT_NOPROFILE: 5313 if (pan.active) 5314 _action_bt_pan(rtwdev); 5315 else 5316 _action_bt_idle(rtwdev); 5317 break; 5318 case BTC_BT_HFP: 5319 _action_bt_hfp(rtwdev); 5320 break; 5321 case BTC_BT_HFP | BTC_BT_HID: 5322 case BTC_BT_HID: 5323 _action_bt_hid(rtwdev); 5324 break; 5325 case BTC_BT_A2DP: 5326 if (a2dp.sink) 5327 _action_bt_a2dpsink(rtwdev); 5328 else if (bt_linfo->multi_link.now && !hid.pair_cnt) 5329 _action_bt_a2dp_pan(rtwdev); 5330 else 5331 _action_bt_a2dp(rtwdev); 5332 break; 5333 case BTC_BT_PAN: 5334 _action_bt_pan(rtwdev); 5335 break; 5336 case BTC_BT_A2DP | BTC_BT_HFP: 5337 case BTC_BT_A2DP | BTC_BT_HID: 5338 case BTC_BT_A2DP | BTC_BT_HFP | BTC_BT_HID: 5339 if (a2dp.sink) 5340 _action_bt_a2dpsink(rtwdev); 5341 else if (pan.active) 5342 _action_bt_a2dp_pan_hid(rtwdev); 5343 else 5344 _action_bt_a2dp_hid(rtwdev); 5345 break; 5346 case BTC_BT_A2DP | BTC_BT_PAN: 5347 if (a2dp.sink) 5348 _action_bt_a2dpsink(rtwdev); 5349 else 5350 _action_bt_a2dp_pan(rtwdev); 5351 break; 5352 case BTC_BT_PAN | BTC_BT_HFP: 5353 case BTC_BT_PAN | BTC_BT_HID: 5354 case BTC_BT_PAN | BTC_BT_HFP | BTC_BT_HID: 5355 _action_bt_pan_hid(rtwdev); 5356 break; 5357 case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HID: 5358 case BTC_BT_A2DP | BTC_BT_PAN | BTC_BT_HFP: 5359 default: 5360 if (a2dp.sink) 5361 _action_bt_a2dpsink(rtwdev); 5362 else 5363 _action_bt_a2dp_pan_hid(rtwdev); 5364 break; 5365 } 5366 } 5367 5368 static void _action_wl_2g_sta(struct rtw89_dev *rtwdev) 5369 { 5370 _action_by_bt(rtwdev); 5371 } 5372 5373 static void _action_wl_25g_mcc(struct rtw89_dev *rtwdev) 5374 { 5375 struct rtw89_btc *btc = &rtwdev->btc; 5376 u16 policy_type = BTC_CXP_OFF_BT; 5377 5378 if (btc->ant_type == BTC_ANT_SHARED) { 5379 if (btc->cx.wl.status.map._4way) 5380 policy_type = BTC_CXP_OFFE_WL; 5381 else if (btc->cx.wl.status.val & btc_scanning_map.val) 5382 policy_type = BTC_CXP_OFFE_2GBWMIXB; 5383 else if (btc->cx.bt.link_info.status.map.connect == 0) 5384 policy_type = BTC_CXP_OFFE_2GISOB; 5385 else 5386 policy_type = BTC_CXP_OFFE_2GBWISOB; 5387 } else { /* dedicated-antenna */ 5388 policy_type = BTC_CXP_OFF_EQ0; 5389 } 5390 5391 btc->dm.e2g_slot_limit = BTC_E2G_LIMIT_DEF; 5392 5393 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W25G); 5394 _set_policy(rtwdev, policy_type, BTC_ACT_WL_25G_MCC); 5395 } 5396 5397 static void _action_wl_scan(struct rtw89_dev *rtwdev) 5398 { 5399 struct rtw89_btc *btc = &rtwdev->btc; 5400 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 5401 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 5402 5403 if (RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) { 5404 _action_wl_25g_mcc(rtwdev); 5405 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], Scan offload!\n"); 5406 } else if (rtwdev->dbcc_en) { 5407 if (wl_dinfo->real_band[RTW89_PHY_0] != RTW89_BAND_2G && 5408 wl_dinfo->real_band[RTW89_PHY_1] != RTW89_BAND_2G) 5409 _action_wl_5g(rtwdev); 5410 else 5411 _action_by_bt(rtwdev); 5412 } else { 5413 if (wl->scan_info.band[RTW89_PHY_0] != RTW89_BAND_2G) 5414 _action_wl_5g(rtwdev); 5415 else 5416 _action_by_bt(rtwdev); 5417 } 5418 } 5419 5420 static void _action_wl_2g_mcc(struct rtw89_dev *rtwdev) 5421 { struct rtw89_btc *btc = &rtwdev->btc; 5422 5423 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 5424 5425 if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ 5426 if (btc->cx.bt.link_info.profile_cnt.now == 0) 5427 _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, 5428 BTC_ACT_WL_2G_MCC); 5429 else 5430 _set_policy(rtwdev, BTC_CXP_OFFE_DEF, 5431 BTC_ACT_WL_2G_MCC); 5432 } else { /* dedicated-antenna */ 5433 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_MCC); 5434 } 5435 } 5436 5437 static void _action_wl_2g_scc(struct rtw89_dev *rtwdev) 5438 { 5439 struct rtw89_btc *btc = &rtwdev->btc; 5440 5441 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 5442 5443 if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ 5444 if (btc->cx.bt.link_info.profile_cnt.now == 0) 5445 _set_policy(rtwdev, 5446 BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_SCC); 5447 else 5448 _set_policy(rtwdev, 5449 BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_SCC); 5450 } else { /* dedicated-antenna */ 5451 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_SCC); 5452 } 5453 } 5454 5455 static void _action_wl_2g_scc_v1(struct rtw89_dev *rtwdev) 5456 { 5457 struct rtw89_btc *btc = &rtwdev->btc; 5458 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 5459 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 5460 struct rtw89_btc_dm *dm = &btc->dm; 5461 struct rtw89_btc_wl_role_info_v1 *wl_rinfo = &wl->role_info_v1; 5462 u16 policy_type = BTC_CXP_OFF_BT; 5463 u32 dur; 5464 5465 if (btc->ant_type == BTC_ANT_DEDICATED) { 5466 policy_type = BTC_CXP_OFF_EQ0; 5467 } else { 5468 /* shared-antenna */ 5469 switch (wl_rinfo->mrole_type) { 5470 case BTC_WLMROLE_STA_GC: 5471 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION; 5472 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_P2P_CLIENT; 5473 dm->wl_scc.ebt_null = 0; /* no ext-slot-control */ 5474 _action_by_bt(rtwdev); 5475 return; 5476 case BTC_WLMROLE_STA_STA: 5477 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION; 5478 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_STATION; 5479 dm->wl_scc.ebt_null = 0; /* no ext-slot-control */ 5480 _action_by_bt(rtwdev); 5481 return; 5482 case BTC_WLMROLE_STA_GC_NOA: 5483 case BTC_WLMROLE_STA_GO: 5484 case BTC_WLMROLE_STA_GO_NOA: 5485 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION; 5486 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_NONE; 5487 dur = wl_rinfo->mrole_noa_duration; 5488 5489 if (wl->status.map._4way) { 5490 dm->wl_scc.ebt_null = 0; 5491 policy_type = BTC_CXP_OFFE_WL; 5492 } else if (bt->link_info.status.map.connect == 0) { 5493 dm->wl_scc.ebt_null = 0; 5494 policy_type = BTC_CXP_OFFE_2GISOB; 5495 } else if (bt->link_info.a2dp_desc.exist && 5496 dur < btc->bt_req_len) { 5497 dm->wl_scc.ebt_null = 1; /* tx null at EBT */ 5498 policy_type = BTC_CXP_OFFE_2GBWMIXB2; 5499 } else if (bt->link_info.a2dp_desc.exist || 5500 bt->link_info.pan_desc.exist) { 5501 dm->wl_scc.ebt_null = 1; /* tx null at EBT */ 5502 policy_type = BTC_CXP_OFFE_2GBWISOB; 5503 } else { 5504 dm->wl_scc.ebt_null = 0; 5505 policy_type = BTC_CXP_OFFE_2GBWISOB; 5506 } 5507 break; 5508 default: 5509 break; 5510 } 5511 } 5512 5513 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 5514 _set_policy(rtwdev, policy_type, BTC_ACT_WL_2G_SCC); 5515 } 5516 5517 static void _action_wl_2g_scc_v2(struct rtw89_dev *rtwdev) 5518 { 5519 struct rtw89_btc *btc = &rtwdev->btc; 5520 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 5521 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 5522 struct rtw89_btc_dm *dm = &btc->dm; 5523 struct rtw89_btc_wl_role_info_v2 *rinfo_v2 = &wl->role_info_v2; 5524 struct rtw89_btc_wl_role_info_v7 *rinfo_v7 = &wl->role_info_v7; 5525 u32 dur, mrole_type, mrole_noa_duration; 5526 u16 policy_type = BTC_CXP_OFF_BT; 5527 5528 if (btc->ver->fwlrole == 2) { 5529 mrole_type = rinfo_v2->mrole_type; 5530 mrole_noa_duration = rinfo_v2->mrole_noa_duration; 5531 } else if (btc->ver->fwlrole == 7) { 5532 mrole_type = rinfo_v7->mrole_type; 5533 mrole_noa_duration = rinfo_v7->mrole_noa_duration; 5534 } else { 5535 return; 5536 } 5537 5538 if (btc->ant_type == BTC_ANT_DEDICATED) { 5539 policy_type = BTC_CXP_OFF_EQ0; 5540 } else { 5541 /* shared-antenna */ 5542 switch (mrole_type) { 5543 case BTC_WLMROLE_STA_GC: 5544 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION; 5545 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_P2P_CLIENT; 5546 dm->wl_scc.ebt_null = 0; /* no ext-slot-control */ 5547 _action_by_bt(rtwdev); 5548 return; 5549 case BTC_WLMROLE_STA_STA: 5550 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION; 5551 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_STATION; 5552 dm->wl_scc.ebt_null = 0; /* no ext-slot-control */ 5553 _action_by_bt(rtwdev); 5554 return; 5555 case BTC_WLMROLE_STA_GC_NOA: 5556 case BTC_WLMROLE_STA_GO: 5557 case BTC_WLMROLE_STA_GO_NOA: 5558 dm->wl_scc.null_role1 = RTW89_WIFI_ROLE_STATION; 5559 dm->wl_scc.null_role2 = RTW89_WIFI_ROLE_NONE; 5560 dur = mrole_noa_duration; 5561 5562 if (wl->status.map._4way) { 5563 dm->wl_scc.ebt_null = 0; 5564 policy_type = BTC_CXP_OFFE_WL; 5565 } else if (bt->link_info.status.map.connect == 0) { 5566 dm->wl_scc.ebt_null = 0; 5567 policy_type = BTC_CXP_OFFE_2GISOB; 5568 } else if (bt->link_info.a2dp_desc.exist && 5569 dur < btc->bt_req_len) { 5570 dm->wl_scc.ebt_null = 1; /* tx null at EBT */ 5571 policy_type = BTC_CXP_OFFE_2GBWMIXB2; 5572 } else if (bt->link_info.a2dp_desc.exist || 5573 bt->link_info.pan_desc.exist) { 5574 dm->wl_scc.ebt_null = 1; /* tx null at EBT */ 5575 policy_type = BTC_CXP_OFFE_2GBWISOB; 5576 } else { 5577 dm->wl_scc.ebt_null = 0; 5578 policy_type = BTC_CXP_OFFE_2GBWISOB; 5579 } 5580 break; 5581 default: 5582 break; 5583 } 5584 } 5585 5586 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 5587 _set_policy(rtwdev, policy_type, BTC_ACT_WL_2G_SCC); 5588 } 5589 5590 static void _action_wl_2g_scc_v8(struct rtw89_dev *rtwdev) 5591 { 5592 struct rtw89_btc *btc = &rtwdev->btc; 5593 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 5594 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 5595 struct rtw89_btc_dm *dm = &btc->dm; 5596 u16 policy_type = BTC_CXP_OFF_BT; 5597 5598 if (btc->ant_type == BTC_ANT_SHARED) { 5599 if (wl->status.map._4way) 5600 policy_type = BTC_CXP_OFFE_WL; 5601 else if (bt->link_info.status.map.connect == 0) 5602 policy_type = BTC_CXP_OFFE_2GISOB; 5603 else 5604 policy_type = BTC_CXP_OFFE_2GBWISOB; 5605 } else { 5606 policy_type = BTC_CXP_OFF_EQ0; 5607 } 5608 5609 dm->e2g_slot_limit = BTC_E2G_LIMIT_DEF; 5610 5611 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 5612 _set_policy(rtwdev, policy_type, BTC_ACT_WL_2G_SCC); 5613 } 5614 5615 static void _action_wl_2g_ap(struct rtw89_dev *rtwdev) 5616 { 5617 struct rtw89_btc *btc = &rtwdev->btc; 5618 5619 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 5620 5621 if (btc->ant_type == BTC_ANT_SHARED) { 5622 if (btc->cx.bt.link_info.profile_cnt.now == 0) 5623 _set_policy(rtwdev, BTC_CXP_OFFE_DEF2, 5624 BTC_ACT_WL_2G_AP); 5625 else 5626 _set_policy(rtwdev, BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_AP); 5627 } else {/* dedicated-antenna */ 5628 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_AP); 5629 } 5630 } 5631 5632 static void _action_wl_2g_go(struct rtw89_dev *rtwdev) 5633 { 5634 struct rtw89_btc *btc = &rtwdev->btc; 5635 5636 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 5637 5638 if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ 5639 if (btc->cx.bt.link_info.profile_cnt.now == 0) 5640 _set_policy(rtwdev, 5641 BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_GO); 5642 else 5643 _set_policy(rtwdev, 5644 BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_GO); 5645 } else { /* dedicated-antenna */ 5646 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_GO); 5647 } 5648 } 5649 5650 static void _action_wl_2g_gc(struct rtw89_dev *rtwdev) 5651 { 5652 struct rtw89_btc *btc = &rtwdev->btc; 5653 5654 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 5655 5656 if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ 5657 _action_by_bt(rtwdev); 5658 } else {/* dedicated-antenna */ 5659 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_GC); 5660 } 5661 } 5662 5663 static void _action_wl_2g_nan(struct rtw89_dev *rtwdev) 5664 { 5665 struct rtw89_btc *btc = &rtwdev->btc; 5666 5667 _set_ant(rtwdev, NM_EXEC, BTC_PHY_ALL, BTC_ANT_W2G); 5668 5669 if (btc->ant_type == BTC_ANT_SHARED) { /* shared-antenna */ 5670 if (btc->cx.bt.link_info.profile_cnt.now == 0) 5671 _set_policy(rtwdev, 5672 BTC_CXP_OFFE_DEF2, BTC_ACT_WL_2G_NAN); 5673 else 5674 _set_policy(rtwdev, 5675 BTC_CXP_OFFE_DEF, BTC_ACT_WL_2G_NAN); 5676 } else { /* dedicated-antenna */ 5677 _set_policy(rtwdev, BTC_CXP_OFF_EQ0, BTC_ACT_WL_2G_NAN); 5678 } 5679 } 5680 5681 static u32 _read_scbd(struct rtw89_dev *rtwdev) 5682 { 5683 const struct rtw89_chip_info *chip = rtwdev->chip; 5684 struct rtw89_btc *btc = &rtwdev->btc; 5685 u32 scbd_val = 0; 5686 5687 if (!chip->scbd) 5688 return 0; 5689 5690 scbd_val = rtw89_mac_get_sb(rtwdev); 5691 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], read scbd: 0x%08x\n", 5692 scbd_val); 5693 5694 btc->cx.cnt_bt[BTC_BCNT_SCBDREAD]++; 5695 return scbd_val; 5696 } 5697 5698 static void _write_scbd(struct rtw89_dev *rtwdev, u32 val, bool state) 5699 { 5700 const struct rtw89_chip_info *chip = rtwdev->chip; 5701 struct rtw89_btc *btc = &rtwdev->btc; 5702 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 5703 u32 scbd_val = 0; 5704 u8 force_exec = false; 5705 5706 if (!chip->scbd) 5707 return; 5708 5709 scbd_val = state ? wl->scbd | val : wl->scbd & ~val; 5710 5711 if (val & BTC_WSCB_ACTIVE || val & BTC_WSCB_ON) 5712 force_exec = true; 5713 5714 if (scbd_val != wl->scbd || force_exec) { 5715 wl->scbd = scbd_val; 5716 wl->scbd_change = true; 5717 } 5718 } 5719 5720 static u8 5721 _update_rssi_state(struct rtw89_dev *rtwdev, u8 pre_state, u8 rssi, u8 thresh) 5722 { 5723 const struct rtw89_chip_info *chip = rtwdev->chip; 5724 u8 next_state, tol = chip->rssi_tol; 5725 5726 if (pre_state == BTC_RSSI_ST_LOW || 5727 pre_state == BTC_RSSI_ST_STAY_LOW) { 5728 if (rssi >= (thresh + tol)) 5729 next_state = BTC_RSSI_ST_HIGH; 5730 else 5731 next_state = BTC_RSSI_ST_STAY_LOW; 5732 } else { 5733 if (rssi < thresh) 5734 next_state = BTC_RSSI_ST_LOW; 5735 else 5736 next_state = BTC_RSSI_ST_STAY_HIGH; 5737 } 5738 5739 return next_state; 5740 } 5741 5742 static void _wl_req_mac(struct rtw89_dev *rtwdev, u8 mac) 5743 { 5744 if (mac == RTW89_MAC_0) 5745 rtw89_write32_clr(rtwdev, R_AX_BTC_CFG, B_AX_WL_SRC); 5746 else 5747 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, B_AX_WL_SRC); 5748 } 5749 5750 static 5751 void _update_dbcc_band(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 5752 { 5753 struct rtw89_btc *btc = &rtwdev->btc; 5754 5755 btc->cx.wl.dbcc_info.real_band[phy_idx] = 5756 btc->cx.wl.scan_info.phy_map & BIT(phy_idx) ? 5757 btc->cx.wl.dbcc_info.scan_band[phy_idx] : 5758 btc->cx.wl.dbcc_info.op_band[phy_idx]; 5759 } 5760 5761 static void _update_wl_info(struct rtw89_dev *rtwdev) 5762 { 5763 struct rtw89_btc *btc = &rtwdev->btc; 5764 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 5765 struct rtw89_btc_wl_link_info *wl_linfo = wl->link_info; 5766 struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; 5767 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 5768 u8 i, cnt_connect = 0, cnt_connecting = 0, cnt_active = 0; 5769 u8 cnt_2g = 0, cnt_5g = 0, phy; 5770 u32 wl_2g_ch[2] = {0}, wl_5g_ch[2] = {0}; 5771 bool b2g = false, b5g = false, client_joined = false; 5772 5773 memset(wl_rinfo, 0, sizeof(*wl_rinfo)); 5774 5775 for (i = 0; i < RTW89_PORT_NUM; i++) { 5776 /* check if role active? */ 5777 if (!wl_linfo[i].active) 5778 continue; 5779 5780 cnt_active++; 5781 wl_rinfo->active_role[cnt_active - 1].role = wl_linfo[i].role; 5782 wl_rinfo->active_role[cnt_active - 1].pid = wl_linfo[i].pid; 5783 wl_rinfo->active_role[cnt_active - 1].phy = wl_linfo[i].phy; 5784 wl_rinfo->active_role[cnt_active - 1].band = wl_linfo[i].band; 5785 wl_rinfo->active_role[cnt_active - 1].noa = (u8)wl_linfo[i].noa; 5786 wl_rinfo->active_role[cnt_active - 1].connected = 0; 5787 5788 wl->port_id[wl_linfo[i].role] = wl_linfo[i].pid; 5789 5790 phy = wl_linfo[i].phy; 5791 5792 /* check dbcc role */ 5793 if (rtwdev->dbcc_en && phy < RTW89_PHY_MAX) { 5794 wl_dinfo->role[phy] = wl_linfo[i].role; 5795 wl_dinfo->op_band[phy] = wl_linfo[i].band; 5796 _update_dbcc_band(rtwdev, phy); 5797 _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); 5798 } 5799 5800 if (wl_linfo[i].connected == MLME_NO_LINK) { 5801 continue; 5802 } else if (wl_linfo[i].connected == MLME_LINKING) { 5803 cnt_connecting++; 5804 } else { 5805 cnt_connect++; 5806 if ((wl_linfo[i].role == RTW89_WIFI_ROLE_P2P_GO || 5807 wl_linfo[i].role == RTW89_WIFI_ROLE_AP) && 5808 wl_linfo[i].client_cnt > 1) 5809 client_joined = true; 5810 } 5811 5812 wl_rinfo->role_map.val |= BIT(wl_linfo[i].role); 5813 wl_rinfo->active_role[cnt_active - 1].ch = wl_linfo[i].ch; 5814 wl_rinfo->active_role[cnt_active - 1].bw = wl_linfo[i].bw; 5815 wl_rinfo->active_role[cnt_active - 1].connected = 1; 5816 5817 /* only care 2 roles + BT coex */ 5818 if (wl_linfo[i].band != RTW89_BAND_2G) { 5819 if (cnt_5g <= ARRAY_SIZE(wl_5g_ch) - 1) 5820 wl_5g_ch[cnt_5g] = wl_linfo[i].ch; 5821 cnt_5g++; 5822 b5g = true; 5823 } else { 5824 if (cnt_2g <= ARRAY_SIZE(wl_2g_ch) - 1) 5825 wl_2g_ch[cnt_2g] = wl_linfo[i].ch; 5826 cnt_2g++; 5827 b2g = true; 5828 } 5829 } 5830 5831 wl_rinfo->connect_cnt = cnt_connect; 5832 5833 /* Be careful to change the following sequence!! */ 5834 if (cnt_connect == 0) { 5835 wl_rinfo->link_mode = BTC_WLINK_NOLINK; 5836 wl_rinfo->role_map.role.none = 1; 5837 } else if (!b2g && b5g) { 5838 wl_rinfo->link_mode = BTC_WLINK_5G; 5839 } else if (wl_rinfo->role_map.role.nan) { 5840 wl_rinfo->link_mode = BTC_WLINK_2G_NAN; 5841 } else if (cnt_connect > BTC_TDMA_WLROLE_MAX) { 5842 wl_rinfo->link_mode = BTC_WLINK_OTHER; 5843 } else if (b2g && b5g && cnt_connect == 2) { 5844 if (rtwdev->dbcc_en) { 5845 switch (wl_dinfo->role[RTW89_PHY_0]) { 5846 case RTW89_WIFI_ROLE_STATION: 5847 wl_rinfo->link_mode = BTC_WLINK_2G_STA; 5848 break; 5849 case RTW89_WIFI_ROLE_P2P_GO: 5850 wl_rinfo->link_mode = BTC_WLINK_2G_GO; 5851 break; 5852 case RTW89_WIFI_ROLE_P2P_CLIENT: 5853 wl_rinfo->link_mode = BTC_WLINK_2G_GC; 5854 break; 5855 case RTW89_WIFI_ROLE_AP: 5856 wl_rinfo->link_mode = BTC_WLINK_2G_AP; 5857 break; 5858 default: 5859 wl_rinfo->link_mode = BTC_WLINK_OTHER; 5860 break; 5861 } 5862 } else { 5863 wl_rinfo->link_mode = BTC_WLINK_25G_MCC; 5864 } 5865 } else if (!b5g && cnt_connect == 2) { 5866 if (wl_rinfo->role_map.role.station && 5867 (wl_rinfo->role_map.role.p2p_go || 5868 wl_rinfo->role_map.role.p2p_gc || 5869 wl_rinfo->role_map.role.ap)) { 5870 if (wl_2g_ch[0] == wl_2g_ch[1]) 5871 wl_rinfo->link_mode = BTC_WLINK_2G_SCC; 5872 else 5873 wl_rinfo->link_mode = BTC_WLINK_2G_MCC; 5874 } else { 5875 wl_rinfo->link_mode = BTC_WLINK_2G_MCC; 5876 } 5877 } else if (!b5g && cnt_connect == 1) { 5878 if (wl_rinfo->role_map.role.station) 5879 wl_rinfo->link_mode = BTC_WLINK_2G_STA; 5880 else if (wl_rinfo->role_map.role.ap) 5881 wl_rinfo->link_mode = BTC_WLINK_2G_AP; 5882 else if (wl_rinfo->role_map.role.p2p_go) 5883 wl_rinfo->link_mode = BTC_WLINK_2G_GO; 5884 else if (wl_rinfo->role_map.role.p2p_gc) 5885 wl_rinfo->link_mode = BTC_WLINK_2G_GC; 5886 else 5887 wl_rinfo->link_mode = BTC_WLINK_OTHER; 5888 } 5889 5890 /* if no client_joined, don't care P2P-GO/AP role */ 5891 if (wl_rinfo->role_map.role.p2p_go || wl_rinfo->role_map.role.ap) { 5892 if (!client_joined) { 5893 if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC || 5894 wl_rinfo->link_mode == BTC_WLINK_2G_MCC) { 5895 wl_rinfo->link_mode = BTC_WLINK_2G_STA; 5896 wl_rinfo->connect_cnt = 1; 5897 } else if (wl_rinfo->link_mode == BTC_WLINK_2G_GO || 5898 wl_rinfo->link_mode == BTC_WLINK_2G_AP) { 5899 wl_rinfo->link_mode = BTC_WLINK_NOLINK; 5900 wl_rinfo->connect_cnt = 0; 5901 } 5902 } 5903 } 5904 5905 rtw89_debug(rtwdev, RTW89_DBG_BTC, 5906 "[BTC], cnt_connect = %d, connecting = %d, link_mode = %d\n", 5907 cnt_connect, cnt_connecting, wl_rinfo->link_mode); 5908 5909 _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); 5910 } 5911 5912 static void _update_wl_info_v1(struct rtw89_dev *rtwdev) 5913 { 5914 struct rtw89_btc *btc = &rtwdev->btc; 5915 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 5916 struct rtw89_btc_wl_link_info *wl_linfo = wl->link_info; 5917 struct rtw89_btc_wl_role_info_v1 *wl_rinfo = &wl->role_info_v1; 5918 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 5919 u8 cnt_connect = 0, cnt_connecting = 0, cnt_active = 0; 5920 u8 cnt_2g = 0, cnt_5g = 0, phy; 5921 u32 wl_2g_ch[2] = {}, wl_5g_ch[2] = {}; 5922 bool b2g = false, b5g = false, client_joined = false; 5923 u8 i; 5924 5925 memset(wl_rinfo, 0, sizeof(*wl_rinfo)); 5926 5927 for (i = 0; i < RTW89_PORT_NUM; i++) { 5928 if (!wl_linfo[i].active) 5929 continue; 5930 5931 cnt_active++; 5932 wl_rinfo->active_role_v1[cnt_active - 1].role = wl_linfo[i].role; 5933 wl_rinfo->active_role_v1[cnt_active - 1].pid = wl_linfo[i].pid; 5934 wl_rinfo->active_role_v1[cnt_active - 1].phy = wl_linfo[i].phy; 5935 wl_rinfo->active_role_v1[cnt_active - 1].band = wl_linfo[i].band; 5936 wl_rinfo->active_role_v1[cnt_active - 1].noa = (u8)wl_linfo[i].noa; 5937 wl_rinfo->active_role_v1[cnt_active - 1].connected = 0; 5938 5939 wl->port_id[wl_linfo[i].role] = wl_linfo[i].pid; 5940 5941 phy = wl_linfo[i].phy; 5942 5943 if (rtwdev->dbcc_en && phy < RTW89_PHY_MAX) { 5944 wl_dinfo->role[phy] = wl_linfo[i].role; 5945 wl_dinfo->op_band[phy] = wl_linfo[i].band; 5946 _update_dbcc_band(rtwdev, phy); 5947 _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); 5948 } 5949 5950 if (wl_linfo[i].connected == MLME_NO_LINK) { 5951 continue; 5952 } else if (wl_linfo[i].connected == MLME_LINKING) { 5953 cnt_connecting++; 5954 } else { 5955 cnt_connect++; 5956 if ((wl_linfo[i].role == RTW89_WIFI_ROLE_P2P_GO || 5957 wl_linfo[i].role == RTW89_WIFI_ROLE_AP) && 5958 wl_linfo[i].client_cnt > 1) 5959 client_joined = true; 5960 } 5961 5962 wl_rinfo->role_map.val |= BIT(wl_linfo[i].role); 5963 wl_rinfo->active_role_v1[cnt_active - 1].ch = wl_linfo[i].ch; 5964 wl_rinfo->active_role_v1[cnt_active - 1].bw = wl_linfo[i].bw; 5965 wl_rinfo->active_role_v1[cnt_active - 1].connected = 1; 5966 5967 /* only care 2 roles + BT coex */ 5968 if (wl_linfo[i].band != RTW89_BAND_2G) { 5969 if (cnt_5g <= ARRAY_SIZE(wl_5g_ch) - 1) 5970 wl_5g_ch[cnt_5g] = wl_linfo[i].ch; 5971 cnt_5g++; 5972 b5g = true; 5973 } else { 5974 if (cnt_2g <= ARRAY_SIZE(wl_2g_ch) - 1) 5975 wl_2g_ch[cnt_2g] = wl_linfo[i].ch; 5976 cnt_2g++; 5977 b2g = true; 5978 } 5979 } 5980 5981 wl_rinfo->connect_cnt = cnt_connect; 5982 5983 /* Be careful to change the following sequence!! */ 5984 if (cnt_connect == 0) { 5985 wl_rinfo->link_mode = BTC_WLINK_NOLINK; 5986 wl_rinfo->role_map.role.none = 1; 5987 } else if (!b2g && b5g) { 5988 wl_rinfo->link_mode = BTC_WLINK_5G; 5989 } else if (wl_rinfo->role_map.role.nan) { 5990 wl_rinfo->link_mode = BTC_WLINK_2G_NAN; 5991 } else if (cnt_connect > BTC_TDMA_WLROLE_MAX) { 5992 wl_rinfo->link_mode = BTC_WLINK_OTHER; 5993 } else if (b2g && b5g && cnt_connect == 2) { 5994 if (rtwdev->dbcc_en) { 5995 switch (wl_dinfo->role[RTW89_PHY_0]) { 5996 case RTW89_WIFI_ROLE_STATION: 5997 wl_rinfo->link_mode = BTC_WLINK_2G_STA; 5998 break; 5999 case RTW89_WIFI_ROLE_P2P_GO: 6000 wl_rinfo->link_mode = BTC_WLINK_2G_GO; 6001 break; 6002 case RTW89_WIFI_ROLE_P2P_CLIENT: 6003 wl_rinfo->link_mode = BTC_WLINK_2G_GC; 6004 break; 6005 case RTW89_WIFI_ROLE_AP: 6006 wl_rinfo->link_mode = BTC_WLINK_2G_AP; 6007 break; 6008 default: 6009 wl_rinfo->link_mode = BTC_WLINK_OTHER; 6010 break; 6011 } 6012 } else { 6013 wl_rinfo->link_mode = BTC_WLINK_25G_MCC; 6014 } 6015 } else if (!b5g && cnt_connect == 2) { 6016 if (wl_rinfo->role_map.role.station && 6017 (wl_rinfo->role_map.role.p2p_go || 6018 wl_rinfo->role_map.role.p2p_gc || 6019 wl_rinfo->role_map.role.ap)) { 6020 if (wl_2g_ch[0] == wl_2g_ch[1]) 6021 wl_rinfo->link_mode = BTC_WLINK_2G_SCC; 6022 else 6023 wl_rinfo->link_mode = BTC_WLINK_2G_MCC; 6024 } else { 6025 wl_rinfo->link_mode = BTC_WLINK_2G_MCC; 6026 } 6027 } else if (!b5g && cnt_connect == 1) { 6028 if (wl_rinfo->role_map.role.station) 6029 wl_rinfo->link_mode = BTC_WLINK_2G_STA; 6030 else if (wl_rinfo->role_map.role.ap) 6031 wl_rinfo->link_mode = BTC_WLINK_2G_AP; 6032 else if (wl_rinfo->role_map.role.p2p_go) 6033 wl_rinfo->link_mode = BTC_WLINK_2G_GO; 6034 else if (wl_rinfo->role_map.role.p2p_gc) 6035 wl_rinfo->link_mode = BTC_WLINK_2G_GC; 6036 else 6037 wl_rinfo->link_mode = BTC_WLINK_OTHER; 6038 } 6039 6040 /* if no client_joined, don't care P2P-GO/AP role */ 6041 if (wl_rinfo->role_map.role.p2p_go || wl_rinfo->role_map.role.ap) { 6042 if (!client_joined) { 6043 if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC || 6044 wl_rinfo->link_mode == BTC_WLINK_2G_MCC) { 6045 wl_rinfo->link_mode = BTC_WLINK_2G_STA; 6046 wl_rinfo->connect_cnt = 1; 6047 } else if (wl_rinfo->link_mode == BTC_WLINK_2G_GO || 6048 wl_rinfo->link_mode == BTC_WLINK_2G_AP) { 6049 wl_rinfo->link_mode = BTC_WLINK_NOLINK; 6050 wl_rinfo->connect_cnt = 0; 6051 } 6052 } 6053 } 6054 6055 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6056 "[BTC], cnt_connect = %d, connecting = %d, link_mode = %d\n", 6057 cnt_connect, cnt_connecting, wl_rinfo->link_mode); 6058 6059 _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); 6060 } 6061 6062 static void _update_wl_info_v2(struct rtw89_dev *rtwdev) 6063 { 6064 struct rtw89_btc *btc = &rtwdev->btc; 6065 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 6066 struct rtw89_btc_wl_link_info *wl_linfo = wl->link_info; 6067 struct rtw89_btc_wl_role_info_v2 *wl_rinfo = &wl->role_info_v2; 6068 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 6069 u8 cnt_connect = 0, cnt_connecting = 0, cnt_active = 0; 6070 u8 cnt_2g = 0, cnt_5g = 0, phy; 6071 u32 wl_2g_ch[2] = {}, wl_5g_ch[2] = {}; 6072 bool b2g = false, b5g = false, client_joined = false; 6073 u8 i; 6074 6075 memset(wl_rinfo, 0, sizeof(*wl_rinfo)); 6076 6077 for (i = 0; i < RTW89_PORT_NUM; i++) { 6078 if (!wl_linfo[i].active) 6079 continue; 6080 6081 cnt_active++; 6082 wl_rinfo->active_role_v2[cnt_active - 1].role = wl_linfo[i].role; 6083 wl_rinfo->active_role_v2[cnt_active - 1].pid = wl_linfo[i].pid; 6084 wl_rinfo->active_role_v2[cnt_active - 1].phy = wl_linfo[i].phy; 6085 wl_rinfo->active_role_v2[cnt_active - 1].band = wl_linfo[i].band; 6086 wl_rinfo->active_role_v2[cnt_active - 1].noa = (u8)wl_linfo[i].noa; 6087 wl_rinfo->active_role_v2[cnt_active - 1].connected = 0; 6088 6089 wl->port_id[wl_linfo[i].role] = wl_linfo[i].pid; 6090 6091 phy = wl_linfo[i].phy; 6092 6093 if (rtwdev->dbcc_en && phy < RTW89_PHY_MAX) { 6094 wl_dinfo->role[phy] = wl_linfo[i].role; 6095 wl_dinfo->op_band[phy] = wl_linfo[i].band; 6096 _update_dbcc_band(rtwdev, phy); 6097 _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); 6098 } 6099 6100 if (wl_linfo[i].connected == MLME_NO_LINK) { 6101 continue; 6102 } else if (wl_linfo[i].connected == MLME_LINKING) { 6103 cnt_connecting++; 6104 } else { 6105 cnt_connect++; 6106 if ((wl_linfo[i].role == RTW89_WIFI_ROLE_P2P_GO || 6107 wl_linfo[i].role == RTW89_WIFI_ROLE_AP) && 6108 wl_linfo[i].client_cnt > 1) 6109 client_joined = true; 6110 } 6111 6112 wl_rinfo->role_map.val |= BIT(wl_linfo[i].role); 6113 wl_rinfo->active_role_v2[cnt_active - 1].ch = wl_linfo[i].ch; 6114 wl_rinfo->active_role_v2[cnt_active - 1].bw = wl_linfo[i].bw; 6115 wl_rinfo->active_role_v2[cnt_active - 1].connected = 1; 6116 6117 /* only care 2 roles + BT coex */ 6118 if (wl_linfo[i].band != RTW89_BAND_2G) { 6119 if (cnt_5g <= ARRAY_SIZE(wl_5g_ch) - 1) 6120 wl_5g_ch[cnt_5g] = wl_linfo[i].ch; 6121 cnt_5g++; 6122 b5g = true; 6123 } else { 6124 if (cnt_2g <= ARRAY_SIZE(wl_2g_ch) - 1) 6125 wl_2g_ch[cnt_2g] = wl_linfo[i].ch; 6126 cnt_2g++; 6127 b2g = true; 6128 } 6129 } 6130 6131 wl_rinfo->connect_cnt = cnt_connect; 6132 6133 /* Be careful to change the following sequence!! */ 6134 if (cnt_connect == 0) { 6135 wl_rinfo->link_mode = BTC_WLINK_NOLINK; 6136 wl_rinfo->role_map.role.none = 1; 6137 } else if (!b2g && b5g) { 6138 wl_rinfo->link_mode = BTC_WLINK_5G; 6139 } else if (wl_rinfo->role_map.role.nan) { 6140 wl_rinfo->link_mode = BTC_WLINK_2G_NAN; 6141 } else if (cnt_connect > BTC_TDMA_WLROLE_MAX) { 6142 wl_rinfo->link_mode = BTC_WLINK_OTHER; 6143 } else if (b2g && b5g && cnt_connect == 2) { 6144 if (rtwdev->dbcc_en) { 6145 switch (wl_dinfo->role[RTW89_PHY_0]) { 6146 case RTW89_WIFI_ROLE_STATION: 6147 wl_rinfo->link_mode = BTC_WLINK_2G_STA; 6148 break; 6149 case RTW89_WIFI_ROLE_P2P_GO: 6150 wl_rinfo->link_mode = BTC_WLINK_2G_GO; 6151 break; 6152 case RTW89_WIFI_ROLE_P2P_CLIENT: 6153 wl_rinfo->link_mode = BTC_WLINK_2G_GC; 6154 break; 6155 case RTW89_WIFI_ROLE_AP: 6156 wl_rinfo->link_mode = BTC_WLINK_2G_AP; 6157 break; 6158 default: 6159 wl_rinfo->link_mode = BTC_WLINK_OTHER; 6160 break; 6161 } 6162 } else { 6163 wl_rinfo->link_mode = BTC_WLINK_25G_MCC; 6164 } 6165 } else if (!b5g && cnt_connect == 2) { 6166 if (wl_rinfo->role_map.role.station && 6167 (wl_rinfo->role_map.role.p2p_go || 6168 wl_rinfo->role_map.role.p2p_gc || 6169 wl_rinfo->role_map.role.ap)) { 6170 if (wl_2g_ch[0] == wl_2g_ch[1]) 6171 wl_rinfo->link_mode = BTC_WLINK_2G_SCC; 6172 else 6173 wl_rinfo->link_mode = BTC_WLINK_2G_MCC; 6174 } else { 6175 wl_rinfo->link_mode = BTC_WLINK_2G_MCC; 6176 } 6177 } else if (!b5g && cnt_connect == 1) { 6178 if (wl_rinfo->role_map.role.station) 6179 wl_rinfo->link_mode = BTC_WLINK_2G_STA; 6180 else if (wl_rinfo->role_map.role.ap) 6181 wl_rinfo->link_mode = BTC_WLINK_2G_AP; 6182 else if (wl_rinfo->role_map.role.p2p_go) 6183 wl_rinfo->link_mode = BTC_WLINK_2G_GO; 6184 else if (wl_rinfo->role_map.role.p2p_gc) 6185 wl_rinfo->link_mode = BTC_WLINK_2G_GC; 6186 else 6187 wl_rinfo->link_mode = BTC_WLINK_OTHER; 6188 } 6189 6190 /* if no client_joined, don't care P2P-GO/AP role */ 6191 if (wl_rinfo->role_map.role.p2p_go || wl_rinfo->role_map.role.ap) { 6192 if (!client_joined) { 6193 if (wl_rinfo->link_mode == BTC_WLINK_2G_SCC || 6194 wl_rinfo->link_mode == BTC_WLINK_2G_MCC) { 6195 wl_rinfo->link_mode = BTC_WLINK_2G_STA; 6196 wl_rinfo->connect_cnt = 1; 6197 } else if (wl_rinfo->link_mode == BTC_WLINK_2G_GO || 6198 wl_rinfo->link_mode == BTC_WLINK_2G_AP) { 6199 wl_rinfo->link_mode = BTC_WLINK_NOLINK; 6200 wl_rinfo->connect_cnt = 0; 6201 } 6202 } 6203 } 6204 6205 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6206 "[BTC], cnt_connect = %d, connecting = %d, link_mode = %d\n", 6207 cnt_connect, cnt_connecting, wl_rinfo->link_mode); 6208 6209 _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); 6210 } 6211 6212 #define BTC_CHK_HANG_MAX 3 6213 #define BTC_SCB_INV_VALUE GENMASK(31, 0) 6214 6215 static u8 _get_role_link_mode(u8 role) 6216 { 6217 switch (role) { 6218 case RTW89_WIFI_ROLE_STATION: 6219 return BTC_WLINK_2G_STA; 6220 case RTW89_WIFI_ROLE_P2P_GO: 6221 return BTC_WLINK_2G_GO; 6222 case RTW89_WIFI_ROLE_P2P_CLIENT: 6223 return BTC_WLINK_2G_GC; 6224 case RTW89_WIFI_ROLE_AP: 6225 return BTC_WLINK_2G_AP; 6226 default: 6227 return BTC_WLINK_OTHER; 6228 } 6229 } 6230 6231 static bool _chk_role_ch_group(const struct rtw89_btc_chdef *r1, 6232 const struct rtw89_btc_chdef *r2) 6233 { 6234 if (r1->chan != r2->chan) { /* primary ch is different */ 6235 return false; 6236 } else if (r1->bw == RTW89_CHANNEL_WIDTH_40 && 6237 r2->bw == RTW89_CHANNEL_WIDTH_40) { 6238 if (r1->offset != r2->offset) 6239 return false; 6240 } 6241 return true; 6242 } 6243 6244 static u8 _chk_dbcc(struct rtw89_dev *rtwdev, struct rtw89_btc_chdef *ch, 6245 u8 *phy, u8 *role, u8 *dbcc_2g_phy) 6246 { 6247 struct rtw89_btc_wl_info *wl = &rtwdev->btc.cx.wl; 6248 struct rtw89_btc_wl_role_info_v7 *rinfo_v7 = &wl->role_info_v7; 6249 struct rtw89_btc_wl_role_info_v8 *rinfo_v8 = &wl->role_info_v8; 6250 bool is_2g_ch_exist = false, is_multi_role_in_2g_phy = false; 6251 u8 j, k, dbcc_2g_cid, dbcc_2g_cid2, connect_cnt; 6252 6253 if (rtwdev->btc.ver->fwlrole == 7) 6254 connect_cnt = rinfo_v7->connect_cnt; 6255 else if (rtwdev->btc.ver->fwlrole == 8) 6256 connect_cnt = rinfo_v8->connect_cnt; 6257 else 6258 return BTC_WLINK_NOLINK; 6259 6260 /* find out the 2G-PHY by connect-id ->ch */ 6261 for (j = 0; j < connect_cnt; j++) { 6262 if (ch[j].center_ch <= 14) { 6263 is_2g_ch_exist = true; 6264 break; 6265 } 6266 } 6267 6268 /* If no any 2G-port exist, it's impossible because 5G-exclude */ 6269 if (!is_2g_ch_exist) 6270 return BTC_WLINK_OTHER; 6271 6272 dbcc_2g_cid = j; 6273 *dbcc_2g_phy = phy[dbcc_2g_cid]; 6274 6275 /* connect_cnt <= 2 */ 6276 if (connect_cnt < BTC_TDMA_WLROLE_MAX) 6277 return (_get_role_link_mode((role[dbcc_2g_cid]))); 6278 6279 /* find the other-port in the 2G-PHY, ex: PHY-0:6G, PHY1: mcc/scc */ 6280 for (k = 0; k < connect_cnt; k++) { 6281 if (k == dbcc_2g_cid) 6282 continue; 6283 6284 if (phy[k] == *dbcc_2g_phy) { 6285 is_multi_role_in_2g_phy = true; 6286 dbcc_2g_cid2 = k; 6287 break; 6288 } 6289 } 6290 6291 /* Single-role in 2G-PHY */ 6292 if (!is_multi_role_in_2g_phy) 6293 return (_get_role_link_mode(role[dbcc_2g_cid])); 6294 6295 /* 2-role in 2G-PHY */ 6296 if (ch[dbcc_2g_cid2].center_ch > 14) 6297 return BTC_WLINK_25G_MCC; 6298 else if (_chk_role_ch_group(&ch[dbcc_2g_cid], &ch[dbcc_2g_cid2])) 6299 return BTC_WLINK_2G_SCC; 6300 else 6301 return BTC_WLINK_2G_MCC; 6302 } 6303 6304 static void _update_role_link_mode(struct rtw89_dev *rtwdev, 6305 bool client_joined, u32 noa) 6306 { 6307 struct rtw89_btc_wl_role_info_v8 *rinfo_v8 = &rtwdev->btc.cx.wl.role_info_v8; 6308 struct rtw89_btc_wl_role_info_v7 *rinfo_v7 = &rtwdev->btc.cx.wl.role_info_v7; 6309 u8 role_ver = rtwdev->btc.ver->fwlrole; 6310 u32 type = BTC_WLMROLE_NONE, dur = 0; 6311 u8 link_mode, connect_cnt; 6312 u32 wl_role; 6313 6314 if (role_ver == 7) { 6315 wl_role = rinfo_v7->role_map; 6316 link_mode = rinfo_v7->link_mode; 6317 connect_cnt = rinfo_v7->connect_cnt; 6318 } else if (role_ver == 8) { 6319 wl_role = rinfo_v8->role_map; 6320 link_mode = rinfo_v8->link_mode; 6321 connect_cnt = rinfo_v8->connect_cnt; 6322 } else { 6323 return; 6324 } 6325 6326 /* if no client_joined, don't care P2P-GO/AP role */ 6327 if (((wl_role & BIT(RTW89_WIFI_ROLE_P2P_GO)) || 6328 (wl_role & BIT(RTW89_WIFI_ROLE_AP))) && !client_joined) { 6329 if (link_mode == BTC_WLINK_2G_SCC) { 6330 if (role_ver == 7) { 6331 rinfo_v7->link_mode = BTC_WLINK_2G_STA; 6332 rinfo_v7->connect_cnt--; 6333 } else if (role_ver == 8) { 6334 rinfo_v8->link_mode = BTC_WLINK_2G_STA; 6335 rinfo_v8->connect_cnt--; 6336 } 6337 } else if (link_mode == BTC_WLINK_2G_GO || 6338 link_mode == BTC_WLINK_2G_AP) { 6339 if (role_ver == 7) { 6340 rinfo_v7->link_mode = BTC_WLINK_NOLINK; 6341 rinfo_v7->connect_cnt--; 6342 } else if (role_ver == 8) { 6343 rinfo_v8->link_mode = BTC_WLINK_NOLINK; 6344 rinfo_v8->connect_cnt--; 6345 } 6346 } 6347 } 6348 6349 /* Identify 2-Role type */ 6350 if (connect_cnt >= 2 && 6351 (link_mode == BTC_WLINK_2G_SCC || 6352 link_mode == BTC_WLINK_2G_MCC || 6353 link_mode == BTC_WLINK_25G_MCC || 6354 link_mode == BTC_WLINK_5G)) { 6355 if ((wl_role & BIT(RTW89_WIFI_ROLE_P2P_GO)) || 6356 (wl_role & BIT(RTW89_WIFI_ROLE_AP))) 6357 type = noa ? BTC_WLMROLE_STA_GO_NOA : BTC_WLMROLE_STA_GO; 6358 else if (wl_role & BIT(RTW89_WIFI_ROLE_P2P_CLIENT)) 6359 type = noa ? BTC_WLMROLE_STA_GC_NOA : BTC_WLMROLE_STA_GC; 6360 else 6361 type = BTC_WLMROLE_STA_STA; 6362 6363 dur = noa; 6364 } 6365 6366 if (role_ver == 7) { 6367 rinfo_v7->mrole_type = type; 6368 rinfo_v7->mrole_noa_duration = dur; 6369 } else if (role_ver == 8) { 6370 rinfo_v8->mrole_type = type; 6371 rinfo_v8->mrole_noa_duration = dur; 6372 } 6373 } 6374 6375 static void _update_wl_info_v7(struct rtw89_dev *rtwdev, u8 rid) 6376 { 6377 struct rtw89_btc_chdef cid_ch[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 6378 struct rtw89_btc *btc = &rtwdev->btc; 6379 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 6380 struct rtw89_btc_wl_role_info_v7 *wl_rinfo = &wl->role_info_v7; 6381 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 6382 struct rtw89_btc_wl_link_info *wl_linfo = wl->link_info; 6383 struct rtw89_btc_wl_active_role_v7 *act_role = NULL; 6384 u8 i, mode, cnt = 0, cnt_2g = 0, cnt_5g = 0, phy_now = RTW89_PHY_MAX, phy_dbcc; 6385 bool b2g = false, b5g = false, client_joined = false, client_inc_2g = false; 6386 u8 client_cnt_last[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER] = {}; 6387 u8 cid_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER] = {}; 6388 u8 cid_phy[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER] = {}; 6389 u8 mac = RTW89_MAC_0, dbcc_2g_phy = RTW89_PHY_0; 6390 u32 noa_duration = 0; 6391 6392 memset(wl_rinfo, 0, sizeof(*wl_rinfo)); 6393 6394 for (i = 0; i < RTW89_PORT_NUM; i++) { 6395 if (!wl_linfo[i].active || wl_linfo[i].phy >= RTW89_PHY_MAX) 6396 continue; 6397 6398 act_role = &wl_rinfo->active_role[i]; 6399 act_role->role = wl_linfo[i].role; 6400 6401 /* check if role connect? */ 6402 if (wl_linfo[i].connected == MLME_NO_LINK) { 6403 act_role->connected = 0; 6404 continue; 6405 } else if (wl_linfo[i].connected == MLME_LINKING) { 6406 continue; 6407 } 6408 6409 cnt++; 6410 act_role->connected = 1; 6411 act_role->pid = wl_linfo[i].pid; 6412 act_role->phy = wl_linfo[i].phy; 6413 act_role->band = wl_linfo[i].band; 6414 act_role->ch = wl_linfo[i].ch; 6415 act_role->bw = wl_linfo[i].bw; 6416 act_role->noa = wl_linfo[i].noa; 6417 act_role->noa_dur = wl_linfo[i].noa_duration; 6418 cid_ch[cnt - 1] = wl_linfo[i].chdef; 6419 cid_phy[cnt - 1] = wl_linfo[i].phy; 6420 cid_role[cnt - 1] = wl_linfo[i].role; 6421 wl_rinfo->role_map |= BIT(wl_linfo[i].role); 6422 6423 if (rid == i) 6424 phy_now = act_role->phy; 6425 6426 if (wl_linfo[i].role == RTW89_WIFI_ROLE_P2P_GO || 6427 wl_linfo[i].role == RTW89_WIFI_ROLE_AP) { 6428 if (wl_linfo[i].client_cnt > 1) 6429 client_joined = true; 6430 if (client_cnt_last[i] < wl_linfo[i].client_cnt && 6431 wl_linfo[i].chdef.band == RTW89_BAND_2G) 6432 client_inc_2g = true; 6433 act_role->client_cnt = wl_linfo[i].client_cnt; 6434 } else { 6435 act_role->client_cnt = 0; 6436 } 6437 6438 if (act_role->noa && act_role->noa_dur > 0) 6439 noa_duration = act_role->noa_dur; 6440 6441 if (rtwdev->dbcc_en) { 6442 phy_dbcc = wl_linfo[i].phy; 6443 wl_dinfo->role[phy_dbcc] |= BIT(wl_linfo[i].role); 6444 wl_dinfo->op_band[phy_dbcc] = wl_linfo[i].chdef.band; 6445 } 6446 6447 if (wl_linfo[i].chdef.band != RTW89_BAND_2G) { 6448 cnt_5g++; 6449 b5g = true; 6450 } else { 6451 if (((wl_linfo[i].role == RTW89_WIFI_ROLE_P2P_GO || 6452 wl_linfo[i].role == RTW89_WIFI_ROLE_AP) && 6453 client_joined) || 6454 wl_linfo[i].role == RTW89_WIFI_ROLE_P2P_CLIENT) 6455 wl_rinfo->p2p_2g = 1; 6456 6457 if ((wl_linfo[i].mode & BIT(BTC_WL_MODE_11B)) || 6458 (wl_linfo[i].mode & BIT(BTC_WL_MODE_11G))) 6459 wl->bg_mode = 1; 6460 else if (wl_linfo[i].mode & BIT(BTC_WL_MODE_HE)) 6461 wl->he_mode = true; 6462 6463 cnt_2g++; 6464 b2g = true; 6465 } 6466 6467 if (act_role->band == RTW89_BAND_5G && act_role->ch >= 100) 6468 wl->is_5g_hi_channel = 1; 6469 else 6470 wl->is_5g_hi_channel = 0; 6471 } 6472 6473 wl_rinfo->connect_cnt = cnt; 6474 wl->client_cnt_inc_2g = client_inc_2g; 6475 6476 if (cnt == 0) { 6477 mode = BTC_WLINK_NOLINK; 6478 wl_rinfo->role_map = BIT(RTW89_WIFI_ROLE_NONE); 6479 } else if (!b2g && b5g) { 6480 mode = BTC_WLINK_5G; 6481 } else if (wl_rinfo->role_map & BIT(RTW89_WIFI_ROLE_NAN)) { 6482 mode = BTC_WLINK_2G_NAN; 6483 } else if (cnt > BTC_TDMA_WLROLE_MAX) { 6484 mode = BTC_WLINK_OTHER; 6485 } else if (rtwdev->dbcc_en) { 6486 mode = _chk_dbcc(rtwdev, cid_ch, cid_phy, cid_role, &dbcc_2g_phy); 6487 6488 /* correct 2G-located PHY band for gnt ctrl */ 6489 if (dbcc_2g_phy < RTW89_PHY_MAX) 6490 wl_dinfo->op_band[dbcc_2g_phy] = RTW89_BAND_2G; 6491 } else if (b2g && b5g && cnt == 2) { 6492 mode = BTC_WLINK_25G_MCC; 6493 } else if (!b5g && cnt == 2) { /* cnt_connect = 2 */ 6494 if (_chk_role_ch_group(&cid_ch[0], &cid_ch[cnt - 1])) 6495 mode = BTC_WLINK_2G_SCC; 6496 else 6497 mode = BTC_WLINK_2G_MCC; 6498 } else if (!b5g && cnt == 1) { /* cnt_connect = 1 */ 6499 mode = _get_role_link_mode(cid_role[0]); 6500 } else { 6501 mode = BTC_WLINK_NOLINK; 6502 } 6503 6504 wl_rinfo->link_mode = mode; 6505 _update_role_link_mode(rtwdev, client_joined, noa_duration); 6506 6507 /* todo DBCC related event */ 6508 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC] wl_info phy_now=%d\n", phy_now); 6509 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6510 "[BTC] rlink cnt_2g=%d cnt_5g=%d\n", cnt_2g, cnt_5g); 6511 6512 if (wl_rinfo->dbcc_en != rtwdev->dbcc_en) { 6513 wl_rinfo->dbcc_chg = 1; 6514 wl_rinfo->dbcc_en = rtwdev->dbcc_en; 6515 btc->cx.cnt_wl[BTC_WCNT_DBCC_CHG]++; 6516 } 6517 6518 if (rtwdev->dbcc_en) { 6519 wl_rinfo->dbcc_2g_phy = dbcc_2g_phy; 6520 6521 if (dbcc_2g_phy == RTW89_PHY_1) 6522 mac = RTW89_MAC_1; 6523 6524 _update_dbcc_band(rtwdev, RTW89_PHY_0); 6525 _update_dbcc_band(rtwdev, RTW89_PHY_1); 6526 } 6527 _wl_req_mac(rtwdev, mac); 6528 _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); 6529 } 6530 6531 static void _update_wl_info_v8(struct rtw89_dev *rtwdev, u8 role_id, u8 rlink_id, 6532 enum btc_role_state state) 6533 { 6534 struct rtw89_btc *btc = &rtwdev->btc; 6535 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 6536 struct rtw89_btc_chdef cid_ch[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER]; 6537 struct rtw89_btc_wl_role_info_v8 *wl_rinfo = &wl->role_info_v8; 6538 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 6539 bool client_joined = false, b2g = false, b5g = false; 6540 u8 cid_role[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER] = {}; 6541 u8 cid_phy[RTW89_BE_BTC_WL_MAX_ROLE_NUMBER] = {}; 6542 u8 dbcc_en = 0, pta_req_band = RTW89_MAC_0; 6543 u8 i, j, cnt = 0, cnt_2g = 0, cnt_5g = 0; 6544 struct rtw89_btc_wl_link_info *wl_linfo; 6545 struct rtw89_btc_wl_rlink *rlink = NULL; 6546 u8 dbcc_2g_phy = RTW89_PHY_0; 6547 u8 mode = BTC_WLINK_NOLINK; 6548 u32 noa_dur = 0; 6549 6550 if (role_id >= RTW89_BE_BTC_WL_MAX_ROLE_NUMBER || rlink_id > RTW89_MAC_1) 6551 return; 6552 6553 /* Extract wl->link_info[role_id][rlink_id] to wl->role_info 6554 * role_id: role index 6555 * rlink_id: rlink index (= HW-band index) 6556 * pid: port_index 6557 */ 6558 6559 wl_linfo = &wl->rlink_info[role_id][rlink_id]; 6560 if (wl_linfo->connected == MLME_LINKING) 6561 return; 6562 6563 rlink = &wl_rinfo->rlink[role_id][rlink_id]; 6564 rlink->role = wl_linfo->role; 6565 rlink->active = wl_linfo->active; /* Doze or not */ 6566 rlink->pid = wl_linfo->pid; 6567 rlink->phy = wl_linfo->phy; 6568 rlink->rf_band = wl_linfo->band; 6569 rlink->ch = wl_linfo->ch; 6570 rlink->bw = wl_linfo->bw; 6571 rlink->noa = wl_linfo->noa; 6572 rlink->noa_dur = wl_linfo->noa_duration / 1000; 6573 rlink->client_cnt = wl_linfo->client_cnt; 6574 rlink->mode = wl_linfo->mode; 6575 6576 switch (wl_linfo->connected) { 6577 case MLME_NO_LINK: 6578 rlink->connected = 0; 6579 if (rlink->role == RTW89_WIFI_ROLE_STATION) 6580 btc->dm.leak_ap = 0; 6581 break; 6582 case MLME_LINKED: 6583 rlink->connected = 1; 6584 break; 6585 default: 6586 return; 6587 } 6588 6589 wl->is_5g_hi_channel = false; 6590 wl->bg_mode = false; 6591 wl_rinfo->role_map = 0; 6592 wl_rinfo->p2p_2g = 0; 6593 memset(cid_ch, 0, sizeof(cid_ch)); 6594 6595 for (i = 0; i < RTW89_BE_BTC_WL_MAX_ROLE_NUMBER; i++) { 6596 for (j = RTW89_MAC_0; j <= RTW89_MAC_1; j++) { 6597 rlink = &wl_rinfo->rlink[i][j]; 6598 6599 if (!rlink->active || !rlink->connected) 6600 continue; 6601 6602 cnt++; 6603 wl_rinfo->role_map |= BIT(rlink->role); 6604 6605 /* only if client connect for p2p-Go/AP */ 6606 if ((rlink->role == RTW89_WIFI_ROLE_P2P_GO || 6607 rlink->role == RTW89_WIFI_ROLE_AP) && 6608 rlink->client_cnt > 1) 6609 client_joined = true; 6610 6611 /* Identufy if P2P-Go (GO/GC/AP) exist at 2G band*/ 6612 if (rlink->rf_band == RTW89_BAND_2G && 6613 (client_joined || rlink->role == RTW89_WIFI_ROLE_P2P_CLIENT)) 6614 wl_rinfo->p2p_2g = 1; 6615 6616 /* only one noa-role exist */ 6617 if (rlink->noa && rlink->noa_dur > 0) 6618 noa_dur = rlink->noa_dur; 6619 6620 /* for WL 5G-Rx interfered with BT issue */ 6621 if (rlink->rf_band == RTW89_BAND_5G && rlink->ch >= 100) 6622 wl->is_5g_hi_channel = 1; 6623 6624 if ((rlink->mode & BIT(BTC_WL_MODE_11B)) || 6625 (rlink->mode & BIT(BTC_WL_MODE_11G))) 6626 wl->bg_mode = 1; 6627 6628 if (rtwdev->chip->para_ver & BTC_FEAT_MLO_SUPPORT) 6629 continue; 6630 6631 cid_ch[cnt - 1] = wl_linfo->chdef; 6632 cid_phy[cnt - 1] = rlink->phy; 6633 cid_role[cnt - 1] = rlink->role; 6634 6635 if (rlink->rf_band != RTW89_BAND_2G) { 6636 cnt_5g++; 6637 b5g = true; 6638 } else { 6639 cnt_2g++; 6640 b2g = true; 6641 } 6642 } 6643 } 6644 6645 if (rtwdev->chip->para_ver & BTC_FEAT_MLO_SUPPORT) { 6646 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6647 "[BTC] rlink cnt_2g=%d cnt_5g=%d\n", cnt_2g, cnt_5g); 6648 rtw89_warn(rtwdev, "not support MLO feature yet"); 6649 } else { 6650 dbcc_en = rtwdev->dbcc_en; 6651 6652 /* Be careful to change the following sequence!! */ 6653 if (cnt == 0) { 6654 mode = BTC_WLINK_NOLINK; 6655 } else if (!b2g && b5g) { 6656 mode = BTC_WLINK_5G; 6657 } else if (wl_rinfo->role_map & BIT(RTW89_WIFI_ROLE_NAN)) { 6658 mode = BTC_WLINK_2G_NAN; 6659 } else if (cnt > BTC_TDMA_WLROLE_MAX) { 6660 mode = BTC_WLINK_OTHER; 6661 } else if (dbcc_en) { 6662 mode = _chk_dbcc(rtwdev, cid_ch, cid_phy, cid_role, 6663 &dbcc_2g_phy); 6664 } else if (b2g && b5g && cnt == 2) { 6665 mode = BTC_WLINK_25G_MCC; 6666 } else if (!b5g && cnt == 2) { /* cnt_connect = 2 */ 6667 if (_chk_role_ch_group(&cid_ch[0], &cid_ch[cnt - 1])) 6668 mode = BTC_WLINK_2G_SCC; 6669 else 6670 mode = BTC_WLINK_2G_MCC; 6671 } else if (!b5g && cnt == 1) { /* cnt_connect = 1 */ 6672 mode = _get_role_link_mode(cid_role[0]); 6673 } 6674 } 6675 6676 wl_rinfo->link_mode = mode; 6677 wl_rinfo->connect_cnt = cnt; 6678 if (wl_rinfo->connect_cnt == 0) 6679 wl_rinfo->role_map = BIT(RTW89_WIFI_ROLE_NONE); 6680 _update_role_link_mode(rtwdev, client_joined, noa_dur); 6681 6682 wl_rinfo->dbcc_2g_phy = dbcc_2g_phy; 6683 if (wl_rinfo->dbcc_en != dbcc_en) { 6684 wl_rinfo->dbcc_en = dbcc_en; 6685 wl_rinfo->dbcc_chg = 1; 6686 btc->cx.cnt_wl[BTC_WCNT_DBCC_CHG]++; 6687 } else { 6688 wl_rinfo->dbcc_chg = 0; 6689 } 6690 6691 if (wl_rinfo->dbcc_en) { 6692 memset(wl_dinfo, 0, sizeof(struct rtw89_btc_wl_dbcc_info)); 6693 6694 if (mode == BTC_WLINK_5G) { 6695 pta_req_band = RTW89_PHY_0; 6696 wl_dinfo->op_band[RTW89_PHY_0] = RTW89_BAND_5G; 6697 wl_dinfo->op_band[RTW89_PHY_1] = RTW89_BAND_2G; 6698 } else if (wl_rinfo->dbcc_2g_phy == RTW89_PHY_1) { 6699 pta_req_band = RTW89_PHY_1; 6700 wl_dinfo->op_band[RTW89_PHY_0] = RTW89_BAND_5G; 6701 wl_dinfo->op_band[RTW89_PHY_1] = RTW89_BAND_2G; 6702 } else { 6703 pta_req_band = RTW89_PHY_0; 6704 wl_dinfo->op_band[RTW89_PHY_0] = RTW89_BAND_2G; 6705 wl_dinfo->op_band[RTW89_PHY_1] = RTW89_BAND_5G; 6706 } 6707 _update_dbcc_band(rtwdev, RTW89_PHY_0); 6708 _update_dbcc_band(rtwdev, RTW89_PHY_1); 6709 } 6710 6711 wl_rinfo->pta_req_band = pta_req_band; 6712 _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); 6713 } 6714 6715 void rtw89_coex_act1_work(struct work_struct *work) 6716 { 6717 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 6718 coex_act1_work.work); 6719 struct rtw89_btc *btc = &rtwdev->btc; 6720 struct rtw89_btc_dm *dm = &rtwdev->btc.dm; 6721 struct rtw89_btc_cx *cx = &btc->cx; 6722 struct rtw89_btc_wl_info *wl = &cx->wl; 6723 6724 mutex_lock(&rtwdev->mutex); 6725 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): enter\n", __func__); 6726 dm->cnt_notify[BTC_NCNT_TIMER]++; 6727 if (wl->status.map._4way) 6728 wl->status.map._4way = false; 6729 if (wl->status.map.connecting) 6730 wl->status.map.connecting = false; 6731 6732 _run_coex(rtwdev, BTC_RSN_ACT1_WORK); 6733 mutex_unlock(&rtwdev->mutex); 6734 } 6735 6736 void rtw89_coex_bt_devinfo_work(struct work_struct *work) 6737 { 6738 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 6739 coex_bt_devinfo_work.work); 6740 struct rtw89_btc *btc = &rtwdev->btc; 6741 struct rtw89_btc_dm *dm = &rtwdev->btc.dm; 6742 struct rtw89_btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; 6743 6744 mutex_lock(&rtwdev->mutex); 6745 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): enter\n", __func__); 6746 dm->cnt_notify[BTC_NCNT_TIMER]++; 6747 a2dp->play_latency = 0; 6748 _run_coex(rtwdev, BTC_RSN_BT_DEVINFO_WORK); 6749 mutex_unlock(&rtwdev->mutex); 6750 } 6751 6752 void rtw89_coex_rfk_chk_work(struct work_struct *work) 6753 { 6754 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 6755 coex_rfk_chk_work.work); 6756 struct rtw89_btc *btc = &rtwdev->btc; 6757 struct rtw89_btc_dm *dm = &rtwdev->btc.dm; 6758 struct rtw89_btc_cx *cx = &btc->cx; 6759 struct rtw89_btc_wl_info *wl = &cx->wl; 6760 6761 mutex_lock(&rtwdev->mutex); 6762 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): enter\n", __func__); 6763 dm->cnt_notify[BTC_NCNT_TIMER]++; 6764 if (wl->rfk_info.state != BTC_WRFK_STOP) { 6765 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6766 "[BTC], %s(): RFK timeout\n", __func__); 6767 cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]++; 6768 dm->error.map.wl_rfk_timeout = true; 6769 wl->rfk_info.state = BTC_WRFK_STOP; 6770 _write_scbd(rtwdev, BTC_WSCB_WLRFK, false); 6771 _run_coex(rtwdev, BTC_RSN_RFK_CHK_WORK); 6772 } 6773 mutex_unlock(&rtwdev->mutex); 6774 } 6775 6776 static void _update_bt_scbd(struct rtw89_dev *rtwdev, bool only_update) 6777 { 6778 const struct rtw89_chip_info *chip = rtwdev->chip; 6779 struct rtw89_btc *btc = &rtwdev->btc; 6780 struct rtw89_btc_cx *cx = &btc->cx; 6781 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 6782 u32 val; 6783 bool status_change = false; 6784 6785 if (!chip->scbd) 6786 return; 6787 6788 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s\n", __func__); 6789 6790 val = _read_scbd(rtwdev); 6791 if (val == BTC_SCB_INV_VALUE) { 6792 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6793 "[BTC], %s(): return by invalid scbd value\n", 6794 __func__); 6795 return; 6796 } 6797 6798 if (!(val & BTC_BSCB_ON)) 6799 bt->enable.now = 0; 6800 else 6801 bt->enable.now = 1; 6802 6803 if (bt->enable.now != bt->enable.last) 6804 status_change = true; 6805 6806 /* reset bt info if bt re-enable */ 6807 if (bt->enable.now && !bt->enable.last) { 6808 _reset_btc_var(rtwdev, BTC_RESET_BTINFO); 6809 cx->cnt_bt[BTC_BCNT_REENABLE]++; 6810 bt->enable.now = 1; 6811 } 6812 6813 bt->enable.last = bt->enable.now; 6814 bt->scbd = val; 6815 bt->mbx_avl = !!(val & BTC_BSCB_ACT); 6816 6817 if (bt->whql_test != !!(val & BTC_BSCB_WHQL)) 6818 status_change = true; 6819 6820 bt->whql_test = !!(val & BTC_BSCB_WHQL); 6821 bt->btg_type = val & BTC_BSCB_BT_S1 ? BTC_BT_BTG : BTC_BT_ALONE; 6822 bt->link_info.a2dp_desc.exist = !!(val & BTC_BSCB_A2DP_ACT); 6823 6824 bt->lna_constrain = !!(val & BTC_BSCB_BT_LNAB0) + 6825 !!(val & BTC_BSCB_BT_LNAB1) * 2 + 4; 6826 6827 /* if rfk run 1->0 */ 6828 if (bt->rfk_info.map.run && !(val & BTC_BSCB_RFK_RUN)) 6829 status_change = true; 6830 6831 bt->rfk_info.map.run = !!(val & BTC_BSCB_RFK_RUN); 6832 bt->rfk_info.map.req = !!(val & BTC_BSCB_RFK_REQ); 6833 bt->hi_lna_rx = !!(val & BTC_BSCB_BT_HILNA); 6834 bt->link_info.status.map.connect = !!(val & BTC_BSCB_BT_CONNECT); 6835 bt->run_patch_code = !!(val & BTC_BSCB_PATCH_CODE); 6836 6837 if (!only_update && status_change) 6838 _run_coex(rtwdev, BTC_RSN_UPDATE_BT_SCBD); 6839 } 6840 6841 static bool _chk_wl_rfk_request(struct rtw89_dev *rtwdev) 6842 { 6843 struct rtw89_btc *btc = &rtwdev->btc; 6844 struct rtw89_btc_cx *cx = &btc->cx; 6845 struct rtw89_btc_bt_info *bt = &cx->bt; 6846 6847 _update_bt_scbd(rtwdev, true); 6848 6849 cx->cnt_wl[BTC_WCNT_RFK_REQ]++; 6850 6851 if ((bt->rfk_info.map.run || bt->rfk_info.map.req) && 6852 !bt->rfk_info.map.timeout) { 6853 cx->cnt_wl[BTC_WCNT_RFK_REJECT]++; 6854 } else { 6855 cx->cnt_wl[BTC_WCNT_RFK_GO]++; 6856 return true; 6857 } 6858 return false; 6859 } 6860 6861 static 6862 void _run_coex(struct rtw89_dev *rtwdev, enum btc_reason_and_action reason) 6863 { 6864 struct rtw89_btc *btc = &rtwdev->btc; 6865 const struct rtw89_btc_ver *ver = btc->ver; 6866 struct rtw89_btc_dm *dm = &rtwdev->btc.dm; 6867 struct rtw89_btc_cx *cx = &btc->cx; 6868 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 6869 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 6870 struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; 6871 struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; 6872 struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; 6873 struct rtw89_btc_wl_role_info_v7 *wl_rinfo_v7 = &wl->role_info_v7; 6874 struct rtw89_btc_wl_role_info_v8 *wl_rinfo_v8 = &wl->role_info_v8; 6875 u8 mode, igno_bt, always_freerun; 6876 6877 lockdep_assert_held(&rtwdev->mutex); 6878 6879 dm->run_reason = reason; 6880 _update_dm_step(rtwdev, reason); 6881 _update_btc_state_map(rtwdev); 6882 6883 if (ver->fwlrole == 0) 6884 mode = wl_rinfo->link_mode; 6885 else if (ver->fwlrole == 1) 6886 mode = wl_rinfo_v1->link_mode; 6887 else if (ver->fwlrole == 2) 6888 mode = wl_rinfo_v2->link_mode; 6889 else if (ver->fwlrole == 7) 6890 mode = wl_rinfo_v7->link_mode; 6891 else if (ver->fwlrole == 8) 6892 mode = wl_rinfo_v8->link_mode; 6893 else 6894 return; 6895 6896 if (ver->fcxctrl == 7) { 6897 igno_bt = btc->ctrl.ctrl_v7.igno_bt; 6898 always_freerun = btc->ctrl.ctrl_v7.always_freerun; 6899 } else { 6900 igno_bt = btc->ctrl.ctrl.igno_bt; 6901 always_freerun = btc->ctrl.ctrl.always_freerun; 6902 } 6903 6904 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): reason=%d, mode=%d\n", 6905 __func__, reason, mode); 6906 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): wl_only=%d, bt_only=%d\n", 6907 __func__, dm->wl_only, dm->bt_only); 6908 6909 /* Be careful to change the following function sequence!! */ 6910 if (btc->manual_ctrl) { 6911 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6912 "[BTC], %s(): return for Manual CTRL!!\n", 6913 __func__); 6914 return; 6915 } 6916 6917 if (igno_bt && 6918 (reason == BTC_RSN_UPDATE_BT_INFO || 6919 reason == BTC_RSN_UPDATE_BT_SCBD)) { 6920 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6921 "[BTC], %s(): return for Stop Coex DM!!\n", 6922 __func__); 6923 return; 6924 } 6925 6926 if (!wl->status.map.init_ok) { 6927 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6928 "[BTC], %s(): return for WL init fail!!\n", 6929 __func__); 6930 return; 6931 } 6932 6933 if (wl->status.map.rf_off_pre == wl->status.map.rf_off && 6934 wl->status.map.lps_pre == wl->status.map.lps) { 6935 if (reason == BTC_RSN_NTFY_POWEROFF || 6936 reason == BTC_RSN_NTFY_RADIO_STATE) { 6937 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6938 "[BTC], %s(): return for WL rf off state no change!!\n", 6939 __func__); 6940 return; 6941 } 6942 if (wl->status.map.rf_off == 1 || 6943 wl->status.map.lps == BTC_LPS_RF_OFF) { 6944 rtw89_debug(rtwdev, RTW89_DBG_BTC, 6945 "[BTC], %s(): return for WL rf off state!!\n", 6946 __func__); 6947 return; 6948 } 6949 } 6950 6951 dm->freerun = false; 6952 dm->cnt_dm[BTC_DCNT_RUN]++; 6953 dm->fddt_train = BTC_FDDT_DISABLE; 6954 bt->scan_rx_low_pri = false; 6955 igno_bt = false; 6956 6957 dm->freerun_chk = _check_freerun(rtwdev); /* check if meet freerun */ 6958 6959 if (always_freerun) { 6960 _action_freerun(rtwdev); 6961 igno_bt = true; 6962 goto exit; 6963 } 6964 6965 if (dm->wl_only) { 6966 _action_wl_only(rtwdev); 6967 igno_bt = true; 6968 goto exit; 6969 } 6970 6971 if (wl->status.map.rf_off || wl->status.map.lps || dm->bt_only) { 6972 _action_wl_off(rtwdev, mode); 6973 igno_bt = true; 6974 goto exit; 6975 } 6976 6977 if (reason == BTC_RSN_NTFY_INIT) { 6978 _action_wl_init(rtwdev); 6979 goto exit; 6980 } 6981 6982 if (!cx->bt.enable.now && !cx->other.type) { 6983 _action_bt_off(rtwdev); 6984 goto exit; 6985 } 6986 6987 if (cx->bt.whql_test) { 6988 _action_bt_whql(rtwdev); 6989 goto exit; 6990 } 6991 6992 if (wl->rfk_info.state != BTC_WRFK_STOP) { 6993 _action_wl_rfk(rtwdev); 6994 goto exit; 6995 } 6996 6997 if (wl->status.val & btc_scanning_map.val) { 6998 _action_wl_scan(rtwdev); 6999 bt->scan_rx_low_pri = true; 7000 goto exit; 7001 } 7002 7003 switch (mode) { 7004 case BTC_WLINK_NOLINK: 7005 _action_wl_nc(rtwdev); 7006 break; 7007 case BTC_WLINK_2G_STA: 7008 if (wl->status.map.traffic_dir & BIT(RTW89_TFC_DL)) 7009 bt->scan_rx_low_pri = true; 7010 _action_wl_2g_sta(rtwdev); 7011 break; 7012 case BTC_WLINK_2G_AP: 7013 bt->scan_rx_low_pri = true; 7014 _action_wl_2g_ap(rtwdev); 7015 break; 7016 case BTC_WLINK_2G_GO: 7017 bt->scan_rx_low_pri = true; 7018 _action_wl_2g_go(rtwdev); 7019 break; 7020 case BTC_WLINK_2G_GC: 7021 bt->scan_rx_low_pri = true; 7022 _action_wl_2g_gc(rtwdev); 7023 break; 7024 case BTC_WLINK_2G_SCC: 7025 bt->scan_rx_low_pri = true; 7026 if (ver->fwlrole == 0) 7027 _action_wl_2g_scc(rtwdev); 7028 else if (ver->fwlrole == 1) 7029 _action_wl_2g_scc_v1(rtwdev); 7030 else if (ver->fwlrole == 2 || ver->fwlrole == 7) 7031 _action_wl_2g_scc_v2(rtwdev); 7032 else if (ver->fwlrole == 8) 7033 _action_wl_2g_scc_v8(rtwdev); 7034 break; 7035 case BTC_WLINK_2G_MCC: 7036 bt->scan_rx_low_pri = true; 7037 _action_wl_2g_mcc(rtwdev); 7038 break; 7039 case BTC_WLINK_25G_MCC: 7040 bt->scan_rx_low_pri = true; 7041 _action_wl_25g_mcc(rtwdev); 7042 break; 7043 case BTC_WLINK_5G: 7044 _action_wl_5g(rtwdev); 7045 break; 7046 case BTC_WLINK_2G_NAN: 7047 _action_wl_2g_nan(rtwdev); 7048 break; 7049 default: 7050 _action_wl_other(rtwdev); 7051 break; 7052 } 7053 7054 exit: 7055 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): exit\n", __func__); 7056 if (ver->fcxctrl == 7) 7057 btc->ctrl.ctrl_v7.igno_bt = igno_bt; 7058 else 7059 btc->ctrl.ctrl.igno_bt = igno_bt; 7060 _action_common(rtwdev); 7061 } 7062 7063 void rtw89_btc_ntfy_poweron(struct rtw89_dev *rtwdev) 7064 { 7065 struct rtw89_btc *btc = &rtwdev->btc; 7066 7067 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); 7068 btc->dm.cnt_notify[BTC_NCNT_POWER_ON]++; 7069 } 7070 7071 void rtw89_btc_ntfy_poweroff(struct rtw89_dev *rtwdev) 7072 { 7073 struct rtw89_btc *btc = &rtwdev->btc; 7074 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 7075 7076 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): !!\n", __func__); 7077 btc->dm.cnt_notify[BTC_NCNT_POWER_OFF]++; 7078 7079 btc->cx.wl.status.map.rf_off = 1; 7080 btc->cx.wl.status.map.busy = 0; 7081 wl->status.map.lps = BTC_LPS_OFF; 7082 7083 _write_scbd(rtwdev, BTC_WSCB_ALL, false); 7084 _run_coex(rtwdev, BTC_RSN_NTFY_POWEROFF); 7085 7086 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_ALL, 0); 7087 7088 btc->cx.wl.status.map.rf_off_pre = btc->cx.wl.status.map.rf_off; 7089 } 7090 7091 static void _set_init_info(struct rtw89_dev *rtwdev) 7092 { 7093 const struct rtw89_chip_info *chip = rtwdev->chip; 7094 struct rtw89_btc *btc = &rtwdev->btc; 7095 const struct rtw89_btc_ver *ver = btc->ver; 7096 struct rtw89_btc_dm *dm = &btc->dm; 7097 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 7098 7099 if (ver->fcxinit == 7) { 7100 dm->init_info.init_v7.wl_only = (u8)dm->wl_only; 7101 dm->init_info.init_v7.bt_only = (u8)dm->bt_only; 7102 dm->init_info.init_v7.wl_init_ok = (u8)wl->status.map.init_ok; 7103 dm->init_info.init_v7.cx_other = btc->cx.other.type; 7104 dm->init_info.init_v7.wl_guard_ch = chip->afh_guard_ch; 7105 dm->init_info.init_v7.module = btc->mdinfo.md_v7; 7106 } else { 7107 dm->init_info.init.wl_only = (u8)dm->wl_only; 7108 dm->init_info.init.bt_only = (u8)dm->bt_only; 7109 dm->init_info.init.wl_init_ok = (u8)wl->status.map.init_ok; 7110 dm->init_info.init.dbcc_en = rtwdev->dbcc_en; 7111 dm->init_info.init.cx_other = btc->cx.other.type; 7112 dm->init_info.init.wl_guard_ch = chip->afh_guard_ch; 7113 dm->init_info.init.module = btc->mdinfo.md; 7114 } 7115 } 7116 7117 void rtw89_btc_ntfy_init(struct rtw89_dev *rtwdev, u8 mode) 7118 { 7119 struct rtw89_btc *btc = &rtwdev->btc; 7120 struct rtw89_btc_dm *dm = &rtwdev->btc.dm; 7121 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 7122 const struct rtw89_chip_info *chip = rtwdev->chip; 7123 const struct rtw89_btc_ver *ver = btc->ver; 7124 7125 _reset_btc_var(rtwdev, BTC_RESET_ALL); 7126 btc->dm.run_reason = BTC_RSN_NONE; 7127 btc->dm.run_action = BTC_ACT_NONE; 7128 if (ver->fcxctrl == 7) 7129 btc->ctrl.ctrl_v7.igno_bt = true; 7130 else 7131 btc->ctrl.ctrl.igno_bt = true; 7132 7133 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7134 "[BTC], %s(): mode=%d\n", __func__, mode); 7135 7136 wl->coex_mode = mode; 7137 dm->cnt_notify[BTC_NCNT_INIT_COEX]++; 7138 dm->wl_only = mode == BTC_MODE_WL ? 1 : 0; 7139 dm->bt_only = mode == BTC_MODE_BT ? 1 : 0; 7140 wl->status.map.rf_off = mode == BTC_MODE_WLOFF ? 1 : 0; 7141 7142 chip->ops->btc_set_rfe(rtwdev); 7143 chip->ops->btc_init_cfg(rtwdev); 7144 7145 if (!wl->status.map.init_ok) { 7146 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7147 "[BTC], %s(): return for WL init fail!!\n", 7148 __func__); 7149 dm->error.map.init = true; 7150 return; 7151 } 7152 7153 _write_scbd(rtwdev, 7154 BTC_WSCB_ACTIVE | BTC_WSCB_ON | BTC_WSCB_BTLOG, true); 7155 _update_bt_scbd(rtwdev, true); 7156 if (rtw89_mac_get_ctrl_path(rtwdev)) { 7157 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7158 "[BTC], %s(): PTA owner warning!!\n", 7159 __func__); 7160 dm->error.map.pta_owner = true; 7161 } 7162 7163 _set_init_info(rtwdev); 7164 _set_wl_tx_power(rtwdev, RTW89_BTC_WL_DEF_TX_PWR); 7165 btc_fw_set_monreg(rtwdev); 7166 rtw89_btc_fw_set_slots(rtwdev); 7167 _fw_set_drv_info(rtwdev, CXDRVINFO_INIT); 7168 _fw_set_drv_info(rtwdev, CXDRVINFO_CTRL); 7169 7170 _run_coex(rtwdev, BTC_RSN_NTFY_INIT); 7171 } 7172 7173 void rtw89_btc_ntfy_scan_start(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band) 7174 { 7175 struct rtw89_btc *btc = &rtwdev->btc; 7176 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 7177 7178 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7179 "[BTC], %s(): phy_idx=%d, band=%d\n", 7180 __func__, phy_idx, band); 7181 7182 if (phy_idx >= RTW89_PHY_MAX) 7183 return; 7184 7185 btc->dm.cnt_notify[BTC_NCNT_SCAN_START]++; 7186 wl->status.map.scan = true; 7187 wl->scan_info.band[phy_idx] = band; 7188 wl->scan_info.phy_map |= BIT(phy_idx); 7189 _fw_set_drv_info(rtwdev, CXDRVINFO_SCAN); 7190 7191 if (rtwdev->dbcc_en) { 7192 wl->dbcc_info.scan_band[phy_idx] = band; 7193 _update_dbcc_band(rtwdev, phy_idx); 7194 _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); 7195 } 7196 7197 _run_coex(rtwdev, BTC_RSN_NTFY_SCAN_START); 7198 } 7199 7200 void rtw89_btc_ntfy_scan_finish(struct rtw89_dev *rtwdev, u8 phy_idx) 7201 { 7202 struct rtw89_btc *btc = &rtwdev->btc; 7203 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 7204 7205 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7206 "[BTC], %s(): phy_idx=%d\n", __func__, phy_idx); 7207 btc->dm.cnt_notify[BTC_NCNT_SCAN_FINISH]++; 7208 7209 wl->status.map.scan = false; 7210 wl->scan_info.phy_map &= ~BIT(phy_idx); 7211 _fw_set_drv_info(rtwdev, CXDRVINFO_SCAN); 7212 7213 if (rtwdev->dbcc_en) { 7214 _update_dbcc_band(rtwdev, phy_idx); 7215 _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); 7216 } 7217 7218 _run_coex(rtwdev, BTC_RSN_NTFY_SCAN_FINISH); 7219 } 7220 7221 void rtw89_btc_ntfy_switch_band(struct rtw89_dev *rtwdev, u8 phy_idx, u8 band) 7222 { 7223 struct rtw89_btc *btc = &rtwdev->btc; 7224 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 7225 7226 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7227 "[BTC], %s(): phy_idx=%d, band=%d\n", 7228 __func__, phy_idx, band); 7229 7230 if (phy_idx >= RTW89_PHY_MAX) 7231 return; 7232 7233 btc->dm.cnt_notify[BTC_NCNT_SWITCH_BAND]++; 7234 7235 if (rtwdev->dbcc_en) { 7236 wl->dbcc_info.scan_band[phy_idx] = band; 7237 _update_dbcc_band(rtwdev, phy_idx); 7238 _fw_set_drv_info(rtwdev, CXDRVINFO_DBCC); 7239 } 7240 _run_coex(rtwdev, BTC_RSN_NTFY_SWBAND); 7241 } 7242 7243 void rtw89_btc_ntfy_specific_packet(struct rtw89_dev *rtwdev, 7244 enum btc_pkt_type pkt_type) 7245 { 7246 struct rtw89_btc *btc = &rtwdev->btc; 7247 struct rtw89_btc_cx *cx = &btc->cx; 7248 struct rtw89_btc_wl_info *wl = &cx->wl; 7249 struct rtw89_btc_bt_link_info *b = &cx->bt.link_info; 7250 struct rtw89_btc_bt_hfp_desc *hfp = &b->hfp_desc; 7251 struct rtw89_btc_bt_hid_desc *hid = &b->hid_desc; 7252 u32 cnt; 7253 u32 delay = RTW89_COEX_ACT1_WORK_PERIOD; 7254 bool delay_work = false; 7255 7256 switch (pkt_type) { 7257 case PACKET_DHCP: 7258 cnt = ++cx->cnt_wl[BTC_WCNT_DHCP]; 7259 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7260 "[BTC], %s(): DHCP cnt=%d\n", __func__, cnt); 7261 wl->status.map.connecting = true; 7262 delay_work = true; 7263 break; 7264 case PACKET_EAPOL: 7265 cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL]; 7266 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7267 "[BTC], %s(): EAPOL cnt=%d\n", __func__, cnt); 7268 wl->status.map._4way = true; 7269 delay_work = true; 7270 if (hfp->exist || hid->exist) 7271 delay /= 2; 7272 break; 7273 case PACKET_EAPOL_END: 7274 cnt = ++cx->cnt_wl[BTC_WCNT_EAPOL]; 7275 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7276 "[BTC], %s(): EAPOL_End cnt=%d\n", 7277 __func__, cnt); 7278 wl->status.map._4way = false; 7279 cancel_delayed_work(&rtwdev->coex_act1_work); 7280 break; 7281 case PACKET_ARP: 7282 cnt = ++cx->cnt_wl[BTC_WCNT_ARP]; 7283 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7284 "[BTC], %s(): ARP cnt=%d\n", __func__, cnt); 7285 return; 7286 case PACKET_ICMP: 7287 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7288 "[BTC], %s(): ICMP pkt\n", __func__); 7289 return; 7290 default: 7291 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7292 "[BTC], %s(): unknown packet type %d\n", 7293 __func__, pkt_type); 7294 return; 7295 } 7296 7297 if (delay_work) { 7298 cancel_delayed_work(&rtwdev->coex_act1_work); 7299 ieee80211_queue_delayed_work(rtwdev->hw, 7300 &rtwdev->coex_act1_work, delay); 7301 } 7302 7303 btc->dm.cnt_notify[BTC_NCNT_SPECIAL_PACKET]++; 7304 _run_coex(rtwdev, BTC_RSN_NTFY_SPECIFIC_PACKET); 7305 } 7306 7307 void rtw89_btc_ntfy_eapol_packet_work(struct work_struct *work) 7308 { 7309 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 7310 btc.eapol_notify_work); 7311 7312 mutex_lock(&rtwdev->mutex); 7313 rtw89_leave_ps_mode(rtwdev); 7314 rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_EAPOL); 7315 mutex_unlock(&rtwdev->mutex); 7316 } 7317 7318 void rtw89_btc_ntfy_arp_packet_work(struct work_struct *work) 7319 { 7320 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 7321 btc.arp_notify_work); 7322 7323 mutex_lock(&rtwdev->mutex); 7324 rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_ARP); 7325 mutex_unlock(&rtwdev->mutex); 7326 } 7327 7328 void rtw89_btc_ntfy_dhcp_packet_work(struct work_struct *work) 7329 { 7330 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 7331 btc.dhcp_notify_work); 7332 7333 mutex_lock(&rtwdev->mutex); 7334 rtw89_leave_ps_mode(rtwdev); 7335 rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_DHCP); 7336 mutex_unlock(&rtwdev->mutex); 7337 } 7338 7339 void rtw89_btc_ntfy_icmp_packet_work(struct work_struct *work) 7340 { 7341 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev, 7342 btc.icmp_notify_work); 7343 7344 mutex_lock(&rtwdev->mutex); 7345 rtw89_leave_ps_mode(rtwdev); 7346 rtw89_btc_ntfy_specific_packet(rtwdev, PACKET_ICMP); 7347 mutex_unlock(&rtwdev->mutex); 7348 } 7349 7350 static u8 _update_bt_rssi_level(struct rtw89_dev *rtwdev, u8 rssi) 7351 { 7352 const struct rtw89_chip_info *chip = rtwdev->chip; 7353 struct rtw89_btc *btc = &rtwdev->btc; 7354 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 7355 u8 *rssi_st, rssi_th, rssi_level = 0; 7356 u8 i; 7357 7358 /* for rssi locate in which {40, 36, 31, 28} 7359 * if rssi >= 40% (-60dBm) --> rssi_level = 4 7360 * if 36% <= rssi < 40% --> rssi_level = 3 7361 * if 31% <= rssi < 36% --> rssi_level = 2 7362 * if 28% <= rssi < 31% --> rssi_level = 1 7363 * if rssi < 28% --> rssi_level = 0 7364 */ 7365 7366 /* check if rssi across bt_rssi_thres boundary */ 7367 for (i = 0; i < BTC_BT_RSSI_THMAX; i++) { 7368 rssi_th = chip->bt_rssi_thres[i]; 7369 rssi_st = &bt->link_info.rssi_state[i]; 7370 7371 *rssi_st = _update_rssi_state(rtwdev, *rssi_st, rssi, rssi_th); 7372 7373 if (BTC_RSSI_HIGH(*rssi_st)) { 7374 rssi_level = BTC_BT_RSSI_THMAX - i; 7375 break; 7376 } 7377 } 7378 return rssi_level; 7379 } 7380 7381 static void _update_zb_coex_tbl(struct rtw89_dev *rtwdev) 7382 { 7383 u8 mode = rtwdev->btc.cx.wl.role_info.link_mode; 7384 u32 zb_tbl0 = 0xda5a5a5a, zb_tbl1 = 0xda5a5a5a; 7385 7386 if (mode == BTC_WLINK_5G || rtwdev->btc.dm.freerun) { 7387 zb_tbl0 = 0xffffffff; 7388 zb_tbl1 = 0xffffffff; 7389 } else if (mode == BTC_WLINK_25G_MCC) { 7390 zb_tbl0 = 0xffffffff; /* for E5G slot */ 7391 zb_tbl1 = 0xda5a5a5a; /* for E2G slot */ 7392 } 7393 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_0, zb_tbl0); 7394 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_1, zb_tbl1); 7395 } 7396 7397 #define BT_PROFILE_PROTOCOL_MASK GENMASK(7, 4) 7398 7399 static void _update_bt_info(struct rtw89_dev *rtwdev, u8 *buf, u32 len) 7400 { 7401 const struct rtw89_chip_info *chip = rtwdev->chip; 7402 struct rtw89_btc *btc = &rtwdev->btc; 7403 struct rtw89_btc_cx *cx = &btc->cx; 7404 struct rtw89_btc_bt_info *bt = &cx->bt; 7405 struct rtw89_btc_bt_link_info *b = &bt->link_info; 7406 struct rtw89_btc_bt_hfp_desc *hfp = &b->hfp_desc; 7407 struct rtw89_btc_bt_hid_desc *hid = &b->hid_desc; 7408 struct rtw89_btc_bt_a2dp_desc *a2dp = &b->a2dp_desc; 7409 struct rtw89_btc_bt_pan_desc *pan = &b->pan_desc; 7410 union btc_btinfo btinfo; 7411 7412 if (buf[BTC_BTINFO_L1] != 6) 7413 return; 7414 7415 if (!memcmp(bt->raw_info, buf, BTC_BTINFO_MAX)) { 7416 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7417 "[BTC], %s(): return by bt-info duplicate!!\n", 7418 __func__); 7419 cx->cnt_bt[BTC_BCNT_INFOSAME]++; 7420 return; 7421 } 7422 7423 memcpy(bt->raw_info, buf, BTC_BTINFO_MAX); 7424 7425 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7426 "[BTC], %s(): bt_info[2]=0x%02x\n", 7427 __func__, bt->raw_info[2]); 7428 7429 b->profile_cnt.last = b->profile_cnt.now; 7430 b->profile_cnt.now = 0; 7431 hid->type = 0; 7432 7433 /* parse raw info low-Byte2 */ 7434 btinfo.val = bt->raw_info[BTC_BTINFO_L2]; 7435 b->status.map.connect = btinfo.lb2.connect; 7436 b->status.map.sco_busy = btinfo.lb2.sco_busy; 7437 b->status.map.acl_busy = btinfo.lb2.acl_busy; 7438 b->status.map.inq_pag = btinfo.lb2.inq_pag; 7439 bt->inq_pag.now = btinfo.lb2.inq_pag; 7440 cx->cnt_bt[BTC_BCNT_INQPAG] += !!(bt->inq_pag.now && !bt->inq_pag.last); 7441 7442 hfp->exist = btinfo.lb2.hfp; 7443 b->profile_cnt.now += (u8)hfp->exist; 7444 hid->exist = btinfo.lb2.hid; 7445 b->profile_cnt.now += (u8)hid->exist; 7446 a2dp->exist = btinfo.lb2.a2dp; 7447 b->profile_cnt.now += (u8)a2dp->exist; 7448 pan->exist = btinfo.lb2.pan; 7449 b->profile_cnt.now += (u8)pan->exist; 7450 btc->dm.trx_info.bt_profile = u32_get_bits(btinfo.val, BT_PROFILE_PROTOCOL_MASK); 7451 7452 /* parse raw info low-Byte3 */ 7453 btinfo.val = bt->raw_info[BTC_BTINFO_L3]; 7454 if (btinfo.lb3.retry != 0) 7455 cx->cnt_bt[BTC_BCNT_RETRY]++; 7456 b->cqddr = btinfo.lb3.cqddr; 7457 cx->cnt_bt[BTC_BCNT_INQ] += !!(btinfo.lb3.inq && !bt->inq); 7458 bt->inq = btinfo.lb3.inq; 7459 cx->cnt_bt[BTC_BCNT_PAGE] += !!(btinfo.lb3.pag && !bt->pag); 7460 bt->pag = btinfo.lb3.pag; 7461 7462 b->status.map.mesh_busy = btinfo.lb3.mesh_busy; 7463 /* parse raw info high-Byte0 */ 7464 btinfo.val = bt->raw_info[BTC_BTINFO_H0]; 7465 /* raw val is dBm unit, translate from -100~ 0dBm to 0~100%*/ 7466 b->rssi = chip->ops->btc_get_bt_rssi(rtwdev, btinfo.hb0.rssi); 7467 bt->rssi_level = _update_bt_rssi_level(rtwdev, b->rssi); 7468 btc->dm.trx_info.bt_rssi = bt->rssi_level; 7469 7470 /* parse raw info high-Byte1 */ 7471 btinfo.val = bt->raw_info[BTC_BTINFO_H1]; 7472 b->status.map.ble_connect = btinfo.hb1.ble_connect; 7473 if (btinfo.hb1.ble_connect) { 7474 if (hid->exist) 7475 hid->type |= BTC_HID_BLE; 7476 else if (btinfo.hb1.voice) 7477 hid->type |= BTC_HID_RCU_VOICE; 7478 else 7479 hid->type |= BTC_HID_RCU; 7480 } 7481 7482 cx->cnt_bt[BTC_BCNT_REINIT] += !!(btinfo.hb1.reinit && !bt->reinit); 7483 bt->reinit = btinfo.hb1.reinit; 7484 cx->cnt_bt[BTC_BCNT_RELINK] += !!(btinfo.hb1.relink && !b->relink.now); 7485 b->relink.now = btinfo.hb1.relink; 7486 cx->cnt_bt[BTC_BCNT_IGNOWL] += !!(btinfo.hb1.igno_wl && !bt->igno_wl); 7487 bt->igno_wl = btinfo.hb1.igno_wl; 7488 7489 if (bt->igno_wl && !cx->wl.status.map.rf_off) 7490 _set_bt_ignore_wlan_act(rtwdev, false); 7491 7492 bt->ble_scan_en = btinfo.hb1.ble_scan; 7493 7494 cx->cnt_bt[BTC_BCNT_ROLESW] += !!(btinfo.hb1.role_sw && !b->role_sw); 7495 b->role_sw = btinfo.hb1.role_sw; 7496 7497 b->multi_link.now = btinfo.hb1.multi_link; 7498 7499 /* parse raw info high-Byte2 */ 7500 btinfo.val = bt->raw_info[BTC_BTINFO_H2]; 7501 pan->active = !!btinfo.hb2.pan_active; 7502 7503 cx->cnt_bt[BTC_BCNT_AFH] += !!(btinfo.hb2.afh_update && !b->afh_update); 7504 b->afh_update = btinfo.hb2.afh_update; 7505 a2dp->active = btinfo.hb2.a2dp_active; 7506 b->slave_role = btinfo.hb2.slave; 7507 hid->slot_info = btinfo.hb2.hid_slot; 7508 hid->pair_cnt = btinfo.hb2.hid_cnt; 7509 if (!b->status.map.ble_connect || hid->pair_cnt > 1) 7510 hid->type |= (hid->slot_info == BTC_HID_218 ? 7511 BTC_HID_218 : BTC_HID_418); 7512 /* parse raw info high-Byte3 */ 7513 btinfo.val = bt->raw_info[BTC_BTINFO_H3]; 7514 a2dp->bitpool = btinfo.hb3.a2dp_bitpool; 7515 7516 if (b->tx_3m != (u32)btinfo.hb3.tx_3m) 7517 cx->cnt_bt[BTC_BCNT_RATECHG]++; 7518 b->tx_3m = (u32)btinfo.hb3.tx_3m; 7519 7520 a2dp->sink = btinfo.hb3.a2dp_sink; 7521 7522 if (!a2dp->exist_last && a2dp->exist) { 7523 a2dp->vendor_id = 0; 7524 a2dp->flush_time = 0; 7525 a2dp->play_latency = 1; 7526 ieee80211_queue_delayed_work(rtwdev->hw, 7527 &rtwdev->coex_bt_devinfo_work, 7528 RTW89_COEX_BT_DEVINFO_WORK_PERIOD); 7529 } 7530 7531 _run_coex(rtwdev, BTC_RSN_UPDATE_BT_INFO); 7532 } 7533 7534 void rtw89_btc_ntfy_role_info(struct rtw89_dev *rtwdev, 7535 struct rtw89_vif_link *rtwvif_link, 7536 struct rtw89_sta_link *rtwsta_link, 7537 enum btc_role_state state) 7538 { 7539 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, 7540 rtwvif_link->chanctx_idx); 7541 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link); 7542 struct ieee80211_bss_conf *bss_conf; 7543 struct ieee80211_link_sta *link_sta; 7544 struct rtw89_btc *btc = &rtwdev->btc; 7545 const struct rtw89_btc_ver *ver = btc->ver; 7546 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 7547 struct rtw89_btc_wl_link_info r = {0}; 7548 struct rtw89_btc_wl_link_info *wlinfo = NULL; 7549 u8 mode = 0, rlink_id, link_mode_ori, pta_req_mac_ori, wa_type; 7550 7551 rcu_read_lock(); 7552 7553 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false); 7554 7555 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], state=%d\n", state); 7556 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7557 "[BTC], role is STA=%d\n", 7558 vif->type == NL80211_IFTYPE_STATION); 7559 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], port=%d\n", rtwvif_link->port); 7560 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], band=%d ch=%d bw=%d\n", 7561 chan->band_type, chan->channel, chan->band_width); 7562 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], associated=%d\n", 7563 state == BTC_ROLE_MSTS_STA_CONN_END); 7564 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7565 "[BTC], bcn_period=%d dtim_period=%d\n", 7566 bss_conf->beacon_int, bss_conf->dtim_period); 7567 7568 if (rtwsta_link) { 7569 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false); 7570 7571 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], STA mac_id=%d\n", 7572 rtwsta_link->mac_id); 7573 7574 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7575 "[BTC], STA support HE=%d VHT=%d HT=%d\n", 7576 link_sta->he_cap.has_he, 7577 link_sta->vht_cap.vht_supported, 7578 link_sta->ht_cap.ht_supported); 7579 if (link_sta->he_cap.has_he) 7580 mode |= BIT(BTC_WL_MODE_HE); 7581 if (link_sta->vht_cap.vht_supported) 7582 mode |= BIT(BTC_WL_MODE_VHT); 7583 if (link_sta->ht_cap.ht_supported) 7584 mode |= BIT(BTC_WL_MODE_HT); 7585 7586 r.mode = mode; 7587 } 7588 7589 if (rtwvif_link->wifi_role >= RTW89_WIFI_ROLE_MLME_MAX) { 7590 rcu_read_unlock(); 7591 return; 7592 } 7593 7594 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7595 "[BTC], wifi_role=%d\n", rtwvif_link->wifi_role); 7596 7597 r.role = rtwvif_link->wifi_role; 7598 r.phy = rtwvif_link->phy_idx; 7599 r.pid = rtwvif_link->port; 7600 r.active = true; 7601 r.connected = MLME_LINKED; 7602 r.bcn_period = bss_conf->beacon_int; 7603 r.dtim_period = bss_conf->dtim_period; 7604 r.band = chan->band_type; 7605 r.ch = chan->channel; 7606 r.bw = chan->band_width; 7607 r.chdef.band = chan->band_type; 7608 r.chdef.center_ch = chan->channel; 7609 r.chdef.bw = chan->band_width; 7610 r.chdef.chan = chan->primary_channel; 7611 ether_addr_copy(r.mac_addr, rtwvif_link->mac_addr); 7612 7613 rcu_read_unlock(); 7614 7615 if (rtwsta_link && vif->type == NL80211_IFTYPE_STATION) 7616 r.mac_id = rtwsta_link->mac_id; 7617 7618 btc->dm.cnt_notify[BTC_NCNT_ROLE_INFO]++; 7619 7620 wlinfo = &wl->link_info[r.pid]; 7621 7622 rlink_id = 0; /* to do */ 7623 if (ver->fwlrole == 0) { 7624 *wlinfo = r; 7625 _update_wl_info(rtwdev); 7626 } else if (ver->fwlrole == 1) { 7627 *wlinfo = r; 7628 _update_wl_info_v1(rtwdev); 7629 } else if (ver->fwlrole == 2) { 7630 *wlinfo = r; 7631 _update_wl_info_v2(rtwdev); 7632 } else if (ver->fwlrole == 7) { 7633 *wlinfo = r; 7634 _update_wl_info_v7(rtwdev, r.pid); 7635 } else if (ver->fwlrole == 8) { 7636 wlinfo = &wl->rlink_info[r.pid][rlink_id]; 7637 *wlinfo = r; 7638 link_mode_ori = wl->role_info_v8.link_mode; 7639 pta_req_mac_ori = wl->pta_req_mac; 7640 _update_wl_info_v8(rtwdev, r.pid, rlink_id, state); 7641 7642 if (wl->role_info_v8.link_mode != link_mode_ori) { 7643 wl->role_info_v8.link_mode_chg = 1; 7644 if (ver->fcxinit == 7) 7645 wa_type = btc->mdinfo.md_v7.wa_type; 7646 else 7647 wa_type = btc->mdinfo.md.wa_type; 7648 7649 if (wa_type & BTC_WA_HFP_ZB) 7650 _update_zb_coex_tbl(rtwdev); 7651 } 7652 7653 if (wl->pta_req_mac != pta_req_mac_ori) 7654 wl->pta_reg_mac_chg = 1; 7655 } 7656 7657 if (wlinfo->role == RTW89_WIFI_ROLE_STATION && 7658 wlinfo->connected == MLME_NO_LINK) 7659 btc->dm.leak_ap = 0; 7660 7661 if (state == BTC_ROLE_MSTS_STA_CONN_START) 7662 wl->status.map.connecting = 1; 7663 else 7664 wl->status.map.connecting = 0; 7665 7666 if (state == BTC_ROLE_MSTS_STA_DIS_CONN) 7667 wl->status.map._4way = false; 7668 7669 _run_coex(rtwdev, BTC_RSN_NTFY_ROLE_INFO); 7670 } 7671 7672 void rtw89_btc_ntfy_radio_state(struct rtw89_dev *rtwdev, enum btc_rfctrl rf_state) 7673 { 7674 const struct rtw89_chip_info *chip = rtwdev->chip; 7675 struct rtw89_btc *btc = &rtwdev->btc; 7676 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 7677 u32 val; 7678 7679 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): rf_state = %d\n", 7680 __func__, rf_state); 7681 btc->dm.cnt_notify[BTC_NCNT_RADIO_STATE]++; 7682 7683 switch (rf_state) { 7684 case BTC_RFCTRL_WL_OFF: 7685 wl->status.map.rf_off = 1; 7686 wl->status.map.lps = BTC_LPS_OFF; 7687 wl->status.map.busy = 0; 7688 break; 7689 case BTC_RFCTRL_FW_CTRL: 7690 wl->status.map.rf_off = 0; 7691 wl->status.map.lps = BTC_LPS_RF_OFF; 7692 wl->status.map.busy = 0; 7693 break; 7694 case BTC_RFCTRL_LPS_WL_ON: /* LPS-Protocol (RFon) */ 7695 wl->status.map.rf_off = 0; 7696 wl->status.map.lps = BTC_LPS_RF_ON; 7697 wl->status.map.busy = 0; 7698 break; 7699 case BTC_RFCTRL_WL_ON: 7700 default: 7701 wl->status.map.rf_off = 0; 7702 wl->status.map.lps = BTC_LPS_OFF; 7703 break; 7704 } 7705 7706 if (rf_state == BTC_RFCTRL_WL_ON) { 7707 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_MREG, true); 7708 val = BTC_WSCB_ACTIVE | BTC_WSCB_ON | BTC_WSCB_BTLOG; 7709 _write_scbd(rtwdev, val, true); 7710 _update_bt_scbd(rtwdev, true); 7711 chip->ops->btc_init_cfg(rtwdev); 7712 } else { 7713 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_ALL, false); 7714 if (rf_state == BTC_RFCTRL_FW_CTRL) 7715 _write_scbd(rtwdev, BTC_WSCB_ACTIVE, false); 7716 else if (rf_state == BTC_RFCTRL_WL_OFF) 7717 _write_scbd(rtwdev, BTC_WSCB_ALL, false); 7718 else 7719 _write_scbd(rtwdev, BTC_WSCB_ACTIVE, false); 7720 7721 if (rf_state == BTC_RFCTRL_LPS_WL_ON && 7722 wl->status.map.lps_pre != BTC_LPS_OFF) 7723 _update_bt_scbd(rtwdev, true); 7724 } 7725 7726 btc->dm.cnt_dm[BTC_DCNT_BTCNT_HANG] = 0; 7727 btc->dm.tdma_instant_excute = 1; 7728 7729 _run_coex(rtwdev, BTC_RSN_NTFY_RADIO_STATE); 7730 wl->status.map.rf_off_pre = wl->status.map.rf_off; 7731 wl->status.map.lps_pre = wl->status.map.lps; 7732 } 7733 7734 static bool _ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_path, 7735 enum btc_wl_rfk_type type, 7736 enum btc_wl_rfk_state state) 7737 { 7738 struct rtw89_btc *btc = &rtwdev->btc; 7739 struct rtw89_btc_cx *cx = &btc->cx; 7740 struct rtw89_btc_wl_info *wl = &cx->wl; 7741 bool result = BTC_WRFK_REJECT; 7742 7743 wl->rfk_info.type = type; 7744 wl->rfk_info.path_map = FIELD_GET(BTC_RFK_PATH_MAP, phy_path); 7745 wl->rfk_info.phy_map = FIELD_GET(BTC_RFK_PHY_MAP, phy_path); 7746 wl->rfk_info.band = FIELD_GET(BTC_RFK_BAND_MAP, phy_path); 7747 7748 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7749 "[BTC], %s()_start: phy=0x%x, path=0x%x, type=%d, state=%d\n", 7750 __func__, wl->rfk_info.phy_map, wl->rfk_info.path_map, 7751 type, state); 7752 7753 switch (state) { 7754 case BTC_WRFK_START: 7755 result = _chk_wl_rfk_request(rtwdev); 7756 wl->rfk_info.state = result ? BTC_WRFK_START : BTC_WRFK_STOP; 7757 7758 _write_scbd(rtwdev, BTC_WSCB_WLRFK, result); 7759 7760 btc->dm.cnt_notify[BTC_NCNT_WL_RFK]++; 7761 break; 7762 case BTC_WRFK_ONESHOT_START: 7763 case BTC_WRFK_ONESHOT_STOP: 7764 if (wl->rfk_info.state == BTC_WRFK_STOP) { 7765 result = BTC_WRFK_REJECT; 7766 } else { 7767 result = BTC_WRFK_ALLOW; 7768 wl->rfk_info.state = state; 7769 } 7770 break; 7771 case BTC_WRFK_STOP: 7772 result = BTC_WRFK_ALLOW; 7773 wl->rfk_info.state = BTC_WRFK_STOP; 7774 7775 _write_scbd(rtwdev, BTC_WSCB_WLRFK, false); 7776 cancel_delayed_work(&rtwdev->coex_rfk_chk_work); 7777 break; 7778 default: 7779 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7780 "[BTC], %s() warning state=%d\n", __func__, state); 7781 break; 7782 } 7783 7784 if (result == BTC_WRFK_ALLOW) { 7785 if (wl->rfk_info.state == BTC_WRFK_START || 7786 wl->rfk_info.state == BTC_WRFK_STOP) 7787 _run_coex(rtwdev, BTC_RSN_NTFY_WL_RFK); 7788 7789 if (wl->rfk_info.state == BTC_WRFK_START) 7790 ieee80211_queue_delayed_work(rtwdev->hw, 7791 &rtwdev->coex_rfk_chk_work, 7792 RTW89_COEX_RFK_CHK_WORK_PERIOD); 7793 } 7794 7795 rtw89_debug(rtwdev, RTW89_DBG_BTC, 7796 "[BTC], %s()_finish: rfk_cnt=%d, result=%d\n", 7797 __func__, btc->dm.cnt_notify[BTC_NCNT_WL_RFK], result); 7798 7799 return result == BTC_WRFK_ALLOW; 7800 } 7801 7802 void rtw89_btc_ntfy_wl_rfk(struct rtw89_dev *rtwdev, u8 phy_map, 7803 enum btc_wl_rfk_type type, 7804 enum btc_wl_rfk_state state) 7805 { 7806 u8 band; 7807 bool allow; 7808 int ret; 7809 7810 band = FIELD_GET(BTC_RFK_BAND_MAP, phy_map); 7811 7812 rtw89_debug(rtwdev, RTW89_DBG_RFK, 7813 "[RFK] RFK notify (%s / PHY%u / K_type = %u / path_idx = %lu / process = %s)\n", 7814 band == RTW89_BAND_2G ? "2G" : 7815 band == RTW89_BAND_5G ? "5G" : "6G", 7816 !!(FIELD_GET(BTC_RFK_PHY_MAP, phy_map) & BIT(RTW89_PHY_1)), 7817 type, 7818 FIELD_GET(BTC_RFK_PATH_MAP, phy_map), 7819 state == BTC_WRFK_STOP ? "RFK_STOP" : 7820 state == BTC_WRFK_START ? "RFK_START" : 7821 state == BTC_WRFK_ONESHOT_START ? "ONE-SHOT_START" : 7822 "ONE-SHOT_STOP"); 7823 7824 if (state != BTC_WRFK_START || rtwdev->is_bt_iqk_timeout) { 7825 _ntfy_wl_rfk(rtwdev, phy_map, type, state); 7826 return; 7827 } 7828 7829 ret = read_poll_timeout(_ntfy_wl_rfk, allow, allow, 40, 100000, false, 7830 rtwdev, phy_map, type, state); 7831 if (ret) { 7832 rtw89_warn(rtwdev, "RFK notify timeout\n"); 7833 rtwdev->is_bt_iqk_timeout = true; 7834 } 7835 } 7836 EXPORT_SYMBOL(rtw89_btc_ntfy_wl_rfk); 7837 7838 struct rtw89_btc_wl_sta_iter_data { 7839 struct rtw89_dev *rtwdev; 7840 u8 busy_all; 7841 u8 dir_all; 7842 u8 rssi_map_all; 7843 bool is_sta_change; 7844 bool is_traffic_change; 7845 }; 7846 7847 static 7848 void __rtw89_btc_ntfy_wl_sta_iter(struct rtw89_vif_link *rtwvif_link, 7849 struct rtw89_sta_link *rtwsta_link, 7850 struct rtw89_btc_wl_sta_iter_data *iter_data) 7851 { 7852 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif; 7853 struct rtw89_dev *rtwdev = iter_data->rtwdev; 7854 struct rtw89_btc *btc = &rtwdev->btc; 7855 struct rtw89_btc_dm *dm = &btc->dm; 7856 const struct rtw89_btc_ver *ver = btc->ver; 7857 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 7858 struct rtw89_btc_wl_link_info *link_info = NULL; 7859 struct rtw89_traffic_stats *link_info_t = NULL; 7860 struct rtw89_traffic_stats *stats = &rtwvif->stats; 7861 const struct rtw89_chip_info *chip = rtwdev->chip; 7862 struct rtw89_btc_wl_role_info *r; 7863 struct rtw89_btc_wl_role_info_v1 *r1; 7864 u32 last_tx_rate, last_rx_rate; 7865 u16 last_tx_lvl, last_rx_lvl; 7866 u8 port = rtwvif_link->port; 7867 u8 rssi; 7868 u8 busy = 0; 7869 u8 dir = 0; 7870 u8 rssi_map = 0; 7871 u8 i = 0; 7872 bool is_sta_change = false, is_traffic_change = false; 7873 7874 rssi = ewma_rssi_read(&rtwsta_link->avg_rssi) >> RSSI_FACTOR; 7875 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], rssi=%d\n", rssi); 7876 7877 link_info = &wl->link_info[port]; 7878 link_info->stat.traffic = *stats; 7879 link_info_t = &link_info->stat.traffic; 7880 7881 if (link_info->connected == MLME_NO_LINK) { 7882 link_info->rx_rate_drop_cnt = 0; 7883 return; 7884 } 7885 7886 link_info->stat.rssi = rssi; 7887 for (i = 0; i < BTC_WL_RSSI_THMAX; i++) { 7888 link_info->rssi_state[i] = 7889 _update_rssi_state(rtwdev, 7890 link_info->rssi_state[i], 7891 link_info->stat.rssi, 7892 chip->wl_rssi_thres[i]); 7893 if (BTC_RSSI_LOW(link_info->rssi_state[i])) 7894 rssi_map |= BIT(i); 7895 7896 if (btc->ant_type == BTC_ANT_DEDICATED && 7897 BTC_RSSI_CHANGE(link_info->rssi_state[i])) 7898 is_sta_change = true; 7899 } 7900 iter_data->rssi_map_all |= rssi_map; 7901 7902 last_tx_rate = link_info_t->tx_rate; 7903 last_rx_rate = link_info_t->rx_rate; 7904 last_tx_lvl = (u16)link_info_t->tx_tfc_lv; 7905 last_rx_lvl = (u16)link_info_t->rx_tfc_lv; 7906 7907 if (stats->tx_tfc_lv != RTW89_TFC_IDLE || 7908 stats->rx_tfc_lv != RTW89_TFC_IDLE) 7909 busy = 1; 7910 7911 if (stats->tx_tfc_lv > stats->rx_tfc_lv) 7912 dir = RTW89_TFC_UL; 7913 else 7914 dir = RTW89_TFC_DL; 7915 7916 link_info = &wl->link_info[port]; 7917 if (link_info->busy != busy || link_info->dir != dir) { 7918 is_sta_change = true; 7919 link_info->busy = busy; 7920 link_info->dir = dir; 7921 } 7922 7923 iter_data->busy_all |= busy; 7924 iter_data->dir_all |= BIT(dir); 7925 7926 if (rtwsta_link->rx_hw_rate <= RTW89_HW_RATE_CCK2 && 7927 last_rx_rate > RTW89_HW_RATE_CCK2 && 7928 link_info_t->rx_tfc_lv > RTW89_TFC_IDLE) 7929 link_info->rx_rate_drop_cnt++; 7930 7931 if (last_tx_rate != rtwsta_link->ra_report.hw_rate || 7932 last_rx_rate != rtwsta_link->rx_hw_rate || 7933 last_tx_lvl != link_info_t->tx_tfc_lv || 7934 last_rx_lvl != link_info_t->rx_tfc_lv) 7935 is_traffic_change = true; 7936 7937 link_info_t->tx_rate = rtwsta_link->ra_report.hw_rate; 7938 link_info_t->rx_rate = rtwsta_link->rx_hw_rate; 7939 7940 if (link_info->role == RTW89_WIFI_ROLE_STATION || 7941 link_info->role == RTW89_WIFI_ROLE_P2P_CLIENT) { 7942 dm->trx_info.tx_rate = link_info_t->tx_rate; 7943 dm->trx_info.rx_rate = link_info_t->rx_rate; 7944 } 7945 7946 if (ver->fwlrole == 0) { 7947 r = &wl->role_info; 7948 r->active_role[port].tx_lvl = stats->tx_tfc_lv; 7949 r->active_role[port].rx_lvl = stats->rx_tfc_lv; 7950 r->active_role[port].tx_rate = rtwsta_link->ra_report.hw_rate; 7951 r->active_role[port].rx_rate = rtwsta_link->rx_hw_rate; 7952 } else if (ver->fwlrole == 1) { 7953 r1 = &wl->role_info_v1; 7954 r1->active_role_v1[port].tx_lvl = stats->tx_tfc_lv; 7955 r1->active_role_v1[port].rx_lvl = stats->rx_tfc_lv; 7956 r1->active_role_v1[port].tx_rate = rtwsta_link->ra_report.hw_rate; 7957 r1->active_role_v1[port].rx_rate = rtwsta_link->rx_hw_rate; 7958 } else if (ver->fwlrole == 2) { 7959 dm->trx_info.tx_lvl = stats->tx_tfc_lv; 7960 dm->trx_info.rx_lvl = stats->rx_tfc_lv; 7961 dm->trx_info.tx_rate = rtwsta_link->ra_report.hw_rate; 7962 dm->trx_info.rx_rate = rtwsta_link->rx_hw_rate; 7963 } 7964 7965 dm->trx_info.tx_tp = link_info_t->tx_throughput; 7966 dm->trx_info.rx_tp = link_info_t->rx_throughput; 7967 7968 /* Trigger coex-run if 0x10980 reg-value is diff with coex setup */ 7969 if ((dm->wl_btg_rx_rb != dm->wl_btg_rx && 7970 dm->wl_btg_rx_rb != BTC_BTGCTRL_BB_GNT_NOTFOUND) || 7971 (dm->wl_pre_agc_rb != dm->wl_pre_agc && 7972 dm->wl_pre_agc_rb != BTC_PREAGC_NOTFOUND)) 7973 iter_data->is_sta_change = true; 7974 7975 if (is_sta_change) 7976 iter_data->is_sta_change = true; 7977 7978 if (is_traffic_change) 7979 iter_data->is_traffic_change = true; 7980 } 7981 7982 static void rtw89_btc_ntfy_wl_sta_iter(void *data, struct ieee80211_sta *sta) 7983 { 7984 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta); 7985 struct rtw89_btc_wl_sta_iter_data *iter_data = 7986 (struct rtw89_btc_wl_sta_iter_data *)data; 7987 struct rtw89_vif_link *rtwvif_link; 7988 struct rtw89_sta_link *rtwsta_link; 7989 unsigned int link_id; 7990 7991 rtw89_sta_for_each_link(rtwsta, rtwsta_link, link_id) { 7992 rtwvif_link = rtwsta_link->rtwvif_link; 7993 __rtw89_btc_ntfy_wl_sta_iter(rtwvif_link, rtwsta_link, iter_data); 7994 } 7995 } 7996 7997 #define BTC_NHM_CHK_INTVL 20 7998 7999 void rtw89_btc_ntfy_wl_sta(struct rtw89_dev *rtwdev) 8000 { 8001 struct rtw89_btc *btc = &rtwdev->btc; 8002 struct rtw89_btc_dm *dm = &btc->dm; 8003 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 8004 struct rtw89_btc_wl_sta_iter_data data = {.rtwdev = rtwdev}; 8005 u8 i; 8006 8007 ieee80211_iterate_stations_atomic(rtwdev->hw, 8008 rtw89_btc_ntfy_wl_sta_iter, 8009 &data); 8010 8011 wl->rssi_level = 0; 8012 btc->dm.cnt_notify[BTC_NCNT_WL_STA]++; 8013 for (i = BTC_WL_RSSI_THMAX; i > 0; i--) { 8014 /* set RSSI level 4 ~ 0 if rssi bit map match */ 8015 if (data.rssi_map_all & BIT(i - 1)) { 8016 wl->rssi_level = i; 8017 break; 8018 } 8019 } 8020 8021 if (dm->trx_info.wl_rssi != wl->rssi_level) 8022 dm->trx_info.wl_rssi = wl->rssi_level; 8023 8024 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC], %s(): busy=%d\n", 8025 __func__, !!wl->status.map.busy); 8026 8027 _write_scbd(rtwdev, BTC_WSCB_WLBUSY, (!!wl->status.map.busy)); 8028 8029 if (data.is_traffic_change) 8030 _fw_set_drv_info(rtwdev, CXDRVINFO_ROLE); 8031 if (data.is_sta_change) { 8032 wl->status.map.busy = data.busy_all; 8033 wl->status.map.traffic_dir = data.dir_all; 8034 _run_coex(rtwdev, BTC_RSN_NTFY_WL_STA); 8035 } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] >= 8036 btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] + BTC_NHM_CHK_INTVL) { 8037 btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] = 8038 btc->dm.cnt_notify[BTC_NCNT_WL_STA]; 8039 } else if (btc->dm.cnt_notify[BTC_NCNT_WL_STA] < 8040 btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST]) { 8041 btc->dm.cnt_dm[BTC_DCNT_WL_STA_LAST] = 8042 btc->dm.cnt_notify[BTC_NCNT_WL_STA]; 8043 } 8044 } 8045 8046 static u8 rtw89_btc_c2h_get_index_by_ver(struct rtw89_dev *rtwdev, u8 func) 8047 { 8048 struct rtw89_btc *btc = &rtwdev->btc; 8049 const struct rtw89_btc_ver *ver = btc->ver; 8050 8051 switch (func) { 8052 case BTF_EVNT_RPT: 8053 case BTF_EVNT_BT_INFO: 8054 case BTF_EVNT_BT_SCBD: 8055 case BTF_EVNT_BT_REG: 8056 case BTF_EVNT_CX_RUNINFO: 8057 case BTF_EVNT_BT_PSD: 8058 return func; 8059 case BTF_EVNT_BT_DEV_INFO: 8060 if (ver->fwc2hfunc == 0) 8061 return BTF_EVNT_BUF_OVERFLOW; 8062 else 8063 return BTF_EVNT_BT_DEV_INFO; 8064 case BTF_EVNT_BT_LEAUDIO_INFO: 8065 if (ver->fwc2hfunc == 0) 8066 return BTF_EVNT_C2H_LOOPBACK; 8067 else if (ver->fwc2hfunc == 1) 8068 return BTF_EVNT_BUF_OVERFLOW; 8069 else if (ver->fwc2hfunc == 2) 8070 return func; 8071 else 8072 return BTF_EVNT_MAX; 8073 case BTF_EVNT_BUF_OVERFLOW: 8074 if (ver->fwc2hfunc == 0) 8075 return BTF_EVNT_MAX; 8076 else if (ver->fwc2hfunc == 1) 8077 return BTF_EVNT_C2H_LOOPBACK; 8078 else if (ver->fwc2hfunc == 2) 8079 return func; 8080 else 8081 return BTF_EVNT_MAX; 8082 case BTF_EVNT_C2H_LOOPBACK: 8083 if (ver->fwc2hfunc == 2) 8084 return func; 8085 else 8086 return BTF_EVNT_MAX; 8087 case BTF_EVNT_MAX: 8088 default: 8089 return BTF_EVNT_MAX; 8090 } 8091 } 8092 8093 void rtw89_btc_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 8094 u32 len, u8 class, u8 func) 8095 { 8096 struct rtw89_btc *btc = &rtwdev->btc; 8097 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 8098 u8 *buf = &skb->data[RTW89_C2H_HEADER_LEN]; 8099 8100 len -= RTW89_C2H_HEADER_LEN; 8101 8102 rtw89_debug(rtwdev, RTW89_DBG_BTC, 8103 "[BTC], %s(): C2H BT len:%d class:%d fun:%d\n", 8104 __func__, len, class, func); 8105 8106 if (class != BTFC_FW_EVENT) 8107 return; 8108 8109 func = rtw89_btc_c2h_get_index_by_ver(rtwdev, func); 8110 8111 switch (func) { 8112 case BTF_EVNT_BUF_OVERFLOW: 8113 pfwinfo->event[func]++; 8114 break; 8115 case BTF_EVNT_RPT: 8116 pfwinfo->event[func]++; 8117 /* Don't need rtw89_leave_ps_mode() */ 8118 btc_fw_event(rtwdev, func, buf, len); 8119 break; 8120 case BTF_EVNT_BT_INFO: 8121 rtw89_debug(rtwdev, RTW89_DBG_BTC, 8122 "[BTC], handle C2H BT INFO with data %8ph\n", buf); 8123 btc->cx.cnt_bt[BTC_BCNT_INFOUPDATE]++; 8124 _update_bt_info(rtwdev, buf, len); 8125 break; 8126 case BTF_EVNT_BT_SCBD: 8127 rtw89_debug(rtwdev, RTW89_DBG_BTC, 8128 "[BTC], handle C2H BT SCBD with data %8ph\n", buf); 8129 btc->cx.cnt_bt[BTC_BCNT_SCBDUPDATE]++; 8130 _update_bt_scbd(rtwdev, false); 8131 break; 8132 case BTF_EVNT_BT_PSD: 8133 break; 8134 case BTF_EVNT_BT_REG: 8135 btc->dbg.rb_done = true; 8136 btc->dbg.rb_val = le32_to_cpu(*((__le32 *)buf)); 8137 8138 break; 8139 case BTF_EVNT_C2H_LOOPBACK: 8140 btc->dbg.rb_done = true; 8141 btc->dbg.rb_val = buf[0]; 8142 break; 8143 case BTF_EVNT_CX_RUNINFO: 8144 btc->dm.cnt_dm[BTC_DCNT_CX_RUNINFO]++; 8145 break; 8146 } 8147 } 8148 8149 #define BTC_CX_FW_OFFLOAD 0 8150 8151 static void _show_cx_info(struct rtw89_dev *rtwdev, struct seq_file *m) 8152 { 8153 union rtw89_btc_module_info *md = &rtwdev->btc.mdinfo; 8154 const struct rtw89_chip_info *chip = rtwdev->chip; 8155 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 8156 struct rtw89_hal *hal = &rtwdev->hal; 8157 struct rtw89_btc *btc = &rtwdev->btc; 8158 struct rtw89_btc_dm *dm = &btc->dm; 8159 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 8160 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 8161 u32 ver_main = 0, ver_sub = 0, ver_hotfix = 0, id_branch = 0; 8162 u8 cv, rfe, iso, ant_num, ant_single_pos; 8163 8164 if (!(dm->coex_info_map & BTC_COEX_INFO_CX)) 8165 return; 8166 8167 dm->cnt_notify[BTC_NCNT_SHOW_COEX_INFO]++; 8168 8169 seq_printf(m, "========== [BTC COEX INFO (%d)] ==========\n", 8170 chip->chip_id); 8171 8172 ver_main = FIELD_GET(GENMASK(31, 24), RTW89_COEX_VERSION); 8173 ver_sub = FIELD_GET(GENMASK(23, 16), RTW89_COEX_VERSION); 8174 ver_hotfix = FIELD_GET(GENMASK(15, 8), RTW89_COEX_VERSION); 8175 id_branch = FIELD_GET(GENMASK(7, 0), RTW89_COEX_VERSION); 8176 seq_printf(m, " %-15s : Coex:%d.%d.%d(branch:%d), ", 8177 "[coex_version]", ver_main, ver_sub, ver_hotfix, id_branch); 8178 8179 ver_main = FIELD_GET(GENMASK(31, 24), wl->ver_info.fw_coex); 8180 ver_sub = FIELD_GET(GENMASK(23, 16), wl->ver_info.fw_coex); 8181 ver_hotfix = FIELD_GET(GENMASK(15, 8), wl->ver_info.fw_coex); 8182 id_branch = FIELD_GET(GENMASK(7, 0), wl->ver_info.fw_coex); 8183 seq_printf(m, "WL_FW_coex:%d.%d.%d(branch:%d)", 8184 ver_main, ver_sub, ver_hotfix, id_branch); 8185 8186 ver_main = FIELD_GET(GENMASK(31, 24), chip->wlcx_desired); 8187 ver_sub = FIELD_GET(GENMASK(23, 16), chip->wlcx_desired); 8188 ver_hotfix = FIELD_GET(GENMASK(15, 8), chip->wlcx_desired); 8189 seq_printf(m, "(%s, desired:%d.%d.%d), ", 8190 (wl->ver_info.fw_coex >= chip->wlcx_desired ? 8191 "Match" : "Mismatch"), ver_main, ver_sub, ver_hotfix); 8192 8193 seq_printf(m, "BT_FW_coex:%d(%s, desired:%d)\n", 8194 bt->ver_info.fw_coex, 8195 (bt->ver_info.fw_coex >= chip->btcx_desired ? 8196 "Match" : "Mismatch"), chip->btcx_desired); 8197 8198 if (bt->enable.now && bt->ver_info.fw == 0) 8199 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_VER_INFO, true); 8200 else 8201 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_VER_INFO, false); 8202 8203 ver_main = FIELD_GET(GENMASK(31, 24), wl->ver_info.fw); 8204 ver_sub = FIELD_GET(GENMASK(23, 16), wl->ver_info.fw); 8205 ver_hotfix = FIELD_GET(GENMASK(15, 8), wl->ver_info.fw); 8206 id_branch = FIELD_GET(GENMASK(7, 0), wl->ver_info.fw); 8207 seq_printf(m, " %-15s : WL_FW:%d.%d.%d.%d, BT_FW:0x%x(%s)\n", 8208 "[sub_module]", 8209 ver_main, ver_sub, ver_hotfix, id_branch, 8210 bt->ver_info.fw, bt->run_patch_code ? "patch" : "ROM"); 8211 8212 if (ver->fcxinit == 7) { 8213 cv = md->md_v7.kt_ver; 8214 rfe = md->md_v7.rfe_type; 8215 iso = md->md_v7.ant.isolation; 8216 ant_num = md->md_v7.ant.num; 8217 ant_single_pos = md->md_v7.ant.single_pos; 8218 } else { 8219 cv = md->md.cv; 8220 rfe = md->md.rfe_type; 8221 iso = md->md.ant.isolation; 8222 ant_num = md->md.ant.num; 8223 ant_single_pos = md->md.ant.single_pos; 8224 } 8225 8226 seq_printf(m, " %-15s : cv:%x, rfe_type:0x%x, ant_iso:%d, ant_pg:%d, %s", 8227 "[hw_info]", cv, rfe, iso, ant_num, 8228 ant_num > 1 ? "" : 8229 ant_single_pos ? "1Ant_Pos:S1, " : "1Ant_Pos:S0, "); 8230 8231 seq_printf(m, "3rd_coex:%d, dbcc:%d, tx_num:%d, rx_num:%d\n", 8232 btc->cx.other.type, rtwdev->dbcc_en, hal->tx_nss, 8233 hal->rx_nss); 8234 } 8235 8236 static void _show_wl_role_info(struct rtw89_dev *rtwdev, struct seq_file *m) 8237 { 8238 struct rtw89_btc *btc = &rtwdev->btc; 8239 struct rtw89_btc_wl_link_info *plink = NULL; 8240 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 8241 struct rtw89_btc_wl_dbcc_info *wl_dinfo = &wl->dbcc_info; 8242 struct rtw89_traffic_stats *t; 8243 u8 i; 8244 8245 if (rtwdev->dbcc_en) { 8246 seq_printf(m, 8247 " %-15s : PHY0_band(op:%d/scan:%d/real:%d), ", 8248 "[dbcc_info]", wl_dinfo->op_band[RTW89_PHY_0], 8249 wl_dinfo->scan_band[RTW89_PHY_0], 8250 wl_dinfo->real_band[RTW89_PHY_0]); 8251 seq_printf(m, 8252 "PHY1_band(op:%d/scan:%d/real:%d)\n", 8253 wl_dinfo->op_band[RTW89_PHY_1], 8254 wl_dinfo->scan_band[RTW89_PHY_1], 8255 wl_dinfo->real_band[RTW89_PHY_1]); 8256 } 8257 8258 for (i = 0; i < RTW89_PORT_NUM; i++) { 8259 if (btc->ver->fwlrole == 8) 8260 plink = &btc->cx.wl.rlink_info[i][0]; 8261 else 8262 plink = &btc->cx.wl.link_info[i]; 8263 8264 if (!plink->active) 8265 continue; 8266 8267 seq_printf(m, 8268 " [port_%d] : role=%d(phy-%d), connect=%d(client_cnt=%d), mode=%d, center_ch=%d, bw=%d", 8269 plink->pid, (u32)plink->role, plink->phy, 8270 (u32)plink->connected, plink->client_cnt - 1, 8271 (u32)plink->mode, plink->ch, (u32)plink->bw); 8272 8273 if (plink->connected == MLME_NO_LINK) 8274 continue; 8275 8276 seq_printf(m, 8277 ", mac_id=%d, max_tx_time=%dus, max_tx_retry=%d\n", 8278 plink->mac_id, plink->tx_time, plink->tx_retry); 8279 8280 seq_printf(m, 8281 " [port_%d] : rssi=-%ddBm(%d), busy=%d, dir=%s, ", 8282 plink->pid, 110 - plink->stat.rssi, 8283 plink->stat.rssi, plink->busy, 8284 plink->dir == RTW89_TFC_UL ? "UL" : "DL"); 8285 8286 t = &plink->stat.traffic; 8287 8288 seq_printf(m, 8289 "tx[rate:%d/busy_level:%d], ", 8290 (u32)t->tx_rate, t->tx_tfc_lv); 8291 8292 seq_printf(m, "rx[rate:%d/busy_level:%d/drop:%d]\n", 8293 (u32)t->rx_rate, 8294 t->rx_tfc_lv, plink->rx_rate_drop_cnt); 8295 } 8296 } 8297 8298 static void _show_wl_info(struct rtw89_dev *rtwdev, struct seq_file *m) 8299 { 8300 struct rtw89_btc *btc = &rtwdev->btc; 8301 const struct rtw89_btc_ver *ver = btc->ver; 8302 struct rtw89_btc_cx *cx = &btc->cx; 8303 struct rtw89_btc_wl_info *wl = &cx->wl; 8304 struct rtw89_btc_wl_role_info *wl_rinfo = &wl->role_info; 8305 struct rtw89_btc_wl_role_info_v1 *wl_rinfo_v1 = &wl->role_info_v1; 8306 struct rtw89_btc_wl_role_info_v2 *wl_rinfo_v2 = &wl->role_info_v2; 8307 struct rtw89_btc_wl_role_info_v7 *wl_rinfo_v7 = &wl->role_info_v7; 8308 struct rtw89_btc_wl_role_info_v8 *wl_rinfo_v8 = &wl->role_info_v8; 8309 u8 mode; 8310 8311 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_WL)) 8312 return; 8313 8314 seq_puts(m, "========== [WL Status] ==========\n"); 8315 8316 if (ver->fwlrole == 0) 8317 mode = wl_rinfo->link_mode; 8318 else if (ver->fwlrole == 1) 8319 mode = wl_rinfo_v1->link_mode; 8320 else if (ver->fwlrole == 2) 8321 mode = wl_rinfo_v2->link_mode; 8322 else if (ver->fwlrole == 7) 8323 mode = wl_rinfo_v7->link_mode; 8324 else if (ver->fwlrole == 8) 8325 mode = wl_rinfo_v8->link_mode; 8326 else 8327 return; 8328 8329 seq_printf(m, " %-15s : link_mode:%d, ", "[status]", mode); 8330 8331 seq_printf(m, 8332 "rf_off:%d, power_save:%d, scan:%s(band:%d/phy_map:0x%x), ", 8333 wl->status.map.rf_off, wl->status.map.lps, 8334 wl->status.map.scan ? "Y" : "N", 8335 wl->scan_info.band[RTW89_PHY_0], wl->scan_info.phy_map); 8336 8337 seq_printf(m, 8338 "connecting:%s, roam:%s, 4way:%s, init_ok:%s\n", 8339 wl->status.map.connecting ? "Y" : "N", 8340 wl->status.map.roaming ? "Y" : "N", 8341 wl->status.map._4way ? "Y" : "N", 8342 wl->status.map.init_ok ? "Y" : "N"); 8343 8344 _show_wl_role_info(rtwdev, m); 8345 } 8346 8347 enum btc_bt_a2dp_type { 8348 BTC_A2DP_LEGACY = 0, 8349 BTC_A2DP_TWS_SNIFF = 1, 8350 BTC_A2DP_TWS_RELAY = 2, 8351 }; 8352 8353 static void _show_bt_profile_info(struct rtw89_dev *rtwdev, struct seq_file *m) 8354 { 8355 struct rtw89_btc *btc = &rtwdev->btc; 8356 struct rtw89_btc_bt_link_info *bt_linfo = &btc->cx.bt.link_info; 8357 struct rtw89_btc_bt_hfp_desc hfp = bt_linfo->hfp_desc; 8358 struct rtw89_btc_bt_hid_desc hid = bt_linfo->hid_desc; 8359 struct rtw89_btc_bt_a2dp_desc a2dp = bt_linfo->a2dp_desc; 8360 struct rtw89_btc_bt_pan_desc pan = bt_linfo->pan_desc; 8361 8362 if (hfp.exist) { 8363 seq_printf(m, " %-15s : type:%s, sut_pwr:%d, golden-rx:%d", 8364 "[HFP]", (hfp.type == 0 ? "SCO" : "eSCO"), 8365 bt_linfo->sut_pwr_level[0], 8366 bt_linfo->golden_rx_shift[0]); 8367 } 8368 8369 if (hid.exist) { 8370 seq_printf(m, 8371 "\n\r %-15s : type:%s%s%s%s%s pair-cnt:%d, sut_pwr:%d, golden-rx:%d\n", 8372 "[HID]", 8373 hid.type & BTC_HID_218 ? "2/18," : "", 8374 hid.type & BTC_HID_418 ? "4/18," : "", 8375 hid.type & BTC_HID_BLE ? "BLE," : "", 8376 hid.type & BTC_HID_RCU ? "RCU," : "", 8377 hid.type & BTC_HID_RCU_VOICE ? "RCU-Voice," : "", 8378 hid.pair_cnt, bt_linfo->sut_pwr_level[1], 8379 bt_linfo->golden_rx_shift[1]); 8380 } 8381 8382 if (a2dp.exist) { 8383 seq_printf(m, 8384 " %-15s : type:%s, bit-pool:%d, flush-time:%d, ", 8385 "[A2DP]", 8386 a2dp.type == BTC_A2DP_LEGACY ? "Legacy" : "TWS", 8387 a2dp.bitpool, a2dp.flush_time); 8388 8389 seq_printf(m, 8390 "vid:0x%x, Dev-name:0x%x, sut_pwr:%d, golden-rx:%d\n", 8391 a2dp.vendor_id, a2dp.device_name, 8392 bt_linfo->sut_pwr_level[2], 8393 bt_linfo->golden_rx_shift[2]); 8394 } 8395 8396 if (pan.exist) { 8397 seq_printf(m, " %-15s : sut_pwr:%d, golden-rx:%d\n", 8398 "[PAN]", 8399 bt_linfo->sut_pwr_level[3], 8400 bt_linfo->golden_rx_shift[3]); 8401 } 8402 } 8403 8404 static void _show_bt_info(struct rtw89_dev *rtwdev, struct seq_file *m) 8405 { 8406 struct rtw89_btc *btc = &rtwdev->btc; 8407 const struct rtw89_btc_ver *ver = btc->ver; 8408 struct rtw89_btc_cx *cx = &btc->cx; 8409 struct rtw89_btc_bt_info *bt = &cx->bt; 8410 struct rtw89_btc_wl_info *wl = &cx->wl; 8411 struct rtw89_btc_bt_link_info *bt_linfo = &bt->link_info; 8412 union rtw89_btc_module_info *md = &btc->mdinfo; 8413 u8 *afh = bt_linfo->afh_map; 8414 u8 *afh_le = bt_linfo->afh_map_le; 8415 u8 bt_pos; 8416 8417 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_BT)) 8418 return; 8419 8420 if (ver->fcxinit == 7) 8421 bt_pos = md->md_v7.bt_pos; 8422 else 8423 bt_pos = md->md.bt_pos; 8424 8425 seq_puts(m, "========== [BT Status] ==========\n"); 8426 8427 seq_printf(m, " %-15s : enable:%s, btg:%s%s, connect:%s, ", 8428 "[status]", bt->enable.now ? "Y" : "N", 8429 bt->btg_type ? "Y" : "N", 8430 (bt->enable.now && (bt->btg_type != bt_pos) ? 8431 "(efuse-mismatch!!)" : ""), 8432 (bt_linfo->status.map.connect ? "Y" : "N")); 8433 8434 seq_printf(m, "igno_wl:%s, mailbox_avl:%s, rfk_state:0x%x\n", 8435 bt->igno_wl ? "Y" : "N", 8436 bt->mbx_avl ? "Y" : "N", bt->rfk_info.val); 8437 8438 seq_printf(m, " %-15s : profile:%s%s%s%s%s ", 8439 "[profile]", 8440 (bt_linfo->profile_cnt.now == 0) ? "None," : "", 8441 bt_linfo->hfp_desc.exist ? "HFP," : "", 8442 bt_linfo->hid_desc.exist ? "HID," : "", 8443 bt_linfo->a2dp_desc.exist ? 8444 (bt_linfo->a2dp_desc.sink ? "A2DP_sink," : "A2DP,") : "", 8445 bt_linfo->pan_desc.exist ? "PAN," : ""); 8446 8447 seq_printf(m, 8448 "multi-link:%s, role:%s, ble-connect:%s, CQDDR:%s, A2DP_active:%s, PAN_active:%s\n", 8449 bt_linfo->multi_link.now ? "Y" : "N", 8450 bt_linfo->slave_role ? "Slave" : "Master", 8451 bt_linfo->status.map.ble_connect ? "Y" : "N", 8452 bt_linfo->cqddr ? "Y" : "N", 8453 bt_linfo->a2dp_desc.active ? "Y" : "N", 8454 bt_linfo->pan_desc.active ? "Y" : "N"); 8455 8456 seq_printf(m, 8457 " %-15s : rssi:%ddBm(lvl:%d), tx_rate:%dM, %s%s%s", 8458 "[link]", bt_linfo->rssi - 100, 8459 bt->rssi_level, 8460 bt_linfo->tx_3m ? 3 : 2, 8461 bt_linfo->status.map.inq_pag ? " inq-page!!" : "", 8462 bt_linfo->status.map.acl_busy ? " acl_busy!!" : "", 8463 bt_linfo->status.map.mesh_busy ? " mesh_busy!!" : ""); 8464 8465 seq_printf(m, 8466 "%s afh_map[%02x%02x_%02x%02x_%02x%02x_%02x%02x_%02x%02x], ", 8467 bt_linfo->relink.now ? " ReLink!!" : "", 8468 afh[0], afh[1], afh[2], afh[3], afh[4], 8469 afh[5], afh[6], afh[7], afh[8], afh[9]); 8470 8471 if (ver->fcxbtafh == 2 && bt_linfo->status.map.ble_connect) 8472 seq_printf(m, 8473 "LE[%02x%02x_%02x_%02x%02x]", 8474 afh_le[0], afh_le[1], afh_le[2], 8475 afh_le[3], afh_le[4]); 8476 8477 seq_printf(m, "wl_ch_map[en:%d/ch:%d/bw:%d]\n", 8478 wl->afh_info.en, wl->afh_info.ch, wl->afh_info.bw); 8479 8480 seq_printf(m, 8481 " %-15s : retry:%d, relink:%d, rate_chg:%d, reinit:%d, reenable:%d, ", 8482 "[stat_cnt]", cx->cnt_bt[BTC_BCNT_RETRY], 8483 cx->cnt_bt[BTC_BCNT_RELINK], cx->cnt_bt[BTC_BCNT_RATECHG], 8484 cx->cnt_bt[BTC_BCNT_REINIT], cx->cnt_bt[BTC_BCNT_REENABLE]); 8485 8486 seq_printf(m, 8487 "role-switch:%d, afh:%d, inq_page:%d(inq:%d/page:%d), igno_wl:%d\n", 8488 cx->cnt_bt[BTC_BCNT_ROLESW], cx->cnt_bt[BTC_BCNT_AFH], 8489 cx->cnt_bt[BTC_BCNT_INQPAG], cx->cnt_bt[BTC_BCNT_INQ], 8490 cx->cnt_bt[BTC_BCNT_PAGE], cx->cnt_bt[BTC_BCNT_IGNOWL]); 8491 8492 _show_bt_profile_info(rtwdev, m); 8493 8494 seq_printf(m, 8495 " %-15s : raw_data[%02x %02x %02x %02x %02x %02x] (type:%s/cnt:%d/same:%d)\n", 8496 "[bt_info]", bt->raw_info[2], bt->raw_info[3], 8497 bt->raw_info[4], bt->raw_info[5], bt->raw_info[6], 8498 bt->raw_info[7], 8499 bt->raw_info[0] == BTC_BTINFO_AUTO ? "auto" : "reply", 8500 cx->cnt_bt[BTC_BCNT_INFOUPDATE], 8501 cx->cnt_bt[BTC_BCNT_INFOSAME]); 8502 8503 seq_printf(m, 8504 " %-15s : Hi-rx = %d, Hi-tx = %d, Lo-rx = %d, Lo-tx = %d (bt_polut_wl_tx = %d)", 8505 "[trx_req_cnt]", cx->cnt_bt[BTC_BCNT_HIPRI_RX], 8506 cx->cnt_bt[BTC_BCNT_HIPRI_TX], cx->cnt_bt[BTC_BCNT_LOPRI_RX], 8507 cx->cnt_bt[BTC_BCNT_LOPRI_TX], cx->cnt_bt[BTC_BCNT_POLUT]); 8508 8509 if (!bt->scan_info_update) { 8510 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_SCAN_INFO, true); 8511 seq_puts(m, "\n"); 8512 } else { 8513 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_SCAN_INFO, false); 8514 if (ver->fcxbtscan == 1) { 8515 seq_printf(m, 8516 "(INQ:%d-%d/PAGE:%d-%d/LE:%d-%d/INIT:%d-%d)", 8517 le16_to_cpu(bt->scan_info_v1[BTC_SCAN_INQ].win), 8518 le16_to_cpu(bt->scan_info_v1[BTC_SCAN_INQ].intvl), 8519 le16_to_cpu(bt->scan_info_v1[BTC_SCAN_PAGE].win), 8520 le16_to_cpu(bt->scan_info_v1[BTC_SCAN_PAGE].intvl), 8521 le16_to_cpu(bt->scan_info_v1[BTC_SCAN_BLE].win), 8522 le16_to_cpu(bt->scan_info_v1[BTC_SCAN_BLE].intvl), 8523 le16_to_cpu(bt->scan_info_v1[BTC_SCAN_INIT].win), 8524 le16_to_cpu(bt->scan_info_v1[BTC_SCAN_INIT].intvl)); 8525 } else if (ver->fcxbtscan == 2) { 8526 seq_printf(m, 8527 "(BG:%d-%d/INIT:%d-%d/LE:%d-%d)", 8528 le16_to_cpu(bt->scan_info_v2[CXSCAN_BG].win), 8529 le16_to_cpu(bt->scan_info_v2[CXSCAN_BG].intvl), 8530 le16_to_cpu(bt->scan_info_v2[CXSCAN_INIT].win), 8531 le16_to_cpu(bt->scan_info_v2[CXSCAN_INIT].intvl), 8532 le16_to_cpu(bt->scan_info_v2[CXSCAN_LE].win), 8533 le16_to_cpu(bt->scan_info_v2[CXSCAN_LE].intvl)); 8534 } 8535 seq_puts(m, "\n"); 8536 } 8537 8538 if (bt_linfo->profile_cnt.now || bt_linfo->status.map.ble_connect) 8539 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_AFH_MAP, true); 8540 else 8541 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_AFH_MAP, false); 8542 8543 if (ver->fcxbtafh == 2 && bt_linfo->status.map.ble_connect) 8544 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_AFH_MAP_LE, true); 8545 else 8546 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_AFH_MAP_LE, false); 8547 8548 if (bt_linfo->a2dp_desc.exist && 8549 (bt_linfo->a2dp_desc.flush_time == 0 || 8550 bt_linfo->a2dp_desc.vendor_id == 0 || 8551 bt_linfo->a2dp_desc.play_latency == 1)) 8552 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_DEVICE_INFO, true); 8553 else 8554 rtw89_btc_fw_en_rpt(rtwdev, RPT_EN_BT_DEVICE_INFO, false); 8555 } 8556 8557 #define CASE_BTC_RSN_STR(e) case BTC_RSN_ ## e: return #e 8558 #define CASE_BTC_ACT_STR(e) case BTC_ACT_ ## e | BTC_ACT_EXT_BIT: return #e 8559 #define CASE_BTC_POLICY_STR(e) \ 8560 case BTC_CXP_ ## e | BTC_POLICY_EXT_BIT: return #e 8561 #define CASE_BTC_SLOT_STR(e) case CXST_ ## e: return #e 8562 #define CASE_BTC_EVT_STR(e) case CXEVNT_## e: return #e 8563 #define CASE_BTC_INIT(e) case BTC_MODE_## e: return #e 8564 #define CASE_BTC_ANTPATH_STR(e) case BTC_ANT_##e: return #e 8565 #define CASE_BTC_POLUT_STR(e) case BTC_PLT_## e: return #e 8566 #define CASE_BTC_REGTYPE_STR(e) case REG_## e: return #e 8567 #define CASE_BTC_GDBG_STR(e) case BTC_DBG_## e: return #e 8568 8569 static const char *id_to_polut(u32 id) 8570 { 8571 switch (id) { 8572 CASE_BTC_POLUT_STR(NONE); 8573 CASE_BTC_POLUT_STR(GNT_BT_TX); 8574 CASE_BTC_POLUT_STR(GNT_BT_RX); 8575 CASE_BTC_POLUT_STR(GNT_WL); 8576 CASE_BTC_POLUT_STR(BT); 8577 CASE_BTC_POLUT_STR(ALL); 8578 default: 8579 return "unknown"; 8580 } 8581 } 8582 8583 static const char *id_to_regtype(u32 id) 8584 { 8585 switch (id) { 8586 CASE_BTC_REGTYPE_STR(MAC); 8587 CASE_BTC_REGTYPE_STR(BB); 8588 CASE_BTC_REGTYPE_STR(RF); 8589 CASE_BTC_REGTYPE_STR(BT_RF); 8590 CASE_BTC_REGTYPE_STR(BT_MODEM); 8591 CASE_BTC_REGTYPE_STR(BT_BLUEWIZE); 8592 CASE_BTC_REGTYPE_STR(BT_VENDOR); 8593 CASE_BTC_REGTYPE_STR(BT_LE); 8594 default: 8595 return "unknown"; 8596 } 8597 } 8598 8599 static const char *id_to_gdbg(u32 id) 8600 { 8601 switch (id) { 8602 CASE_BTC_GDBG_STR(GNT_BT); 8603 CASE_BTC_GDBG_STR(GNT_WL); 8604 CASE_BTC_GDBG_STR(BCN_EARLY); 8605 CASE_BTC_GDBG_STR(WL_NULL0); 8606 CASE_BTC_GDBG_STR(WL_NULL1); 8607 CASE_BTC_GDBG_STR(WL_RXISR); 8608 CASE_BTC_GDBG_STR(TDMA_ENTRY); 8609 CASE_BTC_GDBG_STR(A2DP_EMPTY); 8610 CASE_BTC_GDBG_STR(BT_RETRY); 8611 CASE_BTC_GDBG_STR(BT_RELINK); 8612 CASE_BTC_GDBG_STR(SLOT_WL); 8613 CASE_BTC_GDBG_STR(SLOT_BT); 8614 CASE_BTC_GDBG_STR(WL_ERR); 8615 CASE_BTC_GDBG_STR(WL_OK); 8616 CASE_BTC_GDBG_STR(SLOT_B2W); 8617 CASE_BTC_GDBG_STR(SLOT_W1); 8618 CASE_BTC_GDBG_STR(SLOT_W2); 8619 CASE_BTC_GDBG_STR(SLOT_W2B); 8620 CASE_BTC_GDBG_STR(SLOT_B1); 8621 CASE_BTC_GDBG_STR(SLOT_B2); 8622 CASE_BTC_GDBG_STR(SLOT_B3); 8623 CASE_BTC_GDBG_STR(SLOT_B4); 8624 CASE_BTC_GDBG_STR(SLOT_LK); 8625 CASE_BTC_GDBG_STR(SLOT_E2G); 8626 CASE_BTC_GDBG_STR(SLOT_E5G); 8627 CASE_BTC_GDBG_STR(SLOT_EBT); 8628 CASE_BTC_GDBG_STR(SLOT_WLK); 8629 CASE_BTC_GDBG_STR(SLOT_B1FDD); 8630 CASE_BTC_GDBG_STR(BT_CHANGE); 8631 CASE_BTC_GDBG_STR(WL_CCA); 8632 CASE_BTC_GDBG_STR(BT_LEAUDIO); 8633 CASE_BTC_GDBG_STR(USER_DEF); 8634 default: 8635 return "unknown"; 8636 } 8637 } 8638 8639 static const char *steps_to_str(u16 step) 8640 { 8641 switch (step) { 8642 CASE_BTC_RSN_STR(NONE); 8643 CASE_BTC_RSN_STR(NTFY_INIT); 8644 CASE_BTC_RSN_STR(NTFY_SWBAND); 8645 CASE_BTC_RSN_STR(NTFY_WL_STA); 8646 CASE_BTC_RSN_STR(NTFY_RADIO_STATE); 8647 CASE_BTC_RSN_STR(UPDATE_BT_SCBD); 8648 CASE_BTC_RSN_STR(NTFY_WL_RFK); 8649 CASE_BTC_RSN_STR(UPDATE_BT_INFO); 8650 CASE_BTC_RSN_STR(NTFY_SCAN_START); 8651 CASE_BTC_RSN_STR(NTFY_SCAN_FINISH); 8652 CASE_BTC_RSN_STR(NTFY_SPECIFIC_PACKET); 8653 CASE_BTC_RSN_STR(NTFY_POWEROFF); 8654 CASE_BTC_RSN_STR(NTFY_ROLE_INFO); 8655 CASE_BTC_RSN_STR(CMD_SET_COEX); 8656 CASE_BTC_RSN_STR(ACT1_WORK); 8657 CASE_BTC_RSN_STR(BT_DEVINFO_WORK); 8658 CASE_BTC_RSN_STR(RFK_CHK_WORK); 8659 8660 CASE_BTC_ACT_STR(NONE); 8661 CASE_BTC_ACT_STR(WL_ONLY); 8662 CASE_BTC_ACT_STR(WL_5G); 8663 CASE_BTC_ACT_STR(WL_OTHER); 8664 CASE_BTC_ACT_STR(WL_IDLE); 8665 CASE_BTC_ACT_STR(WL_NC); 8666 CASE_BTC_ACT_STR(WL_RFK); 8667 CASE_BTC_ACT_STR(WL_INIT); 8668 CASE_BTC_ACT_STR(WL_OFF); 8669 CASE_BTC_ACT_STR(FREERUN); 8670 CASE_BTC_ACT_STR(BT_WHQL); 8671 CASE_BTC_ACT_STR(BT_RFK); 8672 CASE_BTC_ACT_STR(BT_OFF); 8673 CASE_BTC_ACT_STR(BT_IDLE); 8674 CASE_BTC_ACT_STR(BT_HFP); 8675 CASE_BTC_ACT_STR(BT_HID); 8676 CASE_BTC_ACT_STR(BT_A2DP); 8677 CASE_BTC_ACT_STR(BT_A2DPSINK); 8678 CASE_BTC_ACT_STR(BT_PAN); 8679 CASE_BTC_ACT_STR(BT_A2DP_HID); 8680 CASE_BTC_ACT_STR(BT_A2DP_PAN); 8681 CASE_BTC_ACT_STR(BT_PAN_HID); 8682 CASE_BTC_ACT_STR(BT_A2DP_PAN_HID); 8683 CASE_BTC_ACT_STR(WL_25G_MCC); 8684 CASE_BTC_ACT_STR(WL_2G_MCC); 8685 CASE_BTC_ACT_STR(WL_2G_SCC); 8686 CASE_BTC_ACT_STR(WL_2G_AP); 8687 CASE_BTC_ACT_STR(WL_2G_GO); 8688 CASE_BTC_ACT_STR(WL_2G_GC); 8689 CASE_BTC_ACT_STR(WL_2G_NAN); 8690 8691 CASE_BTC_POLICY_STR(OFF_BT); 8692 CASE_BTC_POLICY_STR(OFF_WL); 8693 CASE_BTC_POLICY_STR(OFF_EQ0); 8694 CASE_BTC_POLICY_STR(OFF_EQ1); 8695 CASE_BTC_POLICY_STR(OFF_EQ2); 8696 CASE_BTC_POLICY_STR(OFF_EQ3); 8697 CASE_BTC_POLICY_STR(OFF_EQ4); 8698 CASE_BTC_POLICY_STR(OFF_EQ5); 8699 CASE_BTC_POLICY_STR(OFF_BWB0); 8700 CASE_BTC_POLICY_STR(OFF_BWB1); 8701 CASE_BTC_POLICY_STR(OFF_BWB2); 8702 CASE_BTC_POLICY_STR(OFF_BWB3); 8703 CASE_BTC_POLICY_STR(OFF_WL2); 8704 CASE_BTC_POLICY_STR(OFFB_BWB0); 8705 CASE_BTC_POLICY_STR(OFFE_DEF); 8706 CASE_BTC_POLICY_STR(OFFE_DEF2); 8707 CASE_BTC_POLICY_STR(OFFE_2GBWISOB); 8708 CASE_BTC_POLICY_STR(OFFE_2GISOB); 8709 CASE_BTC_POLICY_STR(OFFE_2GBWMIXB); 8710 CASE_BTC_POLICY_STR(OFFE_WL); 8711 CASE_BTC_POLICY_STR(OFFE_2GBWMIXB2); 8712 CASE_BTC_POLICY_STR(FIX_TD3030); 8713 CASE_BTC_POLICY_STR(FIX_TD5050); 8714 CASE_BTC_POLICY_STR(FIX_TD2030); 8715 CASE_BTC_POLICY_STR(FIX_TD4010); 8716 CASE_BTC_POLICY_STR(FIX_TD7010); 8717 CASE_BTC_POLICY_STR(FIX_TD2060); 8718 CASE_BTC_POLICY_STR(FIX_TD3060); 8719 CASE_BTC_POLICY_STR(FIX_TD2080); 8720 CASE_BTC_POLICY_STR(FIX_TDW1B1); 8721 CASE_BTC_POLICY_STR(FIX_TD4010ISO); 8722 CASE_BTC_POLICY_STR(FIX_TD4010ISO_DL); 8723 CASE_BTC_POLICY_STR(FIX_TD4010ISO_UL); 8724 CASE_BTC_POLICY_STR(PFIX_TD3030); 8725 CASE_BTC_POLICY_STR(PFIX_TD5050); 8726 CASE_BTC_POLICY_STR(PFIX_TD2030); 8727 CASE_BTC_POLICY_STR(PFIX_TD2060); 8728 CASE_BTC_POLICY_STR(PFIX_TD3070); 8729 CASE_BTC_POLICY_STR(PFIX_TD2080); 8730 CASE_BTC_POLICY_STR(PFIX_TDW1B1); 8731 CASE_BTC_POLICY_STR(AUTO_TD50B1); 8732 CASE_BTC_POLICY_STR(AUTO_TD60B1); 8733 CASE_BTC_POLICY_STR(AUTO_TD20B1); 8734 CASE_BTC_POLICY_STR(AUTO_TDW1B1); 8735 CASE_BTC_POLICY_STR(PAUTO_TD50B1); 8736 CASE_BTC_POLICY_STR(PAUTO_TD60B1); 8737 CASE_BTC_POLICY_STR(PAUTO_TD20B1); 8738 CASE_BTC_POLICY_STR(PAUTO_TDW1B1); 8739 CASE_BTC_POLICY_STR(AUTO2_TD3050); 8740 CASE_BTC_POLICY_STR(AUTO2_TD3070); 8741 CASE_BTC_POLICY_STR(AUTO2_TD5050); 8742 CASE_BTC_POLICY_STR(AUTO2_TD6060); 8743 CASE_BTC_POLICY_STR(AUTO2_TD2080); 8744 CASE_BTC_POLICY_STR(AUTO2_TDW1B4); 8745 CASE_BTC_POLICY_STR(PAUTO2_TD3050); 8746 CASE_BTC_POLICY_STR(PAUTO2_TD3070); 8747 CASE_BTC_POLICY_STR(PAUTO2_TD5050); 8748 CASE_BTC_POLICY_STR(PAUTO2_TD6060); 8749 CASE_BTC_POLICY_STR(PAUTO2_TD2080); 8750 CASE_BTC_POLICY_STR(PAUTO2_TDW1B4); 8751 default: 8752 return "unknown step"; 8753 } 8754 } 8755 8756 static const char *id_to_slot(u32 id) 8757 { 8758 switch (id) { 8759 CASE_BTC_SLOT_STR(OFF); 8760 CASE_BTC_SLOT_STR(B2W); 8761 CASE_BTC_SLOT_STR(W1); 8762 CASE_BTC_SLOT_STR(W2); 8763 CASE_BTC_SLOT_STR(W2B); 8764 CASE_BTC_SLOT_STR(B1); 8765 CASE_BTC_SLOT_STR(B2); 8766 CASE_BTC_SLOT_STR(B3); 8767 CASE_BTC_SLOT_STR(B4); 8768 CASE_BTC_SLOT_STR(LK); 8769 CASE_BTC_SLOT_STR(BLK); 8770 CASE_BTC_SLOT_STR(E2G); 8771 CASE_BTC_SLOT_STR(E5G); 8772 CASE_BTC_SLOT_STR(EBT); 8773 CASE_BTC_SLOT_STR(ENULL); 8774 CASE_BTC_SLOT_STR(WLK); 8775 CASE_BTC_SLOT_STR(W1FDD); 8776 CASE_BTC_SLOT_STR(B1FDD); 8777 default: 8778 return "unknown"; 8779 } 8780 } 8781 8782 static const char *id_to_evt(u32 id) 8783 { 8784 switch (id) { 8785 CASE_BTC_EVT_STR(TDMA_ENTRY); 8786 CASE_BTC_EVT_STR(WL_TMR); 8787 CASE_BTC_EVT_STR(B1_TMR); 8788 CASE_BTC_EVT_STR(B2_TMR); 8789 CASE_BTC_EVT_STR(B3_TMR); 8790 CASE_BTC_EVT_STR(B4_TMR); 8791 CASE_BTC_EVT_STR(W2B_TMR); 8792 CASE_BTC_EVT_STR(B2W_TMR); 8793 CASE_BTC_EVT_STR(BCN_EARLY); 8794 CASE_BTC_EVT_STR(A2DP_EMPTY); 8795 CASE_BTC_EVT_STR(LK_END); 8796 CASE_BTC_EVT_STR(RX_ISR); 8797 CASE_BTC_EVT_STR(RX_FC0); 8798 CASE_BTC_EVT_STR(RX_FC1); 8799 CASE_BTC_EVT_STR(BT_RELINK); 8800 CASE_BTC_EVT_STR(BT_RETRY); 8801 CASE_BTC_EVT_STR(E2G); 8802 CASE_BTC_EVT_STR(E5G); 8803 CASE_BTC_EVT_STR(EBT); 8804 CASE_BTC_EVT_STR(ENULL); 8805 CASE_BTC_EVT_STR(DRV_WLK); 8806 CASE_BTC_EVT_STR(BCN_OK); 8807 CASE_BTC_EVT_STR(BT_CHANGE); 8808 CASE_BTC_EVT_STR(EBT_EXTEND); 8809 CASE_BTC_EVT_STR(E2G_NULL1); 8810 CASE_BTC_EVT_STR(B1FDD_TMR); 8811 default: 8812 return "unknown"; 8813 } 8814 } 8815 8816 static const char *id_to_mode(u8 id) 8817 { 8818 switch (id) { 8819 CASE_BTC_INIT(NORMAL); 8820 CASE_BTC_INIT(WL); 8821 CASE_BTC_INIT(BT); 8822 CASE_BTC_INIT(WLOFF); 8823 default: 8824 return "unknown"; 8825 } 8826 } 8827 8828 static const char *id_to_ant(u32 id) 8829 { 8830 switch (id) { 8831 CASE_BTC_ANTPATH_STR(WPOWERON); 8832 CASE_BTC_ANTPATH_STR(WINIT); 8833 CASE_BTC_ANTPATH_STR(WONLY); 8834 CASE_BTC_ANTPATH_STR(WOFF); 8835 CASE_BTC_ANTPATH_STR(W2G); 8836 CASE_BTC_ANTPATH_STR(W5G); 8837 CASE_BTC_ANTPATH_STR(W25G); 8838 CASE_BTC_ANTPATH_STR(FREERUN); 8839 CASE_BTC_ANTPATH_STR(WRFK); 8840 CASE_BTC_ANTPATH_STR(BRFK); 8841 CASE_BTC_ANTPATH_STR(MAX); 8842 default: 8843 return "unknown"; 8844 } 8845 } 8846 8847 static 8848 void seq_print_segment(struct seq_file *m, const char *prefix, u16 *data, 8849 u8 len, u8 seg_len, u8 start_idx, u8 ring_len) 8850 { 8851 u8 i; 8852 u8 cur_index; 8853 8854 for (i = 0; i < len ; i++) { 8855 if ((i % seg_len) == 0) 8856 seq_printf(m, " %-15s : ", prefix); 8857 cur_index = (start_idx + i) % ring_len; 8858 if (i % 3 == 0) 8859 seq_printf(m, "-> %-20s", 8860 steps_to_str(*(data + cur_index))); 8861 else if (i % 3 == 1) 8862 seq_printf(m, "-> %-15s", 8863 steps_to_str(*(data + cur_index))); 8864 else 8865 seq_printf(m, "-> %-13s", 8866 steps_to_str(*(data + cur_index))); 8867 if (i == (len - 1) || (i % seg_len) == (seg_len - 1)) 8868 seq_puts(m, "\n"); 8869 } 8870 } 8871 8872 static void _show_dm_step(struct rtw89_dev *rtwdev, struct seq_file *m) 8873 { 8874 struct rtw89_btc *btc = &rtwdev->btc; 8875 struct rtw89_btc_dm *dm = &btc->dm; 8876 u8 start_idx; 8877 u8 len; 8878 8879 len = dm->dm_step.step_ov ? RTW89_BTC_DM_MAXSTEP : dm->dm_step.step_pos; 8880 start_idx = dm->dm_step.step_ov ? dm->dm_step.step_pos : 0; 8881 8882 seq_print_segment(m, "[dm_steps]", dm->dm_step.step, len, 6, start_idx, 8883 ARRAY_SIZE(dm->dm_step.step)); 8884 } 8885 8886 static void _show_dm_info(struct rtw89_dev *rtwdev, struct seq_file *m) 8887 { 8888 struct rtw89_btc *btc = &rtwdev->btc; 8889 const struct rtw89_btc_ver *ver = btc->ver; 8890 struct rtw89_btc_dm *dm = &btc->dm; 8891 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 8892 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 8893 u8 igno_bt; 8894 8895 if (!(dm->coex_info_map & BTC_COEX_INFO_DM)) 8896 return; 8897 8898 seq_printf(m, "========== [Mechanism Status %s] ==========\n", 8899 (btc->manual_ctrl ? "(Manual)" : "(Auto)")); 8900 8901 seq_printf(m, 8902 " %-15s : type:%s, reason:%s(), action:%s(), ant_path:%s, init_mode:%s, run_cnt:%d\n", 8903 "[status]", 8904 btc->ant_type == BTC_ANT_SHARED ? "shared" : "dedicated", 8905 steps_to_str(dm->run_reason), 8906 steps_to_str(dm->run_action | BTC_ACT_EXT_BIT), 8907 id_to_ant(FIELD_GET(GENMASK(7, 0), dm->set_ant_path)), 8908 id_to_mode(wl->coex_mode), 8909 dm->cnt_dm[BTC_DCNT_RUN]); 8910 8911 _show_dm_step(rtwdev, m); 8912 8913 if (ver->fcxctrl == 7) 8914 igno_bt = btc->ctrl.ctrl_v7.igno_bt; 8915 else 8916 igno_bt = btc->ctrl.ctrl.igno_bt; 8917 8918 seq_printf(m, " %-15s : wl_only:%d, bt_only:%d, igno_bt:%d, free_run:%d, wl_ps_ctrl:%d, wl_mimo_ps:%d, ", 8919 "[dm_flag]", dm->wl_only, dm->bt_only, igno_bt, 8920 dm->freerun, btc->lps, dm->wl_mimo_ps); 8921 8922 seq_printf(m, "leak_ap:%d, fw_offload:%s%s\n", dm->leak_ap, 8923 (BTC_CX_FW_OFFLOAD ? "Y" : "N"), 8924 (dm->wl_fw_cx_offload == BTC_CX_FW_OFFLOAD ? 8925 "" : "(Mismatch!!)")); 8926 8927 if (dm->rf_trx_para.wl_tx_power == 0xff) 8928 seq_printf(m, 8929 " %-15s : wl_rssi_lvl:%d, para_lvl:%d, wl_tx_pwr:orig, ", 8930 "[trx_ctrl]", wl->rssi_level, dm->trx_para_level); 8931 8932 else 8933 seq_printf(m, 8934 " %-15s : wl_rssi_lvl:%d, para_lvl:%d, wl_tx_pwr:%d, ", 8935 "[trx_ctrl]", wl->rssi_level, dm->trx_para_level, 8936 dm->rf_trx_para.wl_tx_power); 8937 8938 seq_printf(m, 8939 "wl_rx_lvl:%d, bt_tx_pwr_dec:%d, bt_rx_lna:%d(%s-tbl), wl_btg_rx:%d\n", 8940 dm->rf_trx_para.wl_rx_gain, dm->rf_trx_para.bt_tx_power, 8941 dm->rf_trx_para.bt_rx_gain, 8942 (bt->hi_lna_rx ? "Hi" : "Ori"), dm->wl_btg_rx); 8943 8944 seq_printf(m, 8945 " %-15s : wl_tx_limit[en:%d/max_t:%dus/max_retry:%d], bt_slot_reg:%d-TU, bt_scan_rx_low_pri:%d\n", 8946 "[dm_ctrl]", dm->wl_tx_limit.enable, dm->wl_tx_limit.tx_time, 8947 dm->wl_tx_limit.tx_retry, btc->bt_req_len, bt->scan_rx_low_pri); 8948 } 8949 8950 static void _show_error(struct rtw89_dev *rtwdev, struct seq_file *m) 8951 { 8952 struct rtw89_btc *btc = &rtwdev->btc; 8953 const struct rtw89_btc_ver *ver = btc->ver; 8954 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 8955 union rtw89_btc_fbtc_cysta_info *pcysta; 8956 u32 except_cnt, exception_map; 8957 8958 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo; 8959 if (ver->fcxcysta == 2) { 8960 pcysta->v2 = pfwinfo->rpt_fbtc_cysta.finfo.v2; 8961 except_cnt = le32_to_cpu(pcysta->v2.except_cnt); 8962 exception_map = le32_to_cpu(pcysta->v2.exception); 8963 } else if (ver->fcxcysta == 3) { 8964 pcysta->v3 = pfwinfo->rpt_fbtc_cysta.finfo.v3; 8965 except_cnt = le32_to_cpu(pcysta->v3.except_cnt); 8966 exception_map = le32_to_cpu(pcysta->v3.except_map); 8967 } else if (ver->fcxcysta == 4) { 8968 pcysta->v4 = pfwinfo->rpt_fbtc_cysta.finfo.v4; 8969 except_cnt = pcysta->v4.except_cnt; 8970 exception_map = le32_to_cpu(pcysta->v4.except_map); 8971 } else if (ver->fcxcysta == 5) { 8972 pcysta->v5 = pfwinfo->rpt_fbtc_cysta.finfo.v5; 8973 except_cnt = pcysta->v5.except_cnt; 8974 exception_map = le32_to_cpu(pcysta->v5.except_map); 8975 } else if (ver->fcxcysta == 7) { 8976 pcysta->v7 = pfwinfo->rpt_fbtc_cysta.finfo.v7; 8977 except_cnt = pcysta->v7.except_cnt; 8978 exception_map = le32_to_cpu(pcysta->v7.except_map); 8979 } else { 8980 return; 8981 } 8982 8983 if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW] == 0 && except_cnt == 0 && 8984 !pfwinfo->len_mismch && !pfwinfo->fver_mismch) 8985 return; 8986 8987 seq_printf(m, " %-15s : ", "[error]"); 8988 8989 if (pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]) { 8990 seq_printf(m, 8991 "overflow-cnt: %d, ", 8992 pfwinfo->event[BTF_EVNT_BUF_OVERFLOW]); 8993 } 8994 8995 if (pfwinfo->len_mismch) { 8996 seq_printf(m, 8997 "len-mismatch: 0x%x, ", 8998 pfwinfo->len_mismch); 8999 } 9000 9001 if (pfwinfo->fver_mismch) { 9002 seq_printf(m, 9003 "fver-mismatch: 0x%x, ", 9004 pfwinfo->fver_mismch); 9005 } 9006 9007 /* cycle statistics exceptions */ 9008 if (exception_map || except_cnt) { 9009 seq_printf(m, 9010 "exception-type: 0x%x, exception-cnt = %d", 9011 exception_map, except_cnt); 9012 } 9013 seq_puts(m, "\n"); 9014 } 9015 9016 static void _show_fbtc_tdma(struct rtw89_dev *rtwdev, struct seq_file *m) 9017 { 9018 struct rtw89_btc *btc = &rtwdev->btc; 9019 const struct rtw89_btc_ver *ver = btc->ver; 9020 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 9021 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 9022 struct rtw89_btc_fbtc_tdma *t = NULL; 9023 9024 pcinfo = &pfwinfo->rpt_fbtc_tdma.cinfo; 9025 if (!pcinfo->valid) 9026 return; 9027 9028 if (ver->fcxtdma == 1) 9029 t = &pfwinfo->rpt_fbtc_tdma.finfo.v1; 9030 else 9031 t = &pfwinfo->rpt_fbtc_tdma.finfo.v3.tdma; 9032 9033 seq_printf(m, 9034 " %-15s : ", "[tdma_policy]"); 9035 seq_printf(m, 9036 "type:%d, rx_flow_ctrl:%d, tx_pause:%d, ", 9037 (u32)t->type, 9038 t->rxflctrl, t->txpause); 9039 9040 seq_printf(m, 9041 "wl_toggle_n:%d, leak_n:%d, ext_ctrl:%d, ", 9042 t->wtgle_n, t->leak_n, t->ext_ctrl); 9043 9044 seq_printf(m, 9045 "policy_type:%d", 9046 (u32)btc->policy_type); 9047 9048 seq_puts(m, "\n"); 9049 } 9050 9051 static void _show_fbtc_slots(struct rtw89_dev *rtwdev, struct seq_file *m) 9052 { 9053 struct rtw89_btc *btc = &rtwdev->btc; 9054 struct rtw89_btc_dm *dm = &btc->dm; 9055 u16 dur, cxtype; 9056 u32 tbl; 9057 u8 i = 0; 9058 9059 for (i = 0; i < CXST_MAX; i++) { 9060 if (btc->ver->fcxslots == 1) { 9061 dur = le16_to_cpu(dm->slot_now.v1[i].dur); 9062 tbl = le32_to_cpu(dm->slot_now.v1[i].cxtbl); 9063 cxtype = le16_to_cpu(dm->slot_now.v1[i].cxtype); 9064 } else if (btc->ver->fcxslots == 7) { 9065 dur = le16_to_cpu(dm->slot_now.v7[i].dur); 9066 tbl = le32_to_cpu(dm->slot_now.v7[i].cxtbl); 9067 cxtype = le16_to_cpu(dm->slot_now.v7[i].cxtype); 9068 } else { 9069 return; 9070 } 9071 9072 if (i % 5 == 0) 9073 seq_printf(m, 9074 " %-15s : %5s[%03d/0x%x/%d]", 9075 "[slot_list]", 9076 id_to_slot((u32)i), 9077 dur, tbl, cxtype); 9078 else 9079 seq_printf(m, 9080 ", %5s[%03d/0x%x/%d]", 9081 id_to_slot((u32)i), 9082 dur, tbl, cxtype); 9083 9084 if (i % 5 == 4) 9085 seq_puts(m, "\n"); 9086 } 9087 seq_puts(m, "\n"); 9088 } 9089 9090 static void _show_fbtc_cysta_v2(struct rtw89_dev *rtwdev, struct seq_file *m) 9091 { 9092 struct rtw89_btc *btc = &rtwdev->btc; 9093 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 9094 struct rtw89_btc_dm *dm = &btc->dm; 9095 struct rtw89_btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; 9096 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 9097 struct rtw89_btc_fbtc_cysta_v2 *pcysta_le32 = NULL; 9098 union rtw89_btc_fbtc_rxflct r; 9099 u8 i, cnt = 0, slot_pair; 9100 u16 cycle, c_begin, c_end, store_index; 9101 9102 pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; 9103 if (!pcinfo->valid) 9104 return; 9105 9106 pcysta_le32 = &pfwinfo->rpt_fbtc_cysta.finfo.v2; 9107 seq_printf(m, 9108 " %-15s : cycle:%d, bcn[all:%d/all_ok:%d/bt:%d/bt_ok:%d]", 9109 "[cycle_cnt]", 9110 le16_to_cpu(pcysta_le32->cycles), 9111 le32_to_cpu(pcysta_le32->bcn_cnt[CXBCN_ALL]), 9112 le32_to_cpu(pcysta_le32->bcn_cnt[CXBCN_ALL_OK]), 9113 le32_to_cpu(pcysta_le32->bcn_cnt[CXBCN_BT_SLOT]), 9114 le32_to_cpu(pcysta_le32->bcn_cnt[CXBCN_BT_OK])); 9115 9116 for (i = 0; i < CXST_MAX; i++) { 9117 if (!le32_to_cpu(pcysta_le32->slot_cnt[i])) 9118 continue; 9119 seq_printf(m, ", %s:%d", id_to_slot((u32)i), 9120 le32_to_cpu(pcysta_le32->slot_cnt[i])); 9121 } 9122 9123 if (dm->tdma_now.rxflctrl) { 9124 seq_printf(m, ", leak_rx:%d", 9125 le32_to_cpu(pcysta_le32->leakrx_cnt)); 9126 } 9127 9128 if (le32_to_cpu(pcysta_le32->collision_cnt)) { 9129 seq_printf(m, ", collision:%d", 9130 le32_to_cpu(pcysta_le32->collision_cnt)); 9131 } 9132 9133 if (le32_to_cpu(pcysta_le32->skip_cnt)) { 9134 seq_printf(m, ", skip:%d", 9135 le32_to_cpu(pcysta_le32->skip_cnt)); 9136 } 9137 seq_puts(m, "\n"); 9138 9139 seq_printf(m, " %-15s : avg_t[wl:%d/bt:%d/lk:%d.%03d]", 9140 "[cycle_time]", 9141 le16_to_cpu(pcysta_le32->tavg_cycle[CXT_WL]), 9142 le16_to_cpu(pcysta_le32->tavg_cycle[CXT_BT]), 9143 le16_to_cpu(pcysta_le32->tavg_lk) / 1000, 9144 le16_to_cpu(pcysta_le32->tavg_lk) % 1000); 9145 seq_printf(m, ", max_t[wl:%d/bt:%d/lk:%d.%03d]", 9146 le16_to_cpu(pcysta_le32->tmax_cycle[CXT_WL]), 9147 le16_to_cpu(pcysta_le32->tmax_cycle[CXT_BT]), 9148 le16_to_cpu(pcysta_le32->tmax_lk) / 1000, 9149 le16_to_cpu(pcysta_le32->tmax_lk) % 1000); 9150 seq_printf(m, ", maxdiff_t[wl:%d/bt:%d]\n", 9151 le16_to_cpu(pcysta_le32->tmaxdiff_cycle[CXT_WL]), 9152 le16_to_cpu(pcysta_le32->tmaxdiff_cycle[CXT_BT])); 9153 9154 if (le16_to_cpu(pcysta_le32->cycles) <= 1) 9155 return; 9156 9157 /* 1 cycle record 1 wl-slot and 1 bt-slot */ 9158 slot_pair = BTC_CYCLE_SLOT_MAX / 2; 9159 9160 if (le16_to_cpu(pcysta_le32->cycles) <= slot_pair) 9161 c_begin = 1; 9162 else 9163 c_begin = le16_to_cpu(pcysta_le32->cycles) - slot_pair + 1; 9164 9165 c_end = le16_to_cpu(pcysta_le32->cycles); 9166 9167 for (cycle = c_begin; cycle <= c_end; cycle++) { 9168 cnt++; 9169 store_index = ((cycle - 1) % slot_pair) * 2; 9170 9171 if (cnt % (BTC_CYCLE_SLOT_MAX / 4) == 1) 9172 seq_printf(m, 9173 " %-15s : ->b%02d->w%02d", "[cycle_step]", 9174 le16_to_cpu(pcysta_le32->tslot_cycle[store_index]), 9175 le16_to_cpu(pcysta_le32->tslot_cycle[store_index + 1])); 9176 else 9177 seq_printf(m, 9178 "->b%02d->w%02d", 9179 le16_to_cpu(pcysta_le32->tslot_cycle[store_index]), 9180 le16_to_cpu(pcysta_le32->tslot_cycle[store_index + 1])); 9181 if (cnt % (BTC_CYCLE_SLOT_MAX / 4) == 0 || cnt == c_end) 9182 seq_puts(m, "\n"); 9183 } 9184 9185 if (a2dp->exist) { 9186 seq_printf(m, 9187 " %-15s : a2dp_ept:%d, a2dp_late:%d", 9188 "[a2dp_t_sta]", 9189 le16_to_cpu(pcysta_le32->a2dpept), 9190 le16_to_cpu(pcysta_le32->a2dpeptto)); 9191 9192 seq_printf(m, 9193 ", avg_t:%d, max_t:%d", 9194 le16_to_cpu(pcysta_le32->tavg_a2dpept), 9195 le16_to_cpu(pcysta_le32->tmax_a2dpept)); 9196 r.val = dm->tdma_now.rxflctrl; 9197 9198 if (r.type && r.tgln_n) { 9199 seq_printf(m, 9200 ", cycle[PSTDMA:%d/TDMA:%d], ", 9201 le16_to_cpu(pcysta_le32->cycles_a2dp[CXT_FLCTRL_ON]), 9202 le16_to_cpu(pcysta_le32->cycles_a2dp[CXT_FLCTRL_OFF])); 9203 9204 seq_printf(m, 9205 "avg_t[PSTDMA:%d/TDMA:%d], ", 9206 le16_to_cpu(pcysta_le32->tavg_a2dp[CXT_FLCTRL_ON]), 9207 le16_to_cpu(pcysta_le32->tavg_a2dp[CXT_FLCTRL_OFF])); 9208 9209 seq_printf(m, 9210 "max_t[PSTDMA:%d/TDMA:%d]", 9211 le16_to_cpu(pcysta_le32->tmax_a2dp[CXT_FLCTRL_ON]), 9212 le16_to_cpu(pcysta_le32->tmax_a2dp[CXT_FLCTRL_OFF])); 9213 } 9214 seq_puts(m, "\n"); 9215 } 9216 } 9217 9218 static void _show_fbtc_cysta_v3(struct rtw89_dev *rtwdev, struct seq_file *m) 9219 { 9220 struct rtw89_btc *btc = &rtwdev->btc; 9221 struct rtw89_btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; 9222 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 9223 struct rtw89_btc_dm *dm = &btc->dm; 9224 struct rtw89_btc_fbtc_a2dp_trx_stat *a2dp_trx; 9225 struct rtw89_btc_fbtc_cysta_v3 *pcysta; 9226 struct rtw89_btc_rpt_cmn_info *pcinfo; 9227 u8 i, cnt = 0, slot_pair, divide_cnt; 9228 u16 cycle, c_begin, c_end, store_index; 9229 9230 pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; 9231 if (!pcinfo->valid) 9232 return; 9233 9234 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo.v3; 9235 seq_printf(m, 9236 " %-15s : cycle:%d, bcn[all:%d/all_ok:%d/bt:%d/bt_ok:%d]", 9237 "[cycle_cnt]", 9238 le16_to_cpu(pcysta->cycles), 9239 le32_to_cpu(pcysta->bcn_cnt[CXBCN_ALL]), 9240 le32_to_cpu(pcysta->bcn_cnt[CXBCN_ALL_OK]), 9241 le32_to_cpu(pcysta->bcn_cnt[CXBCN_BT_SLOT]), 9242 le32_to_cpu(pcysta->bcn_cnt[CXBCN_BT_OK])); 9243 9244 for (i = 0; i < CXST_MAX; i++) { 9245 if (!le32_to_cpu(pcysta->slot_cnt[i])) 9246 continue; 9247 9248 seq_printf(m, ", %s:%d", id_to_slot(i), 9249 le32_to_cpu(pcysta->slot_cnt[i])); 9250 } 9251 9252 if (dm->tdma_now.rxflctrl) 9253 seq_printf(m, ", leak_rx:%d", le32_to_cpu(pcysta->leak_slot.cnt_rximr)); 9254 9255 if (le32_to_cpu(pcysta->collision_cnt)) 9256 seq_printf(m, ", collision:%d", le32_to_cpu(pcysta->collision_cnt)); 9257 9258 if (le32_to_cpu(pcysta->skip_cnt)) 9259 seq_printf(m, ", skip:%d", le32_to_cpu(pcysta->skip_cnt)); 9260 9261 seq_puts(m, "\n"); 9262 9263 seq_printf(m, " %-15s : avg_t[wl:%d/bt:%d/lk:%d.%03d]", 9264 "[cycle_time]", 9265 le16_to_cpu(pcysta->cycle_time.tavg[CXT_WL]), 9266 le16_to_cpu(pcysta->cycle_time.tavg[CXT_BT]), 9267 le16_to_cpu(pcysta->leak_slot.tavg) / 1000, 9268 le16_to_cpu(pcysta->leak_slot.tavg) % 1000); 9269 seq_printf(m, 9270 ", max_t[wl:%d/bt:%d/lk:%d.%03d]", 9271 le16_to_cpu(pcysta->cycle_time.tmax[CXT_WL]), 9272 le16_to_cpu(pcysta->cycle_time.tmax[CXT_BT]), 9273 le16_to_cpu(pcysta->leak_slot.tmax) / 1000, 9274 le16_to_cpu(pcysta->leak_slot.tmax) % 1000); 9275 seq_printf(m, 9276 ", maxdiff_t[wl:%d/bt:%d]\n", 9277 le16_to_cpu(pcysta->cycle_time.tmaxdiff[CXT_WL]), 9278 le16_to_cpu(pcysta->cycle_time.tmaxdiff[CXT_BT])); 9279 9280 cycle = le16_to_cpu(pcysta->cycles); 9281 if (cycle <= 1) 9282 return; 9283 9284 /* 1 cycle record 1 wl-slot and 1 bt-slot */ 9285 slot_pair = BTC_CYCLE_SLOT_MAX / 2; 9286 9287 if (cycle <= slot_pair) 9288 c_begin = 1; 9289 else 9290 c_begin = cycle - slot_pair + 1; 9291 9292 c_end = cycle; 9293 9294 if (a2dp->exist) 9295 divide_cnt = 3; 9296 else 9297 divide_cnt = BTC_CYCLE_SLOT_MAX / 4; 9298 9299 for (cycle = c_begin; cycle <= c_end; cycle++) { 9300 cnt++; 9301 store_index = ((cycle - 1) % slot_pair) * 2; 9302 9303 if (cnt % divide_cnt == 1) 9304 seq_printf(m, " %-15s : ", "[cycle_step]"); 9305 9306 seq_printf(m, "->b%02d", 9307 le16_to_cpu(pcysta->slot_step_time[store_index])); 9308 if (a2dp->exist) { 9309 a2dp_trx = &pcysta->a2dp_trx[store_index]; 9310 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)", 9311 a2dp_trx->empty_cnt, 9312 a2dp_trx->retry_cnt, 9313 a2dp_trx->tx_rate ? 3 : 2, 9314 a2dp_trx->tx_cnt, 9315 a2dp_trx->ack_cnt, 9316 a2dp_trx->nack_cnt); 9317 } 9318 seq_printf(m, "->w%02d", 9319 le16_to_cpu(pcysta->slot_step_time[store_index + 1])); 9320 if (a2dp->exist) { 9321 a2dp_trx = &pcysta->a2dp_trx[store_index + 1]; 9322 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)", 9323 a2dp_trx->empty_cnt, 9324 a2dp_trx->retry_cnt, 9325 a2dp_trx->tx_rate ? 3 : 2, 9326 a2dp_trx->tx_cnt, 9327 a2dp_trx->ack_cnt, 9328 a2dp_trx->nack_cnt); 9329 } 9330 if (cnt % divide_cnt == 0 || cnt == c_end) 9331 seq_puts(m, "\n"); 9332 } 9333 9334 if (a2dp->exist) { 9335 seq_printf(m, " %-15s : a2dp_ept:%d, a2dp_late:%d", 9336 "[a2dp_t_sta]", 9337 le16_to_cpu(pcysta->a2dp_ept.cnt), 9338 le16_to_cpu(pcysta->a2dp_ept.cnt_timeout)); 9339 9340 seq_printf(m, ", avg_t:%d, max_t:%d", 9341 le16_to_cpu(pcysta->a2dp_ept.tavg), 9342 le16_to_cpu(pcysta->a2dp_ept.tmax)); 9343 9344 seq_puts(m, "\n"); 9345 } 9346 } 9347 9348 static void _show_fbtc_cysta_v4(struct rtw89_dev *rtwdev, struct seq_file *m) 9349 { 9350 struct rtw89_btc *btc = &rtwdev->btc; 9351 struct rtw89_btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; 9352 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 9353 struct rtw89_btc_dm *dm = &btc->dm; 9354 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 *a2dp_trx; 9355 struct rtw89_btc_fbtc_cysta_v4 *pcysta; 9356 struct rtw89_btc_rpt_cmn_info *pcinfo; 9357 u8 i, cnt = 0, slot_pair, divide_cnt; 9358 u16 cycle, c_begin, c_end, store_index; 9359 9360 pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; 9361 if (!pcinfo->valid) 9362 return; 9363 9364 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo.v4; 9365 seq_printf(m, 9366 " %-15s : cycle:%d, bcn[all:%d/all_ok:%d/bt:%d/bt_ok:%d]", 9367 "[cycle_cnt]", 9368 le16_to_cpu(pcysta->cycles), 9369 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL]), 9370 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL_OK]), 9371 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_SLOT]), 9372 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_OK])); 9373 9374 for (i = 0; i < CXST_MAX; i++) { 9375 if (!le16_to_cpu(pcysta->slot_cnt[i])) 9376 continue; 9377 9378 seq_printf(m, ", %s:%d", id_to_slot(i), 9379 le16_to_cpu(pcysta->slot_cnt[i])); 9380 } 9381 9382 if (dm->tdma_now.rxflctrl) 9383 seq_printf(m, ", leak_rx:%d", 9384 le32_to_cpu(pcysta->leak_slot.cnt_rximr)); 9385 9386 if (pcysta->collision_cnt) 9387 seq_printf(m, ", collision:%d", pcysta->collision_cnt); 9388 9389 if (le16_to_cpu(pcysta->skip_cnt)) 9390 seq_printf(m, ", skip:%d", 9391 le16_to_cpu(pcysta->skip_cnt)); 9392 9393 seq_puts(m, "\n"); 9394 9395 seq_printf(m, " %-15s : avg_t[wl:%d/bt:%d/lk:%d.%03d]", 9396 "[cycle_time]", 9397 le16_to_cpu(pcysta->cycle_time.tavg[CXT_WL]), 9398 le16_to_cpu(pcysta->cycle_time.tavg[CXT_BT]), 9399 le16_to_cpu(pcysta->leak_slot.tavg) / 1000, 9400 le16_to_cpu(pcysta->leak_slot.tavg) % 1000); 9401 seq_printf(m, 9402 ", max_t[wl:%d/bt:%d/lk:%d.%03d]", 9403 le16_to_cpu(pcysta->cycle_time.tmax[CXT_WL]), 9404 le16_to_cpu(pcysta->cycle_time.tmax[CXT_BT]), 9405 le16_to_cpu(pcysta->leak_slot.tmax) / 1000, 9406 le16_to_cpu(pcysta->leak_slot.tmax) % 1000); 9407 seq_printf(m, 9408 ", maxdiff_t[wl:%d/bt:%d]\n", 9409 le16_to_cpu(pcysta->cycle_time.tmaxdiff[CXT_WL]), 9410 le16_to_cpu(pcysta->cycle_time.tmaxdiff[CXT_BT])); 9411 9412 cycle = le16_to_cpu(pcysta->cycles); 9413 if (cycle <= 1) 9414 return; 9415 9416 /* 1 cycle record 1 wl-slot and 1 bt-slot */ 9417 slot_pair = BTC_CYCLE_SLOT_MAX / 2; 9418 9419 if (cycle <= slot_pair) 9420 c_begin = 1; 9421 else 9422 c_begin = cycle - slot_pair + 1; 9423 9424 c_end = cycle; 9425 9426 if (a2dp->exist) 9427 divide_cnt = 3; 9428 else 9429 divide_cnt = BTC_CYCLE_SLOT_MAX / 4; 9430 9431 for (cycle = c_begin; cycle <= c_end; cycle++) { 9432 cnt++; 9433 store_index = ((cycle - 1) % slot_pair) * 2; 9434 9435 if (cnt % divide_cnt == 1) 9436 seq_printf(m, " %-15s : ", "[cycle_step]"); 9437 9438 seq_printf(m, "->b%02d", 9439 le16_to_cpu(pcysta->slot_step_time[store_index])); 9440 if (a2dp->exist) { 9441 a2dp_trx = &pcysta->a2dp_trx[store_index]; 9442 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)", 9443 a2dp_trx->empty_cnt, 9444 a2dp_trx->retry_cnt, 9445 a2dp_trx->tx_rate ? 3 : 2, 9446 a2dp_trx->tx_cnt, 9447 a2dp_trx->ack_cnt, 9448 a2dp_trx->nack_cnt); 9449 } 9450 seq_printf(m, "->w%02d", 9451 le16_to_cpu(pcysta->slot_step_time[store_index + 1])); 9452 if (a2dp->exist) { 9453 a2dp_trx = &pcysta->a2dp_trx[store_index + 1]; 9454 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)", 9455 a2dp_trx->empty_cnt, 9456 a2dp_trx->retry_cnt, 9457 a2dp_trx->tx_rate ? 3 : 2, 9458 a2dp_trx->tx_cnt, 9459 a2dp_trx->ack_cnt, 9460 a2dp_trx->nack_cnt); 9461 } 9462 if (cnt % divide_cnt == 0 || cnt == c_end) 9463 seq_puts(m, "\n"); 9464 } 9465 9466 if (a2dp->exist) { 9467 seq_printf(m, " %-15s : a2dp_ept:%d, a2dp_late:%d", 9468 "[a2dp_t_sta]", 9469 le16_to_cpu(pcysta->a2dp_ept.cnt), 9470 le16_to_cpu(pcysta->a2dp_ept.cnt_timeout)); 9471 9472 seq_printf(m, ", avg_t:%d, max_t:%d", 9473 le16_to_cpu(pcysta->a2dp_ept.tavg), 9474 le16_to_cpu(pcysta->a2dp_ept.tmax)); 9475 9476 seq_puts(m, "\n"); 9477 } 9478 } 9479 9480 static void _show_fbtc_cysta_v5(struct rtw89_dev *rtwdev, struct seq_file *m) 9481 { 9482 struct rtw89_btc *btc = &rtwdev->btc; 9483 struct rtw89_btc_bt_a2dp_desc *a2dp = &btc->cx.bt.link_info.a2dp_desc; 9484 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 9485 struct rtw89_btc_dm *dm = &btc->dm; 9486 struct rtw89_btc_fbtc_a2dp_trx_stat_v4 *a2dp_trx; 9487 struct rtw89_btc_fbtc_cysta_v5 *pcysta; 9488 struct rtw89_btc_rpt_cmn_info *pcinfo; 9489 u8 i, cnt = 0, slot_pair, divide_cnt; 9490 u16 cycle, c_begin, c_end, store_index; 9491 9492 pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; 9493 if (!pcinfo->valid) 9494 return; 9495 9496 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo.v5; 9497 seq_printf(m, 9498 " %-15s : cycle:%d, bcn[all:%d/all_ok:%d/bt:%d/bt_ok:%d]", 9499 "[cycle_cnt]", 9500 le16_to_cpu(pcysta->cycles), 9501 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL]), 9502 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL_OK]), 9503 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_SLOT]), 9504 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_OK])); 9505 9506 for (i = 0; i < CXST_MAX; i++) { 9507 if (!le16_to_cpu(pcysta->slot_cnt[i])) 9508 continue; 9509 9510 seq_printf(m, ", %s:%d", id_to_slot(i), 9511 le16_to_cpu(pcysta->slot_cnt[i])); 9512 } 9513 9514 if (dm->tdma_now.rxflctrl) 9515 seq_printf(m, ", leak_rx:%d", 9516 le32_to_cpu(pcysta->leak_slot.cnt_rximr)); 9517 9518 if (pcysta->collision_cnt) 9519 seq_printf(m, ", collision:%d", pcysta->collision_cnt); 9520 9521 if (le16_to_cpu(pcysta->skip_cnt)) 9522 seq_printf(m, ", skip:%d", 9523 le16_to_cpu(pcysta->skip_cnt)); 9524 9525 seq_puts(m, "\n"); 9526 9527 seq_printf(m, " %-15s : avg_t[wl:%d/bt:%d/lk:%d.%03d]", 9528 "[cycle_time]", 9529 le16_to_cpu(pcysta->cycle_time.tavg[CXT_WL]), 9530 le16_to_cpu(pcysta->cycle_time.tavg[CXT_BT]), 9531 le16_to_cpu(pcysta->leak_slot.tavg) / 1000, 9532 le16_to_cpu(pcysta->leak_slot.tavg) % 1000); 9533 seq_printf(m, 9534 ", max_t[wl:%d/bt:%d/lk:%d.%03d]\n", 9535 le16_to_cpu(pcysta->cycle_time.tmax[CXT_WL]), 9536 le16_to_cpu(pcysta->cycle_time.tmax[CXT_BT]), 9537 le16_to_cpu(pcysta->leak_slot.tmax) / 1000, 9538 le16_to_cpu(pcysta->leak_slot.tmax) % 1000); 9539 9540 cycle = le16_to_cpu(pcysta->cycles); 9541 if (cycle <= 1) 9542 return; 9543 9544 /* 1 cycle record 1 wl-slot and 1 bt-slot */ 9545 slot_pair = BTC_CYCLE_SLOT_MAX / 2; 9546 9547 if (cycle <= slot_pair) 9548 c_begin = 1; 9549 else 9550 c_begin = cycle - slot_pair + 1; 9551 9552 c_end = cycle; 9553 9554 if (a2dp->exist) 9555 divide_cnt = 3; 9556 else 9557 divide_cnt = BTC_CYCLE_SLOT_MAX / 4; 9558 9559 if (c_begin > c_end) 9560 return; 9561 9562 for (cycle = c_begin; cycle <= c_end; cycle++) { 9563 cnt++; 9564 store_index = ((cycle - 1) % slot_pair) * 2; 9565 9566 if (cnt % divide_cnt == 1) 9567 seq_printf(m, " %-15s : ", "[cycle_step]"); 9568 9569 seq_printf(m, "->b%02d", 9570 le16_to_cpu(pcysta->slot_step_time[store_index])); 9571 if (a2dp->exist) { 9572 a2dp_trx = &pcysta->a2dp_trx[store_index]; 9573 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)", 9574 a2dp_trx->empty_cnt, 9575 a2dp_trx->retry_cnt, 9576 a2dp_trx->tx_rate ? 3 : 2, 9577 a2dp_trx->tx_cnt, 9578 a2dp_trx->ack_cnt, 9579 a2dp_trx->nack_cnt); 9580 } 9581 seq_printf(m, "->w%02d", 9582 le16_to_cpu(pcysta->slot_step_time[store_index + 1])); 9583 if (a2dp->exist) { 9584 a2dp_trx = &pcysta->a2dp_trx[store_index + 1]; 9585 seq_printf(m, "(%d/%d/%dM/%d/%d/%d)", 9586 a2dp_trx->empty_cnt, 9587 a2dp_trx->retry_cnt, 9588 a2dp_trx->tx_rate ? 3 : 2, 9589 a2dp_trx->tx_cnt, 9590 a2dp_trx->ack_cnt, 9591 a2dp_trx->nack_cnt); 9592 } 9593 if (cnt % divide_cnt == 0 || cnt == c_end) 9594 seq_puts(m, "\n"); 9595 } 9596 9597 if (a2dp->exist) { 9598 seq_printf(m, " %-15s : a2dp_ept:%d, a2dp_late:%d", 9599 "[a2dp_t_sta]", 9600 le16_to_cpu(pcysta->a2dp_ept.cnt), 9601 le16_to_cpu(pcysta->a2dp_ept.cnt_timeout)); 9602 9603 seq_printf(m, ", avg_t:%d, max_t:%d", 9604 le16_to_cpu(pcysta->a2dp_ept.tavg), 9605 le16_to_cpu(pcysta->a2dp_ept.tmax)); 9606 9607 seq_puts(m, "\n"); 9608 } 9609 } 9610 9611 static void _show_fbtc_cysta_v7(struct rtw89_dev *rtwdev, struct seq_file *m) 9612 { 9613 struct rtw89_btc_bt_info *bt = &rtwdev->btc.cx.bt; 9614 struct rtw89_btc_bt_a2dp_desc *a2dp = &bt->link_info.a2dp_desc; 9615 struct rtw89_btc_btf_fwinfo *pfwinfo = &rtwdev->btc.fwinfo; 9616 struct rtw89_btc_fbtc_cysta_v7 *pcysta = NULL; 9617 struct rtw89_btc_dm *dm = &rtwdev->btc.dm; 9618 struct rtw89_btc_rpt_cmn_info *pcinfo; 9619 u16 cycle, c_begin, c_end, s_id; 9620 u8 i, cnt = 0, divide_cnt; 9621 u8 slot_pair; 9622 9623 pcinfo = &pfwinfo->rpt_fbtc_cysta.cinfo; 9624 if (!pcinfo->valid) 9625 return; 9626 9627 pcysta = &pfwinfo->rpt_fbtc_cysta.finfo.v7; 9628 seq_printf(m, "\n\r %-15s : cycle:%d", "[slot_stat]", 9629 le16_to_cpu(pcysta->cycles)); 9630 9631 for (i = 0; i < CXST_MAX; i++) { 9632 if (!le16_to_cpu(pcysta->slot_cnt[i])) 9633 continue; 9634 seq_printf(m, ", %s:%d", 9635 id_to_slot(i), le16_to_cpu(pcysta->slot_cnt[i])); 9636 } 9637 9638 if (dm->tdma_now.rxflctrl) 9639 seq_printf(m, ", leak_rx:%d", 9640 le32_to_cpu(pcysta->leak_slot.cnt_rximr)); 9641 9642 if (pcysta->collision_cnt) 9643 seq_printf(m, ", collision:%d", pcysta->collision_cnt); 9644 9645 if (pcysta->skip_cnt) 9646 seq_printf(m, ", skip:%d", le16_to_cpu(pcysta->skip_cnt)); 9647 9648 seq_printf(m, "\n\r %-15s : avg_t[wl:%d/bt:%d/lk:%d.%03d]", 9649 "[cycle_stat]", 9650 le16_to_cpu(pcysta->cycle_time.tavg[CXT_WL]), 9651 le16_to_cpu(pcysta->cycle_time.tavg[CXT_BT]), 9652 le16_to_cpu(pcysta->leak_slot.tavg) / 1000, 9653 le16_to_cpu(pcysta->leak_slot.tavg) % 1000); 9654 seq_printf(m, ", max_t[wl:%d/bt:%d(>%dms:%d)/lk:%d.%03d]", 9655 le16_to_cpu(pcysta->cycle_time.tmax[CXT_WL]), 9656 le16_to_cpu(pcysta->cycle_time.tmax[CXT_BT]), 9657 dm->bt_slot_flood, dm->cnt_dm[BTC_DCNT_BT_SLOT_FLOOD], 9658 le16_to_cpu(pcysta->leak_slot.tamx) / 1000, 9659 le16_to_cpu(pcysta->leak_slot.tamx) % 1000); 9660 seq_printf(m, ", bcn[all:%d/ok:%d/in_bt:%d/in_bt_ok:%d]", 9661 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL]), 9662 le16_to_cpu(pcysta->bcn_cnt[CXBCN_ALL_OK]), 9663 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_SLOT]), 9664 le16_to_cpu(pcysta->bcn_cnt[CXBCN_BT_OK])); 9665 9666 if (a2dp->exist) { 9667 seq_printf(m, 9668 "\n\r %-15s : a2dp_ept:%d, a2dp_late:%d(streak 2S:%d/max:%d)", 9669 "[a2dp_stat]", 9670 le16_to_cpu(pcysta->a2dp_ept.cnt), 9671 le16_to_cpu(pcysta->a2dp_ept.cnt_timeout), 9672 a2dp->no_empty_streak_2s, a2dp->no_empty_streak_max); 9673 9674 seq_printf(m, ", avg_t:%d, max_t:%d", 9675 le16_to_cpu(pcysta->a2dp_ept.tavg), 9676 le16_to_cpu(pcysta->a2dp_ept.tmax)); 9677 } 9678 9679 if (le16_to_cpu(pcysta->cycles) <= 1) 9680 return; 9681 9682 /* 1 cycle = 1 wl-slot + 1 bt-slot */ 9683 slot_pair = BTC_CYCLE_SLOT_MAX / 2; 9684 9685 if (le16_to_cpu(pcysta->cycles) <= slot_pair) 9686 c_begin = 1; 9687 else 9688 c_begin = le16_to_cpu(pcysta->cycles) - slot_pair + 1; 9689 9690 c_end = le16_to_cpu(pcysta->cycles); 9691 9692 if (a2dp->exist) 9693 divide_cnt = 2; 9694 else 9695 divide_cnt = 6; 9696 9697 if (c_begin > c_end) 9698 return; 9699 9700 for (cycle = c_begin; cycle <= c_end; cycle++) { 9701 cnt++; 9702 s_id = ((cycle - 1) % slot_pair) * 2; 9703 9704 if (cnt % divide_cnt == 1) { 9705 if (a2dp->exist) 9706 seq_printf(m, "\n\r %-15s : ", "[slotT_wermtan]"); 9707 else 9708 seq_printf(m, "\n\r %-15s : ", "[slotT_rxerr]"); 9709 } 9710 9711 seq_printf(m, "->b%d", le16_to_cpu(pcysta->slot_step_time[s_id])); 9712 9713 if (a2dp->exist) 9714 seq_printf(m, "(%d/%d/%d/%dM/%d/%d/%d)", 9715 pcysta->wl_rx_err_ratio[s_id], 9716 pcysta->a2dp_trx[s_id].empty_cnt, 9717 pcysta->a2dp_trx[s_id].retry_cnt, 9718 (pcysta->a2dp_trx[s_id].tx_rate ? 3 : 2), 9719 pcysta->a2dp_trx[s_id].tx_cnt, 9720 pcysta->a2dp_trx[s_id].ack_cnt, 9721 pcysta->a2dp_trx[s_id].nack_cnt); 9722 else 9723 seq_printf(m, "(%d)", pcysta->wl_rx_err_ratio[s_id]); 9724 9725 seq_printf(m, "->w%d", le16_to_cpu(pcysta->slot_step_time[s_id + 1])); 9726 9727 if (a2dp->exist) 9728 seq_printf(m, "(%d/%d/%d/%dM/%d/%d/%d)", 9729 pcysta->wl_rx_err_ratio[s_id + 1], 9730 pcysta->a2dp_trx[s_id + 1].empty_cnt, 9731 pcysta->a2dp_trx[s_id + 1].retry_cnt, 9732 (pcysta->a2dp_trx[s_id + 1].tx_rate ? 3 : 2), 9733 pcysta->a2dp_trx[s_id + 1].tx_cnt, 9734 pcysta->a2dp_trx[s_id + 1].ack_cnt, 9735 pcysta->a2dp_trx[s_id + 1].nack_cnt); 9736 else 9737 seq_printf(m, "(%d)", pcysta->wl_rx_err_ratio[s_id + 1]); 9738 } 9739 } 9740 9741 static void _show_fbtc_nullsta(struct rtw89_dev *rtwdev, struct seq_file *m) 9742 { 9743 struct rtw89_btc *btc = &rtwdev->btc; 9744 const struct rtw89_btc_ver *ver = btc->ver; 9745 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 9746 struct rtw89_btc_rpt_cmn_info *pcinfo; 9747 union rtw89_btc_fbtc_cynullsta_info *ns; 9748 u8 i = 0; 9749 9750 if (!btc->dm.tdma_now.rxflctrl) 9751 return; 9752 9753 pcinfo = &pfwinfo->rpt_fbtc_nullsta.cinfo; 9754 if (!pcinfo->valid) 9755 return; 9756 9757 ns = &pfwinfo->rpt_fbtc_nullsta.finfo; 9758 if (ver->fcxnullsta == 1) { 9759 for (i = 0; i < 2; i++) { 9760 seq_printf(m, " %-15s : ", "[NULL-STA]"); 9761 seq_printf(m, "null-%d", i); 9762 seq_printf(m, "[ok:%d/", 9763 le32_to_cpu(ns->v1.result[i][1])); 9764 seq_printf(m, "fail:%d/", 9765 le32_to_cpu(ns->v1.result[i][0])); 9766 seq_printf(m, "on_time:%d/", 9767 le32_to_cpu(ns->v1.result[i][2])); 9768 seq_printf(m, "retry:%d/", 9769 le32_to_cpu(ns->v1.result[i][3])); 9770 seq_printf(m, "avg_t:%d.%03d/", 9771 le32_to_cpu(ns->v1.avg_t[i]) / 1000, 9772 le32_to_cpu(ns->v1.avg_t[i]) % 1000); 9773 seq_printf(m, "max_t:%d.%03d]\n", 9774 le32_to_cpu(ns->v1.max_t[i]) / 1000, 9775 le32_to_cpu(ns->v1.max_t[i]) % 1000); 9776 } 9777 } else if (ver->fcxnullsta == 7) { 9778 for (i = 0; i < 2; i++) { 9779 seq_printf(m, " %-15s : ", "[NULL-STA]"); 9780 seq_printf(m, "null-%d", i); 9781 seq_printf(m, "[Tx:%d/", 9782 le32_to_cpu(ns->v7.result[i][4])); 9783 seq_printf(m, "[ok:%d/", 9784 le32_to_cpu(ns->v7.result[i][1])); 9785 seq_printf(m, "fail:%d/", 9786 le32_to_cpu(ns->v7.result[i][0])); 9787 seq_printf(m, "on_time:%d/", 9788 le32_to_cpu(ns->v7.result[i][2])); 9789 seq_printf(m, "retry:%d/", 9790 le32_to_cpu(ns->v7.result[i][3])); 9791 seq_printf(m, "avg_t:%d.%03d/", 9792 le32_to_cpu(ns->v7.tavg[i]) / 1000, 9793 le32_to_cpu(ns->v7.tavg[i]) % 1000); 9794 seq_printf(m, "max_t:%d.%03d]\n", 9795 le32_to_cpu(ns->v7.tmax[i]) / 1000, 9796 le32_to_cpu(ns->v7.tmax[i]) % 1000); 9797 } 9798 } else { 9799 for (i = 0; i < 2; i++) { 9800 seq_printf(m, " %-15s : ", "[NULL-STA]"); 9801 seq_printf(m, "null-%d", i); 9802 seq_printf(m, "[Tx:%d/", 9803 le32_to_cpu(ns->v2.result[i][4])); 9804 seq_printf(m, "[ok:%d/", 9805 le32_to_cpu(ns->v2.result[i][1])); 9806 seq_printf(m, "fail:%d/", 9807 le32_to_cpu(ns->v2.result[i][0])); 9808 seq_printf(m, "on_time:%d/", 9809 le32_to_cpu(ns->v2.result[i][2])); 9810 seq_printf(m, "retry:%d/", 9811 le32_to_cpu(ns->v2.result[i][3])); 9812 seq_printf(m, "avg_t:%d.%03d/", 9813 le32_to_cpu(ns->v2.avg_t[i]) / 1000, 9814 le32_to_cpu(ns->v2.avg_t[i]) % 1000); 9815 seq_printf(m, "max_t:%d.%03d]\n", 9816 le32_to_cpu(ns->v2.max_t[i]) / 1000, 9817 le32_to_cpu(ns->v2.max_t[i]) % 1000); 9818 } 9819 } 9820 } 9821 9822 static void _show_fbtc_step_v2(struct rtw89_dev *rtwdev, struct seq_file *m) 9823 { 9824 struct rtw89_btc *btc = &rtwdev->btc; 9825 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 9826 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 9827 struct rtw89_btc_fbtc_steps_v2 *pstep = NULL; 9828 const struct rtw89_btc_ver *ver = btc->ver; 9829 u8 type, val, cnt = 0, state = 0; 9830 bool outloop = false; 9831 u16 i, diff_t, n_start = 0, n_stop = 0; 9832 u16 pos_old, pos_new, trace_step; 9833 9834 pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; 9835 if (!pcinfo->valid) 9836 return; 9837 9838 pstep = &pfwinfo->rpt_fbtc_step.finfo.v2; 9839 pos_old = le16_to_cpu(pstep->pos_old); 9840 pos_new = le16_to_cpu(pstep->pos_new); 9841 9842 if (pcinfo->req_fver != pstep->fver) 9843 return; 9844 9845 /* store step info by using ring instead of FIFO*/ 9846 do { 9847 switch (state) { 9848 case 0: 9849 if (ver->fcxctrl == 7 || ver->fcxctrl == 1) 9850 trace_step = 50; 9851 else 9852 trace_step = btc->ctrl.ctrl.trace_step; 9853 9854 n_start = pos_old; 9855 if (pos_new >= pos_old) 9856 n_stop = pos_new; 9857 else 9858 n_stop = trace_step - 1; 9859 9860 state = 1; 9861 break; 9862 case 1: 9863 for (i = n_start; i <= n_stop; i++) { 9864 type = pstep->step[i].type; 9865 val = pstep->step[i].val; 9866 diff_t = le16_to_cpu(pstep->step[i].difft); 9867 9868 if (type == CXSTEP_NONE || type >= CXSTEP_MAX) 9869 continue; 9870 9871 if (cnt % 10 == 0) 9872 seq_printf(m, " %-15s : ", "[steps]"); 9873 9874 seq_printf(m, "-> %s(%02d)(%02d)", 9875 (type == CXSTEP_SLOT ? "SLT" : 9876 "EVT"), (u32)val, diff_t); 9877 if (cnt % 10 == 9) 9878 seq_puts(m, "\n"); 9879 cnt++; 9880 } 9881 9882 state = 2; 9883 break; 9884 case 2: 9885 if (pos_new < pos_old && n_start != 0) { 9886 n_start = 0; 9887 n_stop = pos_new; 9888 state = 1; 9889 } else { 9890 outloop = true; 9891 } 9892 break; 9893 } 9894 } while (!outloop); 9895 } 9896 9897 static void _show_fbtc_step_v3(struct rtw89_dev *rtwdev, struct seq_file *m) 9898 { 9899 struct rtw89_btc *btc = &rtwdev->btc; 9900 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 9901 struct rtw89_btc_rpt_cmn_info *pcinfo; 9902 struct rtw89_btc_fbtc_steps_v3 *pstep; 9903 u32 i, n_begin, n_end, array_idx, cnt = 0; 9904 u8 type, val; 9905 u16 diff_t; 9906 9907 if ((pfwinfo->rpt_en_map & 9908 rtw89_btc_fw_rpt_ver(rtwdev, RPT_EN_FW_STEP_INFO)) == 0) 9909 return; 9910 9911 pcinfo = &pfwinfo->rpt_fbtc_step.cinfo; 9912 if (!pcinfo->valid) 9913 return; 9914 9915 pstep = &pfwinfo->rpt_fbtc_step.finfo.v3; 9916 if (pcinfo->req_fver != pstep->fver) 9917 return; 9918 9919 if (le32_to_cpu(pstep->cnt) <= FCXDEF_STEP) 9920 n_begin = 1; 9921 else 9922 n_begin = le32_to_cpu(pstep->cnt) - FCXDEF_STEP + 1; 9923 9924 n_end = le32_to_cpu(pstep->cnt); 9925 9926 if (n_begin > n_end) 9927 return; 9928 9929 /* restore step info by using ring instead of FIFO */ 9930 for (i = n_begin; i <= n_end; i++) { 9931 array_idx = (i - 1) % FCXDEF_STEP; 9932 type = pstep->step[array_idx].type; 9933 val = pstep->step[array_idx].val; 9934 diff_t = le16_to_cpu(pstep->step[array_idx].difft); 9935 9936 if (type == CXSTEP_NONE || type >= CXSTEP_MAX) 9937 continue; 9938 9939 if (cnt % 10 == 0) 9940 seq_printf(m, " %-15s : ", "[steps]"); 9941 9942 seq_printf(m, "-> %s(%02d)", 9943 (type == CXSTEP_SLOT ? 9944 id_to_slot((u32)val) : 9945 id_to_evt((u32)val)), diff_t); 9946 9947 if (cnt % 10 == 9) 9948 seq_puts(m, "\n"); 9949 9950 cnt++; 9951 } 9952 } 9953 9954 static void _show_fw_dm_msg(struct rtw89_dev *rtwdev, struct seq_file *m) 9955 { 9956 struct rtw89_btc *btc = &rtwdev->btc; 9957 const struct rtw89_btc_ver *ver = btc->ver; 9958 9959 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_DM)) 9960 return; 9961 9962 _show_error(rtwdev, m); 9963 _show_fbtc_tdma(rtwdev, m); 9964 _show_fbtc_slots(rtwdev, m); 9965 9966 if (ver->fcxcysta == 2) 9967 _show_fbtc_cysta_v2(rtwdev, m); 9968 else if (ver->fcxcysta == 3) 9969 _show_fbtc_cysta_v3(rtwdev, m); 9970 else if (ver->fcxcysta == 4) 9971 _show_fbtc_cysta_v4(rtwdev, m); 9972 else if (ver->fcxcysta == 5) 9973 _show_fbtc_cysta_v5(rtwdev, m); 9974 else if (ver->fcxcysta == 7) 9975 _show_fbtc_cysta_v7(rtwdev, m); 9976 9977 _show_fbtc_nullsta(rtwdev, m); 9978 9979 if (ver->fcxstep == 2) 9980 _show_fbtc_step_v2(rtwdev, m); 9981 else if (ver->fcxstep == 3) 9982 _show_fbtc_step_v3(rtwdev, m); 9983 9984 } 9985 9986 static void _get_gnt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_coex_gnt *gnt_cfg) 9987 { 9988 const struct rtw89_chip_info *chip = rtwdev->chip; 9989 struct rtw89_mac_ax_gnt *gnt; 9990 u32 val, status; 9991 9992 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 9993 chip->chip_id == RTL8851B || chip->chip_id == RTL8852BT) { 9994 rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_1, &val); 9995 rtw89_mac_read_lte(rtwdev, R_AX_GNT_VAL, &status); 9996 9997 gnt = &gnt_cfg->band[0]; 9998 gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S0_SW_CTRL); 9999 gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S0_STA); 10000 gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S0_SW_CTRL); 10001 gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S0_STA); 10002 10003 gnt = &gnt_cfg->band[1]; 10004 gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S1_SW_CTRL); 10005 gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S1_STA); 10006 gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S1_SW_CTRL); 10007 gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S1_STA); 10008 } else if (chip->chip_id == RTL8852C) { 10009 val = rtw89_read32(rtwdev, R_AX_GNT_SW_CTRL); 10010 status = rtw89_read32(rtwdev, R_AX_GNT_VAL_V1); 10011 10012 gnt = &gnt_cfg->band[0]; 10013 gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S0_SWCTRL); 10014 gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S0); 10015 gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S0_SWCTRL); 10016 gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S0); 10017 10018 gnt = &gnt_cfg->band[1]; 10019 gnt->gnt_bt_sw_en = !!(val & B_AX_GNT_BT_RFC_S1_SWCTRL); 10020 gnt->gnt_bt = !!(status & B_AX_GNT_BT_RFC_S1); 10021 gnt->gnt_wl_sw_en = !!(val & B_AX_GNT_WL_RFC_S1_SWCTRL); 10022 gnt->gnt_wl = !!(status & B_AX_GNT_WL_RFC_S1); 10023 } else { 10024 return; 10025 } 10026 } 10027 10028 static void _show_gpio_dbg(struct rtw89_dev *rtwdev, struct seq_file *m) 10029 { 10030 struct rtw89_btc_btf_fwinfo *pfwinfo = &rtwdev->btc.fwinfo; 10031 const struct rtw89_btc_ver *ver = rtwdev->btc.ver; 10032 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 10033 union rtw89_btc_fbtc_gpio_dbg *gdbg = NULL; 10034 u8 *gpio_map, i; 10035 u32 en_map; 10036 10037 pcinfo = &pfwinfo->rpt_fbtc_gpio_dbg.cinfo; 10038 gdbg = &rtwdev->btc.fwinfo.rpt_fbtc_gpio_dbg.finfo; 10039 if (!pcinfo->valid) { 10040 rtw89_debug(rtwdev, RTW89_DBG_BTC, 10041 "[BTC], %s(): stop due rpt_fbtc_gpio_dbg.cinfo\n", 10042 __func__); 10043 seq_puts(m, "\n"); 10044 return; 10045 } 10046 10047 if (ver->fcxgpiodbg == 7) { 10048 en_map = le32_to_cpu(gdbg->v7.en_map); 10049 gpio_map = gdbg->v7.gpio_map; 10050 } else { 10051 en_map = le32_to_cpu(gdbg->v1.en_map); 10052 gpio_map = gdbg->v1.gpio_map; 10053 } 10054 10055 if (!en_map) 10056 return; 10057 10058 seq_printf(m, " %-15s : enable_map:0x%08x", 10059 "[gpio_dbg]", en_map); 10060 10061 for (i = 0; i < BTC_DBG_MAX1; i++) { 10062 if (!(en_map & BIT(i))) 10063 continue; 10064 seq_printf(m, ", %s->GPIO%d", id_to_gdbg(i), gpio_map[i]); 10065 } 10066 seq_puts(m, "\n"); 10067 } 10068 10069 static void _show_mreg_v1(struct rtw89_dev *rtwdev, struct seq_file *m) 10070 { 10071 const struct rtw89_chip_info *chip = rtwdev->chip; 10072 struct rtw89_btc *btc = &rtwdev->btc; 10073 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 10074 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 10075 struct rtw89_btc_fbtc_mreg_val_v1 *pmreg = NULL; 10076 struct rtw89_btc_cx *cx = &btc->cx; 10077 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 10078 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 10079 struct rtw89_mac_ax_coex_gnt gnt_cfg = {}; 10080 struct rtw89_mac_ax_gnt gnt; 10081 u8 i = 0, type = 0, cnt = 0; 10082 u32 val, offset; 10083 10084 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_MREG)) 10085 return; 10086 10087 seq_puts(m, "========== [HW Status] ==========\n"); 10088 10089 seq_printf(m, 10090 " %-15s : WL->BT:0x%08x(cnt:%d), BT->WL:0x%08x(total:%d, bt_update:%d)\n", 10091 "[scoreboard]", wl->scbd, cx->cnt_wl[BTC_WCNT_SCBDUPDATE], 10092 bt->scbd, cx->cnt_bt[BTC_BCNT_SCBDREAD], 10093 cx->cnt_bt[BTC_BCNT_SCBDUPDATE]); 10094 10095 btc->dm.pta_owner = rtw89_mac_get_ctrl_path(rtwdev); 10096 _get_gnt(rtwdev, &gnt_cfg); 10097 10098 gnt = gnt_cfg.band[0]; 10099 seq_printf(m, 10100 " %-15s : pta_owner:%s, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d], ", 10101 "[gnt_status]", 10102 chip->chip_id == RTL8852C ? "HW" : 10103 btc->dm.pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT", 10104 gnt.gnt_wl_sw_en ? "SW" : "HW", gnt.gnt_wl, 10105 gnt.gnt_bt_sw_en ? "SW" : "HW", gnt.gnt_bt); 10106 10107 gnt = gnt_cfg.band[1]; 10108 seq_printf(m, "phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d]\n", 10109 gnt.gnt_wl_sw_en ? "SW" : "HW", 10110 gnt.gnt_wl, 10111 gnt.gnt_bt_sw_en ? "SW" : "HW", 10112 gnt.gnt_bt); 10113 10114 pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; 10115 if (!pcinfo->valid) { 10116 rtw89_debug(rtwdev, RTW89_DBG_BTC, 10117 "[BTC], %s(): stop due rpt_fbtc_mregval.cinfo\n", 10118 __func__); 10119 return; 10120 } 10121 10122 pmreg = &pfwinfo->rpt_fbtc_mregval.finfo.v1; 10123 rtw89_debug(rtwdev, RTW89_DBG_BTC, 10124 "[BTC], %s(): rpt_fbtc_mregval reg_num = %d\n", 10125 __func__, pmreg->reg_num); 10126 10127 for (i = 0; i < pmreg->reg_num; i++) { 10128 type = (u8)le16_to_cpu(chip->mon_reg[i].type); 10129 offset = le32_to_cpu(chip->mon_reg[i].offset); 10130 val = le32_to_cpu(pmreg->mreg_val[i]); 10131 10132 if (cnt % 6 == 0) 10133 seq_printf(m, " %-15s : %d_0x%04x=0x%08x", 10134 "[reg]", (u32)type, offset, val); 10135 else 10136 seq_printf(m, ", %d_0x%04x=0x%08x", (u32)type, 10137 offset, val); 10138 if (cnt % 6 == 5) 10139 seq_puts(m, "\n"); 10140 cnt++; 10141 10142 if (i >= pmreg->reg_num) 10143 seq_puts(m, "\n"); 10144 } 10145 } 10146 10147 static void _show_mreg_v2(struct rtw89_dev *rtwdev, struct seq_file *m) 10148 { 10149 const struct rtw89_chip_info *chip = rtwdev->chip; 10150 struct rtw89_btc *btc = &rtwdev->btc; 10151 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 10152 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 10153 struct rtw89_btc_fbtc_mreg_val_v2 *pmreg = NULL; 10154 struct rtw89_btc_cx *cx = &btc->cx; 10155 struct rtw89_btc_wl_info *wl = &btc->cx.wl; 10156 struct rtw89_btc_bt_info *bt = &btc->cx.bt; 10157 struct rtw89_mac_ax_coex_gnt gnt_cfg = {}; 10158 struct rtw89_mac_ax_gnt gnt; 10159 u8 i = 0, type = 0, cnt = 0; 10160 u32 val, offset; 10161 10162 if (!(btc->dm.coex_info_map & BTC_COEX_INFO_MREG)) 10163 return; 10164 10165 seq_puts(m, "========== [HW Status] ==========\n"); 10166 10167 seq_printf(m, 10168 " %-15s : WL->BT:0x%08x(cnt:%d), BT->WL:0x%08x(total:%d, bt_update:%d)\n", 10169 "[scoreboard]", wl->scbd, cx->cnt_wl[BTC_WCNT_SCBDUPDATE], 10170 bt->scbd, cx->cnt_bt[BTC_BCNT_SCBDREAD], 10171 cx->cnt_bt[BTC_BCNT_SCBDUPDATE]); 10172 10173 btc->dm.pta_owner = rtw89_mac_get_ctrl_path(rtwdev); 10174 _get_gnt(rtwdev, &gnt_cfg); 10175 10176 gnt = gnt_cfg.band[0]; 10177 seq_printf(m, 10178 " %-15s : pta_owner:%s, phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d], polut_type:%s", 10179 "[gnt_status]", 10180 chip->chip_id == RTL8852C ? "HW" : 10181 btc->dm.pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT", 10182 gnt.gnt_wl_sw_en ? "SW" : "HW", gnt.gnt_wl, 10183 gnt.gnt_bt_sw_en ? "SW" : "HW", gnt.gnt_bt, 10184 id_to_polut(wl->bt_polut_type[wl->pta_req_mac])); 10185 10186 gnt = gnt_cfg.band[1]; 10187 seq_printf(m, "phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d]\n", 10188 gnt.gnt_wl_sw_en ? "SW" : "HW", 10189 gnt.gnt_wl, 10190 gnt.gnt_bt_sw_en ? "SW" : "HW", 10191 gnt.gnt_bt); 10192 10193 pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; 10194 if (!pcinfo->valid) { 10195 rtw89_debug(rtwdev, RTW89_DBG_BTC, 10196 "[BTC], %s(): stop due rpt_fbtc_mregval.cinfo\n", 10197 __func__); 10198 return; 10199 } 10200 10201 pmreg = &pfwinfo->rpt_fbtc_mregval.finfo.v2; 10202 rtw89_debug(rtwdev, RTW89_DBG_BTC, 10203 "[BTC], %s(): rpt_fbtc_mregval reg_num = %d\n", 10204 __func__, pmreg->reg_num); 10205 10206 for (i = 0; i < pmreg->reg_num; i++) { 10207 type = (u8)le16_to_cpu(chip->mon_reg[i].type); 10208 offset = le32_to_cpu(chip->mon_reg[i].offset); 10209 val = le32_to_cpu(pmreg->mreg_val[i]); 10210 10211 if (cnt % 6 == 0) 10212 seq_printf(m, " %-15s : %d_0x%04x=0x%08x", 10213 "[reg]", (u32)type, offset, val); 10214 else 10215 seq_printf(m, ", %d_0x%04x=0x%08x", (u32)type, 10216 offset, val); 10217 if (cnt % 6 == 5) 10218 seq_puts(m, "\n"); 10219 cnt++; 10220 10221 if (i >= pmreg->reg_num) 10222 seq_puts(m, "\n"); 10223 } 10224 } 10225 10226 static void _show_mreg_v7(struct rtw89_dev *rtwdev, struct seq_file *m) 10227 { 10228 struct rtw89_btc *btc = &rtwdev->btc; 10229 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 10230 struct rtw89_btc_fbtc_mreg_val_v7 *pmreg = NULL; 10231 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 10232 struct rtw89_btc_cx *cx = &btc->cx; 10233 struct rtw89_btc_wl_info *wl = &cx->wl; 10234 struct rtw89_btc_bt_info *bt = &cx->bt; 10235 struct rtw89_mac_ax_gnt *gnt = NULL; 10236 struct rtw89_btc_dm *dm = &btc->dm; 10237 u8 i, type, cnt = 0; 10238 u32 val, offset; 10239 10240 if (!(dm->coex_info_map & BTC_COEX_INFO_MREG)) 10241 return; 10242 10243 seq_puts(m, "\n\r========== [HW Status] =========="); 10244 10245 seq_printf(m, 10246 "\n\r %-15s : WL->BT:0x%08x(cnt:%d), BT->WL:0x%08x(total:%d, bt_update:%d)", 10247 "[scoreboard]", wl->scbd, cx->cnt_wl[BTC_WCNT_SCBDUPDATE], 10248 bt->scbd, cx->cnt_bt[BTC_BCNT_SCBDREAD], 10249 cx->cnt_bt[BTC_BCNT_SCBDUPDATE]); 10250 10251 /* To avoid I/O if WL LPS or power-off */ 10252 dm->pta_owner = rtw89_mac_get_ctrl_path(rtwdev); 10253 10254 seq_printf(m, 10255 "\n\r %-15s : pta_owner:%s, pta_req_mac:MAC%d, rf_gnt_source: polut_type:%s", 10256 "[gnt_status]", 10257 rtwdev->chip->para_ver & BTC_FEAT_PTA_ONOFF_CTRL ? "HW" : 10258 dm->pta_owner == BTC_CTRL_BY_WL ? "WL" : "BT", 10259 wl->pta_req_mac, id_to_polut(wl->bt_polut_type[wl->pta_req_mac])); 10260 10261 gnt = &dm->gnt.band[RTW89_PHY_0]; 10262 10263 seq_printf(m, ", phy-0[gnt_wl:%s-%d/gnt_bt:%s-%d]", 10264 gnt->gnt_wl_sw_en ? "SW" : "HW", gnt->gnt_wl, 10265 gnt->gnt_bt_sw_en ? "SW" : "HW", gnt->gnt_bt); 10266 10267 if (rtwdev->dbcc_en) { 10268 gnt = &dm->gnt.band[RTW89_PHY_1]; 10269 seq_printf(m, ", phy-1[gnt_wl:%s-%d/gnt_bt:%s-%d]", 10270 gnt->gnt_wl_sw_en ? "SW" : "HW", gnt->gnt_wl, 10271 gnt->gnt_bt_sw_en ? "SW" : "HW", gnt->gnt_bt); 10272 } 10273 10274 pcinfo = &pfwinfo->rpt_fbtc_mregval.cinfo; 10275 if (!pcinfo->valid) 10276 return; 10277 10278 pmreg = &pfwinfo->rpt_fbtc_mregval.finfo.v7; 10279 10280 for (i = 0; i < pmreg->reg_num; i++) { 10281 type = (u8)le16_to_cpu(rtwdev->chip->mon_reg[i].type); 10282 offset = le32_to_cpu(rtwdev->chip->mon_reg[i].offset); 10283 val = le32_to_cpu(pmreg->mreg_val[i]); 10284 10285 if (cnt % 6 == 0) 10286 seq_printf(m, "\n\r %-15s : %s_0x%x=0x%x", "[reg]", 10287 id_to_regtype(type), offset, val); 10288 else 10289 seq_printf(m, ", %s_0x%x=0x%x", 10290 id_to_regtype(type), offset, val); 10291 cnt++; 10292 } 10293 seq_puts(m, "\n"); 10294 } 10295 10296 static void _show_summary_v1(struct rtw89_dev *rtwdev, struct seq_file *m) 10297 { 10298 struct rtw89_btc *btc = &rtwdev->btc; 10299 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 10300 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 10301 struct rtw89_btc_fbtc_rpt_ctrl_v1 *prptctrl = NULL; 10302 struct rtw89_btc_cx *cx = &btc->cx; 10303 struct rtw89_btc_dm *dm = &btc->dm; 10304 struct rtw89_btc_wl_info *wl = &cx->wl; 10305 struct rtw89_btc_bt_info *bt = &cx->bt; 10306 u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify; 10307 u8 i; 10308 10309 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY)) 10310 return; 10311 10312 seq_puts(m, "========== [Statistics] ==========\n"); 10313 10314 pcinfo = &pfwinfo->rpt_ctrl.cinfo; 10315 if (pcinfo->valid && !wl->status.map.lps && !wl->status.map.rf_off) { 10316 prptctrl = &pfwinfo->rpt_ctrl.finfo.v1; 10317 10318 seq_printf(m, 10319 " %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d), c2h_cnt=%d(fw_send:%d), ", 10320 "[summary]", pfwinfo->cnt_h2c, 10321 pfwinfo->cnt_h2c_fail, prptctrl->h2c_cnt, 10322 pfwinfo->cnt_c2h, prptctrl->c2h_cnt); 10323 10324 seq_printf(m, 10325 "rpt_cnt=%d(fw_send:%d), rpt_map=0x%x, dm_error_map:0x%x", 10326 pfwinfo->event[BTF_EVNT_RPT], prptctrl->rpt_cnt, 10327 prptctrl->rpt_enable, dm->error.val); 10328 10329 if (dm->error.map.wl_fw_hang) 10330 seq_puts(m, " (WL FW Hang!!)"); 10331 seq_puts(m, "\n"); 10332 seq_printf(m, 10333 " %-15s : send_ok:%d, send_fail:%d, recv:%d", 10334 "[mailbox]", prptctrl->mb_send_ok_cnt, 10335 prptctrl->mb_send_fail_cnt, prptctrl->mb_recv_cnt); 10336 10337 seq_printf(m, 10338 "(A2DP_empty:%d, A2DP_flowstop:%d, A2DP_full:%d)\n", 10339 prptctrl->mb_a2dp_empty_cnt, 10340 prptctrl->mb_a2dp_flct_cnt, 10341 prptctrl->mb_a2dp_full_cnt); 10342 10343 seq_printf(m, 10344 " %-15s : wl_rfk[req:%d/go:%d/reject:%d/timeout:%d]", 10345 "[RFK]", cx->cnt_wl[BTC_WCNT_RFK_REQ], 10346 cx->cnt_wl[BTC_WCNT_RFK_GO], 10347 cx->cnt_wl[BTC_WCNT_RFK_REJECT], 10348 cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]); 10349 10350 seq_printf(m, 10351 ", bt_rfk[req:%d/go:%d/reject:%d/timeout:%d/fail:%d]\n", 10352 prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REQ], 10353 prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_GO], 10354 prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_REJECT], 10355 prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT], 10356 prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_FAIL]); 10357 10358 if (prptctrl->bt_rfk_cnt[BTC_BCNT_RFK_TIMEOUT] > 0) 10359 bt->rfk_info.map.timeout = 1; 10360 else 10361 bt->rfk_info.map.timeout = 0; 10362 10363 dm->error.map.wl_rfk_timeout = bt->rfk_info.map.timeout; 10364 } else { 10365 seq_printf(m, 10366 " %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d, rpt_cnt=%d, rpt_map=0x%x", 10367 "[summary]", pfwinfo->cnt_h2c, 10368 pfwinfo->cnt_h2c_fail, pfwinfo->cnt_c2h, 10369 pfwinfo->event[BTF_EVNT_RPT], 10370 btc->fwinfo.rpt_en_map); 10371 seq_puts(m, " (WL FW report invalid!!)\n"); 10372 } 10373 10374 for (i = 0; i < BTC_NCNT_NUM; i++) 10375 cnt_sum += dm->cnt_notify[i]; 10376 10377 seq_printf(m, 10378 " %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ", 10379 "[notify_cnt]", cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO], 10380 cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]); 10381 10382 seq_printf(m, 10383 "power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d\n", 10384 cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE], 10385 cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK], 10386 cnt[BTC_NCNT_WL_STA]); 10387 10388 seq_printf(m, 10389 " %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, special_pkt=%d, ", 10390 "[notify_cnt]", cnt[BTC_NCNT_SCAN_START], 10391 cnt[BTC_NCNT_SCAN_FINISH], cnt[BTC_NCNT_SWITCH_BAND], 10392 cnt[BTC_NCNT_SPECIAL_PACKET]); 10393 10394 seq_printf(m, 10395 "timer=%d, control=%d, customerize=%d\n", 10396 cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CONTROL], 10397 cnt[BTC_NCNT_CUSTOMERIZE]); 10398 } 10399 10400 static void _show_summary_v4(struct rtw89_dev *rtwdev, struct seq_file *m) 10401 { 10402 struct rtw89_btc *btc = &rtwdev->btc; 10403 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 10404 struct rtw89_btc_fbtc_rpt_ctrl_v4 *prptctrl; 10405 struct rtw89_btc_rpt_cmn_info *pcinfo; 10406 struct rtw89_btc_cx *cx = &btc->cx; 10407 struct rtw89_btc_dm *dm = &btc->dm; 10408 struct rtw89_btc_wl_info *wl = &cx->wl; 10409 struct rtw89_btc_bt_info *bt = &cx->bt; 10410 u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify; 10411 u8 i; 10412 10413 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY)) 10414 return; 10415 10416 seq_puts(m, "========== [Statistics] ==========\n"); 10417 10418 pcinfo = &pfwinfo->rpt_ctrl.cinfo; 10419 if (pcinfo->valid && !wl->status.map.lps && !wl->status.map.rf_off) { 10420 prptctrl = &pfwinfo->rpt_ctrl.finfo.v4; 10421 10422 seq_printf(m, 10423 " %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d), c2h_cnt=%d(fw_send:%d), ", 10424 "[summary]", pfwinfo->cnt_h2c, 10425 pfwinfo->cnt_h2c_fail, 10426 le32_to_cpu(prptctrl->rpt_info.cnt_h2c), 10427 pfwinfo->cnt_c2h, 10428 le32_to_cpu(prptctrl->rpt_info.cnt_c2h)); 10429 10430 seq_printf(m, 10431 "rpt_cnt=%d(fw_send:%d), rpt_map=0x%x, dm_error_map:0x%x", 10432 pfwinfo->event[BTF_EVNT_RPT], 10433 le32_to_cpu(prptctrl->rpt_info.cnt), 10434 le32_to_cpu(prptctrl->rpt_info.en), 10435 dm->error.val); 10436 10437 if (dm->error.map.wl_fw_hang) 10438 seq_puts(m, " (WL FW Hang!!)"); 10439 seq_puts(m, "\n"); 10440 seq_printf(m, 10441 " %-15s : send_ok:%d, send_fail:%d, recv:%d, ", 10442 "[mailbox]", 10443 le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_ok), 10444 le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_fail), 10445 le32_to_cpu(prptctrl->bt_mbx_info.cnt_recv)); 10446 10447 seq_printf(m, 10448 "A2DP_empty:%d(stop:%d, tx:%d, ack:%d, nack:%d)\n", 10449 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_empty), 10450 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_flowctrl), 10451 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_tx), 10452 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_ack), 10453 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_nack)); 10454 10455 seq_printf(m, 10456 " %-15s : wl_rfk[req:%d/go:%d/reject:%d/timeout:%d]", 10457 "[RFK]", cx->cnt_wl[BTC_WCNT_RFK_REQ], 10458 cx->cnt_wl[BTC_WCNT_RFK_GO], 10459 cx->cnt_wl[BTC_WCNT_RFK_REJECT], 10460 cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]); 10461 10462 seq_printf(m, 10463 ", bt_rfk[req:%d/go:%d/reject:%d/timeout:%d/fail:%d]\n", 10464 le32_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_REQ]), 10465 le32_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_GO]), 10466 le32_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_REJECT]), 10467 le32_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_TIMEOUT]), 10468 le32_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_FAIL])); 10469 10470 if (le32_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_TIMEOUT]) > 0) 10471 bt->rfk_info.map.timeout = 1; 10472 else 10473 bt->rfk_info.map.timeout = 0; 10474 10475 dm->error.map.wl_rfk_timeout = bt->rfk_info.map.timeout; 10476 } else { 10477 seq_printf(m, 10478 " %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d, rpt_cnt=%d, rpt_map=0x%x", 10479 "[summary]", pfwinfo->cnt_h2c, 10480 pfwinfo->cnt_h2c_fail, pfwinfo->cnt_c2h, 10481 pfwinfo->event[BTF_EVNT_RPT], 10482 btc->fwinfo.rpt_en_map); 10483 seq_puts(m, " (WL FW report invalid!!)\n"); 10484 } 10485 10486 for (i = 0; i < BTC_NCNT_NUM; i++) 10487 cnt_sum += dm->cnt_notify[i]; 10488 10489 seq_printf(m, 10490 " %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ", 10491 "[notify_cnt]", cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO], 10492 cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]); 10493 10494 seq_printf(m, 10495 "power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d\n", 10496 cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE], 10497 cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK], 10498 cnt[BTC_NCNT_WL_STA]); 10499 10500 seq_printf(m, 10501 " %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, special_pkt=%d, ", 10502 "[notify_cnt]", cnt[BTC_NCNT_SCAN_START], 10503 cnt[BTC_NCNT_SCAN_FINISH], cnt[BTC_NCNT_SWITCH_BAND], 10504 cnt[BTC_NCNT_SPECIAL_PACKET]); 10505 10506 seq_printf(m, 10507 "timer=%d, control=%d, customerize=%d\n", 10508 cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CONTROL], 10509 cnt[BTC_NCNT_CUSTOMERIZE]); 10510 } 10511 10512 static void _show_summary_v5(struct rtw89_dev *rtwdev, struct seq_file *m) 10513 { 10514 struct rtw89_btc *btc = &rtwdev->btc; 10515 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 10516 struct rtw89_btc_fbtc_rpt_ctrl_v5 *prptctrl; 10517 struct rtw89_btc_rpt_cmn_info *pcinfo; 10518 struct rtw89_btc_cx *cx = &btc->cx; 10519 struct rtw89_btc_dm *dm = &btc->dm; 10520 struct rtw89_btc_wl_info *wl = &cx->wl; 10521 u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify; 10522 u8 i; 10523 10524 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY)) 10525 return; 10526 10527 seq_puts(m, "========== [Statistics] ==========\n"); 10528 10529 pcinfo = &pfwinfo->rpt_ctrl.cinfo; 10530 if (pcinfo->valid && !wl->status.map.lps && !wl->status.map.rf_off) { 10531 prptctrl = &pfwinfo->rpt_ctrl.finfo.v5; 10532 10533 seq_printf(m, 10534 " %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d), c2h_cnt=%d(fw_send:%d, len:%d), ", 10535 "[summary]", pfwinfo->cnt_h2c, pfwinfo->cnt_h2c_fail, 10536 le16_to_cpu(prptctrl->rpt_info.cnt_h2c), 10537 pfwinfo->cnt_c2h, 10538 le16_to_cpu(prptctrl->rpt_info.cnt_c2h), 10539 le16_to_cpu(prptctrl->rpt_info.len_c2h)); 10540 10541 seq_printf(m, 10542 "rpt_cnt=%d(fw_send:%d), rpt_map=0x%x", 10543 pfwinfo->event[BTF_EVNT_RPT], 10544 le16_to_cpu(prptctrl->rpt_info.cnt), 10545 le32_to_cpu(prptctrl->rpt_info.en)); 10546 10547 if (dm->error.map.wl_fw_hang) 10548 seq_puts(m, " (WL FW Hang!!)"); 10549 seq_puts(m, "\n"); 10550 seq_printf(m, 10551 " %-15s : send_ok:%d, send_fail:%d, recv:%d, ", 10552 "[mailbox]", 10553 le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_ok), 10554 le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_fail), 10555 le32_to_cpu(prptctrl->bt_mbx_info.cnt_recv)); 10556 10557 seq_printf(m, 10558 "A2DP_empty:%d(stop:%d, tx:%d, ack:%d, nack:%d)\n", 10559 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_empty), 10560 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_flowctrl), 10561 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_tx), 10562 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_ack), 10563 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_nack)); 10564 10565 seq_printf(m, 10566 " %-15s : wl_rfk[req:%d/go:%d/reject:%d/tout:%d]", 10567 "[RFK/LPS]", cx->cnt_wl[BTC_WCNT_RFK_REQ], 10568 cx->cnt_wl[BTC_WCNT_RFK_GO], 10569 cx->cnt_wl[BTC_WCNT_RFK_REJECT], 10570 cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]); 10571 10572 seq_printf(m, 10573 ", bt_rfk[req:%d]", 10574 le16_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_REQ])); 10575 10576 seq_printf(m, 10577 ", AOAC[RF_on:%d/RF_off:%d]", 10578 le16_to_cpu(prptctrl->rpt_info.cnt_aoac_rf_on), 10579 le16_to_cpu(prptctrl->rpt_info.cnt_aoac_rf_off)); 10580 } else { 10581 seq_printf(m, 10582 " %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d", 10583 "[summary]", pfwinfo->cnt_h2c, 10584 pfwinfo->cnt_h2c_fail, pfwinfo->cnt_c2h); 10585 } 10586 10587 if (!pcinfo->valid || pfwinfo->len_mismch || pfwinfo->fver_mismch || 10588 pfwinfo->err[BTFRE_EXCEPTION]) { 10589 seq_puts(m, "\n"); 10590 seq_printf(m, 10591 " %-15s : WL FW rpt error!![rpt_ctrl_valid:%d/len:" 10592 "0x%x/ver:0x%x/ex:%d/lps=%d/rf_off=%d]", 10593 "[ERROR]", pcinfo->valid, pfwinfo->len_mismch, 10594 pfwinfo->fver_mismch, pfwinfo->err[BTFRE_EXCEPTION], 10595 wl->status.map.lps, wl->status.map.rf_off); 10596 } 10597 10598 for (i = 0; i < BTC_NCNT_NUM; i++) 10599 cnt_sum += dm->cnt_notify[i]; 10600 10601 seq_puts(m, "\n"); 10602 seq_printf(m, 10603 " %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ", 10604 "[notify_cnt]", 10605 cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO], 10606 cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]); 10607 10608 seq_printf(m, 10609 "power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d", 10610 cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE], 10611 cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK], 10612 cnt[BTC_NCNT_WL_STA]); 10613 10614 seq_puts(m, "\n"); 10615 seq_printf(m, 10616 " %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, special_pkt=%d, ", 10617 "[notify_cnt]", 10618 cnt[BTC_NCNT_SCAN_START], cnt[BTC_NCNT_SCAN_FINISH], 10619 cnt[BTC_NCNT_SWITCH_BAND], cnt[BTC_NCNT_SPECIAL_PACKET]); 10620 10621 seq_printf(m, 10622 "timer=%d, control=%d, customerize=%d", 10623 cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CONTROL], 10624 cnt[BTC_NCNT_CUSTOMERIZE]); 10625 } 10626 10627 static void _show_summary_v105(struct rtw89_dev *rtwdev, struct seq_file *m) 10628 { 10629 struct rtw89_btc *btc = &rtwdev->btc; 10630 struct rtw89_btc_btf_fwinfo *pfwinfo = &btc->fwinfo; 10631 struct rtw89_btc_fbtc_rpt_ctrl_v105 *prptctrl; 10632 struct rtw89_btc_rpt_cmn_info *pcinfo; 10633 struct rtw89_btc_cx *cx = &btc->cx; 10634 struct rtw89_btc_dm *dm = &btc->dm; 10635 struct rtw89_btc_wl_info *wl = &cx->wl; 10636 u32 cnt_sum = 0, *cnt = btc->dm.cnt_notify; 10637 u8 i; 10638 10639 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY)) 10640 return; 10641 10642 seq_puts(m, "========== [Statistics] ==========\n"); 10643 10644 pcinfo = &pfwinfo->rpt_ctrl.cinfo; 10645 if (pcinfo->valid && !wl->status.map.lps && !wl->status.map.rf_off) { 10646 prptctrl = &pfwinfo->rpt_ctrl.finfo.v105; 10647 10648 seq_printf(m, 10649 " %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d), c2h_cnt=%d(fw_send:%d, len:%d), ", 10650 "[summary]", pfwinfo->cnt_h2c, pfwinfo->cnt_h2c_fail, 10651 le16_to_cpu(prptctrl->rpt_info.cnt_h2c), 10652 pfwinfo->cnt_c2h, 10653 le16_to_cpu(prptctrl->rpt_info.cnt_c2h), 10654 le16_to_cpu(prptctrl->rpt_info.len_c2h)); 10655 10656 seq_printf(m, 10657 "rpt_cnt=%d(fw_send:%d), rpt_map=0x%x", 10658 pfwinfo->event[BTF_EVNT_RPT], 10659 le16_to_cpu(prptctrl->rpt_info.cnt), 10660 le32_to_cpu(prptctrl->rpt_info.en)); 10661 10662 if (dm->error.map.wl_fw_hang) 10663 seq_puts(m, " (WL FW Hang!!)"); 10664 seq_puts(m, "\n"); 10665 seq_printf(m, 10666 " %-15s : send_ok:%d, send_fail:%d, recv:%d, ", 10667 "[mailbox]", 10668 le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_ok), 10669 le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_fail), 10670 le32_to_cpu(prptctrl->bt_mbx_info.cnt_recv)); 10671 10672 seq_printf(m, 10673 "A2DP_empty:%d(stop:%d, tx:%d, ack:%d, nack:%d)\n", 10674 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_empty), 10675 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_flowctrl), 10676 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_tx), 10677 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_ack), 10678 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_nack)); 10679 10680 seq_printf(m, 10681 " %-15s : wl_rfk[req:%d/go:%d/reject:%d/tout:%d]", 10682 "[RFK/LPS]", cx->cnt_wl[BTC_WCNT_RFK_REQ], 10683 cx->cnt_wl[BTC_WCNT_RFK_GO], 10684 cx->cnt_wl[BTC_WCNT_RFK_REJECT], 10685 cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT]); 10686 10687 seq_printf(m, 10688 ", bt_rfk[req:%d]", 10689 le16_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_REQ])); 10690 10691 seq_printf(m, 10692 ", AOAC[RF_on:%d/RF_off:%d]", 10693 le16_to_cpu(prptctrl->rpt_info.cnt_aoac_rf_on), 10694 le16_to_cpu(prptctrl->rpt_info.cnt_aoac_rf_off)); 10695 } else { 10696 seq_printf(m, 10697 " %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d", 10698 "[summary]", pfwinfo->cnt_h2c, 10699 pfwinfo->cnt_h2c_fail, pfwinfo->cnt_c2h); 10700 } 10701 10702 if (!pcinfo->valid || pfwinfo->len_mismch || pfwinfo->fver_mismch || 10703 pfwinfo->err[BTFRE_EXCEPTION]) { 10704 seq_puts(m, "\n"); 10705 seq_printf(m, 10706 " %-15s : WL FW rpt error!![rpt_ctrl_valid:%d/len:" 10707 "0x%x/ver:0x%x/ex:%d/lps=%d/rf_off=%d]", 10708 "[ERROR]", pcinfo->valid, pfwinfo->len_mismch, 10709 pfwinfo->fver_mismch, pfwinfo->err[BTFRE_EXCEPTION], 10710 wl->status.map.lps, wl->status.map.rf_off); 10711 } 10712 10713 for (i = 0; i < BTC_NCNT_NUM; i++) 10714 cnt_sum += dm->cnt_notify[i]; 10715 10716 seq_puts(m, "\n"); 10717 seq_printf(m, 10718 " %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ", 10719 "[notify_cnt]", 10720 cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO], 10721 cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]); 10722 10723 seq_printf(m, 10724 "power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d", 10725 cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE], 10726 cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK], 10727 cnt[BTC_NCNT_WL_STA]); 10728 10729 seq_puts(m, "\n"); 10730 seq_printf(m, 10731 " %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, special_pkt=%d, ", 10732 "[notify_cnt]", 10733 cnt[BTC_NCNT_SCAN_START], cnt[BTC_NCNT_SCAN_FINISH], 10734 cnt[BTC_NCNT_SWITCH_BAND], cnt[BTC_NCNT_SPECIAL_PACKET]); 10735 10736 seq_printf(m, 10737 "timer=%d, control=%d, customerize=%d", 10738 cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CONTROL], 10739 cnt[BTC_NCNT_CUSTOMERIZE]); 10740 } 10741 10742 static void _show_summary_v7(struct rtw89_dev *rtwdev, struct seq_file *m) 10743 { 10744 struct rtw89_btc_btf_fwinfo *pfwinfo = &rtwdev->btc.fwinfo; 10745 struct rtw89_btc_fbtc_rpt_ctrl_v7 *prptctrl = NULL; 10746 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 10747 struct rtw89_btc_cx *cx = &rtwdev->btc.cx; 10748 struct rtw89_btc_dm *dm = &rtwdev->btc.dm; 10749 struct rtw89_btc_wl_info *wl = &cx->wl; 10750 u32 *cnt = rtwdev->btc.dm.cnt_notify; 10751 u32 cnt_sum = 0; 10752 u8 i; 10753 10754 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY)) 10755 return; 10756 10757 seq_printf(m, "%s", "\n\r========== [Statistics] =========="); 10758 10759 pcinfo = &pfwinfo->rpt_ctrl.cinfo; 10760 if (pcinfo->valid && wl->status.map.lps != BTC_LPS_RF_OFF && 10761 !wl->status.map.rf_off) { 10762 prptctrl = &pfwinfo->rpt_ctrl.finfo.v7; 10763 10764 seq_printf(m, 10765 "\n\r %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d)," 10766 "c2h_cnt=%d(fw_send:%d, len:%d, max:%d), ", 10767 "[summary]", pfwinfo->cnt_h2c, pfwinfo->cnt_h2c_fail, 10768 le16_to_cpu(prptctrl->rpt_info.cnt_h2c), pfwinfo->cnt_c2h, 10769 le16_to_cpu(prptctrl->rpt_info.cnt_c2h), 10770 le16_to_cpu(prptctrl->rpt_info.len_c2h), 10771 rtwdev->btc.ver->info_buf); 10772 10773 seq_printf(m, "rpt_cnt=%d(fw_send:%d), rpt_map=0x%x", 10774 pfwinfo->event[BTF_EVNT_RPT], 10775 le16_to_cpu(prptctrl->rpt_info.cnt), 10776 le32_to_cpu(prptctrl->rpt_info.en)); 10777 10778 if (dm->error.map.wl_fw_hang) 10779 seq_puts(m, " (WL FW Hang!!)"); 10780 10781 seq_printf(m, "\n\r %-15s : send_ok:%d, send_fail:%d, recv:%d, ", 10782 "[mailbox]", le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_ok), 10783 le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_fail), 10784 le32_to_cpu(prptctrl->bt_mbx_info.cnt_recv)); 10785 10786 seq_printf(m, "A2DP_empty:%d(stop:%d/tx:%d/ack:%d/nack:%d)", 10787 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_empty), 10788 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_flowctrl), 10789 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_tx), 10790 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_ack), 10791 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_nack)); 10792 10793 seq_printf(m, 10794 "\n\r %-15s : wl_rfk[req:%d/go:%d/reject:%d/tout:%d/time:%dms]", 10795 "[RFK/LPS]", cx->cnt_wl[BTC_WCNT_RFK_REQ], 10796 cx->cnt_wl[BTC_WCNT_RFK_GO], 10797 cx->cnt_wl[BTC_WCNT_RFK_REJECT], 10798 cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT], 10799 wl->rfk_info.proc_time); 10800 10801 seq_printf(m, ", bt_rfk[req:%d]", 10802 le16_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_REQ])); 10803 10804 seq_printf(m, ", AOAC[RF_on:%d/RF_off:%d]", 10805 le16_to_cpu(prptctrl->rpt_info.cnt_aoac_rf_on), 10806 le16_to_cpu(prptctrl->rpt_info.cnt_aoac_rf_off)); 10807 } else { 10808 seq_printf(m, 10809 "\n\r %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d (lps=%d/rf_off=%d)", 10810 "[summary]", 10811 pfwinfo->cnt_h2c, pfwinfo->cnt_h2c_fail, 10812 pfwinfo->cnt_c2h, 10813 wl->status.map.lps, wl->status.map.rf_off); 10814 } 10815 10816 for (i = 0; i < BTC_NCNT_NUM; i++) 10817 cnt_sum += dm->cnt_notify[i]; 10818 10819 seq_printf(m, 10820 "\n\r %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ", 10821 "[notify_cnt]", 10822 cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO], 10823 cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]); 10824 10825 seq_printf(m, 10826 "power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d", 10827 cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE], 10828 cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK], 10829 cnt[BTC_NCNT_WL_STA]); 10830 10831 seq_printf(m, 10832 "\n\r %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, switch_chbw=%d, special_pkt=%d, ", 10833 "[notify_cnt]", 10834 cnt[BTC_NCNT_SCAN_START], cnt[BTC_NCNT_SCAN_FINISH], 10835 cnt[BTC_NCNT_SWITCH_BAND], cnt[BTC_NCNT_SWITCH_CHBW], 10836 cnt[BTC_NCNT_SPECIAL_PACKET]); 10837 10838 seq_printf(m, "timer=%d, customerize=%d, hub_msg=%d, chg_fw=%d, send_cc=%d", 10839 cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CUSTOMERIZE], 10840 rtwdev->btc.hubmsg_cnt, cnt[BTC_NCNT_RESUME_DL_FW], 10841 cnt[BTC_NCNT_COUNTRYCODE]); 10842 } 10843 10844 static void _show_summary_v8(struct rtw89_dev *rtwdev, struct seq_file *m) 10845 { 10846 struct rtw89_btc_btf_fwinfo *pfwinfo = &rtwdev->btc.fwinfo; 10847 struct rtw89_btc_rpt_cmn_info *pcinfo = NULL; 10848 struct rtw89_btc_fbtc_rpt_ctrl_v8 *prptctrl = NULL; 10849 struct rtw89_btc_cx *cx = &rtwdev->btc.cx; 10850 struct rtw89_btc_dm *dm = &rtwdev->btc.dm; 10851 struct rtw89_btc_wl_info *wl = &cx->wl; 10852 u32 *cnt = rtwdev->btc.dm.cnt_notify; 10853 u32 cnt_sum = 0; 10854 u8 i; 10855 10856 if (!(dm->coex_info_map & BTC_COEX_INFO_SUMMARY)) 10857 return; 10858 10859 seq_printf(m, "%s", "\n\r========== [Statistics] =========="); 10860 10861 pcinfo = &pfwinfo->rpt_ctrl.cinfo; 10862 if (pcinfo->valid && wl->status.map.lps != BTC_LPS_RF_OFF && 10863 !wl->status.map.rf_off) { 10864 prptctrl = &pfwinfo->rpt_ctrl.finfo.v8; 10865 10866 seq_printf(m, 10867 "\n\r %-15s : h2c_cnt=%d(fail:%d, fw_recv:%d), c2h_cnt=%d(fw_send:%d, len:%d, max:fw-%d/drv-%d), ", 10868 "[summary]", pfwinfo->cnt_h2c, pfwinfo->cnt_h2c_fail, 10869 le16_to_cpu(prptctrl->rpt_info.cnt_h2c), pfwinfo->cnt_c2h, 10870 le16_to_cpu(prptctrl->rpt_info.cnt_c2h), 10871 le16_to_cpu(prptctrl->rpt_info.len_c2h), 10872 (prptctrl->rpt_len_max_h << 8) + prptctrl->rpt_len_max_l, 10873 rtwdev->btc.ver->info_buf); 10874 10875 seq_printf(m, "rpt_cnt=%d(fw_send:%d), rpt_map=0x%x", 10876 pfwinfo->event[BTF_EVNT_RPT], 10877 le16_to_cpu(prptctrl->rpt_info.cnt), 10878 le32_to_cpu(prptctrl->rpt_info.en)); 10879 10880 if (dm->error.map.wl_fw_hang) 10881 seq_puts(m, " (WL FW Hang!!)"); 10882 10883 seq_printf(m, "\n\r %-15s : send_ok:%d, send_fail:%d, recv:%d, ", 10884 "[mailbox]", le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_ok), 10885 le32_to_cpu(prptctrl->bt_mbx_info.cnt_send_fail), 10886 le32_to_cpu(prptctrl->bt_mbx_info.cnt_recv)); 10887 10888 seq_printf(m, "A2DP_empty:%d(stop:%d/tx:%d/ack:%d/nack:%d)", 10889 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_empty), 10890 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_flowctrl), 10891 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_tx), 10892 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_ack), 10893 le32_to_cpu(prptctrl->bt_mbx_info.a2dp.cnt_nack)); 10894 10895 seq_printf(m, 10896 "\n\r %-15s : wl_rfk[req:%d/go:%d/reject:%d/tout:%d/time:%dms]", 10897 "[RFK/LPS]", cx->cnt_wl[BTC_WCNT_RFK_REQ], 10898 cx->cnt_wl[BTC_WCNT_RFK_GO], 10899 cx->cnt_wl[BTC_WCNT_RFK_REJECT], 10900 cx->cnt_wl[BTC_WCNT_RFK_TIMEOUT], 10901 wl->rfk_info.proc_time); 10902 10903 seq_printf(m, ", bt_rfk[req:%d]", 10904 le16_to_cpu(prptctrl->bt_cnt[BTC_BCNT_RFK_REQ])); 10905 10906 seq_printf(m, ", AOAC[RF_on:%d/RF_off:%d]", 10907 le16_to_cpu(prptctrl->rpt_info.cnt_aoac_rf_on), 10908 le16_to_cpu(prptctrl->rpt_info.cnt_aoac_rf_off)); 10909 } else { 10910 seq_printf(m, 10911 "\n\r %-15s : h2c_cnt=%d(fail:%d), c2h_cnt=%d (lps=%d/rf_off=%d)", 10912 "[summary]", 10913 pfwinfo->cnt_h2c, pfwinfo->cnt_h2c_fail, 10914 pfwinfo->cnt_c2h, 10915 wl->status.map.lps, wl->status.map.rf_off); 10916 } 10917 10918 for (i = 0; i < BTC_NCNT_NUM; i++) 10919 cnt_sum += dm->cnt_notify[i]; 10920 10921 seq_printf(m, 10922 "\n\r %-15s : total=%d, show_coex_info=%d, power_on=%d, init_coex=%d, ", 10923 "[notify_cnt]", 10924 cnt_sum, cnt[BTC_NCNT_SHOW_COEX_INFO], 10925 cnt[BTC_NCNT_POWER_ON], cnt[BTC_NCNT_INIT_COEX]); 10926 10927 seq_printf(m, 10928 "power_off=%d, radio_state=%d, role_info=%d, wl_rfk=%d, wl_sta=%d", 10929 cnt[BTC_NCNT_POWER_OFF], cnt[BTC_NCNT_RADIO_STATE], 10930 cnt[BTC_NCNT_ROLE_INFO], cnt[BTC_NCNT_WL_RFK], 10931 cnt[BTC_NCNT_WL_STA]); 10932 10933 seq_printf(m, 10934 "\n\r %-15s : scan_start=%d, scan_finish=%d, switch_band=%d, switch_chbw=%d, special_pkt=%d, ", 10935 "[notify_cnt]", 10936 cnt[BTC_NCNT_SCAN_START], cnt[BTC_NCNT_SCAN_FINISH], 10937 cnt[BTC_NCNT_SWITCH_BAND], cnt[BTC_NCNT_SWITCH_CHBW], 10938 cnt[BTC_NCNT_SPECIAL_PACKET]); 10939 10940 seq_printf(m, "timer=%d, customerize=%d, hub_msg=%d, chg_fw=%d, send_cc=%d", 10941 cnt[BTC_NCNT_TIMER], cnt[BTC_NCNT_CUSTOMERIZE], 10942 rtwdev->btc.hubmsg_cnt, cnt[BTC_NCNT_RESUME_DL_FW], 10943 cnt[BTC_NCNT_COUNTRYCODE]); 10944 } 10945 10946 void rtw89_btc_dump_info(struct rtw89_dev *rtwdev, struct seq_file *m) 10947 { 10948 struct rtw89_fw_suit *fw_suit = &rtwdev->fw.normal; 10949 struct rtw89_btc *btc = &rtwdev->btc; 10950 const struct rtw89_btc_ver *ver = btc->ver; 10951 struct rtw89_btc_cx *cx = &btc->cx; 10952 struct rtw89_btc_bt_info *bt = &cx->bt; 10953 10954 seq_puts(m, "=========================================\n"); 10955 seq_printf(m, "WL FW / BT FW %d.%d.%d.%d / NA\n", 10956 fw_suit->major_ver, fw_suit->minor_ver, 10957 fw_suit->sub_ver, fw_suit->sub_idex); 10958 seq_printf(m, "manual %d\n", btc->manual_ctrl); 10959 10960 seq_puts(m, "=========================================\n"); 10961 10962 seq_printf(m, "\n\r %-15s : raw_data[%02x %02x %02x %02x %02x %02x] (type:%s/cnt:%d/same:%d)", 10963 "[bt_info]", 10964 bt->raw_info[2], bt->raw_info[3], 10965 bt->raw_info[4], bt->raw_info[5], 10966 bt->raw_info[6], bt->raw_info[7], 10967 bt->raw_info[0] == BTC_BTINFO_AUTO ? "auto" : "reply", 10968 cx->cnt_bt[BTC_BCNT_INFOUPDATE], 10969 cx->cnt_bt[BTC_BCNT_INFOSAME]); 10970 10971 seq_puts(m, "\n=========================================\n"); 10972 10973 _show_cx_info(rtwdev, m); 10974 _show_wl_info(rtwdev, m); 10975 _show_bt_info(rtwdev, m); 10976 _show_dm_info(rtwdev, m); 10977 _show_fw_dm_msg(rtwdev, m); 10978 10979 if (ver->fcxmreg == 1) 10980 _show_mreg_v1(rtwdev, m); 10981 else if (ver->fcxmreg == 2) 10982 _show_mreg_v2(rtwdev, m); 10983 else if (ver->fcxmreg == 7) 10984 _show_mreg_v7(rtwdev, m); 10985 10986 _show_gpio_dbg(rtwdev, m); 10987 10988 if (ver->fcxbtcrpt == 1) 10989 _show_summary_v1(rtwdev, m); 10990 else if (ver->fcxbtcrpt == 4) 10991 _show_summary_v4(rtwdev, m); 10992 else if (ver->fcxbtcrpt == 5) 10993 _show_summary_v5(rtwdev, m); 10994 else if (ver->fcxbtcrpt == 105) 10995 _show_summary_v105(rtwdev, m); 10996 else if (ver->fcxbtcrpt == 7) 10997 _show_summary_v7(rtwdev, m); 10998 else if (ver->fcxbtcrpt == 8) 10999 _show_summary_v8(rtwdev, m); 11000 } 11001 11002 void rtw89_coex_recognize_ver(struct rtw89_dev *rtwdev) 11003 { 11004 const struct rtw89_chip_info *chip = rtwdev->chip; 11005 struct rtw89_btc *btc = &rtwdev->btc; 11006 const struct rtw89_btc_ver *btc_ver_def; 11007 const struct rtw89_fw_suit *fw_suit; 11008 u32 suit_ver_code; 11009 int i; 11010 11011 fw_suit = rtw89_fw_suit_get(rtwdev, RTW89_FW_NORMAL); 11012 suit_ver_code = RTW89_FW_SUIT_VER_CODE(fw_suit); 11013 11014 for (i = 0; i < ARRAY_SIZE(rtw89_btc_ver_defs); i++) { 11015 btc_ver_def = &rtw89_btc_ver_defs[i]; 11016 11017 if (chip->chip_id != btc_ver_def->chip_id) 11018 continue; 11019 11020 if (suit_ver_code >= btc_ver_def->fw_ver_code) { 11021 btc->ver = btc_ver_def; 11022 goto out; 11023 } 11024 } 11025 11026 btc->ver = &rtw89_btc_ver_defs[RTW89_DEFAULT_BTC_VER_IDX]; 11027 11028 out: 11029 rtw89_debug(rtwdev, RTW89_DBG_BTC, "[BTC] use version def[%d] = 0x%08x\n", 11030 (int)(btc->ver - rtw89_btc_ver_defs), btc->ver->fw_ver_code); 11031 } 11032