1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_CAM_H__ 6 #define __RTW89_CAM_H__ 7 8 #include "core.h" 9 10 #define RTW89_SEC_CAM_LEN 20 11 12 #define RTW89_BSSID_MATCH_ALL GENMASK(5, 0) 13 #define RTW89_BSSID_MATCH_5_BYTES GENMASK(4, 0) 14 15 struct rtw89_h2c_addr_cam_v0 { 16 __le32 w0; 17 __le32 w1; 18 __le32 w2; 19 __le32 w3; 20 __le32 w4; 21 __le32 w5; 22 __le32 w6; 23 __le32 w7; 24 __le32 w8; 25 __le32 w9; 26 __le32 w10; 27 __le32 w11; 28 __le32 w12; 29 __le32 w13; 30 __le32 w14; 31 } __packed; 32 33 struct rtw89_h2c_addr_cam { 34 struct rtw89_h2c_addr_cam_v0 v0; 35 __le32 w15; 36 } __packed; 37 38 #define ADDR_CAM_W1_IDX GENMASK(7, 0) 39 #define ADDR_CAM_W1_OFFSET GENMASK(15, 8) 40 #define ADDR_CAM_W1_LEN GENMASK(23, 16) 41 #define ADDR_CAM_W1_V1_IDX GENMASK(9, 0) 42 #define ADDR_CAM_W1_V1_OFFSET GENMASK(23, 16) 43 #define ADDR_CAM_W1_V1_LEN GENMASK(31, 24) 44 #define ADDR_CAM_W2_VALID BIT(0) 45 #define ADDR_CAM_W2_NET_TYPE GENMASK(2, 1) 46 #define ADDR_CAM_W2_BCN_HIT_COND GENMASK(4, 3) 47 #define ADDR_CAM_W2_HIT_RULE GENMASK(6, 5) 48 #define ADDR_CAM_W2_BB_SEL BIT(7) 49 #define ADDR_CAM_W2_ADDR_MASK GENMASK(13, 8) 50 #define ADDR_CAM_W2_MASK_SEL GENMASK(15, 14) 51 #define ADDR_CAM_W2_SMA_HASH GENMASK(23, 16) 52 #define ADDR_CAM_W2_TMA_HASH GENMASK(31, 24) 53 #define ADDR_CAM_W3_BSSID_CAM_IDX GENMASK(5, 0) 54 #define ADDR_CAM_W4_SMA0 GENMASK(7, 0) 55 #define ADDR_CAM_W4_SMA1 GENMASK(15, 8) 56 #define ADDR_CAM_W4_SMA2 GENMASK(23, 16) 57 #define ADDR_CAM_W4_SMA3 GENMASK(31, 24) 58 #define ADDR_CAM_W5_SMA4 GENMASK(7, 0) 59 #define ADDR_CAM_W5_SMA5 GENMASK(15, 8) 60 #define ADDR_CAM_W5_TMA0 GENMASK(23, 16) 61 #define ADDR_CAM_W5_TMA1 GENMASK(31, 24) 62 #define ADDR_CAM_W6_TMA2 GENMASK(7, 0) 63 #define ADDR_CAM_W6_TMA3 GENMASK(15, 8) 64 #define ADDR_CAM_W6_TMA4 GENMASK(23, 16) 65 #define ADDR_CAM_W6_TMA5 GENMASK(31, 24) 66 #define ADDR_CAM_W8_MACID GENMASK(7, 0) 67 #define ADDR_CAM_W8_PORT_INT GENMASK(10, 8) 68 #define ADDR_CAM_W8_TSF_SYNC GENMASK(13, 11) 69 #define ADDR_CAM_W8_TF_TRS BIT(14) 70 #define ADDR_CAM_W8_LSIG_TXOP BIT(15) 71 #define ADDR_CAM_W8_TGT_IND GENMASK(26, 24) 72 #define ADDR_CAM_W8_FRM_TGT_IND GENMASK(29, 27) 73 #define ADDR_CAM_W8_V1_MACID GENMASK(9, 0) 74 #define ADDR_CAM_W8_V1_PORT_INT GENMASK(18, 16) 75 #define ADDR_CAM_W8_V1_TSF_SYNC GENMASK(21, 19) 76 #define ADDR_CAM_W8_V1_TF_TRS BIT(22) 77 #define ADDR_CAM_W8_V1_LSIG_TXOP BIT(23) 78 #define ADDR_CAM_W8_V1_TB_RANGING BIT(24) 79 #define ADDR_CAM_W8_V1_TB_SENSING BIT(25) 80 #define ADDR_CAM_W8_V1_SENS_EN BIT(26) 81 #define ADDR_CAM_W9_AID12 GENMASK(11, 0) 82 #define ADDR_CAM_W9_AID12_0 GENMASK(7, 0) 83 #define ADDR_CAM_W9_AID12_1 GENMASK(11, 8) 84 #define ADDR_CAM_W9_WOL_PATTERN BIT(12) 85 #define ADDR_CAM_W9_WOL_UC BIT(13) 86 #define ADDR_CAM_W9_WOL_MAGIC BIT(14) 87 #define ADDR_CAM_W9_WAPI BIT(15) 88 #define ADDR_CAM_W9_SEC_ENT_MODE GENMASK(17, 16) 89 #define ADDR_CAM_W9_SEC_ENT0_KEYID GENMASK(19, 18) 90 #define ADDR_CAM_W9_SEC_ENT1_KEYID GENMASK(21, 20) 91 #define ADDR_CAM_W9_SEC_ENT2_KEYID GENMASK(23, 22) 92 #define ADDR_CAM_W9_SEC_ENT3_KEYID GENMASK(25, 24) 93 #define ADDR_CAM_W9_SEC_ENT4_KEYID GENMASK(27, 26) 94 #define ADDR_CAM_W9_SEC_ENT5_KEYID GENMASK(29, 28) 95 #define ADDR_CAM_W9_SEC_ENT6_KEYID GENMASK(31, 30) 96 #define ADDR_CAM_W10_SEC_ENT_VALID GENMASK(7, 0) 97 #define ADDR_CAM_W10_SEC_ENT0 GENMASK(15, 8) 98 #define ADDR_CAM_W10_SEC_ENT1 GENMASK(23, 16) 99 #define ADDR_CAM_W10_SEC_ENT2 GENMASK(31, 24) 100 #define ADDR_CAM_W11_SEC_ENT3 GENMASK(7, 0) 101 #define ADDR_CAM_W11_SEC_ENT4 GENMASK(15, 8) 102 #define ADDR_CAM_W11_SEC_ENT5 GENMASK(23, 16) 103 #define ADDR_CAM_W11_SEC_ENT6 GENMASK(31, 24) 104 #define ADDR_CAM_W12_BSSID_IDX GENMASK(7, 0) 105 #define ADDR_CAM_W12_BSSID_OFFSET GENMASK(15, 8) 106 #define ADDR_CAM_W12_BSSID_LEN GENMASK(23, 16) 107 #define ADDR_CAM_W13_BSSID_VALID BIT(0) 108 #define ADDR_CAM_W13_BSSID_BB_SEL BIT(1) 109 #define ADDR_CAM_W13_BSSID_MASK GENMASK(7, 2) 110 #define ADDR_CAM_W13_BSSID_BSS_COLOR GENMASK(13, 8) 111 #define ADDR_CAM_W13_BSSID_BSSID0 GENMASK(23, 16) 112 #define ADDR_CAM_W13_BSSID_BSSID1 GENMASK(31, 24) 113 #define ADDR_CAM_W14_BSSID_BSSID2 GENMASK(7, 0) 114 #define ADDR_CAM_W14_BSSID_BSSID3 GENMASK(15, 8) 115 #define ADDR_CAM_W14_BSSID_BSSID4 GENMASK(23, 16) 116 #define ADDR_CAM_W14_BSSID_BSSID5 GENMASK(31, 24) 117 #define ADDR_CAM_W15_UPD_MODE GENMASK(2, 0) 118 119 struct rtw89_h2c_dctlinfo_ud_v1 { 120 __le32 c0; 121 __le32 w0; 122 __le32 w1; 123 __le32 w2; 124 __le32 w3; 125 __le32 w4; 126 __le32 w5; 127 __le32 w6; 128 __le32 w7; 129 __le32 m0; 130 __le32 m1; 131 __le32 m2; 132 __le32 m3; 133 __le32 m4; 134 __le32 m5; 135 __le32 m6; 136 __le32 m7; 137 } __packed; 138 139 #define DCTLINFO_V1_C0_MACID GENMASK(6, 0) 140 #define DCTLINFO_V1_C0_OP BIT(7) 141 142 #define DCTLINFO_V1_W0_QOS_FIELD_H GENMASK(7, 0) 143 #define DCTLINFO_V1_W0_HW_EXSEQ_MACID GENMASK(14, 8) 144 #define DCTLINFO_V1_W0_QOS_DATA BIT(15) 145 #define DCTLINFO_V1_W0_AES_IV_L GENMASK(31, 16) 146 #define DCTLINFO_V1_W0_ALL GENMASK(31, 0) 147 #define DCTLINFO_V1_W1_AES_IV_H GENMASK(31, 0) 148 #define DCTLINFO_V1_W1_ALL GENMASK(31, 0) 149 #define DCTLINFO_V1_W2_SEQ0 GENMASK(11, 0) 150 #define DCTLINFO_V1_W2_SEQ1 GENMASK(23, 12) 151 #define DCTLINFO_V1_W2_AMSDU_MAX_LEN GENMASK(26, 24) 152 #define DCTLINFO_V1_W2_STA_AMSDU_EN BIT(27) 153 #define DCTLINFO_V1_W2_CHKSUM_OFLD_EN BIT(28) 154 #define DCTLINFO_V1_W2_WITH_LLC BIT(29) 155 #define DCTLINFO_V1_W2_ALL GENMASK(29, 0) 156 #define DCTLINFO_V1_W3_SEQ2 GENMASK(11, 0) 157 #define DCTLINFO_V1_W3_SEQ3 GENMASK(23, 12) 158 #define DCTLINFO_V1_W3_TGT_IND GENMASK(27, 24) 159 #define DCTLINFO_V1_W3_TGT_IND_EN BIT(28) 160 #define DCTLINFO_V1_W3_HTC_LB GENMASK(31, 29) 161 #define DCTLINFO_V1_W3_ALL GENMASK(31, 0) 162 #define DCTLINFO_V1_W4_MHDR_LEN GENMASK(4, 0) 163 #define DCTLINFO_V1_W4_VLAN_TAG_VALID BIT(5) 164 #define DCTLINFO_V1_W4_VLAN_TAG_SEL GENMASK(7, 6) 165 #define DCTLINFO_V1_W4_HTC_ORDER BIT(8) 166 #define DCTLINFO_V1_W4_SEC_KEY_ID GENMASK(10, 9) 167 #define DCTLINFO_V1_W4_WAPI BIT(15) 168 #define DCTLINFO_V1_W4_SEC_ENT_MODE GENMASK(17, 16) 169 #define DCTLINFO_V1_W4_SEC_ENT0_KEYID GENMASK(19, 18) 170 #define DCTLINFO_V1_W4_SEC_ENT1_KEYID GENMASK(21, 20) 171 #define DCTLINFO_V1_W4_SEC_ENT2_KEYID GENMASK(23, 22) 172 #define DCTLINFO_V1_W4_SEC_ENT3_KEYID GENMASK(25, 24) 173 #define DCTLINFO_V1_W4_SEC_ENT4_KEYID GENMASK(27, 26) 174 #define DCTLINFO_V1_W4_SEC_ENT5_KEYID GENMASK(29, 28) 175 #define DCTLINFO_V1_W4_SEC_ENT6_KEYID GENMASK(31, 30) 176 #define DCTLINFO_V1_W4_ALL (GENMASK(31, 15) | GENMASK(10, 0)) 177 #define DCTLINFO_V1_W5_SEC_ENT_VALID GENMASK(7, 0) 178 #define DCTLINFO_V1_W5_SEC_ENT0 GENMASK(15, 8) 179 #define DCTLINFO_V1_W5_SEC_ENT1 GENMASK(23, 16) 180 #define DCTLINFO_V1_W5_SEC_ENT2 GENMASK(31, 24) 181 #define DCTLINFO_V1_W5_ALL GENMASK(31, 0) 182 #define DCTLINFO_V1_W6_SEC_ENT3 GENMASK(7, 0) 183 #define DCTLINFO_V1_W6_SEC_ENT4 GENMASK(15, 8) 184 #define DCTLINFO_V1_W6_SEC_ENT5 GENMASK(23, 16) 185 #define DCTLINFO_V1_W6_SEC_ENT6 GENMASK(31, 24) 186 #define DCTLINFO_V1_W6_ALL GENMASK(31, 0) 187 188 struct rtw89_h2c_dctlinfo_ud_v2 { 189 __le32 c0; 190 __le32 w0; 191 __le32 w1; 192 __le32 w2; 193 __le32 w3; 194 __le32 w4; 195 __le32 w5; 196 __le32 w6; 197 __le32 w7; 198 __le32 w8; 199 __le32 w9; 200 __le32 w10; 201 __le32 w11; 202 __le32 w12; 203 __le32 w13; 204 __le32 w14; 205 __le32 w15; 206 __le32 m0; 207 __le32 m1; 208 __le32 m2; 209 __le32 m3; 210 __le32 m4; 211 __le32 m5; 212 __le32 m6; 213 __le32 m7; 214 __le32 m8; 215 __le32 m9; 216 __le32 m10; 217 __le32 m11; 218 __le32 m12; 219 __le32 m13; 220 __le32 m14; 221 __le32 m15; 222 } __packed; 223 224 #define DCTLINFO_V2_C0_MACID GENMASK(6, 0) 225 #define DCTLINFO_V2_C0_OP BIT(7) 226 227 #define DCTLINFO_V2_W0_QOS_FIELD_H GENMASK(7, 0) 228 #define DCTLINFO_V2_W0_HW_EXSEQ_MACID GENMASK(14, 8) 229 #define DCTLINFO_V2_W0_QOS_DATA BIT(15) 230 #define DCTLINFO_V2_W0_AES_IV_L GENMASK(31, 16) 231 #define DCTLINFO_V2_W0_ALL GENMASK(31, 0) 232 #define DCTLINFO_V2_W1_AES_IV_H GENMASK(31, 0) 233 #define DCTLINFO_V2_W1_ALL GENMASK(31, 0) 234 #define DCTLINFO_V2_W2_SEQ0 GENMASK(11, 0) 235 #define DCTLINFO_V2_W2_SEQ1 GENMASK(23, 12) 236 #define DCTLINFO_V2_W2_AMSDU_MAX_LEN GENMASK(26, 24) 237 #define DCTLINFO_V2_W2_STA_AMSDU_EN BIT(27) 238 #define DCTLINFO_V2_W2_CHKSUM_OFLD_EN BIT(28) 239 #define DCTLINFO_V2_W2_WITH_LLC BIT(29) 240 #define DCTLINFO_V2_W2_NAT25_EN BIT(30) 241 #define DCTLINFO_V2_W2_IS_MLD BIT(31) 242 #define DCTLINFO_V2_W2_ALL GENMASK(31, 0) 243 #define DCTLINFO_V2_W3_SEQ2 GENMASK(11, 0) 244 #define DCTLINFO_V2_W3_SEQ3 GENMASK(23, 12) 245 #define DCTLINFO_V2_W3_TGT_IND GENMASK(27, 24) 246 #define DCTLINFO_V2_W3_TGT_IND_EN BIT(28) 247 #define DCTLINFO_V2_W3_HTC_LB GENMASK(31, 29) 248 #define DCTLINFO_V2_W3_ALL GENMASK(31, 0) 249 #define DCTLINFO_V2_W4_VLAN_TAG_SEL GENMASK(7, 5) 250 #define DCTLINFO_V2_W4_HTC_ORDER BIT(8) 251 #define DCTLINFO_V2_W4_SEC_KEY_ID GENMASK(10, 9) 252 #define DCTLINFO_V2_W4_VLAN_RX_DYNAMIC_PCP_EN BIT(11) 253 #define DCTLINFO_V2_W4_VLAN_RX_PKT_DROP BIT(12) 254 #define DCTLINFO_V2_W4_VLAN_RX_VALID BIT(13) 255 #define DCTLINFO_V2_W4_VLAN_TX_VALID BIT(14) 256 #define DCTLINFO_V2_W4_WAPI BIT(15) 257 #define DCTLINFO_V2_W4_SEC_ENT_MODE GENMASK(17, 16) 258 #define DCTLINFO_V2_W4_SEC_ENT0_KEYID GENMASK(19, 18) 259 #define DCTLINFO_V2_W4_SEC_ENT1_KEYID GENMASK(21, 20) 260 #define DCTLINFO_V2_W4_SEC_ENT2_KEYID GENMASK(23, 22) 261 #define DCTLINFO_V2_W4_SEC_ENT3_KEYID GENMASK(25, 24) 262 #define DCTLINFO_V2_W4_SEC_ENT4_KEYID GENMASK(27, 26) 263 #define DCTLINFO_V2_W4_SEC_ENT5_KEYID GENMASK(29, 28) 264 #define DCTLINFO_V2_W4_SEC_ENT6_KEYID GENMASK(31, 30) 265 #define DCTLINFO_V2_W4_ALL GENMASK(31, 5) 266 #define DCTLINFO_V2_W5_SEC_ENT7_KEYID GENMASK(1, 0) 267 #define DCTLINFO_V2_W5_SEC_ENT8_KEYID GENMASK(3, 2) 268 #define DCTLINFO_V2_W5_SEC_ENT_VALID_V1 GENMASK(23, 8) 269 #define DCTLINFO_V2_W5_SEC_ENT0_V1 GENMASK(31, 24) 270 #define DCTLINFO_V2_W5_ALL (GENMASK(31, 8) | GENMASK(3, 0)) 271 #define DCTLINFO_V2_W6_SEC_ENT1_V1 GENMASK(7, 0) 272 #define DCTLINFO_V2_W6_SEC_ENT2_V1 GENMASK(15, 8) 273 #define DCTLINFO_V2_W6_SEC_ENT3_V1 GENMASK(23, 16) 274 #define DCTLINFO_V2_W6_SEC_ENT4_V1 GENMASK(31, 24) 275 #define DCTLINFO_V2_W6_ALL GENMASK(31, 0) 276 #define DCTLINFO_V2_W7_SEC_ENT5_V1 GENMASK(7, 0) 277 #define DCTLINFO_V2_W7_SEC_ENT6_V1 GENMASK(15, 8) 278 #define DCTLINFO_V2_W7_SEC_ENT7 GENMASK(23, 16) 279 #define DCTLINFO_V2_W7_SEC_ENT8 GENMASK(31, 24) 280 #define DCTLINFO_V2_W7_ALL GENMASK(31, 0) 281 #define DCTLINFO_V2_W8_MLD_SMA_0 GENMASK(7, 0) 282 #define DCTLINFO_V2_W8_MLD_SMA_1 GENMASK(15, 8) 283 #define DCTLINFO_V2_W8_MLD_SMA_2 GENMASK(23, 16) 284 #define DCTLINFO_V2_W8_MLD_SMA_3 GENMASK(31, 24) 285 #define DCTLINFO_V2_W8_ALL GENMASK(31, 0) 286 #define DCTLINFO_V2_W9_MLD_SMA_4 GENMASK(7, 0) 287 #define DCTLINFO_V2_W9_MLD_SMA_5 GENMASK(15, 8) 288 #define DCTLINFO_V2_W9_MLD_TMA_0 GENMASK(23, 16) 289 #define DCTLINFO_V2_W9_MLD_TMA_1 GENMASK(31, 24) 290 #define DCTLINFO_V2_W9_ALL GENMASK(31, 0) 291 #define DCTLINFO_V2_W10_MLD_TMA_2 GENMASK(7, 0) 292 #define DCTLINFO_V2_W10_MLD_TMA_3 GENMASK(15, 8) 293 #define DCTLINFO_V2_W10_MLD_TMA_4 GENMASK(23, 16) 294 #define DCTLINFO_V2_W10_MLD_TMA_5 GENMASK(31, 24) 295 #define DCTLINFO_V2_W10_ALL GENMASK(31, 0) 296 #define DCTLINFO_V2_W11_MLD_BSSID_0 GENMASK(7, 0) 297 #define DCTLINFO_V2_W11_MLD_BSSID_1 GENMASK(15, 8) 298 #define DCTLINFO_V2_W11_MLD_BSSID_2 GENMASK(23, 16) 299 #define DCTLINFO_V2_W11_MLD_BSSID_3 GENMASK(31, 24) 300 #define DCTLINFO_V2_W11_ALL GENMASK(31, 0) 301 #define DCTLINFO_V2_W12_MLD_BSSID_4 GENMASK(7, 0) 302 #define DCTLINFO_V2_W12_MLD_BSSID_5 GENMASK(15, 8) 303 #define DCTLINFO_V2_W12_ALL GENMASK(15, 0) 304 305 struct rtw89_h2c_dctlinfo_ud_v3 { 306 __le32 c0; 307 __le32 w0; 308 __le32 w1; 309 __le32 w2; 310 __le32 w3; 311 __le32 w4; 312 __le32 w5; 313 __le32 w6; 314 __le32 w7; 315 __le32 w8; 316 __le32 w9; 317 __le32 w10; 318 __le32 w11; 319 __le32 w12; 320 __le32 w13; 321 __le32 w14; 322 __le32 w15; 323 __le32 m0; 324 __le32 m1; 325 __le32 m2; 326 __le32 m3; 327 __le32 m4; 328 __le32 m5; 329 __le32 m6; 330 __le32 m7; 331 __le32 m8; 332 __le32 m9; 333 __le32 m10; 334 __le32 m11; 335 __le32 m12; 336 __le32 m13; 337 __le32 m14; 338 __le32 m15; 339 } __packed; 340 341 #define DCTLINFO_V3_C0_MACID GENMASK(15, 0) 342 #define DCTLINFO_V3_C0_OP BIT(16) 343 344 #define DCTLINFO_V3_W0_QOS_FIELD_H GENMASK(7, 0) 345 #define DCTLINFO_V3_W0_HW_EXSEQ_MACID GENMASK(14, 8) 346 #define DCTLINFO_V3_W0_QOS_DATA BIT(15) 347 #define DCTLINFO_V3_W0_AES_IV_L GENMASK(31, 16) 348 #define DCTLINFO_V3_W0_ALL GENMASK(31, 0) 349 #define DCTLINFO_V3_W1_AES_IV_H GENMASK(31, 0) 350 #define DCTLINFO_V3_W1_ALL GENMASK(31, 0) 351 #define DCTLINFO_V3_W2_SEQ0 GENMASK(11, 0) 352 #define DCTLINFO_V3_W2_SEQ1 GENMASK(23, 12) 353 #define DCTLINFO_V3_W2_AMSDU_MAX_LEN GENMASK(26, 24) 354 #define DCTLINFO_V3_W2_STA_AMSDU_EN BIT(27) 355 #define DCTLINFO_V3_W2_CHKSUM_OFLD_EN BIT(28) 356 #define DCTLINFO_V3_W2_WITH_LLC BIT(29) 357 #define DCTLINFO_V3_W2_NAT25_EN BIT(30) 358 #define DCTLINFO_V3_W2_IS_MLD BIT(31) 359 #define DCTLINFO_V3_W2_ALL GENMASK(31, 0) 360 #define DCTLINFO_V3_W3_SEQ2 GENMASK(11, 0) 361 #define DCTLINFO_V3_W3_SEQ3 GENMASK(23, 12) 362 #define DCTLINFO_V3_W3_TGT_IND GENMASK(27, 24) 363 #define DCTLINFO_V3_W3_TGT_IND_EN BIT(28) 364 #define DCTLINFO_V3_W3_HTC_LB GENMASK(31, 29) 365 #define DCTLINFO_V3_W3_ALL GENMASK(31, 0) 366 #define DCTLINFO_V3_W4_VLAN_TAG_SEL GENMASK(7, 5) 367 #define DCTLINFO_V3_W4_HTC_ORDER BIT(8) 368 #define DCTLINFO_V3_W4_SEC_KEY_ID GENMASK(10, 9) 369 #define DCTLINFO_V3_W4_VLAN_RX_DYNAMIC_PCP_EN BIT(11) 370 #define DCTLINFO_V3_W4_VLAN_RX_PKT_DROP BIT(12) 371 #define DCTLINFO_V3_W4_VLAN_RX_VALID BIT(13) 372 #define DCTLINFO_V3_W4_VLAN_TX_VALID BIT(14) 373 #define DCTLINFO_V3_W4_WAPI BIT(15) 374 #define DCTLINFO_V3_W4_SEC_ENT_MODE GENMASK(17, 16) 375 #define DCTLINFO_V3_W4_SEC_ENT0_KEYID GENMASK(19, 18) 376 #define DCTLINFO_V3_W4_SEC_ENT1_KEYID GENMASK(21, 20) 377 #define DCTLINFO_V3_W4_SEC_ENT2_KEYID GENMASK(23, 22) 378 #define DCTLINFO_V3_W4_SEC_ENT3_KEYID GENMASK(25, 24) 379 #define DCTLINFO_V3_W4_SEC_ENT4_KEYID GENMASK(27, 26) 380 #define DCTLINFO_V3_W4_SEC_ENT5_KEYID GENMASK(29, 28) 381 #define DCTLINFO_V3_W4_SEC_ENT6_KEYID GENMASK(31, 30) 382 #define DCTLINFO_V3_W4_ALL GENMASK(31, 5) 383 #define DCTLINFO_V3_W5_SEC_ENT7_KEYID GENMASK(1, 0) 384 #define DCTLINFO_V3_W5_SEC_ENT8_KEYID GENMASK(3, 2) 385 #define DCTLINFO_V3_W5_SEC_ENT_VALID_V1 GENMASK(23, 8) 386 #define DCTLINFO_V3_W5_ALL (GENMASK(23, 8) | GENMASK(3, 0)) 387 #define DCTLINFO_V3_W6_SEC_ENT0_V2 GENMASK(8, 0) 388 #define DCTLINFO_V3_W6_SEC_ENT1_V2 GENMASK(18, 10) 389 #define DCTLINFO_V3_W6_SEC_ENT2_V2 GENMASK(28, 20) 390 #define DCTLINFO_V3_W6_ALL GENMASK(28, 0) 391 #define DCTLINFO_V3_W7_SEC_ENT3_V2 GENMASK(8, 0) 392 #define DCTLINFO_V3_W7_SEC_ENT4_V2 GENMASK(18, 10) 393 #define DCTLINFO_V3_W7_SEC_ENT5_V2 GENMASK(28, 20) 394 #define DCTLINFO_V3_W7_ALL GENMASK(28, 0) 395 #define DCTLINFO_V3_W8_SEC_ENT6_V2 GENMASK(8, 0) 396 #define DCTLINFO_V3_W8_SEC_ENT7_V1 GENMASK(18, 10) 397 #define DCTLINFO_V3_W8_SEC_ENT8_V1 GENMASK(28, 20) 398 #define DCTLINFO_V3_W8_ALL GENMASK(28, 0) 399 #define DCTLINFO_V3_W9_MLD_SMA_0_V2 GENMASK(7, 0) 400 #define DCTLINFO_V3_W9_MLD_SMA_1_V2 GENMASK(15, 8) 401 #define DCTLINFO_V3_W9_MLD_SMA_2_V2 GENMASK(23, 16) 402 #define DCTLINFO_V3_W9_MLD_SMA_3_V2 GENMASK(31, 24) 403 #define DCTLINFO_V3_W9_MLD_SMA_L_V2 GENMASK(31, 0) 404 #define DCTLINFO_V3_W9_ALL GENMASK(31, 0) 405 #define DCTLINFO_V3_W10_MLD_SMA_4_V2 GENMASK(7, 0) 406 #define DCTLINFO_V3_W10_MLD_SMA_5_V2 GENMASK(15, 8) 407 #define DCTLINFO_V3_W10_MLD_SMA_H_V2 GENMASK(15, 0) 408 #define DCTLINFO_V3_W10_MLD_TMA_0_V2 GENMASK(23, 16) 409 #define DCTLINFO_V3_W10_MLD_TMA_1_V2 GENMASK(31, 24) 410 #define DCTLINFO_V3_W10_MLD_TMA_L_V2 GENMASK(31, 16) 411 #define DCTLINFO_V3_W10_ALL GENMASK(31, 0) 412 #define DCTLINFO_V3_W11_MLD_TMA_2_V2 GENMASK(7, 0) 413 #define DCTLINFO_V3_W11_MLD_TMA_3_V2 GENMASK(15, 8) 414 #define DCTLINFO_V3_W11_MLD_TMA_4_V2 GENMASK(23, 16) 415 #define DCTLINFO_V3_W11_MLD_TMA_5_V2 GENMASK(31, 24) 416 #define DCTLINFO_V3_W11_MLD_TMA_H_V2 GENMASK(31, 0) 417 #define DCTLINFO_V3_W11_ALL GENMASK(31, 0) 418 #define DCTLINFO_V3_W12_MLD_TA_BSSID_0_V2 GENMASK(7, 0) 419 #define DCTLINFO_V3_W12_MLD_TA_BSSID_1_V2 GENMASK(15, 8) 420 #define DCTLINFO_V3_W12_MLD_TA_BSSID_2_V2 GENMASK(23, 16) 421 #define DCTLINFO_V3_W12_MLD_TA_BSSID_3_V2 GENMASK(31, 24) 422 #define DCTLINFO_V3_W12_MLD_TA_BSSID_L_V2 GENMASK(31, 0) 423 #define DCTLINFO_V3_W12_ALL GENMASK(31, 0) 424 #define DCTLINFO_V3_W13_MLD_TA_BSSID_4_V2 GENMASK(7, 0) 425 #define DCTLINFO_V3_W13_MLD_TA_BSSID_5_V2 GENMASK(15, 8) 426 #define DCTLINFO_V3_W13_MLD_TA_BSSID_H_V2 GENMASK(15, 0) 427 #define DCTLINFO_V3_W13_HW_EXSEQ_MACID_V1 GENMASK(24, 16) 428 #define DCTLINFO_V3_W13_ALL GENMASK(24, 0) 429 430 int rtw89_cam_init(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif); 431 void rtw89_cam_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif_link *vif); 432 int rtw89_cam_init_addr_cam(struct rtw89_dev *rtwdev, 433 struct rtw89_addr_cam_entry *addr_cam, 434 const struct rtw89_bssid_cam_entry *bssid_cam); 435 void rtw89_cam_deinit_addr_cam(struct rtw89_dev *rtwdev, 436 struct rtw89_addr_cam_entry *addr_cam); 437 int rtw89_cam_init_bssid_cam(struct rtw89_dev *rtwdev, 438 struct rtw89_vif_link *rtwvif_link, 439 struct rtw89_bssid_cam_entry *bssid_cam, 440 const u8 *bssid); 441 void rtw89_cam_deinit_bssid_cam(struct rtw89_dev *rtwdev, 442 struct rtw89_bssid_cam_entry *bssid_cam); 443 void rtw89_cam_fill_addr_cam_info(struct rtw89_dev *rtwdev, 444 struct rtw89_vif_link *rtwvif_link, 445 struct rtw89_sta_link *rtwsta_link, 446 const u8 *scan_mac_addr, 447 struct rtw89_h2c_addr_cam_v0 *h2c); 448 void rtw89_cam_fill_dctl_sec_cam_info_v1(struct rtw89_dev *rtwdev, 449 struct rtw89_vif_link *rtwvif_link, 450 struct rtw89_sta_link *rtwsta_link, 451 struct rtw89_h2c_dctlinfo_ud_v1 *h2c); 452 void rtw89_cam_fill_dctl_sec_cam_info_v2(struct rtw89_dev *rtwdev, 453 struct rtw89_vif_link *rtwvif_link, 454 struct rtw89_sta_link *rtwsta_link, 455 struct rtw89_h2c_dctlinfo_ud_v2 *h2c); 456 void rtw89_cam_fill_dctl_sec_cam_info_v3(struct rtw89_dev *rtwdev, 457 struct rtw89_vif_link *rtwvif_link, 458 struct rtw89_sta_link *rtwsta_link, 459 struct rtw89_h2c_dctlinfo_ud_v3 *h2c); 460 int rtw89_cam_fill_bssid_cam_info(struct rtw89_dev *rtwdev, 461 struct rtw89_vif_link *rtwvif_link, 462 struct rtw89_sta_link *rtwsta_link, 463 struct rtw89_h2c_addr_cam_v0 *h2c); 464 int rtw89_cam_sec_key_add(struct rtw89_dev *rtwdev, 465 struct ieee80211_vif *vif, 466 struct ieee80211_sta *sta, 467 struct ieee80211_key_conf *key); 468 int rtw89_cam_sec_key_del(struct rtw89_dev *rtwdev, 469 struct ieee80211_vif *vif, 470 struct ieee80211_sta *sta, 471 struct ieee80211_key_conf *key, 472 bool inform_fw); 473 void rtw89_cam_bssid_changed(struct rtw89_dev *rtwdev, 474 struct rtw89_vif_link *rtwvif_link); 475 void rtw89_cam_reset_keys(struct rtw89_dev *rtwdev); 476 int rtw89_cam_attach_link_sec_cam(struct rtw89_dev *rtwdev, 477 struct rtw89_vif_link *rtwvif_link, 478 struct rtw89_sta_link *rtwsta_link, 479 u8 sec_cam_idx); 480 481 #endif 482