1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW8822C_H__ 6 #define __RTW8822C_H__ 7 8 #include <asm/byteorder.h> 9 10 struct rtw8822cu_efuse { 11 u8 res0[0x30]; /* 0x120 */ 12 u8 vid[2]; /* 0x150 */ 13 u8 pid[2]; 14 u8 res1[3]; 15 u8 mac_addr[ETH_ALEN]; /* 0x157 */ 16 u8 res2[0x3d]; 17 }; 18 19 struct rtw8822cs_efuse { 20 u8 res0[0x4a]; /* 0x120 */ 21 u8 mac_addr[ETH_ALEN]; /* 0x16a */ 22 } __packed; 23 24 struct rtw8822ce_efuse { 25 u8 mac_addr[ETH_ALEN]; /* 0x120 */ 26 u8 vender_id[2]; 27 u8 device_id[2]; 28 u8 sub_vender_id[2]; 29 u8 sub_device_id[2]; 30 u8 pmc[2]; 31 u8 exp_device_cap[2]; 32 u8 msi_cap; 33 u8 ltr_cap; /* 0x133 */ 34 u8 exp_link_control[2]; 35 u8 link_cap[4]; 36 u8 link_control[2]; 37 u8 serial_number[8]; 38 u8 res0:2; /* 0x144 */ 39 u8 ltr_en:1; 40 u8 res1:2; 41 u8 obff:2; 42 u8 res2:3; 43 u8 obff_cap:2; 44 u8 res3:4; 45 u8 class_code[3]; 46 u8 res4; 47 u8 pci_pm_L1_2_supp:1; 48 u8 pci_pm_L1_1_supp:1; 49 u8 aspm_pm_L1_2_supp:1; 50 u8 aspm_pm_L1_1_supp:1; 51 u8 L1_pm_substates_supp:1; 52 u8 res5:3; 53 u8 port_common_mode_restore_time; 54 u8 port_t_power_on_scale:2; 55 u8 res6:1; 56 u8 port_t_power_on_value:5; 57 u8 res7; 58 }; 59 60 struct rtw8822c_efuse { 61 __le16 rtl_id; 62 u8 res0[4]; 63 u8 usb_mode; 64 u8 res1[0x09]; 65 66 /* power index for four RF paths */ 67 struct rtw_txpwr_idx txpwr_idx_table[4]; 68 69 u8 channel_plan; /* 0xb8 */ 70 u8 xtal_k; 71 u8 res2; 72 u8 iqk_lck; 73 u8 res3[5]; /* 0xbc */ 74 u8 rf_board_option; 75 u8 rf_feature_option; 76 u8 rf_bt_setting; 77 u8 eeprom_version; 78 u8 eeprom_customer_id; 79 u8 tx_bb_swing_setting_2g; 80 u8 tx_bb_swing_setting_5g; 81 u8 tx_pwr_calibrate_rate; 82 u8 rf_antenna_option; /* 0xc9 */ 83 u8 rfe_option; 84 u8 country_code[2]; 85 u8 res4[3]; 86 u8 path_a_thermal; /* 0xd0 */ 87 u8 path_b_thermal; 88 u8 res5[2]; 89 u8 rx_gain_gap_2g_ofdm; 90 u8 res6; 91 u8 rx_gain_gap_2g_cck; 92 u8 res7; 93 u8 rx_gain_gap_5gl; 94 u8 res8; 95 u8 rx_gain_gap_5gm; 96 u8 res9; 97 u8 rx_gain_gap_5gh; 98 u8 res10; 99 u8 res11[0x42]; 100 union { 101 struct rtw8822ce_efuse e; 102 struct rtw8822cu_efuse u; 103 struct rtw8822cs_efuse s; 104 }; 105 }; 106 107 enum rtw8822c_dpk_agc_phase { 108 RTW_DPK_GAIN_CHECK, 109 RTW_DPK_GAIN_LARGE, 110 RTW_DPK_GAIN_LESS, 111 RTW_DPK_GL_LARGE, 112 RTW_DPK_GL_LESS, 113 RTW_DPK_LOSS_CHECK, 114 RTW_DPK_AGC_OUT, 115 }; 116 117 enum rtw8822c_dpk_one_shot_action { 118 RTW_DPK_CAL_PWR, 119 RTW_DPK_GAIN_LOSS, 120 RTW_DPK_DO_DPK, 121 RTW_DPK_DPK_ON, 122 RTW_DPK_DAGC, 123 RTW_DPK_ACTION_MAX 124 }; 125 126 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev, 127 const struct rtw_table *tbl); 128 129 extern const struct rtw_chip_info rtw8822c_hw_spec; 130 131 #define RTW_DECL_TABLE_DPK(name) \ 132 const struct rtw_table name ## _tbl = { \ 133 .data = name, \ 134 .size = ARRAY_SIZE(name), \ 135 .parse = rtw8822c_parse_tbl_dpk, \ 136 } 137 138 #define DACK_PATH_8822C 2 139 #define DACK_REG_8822C 16 140 #define DACK_RF_8822C 1 141 #define DACK_SN_8822C 100 142 143 /* phy status page0 */ 144 #define GET_PHY_STAT_P0_PWDB_A(phy_stat) \ 145 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 146 #define GET_PHY_STAT_P0_PWDB_B(phy_stat) \ 147 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0)) 148 #define GET_PHY_STAT_P0_GAIN_A(phy_stat) \ 149 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(21, 16)) 150 #define GET_PHY_STAT_P0_CHANNEL(phy_stat) \ 151 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16)) 152 #define GET_PHY_STAT_P0_GAIN_B(phy_stat) \ 153 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(29, 24)) 154 155 /* phy status page1 */ 156 #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \ 157 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 158 #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \ 159 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16)) 160 #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \ 161 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8)) 162 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \ 163 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12)) 164 #define GET_PHY_STAT_P1_CHANNEL(phy_stat) \ 165 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(23, 16)) 166 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \ 167 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0)) 168 #define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \ 169 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8)) 170 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \ 171 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0)) 172 #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \ 173 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8)) 174 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \ 175 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0)) 176 #define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \ 177 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8)) 178 179 #define RTW8822C_EDCCA_MAX 0x7f 180 #define REG_ANAPARLDO_POW_MAC 0x0029 181 #define BIT_LDOE25_PON BIT(0) 182 #define XCAP_MASK GENMASK(6, 0) 183 #define CFO_TRK_ENABLE_TH 20 184 #define CFO_TRK_STOP_TH 10 185 #define CFO_TRK_ADJ_TH 10 186 187 #define REG_TXDFIR0 0x808 188 #define REG_DFIRBW 0x810 189 #define REG_ANTMAP0 0x820 190 #define BIT_ANT_PATH GENMASK(1, 0) 191 #define REG_ANTMAP 0x824 192 #define REG_EDCCA_DECISION 0x844 193 #define BIT_EDCCA_OPTION GENMASK(30, 29) 194 #define REG_DYMPRITH 0x86c 195 #define REG_DYMENTH0 0x870 196 #define REG_DYMENTH 0x874 197 #define REG_SBD 0x88c 198 #define BITS_SUBTUNE GENMASK(15, 12) 199 #define REG_DYMTHMIN 0x8a4 200 201 #define REG_TXBWCTL 0x9b0 202 #define REG_TXCLK 0x9b4 203 204 #define REG_SCOTRK 0xc30 205 #define REG_MRCM 0xc38 206 #define REG_AGCSWSH 0xc44 207 #define REG_ANTWTPD 0xc54 208 #define REG_PT_CHSMO 0xcbc 209 #define BIT_PT_OPT BIT(21) 210 211 #define REG_ORITXCODE 0x1800 212 #define BIT_PATH_EN BIT(31) 213 #define REG_3WIRE 0x180c 214 #define BIT_DIS_SHARERX_TXGAT BIT(27) 215 #define BIT_3WIRE_TX_EN BIT(0) 216 #define BIT_3WIRE_RX_EN BIT(1) 217 #define BIT_3WIRE_EN GENMASK(1, 0) 218 #define BIT_3WIRE_PI_ON BIT(28) 219 #define REG_ANAPAR_A 0x1830 220 #define BIT_ANAPAR_UPDATE BIT(29) 221 #define REG_RFTXEN_GCK_A 0x1864 222 #define BIT_RFTXEN_GCK_FORCE_ON BIT(31) 223 #define REG_DIS_SHARE_RX_A 0x186c 224 #define BIT_TX_SCALE_0DB BIT(7) 225 #define REG_RXAGCCTL0 0x18ac 226 #define BITS_RXAGC_CCK GENMASK(15, 12) 227 #define BITS_RXAGC_OFDM GENMASK(8, 4) 228 #define REG_DCKA_I_0 0x18bc 229 #define REG_DCKA_I_1 0x18c0 230 #define REG_DCKA_Q_0 0x18d8 231 #define REG_DCKA_Q_1 0x18dc 232 233 #define REG_CCKSB 0x1a00 234 #define BIT_BBMODE GENMASK(2, 1) 235 #define REG_RXCCKSEL 0x1a04 236 #define REG_BGCTRL 0x1a14 237 #define BITS_RX_IQ_WEIGHT (BIT(8) | BIT(9)) 238 #define REG_TXF0 0x1a20 239 #define REG_TXF1 0x1a24 240 #define REG_TXF2 0x1a28 241 #define REG_CCANRX 0x1a2c 242 #define BIT_CCK_FA_RST (BIT(14) | BIT(15)) 243 #define BIT_OFDM_FA_RST (BIT(12) | BIT(13)) 244 #define REG_CCK_FACNT 0x1a5c 245 #define REG_CCKTXONLY 0x1a80 246 #define BIT_BB_CCK_CHECK_EN BIT(18) 247 #define REG_TXF3 0x1a98 248 #define REG_TXF4 0x1a9c 249 #define REG_TXF5 0x1aa0 250 #define REG_TXF6 0x1aac 251 #define REG_TXF7 0x1ab0 252 #define REG_CCK_SOURCE 0x1abc 253 #define BIT_NBI_EN BIT(30) 254 255 #define REG_NCTL0 0x1b00 256 #define BIT_SEL_PATH GENMASK(2, 1) 257 #define BIT_SUBPAGE GENMASK(3, 0) 258 #define REG_DPD_CTL0_S0 0x1b04 259 #define BIT_GS_PWSF GENMASK(27, 0) 260 #define REG_DPD_CTL1_S0 0x1b08 261 #define BIT_DPD_EN BIT(31) 262 #define BIT_PS_EN BIT(7) 263 #define REG_IQKSTAT 0x1b10 264 #define REG_IQK_CTL1 0x1b20 265 #define BIT_TX_CFIR GENMASK(31, 30) 266 #define BIT_CFIR_EN GENMASK(26, 24) 267 #define BIT_BYPASS_DPD BIT(25) 268 269 #define REG_TX_TONE_IDX 0x1b2c 270 #define REG_DPD_LUT0 0x1b44 271 #define BIT_GLOSS_DB GENMASK(14, 12) 272 #define REG_DPD_CTL0_S1 0x1b5c 273 #define REG_DPD_CTL1_S1 0x1b60 274 #define REG_DPD_AGC 0x1b67 275 #define REG_TABLE_SEL 0x1b98 276 #define BIT_I_GAIN GENMASK(19, 16) 277 #define BIT_GAIN_RST BIT(15) 278 #define BIT_Q_GAIN_SEL GENMASK(14, 12) 279 #define BIT_Q_GAIN GENMASK(11, 0) 280 #define REG_TX_GAIN_SET 0x1b9c 281 #define BIT_GAPK_RPT_IDX GENMASK(11, 8) 282 #define REG_DPD_CTL0 0x1bb4 283 #define REG_SINGLE_TONE_SW 0x1bb8 284 #define BIT_IRQ_TEST_MODE BIT(20) 285 #define REG_R_CONFIG 0x1bcc 286 #define BIT_INNER_LB BIT(21) 287 #define BIT_IQ_SWITCH GENMASK(5, 0) 288 #define BIT_2G_SWING 0x2d 289 #define BIT_5G_SWING 0x36 290 #define REG_RXSRAM_CTL 0x1bd4 291 #define BIT_RPT_EN BIT(21) 292 #define BIT_RPT_SEL GENMASK(20, 16) 293 #define BIT_DPD_CLK GENMASK(7, 4) 294 #define REG_DPD_CTL11 0x1be4 295 #define REG_DPD_CTL12 0x1be8 296 #define REG_DPD_CTL15 0x1bf4 297 #define REG_DPD_CTL16 0x1bf8 298 #define REG_STAT_RPT 0x1bfc 299 #define BIT_RPT_DGAIN GENMASK(27, 16) 300 #define BIT_GAPK_RPT0 GENMASK(3, 0) 301 #define BIT_GAPK_RPT1 GENMASK(7, 4) 302 #define BIT_GAPK_RPT2 GENMASK(11, 8) 303 #define BIT_GAPK_RPT3 GENMASK(15, 12) 304 #define BIT_GAPK_RPT4 GENMASK(19, 16) 305 #define BIT_GAPK_RPT5 GENMASK(23, 20) 306 #define BIT_GAPK_RPT6 GENMASK(27, 24) 307 #define BIT_GAPK_RPT7 GENMASK(31, 28) 308 309 #define REG_TXANT 0x1c28 310 #define REG_IQK_CTRL 0x1c38 311 #define REG_ENCCK 0x1c3c 312 #define BIT_CCK_BLK_EN BIT(1) 313 #define BIT_CCK_OFDM_BLK_EN (BIT(0) | BIT(1)) 314 #define REG_CCAMSK 0x1c80 315 #define REG_RSTB 0x1c90 316 #define BIT_RSTB_3WIRE BIT(8) 317 #define REG_CH_DELAY_EXTR2 0x1cd0 318 #define BIT_TST_IQK2SET_SRC BIT(31) 319 #define BIT_EN_IOQ_IQK_DPK BIT(30) 320 #define BIT_IQK_DPK_RESET_SRC BIT(29) 321 #define BIT_IQK_DPK_CLOCK_SRC BIT(28) 322 323 #define REG_RX_BREAK 0x1d2c 324 #define BIT_COM_RX_GCK_EN BIT(31) 325 #define REG_RXFNCTL 0x1d30 326 #define REG_CCA_OFF 0x1d58 327 #define BIT_CCA_ON_BY_PW GENMASK(11, 3) 328 #define REG_RXIGI 0x1d70 329 330 #define REG_ENFN 0x1e24 331 #define BIT_IQK_DPK_EN BIT(17) 332 #define REG_TXANTSEG 0x1e28 333 #define BIT_ANTSEG GENMASK(3, 0) 334 #define REG_TXLGMAP 0x1e2c 335 #define REG_CCKPATH 0x1e5c 336 #define REG_TX_FIFO 0x1e70 337 #define BIT_STOP_TX GENMASK(3, 0) 338 #define REG_CNT_CTRL 0x1eb4 339 #define BIT_ALL_CNT_RST BIT(25) 340 341 #define REG_OFDM_FACNT 0x2d00 342 #define REG_OFDM_FACNT1 0x2d04 343 #define REG_OFDM_FACNT2 0x2d08 344 #define REG_OFDM_FACNT3 0x2d0c 345 #define REG_OFDM_FACNT4 0x2d10 346 #define REG_OFDM_FACNT5 0x2d20 347 #define REG_RPT_CIP 0x2d9c 348 #define BIT_RPT_CIP_STATUS GENMASK(7, 0) 349 #define REG_OFDM_TXCNT 0x2de0 350 351 #define REG_ORITXCODE2 0x4100 352 #define REG_3WIRE2 0x410c 353 #define REG_ANAPAR_B 0x4130 354 #define REG_RFTXEN_GCK_B 0x4164 355 #define REG_DIS_SHARE_RX_B 0x416c 356 #define BIT_EXT_TIA_BW BIT(1) 357 #define REG_RXAGCCTL 0x41ac 358 #define REG_DCKB_I_0 0x41bc 359 #define REG_DCKB_I_1 0x41c0 360 #define REG_DCKB_Q_0 0x41d8 361 #define REG_DCKB_Q_1 0x41dc 362 363 #define RF_MODE_TRXAGC 0x00 364 #define BIT_RF_MODE GENMASK(19, 16) 365 #define BIT_RXAGC GENMASK(9, 5) 366 #define BIT_TXAGC GENMASK(4, 0) 367 #define RF_RXAGC_OFFSET 0x19 368 #define RF_BW_TRXBB 0x1a 369 #define BIT_TX_CCK_IND BIT(16) 370 #define BIT_BW_TXBB GENMASK(14, 12) 371 #define BIT_BW_RXBB GENMASK(11, 10) 372 #define BIT_DBG_CCK_CCA BIT(1) 373 #define RF_TX_GAIN_OFFSET 0x55 374 #define BIT_BB_GAIN GENMASK(18, 14) 375 #define BIT_RF_GAIN GENMASK(4, 2) 376 #define RF_TX_GAIN 0x56 377 #define BIT_GAIN_TXBB GENMASK(4, 0) 378 #define RF_IDAC 0x58 379 #define BIT_TX_MODE GENMASK(19, 8) 380 #define RF_TX_RESULT 0x5f 381 #define BIT_GAIN_TX_PAD_H GENMASK(11, 8) 382 #define BIT_GAIN_TX_PAD_L GENMASK(7, 4) 383 #define RF_PA 0x60 384 #define RF_PABIAS_2G_MASK GENMASK(15, 12) 385 #define RF_PABIAS_5G_MASK GENMASK(19, 16) 386 #define RF_TXA_LB_SW 0x63 387 #define BIT_TXA_LB_ATT GENMASK(15, 14) 388 #define BIT_LB_SW GENMASK(13, 12) 389 #define BIT_LB_ATT GENMASK(4, 2) 390 #define RF_RXG_GAIN 0x87 391 #define BIT_RXG_GAIN BIT(18) 392 #define RF_RXA_MIX_GAIN 0x8a 393 #define BIT_RXA_MIX_GAIN GENMASK(4, 3) 394 #define RF_EXT_TIA_BW 0x8f 395 #define BIT_PW_EXT_TIA BIT(1) 396 #define RF_DIS_BYPASS_TXBB 0x9e 397 #define BIT_TXBB BIT(10) 398 #define BIT_TIA_BYPASS BIT(5) 399 #define RF_DEBUG 0xde 400 #define BIT_DE_PWR_TRIM BIT(19) 401 #define BIT_DE_TX_GAIN BIT(16) 402 #define BIT_DE_TRXBW BIT(2) 403 404 #define PPG_THERMAL_B 0x1b0 405 #define RF_THEMAL_MASK GENMASK(19, 16) 406 #define PPG_2GH_TXAB 0x1d2 407 #define PPG_2G_A_MASK GENMASK(3, 0) 408 #define PPG_2G_B_MASK GENMASK(7, 4) 409 #define PPG_2GL_TXAB 0x1d4 410 #define PPG_PABIAS_2GB 0x1d5 411 #define PPG_PABIAS_2GA 0x1d6 412 #define PPG_PABIAS_MASK GENMASK(3, 0) 413 #define PPG_PABIAS_5GB 0x1d7 414 #define PPG_PABIAS_5GA 0x1d8 415 #define PPG_5G_MASK GENMASK(4, 0) 416 #define PPG_5GH1_TXB 0x1db 417 #define PPG_5GH1_TXA 0x1dc 418 #define PPG_5GM2_TXB 0x1df 419 #define PPG_5GM2_TXA 0x1e0 420 #define PPG_5GM1_TXB 0x1e3 421 #define PPG_5GM1_TXA 0x1e4 422 #define PPG_5GL2_TXB 0x1e7 423 #define PPG_5GL2_TXA 0x1e8 424 #define PPG_5GL1_TXB 0x1eb 425 #define PPG_5GL1_TXA 0x1ec 426 #define PPG_2GM_TXAB 0x1ee 427 #define PPG_THERMAL_A 0x1ef 428 #endif 429