1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include "main.h" 6 #include "coex.h" 7 #include "fw.h" 8 #include "tx.h" 9 #include "rx.h" 10 #include "phy.h" 11 #include "rtw8822c.h" 12 #include "rtw8822c_table.h" 13 #include "mac.h" 14 #include "reg.h" 15 #include "debug.h" 16 #include "util.h" 17 #include "bf.h" 18 #include "efuse.h" 19 20 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 21 u8 rx_path, bool is_tx2_path); 22 23 static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8822c_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 30 { 31 struct rtw_efuse *efuse = &rtwdev->efuse; 32 struct rtw8822c_efuse *map; 33 int i; 34 35 map = (struct rtw8822c_efuse *)log_map; 36 37 efuse->rfe_option = map->rfe_option; 38 efuse->rf_board_option = map->rf_board_option; 39 efuse->crystal_cap = map->xtal_k; 40 efuse->channel_plan = map->channel_plan; 41 efuse->country_code[0] = map->country_code[0]; 42 efuse->country_code[1] = map->country_code[1]; 43 efuse->bt_setting = map->rf_bt_setting; 44 efuse->regd = map->rf_board_option & 0x7; 45 efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal; 46 efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal; 47 efuse->thermal_meter_k = 48 (map->path_a_thermal + map->path_b_thermal) >> 1; 49 efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf; 50 51 for (i = 0; i < 4; i++) 52 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 53 54 switch (rtw_hci_type(rtwdev)) { 55 case RTW_HCI_TYPE_PCIE: 56 rtw8822ce_efuse_parsing(efuse, map); 57 break; 58 default: 59 /* unsupported now */ 60 return -ENOTSUPP; 61 } 62 63 return 0; 64 } 65 66 static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre) 67 { 68 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 69 rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON); 70 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN); 71 rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON); 72 73 if (pre) 74 rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 75 else 76 rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN); 77 } 78 79 static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev, 80 struct rtw_backup_info *backup, 81 struct rtw_backup_info *backup_rf) 82 { 83 u32 path, i; 84 u32 val; 85 u32 reg; 86 u32 rf_addr[DACK_RF_8822C] = {0x8f}; 87 u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110, 88 0x1c3c, 0x1c24, 0x1d70, 0x9b4, 89 0x1a00, 0x1a14, 0x1d58, 0x1c38, 90 0x1e24, 0x1e28, 0x1860, 0x4160}; 91 92 for (i = 0; i < DACK_REG_8822C; i++) { 93 backup[i].len = 4; 94 backup[i].reg = addrs[i]; 95 backup[i].val = rtw_read32(rtwdev, addrs[i]); 96 } 97 98 for (path = 0; path < DACK_PATH_8822C; path++) { 99 for (i = 0; i < DACK_RF_8822C; i++) { 100 reg = rf_addr[i]; 101 val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK); 102 backup_rf[path * i + i].reg = reg; 103 backup_rf[path * i + i].val = val; 104 } 105 } 106 } 107 108 static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev, 109 struct rtw_backup_info *backup, 110 struct rtw_backup_info *backup_rf) 111 { 112 u32 path, i; 113 u32 val; 114 u32 reg; 115 116 rtw_restore_reg(rtwdev, backup, DACK_REG_8822C); 117 118 for (path = 0; path < DACK_PATH_8822C; path++) { 119 for (i = 0; i < DACK_RF_8822C; i++) { 120 val = backup_rf[path * i + i].val; 121 reg = backup_rf[path * i + i].reg; 122 rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val); 123 } 124 } 125 } 126 127 static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value, 128 u32 *min, u32 *max) 129 { 130 if (value >= 0x200) { 131 if (*min >= 0x200) { 132 if (*min > value) 133 *min = value; 134 } else { 135 *min = value; 136 } 137 if (*max >= 0x200) { 138 if (*max < value) 139 *max = value; 140 } 141 } else { 142 if (*min < 0x200) { 143 if (*min > value) 144 *min = value; 145 } 146 147 if (*max >= 0x200) { 148 *max = value; 149 } else { 150 if (*max < value) 151 *max = value; 152 } 153 } 154 } 155 156 static void swap_u32(u32 *v1, u32 *v2) 157 { 158 u32 tmp; 159 160 tmp = *v1; 161 *v1 = *v2; 162 *v2 = tmp; 163 } 164 165 static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2) 166 { 167 if (*v1 >= 0x200 && *v2 >= 0x200) { 168 if (*v1 > *v2) 169 swap_u32(v1, v2); 170 } else if (*v1 < 0x200 && *v2 < 0x200) { 171 if (*v1 > *v2) 172 swap_u32(v1, v2); 173 } else if (*v1 < 0x200 && *v2 >= 0x200) { 174 swap_u32(v1, v2); 175 } 176 } 177 178 static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 179 { 180 u32 i, j; 181 182 for (i = 0; i < DACK_SN_8822C - 1; i++) { 183 for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) { 184 __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]); 185 __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]); 186 } 187 } 188 } 189 190 static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val) 191 { 192 u32 p, m, t, i; 193 194 m = 0; 195 p = 0; 196 for (i = 10; i < DACK_SN_8822C - 10; i++) { 197 if (vec[i] > 0x200) 198 m = (0x400 - vec[i]) + m; 199 else 200 p = vec[i] + p; 201 } 202 203 if (p > m) { 204 t = p - m; 205 t = t / (DACK_SN_8822C - 20); 206 } else { 207 t = m - p; 208 t = t / (DACK_SN_8822C - 20); 209 if (t != 0x0) 210 t = 0x400 - t; 211 } 212 213 *val = t; 214 } 215 216 static u32 rtw8822c_get_path_write_addr(u8 path) 217 { 218 u32 base_addr; 219 220 switch (path) { 221 case RF_PATH_A: 222 base_addr = 0x1800; 223 break; 224 case RF_PATH_B: 225 base_addr = 0x4100; 226 break; 227 default: 228 WARN_ON(1); 229 return -1; 230 } 231 232 return base_addr; 233 } 234 235 static u32 rtw8822c_get_path_read_addr(u8 path) 236 { 237 u32 base_addr; 238 239 switch (path) { 240 case RF_PATH_A: 241 base_addr = 0x2800; 242 break; 243 case RF_PATH_B: 244 base_addr = 0x4500; 245 break; 246 default: 247 WARN_ON(1); 248 return -1; 249 } 250 251 return base_addr; 252 } 253 254 static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value) 255 { 256 bool ret = true; 257 258 if ((value >= 0x200 && (0x400 - value) > 0x64) || 259 (value < 0x200 && value > 0x64)) { 260 ret = false; 261 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n"); 262 } 263 264 return ret; 265 } 266 267 static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv) 268 { 269 u32 temp; 270 int i = 0, cnt = 0; 271 272 while (i < DACK_SN_8822C && cnt < 10000) { 273 cnt++; 274 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 275 iv[i] = (temp & 0x3ff000) >> 12; 276 qv[i] = temp & 0x3ff; 277 278 if (rtw8822c_dac_iq_check(rtwdev, iv[i]) && 279 rtw8822c_dac_iq_check(rtwdev, qv[i])) 280 i++; 281 } 282 } 283 284 static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev, 285 u32 *iv, u32 *qv, 286 u32 *i_value, u32 *q_value) 287 { 288 u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0; 289 u32 i_delta, q_delta; 290 u32 temp; 291 int i, cnt = 0; 292 293 do { 294 i_min = iv[0]; 295 i_max = iv[0]; 296 q_min = qv[0]; 297 q_max = qv[0]; 298 for (i = 0; i < DACK_SN_8822C; i++) { 299 rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max); 300 rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max); 301 } 302 303 if (i_max < 0x200 && i_min < 0x200) 304 i_delta = i_max - i_min; 305 else if (i_max >= 0x200 && i_min >= 0x200) 306 i_delta = i_max - i_min; 307 else 308 i_delta = i_max + (0x400 - i_min); 309 310 if (q_max < 0x200 && q_min < 0x200) 311 q_delta = q_max - q_min; 312 else if (q_max >= 0x200 && q_min >= 0x200) 313 q_delta = q_max - q_min; 314 else 315 q_delta = q_max + (0x400 - q_min); 316 317 rtw_dbg(rtwdev, RTW_DBG_RFK, 318 "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n", 319 i_min, i_max, i_delta); 320 rtw_dbg(rtwdev, RTW_DBG_RFK, 321 "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n", 322 q_min, q_max, q_delta); 323 324 rtw8822c_dac_iq_sort(rtwdev, iv, qv); 325 326 if (i_delta > 5 || q_delta > 5) { 327 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 328 iv[0] = (temp & 0x3ff000) >> 12; 329 qv[0] = temp & 0x3ff; 330 temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff); 331 iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12; 332 qv[DACK_SN_8822C - 1] = temp & 0x3ff; 333 } else { 334 break; 335 } 336 } while (cnt++ < 100); 337 338 rtw8822c_dac_iq_offset(rtwdev, iv, i_value); 339 rtw8822c_dac_iq_offset(rtwdev, qv, q_value); 340 } 341 342 static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev, 343 u32 *i_value, u32 *q_value) 344 { 345 u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C]; 346 u32 rf_a, rf_b; 347 348 rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK); 349 rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK); 350 351 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a); 352 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b); 353 354 rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv); 355 rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value); 356 } 357 358 static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev) 359 { 360 rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff); 361 rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2); 362 rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3); 363 rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e); 364 rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0); 365 rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0); 366 rtw_write32(rtwdev, 0x1b00, 0x00000008); 367 rtw_write8(rtwdev, 0x1bcc, 0x3f); 368 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 369 rtw_write8(rtwdev, 0x1bcc, 0x3f); 370 rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0); 371 rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3); 372 } 373 374 static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev, 375 u8 path, u32 *adc_ic, u32 *adc_qc) 376 { 377 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 378 u32 ic = 0, qc = 0, temp = 0; 379 u32 base_addr; 380 u32 path_sel; 381 int i; 382 383 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path); 384 385 base_addr = rtw8822c_get_path_write_addr(path); 386 switch (path) { 387 case RF_PATH_A: 388 path_sel = 0xa0000; 389 break; 390 case RF_PATH_B: 391 path_sel = 0x80000; 392 break; 393 default: 394 WARN_ON(1); 395 return; 396 } 397 398 /* ADCK step1 */ 399 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0); 400 if (path == RF_PATH_B) 401 rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041); 402 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 403 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 404 rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4); 405 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 406 rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000); 407 rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000); 408 for (i = 0; i < 10; i++) { 409 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i); 410 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003); 411 rtw_write32(rtwdev, 0x1c24, 0x00010002); 412 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 413 rtw_dbg(rtwdev, RTW_DBG_RFK, 414 "[DACK] before: i=0x%x, q=0x%x\n", ic, qc); 415 416 /* compensation value */ 417 if (ic != 0x0) { 418 ic = 0x400 - ic; 419 *adc_ic = ic; 420 } 421 if (qc != 0x0) { 422 qc = 0x400 - qc; 423 *adc_qc = qc; 424 } 425 temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10); 426 rtw_write32(rtwdev, base_addr + 0x68, temp); 427 dm_info->dack_adck[path] = temp; 428 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n", 429 base_addr + 0x68, temp); 430 /* check ADC DC offset */ 431 rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103); 432 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 433 rtw_dbg(rtwdev, RTW_DBG_RFK, 434 "[DACK] after: i=0x%08x, q=0x%08x\n", ic, qc); 435 if (ic >= 0x200) 436 ic = 0x400 - ic; 437 if (qc >= 0x200) 438 qc = 0x400 - qc; 439 if (ic < 5 && qc < 5) 440 break; 441 } 442 443 /* ADCK step2 */ 444 rtw_write32(rtwdev, 0x1c3c, 0x00000003); 445 rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260); 446 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 447 448 /* release pull low switch on IQ path */ 449 rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1); 450 } 451 452 static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path) 453 { 454 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 455 u32 base_addr; 456 u32 read_addr; 457 458 base_addr = rtw8822c_get_path_write_addr(path); 459 read_addr = rtw8822c_get_path_read_addr(path); 460 461 rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]); 462 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 463 if (path == RF_PATH_A) { 464 rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0); 465 rtw_write32(rtwdev, 0x1c38, 0xffffffff); 466 } 467 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 468 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 469 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 470 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81); 471 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 472 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 473 rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81); 474 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 475 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 476 mdelay(2); 477 rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d); 478 mdelay(2); 479 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 480 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 481 mdelay(1); 482 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 483 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 484 mdelay(20); 485 if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) || 486 !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff)) 487 rtw_err(rtwdev, "failed to wait for dack ready\n"); 488 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 489 mdelay(1); 490 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 491 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 492 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 493 rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87); 494 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 495 } 496 497 static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev, 498 u8 path, u32 *ic_out, u32 *qc_out) 499 { 500 u32 base_addr; 501 u32 ic, qc, ic_in, qc_in; 502 503 base_addr = rtw8822c_get_path_write_addr(path); 504 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0); 505 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8); 506 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0); 507 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8); 508 509 rtw_write32(rtwdev, 0x1b00, 0x00000008); 510 rtw_write8(rtwdev, 0x1bcc, 0x03f); 511 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 512 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 513 rtw_write32(rtwdev, 0x1c3c, 0x00088103); 514 515 rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in); 516 ic = ic_in; 517 qc = qc_in; 518 519 /* compensation value */ 520 if (ic != 0x0) 521 ic = 0x400 - ic; 522 if (qc != 0x0) 523 qc = 0x400 - qc; 524 if (ic < 0x300) { 525 ic = ic * 2 * 6 / 5; 526 ic = ic + 0x80; 527 } else { 528 ic = (0x400 - ic) * 2 * 6 / 5; 529 ic = 0x7f - ic; 530 } 531 if (qc < 0x300) { 532 qc = qc * 2 * 6 / 5; 533 qc = qc + 0x80; 534 } else { 535 qc = (0x400 - qc) * 2 * 6 / 5; 536 qc = 0x7f - qc; 537 } 538 539 *ic_out = ic; 540 *qc_out = qc; 541 542 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in); 543 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after i=0x%x, q=0x%x\n", ic, qc); 544 } 545 546 static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path, 547 u32 adc_ic, u32 adc_qc, 548 u32 *ic_in, u32 *qc_in, 549 u32 *i_out, u32 *q_out) 550 { 551 u32 base_addr; 552 u32 read_addr; 553 u32 ic, qc; 554 u32 temp; 555 556 base_addr = rtw8822c_get_path_write_addr(path); 557 read_addr = rtw8822c_get_path_read_addr(path); 558 ic = *ic_in; 559 qc = *qc_in; 560 561 rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220); 562 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 563 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 564 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88); 565 rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81); 566 rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208); 567 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf); 568 rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4); 569 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88); 570 rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81); 571 rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208); 572 rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf); 573 rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4); 574 rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000); 575 mdelay(2); 576 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6); 577 mdelay(2); 578 rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89); 579 rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89); 580 mdelay(1); 581 rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000); 582 rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000); 583 mdelay(20); 584 if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) || 585 !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc)) 586 rtw_err(rtwdev, "failed to write IQ vector to hardware\n"); 587 rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000); 588 mdelay(1); 589 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3); 590 rtw_write32(rtwdev, 0x9b4, 0xdb6db600); 591 592 /* check DAC DC offset */ 593 temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10); 594 rtw_write32(rtwdev, base_addr + 0x68, temp); 595 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5); 596 rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000); 597 rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc); 598 if (ic >= 0x10) 599 ic = ic - 0x10; 600 else 601 ic = 0x400 - (0x10 - ic); 602 603 if (qc >= 0x10) 604 qc = qc - 0x10; 605 else 606 qc = 0x400 - (0x10 - qc); 607 608 *i_out = ic; 609 *q_out = qc; 610 611 if (ic >= 0x200) 612 ic = 0x400 - ic; 613 if (qc >= 0x200) 614 qc = 0x400 - qc; 615 616 *ic_in = ic; 617 *qc_in = qc; 618 619 rtw_dbg(rtwdev, RTW_DBG_RFK, 620 "[DACK] after DACK i=0x%x, q=0x%x\n", *i_out, *q_out); 621 } 622 623 static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path) 624 { 625 u32 base_addr = rtw8822c_get_path_write_addr(path); 626 627 rtw_write32(rtwdev, base_addr + 0x68, 0x0); 628 rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4); 629 rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0); 630 rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1); 631 } 632 633 static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev, 634 u8 path, u8 vec, u32 w_addr, u32 r_addr) 635 { 636 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 637 u16 val; 638 u32 i; 639 640 if (WARN_ON(vec >= 2)) 641 return; 642 643 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 644 rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i); 645 val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000); 646 dm_info->dack_msbk[path][vec][i] = val; 647 } 648 } 649 650 static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path) 651 { 652 u32 w_off = 0x1c; 653 u32 r_off = 0x2c; 654 u32 w_addr, r_addr; 655 656 if (WARN_ON(path >= 2)) 657 return; 658 659 /* backup I vector */ 660 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0; 661 r_addr = rtw8822c_get_path_read_addr(path) + 0x10; 662 rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr); 663 664 /* backup Q vector */ 665 w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 666 r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off; 667 rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr); 668 } 669 670 static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev) 671 { 672 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 673 u8 val; 674 675 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000); 676 dm_info->dack_dck[RF_PATH_A][0][0] = val; 677 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf); 678 dm_info->dack_dck[RF_PATH_A][0][1] = val; 679 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000); 680 dm_info->dack_dck[RF_PATH_A][1][0] = val; 681 val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf); 682 dm_info->dack_dck[RF_PATH_A][1][1] = val; 683 684 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000); 685 dm_info->dack_dck[RF_PATH_B][0][0] = val; 686 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf); 687 dm_info->dack_dck[RF_PATH_B][1][0] = val; 688 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000); 689 dm_info->dack_dck[RF_PATH_B][0][1] = val; 690 val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf); 691 dm_info->dack_dck[RF_PATH_B][1][1] = val; 692 } 693 694 static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev) 695 { 696 u32 temp[3]; 697 698 temp[0] = rtw_read32(rtwdev, 0x1860); 699 temp[1] = rtw_read32(rtwdev, 0x4160); 700 temp[2] = rtw_read32(rtwdev, 0x9b4); 701 702 /* set clock */ 703 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 704 705 /* backup path-A I/Q */ 706 rtw_write32_clr(rtwdev, 0x1830, BIT(30)); 707 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 708 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A); 709 710 /* backup path-B I/Q */ 711 rtw_write32_clr(rtwdev, 0x4130, BIT(30)); 712 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 713 rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B); 714 715 rtw8822c_dac_cal_backup_dck(rtwdev); 716 rtw_write32_set(rtwdev, 0x1830, BIT(30)); 717 rtw_write32_set(rtwdev, 0x4130, BIT(30)); 718 719 rtw_write32(rtwdev, 0x1860, temp[0]); 720 rtw_write32(rtwdev, 0x4160, temp[1]); 721 rtw_write32(rtwdev, 0x9b4, temp[2]); 722 } 723 724 static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev) 725 { 726 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 727 u8 val; 728 729 rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19)); 730 val = dm_info->dack_dck[RF_PATH_A][0][0]; 731 rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val); 732 val = dm_info->dack_dck[RF_PATH_A][0][1]; 733 rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val); 734 735 rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19)); 736 val = dm_info->dack_dck[RF_PATH_A][1][0]; 737 rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val); 738 val = dm_info->dack_dck[RF_PATH_A][1][1]; 739 rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val); 740 741 rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19)); 742 val = dm_info->dack_dck[RF_PATH_B][0][0]; 743 rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val); 744 val = dm_info->dack_dck[RF_PATH_B][0][1]; 745 rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val); 746 747 rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19)); 748 val = dm_info->dack_dck[RF_PATH_B][1][0]; 749 rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val); 750 val = dm_info->dack_dck[RF_PATH_B][1][1]; 751 rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val); 752 } 753 754 static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev) 755 { 756 rtw_write32(rtwdev, 0x9b4, 0xdb66db00); 757 758 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0); 759 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0); 760 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0); 761 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0); 762 763 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0); 764 rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c); 765 rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1); 766 rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1); 767 768 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0); 769 rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c); 770 rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1); 771 rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1); 772 773 rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0); 774 rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0); 775 rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0); 776 rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0); 777 778 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0); 779 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0); 780 rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1); 781 rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1); 782 783 rtw8822c_dac_cal_restore_dck(rtwdev); 784 785 rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7); 786 rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7); 787 rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7); 788 rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7); 789 790 rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1); 791 rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1); 792 793 rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0); 794 rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0); 795 rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0); 796 rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0); 797 798 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0); 799 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0); 800 rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1); 801 rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1); 802 803 rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1); 804 rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1); 805 } 806 807 static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev, 808 u32 target_addr, u32 toggle_addr) 809 { 810 u32 cnt = 0; 811 812 do { 813 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0); 814 rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2); 815 816 if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6) 817 return true; 818 819 } while (cnt++ < 100); 820 821 return false; 822 } 823 824 static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path) 825 { 826 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 827 u32 w_off = 0x1c; 828 u32 r_off = 0x2c; 829 u32 w_i, r_i, w_q, r_q; 830 u32 value; 831 u32 i; 832 833 w_i = rtw8822c_get_path_write_addr(path) + 0xb0; 834 r_i = rtw8822c_get_path_read_addr(path) + 0x08; 835 w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off; 836 r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off; 837 838 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8)) 839 return false; 840 841 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 842 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 843 value = dm_info->dack_msbk[path][0][i]; 844 rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value); 845 rtw_write32_mask(rtwdev, w_i, 0xf0000000, i); 846 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1); 847 } 848 849 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0); 850 851 if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8)) 852 return false; 853 854 for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) { 855 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 856 value = dm_info->dack_msbk[path][1][i]; 857 rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value); 858 rtw_write32_mask(rtwdev, w_q, 0xf0000000, i); 859 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1); 860 } 861 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0); 862 863 rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0); 864 rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0); 865 rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0); 866 rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0); 867 868 return true; 869 } 870 871 static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 872 { 873 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A)) 874 return false; 875 876 if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B)) 877 return false; 878 879 return true; 880 } 881 882 static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev) 883 { 884 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 885 u32 temp[3]; 886 887 /* sample the first element for both path's IQ vector */ 888 if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 && 889 dm_info->dack_msbk[RF_PATH_A][1][0] == 0 && 890 dm_info->dack_msbk[RF_PATH_B][0][0] == 0 && 891 dm_info->dack_msbk[RF_PATH_B][1][0] == 0) 892 return false; 893 894 temp[0] = rtw_read32(rtwdev, 0x1860); 895 temp[1] = rtw_read32(rtwdev, 0x4160); 896 temp[2] = rtw_read32(rtwdev, 0x9b4); 897 898 rtw8822c_dac_cal_restore_prepare(rtwdev); 899 if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) || 900 !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) || 901 !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) || 902 !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff)) 903 return false; 904 905 if (!__rtw8822c_dac_cal_restore(rtwdev)) { 906 rtw_err(rtwdev, "failed to restore dack vectors\n"); 907 return false; 908 } 909 910 rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1); 911 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 912 rtw_write32(rtwdev, 0x1860, temp[0]); 913 rtw_write32(rtwdev, 0x4160, temp[1]); 914 rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1); 915 rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1); 916 rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1); 917 rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1); 918 rtw_write32(rtwdev, 0x9b4, temp[2]); 919 920 return true; 921 } 922 923 static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev) 924 { 925 struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C]; 926 struct rtw_backup_info backup[DACK_REG_8822C]; 927 u32 ic = 0, qc = 0, i; 928 u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0; 929 u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0; 930 u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0; 931 932 if (rtw8822c_dac_cal_restore(rtwdev)) 933 return; 934 935 /* not able to restore, do it */ 936 937 rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf); 938 939 rtw8822c_dac_bb_setting(rtwdev); 940 941 /* path-A */ 942 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a); 943 for (i = 0; i < 10; i++) { 944 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A); 945 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc); 946 ic_a = ic; 947 qc_a = qc; 948 949 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a, 950 &ic, &qc, &i_a, &q_a); 951 952 if (ic < 5 && qc < 5) 953 break; 954 } 955 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A); 956 957 /* path-B */ 958 rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b); 959 for (i = 0; i < 10; i++) { 960 rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B); 961 rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc); 962 ic_b = ic; 963 qc_b = qc; 964 965 rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b, 966 &ic, &qc, &i_b, &q_b); 967 968 if (ic < 5 && qc < 5) 969 break; 970 } 971 rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B); 972 973 rtw_write32(rtwdev, 0x1b00, 0x00000008); 974 rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1); 975 rtw_write8(rtwdev, 0x1bcc, 0x0); 976 rtw_write32(rtwdev, 0x1b00, 0x0000000a); 977 rtw_write8(rtwdev, 0x1bcc, 0x0); 978 979 rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf); 980 981 /* backup results to restore, saving a lot of time */ 982 rtw8822c_dac_cal_backup(rtwdev); 983 984 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a); 985 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b); 986 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a); 987 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b); 988 } 989 990 static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev) 991 { 992 u8 x2k_busy; 993 994 mdelay(1); 995 x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15)); 996 if (x2k_busy == 1) { 997 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440); 998 rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D); 999 rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440); 1000 mdelay(1); 1001 } 1002 } 1003 1004 static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8]) 1005 { 1006 #define RF_SET_POWER_TRIM(_path, _seq, _idx) \ 1007 do { \ 1008 rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq); \ 1009 rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK, \ 1010 bb_gain[_path][_idx]); \ 1011 } while (0) 1012 u8 path; 1013 1014 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1015 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1); 1016 RF_SET_POWER_TRIM(path, 0x0, 0); 1017 RF_SET_POWER_TRIM(path, 0x1, 1); 1018 RF_SET_POWER_TRIM(path, 0x2, 2); 1019 RF_SET_POWER_TRIM(path, 0x3, 2); 1020 RF_SET_POWER_TRIM(path, 0x4, 3); 1021 RF_SET_POWER_TRIM(path, 0x5, 4); 1022 RF_SET_POWER_TRIM(path, 0x6, 5); 1023 RF_SET_POWER_TRIM(path, 0x7, 6); 1024 RF_SET_POWER_TRIM(path, 0x8, 7); 1025 RF_SET_POWER_TRIM(path, 0x9, 3); 1026 RF_SET_POWER_TRIM(path, 0xa, 4); 1027 RF_SET_POWER_TRIM(path, 0xb, 5); 1028 RF_SET_POWER_TRIM(path, 0xc, 6); 1029 RF_SET_POWER_TRIM(path, 0xd, 7); 1030 RF_SET_POWER_TRIM(path, 0xe, 7); 1031 rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0); 1032 } 1033 #undef RF_SET_POWER_TRIM 1034 } 1035 1036 static void rtw8822c_power_trim(struct rtw_dev *rtwdev) 1037 { 1038 u8 pg_pwr = 0xff, i, path, idx; 1039 s8 bb_gain[2][8] = {0}; 1040 u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB}; 1041 u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA, 1042 PPG_5GM2_TXA, PPG_5GH1_TXA}, 1043 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB, 1044 PPG_5GM2_TXB, PPG_5GH1_TXB} }; 1045 bool set = false; 1046 1047 for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) { 1048 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr); 1049 if (pg_pwr == EFUSE_READ_FAIL) 1050 continue; 1051 set = true; 1052 bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr); 1053 bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr); 1054 } 1055 1056 for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) { 1057 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1058 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i], 1059 &pg_pwr); 1060 if (pg_pwr == EFUSE_READ_FAIL) 1061 continue; 1062 set = true; 1063 idx = i + ARRAY_SIZE(rf_efuse_2g); 1064 bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr); 1065 } 1066 } 1067 if (set) 1068 rtw8822c_set_power_trim(rtwdev, bb_gain); 1069 1070 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1071 } 1072 1073 static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev) 1074 { 1075 u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B}; 1076 u8 pg_therm = 0xff, thermal[2] = {0}, path; 1077 1078 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1079 rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm); 1080 if (pg_therm == EFUSE_READ_FAIL) 1081 return; 1082 /* Efuse value of BIT(0) shall be move to BIT(3), and the value 1083 * of BIT(1) to BIT(3) should be right shifted 1 bit. 1084 */ 1085 thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm); 1086 thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0)); 1087 rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]); 1088 } 1089 } 1090 1091 static void rtw8822c_pa_bias(struct rtw_dev *rtwdev) 1092 { 1093 u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB}; 1094 u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB}; 1095 u8 pg_pa_bias = 0xff, path; 1096 1097 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1098 rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path], 1099 &pg_pa_bias); 1100 if (pg_pa_bias == EFUSE_READ_FAIL) 1101 return; 1102 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1103 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_2G_MASK, pg_pa_bias); 1104 } 1105 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 1106 rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path], 1107 &pg_pa_bias); 1108 pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias); 1109 rtw_write_rf(rtwdev, path, 0x60, RF_PABIAS_5G_MASK, pg_pa_bias); 1110 } 1111 } 1112 1113 static void rtw8822c_rf_init(struct rtw_dev *rtwdev) 1114 { 1115 rtw8822c_rf_dac_cal(rtwdev); 1116 rtw8822c_rf_x2_check(rtwdev); 1117 rtw8822c_thermal_trim(rtwdev); 1118 rtw8822c_power_trim(rtwdev); 1119 rtw8822c_pa_bias(rtwdev); 1120 } 1121 1122 static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev) 1123 { 1124 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1125 u8 path; 1126 1127 for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) { 1128 dm_info->delta_power_index[path] = 0; 1129 ewma_thermal_init(&dm_info->avg_thermal[path]); 1130 dm_info->thermal_avg[path] = 0xff; 1131 } 1132 1133 dm_info->pwr_trk_triggered = false; 1134 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 1135 } 1136 1137 static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev) 1138 { 1139 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1140 struct rtw_hal *hal = &rtwdev->hal; 1141 u8 crystal_cap; 1142 u8 cck_gi_u_bnd_msb = 0; 1143 u8 cck_gi_u_bnd_lsb = 0; 1144 u8 cck_gi_l_bnd_msb = 0; 1145 u8 cck_gi_l_bnd_lsb = 0; 1146 bool is_tx2_path; 1147 1148 /* power on BB/RF domain */ 1149 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 1150 BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB); 1151 rtw_write8_set(rtwdev, REG_RF_CTRL, 1152 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 1153 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 1154 1155 /* disable low rate DPD */ 1156 rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL); 1157 1158 /* pre init before header files config */ 1159 rtw8822c_header_file_init(rtwdev, true); 1160 1161 rtw_phy_load_tables(rtwdev); 1162 1163 crystal_cap = rtwdev->efuse.crystal_cap & 0x7f; 1164 rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00, 1165 crystal_cap | (crystal_cap << 7)); 1166 1167 /* post init after header files config */ 1168 rtw8822c_header_file_init(rtwdev, false); 1169 1170 is_tx2_path = false; 1171 rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 1172 is_tx2_path); 1173 rtw_phy_init(rtwdev); 1174 1175 cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000); 1176 cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000); 1177 cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0); 1178 cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000); 1179 1180 dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb)); 1181 dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb)); 1182 1183 rtw8822c_rf_init(rtwdev); 1184 rtw8822c_pwrtrack_init(rtwdev); 1185 1186 rtw_bf_phy_init(rtwdev); 1187 } 1188 1189 #define WLAN_TXQ_RPT_EN 0x1F 1190 #define WLAN_SLOT_TIME 0x09 1191 #define WLAN_PIFS_TIME 0x1C 1192 #define WLAN_SIFS_CCK_CONT_TX 0x0A 1193 #define WLAN_SIFS_OFDM_CONT_TX 0x0E 1194 #define WLAN_SIFS_CCK_TRX 0x0A 1195 #define WLAN_SIFS_OFDM_TRX 0x10 1196 #define WLAN_NAV_MAX 0xC8 1197 #define WLAN_RDG_NAV 0x05 1198 #define WLAN_TXOP_NAV 0x1B 1199 #define WLAN_CCK_RX_TSF 0x30 1200 #define WLAN_OFDM_RX_TSF 0x30 1201 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 1202 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 1203 #define WLAN_DRV_EARLY_INT 0x04 1204 #define WLAN_BCN_CTRL_CLT0 0x10 1205 #define WLAN_BCN_DMA_TIME 0x02 1206 #define WLAN_BCN_MAX_ERR 0xFF 1207 #define WLAN_SIFS_CCK_DUR_TUNE 0x0A 1208 #define WLAN_SIFS_OFDM_DUR_TUNE 0x10 1209 #define WLAN_SIFS_CCK_CTX 0x0A 1210 #define WLAN_SIFS_CCK_IRX 0x0A 1211 #define WLAN_SIFS_OFDM_CTX 0x0E 1212 #define WLAN_SIFS_OFDM_IRX 0x0E 1213 #define WLAN_EIFS_DUR_TUNE 0x40 1214 #define WLAN_EDCA_VO_PARAM 0x002FA226 1215 #define WLAN_EDCA_VI_PARAM 0x005EA328 1216 #define WLAN_EDCA_BE_PARAM 0x005EA42B 1217 #define WLAN_EDCA_BK_PARAM 0x0000A44F 1218 1219 #define WLAN_RX_FILTER0 0xFFFFFFFF 1220 #define WLAN_RX_FILTER2 0xFFFF 1221 #define WLAN_RCR_CFG 0xE400220E 1222 #define WLAN_RXPKT_MAX_SZ 12288 1223 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 1224 1225 #define WLAN_AMPDU_MAX_TIME 0x70 1226 #define WLAN_RTS_LEN_TH 0xFF 1227 #define WLAN_RTS_TX_TIME_TH 0x08 1228 #define WLAN_MAX_AGG_PKT_LIMIT 0x3f 1229 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x3f 1230 #define WLAN_PRE_TXCNT_TIME_TH 0x1E0 1231 #define FAST_EDCA_VO_TH 0x06 1232 #define FAST_EDCA_VI_TH 0x06 1233 #define FAST_EDCA_BE_TH 0x06 1234 #define FAST_EDCA_BK_TH 0x06 1235 #define WLAN_BAR_RETRY_LIMIT 0x01 1236 #define WLAN_BAR_ACK_TYPE 0x05 1237 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 1238 #define WLAN_RESP_TXRATE 0x84 1239 #define WLAN_ACK_TO 0x21 1240 #define WLAN_ACK_TO_CCK 0x6A 1241 #define WLAN_DATA_RATE_FB_CNT_1_4 0x01000000 1242 #define WLAN_DATA_RATE_FB_CNT_5_8 0x08070504 1243 #define WLAN_RTS_RATE_FB_CNT_5_8 0x08070504 1244 #define WLAN_DATA_RATE_FB_RATE0 0xFE01F010 1245 #define WLAN_DATA_RATE_FB_RATE0_H 0x40000000 1246 #define WLAN_RTS_RATE_FB_RATE1 0x003FF010 1247 #define WLAN_RTS_RATE_FB_RATE1_H 0x40000000 1248 #define WLAN_RTS_RATE_FB_RATE4 0x0600F010 1249 #define WLAN_RTS_RATE_FB_RATE4_H 0x400003E0 1250 #define WLAN_RTS_RATE_FB_RATE5 0x0600F015 1251 #define WLAN_RTS_RATE_FB_RATE5_H 0x000000E0 1252 #define WLAN_MULTI_ADDR 0xFFFFFFFF 1253 1254 #define WLAN_TX_FUNC_CFG1 0x30 1255 #define WLAN_TX_FUNC_CFG2 0x30 1256 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 1257 #define WLAN_MAC_OPT_LB_FUNC1 0x80 1258 #define WLAN_MAC_OPT_FUNC2 0x30810041 1259 #define WLAN_MAC_INT_MIG_CFG 0x33330000 1260 1261 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 1262 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 1263 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 1264 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 1265 1266 #define WLAN_SIFS_DUR_TUNE (WLAN_SIFS_CCK_DUR_TUNE | \ 1267 (WLAN_SIFS_OFDM_DUR_TUNE << 8)) 1268 1269 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 1270 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 1271 1272 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 1273 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 1274 1275 #define MAC_CLK_SPEED 80 /* 80M */ 1276 #define EFUSE_PCB_INFO_OFFSET 0xCA 1277 1278 static int rtw8822c_mac_init(struct rtw_dev *rtwdev) 1279 { 1280 u8 value8; 1281 u16 value16; 1282 u32 value32; 1283 u16 pre_txcnt; 1284 1285 /* txq control */ 1286 value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL); 1287 value8 |= (BIT(7) & ~BIT(1) & ~BIT(2)); 1288 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8); 1289 rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN); 1290 /* sifs control */ 1291 rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE); 1292 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 1293 rtw_write16(rtwdev, REG_RESP_SIFS_CCK, 1294 WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8); 1295 rtw_write16(rtwdev, REG_RESP_SIFS_OFDM, 1296 WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8); 1297 /* rate fallback control */ 1298 rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4); 1299 rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8); 1300 rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8); 1301 rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0); 1302 rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H); 1303 rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1); 1304 rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H); 1305 rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4); 1306 rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H); 1307 rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5); 1308 rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H); 1309 /* protocol configuration */ 1310 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 1311 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 1312 pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT; 1313 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); 1314 rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8)); 1315 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 1316 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 1317 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 1318 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 1319 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 1320 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 1321 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 1322 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 1323 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 1324 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 1325 /* close BA parser */ 1326 rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN); 1327 rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC); 1328 1329 /* EDCA configuration */ 1330 rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM); 1331 rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM); 1332 rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM); 1333 rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM); 1334 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 1335 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 1336 rtw_write8_set(rtwdev, REG_RD_CTRL + 1, 1337 (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE | 1338 BIT_DIS_STBC_CFE) >> 8); 1339 1340 /* MAC clock configuration */ 1341 rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL); 1342 rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED); 1343 rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED); 1344 1345 rtw_write8_set(rtwdev, REG_MISC_CTRL, 1346 BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA); 1347 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 1348 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 1349 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 1350 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 1351 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 1352 /* Set beacon cotnrol - enable TSF and other related functions */ 1353 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1354 /* Set send beacon related registers */ 1355 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 1356 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 1357 rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0); 1358 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 1359 rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR); 1360 1361 /* WMAC configuration */ 1362 rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR); 1363 rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR); 1364 rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE); 1365 rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO); 1366 rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK); 1367 rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE); 1368 rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX); 1369 rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H + 2, WLAN_BAR_ACK_TYPE); 1370 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 1371 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 1372 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 1373 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 1374 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 1375 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 1376 rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN); 1377 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 1378 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1); 1379 1380 /* init low power */ 1381 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F; 1382 value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) | 1383 BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16; 1384 rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16); 1385 value16 = 0; 1386 value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1); 1387 value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN 1388 | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN 1389 | BIT_RXPSF_OFDMRST; 1390 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1391 rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF); 1392 /* rx ignore configuration */ 1393 value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL); 1394 value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST | 1395 BIT_RXPSF_CONT_ERRCHKEN); 1396 value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07); 1397 rtw_write16(rtwdev, REG_RXPSF_CTRL, value16); 1398 1399 /* Interrupt migration configuration */ 1400 rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG); 1401 1402 return 0; 1403 } 1404 1405 static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable) 1406 { 1407 if (enable) { 1408 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1); 1409 rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1); 1410 rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1); 1411 } else { 1412 rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0); 1413 } 1414 } 1415 1416 static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 1417 { 1418 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 1419 #define RF18_BAND_2G (0) 1420 #define RF18_BAND_5G (BIT(16) | BIT(8)) 1421 #define RF18_CHANNEL_MASK (MASKBYTE0) 1422 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 1423 #define RF18_RFSI_GE_CH80 (BIT(17)) 1424 #define RF18_RFSI_GT_CH140 (BIT(18)) 1425 #define RF18_BW_MASK (BIT(13) | BIT(12)) 1426 #define RF18_BW_20M (BIT(13) | BIT(12)) 1427 #define RF18_BW_40M (BIT(13)) 1428 #define RF18_BW_80M (BIT(12)) 1429 1430 u32 rf_reg18 = 0; 1431 u32 rf_rxbb = 0; 1432 1433 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 1434 1435 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 1436 RF18_BW_MASK); 1437 1438 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 1439 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 1440 if (IS_CH_5G_BAND_4(channel)) 1441 rf_reg18 |= RF18_RFSI_GT_CH140; 1442 else if (IS_CH_5G_BAND_3(channel)) 1443 rf_reg18 |= RF18_RFSI_GE_CH80; 1444 1445 switch (bw) { 1446 case RTW_CHANNEL_WIDTH_5: 1447 case RTW_CHANNEL_WIDTH_10: 1448 case RTW_CHANNEL_WIDTH_20: 1449 default: 1450 rf_reg18 |= RF18_BW_20M; 1451 rf_rxbb = 0x18; 1452 break; 1453 case RTW_CHANNEL_WIDTH_40: 1454 /* RF bandwidth */ 1455 rf_reg18 |= RF18_BW_40M; 1456 rf_rxbb = 0x10; 1457 break; 1458 case RTW_CHANNEL_WIDTH_80: 1459 rf_reg18 |= RF18_BW_80M; 1460 rf_rxbb = 0x8; 1461 break; 1462 } 1463 1464 rtw8822c_rstb_3wire(rtwdev, false); 1465 1466 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01); 1467 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12); 1468 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb); 1469 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00); 1470 1471 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01); 1472 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12); 1473 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb); 1474 rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00); 1475 1476 rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18); 1477 rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18); 1478 1479 rtw8822c_rstb_3wire(rtwdev, true); 1480 } 1481 1482 static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev) 1483 { 1484 u32 igi; 1485 1486 igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f); 1487 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2); 1488 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2); 1489 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi); 1490 rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi); 1491 } 1492 1493 static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1494 u8 primary_ch_idx) 1495 { 1496 if (IS_CH_2G_BAND(channel)) { 1497 rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1498 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1499 rtw_write32_set(rtwdev, REG_TXF4, BIT(20)); 1500 rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1501 rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1502 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF); 1503 1504 switch (bw) { 1505 case RTW_CHANNEL_WIDTH_20: 1506 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1507 0x5); 1508 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1509 0x5); 1510 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1511 0x6); 1512 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1513 0x6); 1514 break; 1515 case RTW_CHANNEL_WIDTH_40: 1516 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK, 1517 0x4); 1518 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK, 1519 0x4); 1520 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1521 0x0); 1522 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1523 0x0); 1524 break; 1525 } 1526 if (channel == 13 || channel == 14) 1527 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969); 1528 else if (channel == 11 || channel == 12) 1529 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a); 1530 else 1531 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa); 1532 if (channel == 14) { 1533 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0); 1534 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1535 0x4962c931); 1536 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3); 1537 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b); 1538 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7); 1539 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0); 1540 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1541 0xff012455); 1542 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff); 1543 } else { 1544 rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284); 1545 rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD, 1546 0x3e18fec8); 1547 rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88); 1548 rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4); 1549 rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2); 1550 rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 1551 0x00faf0de); 1552 rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD, 1553 0x00122344); 1554 rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 1555 0x0fffffff); 1556 } 1557 if (channel == 13) 1558 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1559 else 1560 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1); 1561 } else if (IS_CH_5G_BAND(channel)) { 1562 rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN); 1563 rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN); 1564 rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT); 1565 rtw_write32_clr(rtwdev, REG_TXF4, BIT(20)); 1566 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x0); 1567 rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22); 1568 rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3); 1569 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) { 1570 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1571 0x1); 1572 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1573 0x1); 1574 } else if (IS_CH_5G_BAND_3(channel)) { 1575 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1576 0x2); 1577 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1578 0x2); 1579 } else if (IS_CH_5G_BAND_4(channel)) { 1580 rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM, 1581 0x3); 1582 rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM, 1583 0x3); 1584 } 1585 1586 if (channel >= 36 && channel <= 51) 1587 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494); 1588 else if (channel >= 52 && channel <= 55) 1589 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493); 1590 else if (channel >= 56 && channel <= 111) 1591 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453); 1592 else if (channel >= 112 && channel <= 119) 1593 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452); 1594 else if (channel >= 120 && channel <= 172) 1595 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412); 1596 else if (channel >= 173 && channel <= 177) 1597 rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411); 1598 } 1599 1600 switch (bw) { 1601 case RTW_CHANNEL_WIDTH_20: 1602 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B); 1603 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1604 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0); 1605 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7); 1606 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6); 1607 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1608 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1609 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1610 break; 1611 case RTW_CHANNEL_WIDTH_40: 1612 rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4), 1613 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0)); 1614 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5); 1615 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1616 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1617 (primary_ch_idx | (primary_ch_idx << 4))); 1618 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1); 1619 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1620 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1621 break; 1622 case RTW_CHANNEL_WIDTH_80: 1623 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa); 1624 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0); 1625 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00, 1626 (primary_ch_idx | (primary_ch_idx << 4))); 1627 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6); 1628 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1); 1629 break; 1630 case RTW_CHANNEL_WIDTH_5: 1631 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1632 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1633 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1); 1634 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4); 1635 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4); 1636 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1637 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1638 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1639 break; 1640 case RTW_CHANNEL_WIDTH_10: 1641 rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB); 1642 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0); 1643 rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2); 1644 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6); 1645 rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5); 1646 rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0); 1647 rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1); 1648 rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0); 1649 break; 1650 } 1651 } 1652 1653 static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 1654 u8 primary_chan_idx) 1655 { 1656 rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 1657 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 1658 rtw8822c_set_channel_rf(rtwdev, channel, bw); 1659 rtw8822c_toggle_igi(rtwdev); 1660 } 1661 1662 static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1663 { 1664 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1665 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0); 1666 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0); 1667 } else if (rx_path == BB_PATH_AB) { 1668 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1); 1669 rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1); 1670 } 1671 1672 if (rx_path == BB_PATH_A) 1673 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0); 1674 else if (rx_path == BB_PATH_B) 1675 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5); 1676 else if (rx_path == BB_PATH_AB) 1677 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1); 1678 } 1679 1680 static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1681 { 1682 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 1683 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0); 1684 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0); 1685 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0); 1686 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0); 1687 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0); 1688 } else if (rx_path == BB_PATH_AB) { 1689 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1); 1690 rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1); 1691 rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1); 1692 rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1); 1693 rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1); 1694 } 1695 1696 rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path); 1697 rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path); 1698 } 1699 1700 static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path) 1701 { 1702 rtw8822c_config_cck_rx_path(rtwdev, rx_path); 1703 rtw8822c_config_ofdm_rx_path(rtwdev, rx_path); 1704 } 1705 1706 static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1707 bool is_tx2_path) 1708 { 1709 if (tx_path == BB_PATH_A) { 1710 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1711 } else if (tx_path == BB_PATH_B) { 1712 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4); 1713 } else { 1714 if (is_tx2_path) 1715 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc); 1716 else 1717 rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8); 1718 } 1719 } 1720 1721 static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1722 bool is_tx2_path) 1723 { 1724 if (tx_path == BB_PATH_A) { 1725 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11); 1726 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1727 } else if (tx_path == BB_PATH_B) { 1728 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12); 1729 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0); 1730 } else { 1731 if (is_tx2_path) { 1732 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33); 1733 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404); 1734 } else { 1735 rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31); 1736 rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400); 1737 } 1738 } 1739 } 1740 1741 static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path, 1742 bool is_tx2_path) 1743 { 1744 rtw8822c_config_cck_tx_path(rtwdev, tx_path, is_tx2_path); 1745 rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, is_tx2_path); 1746 } 1747 1748 static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 1749 u8 rx_path, bool is_tx2_path) 1750 { 1751 if ((tx_path | rx_path) & BB_PATH_A) 1752 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312); 1753 else 1754 rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111); 1755 if ((tx_path | rx_path) & BB_PATH_B) 1756 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312); 1757 else 1758 rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111); 1759 1760 rtw8822c_config_rx_path(rtwdev, rx_path); 1761 rtw8822c_config_tx_path(rtwdev, tx_path, is_tx2_path); 1762 1763 rtw8822c_toggle_igi(rtwdev); 1764 } 1765 1766 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 1767 struct rtw_rx_pkt_stat *pkt_stat) 1768 { 1769 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1770 u8 l_bnd, u_bnd; 1771 u8 gain_a, gain_b; 1772 s8 rx_power[RTW_RF_PATH_MAX]; 1773 s8 min_rx_power = -120; 1774 u8 rssi; 1775 int path; 1776 1777 rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status); 1778 rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status); 1779 l_bnd = dm_info->cck_gi_l_bnd; 1780 u_bnd = dm_info->cck_gi_u_bnd; 1781 gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status); 1782 gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status); 1783 if (gain_a < l_bnd) 1784 rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1; 1785 else if (gain_a > u_bnd) 1786 rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1; 1787 if (gain_b < l_bnd) 1788 rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1; 1789 else if (gain_b > u_bnd) 1790 rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1; 1791 1792 rx_power[RF_PATH_A] -= 110; 1793 rx_power[RF_PATH_B] -= 110; 1794 1795 pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A]; 1796 pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B]; 1797 1798 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1799 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1800 dm_info->rssi[path] = rssi; 1801 } 1802 1803 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 1804 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 1805 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 1806 min_rx_power); 1807 } 1808 1809 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 1810 struct rtw_rx_pkt_stat *pkt_stat) 1811 { 1812 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1813 u8 rxsc, bw; 1814 s8 min_rx_power = -120; 1815 s8 rx_evm; 1816 u8 evm_dbm = 0; 1817 u8 rssi; 1818 int path; 1819 1820 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 1821 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 1822 else 1823 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 1824 1825 if (rxsc >= 9 && rxsc <= 12) 1826 bw = RTW_CHANNEL_WIDTH_40; 1827 else if (rxsc >= 13) 1828 bw = RTW_CHANNEL_WIDTH_80; 1829 else 1830 bw = RTW_CHANNEL_WIDTH_20; 1831 1832 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 1833 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 1834 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 1835 pkt_stat->bw = bw; 1836 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 1837 pkt_stat->rx_power[RF_PATH_B], 1838 min_rx_power); 1839 1840 dm_info->curr_rx_rate = pkt_stat->rate; 1841 1842 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 1843 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 1844 1845 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 1846 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 1847 1848 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 1849 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 1850 1851 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 1852 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 1853 dm_info->rssi[path] = rssi; 1854 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 1855 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 1856 1857 rx_evm = pkt_stat->rx_evm[path]; 1858 1859 if (rx_evm < 0) { 1860 if (rx_evm == S8_MIN) 1861 evm_dbm = 0; 1862 else 1863 evm_dbm = ((u8)-rx_evm >> 1); 1864 } 1865 dm_info->rx_evm_dbm[path] = evm_dbm; 1866 } 1867 } 1868 1869 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 1870 struct rtw_rx_pkt_stat *pkt_stat) 1871 { 1872 u8 page; 1873 1874 page = *phy_status & 0xf; 1875 1876 switch (page) { 1877 case 0: 1878 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 1879 break; 1880 case 1: 1881 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 1882 break; 1883 default: 1884 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 1885 return; 1886 } 1887 } 1888 1889 static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 1890 struct rtw_rx_pkt_stat *pkt_stat, 1891 struct ieee80211_rx_status *rx_status) 1892 { 1893 struct ieee80211_hdr *hdr; 1894 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 1895 u8 *phy_status = NULL; 1896 1897 memset(pkt_stat, 0, sizeof(*pkt_stat)); 1898 1899 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 1900 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 1901 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 1902 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 1903 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 1904 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 1905 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 1906 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 1907 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 1908 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 1909 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 1910 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 1911 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 1912 1913 /* drv_info_sz is in unit of 8-bytes */ 1914 pkt_stat->drv_info_sz *= 8; 1915 1916 /* c2h cmd pkt's rx/phy status is not interested */ 1917 if (pkt_stat->is_c2h) 1918 return; 1919 1920 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 1921 pkt_stat->drv_info_sz); 1922 if (pkt_stat->phy_status) { 1923 phy_status = rx_desc + desc_sz + pkt_stat->shift; 1924 query_phy_status(rtwdev, phy_status, pkt_stat); 1925 } 1926 1927 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 1928 } 1929 1930 static void 1931 rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck, 1932 u8 *tx_pwr_ref_ofdm) 1933 { 1934 struct rtw_hal *hal = &rtwdev->hal; 1935 u32 txref_cck[2] = {0x18a0, 0x41a0}; 1936 u32 txref_ofdm[2] = {0x18e8, 0x41e8}; 1937 u8 path; 1938 1939 for (path = 0; path < hal->rf_path_num; path++) { 1940 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1941 rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000, 1942 tx_pwr_ref_cck[path]); 1943 } 1944 for (path = 0; path < hal->rf_path_num; path++) { 1945 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0); 1946 rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00, 1947 tx_pwr_ref_ofdm[path]); 1948 } 1949 } 1950 1951 static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate, 1952 s8 *diff_idx) 1953 { 1954 u32 offset_txagc = 0x3a00; 1955 u8 rate_idx = rate & 0xfc; 1956 u8 pwr_idx[4]; 1957 u32 phy_pwr_idx; 1958 int i; 1959 1960 for (i = 0; i < 4; i++) 1961 pwr_idx[i] = diff_idx[i] & 0x7f; 1962 1963 phy_pwr_idx = pwr_idx[0] | 1964 (pwr_idx[1] << 8) | 1965 (pwr_idx[2] << 16) | 1966 (pwr_idx[3] << 24); 1967 1968 rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0); 1969 rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD, 1970 phy_pwr_idx); 1971 } 1972 1973 static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev) 1974 { 1975 struct rtw_hal *hal = &rtwdev->hal; 1976 u8 rs, rate, j; 1977 u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M], 1978 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]}; 1979 u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7], 1980 hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]}; 1981 s8 diff_a, diff_b; 1982 u8 pwr_a, pwr_b; 1983 s8 diff_idx[4]; 1984 1985 rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm); 1986 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) { 1987 for (j = 0; j < rtw_rate_size[rs]; j++) { 1988 rate = rtw_rate_section[rs][j]; 1989 pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate]; 1990 pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate]; 1991 if (rs == 0) { 1992 diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0]; 1993 diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1]; 1994 } else { 1995 diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0]; 1996 diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1]; 1997 } 1998 diff_idx[rate % 4] = min(diff_a, diff_b); 1999 if (rate % 4 == 3) 2000 rtw8822c_set_tx_power_diff(rtwdev, rate - 3, 2001 diff_idx); 2002 } 2003 } 2004 } 2005 2006 static int rtw8822c_set_antenna(struct rtw_dev *rtwdev, 2007 u32 antenna_tx, 2008 u32 antenna_rx) 2009 { 2010 struct rtw_hal *hal = &rtwdev->hal; 2011 2012 switch (antenna_tx) { 2013 case BB_PATH_A: 2014 case BB_PATH_B: 2015 case BB_PATH_AB: 2016 break; 2017 default: 2018 rtw_info(rtwdev, "unsupport tx path 0x%x\n", antenna_tx); 2019 return -EINVAL; 2020 } 2021 2022 /* path B only is not available for RX */ 2023 switch (antenna_rx) { 2024 case BB_PATH_A: 2025 case BB_PATH_AB: 2026 break; 2027 default: 2028 rtw_info(rtwdev, "unsupport rx path 0x%x\n", antenna_rx); 2029 return -EINVAL; 2030 } 2031 2032 hal->antenna_tx = antenna_tx; 2033 hal->antenna_rx = antenna_rx; 2034 2035 rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 2036 2037 return 0; 2038 } 2039 2040 static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 2041 { 2042 u8 ldo_pwr; 2043 2044 ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC); 2045 ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON; 2046 rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr); 2047 } 2048 2049 static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev) 2050 { 2051 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 2052 u32 cck_enable; 2053 u32 cck_fa_cnt; 2054 u32 crc32_cnt; 2055 u32 cca32_cnt; 2056 u32 ofdm_fa_cnt; 2057 u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5; 2058 u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail, 2059 fast_fsync, crc8_fail_vhta, mcs_fail_vht; 2060 2061 cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN; 2062 cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT); 2063 2064 ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1); 2065 ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2); 2066 ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3); 2067 ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4); 2068 ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5); 2069 2070 parity_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1); 2071 rate_illegal = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2); 2072 crc8_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2); 2073 crc8_fail_vhta = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3); 2074 mcs_fail = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4); 2075 mcs_fail_vht = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4); 2076 fast_fsync = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5); 2077 sb_search_fail = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5); 2078 2079 ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta + 2080 mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail; 2081 2082 dm_info->cck_fa_cnt = cck_fa_cnt; 2083 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 2084 dm_info->total_fa_cnt = ofdm_fa_cnt; 2085 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 2086 2087 crc32_cnt = rtw_read32(rtwdev, 0x2c04); 2088 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 2089 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2090 crc32_cnt = rtw_read32(rtwdev, 0x2c14); 2091 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 2092 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2093 crc32_cnt = rtw_read32(rtwdev, 0x2c10); 2094 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 2095 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2096 crc32_cnt = rtw_read32(rtwdev, 0x2c0c); 2097 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 2098 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 2099 2100 cca32_cnt = rtw_read32(rtwdev, 0x2c08); 2101 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 2102 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 2103 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 2104 if (cck_enable) 2105 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 2106 2107 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0); 2108 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2); 2109 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0); 2110 rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2); 2111 2112 /* disable rx clk gating to reset counters */ 2113 rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2114 rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2115 rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST); 2116 rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN); 2117 } 2118 2119 static void rtw8822c_do_iqk(struct rtw_dev *rtwdev) 2120 { 2121 struct rtw_iqk_para para = {0}; 2122 u8 iqk_chk; 2123 int counter; 2124 2125 para.clear = 1; 2126 rtw_fw_do_iqk(rtwdev, ¶); 2127 2128 for (counter = 0; counter < 300; counter++) { 2129 iqk_chk = rtw_read8(rtwdev, REG_RPT_CIP); 2130 if (iqk_chk == 0xaa) 2131 break; 2132 msleep(20); 2133 } 2134 rtw_write8(rtwdev, REG_IQKSTAT, 0x0); 2135 2136 rtw_dbg(rtwdev, RTW_DBG_RFK, "iqk counter=%d\n", counter); 2137 } 2138 2139 /* for coex */ 2140 static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev) 2141 { 2142 /* enable TBTT nterrupt */ 2143 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 2144 2145 /* BT report packet sample rate */ 2146 /* 0x790[5:0]=0x5 */ 2147 rtw_write8_set(rtwdev, REG_BT_TDMA_TIME, 0x05); 2148 2149 /* enable BT counter statistics */ 2150 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 2151 2152 /* enable PTA (3-wire function form BT side) */ 2153 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 2154 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_AOD_GPIO3); 2155 2156 /* enable PTA (tx/rx signal form WiFi side) */ 2157 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 2158 /* wl tx signal to PTA not case EDCCA */ 2159 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 2160 /* GNT_BT=1 while select both */ 2161 rtw_write8_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 2162 /* BT_CCA = ~GNT_WL_BB, (not or GNT_BT_BB, LTE_Rx */ 2163 rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL); 2164 2165 /* to avoid RF parameter error */ 2166 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, 0x40000); 2167 } 2168 2169 static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 2170 { 2171 struct rtw_coex *coex = &rtwdev->coex; 2172 struct rtw_coex_stat *coex_stat = &coex->stat; 2173 struct rtw_efuse *efuse = &rtwdev->efuse; 2174 u32 rf_0x1; 2175 2176 if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode) 2177 return; 2178 2179 coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode; 2180 2181 if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun) 2182 rf_0x1 = 0x40021; 2183 else 2184 rf_0x1 = 0x40000; 2185 2186 /* BT at S1 for Shared-Ant */ 2187 if (efuse->share_ant) 2188 rf_0x1 |= BIT(13); 2189 2190 rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1); 2191 2192 /* WL-S0 2G RF TRX cannot be masked by GNT_BT 2193 * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type 2194 * disable:0x1860[3] = 1, enable:0x1860[3] = 0 2195 * 2196 * enable "DAC off if GNT_WL = 0" for non-shared-antenna 2197 * disable 0x1c30[22] = 0, 2198 * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1 2199 * 2200 * disable WL-S1 BB chage RF mode if GNT_BT 2201 * since RF TRx mask can do it 2202 */ 2203 rtw_write8_mask(rtwdev, 0x1c32, BIT(6), 1); 2204 rtw_write8_mask(rtwdev, 0x1c39, BIT(4), 0); 2205 rtw_write8_mask(rtwdev, 0x1c3b, BIT(4), 1); 2206 rtw_write8_mask(rtwdev, 0x4160, BIT(3), 1); 2207 2208 /* disable WL-S0 BB chage RF mode if wifi is at 5G, 2209 * or antenna path is separated 2210 */ 2211 if (coex_stat->wl_coex_mode == COEX_WLINK_5G || 2212 coex->under_5g || !efuse->share_ant) { 2213 if (coex_stat->kt_ver >= 3) { 2214 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 2215 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 1); 2216 } else { 2217 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 1); 2218 } 2219 } else { 2220 /* shared-antenna */ 2221 rtw_write8_mask(rtwdev, 0x1860, BIT(3), 0); 2222 if (coex_stat->kt_ver >= 3) 2223 rtw_write8_mask(rtwdev, 0x1ca7, BIT(3), 0); 2224 } 2225 } 2226 2227 static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 2228 { 2229 rtw_write8_mask(rtwdev, 0x66, BIT(4), 0); 2230 rtw_write8_mask(rtwdev, 0x67, BIT(0), 0); 2231 rtw_write8_mask(rtwdev, 0x42, BIT(3), 0); 2232 rtw_write8_mask(rtwdev, 0x65, BIT(7), 0); 2233 rtw_write8_mask(rtwdev, 0x73, BIT(3), 0); 2234 } 2235 2236 static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 2237 { 2238 struct rtw_coex *coex = &rtwdev->coex; 2239 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 2240 struct rtw_efuse *efuse = &rtwdev->efuse; 2241 2242 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 2243 coex_rfe->ant_switch_polarity = 0; 2244 coex_rfe->ant_switch_exist = false; 2245 coex_rfe->ant_switch_with_bt = false; 2246 coex_rfe->ant_switch_diversity = false; 2247 2248 if (efuse->share_ant) 2249 coex_rfe->wlg_at_btg = true; 2250 else 2251 coex_rfe->wlg_at_btg = false; 2252 2253 /* disable LTE coex in wifi side */ 2254 rtw_coex_write_indirect_reg(rtwdev, 0x38, BIT_LTE_COEX_EN, 0x0); 2255 rtw_coex_write_indirect_reg(rtwdev, 0xa0, MASKLWORD, 0xffff); 2256 rtw_coex_write_indirect_reg(rtwdev, 0xa4, MASKLWORD, 0xffff); 2257 } 2258 2259 static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 2260 { 2261 struct rtw_coex *coex = &rtwdev->coex; 2262 struct rtw_coex_dm *coex_dm = &coex->dm; 2263 2264 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 2265 return; 2266 2267 coex_dm->cur_wl_pwr_lvl = wl_pwr; 2268 } 2269 2270 static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 2271 { 2272 struct rtw_coex *coex = &rtwdev->coex; 2273 struct rtw_coex_dm *coex_dm = &coex->dm; 2274 2275 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 2276 return; 2277 2278 coex_dm->cur_wl_rx_low_gain_en = low_gain; 2279 2280 if (coex_dm->cur_wl_rx_low_gain_en) { 2281 /* set Rx filter corner RCK offset */ 2282 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x22); 2283 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x36); 2284 rtw_write_rf(rtwdev, RF_PATH_B, 0xde, 0xfffff, 0x22); 2285 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x36); 2286 } else { 2287 /* set Rx filter corner RCK offset */ 2288 rtw_write_rf(rtwdev, RF_PATH_A, 0xde, 0xfffff, 0x20); 2289 rtw_write_rf(rtwdev, RF_PATH_A, 0x1d, 0xfffff, 0x0); 2290 rtw_write_rf(rtwdev, RF_PATH_B, 0x1d, 0xfffff, 0x0); 2291 } 2292 } 2293 2294 static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev, 2295 struct rtw_vif *vif, 2296 struct rtw_bfee *bfee) 2297 { 2298 u8 csi_rsc = 0; 2299 u32 tmp6dc; 2300 2301 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 2302 2303 tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) | 2304 BIT_WMAC_USE_NDPARATE | 2305 (csi_rsc << 13); 2306 if (vif->net_type == RTW_NET_AP_MODE) 2307 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12)); 2308 else 2309 rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12)); 2310 2311 rtw_write32(rtwdev, REG_CSI_RRSR, 0x550); 2312 } 2313 2314 static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev, 2315 struct rtw_vif *vif, 2316 struct rtw_bfee *bfee, bool enable) 2317 { 2318 if (enable) 2319 rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee); 2320 else 2321 rtw_bf_remove_bfee_su(rtwdev, bfee); 2322 } 2323 2324 static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev, 2325 struct rtw_vif *vif, 2326 struct rtw_bfee *bfee, bool enable) 2327 { 2328 if (enable) 2329 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 2330 else 2331 rtw_bf_remove_bfee_mu(rtwdev, bfee); 2332 } 2333 2334 static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 2335 struct rtw_bfee *bfee, bool enable) 2336 { 2337 if (bfee->role == RTW_BFEE_SU) 2338 rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable); 2339 else if (bfee->role == RTW_BFEE_MU) 2340 rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 2341 else 2342 rtw_warn(rtwdev, "wrong bfee role\n"); 2343 } 2344 2345 struct dpk_cfg_pair { 2346 u32 addr; 2347 u32 bitmask; 2348 u32 data; 2349 }; 2350 2351 void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev, 2352 const struct rtw_table *tbl) 2353 { 2354 const struct dpk_cfg_pair *p = tbl->data; 2355 const struct dpk_cfg_pair *end = p + tbl->size / 3; 2356 2357 BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3); 2358 2359 for (; p < end; p++) 2360 rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data); 2361 } 2362 2363 static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k) 2364 { 2365 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2366 2367 if (is_before_k) { 2368 dpk_info->gnt_control = rtw_read32(rtwdev, 0x70); 2369 dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38); 2370 rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1); 2371 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77); 2372 } else { 2373 rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD, 2374 dpk_info->gnt_value); 2375 rtw_write32(rtwdev, 0x70, dpk_info->gnt_control); 2376 } 2377 } 2378 2379 static void 2380 rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num, 2381 struct rtw_backup_info *bckp) 2382 { 2383 rtw_restore_reg(rtwdev, bckp, reg_num); 2384 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2385 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4); 2386 } 2387 2388 static void 2389 rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg, 2390 u32 reg_num, struct rtw_backup_info *bckp) 2391 { 2392 u32 i; 2393 2394 for (i = 0; i < reg_num; i++) { 2395 bckp[i].len = 4; 2396 bckp[i].reg = reg[i]; 2397 bckp[i].val = rtw_read32(rtwdev, reg[i]); 2398 } 2399 } 2400 2401 static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev, 2402 u32 *rf_reg, 2403 u32 rf_reg_bak[][2]) 2404 { 2405 u32 i; 2406 2407 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2408 rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A, 2409 rf_reg[i], RFREG_MASK); 2410 rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B, 2411 rf_reg[i], RFREG_MASK); 2412 } 2413 } 2414 2415 static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev, 2416 u32 *rf_reg, 2417 u32 rf_reg_bak[][2]) 2418 { 2419 u32 i; 2420 2421 for (i = 0; i < DPK_RF_REG_NUM; i++) { 2422 rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK, 2423 rf_reg_bak[i][RF_PATH_A]); 2424 rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK, 2425 rf_reg_bak[i][RF_PATH_B]); 2426 } 2427 } 2428 2429 static void rtw8822c_dpk_information(struct rtw_dev *rtwdev) 2430 { 2431 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2432 u32 reg; 2433 u8 band_shift; 2434 2435 reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 2436 2437 band_shift = FIELD_GET(BIT(16), reg); 2438 dpk_info->dpk_band = 1 << band_shift; 2439 dpk_info->dpk_ch = FIELD_GET(0xff, reg); 2440 dpk_info->dpk_bw = FIELD_GET(0x3000, reg); 2441 } 2442 2443 static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path) 2444 { 2445 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2446 udelay(5); 2447 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801); 2448 usleep_range(600, 610); 2449 rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800); 2450 } 2451 2452 static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path) 2453 { 2454 u16 dc_i, dc_q; 2455 u8 corr_val, corr_idx; 2456 2457 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0); 2458 dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2459 dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0)); 2460 2461 if (dc_i & BIT(11)) 2462 dc_i = 0x1000 - dc_i; 2463 if (dc_q & BIT(11)) 2464 dc_q = 0x1000 - dc_q; 2465 2466 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2467 corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0)); 2468 corr_val = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8)); 2469 2470 if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65) 2471 return 1; 2472 else 2473 return 0; 2474 2475 } 2476 2477 static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev) 2478 { 2479 u8 reg_a, reg_b; 2480 u16 count = 0; 2481 2482 rtw_write8(rtwdev, 0x522, 0xff); 2483 rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2); 2484 2485 do { 2486 reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000); 2487 reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000); 2488 udelay(2); 2489 count++; 2490 } while ((reg_a == 2 || reg_b == 2) && count < 2500); 2491 } 2492 2493 static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev) 2494 { 2495 rtw8822c_dpk_tx_pause(rtwdev); 2496 rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl); 2497 } 2498 2499 static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk) 2500 { 2501 if (is_do_dpk) 2502 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl); 2503 else 2504 rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl); 2505 } 2506 2507 static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev) 2508 { 2509 u8 path; 2510 2511 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 2512 rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0); 2513 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2514 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) 2515 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 2516 else 2517 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 2518 rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4); 2519 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3); 2520 } 2521 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2522 rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b); 2523 rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347); 2524 } 2525 2526 static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path) 2527 { 2528 u32 ori_txbb; 2529 2530 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017); 2531 ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK); 2532 2533 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1); 2534 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1); 2535 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_TX_OFFSET_VAL, 0x0); 2536 rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb); 2537 2538 if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) { 2539 rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_LB_ATT, 0x1); 2540 rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0); 2541 } else { 2542 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0); 2543 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6); 2544 rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1); 2545 rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0); 2546 } 2547 2548 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2549 rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1); 2550 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0); 2551 2552 if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80) 2553 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2); 2554 else 2555 rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1); 2556 2557 rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1); 2558 2559 usleep_range(100, 110); 2560 2561 return ori_txbb & 0x1f; 2562 } 2563 2564 static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path) 2565 { 2566 u16 cmd; 2567 u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0; 2568 2569 switch (action) { 2570 case RTW_DPK_GAIN_LOSS: 2571 cmd = 0x14 + path; 2572 break; 2573 case RTW_DPK_DO_DPK: 2574 cmd = 0x16 + path + bw; 2575 break; 2576 case RTW_DPK_DPK_ON: 2577 cmd = 0x1a + path; 2578 break; 2579 case RTW_DPK_DAGC: 2580 cmd = 0x1c + path + bw; 2581 break; 2582 default: 2583 return 0; 2584 } 2585 2586 return (cmd << 8) | 0x48; 2587 } 2588 2589 static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action) 2590 { 2591 u16 dpk_cmd; 2592 u8 result = 0; 2593 2594 rtw8822c_dpk_set_gnt_wl(rtwdev, true); 2595 2596 if (action == RTW_DPK_CAL_PWR) { 2597 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1); 2598 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0); 2599 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 2600 msleep(10); 2601 if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) { 2602 result = 1; 2603 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2604 } 2605 } else { 2606 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2607 0x8 | (path << 1)); 2608 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 2609 2610 dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path); 2611 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd); 2612 rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1); 2613 msleep(10); 2614 if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) { 2615 result = 1; 2616 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n"); 2617 } 2618 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 2619 0x8 | (path << 1)); 2620 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 2621 } 2622 2623 rtw8822c_dpk_set_gnt_wl(rtwdev, false); 2624 2625 rtw_write8(rtwdev, 0x1b10, 0x0); 2626 2627 return result; 2628 } 2629 2630 static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path) 2631 { 2632 u16 dgain; 2633 2634 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 2635 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0); 2636 2637 dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16)); 2638 2639 return dgain; 2640 } 2641 2642 static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path) 2643 { 2644 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2645 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0); 2646 rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1); 2647 udelay(15); 2648 2649 return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e); 2650 } 2651 2652 static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path) 2653 { 2654 u32 i_val, q_val; 2655 2656 rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1)); 2657 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2658 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001); 2659 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2660 rtw_write32(rtwdev, 0x1b4c, 0x00080000); 2661 2662 q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD); 2663 i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD); 2664 2665 if (i_val & BIT(15)) 2666 i_val = 0x10000 - i_val; 2667 if (q_val & BIT(15)) 2668 q_val = 0x10000 - q_val; 2669 2670 rtw_write32(rtwdev, 0x1b4c, 0x00000000); 2671 2672 return i_val * i_val + q_val * q_val; 2673 } 2674 2675 static u32 rtw8822c_psd_log2base(u32 val) 2676 { 2677 u32 tmp, val_integerd_b, tindex; 2678 u32 result, val_fractiond_b; 2679 u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174, 2680 151, 132, 115, 100, 86, 74, 62, 51, 2681 42, 32, 23, 15, 7, 0}; 2682 2683 if (val == 0) 2684 return 0; 2685 2686 val_integerd_b = __fls(val) + 1; 2687 2688 tmp = (val * 100) / (1 << val_integerd_b); 2689 tindex = tmp / 5; 2690 2691 if (tindex >= ARRAY_SIZE(table_fraction)) 2692 tindex = ARRAY_SIZE(table_fraction) - 1; 2693 2694 val_fractiond_b = table_fraction[tindex]; 2695 2696 result = val_integerd_b * 100 - val_fractiond_b; 2697 2698 return result; 2699 } 2700 2701 static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path) 2702 { 2703 u8 result; 2704 2705 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2706 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1); 2707 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000); 2708 2709 result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0); 2710 2711 rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0); 2712 2713 return result; 2714 } 2715 2716 static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path, 2717 u8 limited_pga) 2718 { 2719 u8 result = 0; 2720 u16 dgain; 2721 2722 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 2723 dgain = rtw8822c_dpk_dgain_read(rtwdev, path); 2724 2725 if (dgain > 1535 && !limited_pga) 2726 return RTW_DPK_GAIN_LESS; 2727 else if (dgain < 768 && !limited_pga) 2728 return RTW_DPK_GAIN_LARGE; 2729 else 2730 return result; 2731 } 2732 2733 static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path) 2734 { 2735 u32 loss, loss_db; 2736 2737 loss = rtw8822c_dpk_pas_read(rtwdev, path); 2738 if (loss < 0x4000000) 2739 return RTW_DPK_GL_LESS; 2740 loss_db = 3 * rtw8822c_psd_log2base(loss >> 13) - 3870; 2741 2742 if (loss_db > 1000) 2743 return RTW_DPK_GL_LARGE; 2744 else if (loss_db < 250) 2745 return RTW_DPK_GL_LESS; 2746 else 2747 return RTW_DPK_AGC_OUT; 2748 } 2749 2750 struct rtw8822c_dpk_data { 2751 u8 txbb; 2752 u8 pga; 2753 u8 limited_pga; 2754 u8 agc_cnt; 2755 bool loss_only; 2756 bool gain_only; 2757 u8 path; 2758 }; 2759 2760 static u8 rtw8822c_gain_check_state(struct rtw_dev *rtwdev, 2761 struct rtw8822c_dpk_data *data) 2762 { 2763 u8 state; 2764 2765 data->txbb = (u8)rtw_read_rf(rtwdev, data->path, RF_TX_GAIN, 2766 BIT_GAIN_TXBB); 2767 data->pga = (u8)rtw_read_rf(rtwdev, data->path, RF_MODE_TRXAGC, 2768 BIT_RXAGC); 2769 2770 if (data->loss_only) { 2771 state = RTW_DPK_LOSS_CHECK; 2772 goto check_end; 2773 } 2774 2775 state = rtw8822c_dpk_agc_gain_chk(rtwdev, data->path, 2776 data->limited_pga); 2777 if (state == RTW_DPK_GAIN_CHECK && data->gain_only) 2778 state = RTW_DPK_AGC_OUT; 2779 else if (state == RTW_DPK_GAIN_CHECK) 2780 state = RTW_DPK_LOSS_CHECK; 2781 2782 check_end: 2783 data->agc_cnt++; 2784 if (data->agc_cnt >= 6) 2785 state = RTW_DPK_AGC_OUT; 2786 2787 return state; 2788 } 2789 2790 static u8 rtw8822c_gain_large_state(struct rtw_dev *rtwdev, 2791 struct rtw8822c_dpk_data *data) 2792 { 2793 u8 pga = data->pga; 2794 2795 if (pga > 0xe) 2796 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2797 else if (pga > 0xb && pga < 0xf) 2798 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0); 2799 else if (pga < 0xc) 2800 data->limited_pga = 1; 2801 2802 return RTW_DPK_GAIN_CHECK; 2803 } 2804 2805 static u8 rtw8822c_gain_less_state(struct rtw_dev *rtwdev, 2806 struct rtw8822c_dpk_data *data) 2807 { 2808 u8 pga = data->pga; 2809 2810 if (pga < 0xc) 2811 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xc); 2812 else if (pga > 0xb && pga < 0xf) 2813 rtw_write_rf(rtwdev, data->path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf); 2814 else if (pga > 0xe) 2815 data->limited_pga = 1; 2816 2817 return RTW_DPK_GAIN_CHECK; 2818 } 2819 2820 static u8 rtw8822c_gl_state(struct rtw_dev *rtwdev, 2821 struct rtw8822c_dpk_data *data, u8 is_large) 2822 { 2823 u8 txbb_bound[] = {0x1f, 0}; 2824 2825 if (data->txbb == txbb_bound[is_large]) 2826 return RTW_DPK_AGC_OUT; 2827 2828 if (is_large == 1) 2829 data->txbb -= 2; 2830 else 2831 data->txbb += 3; 2832 2833 rtw_write_rf(rtwdev, data->path, RF_TX_GAIN, BIT_GAIN_TXBB, data->txbb); 2834 data->limited_pga = 0; 2835 2836 return RTW_DPK_GAIN_CHECK; 2837 } 2838 2839 static u8 rtw8822c_gl_large_state(struct rtw_dev *rtwdev, 2840 struct rtw8822c_dpk_data *data) 2841 { 2842 return rtw8822c_gl_state(rtwdev, data, 1); 2843 } 2844 2845 static u8 rtw8822c_gl_less_state(struct rtw_dev *rtwdev, 2846 struct rtw8822c_dpk_data *data) 2847 { 2848 return rtw8822c_gl_state(rtwdev, data, 0); 2849 } 2850 2851 static u8 rtw8822c_loss_check_state(struct rtw_dev *rtwdev, 2852 struct rtw8822c_dpk_data *data) 2853 { 2854 u8 path = data->path; 2855 u8 state; 2856 2857 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_GAIN_LOSS); 2858 state = rtw8822c_dpk_agc_loss_chk(rtwdev, path); 2859 2860 return state; 2861 } 2862 2863 static u8 (*dpk_state[])(struct rtw_dev *rtwdev, 2864 struct rtw8822c_dpk_data *data) = { 2865 rtw8822c_gain_check_state, rtw8822c_gain_large_state, 2866 rtw8822c_gain_less_state, rtw8822c_gl_large_state, 2867 rtw8822c_gl_less_state, rtw8822c_loss_check_state }; 2868 2869 static u8 rtw8822c_dpk_pas_agc(struct rtw_dev *rtwdev, u8 path, 2870 bool gain_only, bool loss_only) 2871 { 2872 struct rtw8822c_dpk_data data = {0}; 2873 u8 (*func)(struct rtw_dev *rtwdev, struct rtw8822c_dpk_data *data); 2874 u8 state = RTW_DPK_GAIN_CHECK; 2875 2876 data.loss_only = loss_only; 2877 data.gain_only = gain_only; 2878 data.path = path; 2879 2880 for (;;) { 2881 func = dpk_state[state]; 2882 state = func(rtwdev, &data); 2883 if (state == RTW_DPK_AGC_OUT) 2884 break; 2885 } 2886 2887 return data.txbb; 2888 } 2889 2890 static bool rtw8822c_dpk_coef_iq_check(struct rtw_dev *rtwdev, 2891 u16 coef_i, u16 coef_q) 2892 { 2893 if (coef_i == 0x1000 || coef_i == 0x0fff || 2894 coef_q == 0x1000 || coef_q == 0x0fff) 2895 return true; 2896 2897 return false; 2898 } 2899 2900 static u32 rtw8822c_dpk_coef_transfer(struct rtw_dev *rtwdev) 2901 { 2902 u32 reg = 0; 2903 u16 coef_i = 0, coef_q = 0; 2904 2905 reg = rtw_read32(rtwdev, REG_STAT_RPT); 2906 2907 coef_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD) & 0x1fff; 2908 coef_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD) & 0x1fff; 2909 2910 coef_q = ((0x2000 - coef_q) & 0x1fff) - 1; 2911 2912 reg = (coef_i << 16) | coef_q; 2913 2914 return reg; 2915 } 2916 2917 static const u32 rtw8822c_dpk_get_coef_tbl[] = { 2918 0x000400f0, 0x040400f0, 0x080400f0, 0x010400f0, 0x050400f0, 2919 0x090400f0, 0x020400f0, 0x060400f0, 0x0a0400f0, 0x030400f0, 2920 0x070400f0, 0x0b0400f0, 0x0c0400f0, 0x100400f0, 0x0d0400f0, 2921 0x110400f0, 0x0e0400f0, 0x120400f0, 0x0f0400f0, 0x130400f0, 2922 }; 2923 2924 static void rtw8822c_dpk_coef_tbl_apply(struct rtw_dev *rtwdev, u8 path) 2925 { 2926 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2927 int i; 2928 2929 for (i = 0; i < 20; i++) { 2930 rtw_write32(rtwdev, REG_RXSRAM_CTL, 2931 rtw8822c_dpk_get_coef_tbl[i]); 2932 dpk_info->coef[path][i] = rtw8822c_dpk_coef_transfer(rtwdev); 2933 } 2934 } 2935 2936 static void rtw8822c_dpk_get_coef(struct rtw_dev *rtwdev, u8 path) 2937 { 2938 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2939 2940 if (path == RF_PATH_A) { 2941 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x0); 2942 rtw_write32(rtwdev, REG_DPD_CTL0_S0, 0x30000080); 2943 } else if (path == RF_PATH_B) { 2944 rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(24), 0x1); 2945 rtw_write32(rtwdev, REG_DPD_CTL0_S1, 0x30000080); 2946 } 2947 2948 rtw8822c_dpk_coef_tbl_apply(rtwdev, path); 2949 } 2950 2951 static u8 rtw8822c_dpk_coef_read(struct rtw_dev *rtwdev, u8 path) 2952 { 2953 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2954 u8 addr, result = 1; 2955 u16 coef_i, coef_q; 2956 2957 for (addr = 0; addr < 20; addr++) { 2958 coef_i = FIELD_GET(0x1fff0000, dpk_info->coef[path][addr]); 2959 coef_q = FIELD_GET(0x1fff, dpk_info->coef[path][addr]); 2960 2961 if (rtw8822c_dpk_coef_iq_check(rtwdev, coef_i, coef_q)) { 2962 result = 0; 2963 break; 2964 } 2965 } 2966 return result; 2967 } 2968 2969 static void rtw8822c_dpk_coef_write(struct rtw_dev *rtwdev, u8 path, u8 result) 2970 { 2971 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2972 u16 reg[DPK_RF_PATH_NUM] = {0x1b0c, 0x1b64}; 2973 u32 coef; 2974 u8 addr; 2975 2976 rtw_write32(rtwdev, REG_NCTL0, 0x0000000c); 2977 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 2978 2979 for (addr = 0; addr < 20; addr++) { 2980 if (result == 0) { 2981 if (addr == 3) 2982 coef = 0x04001fff; 2983 else 2984 coef = 0x00001fff; 2985 } else { 2986 coef = dpk_info->coef[path][addr]; 2987 } 2988 rtw_write32(rtwdev, reg[path] + addr * 4, coef); 2989 } 2990 } 2991 2992 static void rtw8822c_dpk_fill_result(struct rtw_dev *rtwdev, u32 dpk_txagc, 2993 u8 path, u8 result) 2994 { 2995 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 2996 2997 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 2998 2999 if (result) 3000 rtw_write8(rtwdev, REG_DPD_AGC, (u8)(dpk_txagc - 6)); 3001 else 3002 rtw_write8(rtwdev, REG_DPD_AGC, 0x00); 3003 3004 dpk_info->result[path] = result; 3005 dpk_info->dpk_txagc[path] = rtw_read8(rtwdev, REG_DPD_AGC); 3006 3007 rtw8822c_dpk_coef_write(rtwdev, path, result); 3008 } 3009 3010 static u32 rtw8822c_dpk_gainloss(struct rtw_dev *rtwdev, u8 path) 3011 { 3012 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3013 u8 tx_agc, tx_bb, ori_txbb, ori_txagc, tx_agc_search, t1, t2; 3014 3015 ori_txbb = rtw8822c_dpk_rf_setting(rtwdev, path); 3016 ori_txagc = (u8)rtw_read_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_TXAGC); 3017 3018 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3019 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3020 rtw8822c_dpk_dgain_read(rtwdev, path); 3021 3022 if (rtw8822c_dpk_dc_corr_check(rtwdev, path)) { 3023 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3024 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC); 3025 rtw8822c_dpk_dc_corr_check(rtwdev, path); 3026 } 3027 3028 t1 = rtw8822c_dpk_thermal_read(rtwdev, path); 3029 tx_bb = rtw8822c_dpk_pas_agc(rtwdev, path, false, true); 3030 tx_agc_search = rtw8822c_dpk_gainloss_result(rtwdev, path); 3031 3032 if (tx_bb < tx_agc_search) 3033 tx_bb = 0; 3034 else 3035 tx_bb = tx_bb - tx_agc_search; 3036 3037 rtw_write_rf(rtwdev, path, RF_TX_GAIN, BIT_GAIN_TXBB, tx_bb); 3038 3039 tx_agc = ori_txagc - (ori_txbb - tx_bb); 3040 3041 t2 = rtw8822c_dpk_thermal_read(rtwdev, path); 3042 3043 dpk_info->thermal_dpk_delta[path] = abs(t2 - t1); 3044 3045 return tx_agc; 3046 } 3047 3048 static u8 rtw8822c_dpk_by_path(struct rtw_dev *rtwdev, u32 tx_agc, u8 path) 3049 { 3050 u8 result; 3051 3052 result = rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DO_DPK); 3053 3054 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3055 3056 result = result | (u8)rtw_read32_mask(rtwdev, REG_DPD_CTL1_S0, BIT(26)); 3057 3058 rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x33e14); 3059 3060 rtw8822c_dpk_get_coef(rtwdev, path); 3061 3062 return result; 3063 } 3064 3065 static void rtw8822c_dpk_cal_gs(struct rtw_dev *rtwdev, u8 path) 3066 { 3067 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3068 u32 tmp_gs = 0; 3069 3070 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3071 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_BYPASS_DPD, 0x0); 3072 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3073 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9); 3074 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x1); 3075 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3076 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0xf); 3077 3078 if (path == RF_PATH_A) { 3079 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3080 0x1066680); 3081 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 0x1); 3082 } else { 3083 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3084 0x1066680); 3085 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 0x1); 3086 } 3087 3088 if (dpk_info->dpk_bw == DPK_CHANNEL_WIDTH_80) { 3089 rtw_write32(rtwdev, REG_DPD_CTL16, 0x80001310); 3090 rtw_write32(rtwdev, REG_DPD_CTL16, 0x00001310); 3091 rtw_write32(rtwdev, REG_DPD_CTL16, 0x810000db); 3092 rtw_write32(rtwdev, REG_DPD_CTL16, 0x010000db); 3093 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3094 rtw_write32(rtwdev, REG_DPD_CTL15, 3095 0x05020000 | (BIT(path) << 28)); 3096 } else { 3097 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8200190c); 3098 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0200190c); 3099 rtw_write32(rtwdev, REG_DPD_CTL16, 0x8301ee14); 3100 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0301ee14); 3101 rtw_write32(rtwdev, REG_DPD_CTL16, 0x0000b428); 3102 rtw_write32(rtwdev, REG_DPD_CTL15, 3103 0x05020008 | (BIT(path) << 28)); 3104 } 3105 3106 rtw_write32_mask(rtwdev, REG_DPD_CTL0, MASKBYTE3, 0x8 | path); 3107 3108 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_CAL_PWR); 3109 3110 rtw_write32_mask(rtwdev, REG_DPD_CTL15, MASKBYTE3, 0x0); 3111 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3112 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0); 3113 rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_INNER_LB, 0x0); 3114 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3115 3116 if (path == RF_PATH_A) 3117 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 0x5b); 3118 else 3119 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 0x5b); 3120 3121 rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0); 3122 3123 tmp_gs = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, BIT_RPT_DGAIN); 3124 tmp_gs = (tmp_gs * 910) >> 10; 3125 tmp_gs = DIV_ROUND_CLOSEST(tmp_gs, 10); 3126 3127 if (path == RF_PATH_A) 3128 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, tmp_gs); 3129 else 3130 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, tmp_gs); 3131 3132 dpk_info->dpk_gs[path] = tmp_gs; 3133 } 3134 3135 static void rtw8822c_dpk_cal_coef1(struct rtw_dev *rtwdev) 3136 { 3137 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3138 u32 offset[DPK_RF_PATH_NUM] = {0, 0x58}; 3139 u32 i_scaling; 3140 u8 path; 3141 3142 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3143 rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0); 3144 rtw_write32(rtwdev, REG_NCTL0, 0x00001148); 3145 rtw_write32(rtwdev, REG_NCTL0, 0x00001149); 3146 3147 check_hw_ready(rtwdev, 0x2d9c, MASKBYTE0, 0x55); 3148 3149 rtw_write8(rtwdev, 0x1b10, 0x0); 3150 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x0000000c); 3151 3152 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3153 i_scaling = 0x16c00 / dpk_info->dpk_gs[path]; 3154 3155 rtw_write32_mask(rtwdev, 0x1b18 + offset[path], MASKHWORD, 3156 i_scaling); 3157 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3158 GENMASK(31, 28), 0x9); 3159 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3160 GENMASK(31, 28), 0x1); 3161 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0 + offset[path], 3162 GENMASK(31, 28), 0x0); 3163 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0 + offset[path], 3164 BIT(14), 0x0); 3165 } 3166 } 3167 3168 static void rtw8822c_dpk_on(struct rtw_dev *rtwdev, u8 path) 3169 { 3170 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3171 3172 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3173 3174 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1)); 3175 rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0); 3176 3177 if (test_bit(path, dpk_info->dpk_path_ok)) 3178 rtw8822c_dpk_cal_gs(rtwdev, path); 3179 } 3180 3181 static bool rtw8822c_dpk_check_pass(struct rtw_dev *rtwdev, bool is_fail, 3182 u32 dpk_txagc, u8 path) 3183 { 3184 bool result; 3185 3186 if (!is_fail) { 3187 if (rtw8822c_dpk_coef_read(rtwdev, path)) 3188 result = true; 3189 else 3190 result = false; 3191 } else { 3192 result = false; 3193 } 3194 3195 rtw8822c_dpk_fill_result(rtwdev, dpk_txagc, path, result); 3196 3197 return result; 3198 } 3199 3200 static void rtw8822c_dpk_result_reset(struct rtw_dev *rtwdev) 3201 { 3202 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3203 u8 path; 3204 3205 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3206 clear_bit(path, dpk_info->dpk_path_ok); 3207 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3208 0x8 | (path << 1)); 3209 rtw_write32_mask(rtwdev, 0x1b58, 0x0000007f, 0x0); 3210 3211 dpk_info->dpk_txagc[path] = 0; 3212 dpk_info->result[path] = 0; 3213 dpk_info->dpk_gs[path] = 0x5b; 3214 dpk_info->pre_pwsf[path] = 0; 3215 dpk_info->thermal_dpk[path] = rtw8822c_dpk_thermal_read(rtwdev, 3216 path); 3217 } 3218 } 3219 3220 static void rtw8822c_dpk_calibrate(struct rtw_dev *rtwdev, u8 path) 3221 { 3222 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3223 u32 dpk_txagc; 3224 u8 dpk_fail; 3225 3226 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk start\n", path); 3227 3228 dpk_txagc = rtw8822c_dpk_gainloss(rtwdev, path); 3229 3230 dpk_fail = rtw8822c_dpk_by_path(rtwdev, dpk_txagc, path); 3231 3232 if (!rtw8822c_dpk_check_pass(rtwdev, dpk_fail, dpk_txagc, path)) 3233 rtw_err(rtwdev, "failed to do dpk calibration\n"); 3234 3235 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] s%d dpk finish\n", path); 3236 3237 if (dpk_info->result[path]) 3238 set_bit(path, dpk_info->dpk_path_ok); 3239 } 3240 3241 static void rtw8822c_dpk_path_select(struct rtw_dev *rtwdev) 3242 { 3243 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_A); 3244 rtw8822c_dpk_calibrate(rtwdev, RF_PATH_B); 3245 rtw8822c_dpk_on(rtwdev, RF_PATH_A); 3246 rtw8822c_dpk_on(rtwdev, RF_PATH_B); 3247 rtw8822c_dpk_cal_coef1(rtwdev); 3248 } 3249 3250 static void rtw8822c_dpk_enable_disable(struct rtw_dev *rtwdev) 3251 { 3252 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3253 u32 mask = BIT(15) | BIT(14); 3254 3255 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3256 3257 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_DPD_EN, 3258 dpk_info->is_dpk_pwr_on); 3259 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, BIT_DPD_EN, 3260 dpk_info->is_dpk_pwr_on); 3261 3262 if (test_bit(RF_PATH_A, dpk_info->dpk_path_ok)) { 3263 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, mask, 0x0); 3264 rtw_write8(rtwdev, REG_DPD_CTL0_S0, dpk_info->dpk_gs[RF_PATH_A]); 3265 } 3266 if (test_bit(RF_PATH_B, dpk_info->dpk_path_ok)) { 3267 rtw_write32_mask(rtwdev, REG_DPD_CTL1_S1, mask, 0x0); 3268 rtw_write8(rtwdev, REG_DPD_CTL0_S1, dpk_info->dpk_gs[RF_PATH_B]); 3269 } 3270 } 3271 3272 static void rtw8822c_dpk_reload_data(struct rtw_dev *rtwdev) 3273 { 3274 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3275 u8 path; 3276 3277 if (!test_bit(RF_PATH_A, dpk_info->dpk_path_ok) && 3278 !test_bit(RF_PATH_B, dpk_info->dpk_path_ok) && 3279 dpk_info->dpk_ch == 0) 3280 return; 3281 3282 for (path = 0; path < rtwdev->hal.rf_path_num; path++) { 3283 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3284 0x8 | (path << 1)); 3285 if (dpk_info->dpk_band == RTW_BAND_2G) 3286 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f100000); 3287 else 3288 rtw_write32(rtwdev, REG_DPD_LUT3, 0x1f0d0000); 3289 3290 rtw_write8(rtwdev, REG_DPD_AGC, dpk_info->dpk_txagc[path]); 3291 3292 rtw8822c_dpk_coef_write(rtwdev, path, 3293 test_bit(path, dpk_info->dpk_path_ok)); 3294 3295 rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DPK_ON); 3296 3297 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc); 3298 3299 if (path == RF_PATH_A) 3300 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S0, BIT_GS_PWSF, 3301 dpk_info->dpk_gs[path]); 3302 else 3303 rtw_write32_mask(rtwdev, REG_DPD_CTL0_S1, BIT_GS_PWSF, 3304 dpk_info->dpk_gs[path]); 3305 } 3306 rtw8822c_dpk_cal_coef1(rtwdev); 3307 } 3308 3309 static bool rtw8822c_dpk_reload(struct rtw_dev *rtwdev) 3310 { 3311 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3312 u8 channel; 3313 3314 dpk_info->is_reload = false; 3315 3316 channel = (u8)(rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK) & 0xff); 3317 3318 if (channel == dpk_info->dpk_ch) { 3319 rtw_dbg(rtwdev, RTW_DBG_RFK, 3320 "[DPK] DPK reload for CH%d!!\n", dpk_info->dpk_ch); 3321 rtw8822c_dpk_reload_data(rtwdev); 3322 dpk_info->is_reload = true; 3323 } 3324 3325 return dpk_info->is_reload; 3326 } 3327 3328 static void rtw8822c_do_dpk(struct rtw_dev *rtwdev) 3329 { 3330 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3331 struct rtw_backup_info bckp[DPK_BB_REG_NUM]; 3332 u32 rf_reg_backup[DPK_RF_REG_NUM][DPK_RF_PATH_NUM]; 3333 u32 bb_reg[DPK_BB_REG_NUM] = { 3334 0x520, 0x820, 0x824, 0x1c3c, 0x1d58, 0x1864, 3335 0x4164, 0x180c, 0x410c, 0x186c, 0x416c, 3336 0x1a14, 0x1e70, 0x80c, 0x1d70, 0x1e7c, 0x18a4, 0x41a4}; 3337 u32 rf_reg[DPK_RF_REG_NUM] = { 3338 0x0, 0x1a, 0x55, 0x63, 0x87, 0x8f, 0xde}; 3339 u8 path; 3340 3341 if (!dpk_info->is_dpk_pwr_on) { 3342 rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] Skip DPK due to DPD PWR off\n"); 3343 return; 3344 } else if (rtw8822c_dpk_reload(rtwdev)) { 3345 return; 3346 } 3347 3348 for (path = RF_PATH_A; path < DPK_RF_PATH_NUM; path++) 3349 ewma_thermal_init(&dpk_info->avg_thermal[path]); 3350 3351 rtw8822c_dpk_information(rtwdev); 3352 3353 rtw8822c_dpk_backup_registers(rtwdev, bb_reg, DPK_BB_REG_NUM, bckp); 3354 rtw8822c_dpk_backup_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3355 3356 rtw8822c_dpk_mac_bb_setting(rtwdev); 3357 rtw8822c_dpk_afe_setting(rtwdev, true); 3358 rtw8822c_dpk_pre_setting(rtwdev); 3359 rtw8822c_dpk_result_reset(rtwdev); 3360 rtw8822c_dpk_path_select(rtwdev); 3361 rtw8822c_dpk_afe_setting(rtwdev, false); 3362 rtw8822c_dpk_enable_disable(rtwdev); 3363 3364 rtw8822c_dpk_reload_rf_registers(rtwdev, rf_reg, rf_reg_backup); 3365 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 3366 rtw8822c_dpk_rxbb_dc_cal(rtwdev, path); 3367 rtw8822c_dpk_restore_registers(rtwdev, DPK_BB_REG_NUM, bckp); 3368 } 3369 3370 static void rtw8822c_phy_calibration(struct rtw_dev *rtwdev) 3371 { 3372 rtw8822c_do_iqk(rtwdev); 3373 rtw8822c_do_dpk(rtwdev); 3374 } 3375 3376 static void rtw8822c_dpk_track(struct rtw_dev *rtwdev) 3377 { 3378 struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info; 3379 u8 path; 3380 u8 thermal_value[DPK_RF_PATH_NUM] = {0}; 3381 s8 offset[DPK_RF_PATH_NUM], delta_dpk[DPK_RF_PATH_NUM]; 3382 3383 if (dpk_info->thermal_dpk[0] == 0 && dpk_info->thermal_dpk[1] == 0) 3384 return; 3385 3386 for (path = 0; path < DPK_RF_PATH_NUM; path++) { 3387 thermal_value[path] = rtw8822c_dpk_thermal_read(rtwdev, path); 3388 ewma_thermal_add(&dpk_info->avg_thermal[path], 3389 thermal_value[path]); 3390 thermal_value[path] = 3391 ewma_thermal_read(&dpk_info->avg_thermal[path]); 3392 delta_dpk[path] = dpk_info->thermal_dpk[path] - 3393 thermal_value[path]; 3394 offset[path] = delta_dpk[path] - 3395 dpk_info->thermal_dpk_delta[path]; 3396 offset[path] &= 0x7f; 3397 3398 if (offset[path] != dpk_info->pre_pwsf[path]) { 3399 rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 3400 0x8 | (path << 1)); 3401 rtw_write32_mask(rtwdev, 0x1b58, GENMASK(6, 0), 3402 offset[path]); 3403 dpk_info->pre_pwsf[path] = offset[path]; 3404 } 3405 } 3406 } 3407 3408 static const struct rtw_phy_cck_pd_reg 3409 rtw8822c_cck_pd_reg[RTW_CHANNEL_WIDTH_40 + 1][RTW_RF_PATH_MAX] = { 3410 { 3411 {0x1ac8, 0x00ff, 0x1ad0, 0x01f}, 3412 {0x1ac8, 0xff00, 0x1ad0, 0x3e0} 3413 }, 3414 { 3415 {0x1acc, 0x00ff, 0x1ad0, 0x01F00000}, 3416 {0x1acc, 0xff00, 0x1ad0, 0x3E000000} 3417 }, 3418 }; 3419 3420 #define RTW_CCK_PD_MAX 255 3421 #define RTW_CCK_CS_MAX 31 3422 #define RTW_CCK_CS_ERR1 27 3423 #define RTW_CCK_CS_ERR2 29 3424 static void 3425 rtw8822c_phy_cck_pd_set_reg(struct rtw_dev *rtwdev, 3426 s8 pd_diff, s8 cs_diff, u8 bw, u8 nrx) 3427 { 3428 u32 pd, cs; 3429 3430 if (WARN_ON(bw > RTW_CHANNEL_WIDTH_40 || nrx >= RTW_RF_PATH_MAX)) 3431 return; 3432 3433 pd = rtw_read32_mask(rtwdev, 3434 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3435 rtw8822c_cck_pd_reg[bw][nrx].mask_pd); 3436 cs = rtw_read32_mask(rtwdev, 3437 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3438 rtw8822c_cck_pd_reg[bw][nrx].mask_cs); 3439 pd += pd_diff; 3440 cs += cs_diff; 3441 if (pd > RTW_CCK_PD_MAX) 3442 pd = RTW_CCK_PD_MAX; 3443 if (cs == RTW_CCK_CS_ERR1 || cs == RTW_CCK_CS_ERR2) 3444 cs++; 3445 else if (cs > RTW_CCK_CS_MAX) 3446 cs = RTW_CCK_CS_MAX; 3447 rtw_write32_mask(rtwdev, 3448 rtw8822c_cck_pd_reg[bw][nrx].reg_pd, 3449 rtw8822c_cck_pd_reg[bw][nrx].mask_pd, 3450 pd); 3451 rtw_write32_mask(rtwdev, 3452 rtw8822c_cck_pd_reg[bw][nrx].reg_cs, 3453 rtw8822c_cck_pd_reg[bw][nrx].mask_cs, 3454 cs); 3455 } 3456 3457 static void rtw8822c_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl) 3458 { 3459 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3460 s8 pd_lvl[CCK_PD_LV_MAX] = {0, 2, 4, 6, 8}; 3461 s8 cs_lvl[CCK_PD_LV_MAX] = {0, 2, 2, 2, 4}; 3462 u8 cur_lvl; 3463 u8 nrx, bw; 3464 3465 nrx = (u8)rtw_read32_mask(rtwdev, 0x1a2c, 0x60000); 3466 bw = (u8)rtw_read32_mask(rtwdev, 0x9b0, 0xc); 3467 3468 if (dm_info->cck_pd_lv[bw][nrx] == new_lvl) 3469 return; 3470 3471 cur_lvl = dm_info->cck_pd_lv[bw][nrx]; 3472 3473 /* update cck pd info */ 3474 dm_info->cck_fa_avg = CCK_FA_AVG_RESET; 3475 3476 rtw8822c_phy_cck_pd_set_reg(rtwdev, 3477 pd_lvl[new_lvl] - pd_lvl[cur_lvl], 3478 cs_lvl[new_lvl] - cs_lvl[cur_lvl], 3479 bw, nrx); 3480 dm_info->cck_pd_lv[bw][nrx] = new_lvl; 3481 } 3482 3483 #define PWR_TRACK_MASK 0x7f 3484 static void rtw8822c_pwrtrack_set(struct rtw_dev *rtwdev, u8 rf_path) 3485 { 3486 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3487 3488 switch (rf_path) { 3489 case RF_PATH_A: 3490 rtw_write32_mask(rtwdev, 0x18a0, PWR_TRACK_MASK, 3491 dm_info->delta_power_index[rf_path]); 3492 break; 3493 case RF_PATH_B: 3494 rtw_write32_mask(rtwdev, 0x41a0, PWR_TRACK_MASK, 3495 dm_info->delta_power_index[rf_path]); 3496 break; 3497 default: 3498 break; 3499 } 3500 } 3501 3502 static void rtw8822c_pwr_track_path(struct rtw_dev *rtwdev, 3503 struct rtw_swing_table *swing_table, 3504 u8 path) 3505 { 3506 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3507 u8 thermal_value, delta; 3508 3509 if (rtwdev->efuse.thermal_meter[path] == 0xff) 3510 return; 3511 3512 thermal_value = rtw_read_rf(rtwdev, path, RF_T_METER, 0x7e); 3513 3514 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, path); 3515 3516 delta = rtw_phy_pwrtrack_get_delta(rtwdev, path); 3517 3518 dm_info->delta_power_index[path] = 3519 rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, path, path, 3520 delta); 3521 3522 rtw8822c_pwrtrack_set(rtwdev, path); 3523 } 3524 3525 static void __rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3526 { 3527 struct rtw_swing_table swing_table; 3528 u8 i; 3529 3530 rtw_phy_config_swing_table(rtwdev, &swing_table); 3531 3532 for (i = 0; i < rtwdev->hal.rf_path_num; i++) 3533 rtw8822c_pwr_track_path(rtwdev, &swing_table, i); 3534 3535 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 3536 rtw8822c_do_iqk(rtwdev); 3537 } 3538 3539 static void rtw8822c_pwr_track(struct rtw_dev *rtwdev) 3540 { 3541 struct rtw_efuse *efuse = &rtwdev->efuse; 3542 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 3543 3544 if (efuse->power_track_type != 0) 3545 return; 3546 3547 if (!dm_info->pwr_trk_triggered) { 3548 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3549 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x00); 3550 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, BIT(19), 0x01); 3551 3552 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3553 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x00); 3554 rtw_write_rf(rtwdev, RF_PATH_B, RF_T_METER, BIT(19), 0x01); 3555 3556 dm_info->pwr_trk_triggered = true; 3557 return; 3558 } 3559 3560 __rtw8822c_pwr_track(rtwdev); 3561 dm_info->pwr_trk_triggered = false; 3562 } 3563 3564 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822c[] = { 3565 {0x0086, 3566 RTW_PWR_CUT_ALL_MSK, 3567 RTW_PWR_INTF_SDIO_MSK, 3568 RTW_PWR_ADDR_SDIO, 3569 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3570 {0x0086, 3571 RTW_PWR_CUT_ALL_MSK, 3572 RTW_PWR_INTF_SDIO_MSK, 3573 RTW_PWR_ADDR_SDIO, 3574 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3575 {0x002E, 3576 RTW_PWR_CUT_ALL_MSK, 3577 RTW_PWR_INTF_ALL_MSK, 3578 RTW_PWR_ADDR_MAC, 3579 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3580 {0x002D, 3581 RTW_PWR_CUT_ALL_MSK, 3582 RTW_PWR_INTF_ALL_MSK, 3583 RTW_PWR_ADDR_MAC, 3584 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3585 {0x007F, 3586 RTW_PWR_CUT_ALL_MSK, 3587 RTW_PWR_INTF_ALL_MSK, 3588 RTW_PWR_ADDR_MAC, 3589 RTW_PWR_CMD_WRITE, BIT(7), 0}, 3590 {0x004A, 3591 RTW_PWR_CUT_ALL_MSK, 3592 RTW_PWR_INTF_USB_MSK, 3593 RTW_PWR_ADDR_MAC, 3594 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3595 {0x0005, 3596 RTW_PWR_CUT_ALL_MSK, 3597 RTW_PWR_INTF_ALL_MSK, 3598 RTW_PWR_ADDR_MAC, 3599 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 3600 {0xFFFF, 3601 RTW_PWR_CUT_ALL_MSK, 3602 RTW_PWR_INTF_ALL_MSK, 3603 0, 3604 RTW_PWR_CMD_END, 0, 0}, 3605 }; 3606 3607 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822c[] = { 3608 {0x0000, 3609 RTW_PWR_CUT_ALL_MSK, 3610 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3611 RTW_PWR_ADDR_MAC, 3612 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3613 {0x0005, 3614 RTW_PWR_CUT_ALL_MSK, 3615 RTW_PWR_INTF_ALL_MSK, 3616 RTW_PWR_ADDR_MAC, 3617 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 3618 {0x0075, 3619 RTW_PWR_CUT_ALL_MSK, 3620 RTW_PWR_INTF_PCI_MSK, 3621 RTW_PWR_ADDR_MAC, 3622 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3623 {0x0006, 3624 RTW_PWR_CUT_ALL_MSK, 3625 RTW_PWR_INTF_ALL_MSK, 3626 RTW_PWR_ADDR_MAC, 3627 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 3628 {0x0075, 3629 RTW_PWR_CUT_ALL_MSK, 3630 RTW_PWR_INTF_PCI_MSK, 3631 RTW_PWR_ADDR_MAC, 3632 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3633 {0xFF1A, 3634 RTW_PWR_CUT_ALL_MSK, 3635 RTW_PWR_INTF_USB_MSK, 3636 RTW_PWR_ADDR_MAC, 3637 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3638 {0x002E, 3639 RTW_PWR_CUT_ALL_MSK, 3640 RTW_PWR_INTF_ALL_MSK, 3641 RTW_PWR_ADDR_MAC, 3642 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3643 {0x0006, 3644 RTW_PWR_CUT_ALL_MSK, 3645 RTW_PWR_INTF_ALL_MSK, 3646 RTW_PWR_ADDR_MAC, 3647 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3648 {0x0005, 3649 RTW_PWR_CUT_ALL_MSK, 3650 RTW_PWR_INTF_ALL_MSK, 3651 RTW_PWR_ADDR_MAC, 3652 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 3653 {0x1018, 3654 RTW_PWR_CUT_ALL_MSK, 3655 RTW_PWR_INTF_ALL_MSK, 3656 RTW_PWR_ADDR_MAC, 3657 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3658 {0x0005, 3659 RTW_PWR_CUT_ALL_MSK, 3660 RTW_PWR_INTF_ALL_MSK, 3661 RTW_PWR_ADDR_MAC, 3662 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3663 {0x0005, 3664 RTW_PWR_CUT_ALL_MSK, 3665 RTW_PWR_INTF_ALL_MSK, 3666 RTW_PWR_ADDR_MAC, 3667 RTW_PWR_CMD_POLLING, BIT(0), 0}, 3668 {0x0074, 3669 RTW_PWR_CUT_ALL_MSK, 3670 RTW_PWR_INTF_PCI_MSK, 3671 RTW_PWR_ADDR_MAC, 3672 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3673 {0x0071, 3674 RTW_PWR_CUT_ALL_MSK, 3675 RTW_PWR_INTF_PCI_MSK, 3676 RTW_PWR_ADDR_MAC, 3677 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3678 {0x0062, 3679 RTW_PWR_CUT_ALL_MSK, 3680 RTW_PWR_INTF_PCI_MSK, 3681 RTW_PWR_ADDR_MAC, 3682 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 3683 (BIT(7) | BIT(6) | BIT(5))}, 3684 {0x0061, 3685 RTW_PWR_CUT_ALL_MSK, 3686 RTW_PWR_INTF_PCI_MSK, 3687 RTW_PWR_ADDR_MAC, 3688 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0}, 3689 {0x001F, 3690 RTW_PWR_CUT_ALL_MSK, 3691 RTW_PWR_INTF_ALL_MSK, 3692 RTW_PWR_ADDR_MAC, 3693 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3694 {0x00EF, 3695 RTW_PWR_CUT_ALL_MSK, 3696 RTW_PWR_INTF_ALL_MSK, 3697 RTW_PWR_ADDR_MAC, 3698 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6)), BIT(7)}, 3699 {0x1045, 3700 RTW_PWR_CUT_ALL_MSK, 3701 RTW_PWR_INTF_ALL_MSK, 3702 RTW_PWR_ADDR_MAC, 3703 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 3704 {0x0010, 3705 RTW_PWR_CUT_ALL_MSK, 3706 RTW_PWR_INTF_ALL_MSK, 3707 RTW_PWR_ADDR_MAC, 3708 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3709 {0x1064, 3710 RTW_PWR_CUT_ALL_MSK, 3711 RTW_PWR_INTF_ALL_MSK, 3712 RTW_PWR_ADDR_MAC, 3713 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3714 {0xFFFF, 3715 RTW_PWR_CUT_ALL_MSK, 3716 RTW_PWR_INTF_ALL_MSK, 3717 0, 3718 RTW_PWR_CMD_END, 0, 0}, 3719 }; 3720 3721 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822c[] = { 3722 {0x0093, 3723 RTW_PWR_CUT_ALL_MSK, 3724 RTW_PWR_INTF_ALL_MSK, 3725 RTW_PWR_ADDR_MAC, 3726 RTW_PWR_CMD_WRITE, BIT(3), 0}, 3727 {0x001F, 3728 RTW_PWR_CUT_ALL_MSK, 3729 RTW_PWR_INTF_ALL_MSK, 3730 RTW_PWR_ADDR_MAC, 3731 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3732 {0x00EF, 3733 RTW_PWR_CUT_ALL_MSK, 3734 RTW_PWR_INTF_ALL_MSK, 3735 RTW_PWR_ADDR_MAC, 3736 RTW_PWR_CMD_WRITE, 0xFF, 0}, 3737 {0x1045, 3738 RTW_PWR_CUT_ALL_MSK, 3739 RTW_PWR_INTF_ALL_MSK, 3740 RTW_PWR_ADDR_MAC, 3741 RTW_PWR_CMD_WRITE, BIT(4), 0}, 3742 {0xFF1A, 3743 RTW_PWR_CUT_ALL_MSK, 3744 RTW_PWR_INTF_USB_MSK, 3745 RTW_PWR_ADDR_MAC, 3746 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 3747 {0x0049, 3748 RTW_PWR_CUT_ALL_MSK, 3749 RTW_PWR_INTF_ALL_MSK, 3750 RTW_PWR_ADDR_MAC, 3751 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3752 {0x0006, 3753 RTW_PWR_CUT_ALL_MSK, 3754 RTW_PWR_INTF_ALL_MSK, 3755 RTW_PWR_ADDR_MAC, 3756 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3757 {0x0002, 3758 RTW_PWR_CUT_ALL_MSK, 3759 RTW_PWR_INTF_ALL_MSK, 3760 RTW_PWR_ADDR_MAC, 3761 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3762 {0x0005, 3763 RTW_PWR_CUT_ALL_MSK, 3764 RTW_PWR_INTF_ALL_MSK, 3765 RTW_PWR_ADDR_MAC, 3766 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 3767 {0x0005, 3768 RTW_PWR_CUT_ALL_MSK, 3769 RTW_PWR_INTF_ALL_MSK, 3770 RTW_PWR_ADDR_MAC, 3771 RTW_PWR_CMD_POLLING, BIT(1), 0}, 3772 {0x0000, 3773 RTW_PWR_CUT_ALL_MSK, 3774 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3775 RTW_PWR_ADDR_MAC, 3776 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 3777 {0xFFFF, 3778 RTW_PWR_CUT_ALL_MSK, 3779 RTW_PWR_INTF_ALL_MSK, 3780 0, 3781 RTW_PWR_CMD_END, 0, 0}, 3782 }; 3783 3784 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822c[] = { 3785 {0x0005, 3786 RTW_PWR_CUT_ALL_MSK, 3787 RTW_PWR_INTF_SDIO_MSK, 3788 RTW_PWR_ADDR_MAC, 3789 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 3790 {0x0007, 3791 RTW_PWR_CUT_ALL_MSK, 3792 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3793 RTW_PWR_ADDR_MAC, 3794 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 3795 {0x0067, 3796 RTW_PWR_CUT_ALL_MSK, 3797 RTW_PWR_INTF_ALL_MSK, 3798 RTW_PWR_ADDR_MAC, 3799 RTW_PWR_CMD_WRITE, BIT(5), 0}, 3800 {0x004A, 3801 RTW_PWR_CUT_ALL_MSK, 3802 RTW_PWR_INTF_USB_MSK, 3803 RTW_PWR_ADDR_MAC, 3804 RTW_PWR_CMD_WRITE, BIT(0), 0}, 3805 {0x0081, 3806 RTW_PWR_CUT_ALL_MSK, 3807 RTW_PWR_INTF_ALL_MSK, 3808 RTW_PWR_ADDR_MAC, 3809 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 3810 {0x0090, 3811 RTW_PWR_CUT_ALL_MSK, 3812 RTW_PWR_INTF_ALL_MSK, 3813 RTW_PWR_ADDR_MAC, 3814 RTW_PWR_CMD_WRITE, BIT(1), 0}, 3815 {0x0092, 3816 RTW_PWR_CUT_ALL_MSK, 3817 RTW_PWR_INTF_PCI_MSK, 3818 RTW_PWR_ADDR_MAC, 3819 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 3820 {0x0093, 3821 RTW_PWR_CUT_ALL_MSK, 3822 RTW_PWR_INTF_PCI_MSK, 3823 RTW_PWR_ADDR_MAC, 3824 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 3825 {0x0005, 3826 RTW_PWR_CUT_ALL_MSK, 3827 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 3828 RTW_PWR_ADDR_MAC, 3829 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 3830 {0x0005, 3831 RTW_PWR_CUT_ALL_MSK, 3832 RTW_PWR_INTF_PCI_MSK, 3833 RTW_PWR_ADDR_MAC, 3834 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 3835 {0x0086, 3836 RTW_PWR_CUT_ALL_MSK, 3837 RTW_PWR_INTF_SDIO_MSK, 3838 RTW_PWR_ADDR_SDIO, 3839 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 3840 {0xFFFF, 3841 RTW_PWR_CUT_ALL_MSK, 3842 RTW_PWR_INTF_ALL_MSK, 3843 0, 3844 RTW_PWR_CMD_END, 0, 0}, 3845 }; 3846 3847 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822c[] = { 3848 trans_carddis_to_cardemu_8822c, 3849 trans_cardemu_to_act_8822c, 3850 NULL 3851 }; 3852 3853 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822c[] = { 3854 trans_act_to_cardemu_8822c, 3855 trans_cardemu_to_carddis_8822c, 3856 NULL 3857 }; 3858 3859 static const struct rtw_intf_phy_para usb2_param_8822c[] = { 3860 {0xFFFF, 0x00, 3861 RTW_IP_SEL_PHY, 3862 RTW_INTF_PHY_CUT_ALL, 3863 RTW_INTF_PHY_PLATFORM_ALL}, 3864 }; 3865 3866 static const struct rtw_intf_phy_para usb3_param_8822c[] = { 3867 {0xFFFF, 0x0000, 3868 RTW_IP_SEL_PHY, 3869 RTW_INTF_PHY_CUT_ALL, 3870 RTW_INTF_PHY_PLATFORM_ALL}, 3871 }; 3872 3873 static const struct rtw_intf_phy_para pcie_gen1_param_8822c[] = { 3874 {0xFFFF, 0x0000, 3875 RTW_IP_SEL_PHY, 3876 RTW_INTF_PHY_CUT_ALL, 3877 RTW_INTF_PHY_PLATFORM_ALL}, 3878 }; 3879 3880 static const struct rtw_intf_phy_para pcie_gen2_param_8822c[] = { 3881 {0xFFFF, 0x0000, 3882 RTW_IP_SEL_PHY, 3883 RTW_INTF_PHY_CUT_ALL, 3884 RTW_INTF_PHY_PLATFORM_ALL}, 3885 }; 3886 3887 static const struct rtw_intf_phy_para_table phy_para_table_8822c = { 3888 .usb2_para = usb2_param_8822c, 3889 .usb3_para = usb3_param_8822c, 3890 .gen1_para = pcie_gen1_param_8822c, 3891 .gen2_para = pcie_gen2_param_8822c, 3892 .n_usb2_para = ARRAY_SIZE(usb2_param_8822c), 3893 .n_usb3_para = ARRAY_SIZE(usb2_param_8822c), 3894 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822c), 3895 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822c), 3896 }; 3897 3898 static const struct rtw_rfe_def rtw8822c_rfe_defs[] = { 3899 [0] = RTW_DEF_RFE(8822c, 0, 0), 3900 [1] = RTW_DEF_RFE(8822c, 0, 0), 3901 [2] = RTW_DEF_RFE(8822c, 0, 0), 3902 [5] = RTW_DEF_RFE(8822c, 0, 5), 3903 }; 3904 3905 static const struct rtw_hw_reg rtw8822c_dig[] = { 3906 [0] = { .addr = 0x1d70, .mask = 0x7f }, 3907 [1] = { .addr = 0x1d70, .mask = 0x7f00 }, 3908 }; 3909 3910 static const struct rtw_page_table page_table_8822c[] = { 3911 {64, 64, 64, 64, 1}, 3912 {64, 64, 64, 64, 1}, 3913 {64, 64, 0, 0, 1}, 3914 {64, 64, 64, 0, 1}, 3915 {64, 64, 64, 64, 1}, 3916 }; 3917 3918 static const struct rtw_rqpn rqpn_table_8822c[] = { 3919 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3920 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3921 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3922 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3923 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3924 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3925 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3926 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 3927 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3928 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3929 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3930 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 3931 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 3932 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 3933 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 3934 }; 3935 3936 static struct rtw_chip_ops rtw8822c_ops = { 3937 .phy_set_param = rtw8822c_phy_set_param, 3938 .read_efuse = rtw8822c_read_efuse, 3939 .query_rx_desc = rtw8822c_query_rx_desc, 3940 .set_channel = rtw8822c_set_channel, 3941 .mac_init = rtw8822c_mac_init, 3942 .read_rf = rtw_phy_read_rf, 3943 .write_rf = rtw_phy_write_rf_reg_mix, 3944 .set_tx_power_index = rtw8822c_set_tx_power_index, 3945 .set_antenna = rtw8822c_set_antenna, 3946 .cfg_ldo25 = rtw8822c_cfg_ldo25, 3947 .false_alarm_statistics = rtw8822c_false_alarm_statistics, 3948 .dpk_track = rtw8822c_dpk_track, 3949 .phy_calibration = rtw8822c_phy_calibration, 3950 .cck_pd_set = rtw8822c_phy_cck_pd_set, 3951 .pwr_track = rtw8822c_pwr_track, 3952 .config_bfee = rtw8822c_bf_config_bfee, 3953 .set_gid_table = rtw_bf_set_gid_table, 3954 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 3955 3956 .coex_set_init = rtw8822c_coex_cfg_init, 3957 .coex_set_ant_switch = NULL, 3958 .coex_set_gnt_fix = rtw8822c_coex_cfg_gnt_fix, 3959 .coex_set_gnt_debug = rtw8822c_coex_cfg_gnt_debug, 3960 .coex_set_rfe_type = rtw8822c_coex_cfg_rfe_type, 3961 .coex_set_wl_tx_power = rtw8822c_coex_cfg_wl_tx_power, 3962 .coex_set_wl_rx_gain = rtw8822c_coex_cfg_wl_rx_gain, 3963 }; 3964 3965 /* Shared-Antenna Coex Table */ 3966 static const struct coex_table_para table_sant_8822c[] = { 3967 {0xffffffff, 0xffffffff}, /* case-0 */ 3968 {0x55555555, 0x55555555}, 3969 {0x66555555, 0x66555555}, 3970 {0xaaaaaaaa, 0xaaaaaaaa}, 3971 {0x5a5a5a5a, 0x5a5a5a5a}, 3972 {0xfafafafa, 0xfafafafa}, /* case-5 */ 3973 {0x6a5a6a5a, 0xaaaaaaaa}, 3974 {0x6a5a56aa, 0x6a5a56aa}, 3975 {0x6a5a5a5a, 0x6a5a5a5a}, 3976 {0x66555555, 0x5a5a5a5a}, 3977 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 3978 {0x66555555, 0xfafafafa}, 3979 {0x66555555, 0x6a5a5aaa}, 3980 {0x66555555, 0x5aaa5aaa}, 3981 {0x66555555, 0xaaaa5aaa}, 3982 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 3983 {0xffff55ff, 0xfafafafa}, 3984 {0xffff55ff, 0x6afa5afa}, 3985 {0xaaffffaa, 0xfafafafa}, 3986 {0xaa5555aa, 0x5a5a5a5a}, 3987 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 3988 {0xaa5555aa, 0xaaaaaaaa}, 3989 {0xffffffff, 0x5a5a5a5a}, 3990 {0xffffffff, 0x6a5a5a5a}, 3991 {0xffffffff, 0x55555555}, 3992 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 3993 {0x55555555, 0x5a5a5a5a}, 3994 {0x55555555, 0xaaaaaaaa}, 3995 {0x55555555, 0x6a5a6a5a}, 3996 {0x66556655, 0x66556655} 3997 }; 3998 3999 /* Non-Shared-Antenna Coex Table */ 4000 static const struct coex_table_para table_nsant_8822c[] = { 4001 {0xffffffff, 0xffffffff}, /* case-100 */ 4002 {0x55555555, 0x55555555}, 4003 {0x66555555, 0x66555555}, 4004 {0xaaaaaaaa, 0xaaaaaaaa}, 4005 {0x5a5a5a5a, 0x5a5a5a5a}, 4006 {0xfafafafa, 0xfafafafa}, /* case-105 */ 4007 {0x5afa5afa, 0x5afa5afa}, 4008 {0x55555555, 0xfafafafa}, 4009 {0x66555555, 0xfafafafa}, 4010 {0x66555555, 0x5a5a5a5a}, 4011 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 4012 {0x66555555, 0xaaaaaaaa}, 4013 {0xffff55ff, 0xfafafafa}, 4014 {0xffff55ff, 0x5afa5afa}, 4015 {0xffff55ff, 0xaaaaaaaa}, 4016 {0xaaffffaa, 0xfafafafa}, /* case-115 */ 4017 {0xaaffffaa, 0x5afa5afa}, 4018 {0xaaffffaa, 0xaaaaaaaa}, 4019 {0xffffffff, 0xfafafafa}, 4020 {0xffffffff, 0x5afa5afa}, 4021 {0xffffffff, 0xaaaaaaaa},/* case-120 */ 4022 {0x55ff55ff, 0x5afa5afa}, 4023 {0x55ff55ff, 0xaaaaaaaa}, 4024 {0x55ff55ff, 0x55ff55ff} 4025 }; 4026 4027 /* Shared-Antenna TDMA */ 4028 static const struct coex_tdma_para tdma_sant_8822c[] = { 4029 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 4030 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 4031 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4032 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4033 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4034 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 4035 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4036 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4037 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4038 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4039 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 4040 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4041 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4042 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4043 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4044 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 4045 { {0x51, 0x45, 0x03, 0x10, 0x10} }, 4046 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4047 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4048 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4049 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 4050 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 4051 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 4052 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 4053 { {0x65, 0x10, 0x03, 0x11, 0x11} }, 4054 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 4055 { {0x51, 0x08, 0x03, 0x10, 0x50} } 4056 }; 4057 4058 /* Non-Shared-Antenna TDMA */ 4059 static const struct coex_tdma_para tdma_nsant_8822c[] = { 4060 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 4061 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 4062 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 4063 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 4064 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 4065 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 4066 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 4067 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 4068 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 4069 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 4070 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 4071 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 4072 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 4073 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 4074 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 4075 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 4076 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 4077 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 4078 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 4079 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 4080 { {0x51, 0x10, 0x03, 0x10, 0x50} } /* case-120 */ 4081 }; 4082 4083 /* rssi in percentage % (dbm = % - 100) */ 4084 static const u8 wl_rssi_step_8822c[] = {60, 50, 44, 30}; 4085 static const u8 bt_rssi_step_8822c[] = {8, 15, 20, 25}; 4086 static const struct coex_5g_afh_map afh_5g_8822c[] = { {0, 0, 0} }; 4087 4088 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 4089 static const struct coex_rf_para rf_para_tx_8822c[] = { 4090 {0, 0, false, 7}, /* for normal */ 4091 {0, 16, false, 7}, /* for WL-CPT */ 4092 {8, 17, true, 4}, 4093 {7, 18, true, 4}, 4094 {6, 19, true, 4}, 4095 {5, 20, true, 4} 4096 }; 4097 4098 static const struct coex_rf_para rf_para_rx_8822c[] = { 4099 {0, 0, false, 7}, /* for normal */ 4100 {0, 16, false, 7}, /* for WL-CPT */ 4101 {3, 24, true, 5}, 4102 {2, 26, true, 5}, 4103 {1, 27, true, 5}, 4104 {0, 28, true, 5} 4105 }; 4106 4107 static_assert(ARRAY_SIZE(rf_para_tx_8822c) == ARRAY_SIZE(rf_para_rx_8822c)); 4108 4109 static const u8 4110 rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4111 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4112 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4113 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4114 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4115 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4116 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4117 { 0, 1, 2, 3, 5, 6, 7, 8, 9, 10, 4118 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 4119 22, 23, 24, 25, 26, 27, 28, 29, 30, 32 }, 4120 }; 4121 4122 static const u8 4123 rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4124 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4125 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4126 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4127 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4128 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4129 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4130 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4131 10, 10, 11, 12, 13, 14, 15, 16, 17, 18, 4132 19, 20, 21, 22, 22, 23, 24, 25, 26, 27 }, 4133 }; 4134 4135 static const u8 4136 rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4137 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4138 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4139 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4140 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4141 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4142 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4143 { 0, 1, 2, 4, 5, 6, 7, 8, 9, 10, 4144 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 4145 23, 24, 25, 26, 27, 28, 29, 30, 31, 33 }, 4146 }; 4147 4148 static const u8 4149 rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 4150 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4151 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4152 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4153 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4154 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4155 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4156 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4157 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 4158 21, 22, 23, 24, 25, 26, 27, 28, 29, 30 }, 4159 }; 4160 4161 static const u8 rtw8822c_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 4162 0, 1, 2, 3, 4, 4, 5, 6, 7, 8, 4163 9, 9, 10, 11, 12, 13, 14, 15, 15, 16, 4164 17, 18, 19, 20, 20, 21, 22, 23, 24, 25 4165 }; 4166 4167 static const u8 rtw8822c_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 4168 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4169 10, 11, 12, 13, 14, 14, 15, 16, 17, 18, 4170 19, 20, 21, 22, 23, 24, 25, 26, 27, 28 4171 }; 4172 4173 static const u8 rtw8822c_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 4174 0, 1, 2, 2, 3, 4, 4, 5, 6, 6, 4175 7, 8, 8, 9, 9, 10, 11, 11, 12, 13, 4176 13, 14, 15, 15, 16, 17, 17, 18, 19, 19 4177 }; 4178 4179 static const u8 rtw8822c_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 4180 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4181 10, 11, 11, 12, 13, 14, 15, 16, 17, 18, 4182 19, 20, 21, 22, 23, 24, 25, 25, 26, 27 4183 }; 4184 4185 static const u8 rtw8822c_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 4186 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4187 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4188 17, 18, 19, 20, 21, 22, 23, 23, 24, 25 4189 }; 4190 4191 static const u8 rtw8822c_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 4192 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 4193 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 4194 20, 21, 22, 23, 24, 25, 26, 27, 28, 29 4195 }; 4196 4197 static const u8 rtw8822c_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 4198 0, 1, 2, 3, 3, 4, 5, 6, 6, 7, 4199 8, 9, 9, 10, 11, 12, 12, 13, 14, 15, 4200 15, 16, 17, 18, 18, 19, 20, 21, 21, 22 4201 }; 4202 4203 static const u8 rtw8822c_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 4204 0, 1, 2, 3, 4, 5, 5, 6, 7, 8, 4205 9, 10, 11, 11, 12, 13, 14, 15, 16, 17, 4206 18, 18, 19, 20, 21, 22, 23, 24, 24, 25 4207 }; 4208 4209 static const struct rtw_pwr_track_tbl rtw8822c_rtw_pwr_track_tbl = { 4210 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 4211 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 4212 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 4213 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 4214 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 4215 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 4216 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 4217 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 4218 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 4219 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 4220 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 4221 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822c_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 4222 .pwrtrk_2gb_n = rtw8822c_pwrtrk_2gb_n, 4223 .pwrtrk_2gb_p = rtw8822c_pwrtrk_2gb_p, 4224 .pwrtrk_2ga_n = rtw8822c_pwrtrk_2ga_n, 4225 .pwrtrk_2ga_p = rtw8822c_pwrtrk_2ga_p, 4226 .pwrtrk_2g_cckb_n = rtw8822c_pwrtrk_2g_cck_b_n, 4227 .pwrtrk_2g_cckb_p = rtw8822c_pwrtrk_2g_cck_b_p, 4228 .pwrtrk_2g_ccka_n = rtw8822c_pwrtrk_2g_cck_a_n, 4229 .pwrtrk_2g_ccka_p = rtw8822c_pwrtrk_2g_cck_a_p, 4230 }; 4231 4232 #ifdef CONFIG_PM 4233 static const struct wiphy_wowlan_support rtw_wowlan_stub_8822c = { 4234 .flags = WIPHY_WOWLAN_MAGIC_PKT | WIPHY_WOWLAN_GTK_REKEY_FAILURE | 4235 WIPHY_WOWLAN_DISCONNECT | WIPHY_WOWLAN_SUPPORTS_GTK_REKEY | 4236 WIPHY_WOWLAN_NET_DETECT, 4237 .n_patterns = RTW_MAX_PATTERN_NUM, 4238 .pattern_max_len = RTW_MAX_PATTERN_SIZE, 4239 .pattern_min_len = 1, 4240 .max_nd_match_sets = 4, 4241 }; 4242 #endif 4243 4244 static const struct rtw_reg_domain coex_info_hw_regs_8822c[] = { 4245 {0x1860, BIT(3), RTW_REG_DOMAIN_MAC8}, 4246 {0x4160, BIT(3), RTW_REG_DOMAIN_MAC8}, 4247 {0x1c32, BIT(6), RTW_REG_DOMAIN_MAC8}, 4248 {0x1c38, BIT(28), RTW_REG_DOMAIN_MAC32}, 4249 {0, 0, RTW_REG_DOMAIN_NL}, 4250 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4251 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4252 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4253 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4254 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 4255 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 4256 {0, 0, RTW_REG_DOMAIN_NL}, 4257 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 4258 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 4259 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 4260 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 4261 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 4262 {0, 0, RTW_REG_DOMAIN_NL}, 4263 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 4264 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4265 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 4266 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 4267 }; 4268 4269 struct rtw_chip_info rtw8822c_hw_spec = { 4270 .ops = &rtw8822c_ops, 4271 .id = RTW_CHIP_TYPE_8822C, 4272 .fw_name = "rtw88/rtw8822c_fw.bin", 4273 .wlan_cpu = RTW_WCPU_11AC, 4274 .tx_pkt_desc_sz = 48, 4275 .tx_buf_desc_sz = 16, 4276 .rx_pkt_desc_sz = 24, 4277 .rx_buf_desc_sz = 8, 4278 .phy_efuse_size = 512, 4279 .log_efuse_size = 768, 4280 .ptct_efuse_size = 124, 4281 .txff_size = 262144, 4282 .rxff_size = 24576, 4283 .txgi_factor = 2, 4284 .is_pwr_by_rate_dec = false, 4285 .max_power_index = 0x7f, 4286 .csi_buf_pg_num = 50, 4287 .band = RTW_BAND_2G | RTW_BAND_5G, 4288 .page_size = 128, 4289 .dig_min = 0x20, 4290 .ht_supported = true, 4291 .vht_supported = true, 4292 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK) | BIT(LPS_DEEP_MODE_PG), 4293 .sys_func_en = 0xD8, 4294 .pwr_on_seq = card_enable_flow_8822c, 4295 .pwr_off_seq = card_disable_flow_8822c, 4296 .page_table = page_table_8822c, 4297 .rqpn_table = rqpn_table_8822c, 4298 .intf_table = &phy_para_table_8822c, 4299 .dig = rtw8822c_dig, 4300 .dig_cck = NULL, 4301 .rf_base_addr = {0x3c00, 0x4c00}, 4302 .rf_sipi_addr = {0x1808, 0x4108}, 4303 .mac_tbl = &rtw8822c_mac_tbl, 4304 .agc_tbl = &rtw8822c_agc_tbl, 4305 .bb_tbl = &rtw8822c_bb_tbl, 4306 .rfk_init_tbl = &rtw8822c_array_mp_cal_init_tbl, 4307 .rf_tbl = {&rtw8822c_rf_b_tbl, &rtw8822c_rf_a_tbl}, 4308 .rfe_defs = rtw8822c_rfe_defs, 4309 .rfe_defs_size = ARRAY_SIZE(rtw8822c_rfe_defs), 4310 .en_dis_dpd = true, 4311 .dpd_ratemask = DIS_DPD_RATEALL, 4312 .pwr_track_tbl = &rtw8822c_rtw_pwr_track_tbl, 4313 .iqk_threshold = 8, 4314 .bfer_su_max_num = 2, 4315 .bfer_mu_max_num = 1, 4316 .rx_ldpc = true, 4317 4318 #ifdef CONFIG_PM 4319 .wow_fw_name = "rtw88/rtw8822c_wow_fw.bin", 4320 .wowlan_stub = &rtw_wowlan_stub_8822c, 4321 .max_sched_scan_ssids = 4, 4322 #endif 4323 .coex_para_ver = 0x19062706, 4324 .bt_desired_ver = 0x6, 4325 .scbd_support = true, 4326 .new_scbd10_def = true, 4327 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 4328 .bt_rssi_type = COEX_BTRSSI_DBM, 4329 .ant_isolation = 15, 4330 .rssi_tolerance = 2, 4331 .wl_rssi_step = wl_rssi_step_8822c, 4332 .bt_rssi_step = bt_rssi_step_8822c, 4333 .table_sant_num = ARRAY_SIZE(table_sant_8822c), 4334 .table_sant = table_sant_8822c, 4335 .table_nsant_num = ARRAY_SIZE(table_nsant_8822c), 4336 .table_nsant = table_nsant_8822c, 4337 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822c), 4338 .tdma_sant = tdma_sant_8822c, 4339 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822c), 4340 .tdma_nsant = tdma_nsant_8822c, 4341 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822c), 4342 .wl_rf_para_tx = rf_para_tx_8822c, 4343 .wl_rf_para_rx = rf_para_rx_8822c, 4344 .bt_afh_span_bw20 = 0x24, 4345 .bt_afh_span_bw40 = 0x36, 4346 .afh_5g_num = ARRAY_SIZE(afh_5g_8822c), 4347 .afh_5g = afh_5g_8822c, 4348 4349 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822c), 4350 .coex_info_hw_regs = coex_info_hw_regs_8822c, 4351 }; 4352 EXPORT_SYMBOL(rtw8822c_hw_spec); 4353 4354 MODULE_FIRMWARE("rtw88/rtw8822c_fw.bin"); 4355 MODULE_FIRMWARE("rtw88/rtw8822c_wow_fw.bin"); 4356