1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #include <linux/module.h> 6 #include "main.h" 7 #include "coex.h" 8 #include "fw.h" 9 #include "tx.h" 10 #include "rx.h" 11 #include "phy.h" 12 #include "rtw8822b.h" 13 #include "rtw8822b_table.h" 14 #include "mac.h" 15 #include "reg.h" 16 #include "debug.h" 17 #include "bf.h" 18 #include "regd.h" 19 20 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 21 u8 rx_path, bool is_tx2_path); 22 23 static void rtw8822be_efuse_parsing(struct rtw_efuse *efuse, 24 struct rtw8822b_efuse *map) 25 { 26 ether_addr_copy(efuse->addr, map->e.mac_addr); 27 } 28 29 static void rtw8822bu_efuse_parsing(struct rtw_efuse *efuse, 30 struct rtw8822b_efuse *map) 31 { 32 ether_addr_copy(efuse->addr, map->u.mac_addr); 33 } 34 35 static void rtw8822bs_efuse_parsing(struct rtw_efuse *efuse, 36 struct rtw8822b_efuse *map) 37 { 38 ether_addr_copy(efuse->addr, map->s.mac_addr); 39 } 40 41 static int rtw8822b_read_efuse(struct rtw_dev *rtwdev, u8 *log_map) 42 { 43 struct rtw_efuse *efuse = &rtwdev->efuse; 44 struct rtw8822b_efuse *map; 45 int i; 46 47 map = (struct rtw8822b_efuse *)log_map; 48 49 efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(7)); 50 efuse->rfe_option = map->rfe_option; 51 efuse->rf_board_option = map->rf_board_option; 52 efuse->crystal_cap = map->xtal_k; 53 efuse->pa_type_2g = map->pa_type; 54 efuse->pa_type_5g = map->pa_type; 55 efuse->lna_type_2g = map->lna_type_2g[0]; 56 efuse->lna_type_5g = map->lna_type_5g[0]; 57 efuse->channel_plan = map->channel_plan; 58 efuse->country_code[0] = map->country_code[0]; 59 efuse->country_code[1] = map->country_code[1]; 60 efuse->bt_setting = map->rf_bt_setting; 61 efuse->regd = map->rf_board_option & 0x7; 62 efuse->thermal_meter[RF_PATH_A] = map->thermal_meter; 63 efuse->thermal_meter_k = map->thermal_meter; 64 65 for (i = 0; i < 4; i++) 66 efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i]; 67 68 switch (rtw_hci_type(rtwdev)) { 69 case RTW_HCI_TYPE_PCIE: 70 rtw8822be_efuse_parsing(efuse, map); 71 break; 72 case RTW_HCI_TYPE_USB: 73 rtw8822bu_efuse_parsing(efuse, map); 74 break; 75 case RTW_HCI_TYPE_SDIO: 76 rtw8822bs_efuse_parsing(efuse, map); 77 break; 78 default: 79 /* unsupported now */ 80 return -ENOTSUPP; 81 } 82 83 return 0; 84 } 85 86 static void rtw8822b_phy_rfe_init(struct rtw_dev *rtwdev) 87 { 88 /* chip top mux */ 89 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); 90 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); 91 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); 92 93 /* from s0 or s1 */ 94 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); 95 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); 96 97 /* input or output */ 98 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); 99 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); 100 } 101 102 #define RTW_TXSCALE_SIZE 37 103 static const u32 rtw8822b_txscale_tbl[RTW_TXSCALE_SIZE] = { 104 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8, 105 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180, 106 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab, 107 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe 108 }; 109 110 static u8 rtw8822b_get_swing_index(struct rtw_dev *rtwdev) 111 { 112 u8 i = 0; 113 u32 swing, table_value; 114 115 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000); 116 for (i = 0; i < RTW_TXSCALE_SIZE; i++) { 117 table_value = rtw8822b_txscale_tbl[i]; 118 if (swing == table_value) 119 break; 120 } 121 122 return i; 123 } 124 125 static void rtw8822b_pwrtrack_init(struct rtw_dev *rtwdev) 126 { 127 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 128 u8 swing_idx = rtw8822b_get_swing_index(rtwdev); 129 u8 path; 130 131 if (swing_idx >= RTW_TXSCALE_SIZE) 132 dm_info->default_ofdm_index = 24; 133 else 134 dm_info->default_ofdm_index = swing_idx; 135 136 for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) { 137 ewma_thermal_init(&dm_info->avg_thermal[path]); 138 dm_info->delta_power_index[path] = 0; 139 } 140 dm_info->pwr_trk_triggered = false; 141 dm_info->pwr_trk_init_trigger = true; 142 dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k; 143 } 144 145 static void rtw8822b_phy_bf_init(struct rtw_dev *rtwdev) 146 { 147 rtw_bf_phy_init(rtwdev); 148 /* Grouping bitmap parameters */ 149 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); 150 } 151 152 static void rtw8822b_phy_set_param(struct rtw_dev *rtwdev) 153 { 154 struct rtw_hal *hal = &rtwdev->hal; 155 u8 crystal_cap; 156 bool is_tx2_path; 157 158 /* power on BB/RF domain */ 159 rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, 160 BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST); 161 rtw_write8_set(rtwdev, REG_RF_CTRL, 162 BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB); 163 rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN); 164 165 /* pre init before header files config */ 166 rtw_write32_clr(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 167 168 rtw_phy_load_tables(rtwdev); 169 170 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; 171 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); 172 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); 173 174 /* post init after header files config */ 175 rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST); 176 177 is_tx2_path = false; 178 rtw8822b_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx, 179 is_tx2_path); 180 rtw_phy_init(rtwdev); 181 182 rtw8822b_phy_rfe_init(rtwdev); 183 rtw8822b_pwrtrack_init(rtwdev); 184 185 rtw8822b_phy_bf_init(rtwdev); 186 } 187 188 #define WLAN_SLOT_TIME 0x09 189 #define WLAN_PIFS_TIME 0x19 190 #define WLAN_SIFS_CCK_CONT_TX 0xA 191 #define WLAN_SIFS_OFDM_CONT_TX 0xE 192 #define WLAN_SIFS_CCK_TRX 0x10 193 #define WLAN_SIFS_OFDM_TRX 0x10 194 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */ 195 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */ 196 #define WLAN_RDG_NAV 0x05 197 #define WLAN_TXOP_NAV 0x1B 198 #define WLAN_CCK_RX_TSF 0x30 199 #define WLAN_OFDM_RX_TSF 0x30 200 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */ 201 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */ 202 #define WLAN_DRV_EARLY_INT 0x04 203 #define WLAN_BCN_DMA_TIME 0x02 204 205 #define WLAN_RX_FILTER0 0x0FFFFFFF 206 #define WLAN_RX_FILTER2 0xFFFF 207 #define WLAN_RCR_CFG 0xE400220E 208 #define WLAN_RXPKT_MAX_SZ 12288 209 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 210 211 #define WLAN_AMPDU_MAX_TIME 0x70 212 #define WLAN_RTS_LEN_TH 0xFF 213 #define WLAN_RTS_TX_TIME_TH 0x08 214 #define WLAN_MAX_AGG_PKT_LIMIT 0x20 215 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 216 #define FAST_EDCA_VO_TH 0x06 217 #define FAST_EDCA_VI_TH 0x06 218 #define FAST_EDCA_BE_TH 0x06 219 #define FAST_EDCA_BK_TH 0x06 220 #define WLAN_BAR_RETRY_LIMIT 0x01 221 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 222 223 #define WLAN_TX_FUNC_CFG1 0x30 224 #define WLAN_TX_FUNC_CFG2 0x30 225 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 226 #define WLAN_MAC_OPT_LB_FUNC1 0x80 227 #define WLAN_MAC_OPT_FUNC2 0xb0810041 228 229 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 230 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 231 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 232 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 233 234 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 235 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 236 237 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 238 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 239 240 static int rtw8822b_mac_init(struct rtw_dev *rtwdev) 241 { 242 u32 value32; 243 244 /* protocol configuration */ 245 rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL, BIT_PRE_TX_CMD); 246 rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME); 247 rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1); 248 value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) | 249 (WLAN_MAX_AGG_PKT_LIMIT << 16) | 250 (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24); 251 rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32); 252 rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2, 253 WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8); 254 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH); 255 rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH); 256 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH); 257 rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH); 258 /* EDCA configuration */ 259 rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0); 260 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); 261 rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME); 262 rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME); 263 rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG); 264 rtw_write16(rtwdev, REG_EDCA_VO_PARAM + 2, WLAN_VO_TXOP_LIMIT); 265 rtw_write16(rtwdev, REG_EDCA_VI_PARAM + 2, WLAN_VI_TXOP_LIMIT); 266 rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG); 267 rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG); 268 /* Set beacon cotnrol - enable TSF and other related functions */ 269 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 270 /* Set send beacon related registers */ 271 rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME); 272 rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT); 273 rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME); 274 rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8); 275 /* WMAC configuration */ 276 rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0); 277 rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2); 278 rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG); 279 rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512); 280 rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2); 281 rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1); 282 rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2); 283 rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION + 4, WLAN_MAC_OPT_NORM_FUNC1); 284 rtw_write8_set(rtwdev, REG_SND_PTCL_CTRL, 285 BIT_DIS_CHK_VHTSIGB_CRC); 286 287 return 0; 288 } 289 290 static void rtw8822b_set_channel_rfe_efem(struct rtw_dev *rtwdev, u8 channel) 291 { 292 struct rtw_hal *hal = &rtwdev->hal; 293 294 if (IS_CH_2G_BAND(channel)) { 295 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); 296 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 297 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); 298 } else { 299 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); 300 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 301 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); 302 } 303 304 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 305 306 if (hal->antenna_rx == BB_PATH_AB || 307 hal->antenna_tx == BB_PATH_AB) { 308 /* 2TX or 2RX */ 309 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 310 } else if (hal->antenna_rx == hal->antenna_tx) { 311 /* TXA+RXA or TXB+RXB */ 312 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 313 } else { 314 /* TXB+RXA or TXA+RXB */ 315 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 316 } 317 } 318 319 static void rtw8822b_set_channel_rfe_ifem(struct rtw_dev *rtwdev, u8 channel) 320 { 321 struct rtw_hal *hal = &rtwdev->hal; 322 323 if (IS_CH_2G_BAND(channel)) { 324 /* signal source */ 325 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); 326 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); 327 } else { 328 /* signal source */ 329 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); 330 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); 331 } 332 333 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); 334 335 if (IS_CH_2G_BAND(channel)) { 336 if (hal->antenna_rx == BB_PATH_AB || 337 hal->antenna_tx == BB_PATH_AB) { 338 /* 2TX or 2RX */ 339 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); 340 } else if (hal->antenna_rx == hal->antenna_tx) { 341 /* TXA+RXA or TXB+RXB */ 342 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); 343 } else { 344 /* TXB+RXA or TXA+RXB */ 345 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); 346 } 347 } else { 348 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); 349 } 350 } 351 352 enum { 353 CCUT_IDX_1R_2G, 354 CCUT_IDX_2R_2G, 355 CCUT_IDX_1R_5G, 356 CCUT_IDX_2R_5G, 357 CCUT_IDX_NR, 358 }; 359 360 struct cca_ccut { 361 u32 reg82c[CCUT_IDX_NR]; 362 u32 reg830[CCUT_IDX_NR]; 363 u32 reg838[CCUT_IDX_NR]; 364 }; 365 366 static const struct cca_ccut cca_ifem_ccut = { 367 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/ 368 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 369 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/ 370 }; 371 372 static const struct cca_ccut cca_efem_ccut = { 373 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/ 374 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/ 375 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/ 376 }; 377 378 static const struct cca_ccut cca_ifem_ccut_ext = { 379 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/ 380 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/ 381 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/ 382 }; 383 384 static void rtw8822b_get_cca_val(const struct cca_ccut *cca_ccut, u8 col, 385 u32 *reg82c, u32 *reg830, u32 *reg838) 386 { 387 *reg82c = cca_ccut->reg82c[col]; 388 *reg830 = cca_ccut->reg830[col]; 389 *reg838 = cca_ccut->reg838[col]; 390 } 391 392 struct rtw8822b_rfe_info { 393 const struct cca_ccut *cca_ccut_2g; 394 const struct cca_ccut *cca_ccut_5g; 395 enum rtw_rfe_fem fem; 396 bool ifem_ext; 397 void (*rtw_set_channel_rfe)(struct rtw_dev *rtwdev, u8 channel); 398 }; 399 400 #define I2GE5G_CCUT(set_ch) { \ 401 .cca_ccut_2g = &cca_ifem_ccut, \ 402 .cca_ccut_5g = &cca_efem_ccut, \ 403 .fem = RTW_RFE_IFEM2G_EFEM5G, \ 404 .ifem_ext = false, \ 405 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 406 } 407 #define IFEM_EXT_CCUT(set_ch) { \ 408 .cca_ccut_2g = &cca_ifem_ccut_ext, \ 409 .cca_ccut_5g = &cca_ifem_ccut_ext, \ 410 .fem = RTW_RFE_IFEM, \ 411 .ifem_ext = true, \ 412 .rtw_set_channel_rfe = &rtw8822b_set_channel_rfe_ ## set_ch, \ 413 } 414 415 static const struct rtw8822b_rfe_info rtw8822b_rfe_info[] = { 416 [2] = I2GE5G_CCUT(efem), 417 [3] = IFEM_EXT_CCUT(ifem), 418 [5] = IFEM_EXT_CCUT(ifem), 419 }; 420 421 static void rtw8822b_set_channel_cca(struct rtw_dev *rtwdev, u8 channel, u8 bw, 422 const struct rtw8822b_rfe_info *rfe_info) 423 { 424 struct rtw_hal *hal = &rtwdev->hal; 425 struct rtw_efuse *efuse = &rtwdev->efuse; 426 const struct cca_ccut *cca_ccut; 427 u8 col; 428 u32 reg82c, reg830, reg838; 429 bool is_efem_cca = false, is_ifem_cca = false, is_rfe_type = false; 430 431 if (IS_CH_2G_BAND(channel)) { 432 cca_ccut = rfe_info->cca_ccut_2g; 433 434 if (hal->antenna_rx == BB_PATH_A || 435 hal->antenna_rx == BB_PATH_B) 436 col = CCUT_IDX_1R_2G; 437 else 438 col = CCUT_IDX_2R_2G; 439 } else { 440 cca_ccut = rfe_info->cca_ccut_5g; 441 442 if (hal->antenna_rx == BB_PATH_A || 443 hal->antenna_rx == BB_PATH_B) 444 col = CCUT_IDX_1R_5G; 445 else 446 col = CCUT_IDX_2R_5G; 447 } 448 449 rtw8822b_get_cca_val(cca_ccut, col, ®82c, ®830, ®838); 450 451 switch (rfe_info->fem) { 452 case RTW_RFE_IFEM: 453 default: 454 is_ifem_cca = true; 455 if (rfe_info->ifem_ext) 456 is_rfe_type = true; 457 break; 458 case RTW_RFE_EFEM: 459 is_efem_cca = true; 460 break; 461 case RTW_RFE_IFEM2G_EFEM5G: 462 if (IS_CH_2G_BAND(channel)) 463 is_ifem_cca = true; 464 else 465 is_efem_cca = true; 466 break; 467 } 468 469 if (is_ifem_cca) { 470 if ((hal->cut_version == RTW_CHIP_VER_CUT_B && 471 (col == CCUT_IDX_2R_2G || col == CCUT_IDX_2R_5G) && 472 bw == RTW_CHANNEL_WIDTH_40) || 473 (!is_rfe_type && col == CCUT_IDX_2R_5G && 474 bw == RTW_CHANNEL_WIDTH_40) || 475 (efuse->rfe_option == 5 && col == CCUT_IDX_2R_5G)) 476 reg830 = 0x79a0ea28; 477 } 478 479 rtw_write32_mask(rtwdev, REG_CCASEL, MASKDWORD, reg82c); 480 rtw_write32_mask(rtwdev, REG_PDMFTH, MASKDWORD, reg830); 481 rtw_write32_mask(rtwdev, REG_CCA2ND, MASKDWORD, reg838); 482 483 if (is_efem_cca && !(hal->cut_version == RTW_CHIP_VER_CUT_B)) 484 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); 485 486 if (bw == RTW_CHANNEL_WIDTH_20 && IS_CH_5G_BAND_MID(channel)) 487 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); 488 } 489 490 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6, 491 0x5, 0x0, 0x0, 0x7, 0x6, 0x6}; 492 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0, 493 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6, 494 0x6, 0x5, 0x0, 0x0, 0x7}; 495 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0, 496 0x7, 0x7, 0x6, 0x5, 0x5, 0x0}; 497 498 static void rtw8822b_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw) 499 { 500 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 501 #define RF18_BAND_2G (0) 502 #define RF18_BAND_5G (BIT(16) | BIT(8)) 503 #define RF18_CHANNEL_MASK (MASKBYTE0) 504 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 505 #define RF18_RFSI_GE_CH80 (BIT(17)) 506 #define RF18_RFSI_GT_CH144 (BIT(18)) 507 #define RF18_BW_MASK (BIT(11) | BIT(10)) 508 #define RF18_BW_20M (BIT(11) | BIT(10)) 509 #define RF18_BW_40M (BIT(11)) 510 #define RF18_BW_80M (BIT(10)) 511 #define RFBE_MASK (BIT(17) | BIT(16) | BIT(15)) 512 513 struct rtw_hal *hal = &rtwdev->hal; 514 u32 rf_reg18, rf_reg_be; 515 516 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); 517 518 rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK | 519 RF18_BW_MASK); 520 521 rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G); 522 rf_reg18 |= (channel & RF18_CHANNEL_MASK); 523 if (channel > 144) 524 rf_reg18 |= RF18_RFSI_GT_CH144; 525 else if (channel >= 80) 526 rf_reg18 |= RF18_RFSI_GE_CH80; 527 528 switch (bw) { 529 case RTW_CHANNEL_WIDTH_5: 530 case RTW_CHANNEL_WIDTH_10: 531 case RTW_CHANNEL_WIDTH_20: 532 default: 533 rf_reg18 |= RF18_BW_20M; 534 break; 535 case RTW_CHANNEL_WIDTH_40: 536 rf_reg18 |= RF18_BW_40M; 537 break; 538 case RTW_CHANNEL_WIDTH_80: 539 rf_reg18 |= RF18_BW_80M; 540 break; 541 } 542 543 if (IS_CH_2G_BAND(channel)) 544 rf_reg_be = 0x0; 545 else if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) 546 rf_reg_be = low_band[(channel - 36) >> 1]; 547 else if (IS_CH_5G_BAND_3(channel)) 548 rf_reg_be = middle_band[(channel - 100) >> 1]; 549 else if (IS_CH_5G_BAND_4(channel)) 550 rf_reg_be = high_band[(channel - 149) >> 1]; 551 else 552 goto err; 553 554 rtw_write_rf(rtwdev, RF_PATH_A, RF_MALSEL, RFBE_MASK, rf_reg_be); 555 556 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ 557 if (channel == 144) 558 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); 559 else 560 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); 561 562 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); 563 if (hal->rf_type > RF_1T1R) 564 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); 565 566 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); 567 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 1); 568 569 return; 570 571 err: 572 WARN_ON(1); 573 } 574 575 static void rtw8822b_toggle_igi(struct rtw_dev *rtwdev) 576 { 577 struct rtw_hal *hal = &rtwdev->hal; 578 u32 igi; 579 580 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); 581 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); 582 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); 583 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); 584 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); 585 586 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); 587 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 588 hal->antenna_rx | (hal->antenna_rx << 4)); 589 } 590 591 static void rtw8822b_set_channel_rxdfir(struct rtw_dev *rtwdev, u8 bw) 592 { 593 if (bw == RTW_CHANNEL_WIDTH_40) { 594 /* RX DFIR for BW40 */ 595 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); 596 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); 597 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 598 } else if (bw == RTW_CHANNEL_WIDTH_80) { 599 /* RX DFIR for BW80 */ 600 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 601 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); 602 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); 603 } else { 604 /* RX DFIR for BW20, BW10 and BW5*/ 605 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); 606 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); 607 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); 608 } 609 } 610 611 static void rtw8822b_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw, 612 u8 primary_ch_idx) 613 { 614 struct rtw_efuse *efuse = &rtwdev->efuse; 615 u8 rfe_option = efuse->rfe_option; 616 u32 val32; 617 618 if (IS_CH_2G_BAND(channel)) { 619 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); 620 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); 621 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); 622 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); 623 624 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); 625 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); 626 if (channel == 14) { 627 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); 628 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); 629 } else { 630 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); 631 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); 632 } 633 634 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); 635 } else if (IS_CH_5G_BAND(channel)) { 636 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); 637 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); 638 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); 639 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); 640 641 if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) 642 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); 643 else if (IS_CH_5G_BAND_3(channel)) 644 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); 645 else if (IS_CH_5G_BAND_4(channel)) 646 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); 647 648 if (IS_CH_5G_BAND_1(channel)) 649 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); 650 else if (IS_CH_5G_BAND_2(channel)) 651 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); 652 else if (channel >= 100 && channel <= 116) 653 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); 654 else if (channel >= 118 && channel <= 177) 655 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); 656 657 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); 658 } 659 660 switch (bw) { 661 case RTW_CHANNEL_WIDTH_20: 662 default: 663 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 664 val32 &= 0xFFCFFC00; 665 val32 |= (RTW_CHANNEL_WIDTH_20); 666 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 667 668 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 669 break; 670 case RTW_CHANNEL_WIDTH_40: 671 if (primary_ch_idx == RTW_SC_20_UPPER) 672 rtw_write32_set(rtwdev, REG_RXSB, BIT(4)); 673 else 674 rtw_write32_clr(rtwdev, REG_RXSB, BIT(4)); 675 676 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 677 val32 &= 0xFF3FF300; 678 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); 679 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 680 681 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 682 break; 683 case RTW_CHANNEL_WIDTH_80: 684 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 685 val32 &= 0xFCEFCF00; 686 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); 687 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 688 689 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); 690 691 if (rfe_option == 2 || rfe_option == 3) { 692 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); 693 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); 694 } 695 break; 696 case RTW_CHANNEL_WIDTH_5: 697 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 698 val32 &= 0xEFEEFE00; 699 val32 |= ((BIT(6) | RTW_CHANNEL_WIDTH_20)); 700 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 701 702 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 703 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 704 break; 705 case RTW_CHANNEL_WIDTH_10: 706 val32 = rtw_read32_mask(rtwdev, REG_ADCCLK, MASKDWORD); 707 val32 &= 0xEFFEFF00; 708 val32 |= ((BIT(7) | RTW_CHANNEL_WIDTH_20)); 709 rtw_write32_mask(rtwdev, REG_ADCCLK, MASKDWORD, val32); 710 711 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); 712 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); 713 break; 714 } 715 } 716 717 static void rtw8822b_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw, 718 u8 primary_chan_idx) 719 { 720 struct rtw_efuse *efuse = &rtwdev->efuse; 721 const struct rtw8822b_rfe_info *rfe_info; 722 723 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 724 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 725 return; 726 727 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 728 729 rtw8822b_set_channel_bb(rtwdev, channel, bw, primary_chan_idx); 730 rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx); 731 rtw8822b_set_channel_rf(rtwdev, channel, bw); 732 rtw8822b_set_channel_rxdfir(rtwdev, bw); 733 rtw8822b_toggle_igi(rtwdev); 734 rtw8822b_set_channel_cca(rtwdev, channel, bw, rfe_info); 735 (*rfe_info->rtw_set_channel_rfe)(rtwdev, channel); 736 } 737 738 static void rtw8822b_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path, 739 u8 rx_path, bool is_tx2_path) 740 { 741 struct rtw_efuse *efuse = &rtwdev->efuse; 742 const struct rtw8822b_rfe_info *rfe_info; 743 u8 ch = rtwdev->hal.current_channel; 744 u8 tx_path_sel, rx_path_sel; 745 int counter; 746 747 if (WARN(efuse->rfe_option >= ARRAY_SIZE(rtw8822b_rfe_info), 748 "rfe_option %d is out of boundary\n", efuse->rfe_option)) 749 return; 750 751 rfe_info = &rtw8822b_rfe_info[efuse->rfe_option]; 752 753 if ((tx_path | rx_path) & BB_PATH_A) 754 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); 755 else 756 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); 757 758 if ((tx_path | rx_path) & BB_PATH_B) 759 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); 760 else 761 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); 762 763 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); 764 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); 765 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); 766 767 if (tx_path & BB_PATH_A) { 768 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); 769 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); 770 } else if (tx_path & BB_PATH_B) { 771 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); 772 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); 773 } 774 775 if (tx_path == BB_PATH_A || tx_path == BB_PATH_B) 776 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); 777 else 778 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); 779 780 tx_path_sel = (tx_path << 4) | tx_path; 781 rtw_write32_mask(rtwdev, REG_TXPSEL, MASKBYTE0, tx_path_sel); 782 783 if (tx_path != BB_PATH_A && tx_path != BB_PATH_B) { 784 if (is_tx2_path || rtwdev->mp_mode) { 785 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); 786 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); 787 } 788 } 789 790 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); 791 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); 792 793 if (rx_path & BB_PATH_A) 794 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); 795 else if (rx_path & BB_PATH_B) 796 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); 797 798 rx_path_sel = (rx_path << 4) | rx_path; 799 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, rx_path_sel); 800 801 if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) { 802 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); 803 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); 804 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); 805 } else { 806 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); 807 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); 808 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); 809 } 810 811 for (counter = 100; counter > 0; counter--) { 812 u32 rf_reg33; 813 814 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 815 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 816 817 udelay(2); 818 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); 819 820 if (rf_reg33 == 0x00001) 821 break; 822 } 823 824 if (WARN(counter <= 0, "write RF mode table fail\n")) 825 return; 826 827 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); 828 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); 829 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); 830 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); 831 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 832 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); 833 834 rtw8822b_toggle_igi(rtwdev); 835 rtw8822b_set_channel_cca(rtwdev, 1, RTW_CHANNEL_WIDTH_20, rfe_info); 836 (*rfe_info->rtw_set_channel_rfe)(rtwdev, ch); 837 } 838 839 static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status, 840 struct rtw_rx_pkt_stat *pkt_stat) 841 { 842 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 843 s8 min_rx_power = -120; 844 u8 pwdb = GET_PHY_STAT_P0_PWDB(phy_status); 845 846 /* 8822B uses only 1 antenna to RX CCK rates */ 847 pkt_stat->rx_power[RF_PATH_A] = pwdb - 110; 848 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1); 849 pkt_stat->bw = RTW_CHANNEL_WIDTH_20; 850 pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A], 851 min_rx_power); 852 dm_info->rssi[RF_PATH_A] = pkt_stat->rssi; 853 } 854 855 static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status, 856 struct rtw_rx_pkt_stat *pkt_stat) 857 { 858 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 859 u8 rxsc, bw; 860 s8 min_rx_power = -120; 861 s8 rx_evm; 862 u8 evm_dbm = 0; 863 u8 rssi; 864 int path; 865 866 if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0) 867 rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status); 868 else 869 rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status); 870 871 if (rxsc >= 1 && rxsc <= 8) 872 bw = RTW_CHANNEL_WIDTH_20; 873 else if (rxsc >= 9 && rxsc <= 12) 874 bw = RTW_CHANNEL_WIDTH_40; 875 else if (rxsc >= 13) 876 bw = RTW_CHANNEL_WIDTH_80; 877 else 878 bw = GET_PHY_STAT_P1_RF_MODE(phy_status); 879 880 pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110; 881 pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110; 882 pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2); 883 pkt_stat->bw = bw; 884 pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A], 885 pkt_stat->rx_power[RF_PATH_B], 886 min_rx_power); 887 888 dm_info->curr_rx_rate = pkt_stat->rate; 889 890 pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status); 891 pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status); 892 893 pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status); 894 pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status); 895 896 pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status); 897 pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status); 898 899 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { 900 rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1); 901 dm_info->rssi[path] = rssi; 902 dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1; 903 dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1; 904 905 rx_evm = pkt_stat->rx_evm[path]; 906 907 if (rx_evm < 0) { 908 if (rx_evm == S8_MIN) 909 evm_dbm = 0; 910 else 911 evm_dbm = ((u8)-rx_evm >> 1); 912 } 913 dm_info->rx_evm_dbm[path] = evm_dbm; 914 } 915 } 916 917 static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status, 918 struct rtw_rx_pkt_stat *pkt_stat) 919 { 920 u8 page; 921 922 page = *phy_status & 0xf; 923 924 switch (page) { 925 case 0: 926 query_phy_status_page0(rtwdev, phy_status, pkt_stat); 927 break; 928 case 1: 929 query_phy_status_page1(rtwdev, phy_status, pkt_stat); 930 break; 931 default: 932 rtw_warn(rtwdev, "unused phy status page (%d)\n", page); 933 return; 934 } 935 } 936 937 static void rtw8822b_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc, 938 struct rtw_rx_pkt_stat *pkt_stat, 939 struct ieee80211_rx_status *rx_status) 940 { 941 struct ieee80211_hdr *hdr; 942 u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz; 943 u8 *phy_status = NULL; 944 945 memset(pkt_stat, 0, sizeof(*pkt_stat)); 946 947 pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc); 948 pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc); 949 pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc); 950 pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) && 951 GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE; 952 pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc); 953 pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc); 954 pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc); 955 pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc); 956 pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc); 957 pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc); 958 pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc); 959 pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc); 960 961 /* drv_info_sz is in unit of 8-bytes */ 962 pkt_stat->drv_info_sz *= 8; 963 964 /* c2h cmd pkt's rx/phy status is not interested */ 965 if (pkt_stat->is_c2h) 966 return; 967 968 hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift + 969 pkt_stat->drv_info_sz); 970 if (pkt_stat->phy_status) { 971 phy_status = rx_desc + desc_sz + pkt_stat->shift; 972 query_phy_status(rtwdev, phy_status, pkt_stat); 973 } 974 975 rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status); 976 } 977 978 static void 979 rtw8822b_set_tx_power_index_by_rate(struct rtw_dev *rtwdev, u8 path, u8 rs) 980 { 981 struct rtw_hal *hal = &rtwdev->hal; 982 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; 983 static u32 phy_pwr_idx; 984 u8 rate, rate_idx, pwr_index, shift; 985 int j; 986 987 for (j = 0; j < rtw_rate_size[rs]; j++) { 988 rate = rtw_rate_section[rs][j]; 989 pwr_index = hal->tx_pwr_tbl[path][rate]; 990 shift = rate & 0x3; 991 phy_pwr_idx |= ((u32)pwr_index << (shift * 8)); 992 if (shift == 0x3) { 993 rate_idx = rate & 0xfc; 994 rtw_write32(rtwdev, offset_txagc[path] + rate_idx, 995 phy_pwr_idx); 996 phy_pwr_idx = 0; 997 } 998 } 999 } 1000 1001 static void rtw8822b_set_tx_power_index(struct rtw_dev *rtwdev) 1002 { 1003 struct rtw_hal *hal = &rtwdev->hal; 1004 int rs, path; 1005 1006 for (path = 0; path < hal->rf_path_num; path++) { 1007 for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) 1008 rtw8822b_set_tx_power_index_by_rate(rtwdev, path, rs); 1009 } 1010 } 1011 1012 static bool rtw8822b_check_rf_path(u8 antenna) 1013 { 1014 switch (antenna) { 1015 case BB_PATH_A: 1016 case BB_PATH_B: 1017 case BB_PATH_AB: 1018 return true; 1019 default: 1020 return false; 1021 } 1022 } 1023 1024 static int rtw8822b_set_antenna(struct rtw_dev *rtwdev, 1025 u32 antenna_tx, 1026 u32 antenna_rx) 1027 { 1028 struct rtw_hal *hal = &rtwdev->hal; 1029 1030 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", 1031 antenna_tx, antenna_rx); 1032 1033 if (!rtw8822b_check_rf_path(antenna_tx)) { 1034 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); 1035 return -EINVAL; 1036 } 1037 1038 if (!rtw8822b_check_rf_path(antenna_rx)) { 1039 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); 1040 return -EINVAL; 1041 } 1042 1043 hal->antenna_tx = antenna_tx; 1044 hal->antenna_rx = antenna_rx; 1045 1046 rtw8822b_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false); 1047 1048 return 0; 1049 } 1050 1051 static void rtw8822b_cfg_ldo25(struct rtw_dev *rtwdev, bool enable) 1052 { 1053 u8 ldo_pwr; 1054 1055 ldo_pwr = rtw_read8(rtwdev, REG_LDO_EFUSE_CTRL + 3); 1056 ldo_pwr = enable ? ldo_pwr | BIT_LDO25_EN : ldo_pwr & ~BIT_LDO25_EN; 1057 rtw_write8(rtwdev, REG_LDO_EFUSE_CTRL + 3, ldo_pwr); 1058 } 1059 1060 static void rtw8822b_false_alarm_statistics(struct rtw_dev *rtwdev) 1061 { 1062 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1063 u32 cck_enable; 1064 u32 cck_fa_cnt; 1065 u32 ofdm_fa_cnt; 1066 u32 crc32_cnt; 1067 u32 cca32_cnt; 1068 1069 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); 1070 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); 1071 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); 1072 1073 dm_info->cck_fa_cnt = cck_fa_cnt; 1074 dm_info->ofdm_fa_cnt = ofdm_fa_cnt; 1075 dm_info->total_fa_cnt = ofdm_fa_cnt; 1076 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; 1077 1078 crc32_cnt = rtw_read32(rtwdev, 0xf04); 1079 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; 1080 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1081 crc32_cnt = rtw_read32(rtwdev, 0xf14); 1082 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; 1083 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1084 crc32_cnt = rtw_read32(rtwdev, 0xf10); 1085 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; 1086 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1087 crc32_cnt = rtw_read32(rtwdev, 0xf0c); 1088 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; 1089 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; 1090 1091 cca32_cnt = rtw_read32(rtwdev, 0xf08); 1092 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); 1093 dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt; 1094 if (cck_enable) { 1095 cca32_cnt = rtw_read32(rtwdev, 0xfcc); 1096 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; 1097 dm_info->total_cca_cnt += dm_info->cck_cca_cnt; 1098 } 1099 1100 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); 1101 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); 1102 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); 1103 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); 1104 rtw_write32_set(rtwdev, 0xb58, BIT(0)); 1105 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); 1106 } 1107 1108 static void rtw8822b_do_iqk(struct rtw_dev *rtwdev) 1109 { 1110 static int do_iqk_cnt; 1111 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; 1112 u32 rf_reg, iqk_fail_mask; 1113 int counter; 1114 bool reload; 1115 1116 rtw_fw_do_iqk(rtwdev, ¶); 1117 1118 for (counter = 0; counter < 300; counter++) { 1119 rf_reg = rtw_read_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK); 1120 if (rf_reg == 0xabcde) 1121 break; 1122 msleep(20); 1123 } 1124 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); 1125 1126 reload = !!rtw_read32_mask(rtwdev, REG_IQKFAILMSK, BIT(16)); 1127 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); 1128 rtw_dbg(rtwdev, RTW_DBG_PHY, 1129 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", 1130 counter, reload, ++do_iqk_cnt, iqk_fail_mask); 1131 } 1132 1133 static void rtw8822b_phy_calibration(struct rtw_dev *rtwdev) 1134 { 1135 rtw8822b_do_iqk(rtwdev); 1136 } 1137 1138 static void rtw8822b_coex_cfg_init(struct rtw_dev *rtwdev) 1139 { 1140 /* enable TBTT nterrupt */ 1141 rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION); 1142 1143 /* BT report packet sample rate */ 1144 /* 0x790[5:0]=0x5 */ 1145 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); 1146 1147 /* enable BT counter statistics */ 1148 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); 1149 1150 /* enable PTA (3-wire function form BT side) */ 1151 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN); 1152 rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS); 1153 1154 /* enable PTA (tx/rx signal form WiFi side) */ 1155 rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN); 1156 /* wl tx signal to PTA not case EDCCA */ 1157 rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN); 1158 /* GNT_BT=1 while select both */ 1159 rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY); 1160 } 1161 1162 static void rtw8822b_coex_cfg_ant_switch(struct rtw_dev *rtwdev, 1163 u8 ctrl_type, u8 pos_type) 1164 { 1165 struct rtw_coex *coex = &rtwdev->coex; 1166 struct rtw_coex_dm *coex_dm = &coex->dm; 1167 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1168 bool polarity_inverse; 1169 u8 regval = 0; 1170 1171 if (((ctrl_type << 8) + pos_type) == coex_dm->cur_switch_status) 1172 return; 1173 1174 coex_dm->cur_switch_status = (ctrl_type << 8) + pos_type; 1175 1176 if (coex_rfe->ant_switch_diversity && 1177 ctrl_type == COEX_SWITCH_CTRL_BY_BBSW) 1178 ctrl_type = COEX_SWITCH_CTRL_BY_ANTDIV; 1179 1180 polarity_inverse = (coex_rfe->ant_switch_polarity == 1); 1181 1182 switch (ctrl_type) { 1183 default: 1184 case COEX_SWITCH_CTRL_BY_BBSW: 1185 /* 0x4c[23] = 0 */ 1186 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1187 /* 0x4c[24] = 1 */ 1188 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1189 /* BB SW, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1190 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); 1191 1192 if (pos_type == COEX_SWITCH_TO_WLG_BT) { 1193 if (coex_rfe->rfe_module_type != 0x4 && 1194 coex_rfe->rfe_module_type != 0x2) 1195 regval = 0x3; 1196 else 1197 regval = (!polarity_inverse ? 0x2 : 0x1); 1198 } else if (pos_type == COEX_SWITCH_TO_WLG) { 1199 regval = (!polarity_inverse ? 0x2 : 0x1); 1200 } else { 1201 regval = (!polarity_inverse ? 0x1 : 0x2); 1202 } 1203 1204 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1205 break; 1206 case COEX_SWITCH_CTRL_BY_PTA: 1207 /* 0x4c[23] = 0 */ 1208 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1209 /* 0x4c[24] = 1 */ 1210 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1211 /* PTA, DPDT use RFE_ctrl8 and RFE_ctrl9 as ctrl pin */ 1212 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); 1213 1214 regval = (!polarity_inverse ? 0x2 : 0x1); 1215 rtw_write8_mask(rtwdev, REG_RFE_INV8, BIT_MASK_RFE_INV89, regval); 1216 break; 1217 case COEX_SWITCH_CTRL_BY_ANTDIV: 1218 /* 0x4c[23] = 0 */ 1219 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1220 /* 0x4c[24] = 1 */ 1221 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1222 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); 1223 break; 1224 case COEX_SWITCH_CTRL_BY_MAC: 1225 /* 0x4c[23] = 1 */ 1226 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); 1227 1228 regval = (!polarity_inverse ? 0x0 : 0x1); 1229 rtw_write8_mask(rtwdev, REG_PAD_CTRL1, BIT_SW_DPDT_SEL_DATA, regval); 1230 break; 1231 case COEX_SWITCH_CTRL_BY_FW: 1232 /* 0x4c[23] = 0 */ 1233 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1234 /* 0x4c[24] = 1 */ 1235 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); 1236 break; 1237 case COEX_SWITCH_CTRL_BY_BT: 1238 /* 0x4c[23] = 0 */ 1239 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); 1240 /* 0x4c[24] = 0 */ 1241 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); 1242 break; 1243 } 1244 } 1245 1246 static void rtw8822b_coex_cfg_gnt_fix(struct rtw_dev *rtwdev) 1247 { 1248 } 1249 1250 static void rtw8822b_coex_cfg_gnt_debug(struct rtw_dev *rtwdev) 1251 { 1252 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); 1253 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); 1254 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); 1255 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); 1256 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); 1257 } 1258 1259 static void rtw8822b_coex_cfg_rfe_type(struct rtw_dev *rtwdev) 1260 { 1261 struct rtw_coex *coex = &rtwdev->coex; 1262 struct rtw_coex_rfe *coex_rfe = &coex->rfe; 1263 struct rtw_efuse *efuse = &rtwdev->efuse; 1264 bool is_ext_fem = false; 1265 1266 coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option; 1267 coex_rfe->ant_switch_polarity = 0; 1268 coex_rfe->ant_switch_diversity = false; 1269 if (coex_rfe->rfe_module_type == 0x12 || 1270 coex_rfe->rfe_module_type == 0x15 || 1271 coex_rfe->rfe_module_type == 0x16) 1272 coex_rfe->ant_switch_exist = false; 1273 else 1274 coex_rfe->ant_switch_exist = true; 1275 1276 if (coex_rfe->rfe_module_type == 2 || 1277 coex_rfe->rfe_module_type == 4) { 1278 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, true); 1279 is_ext_fem = true; 1280 } else { 1281 rtw_coex_write_scbd(rtwdev, COEX_SCBD_EXTFEM, false); 1282 } 1283 1284 coex_rfe->wlg_at_btg = false; 1285 1286 if (efuse->share_ant && 1287 coex_rfe->ant_switch_exist && !is_ext_fem) 1288 coex_rfe->ant_switch_with_bt = true; 1289 else 1290 coex_rfe->ant_switch_with_bt = false; 1291 1292 /* Ext switch buffer mux */ 1293 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); 1294 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); 1295 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); 1296 1297 /* Disable LTE Coex Function in WiFi side */ 1298 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); 1299 1300 /* BTC_CTT_WL_VS_LTE */ 1301 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); 1302 1303 /* BTC_CTT_BT_VS_LTE */ 1304 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); 1305 } 1306 1307 static void rtw8822b_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr) 1308 { 1309 struct rtw_coex *coex = &rtwdev->coex; 1310 struct rtw_coex_dm *coex_dm = &coex->dm; 1311 static const u16 reg_addr[] = {0xc58, 0xe58}; 1312 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; 1313 u8 i, pwr; 1314 1315 if (wl_pwr == coex_dm->cur_wl_pwr_lvl) 1316 return; 1317 1318 coex_dm->cur_wl_pwr_lvl = wl_pwr; 1319 1320 if (coex_dm->cur_wl_pwr_lvl >= ARRAY_SIZE(wl_tx_power)) 1321 coex_dm->cur_wl_pwr_lvl = ARRAY_SIZE(wl_tx_power) - 1; 1322 1323 pwr = wl_tx_power[coex_dm->cur_wl_pwr_lvl]; 1324 1325 for (i = 0; i < ARRAY_SIZE(reg_addr); i++) 1326 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); 1327 } 1328 1329 static void rtw8822b_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain) 1330 { 1331 struct rtw_coex *coex = &rtwdev->coex; 1332 struct rtw_coex_dm *coex_dm = &coex->dm; 1333 /* WL Rx Low gain on */ 1334 static const u32 wl_rx_low_gain_on[] = { 1335 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, 1336 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, 1337 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, 1338 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, 1339 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, 1340 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, 1341 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, 1342 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, 1343 0x007e0403 1344 }; 1345 1346 /* WL Rx Low gain off */ 1347 static const u32 wl_rx_low_gain_off[] = { 1348 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, 1349 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, 1350 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, 1351 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, 1352 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, 1353 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, 1354 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, 1355 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, 1356 0x007e0403 1357 }; 1358 u8 i; 1359 1360 if (low_gain == coex_dm->cur_wl_rx_low_gain_en) 1361 return; 1362 1363 coex_dm->cur_wl_rx_low_gain_en = low_gain; 1364 1365 if (coex_dm->cur_wl_rx_low_gain_en) { 1366 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n"); 1367 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) 1368 rtw_write32(rtwdev, REG_RX_GAIN_EN, wl_rx_low_gain_on[i]); 1369 1370 /* set Rx filter corner RCK offset */ 1371 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); 1372 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); 1373 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); 1374 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); 1375 } else { 1376 rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n"); 1377 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) 1378 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); 1379 1380 /* set Rx filter corner RCK offset */ 1381 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); 1382 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); 1383 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); 1384 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); 1385 } 1386 } 1387 1388 static void rtw8822b_txagc_swing_offset(struct rtw_dev *rtwdev, u8 path, 1389 u8 tx_pwr_idx_offset, 1390 s8 *txagc_idx, u8 *swing_idx) 1391 { 1392 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1393 s8 delta_pwr_idx = dm_info->delta_power_index[path]; 1394 u8 swing_upper_bound = dm_info->default_ofdm_index + 10; 1395 u8 swing_lower_bound = 0; 1396 u8 max_tx_pwr_idx_offset = 0xf; 1397 s8 agc_index = 0; 1398 u8 swing_index = dm_info->default_ofdm_index; 1399 1400 tx_pwr_idx_offset = min_t(u8, tx_pwr_idx_offset, max_tx_pwr_idx_offset); 1401 1402 if (delta_pwr_idx >= 0) { 1403 if (delta_pwr_idx <= tx_pwr_idx_offset) { 1404 agc_index = delta_pwr_idx; 1405 swing_index = dm_info->default_ofdm_index; 1406 } else if (delta_pwr_idx > tx_pwr_idx_offset) { 1407 agc_index = tx_pwr_idx_offset; 1408 swing_index = dm_info->default_ofdm_index + 1409 delta_pwr_idx - tx_pwr_idx_offset; 1410 swing_index = min_t(u8, swing_index, swing_upper_bound); 1411 } 1412 } else { 1413 if (dm_info->default_ofdm_index > abs(delta_pwr_idx)) 1414 swing_index = 1415 dm_info->default_ofdm_index + delta_pwr_idx; 1416 else 1417 swing_index = swing_lower_bound; 1418 swing_index = max_t(u8, swing_index, swing_lower_bound); 1419 1420 agc_index = 0; 1421 } 1422 1423 if (swing_index >= RTW_TXSCALE_SIZE) { 1424 rtw_warn(rtwdev, "swing index overflow\n"); 1425 swing_index = RTW_TXSCALE_SIZE - 1; 1426 } 1427 *txagc_idx = agc_index; 1428 *swing_idx = swing_index; 1429 } 1430 1431 static void rtw8822b_pwrtrack_set_pwr(struct rtw_dev *rtwdev, u8 path, 1432 u8 pwr_idx_offset) 1433 { 1434 s8 txagc_idx; 1435 u8 swing_idx; 1436 u32 reg1, reg2; 1437 1438 if (path == RF_PATH_A) { 1439 reg1 = 0xc94; 1440 reg2 = 0xc1c; 1441 } else if (path == RF_PATH_B) { 1442 reg1 = 0xe94; 1443 reg2 = 0xe1c; 1444 } else { 1445 return; 1446 } 1447 1448 rtw8822b_txagc_swing_offset(rtwdev, path, pwr_idx_offset, 1449 &txagc_idx, &swing_idx); 1450 rtw_write32_mask(rtwdev, reg1, GENMASK(29, 25), txagc_idx); 1451 rtw_write32_mask(rtwdev, reg2, GENMASK(31, 21), 1452 rtw8822b_txscale_tbl[swing_idx]); 1453 } 1454 1455 static void rtw8822b_pwrtrack_set(struct rtw_dev *rtwdev, u8 path) 1456 { 1457 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1458 u8 pwr_idx_offset, tx_pwr_idx; 1459 u8 channel = rtwdev->hal.current_channel; 1460 u8 band_width = rtwdev->hal.current_band_width; 1461 u8 regd = rtw_regd_get(rtwdev); 1462 u8 tx_rate = dm_info->tx_rate; 1463 u8 max_pwr_idx = rtwdev->chip->max_power_index; 1464 1465 tx_pwr_idx = rtw_phy_get_tx_power_index(rtwdev, path, tx_rate, 1466 band_width, channel, regd); 1467 1468 tx_pwr_idx = min_t(u8, tx_pwr_idx, max_pwr_idx); 1469 1470 pwr_idx_offset = max_pwr_idx - tx_pwr_idx; 1471 1472 rtw8822b_pwrtrack_set_pwr(rtwdev, path, pwr_idx_offset); 1473 } 1474 1475 static void rtw8822b_phy_pwrtrack_path(struct rtw_dev *rtwdev, 1476 struct rtw_swing_table *swing_table, 1477 u8 path) 1478 { 1479 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1480 u8 power_idx_cur, power_idx_last; 1481 u8 delta; 1482 1483 /* 8822B only has one thermal meter at PATH A */ 1484 delta = rtw_phy_pwrtrack_get_delta(rtwdev, RF_PATH_A); 1485 1486 power_idx_last = dm_info->delta_power_index[path]; 1487 power_idx_cur = rtw_phy_pwrtrack_get_pwridx(rtwdev, swing_table, 1488 path, RF_PATH_A, delta); 1489 1490 /* if delta of power indexes are the same, just skip */ 1491 if (power_idx_cur == power_idx_last) 1492 return; 1493 1494 dm_info->delta_power_index[path] = power_idx_cur; 1495 rtw8822b_pwrtrack_set(rtwdev, path); 1496 } 1497 1498 static void rtw8822b_phy_pwrtrack(struct rtw_dev *rtwdev) 1499 { 1500 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1501 struct rtw_swing_table swing_table; 1502 u8 thermal_value, path; 1503 1504 rtw_phy_config_swing_table(rtwdev, &swing_table); 1505 1506 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) 1507 return; 1508 1509 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); 1510 1511 rtw_phy_pwrtrack_avg(rtwdev, thermal_value, RF_PATH_A); 1512 1513 if (dm_info->pwr_trk_init_trigger) 1514 dm_info->pwr_trk_init_trigger = false; 1515 else if (!rtw_phy_pwrtrack_thermal_changed(rtwdev, thermal_value, 1516 RF_PATH_A)) 1517 goto iqk; 1518 1519 for (path = 0; path < rtwdev->hal.rf_path_num; path++) 1520 rtw8822b_phy_pwrtrack_path(rtwdev, &swing_table, path); 1521 1522 iqk: 1523 if (rtw_phy_pwrtrack_need_iqk(rtwdev)) 1524 rtw8822b_do_iqk(rtwdev); 1525 } 1526 1527 static void rtw8822b_pwr_track(struct rtw_dev *rtwdev) 1528 { 1529 struct rtw_efuse *efuse = &rtwdev->efuse; 1530 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1531 1532 if (efuse->power_track_type != 0) 1533 return; 1534 1535 if (!dm_info->pwr_trk_triggered) { 1536 rtw_write_rf(rtwdev, RF_PATH_A, RF_T_METER, 1537 GENMASK(17, 16), 0x03); 1538 dm_info->pwr_trk_triggered = true; 1539 return; 1540 } 1541 1542 rtw8822b_phy_pwrtrack(rtwdev); 1543 dm_info->pwr_trk_triggered = false; 1544 } 1545 1546 static void rtw8822b_bf_config_bfee_su(struct rtw_dev *rtwdev, 1547 struct rtw_vif *vif, 1548 struct rtw_bfee *bfee, bool enable) 1549 { 1550 if (enable) 1551 rtw_bf_enable_bfee_su(rtwdev, vif, bfee); 1552 else 1553 rtw_bf_remove_bfee_su(rtwdev, bfee); 1554 } 1555 1556 static void rtw8822b_bf_config_bfee_mu(struct rtw_dev *rtwdev, 1557 struct rtw_vif *vif, 1558 struct rtw_bfee *bfee, bool enable) 1559 { 1560 if (enable) 1561 rtw_bf_enable_bfee_mu(rtwdev, vif, bfee); 1562 else 1563 rtw_bf_remove_bfee_mu(rtwdev, bfee); 1564 } 1565 1566 static void rtw8822b_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif, 1567 struct rtw_bfee *bfee, bool enable) 1568 { 1569 if (bfee->role == RTW_BFEE_SU) 1570 rtw8822b_bf_config_bfee_su(rtwdev, vif, bfee, enable); 1571 else if (bfee->role == RTW_BFEE_MU) 1572 rtw8822b_bf_config_bfee_mu(rtwdev, vif, bfee, enable); 1573 else 1574 rtw_warn(rtwdev, "wrong bfee role\n"); 1575 } 1576 1577 static void rtw8822b_adaptivity_init(struct rtw_dev *rtwdev) 1578 { 1579 rtw_phy_set_edcca_th(rtwdev, RTW8822B_EDCCA_MAX, RTW8822B_EDCCA_MAX); 1580 1581 /* mac edcca state setting */ 1582 rtw_write32_clr(rtwdev, REG_TX_PTCL_CTRL, BIT_DIS_EDCCA); 1583 rtw_write32_set(rtwdev, REG_RD_CTRL, BIT_EDCCA_MSK_CNTDOWN_EN); 1584 rtw_write32_mask(rtwdev, REG_EDCCA_SOURCE, BIT_SOURCE_OPTION, 1585 RTW8822B_EDCCA_SRC_DEF); 1586 rtw_write32_mask(rtwdev, REG_EDCCA_POW_MA, BIT_MA_LEVEL, 0); 1587 1588 /* edcca decision opt */ 1589 rtw_write32_set(rtwdev, REG_EDCCA_DECISION, BIT_EDCCA_OPTION); 1590 } 1591 1592 static void rtw8822b_adaptivity(struct rtw_dev *rtwdev) 1593 { 1594 struct rtw_dm_info *dm_info = &rtwdev->dm_info; 1595 s8 l2h, h2l; 1596 u8 igi; 1597 1598 igi = dm_info->igi_history[0]; 1599 if (dm_info->edcca_mode == RTW_EDCCA_NORMAL) { 1600 l2h = max_t(s8, igi + EDCCA_IGI_L2H_DIFF, EDCCA_TH_L2H_LB); 1601 h2l = l2h - EDCCA_L2H_H2L_DIFF_NORMAL; 1602 } else { 1603 l2h = min_t(s8, igi, dm_info->l2h_th_ini); 1604 h2l = l2h - EDCCA_L2H_H2L_DIFF; 1605 } 1606 1607 rtw_phy_set_edcca_th(rtwdev, l2h, h2l); 1608 } 1609 1610 static void rtw8822b_fill_txdesc_checksum(struct rtw_dev *rtwdev, 1611 struct rtw_tx_pkt_info *pkt_info, 1612 u8 *txdesc) 1613 { 1614 size_t words = 32 / 2; /* calculate the first 32 bytes (16 words) */ 1615 1616 fill_txdesc_checksum_common(txdesc, words); 1617 } 1618 1619 static const struct rtw_pwr_seq_cmd trans_carddis_to_cardemu_8822b[] = { 1620 {0x0086, 1621 RTW_PWR_CUT_ALL_MSK, 1622 RTW_PWR_INTF_SDIO_MSK, 1623 RTW_PWR_ADDR_SDIO, 1624 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1625 {0x0086, 1626 RTW_PWR_CUT_ALL_MSK, 1627 RTW_PWR_INTF_SDIO_MSK, 1628 RTW_PWR_ADDR_SDIO, 1629 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1630 {0x004A, 1631 RTW_PWR_CUT_ALL_MSK, 1632 RTW_PWR_INTF_USB_MSK, 1633 RTW_PWR_ADDR_MAC, 1634 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1635 {0x0005, 1636 RTW_PWR_CUT_ALL_MSK, 1637 RTW_PWR_INTF_ALL_MSK, 1638 RTW_PWR_ADDR_MAC, 1639 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0}, 1640 {0x0300, 1641 RTW_PWR_CUT_ALL_MSK, 1642 RTW_PWR_INTF_PCI_MSK, 1643 RTW_PWR_ADDR_MAC, 1644 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1645 {0x0301, 1646 RTW_PWR_CUT_ALL_MSK, 1647 RTW_PWR_INTF_PCI_MSK, 1648 RTW_PWR_ADDR_MAC, 1649 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1650 {0xFFFF, 1651 RTW_PWR_CUT_ALL_MSK, 1652 RTW_PWR_INTF_ALL_MSK, 1653 0, 1654 RTW_PWR_CMD_END, 0, 0}, 1655 }; 1656 1657 static const struct rtw_pwr_seq_cmd trans_cardemu_to_act_8822b[] = { 1658 {0x0012, 1659 RTW_PWR_CUT_ALL_MSK, 1660 RTW_PWR_INTF_ALL_MSK, 1661 RTW_PWR_ADDR_MAC, 1662 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1663 {0x0012, 1664 RTW_PWR_CUT_ALL_MSK, 1665 RTW_PWR_INTF_ALL_MSK, 1666 RTW_PWR_ADDR_MAC, 1667 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1668 {0x0020, 1669 RTW_PWR_CUT_ALL_MSK, 1670 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1671 RTW_PWR_ADDR_MAC, 1672 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1673 {0x0001, 1674 RTW_PWR_CUT_ALL_MSK, 1675 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1676 RTW_PWR_ADDR_MAC, 1677 RTW_PWR_CMD_DELAY, 1, RTW_PWR_DELAY_MS}, 1678 {0x0000, 1679 RTW_PWR_CUT_ALL_MSK, 1680 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1681 RTW_PWR_ADDR_MAC, 1682 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1683 {0x0005, 1684 RTW_PWR_CUT_ALL_MSK, 1685 RTW_PWR_INTF_ALL_MSK, 1686 RTW_PWR_ADDR_MAC, 1687 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0}, 1688 {0x0075, 1689 RTW_PWR_CUT_ALL_MSK, 1690 RTW_PWR_INTF_PCI_MSK, 1691 RTW_PWR_ADDR_MAC, 1692 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1693 {0x0006, 1694 RTW_PWR_CUT_ALL_MSK, 1695 RTW_PWR_INTF_ALL_MSK, 1696 RTW_PWR_ADDR_MAC, 1697 RTW_PWR_CMD_POLLING, BIT(1), BIT(1)}, 1698 {0x0075, 1699 RTW_PWR_CUT_ALL_MSK, 1700 RTW_PWR_INTF_PCI_MSK, 1701 RTW_PWR_ADDR_MAC, 1702 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1703 {0xFF1A, 1704 RTW_PWR_CUT_ALL_MSK, 1705 RTW_PWR_INTF_USB_MSK, 1706 RTW_PWR_ADDR_MAC, 1707 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1708 {0x0006, 1709 RTW_PWR_CUT_ALL_MSK, 1710 RTW_PWR_INTF_ALL_MSK, 1711 RTW_PWR_ADDR_MAC, 1712 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1713 {0x0005, 1714 RTW_PWR_CUT_ALL_MSK, 1715 RTW_PWR_INTF_ALL_MSK, 1716 RTW_PWR_ADDR_MAC, 1717 RTW_PWR_CMD_WRITE, BIT(7), 0}, 1718 {0x0005, 1719 RTW_PWR_CUT_ALL_MSK, 1720 RTW_PWR_INTF_ALL_MSK, 1721 RTW_PWR_ADDR_MAC, 1722 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0}, 1723 {0x10C3, 1724 RTW_PWR_CUT_ALL_MSK, 1725 RTW_PWR_INTF_USB_MSK, 1726 RTW_PWR_ADDR_MAC, 1727 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1728 {0x0005, 1729 RTW_PWR_CUT_ALL_MSK, 1730 RTW_PWR_INTF_ALL_MSK, 1731 RTW_PWR_ADDR_MAC, 1732 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1733 {0x0005, 1734 RTW_PWR_CUT_ALL_MSK, 1735 RTW_PWR_INTF_ALL_MSK, 1736 RTW_PWR_ADDR_MAC, 1737 RTW_PWR_CMD_POLLING, BIT(0), 0}, 1738 {0x0020, 1739 RTW_PWR_CUT_ALL_MSK, 1740 RTW_PWR_INTF_ALL_MSK, 1741 RTW_PWR_ADDR_MAC, 1742 RTW_PWR_CMD_WRITE, BIT(3), BIT(3)}, 1743 {0x10A8, 1744 RTW_PWR_CUT_C_MSK, 1745 RTW_PWR_INTF_ALL_MSK, 1746 RTW_PWR_ADDR_MAC, 1747 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1748 {0x10A9, 1749 RTW_PWR_CUT_C_MSK, 1750 RTW_PWR_INTF_ALL_MSK, 1751 RTW_PWR_ADDR_MAC, 1752 RTW_PWR_CMD_WRITE, 0xFF, 0xef}, 1753 {0x10AA, 1754 RTW_PWR_CUT_C_MSK, 1755 RTW_PWR_INTF_ALL_MSK, 1756 RTW_PWR_ADDR_MAC, 1757 RTW_PWR_CMD_WRITE, 0xFF, 0x0c}, 1758 {0x0068, 1759 RTW_PWR_CUT_C_MSK, 1760 RTW_PWR_INTF_SDIO_MSK, 1761 RTW_PWR_ADDR_MAC, 1762 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1763 {0x0029, 1764 RTW_PWR_CUT_ALL_MSK, 1765 RTW_PWR_INTF_ALL_MSK, 1766 RTW_PWR_ADDR_MAC, 1767 RTW_PWR_CMD_WRITE, 0xFF, 0xF9}, 1768 {0x0024, 1769 RTW_PWR_CUT_ALL_MSK, 1770 RTW_PWR_INTF_ALL_MSK, 1771 RTW_PWR_ADDR_MAC, 1772 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1773 {0x0074, 1774 RTW_PWR_CUT_ALL_MSK, 1775 RTW_PWR_INTF_PCI_MSK, 1776 RTW_PWR_ADDR_MAC, 1777 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1778 {0x00AF, 1779 RTW_PWR_CUT_ALL_MSK, 1780 RTW_PWR_INTF_ALL_MSK, 1781 RTW_PWR_ADDR_MAC, 1782 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1783 {0xFFFF, 1784 RTW_PWR_CUT_ALL_MSK, 1785 RTW_PWR_INTF_ALL_MSK, 1786 0, 1787 RTW_PWR_CMD_END, 0, 0}, 1788 }; 1789 1790 static const struct rtw_pwr_seq_cmd trans_act_to_cardemu_8822b[] = { 1791 {0x0003, 1792 RTW_PWR_CUT_ALL_MSK, 1793 RTW_PWR_INTF_SDIO_MSK, 1794 RTW_PWR_ADDR_MAC, 1795 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1796 {0x0093, 1797 RTW_PWR_CUT_ALL_MSK, 1798 RTW_PWR_INTF_ALL_MSK, 1799 RTW_PWR_ADDR_MAC, 1800 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1801 {0x001F, 1802 RTW_PWR_CUT_ALL_MSK, 1803 RTW_PWR_INTF_ALL_MSK, 1804 RTW_PWR_ADDR_MAC, 1805 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1806 {0x00EF, 1807 RTW_PWR_CUT_ALL_MSK, 1808 RTW_PWR_INTF_ALL_MSK, 1809 RTW_PWR_ADDR_MAC, 1810 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1811 {0xFF1A, 1812 RTW_PWR_CUT_ALL_MSK, 1813 RTW_PWR_INTF_USB_MSK, 1814 RTW_PWR_ADDR_MAC, 1815 RTW_PWR_CMD_WRITE, 0xFF, 0x30}, 1816 {0x0049, 1817 RTW_PWR_CUT_ALL_MSK, 1818 RTW_PWR_INTF_ALL_MSK, 1819 RTW_PWR_ADDR_MAC, 1820 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1821 {0x0006, 1822 RTW_PWR_CUT_ALL_MSK, 1823 RTW_PWR_INTF_ALL_MSK, 1824 RTW_PWR_ADDR_MAC, 1825 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1826 {0x0002, 1827 RTW_PWR_CUT_ALL_MSK, 1828 RTW_PWR_INTF_ALL_MSK, 1829 RTW_PWR_ADDR_MAC, 1830 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1831 {0x10C3, 1832 RTW_PWR_CUT_ALL_MSK, 1833 RTW_PWR_INTF_USB_MSK, 1834 RTW_PWR_ADDR_MAC, 1835 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1836 {0x0005, 1837 RTW_PWR_CUT_ALL_MSK, 1838 RTW_PWR_INTF_ALL_MSK, 1839 RTW_PWR_ADDR_MAC, 1840 RTW_PWR_CMD_WRITE, BIT(1), BIT(1)}, 1841 {0x0005, 1842 RTW_PWR_CUT_ALL_MSK, 1843 RTW_PWR_INTF_ALL_MSK, 1844 RTW_PWR_ADDR_MAC, 1845 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1846 {0x0020, 1847 RTW_PWR_CUT_ALL_MSK, 1848 RTW_PWR_INTF_ALL_MSK, 1849 RTW_PWR_ADDR_MAC, 1850 RTW_PWR_CMD_WRITE, BIT(3), 0}, 1851 {0x0000, 1852 RTW_PWR_CUT_ALL_MSK, 1853 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1854 RTW_PWR_ADDR_MAC, 1855 RTW_PWR_CMD_WRITE, BIT(5), BIT(5)}, 1856 {0xFFFF, 1857 RTW_PWR_CUT_ALL_MSK, 1858 RTW_PWR_INTF_ALL_MSK, 1859 0, 1860 RTW_PWR_CMD_END, 0, 0}, 1861 }; 1862 1863 static const struct rtw_pwr_seq_cmd trans_cardemu_to_carddis_8822b[] = { 1864 {0x0005, 1865 RTW_PWR_CUT_ALL_MSK, 1866 RTW_PWR_INTF_SDIO_MSK, 1867 RTW_PWR_ADDR_MAC, 1868 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1869 {0x0007, 1870 RTW_PWR_CUT_ALL_MSK, 1871 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1872 RTW_PWR_ADDR_MAC, 1873 RTW_PWR_CMD_WRITE, 0xFF, 0x20}, 1874 {0x0067, 1875 RTW_PWR_CUT_ALL_MSK, 1876 RTW_PWR_INTF_ALL_MSK, 1877 RTW_PWR_ADDR_MAC, 1878 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1879 {0x0005, 1880 RTW_PWR_CUT_ALL_MSK, 1881 RTW_PWR_INTF_PCI_MSK, 1882 RTW_PWR_ADDR_MAC, 1883 RTW_PWR_CMD_WRITE, BIT(2), BIT(2)}, 1884 {0x004A, 1885 RTW_PWR_CUT_ALL_MSK, 1886 RTW_PWR_INTF_USB_MSK, 1887 RTW_PWR_ADDR_MAC, 1888 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1889 {0x0067, 1890 RTW_PWR_CUT_ALL_MSK, 1891 RTW_PWR_INTF_SDIO_MSK, 1892 RTW_PWR_ADDR_MAC, 1893 RTW_PWR_CMD_WRITE, BIT(5), 0}, 1894 {0x0067, 1895 RTW_PWR_CUT_ALL_MSK, 1896 RTW_PWR_INTF_SDIO_MSK, 1897 RTW_PWR_ADDR_MAC, 1898 RTW_PWR_CMD_WRITE, BIT(4), 0}, 1899 {0x004F, 1900 RTW_PWR_CUT_ALL_MSK, 1901 RTW_PWR_INTF_SDIO_MSK, 1902 RTW_PWR_ADDR_MAC, 1903 RTW_PWR_CMD_WRITE, BIT(0), 0}, 1904 {0x0067, 1905 RTW_PWR_CUT_ALL_MSK, 1906 RTW_PWR_INTF_SDIO_MSK, 1907 RTW_PWR_ADDR_MAC, 1908 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1909 {0x0046, 1910 RTW_PWR_CUT_ALL_MSK, 1911 RTW_PWR_INTF_SDIO_MSK, 1912 RTW_PWR_ADDR_MAC, 1913 RTW_PWR_CMD_WRITE, BIT(6), BIT(6)}, 1914 {0x0067, 1915 RTW_PWR_CUT_ALL_MSK, 1916 RTW_PWR_INTF_SDIO_MSK, 1917 RTW_PWR_ADDR_MAC, 1918 RTW_PWR_CMD_WRITE, BIT(2), 0}, 1919 {0x0046, 1920 RTW_PWR_CUT_ALL_MSK, 1921 RTW_PWR_INTF_SDIO_MSK, 1922 RTW_PWR_ADDR_MAC, 1923 RTW_PWR_CMD_WRITE, BIT(7), BIT(7)}, 1924 {0x0062, 1925 RTW_PWR_CUT_ALL_MSK, 1926 RTW_PWR_INTF_SDIO_MSK, 1927 RTW_PWR_ADDR_MAC, 1928 RTW_PWR_CMD_WRITE, BIT(4), BIT(4)}, 1929 {0x0081, 1930 RTW_PWR_CUT_ALL_MSK, 1931 RTW_PWR_INTF_ALL_MSK, 1932 RTW_PWR_ADDR_MAC, 1933 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0}, 1934 {0x0005, 1935 RTW_PWR_CUT_ALL_MSK, 1936 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_SDIO_MSK, 1937 RTW_PWR_ADDR_MAC, 1938 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, 1939 {0x0086, 1940 RTW_PWR_CUT_ALL_MSK, 1941 RTW_PWR_INTF_SDIO_MSK, 1942 RTW_PWR_ADDR_SDIO, 1943 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)}, 1944 {0x0086, 1945 RTW_PWR_CUT_ALL_MSK, 1946 RTW_PWR_INTF_SDIO_MSK, 1947 RTW_PWR_ADDR_SDIO, 1948 RTW_PWR_CMD_POLLING, BIT(1), 0}, 1949 {0x0090, 1950 RTW_PWR_CUT_ALL_MSK, 1951 RTW_PWR_INTF_USB_MSK | RTW_PWR_INTF_PCI_MSK, 1952 RTW_PWR_ADDR_MAC, 1953 RTW_PWR_CMD_WRITE, BIT(1), 0}, 1954 {0x0044, 1955 RTW_PWR_CUT_ALL_MSK, 1956 RTW_PWR_INTF_SDIO_MSK, 1957 RTW_PWR_ADDR_SDIO, 1958 RTW_PWR_CMD_WRITE, 0xFF, 0}, 1959 {0x0040, 1960 RTW_PWR_CUT_ALL_MSK, 1961 RTW_PWR_INTF_SDIO_MSK, 1962 RTW_PWR_ADDR_SDIO, 1963 RTW_PWR_CMD_WRITE, 0xFF, 0x90}, 1964 {0x0041, 1965 RTW_PWR_CUT_ALL_MSK, 1966 RTW_PWR_INTF_SDIO_MSK, 1967 RTW_PWR_ADDR_SDIO, 1968 RTW_PWR_CMD_WRITE, 0xFF, 0x00}, 1969 {0x0042, 1970 RTW_PWR_CUT_ALL_MSK, 1971 RTW_PWR_INTF_SDIO_MSK, 1972 RTW_PWR_ADDR_SDIO, 1973 RTW_PWR_CMD_WRITE, 0xFF, 0x04}, 1974 {0xFFFF, 1975 RTW_PWR_CUT_ALL_MSK, 1976 RTW_PWR_INTF_ALL_MSK, 1977 0, 1978 RTW_PWR_CMD_END, 0, 0}, 1979 }; 1980 1981 static const struct rtw_pwr_seq_cmd *card_enable_flow_8822b[] = { 1982 trans_carddis_to_cardemu_8822b, 1983 trans_cardemu_to_act_8822b, 1984 NULL 1985 }; 1986 1987 static const struct rtw_pwr_seq_cmd *card_disable_flow_8822b[] = { 1988 trans_act_to_cardemu_8822b, 1989 trans_cardemu_to_carddis_8822b, 1990 NULL 1991 }; 1992 1993 static const struct rtw_intf_phy_para usb2_param_8822b[] = { 1994 {0xFFFF, 0x00, 1995 RTW_IP_SEL_PHY, 1996 RTW_INTF_PHY_CUT_ALL, 1997 RTW_INTF_PHY_PLATFORM_ALL}, 1998 }; 1999 2000 static const struct rtw_intf_phy_para usb3_param_8822b[] = { 2001 {0x0001, 0xA841, 2002 RTW_IP_SEL_PHY, 2003 RTW_INTF_PHY_CUT_D, 2004 RTW_INTF_PHY_PLATFORM_ALL}, 2005 {0xFFFF, 0x0000, 2006 RTW_IP_SEL_PHY, 2007 RTW_INTF_PHY_CUT_ALL, 2008 RTW_INTF_PHY_PLATFORM_ALL}, 2009 }; 2010 2011 static const struct rtw_intf_phy_para pcie_gen1_param_8822b[] = { 2012 {0x0001, 0xA841, 2013 RTW_IP_SEL_PHY, 2014 RTW_INTF_PHY_CUT_C, 2015 RTW_INTF_PHY_PLATFORM_ALL}, 2016 {0x0002, 0x60C6, 2017 RTW_IP_SEL_PHY, 2018 RTW_INTF_PHY_CUT_C, 2019 RTW_INTF_PHY_PLATFORM_ALL}, 2020 {0x0008, 0x3596, 2021 RTW_IP_SEL_PHY, 2022 RTW_INTF_PHY_CUT_C, 2023 RTW_INTF_PHY_PLATFORM_ALL}, 2024 {0x0009, 0x321C, 2025 RTW_IP_SEL_PHY, 2026 RTW_INTF_PHY_CUT_C, 2027 RTW_INTF_PHY_PLATFORM_ALL}, 2028 {0x000A, 0x9623, 2029 RTW_IP_SEL_PHY, 2030 RTW_INTF_PHY_CUT_C, 2031 RTW_INTF_PHY_PLATFORM_ALL}, 2032 {0x0020, 0x94FF, 2033 RTW_IP_SEL_PHY, 2034 RTW_INTF_PHY_CUT_C, 2035 RTW_INTF_PHY_PLATFORM_ALL}, 2036 {0x0021, 0xFFCF, 2037 RTW_IP_SEL_PHY, 2038 RTW_INTF_PHY_CUT_C, 2039 RTW_INTF_PHY_PLATFORM_ALL}, 2040 {0x0026, 0xC006, 2041 RTW_IP_SEL_PHY, 2042 RTW_INTF_PHY_CUT_C, 2043 RTW_INTF_PHY_PLATFORM_ALL}, 2044 {0x0029, 0xFF0E, 2045 RTW_IP_SEL_PHY, 2046 RTW_INTF_PHY_CUT_C, 2047 RTW_INTF_PHY_PLATFORM_ALL}, 2048 {0x002A, 0x1840, 2049 RTW_IP_SEL_PHY, 2050 RTW_INTF_PHY_CUT_C, 2051 RTW_INTF_PHY_PLATFORM_ALL}, 2052 {0xFFFF, 0x0000, 2053 RTW_IP_SEL_PHY, 2054 RTW_INTF_PHY_CUT_ALL, 2055 RTW_INTF_PHY_PLATFORM_ALL}, 2056 }; 2057 2058 static const struct rtw_intf_phy_para pcie_gen2_param_8822b[] = { 2059 {0x0001, 0xA841, 2060 RTW_IP_SEL_PHY, 2061 RTW_INTF_PHY_CUT_C, 2062 RTW_INTF_PHY_PLATFORM_ALL}, 2063 {0x0002, 0x60C6, 2064 RTW_IP_SEL_PHY, 2065 RTW_INTF_PHY_CUT_C, 2066 RTW_INTF_PHY_PLATFORM_ALL}, 2067 {0x0008, 0x3597, 2068 RTW_IP_SEL_PHY, 2069 RTW_INTF_PHY_CUT_C, 2070 RTW_INTF_PHY_PLATFORM_ALL}, 2071 {0x0009, 0x321C, 2072 RTW_IP_SEL_PHY, 2073 RTW_INTF_PHY_CUT_C, 2074 RTW_INTF_PHY_PLATFORM_ALL}, 2075 {0x000A, 0x9623, 2076 RTW_IP_SEL_PHY, 2077 RTW_INTF_PHY_CUT_C, 2078 RTW_INTF_PHY_PLATFORM_ALL}, 2079 {0x0020, 0x94FF, 2080 RTW_IP_SEL_PHY, 2081 RTW_INTF_PHY_CUT_C, 2082 RTW_INTF_PHY_PLATFORM_ALL}, 2083 {0x0021, 0xFFCF, 2084 RTW_IP_SEL_PHY, 2085 RTW_INTF_PHY_CUT_C, 2086 RTW_INTF_PHY_PLATFORM_ALL}, 2087 {0x0026, 0xC006, 2088 RTW_IP_SEL_PHY, 2089 RTW_INTF_PHY_CUT_C, 2090 RTW_INTF_PHY_PLATFORM_ALL}, 2091 {0x0029, 0xFF0E, 2092 RTW_IP_SEL_PHY, 2093 RTW_INTF_PHY_CUT_C, 2094 RTW_INTF_PHY_PLATFORM_ALL}, 2095 {0x002A, 0x3040, 2096 RTW_IP_SEL_PHY, 2097 RTW_INTF_PHY_CUT_C, 2098 RTW_INTF_PHY_PLATFORM_ALL}, 2099 {0xFFFF, 0x0000, 2100 RTW_IP_SEL_PHY, 2101 RTW_INTF_PHY_CUT_ALL, 2102 RTW_INTF_PHY_PLATFORM_ALL}, 2103 }; 2104 2105 static const struct rtw_intf_phy_para_table phy_para_table_8822b = { 2106 .usb2_para = usb2_param_8822b, 2107 .usb3_para = usb3_param_8822b, 2108 .gen1_para = pcie_gen1_param_8822b, 2109 .gen2_para = pcie_gen2_param_8822b, 2110 .n_usb2_para = ARRAY_SIZE(usb2_param_8822b), 2111 .n_usb3_para = ARRAY_SIZE(usb2_param_8822b), 2112 .n_gen1_para = ARRAY_SIZE(pcie_gen1_param_8822b), 2113 .n_gen2_para = ARRAY_SIZE(pcie_gen2_param_8822b), 2114 }; 2115 2116 static const struct rtw_rfe_def rtw8822b_rfe_defs[] = { 2117 [2] = RTW_DEF_RFE(8822b, 2, 2), 2118 [3] = RTW_DEF_RFE(8822b, 3, 0), 2119 [5] = RTW_DEF_RFE(8822b, 5, 5), 2120 }; 2121 2122 static const struct rtw_hw_reg rtw8822b_dig[] = { 2123 [0] = { .addr = 0xc50, .mask = 0x7f }, 2124 [1] = { .addr = 0xe50, .mask = 0x7f }, 2125 }; 2126 2127 static const struct rtw_ltecoex_addr rtw8822b_ltecoex_addr = { 2128 .ctrl = LTECOEX_ACCESS_CTRL, 2129 .wdata = LTECOEX_WRITE_DATA, 2130 .rdata = LTECOEX_READ_DATA, 2131 }; 2132 2133 static const struct rtw_page_table page_table_8822b[] = { 2134 {64, 64, 64, 64, 1}, 2135 {64, 64, 64, 64, 1}, 2136 {64, 64, 0, 0, 1}, 2137 {64, 64, 64, 0, 1}, 2138 {64, 64, 64, 64, 1}, 2139 }; 2140 2141 static const struct rtw_rqpn rqpn_table_8822b[] = { 2142 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2143 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2144 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2145 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2146 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2147 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2148 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2149 RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_HIGH, 2150 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2151 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2152 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2153 RTW_DMA_MAPPING_HIGH, RTW_DMA_MAPPING_HIGH}, 2154 {RTW_DMA_MAPPING_NORMAL, RTW_DMA_MAPPING_NORMAL, 2155 RTW_DMA_MAPPING_LOW, RTW_DMA_MAPPING_LOW, 2156 RTW_DMA_MAPPING_EXTRA, RTW_DMA_MAPPING_HIGH}, 2157 }; 2158 2159 static struct rtw_prioq_addrs prioq_addrs_8822b = { 2160 .prio[RTW_DMA_MAPPING_EXTRA] = { 2161 .rsvd = REG_FIFOPAGE_INFO_4, .avail = REG_FIFOPAGE_INFO_4 + 2, 2162 }, 2163 .prio[RTW_DMA_MAPPING_LOW] = { 2164 .rsvd = REG_FIFOPAGE_INFO_2, .avail = REG_FIFOPAGE_INFO_2 + 2, 2165 }, 2166 .prio[RTW_DMA_MAPPING_NORMAL] = { 2167 .rsvd = REG_FIFOPAGE_INFO_3, .avail = REG_FIFOPAGE_INFO_3 + 2, 2168 }, 2169 .prio[RTW_DMA_MAPPING_HIGH] = { 2170 .rsvd = REG_FIFOPAGE_INFO_1, .avail = REG_FIFOPAGE_INFO_1 + 2, 2171 }, 2172 .wsize = true, 2173 }; 2174 2175 static struct rtw_chip_ops rtw8822b_ops = { 2176 .phy_set_param = rtw8822b_phy_set_param, 2177 .read_efuse = rtw8822b_read_efuse, 2178 .query_rx_desc = rtw8822b_query_rx_desc, 2179 .set_channel = rtw8822b_set_channel, 2180 .mac_init = rtw8822b_mac_init, 2181 .read_rf = rtw_phy_read_rf, 2182 .write_rf = rtw_phy_write_rf_reg_sipi, 2183 .set_tx_power_index = rtw8822b_set_tx_power_index, 2184 .set_antenna = rtw8822b_set_antenna, 2185 .cfg_ldo25 = rtw8822b_cfg_ldo25, 2186 .false_alarm_statistics = rtw8822b_false_alarm_statistics, 2187 .phy_calibration = rtw8822b_phy_calibration, 2188 .pwr_track = rtw8822b_pwr_track, 2189 .config_bfee = rtw8822b_bf_config_bfee, 2190 .set_gid_table = rtw_bf_set_gid_table, 2191 .cfg_csi_rate = rtw_bf_cfg_csi_rate, 2192 .adaptivity_init = rtw8822b_adaptivity_init, 2193 .adaptivity = rtw8822b_adaptivity, 2194 .fill_txdesc_checksum = rtw8822b_fill_txdesc_checksum, 2195 2196 .coex_set_init = rtw8822b_coex_cfg_init, 2197 .coex_set_ant_switch = rtw8822b_coex_cfg_ant_switch, 2198 .coex_set_gnt_fix = rtw8822b_coex_cfg_gnt_fix, 2199 .coex_set_gnt_debug = rtw8822b_coex_cfg_gnt_debug, 2200 .coex_set_rfe_type = rtw8822b_coex_cfg_rfe_type, 2201 .coex_set_wl_tx_power = rtw8822b_coex_cfg_wl_tx_power, 2202 .coex_set_wl_rx_gain = rtw8822b_coex_cfg_wl_rx_gain, 2203 }; 2204 2205 /* Shared-Antenna Coex Table */ 2206 static const struct coex_table_para table_sant_8822b[] = { 2207 {0xffffffff, 0xffffffff}, /* case-0 */ 2208 {0x55555555, 0x55555555}, 2209 {0x66555555, 0x66555555}, 2210 {0xaaaaaaaa, 0xaaaaaaaa}, 2211 {0x5a5a5a5a, 0x5a5a5a5a}, 2212 {0xfafafafa, 0xfafafafa}, /* case-5 */ 2213 {0x6a5a5555, 0xaaaaaaaa}, 2214 {0x6a5a56aa, 0x6a5a56aa}, 2215 {0x6a5a5a5a, 0x6a5a5a5a}, 2216 {0x66555555, 0x5a5a5a5a}, 2217 {0x66555555, 0x6a5a5a5a}, /* case-10 */ 2218 {0x66555555, 0xfafafafa}, 2219 {0x66555555, 0x5a5a5aaa}, 2220 {0x66555555, 0x6aaa5aaa}, 2221 {0x66555555, 0xaaaa5aaa}, 2222 {0x66555555, 0xaaaaaaaa}, /* case-15 */ 2223 {0xffff55ff, 0xfafafafa}, 2224 {0xffff55ff, 0x6afa5afa}, 2225 {0xaaffffaa, 0xfafafafa}, 2226 {0xaa5555aa, 0x5a5a5a5a}, 2227 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */ 2228 {0xaa5555aa, 0xaaaaaaaa}, 2229 {0xffffffff, 0x5a5a5a5a}, 2230 {0xffffffff, 0x5a5a5a5a}, 2231 {0xffffffff, 0x55555555}, 2232 {0xffffffff, 0x6a5a5aaa}, /* case-25 */ 2233 {0x55555555, 0x5a5a5a5a}, 2234 {0x55555555, 0xaaaaaaaa}, 2235 {0x55555555, 0x6a5a6a5a}, 2236 {0x66556655, 0x66556655}, 2237 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */ 2238 {0xffffffff, 0x5aaa5aaa}, 2239 {0x56555555, 0x5a5a5aaa}, 2240 }; 2241 2242 /* Non-Shared-Antenna Coex Table */ 2243 static const struct coex_table_para table_nsant_8822b[] = { 2244 {0xffffffff, 0xffffffff}, /* case-100 */ 2245 {0x55555555, 0x55555555}, 2246 {0x66555555, 0x66555555}, 2247 {0xaaaaaaaa, 0xaaaaaaaa}, 2248 {0x5a5a5a5a, 0x5a5a5a5a}, 2249 {0xfafafafa, 0xfafafafa}, /* case-105 */ 2250 {0x5afa5afa, 0x5afa5afa}, 2251 {0x55555555, 0xfafafafa}, 2252 {0x66555555, 0xfafafafa}, 2253 {0x66555555, 0x5a5a5a5a}, 2254 {0x66555555, 0x6a5a5a5a}, /* case-110 */ 2255 {0x66555555, 0xaaaaaaaa}, 2256 {0xffff55ff, 0xfafafafa}, 2257 {0xffff55ff, 0x5afa5afa}, 2258 {0xffff55ff, 0xaaaaaaaa}, 2259 {0xffff55ff, 0xffff55ff}, /* case-115 */ 2260 {0xaaffffaa, 0x5afa5afa}, 2261 {0xaaffffaa, 0xaaaaaaaa}, 2262 {0xffffffff, 0xfafafafa}, 2263 {0xffffffff, 0x5afa5afa}, 2264 {0xffffffff, 0xaaaaaaaa}, /* case-120 */ 2265 {0x55ff55ff, 0x5afa5afa}, 2266 {0x55ff55ff, 0xaaaaaaaa}, 2267 {0x55ff55ff, 0x55ff55ff} 2268 }; 2269 2270 /* Shared-Antenna TDMA */ 2271 static const struct coex_tdma_para tdma_sant_8822b[] = { 2272 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */ 2273 { {0x61, 0x45, 0x03, 0x11, 0x11} }, 2274 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2275 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2276 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2277 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */ 2278 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2279 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2280 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2281 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2282 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */ 2283 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2284 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2285 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2286 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2287 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */ 2288 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2289 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2290 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2291 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2292 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */ 2293 { {0x51, 0x4a, 0x03, 0x10, 0x50} }, 2294 { {0x51, 0x0c, 0x03, 0x10, 0x54} }, 2295 { {0x55, 0x08, 0x03, 0x10, 0x54} }, 2296 { {0x65, 0x10, 0x03, 0x11, 0x10} }, 2297 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */ 2298 { {0x51, 0x08, 0x03, 0x10, 0x50} }, 2299 { {0x61, 0x08, 0x03, 0x11, 0x11} } 2300 }; 2301 2302 /* Non-Shared-Antenna TDMA */ 2303 static const struct coex_tdma_para tdma_nsant_8822b[] = { 2304 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */ 2305 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */ 2306 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, 2307 { {0x61, 0x30, 0x03, 0x11, 0x11} }, 2308 { {0x61, 0x20, 0x03, 0x11, 0x11} }, 2309 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */ 2310 { {0x61, 0x45, 0x03, 0x11, 0x10} }, 2311 { {0x61, 0x3a, 0x03, 0x11, 0x10} }, 2312 { {0x61, 0x30, 0x03, 0x11, 0x10} }, 2313 { {0x61, 0x20, 0x03, 0x11, 0x10} }, 2314 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */ 2315 { {0x61, 0x08, 0x03, 0x11, 0x14} }, 2316 { {0x61, 0x08, 0x03, 0x10, 0x14} }, 2317 { {0x51, 0x08, 0x03, 0x10, 0x54} }, 2318 { {0x51, 0x08, 0x03, 0x10, 0x55} }, 2319 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */ 2320 { {0x51, 0x45, 0x03, 0x10, 0x50} }, 2321 { {0x51, 0x3a, 0x03, 0x10, 0x50} }, 2322 { {0x51, 0x30, 0x03, 0x10, 0x50} }, 2323 { {0x51, 0x20, 0x03, 0x10, 0x50} }, 2324 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */ 2325 { {0x51, 0x08, 0x03, 0x10, 0x50} } 2326 }; 2327 2328 /* rssi in percentage % (dbm = % - 100) */ 2329 static const u8 wl_rssi_step_8822b[] = {60, 50, 44, 30}; 2330 static const u8 bt_rssi_step_8822b[] = {30, 30, 30, 30}; 2331 2332 /* wl_tx_dec_power, bt_tx_dec_power, wl_rx_gain, bt_rx_lna_constrain */ 2333 static const struct coex_rf_para rf_para_tx_8822b[] = { 2334 {0, 0, false, 7}, /* for normal */ 2335 {0, 16, false, 7}, /* for WL-CPT */ 2336 {4, 0, true, 1}, 2337 {3, 6, true, 1}, 2338 {2, 9, true, 1}, 2339 {1, 13, true, 1} 2340 }; 2341 2342 static const struct coex_rf_para rf_para_rx_8822b[] = { 2343 {0, 0, false, 7}, /* for normal */ 2344 {0, 16, false, 7}, /* for WL-CPT */ 2345 {4, 0, true, 1}, 2346 {3, 6, true, 1}, 2347 {2, 9, true, 1}, 2348 {1, 13, true, 1} 2349 }; 2350 2351 static const struct coex_5g_afh_map afh_5g_8822b[] = { 2352 {120, 2, 4}, 2353 {124, 8, 8}, 2354 {128, 17, 8}, 2355 {132, 26, 10}, 2356 {136, 34, 8}, 2357 {140, 42, 10}, 2358 {144, 51, 8}, 2359 {149, 62, 8}, 2360 {153, 71, 10}, 2361 {157, 77, 4}, 2362 {118, 2, 4}, 2363 {126, 12, 16}, 2364 {134, 29, 16}, 2365 {142, 46, 16}, 2366 {151, 66, 16}, 2367 {159, 76, 4}, 2368 {122, 10, 20}, 2369 {138, 37, 34}, 2370 {155, 68, 20} 2371 }; 2372 static_assert(ARRAY_SIZE(rf_para_tx_8822b) == ARRAY_SIZE(rf_para_rx_8822b)); 2373 2374 static const u8 2375 rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2376 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2377 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2378 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2379 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2380 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2381 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2382 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2383 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2384 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2385 }; 2386 2387 static const u8 2388 rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2389 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2390 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2391 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2392 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2393 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2394 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2395 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2396 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2397 16, 17, 18, 19, 19, 20, 21, 22, 22, 23 }, 2398 }; 2399 2400 static const u8 2401 rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2402 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2403 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2404 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2405 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2406 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2407 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2408 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2409 8, 8, 9, 10, 11, 11, 12, 13, 14, 14, 2410 15, 16, 17, 17, 18, 19, 20, 20, 21, 22 }, 2411 }; 2412 2413 static const u8 2414 rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_NUM][RTW_PWR_TRK_TBL_SZ] = { 2415 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2416 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2417 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2418 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2419 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2420 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2421 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7, 2422 8, 9, 9, 10, 11, 12, 13, 14, 14, 15, 2423 16, 17, 18, 19, 19, 20, 21, 22, 22, 23}, 2424 }; 2425 2426 static const u8 rtw8822b_pwrtrk_2gb_n[RTW_PWR_TRK_TBL_SZ] = { 2427 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2428 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2429 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2430 }; 2431 2432 static const u8 rtw8822b_pwrtrk_2gb_p[RTW_PWR_TRK_TBL_SZ] = { 2433 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 2434 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 2435 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 2436 }; 2437 2438 static const u8 rtw8822b_pwrtrk_2ga_n[RTW_PWR_TRK_TBL_SZ] = { 2439 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2440 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2441 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2442 }; 2443 2444 static const u8 rtw8822b_pwrtrk_2ga_p[RTW_PWR_TRK_TBL_SZ] = { 2445 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 2446 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 2447 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 2448 }; 2449 2450 static const u8 rtw8822b_pwrtrk_2g_cck_b_n[RTW_PWR_TRK_TBL_SZ] = { 2451 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2452 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2453 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2454 }; 2455 2456 static const u8 rtw8822b_pwrtrk_2g_cck_b_p[RTW_PWR_TRK_TBL_SZ] = { 2457 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 2458 5, 5, 6, 6, 6, 7, 7, 8, 8, 9, 2459 9, 10, 10, 11, 11, 12, 12, 12, 13, 13 2460 }; 2461 2462 static const u8 rtw8822b_pwrtrk_2g_cck_a_n[RTW_PWR_TRK_TBL_SZ] = { 2463 0, 1, 1, 1, 2, 2, 3, 3, 3, 4, 2464 4, 5, 5, 5, 6, 6, 7, 7, 7, 8, 2465 8, 9, 9, 9, 10, 10, 11, 11, 11, 12 2466 }; 2467 2468 static const u8 rtw8822b_pwrtrk_2g_cck_a_p[RTW_PWR_TRK_TBL_SZ] = { 2469 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 2470 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 2471 10, 11, 11, 12, 12, 13, 13, 14, 14, 15 2472 }; 2473 2474 static const struct rtw_pwr_track_tbl rtw8822b_rtw_pwr_track_tbl = { 2475 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_1], 2476 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_2], 2477 .pwrtrk_5gb_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_n[RTW_PWR_TRK_5G_3], 2478 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_1], 2479 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_2], 2480 .pwrtrk_5gb_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5gb_p[RTW_PWR_TRK_5G_3], 2481 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_1], 2482 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_2], 2483 .pwrtrk_5ga_n[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_n[RTW_PWR_TRK_5G_3], 2484 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_1] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_1], 2485 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_2] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_2], 2486 .pwrtrk_5ga_p[RTW_PWR_TRK_5G_3] = rtw8822b_pwrtrk_5ga_p[RTW_PWR_TRK_5G_3], 2487 .pwrtrk_2gb_n = rtw8822b_pwrtrk_2gb_n, 2488 .pwrtrk_2gb_p = rtw8822b_pwrtrk_2gb_p, 2489 .pwrtrk_2ga_n = rtw8822b_pwrtrk_2ga_n, 2490 .pwrtrk_2ga_p = rtw8822b_pwrtrk_2ga_p, 2491 .pwrtrk_2g_cckb_n = rtw8822b_pwrtrk_2g_cck_b_n, 2492 .pwrtrk_2g_cckb_p = rtw8822b_pwrtrk_2g_cck_b_p, 2493 .pwrtrk_2g_ccka_n = rtw8822b_pwrtrk_2g_cck_a_n, 2494 .pwrtrk_2g_ccka_p = rtw8822b_pwrtrk_2g_cck_a_p, 2495 }; 2496 2497 static const struct rtw_reg_domain coex_info_hw_regs_8822b[] = { 2498 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2499 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2500 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2501 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2502 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2503 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8}, 2504 {0, 0, RTW_REG_DOMAIN_NL}, 2505 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2506 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2507 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2508 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2509 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8}, 2510 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16}, 2511 {0, 0, RTW_REG_DOMAIN_NL}, 2512 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32}, 2513 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8}, 2514 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8}, 2515 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8}, 2516 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B}, 2517 {0, 0, RTW_REG_DOMAIN_NL}, 2518 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32}, 2519 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2520 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8}, 2521 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8}, 2522 }; 2523 2524 static struct rtw_hw_reg_offset rtw8822b_edcca_th[] = { 2525 [EDCCA_TH_L2H_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE0}, .offset = 0}, 2526 [EDCCA_TH_H2L_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE1}, .offset = 0}, 2527 }; 2528 2529 const struct rtw_chip_info rtw8822b_hw_spec = { 2530 .ops = &rtw8822b_ops, 2531 .id = RTW_CHIP_TYPE_8822B, 2532 .fw_name = "rtw88/rtw8822b_fw.bin", 2533 .wlan_cpu = RTW_WCPU_11AC, 2534 .tx_pkt_desc_sz = 48, 2535 .tx_buf_desc_sz = 16, 2536 .rx_pkt_desc_sz = 24, 2537 .rx_buf_desc_sz = 8, 2538 .phy_efuse_size = 1024, 2539 .log_efuse_size = 768, 2540 .ptct_efuse_size = 96, 2541 .txff_size = 262144, 2542 .rxff_size = 24576, 2543 .fw_rxff_size = 12288, 2544 .rsvd_drv_pg_num = 8, 2545 .txgi_factor = 1, 2546 .is_pwr_by_rate_dec = true, 2547 .max_power_index = 0x3f, 2548 .csi_buf_pg_num = 0, 2549 .band = RTW_BAND_2G | RTW_BAND_5G, 2550 .page_size = TX_PAGE_SIZE, 2551 .dig_min = 0x1c, 2552 .usb_tx_agg_desc_num = 3, 2553 .ht_supported = true, 2554 .vht_supported = true, 2555 .lps_deep_mode_supported = BIT(LPS_DEEP_MODE_LCLK), 2556 .sys_func_en = 0xDC, 2557 .pwr_on_seq = card_enable_flow_8822b, 2558 .pwr_off_seq = card_disable_flow_8822b, 2559 .page_table = page_table_8822b, 2560 .rqpn_table = rqpn_table_8822b, 2561 .prioq_addrs = &prioq_addrs_8822b, 2562 .intf_table = &phy_para_table_8822b, 2563 .dig = rtw8822b_dig, 2564 .dig_cck = NULL, 2565 .rf_base_addr = {0x2800, 0x2c00}, 2566 .rf_sipi_addr = {0xc90, 0xe90}, 2567 .ltecoex_addr = &rtw8822b_ltecoex_addr, 2568 .mac_tbl = &rtw8822b_mac_tbl, 2569 .agc_tbl = &rtw8822b_agc_tbl, 2570 .bb_tbl = &rtw8822b_bb_tbl, 2571 .rf_tbl = {&rtw8822b_rf_a_tbl, &rtw8822b_rf_b_tbl}, 2572 .rfe_defs = rtw8822b_rfe_defs, 2573 .rfe_defs_size = ARRAY_SIZE(rtw8822b_rfe_defs), 2574 .pwr_track_tbl = &rtw8822b_rtw_pwr_track_tbl, 2575 .iqk_threshold = 8, 2576 .bfer_su_max_num = 2, 2577 .bfer_mu_max_num = 1, 2578 .rx_ldpc = true, 2579 .edcca_th = rtw8822b_edcca_th, 2580 .l2h_th_ini_cs = 10 + EDCCA_IGI_BASE, 2581 .l2h_th_ini_ad = -14 + EDCCA_IGI_BASE, 2582 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_2, 2583 .max_scan_ie_len = IEEE80211_MAX_DATA_LEN, 2584 2585 .coex_para_ver = 0x20070206, 2586 .bt_desired_ver = 0x6, 2587 .scbd_support = true, 2588 .new_scbd10_def = false, 2589 .ble_hid_profile_support = false, 2590 .wl_mimo_ps_support = false, 2591 .pstdma_type = COEX_PSTDMA_FORCE_LPSOFF, 2592 .bt_rssi_type = COEX_BTRSSI_RATIO, 2593 .ant_isolation = 15, 2594 .rssi_tolerance = 2, 2595 .wl_rssi_step = wl_rssi_step_8822b, 2596 .bt_rssi_step = bt_rssi_step_8822b, 2597 .table_sant_num = ARRAY_SIZE(table_sant_8822b), 2598 .table_sant = table_sant_8822b, 2599 .table_nsant_num = ARRAY_SIZE(table_nsant_8822b), 2600 .table_nsant = table_nsant_8822b, 2601 .tdma_sant_num = ARRAY_SIZE(tdma_sant_8822b), 2602 .tdma_sant = tdma_sant_8822b, 2603 .tdma_nsant_num = ARRAY_SIZE(tdma_nsant_8822b), 2604 .tdma_nsant = tdma_nsant_8822b, 2605 .wl_rf_para_num = ARRAY_SIZE(rf_para_tx_8822b), 2606 .wl_rf_para_tx = rf_para_tx_8822b, 2607 .wl_rf_para_rx = rf_para_rx_8822b, 2608 .bt_afh_span_bw20 = 0x24, 2609 .bt_afh_span_bw40 = 0x36, 2610 .afh_5g_num = ARRAY_SIZE(afh_5g_8822b), 2611 .afh_5g = afh_5g_8822b, 2612 2613 .coex_info_hw_regs_num = ARRAY_SIZE(coex_info_hw_regs_8822b), 2614 .coex_info_hw_regs = coex_info_hw_regs_8822b, 2615 2616 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680}, 2617 }; 2618 EXPORT_SYMBOL(rtw8822b_hw_spec); 2619 2620 MODULE_FIRMWARE("rtw88/rtw8822b_fw.bin"); 2621 2622 MODULE_AUTHOR("Realtek Corporation"); 2623 MODULE_DESCRIPTION("Realtek 802.11ac wireless 8822b driver"); 2624 MODULE_LICENSE("Dual BSD/GPL"); 2625