1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW8821C_H__ 6 #define __RTW8821C_H__ 7 8 #include <asm/byteorder.h> 9 10 #define RCR_VHT_ACK BIT(26) 11 12 struct rtw8821cu_efuse { 13 u8 res4[4]; /* 0xd0 */ 14 u8 usb_optional_function; 15 u8 res5[0x1e]; 16 u8 res6[2]; 17 u8 serial[0x0b]; /* 0xf5 */ 18 u8 vid; /* 0x100 */ 19 u8 res7; 20 u8 pid; 21 u8 res8[4]; 22 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 23 u8 res9[2]; 24 u8 vendor_name[0x07]; 25 u8 res10[2]; 26 u8 device_name[0x14]; 27 u8 res11[0xcf]; 28 u8 package_type; /* 0x1fb */ 29 u8 res12[0x4]; 30 }; 31 32 struct rtw8821ce_efuse { 33 u8 mac_addr[ETH_ALEN]; /* 0xd0 */ 34 u8 vender_id[2]; 35 u8 device_id[2]; 36 u8 sub_vender_id[2]; 37 u8 sub_device_id[2]; 38 u8 pmc[2]; 39 u8 exp_device_cap[2]; 40 u8 msi_cap; 41 u8 ltr_cap; /* 0xe3 */ 42 u8 exp_link_control[2]; 43 u8 link_cap[4]; 44 u8 link_control[2]; 45 u8 serial_number[8]; 46 u8 res0:2; /* 0xf4 */ 47 u8 ltr_en:1; 48 u8 res1:2; 49 u8 obff:2; 50 u8 res2:3; 51 u8 obff_cap:2; 52 u8 res3:4; 53 u8 res4[3]; 54 u8 class_code[3]; 55 u8 pci_pm_L1_2_supp:1; 56 u8 pci_pm_L1_1_supp:1; 57 u8 aspm_pm_L1_2_supp:1; 58 u8 aspm_pm_L1_1_supp:1; 59 u8 L1_pm_substates_supp:1; 60 u8 res5:3; 61 u8 port_common_mode_restore_time; 62 u8 port_t_power_on_scale:2; 63 u8 res6:1; 64 u8 port_t_power_on_value:5; 65 u8 res7; 66 }; 67 68 struct rtw8821c_efuse { 69 __le16 rtl_id; 70 u8 res0[0x0e]; 71 72 /* power index for four RF paths */ 73 struct rtw_txpwr_idx txpwr_idx_table[4]; 74 75 u8 channel_plan; /* 0xb8 */ 76 u8 xtal_k; 77 u8 thermal_meter; 78 u8 iqk_lck; 79 u8 pa_type; /* 0xbc */ 80 u8 lna_type_2g[2]; /* 0xbd */ 81 u8 lna_type_5g[2]; 82 u8 rf_board_option; 83 u8 rf_feature_option; 84 u8 rf_bt_setting; 85 u8 eeprom_version; 86 u8 eeprom_customer_id; 87 u8 tx_bb_swing_setting_2g; 88 u8 tx_bb_swing_setting_5g; 89 u8 tx_pwr_calibrate_rate; 90 u8 rf_antenna_option; /* 0xc9 */ 91 u8 rfe_option; 92 u8 country_code[2]; 93 u8 res[3]; 94 union { 95 struct rtw8821ce_efuse e; 96 struct rtw8821cu_efuse u; 97 }; 98 }; 99 100 static inline void 101 _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) 102 { 103 /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */ 104 rtw_write32_mask(rtwdev, addr, mask, data); 105 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); 106 } 107 108 extern const struct rtw_chip_info rtw8821c_hw_spec; 109 110 #define rtw_write32s_mask(rtwdev, addr, mask, data) \ 111 do { \ 112 BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \ 113 \ 114 _rtw_write32s_mask(rtwdev, addr, mask, data); \ 115 } while (0) 116 117 #define BIT_FEN_PCIEA BIT(6) 118 #define WLAN_SLOT_TIME 0x09 119 #define WLAN_PIFS_TIME 0x19 120 #define WLAN_SIFS_CCK_CONT_TX 0xA 121 #define WLAN_SIFS_OFDM_CONT_TX 0xE 122 #define WLAN_SIFS_CCK_TRX 0x10 123 #define WLAN_SIFS_OFDM_TRX 0x10 124 #define WLAN_VO_TXOP_LIMIT 0x186 125 #define WLAN_VI_TXOP_LIMIT 0x3BC 126 #define WLAN_RDG_NAV 0x05 127 #define WLAN_TXOP_NAV 0x1B 128 #define WLAN_CCK_RX_TSF 0x30 129 #define WLAN_OFDM_RX_TSF 0x30 130 #define WLAN_TBTT_PROHIBIT 0x04 131 #define WLAN_TBTT_HOLD_TIME 0x064 132 #define WLAN_DRV_EARLY_INT 0x04 133 #define WLAN_BCN_DMA_TIME 0x02 134 135 #define WLAN_RX_FILTER0 0x0FFFFFFF 136 #define WLAN_RX_FILTER2 0xFFFF 137 #define WLAN_RCR_CFG 0xE400220E 138 #define WLAN_RXPKT_MAX_SZ 12288 139 #define WLAN_RXPKT_MAX_SZ_512 (WLAN_RXPKT_MAX_SZ >> 9) 140 141 #define WLAN_AMPDU_MAX_TIME 0x70 142 #define WLAN_RTS_LEN_TH 0xFF 143 #define WLAN_RTS_TX_TIME_TH 0x08 144 #define WLAN_MAX_AGG_PKT_LIMIT 0x20 145 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20 146 #define FAST_EDCA_VO_TH 0x06 147 #define FAST_EDCA_VI_TH 0x06 148 #define FAST_EDCA_BE_TH 0x06 149 #define FAST_EDCA_BK_TH 0x06 150 #define WLAN_BAR_RETRY_LIMIT 0x01 151 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08 152 153 #define WLAN_TX_FUNC_CFG1 0x30 154 #define WLAN_TX_FUNC_CFG2 0x30 155 #define WLAN_MAC_OPT_NORM_FUNC1 0x98 156 #define WLAN_MAC_OPT_LB_FUNC1 0x80 157 #define WLAN_MAC_OPT_FUNC2 0xb0810041 158 159 #define WLAN_SIFS_CFG (WLAN_SIFS_CCK_CONT_TX | \ 160 (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \ 161 (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \ 162 (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX)) 163 164 #define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\ 165 (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP)) 166 167 #define WLAN_NAV_CFG (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16)) 168 #define WLAN_RX_TSF_CFG (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8) 169 #define WLAN_PRE_TXCNT_TIME_TH 0x1E4 170 171 /* phy status page0 */ 172 #define GET_PHY_STAT_P0_PWDB(phy_stat) \ 173 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 174 #define GET_PHY_STAT_P0_VGA(phy_stat) \ 175 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(12, 8)) 176 #define GET_PHY_STAT_P0_LNA_L(phy_stat) \ 177 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(15, 13)) 178 #define GET_PHY_STAT_P0_LNA_H(phy_stat) \ 179 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), BIT(23)) 180 #define BIT_LNA_H_MASK BIT(3) 181 #define BIT_LNA_L_MASK GENMASK(2, 0) 182 183 /* phy status page1 */ 184 #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \ 185 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 186 #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \ 187 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16)) 188 #define GET_PHY_STAT_P1_RF_MODE(phy_stat) \ 189 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28)) 190 #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \ 191 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8)) 192 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \ 193 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12)) 194 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \ 195 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0)) 196 #define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \ 197 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8)) 198 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \ 199 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0)) 200 #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \ 201 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8)) 202 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \ 203 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0)) 204 #define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \ 205 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8)) 206 207 #define REG_SYS_CTRL 0x000 208 #define BIT_FEN_EN BIT(26) 209 #define REG_INIRTS_RATE_SEL 0x0480 210 #define REG_HTSTFWT 0x800 211 #define REG_RXPSEL 0x808 212 #define BIT_RX_PSEL_RST (BIT(28) | BIT(29)) 213 #define REG_TXPSEL 0x80c 214 #define REG_RXCCAMSK 0x814 215 #define REG_CCASEL 0x82c 216 #define REG_PDMFTH 0x830 217 #define REG_CCA2ND 0x838 218 #define REG_L1WT 0x83c 219 #define REG_L1PKWT 0x840 220 #define REG_MRC 0x850 221 #define REG_CLKTRK 0x860 222 #define REG_ADCCLK 0x8ac 223 #define REG_ADC160 0x8c4 224 #define REG_ADC40 0x8c8 225 #define REG_CHFIR 0x8f0 226 #define REG_CDDTXP 0x93c 227 #define REG_TXPSEL1 0x940 228 #define REG_ACBB0 0x948 229 #define REG_ACBBRXFIR 0x94c 230 #define REG_ACGG2TBL 0x958 231 #define REG_FAS 0x9a4 232 #define REG_RXSB 0xa00 233 #define REG_ADCINI 0xa04 234 #define REG_PWRTH 0xa08 235 #define REG_TXSF2 0xa24 236 #define REG_TXSF6 0xa28 237 #define REG_FA_CCK 0xa5c 238 #define REG_RXDESC 0xa2c 239 #define REG_ENTXCCK 0xa80 240 #define BTG_LNA 0xfc84 241 #define WLG_LNA 0x7532 242 #define REG_ENRXCCA 0xa84 243 #define BTG_CCA 0x0e 244 #define WLG_CCA 0x12 245 #define REG_PWRTH2 0xaa8 246 #define REG_CSRATIO 0xaaa 247 #define REG_TXFILTER 0xaac 248 #define REG_CNTRST 0xb58 249 #define REG_AGCTR_A 0xc08 250 #define REG_TXSCALE_A 0xc1c 251 #define REG_TXDFIR 0xc20 252 #define REG_RXIGI_A 0xc50 253 #define REG_TXAGCIDX 0xc94 254 #define REG_TRSW 0xca0 255 #define REG_RFESEL0 0xcb0 256 #define REG_RFESEL8 0xcb4 257 #define REG_RFECTL 0xcb8 258 #define B_BTG_SWITCH BIT(16) 259 #define B_CTRL_SWITCH BIT(18) 260 #define B_WL_SWITCH (BIT(20) | BIT(22)) 261 #define B_WLG_SWITCH BIT(21) 262 #define B_WLA_SWITCH BIT(23) 263 #define REG_RFEINV 0xcbc 264 #define REG_AGCTR_B 0xe08 265 #define REG_RXIGI_B 0xe50 266 #define REG_CRC_CCK 0xf04 267 #define REG_CRC_OFDM 0xf14 268 #define REG_CRC_HT 0xf10 269 #define REG_CRC_VHT 0xf0c 270 #define REG_CCA_OFDM 0xf08 271 #define REG_FA_OFDM 0xf48 272 #define REG_CCA_CCK 0xfcc 273 #define REG_DMEM_CTRL 0x1080 274 #define BIT_WL_RST BIT(16) 275 #define REG_ANTWT 0x1904 276 #define REG_IQKFAILMSK 0x1bf0 277 #define BIT_MASK_R_RFE_SEL_15 GENMASK(31, 28) 278 #define BIT_SDIO_INT BIT(18) 279 #define BT_CNT_ENABLE 0x1 280 #define BIT_BCN_QUEUE BIT(3) 281 #define BCN_PRI_EN 0x1 282 #define PTA_CTRL_PIN 0x66 283 #define DPDT_CTRL_PIN 0x77 284 #define ANTDIC_CTRL_PIN 0x88 285 #define REG_CTRL_TYPE 0x67 286 #define BIT_CTRL_TYPE1 BIT(5) 287 #define BIT_CTRL_TYPE2 BIT(4) 288 #define CTRL_TYPE_MASK GENMASK(15, 8) 289 290 #define RF18_BAND_MASK (BIT(16) | BIT(9) | BIT(8)) 291 #define RF18_BAND_2G (0) 292 #define RF18_BAND_5G (BIT(16) | BIT(8)) 293 #define RF18_CHANNEL_MASK (MASKBYTE0) 294 #define RF18_RFSI_MASK (BIT(18) | BIT(17)) 295 #define RF18_RFSI_GE (BIT(17)) 296 #define RF18_RFSI_GT (BIT(18)) 297 #define RF18_BW_MASK (BIT(11) | BIT(10)) 298 #define RF18_BW_20M (BIT(11) | BIT(10)) 299 #define RF18_BW_40M (BIT(11)) 300 #define RF18_BW_80M (BIT(10)) 301 302 #endif 303